1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_ratelimit.h" 37 #include "opt_rss.h" 38 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/priv.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #if defined(__i386__) || defined(__amd64__) 67 #include <machine/md_var.h> 68 #include <machine/cputypes.h> 69 #include <vm/vm.h> 70 #include <vm/pmap.h> 71 #endif 72 #include <crypto/rijndael/rijndael.h> 73 #ifdef DDB 74 #include <ddb/ddb.h> 75 #include <ddb/db_lex.h> 76 #endif 77 78 #include "common/common.h" 79 #include "common/t4_msg.h" 80 #include "common/t4_regs.h" 81 #include "common/t4_regs_values.h" 82 #include "cudbg/cudbg.h" 83 #include "t4_ioctl.h" 84 #include "t4_l2t.h" 85 #include "t4_mp_ring.h" 86 #include "t4_if.h" 87 88 /* T4 bus driver interface */ 89 static int t4_probe(device_t); 90 static int t4_attach(device_t); 91 static int t4_detach(device_t); 92 static int t4_ready(device_t); 93 static int t4_read_port_device(device_t, int, device_t *); 94 static device_method_t t4_methods[] = { 95 DEVMETHOD(device_probe, t4_probe), 96 DEVMETHOD(device_attach, t4_attach), 97 DEVMETHOD(device_detach, t4_detach), 98 99 DEVMETHOD(t4_is_main_ready, t4_ready), 100 DEVMETHOD(t4_read_port_device, t4_read_port_device), 101 102 DEVMETHOD_END 103 }; 104 static driver_t t4_driver = { 105 "t4nex", 106 t4_methods, 107 sizeof(struct adapter) 108 }; 109 110 111 /* T4 port (cxgbe) interface */ 112 static int cxgbe_probe(device_t); 113 static int cxgbe_attach(device_t); 114 static int cxgbe_detach(device_t); 115 device_method_t cxgbe_methods[] = { 116 DEVMETHOD(device_probe, cxgbe_probe), 117 DEVMETHOD(device_attach, cxgbe_attach), 118 DEVMETHOD(device_detach, cxgbe_detach), 119 { 0, 0 } 120 }; 121 static driver_t cxgbe_driver = { 122 "cxgbe", 123 cxgbe_methods, 124 sizeof(struct port_info) 125 }; 126 127 /* T4 VI (vcxgbe) interface */ 128 static int vcxgbe_probe(device_t); 129 static int vcxgbe_attach(device_t); 130 static int vcxgbe_detach(device_t); 131 static device_method_t vcxgbe_methods[] = { 132 DEVMETHOD(device_probe, vcxgbe_probe), 133 DEVMETHOD(device_attach, vcxgbe_attach), 134 DEVMETHOD(device_detach, vcxgbe_detach), 135 { 0, 0 } 136 }; 137 static driver_t vcxgbe_driver = { 138 "vcxgbe", 139 vcxgbe_methods, 140 sizeof(struct vi_info) 141 }; 142 143 static d_ioctl_t t4_ioctl; 144 145 static struct cdevsw t4_cdevsw = { 146 .d_version = D_VERSION, 147 .d_ioctl = t4_ioctl, 148 .d_name = "t4nex", 149 }; 150 151 /* T5 bus driver interface */ 152 static int t5_probe(device_t); 153 static device_method_t t5_methods[] = { 154 DEVMETHOD(device_probe, t5_probe), 155 DEVMETHOD(device_attach, t4_attach), 156 DEVMETHOD(device_detach, t4_detach), 157 158 DEVMETHOD(t4_is_main_ready, t4_ready), 159 DEVMETHOD(t4_read_port_device, t4_read_port_device), 160 161 DEVMETHOD_END 162 }; 163 static driver_t t5_driver = { 164 "t5nex", 165 t5_methods, 166 sizeof(struct adapter) 167 }; 168 169 170 /* T5 port (cxl) interface */ 171 static driver_t cxl_driver = { 172 "cxl", 173 cxgbe_methods, 174 sizeof(struct port_info) 175 }; 176 177 /* T5 VI (vcxl) interface */ 178 static driver_t vcxl_driver = { 179 "vcxl", 180 vcxgbe_methods, 181 sizeof(struct vi_info) 182 }; 183 184 /* T6 bus driver interface */ 185 static int t6_probe(device_t); 186 static device_method_t t6_methods[] = { 187 DEVMETHOD(device_probe, t6_probe), 188 DEVMETHOD(device_attach, t4_attach), 189 DEVMETHOD(device_detach, t4_detach), 190 191 DEVMETHOD(t4_is_main_ready, t4_ready), 192 DEVMETHOD(t4_read_port_device, t4_read_port_device), 193 194 DEVMETHOD_END 195 }; 196 static driver_t t6_driver = { 197 "t6nex", 198 t6_methods, 199 sizeof(struct adapter) 200 }; 201 202 203 /* T6 port (cc) interface */ 204 static driver_t cc_driver = { 205 "cc", 206 cxgbe_methods, 207 sizeof(struct port_info) 208 }; 209 210 /* T6 VI (vcc) interface */ 211 static driver_t vcc_driver = { 212 "vcc", 213 vcxgbe_methods, 214 sizeof(struct vi_info) 215 }; 216 217 /* ifnet + media interface */ 218 static void cxgbe_init(void *); 219 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 220 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 221 static void cxgbe_qflush(struct ifnet *); 222 static int cxgbe_media_change(struct ifnet *); 223 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 224 225 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 226 227 /* 228 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 229 * then ADAPTER_LOCK, then t4_uld_list_lock. 230 */ 231 static struct sx t4_list_lock; 232 SLIST_HEAD(, adapter) t4_list; 233 #ifdef TCP_OFFLOAD 234 static struct sx t4_uld_list_lock; 235 SLIST_HEAD(, uld_info) t4_uld_list; 236 #endif 237 238 /* 239 * Tunables. See tweak_tunables() too. 240 * 241 * Each tunable is set to a default value here if it's known at compile-time. 242 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 243 * provide a reasonable default (upto n) when the driver is loaded. 244 * 245 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 246 * T5 are under hw.cxl. 247 */ 248 249 /* 250 * Number of queues for tx and rx, NIC and offload. 251 */ 252 #define NTXQ 16 253 int t4_ntxq = -NTXQ; 254 TUNABLE_INT("hw.cxgbe.ntxq", &t4_ntxq); 255 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 256 257 #define NRXQ 8 258 int t4_nrxq = -NRXQ; 259 TUNABLE_INT("hw.cxgbe.nrxq", &t4_nrxq); 260 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 261 262 #define NTXQ_VI 1 263 static int t4_ntxq_vi = -NTXQ_VI; 264 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi); 265 266 #define NRXQ_VI 1 267 static int t4_nrxq_vi = -NRXQ_VI; 268 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi); 269 270 static int t4_rsrv_noflowq = 0; 271 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq); 272 273 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 274 #define NOFLDTXQ 8 275 static int t4_nofldtxq = -NOFLDTXQ; 276 TUNABLE_INT("hw.cxgbe.nofldtxq", &t4_nofldtxq); 277 278 #define NOFLDRXQ 2 279 static int t4_nofldrxq = -NOFLDRXQ; 280 TUNABLE_INT("hw.cxgbe.nofldrxq", &t4_nofldrxq); 281 282 #define NOFLDTXQ_VI 1 283 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 284 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi); 285 286 #define NOFLDRXQ_VI 1 287 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 288 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi); 289 290 #define TMR_IDX_OFLD 1 291 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 292 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_ofld", &t4_tmr_idx_ofld); 293 294 #define PKTC_IDX_OFLD (-1) 295 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 296 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_ofld", &t4_pktc_idx_ofld); 297 298 /* 0 means chip/fw default, non-zero number is value in microseconds */ 299 static u_long t4_toe_keepalive_idle = 0; 300 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_idle", &t4_toe_keepalive_idle); 301 302 /* 0 means chip/fw default, non-zero number is value in microseconds */ 303 static u_long t4_toe_keepalive_interval = 0; 304 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_interval", &t4_toe_keepalive_interval); 305 306 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 307 static int t4_toe_keepalive_count = 0; 308 TUNABLE_INT("hw.cxgbe.toe.keepalive_count", &t4_toe_keepalive_count); 309 310 /* 0 means chip/fw default, non-zero number is value in microseconds */ 311 static u_long t4_toe_rexmt_min = 0; 312 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_min", &t4_toe_rexmt_min); 313 314 /* 0 means chip/fw default, non-zero number is value in microseconds */ 315 static u_long t4_toe_rexmt_max = 0; 316 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_max", &t4_toe_rexmt_max); 317 318 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 319 static int t4_toe_rexmt_count = 0; 320 TUNABLE_INT("hw.cxgbe.toe.rexmt_count", &t4_toe_rexmt_count); 321 322 /* -1 means chip/fw default, other values are raw backoff values to use */ 323 static int t4_toe_rexmt_backoff[16] = { 324 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 325 }; 326 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.0", &t4_toe_rexmt_backoff[0]); 327 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.1", &t4_toe_rexmt_backoff[1]); 328 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.2", &t4_toe_rexmt_backoff[2]); 329 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.3", &t4_toe_rexmt_backoff[3]); 330 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.4", &t4_toe_rexmt_backoff[4]); 331 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.5", &t4_toe_rexmt_backoff[5]); 332 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.6", &t4_toe_rexmt_backoff[6]); 333 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.7", &t4_toe_rexmt_backoff[7]); 334 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.8", &t4_toe_rexmt_backoff[8]); 335 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.9", &t4_toe_rexmt_backoff[9]); 336 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.10", &t4_toe_rexmt_backoff[10]); 337 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.11", &t4_toe_rexmt_backoff[11]); 338 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.12", &t4_toe_rexmt_backoff[12]); 339 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.13", &t4_toe_rexmt_backoff[13]); 340 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.14", &t4_toe_rexmt_backoff[14]); 341 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.15", &t4_toe_rexmt_backoff[15]); 342 #endif 343 344 #ifdef DEV_NETMAP 345 #define NNMTXQ_VI 2 346 static int t4_nnmtxq_vi = -NNMTXQ_VI; 347 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi); 348 349 #define NNMRXQ_VI 2 350 static int t4_nnmrxq_vi = -NNMRXQ_VI; 351 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi); 352 #endif 353 354 /* 355 * Holdoff parameters for ports. 356 */ 357 #define TMR_IDX 1 358 int t4_tmr_idx = TMR_IDX; 359 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx", &t4_tmr_idx); 360 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 361 362 #define PKTC_IDX (-1) 363 int t4_pktc_idx = PKTC_IDX; 364 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx", &t4_pktc_idx); 365 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 366 367 /* 368 * Size (# of entries) of each tx and rx queue. 369 */ 370 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 371 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 372 373 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 374 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 375 376 /* 377 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 378 */ 379 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 380 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 381 382 /* 383 * Configuration file. All the _CF names here are special. 384 */ 385 #define DEFAULT_CF "default" 386 #define BUILTIN_CF "built-in" 387 #define FLASH_CF "flash" 388 #define UWIRE_CF "uwire" 389 #define FPGA_CF "fpga" 390 static char t4_cfg_file[32] = DEFAULT_CF; 391 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 392 393 /* 394 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively). 395 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 396 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 397 * mark or when signalled to do so, 0 to never emit PAUSE. 398 */ 399 static int t4_pause_settings = PAUSE_TX | PAUSE_RX; 400 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings); 401 402 /* 403 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS, 404 * FEC_RESERVED respectively). 405 * -1 to run with the firmware default. 406 * 0 to disable FEC. 407 */ 408 static int t4_fec = -1; 409 TUNABLE_INT("hw.cxgbe.fec", &t4_fec); 410 411 /* 412 * Link autonegotiation. 413 * -1 to run with the firmware default. 414 * 0 to disable. 415 * 1 to enable. 416 */ 417 static int t4_autoneg = -1; 418 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg); 419 420 /* 421 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 422 * encouraged respectively). 423 */ 424 static unsigned int t4_fw_install = 1; 425 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 426 427 /* 428 * ASIC features that will be used. Disable the ones you don't want so that the 429 * chip resources aren't wasted on features that will not be used. 430 */ 431 static int t4_nbmcaps_allowed = 0; 432 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed); 433 434 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 435 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 436 437 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 438 FW_CAPS_CONFIG_SWITCH_EGRESS; 439 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed); 440 441 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 442 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 443 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 444 445 static int t4_toecaps_allowed = -1; 446 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 447 448 static int t4_rdmacaps_allowed = -1; 449 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 450 451 static int t4_cryptocaps_allowed = -1; 452 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed); 453 454 static int t4_iscsicaps_allowed = -1; 455 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 456 457 static int t4_fcoecaps_allowed = 0; 458 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 459 460 static int t5_write_combine = 0; 461 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 462 463 static int t4_num_vis = 1; 464 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis); 465 /* 466 * PCIe Relaxed Ordering. 467 * -1: driver should figure out a good value. 468 * 0: disable RO. 469 * 1: enable RO. 470 * 2: leave RO alone. 471 */ 472 static int pcie_relaxed_ordering = -1; 473 TUNABLE_INT("hw.cxgbe.pcie_relaxed_ordering", &pcie_relaxed_ordering); 474 475 static int t4_panic_on_fatal_err = 0; 476 TUNABLE_INT("hw.cxgbe.panic_on_fatal_err", &t4_panic_on_fatal_err); 477 478 #ifdef TCP_OFFLOAD 479 /* 480 * TOE tunables. 481 */ 482 static int t4_cop_managed_offloading = 0; 483 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading); 484 #endif 485 486 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 487 static int vi_mac_funcs[] = { 488 FW_VI_FUNC_ETH, 489 FW_VI_FUNC_OFLD, 490 FW_VI_FUNC_IWARP, 491 FW_VI_FUNC_OPENISCSI, 492 FW_VI_FUNC_OPENFCOE, 493 FW_VI_FUNC_FOISCSI, 494 FW_VI_FUNC_FOFCOE, 495 }; 496 497 struct intrs_and_queues { 498 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 499 uint16_t num_vis; /* number of VIs for each port */ 500 uint16_t nirq; /* Total # of vectors */ 501 uint16_t ntxq; /* # of NIC txq's for each port */ 502 uint16_t nrxq; /* # of NIC rxq's for each port */ 503 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 504 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 505 506 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 507 uint16_t ntxq_vi; /* # of NIC txq's */ 508 uint16_t nrxq_vi; /* # of NIC rxq's */ 509 uint16_t nofldtxq_vi; /* # of TOE txq's */ 510 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 511 uint16_t nnmtxq_vi; /* # of netmap txq's */ 512 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 513 }; 514 515 static void setup_memwin(struct adapter *); 516 static void position_memwin(struct adapter *, int, uint32_t); 517 static int validate_mem_range(struct adapter *, uint32_t, int); 518 static int fwmtype_to_hwmtype(int); 519 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 520 uint32_t *); 521 static int fixup_devlog_params(struct adapter *); 522 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 523 static int prep_firmware(struct adapter *); 524 static int partition_resources(struct adapter *, const struct firmware *, 525 const char *); 526 static int get_params__pre_init(struct adapter *); 527 static int get_params__post_init(struct adapter *); 528 static int set_params__post_init(struct adapter *); 529 static void t4_set_desc(struct adapter *); 530 static void build_medialist(struct port_info *, struct ifmedia *); 531 static void init_l1cfg(struct port_info *); 532 static int cxgbe_init_synchronized(struct vi_info *); 533 static int cxgbe_uninit_synchronized(struct vi_info *); 534 static void quiesce_txq(struct adapter *, struct sge_txq *); 535 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 536 static void quiesce_iq(struct adapter *, struct sge_iq *); 537 static void quiesce_fl(struct adapter *, struct sge_fl *); 538 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 539 driver_intr_t *, void *, char *); 540 static int t4_free_irq(struct adapter *, struct irq *); 541 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 542 static void vi_refresh_stats(struct adapter *, struct vi_info *); 543 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 544 static void cxgbe_tick(void *); 545 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 546 static void cxgbe_sysctls(struct port_info *); 547 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 548 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 549 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 550 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 551 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 552 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 553 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 554 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 555 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 556 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 557 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 558 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 559 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 560 #ifdef SBUF_DRAIN 561 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 562 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 563 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 564 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 565 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 566 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 567 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 568 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 569 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 570 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 571 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 572 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 573 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 574 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 575 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 576 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 577 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 578 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 579 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 580 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 581 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 582 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 583 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 584 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 585 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 586 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 587 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 588 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 589 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 590 #endif 591 #ifdef TCP_OFFLOAD 592 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 593 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 594 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 595 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 596 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 597 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 598 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 599 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 600 #endif 601 static int get_sge_context(struct adapter *, struct t4_sge_context *); 602 static int load_fw(struct adapter *, struct t4_data *); 603 static int load_cfg(struct adapter *, struct t4_data *); 604 static int load_boot(struct adapter *, struct t4_bootrom *); 605 static int load_bootcfg(struct adapter *, struct t4_data *); 606 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 607 static void free_offload_policy(struct t4_offload_policy *); 608 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 609 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 610 static int read_i2c(struct adapter *, struct t4_i2c_data *); 611 #ifdef TCP_OFFLOAD 612 static int toe_capability(struct vi_info *, int); 613 #endif 614 static int mod_event(module_t, int, void *); 615 static int notify_siblings(device_t, int); 616 617 struct { 618 uint16_t device; 619 char *desc; 620 } t4_pciids[] = { 621 {0xa000, "Chelsio Terminator 4 FPGA"}, 622 {0x4400, "Chelsio T440-dbg"}, 623 {0x4401, "Chelsio T420-CR"}, 624 {0x4402, "Chelsio T422-CR"}, 625 {0x4403, "Chelsio T440-CR"}, 626 {0x4404, "Chelsio T420-BCH"}, 627 {0x4405, "Chelsio T440-BCH"}, 628 {0x4406, "Chelsio T440-CH"}, 629 {0x4407, "Chelsio T420-SO"}, 630 {0x4408, "Chelsio T420-CX"}, 631 {0x4409, "Chelsio T420-BT"}, 632 {0x440a, "Chelsio T404-BT"}, 633 {0x440e, "Chelsio T440-LP-CR"}, 634 }, t5_pciids[] = { 635 {0xb000, "Chelsio Terminator 5 FPGA"}, 636 {0x5400, "Chelsio T580-dbg"}, 637 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 638 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 639 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 640 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 641 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 642 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 643 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 644 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 645 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 646 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 647 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 648 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 649 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 650 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 651 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 652 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 653 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 654 }, t6_pciids[] = { 655 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 656 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 657 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 658 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 659 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 660 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 661 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 662 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 663 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 664 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 665 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 666 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 667 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 668 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 669 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 670 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 671 672 /* Custom */ 673 {0x6480, "Custom T6225-CR"}, 674 {0x6481, "Custom T62100-CR"}, 675 {0x6482, "Custom T6225-CR"}, 676 {0x6483, "Custom T62100-CR"}, 677 {0x6484, "Custom T64100-CR"}, 678 {0x6485, "Custom T6240-SO"}, 679 {0x6486, "Custom T6225-SO-CR"}, 680 {0x6487, "Custom T6225-CR"}, 681 }; 682 683 #ifdef TCP_OFFLOAD 684 /* 685 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 686 * exactly the same for both rxq and ofld_rxq. 687 */ 688 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 689 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 690 #endif 691 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 692 693 static int 694 t4_probe(device_t dev) 695 { 696 int i; 697 uint16_t v = pci_get_vendor(dev); 698 uint16_t d = pci_get_device(dev); 699 uint8_t f = pci_get_function(dev); 700 701 if (v != PCI_VENDOR_ID_CHELSIO) 702 return (ENXIO); 703 704 /* Attach only to PF0 of the FPGA */ 705 if (d == 0xa000 && f != 0) 706 return (ENXIO); 707 708 for (i = 0; i < nitems(t4_pciids); i++) { 709 if (d == t4_pciids[i].device) { 710 device_set_desc(dev, t4_pciids[i].desc); 711 return (BUS_PROBE_DEFAULT); 712 } 713 } 714 715 return (ENXIO); 716 } 717 718 static int 719 t5_probe(device_t dev) 720 { 721 int i; 722 uint16_t v = pci_get_vendor(dev); 723 uint16_t d = pci_get_device(dev); 724 uint8_t f = pci_get_function(dev); 725 726 if (v != PCI_VENDOR_ID_CHELSIO) 727 return (ENXIO); 728 729 /* Attach only to PF0 of the FPGA */ 730 if (d == 0xb000 && f != 0) 731 return (ENXIO); 732 733 for (i = 0; i < nitems(t5_pciids); i++) { 734 if (d == t5_pciids[i].device) { 735 device_set_desc(dev, t5_pciids[i].desc); 736 return (BUS_PROBE_DEFAULT); 737 } 738 } 739 740 return (ENXIO); 741 } 742 743 static int 744 t6_probe(device_t dev) 745 { 746 int i; 747 uint16_t v = pci_get_vendor(dev); 748 uint16_t d = pci_get_device(dev); 749 750 if (v != PCI_VENDOR_ID_CHELSIO) 751 return (ENXIO); 752 753 for (i = 0; i < nitems(t6_pciids); i++) { 754 if (d == t6_pciids[i].device) { 755 device_set_desc(dev, t6_pciids[i].desc); 756 return (BUS_PROBE_DEFAULT); 757 } 758 } 759 760 return (ENXIO); 761 } 762 763 static void 764 t5_attribute_workaround(device_t dev) 765 { 766 device_t root_port; 767 uint32_t v; 768 769 /* 770 * The T5 chips do not properly echo the No Snoop and Relaxed 771 * Ordering attributes when replying to a TLP from a Root 772 * Port. As a workaround, find the parent Root Port and 773 * disable No Snoop and Relaxed Ordering. Note that this 774 * affects all devices under this root port. 775 */ 776 root_port = pci_find_pcie_root_port(dev); 777 if (root_port == NULL) { 778 device_printf(dev, "Unable to find parent root port\n"); 779 return; 780 } 781 782 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 783 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 784 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 785 0) 786 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 787 device_get_nameunit(root_port)); 788 } 789 790 static const struct devnames devnames[] = { 791 { 792 .nexus_name = "t4nex", 793 .ifnet_name = "cxgbe", 794 .vi_ifnet_name = "vcxgbe", 795 .pf03_drv_name = "t4iov", 796 .vf_nexus_name = "t4vf", 797 .vf_ifnet_name = "cxgbev" 798 }, { 799 .nexus_name = "t5nex", 800 .ifnet_name = "cxl", 801 .vi_ifnet_name = "vcxl", 802 .pf03_drv_name = "t5iov", 803 .vf_nexus_name = "t5vf", 804 .vf_ifnet_name = "cxlv" 805 }, { 806 .nexus_name = "t6nex", 807 .ifnet_name = "cc", 808 .vi_ifnet_name = "vcc", 809 .pf03_drv_name = "t6iov", 810 .vf_nexus_name = "t6vf", 811 .vf_ifnet_name = "ccv" 812 } 813 }; 814 815 void 816 t4_init_devnames(struct adapter *sc) 817 { 818 int id; 819 820 id = chip_id(sc); 821 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 822 sc->names = &devnames[id - CHELSIO_T4]; 823 else { 824 device_printf(sc->dev, "chip id %d is not supported.\n", id); 825 sc->names = NULL; 826 } 827 } 828 829 static int 830 t4_attach(device_t dev) 831 { 832 struct adapter *sc; 833 int rc = 0, i, j, rqidx, tqidx, nports; 834 struct make_dev_args mda; 835 struct intrs_and_queues iaq; 836 struct sge *s; 837 uint32_t *buf; 838 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 839 int ofld_tqidx; 840 #endif 841 #ifdef TCP_OFFLOAD 842 int ofld_rqidx; 843 #endif 844 #ifdef DEV_NETMAP 845 int nm_rqidx, nm_tqidx; 846 #endif 847 int num_vis; 848 849 sc = device_get_softc(dev); 850 sc->dev = dev; 851 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 852 853 if ((pci_get_device(dev) & 0xff00) == 0x5400) 854 t5_attribute_workaround(dev); 855 pci_enable_busmaster(dev); 856 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 857 uint32_t v; 858 859 pci_set_max_read_req(dev, 4096); 860 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 861 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 862 if (pcie_relaxed_ordering == 0 && 863 (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 864 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 865 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 866 } else if (pcie_relaxed_ordering == 1 && 867 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 868 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 869 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 870 } 871 } 872 873 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 874 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 875 sc->traceq = -1; 876 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 877 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 878 device_get_nameunit(dev)); 879 880 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 881 device_get_nameunit(dev)); 882 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 883 t4_add_adapter(sc); 884 885 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 886 TAILQ_INIT(&sc->sfl); 887 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 888 889 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 890 891 sc->policy = NULL; 892 rw_init(&sc->policy_lock, "connection offload policy"); 893 894 rc = t4_map_bars_0_and_4(sc); 895 if (rc != 0) 896 goto done; /* error message displayed already */ 897 898 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 899 900 /* Prepare the adapter for operation. */ 901 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 902 rc = -t4_prep_adapter(sc, buf); 903 free(buf, M_CXGBE); 904 if (rc != 0) { 905 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 906 goto done; 907 } 908 909 /* 910 * This is the real PF# to which we're attaching. Works from within PCI 911 * passthrough environments too, where pci_get_function() could return a 912 * different PF# depending on the passthrough configuration. We need to 913 * use the real PF# in all our communication with the firmware. 914 */ 915 j = t4_read_reg(sc, A_PL_WHOAMI); 916 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 917 sc->mbox = sc->pf; 918 919 t4_init_devnames(sc); 920 if (sc->names == NULL) { 921 rc = ENOTSUP; 922 goto done; /* error message displayed already */ 923 } 924 925 /* 926 * Do this really early, with the memory windows set up even before the 927 * character device. The userland tool's register i/o and mem read 928 * will work even in "recovery mode". 929 */ 930 setup_memwin(sc); 931 if (t4_init_devlog_params(sc, 0) == 0) 932 fixup_devlog_params(sc); 933 make_dev_args_init(&mda); 934 mda.mda_devsw = &t4_cdevsw; 935 mda.mda_uid = UID_ROOT; 936 mda.mda_gid = GID_WHEEL; 937 mda.mda_mode = 0600; 938 mda.mda_si_drv1 = sc; 939 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 940 if (rc != 0) 941 device_printf(dev, "failed to create nexus char device: %d.\n", 942 rc); 943 944 /* Go no further if recovery mode has been requested. */ 945 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 946 device_printf(dev, "recovery mode.\n"); 947 goto done; 948 } 949 950 #if defined(__i386__) 951 if ((cpu_feature & CPUID_CX8) == 0) { 952 device_printf(dev, "64 bit atomics not available.\n"); 953 rc = ENOTSUP; 954 goto done; 955 } 956 #endif 957 958 /* Prepare the firmware for operation */ 959 rc = prep_firmware(sc); 960 if (rc != 0) 961 goto done; /* error message displayed already */ 962 963 rc = get_params__post_init(sc); 964 if (rc != 0) 965 goto done; /* error message displayed already */ 966 967 rc = set_params__post_init(sc); 968 if (rc != 0) 969 goto done; /* error message displayed already */ 970 971 rc = t4_map_bar_2(sc); 972 if (rc != 0) 973 goto done; /* error message displayed already */ 974 975 rc = t4_create_dma_tag(sc); 976 if (rc != 0) 977 goto done; /* error message displayed already */ 978 979 /* 980 * First pass over all the ports - allocate VIs and initialize some 981 * basic parameters like mac address, port type, etc. 982 */ 983 for_each_port(sc, i) { 984 struct port_info *pi; 985 986 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 987 sc->port[i] = pi; 988 989 /* These must be set before t4_port_init */ 990 pi->adapter = sc; 991 pi->port_id = i; 992 /* 993 * XXX: vi[0] is special so we can't delay this allocation until 994 * pi->nvi's final value is known. 995 */ 996 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 997 M_ZERO | M_WAITOK); 998 999 /* 1000 * Allocate the "main" VI and initialize parameters 1001 * like mac addr. 1002 */ 1003 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1004 if (rc != 0) { 1005 device_printf(dev, "unable to initialize port %d: %d\n", 1006 i, rc); 1007 free(pi->vi, M_CXGBE); 1008 free(pi, M_CXGBE); 1009 sc->port[i] = NULL; 1010 goto done; 1011 } 1012 1013 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1014 device_get_nameunit(dev), i); 1015 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1016 sc->chan_map[pi->tx_chan] = i; 1017 1018 /* All VIs on this port share this media. */ 1019 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1020 cxgbe_media_status); 1021 1022 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1); 1023 if (pi->dev == NULL) { 1024 device_printf(dev, 1025 "failed to add device for port %d.\n", i); 1026 rc = ENXIO; 1027 goto done; 1028 } 1029 pi->vi[0].dev = pi->dev; 1030 device_set_softc(pi->dev, pi); 1031 } 1032 1033 /* 1034 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1035 */ 1036 nports = sc->params.nports; 1037 rc = cfg_itype_and_nqueues(sc, &iaq); 1038 if (rc != 0) 1039 goto done; /* error message displayed already */ 1040 1041 num_vis = iaq.num_vis; 1042 sc->intr_type = iaq.intr_type; 1043 sc->intr_count = iaq.nirq; 1044 1045 s = &sc->sge; 1046 s->nrxq = nports * iaq.nrxq; 1047 s->ntxq = nports * iaq.ntxq; 1048 if (num_vis > 1) { 1049 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1050 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1051 } 1052 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1053 s->neq += nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 1054 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1055 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1056 if (is_offload(sc) || is_ethoffload(sc)) { 1057 s->nofldtxq = nports * iaq.nofldtxq; 1058 if (num_vis > 1) 1059 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1060 s->neq += s->nofldtxq; 1061 1062 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1063 M_CXGBE, M_ZERO | M_WAITOK); 1064 } 1065 #endif 1066 #ifdef TCP_OFFLOAD 1067 if (is_offload(sc)) { 1068 s->nofldrxq = nports * iaq.nofldrxq; 1069 if (num_vis > 1) 1070 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1071 s->neq += s->nofldrxq; /* free list */ 1072 s->niq += s->nofldrxq; 1073 1074 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1075 M_CXGBE, M_ZERO | M_WAITOK); 1076 } 1077 #endif 1078 #ifdef DEV_NETMAP 1079 if (num_vis > 1) { 1080 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1081 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1082 } 1083 s->neq += s->nnmtxq + s->nnmrxq; 1084 s->niq += s->nnmrxq; 1085 1086 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1087 M_CXGBE, M_ZERO | M_WAITOK); 1088 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1089 M_CXGBE, M_ZERO | M_WAITOK); 1090 #endif 1091 1092 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1093 M_ZERO | M_WAITOK); 1094 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1095 M_ZERO | M_WAITOK); 1096 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1097 M_ZERO | M_WAITOK); 1098 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1099 M_ZERO | M_WAITOK); 1100 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1101 M_ZERO | M_WAITOK); 1102 1103 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1104 M_ZERO | M_WAITOK); 1105 1106 t4_init_l2t(sc, M_WAITOK); 1107 t4_init_tx_sched(sc); 1108 #ifdef RATELIMIT 1109 t4_init_etid_table(sc); 1110 #endif 1111 1112 /* 1113 * Second pass over the ports. This time we know the number of rx and 1114 * tx queues that each port should get. 1115 */ 1116 rqidx = tqidx = 0; 1117 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1118 ofld_tqidx = 0; 1119 #endif 1120 #ifdef TCP_OFFLOAD 1121 ofld_rqidx = 0; 1122 #endif 1123 #ifdef DEV_NETMAP 1124 nm_rqidx = nm_tqidx = 0; 1125 #endif 1126 for_each_port(sc, i) { 1127 struct port_info *pi = sc->port[i]; 1128 struct vi_info *vi; 1129 1130 if (pi == NULL) 1131 continue; 1132 1133 pi->nvi = num_vis; 1134 for_each_vi(pi, j, vi) { 1135 vi->pi = pi; 1136 vi->qsize_rxq = t4_qsize_rxq; 1137 vi->qsize_txq = t4_qsize_txq; 1138 1139 vi->first_rxq = rqidx; 1140 vi->first_txq = tqidx; 1141 vi->tmr_idx = t4_tmr_idx; 1142 vi->pktc_idx = t4_pktc_idx; 1143 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1144 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1145 1146 rqidx += vi->nrxq; 1147 tqidx += vi->ntxq; 1148 1149 if (j == 0 && vi->ntxq > 1) 1150 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1151 else 1152 vi->rsrv_noflowq = 0; 1153 1154 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1155 vi->first_ofld_txq = ofld_tqidx; 1156 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1157 ofld_tqidx += vi->nofldtxq; 1158 #endif 1159 #ifdef TCP_OFFLOAD 1160 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1161 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1162 vi->first_ofld_rxq = ofld_rqidx; 1163 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1164 1165 ofld_rqidx += vi->nofldrxq; 1166 #endif 1167 #ifdef DEV_NETMAP 1168 if (j > 0) { 1169 vi->first_nm_rxq = nm_rqidx; 1170 vi->first_nm_txq = nm_tqidx; 1171 vi->nnmrxq = iaq.nnmrxq_vi; 1172 vi->nnmtxq = iaq.nnmtxq_vi; 1173 nm_rqidx += vi->nnmrxq; 1174 nm_tqidx += vi->nnmtxq; 1175 } 1176 #endif 1177 } 1178 } 1179 1180 rc = t4_setup_intr_handlers(sc); 1181 if (rc != 0) { 1182 device_printf(dev, 1183 "failed to setup interrupt handlers: %d\n", rc); 1184 goto done; 1185 } 1186 1187 rc = bus_generic_probe(dev); 1188 if (rc != 0) { 1189 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1190 goto done; 1191 } 1192 1193 /* 1194 * Ensure thread-safe mailbox access (in debug builds). 1195 * 1196 * So far this was the only thread accessing the mailbox but various 1197 * ifnets and sysctls are about to be created and their handlers/ioctls 1198 * will access the mailbox from different threads. 1199 */ 1200 sc->flags |= CHK_MBOX_ACCESS; 1201 1202 rc = bus_generic_attach(dev); 1203 if (rc != 0) { 1204 device_printf(dev, 1205 "failed to attach all child ports: %d\n", rc); 1206 goto done; 1207 } 1208 1209 device_printf(dev, 1210 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1211 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1212 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1213 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1214 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1215 1216 t4_set_desc(sc); 1217 1218 notify_siblings(dev, 0); 1219 1220 done: 1221 if (rc != 0 && sc->cdev) { 1222 /* cdev was created and so cxgbetool works; recover that way. */ 1223 device_printf(dev, 1224 "error during attach, adapter is now in recovery mode.\n"); 1225 rc = 0; 1226 } 1227 1228 if (rc != 0) 1229 t4_detach_common(dev); 1230 else 1231 t4_sysctls(sc); 1232 1233 return (rc); 1234 } 1235 1236 static int 1237 t4_ready(device_t dev) 1238 { 1239 struct adapter *sc; 1240 1241 sc = device_get_softc(dev); 1242 if (sc->flags & FW_OK) 1243 return (0); 1244 return (ENXIO); 1245 } 1246 1247 static int 1248 t4_read_port_device(device_t dev, int port, device_t *child) 1249 { 1250 struct adapter *sc; 1251 struct port_info *pi; 1252 1253 sc = device_get_softc(dev); 1254 if (port < 0 || port >= MAX_NPORTS) 1255 return (EINVAL); 1256 pi = sc->port[port]; 1257 if (pi == NULL || pi->dev == NULL) 1258 return (ENXIO); 1259 *child = pi->dev; 1260 return (0); 1261 } 1262 1263 static int 1264 notify_siblings(device_t dev, int detaching) 1265 { 1266 device_t sibling; 1267 int error, i; 1268 1269 error = 0; 1270 for (i = 0; i < PCI_FUNCMAX; i++) { 1271 if (i == pci_get_function(dev)) 1272 continue; 1273 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1274 pci_get_slot(dev), i); 1275 if (sibling == NULL || !device_is_attached(sibling)) 1276 continue; 1277 if (detaching) 1278 error = T4_DETACH_CHILD(sibling); 1279 else 1280 (void)T4_ATTACH_CHILD(sibling); 1281 if (error) 1282 break; 1283 } 1284 return (error); 1285 } 1286 1287 /* 1288 * Idempotent 1289 */ 1290 static int 1291 t4_detach(device_t dev) 1292 { 1293 struct adapter *sc; 1294 int rc; 1295 1296 sc = device_get_softc(dev); 1297 1298 rc = notify_siblings(dev, 1); 1299 if (rc) { 1300 device_printf(dev, 1301 "failed to detach sibling devices: %d\n", rc); 1302 return (rc); 1303 } 1304 1305 return (t4_detach_common(dev)); 1306 } 1307 1308 int 1309 t4_detach_common(device_t dev) 1310 { 1311 struct adapter *sc; 1312 struct port_info *pi; 1313 int i, rc; 1314 1315 sc = device_get_softc(dev); 1316 1317 if (sc->cdev) { 1318 destroy_dev(sc->cdev); 1319 sc->cdev = NULL; 1320 } 1321 1322 sc->flags &= ~CHK_MBOX_ACCESS; 1323 if (sc->flags & FULL_INIT_DONE) { 1324 if (!(sc->flags & IS_VF)) 1325 t4_intr_disable(sc); 1326 } 1327 1328 if (device_is_attached(dev)) { 1329 rc = bus_generic_detach(dev); 1330 if (rc) { 1331 device_printf(dev, 1332 "failed to detach child devices: %d\n", rc); 1333 return (rc); 1334 } 1335 } 1336 1337 for (i = 0; i < sc->intr_count; i++) 1338 t4_free_irq(sc, &sc->irq[i]); 1339 1340 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1341 t4_free_tx_sched(sc); 1342 1343 for (i = 0; i < MAX_NPORTS; i++) { 1344 pi = sc->port[i]; 1345 if (pi) { 1346 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1347 if (pi->dev) 1348 device_delete_child(dev, pi->dev); 1349 1350 mtx_destroy(&pi->pi_lock); 1351 free(pi->vi, M_CXGBE); 1352 free(pi, M_CXGBE); 1353 } 1354 } 1355 1356 device_delete_children(dev); 1357 1358 if (sc->flags & FULL_INIT_DONE) 1359 adapter_full_uninit(sc); 1360 1361 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1362 t4_fw_bye(sc, sc->mbox); 1363 1364 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1365 pci_release_msi(dev); 1366 1367 if (sc->regs_res) 1368 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1369 sc->regs_res); 1370 1371 if (sc->udbs_res) 1372 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1373 sc->udbs_res); 1374 1375 if (sc->msix_res) 1376 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1377 sc->msix_res); 1378 1379 if (sc->l2t) 1380 t4_free_l2t(sc->l2t); 1381 #ifdef RATELIMIT 1382 t4_free_etid_table(sc); 1383 #endif 1384 1385 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1386 free(sc->sge.ofld_txq, M_CXGBE); 1387 #endif 1388 #ifdef TCP_OFFLOAD 1389 free(sc->sge.ofld_rxq, M_CXGBE); 1390 #endif 1391 #ifdef DEV_NETMAP 1392 free(sc->sge.nm_rxq, M_CXGBE); 1393 free(sc->sge.nm_txq, M_CXGBE); 1394 #endif 1395 free(sc->irq, M_CXGBE); 1396 free(sc->sge.rxq, M_CXGBE); 1397 free(sc->sge.txq, M_CXGBE); 1398 free(sc->sge.ctrlq, M_CXGBE); 1399 free(sc->sge.iqmap, M_CXGBE); 1400 free(sc->sge.eqmap, M_CXGBE); 1401 free(sc->tids.ftid_tab, M_CXGBE); 1402 free(sc->tids.hftid_tab, M_CXGBE); 1403 free(sc->tids.atid_tab, M_CXGBE); 1404 free(sc->tids.tid_tab, M_CXGBE); 1405 free(sc->tt.tls_rx_ports, M_CXGBE); 1406 t4_destroy_dma_tag(sc); 1407 if (mtx_initialized(&sc->sc_lock)) { 1408 sx_xlock(&t4_list_lock); 1409 SLIST_REMOVE(&t4_list, sc, adapter, link); 1410 sx_xunlock(&t4_list_lock); 1411 mtx_destroy(&sc->sc_lock); 1412 } 1413 1414 callout_drain(&sc->sfl_callout); 1415 if (mtx_initialized(&sc->tids.ftid_lock)) { 1416 mtx_destroy(&sc->tids.ftid_lock); 1417 cv_destroy(&sc->tids.ftid_cv); 1418 } 1419 if (mtx_initialized(&sc->tids.hftid_lock)) { 1420 mtx_destroy(&sc->tids.hftid_lock); 1421 cv_destroy(&sc->tids.hftid_cv); 1422 } 1423 if (mtx_initialized(&sc->tids.atid_lock)) 1424 mtx_destroy(&sc->tids.atid_lock); 1425 if (mtx_initialized(&sc->sfl_lock)) 1426 mtx_destroy(&sc->sfl_lock); 1427 if (mtx_initialized(&sc->ifp_lock)) 1428 mtx_destroy(&sc->ifp_lock); 1429 if (mtx_initialized(&sc->reg_lock)) 1430 mtx_destroy(&sc->reg_lock); 1431 1432 if (rw_initialized(&sc->policy_lock)) { 1433 rw_destroy(&sc->policy_lock); 1434 #ifdef TCP_OFFLOAD 1435 if (sc->policy != NULL) 1436 free_offload_policy(sc->policy); 1437 #endif 1438 } 1439 1440 for (i = 0; i < NUM_MEMWIN; i++) { 1441 struct memwin *mw = &sc->memwin[i]; 1442 1443 if (rw_initialized(&mw->mw_lock)) 1444 rw_destroy(&mw->mw_lock); 1445 } 1446 1447 bzero(sc, sizeof(*sc)); 1448 1449 return (0); 1450 } 1451 1452 static int 1453 cxgbe_probe(device_t dev) 1454 { 1455 char buf[128]; 1456 struct port_info *pi = device_get_softc(dev); 1457 1458 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1459 device_set_desc_copy(dev, buf); 1460 1461 return (BUS_PROBE_DEFAULT); 1462 } 1463 1464 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1465 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1466 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1467 #define T4_CAP_ENABLE (T4_CAP) 1468 1469 static int 1470 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1471 { 1472 struct ifnet *ifp; 1473 struct sbuf *sb; 1474 1475 vi->xact_addr_filt = -1; 1476 callout_init(&vi->tick, 1); 1477 1478 /* Allocate an ifnet and set it up */ 1479 ifp = if_alloc(IFT_ETHER); 1480 if (ifp == NULL) { 1481 device_printf(dev, "Cannot allocate ifnet\n"); 1482 return (ENOMEM); 1483 } 1484 vi->ifp = ifp; 1485 ifp->if_softc = vi; 1486 1487 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1488 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1489 1490 ifp->if_init = cxgbe_init; 1491 ifp->if_ioctl = cxgbe_ioctl; 1492 ifp->if_transmit = cxgbe_transmit; 1493 ifp->if_qflush = cxgbe_qflush; 1494 ifp->if_get_counter = cxgbe_get_counter; 1495 #ifdef RATELIMIT 1496 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 1497 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify; 1498 ifp->if_snd_tag_query = cxgbe_snd_tag_query; 1499 ifp->if_snd_tag_free = cxgbe_snd_tag_free; 1500 #endif 1501 1502 ifp->if_capabilities = T4_CAP; 1503 #ifdef TCP_OFFLOAD 1504 if (vi->nofldrxq != 0) 1505 ifp->if_capabilities |= IFCAP_TOE; 1506 #endif 1507 #ifdef DEV_NETMAP 1508 if (vi->nnmrxq != 0) 1509 ifp->if_capabilities |= IFCAP_NETMAP; 1510 #endif 1511 #ifdef RATELIMIT 1512 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) 1513 ifp->if_capabilities |= IFCAP_TXRTLMT; 1514 #endif 1515 ifp->if_capenable = T4_CAP_ENABLE; 1516 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1517 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1518 1519 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1520 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1521 ifp->if_hw_tsomaxsegsize = 65536; 1522 1523 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1524 EVENTHANDLER_PRI_ANY); 1525 1526 ether_ifattach(ifp, vi->hw_addr); 1527 #ifdef DEV_NETMAP 1528 if (ifp->if_capabilities & IFCAP_NETMAP) 1529 cxgbe_nm_attach(vi); 1530 #endif 1531 sb = sbuf_new_auto(); 1532 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1533 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1534 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 1535 case IFCAP_TOE: 1536 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 1537 break; 1538 case IFCAP_TOE | IFCAP_TXRTLMT: 1539 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 1540 break; 1541 case IFCAP_TXRTLMT: 1542 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 1543 break; 1544 } 1545 #endif 1546 #ifdef TCP_OFFLOAD 1547 if (ifp->if_capabilities & IFCAP_TOE) 1548 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 1549 #endif 1550 #ifdef DEV_NETMAP 1551 if (ifp->if_capabilities & IFCAP_NETMAP) 1552 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1553 vi->nnmtxq, vi->nnmrxq); 1554 #endif 1555 sbuf_finish(sb); 1556 device_printf(dev, "%s\n", sbuf_data(sb)); 1557 sbuf_delete(sb); 1558 1559 vi_sysctls(vi); 1560 1561 return (0); 1562 } 1563 1564 static int 1565 cxgbe_attach(device_t dev) 1566 { 1567 struct port_info *pi = device_get_softc(dev); 1568 struct adapter *sc = pi->adapter; 1569 struct vi_info *vi; 1570 int i, rc; 1571 1572 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1573 1574 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1575 if (rc) 1576 return (rc); 1577 1578 for_each_vi(pi, i, vi) { 1579 if (i == 0) 1580 continue; 1581 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1582 if (vi->dev == NULL) { 1583 device_printf(dev, "failed to add VI %d\n", i); 1584 continue; 1585 } 1586 device_set_softc(vi->dev, vi); 1587 } 1588 1589 cxgbe_sysctls(pi); 1590 1591 bus_generic_attach(dev); 1592 1593 return (0); 1594 } 1595 1596 static void 1597 cxgbe_vi_detach(struct vi_info *vi) 1598 { 1599 struct ifnet *ifp = vi->ifp; 1600 1601 ether_ifdetach(ifp); 1602 1603 if (vi->vlan_c) 1604 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1605 1606 /* Let detach proceed even if these fail. */ 1607 #ifdef DEV_NETMAP 1608 if (ifp->if_capabilities & IFCAP_NETMAP) 1609 cxgbe_nm_detach(vi); 1610 #endif 1611 cxgbe_uninit_synchronized(vi); 1612 callout_drain(&vi->tick); 1613 vi_full_uninit(vi); 1614 1615 if_free(vi->ifp); 1616 vi->ifp = NULL; 1617 } 1618 1619 static int 1620 cxgbe_detach(device_t dev) 1621 { 1622 struct port_info *pi = device_get_softc(dev); 1623 struct adapter *sc = pi->adapter; 1624 int rc; 1625 1626 /* Detach the extra VIs first. */ 1627 rc = bus_generic_detach(dev); 1628 if (rc) 1629 return (rc); 1630 device_delete_children(dev); 1631 1632 doom_vi(sc, &pi->vi[0]); 1633 1634 if (pi->flags & HAS_TRACEQ) { 1635 sc->traceq = -1; /* cloner should not create ifnet */ 1636 t4_tracer_port_detach(sc); 1637 } 1638 1639 cxgbe_vi_detach(&pi->vi[0]); 1640 callout_drain(&pi->tick); 1641 ifmedia_removeall(&pi->media); 1642 1643 end_synchronized_op(sc, 0); 1644 1645 return (0); 1646 } 1647 1648 static void 1649 cxgbe_init(void *arg) 1650 { 1651 struct vi_info *vi = arg; 1652 struct adapter *sc = vi->pi->adapter; 1653 1654 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1655 return; 1656 cxgbe_init_synchronized(vi); 1657 end_synchronized_op(sc, 0); 1658 } 1659 1660 static int 1661 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1662 { 1663 int rc = 0, mtu, flags, can_sleep; 1664 struct vi_info *vi = ifp->if_softc; 1665 struct port_info *pi = vi->pi; 1666 struct adapter *sc = pi->adapter; 1667 struct ifreq *ifr = (struct ifreq *)data; 1668 uint32_t mask; 1669 1670 switch (cmd) { 1671 case SIOCSIFMTU: 1672 mtu = ifr->ifr_mtu; 1673 if (mtu < ETHERMIN || mtu > MAX_MTU) 1674 return (EINVAL); 1675 1676 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1677 if (rc) 1678 return (rc); 1679 ifp->if_mtu = mtu; 1680 if (vi->flags & VI_INIT_DONE) { 1681 t4_update_fl_bufsize(ifp); 1682 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1683 rc = update_mac_settings(ifp, XGMAC_MTU); 1684 } 1685 end_synchronized_op(sc, 0); 1686 break; 1687 1688 case SIOCSIFFLAGS: 1689 can_sleep = 0; 1690 redo_sifflags: 1691 rc = begin_synchronized_op(sc, vi, 1692 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1693 if (rc) { 1694 if_printf(ifp, "%ssleepable synch operation failed: %d." 1695 " if_flags 0x%08x, if_drv_flags 0x%08x\n", 1696 can_sleep ? "" : "non-", rc, ifp->if_flags, 1697 ifp->if_drv_flags); 1698 return (rc); 1699 } 1700 1701 if (ifp->if_flags & IFF_UP) { 1702 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1703 flags = vi->if_flags; 1704 if ((ifp->if_flags ^ flags) & 1705 (IFF_PROMISC | IFF_ALLMULTI)) { 1706 if (can_sleep == 1) { 1707 end_synchronized_op(sc, 0); 1708 can_sleep = 0; 1709 goto redo_sifflags; 1710 } 1711 rc = update_mac_settings(ifp, 1712 XGMAC_PROMISC | XGMAC_ALLMULTI); 1713 } 1714 } else { 1715 if (can_sleep == 0) { 1716 end_synchronized_op(sc, LOCK_HELD); 1717 can_sleep = 1; 1718 goto redo_sifflags; 1719 } 1720 rc = cxgbe_init_synchronized(vi); 1721 } 1722 vi->if_flags = ifp->if_flags; 1723 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1724 if (can_sleep == 0) { 1725 end_synchronized_op(sc, LOCK_HELD); 1726 can_sleep = 1; 1727 goto redo_sifflags; 1728 } 1729 rc = cxgbe_uninit_synchronized(vi); 1730 } 1731 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1732 break; 1733 1734 case SIOCADDMULTI: 1735 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1736 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1737 if (rc) 1738 return (rc); 1739 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1740 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1741 end_synchronized_op(sc, LOCK_HELD); 1742 break; 1743 1744 case SIOCSIFCAP: 1745 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1746 if (rc) 1747 return (rc); 1748 1749 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1750 if (mask & IFCAP_TXCSUM) { 1751 ifp->if_capenable ^= IFCAP_TXCSUM; 1752 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1753 1754 if (IFCAP_TSO4 & ifp->if_capenable && 1755 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1756 ifp->if_capenable &= ~IFCAP_TSO4; 1757 if_printf(ifp, 1758 "tso4 disabled due to -txcsum.\n"); 1759 } 1760 } 1761 if (mask & IFCAP_TXCSUM_IPV6) { 1762 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1763 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1764 1765 if (IFCAP_TSO6 & ifp->if_capenable && 1766 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1767 ifp->if_capenable &= ~IFCAP_TSO6; 1768 if_printf(ifp, 1769 "tso6 disabled due to -txcsum6.\n"); 1770 } 1771 } 1772 if (mask & IFCAP_RXCSUM) 1773 ifp->if_capenable ^= IFCAP_RXCSUM; 1774 if (mask & IFCAP_RXCSUM_IPV6) 1775 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1776 1777 /* 1778 * Note that we leave CSUM_TSO alone (it is always set). The 1779 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1780 * sending a TSO request our way, so it's sufficient to toggle 1781 * IFCAP_TSOx only. 1782 */ 1783 if (mask & IFCAP_TSO4) { 1784 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1785 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1786 if_printf(ifp, "enable txcsum first.\n"); 1787 rc = EAGAIN; 1788 goto fail; 1789 } 1790 ifp->if_capenable ^= IFCAP_TSO4; 1791 } 1792 if (mask & IFCAP_TSO6) { 1793 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1794 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1795 if_printf(ifp, "enable txcsum6 first.\n"); 1796 rc = EAGAIN; 1797 goto fail; 1798 } 1799 ifp->if_capenable ^= IFCAP_TSO6; 1800 } 1801 if (mask & IFCAP_LRO) { 1802 #if defined(INET) || defined(INET6) 1803 int i; 1804 struct sge_rxq *rxq; 1805 1806 ifp->if_capenable ^= IFCAP_LRO; 1807 for_each_rxq(vi, i, rxq) { 1808 if (ifp->if_capenable & IFCAP_LRO) 1809 rxq->iq.flags |= IQ_LRO_ENABLED; 1810 else 1811 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1812 } 1813 #endif 1814 } 1815 #ifdef TCP_OFFLOAD 1816 if (mask & IFCAP_TOE) { 1817 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1818 1819 rc = toe_capability(vi, enable); 1820 if (rc != 0) 1821 goto fail; 1822 1823 ifp->if_capenable ^= mask; 1824 } 1825 #endif 1826 if (mask & IFCAP_VLAN_HWTAGGING) { 1827 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1828 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1829 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1830 } 1831 if (mask & IFCAP_VLAN_MTU) { 1832 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1833 1834 /* Need to find out how to disable auto-mtu-inflation */ 1835 } 1836 if (mask & IFCAP_VLAN_HWTSO) 1837 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1838 if (mask & IFCAP_VLAN_HWCSUM) 1839 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1840 #ifdef RATELIMIT 1841 if (mask & IFCAP_TXRTLMT) 1842 ifp->if_capenable ^= IFCAP_TXRTLMT; 1843 #endif 1844 1845 #ifdef VLAN_CAPABILITIES 1846 VLAN_CAPABILITIES(ifp); 1847 #endif 1848 fail: 1849 end_synchronized_op(sc, 0); 1850 break; 1851 1852 case SIOCSIFMEDIA: 1853 case SIOCGIFMEDIA: 1854 case SIOCGIFXMEDIA: 1855 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 1856 break; 1857 1858 case SIOCGI2C: { 1859 struct ifi2creq i2c; 1860 1861 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 1862 if (rc != 0) 1863 break; 1864 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1865 rc = EPERM; 1866 break; 1867 } 1868 if (i2c.len > sizeof(i2c.data)) { 1869 rc = EINVAL; 1870 break; 1871 } 1872 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1873 if (rc) 1874 return (rc); 1875 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 1876 i2c.offset, i2c.len, &i2c.data[0]); 1877 end_synchronized_op(sc, 0); 1878 if (rc == 0) 1879 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 1880 break; 1881 } 1882 1883 default: 1884 rc = ether_ioctl(ifp, cmd, data); 1885 } 1886 1887 return (rc); 1888 } 1889 1890 static int 1891 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1892 { 1893 struct vi_info *vi = ifp->if_softc; 1894 struct port_info *pi = vi->pi; 1895 struct adapter *sc = pi->adapter; 1896 struct sge_txq *txq; 1897 void *items[1]; 1898 int rc; 1899 1900 M_ASSERTPKTHDR(m); 1901 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1902 1903 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1904 m_freem(m); 1905 return (ENETDOWN); 1906 } 1907 1908 rc = parse_pkt(sc, &m); 1909 if (__predict_false(rc != 0)) { 1910 MPASS(m == NULL); /* was freed already */ 1911 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1912 return (rc); 1913 } 1914 #ifdef RATELIMIT 1915 if (m->m_pkthdr.snd_tag != NULL) { 1916 /* EAGAIN tells the stack we are not the correct interface. */ 1917 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) { 1918 m_freem(m); 1919 return (EAGAIN); 1920 } 1921 1922 return (ethofld_transmit(ifp, m)); 1923 } 1924 #endif 1925 1926 /* Select a txq. */ 1927 txq = &sc->sge.txq[vi->first_txq]; 1928 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1929 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1930 vi->rsrv_noflowq); 1931 1932 items[0] = m; 1933 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 1934 if (__predict_false(rc != 0)) 1935 m_freem(m); 1936 1937 return (rc); 1938 } 1939 1940 static void 1941 cxgbe_qflush(struct ifnet *ifp) 1942 { 1943 struct vi_info *vi = ifp->if_softc; 1944 struct sge_txq *txq; 1945 int i; 1946 1947 /* queues do not exist if !VI_INIT_DONE. */ 1948 if (vi->flags & VI_INIT_DONE) { 1949 for_each_txq(vi, i, txq) { 1950 TXQ_LOCK(txq); 1951 txq->eq.flags |= EQ_QFLUSH; 1952 TXQ_UNLOCK(txq); 1953 while (!mp_ring_is_idle(txq->r)) { 1954 mp_ring_check_drainage(txq->r, 0); 1955 pause("qflush", 1); 1956 } 1957 TXQ_LOCK(txq); 1958 txq->eq.flags &= ~EQ_QFLUSH; 1959 TXQ_UNLOCK(txq); 1960 } 1961 } 1962 if_qflush(ifp); 1963 } 1964 1965 static uint64_t 1966 vi_get_counter(struct ifnet *ifp, ift_counter c) 1967 { 1968 struct vi_info *vi = ifp->if_softc; 1969 struct fw_vi_stats_vf *s = &vi->stats; 1970 1971 vi_refresh_stats(vi->pi->adapter, vi); 1972 1973 switch (c) { 1974 case IFCOUNTER_IPACKETS: 1975 return (s->rx_bcast_frames + s->rx_mcast_frames + 1976 s->rx_ucast_frames); 1977 case IFCOUNTER_IERRORS: 1978 return (s->rx_err_frames); 1979 case IFCOUNTER_OPACKETS: 1980 return (s->tx_bcast_frames + s->tx_mcast_frames + 1981 s->tx_ucast_frames + s->tx_offload_frames); 1982 case IFCOUNTER_OERRORS: 1983 return (s->tx_drop_frames); 1984 case IFCOUNTER_IBYTES: 1985 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 1986 s->rx_ucast_bytes); 1987 case IFCOUNTER_OBYTES: 1988 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 1989 s->tx_ucast_bytes + s->tx_offload_bytes); 1990 case IFCOUNTER_IMCASTS: 1991 return (s->rx_mcast_frames); 1992 case IFCOUNTER_OMCASTS: 1993 return (s->tx_mcast_frames); 1994 case IFCOUNTER_OQDROPS: { 1995 uint64_t drops; 1996 1997 drops = 0; 1998 if (vi->flags & VI_INIT_DONE) { 1999 int i; 2000 struct sge_txq *txq; 2001 2002 for_each_txq(vi, i, txq) 2003 drops += counter_u64_fetch(txq->r->drops); 2004 } 2005 2006 return (drops); 2007 2008 } 2009 2010 default: 2011 return (if_get_counter_default(ifp, c)); 2012 } 2013 } 2014 2015 uint64_t 2016 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2017 { 2018 struct vi_info *vi = ifp->if_softc; 2019 struct port_info *pi = vi->pi; 2020 struct adapter *sc = pi->adapter; 2021 struct port_stats *s = &pi->stats; 2022 2023 if (pi->nvi > 1 || sc->flags & IS_VF) 2024 return (vi_get_counter(ifp, c)); 2025 2026 cxgbe_refresh_stats(sc, pi); 2027 2028 switch (c) { 2029 case IFCOUNTER_IPACKETS: 2030 return (s->rx_frames); 2031 2032 case IFCOUNTER_IERRORS: 2033 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2034 s->rx_fcs_err + s->rx_len_err); 2035 2036 case IFCOUNTER_OPACKETS: 2037 return (s->tx_frames); 2038 2039 case IFCOUNTER_OERRORS: 2040 return (s->tx_error_frames); 2041 2042 case IFCOUNTER_IBYTES: 2043 return (s->rx_octets); 2044 2045 case IFCOUNTER_OBYTES: 2046 return (s->tx_octets); 2047 2048 case IFCOUNTER_IMCASTS: 2049 return (s->rx_mcast_frames); 2050 2051 case IFCOUNTER_OMCASTS: 2052 return (s->tx_mcast_frames); 2053 2054 case IFCOUNTER_IQDROPS: 2055 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2056 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2057 s->rx_trunc3 + pi->tnl_cong_drops); 2058 2059 case IFCOUNTER_OQDROPS: { 2060 uint64_t drops; 2061 2062 drops = s->tx_drop; 2063 if (vi->flags & VI_INIT_DONE) { 2064 int i; 2065 struct sge_txq *txq; 2066 2067 for_each_txq(vi, i, txq) 2068 drops += counter_u64_fetch(txq->r->drops); 2069 } 2070 2071 return (drops); 2072 2073 } 2074 2075 default: 2076 return (if_get_counter_default(ifp, c)); 2077 } 2078 } 2079 2080 static int 2081 cxgbe_media_change(struct ifnet *ifp) 2082 { 2083 struct vi_info *vi = ifp->if_softc; 2084 2085 device_printf(vi->dev, "%s unimplemented.\n", __func__); 2086 2087 return (EOPNOTSUPP); 2088 } 2089 2090 static void 2091 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2092 { 2093 struct vi_info *vi = ifp->if_softc; 2094 struct port_info *pi = vi->pi; 2095 struct ifmedia_entry *cur; 2096 struct link_config *lc = &pi->link_cfg; 2097 2098 /* 2099 * If all the interfaces are administratively down the firmware does not 2100 * report transceiver changes. Refresh port info here so that ifconfig 2101 * displays accurate information at all times. 2102 */ 2103 if (begin_synchronized_op(pi->adapter, NULL, SLEEP_OK | INTR_OK, 2104 "t4med") == 0) { 2105 PORT_LOCK(pi); 2106 if (pi->up_vis == 0) { 2107 t4_update_port_info(pi); 2108 build_medialist(pi, &pi->media); 2109 } 2110 PORT_UNLOCK(pi); 2111 end_synchronized_op(pi->adapter, 0); 2112 } 2113 2114 ifmr->ifm_status = IFM_AVALID; 2115 if (lc->link_ok == 0) 2116 return; 2117 2118 ifmr->ifm_status |= IFM_ACTIVE; 2119 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2120 if (lc->fc & PAUSE_RX) 2121 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2122 if (lc->fc & PAUSE_TX) 2123 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2124 2125 /* active and current will differ iff current media is autoselect. */ 2126 cur = pi->media.ifm_cur; 2127 if (cur != NULL && IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 2128 return; 2129 2130 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2131 if (lc->fc & PAUSE_RX) 2132 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2133 if (lc->fc & PAUSE_TX) 2134 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2135 switch (lc->speed) { 2136 case 10000: 2137 ifmr->ifm_active |= IFM_10G_T; 2138 break; 2139 case 1000: 2140 ifmr->ifm_active |= IFM_1000_T; 2141 break; 2142 case 100: 2143 ifmr->ifm_active |= IFM_100_TX; 2144 break; 2145 case 10: 2146 ifmr->ifm_active |= IFM_10_T; 2147 break; 2148 default: 2149 device_printf(vi->dev, "link up but speed unknown (%u)\n", 2150 lc->speed); 2151 } 2152 } 2153 2154 static int 2155 vcxgbe_probe(device_t dev) 2156 { 2157 char buf[128]; 2158 struct vi_info *vi = device_get_softc(dev); 2159 2160 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2161 vi - vi->pi->vi); 2162 device_set_desc_copy(dev, buf); 2163 2164 return (BUS_PROBE_DEFAULT); 2165 } 2166 2167 static int 2168 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2169 { 2170 int func, index, rc; 2171 uint32_t param, val; 2172 2173 ASSERT_SYNCHRONIZED_OP(sc); 2174 2175 index = vi - pi->vi; 2176 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2177 KASSERT(index < nitems(vi_mac_funcs), 2178 ("%s: VI %s doesn't have a MAC func", __func__, 2179 device_get_nameunit(vi->dev))); 2180 func = vi_mac_funcs[index]; 2181 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2182 vi->hw_addr, &vi->rss_size, func, 0); 2183 if (rc < 0) { 2184 device_printf(vi->dev, "failed to allocate virtual interface %d" 2185 "for port %d: %d\n", index, pi->port_id, -rc); 2186 return (-rc); 2187 } 2188 vi->viid = rc; 2189 if (chip_id(sc) <= CHELSIO_T5) 2190 vi->smt_idx = (rc & 0x7f) << 1; 2191 else 2192 vi->smt_idx = (rc & 0x7f); 2193 2194 if (vi->rss_size == 1) { 2195 /* 2196 * This VI didn't get a slice of the RSS table. Reduce the 2197 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2198 * configuration file (nvi, rssnvi for this PF) if this is a 2199 * problem. 2200 */ 2201 device_printf(vi->dev, "RSS table not available.\n"); 2202 vi->rss_base = 0xffff; 2203 2204 return (0); 2205 } 2206 2207 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2208 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2209 V_FW_PARAMS_PARAM_YZ(vi->viid); 2210 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2211 if (rc) 2212 vi->rss_base = 0xffff; 2213 else { 2214 MPASS((val >> 16) == vi->rss_size); 2215 vi->rss_base = val & 0xffff; 2216 } 2217 2218 return (0); 2219 } 2220 2221 static int 2222 vcxgbe_attach(device_t dev) 2223 { 2224 struct vi_info *vi; 2225 struct port_info *pi; 2226 struct adapter *sc; 2227 int rc; 2228 2229 vi = device_get_softc(dev); 2230 pi = vi->pi; 2231 sc = pi->adapter; 2232 2233 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2234 if (rc) 2235 return (rc); 2236 rc = alloc_extra_vi(sc, pi, vi); 2237 end_synchronized_op(sc, 0); 2238 if (rc) 2239 return (rc); 2240 2241 rc = cxgbe_vi_attach(dev, vi); 2242 if (rc) { 2243 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2244 return (rc); 2245 } 2246 return (0); 2247 } 2248 2249 static int 2250 vcxgbe_detach(device_t dev) 2251 { 2252 struct vi_info *vi; 2253 struct adapter *sc; 2254 2255 vi = device_get_softc(dev); 2256 sc = vi->pi->adapter; 2257 2258 doom_vi(sc, vi); 2259 2260 cxgbe_vi_detach(vi); 2261 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2262 2263 end_synchronized_op(sc, 0); 2264 2265 return (0); 2266 } 2267 2268 void 2269 t4_fatal_err(struct adapter *sc) 2270 { 2271 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2272 t4_intr_disable(sc); 2273 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2274 device_get_nameunit(sc->dev)); 2275 if (t4_panic_on_fatal_err) 2276 panic("panic requested on fatal error"); 2277 } 2278 2279 void 2280 t4_add_adapter(struct adapter *sc) 2281 { 2282 sx_xlock(&t4_list_lock); 2283 SLIST_INSERT_HEAD(&t4_list, sc, link); 2284 sx_xunlock(&t4_list_lock); 2285 } 2286 2287 int 2288 t4_map_bars_0_and_4(struct adapter *sc) 2289 { 2290 sc->regs_rid = PCIR_BAR(0); 2291 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2292 &sc->regs_rid, RF_ACTIVE); 2293 if (sc->regs_res == NULL) { 2294 device_printf(sc->dev, "cannot map registers.\n"); 2295 return (ENXIO); 2296 } 2297 sc->bt = rman_get_bustag(sc->regs_res); 2298 sc->bh = rman_get_bushandle(sc->regs_res); 2299 sc->mmio_len = rman_get_size(sc->regs_res); 2300 setbit(&sc->doorbells, DOORBELL_KDB); 2301 2302 sc->msix_rid = PCIR_BAR(4); 2303 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2304 &sc->msix_rid, RF_ACTIVE); 2305 if (sc->msix_res == NULL) { 2306 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2307 return (ENXIO); 2308 } 2309 2310 return (0); 2311 } 2312 2313 int 2314 t4_map_bar_2(struct adapter *sc) 2315 { 2316 2317 /* 2318 * T4: only iWARP driver uses the userspace doorbells. There is no need 2319 * to map it if RDMA is disabled. 2320 */ 2321 if (is_t4(sc) && sc->rdmacaps == 0) 2322 return (0); 2323 2324 sc->udbs_rid = PCIR_BAR(2); 2325 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2326 &sc->udbs_rid, RF_ACTIVE); 2327 if (sc->udbs_res == NULL) { 2328 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2329 return (ENXIO); 2330 } 2331 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2332 2333 if (chip_id(sc) >= CHELSIO_T5) { 2334 setbit(&sc->doorbells, DOORBELL_UDB); 2335 #if defined(__i386__) || defined(__amd64__) 2336 if (t5_write_combine) { 2337 int rc, mode; 2338 2339 /* 2340 * Enable write combining on BAR2. This is the 2341 * userspace doorbell BAR and is split into 128B 2342 * (UDBS_SEG_SIZE) doorbell regions, each associated 2343 * with an egress queue. The first 64B has the doorbell 2344 * and the second 64B can be used to submit a tx work 2345 * request with an implicit doorbell. 2346 */ 2347 2348 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2349 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2350 if (rc == 0) { 2351 clrbit(&sc->doorbells, DOORBELL_UDB); 2352 setbit(&sc->doorbells, DOORBELL_WCWR); 2353 setbit(&sc->doorbells, DOORBELL_UDBWC); 2354 } else { 2355 device_printf(sc->dev, 2356 "couldn't enable write combining: %d\n", 2357 rc); 2358 } 2359 2360 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2361 t4_write_reg(sc, A_SGE_STAT_CFG, 2362 V_STATSOURCE_T5(7) | mode); 2363 } 2364 #endif 2365 } 2366 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2367 2368 return (0); 2369 } 2370 2371 struct memwin_init { 2372 uint32_t base; 2373 uint32_t aperture; 2374 }; 2375 2376 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2377 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2378 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2379 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2380 }; 2381 2382 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2383 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2384 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2385 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2386 }; 2387 2388 static void 2389 setup_memwin(struct adapter *sc) 2390 { 2391 const struct memwin_init *mw_init; 2392 struct memwin *mw; 2393 int i; 2394 uint32_t bar0; 2395 2396 if (is_t4(sc)) { 2397 /* 2398 * Read low 32b of bar0 indirectly via the hardware backdoor 2399 * mechanism. Works from within PCI passthrough environments 2400 * too, where rman_get_start() can return a different value. We 2401 * need to program the T4 memory window decoders with the actual 2402 * addresses that will be coming across the PCIe link. 2403 */ 2404 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2405 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2406 2407 mw_init = &t4_memwin[0]; 2408 } else { 2409 /* T5+ use the relative offset inside the PCIe BAR */ 2410 bar0 = 0; 2411 2412 mw_init = &t5_memwin[0]; 2413 } 2414 2415 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2416 rw_init(&mw->mw_lock, "memory window access"); 2417 mw->mw_base = mw_init->base; 2418 mw->mw_aperture = mw_init->aperture; 2419 mw->mw_curpos = 0; 2420 t4_write_reg(sc, 2421 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2422 (mw->mw_base + bar0) | V_BIR(0) | 2423 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2424 rw_wlock(&mw->mw_lock); 2425 position_memwin(sc, i, 0); 2426 rw_wunlock(&mw->mw_lock); 2427 } 2428 2429 /* flush */ 2430 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2431 } 2432 2433 /* 2434 * Positions the memory window at the given address in the card's address space. 2435 * There are some alignment requirements and the actual position may be at an 2436 * address prior to the requested address. mw->mw_curpos always has the actual 2437 * position of the window. 2438 */ 2439 static void 2440 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2441 { 2442 struct memwin *mw; 2443 uint32_t pf; 2444 uint32_t reg; 2445 2446 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2447 mw = &sc->memwin[idx]; 2448 rw_assert(&mw->mw_lock, RA_WLOCKED); 2449 2450 if (is_t4(sc)) { 2451 pf = 0; 2452 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2453 } else { 2454 pf = V_PFNUM(sc->pf); 2455 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2456 } 2457 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2458 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2459 t4_read_reg(sc, reg); /* flush */ 2460 } 2461 2462 int 2463 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2464 int len, int rw) 2465 { 2466 struct memwin *mw; 2467 uint32_t mw_end, v; 2468 2469 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2470 2471 /* Memory can only be accessed in naturally aligned 4 byte units */ 2472 if (addr & 3 || len & 3 || len <= 0) 2473 return (EINVAL); 2474 2475 mw = &sc->memwin[idx]; 2476 while (len > 0) { 2477 rw_rlock(&mw->mw_lock); 2478 mw_end = mw->mw_curpos + mw->mw_aperture; 2479 if (addr >= mw_end || addr < mw->mw_curpos) { 2480 /* Will need to reposition the window */ 2481 if (!rw_try_upgrade(&mw->mw_lock)) { 2482 rw_runlock(&mw->mw_lock); 2483 rw_wlock(&mw->mw_lock); 2484 } 2485 rw_assert(&mw->mw_lock, RA_WLOCKED); 2486 position_memwin(sc, idx, addr); 2487 rw_downgrade(&mw->mw_lock); 2488 mw_end = mw->mw_curpos + mw->mw_aperture; 2489 } 2490 rw_assert(&mw->mw_lock, RA_RLOCKED); 2491 while (addr < mw_end && len > 0) { 2492 if (rw == 0) { 2493 v = t4_read_reg(sc, mw->mw_base + addr - 2494 mw->mw_curpos); 2495 *val++ = le32toh(v); 2496 } else { 2497 v = *val++; 2498 t4_write_reg(sc, mw->mw_base + addr - 2499 mw->mw_curpos, htole32(v)); 2500 } 2501 addr += 4; 2502 len -= 4; 2503 } 2504 rw_runlock(&mw->mw_lock); 2505 } 2506 2507 return (0); 2508 } 2509 2510 int 2511 alloc_atid_tab(struct tid_info *t, int flags) 2512 { 2513 int i; 2514 2515 MPASS(t->natids > 0); 2516 MPASS(t->atid_tab == NULL); 2517 2518 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2519 M_ZERO | flags); 2520 if (t->atid_tab == NULL) 2521 return (ENOMEM); 2522 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2523 t->afree = t->atid_tab; 2524 t->atids_in_use = 0; 2525 for (i = 1; i < t->natids; i++) 2526 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2527 t->atid_tab[t->natids - 1].next = NULL; 2528 2529 return (0); 2530 } 2531 2532 void 2533 free_atid_tab(struct tid_info *t) 2534 { 2535 2536 KASSERT(t->atids_in_use == 0, 2537 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2538 2539 if (mtx_initialized(&t->atid_lock)) 2540 mtx_destroy(&t->atid_lock); 2541 free(t->atid_tab, M_CXGBE); 2542 t->atid_tab = NULL; 2543 } 2544 2545 int 2546 alloc_atid(struct adapter *sc, void *ctx) 2547 { 2548 struct tid_info *t = &sc->tids; 2549 int atid = -1; 2550 2551 mtx_lock(&t->atid_lock); 2552 if (t->afree) { 2553 union aopen_entry *p = t->afree; 2554 2555 atid = p - t->atid_tab; 2556 MPASS(atid <= M_TID_TID); 2557 t->afree = p->next; 2558 p->data = ctx; 2559 t->atids_in_use++; 2560 } 2561 mtx_unlock(&t->atid_lock); 2562 return (atid); 2563 } 2564 2565 void * 2566 lookup_atid(struct adapter *sc, int atid) 2567 { 2568 struct tid_info *t = &sc->tids; 2569 2570 return (t->atid_tab[atid].data); 2571 } 2572 2573 void 2574 free_atid(struct adapter *sc, int atid) 2575 { 2576 struct tid_info *t = &sc->tids; 2577 union aopen_entry *p = &t->atid_tab[atid]; 2578 2579 mtx_lock(&t->atid_lock); 2580 p->next = t->afree; 2581 t->afree = p; 2582 t->atids_in_use--; 2583 mtx_unlock(&t->atid_lock); 2584 } 2585 2586 static void 2587 queue_tid_release(struct adapter *sc, int tid) 2588 { 2589 2590 CXGBE_UNIMPLEMENTED("deferred tid release"); 2591 } 2592 2593 void 2594 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2595 { 2596 struct wrqe *wr; 2597 struct cpl_tid_release *req; 2598 2599 wr = alloc_wrqe(sizeof(*req), ctrlq); 2600 if (wr == NULL) { 2601 queue_tid_release(sc, tid); /* defer */ 2602 return; 2603 } 2604 req = wrtod(wr); 2605 2606 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2607 2608 t4_wrq_tx(sc, wr); 2609 } 2610 2611 static int 2612 t4_range_cmp(const void *a, const void *b) 2613 { 2614 return ((const struct t4_range *)a)->start - 2615 ((const struct t4_range *)b)->start; 2616 } 2617 2618 /* 2619 * Verify that the memory range specified by the addr/len pair is valid within 2620 * the card's address space. 2621 */ 2622 static int 2623 validate_mem_range(struct adapter *sc, uint32_t addr, int len) 2624 { 2625 struct t4_range mem_ranges[4], *r, *next; 2626 uint32_t em, addr_len; 2627 int i, n, remaining; 2628 2629 /* Memory can only be accessed in naturally aligned 4 byte units */ 2630 if (addr & 3 || len & 3 || len <= 0) 2631 return (EINVAL); 2632 2633 /* Enabled memories */ 2634 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2635 2636 r = &mem_ranges[0]; 2637 n = 0; 2638 bzero(r, sizeof(mem_ranges)); 2639 if (em & F_EDRAM0_ENABLE) { 2640 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2641 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2642 if (r->size > 0) { 2643 r->start = G_EDRAM0_BASE(addr_len) << 20; 2644 if (addr >= r->start && 2645 addr + len <= r->start + r->size) 2646 return (0); 2647 r++; 2648 n++; 2649 } 2650 } 2651 if (em & F_EDRAM1_ENABLE) { 2652 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2653 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2654 if (r->size > 0) { 2655 r->start = G_EDRAM1_BASE(addr_len) << 20; 2656 if (addr >= r->start && 2657 addr + len <= r->start + r->size) 2658 return (0); 2659 r++; 2660 n++; 2661 } 2662 } 2663 if (em & F_EXT_MEM_ENABLE) { 2664 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2665 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2666 if (r->size > 0) { 2667 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2668 if (addr >= r->start && 2669 addr + len <= r->start + r->size) 2670 return (0); 2671 r++; 2672 n++; 2673 } 2674 } 2675 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2676 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2677 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2678 if (r->size > 0) { 2679 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2680 if (addr >= r->start && 2681 addr + len <= r->start + r->size) 2682 return (0); 2683 r++; 2684 n++; 2685 } 2686 } 2687 MPASS(n <= nitems(mem_ranges)); 2688 2689 if (n > 1) { 2690 /* Sort and merge the ranges. */ 2691 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2692 2693 /* Start from index 0 and examine the next n - 1 entries. */ 2694 r = &mem_ranges[0]; 2695 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2696 2697 MPASS(r->size > 0); /* r is a valid entry. */ 2698 next = r + 1; 2699 MPASS(next->size > 0); /* and so is the next one. */ 2700 2701 while (r->start + r->size >= next->start) { 2702 /* Merge the next one into the current entry. */ 2703 r->size = max(r->start + r->size, 2704 next->start + next->size) - r->start; 2705 n--; /* One fewer entry in total. */ 2706 if (--remaining == 0) 2707 goto done; /* short circuit */ 2708 next++; 2709 } 2710 if (next != r + 1) { 2711 /* 2712 * Some entries were merged into r and next 2713 * points to the first valid entry that couldn't 2714 * be merged. 2715 */ 2716 MPASS(next->size > 0); /* must be valid */ 2717 memcpy(r + 1, next, remaining * sizeof(*r)); 2718 #ifdef INVARIANTS 2719 /* 2720 * This so that the foo->size assertion in the 2721 * next iteration of the loop do the right 2722 * thing for entries that were pulled up and are 2723 * no longer valid. 2724 */ 2725 MPASS(n < nitems(mem_ranges)); 2726 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2727 sizeof(struct t4_range)); 2728 #endif 2729 } 2730 } 2731 done: 2732 /* Done merging the ranges. */ 2733 MPASS(n > 0); 2734 r = &mem_ranges[0]; 2735 for (i = 0; i < n; i++, r++) { 2736 if (addr >= r->start && 2737 addr + len <= r->start + r->size) 2738 return (0); 2739 } 2740 } 2741 2742 return (EFAULT); 2743 } 2744 2745 static int 2746 fwmtype_to_hwmtype(int mtype) 2747 { 2748 2749 switch (mtype) { 2750 case FW_MEMTYPE_EDC0: 2751 return (MEM_EDC0); 2752 case FW_MEMTYPE_EDC1: 2753 return (MEM_EDC1); 2754 case FW_MEMTYPE_EXTMEM: 2755 return (MEM_MC0); 2756 case FW_MEMTYPE_EXTMEM1: 2757 return (MEM_MC1); 2758 default: 2759 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2760 } 2761 } 2762 2763 /* 2764 * Verify that the memory range specified by the memtype/offset/len pair is 2765 * valid and lies entirely within the memtype specified. The global address of 2766 * the start of the range is returned in addr. 2767 */ 2768 static int 2769 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 2770 uint32_t *addr) 2771 { 2772 uint32_t em, addr_len, maddr; 2773 2774 /* Memory can only be accessed in naturally aligned 4 byte units */ 2775 if (off & 3 || len & 3 || len == 0) 2776 return (EINVAL); 2777 2778 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2779 switch (fwmtype_to_hwmtype(mtype)) { 2780 case MEM_EDC0: 2781 if (!(em & F_EDRAM0_ENABLE)) 2782 return (EINVAL); 2783 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2784 maddr = G_EDRAM0_BASE(addr_len) << 20; 2785 break; 2786 case MEM_EDC1: 2787 if (!(em & F_EDRAM1_ENABLE)) 2788 return (EINVAL); 2789 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2790 maddr = G_EDRAM1_BASE(addr_len) << 20; 2791 break; 2792 case MEM_MC: 2793 if (!(em & F_EXT_MEM_ENABLE)) 2794 return (EINVAL); 2795 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2796 maddr = G_EXT_MEM_BASE(addr_len) << 20; 2797 break; 2798 case MEM_MC1: 2799 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 2800 return (EINVAL); 2801 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2802 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 2803 break; 2804 default: 2805 return (EINVAL); 2806 } 2807 2808 *addr = maddr + off; /* global address */ 2809 return (validate_mem_range(sc, *addr, len)); 2810 } 2811 2812 static int 2813 fixup_devlog_params(struct adapter *sc) 2814 { 2815 struct devlog_params *dparams = &sc->params.devlog; 2816 int rc; 2817 2818 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 2819 dparams->size, &dparams->addr); 2820 2821 return (rc); 2822 } 2823 2824 static void 2825 update_nirq(struct intrs_and_queues *iaq, int nports) 2826 { 2827 int extra = T4_EXTRA_INTR; 2828 2829 iaq->nirq = extra; 2830 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 2831 iaq->nirq += nports * (iaq->num_vis - 1) * 2832 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 2833 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 2834 } 2835 2836 /* 2837 * Adjust requirements to fit the number of interrupts available. 2838 */ 2839 static void 2840 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 2841 int navail) 2842 { 2843 int old_nirq; 2844 const int nports = sc->params.nports; 2845 2846 MPASS(nports > 0); 2847 MPASS(navail > 0); 2848 2849 bzero(iaq, sizeof(*iaq)); 2850 iaq->intr_type = itype; 2851 iaq->num_vis = t4_num_vis; 2852 iaq->ntxq = t4_ntxq; 2853 iaq->ntxq_vi = t4_ntxq_vi; 2854 iaq->nrxq = t4_nrxq; 2855 iaq->nrxq_vi = t4_nrxq_vi; 2856 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2857 if (is_offload(sc) || is_ethoffload(sc)) { 2858 iaq->nofldtxq = t4_nofldtxq; 2859 iaq->nofldtxq_vi = t4_nofldtxq_vi; 2860 } 2861 #endif 2862 #ifdef TCP_OFFLOAD 2863 if (is_offload(sc)) { 2864 iaq->nofldrxq = t4_nofldrxq; 2865 iaq->nofldrxq_vi = t4_nofldrxq_vi; 2866 } 2867 #endif 2868 #ifdef DEV_NETMAP 2869 iaq->nnmtxq_vi = t4_nnmtxq_vi; 2870 iaq->nnmrxq_vi = t4_nnmrxq_vi; 2871 #endif 2872 2873 update_nirq(iaq, nports); 2874 if (iaq->nirq <= navail && 2875 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2876 /* 2877 * This is the normal case -- there are enough interrupts for 2878 * everything. 2879 */ 2880 goto done; 2881 } 2882 2883 /* 2884 * If extra VIs have been configured try reducing their count and see if 2885 * that works. 2886 */ 2887 while (iaq->num_vis > 1) { 2888 iaq->num_vis--; 2889 update_nirq(iaq, nports); 2890 if (iaq->nirq <= navail && 2891 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2892 device_printf(sc->dev, "virtual interfaces per port " 2893 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 2894 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 2895 "itype %d, navail %u, nirq %d.\n", 2896 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 2897 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 2898 itype, navail, iaq->nirq); 2899 goto done; 2900 } 2901 } 2902 2903 /* 2904 * Extra VIs will not be created. Log a message if they were requested. 2905 */ 2906 MPASS(iaq->num_vis == 1); 2907 iaq->ntxq_vi = iaq->nrxq_vi = 0; 2908 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 2909 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 2910 if (iaq->num_vis != t4_num_vis) { 2911 device_printf(sc->dev, "extra virtual interfaces disabled. " 2912 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 2913 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 2914 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 2915 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 2916 } 2917 2918 /* 2919 * Keep reducing the number of NIC rx queues to the next lower power of 2920 * 2 (for even RSS distribution) and halving the TOE rx queues and see 2921 * if that works. 2922 */ 2923 do { 2924 if (iaq->nrxq > 1) { 2925 do { 2926 iaq->nrxq--; 2927 } while (!powerof2(iaq->nrxq)); 2928 } 2929 if (iaq->nofldrxq > 1) 2930 iaq->nofldrxq >>= 1; 2931 2932 old_nirq = iaq->nirq; 2933 update_nirq(iaq, nports); 2934 if (iaq->nirq <= navail && 2935 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2936 device_printf(sc->dev, "running with reduced number of " 2937 "rx queues because of shortage of interrupts. " 2938 "nrxq=%u, nofldrxq=%u. " 2939 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 2940 iaq->nofldrxq, itype, navail, iaq->nirq); 2941 goto done; 2942 } 2943 } while (old_nirq != iaq->nirq); 2944 2945 /* One interrupt for everything. Ugh. */ 2946 device_printf(sc->dev, "running with minimal number of queues. " 2947 "itype %d, navail %u.\n", itype, navail); 2948 iaq->nirq = 1; 2949 MPASS(iaq->nrxq == 1); 2950 iaq->ntxq = 1; 2951 if (iaq->nofldrxq > 1) 2952 iaq->nofldtxq = 1; 2953 done: 2954 MPASS(iaq->num_vis > 0); 2955 if (iaq->num_vis > 1) { 2956 MPASS(iaq->nrxq_vi > 0); 2957 MPASS(iaq->ntxq_vi > 0); 2958 } 2959 MPASS(iaq->nirq > 0); 2960 MPASS(iaq->nrxq > 0); 2961 MPASS(iaq->ntxq > 0); 2962 if (itype == INTR_MSI) { 2963 MPASS(powerof2(iaq->nirq)); 2964 } 2965 } 2966 2967 static int 2968 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 2969 { 2970 int rc, itype, navail, nalloc; 2971 2972 for (itype = INTR_MSIX; itype; itype >>= 1) { 2973 2974 if ((itype & t4_intr_types) == 0) 2975 continue; /* not allowed */ 2976 2977 if (itype == INTR_MSIX) 2978 navail = pci_msix_count(sc->dev); 2979 else if (itype == INTR_MSI) 2980 navail = pci_msi_count(sc->dev); 2981 else 2982 navail = 1; 2983 restart: 2984 if (navail == 0) 2985 continue; 2986 2987 calculate_iaq(sc, iaq, itype, navail); 2988 nalloc = iaq->nirq; 2989 rc = 0; 2990 if (itype == INTR_MSIX) 2991 rc = pci_alloc_msix(sc->dev, &nalloc); 2992 else if (itype == INTR_MSI) 2993 rc = pci_alloc_msi(sc->dev, &nalloc); 2994 2995 if (rc == 0 && nalloc > 0) { 2996 if (nalloc == iaq->nirq) 2997 return (0); 2998 2999 /* 3000 * Didn't get the number requested. Use whatever number 3001 * the kernel is willing to allocate. 3002 */ 3003 device_printf(sc->dev, "fewer vectors than requested, " 3004 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3005 itype, iaq->nirq, nalloc); 3006 pci_release_msi(sc->dev); 3007 navail = nalloc; 3008 goto restart; 3009 } 3010 3011 device_printf(sc->dev, 3012 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3013 itype, rc, iaq->nirq, nalloc); 3014 } 3015 3016 device_printf(sc->dev, 3017 "failed to find a usable interrupt type. " 3018 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3019 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3020 3021 return (ENXIO); 3022 } 3023 3024 #define FW_VERSION(chip) ( \ 3025 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3026 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3027 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3028 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3029 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3030 3031 struct fw_info { 3032 uint8_t chip; 3033 char *kld_name; 3034 char *fw_mod_name; 3035 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 3036 } fw_info[] = { 3037 { 3038 .chip = CHELSIO_T4, 3039 .kld_name = "t4fw_cfg", 3040 .fw_mod_name = "t4fw", 3041 .fw_hdr = { 3042 .chip = FW_HDR_CHIP_T4, 3043 .fw_ver = htobe32_const(FW_VERSION(T4)), 3044 .intfver_nic = FW_INTFVER(T4, NIC), 3045 .intfver_vnic = FW_INTFVER(T4, VNIC), 3046 .intfver_ofld = FW_INTFVER(T4, OFLD), 3047 .intfver_ri = FW_INTFVER(T4, RI), 3048 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3049 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3050 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3051 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3052 }, 3053 }, { 3054 .chip = CHELSIO_T5, 3055 .kld_name = "t5fw_cfg", 3056 .fw_mod_name = "t5fw", 3057 .fw_hdr = { 3058 .chip = FW_HDR_CHIP_T5, 3059 .fw_ver = htobe32_const(FW_VERSION(T5)), 3060 .intfver_nic = FW_INTFVER(T5, NIC), 3061 .intfver_vnic = FW_INTFVER(T5, VNIC), 3062 .intfver_ofld = FW_INTFVER(T5, OFLD), 3063 .intfver_ri = FW_INTFVER(T5, RI), 3064 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3065 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3066 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3067 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3068 }, 3069 }, { 3070 .chip = CHELSIO_T6, 3071 .kld_name = "t6fw_cfg", 3072 .fw_mod_name = "t6fw", 3073 .fw_hdr = { 3074 .chip = FW_HDR_CHIP_T6, 3075 .fw_ver = htobe32_const(FW_VERSION(T6)), 3076 .intfver_nic = FW_INTFVER(T6, NIC), 3077 .intfver_vnic = FW_INTFVER(T6, VNIC), 3078 .intfver_ofld = FW_INTFVER(T6, OFLD), 3079 .intfver_ri = FW_INTFVER(T6, RI), 3080 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3081 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3082 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3083 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3084 }, 3085 } 3086 }; 3087 3088 static struct fw_info * 3089 find_fw_info(int chip) 3090 { 3091 int i; 3092 3093 for (i = 0; i < nitems(fw_info); i++) { 3094 if (fw_info[i].chip == chip) 3095 return (&fw_info[i]); 3096 } 3097 return (NULL); 3098 } 3099 3100 /* 3101 * Is the given firmware API compatible with the one the driver was compiled 3102 * with? 3103 */ 3104 static int 3105 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 3106 { 3107 3108 /* short circuit if it's the exact same firmware version */ 3109 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3110 return (1); 3111 3112 /* 3113 * XXX: Is this too conservative? Perhaps I should limit this to the 3114 * features that are supported in the driver. 3115 */ 3116 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3117 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3118 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3119 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3120 return (1); 3121 #undef SAME_INTF 3122 3123 return (0); 3124 } 3125 3126 /* 3127 * The firmware in the KLD is usable, but should it be installed? This routine 3128 * explains itself in detail if it indicates the KLD firmware should be 3129 * installed. 3130 */ 3131 static int 3132 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 3133 { 3134 const char *reason; 3135 3136 if (!card_fw_usable) { 3137 reason = "incompatible or unusable"; 3138 goto install; 3139 } 3140 3141 if (k > c) { 3142 reason = "older than the version bundled with this driver"; 3143 goto install; 3144 } 3145 3146 if (t4_fw_install == 2 && k != c) { 3147 reason = "different than the version bundled with this driver"; 3148 goto install; 3149 } 3150 3151 return (0); 3152 3153 install: 3154 if (t4_fw_install == 0) { 3155 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3156 "but the driver is prohibited from installing a different " 3157 "firmware on the card.\n", 3158 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3159 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3160 3161 return (0); 3162 } 3163 3164 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3165 "installing firmware %u.%u.%u.%u on card.\n", 3166 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3167 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3168 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3169 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3170 3171 return (1); 3172 } 3173 3174 /* 3175 * Establish contact with the firmware and determine if we are the master driver 3176 * or not, and whether we are responsible for chip initialization. 3177 */ 3178 static int 3179 prep_firmware(struct adapter *sc) 3180 { 3181 const struct firmware *fw = NULL, *default_cfg; 3182 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 3183 enum dev_state state; 3184 struct fw_info *fw_info; 3185 struct fw_hdr *card_fw; /* fw on the card */ 3186 const struct fw_hdr *kld_fw; /* fw in the KLD */ 3187 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 3188 against */ 3189 3190 /* This is the firmware whose headers the driver was compiled against */ 3191 fw_info = find_fw_info(chip_id(sc)); 3192 if (fw_info == NULL) { 3193 device_printf(sc->dev, 3194 "unable to look up firmware information for chip %d.\n", 3195 chip_id(sc)); 3196 return (EINVAL); 3197 } 3198 drv_fw = &fw_info->fw_hdr; 3199 3200 /* 3201 * The firmware KLD contains many modules. The KLD name is also the 3202 * name of the module that contains the default config file. 3203 */ 3204 default_cfg = firmware_get(fw_info->kld_name); 3205 3206 /* This is the firmware in the KLD */ 3207 fw = firmware_get(fw_info->fw_mod_name); 3208 if (fw != NULL) { 3209 kld_fw = (const void *)fw->data; 3210 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 3211 } else { 3212 kld_fw = NULL; 3213 kld_fw_usable = 0; 3214 } 3215 3216 /* Read the header of the firmware on the card */ 3217 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3218 rc = -t4_read_flash(sc, FLASH_FW_START, 3219 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 3220 if (rc == 0) { 3221 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 3222 if (card_fw->fw_ver == be32toh(0xffffffff)) { 3223 uint32_t d = be32toh(kld_fw->fw_ver); 3224 3225 if (!kld_fw_usable) { 3226 device_printf(sc->dev, 3227 "no firmware on the card and no usable " 3228 "firmware bundled with the driver.\n"); 3229 rc = EIO; 3230 goto done; 3231 } else if (t4_fw_install == 0) { 3232 device_printf(sc->dev, 3233 "no firmware on the card and the driver " 3234 "is prohibited from installing new " 3235 "firmware.\n"); 3236 rc = EIO; 3237 goto done; 3238 } 3239 3240 device_printf(sc->dev, "no firmware on the card, " 3241 "installing firmware %d.%d.%d.%d\n", 3242 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3243 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3244 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize); 3245 if (rc < 0) { 3246 rc = -rc; 3247 device_printf(sc->dev, 3248 "firmware install failed: %d.\n", rc); 3249 goto done; 3250 } 3251 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3252 card_fw_usable = 1; 3253 need_fw_reset = 0; 3254 } 3255 } else { 3256 device_printf(sc->dev, 3257 "Unable to read card's firmware header: %d\n", rc); 3258 card_fw_usable = 0; 3259 } 3260 3261 /* Contact firmware. */ 3262 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3263 if (rc < 0 || state == DEV_STATE_ERR) { 3264 rc = -rc; 3265 device_printf(sc->dev, 3266 "failed to connect to the firmware: %d, %d.\n", rc, state); 3267 goto done; 3268 } 3269 pf = rc; 3270 if (pf == sc->mbox) 3271 sc->flags |= MASTER_PF; 3272 else if (state == DEV_STATE_UNINIT) { 3273 /* 3274 * We didn't get to be the master so we definitely won't be 3275 * configuring the chip. It's a bug if someone else hasn't 3276 * configured it already. 3277 */ 3278 device_printf(sc->dev, "couldn't be master(%d), " 3279 "device not already initialized either(%d).\n", rc, state); 3280 rc = EPROTO; 3281 goto done; 3282 } 3283 3284 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 3285 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 3286 /* 3287 * Common case: the firmware on the card is an exact match and 3288 * the KLD is an exact match too, or the KLD is 3289 * absent/incompatible. Note that t4_fw_install = 2 is ignored 3290 * here -- use cxgbetool loadfw if you want to reinstall the 3291 * same firmware as the one on the card. 3292 */ 3293 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 3294 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 3295 be32toh(card_fw->fw_ver))) { 3296 3297 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3298 if (rc != 0) { 3299 device_printf(sc->dev, 3300 "failed to install firmware: %d\n", rc); 3301 goto done; 3302 } 3303 3304 /* Installed successfully, update the cached header too. */ 3305 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3306 card_fw_usable = 1; 3307 need_fw_reset = 0; /* already reset as part of load_fw */ 3308 } 3309 3310 if (!card_fw_usable) { 3311 uint32_t d, c, k; 3312 3313 d = ntohl(drv_fw->fw_ver); 3314 c = ntohl(card_fw->fw_ver); 3315 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3316 3317 device_printf(sc->dev, "Cannot find a usable firmware: " 3318 "fw_install %d, chip state %d, " 3319 "driver compiled with %d.%d.%d.%d, " 3320 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3321 t4_fw_install, state, 3322 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3323 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3324 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3325 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3326 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3327 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3328 rc = EINVAL; 3329 goto done; 3330 } 3331 3332 /* Reset device */ 3333 if (need_fw_reset && 3334 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3335 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3336 if (rc != ETIMEDOUT && rc != EIO) 3337 t4_fw_bye(sc, sc->mbox); 3338 goto done; 3339 } 3340 sc->flags |= FW_OK; 3341 3342 rc = get_params__pre_init(sc); 3343 if (rc != 0) 3344 goto done; /* error message displayed already */ 3345 3346 /* Partition adapter resources as specified in the config file. */ 3347 if (state == DEV_STATE_UNINIT) { 3348 3349 KASSERT(sc->flags & MASTER_PF, 3350 ("%s: trying to change chip settings when not master.", 3351 __func__)); 3352 3353 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3354 if (rc != 0) 3355 goto done; /* error message displayed already */ 3356 3357 t4_tweak_chip_settings(sc); 3358 3359 /* get basic stuff going */ 3360 rc = -t4_fw_initialize(sc, sc->mbox); 3361 if (rc != 0) { 3362 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3363 goto done; 3364 } 3365 } else { 3366 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3367 sc->cfcsum = 0; 3368 } 3369 3370 done: 3371 free(card_fw, M_CXGBE); 3372 if (fw != NULL) 3373 firmware_put(fw, FIRMWARE_UNLOAD); 3374 if (default_cfg != NULL) 3375 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3376 3377 return (rc); 3378 } 3379 3380 #define FW_PARAM_DEV(param) \ 3381 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3382 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3383 #define FW_PARAM_PFVF(param) \ 3384 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3385 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3386 3387 /* 3388 * Partition chip resources for use between various PFs, VFs, etc. 3389 */ 3390 static int 3391 partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3392 const char *name_prefix) 3393 { 3394 const struct firmware *cfg = NULL; 3395 int rc = 0; 3396 struct fw_caps_config_cmd caps; 3397 uint32_t mtype, moff, finicsum, cfcsum; 3398 3399 /* 3400 * Figure out what configuration file to use. Pick the default config 3401 * file for the card if the user hasn't specified one explicitly. 3402 */ 3403 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3404 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3405 /* Card specific overrides go here. */ 3406 if (pci_get_device(sc->dev) == 0x440a) 3407 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3408 if (is_fpga(sc)) 3409 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3410 } else if (strncmp(t4_cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) 3411 goto use_built_in_config; /* go straight to config. */ 3412 3413 /* 3414 * We need to load another module if the profile is anything except 3415 * "default" or "flash". 3416 */ 3417 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3418 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3419 char s[32]; 3420 3421 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3422 cfg = firmware_get(s); 3423 if (cfg == NULL) { 3424 if (default_cfg != NULL) { 3425 device_printf(sc->dev, 3426 "unable to load module \"%s\" for " 3427 "configuration profile \"%s\", will use " 3428 "the default config file instead.\n", 3429 s, sc->cfg_file); 3430 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3431 "%s", DEFAULT_CF); 3432 } else { 3433 device_printf(sc->dev, 3434 "unable to load module \"%s\" for " 3435 "configuration profile \"%s\", will use " 3436 "the config file on the card's flash " 3437 "instead.\n", s, sc->cfg_file); 3438 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3439 "%s", FLASH_CF); 3440 } 3441 } 3442 } 3443 3444 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3445 default_cfg == NULL) { 3446 device_printf(sc->dev, 3447 "default config file not available, will use the config " 3448 "file on the card's flash instead.\n"); 3449 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3450 } 3451 3452 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3453 u_int cflen; 3454 const uint32_t *cfdata; 3455 uint32_t param, val, addr; 3456 3457 KASSERT(cfg != NULL || default_cfg != NULL, 3458 ("%s: no config to upload", __func__)); 3459 3460 /* 3461 * Ask the firmware where it wants us to upload the config file. 3462 */ 3463 param = FW_PARAM_DEV(CF); 3464 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3465 if (rc != 0) { 3466 /* No support for config file? Shouldn't happen. */ 3467 device_printf(sc->dev, 3468 "failed to query config file location: %d.\n", rc); 3469 goto done; 3470 } 3471 mtype = G_FW_PARAMS_PARAM_Y(val); 3472 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3473 3474 /* 3475 * XXX: sheer laziness. We deliberately added 4 bytes of 3476 * useless stuffing/comments at the end of the config file so 3477 * it's ok to simply throw away the last remaining bytes when 3478 * the config file is not an exact multiple of 4. This also 3479 * helps with the validate_mt_off_len check. 3480 */ 3481 if (cfg != NULL) { 3482 cflen = cfg->datasize & ~3; 3483 cfdata = cfg->data; 3484 } else { 3485 cflen = default_cfg->datasize & ~3; 3486 cfdata = default_cfg->data; 3487 } 3488 3489 if (cflen > FLASH_CFG_MAX_SIZE) { 3490 device_printf(sc->dev, 3491 "config file too long (%d, max allowed is %d). " 3492 "Will try to use the config on the card, if any.\n", 3493 cflen, FLASH_CFG_MAX_SIZE); 3494 goto use_config_on_flash; 3495 } 3496 3497 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3498 if (rc != 0) { 3499 device_printf(sc->dev, 3500 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3501 "Will try to use the config on the card, if any.\n", 3502 __func__, mtype, moff, cflen, rc); 3503 goto use_config_on_flash; 3504 } 3505 write_via_memwin(sc, 2, addr, cfdata, cflen); 3506 } else { 3507 use_config_on_flash: 3508 mtype = FW_MEMTYPE_FLASH; 3509 moff = t4_flash_cfg_addr(sc); 3510 } 3511 3512 bzero(&caps, sizeof(caps)); 3513 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3514 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3515 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3516 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3517 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3518 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3519 if (rc != 0) { 3520 device_printf(sc->dev, 3521 "failed to pre-process config file: %d " 3522 "(mtype %d, moff 0x%x). Will reset the firmware and retry " 3523 "with the built-in configuration.\n", rc, mtype, moff); 3524 3525 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3526 if (rc != 0) { 3527 device_printf(sc->dev, 3528 "firmware reset failed: %d.\n", rc); 3529 if (rc != ETIMEDOUT && rc != EIO) { 3530 t4_fw_bye(sc, sc->mbox); 3531 sc->flags &= ~FW_OK; 3532 } 3533 goto done; 3534 } 3535 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "built-in"); 3536 use_built_in_config: 3537 bzero(&caps, sizeof(caps)); 3538 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3539 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3540 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3541 rc = t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3542 if (rc != 0) { 3543 device_printf(sc->dev, 3544 "built-in configuration failed: %d.\n", rc); 3545 goto done; 3546 } 3547 } 3548 3549 finicsum = be32toh(caps.finicsum); 3550 cfcsum = be32toh(caps.cfcsum); 3551 if (finicsum != cfcsum) { 3552 device_printf(sc->dev, 3553 "WARNING: config file checksum mismatch: %08x %08x\n", 3554 finicsum, cfcsum); 3555 } 3556 sc->cfcsum = cfcsum; 3557 3558 #define LIMIT_CAPS(x) do { \ 3559 caps.x &= htobe16(t4_##x##_allowed); \ 3560 } while (0) 3561 3562 /* 3563 * Let the firmware know what features will (not) be used so it can tune 3564 * things accordingly. 3565 */ 3566 LIMIT_CAPS(nbmcaps); 3567 LIMIT_CAPS(linkcaps); 3568 LIMIT_CAPS(switchcaps); 3569 LIMIT_CAPS(niccaps); 3570 LIMIT_CAPS(toecaps); 3571 LIMIT_CAPS(rdmacaps); 3572 LIMIT_CAPS(cryptocaps); 3573 LIMIT_CAPS(iscsicaps); 3574 LIMIT_CAPS(fcoecaps); 3575 #undef LIMIT_CAPS 3576 3577 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3578 /* 3579 * TOE and hashfilters are mutually exclusive. It is a config 3580 * file or firmware bug if both are reported as available. Try 3581 * to cope with the situation in non-debug builds by disabling 3582 * TOE. 3583 */ 3584 MPASS(caps.toecaps == 0); 3585 3586 caps.toecaps = 0; 3587 caps.rdmacaps = 0; 3588 caps.iscsicaps = 0; 3589 } 3590 3591 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3592 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3593 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3594 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3595 if (rc != 0) { 3596 device_printf(sc->dev, 3597 "failed to process config file: %d.\n", rc); 3598 } 3599 done: 3600 if (cfg != NULL) 3601 firmware_put(cfg, FIRMWARE_UNLOAD); 3602 return (rc); 3603 } 3604 3605 /* 3606 * Retrieve parameters that are needed (or nice to have) very early. 3607 */ 3608 static int 3609 get_params__pre_init(struct adapter *sc) 3610 { 3611 int rc; 3612 uint32_t param[2], val[2]; 3613 3614 t4_get_version_info(sc); 3615 3616 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3617 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3618 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3619 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3620 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3621 3622 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3623 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3624 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3625 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3626 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3627 3628 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3629 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3630 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3631 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3632 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3633 3634 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3635 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3636 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3637 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3638 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3639 3640 param[0] = FW_PARAM_DEV(PORTVEC); 3641 param[1] = FW_PARAM_DEV(CCLK); 3642 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3643 if (rc != 0) { 3644 device_printf(sc->dev, 3645 "failed to query parameters (pre_init): %d.\n", rc); 3646 return (rc); 3647 } 3648 3649 sc->params.portvec = val[0]; 3650 sc->params.nports = bitcount32(val[0]); 3651 sc->params.vpd.cclk = val[1]; 3652 3653 /* Read device log parameters. */ 3654 rc = -t4_init_devlog_params(sc, 1); 3655 if (rc == 0) 3656 fixup_devlog_params(sc); 3657 else { 3658 device_printf(sc->dev, 3659 "failed to get devlog parameters: %d.\n", rc); 3660 rc = 0; /* devlog isn't critical for device operation */ 3661 } 3662 3663 return (rc); 3664 } 3665 3666 /* 3667 * Retrieve various parameters that are of interest to the driver. The device 3668 * has been initialized by the firmware at this point. 3669 */ 3670 static int 3671 get_params__post_init(struct adapter *sc) 3672 { 3673 int rc; 3674 uint32_t param[7], val[7]; 3675 struct fw_caps_config_cmd caps; 3676 3677 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3678 param[1] = FW_PARAM_PFVF(EQ_START); 3679 param[2] = FW_PARAM_PFVF(FILTER_START); 3680 param[3] = FW_PARAM_PFVF(FILTER_END); 3681 param[4] = FW_PARAM_PFVF(L2T_START); 3682 param[5] = FW_PARAM_PFVF(L2T_END); 3683 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3684 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 3685 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 3686 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 3687 if (rc != 0) { 3688 device_printf(sc->dev, 3689 "failed to query parameters (post_init): %d.\n", rc); 3690 return (rc); 3691 } 3692 3693 sc->sge.iq_start = val[0]; 3694 sc->sge.eq_start = val[1]; 3695 sc->tids.ftid_base = val[2]; 3696 sc->tids.nftids = val[3] - val[2] + 1; 3697 sc->params.ftid_min = val[2]; 3698 sc->params.ftid_max = val[3]; 3699 sc->vres.l2t.start = val[4]; 3700 sc->vres.l2t.size = val[5] - val[4] + 1; 3701 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3702 ("%s: L2 table size (%u) larger than expected (%u)", 3703 __func__, sc->vres.l2t.size, L2T_SIZE)); 3704 sc->params.core_vdd = val[6]; 3705 3706 /* 3707 * MPSBGMAP is queried separately because only recent firmwares support 3708 * it as a parameter and we don't want the compound query above to fail 3709 * on older firmwares. 3710 */ 3711 param[0] = FW_PARAM_DEV(MPSBGMAP); 3712 val[0] = 0; 3713 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3714 if (rc == 0) 3715 sc->params.mps_bg_map = val[0]; 3716 else 3717 sc->params.mps_bg_map = 0; 3718 3719 /* 3720 * Determine whether the firmware supports the filter2 work request. 3721 * This is queried separately for the same reason as MPSBGMAP above. 3722 */ 3723 param[0] = FW_PARAM_DEV(FILTER2_WR); 3724 val[0] = 0; 3725 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3726 if (rc == 0) 3727 sc->params.filter2_wr_support = val[0] != 0; 3728 else 3729 sc->params.filter2_wr_support = 0; 3730 3731 /* get capabilites */ 3732 bzero(&caps, sizeof(caps)); 3733 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3734 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3735 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3736 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3737 if (rc != 0) { 3738 device_printf(sc->dev, 3739 "failed to get card capabilities: %d.\n", rc); 3740 return (rc); 3741 } 3742 3743 #define READ_CAPS(x) do { \ 3744 sc->x = htobe16(caps.x); \ 3745 } while (0) 3746 READ_CAPS(nbmcaps); 3747 READ_CAPS(linkcaps); 3748 READ_CAPS(switchcaps); 3749 READ_CAPS(niccaps); 3750 READ_CAPS(toecaps); 3751 READ_CAPS(rdmacaps); 3752 READ_CAPS(cryptocaps); 3753 READ_CAPS(iscsicaps); 3754 READ_CAPS(fcoecaps); 3755 3756 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 3757 MPASS(chip_id(sc) > CHELSIO_T4); 3758 MPASS(sc->toecaps == 0); 3759 sc->toecaps = 0; 3760 3761 param[0] = FW_PARAM_DEV(NTID); 3762 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3763 if (rc != 0) { 3764 device_printf(sc->dev, 3765 "failed to query HASHFILTER parameters: %d.\n", rc); 3766 return (rc); 3767 } 3768 sc->tids.ntids = val[0]; 3769 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3770 sc->params.hash_filter = 1; 3771 } 3772 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 3773 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 3774 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 3775 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3776 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 3777 if (rc != 0) { 3778 device_printf(sc->dev, 3779 "failed to query NIC parameters: %d.\n", rc); 3780 return (rc); 3781 } 3782 sc->tids.etid_base = val[0]; 3783 sc->params.etid_min = val[0]; 3784 sc->params.etid_max = val[1]; 3785 sc->tids.netids = val[1] - val[0] + 1; 3786 sc->params.eo_wr_cred = val[2]; 3787 sc->params.ethoffload = 1; 3788 } 3789 if (sc->toecaps) { 3790 /* query offload-related parameters */ 3791 param[0] = FW_PARAM_DEV(NTID); 3792 param[1] = FW_PARAM_PFVF(SERVER_START); 3793 param[2] = FW_PARAM_PFVF(SERVER_END); 3794 param[3] = FW_PARAM_PFVF(TDDP_START); 3795 param[4] = FW_PARAM_PFVF(TDDP_END); 3796 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3797 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3798 if (rc != 0) { 3799 device_printf(sc->dev, 3800 "failed to query TOE parameters: %d.\n", rc); 3801 return (rc); 3802 } 3803 sc->tids.ntids = val[0]; 3804 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3805 sc->tids.stid_base = val[1]; 3806 sc->tids.nstids = val[2] - val[1] + 1; 3807 sc->vres.ddp.start = val[3]; 3808 sc->vres.ddp.size = val[4] - val[3] + 1; 3809 sc->params.ofldq_wr_cred = val[5]; 3810 sc->params.offload = 1; 3811 } else { 3812 /* 3813 * The firmware attempts memfree TOE configuration for -SO cards 3814 * and will report toecaps=0 if it runs out of resources (this 3815 * depends on the config file). It may not report 0 for other 3816 * capabilities dependent on the TOE in this case. Set them to 3817 * 0 here so that the driver doesn't bother tracking resources 3818 * that will never be used. 3819 */ 3820 sc->iscsicaps = 0; 3821 sc->rdmacaps = 0; 3822 } 3823 if (sc->rdmacaps) { 3824 param[0] = FW_PARAM_PFVF(STAG_START); 3825 param[1] = FW_PARAM_PFVF(STAG_END); 3826 param[2] = FW_PARAM_PFVF(RQ_START); 3827 param[3] = FW_PARAM_PFVF(RQ_END); 3828 param[4] = FW_PARAM_PFVF(PBL_START); 3829 param[5] = FW_PARAM_PFVF(PBL_END); 3830 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3831 if (rc != 0) { 3832 device_printf(sc->dev, 3833 "failed to query RDMA parameters(1): %d.\n", rc); 3834 return (rc); 3835 } 3836 sc->vres.stag.start = val[0]; 3837 sc->vres.stag.size = val[1] - val[0] + 1; 3838 sc->vres.rq.start = val[2]; 3839 sc->vres.rq.size = val[3] - val[2] + 1; 3840 sc->vres.pbl.start = val[4]; 3841 sc->vres.pbl.size = val[5] - val[4] + 1; 3842 3843 param[0] = FW_PARAM_PFVF(SQRQ_START); 3844 param[1] = FW_PARAM_PFVF(SQRQ_END); 3845 param[2] = FW_PARAM_PFVF(CQ_START); 3846 param[3] = FW_PARAM_PFVF(CQ_END); 3847 param[4] = FW_PARAM_PFVF(OCQ_START); 3848 param[5] = FW_PARAM_PFVF(OCQ_END); 3849 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3850 if (rc != 0) { 3851 device_printf(sc->dev, 3852 "failed to query RDMA parameters(2): %d.\n", rc); 3853 return (rc); 3854 } 3855 sc->vres.qp.start = val[0]; 3856 sc->vres.qp.size = val[1] - val[0] + 1; 3857 sc->vres.cq.start = val[2]; 3858 sc->vres.cq.size = val[3] - val[2] + 1; 3859 sc->vres.ocq.start = val[4]; 3860 sc->vres.ocq.size = val[5] - val[4] + 1; 3861 3862 param[0] = FW_PARAM_PFVF(SRQ_START); 3863 param[1] = FW_PARAM_PFVF(SRQ_END); 3864 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 3865 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 3866 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 3867 if (rc != 0) { 3868 device_printf(sc->dev, 3869 "failed to query RDMA parameters(3): %d.\n", rc); 3870 return (rc); 3871 } 3872 sc->vres.srq.start = val[0]; 3873 sc->vres.srq.size = val[1] - val[0] + 1; 3874 sc->params.max_ordird_qp = val[2]; 3875 sc->params.max_ird_adapter = val[3]; 3876 } 3877 if (sc->iscsicaps) { 3878 param[0] = FW_PARAM_PFVF(ISCSI_START); 3879 param[1] = FW_PARAM_PFVF(ISCSI_END); 3880 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3881 if (rc != 0) { 3882 device_printf(sc->dev, 3883 "failed to query iSCSI parameters: %d.\n", rc); 3884 return (rc); 3885 } 3886 sc->vres.iscsi.start = val[0]; 3887 sc->vres.iscsi.size = val[1] - val[0] + 1; 3888 } 3889 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 3890 param[0] = FW_PARAM_PFVF(TLS_START); 3891 param[1] = FW_PARAM_PFVF(TLS_END); 3892 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3893 if (rc != 0) { 3894 device_printf(sc->dev, 3895 "failed to query TLS parameters: %d.\n", rc); 3896 return (rc); 3897 } 3898 sc->vres.key.start = val[0]; 3899 sc->vres.key.size = val[1] - val[0] + 1; 3900 } 3901 3902 t4_init_sge_params(sc); 3903 3904 /* 3905 * We've got the params we wanted to query via the firmware. Now grab 3906 * some others directly from the chip. 3907 */ 3908 rc = t4_read_chip_settings(sc); 3909 3910 return (rc); 3911 } 3912 3913 static int 3914 set_params__post_init(struct adapter *sc) 3915 { 3916 uint32_t param, val; 3917 #ifdef TCP_OFFLOAD 3918 int i, v, shift; 3919 #endif 3920 3921 /* ask for encapsulated CPLs */ 3922 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3923 val = 1; 3924 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3925 3926 #ifdef TCP_OFFLOAD 3927 /* 3928 * Override the TOE timers with user provided tunables. This is not the 3929 * recommended way to change the timers (the firmware config file is) so 3930 * these tunables are not documented. 3931 * 3932 * All the timer tunables are in microseconds. 3933 */ 3934 if (t4_toe_keepalive_idle != 0) { 3935 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 3936 v &= M_KEEPALIVEIDLE; 3937 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 3938 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 3939 } 3940 if (t4_toe_keepalive_interval != 0) { 3941 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 3942 v &= M_KEEPALIVEINTVL; 3943 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 3944 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 3945 } 3946 if (t4_toe_keepalive_count != 0) { 3947 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 3948 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 3949 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 3950 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 3951 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 3952 } 3953 if (t4_toe_rexmt_min != 0) { 3954 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 3955 v &= M_RXTMIN; 3956 t4_set_reg_field(sc, A_TP_RXT_MIN, 3957 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 3958 } 3959 if (t4_toe_rexmt_max != 0) { 3960 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 3961 v &= M_RXTMAX; 3962 t4_set_reg_field(sc, A_TP_RXT_MAX, 3963 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 3964 } 3965 if (t4_toe_rexmt_count != 0) { 3966 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 3967 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 3968 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 3969 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 3970 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 3971 } 3972 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 3973 if (t4_toe_rexmt_backoff[i] != -1) { 3974 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 3975 shift = (i & 3) << 3; 3976 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 3977 M_TIMERBACKOFFINDEX0 << shift, v << shift); 3978 } 3979 } 3980 #endif 3981 return (0); 3982 } 3983 3984 #undef FW_PARAM_PFVF 3985 #undef FW_PARAM_DEV 3986 3987 static void 3988 t4_set_desc(struct adapter *sc) 3989 { 3990 char buf[128]; 3991 struct adapter_params *p = &sc->params; 3992 3993 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 3994 3995 device_set_desc_copy(sc->dev, buf); 3996 } 3997 3998 static void 3999 build_medialist(struct port_info *pi, struct ifmedia *media) 4000 { 4001 int m; 4002 4003 PORT_LOCK_ASSERT_OWNED(pi); 4004 4005 ifmedia_removeall(media); 4006 4007 /* 4008 * XXX: Would it be better to ifmedia_add all 4 combinations of pause 4009 * settings for every speed instead of just txpause|rxpause? ifconfig 4010 * media display looks much better if autoselect is the only case where 4011 * ifm_current is different from ifm_active. If the user picks anything 4012 * except txpause|rxpause the display is ugly. 4013 */ 4014 m = IFM_ETHER | IFM_FDX | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4015 4016 switch(pi->port_type) { 4017 case FW_PORT_TYPE_BT_XFI: 4018 case FW_PORT_TYPE_BT_XAUI: 4019 ifmedia_add(media, m | IFM_10G_T, 0, NULL); 4020 /* fall through */ 4021 4022 case FW_PORT_TYPE_BT_SGMII: 4023 ifmedia_add(media, m | IFM_1000_T, 0, NULL); 4024 ifmedia_add(media, m | IFM_100_TX, 0, NULL); 4025 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL); 4026 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 4027 break; 4028 4029 case FW_PORT_TYPE_CX4: 4030 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL); 4031 ifmedia_set(media, m | IFM_10G_CX4); 4032 break; 4033 4034 case FW_PORT_TYPE_QSFP_10G: 4035 case FW_PORT_TYPE_SFP: 4036 case FW_PORT_TYPE_FIBER_XFI: 4037 case FW_PORT_TYPE_FIBER_XAUI: 4038 switch (pi->mod_type) { 4039 4040 case FW_PORT_MOD_TYPE_LR: 4041 ifmedia_add(media, m | IFM_10G_LR, 0, NULL); 4042 ifmedia_set(media, m | IFM_10G_LR); 4043 break; 4044 4045 case FW_PORT_MOD_TYPE_SR: 4046 ifmedia_add(media, m | IFM_10G_SR, 0, NULL); 4047 ifmedia_set(media, m | IFM_10G_SR); 4048 break; 4049 4050 case FW_PORT_MOD_TYPE_LRM: 4051 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL); 4052 ifmedia_set(media, m | IFM_10G_LRM); 4053 break; 4054 4055 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 4056 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 4057 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL); 4058 ifmedia_set(media, m | IFM_10G_TWINAX); 4059 break; 4060 4061 case FW_PORT_MOD_TYPE_NONE: 4062 m &= ~IFM_FDX; 4063 ifmedia_add(media, m | IFM_NONE, 0, NULL); 4064 ifmedia_set(media, m | IFM_NONE); 4065 break; 4066 4067 case FW_PORT_MOD_TYPE_NA: 4068 case FW_PORT_MOD_TYPE_ER: 4069 default: 4070 device_printf(pi->dev, 4071 "unknown port_type (%d), mod_type (%d)\n", 4072 pi->port_type, pi->mod_type); 4073 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4074 ifmedia_set(media, m | IFM_UNKNOWN); 4075 break; 4076 } 4077 break; 4078 4079 case FW_PORT_TYPE_CR_QSFP: 4080 case FW_PORT_TYPE_SFP28: 4081 case FW_PORT_TYPE_KR_SFP28: 4082 switch (pi->mod_type) { 4083 4084 case FW_PORT_MOD_TYPE_SR: 4085 ifmedia_add(media, m | IFM_25G_SR, 0, NULL); 4086 ifmedia_set(media, m | IFM_25G_SR); 4087 break; 4088 4089 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 4090 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 4091 ifmedia_add(media, m | IFM_25G_CR, 0, NULL); 4092 ifmedia_set(media, m | IFM_25G_CR); 4093 break; 4094 4095 case FW_PORT_MOD_TYPE_NONE: 4096 m &= ~IFM_FDX; 4097 ifmedia_add(media, m | IFM_NONE, 0, NULL); 4098 ifmedia_set(media, m | IFM_NONE); 4099 break; 4100 4101 default: 4102 device_printf(pi->dev, 4103 "unknown port_type (%d), mod_type (%d)\n", 4104 pi->port_type, pi->mod_type); 4105 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4106 ifmedia_set(media, m | IFM_UNKNOWN); 4107 break; 4108 } 4109 break; 4110 4111 case FW_PORT_TYPE_QSFP: 4112 switch (pi->mod_type) { 4113 4114 case FW_PORT_MOD_TYPE_LR: 4115 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL); 4116 ifmedia_set(media, m | IFM_40G_LR4); 4117 break; 4118 4119 case FW_PORT_MOD_TYPE_SR: 4120 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL); 4121 ifmedia_set(media, m | IFM_40G_SR4); 4122 break; 4123 4124 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 4125 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 4126 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL); 4127 ifmedia_set(media, m | IFM_40G_CR4); 4128 break; 4129 4130 case FW_PORT_MOD_TYPE_NONE: 4131 m &= ~IFM_FDX; 4132 ifmedia_add(media, m | IFM_NONE, 0, NULL); 4133 ifmedia_set(media, m | IFM_NONE); 4134 break; 4135 4136 default: 4137 device_printf(pi->dev, 4138 "unknown port_type (%d), mod_type (%d)\n", 4139 pi->port_type, pi->mod_type); 4140 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4141 ifmedia_set(media, m | IFM_UNKNOWN); 4142 break; 4143 } 4144 break; 4145 4146 case FW_PORT_TYPE_KR4_100G: 4147 case FW_PORT_TYPE_CR4_QSFP: 4148 switch (pi->mod_type) { 4149 4150 case FW_PORT_MOD_TYPE_LR: 4151 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL); 4152 ifmedia_set(media, m | IFM_100G_LR4); 4153 break; 4154 4155 case FW_PORT_MOD_TYPE_SR: 4156 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL); 4157 ifmedia_set(media, m | IFM_100G_SR4); 4158 break; 4159 4160 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 4161 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 4162 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL); 4163 ifmedia_set(media, m | IFM_100G_CR4); 4164 break; 4165 4166 case FW_PORT_MOD_TYPE_NONE: 4167 m &= ~IFM_FDX; 4168 ifmedia_add(media, m | IFM_NONE, 0, NULL); 4169 ifmedia_set(media, m | IFM_NONE); 4170 break; 4171 4172 default: 4173 device_printf(pi->dev, 4174 "unknown port_type (%d), mod_type (%d)\n", 4175 pi->port_type, pi->mod_type); 4176 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4177 ifmedia_set(media, m | IFM_UNKNOWN); 4178 break; 4179 } 4180 break; 4181 4182 default: 4183 device_printf(pi->dev, 4184 "unknown port_type (%d), mod_type (%d)\n", pi->port_type, 4185 pi->mod_type); 4186 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4187 ifmedia_set(media, m | IFM_UNKNOWN); 4188 break; 4189 } 4190 } 4191 4192 /* 4193 * Update all the requested_* fields in the link config and then send a mailbox 4194 * command to apply the settings. 4195 */ 4196 static void 4197 init_l1cfg(struct port_info *pi) 4198 { 4199 struct adapter *sc = pi->adapter; 4200 struct link_config *lc = &pi->link_cfg; 4201 int rc; 4202 4203 ASSERT_SYNCHRONIZED_OP(sc); 4204 4205 lc->requested_speed = port_top_speed(pi); /* in Gbps */ 4206 if (t4_autoneg != 0 && lc->supported & FW_PORT_CAP_ANEG) { 4207 lc->requested_aneg = AUTONEG_ENABLE; 4208 } else { 4209 lc->requested_aneg = AUTONEG_DISABLE; 4210 } 4211 4212 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX); 4213 4214 if (t4_fec != -1) { 4215 lc->requested_fec = t4_fec & (FEC_RS | FEC_BASER_RS | 4216 FEC_RESERVED); 4217 } else { 4218 /* Use the suggested value provided by the firmware in acaps */ 4219 if (lc->advertising & FW_PORT_CAP_FEC_RS) 4220 lc->requested_fec = FEC_RS; 4221 else if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS) 4222 lc->requested_fec = FEC_BASER_RS; 4223 else 4224 lc->requested_fec = 0; 4225 } 4226 4227 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4228 if (rc != 0) { 4229 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4230 } else { 4231 lc->fc = lc->requested_fc; 4232 lc->fec = lc->requested_fec; 4233 } 4234 } 4235 4236 #define FW_MAC_EXACT_CHUNK 7 4237 4238 /* 4239 * Program the port's XGMAC based on parameters in ifnet. The caller also 4240 * indicates which parameters should be programmed (the rest are left alone). 4241 */ 4242 int 4243 update_mac_settings(struct ifnet *ifp, int flags) 4244 { 4245 int rc = 0; 4246 struct vi_info *vi = ifp->if_softc; 4247 struct port_info *pi = vi->pi; 4248 struct adapter *sc = pi->adapter; 4249 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4250 4251 ASSERT_SYNCHRONIZED_OP(sc); 4252 KASSERT(flags, ("%s: not told what to update.", __func__)); 4253 4254 if (flags & XGMAC_MTU) 4255 mtu = ifp->if_mtu; 4256 4257 if (flags & XGMAC_PROMISC) 4258 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4259 4260 if (flags & XGMAC_ALLMULTI) 4261 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4262 4263 if (flags & XGMAC_VLANEX) 4264 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4265 4266 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4267 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4268 allmulti, 1, vlanex, false); 4269 if (rc) { 4270 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4271 rc); 4272 return (rc); 4273 } 4274 } 4275 4276 if (flags & XGMAC_UCADDR) { 4277 uint8_t ucaddr[ETHER_ADDR_LEN]; 4278 4279 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4280 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4281 ucaddr, true, true); 4282 if (rc < 0) { 4283 rc = -rc; 4284 if_printf(ifp, "change_mac failed: %d\n", rc); 4285 return (rc); 4286 } else { 4287 vi->xact_addr_filt = rc; 4288 rc = 0; 4289 } 4290 } 4291 4292 if (flags & XGMAC_MCADDRS) { 4293 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4294 int del = 1; 4295 uint64_t hash = 0; 4296 struct ifmultiaddr *ifma; 4297 int i = 0, j; 4298 4299 if_maddr_rlock(ifp); 4300 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4301 if (ifma->ifma_addr->sa_family != AF_LINK) 4302 continue; 4303 mcaddr[i] = 4304 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4305 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4306 i++; 4307 4308 if (i == FW_MAC_EXACT_CHUNK) { 4309 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4310 del, i, mcaddr, NULL, &hash, 0); 4311 if (rc < 0) { 4312 rc = -rc; 4313 for (j = 0; j < i; j++) { 4314 if_printf(ifp, 4315 "failed to add mc address" 4316 " %02x:%02x:%02x:" 4317 "%02x:%02x:%02x rc=%d\n", 4318 mcaddr[j][0], mcaddr[j][1], 4319 mcaddr[j][2], mcaddr[j][3], 4320 mcaddr[j][4], mcaddr[j][5], 4321 rc); 4322 } 4323 goto mcfail; 4324 } 4325 del = 0; 4326 i = 0; 4327 } 4328 } 4329 if (i > 0) { 4330 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4331 mcaddr, NULL, &hash, 0); 4332 if (rc < 0) { 4333 rc = -rc; 4334 for (j = 0; j < i; j++) { 4335 if_printf(ifp, 4336 "failed to add mc address" 4337 " %02x:%02x:%02x:" 4338 "%02x:%02x:%02x rc=%d\n", 4339 mcaddr[j][0], mcaddr[j][1], 4340 mcaddr[j][2], mcaddr[j][3], 4341 mcaddr[j][4], mcaddr[j][5], 4342 rc); 4343 } 4344 goto mcfail; 4345 } 4346 } 4347 4348 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4349 if (rc != 0) 4350 if_printf(ifp, "failed to set mc address hash: %d", rc); 4351 mcfail: 4352 if_maddr_runlock(ifp); 4353 } 4354 4355 return (rc); 4356 } 4357 4358 /* 4359 * {begin|end}_synchronized_op must be called from the same thread. 4360 */ 4361 int 4362 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4363 char *wmesg) 4364 { 4365 int rc, pri; 4366 4367 #ifdef WITNESS 4368 /* the caller thinks it's ok to sleep, but is it really? */ 4369 if (flags & SLEEP_OK) 4370 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4371 "begin_synchronized_op"); 4372 #endif 4373 4374 if (INTR_OK) 4375 pri = PCATCH; 4376 else 4377 pri = 0; 4378 4379 ADAPTER_LOCK(sc); 4380 for (;;) { 4381 4382 if (vi && IS_DOOMED(vi)) { 4383 rc = ENXIO; 4384 goto done; 4385 } 4386 4387 if (!IS_BUSY(sc)) { 4388 rc = 0; 4389 break; 4390 } 4391 4392 if (!(flags & SLEEP_OK)) { 4393 rc = EBUSY; 4394 goto done; 4395 } 4396 4397 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4398 rc = EINTR; 4399 goto done; 4400 } 4401 } 4402 4403 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4404 SET_BUSY(sc); 4405 #ifdef INVARIANTS 4406 sc->last_op = wmesg; 4407 sc->last_op_thr = curthread; 4408 sc->last_op_flags = flags; 4409 #endif 4410 4411 done: 4412 if (!(flags & HOLD_LOCK) || rc) 4413 ADAPTER_UNLOCK(sc); 4414 4415 return (rc); 4416 } 4417 4418 /* 4419 * Tell if_ioctl and if_init that the VI is going away. This is 4420 * special variant of begin_synchronized_op and must be paired with a 4421 * call to end_synchronized_op. 4422 */ 4423 void 4424 doom_vi(struct adapter *sc, struct vi_info *vi) 4425 { 4426 4427 ADAPTER_LOCK(sc); 4428 SET_DOOMED(vi); 4429 wakeup(&sc->flags); 4430 while (IS_BUSY(sc)) 4431 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4432 SET_BUSY(sc); 4433 #ifdef INVARIANTS 4434 sc->last_op = "t4detach"; 4435 sc->last_op_thr = curthread; 4436 sc->last_op_flags = 0; 4437 #endif 4438 ADAPTER_UNLOCK(sc); 4439 } 4440 4441 /* 4442 * {begin|end}_synchronized_op must be called from the same thread. 4443 */ 4444 void 4445 end_synchronized_op(struct adapter *sc, int flags) 4446 { 4447 4448 if (flags & LOCK_HELD) 4449 ADAPTER_LOCK_ASSERT_OWNED(sc); 4450 else 4451 ADAPTER_LOCK(sc); 4452 4453 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 4454 CLR_BUSY(sc); 4455 wakeup(&sc->flags); 4456 ADAPTER_UNLOCK(sc); 4457 } 4458 4459 static int 4460 cxgbe_init_synchronized(struct vi_info *vi) 4461 { 4462 struct port_info *pi = vi->pi; 4463 struct adapter *sc = pi->adapter; 4464 struct ifnet *ifp = vi->ifp; 4465 int rc = 0, i; 4466 struct sge_txq *txq; 4467 4468 ASSERT_SYNCHRONIZED_OP(sc); 4469 4470 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4471 return (0); /* already running */ 4472 4473 if (!(sc->flags & FULL_INIT_DONE) && 4474 ((rc = adapter_full_init(sc)) != 0)) 4475 return (rc); /* error message displayed already */ 4476 4477 if (!(vi->flags & VI_INIT_DONE) && 4478 ((rc = vi_full_init(vi)) != 0)) 4479 return (rc); /* error message displayed already */ 4480 4481 rc = update_mac_settings(ifp, XGMAC_ALL); 4482 if (rc) 4483 goto done; /* error message displayed already */ 4484 4485 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 4486 if (rc != 0) { 4487 if_printf(ifp, "enable_vi failed: %d\n", rc); 4488 goto done; 4489 } 4490 4491 /* 4492 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 4493 * if this changes. 4494 */ 4495 4496 for_each_txq(vi, i, txq) { 4497 TXQ_LOCK(txq); 4498 txq->eq.flags |= EQ_ENABLED; 4499 TXQ_UNLOCK(txq); 4500 } 4501 4502 /* 4503 * The first iq of the first port to come up is used for tracing. 4504 */ 4505 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 4506 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 4507 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4508 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4509 V_QUEUENUMBER(sc->traceq)); 4510 pi->flags |= HAS_TRACEQ; 4511 } 4512 4513 /* all ok */ 4514 PORT_LOCK(pi); 4515 if (pi->up_vis++ == 0) { 4516 t4_update_port_info(pi); 4517 build_medialist(pi, &pi->media); 4518 init_l1cfg(pi); 4519 } 4520 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4521 4522 if (pi->nvi > 1 || sc->flags & IS_VF) 4523 callout_reset(&vi->tick, hz, vi_tick, vi); 4524 else 4525 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4526 PORT_UNLOCK(pi); 4527 done: 4528 if (rc != 0) 4529 cxgbe_uninit_synchronized(vi); 4530 4531 return (rc); 4532 } 4533 4534 /* 4535 * Idempotent. 4536 */ 4537 static int 4538 cxgbe_uninit_synchronized(struct vi_info *vi) 4539 { 4540 struct port_info *pi = vi->pi; 4541 struct adapter *sc = pi->adapter; 4542 struct ifnet *ifp = vi->ifp; 4543 int rc, i; 4544 struct sge_txq *txq; 4545 4546 ASSERT_SYNCHRONIZED_OP(sc); 4547 4548 if (!(vi->flags & VI_INIT_DONE)) { 4549 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4550 KASSERT(0, ("uninited VI is running")); 4551 if_printf(ifp, "uninited VI with running ifnet. " 4552 "vi->flags 0x%016lx, if_flags 0x%08x, " 4553 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 4554 ifp->if_drv_flags); 4555 } 4556 return (0); 4557 } 4558 4559 /* 4560 * Disable the VI so that all its data in either direction is discarded 4561 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4562 * tick) intact as the TP can deliver negative advice or data that it's 4563 * holding in its RAM (for an offloaded connection) even after the VI is 4564 * disabled. 4565 */ 4566 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4567 if (rc) { 4568 if_printf(ifp, "disable_vi failed: %d\n", rc); 4569 return (rc); 4570 } 4571 4572 for_each_txq(vi, i, txq) { 4573 TXQ_LOCK(txq); 4574 txq->eq.flags &= ~EQ_ENABLED; 4575 TXQ_UNLOCK(txq); 4576 } 4577 4578 PORT_LOCK(pi); 4579 if (pi->nvi > 1 || sc->flags & IS_VF) 4580 callout_stop(&vi->tick); 4581 else 4582 callout_stop(&pi->tick); 4583 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4584 PORT_UNLOCK(pi); 4585 return (0); 4586 } 4587 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4588 pi->up_vis--; 4589 if (pi->up_vis > 0) { 4590 PORT_UNLOCK(pi); 4591 return (0); 4592 } 4593 PORT_UNLOCK(pi); 4594 4595 pi->link_cfg.link_ok = 0; 4596 pi->link_cfg.speed = 0; 4597 pi->link_cfg.link_down_rc = 255; 4598 t4_os_link_changed(pi); 4599 pi->old_link_cfg = pi->link_cfg; 4600 4601 return (0); 4602 } 4603 4604 /* 4605 * It is ok for this function to fail midway and return right away. t4_detach 4606 * will walk the entire sc->irq list and clean up whatever is valid. 4607 */ 4608 int 4609 t4_setup_intr_handlers(struct adapter *sc) 4610 { 4611 int rc, rid, p, q, v; 4612 char s[8]; 4613 struct irq *irq; 4614 struct port_info *pi; 4615 struct vi_info *vi; 4616 struct sge *sge = &sc->sge; 4617 struct sge_rxq *rxq; 4618 #ifdef TCP_OFFLOAD 4619 struct sge_ofld_rxq *ofld_rxq; 4620 #endif 4621 #ifdef DEV_NETMAP 4622 struct sge_nm_rxq *nm_rxq; 4623 #endif 4624 #ifdef RSS 4625 int nbuckets = rss_getnumbuckets(); 4626 #endif 4627 4628 /* 4629 * Setup interrupts. 4630 */ 4631 irq = &sc->irq[0]; 4632 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4633 if (forwarding_intr_to_fwq(sc)) 4634 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4635 4636 /* Multiple interrupts. */ 4637 if (sc->flags & IS_VF) 4638 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4639 ("%s: too few intr.", __func__)); 4640 else 4641 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4642 ("%s: too few intr.", __func__)); 4643 4644 /* The first one is always error intr on PFs */ 4645 if (!(sc->flags & IS_VF)) { 4646 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4647 if (rc != 0) 4648 return (rc); 4649 irq++; 4650 rid++; 4651 } 4652 4653 /* The second one is always the firmware event queue (first on VFs) */ 4654 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4655 if (rc != 0) 4656 return (rc); 4657 irq++; 4658 rid++; 4659 4660 for_each_port(sc, p) { 4661 pi = sc->port[p]; 4662 for_each_vi(pi, v, vi) { 4663 vi->first_intr = rid - 1; 4664 4665 if (vi->nnmrxq > 0) { 4666 int n = max(vi->nrxq, vi->nnmrxq); 4667 4668 rxq = &sge->rxq[vi->first_rxq]; 4669 #ifdef DEV_NETMAP 4670 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4671 #endif 4672 for (q = 0; q < n; q++) { 4673 snprintf(s, sizeof(s), "%x%c%x", p, 4674 'a' + v, q); 4675 if (q < vi->nrxq) 4676 irq->rxq = rxq++; 4677 #ifdef DEV_NETMAP 4678 if (q < vi->nnmrxq) 4679 irq->nm_rxq = nm_rxq++; 4680 #endif 4681 rc = t4_alloc_irq(sc, irq, rid, 4682 t4_vi_intr, irq, s); 4683 if (rc != 0) 4684 return (rc); 4685 #ifdef RSS 4686 if (q < vi->nrxq) { 4687 bus_bind_intr(sc->dev, irq->res, 4688 rss_getcpu(q % nbuckets)); 4689 } 4690 #endif 4691 irq++; 4692 rid++; 4693 vi->nintr++; 4694 } 4695 } else { 4696 for_each_rxq(vi, q, rxq) { 4697 snprintf(s, sizeof(s), "%x%c%x", p, 4698 'a' + v, q); 4699 rc = t4_alloc_irq(sc, irq, rid, 4700 t4_intr, rxq, s); 4701 if (rc != 0) 4702 return (rc); 4703 #ifdef RSS 4704 bus_bind_intr(sc->dev, irq->res, 4705 rss_getcpu(q % nbuckets)); 4706 #endif 4707 irq++; 4708 rid++; 4709 vi->nintr++; 4710 } 4711 } 4712 #ifdef TCP_OFFLOAD 4713 for_each_ofld_rxq(vi, q, ofld_rxq) { 4714 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 4715 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 4716 ofld_rxq, s); 4717 if (rc != 0) 4718 return (rc); 4719 irq++; 4720 rid++; 4721 vi->nintr++; 4722 } 4723 #endif 4724 } 4725 } 4726 MPASS(irq == &sc->irq[sc->intr_count]); 4727 4728 return (0); 4729 } 4730 4731 int 4732 adapter_full_init(struct adapter *sc) 4733 { 4734 int rc, i; 4735 #ifdef RSS 4736 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4737 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4738 #endif 4739 4740 ASSERT_SYNCHRONIZED_OP(sc); 4741 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4742 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 4743 ("%s: FULL_INIT_DONE already", __func__)); 4744 4745 /* 4746 * queues that belong to the adapter (not any particular port). 4747 */ 4748 rc = t4_setup_adapter_queues(sc); 4749 if (rc != 0) 4750 goto done; 4751 4752 for (i = 0; i < nitems(sc->tq); i++) { 4753 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 4754 taskqueue_thread_enqueue, &sc->tq[i]); 4755 if (sc->tq[i] == NULL) { 4756 device_printf(sc->dev, 4757 "failed to allocate task queue %d\n", i); 4758 rc = ENOMEM; 4759 goto done; 4760 } 4761 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 4762 device_get_nameunit(sc->dev), i); 4763 } 4764 #ifdef RSS 4765 MPASS(RSS_KEYSIZE == 40); 4766 rss_getkey((void *)&raw_rss_key[0]); 4767 for (i = 0; i < nitems(rss_key); i++) { 4768 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 4769 } 4770 t4_write_rss_key(sc, &rss_key[0], -1, 1); 4771 #endif 4772 4773 if (!(sc->flags & IS_VF)) 4774 t4_intr_enable(sc); 4775 sc->flags |= FULL_INIT_DONE; 4776 done: 4777 if (rc != 0) 4778 adapter_full_uninit(sc); 4779 4780 return (rc); 4781 } 4782 4783 int 4784 adapter_full_uninit(struct adapter *sc) 4785 { 4786 int i; 4787 4788 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4789 4790 t4_teardown_adapter_queues(sc); 4791 4792 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 4793 taskqueue_free(sc->tq[i]); 4794 sc->tq[i] = NULL; 4795 } 4796 4797 sc->flags &= ~FULL_INIT_DONE; 4798 4799 return (0); 4800 } 4801 4802 #ifdef RSS 4803 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 4804 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 4805 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 4806 RSS_HASHTYPE_RSS_UDP_IPV6) 4807 4808 /* Translates kernel hash types to hardware. */ 4809 static int 4810 hashconfig_to_hashen(int hashconfig) 4811 { 4812 int hashen = 0; 4813 4814 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 4815 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 4816 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 4817 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 4818 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 4819 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4820 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4821 } 4822 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 4823 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4824 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4825 } 4826 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 4827 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4828 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 4829 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4830 4831 return (hashen); 4832 } 4833 4834 /* Translates hardware hash types to kernel. */ 4835 static int 4836 hashen_to_hashconfig(int hashen) 4837 { 4838 int hashconfig = 0; 4839 4840 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 4841 /* 4842 * If UDP hashing was enabled it must have been enabled for 4843 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 4844 * enabling any 4-tuple hash is nonsense configuration. 4845 */ 4846 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4847 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 4848 4849 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4850 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 4851 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4852 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 4853 } 4854 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4855 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 4856 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4857 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 4858 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 4859 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 4860 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 4861 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 4862 4863 return (hashconfig); 4864 } 4865 #endif 4866 4867 int 4868 vi_full_init(struct vi_info *vi) 4869 { 4870 struct adapter *sc = vi->pi->adapter; 4871 struct ifnet *ifp = vi->ifp; 4872 uint16_t *rss; 4873 struct sge_rxq *rxq; 4874 int rc, i, j, hashen; 4875 #ifdef RSS 4876 int nbuckets = rss_getnumbuckets(); 4877 int hashconfig = rss_gethashconfig(); 4878 int extra; 4879 #endif 4880 4881 ASSERT_SYNCHRONIZED_OP(sc); 4882 KASSERT((vi->flags & VI_INIT_DONE) == 0, 4883 ("%s: VI_INIT_DONE already", __func__)); 4884 4885 sysctl_ctx_init(&vi->ctx); 4886 vi->flags |= VI_SYSCTL_CTX; 4887 4888 /* 4889 * Allocate tx/rx/fl queues for this VI. 4890 */ 4891 rc = t4_setup_vi_queues(vi); 4892 if (rc != 0) 4893 goto done; /* error message displayed already */ 4894 4895 /* 4896 * Setup RSS for this VI. Save a copy of the RSS table for later use. 4897 */ 4898 if (vi->nrxq > vi->rss_size) { 4899 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 4900 "some queues will never receive traffic.\n", vi->nrxq, 4901 vi->rss_size); 4902 } else if (vi->rss_size % vi->nrxq) { 4903 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 4904 "expect uneven traffic distribution.\n", vi->nrxq, 4905 vi->rss_size); 4906 } 4907 #ifdef RSS 4908 if (vi->nrxq != nbuckets) { 4909 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 4910 "performance will be impacted.\n", vi->nrxq, nbuckets); 4911 } 4912 #endif 4913 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 4914 for (i = 0; i < vi->rss_size;) { 4915 #ifdef RSS 4916 j = rss_get_indirection_to_bucket(i); 4917 j %= vi->nrxq; 4918 rxq = &sc->sge.rxq[vi->first_rxq + j]; 4919 rss[i++] = rxq->iq.abs_id; 4920 #else 4921 for_each_rxq(vi, j, rxq) { 4922 rss[i++] = rxq->iq.abs_id; 4923 if (i == vi->rss_size) 4924 break; 4925 } 4926 #endif 4927 } 4928 4929 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 4930 vi->rss_size); 4931 if (rc != 0) { 4932 if_printf(ifp, "rss_config failed: %d\n", rc); 4933 goto done; 4934 } 4935 4936 #ifdef RSS 4937 hashen = hashconfig_to_hashen(hashconfig); 4938 4939 /* 4940 * We may have had to enable some hashes even though the global config 4941 * wants them disabled. This is a potential problem that must be 4942 * reported to the user. 4943 */ 4944 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 4945 4946 /* 4947 * If we consider only the supported hash types, then the enabled hashes 4948 * are a superset of the requested hashes. In other words, there cannot 4949 * be any supported hash that was requested but not enabled, but there 4950 * can be hashes that were not requested but had to be enabled. 4951 */ 4952 extra &= SUPPORTED_RSS_HASHTYPES; 4953 MPASS((extra & hashconfig) == 0); 4954 4955 if (extra) { 4956 if_printf(ifp, 4957 "global RSS config (0x%x) cannot be accommodated.\n", 4958 hashconfig); 4959 } 4960 if (extra & RSS_HASHTYPE_RSS_IPV4) 4961 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 4962 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 4963 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 4964 if (extra & RSS_HASHTYPE_RSS_IPV6) 4965 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 4966 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 4967 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 4968 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 4969 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 4970 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 4971 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 4972 #else 4973 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 4974 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 4975 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4976 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 4977 #endif 4978 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0); 4979 if (rc != 0) { 4980 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 4981 goto done; 4982 } 4983 4984 vi->rss = rss; 4985 vi->flags |= VI_INIT_DONE; 4986 done: 4987 if (rc != 0) 4988 vi_full_uninit(vi); 4989 4990 return (rc); 4991 } 4992 4993 /* 4994 * Idempotent. 4995 */ 4996 int 4997 vi_full_uninit(struct vi_info *vi) 4998 { 4999 struct port_info *pi = vi->pi; 5000 struct adapter *sc = pi->adapter; 5001 int i; 5002 struct sge_rxq *rxq; 5003 struct sge_txq *txq; 5004 #ifdef TCP_OFFLOAD 5005 struct sge_ofld_rxq *ofld_rxq; 5006 struct sge_wrq *ofld_txq; 5007 #endif 5008 5009 if (vi->flags & VI_INIT_DONE) { 5010 5011 /* Need to quiesce queues. */ 5012 5013 /* XXX: Only for the first VI? */ 5014 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5015 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5016 5017 for_each_txq(vi, i, txq) { 5018 quiesce_txq(sc, txq); 5019 } 5020 5021 #ifdef TCP_OFFLOAD 5022 for_each_ofld_txq(vi, i, ofld_txq) { 5023 quiesce_wrq(sc, ofld_txq); 5024 } 5025 #endif 5026 5027 for_each_rxq(vi, i, rxq) { 5028 quiesce_iq(sc, &rxq->iq); 5029 quiesce_fl(sc, &rxq->fl); 5030 } 5031 5032 #ifdef TCP_OFFLOAD 5033 for_each_ofld_rxq(vi, i, ofld_rxq) { 5034 quiesce_iq(sc, &ofld_rxq->iq); 5035 quiesce_fl(sc, &ofld_rxq->fl); 5036 } 5037 #endif 5038 free(vi->rss, M_CXGBE); 5039 free(vi->nm_rss, M_CXGBE); 5040 } 5041 5042 t4_teardown_vi_queues(vi); 5043 vi->flags &= ~VI_INIT_DONE; 5044 5045 return (0); 5046 } 5047 5048 static void 5049 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5050 { 5051 struct sge_eq *eq = &txq->eq; 5052 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5053 5054 (void) sc; /* unused */ 5055 5056 #ifdef INVARIANTS 5057 TXQ_LOCK(txq); 5058 MPASS((eq->flags & EQ_ENABLED) == 0); 5059 TXQ_UNLOCK(txq); 5060 #endif 5061 5062 /* Wait for the mp_ring to empty. */ 5063 while (!mp_ring_is_idle(txq->r)) { 5064 mp_ring_check_drainage(txq->r, 0); 5065 pause("rquiesce", 1); 5066 } 5067 5068 /* Then wait for the hardware to finish. */ 5069 while (spg->cidx != htobe16(eq->pidx)) 5070 pause("equiesce", 1); 5071 5072 /* Finally, wait for the driver to reclaim all descriptors. */ 5073 while (eq->cidx != eq->pidx) 5074 pause("dquiesce", 1); 5075 } 5076 5077 static void 5078 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5079 { 5080 5081 /* XXXTX */ 5082 } 5083 5084 static void 5085 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5086 { 5087 (void) sc; /* unused */ 5088 5089 /* Synchronize with the interrupt handler */ 5090 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5091 pause("iqfree", 1); 5092 } 5093 5094 static void 5095 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5096 { 5097 mtx_lock(&sc->sfl_lock); 5098 FL_LOCK(fl); 5099 fl->flags |= FL_DOOMED; 5100 FL_UNLOCK(fl); 5101 callout_stop(&sc->sfl_callout); 5102 mtx_unlock(&sc->sfl_lock); 5103 5104 KASSERT((fl->flags & FL_STARVING) == 0, 5105 ("%s: still starving", __func__)); 5106 } 5107 5108 static int 5109 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5110 driver_intr_t *handler, void *arg, char *name) 5111 { 5112 int rc; 5113 5114 irq->rid = rid; 5115 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5116 RF_SHAREABLE | RF_ACTIVE); 5117 if (irq->res == NULL) { 5118 device_printf(sc->dev, 5119 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5120 return (ENOMEM); 5121 } 5122 5123 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5124 NULL, handler, arg, &irq->tag); 5125 if (rc != 0) { 5126 device_printf(sc->dev, 5127 "failed to setup interrupt for rid %d, name %s: %d\n", 5128 rid, name, rc); 5129 } else if (name) 5130 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5131 5132 return (rc); 5133 } 5134 5135 static int 5136 t4_free_irq(struct adapter *sc, struct irq *irq) 5137 { 5138 if (irq->tag) 5139 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5140 if (irq->res) 5141 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5142 5143 bzero(irq, sizeof(*irq)); 5144 5145 return (0); 5146 } 5147 5148 static void 5149 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5150 { 5151 5152 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5153 t4_get_regs(sc, buf, regs->len); 5154 } 5155 5156 #define A_PL_INDIR_CMD 0x1f8 5157 5158 #define S_PL_AUTOINC 31 5159 #define M_PL_AUTOINC 0x1U 5160 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5161 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5162 5163 #define S_PL_VFID 20 5164 #define M_PL_VFID 0xffU 5165 #define V_PL_VFID(x) ((x) << S_PL_VFID) 5166 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5167 5168 #define S_PL_ADDR 0 5169 #define M_PL_ADDR 0xfffffU 5170 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5171 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5172 5173 #define A_PL_INDIR_DATA 0x1fc 5174 5175 static uint64_t 5176 read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 5177 { 5178 u32 stats[2]; 5179 5180 mtx_assert(&sc->reg_lock, MA_OWNED); 5181 if (sc->flags & IS_VF) { 5182 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5183 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5184 } else { 5185 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5186 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5187 V_PL_ADDR(VF_MPS_REG(reg))); 5188 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5189 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5190 } 5191 return (((uint64_t)stats[1]) << 32 | stats[0]); 5192 } 5193 5194 static void 5195 t4_get_vi_stats(struct adapter *sc, unsigned int viid, 5196 struct fw_vi_stats_vf *stats) 5197 { 5198 5199 #define GET_STAT(name) \ 5200 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 5201 5202 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5203 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5204 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5205 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5206 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5207 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5208 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5209 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5210 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5211 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5212 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5213 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5214 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5215 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5216 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5217 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5218 5219 #undef GET_STAT 5220 } 5221 5222 static void 5223 t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 5224 { 5225 int reg; 5226 5227 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5228 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5229 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5230 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5231 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5232 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5233 } 5234 5235 static void 5236 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5237 { 5238 struct timeval tv; 5239 const struct timeval interval = {0, 250000}; /* 250ms */ 5240 5241 if (!(vi->flags & VI_INIT_DONE)) 5242 return; 5243 5244 getmicrotime(&tv); 5245 timevalsub(&tv, &interval); 5246 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5247 return; 5248 5249 mtx_lock(&sc->reg_lock); 5250 t4_get_vi_stats(sc, vi->viid, &vi->stats); 5251 getmicrotime(&vi->last_refreshed); 5252 mtx_unlock(&sc->reg_lock); 5253 } 5254 5255 static void 5256 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5257 { 5258 u_int i, v, tnl_cong_drops, bg_map; 5259 struct timeval tv; 5260 const struct timeval interval = {0, 250000}; /* 250ms */ 5261 5262 getmicrotime(&tv); 5263 timevalsub(&tv, &interval); 5264 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5265 return; 5266 5267 tnl_cong_drops = 0; 5268 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5269 bg_map = pi->mps_bg_map; 5270 while (bg_map) { 5271 i = ffs(bg_map) - 1; 5272 mtx_lock(&sc->reg_lock); 5273 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5274 A_TP_MIB_TNL_CNG_DROP_0 + i); 5275 mtx_unlock(&sc->reg_lock); 5276 tnl_cong_drops += v; 5277 bg_map &= ~(1 << i); 5278 } 5279 pi->tnl_cong_drops = tnl_cong_drops; 5280 getmicrotime(&pi->last_refreshed); 5281 } 5282 5283 static void 5284 cxgbe_tick(void *arg) 5285 { 5286 struct port_info *pi = arg; 5287 struct adapter *sc = pi->adapter; 5288 5289 PORT_LOCK_ASSERT_OWNED(pi); 5290 cxgbe_refresh_stats(sc, pi); 5291 5292 callout_schedule(&pi->tick, hz); 5293 } 5294 5295 void 5296 vi_tick(void *arg) 5297 { 5298 struct vi_info *vi = arg; 5299 struct adapter *sc = vi->pi->adapter; 5300 5301 vi_refresh_stats(sc, vi); 5302 5303 callout_schedule(&vi->tick, hz); 5304 } 5305 5306 static void 5307 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 5308 { 5309 struct ifnet *vlan; 5310 5311 if (arg != ifp || ifp->if_type != IFT_ETHER) 5312 return; 5313 5314 vlan = VLAN_DEVAT(ifp, vid); 5315 VLAN_SETCOOKIE(vlan, ifp); 5316 } 5317 5318 /* 5319 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5320 */ 5321 static char *caps_decoder[] = { 5322 "\20\001IPMI\002NCSI", /* 0: NBM */ 5323 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5324 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5325 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5326 "\006HASHFILTER\007ETHOFLD", 5327 "\20\001TOE", /* 4: TOE */ 5328 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5329 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5330 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5331 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5332 "\007T10DIF" 5333 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5334 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5335 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5336 "\004PO_INITIATOR\005PO_TARGET", 5337 }; 5338 5339 void 5340 t4_sysctls(struct adapter *sc) 5341 { 5342 struct sysctl_ctx_list *ctx; 5343 struct sysctl_oid *oid; 5344 struct sysctl_oid_list *children, *c0; 5345 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5346 5347 ctx = device_get_sysctl_ctx(sc->dev); 5348 5349 /* 5350 * dev.t4nex.X. 5351 */ 5352 oid = device_get_sysctl_tree(sc->dev); 5353 c0 = children = SYSCTL_CHILDREN(oid); 5354 5355 sc->sc_do_rxcopy = 1; 5356 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5357 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5358 5359 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5360 sc->params.nports, "# of ports"); 5361 5362 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5363 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 5364 sysctl_bitfield, "A", "available doorbells"); 5365 5366 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5367 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5368 5369 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5370 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5371 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5372 "interrupt holdoff timer values (us)"); 5373 5374 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5375 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5376 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5377 "interrupt holdoff packet counter values"); 5378 5379 t4_sge_sysctls(sc, ctx, children); 5380 5381 sc->lro_timeout = 100; 5382 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5383 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5384 5385 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5386 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5387 5388 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5389 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5390 5391 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5392 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5393 5394 if (sc->flags & IS_VF) 5395 return; 5396 5397 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5398 NULL, chip_rev(sc), "chip hardware revision"); 5399 5400 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5401 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5402 5403 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5404 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5405 5406 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5407 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5408 5409 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5410 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5411 5412 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5413 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5414 5415 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5416 sc->er_version, 0, "expansion ROM version"); 5417 5418 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5419 sc->bs_version, 0, "bootstrap firmware version"); 5420 5421 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5422 NULL, sc->params.scfg_vers, "serial config version"); 5423 5424 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5425 NULL, sc->params.vpd_vers, "VPD version"); 5426 5427 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5428 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5429 5430 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5431 sc->cfcsum, "config file checksum"); 5432 5433 #define SYSCTL_CAP(name, n, text) \ 5434 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5435 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \ 5436 sysctl_bitfield, "A", "available " text " capabilities") 5437 5438 SYSCTL_CAP(nbmcaps, 0, "NBM"); 5439 SYSCTL_CAP(linkcaps, 1, "link"); 5440 SYSCTL_CAP(switchcaps, 2, "switch"); 5441 SYSCTL_CAP(niccaps, 3, "NIC"); 5442 SYSCTL_CAP(toecaps, 4, "TCP offload"); 5443 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 5444 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 5445 SYSCTL_CAP(cryptocaps, 7, "crypto"); 5446 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 5447 #undef SYSCTL_CAP 5448 5449 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 5450 NULL, sc->tids.nftids, "number of filters"); 5451 5452 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 5453 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 5454 "chip temperature (in Celsius)"); 5455 5456 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 5457 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 5458 5459 #ifdef SBUF_DRAIN 5460 /* 5461 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 5462 */ 5463 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 5464 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 5465 "logs and miscellaneous information"); 5466 children = SYSCTL_CHILDREN(oid); 5467 5468 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 5469 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5470 sysctl_cctrl, "A", "congestion control"); 5471 5472 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 5473 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5474 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 5475 5476 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 5477 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 5478 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 5479 5480 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 5481 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 5482 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 5483 5484 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 5485 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 5486 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 5487 5488 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 5489 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 5490 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 5491 5492 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 5493 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 5494 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 5495 5496 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 5497 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5498 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 5499 "A", "CIM logic analyzer"); 5500 5501 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 5502 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5503 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 5504 5505 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 5506 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 5507 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 5508 5509 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 5510 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 5511 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 5512 5513 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 5514 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 5515 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 5516 5517 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 5518 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 5519 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 5520 5521 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 5522 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 5523 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 5524 5525 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 5526 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 5527 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5528 5529 if (chip_id(sc) > CHELSIO_T4) { 5530 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5531 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5532 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5533 5534 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5535 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5536 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5537 } 5538 5539 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5540 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5541 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5542 5543 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5544 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5545 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5546 5547 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5548 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5549 sysctl_cpl_stats, "A", "CPL statistics"); 5550 5551 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5552 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5553 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5554 5555 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5556 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5557 sysctl_devlog, "A", "firmware's device log"); 5558 5559 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5560 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5561 sysctl_fcoe_stats, "A", "FCoE statistics"); 5562 5563 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5564 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5565 sysctl_hw_sched, "A", "hardware scheduler "); 5566 5567 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5568 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5569 sysctl_l2t, "A", "hardware L2 table"); 5570 5571 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5572 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5573 sysctl_lb_stats, "A", "loopback statistics"); 5574 5575 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5576 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5577 sysctl_meminfo, "A", "memory regions"); 5578 5579 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5580 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5581 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5582 "A", "MPS TCAM entries"); 5583 5584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5585 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5586 sysctl_path_mtus, "A", "path MTUs"); 5587 5588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5589 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5590 sysctl_pm_stats, "A", "PM statistics"); 5591 5592 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5593 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5594 sysctl_rdma_stats, "A", "RDMA statistics"); 5595 5596 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5597 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5598 sysctl_tcp_stats, "A", "TCP statistics"); 5599 5600 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5601 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5602 sysctl_tids, "A", "TID information"); 5603 5604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5605 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5606 sysctl_tp_err_stats, "A", "TP error statistics"); 5607 5608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5609 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5610 "TP logic analyzer event capture mask"); 5611 5612 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5613 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5614 sysctl_tp_la, "A", "TP logic analyzer"); 5615 5616 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5617 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5618 sysctl_tx_rate, "A", "Tx rate"); 5619 5620 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5621 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5622 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5623 5624 if (chip_id(sc) >= CHELSIO_T5) { 5625 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5626 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5627 sysctl_wcwr_stats, "A", "write combined work requests"); 5628 } 5629 #endif 5630 5631 #ifdef TCP_OFFLOAD 5632 if (is_offload(sc)) { 5633 int i; 5634 char s[4]; 5635 5636 /* 5637 * dev.t4nex.X.toe. 5638 */ 5639 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5640 NULL, "TOE parameters"); 5641 children = SYSCTL_CHILDREN(oid); 5642 5643 sc->tt.cong_algorithm = -1; 5644 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 5645 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 5646 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 5647 "3 = highspeed)"); 5648 5649 sc->tt.sndbuf = 256 * 1024; 5650 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 5651 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 5652 5653 sc->tt.ddp = 0; 5654 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 5655 &sc->tt.ddp, 0, "DDP allowed"); 5656 5657 sc->tt.rx_coalesce = 1; 5658 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 5659 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 5660 5661 sc->tt.tls = 0; 5662 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 5663 &sc->tt.tls, 0, "Inline TLS allowed"); 5664 5665 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 5666 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 5667 "I", "TCP ports that use inline TLS+TOE RX"); 5668 5669 sc->tt.tx_align = 1; 5670 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 5671 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 5672 5673 sc->tt.tx_zcopy = 0; 5674 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 5675 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 5676 "Enable zero-copy aio_write(2)"); 5677 5678 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 5679 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5680 "cop_managed_offloading", CTLFLAG_RW, 5681 &sc->tt.cop_managed_offloading, 0, 5682 "COP (Connection Offload Policy) controls all TOE offload"); 5683 5684 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 5685 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 5686 "TP timer tick (us)"); 5687 5688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 5689 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 5690 "TCP timestamp tick (us)"); 5691 5692 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 5693 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 5694 "DACK tick (us)"); 5695 5696 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 5697 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 5698 "IU", "DACK timer (us)"); 5699 5700 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 5701 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 5702 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 5703 5704 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 5705 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 5706 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 5707 5708 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 5709 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 5710 sysctl_tp_timer, "LU", "Persist timer min (us)"); 5711 5712 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 5713 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 5714 sysctl_tp_timer, "LU", "Persist timer max (us)"); 5715 5716 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 5717 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 5718 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 5719 5720 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 5721 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 5722 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 5723 5724 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 5725 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 5726 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 5727 5728 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 5729 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 5730 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 5731 5732 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 5733 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 5734 sysctl_tp_shift_cnt, "IU", 5735 "Number of SYN retransmissions before abort"); 5736 5737 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 5738 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 5739 sysctl_tp_shift_cnt, "IU", 5740 "Number of retransmissions before abort"); 5741 5742 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 5743 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 5744 sysctl_tp_shift_cnt, "IU", 5745 "Number of keepalive probes before abort"); 5746 5747 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 5748 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 5749 children = SYSCTL_CHILDREN(oid); 5750 for (i = 0; i < 16; i++) { 5751 snprintf(s, sizeof(s), "%u", i); 5752 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 5753 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 5754 "IU", "TOE retransmit backoff"); 5755 } 5756 } 5757 #endif 5758 } 5759 5760 void 5761 vi_sysctls(struct vi_info *vi) 5762 { 5763 struct sysctl_ctx_list *ctx; 5764 struct sysctl_oid *oid; 5765 struct sysctl_oid_list *children; 5766 5767 ctx = device_get_sysctl_ctx(vi->dev); 5768 5769 /* 5770 * dev.v?(cxgbe|cxl).X. 5771 */ 5772 oid = device_get_sysctl_tree(vi->dev); 5773 children = SYSCTL_CHILDREN(oid); 5774 5775 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 5776 vi->viid, "VI identifer"); 5777 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 5778 &vi->nrxq, 0, "# of rx queues"); 5779 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 5780 &vi->ntxq, 0, "# of tx queues"); 5781 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 5782 &vi->first_rxq, 0, "index of first rx queue"); 5783 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 5784 &vi->first_txq, 0, "index of first tx queue"); 5785 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 5786 vi->rss_size, "size of RSS indirection table"); 5787 5788 if (IS_MAIN_VI(vi)) { 5789 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 5790 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 5791 "Reserve queue 0 for non-flowid packets"); 5792 } 5793 5794 #ifdef TCP_OFFLOAD 5795 if (vi->nofldrxq != 0) { 5796 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 5797 &vi->nofldrxq, 0, 5798 "# of rx queues for offloaded TCP connections"); 5799 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 5800 &vi->nofldtxq, 0, 5801 "# of tx queues for offloaded TCP connections"); 5802 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 5803 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 5804 "index of first TOE rx queue"); 5805 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 5806 CTLFLAG_RD, &vi->first_ofld_txq, 0, 5807 "index of first TOE tx queue"); 5808 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 5809 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5810 sysctl_holdoff_tmr_idx_ofld, "I", 5811 "holdoff timer index for TOE queues"); 5812 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 5813 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5814 sysctl_holdoff_pktc_idx_ofld, "I", 5815 "holdoff packet counter index for TOE queues"); 5816 } 5817 #endif 5818 #ifdef DEV_NETMAP 5819 if (vi->nnmrxq != 0) { 5820 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 5821 &vi->nnmrxq, 0, "# of netmap rx queues"); 5822 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 5823 &vi->nnmtxq, 0, "# of netmap tx queues"); 5824 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 5825 CTLFLAG_RD, &vi->first_nm_rxq, 0, 5826 "index of first netmap rx queue"); 5827 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 5828 CTLFLAG_RD, &vi->first_nm_txq, 0, 5829 "index of first netmap tx queue"); 5830 } 5831 #endif 5832 5833 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 5834 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 5835 "holdoff timer index"); 5836 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 5837 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 5838 "holdoff packet counter index"); 5839 5840 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 5841 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 5842 "rx queue size"); 5843 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 5844 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 5845 "tx queue size"); 5846 } 5847 5848 static void 5849 cxgbe_sysctls(struct port_info *pi) 5850 { 5851 struct sysctl_ctx_list *ctx; 5852 struct sysctl_oid *oid; 5853 struct sysctl_oid_list *children, *children2; 5854 struct adapter *sc = pi->adapter; 5855 int i; 5856 char name[16]; 5857 5858 ctx = device_get_sysctl_ctx(pi->dev); 5859 5860 /* 5861 * dev.cxgbe.X. 5862 */ 5863 oid = device_get_sysctl_tree(pi->dev); 5864 children = SYSCTL_CHILDREN(oid); 5865 5866 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 5867 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 5868 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 5869 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 5870 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 5871 "PHY temperature (in Celsius)"); 5872 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 5873 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 5874 "PHY firmware version"); 5875 } 5876 5877 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 5878 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 5879 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)"); 5880 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 5881 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 5882 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 5883 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 5884 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 5885 "autonegotiation (-1 = not supported)"); 5886 5887 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 5888 port_top_speed(pi), "max speed (in Gbps)"); 5889 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 5890 pi->mps_bg_map, "MPS buffer group map"); 5891 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 5892 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 5893 5894 if (sc->flags & IS_VF) 5895 return; 5896 5897 /* 5898 * dev.(cxgbe|cxl).X.tc. 5899 */ 5900 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 5901 "Tx scheduler traffic classes (cl_rl)"); 5902 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 5903 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 5904 5905 snprintf(name, sizeof(name), "%d", i); 5906 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 5907 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 5908 "traffic class")); 5909 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD, 5910 &tc->flags, 0, "flags"); 5911 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 5912 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 5913 #ifdef SBUF_DRAIN 5914 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 5915 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 5916 sysctl_tc_params, "A", "traffic class parameters"); 5917 #endif 5918 } 5919 5920 /* 5921 * dev.cxgbe.X.stats. 5922 */ 5923 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 5924 NULL, "port statistics"); 5925 children = SYSCTL_CHILDREN(oid); 5926 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 5927 &pi->tx_parse_error, 0, 5928 "# of tx packets with invalid length or # of segments"); 5929 5930 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 5931 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 5932 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 5933 sysctl_handle_t4_reg64, "QU", desc) 5934 5935 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 5936 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 5937 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 5938 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 5939 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 5940 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 5941 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 5942 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 5943 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 5944 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 5945 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 5946 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 5947 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 5948 "# of tx frames in this range", 5949 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 5950 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 5951 "# of tx frames in this range", 5952 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 5953 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 5954 "# of tx frames in this range", 5955 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 5956 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 5957 "# of tx frames in this range", 5958 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 5959 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 5960 "# of tx frames in this range", 5961 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 5962 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 5963 "# of tx frames in this range", 5964 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 5965 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 5966 "# of tx frames in this range", 5967 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 5968 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 5969 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 5970 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 5971 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 5972 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 5973 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 5974 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 5975 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 5976 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 5977 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 5978 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 5979 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 5980 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 5981 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 5982 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 5983 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 5984 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 5985 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 5986 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 5987 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 5988 5989 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 5990 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 5991 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 5992 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 5993 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 5994 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 5995 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 5996 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 5997 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 5998 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 5999 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 6000 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 6001 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 6002 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 6003 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 6004 "# of frames received with bad FCS", 6005 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 6006 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 6007 "# of frames received with length error", 6008 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 6009 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 6010 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 6011 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 6012 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 6013 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 6014 "# of rx frames in this range", 6015 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 6016 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 6017 "# of rx frames in this range", 6018 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 6019 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 6020 "# of rx frames in this range", 6021 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 6022 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 6023 "# of rx frames in this range", 6024 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 6025 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 6026 "# of rx frames in this range", 6027 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 6028 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 6029 "# of rx frames in this range", 6030 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 6031 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 6032 "# of rx frames in this range", 6033 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 6034 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 6035 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 6036 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 6037 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 6038 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 6039 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 6040 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 6041 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 6042 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6043 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6044 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6045 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6046 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6047 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6048 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6049 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6050 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6051 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6052 6053 #undef SYSCTL_ADD_T4_REG64 6054 6055 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6056 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6057 &pi->stats.name, desc) 6058 6059 /* We get these from port_stats and they may be stale by up to 1s */ 6060 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6061 "# drops due to buffer-group 0 overflows"); 6062 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6063 "# drops due to buffer-group 1 overflows"); 6064 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6065 "# drops due to buffer-group 2 overflows"); 6066 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6067 "# drops due to buffer-group 3 overflows"); 6068 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6069 "# of buffer-group 0 truncated packets"); 6070 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6071 "# of buffer-group 1 truncated packets"); 6072 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6073 "# of buffer-group 2 truncated packets"); 6074 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6075 "# of buffer-group 3 truncated packets"); 6076 6077 #undef SYSCTL_ADD_T4_PORTSTAT 6078 6079 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6080 CTLFLAG_RD, &pi->tx_tls_records, 6081 "# of TLS records transmitted"); 6082 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6083 CTLFLAG_RD, &pi->tx_tls_octets, 6084 "# of payload octets in transmitted TLS records"); 6085 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6086 CTLFLAG_RD, &pi->rx_tls_records, 6087 "# of TLS records received"); 6088 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6089 CTLFLAG_RD, &pi->rx_tls_octets, 6090 "# of payload octets in received TLS records"); 6091 } 6092 6093 static int 6094 sysctl_int_array(SYSCTL_HANDLER_ARGS) 6095 { 6096 int rc, *i, space = 0; 6097 struct sbuf sb; 6098 6099 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6100 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6101 if (space) 6102 sbuf_printf(&sb, " "); 6103 sbuf_printf(&sb, "%d", *i); 6104 space = 1; 6105 } 6106 rc = sbuf_finish(&sb); 6107 sbuf_delete(&sb); 6108 return (rc); 6109 } 6110 6111 static int 6112 sysctl_bitfield(SYSCTL_HANDLER_ARGS) 6113 { 6114 int rc; 6115 struct sbuf *sb; 6116 6117 rc = sysctl_wire_old_buffer(req, 0); 6118 if (rc != 0) 6119 return(rc); 6120 6121 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6122 if (sb == NULL) 6123 return (ENOMEM); 6124 6125 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 6126 rc = sbuf_finish(sb); 6127 sbuf_delete(sb); 6128 6129 return (rc); 6130 } 6131 6132 static int 6133 sysctl_btphy(SYSCTL_HANDLER_ARGS) 6134 { 6135 struct port_info *pi = arg1; 6136 int op = arg2; 6137 struct adapter *sc = pi->adapter; 6138 u_int v; 6139 int rc; 6140 6141 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6142 if (rc) 6143 return (rc); 6144 /* XXX: magic numbers */ 6145 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6146 &v); 6147 end_synchronized_op(sc, 0); 6148 if (rc) 6149 return (rc); 6150 if (op == 0) 6151 v /= 256; 6152 6153 rc = sysctl_handle_int(oidp, &v, 0, req); 6154 return (rc); 6155 } 6156 6157 static int 6158 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6159 { 6160 struct vi_info *vi = arg1; 6161 int rc, val; 6162 6163 val = vi->rsrv_noflowq; 6164 rc = sysctl_handle_int(oidp, &val, 0, req); 6165 if (rc != 0 || req->newptr == NULL) 6166 return (rc); 6167 6168 if ((val >= 1) && (vi->ntxq > 1)) 6169 vi->rsrv_noflowq = 1; 6170 else 6171 vi->rsrv_noflowq = 0; 6172 6173 return (rc); 6174 } 6175 6176 static int 6177 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6178 { 6179 struct vi_info *vi = arg1; 6180 struct adapter *sc = vi->pi->adapter; 6181 int idx, rc, i; 6182 struct sge_rxq *rxq; 6183 uint8_t v; 6184 6185 idx = vi->tmr_idx; 6186 6187 rc = sysctl_handle_int(oidp, &idx, 0, req); 6188 if (rc != 0 || req->newptr == NULL) 6189 return (rc); 6190 6191 if (idx < 0 || idx >= SGE_NTIMERS) 6192 return (EINVAL); 6193 6194 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6195 "t4tmr"); 6196 if (rc) 6197 return (rc); 6198 6199 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6200 for_each_rxq(vi, i, rxq) { 6201 #ifdef atomic_store_rel_8 6202 atomic_store_rel_8(&rxq->iq.intr_params, v); 6203 #else 6204 rxq->iq.intr_params = v; 6205 #endif 6206 } 6207 vi->tmr_idx = idx; 6208 6209 end_synchronized_op(sc, LOCK_HELD); 6210 return (0); 6211 } 6212 6213 static int 6214 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6215 { 6216 struct vi_info *vi = arg1; 6217 struct adapter *sc = vi->pi->adapter; 6218 int idx, rc; 6219 6220 idx = vi->pktc_idx; 6221 6222 rc = sysctl_handle_int(oidp, &idx, 0, req); 6223 if (rc != 0 || req->newptr == NULL) 6224 return (rc); 6225 6226 if (idx < -1 || idx >= SGE_NCOUNTERS) 6227 return (EINVAL); 6228 6229 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6230 "t4pktc"); 6231 if (rc) 6232 return (rc); 6233 6234 if (vi->flags & VI_INIT_DONE) 6235 rc = EBUSY; /* cannot be changed once the queues are created */ 6236 else 6237 vi->pktc_idx = idx; 6238 6239 end_synchronized_op(sc, LOCK_HELD); 6240 return (rc); 6241 } 6242 6243 static int 6244 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6245 { 6246 struct vi_info *vi = arg1; 6247 struct adapter *sc = vi->pi->adapter; 6248 int qsize, rc; 6249 6250 qsize = vi->qsize_rxq; 6251 6252 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6253 if (rc != 0 || req->newptr == NULL) 6254 return (rc); 6255 6256 if (qsize < 128 || (qsize & 7)) 6257 return (EINVAL); 6258 6259 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6260 "t4rxqs"); 6261 if (rc) 6262 return (rc); 6263 6264 if (vi->flags & VI_INIT_DONE) 6265 rc = EBUSY; /* cannot be changed once the queues are created */ 6266 else 6267 vi->qsize_rxq = qsize; 6268 6269 end_synchronized_op(sc, LOCK_HELD); 6270 return (rc); 6271 } 6272 6273 static int 6274 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6275 { 6276 struct vi_info *vi = arg1; 6277 struct adapter *sc = vi->pi->adapter; 6278 int qsize, rc; 6279 6280 qsize = vi->qsize_txq; 6281 6282 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6283 if (rc != 0 || req->newptr == NULL) 6284 return (rc); 6285 6286 if (qsize < 128 || qsize > 65536) 6287 return (EINVAL); 6288 6289 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6290 "t4txqs"); 6291 if (rc) 6292 return (rc); 6293 6294 if (vi->flags & VI_INIT_DONE) 6295 rc = EBUSY; /* cannot be changed once the queues are created */ 6296 else 6297 vi->qsize_txq = qsize; 6298 6299 end_synchronized_op(sc, LOCK_HELD); 6300 return (rc); 6301 } 6302 6303 static int 6304 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6305 { 6306 struct port_info *pi = arg1; 6307 struct adapter *sc = pi->adapter; 6308 struct link_config *lc = &pi->link_cfg; 6309 int rc; 6310 6311 if (req->newptr == NULL) { 6312 struct sbuf *sb; 6313 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX"; 6314 6315 rc = sysctl_wire_old_buffer(req, 0); 6316 if (rc != 0) 6317 return(rc); 6318 6319 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6320 if (sb == NULL) 6321 return (ENOMEM); 6322 6323 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits); 6324 rc = sbuf_finish(sb); 6325 sbuf_delete(sb); 6326 } else { 6327 char s[2]; 6328 int n; 6329 6330 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX)); 6331 s[1] = 0; 6332 6333 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6334 if (rc != 0) 6335 return(rc); 6336 6337 if (s[1] != 0) 6338 return (EINVAL); 6339 if (s[0] < '0' || s[0] > '9') 6340 return (EINVAL); /* not a number */ 6341 n = s[0] - '0'; 6342 if (n & ~(PAUSE_TX | PAUSE_RX)) 6343 return (EINVAL); /* some other bit is set too */ 6344 6345 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6346 "t4PAUSE"); 6347 if (rc) 6348 return (rc); 6349 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) { 6350 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 6351 lc->requested_fc |= n; 6352 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6353 if (rc == 0) { 6354 lc->fc = lc->requested_fc; 6355 } 6356 } 6357 end_synchronized_op(sc, 0); 6358 } 6359 6360 return (rc); 6361 } 6362 6363 static int 6364 sysctl_fec(SYSCTL_HANDLER_ARGS) 6365 { 6366 struct port_info *pi = arg1; 6367 struct adapter *sc = pi->adapter; 6368 struct link_config *lc = &pi->link_cfg; 6369 int rc; 6370 6371 if (req->newptr == NULL) { 6372 struct sbuf *sb; 6373 static char *bits = "\20\1RS\2BASER_RS\3RESERVED"; 6374 6375 rc = sysctl_wire_old_buffer(req, 0); 6376 if (rc != 0) 6377 return(rc); 6378 6379 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6380 if (sb == NULL) 6381 return (ENOMEM); 6382 6383 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits); 6384 rc = sbuf_finish(sb); 6385 sbuf_delete(sb); 6386 } else { 6387 char s[2]; 6388 int n; 6389 6390 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC); 6391 s[1] = 0; 6392 6393 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6394 if (rc != 0) 6395 return(rc); 6396 6397 if (s[1] != 0) 6398 return (EINVAL); 6399 if (s[0] < '0' || s[0] > '9') 6400 return (EINVAL); /* not a number */ 6401 n = s[0] - '0'; 6402 if (n & ~M_FW_PORT_CAP_FEC) 6403 return (EINVAL); /* some other bit is set too */ 6404 6405 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6406 "t4fec"); 6407 if (rc) 6408 return (rc); 6409 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) { 6410 lc->requested_fec = n & 6411 G_FW_PORT_CAP_FEC(lc->supported); 6412 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6413 if (rc == 0) { 6414 lc->fec = lc->requested_fec; 6415 } 6416 } 6417 end_synchronized_op(sc, 0); 6418 } 6419 6420 return (rc); 6421 } 6422 6423 static int 6424 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 6425 { 6426 struct port_info *pi = arg1; 6427 struct adapter *sc = pi->adapter; 6428 struct link_config *lc = &pi->link_cfg; 6429 int rc, val, old; 6430 6431 if (lc->supported & FW_PORT_CAP_ANEG) 6432 val = lc->requested_aneg == AUTONEG_ENABLE ? 1 : 0; 6433 else 6434 val = -1; 6435 rc = sysctl_handle_int(oidp, &val, 0, req); 6436 if (rc != 0 || req->newptr == NULL) 6437 return (rc); 6438 if ((lc->supported & FW_PORT_CAP_ANEG) == 0) 6439 return (ENOTSUP); 6440 6441 if (val == 0) 6442 val = AUTONEG_DISABLE; 6443 else if (val == 1) 6444 val = AUTONEG_ENABLE; 6445 else 6446 return (EINVAL); 6447 if (lc->requested_aneg == val) 6448 return (0); /* no change */ 6449 6450 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6451 "t4aneg"); 6452 if (rc) 6453 return (rc); 6454 old = lc->requested_aneg; 6455 lc->requested_aneg = val; 6456 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6457 if (rc != 0) 6458 lc->requested_aneg = old; 6459 end_synchronized_op(sc, 0); 6460 return (rc); 6461 } 6462 6463 static int 6464 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 6465 { 6466 struct adapter *sc = arg1; 6467 int reg = arg2; 6468 uint64_t val; 6469 6470 val = t4_read_reg64(sc, reg); 6471 6472 return (sysctl_handle_64(oidp, &val, 0, req)); 6473 } 6474 6475 static int 6476 sysctl_temperature(SYSCTL_HANDLER_ARGS) 6477 { 6478 struct adapter *sc = arg1; 6479 int rc, t; 6480 uint32_t param, val; 6481 6482 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 6483 if (rc) 6484 return (rc); 6485 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6486 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 6487 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 6488 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6489 end_synchronized_op(sc, 0); 6490 if (rc) 6491 return (rc); 6492 6493 /* unknown is returned as 0 but we display -1 in that case */ 6494 t = val == 0 ? -1 : val; 6495 6496 rc = sysctl_handle_int(oidp, &t, 0, req); 6497 return (rc); 6498 } 6499 6500 #ifdef SBUF_DRAIN 6501 static int 6502 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 6503 { 6504 struct adapter *sc = arg1; 6505 struct sbuf *sb; 6506 int rc, i; 6507 uint16_t incr[NMTUS][NCCTRL_WIN]; 6508 static const char *dec_fac[] = { 6509 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 6510 "0.9375" 6511 }; 6512 6513 rc = sysctl_wire_old_buffer(req, 0); 6514 if (rc != 0) 6515 return (rc); 6516 6517 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6518 if (sb == NULL) 6519 return (ENOMEM); 6520 6521 t4_read_cong_tbl(sc, incr); 6522 6523 for (i = 0; i < NCCTRL_WIN; ++i) { 6524 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 6525 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 6526 incr[5][i], incr[6][i], incr[7][i]); 6527 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 6528 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 6529 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 6530 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 6531 } 6532 6533 rc = sbuf_finish(sb); 6534 sbuf_delete(sb); 6535 6536 return (rc); 6537 } 6538 6539 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 6540 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 6541 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 6542 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 6543 }; 6544 6545 static int 6546 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 6547 { 6548 struct adapter *sc = arg1; 6549 struct sbuf *sb; 6550 int rc, i, n, qid = arg2; 6551 uint32_t *buf, *p; 6552 char *qtype; 6553 u_int cim_num_obq = sc->chip_params->cim_num_obq; 6554 6555 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 6556 ("%s: bad qid %d\n", __func__, qid)); 6557 6558 if (qid < CIM_NUM_IBQ) { 6559 /* inbound queue */ 6560 qtype = "IBQ"; 6561 n = 4 * CIM_IBQ_SIZE; 6562 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6563 rc = t4_read_cim_ibq(sc, qid, buf, n); 6564 } else { 6565 /* outbound queue */ 6566 qtype = "OBQ"; 6567 qid -= CIM_NUM_IBQ; 6568 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 6569 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6570 rc = t4_read_cim_obq(sc, qid, buf, n); 6571 } 6572 6573 if (rc < 0) { 6574 rc = -rc; 6575 goto done; 6576 } 6577 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 6578 6579 rc = sysctl_wire_old_buffer(req, 0); 6580 if (rc != 0) 6581 goto done; 6582 6583 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6584 if (sb == NULL) { 6585 rc = ENOMEM; 6586 goto done; 6587 } 6588 6589 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 6590 for (i = 0, p = buf; i < n; i += 16, p += 4) 6591 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 6592 p[2], p[3]); 6593 6594 rc = sbuf_finish(sb); 6595 sbuf_delete(sb); 6596 done: 6597 free(buf, M_CXGBE); 6598 return (rc); 6599 } 6600 6601 static int 6602 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 6603 { 6604 struct adapter *sc = arg1; 6605 u_int cfg; 6606 struct sbuf *sb; 6607 uint32_t *buf, *p; 6608 int rc; 6609 6610 MPASS(chip_id(sc) <= CHELSIO_T5); 6611 6612 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6613 if (rc != 0) 6614 return (rc); 6615 6616 rc = sysctl_wire_old_buffer(req, 0); 6617 if (rc != 0) 6618 return (rc); 6619 6620 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6621 if (sb == NULL) 6622 return (ENOMEM); 6623 6624 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6625 M_ZERO | M_WAITOK); 6626 6627 rc = -t4_cim_read_la(sc, buf, NULL); 6628 if (rc != 0) 6629 goto done; 6630 6631 sbuf_printf(sb, "Status Data PC%s", 6632 cfg & F_UPDBGLACAPTPCONLY ? "" : 6633 " LS0Stat LS0Addr LS0Data"); 6634 6635 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 6636 if (cfg & F_UPDBGLACAPTPCONLY) { 6637 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 6638 p[6], p[7]); 6639 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 6640 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 6641 p[4] & 0xff, p[5] >> 8); 6642 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 6643 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6644 p[1] & 0xf, p[2] >> 4); 6645 } else { 6646 sbuf_printf(sb, 6647 "\n %02x %x%07x %x%07x %08x %08x " 6648 "%08x%08x%08x%08x", 6649 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6650 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 6651 p[6], p[7]); 6652 } 6653 } 6654 6655 rc = sbuf_finish(sb); 6656 sbuf_delete(sb); 6657 done: 6658 free(buf, M_CXGBE); 6659 return (rc); 6660 } 6661 6662 static int 6663 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 6664 { 6665 struct adapter *sc = arg1; 6666 u_int cfg; 6667 struct sbuf *sb; 6668 uint32_t *buf, *p; 6669 int rc; 6670 6671 MPASS(chip_id(sc) > CHELSIO_T5); 6672 6673 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6674 if (rc != 0) 6675 return (rc); 6676 6677 rc = sysctl_wire_old_buffer(req, 0); 6678 if (rc != 0) 6679 return (rc); 6680 6681 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6682 if (sb == NULL) 6683 return (ENOMEM); 6684 6685 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6686 M_ZERO | M_WAITOK); 6687 6688 rc = -t4_cim_read_la(sc, buf, NULL); 6689 if (rc != 0) 6690 goto done; 6691 6692 sbuf_printf(sb, "Status Inst Data PC%s", 6693 cfg & F_UPDBGLACAPTPCONLY ? "" : 6694 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 6695 6696 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 6697 if (cfg & F_UPDBGLACAPTPCONLY) { 6698 sbuf_printf(sb, "\n %02x %08x %08x %08x", 6699 p[3] & 0xff, p[2], p[1], p[0]); 6700 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 6701 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 6702 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 6703 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 6704 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 6705 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 6706 p[6] >> 16); 6707 } else { 6708 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 6709 "%08x %08x %08x %08x %08x %08x", 6710 (p[9] >> 16) & 0xff, 6711 p[9] & 0xffff, p[8] >> 16, 6712 p[8] & 0xffff, p[7] >> 16, 6713 p[7] & 0xffff, p[6] >> 16, 6714 p[2], p[1], p[0], p[5], p[4], p[3]); 6715 } 6716 } 6717 6718 rc = sbuf_finish(sb); 6719 sbuf_delete(sb); 6720 done: 6721 free(buf, M_CXGBE); 6722 return (rc); 6723 } 6724 6725 static int 6726 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 6727 { 6728 struct adapter *sc = arg1; 6729 u_int i; 6730 struct sbuf *sb; 6731 uint32_t *buf, *p; 6732 int rc; 6733 6734 rc = sysctl_wire_old_buffer(req, 0); 6735 if (rc != 0) 6736 return (rc); 6737 6738 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6739 if (sb == NULL) 6740 return (ENOMEM); 6741 6742 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 6743 M_ZERO | M_WAITOK); 6744 6745 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 6746 p = buf; 6747 6748 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6749 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 6750 p[1], p[0]); 6751 } 6752 6753 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 6754 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6755 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 6756 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 6757 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 6758 (p[1] >> 2) | ((p[2] & 3) << 30), 6759 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 6760 p[0] & 1); 6761 } 6762 6763 rc = sbuf_finish(sb); 6764 sbuf_delete(sb); 6765 free(buf, M_CXGBE); 6766 return (rc); 6767 } 6768 6769 static int 6770 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 6771 { 6772 struct adapter *sc = arg1; 6773 u_int i; 6774 struct sbuf *sb; 6775 uint32_t *buf, *p; 6776 int rc; 6777 6778 rc = sysctl_wire_old_buffer(req, 0); 6779 if (rc != 0) 6780 return (rc); 6781 6782 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6783 if (sb == NULL) 6784 return (ENOMEM); 6785 6786 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 6787 M_ZERO | M_WAITOK); 6788 6789 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 6790 p = buf; 6791 6792 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 6793 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6794 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 6795 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 6796 p[4], p[3], p[2], p[1], p[0]); 6797 } 6798 6799 sbuf_printf(sb, "\n\nCntl ID Data"); 6800 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6801 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 6802 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 6803 } 6804 6805 rc = sbuf_finish(sb); 6806 sbuf_delete(sb); 6807 free(buf, M_CXGBE); 6808 return (rc); 6809 } 6810 6811 static int 6812 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 6813 { 6814 struct adapter *sc = arg1; 6815 struct sbuf *sb; 6816 int rc, i; 6817 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6818 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6819 uint16_t thres[CIM_NUM_IBQ]; 6820 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 6821 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 6822 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 6823 6824 cim_num_obq = sc->chip_params->cim_num_obq; 6825 if (is_t4(sc)) { 6826 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 6827 obq_rdaddr = A_UP_OBQ_0_REALADDR; 6828 } else { 6829 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 6830 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 6831 } 6832 nq = CIM_NUM_IBQ + cim_num_obq; 6833 6834 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 6835 if (rc == 0) 6836 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 6837 if (rc != 0) 6838 return (rc); 6839 6840 t4_read_cimq_cfg(sc, base, size, thres); 6841 6842 rc = sysctl_wire_old_buffer(req, 0); 6843 if (rc != 0) 6844 return (rc); 6845 6846 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6847 if (sb == NULL) 6848 return (ENOMEM); 6849 6850 sbuf_printf(sb, 6851 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 6852 6853 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 6854 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 6855 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 6856 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6857 G_QUEREMFLITS(p[2]) * 16); 6858 for ( ; i < nq; i++, p += 4, wr += 2) 6859 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 6860 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 6861 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6862 G_QUEREMFLITS(p[2]) * 16); 6863 6864 rc = sbuf_finish(sb); 6865 sbuf_delete(sb); 6866 6867 return (rc); 6868 } 6869 6870 static int 6871 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 6872 { 6873 struct adapter *sc = arg1; 6874 struct sbuf *sb; 6875 int rc; 6876 struct tp_cpl_stats stats; 6877 6878 rc = sysctl_wire_old_buffer(req, 0); 6879 if (rc != 0) 6880 return (rc); 6881 6882 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6883 if (sb == NULL) 6884 return (ENOMEM); 6885 6886 mtx_lock(&sc->reg_lock); 6887 t4_tp_get_cpl_stats(sc, &stats, 0); 6888 mtx_unlock(&sc->reg_lock); 6889 6890 if (sc->chip_params->nchan > 2) { 6891 sbuf_printf(sb, " channel 0 channel 1" 6892 " channel 2 channel 3"); 6893 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 6894 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 6895 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 6896 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 6897 } else { 6898 sbuf_printf(sb, " channel 0 channel 1"); 6899 sbuf_printf(sb, "\nCPL requests: %10u %10u", 6900 stats.req[0], stats.req[1]); 6901 sbuf_printf(sb, "\nCPL responses: %10u %10u", 6902 stats.rsp[0], stats.rsp[1]); 6903 } 6904 6905 rc = sbuf_finish(sb); 6906 sbuf_delete(sb); 6907 6908 return (rc); 6909 } 6910 6911 static int 6912 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 6913 { 6914 struct adapter *sc = arg1; 6915 struct sbuf *sb; 6916 int rc; 6917 struct tp_usm_stats stats; 6918 6919 rc = sysctl_wire_old_buffer(req, 0); 6920 if (rc != 0) 6921 return(rc); 6922 6923 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6924 if (sb == NULL) 6925 return (ENOMEM); 6926 6927 t4_get_usm_stats(sc, &stats, 1); 6928 6929 sbuf_printf(sb, "Frames: %u\n", stats.frames); 6930 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 6931 sbuf_printf(sb, "Drops: %u", stats.drops); 6932 6933 rc = sbuf_finish(sb); 6934 sbuf_delete(sb); 6935 6936 return (rc); 6937 } 6938 6939 static const char * const devlog_level_strings[] = { 6940 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 6941 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 6942 [FW_DEVLOG_LEVEL_ERR] = "ERR", 6943 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 6944 [FW_DEVLOG_LEVEL_INFO] = "INFO", 6945 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 6946 }; 6947 6948 static const char * const devlog_facility_strings[] = { 6949 [FW_DEVLOG_FACILITY_CORE] = "CORE", 6950 [FW_DEVLOG_FACILITY_CF] = "CF", 6951 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 6952 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 6953 [FW_DEVLOG_FACILITY_RES] = "RES", 6954 [FW_DEVLOG_FACILITY_HW] = "HW", 6955 [FW_DEVLOG_FACILITY_FLR] = "FLR", 6956 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 6957 [FW_DEVLOG_FACILITY_PHY] = "PHY", 6958 [FW_DEVLOG_FACILITY_MAC] = "MAC", 6959 [FW_DEVLOG_FACILITY_PORT] = "PORT", 6960 [FW_DEVLOG_FACILITY_VI] = "VI", 6961 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 6962 [FW_DEVLOG_FACILITY_ACL] = "ACL", 6963 [FW_DEVLOG_FACILITY_TM] = "TM", 6964 [FW_DEVLOG_FACILITY_QFC] = "QFC", 6965 [FW_DEVLOG_FACILITY_DCB] = "DCB", 6966 [FW_DEVLOG_FACILITY_ETH] = "ETH", 6967 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 6968 [FW_DEVLOG_FACILITY_RI] = "RI", 6969 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 6970 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 6971 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 6972 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 6973 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 6974 }; 6975 6976 static int 6977 sysctl_devlog(SYSCTL_HANDLER_ARGS) 6978 { 6979 struct adapter *sc = arg1; 6980 struct devlog_params *dparams = &sc->params.devlog; 6981 struct fw_devlog_e *buf, *e; 6982 int i, j, rc, nentries, first = 0; 6983 struct sbuf *sb; 6984 uint64_t ftstamp = UINT64_MAX; 6985 6986 if (dparams->addr == 0) 6987 return (ENXIO); 6988 6989 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 6990 if (buf == NULL) 6991 return (ENOMEM); 6992 6993 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 6994 if (rc != 0) 6995 goto done; 6996 6997 nentries = dparams->size / sizeof(struct fw_devlog_e); 6998 for (i = 0; i < nentries; i++) { 6999 e = &buf[i]; 7000 7001 if (e->timestamp == 0) 7002 break; /* end */ 7003 7004 e->timestamp = be64toh(e->timestamp); 7005 e->seqno = be32toh(e->seqno); 7006 for (j = 0; j < 8; j++) 7007 e->params[j] = be32toh(e->params[j]); 7008 7009 if (e->timestamp < ftstamp) { 7010 ftstamp = e->timestamp; 7011 first = i; 7012 } 7013 } 7014 7015 if (buf[first].timestamp == 0) 7016 goto done; /* nothing in the log */ 7017 7018 rc = sysctl_wire_old_buffer(req, 0); 7019 if (rc != 0) 7020 goto done; 7021 7022 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7023 if (sb == NULL) { 7024 rc = ENOMEM; 7025 goto done; 7026 } 7027 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 7028 "Seq#", "Tstamp", "Level", "Facility", "Message"); 7029 7030 i = first; 7031 do { 7032 e = &buf[i]; 7033 if (e->timestamp == 0) 7034 break; /* end */ 7035 7036 sbuf_printf(sb, "%10d %15ju %8s %8s ", 7037 e->seqno, e->timestamp, 7038 (e->level < nitems(devlog_level_strings) ? 7039 devlog_level_strings[e->level] : "UNKNOWN"), 7040 (e->facility < nitems(devlog_facility_strings) ? 7041 devlog_facility_strings[e->facility] : "UNKNOWN")); 7042 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7043 e->params[2], e->params[3], e->params[4], 7044 e->params[5], e->params[6], e->params[7]); 7045 7046 if (++i == nentries) 7047 i = 0; 7048 } while (i != first); 7049 7050 rc = sbuf_finish(sb); 7051 sbuf_delete(sb); 7052 done: 7053 free(buf, M_CXGBE); 7054 return (rc); 7055 } 7056 7057 static int 7058 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7059 { 7060 struct adapter *sc = arg1; 7061 struct sbuf *sb; 7062 int rc; 7063 struct tp_fcoe_stats stats[MAX_NCHAN]; 7064 int i, nchan = sc->chip_params->nchan; 7065 7066 rc = sysctl_wire_old_buffer(req, 0); 7067 if (rc != 0) 7068 return (rc); 7069 7070 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7071 if (sb == NULL) 7072 return (ENOMEM); 7073 7074 for (i = 0; i < nchan; i++) 7075 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7076 7077 if (nchan > 2) { 7078 sbuf_printf(sb, " channel 0 channel 1" 7079 " channel 2 channel 3"); 7080 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7081 stats[0].octets_ddp, stats[1].octets_ddp, 7082 stats[2].octets_ddp, stats[3].octets_ddp); 7083 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7084 stats[0].frames_ddp, stats[1].frames_ddp, 7085 stats[2].frames_ddp, stats[3].frames_ddp); 7086 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7087 stats[0].frames_drop, stats[1].frames_drop, 7088 stats[2].frames_drop, stats[3].frames_drop); 7089 } else { 7090 sbuf_printf(sb, " channel 0 channel 1"); 7091 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7092 stats[0].octets_ddp, stats[1].octets_ddp); 7093 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7094 stats[0].frames_ddp, stats[1].frames_ddp); 7095 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7096 stats[0].frames_drop, stats[1].frames_drop); 7097 } 7098 7099 rc = sbuf_finish(sb); 7100 sbuf_delete(sb); 7101 7102 return (rc); 7103 } 7104 7105 static int 7106 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7107 { 7108 struct adapter *sc = arg1; 7109 struct sbuf *sb; 7110 int rc, i; 7111 unsigned int map, kbps, ipg, mode; 7112 unsigned int pace_tab[NTX_SCHED]; 7113 7114 rc = sysctl_wire_old_buffer(req, 0); 7115 if (rc != 0) 7116 return (rc); 7117 7118 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7119 if (sb == NULL) 7120 return (ENOMEM); 7121 7122 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7123 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7124 t4_read_pace_tbl(sc, pace_tab); 7125 7126 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7127 "Class IPG (0.1 ns) Flow IPG (us)"); 7128 7129 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7130 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7131 sbuf_printf(sb, "\n %u %-5s %u ", i, 7132 (mode & (1 << i)) ? "flow" : "class", map & 3); 7133 if (kbps) 7134 sbuf_printf(sb, "%9u ", kbps); 7135 else 7136 sbuf_printf(sb, " disabled "); 7137 7138 if (ipg) 7139 sbuf_printf(sb, "%13u ", ipg); 7140 else 7141 sbuf_printf(sb, " disabled "); 7142 7143 if (pace_tab[i]) 7144 sbuf_printf(sb, "%10u", pace_tab[i]); 7145 else 7146 sbuf_printf(sb, " disabled"); 7147 } 7148 7149 rc = sbuf_finish(sb); 7150 sbuf_delete(sb); 7151 7152 return (rc); 7153 } 7154 7155 static int 7156 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7157 { 7158 struct adapter *sc = arg1; 7159 struct sbuf *sb; 7160 int rc, i, j; 7161 uint64_t *p0, *p1; 7162 struct lb_port_stats s[2]; 7163 static const char *stat_name[] = { 7164 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7165 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7166 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7167 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7168 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7169 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7170 "BG2FramesTrunc:", "BG3FramesTrunc:" 7171 }; 7172 7173 rc = sysctl_wire_old_buffer(req, 0); 7174 if (rc != 0) 7175 return (rc); 7176 7177 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7178 if (sb == NULL) 7179 return (ENOMEM); 7180 7181 memset(s, 0, sizeof(s)); 7182 7183 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7184 t4_get_lb_stats(sc, i, &s[0]); 7185 t4_get_lb_stats(sc, i + 1, &s[1]); 7186 7187 p0 = &s[0].octets; 7188 p1 = &s[1].octets; 7189 sbuf_printf(sb, "%s Loopback %u" 7190 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7191 7192 for (j = 0; j < nitems(stat_name); j++) 7193 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7194 *p0++, *p1++); 7195 } 7196 7197 rc = sbuf_finish(sb); 7198 sbuf_delete(sb); 7199 7200 return (rc); 7201 } 7202 7203 static int 7204 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7205 { 7206 int rc = 0; 7207 struct port_info *pi = arg1; 7208 struct link_config *lc = &pi->link_cfg; 7209 struct sbuf *sb; 7210 7211 rc = sysctl_wire_old_buffer(req, 0); 7212 if (rc != 0) 7213 return(rc); 7214 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7215 if (sb == NULL) 7216 return (ENOMEM); 7217 7218 if (lc->link_ok || lc->link_down_rc == 255) 7219 sbuf_printf(sb, "n/a"); 7220 else 7221 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7222 7223 rc = sbuf_finish(sb); 7224 sbuf_delete(sb); 7225 7226 return (rc); 7227 } 7228 7229 struct mem_desc { 7230 unsigned int base; 7231 unsigned int limit; 7232 unsigned int idx; 7233 }; 7234 7235 static int 7236 mem_desc_cmp(const void *a, const void *b) 7237 { 7238 return ((const struct mem_desc *)a)->base - 7239 ((const struct mem_desc *)b)->base; 7240 } 7241 7242 static void 7243 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7244 unsigned int to) 7245 { 7246 unsigned int size; 7247 7248 if (from == to) 7249 return; 7250 7251 size = to - from + 1; 7252 if (size == 0) 7253 return; 7254 7255 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7256 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7257 } 7258 7259 static int 7260 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7261 { 7262 struct adapter *sc = arg1; 7263 struct sbuf *sb; 7264 int rc, i, n; 7265 uint32_t lo, hi, used, alloc; 7266 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 7267 static const char *region[] = { 7268 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 7269 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 7270 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 7271 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 7272 "RQUDP region:", "PBL region:", "TXPBL region:", 7273 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 7274 "On-chip queues:", "TLS keys:", 7275 }; 7276 struct mem_desc avail[4]; 7277 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 7278 struct mem_desc *md = mem; 7279 7280 rc = sysctl_wire_old_buffer(req, 0); 7281 if (rc != 0) 7282 return (rc); 7283 7284 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7285 if (sb == NULL) 7286 return (ENOMEM); 7287 7288 for (i = 0; i < nitems(mem); i++) { 7289 mem[i].limit = 0; 7290 mem[i].idx = i; 7291 } 7292 7293 /* Find and sort the populated memory ranges */ 7294 i = 0; 7295 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 7296 if (lo & F_EDRAM0_ENABLE) { 7297 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 7298 avail[i].base = G_EDRAM0_BASE(hi) << 20; 7299 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 7300 avail[i].idx = 0; 7301 i++; 7302 } 7303 if (lo & F_EDRAM1_ENABLE) { 7304 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 7305 avail[i].base = G_EDRAM1_BASE(hi) << 20; 7306 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 7307 avail[i].idx = 1; 7308 i++; 7309 } 7310 if (lo & F_EXT_MEM_ENABLE) { 7311 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 7312 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 7313 avail[i].limit = avail[i].base + 7314 (G_EXT_MEM_SIZE(hi) << 20); 7315 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 7316 i++; 7317 } 7318 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 7319 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 7320 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 7321 avail[i].limit = avail[i].base + 7322 (G_EXT_MEM1_SIZE(hi) << 20); 7323 avail[i].idx = 4; 7324 i++; 7325 } 7326 if (!i) /* no memory available */ 7327 return 0; 7328 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 7329 7330 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 7331 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 7332 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 7333 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 7334 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 7335 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 7336 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 7337 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 7338 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 7339 7340 /* the next few have explicit upper bounds */ 7341 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 7342 md->limit = md->base - 1 + 7343 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 7344 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 7345 md++; 7346 7347 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 7348 md->limit = md->base - 1 + 7349 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 7350 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 7351 md++; 7352 7353 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7354 if (chip_id(sc) <= CHELSIO_T5) 7355 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 7356 else 7357 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 7358 md->limit = 0; 7359 } else { 7360 md->base = 0; 7361 md->idx = nitems(region); /* hide it */ 7362 } 7363 md++; 7364 7365 #define ulp_region(reg) \ 7366 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 7367 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 7368 7369 ulp_region(RX_ISCSI); 7370 ulp_region(RX_TDDP); 7371 ulp_region(TX_TPT); 7372 ulp_region(RX_STAG); 7373 ulp_region(RX_RQ); 7374 ulp_region(RX_RQUDP); 7375 ulp_region(RX_PBL); 7376 ulp_region(TX_PBL); 7377 #undef ulp_region 7378 7379 md->base = 0; 7380 md->idx = nitems(region); 7381 if (!is_t4(sc)) { 7382 uint32_t size = 0; 7383 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 7384 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 7385 7386 if (is_t5(sc)) { 7387 if (sge_ctrl & F_VFIFO_ENABLE) 7388 size = G_DBVFIFO_SIZE(fifo_size); 7389 } else 7390 size = G_T6_DBVFIFO_SIZE(fifo_size); 7391 7392 if (size) { 7393 md->base = G_BASEADDR(t4_read_reg(sc, 7394 A_SGE_DBVFIFO_BADDR)); 7395 md->limit = md->base + (size << 2) - 1; 7396 } 7397 } 7398 md++; 7399 7400 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 7401 md->limit = 0; 7402 md++; 7403 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 7404 md->limit = 0; 7405 md++; 7406 7407 md->base = sc->vres.ocq.start; 7408 if (sc->vres.ocq.size) 7409 md->limit = md->base + sc->vres.ocq.size - 1; 7410 else 7411 md->idx = nitems(region); /* hide it */ 7412 md++; 7413 7414 md->base = sc->vres.key.start; 7415 if (sc->vres.key.size) 7416 md->limit = md->base + sc->vres.key.size - 1; 7417 else 7418 md->idx = nitems(region); /* hide it */ 7419 md++; 7420 7421 /* add any address-space holes, there can be up to 3 */ 7422 for (n = 0; n < i - 1; n++) 7423 if (avail[n].limit < avail[n + 1].base) 7424 (md++)->base = avail[n].limit; 7425 if (avail[n].limit) 7426 (md++)->base = avail[n].limit; 7427 7428 n = md - mem; 7429 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 7430 7431 for (lo = 0; lo < i; lo++) 7432 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 7433 avail[lo].limit - 1); 7434 7435 sbuf_printf(sb, "\n"); 7436 for (i = 0; i < n; i++) { 7437 if (mem[i].idx >= nitems(region)) 7438 continue; /* skip holes */ 7439 if (!mem[i].limit) 7440 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 7441 mem_region_show(sb, region[mem[i].idx], mem[i].base, 7442 mem[i].limit); 7443 } 7444 7445 sbuf_printf(sb, "\n"); 7446 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 7447 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 7448 mem_region_show(sb, "uP RAM:", lo, hi); 7449 7450 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 7451 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 7452 mem_region_show(sb, "uP Extmem2:", lo, hi); 7453 7454 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 7455 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 7456 G_PMRXMAXPAGE(lo), 7457 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 7458 (lo & F_PMRXNUMCHN) ? 2 : 1); 7459 7460 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 7461 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 7462 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 7463 G_PMTXMAXPAGE(lo), 7464 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 7465 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 7466 sbuf_printf(sb, "%u p-structs\n", 7467 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 7468 7469 for (i = 0; i < 4; i++) { 7470 if (chip_id(sc) > CHELSIO_T5) 7471 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 7472 else 7473 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 7474 if (is_t5(sc)) { 7475 used = G_T5_USED(lo); 7476 alloc = G_T5_ALLOC(lo); 7477 } else { 7478 used = G_USED(lo); 7479 alloc = G_ALLOC(lo); 7480 } 7481 /* For T6 these are MAC buffer groups */ 7482 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 7483 i, used, alloc); 7484 } 7485 for (i = 0; i < sc->chip_params->nchan; i++) { 7486 if (chip_id(sc) > CHELSIO_T5) 7487 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 7488 else 7489 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 7490 if (is_t5(sc)) { 7491 used = G_T5_USED(lo); 7492 alloc = G_T5_ALLOC(lo); 7493 } else { 7494 used = G_USED(lo); 7495 alloc = G_ALLOC(lo); 7496 } 7497 /* For T6 these are MAC buffer groups */ 7498 sbuf_printf(sb, 7499 "\nLoopback %d using %u pages out of %u allocated", 7500 i, used, alloc); 7501 } 7502 7503 rc = sbuf_finish(sb); 7504 sbuf_delete(sb); 7505 7506 return (rc); 7507 } 7508 7509 static inline void 7510 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 7511 { 7512 *mask = x | y; 7513 y = htobe64(y); 7514 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 7515 } 7516 7517 static int 7518 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 7519 { 7520 struct adapter *sc = arg1; 7521 struct sbuf *sb; 7522 int rc, i; 7523 7524 MPASS(chip_id(sc) <= CHELSIO_T5); 7525 7526 rc = sysctl_wire_old_buffer(req, 0); 7527 if (rc != 0) 7528 return (rc); 7529 7530 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7531 if (sb == NULL) 7532 return (ENOMEM); 7533 7534 sbuf_printf(sb, 7535 "Idx Ethernet address Mask Vld Ports PF" 7536 " VF Replication P0 P1 P2 P3 ML"); 7537 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7538 uint64_t tcamx, tcamy, mask; 7539 uint32_t cls_lo, cls_hi; 7540 uint8_t addr[ETHER_ADDR_LEN]; 7541 7542 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 7543 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 7544 if (tcamx & tcamy) 7545 continue; 7546 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7547 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7548 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7549 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 7550 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 7551 addr[3], addr[4], addr[5], (uintmax_t)mask, 7552 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 7553 G_PORTMAP(cls_hi), G_PF(cls_lo), 7554 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 7555 7556 if (cls_lo & F_REPLICATE) { 7557 struct fw_ldst_cmd ldst_cmd; 7558 7559 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7560 ldst_cmd.op_to_addrspace = 7561 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7562 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7563 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7564 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7565 ldst_cmd.u.mps.rplc.fid_idx = 7566 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7567 V_FW_LDST_CMD_IDX(i)); 7568 7569 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7570 "t4mps"); 7571 if (rc) 7572 break; 7573 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7574 sizeof(ldst_cmd), &ldst_cmd); 7575 end_synchronized_op(sc, 0); 7576 7577 if (rc != 0) { 7578 sbuf_printf(sb, "%36d", rc); 7579 rc = 0; 7580 } else { 7581 sbuf_printf(sb, " %08x %08x %08x %08x", 7582 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7583 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7584 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7585 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7586 } 7587 } else 7588 sbuf_printf(sb, "%36s", ""); 7589 7590 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 7591 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 7592 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 7593 } 7594 7595 if (rc) 7596 (void) sbuf_finish(sb); 7597 else 7598 rc = sbuf_finish(sb); 7599 sbuf_delete(sb); 7600 7601 return (rc); 7602 } 7603 7604 static int 7605 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 7606 { 7607 struct adapter *sc = arg1; 7608 struct sbuf *sb; 7609 int rc, i; 7610 7611 MPASS(chip_id(sc) > CHELSIO_T5); 7612 7613 rc = sysctl_wire_old_buffer(req, 0); 7614 if (rc != 0) 7615 return (rc); 7616 7617 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7618 if (sb == NULL) 7619 return (ENOMEM); 7620 7621 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 7622 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 7623 " Replication" 7624 " P0 P1 P2 P3 ML\n"); 7625 7626 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7627 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 7628 uint16_t ivlan; 7629 uint64_t tcamx, tcamy, val, mask; 7630 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 7631 uint8_t addr[ETHER_ADDR_LEN]; 7632 7633 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 7634 if (i < 256) 7635 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 7636 else 7637 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 7638 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7639 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7640 tcamy = G_DMACH(val) << 32; 7641 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7642 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7643 lookup_type = G_DATALKPTYPE(data2); 7644 port_num = G_DATAPORTNUM(data2); 7645 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7646 /* Inner header VNI */ 7647 vniy = ((data2 & F_DATAVIDH2) << 23) | 7648 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7649 dip_hit = data2 & F_DATADIPHIT; 7650 vlan_vld = 0; 7651 } else { 7652 vniy = 0; 7653 dip_hit = 0; 7654 vlan_vld = data2 & F_DATAVIDH2; 7655 ivlan = G_VIDL(val); 7656 } 7657 7658 ctl |= V_CTLXYBITSEL(1); 7659 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7660 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7661 tcamx = G_DMACH(val) << 32; 7662 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7663 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7664 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7665 /* Inner header VNI mask */ 7666 vnix = ((data2 & F_DATAVIDH2) << 23) | 7667 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7668 } else 7669 vnix = 0; 7670 7671 if (tcamx & tcamy) 7672 continue; 7673 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7674 7675 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7676 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7677 7678 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7679 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7680 "%012jx %06x %06x - - %3c" 7681 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 7682 addr[1], addr[2], addr[3], addr[4], addr[5], 7683 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 7684 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7685 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7686 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7687 } else { 7688 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7689 "%012jx - - ", i, addr[0], addr[1], 7690 addr[2], addr[3], addr[4], addr[5], 7691 (uintmax_t)mask); 7692 7693 if (vlan_vld) 7694 sbuf_printf(sb, "%4u Y ", ivlan); 7695 else 7696 sbuf_printf(sb, " - N "); 7697 7698 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 7699 lookup_type ? 'I' : 'O', port_num, 7700 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7701 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7702 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7703 } 7704 7705 7706 if (cls_lo & F_T6_REPLICATE) { 7707 struct fw_ldst_cmd ldst_cmd; 7708 7709 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7710 ldst_cmd.op_to_addrspace = 7711 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7712 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7713 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7714 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7715 ldst_cmd.u.mps.rplc.fid_idx = 7716 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7717 V_FW_LDST_CMD_IDX(i)); 7718 7719 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7720 "t6mps"); 7721 if (rc) 7722 break; 7723 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7724 sizeof(ldst_cmd), &ldst_cmd); 7725 end_synchronized_op(sc, 0); 7726 7727 if (rc != 0) { 7728 sbuf_printf(sb, "%72d", rc); 7729 rc = 0; 7730 } else { 7731 sbuf_printf(sb, " %08x %08x %08x %08x" 7732 " %08x %08x %08x %08x", 7733 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 7734 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 7735 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 7736 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 7737 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7738 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7739 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7740 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7741 } 7742 } else 7743 sbuf_printf(sb, "%72s", ""); 7744 7745 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 7746 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 7747 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 7748 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 7749 } 7750 7751 if (rc) 7752 (void) sbuf_finish(sb); 7753 else 7754 rc = sbuf_finish(sb); 7755 sbuf_delete(sb); 7756 7757 return (rc); 7758 } 7759 7760 static int 7761 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 7762 { 7763 struct adapter *sc = arg1; 7764 struct sbuf *sb; 7765 int rc; 7766 uint16_t mtus[NMTUS]; 7767 7768 rc = sysctl_wire_old_buffer(req, 0); 7769 if (rc != 0) 7770 return (rc); 7771 7772 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7773 if (sb == NULL) 7774 return (ENOMEM); 7775 7776 t4_read_mtu_tbl(sc, mtus, NULL); 7777 7778 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 7779 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 7780 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 7781 mtus[14], mtus[15]); 7782 7783 rc = sbuf_finish(sb); 7784 sbuf_delete(sb); 7785 7786 return (rc); 7787 } 7788 7789 static int 7790 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 7791 { 7792 struct adapter *sc = arg1; 7793 struct sbuf *sb; 7794 int rc, i; 7795 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 7796 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 7797 static const char *tx_stats[MAX_PM_NSTATS] = { 7798 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 7799 "Tx FIFO wait", NULL, "Tx latency" 7800 }; 7801 static const char *rx_stats[MAX_PM_NSTATS] = { 7802 "Read:", "Write bypass:", "Write mem:", "Flush:", 7803 "Rx FIFO wait", NULL, "Rx latency" 7804 }; 7805 7806 rc = sysctl_wire_old_buffer(req, 0); 7807 if (rc != 0) 7808 return (rc); 7809 7810 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7811 if (sb == NULL) 7812 return (ENOMEM); 7813 7814 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 7815 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 7816 7817 sbuf_printf(sb, " Tx pcmds Tx bytes"); 7818 for (i = 0; i < 4; i++) { 7819 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7820 tx_cyc[i]); 7821 } 7822 7823 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 7824 for (i = 0; i < 4; i++) { 7825 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7826 rx_cyc[i]); 7827 } 7828 7829 if (chip_id(sc) > CHELSIO_T5) { 7830 sbuf_printf(sb, 7831 "\n Total wait Total occupancy"); 7832 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7833 tx_cyc[i]); 7834 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7835 rx_cyc[i]); 7836 7837 i += 2; 7838 MPASS(i < nitems(tx_stats)); 7839 7840 sbuf_printf(sb, 7841 "\n Reads Total wait"); 7842 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7843 tx_cyc[i]); 7844 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7845 rx_cyc[i]); 7846 } 7847 7848 rc = sbuf_finish(sb); 7849 sbuf_delete(sb); 7850 7851 return (rc); 7852 } 7853 7854 static int 7855 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 7856 { 7857 struct adapter *sc = arg1; 7858 struct sbuf *sb; 7859 int rc; 7860 struct tp_rdma_stats stats; 7861 7862 rc = sysctl_wire_old_buffer(req, 0); 7863 if (rc != 0) 7864 return (rc); 7865 7866 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7867 if (sb == NULL) 7868 return (ENOMEM); 7869 7870 mtx_lock(&sc->reg_lock); 7871 t4_tp_get_rdma_stats(sc, &stats, 0); 7872 mtx_unlock(&sc->reg_lock); 7873 7874 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 7875 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 7876 7877 rc = sbuf_finish(sb); 7878 sbuf_delete(sb); 7879 7880 return (rc); 7881 } 7882 7883 static int 7884 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 7885 { 7886 struct adapter *sc = arg1; 7887 struct sbuf *sb; 7888 int rc; 7889 struct tp_tcp_stats v4, v6; 7890 7891 rc = sysctl_wire_old_buffer(req, 0); 7892 if (rc != 0) 7893 return (rc); 7894 7895 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7896 if (sb == NULL) 7897 return (ENOMEM); 7898 7899 mtx_lock(&sc->reg_lock); 7900 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 7901 mtx_unlock(&sc->reg_lock); 7902 7903 sbuf_printf(sb, 7904 " IP IPv6\n"); 7905 sbuf_printf(sb, "OutRsts: %20u %20u\n", 7906 v4.tcp_out_rsts, v6.tcp_out_rsts); 7907 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 7908 v4.tcp_in_segs, v6.tcp_in_segs); 7909 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 7910 v4.tcp_out_segs, v6.tcp_out_segs); 7911 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 7912 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 7913 7914 rc = sbuf_finish(sb); 7915 sbuf_delete(sb); 7916 7917 return (rc); 7918 } 7919 7920 static int 7921 sysctl_tids(SYSCTL_HANDLER_ARGS) 7922 { 7923 struct adapter *sc = arg1; 7924 struct sbuf *sb; 7925 int rc; 7926 struct tid_info *t = &sc->tids; 7927 7928 rc = sysctl_wire_old_buffer(req, 0); 7929 if (rc != 0) 7930 return (rc); 7931 7932 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7933 if (sb == NULL) 7934 return (ENOMEM); 7935 7936 if (t->natids) { 7937 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 7938 t->atids_in_use); 7939 } 7940 7941 if (t->ntids) { 7942 sbuf_printf(sb, "TID range: "); 7943 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7944 uint32_t b, hb; 7945 7946 if (chip_id(sc) <= CHELSIO_T5) { 7947 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 7948 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 7949 } else { 7950 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 7951 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 7952 } 7953 7954 if (b) 7955 sbuf_printf(sb, "0-%u, ", b - 1); 7956 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 7957 } else 7958 sbuf_printf(sb, "0-%u", t->ntids - 1); 7959 sbuf_printf(sb, ", in use: %u\n", 7960 atomic_load_acq_int(&t->tids_in_use)); 7961 } 7962 7963 if (t->nstids) { 7964 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 7965 t->stid_base + t->nstids - 1, t->stids_in_use); 7966 } 7967 7968 if (t->nftids) { 7969 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 7970 t->ftid_base + t->nftids - 1); 7971 } 7972 7973 if (t->netids) { 7974 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 7975 t->etid_base + t->netids - 1, t->etids_in_use); 7976 } 7977 7978 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 7979 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 7980 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 7981 7982 rc = sbuf_finish(sb); 7983 sbuf_delete(sb); 7984 7985 return (rc); 7986 } 7987 7988 static int 7989 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 7990 { 7991 struct adapter *sc = arg1; 7992 struct sbuf *sb; 7993 int rc; 7994 struct tp_err_stats stats; 7995 7996 rc = sysctl_wire_old_buffer(req, 0); 7997 if (rc != 0) 7998 return (rc); 7999 8000 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8001 if (sb == NULL) 8002 return (ENOMEM); 8003 8004 mtx_lock(&sc->reg_lock); 8005 t4_tp_get_err_stats(sc, &stats, 0); 8006 mtx_unlock(&sc->reg_lock); 8007 8008 if (sc->chip_params->nchan > 2) { 8009 sbuf_printf(sb, " channel 0 channel 1" 8010 " channel 2 channel 3\n"); 8011 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 8012 stats.mac_in_errs[0], stats.mac_in_errs[1], 8013 stats.mac_in_errs[2], stats.mac_in_errs[3]); 8014 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 8015 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 8016 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 8017 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 8018 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 8019 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 8020 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 8021 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 8022 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 8023 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 8024 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 8025 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 8026 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 8027 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 8028 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 8029 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 8030 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 8031 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 8032 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 8033 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 8034 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 8035 } else { 8036 sbuf_printf(sb, " channel 0 channel 1\n"); 8037 sbuf_printf(sb, "macInErrs: %10u %10u\n", 8038 stats.mac_in_errs[0], stats.mac_in_errs[1]); 8039 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 8040 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 8041 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 8042 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8043 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8044 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8045 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8046 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8047 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8048 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8049 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8050 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8051 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8052 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8053 } 8054 8055 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8056 stats.ofld_no_neigh, stats.ofld_cong_defer); 8057 8058 rc = sbuf_finish(sb); 8059 sbuf_delete(sb); 8060 8061 return (rc); 8062 } 8063 8064 static int 8065 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8066 { 8067 struct adapter *sc = arg1; 8068 struct tp_params *tpp = &sc->params.tp; 8069 u_int mask; 8070 int rc; 8071 8072 mask = tpp->la_mask >> 16; 8073 rc = sysctl_handle_int(oidp, &mask, 0, req); 8074 if (rc != 0 || req->newptr == NULL) 8075 return (rc); 8076 if (mask > 0xffff) 8077 return (EINVAL); 8078 tpp->la_mask = mask << 16; 8079 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8080 8081 return (0); 8082 } 8083 8084 struct field_desc { 8085 const char *name; 8086 u_int start; 8087 u_int width; 8088 }; 8089 8090 static void 8091 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8092 { 8093 char buf[32]; 8094 int line_size = 0; 8095 8096 while (f->name) { 8097 uint64_t mask = (1ULL << f->width) - 1; 8098 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8099 ((uintmax_t)v >> f->start) & mask); 8100 8101 if (line_size + len >= 79) { 8102 line_size = 8; 8103 sbuf_printf(sb, "\n "); 8104 } 8105 sbuf_printf(sb, "%s ", buf); 8106 line_size += len + 1; 8107 f++; 8108 } 8109 sbuf_printf(sb, "\n"); 8110 } 8111 8112 static const struct field_desc tp_la0[] = { 8113 { "RcfOpCodeOut", 60, 4 }, 8114 { "State", 56, 4 }, 8115 { "WcfState", 52, 4 }, 8116 { "RcfOpcSrcOut", 50, 2 }, 8117 { "CRxError", 49, 1 }, 8118 { "ERxError", 48, 1 }, 8119 { "SanityFailed", 47, 1 }, 8120 { "SpuriousMsg", 46, 1 }, 8121 { "FlushInputMsg", 45, 1 }, 8122 { "FlushInputCpl", 44, 1 }, 8123 { "RssUpBit", 43, 1 }, 8124 { "RssFilterHit", 42, 1 }, 8125 { "Tid", 32, 10 }, 8126 { "InitTcb", 31, 1 }, 8127 { "LineNumber", 24, 7 }, 8128 { "Emsg", 23, 1 }, 8129 { "EdataOut", 22, 1 }, 8130 { "Cmsg", 21, 1 }, 8131 { "CdataOut", 20, 1 }, 8132 { "EreadPdu", 19, 1 }, 8133 { "CreadPdu", 18, 1 }, 8134 { "TunnelPkt", 17, 1 }, 8135 { "RcfPeerFin", 16, 1 }, 8136 { "RcfReasonOut", 12, 4 }, 8137 { "TxCchannel", 10, 2 }, 8138 { "RcfTxChannel", 8, 2 }, 8139 { "RxEchannel", 6, 2 }, 8140 { "RcfRxChannel", 5, 1 }, 8141 { "RcfDataOutSrdy", 4, 1 }, 8142 { "RxDvld", 3, 1 }, 8143 { "RxOoDvld", 2, 1 }, 8144 { "RxCongestion", 1, 1 }, 8145 { "TxCongestion", 0, 1 }, 8146 { NULL } 8147 }; 8148 8149 static const struct field_desc tp_la1[] = { 8150 { "CplCmdIn", 56, 8 }, 8151 { "CplCmdOut", 48, 8 }, 8152 { "ESynOut", 47, 1 }, 8153 { "EAckOut", 46, 1 }, 8154 { "EFinOut", 45, 1 }, 8155 { "ERstOut", 44, 1 }, 8156 { "SynIn", 43, 1 }, 8157 { "AckIn", 42, 1 }, 8158 { "FinIn", 41, 1 }, 8159 { "RstIn", 40, 1 }, 8160 { "DataIn", 39, 1 }, 8161 { "DataInVld", 38, 1 }, 8162 { "PadIn", 37, 1 }, 8163 { "RxBufEmpty", 36, 1 }, 8164 { "RxDdp", 35, 1 }, 8165 { "RxFbCongestion", 34, 1 }, 8166 { "TxFbCongestion", 33, 1 }, 8167 { "TxPktSumSrdy", 32, 1 }, 8168 { "RcfUlpType", 28, 4 }, 8169 { "Eread", 27, 1 }, 8170 { "Ebypass", 26, 1 }, 8171 { "Esave", 25, 1 }, 8172 { "Static0", 24, 1 }, 8173 { "Cread", 23, 1 }, 8174 { "Cbypass", 22, 1 }, 8175 { "Csave", 21, 1 }, 8176 { "CPktOut", 20, 1 }, 8177 { "RxPagePoolFull", 18, 2 }, 8178 { "RxLpbkPkt", 17, 1 }, 8179 { "TxLpbkPkt", 16, 1 }, 8180 { "RxVfValid", 15, 1 }, 8181 { "SynLearned", 14, 1 }, 8182 { "SetDelEntry", 13, 1 }, 8183 { "SetInvEntry", 12, 1 }, 8184 { "CpcmdDvld", 11, 1 }, 8185 { "CpcmdSave", 10, 1 }, 8186 { "RxPstructsFull", 8, 2 }, 8187 { "EpcmdDvld", 7, 1 }, 8188 { "EpcmdFlush", 6, 1 }, 8189 { "EpcmdTrimPrefix", 5, 1 }, 8190 { "EpcmdTrimPostfix", 4, 1 }, 8191 { "ERssIp4Pkt", 3, 1 }, 8192 { "ERssIp6Pkt", 2, 1 }, 8193 { "ERssTcpUdpPkt", 1, 1 }, 8194 { "ERssFceFipPkt", 0, 1 }, 8195 { NULL } 8196 }; 8197 8198 static const struct field_desc tp_la2[] = { 8199 { "CplCmdIn", 56, 8 }, 8200 { "MpsVfVld", 55, 1 }, 8201 { "MpsPf", 52, 3 }, 8202 { "MpsVf", 44, 8 }, 8203 { "SynIn", 43, 1 }, 8204 { "AckIn", 42, 1 }, 8205 { "FinIn", 41, 1 }, 8206 { "RstIn", 40, 1 }, 8207 { "DataIn", 39, 1 }, 8208 { "DataInVld", 38, 1 }, 8209 { "PadIn", 37, 1 }, 8210 { "RxBufEmpty", 36, 1 }, 8211 { "RxDdp", 35, 1 }, 8212 { "RxFbCongestion", 34, 1 }, 8213 { "TxFbCongestion", 33, 1 }, 8214 { "TxPktSumSrdy", 32, 1 }, 8215 { "RcfUlpType", 28, 4 }, 8216 { "Eread", 27, 1 }, 8217 { "Ebypass", 26, 1 }, 8218 { "Esave", 25, 1 }, 8219 { "Static0", 24, 1 }, 8220 { "Cread", 23, 1 }, 8221 { "Cbypass", 22, 1 }, 8222 { "Csave", 21, 1 }, 8223 { "CPktOut", 20, 1 }, 8224 { "RxPagePoolFull", 18, 2 }, 8225 { "RxLpbkPkt", 17, 1 }, 8226 { "TxLpbkPkt", 16, 1 }, 8227 { "RxVfValid", 15, 1 }, 8228 { "SynLearned", 14, 1 }, 8229 { "SetDelEntry", 13, 1 }, 8230 { "SetInvEntry", 12, 1 }, 8231 { "CpcmdDvld", 11, 1 }, 8232 { "CpcmdSave", 10, 1 }, 8233 { "RxPstructsFull", 8, 2 }, 8234 { "EpcmdDvld", 7, 1 }, 8235 { "EpcmdFlush", 6, 1 }, 8236 { "EpcmdTrimPrefix", 5, 1 }, 8237 { "EpcmdTrimPostfix", 4, 1 }, 8238 { "ERssIp4Pkt", 3, 1 }, 8239 { "ERssIp6Pkt", 2, 1 }, 8240 { "ERssTcpUdpPkt", 1, 1 }, 8241 { "ERssFceFipPkt", 0, 1 }, 8242 { NULL } 8243 }; 8244 8245 static void 8246 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8247 { 8248 8249 field_desc_show(sb, *p, tp_la0); 8250 } 8251 8252 static void 8253 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8254 { 8255 8256 if (idx) 8257 sbuf_printf(sb, "\n"); 8258 field_desc_show(sb, p[0], tp_la0); 8259 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8260 field_desc_show(sb, p[1], tp_la0); 8261 } 8262 8263 static void 8264 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 8265 { 8266 8267 if (idx) 8268 sbuf_printf(sb, "\n"); 8269 field_desc_show(sb, p[0], tp_la0); 8270 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8271 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 8272 } 8273 8274 static int 8275 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 8276 { 8277 struct adapter *sc = arg1; 8278 struct sbuf *sb; 8279 uint64_t *buf, *p; 8280 int rc; 8281 u_int i, inc; 8282 void (*show_func)(struct sbuf *, uint64_t *, int); 8283 8284 rc = sysctl_wire_old_buffer(req, 0); 8285 if (rc != 0) 8286 return (rc); 8287 8288 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8289 if (sb == NULL) 8290 return (ENOMEM); 8291 8292 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 8293 8294 t4_tp_read_la(sc, buf, NULL); 8295 p = buf; 8296 8297 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 8298 case 2: 8299 inc = 2; 8300 show_func = tp_la_show2; 8301 break; 8302 case 3: 8303 inc = 2; 8304 show_func = tp_la_show3; 8305 break; 8306 default: 8307 inc = 1; 8308 show_func = tp_la_show; 8309 } 8310 8311 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 8312 (*show_func)(sb, p, i); 8313 8314 rc = sbuf_finish(sb); 8315 sbuf_delete(sb); 8316 free(buf, M_CXGBE); 8317 return (rc); 8318 } 8319 8320 static int 8321 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 8322 { 8323 struct adapter *sc = arg1; 8324 struct sbuf *sb; 8325 int rc; 8326 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 8327 8328 rc = sysctl_wire_old_buffer(req, 0); 8329 if (rc != 0) 8330 return (rc); 8331 8332 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8333 if (sb == NULL) 8334 return (ENOMEM); 8335 8336 t4_get_chan_txrate(sc, nrate, orate); 8337 8338 if (sc->chip_params->nchan > 2) { 8339 sbuf_printf(sb, " channel 0 channel 1" 8340 " channel 2 channel 3\n"); 8341 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 8342 nrate[0], nrate[1], nrate[2], nrate[3]); 8343 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 8344 orate[0], orate[1], orate[2], orate[3]); 8345 } else { 8346 sbuf_printf(sb, " channel 0 channel 1\n"); 8347 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 8348 nrate[0], nrate[1]); 8349 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 8350 orate[0], orate[1]); 8351 } 8352 8353 rc = sbuf_finish(sb); 8354 sbuf_delete(sb); 8355 8356 return (rc); 8357 } 8358 8359 static int 8360 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 8361 { 8362 struct adapter *sc = arg1; 8363 struct sbuf *sb; 8364 uint32_t *buf, *p; 8365 int rc, i; 8366 8367 rc = sysctl_wire_old_buffer(req, 0); 8368 if (rc != 0) 8369 return (rc); 8370 8371 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8372 if (sb == NULL) 8373 return (ENOMEM); 8374 8375 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 8376 M_ZERO | M_WAITOK); 8377 8378 t4_ulprx_read_la(sc, buf); 8379 p = buf; 8380 8381 sbuf_printf(sb, " Pcmd Type Message" 8382 " Data"); 8383 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 8384 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 8385 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 8386 } 8387 8388 rc = sbuf_finish(sb); 8389 sbuf_delete(sb); 8390 free(buf, M_CXGBE); 8391 return (rc); 8392 } 8393 8394 static int 8395 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 8396 { 8397 struct adapter *sc = arg1; 8398 struct sbuf *sb; 8399 int rc, v; 8400 8401 MPASS(chip_id(sc) >= CHELSIO_T5); 8402 8403 rc = sysctl_wire_old_buffer(req, 0); 8404 if (rc != 0) 8405 return (rc); 8406 8407 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8408 if (sb == NULL) 8409 return (ENOMEM); 8410 8411 v = t4_read_reg(sc, A_SGE_STAT_CFG); 8412 if (G_STATSOURCE_T5(v) == 7) { 8413 int mode; 8414 8415 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 8416 if (mode == 0) { 8417 sbuf_printf(sb, "total %d, incomplete %d", 8418 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8419 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8420 } else if (mode == 1) { 8421 sbuf_printf(sb, "total %d, data overflow %d", 8422 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8423 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8424 } else { 8425 sbuf_printf(sb, "unknown mode %d", mode); 8426 } 8427 } 8428 rc = sbuf_finish(sb); 8429 sbuf_delete(sb); 8430 8431 return (rc); 8432 } 8433 8434 static int 8435 sysctl_tc_params(SYSCTL_HANDLER_ARGS) 8436 { 8437 struct adapter *sc = arg1; 8438 struct tx_cl_rl_params tc; 8439 struct sbuf *sb; 8440 int i, rc, port_id, mbps, gbps; 8441 8442 rc = sysctl_wire_old_buffer(req, 0); 8443 if (rc != 0) 8444 return (rc); 8445 8446 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8447 if (sb == NULL) 8448 return (ENOMEM); 8449 8450 port_id = arg2 >> 16; 8451 MPASS(port_id < sc->params.nports); 8452 MPASS(sc->port[port_id] != NULL); 8453 i = arg2 & 0xffff; 8454 MPASS(i < sc->chip_params->nsched_cls); 8455 8456 mtx_lock(&sc->tc_lock); 8457 tc = sc->port[port_id]->sched_params->cl_rl[i]; 8458 mtx_unlock(&sc->tc_lock); 8459 8460 if (tc.flags & TX_CLRL_ERROR) { 8461 sbuf_printf(sb, "error"); 8462 goto done; 8463 } 8464 8465 if (tc.ratemode == SCHED_CLASS_RATEMODE_REL) { 8466 /* XXX: top speed or actual link speed? */ 8467 gbps = port_top_speed(sc->port[port_id]); 8468 sbuf_printf(sb, " %u%% of %uGbps", tc.maxrate, gbps); 8469 } else if (tc.ratemode == SCHED_CLASS_RATEMODE_ABS) { 8470 switch (tc.rateunit) { 8471 case SCHED_CLASS_RATEUNIT_BITS: 8472 mbps = tc.maxrate / 1000; 8473 gbps = tc.maxrate / 1000000; 8474 if (tc.maxrate == gbps * 1000000) 8475 sbuf_printf(sb, " %uGbps", gbps); 8476 else if (tc.maxrate == mbps * 1000) 8477 sbuf_printf(sb, " %uMbps", mbps); 8478 else 8479 sbuf_printf(sb, " %uKbps", tc.maxrate); 8480 break; 8481 case SCHED_CLASS_RATEUNIT_PKTS: 8482 sbuf_printf(sb, " %upps", tc.maxrate); 8483 break; 8484 default: 8485 rc = ENXIO; 8486 goto done; 8487 } 8488 } 8489 8490 switch (tc.mode) { 8491 case SCHED_CLASS_MODE_CLASS: 8492 sbuf_printf(sb, " aggregate"); 8493 break; 8494 case SCHED_CLASS_MODE_FLOW: 8495 sbuf_printf(sb, " per-flow"); 8496 break; 8497 default: 8498 rc = ENXIO; 8499 goto done; 8500 } 8501 8502 done: 8503 if (rc == 0) 8504 rc = sbuf_finish(sb); 8505 sbuf_delete(sb); 8506 8507 return (rc); 8508 } 8509 #endif 8510 8511 #ifdef TCP_OFFLOAD 8512 static int 8513 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 8514 { 8515 struct adapter *sc = arg1; 8516 int *old_ports, *new_ports; 8517 int i, new_count, rc; 8518 8519 if (req->newptr == NULL && req->oldptr == NULL) 8520 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 8521 sizeof(sc->tt.tls_rx_ports[0]))); 8522 8523 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 8524 if (rc) 8525 return (rc); 8526 8527 if (sc->tt.num_tls_rx_ports == 0) { 8528 i = -1; 8529 rc = SYSCTL_OUT(req, &i, sizeof(i)); 8530 } else 8531 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 8532 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 8533 if (rc == 0 && req->newptr != NULL) { 8534 new_count = req->newlen / sizeof(new_ports[0]); 8535 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 8536 M_WAITOK); 8537 rc = SYSCTL_IN(req, new_ports, new_count * 8538 sizeof(new_ports[0])); 8539 if (rc) 8540 goto err; 8541 8542 /* Allow setting to a single '-1' to clear the list. */ 8543 if (new_count == 1 && new_ports[0] == -1) { 8544 ADAPTER_LOCK(sc); 8545 old_ports = sc->tt.tls_rx_ports; 8546 sc->tt.tls_rx_ports = NULL; 8547 sc->tt.num_tls_rx_ports = 0; 8548 ADAPTER_UNLOCK(sc); 8549 free(old_ports, M_CXGBE); 8550 } else { 8551 for (i = 0; i < new_count; i++) { 8552 if (new_ports[i] < 1 || 8553 new_ports[i] > IPPORT_MAX) { 8554 rc = EINVAL; 8555 goto err; 8556 } 8557 } 8558 8559 ADAPTER_LOCK(sc); 8560 old_ports = sc->tt.tls_rx_ports; 8561 sc->tt.tls_rx_ports = new_ports; 8562 sc->tt.num_tls_rx_ports = new_count; 8563 ADAPTER_UNLOCK(sc); 8564 free(old_ports, M_CXGBE); 8565 new_ports = NULL; 8566 } 8567 err: 8568 free(new_ports, M_CXGBE); 8569 } 8570 end_synchronized_op(sc, 0); 8571 return (rc); 8572 } 8573 8574 static void 8575 unit_conv(char *buf, size_t len, u_int val, u_int factor) 8576 { 8577 u_int rem = val % factor; 8578 8579 if (rem == 0) 8580 snprintf(buf, len, "%u", val / factor); 8581 else { 8582 while (rem % 10 == 0) 8583 rem /= 10; 8584 snprintf(buf, len, "%u.%u", val / factor, rem); 8585 } 8586 } 8587 8588 static int 8589 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 8590 { 8591 struct adapter *sc = arg1; 8592 char buf[16]; 8593 u_int res, re; 8594 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8595 8596 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8597 switch (arg2) { 8598 case 0: 8599 /* timer_tick */ 8600 re = G_TIMERRESOLUTION(res); 8601 break; 8602 case 1: 8603 /* TCP timestamp tick */ 8604 re = G_TIMESTAMPRESOLUTION(res); 8605 break; 8606 case 2: 8607 /* DACK tick */ 8608 re = G_DELAYEDACKRESOLUTION(res); 8609 break; 8610 default: 8611 return (EDOOFUS); 8612 } 8613 8614 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 8615 8616 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 8617 } 8618 8619 static int 8620 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 8621 { 8622 struct adapter *sc = arg1; 8623 u_int res, dack_re, v; 8624 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8625 8626 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8627 dack_re = G_DELAYEDACKRESOLUTION(res); 8628 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 8629 8630 return (sysctl_handle_int(oidp, &v, 0, req)); 8631 } 8632 8633 static int 8634 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 8635 { 8636 struct adapter *sc = arg1; 8637 int reg = arg2; 8638 u_int tre; 8639 u_long tp_tick_us, v; 8640 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8641 8642 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 8643 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 8644 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 8645 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 8646 8647 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 8648 tp_tick_us = (cclk_ps << tre) / 1000000; 8649 8650 if (reg == A_TP_INIT_SRTT) 8651 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 8652 else 8653 v = tp_tick_us * t4_read_reg(sc, reg); 8654 8655 return (sysctl_handle_long(oidp, &v, 0, req)); 8656 } 8657 8658 /* 8659 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 8660 * passed to this function. 8661 */ 8662 static int 8663 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 8664 { 8665 struct adapter *sc = arg1; 8666 int idx = arg2; 8667 u_int v; 8668 8669 MPASS(idx >= 0 && idx <= 24); 8670 8671 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 8672 8673 return (sysctl_handle_int(oidp, &v, 0, req)); 8674 } 8675 8676 static int 8677 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 8678 { 8679 struct adapter *sc = arg1; 8680 int idx = arg2; 8681 u_int shift, v, r; 8682 8683 MPASS(idx >= 0 && idx < 16); 8684 8685 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 8686 shift = (idx & 3) << 3; 8687 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 8688 8689 return (sysctl_handle_int(oidp, &v, 0, req)); 8690 } 8691 8692 static int 8693 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 8694 { 8695 struct vi_info *vi = arg1; 8696 struct adapter *sc = vi->pi->adapter; 8697 int idx, rc, i; 8698 struct sge_ofld_rxq *ofld_rxq; 8699 uint8_t v; 8700 8701 idx = vi->ofld_tmr_idx; 8702 8703 rc = sysctl_handle_int(oidp, &idx, 0, req); 8704 if (rc != 0 || req->newptr == NULL) 8705 return (rc); 8706 8707 if (idx < 0 || idx >= SGE_NTIMERS) 8708 return (EINVAL); 8709 8710 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8711 "t4otmr"); 8712 if (rc) 8713 return (rc); 8714 8715 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 8716 for_each_ofld_rxq(vi, i, ofld_rxq) { 8717 #ifdef atomic_store_rel_8 8718 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 8719 #else 8720 ofld_rxq->iq.intr_params = v; 8721 #endif 8722 } 8723 vi->ofld_tmr_idx = idx; 8724 8725 end_synchronized_op(sc, LOCK_HELD); 8726 return (0); 8727 } 8728 8729 static int 8730 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 8731 { 8732 struct vi_info *vi = arg1; 8733 struct adapter *sc = vi->pi->adapter; 8734 int idx, rc; 8735 8736 idx = vi->ofld_pktc_idx; 8737 8738 rc = sysctl_handle_int(oidp, &idx, 0, req); 8739 if (rc != 0 || req->newptr == NULL) 8740 return (rc); 8741 8742 if (idx < -1 || idx >= SGE_NCOUNTERS) 8743 return (EINVAL); 8744 8745 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8746 "t4opktc"); 8747 if (rc) 8748 return (rc); 8749 8750 if (vi->flags & VI_INIT_DONE) 8751 rc = EBUSY; /* cannot be changed once the queues are created */ 8752 else 8753 vi->ofld_pktc_idx = idx; 8754 8755 end_synchronized_op(sc, LOCK_HELD); 8756 return (rc); 8757 } 8758 #endif 8759 8760 static int 8761 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 8762 { 8763 int rc; 8764 8765 if (cntxt->cid > M_CTXTQID) 8766 return (EINVAL); 8767 8768 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 8769 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 8770 return (EINVAL); 8771 8772 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 8773 if (rc) 8774 return (rc); 8775 8776 if (sc->flags & FW_OK) { 8777 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 8778 &cntxt->data[0]); 8779 if (rc == 0) 8780 goto done; 8781 } 8782 8783 /* 8784 * Read via firmware failed or wasn't even attempted. Read directly via 8785 * the backdoor. 8786 */ 8787 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 8788 done: 8789 end_synchronized_op(sc, 0); 8790 return (rc); 8791 } 8792 8793 static int 8794 load_fw(struct adapter *sc, struct t4_data *fw) 8795 { 8796 int rc; 8797 uint8_t *fw_data; 8798 8799 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 8800 if (rc) 8801 return (rc); 8802 8803 /* 8804 * The firmware, with the sole exception of the memory parity error 8805 * handler, runs from memory and not flash. It is almost always safe to 8806 * install a new firmware on a running system. Just set bit 1 in 8807 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 8808 */ 8809 if (sc->flags & FULL_INIT_DONE && 8810 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 8811 rc = EBUSY; 8812 goto done; 8813 } 8814 8815 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 8816 if (fw_data == NULL) { 8817 rc = ENOMEM; 8818 goto done; 8819 } 8820 8821 rc = copyin(fw->data, fw_data, fw->len); 8822 if (rc == 0) 8823 rc = -t4_load_fw(sc, fw_data, fw->len); 8824 8825 free(fw_data, M_CXGBE); 8826 done: 8827 end_synchronized_op(sc, 0); 8828 return (rc); 8829 } 8830 8831 static int 8832 load_cfg(struct adapter *sc, struct t4_data *cfg) 8833 { 8834 int rc; 8835 uint8_t *cfg_data = NULL; 8836 8837 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 8838 if (rc) 8839 return (rc); 8840 8841 if (cfg->len == 0) { 8842 /* clear */ 8843 rc = -t4_load_cfg(sc, NULL, 0); 8844 goto done; 8845 } 8846 8847 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 8848 if (cfg_data == NULL) { 8849 rc = ENOMEM; 8850 goto done; 8851 } 8852 8853 rc = copyin(cfg->data, cfg_data, cfg->len); 8854 if (rc == 0) 8855 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 8856 8857 free(cfg_data, M_CXGBE); 8858 done: 8859 end_synchronized_op(sc, 0); 8860 return (rc); 8861 } 8862 8863 static int 8864 load_boot(struct adapter *sc, struct t4_bootrom *br) 8865 { 8866 int rc; 8867 uint8_t *br_data = NULL; 8868 u_int offset; 8869 8870 if (br->len > 1024 * 1024) 8871 return (EFBIG); 8872 8873 if (br->pf_offset == 0) { 8874 /* pfidx */ 8875 if (br->pfidx_addr > 7) 8876 return (EINVAL); 8877 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 8878 A_PCIE_PF_EXPROM_OFST))); 8879 } else if (br->pf_offset == 1) { 8880 /* offset */ 8881 offset = G_OFFSET(br->pfidx_addr); 8882 } else { 8883 return (EINVAL); 8884 } 8885 8886 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 8887 if (rc) 8888 return (rc); 8889 8890 if (br->len == 0) { 8891 /* clear */ 8892 rc = -t4_load_boot(sc, NULL, offset, 0); 8893 goto done; 8894 } 8895 8896 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 8897 if (br_data == NULL) { 8898 rc = ENOMEM; 8899 goto done; 8900 } 8901 8902 rc = copyin(br->data, br_data, br->len); 8903 if (rc == 0) 8904 rc = -t4_load_boot(sc, br_data, offset, br->len); 8905 8906 free(br_data, M_CXGBE); 8907 done: 8908 end_synchronized_op(sc, 0); 8909 return (rc); 8910 } 8911 8912 static int 8913 load_bootcfg(struct adapter *sc, struct t4_data *bc) 8914 { 8915 int rc; 8916 uint8_t *bc_data = NULL; 8917 8918 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 8919 if (rc) 8920 return (rc); 8921 8922 if (bc->len == 0) { 8923 /* clear */ 8924 rc = -t4_load_bootcfg(sc, NULL, 0); 8925 goto done; 8926 } 8927 8928 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 8929 if (bc_data == NULL) { 8930 rc = ENOMEM; 8931 goto done; 8932 } 8933 8934 rc = copyin(bc->data, bc_data, bc->len); 8935 if (rc == 0) 8936 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 8937 8938 free(bc_data, M_CXGBE); 8939 done: 8940 end_synchronized_op(sc, 0); 8941 return (rc); 8942 } 8943 8944 static int 8945 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 8946 { 8947 int rc; 8948 struct cudbg_init *cudbg; 8949 void *handle, *buf; 8950 8951 /* buf is large, don't block if no memory is available */ 8952 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 8953 if (buf == NULL) 8954 return (ENOMEM); 8955 8956 handle = cudbg_alloc_handle(); 8957 if (handle == NULL) { 8958 rc = ENOMEM; 8959 goto done; 8960 } 8961 8962 cudbg = cudbg_get_init(handle); 8963 cudbg->adap = sc; 8964 cudbg->print = (cudbg_print_cb)printf; 8965 8966 #ifndef notyet 8967 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 8968 __func__, dump->wr_flash, dump->len, dump->data); 8969 #endif 8970 8971 if (dump->wr_flash) 8972 cudbg->use_flash = 1; 8973 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 8974 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 8975 8976 rc = cudbg_collect(handle, buf, &dump->len); 8977 if (rc != 0) 8978 goto done; 8979 8980 rc = copyout(buf, dump->data, dump->len); 8981 done: 8982 cudbg_free_handle(handle); 8983 free(buf, M_CXGBE); 8984 return (rc); 8985 } 8986 8987 static void 8988 free_offload_policy(struct t4_offload_policy *op) 8989 { 8990 struct offload_rule *r; 8991 int i; 8992 8993 if (op == NULL) 8994 return; 8995 8996 r = &op->rule[0]; 8997 for (i = 0; i < op->nrules; i++, r++) { 8998 free(r->bpf_prog.bf_insns, M_CXGBE); 8999 } 9000 free(op->rule, M_CXGBE); 9001 free(op, M_CXGBE); 9002 } 9003 9004 static int 9005 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 9006 { 9007 int i, rc, len; 9008 struct t4_offload_policy *op, *old; 9009 struct bpf_program *bf; 9010 const struct offload_settings *s; 9011 struct offload_rule *r; 9012 void *u; 9013 9014 if (!is_offload(sc)) 9015 return (ENODEV); 9016 9017 if (uop->nrules == 0) { 9018 /* Delete installed policies. */ 9019 op = NULL; 9020 goto set_policy; 9021 } if (uop->nrules > 256) { /* arbitrary */ 9022 return (E2BIG); 9023 } 9024 9025 /* Copy userspace offload policy to kernel */ 9026 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 9027 op->nrules = uop->nrules; 9028 len = op->nrules * sizeof(struct offload_rule); 9029 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9030 rc = copyin(uop->rule, op->rule, len); 9031 if (rc) { 9032 free(op->rule, M_CXGBE); 9033 free(op, M_CXGBE); 9034 return (rc); 9035 } 9036 9037 r = &op->rule[0]; 9038 for (i = 0; i < op->nrules; i++, r++) { 9039 9040 /* Validate open_type */ 9041 if (r->open_type != OPEN_TYPE_LISTEN && 9042 r->open_type != OPEN_TYPE_ACTIVE && 9043 r->open_type != OPEN_TYPE_PASSIVE && 9044 r->open_type != OPEN_TYPE_DONTCARE) { 9045 error: 9046 /* 9047 * Rules 0 to i have malloc'd filters that need to be 9048 * freed. Rules i+1 to nrules have userspace pointers 9049 * and should be left alone. 9050 */ 9051 op->nrules = i; 9052 free_offload_policy(op); 9053 return (rc); 9054 } 9055 9056 /* Validate settings */ 9057 s = &r->settings; 9058 if ((s->offload != 0 && s->offload != 1) || 9059 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9060 s->sched_class < -1 || 9061 s->sched_class >= sc->chip_params->nsched_cls) { 9062 rc = EINVAL; 9063 goto error; 9064 } 9065 9066 bf = &r->bpf_prog; 9067 u = bf->bf_insns; /* userspace ptr */ 9068 bf->bf_insns = NULL; 9069 if (bf->bf_len == 0) { 9070 /* legal, matches everything */ 9071 continue; 9072 } 9073 len = bf->bf_len * sizeof(*bf->bf_insns); 9074 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9075 rc = copyin(u, bf->bf_insns, len); 9076 if (rc != 0) 9077 goto error; 9078 9079 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9080 rc = EINVAL; 9081 goto error; 9082 } 9083 } 9084 set_policy: 9085 rw_wlock(&sc->policy_lock); 9086 old = sc->policy; 9087 sc->policy = op; 9088 rw_wunlock(&sc->policy_lock); 9089 free_offload_policy(old); 9090 9091 return (0); 9092 } 9093 9094 #define MAX_READ_BUF_SIZE (128 * 1024) 9095 static int 9096 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9097 { 9098 uint32_t addr, remaining, n; 9099 uint32_t *buf; 9100 int rc; 9101 uint8_t *dst; 9102 9103 rc = validate_mem_range(sc, mr->addr, mr->len); 9104 if (rc != 0) 9105 return (rc); 9106 9107 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9108 addr = mr->addr; 9109 remaining = mr->len; 9110 dst = (void *)mr->data; 9111 9112 while (remaining) { 9113 n = min(remaining, MAX_READ_BUF_SIZE); 9114 read_via_memwin(sc, 2, addr, buf, n); 9115 9116 rc = copyout(buf, dst, n); 9117 if (rc != 0) 9118 break; 9119 9120 dst += n; 9121 remaining -= n; 9122 addr += n; 9123 } 9124 9125 free(buf, M_CXGBE); 9126 return (rc); 9127 } 9128 #undef MAX_READ_BUF_SIZE 9129 9130 static int 9131 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9132 { 9133 int rc; 9134 9135 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9136 return (EINVAL); 9137 9138 if (i2cd->len > sizeof(i2cd->data)) 9139 return (EFBIG); 9140 9141 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9142 if (rc) 9143 return (rc); 9144 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9145 i2cd->offset, i2cd->len, &i2cd->data[0]); 9146 end_synchronized_op(sc, 0); 9147 9148 return (rc); 9149 } 9150 9151 int 9152 t4_os_find_pci_capability(struct adapter *sc, int cap) 9153 { 9154 int i; 9155 9156 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9157 } 9158 9159 int 9160 t4_os_pci_save_state(struct adapter *sc) 9161 { 9162 device_t dev; 9163 struct pci_devinfo *dinfo; 9164 9165 dev = sc->dev; 9166 dinfo = device_get_ivars(dev); 9167 9168 pci_cfg_save(dev, dinfo, 0); 9169 return (0); 9170 } 9171 9172 int 9173 t4_os_pci_restore_state(struct adapter *sc) 9174 { 9175 device_t dev; 9176 struct pci_devinfo *dinfo; 9177 9178 dev = sc->dev; 9179 dinfo = device_get_ivars(dev); 9180 9181 pci_cfg_restore(dev, dinfo); 9182 return (0); 9183 } 9184 9185 void 9186 t4_os_portmod_changed(struct port_info *pi) 9187 { 9188 struct adapter *sc = pi->adapter; 9189 struct vi_info *vi; 9190 struct ifnet *ifp; 9191 static const char *mod_str[] = { 9192 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9193 }; 9194 9195 PORT_LOCK(pi); 9196 build_medialist(pi, &pi->media); 9197 PORT_UNLOCK(pi); 9198 vi = &pi->vi[0]; 9199 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9200 init_l1cfg(pi); 9201 end_synchronized_op(sc, LOCK_HELD); 9202 } 9203 9204 ifp = vi->ifp; 9205 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9206 if_printf(ifp, "transceiver unplugged.\n"); 9207 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9208 if_printf(ifp, "unknown transceiver inserted.\n"); 9209 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9210 if_printf(ifp, "unsupported transceiver inserted.\n"); 9211 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9212 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9213 port_top_speed(pi), mod_str[pi->mod_type]); 9214 } else { 9215 if_printf(ifp, "transceiver (type %d) inserted.\n", 9216 pi->mod_type); 9217 } 9218 } 9219 9220 void 9221 t4_os_link_changed(struct port_info *pi) 9222 { 9223 struct vi_info *vi; 9224 struct ifnet *ifp; 9225 struct link_config *lc; 9226 int v; 9227 9228 for_each_vi(pi, v, vi) { 9229 ifp = vi->ifp; 9230 if (ifp == NULL) 9231 continue; 9232 9233 lc = &pi->link_cfg; 9234 if (lc->link_ok) { 9235 ifp->if_baudrate = IF_Mbps(lc->speed); 9236 if_link_state_change(ifp, LINK_STATE_UP); 9237 } else { 9238 if_link_state_change(ifp, LINK_STATE_DOWN); 9239 } 9240 } 9241 } 9242 9243 void 9244 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9245 { 9246 struct adapter *sc; 9247 9248 sx_slock(&t4_list_lock); 9249 SLIST_FOREACH(sc, &t4_list, link) { 9250 /* 9251 * func should not make any assumptions about what state sc is 9252 * in - the only guarantee is that sc->sc_lock is a valid lock. 9253 */ 9254 func(sc, arg); 9255 } 9256 sx_sunlock(&t4_list_lock); 9257 } 9258 9259 static int 9260 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9261 struct thread *td) 9262 { 9263 int rc; 9264 struct adapter *sc = dev->si_drv1; 9265 9266 rc = priv_check(td, PRIV_DRIVER); 9267 if (rc != 0) 9268 return (rc); 9269 9270 switch (cmd) { 9271 case CHELSIO_T4_GETREG: { 9272 struct t4_reg *edata = (struct t4_reg *)data; 9273 9274 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9275 return (EFAULT); 9276 9277 if (edata->size == 4) 9278 edata->val = t4_read_reg(sc, edata->addr); 9279 else if (edata->size == 8) 9280 edata->val = t4_read_reg64(sc, edata->addr); 9281 else 9282 return (EINVAL); 9283 9284 break; 9285 } 9286 case CHELSIO_T4_SETREG: { 9287 struct t4_reg *edata = (struct t4_reg *)data; 9288 9289 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9290 return (EFAULT); 9291 9292 if (edata->size == 4) { 9293 if (edata->val & 0xffffffff00000000) 9294 return (EINVAL); 9295 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9296 } else if (edata->size == 8) 9297 t4_write_reg64(sc, edata->addr, edata->val); 9298 else 9299 return (EINVAL); 9300 break; 9301 } 9302 case CHELSIO_T4_REGDUMP: { 9303 struct t4_regdump *regs = (struct t4_regdump *)data; 9304 int reglen = t4_get_regs_len(sc); 9305 uint8_t *buf; 9306 9307 if (regs->len < reglen) { 9308 regs->len = reglen; /* hint to the caller */ 9309 return (ENOBUFS); 9310 } 9311 9312 regs->len = reglen; 9313 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9314 get_regs(sc, regs, buf); 9315 rc = copyout(buf, regs->data, reglen); 9316 free(buf, M_CXGBE); 9317 break; 9318 } 9319 case CHELSIO_T4_GET_FILTER_MODE: 9320 rc = get_filter_mode(sc, (uint32_t *)data); 9321 break; 9322 case CHELSIO_T4_SET_FILTER_MODE: 9323 rc = set_filter_mode(sc, *(uint32_t *)data); 9324 break; 9325 case CHELSIO_T4_GET_FILTER: 9326 rc = get_filter(sc, (struct t4_filter *)data); 9327 break; 9328 case CHELSIO_T4_SET_FILTER: 9329 rc = set_filter(sc, (struct t4_filter *)data); 9330 break; 9331 case CHELSIO_T4_DEL_FILTER: 9332 rc = del_filter(sc, (struct t4_filter *)data); 9333 break; 9334 case CHELSIO_T4_GET_SGE_CONTEXT: 9335 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9336 break; 9337 case CHELSIO_T4_LOAD_FW: 9338 rc = load_fw(sc, (struct t4_data *)data); 9339 break; 9340 case CHELSIO_T4_GET_MEM: 9341 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9342 break; 9343 case CHELSIO_T4_GET_I2C: 9344 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9345 break; 9346 case CHELSIO_T4_CLEAR_STATS: { 9347 int i, v, bg_map; 9348 u_int port_id = *(uint32_t *)data; 9349 struct port_info *pi; 9350 struct vi_info *vi; 9351 9352 if (port_id >= sc->params.nports) 9353 return (EINVAL); 9354 pi = sc->port[port_id]; 9355 if (pi == NULL) 9356 return (EIO); 9357 9358 /* MAC stats */ 9359 t4_clr_port_stats(sc, pi->tx_chan); 9360 pi->tx_parse_error = 0; 9361 pi->tnl_cong_drops = 0; 9362 mtx_lock(&sc->reg_lock); 9363 for_each_vi(pi, v, vi) { 9364 if (vi->flags & VI_INIT_DONE) 9365 t4_clr_vi_stats(sc, vi->viid); 9366 } 9367 bg_map = pi->mps_bg_map; 9368 v = 0; /* reuse */ 9369 while (bg_map) { 9370 i = ffs(bg_map) - 1; 9371 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 9372 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 9373 bg_map &= ~(1 << i); 9374 } 9375 mtx_unlock(&sc->reg_lock); 9376 9377 /* 9378 * Since this command accepts a port, clear stats for 9379 * all VIs on this port. 9380 */ 9381 for_each_vi(pi, v, vi) { 9382 if (vi->flags & VI_INIT_DONE) { 9383 struct sge_rxq *rxq; 9384 struct sge_txq *txq; 9385 struct sge_wrq *wrq; 9386 9387 for_each_rxq(vi, i, rxq) { 9388 #if defined(INET) || defined(INET6) 9389 rxq->lro.lro_queued = 0; 9390 rxq->lro.lro_flushed = 0; 9391 #endif 9392 rxq->rxcsum = 0; 9393 rxq->vlan_extraction = 0; 9394 } 9395 9396 for_each_txq(vi, i, txq) { 9397 txq->txcsum = 0; 9398 txq->tso_wrs = 0; 9399 txq->vlan_insertion = 0; 9400 txq->imm_wrs = 0; 9401 txq->sgl_wrs = 0; 9402 txq->txpkt_wrs = 0; 9403 txq->txpkts0_wrs = 0; 9404 txq->txpkts1_wrs = 0; 9405 txq->txpkts0_pkts = 0; 9406 txq->txpkts1_pkts = 0; 9407 mp_ring_reset_stats(txq->r); 9408 } 9409 9410 #ifdef TCP_OFFLOAD 9411 /* nothing to clear for each ofld_rxq */ 9412 9413 for_each_ofld_txq(vi, i, wrq) { 9414 wrq->tx_wrs_direct = 0; 9415 wrq->tx_wrs_copied = 0; 9416 } 9417 #endif 9418 9419 if (IS_MAIN_VI(vi)) { 9420 wrq = &sc->sge.ctrlq[pi->port_id]; 9421 wrq->tx_wrs_direct = 0; 9422 wrq->tx_wrs_copied = 0; 9423 } 9424 } 9425 } 9426 break; 9427 } 9428 case CHELSIO_T4_SCHED_CLASS: 9429 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9430 break; 9431 case CHELSIO_T4_SCHED_QUEUE: 9432 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9433 break; 9434 case CHELSIO_T4_GET_TRACER: 9435 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9436 break; 9437 case CHELSIO_T4_SET_TRACER: 9438 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9439 break; 9440 case CHELSIO_T4_LOAD_CFG: 9441 rc = load_cfg(sc, (struct t4_data *)data); 9442 break; 9443 case CHELSIO_T4_LOAD_BOOT: 9444 rc = load_boot(sc, (struct t4_bootrom *)data); 9445 break; 9446 case CHELSIO_T4_LOAD_BOOTCFG: 9447 rc = load_bootcfg(sc, (struct t4_data *)data); 9448 break; 9449 case CHELSIO_T4_CUDBG_DUMP: 9450 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 9451 break; 9452 case CHELSIO_T4_SET_OFLD_POLICY: 9453 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 9454 break; 9455 default: 9456 rc = ENOTTY; 9457 } 9458 9459 return (rc); 9460 } 9461 9462 void 9463 t4_db_full(struct adapter *sc) 9464 { 9465 9466 CXGBE_UNIMPLEMENTED(__func__); 9467 } 9468 9469 void 9470 t4_db_dropped(struct adapter *sc) 9471 { 9472 9473 CXGBE_UNIMPLEMENTED(__func__); 9474 } 9475 9476 #ifdef TCP_OFFLOAD 9477 static int 9478 toe_capability(struct vi_info *vi, int enable) 9479 { 9480 int rc; 9481 struct port_info *pi = vi->pi; 9482 struct adapter *sc = pi->adapter; 9483 9484 ASSERT_SYNCHRONIZED_OP(sc); 9485 9486 if (!is_offload(sc)) 9487 return (ENODEV); 9488 9489 if (enable) { 9490 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9491 /* TOE is already enabled. */ 9492 return (0); 9493 } 9494 9495 /* 9496 * We need the port's queues around so that we're able to send 9497 * and receive CPLs to/from the TOE even if the ifnet for this 9498 * port has never been UP'd administratively. 9499 */ 9500 if (!(vi->flags & VI_INIT_DONE)) { 9501 rc = vi_full_init(vi); 9502 if (rc) 9503 return (rc); 9504 } 9505 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9506 rc = vi_full_init(&pi->vi[0]); 9507 if (rc) 9508 return (rc); 9509 } 9510 9511 if (isset(&sc->offload_map, pi->port_id)) { 9512 /* TOE is enabled on another VI of this port. */ 9513 pi->uld_vis++; 9514 return (0); 9515 } 9516 9517 if (!uld_active(sc, ULD_TOM)) { 9518 rc = t4_activate_uld(sc, ULD_TOM); 9519 if (rc == EAGAIN) { 9520 log(LOG_WARNING, 9521 "You must kldload t4_tom.ko before trying " 9522 "to enable TOE on a cxgbe interface.\n"); 9523 } 9524 if (rc != 0) 9525 return (rc); 9526 KASSERT(sc->tom_softc != NULL, 9527 ("%s: TOM activated but softc NULL", __func__)); 9528 KASSERT(uld_active(sc, ULD_TOM), 9529 ("%s: TOM activated but flag not set", __func__)); 9530 } 9531 9532 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9533 if (!uld_active(sc, ULD_IWARP)) 9534 (void) t4_activate_uld(sc, ULD_IWARP); 9535 if (!uld_active(sc, ULD_ISCSI)) 9536 (void) t4_activate_uld(sc, ULD_ISCSI); 9537 9538 pi->uld_vis++; 9539 setbit(&sc->offload_map, pi->port_id); 9540 } else { 9541 pi->uld_vis--; 9542 9543 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9544 return (0); 9545 9546 KASSERT(uld_active(sc, ULD_TOM), 9547 ("%s: TOM never initialized?", __func__)); 9548 clrbit(&sc->offload_map, pi->port_id); 9549 } 9550 9551 return (0); 9552 } 9553 9554 /* 9555 * Add an upper layer driver to the global list. 9556 */ 9557 int 9558 t4_register_uld(struct uld_info *ui) 9559 { 9560 int rc = 0; 9561 struct uld_info *u; 9562 9563 sx_xlock(&t4_uld_list_lock); 9564 SLIST_FOREACH(u, &t4_uld_list, link) { 9565 if (u->uld_id == ui->uld_id) { 9566 rc = EEXIST; 9567 goto done; 9568 } 9569 } 9570 9571 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9572 ui->refcount = 0; 9573 done: 9574 sx_xunlock(&t4_uld_list_lock); 9575 return (rc); 9576 } 9577 9578 int 9579 t4_unregister_uld(struct uld_info *ui) 9580 { 9581 int rc = EINVAL; 9582 struct uld_info *u; 9583 9584 sx_xlock(&t4_uld_list_lock); 9585 9586 SLIST_FOREACH(u, &t4_uld_list, link) { 9587 if (u == ui) { 9588 if (ui->refcount > 0) { 9589 rc = EBUSY; 9590 goto done; 9591 } 9592 9593 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 9594 rc = 0; 9595 goto done; 9596 } 9597 } 9598 done: 9599 sx_xunlock(&t4_uld_list_lock); 9600 return (rc); 9601 } 9602 9603 int 9604 t4_activate_uld(struct adapter *sc, int id) 9605 { 9606 int rc; 9607 struct uld_info *ui; 9608 9609 ASSERT_SYNCHRONIZED_OP(sc); 9610 9611 if (id < 0 || id > ULD_MAX) 9612 return (EINVAL); 9613 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 9614 9615 sx_slock(&t4_uld_list_lock); 9616 9617 SLIST_FOREACH(ui, &t4_uld_list, link) { 9618 if (ui->uld_id == id) { 9619 if (!(sc->flags & FULL_INIT_DONE)) { 9620 rc = adapter_full_init(sc); 9621 if (rc != 0) 9622 break; 9623 } 9624 9625 rc = ui->activate(sc); 9626 if (rc == 0) { 9627 setbit(&sc->active_ulds, id); 9628 ui->refcount++; 9629 } 9630 break; 9631 } 9632 } 9633 9634 sx_sunlock(&t4_uld_list_lock); 9635 9636 return (rc); 9637 } 9638 9639 int 9640 t4_deactivate_uld(struct adapter *sc, int id) 9641 { 9642 int rc; 9643 struct uld_info *ui; 9644 9645 ASSERT_SYNCHRONIZED_OP(sc); 9646 9647 if (id < 0 || id > ULD_MAX) 9648 return (EINVAL); 9649 rc = ENXIO; 9650 9651 sx_slock(&t4_uld_list_lock); 9652 9653 SLIST_FOREACH(ui, &t4_uld_list, link) { 9654 if (ui->uld_id == id) { 9655 rc = ui->deactivate(sc); 9656 if (rc == 0) { 9657 clrbit(&sc->active_ulds, id); 9658 ui->refcount--; 9659 } 9660 break; 9661 } 9662 } 9663 9664 sx_sunlock(&t4_uld_list_lock); 9665 9666 return (rc); 9667 } 9668 9669 int 9670 uld_active(struct adapter *sc, int uld_id) 9671 { 9672 9673 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 9674 9675 return (isset(&sc->active_ulds, uld_id)); 9676 } 9677 #endif 9678 9679 /* 9680 * t = ptr to tunable. 9681 * nc = number of CPUs. 9682 * c = compiled in default for that tunable. 9683 */ 9684 static void 9685 calculate_nqueues(int *t, int nc, const int c) 9686 { 9687 int nq; 9688 9689 if (*t > 0) 9690 return; 9691 nq = *t < 0 ? -*t : c; 9692 *t = min(nc, nq); 9693 } 9694 9695 /* 9696 * Come up with reasonable defaults for some of the tunables, provided they're 9697 * not set by the user (in which case we'll use the values as is). 9698 */ 9699 static void 9700 tweak_tunables(void) 9701 { 9702 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 9703 9704 if (t4_ntxq < 1) { 9705 #ifdef RSS 9706 t4_ntxq = rss_getnumbuckets(); 9707 #else 9708 calculate_nqueues(&t4_ntxq, nc, NTXQ); 9709 #endif 9710 } 9711 9712 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 9713 9714 if (t4_nrxq < 1) { 9715 #ifdef RSS 9716 t4_nrxq = rss_getnumbuckets(); 9717 #else 9718 calculate_nqueues(&t4_nrxq, nc, NRXQ); 9719 #endif 9720 } 9721 9722 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 9723 9724 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 9725 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 9726 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 9727 #endif 9728 #ifdef TCP_OFFLOAD 9729 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 9730 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 9731 9732 if (t4_toecaps_allowed == -1) 9733 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 9734 9735 if (t4_rdmacaps_allowed == -1) { 9736 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 9737 FW_CAPS_CONFIG_RDMA_RDMAC; 9738 } 9739 9740 if (t4_iscsicaps_allowed == -1) { 9741 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 9742 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 9743 FW_CAPS_CONFIG_ISCSI_T10DIF; 9744 } 9745 9746 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 9747 t4_tmr_idx_ofld = TMR_IDX_OFLD; 9748 9749 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 9750 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 9751 #else 9752 if (t4_toecaps_allowed == -1) 9753 t4_toecaps_allowed = 0; 9754 9755 if (t4_rdmacaps_allowed == -1) 9756 t4_rdmacaps_allowed = 0; 9757 9758 if (t4_iscsicaps_allowed == -1) 9759 t4_iscsicaps_allowed = 0; 9760 #endif 9761 9762 #ifdef DEV_NETMAP 9763 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 9764 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 9765 #endif 9766 9767 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 9768 t4_tmr_idx = TMR_IDX; 9769 9770 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 9771 t4_pktc_idx = PKTC_IDX; 9772 9773 if (t4_qsize_txq < 128) 9774 t4_qsize_txq = 128; 9775 9776 if (t4_qsize_rxq < 128) 9777 t4_qsize_rxq = 128; 9778 while (t4_qsize_rxq & 7) 9779 t4_qsize_rxq++; 9780 9781 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 9782 9783 /* 9784 * Number of VIs to create per-port. The first VI is the "main" regular 9785 * VI for the port. The rest are additional virtual interfaces on the 9786 * same physical port. Note that the main VI does not have native 9787 * netmap support but the extra VIs do. 9788 * 9789 * Limit the number of VIs per port to the number of available 9790 * MAC addresses per port. 9791 */ 9792 if (t4_num_vis < 1) 9793 t4_num_vis = 1; 9794 if (t4_num_vis > nitems(vi_mac_funcs)) { 9795 t4_num_vis = nitems(vi_mac_funcs); 9796 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 9797 } 9798 9799 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 9800 pcie_relaxed_ordering = 1; 9801 #if defined(__i386__) || defined(__amd64__) 9802 if (cpu_vendor_id == CPU_VENDOR_INTEL) 9803 pcie_relaxed_ordering = 0; 9804 #endif 9805 } 9806 } 9807 9808 #ifdef DDB 9809 static void 9810 t4_dump_tcb(struct adapter *sc, int tid) 9811 { 9812 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 9813 9814 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 9815 save = t4_read_reg(sc, reg); 9816 base = sc->memwin[2].mw_base; 9817 9818 /* Dump TCB for the tid */ 9819 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9820 tcb_addr += tid * TCB_SIZE; 9821 9822 if (is_t4(sc)) { 9823 pf = 0; 9824 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 9825 } else { 9826 pf = V_PFNUM(sc->pf); 9827 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 9828 } 9829 t4_write_reg(sc, reg, win_pos | pf); 9830 t4_read_reg(sc, reg); 9831 9832 off = tcb_addr - win_pos; 9833 for (i = 0; i < 4; i++) { 9834 uint32_t buf[8]; 9835 for (j = 0; j < 8; j++, off += 4) 9836 buf[j] = htonl(t4_read_reg(sc, base + off)); 9837 9838 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 9839 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 9840 buf[7]); 9841 } 9842 9843 t4_write_reg(sc, reg, save); 9844 t4_read_reg(sc, reg); 9845 } 9846 9847 static void 9848 t4_dump_devlog(struct adapter *sc) 9849 { 9850 struct devlog_params *dparams = &sc->params.devlog; 9851 struct fw_devlog_e e; 9852 int i, first, j, m, nentries, rc; 9853 uint64_t ftstamp = UINT64_MAX; 9854 9855 if (dparams->start == 0) { 9856 db_printf("devlog params not valid\n"); 9857 return; 9858 } 9859 9860 nentries = dparams->size / sizeof(struct fw_devlog_e); 9861 m = fwmtype_to_hwmtype(dparams->memtype); 9862 9863 /* Find the first entry. */ 9864 first = -1; 9865 for (i = 0; i < nentries && !db_pager_quit; i++) { 9866 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9867 sizeof(e), (void *)&e); 9868 if (rc != 0) 9869 break; 9870 9871 if (e.timestamp == 0) 9872 break; 9873 9874 e.timestamp = be64toh(e.timestamp); 9875 if (e.timestamp < ftstamp) { 9876 ftstamp = e.timestamp; 9877 first = i; 9878 } 9879 } 9880 9881 if (first == -1) 9882 return; 9883 9884 i = first; 9885 do { 9886 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9887 sizeof(e), (void *)&e); 9888 if (rc != 0) 9889 return; 9890 9891 if (e.timestamp == 0) 9892 return; 9893 9894 e.timestamp = be64toh(e.timestamp); 9895 e.seqno = be32toh(e.seqno); 9896 for (j = 0; j < 8; j++) 9897 e.params[j] = be32toh(e.params[j]); 9898 9899 db_printf("%10d %15ju %8s %8s ", 9900 e.seqno, e.timestamp, 9901 (e.level < nitems(devlog_level_strings) ? 9902 devlog_level_strings[e.level] : "UNKNOWN"), 9903 (e.facility < nitems(devlog_facility_strings) ? 9904 devlog_facility_strings[e.facility] : "UNKNOWN")); 9905 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 9906 e.params[3], e.params[4], e.params[5], e.params[6], 9907 e.params[7]); 9908 9909 if (++i == nentries) 9910 i = 0; 9911 } while (i != first && !db_pager_quit); 9912 } 9913 9914 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 9915 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 9916 9917 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 9918 { 9919 device_t dev; 9920 int t; 9921 bool valid; 9922 9923 valid = false; 9924 t = db_read_token(); 9925 if (t == tIDENT) { 9926 dev = device_lookup_by_name(db_tok_string); 9927 valid = true; 9928 } 9929 db_skip_to_eol(); 9930 if (!valid) { 9931 db_printf("usage: show t4 devlog <nexus>\n"); 9932 return; 9933 } 9934 9935 if (dev == NULL) { 9936 db_printf("device not found\n"); 9937 return; 9938 } 9939 9940 t4_dump_devlog(device_get_softc(dev)); 9941 } 9942 9943 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 9944 { 9945 device_t dev; 9946 int radix, tid, t; 9947 bool valid; 9948 9949 valid = false; 9950 radix = db_radix; 9951 db_radix = 10; 9952 t = db_read_token(); 9953 if (t == tIDENT) { 9954 dev = device_lookup_by_name(db_tok_string); 9955 t = db_read_token(); 9956 if (t == tNUMBER) { 9957 tid = db_tok_number; 9958 valid = true; 9959 } 9960 } 9961 db_radix = radix; 9962 db_skip_to_eol(); 9963 if (!valid) { 9964 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 9965 return; 9966 } 9967 9968 if (dev == NULL) { 9969 db_printf("device not found\n"); 9970 return; 9971 } 9972 if (tid < 0) { 9973 db_printf("invalid tid\n"); 9974 return; 9975 } 9976 9977 t4_dump_tcb(device_get_softc(dev), tid); 9978 } 9979 #endif 9980 9981 /* 9982 * Borrowed from cesa_prep_aes_key(). 9983 * 9984 * NB: The crypto engine wants the words in the decryption key in reverse 9985 * order. 9986 */ 9987 void 9988 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 9989 { 9990 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 9991 uint32_t *dkey; 9992 int i; 9993 9994 rijndaelKeySetupEnc(ek, enc_key, kbits); 9995 dkey = dec_key; 9996 dkey += (kbits / 8) / 4; 9997 9998 switch (kbits) { 9999 case 128: 10000 for (i = 0; i < 4; i++) 10001 *--dkey = htobe32(ek[4 * 10 + i]); 10002 break; 10003 case 192: 10004 for (i = 0; i < 2; i++) 10005 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10006 for (i = 0; i < 4; i++) 10007 *--dkey = htobe32(ek[4 * 12 + i]); 10008 break; 10009 case 256: 10010 for (i = 0; i < 4; i++) 10011 *--dkey = htobe32(ek[4 * 13 + i]); 10012 for (i = 0; i < 4; i++) 10013 *--dkey = htobe32(ek[4 * 14 + i]); 10014 break; 10015 } 10016 MPASS(dkey == dec_key); 10017 } 10018 10019 static struct sx mlu; /* mod load unload */ 10020 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10021 10022 static int 10023 mod_event(module_t mod, int cmd, void *arg) 10024 { 10025 int rc = 0; 10026 static int loaded = 0; 10027 10028 switch (cmd) { 10029 case MOD_LOAD: 10030 sx_xlock(&mlu); 10031 if (loaded++ == 0) { 10032 t4_sge_modload(); 10033 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10034 t4_filter_rpl, CPL_COOKIE_FILTER); 10035 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 10036 do_l2t_write_rpl, CPL_COOKIE_FILTER); 10037 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 10038 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 10039 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10040 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 10041 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 10042 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10043 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10044 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10045 sx_init(&t4_list_lock, "T4/T5 adapters"); 10046 SLIST_INIT(&t4_list); 10047 #ifdef TCP_OFFLOAD 10048 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10049 SLIST_INIT(&t4_uld_list); 10050 #endif 10051 t4_tracer_modload(); 10052 tweak_tunables(); 10053 } 10054 sx_xunlock(&mlu); 10055 break; 10056 10057 case MOD_UNLOAD: 10058 sx_xlock(&mlu); 10059 if (--loaded == 0) { 10060 int tries; 10061 10062 sx_slock(&t4_list_lock); 10063 if (!SLIST_EMPTY(&t4_list)) { 10064 rc = EBUSY; 10065 sx_sunlock(&t4_list_lock); 10066 goto done_unload; 10067 } 10068 #ifdef TCP_OFFLOAD 10069 sx_slock(&t4_uld_list_lock); 10070 if (!SLIST_EMPTY(&t4_uld_list)) { 10071 rc = EBUSY; 10072 sx_sunlock(&t4_uld_list_lock); 10073 sx_sunlock(&t4_list_lock); 10074 goto done_unload; 10075 } 10076 #endif 10077 tries = 0; 10078 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10079 uprintf("%ju clusters with custom free routine " 10080 "still is use.\n", t4_sge_extfree_refs()); 10081 pause("t4unload", 2 * hz); 10082 } 10083 #ifdef TCP_OFFLOAD 10084 sx_sunlock(&t4_uld_list_lock); 10085 #endif 10086 sx_sunlock(&t4_list_lock); 10087 10088 if (t4_sge_extfree_refs() == 0) { 10089 t4_tracer_modunload(); 10090 #ifdef TCP_OFFLOAD 10091 sx_destroy(&t4_uld_list_lock); 10092 #endif 10093 sx_destroy(&t4_list_lock); 10094 t4_sge_modunload(); 10095 loaded = 0; 10096 } else { 10097 rc = EBUSY; 10098 loaded++; /* undo earlier decrement */ 10099 } 10100 } 10101 done_unload: 10102 sx_xunlock(&mlu); 10103 break; 10104 } 10105 10106 return (rc); 10107 } 10108 10109 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10110 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10111 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10112 10113 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10114 MODULE_VERSION(t4nex, 1); 10115 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10116 #ifdef DEV_NETMAP 10117 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10118 #endif /* DEV_NETMAP */ 10119 10120 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10121 MODULE_VERSION(t5nex, 1); 10122 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10123 #ifdef DEV_NETMAP 10124 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10125 #endif /* DEV_NETMAP */ 10126 10127 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10128 MODULE_VERSION(t6nex, 1); 10129 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10130 #ifdef DEV_NETMAP 10131 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10132 #endif /* DEV_NETMAP */ 10133 10134 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10135 MODULE_VERSION(cxgbe, 1); 10136 10137 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10138 MODULE_VERSION(cxl, 1); 10139 10140 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10141 MODULE_VERSION(cc, 1); 10142 10143 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10144 MODULE_VERSION(vcxgbe, 1); 10145 10146 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10147 MODULE_VERSION(vcxl, 1); 10148 10149 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10150 MODULE_VERSION(vcc, 1); 10151