1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_kern_tls.h" 37 #include "opt_ratelimit.h" 38 #include "opt_rss.h" 39 40 #include <sys/param.h> 41 #include <sys/conf.h> 42 #include <sys/priv.h> 43 #include <sys/kernel.h> 44 #include <sys/bus.h> 45 #include <sys/eventhandler.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/queue.h> 49 #include <sys/taskqueue.h> 50 #include <sys/pciio.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pci_private.h> 54 #include <sys/firmware.h> 55 #include <sys/sbuf.h> 56 #include <sys/smp.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/sysctl.h> 60 #include <net/ethernet.h> 61 #include <net/if.h> 62 #include <net/if_types.h> 63 #include <net/if_dl.h> 64 #include <net/if_vlan_var.h> 65 #ifdef RSS 66 #include <net/rss_config.h> 67 #endif 68 #include <netinet/in.h> 69 #include <netinet/ip.h> 70 #ifdef KERN_TLS 71 #include <netinet/tcp_seq.h> 72 #endif 73 #if defined(__i386__) || defined(__amd64__) 74 #include <machine/md_var.h> 75 #include <machine/cputypes.h> 76 #include <vm/vm.h> 77 #include <vm/pmap.h> 78 #endif 79 #ifdef DDB 80 #include <ddb/ddb.h> 81 #include <ddb/db_lex.h> 82 #endif 83 84 #include "common/common.h" 85 #include "common/t4_msg.h" 86 #include "common/t4_regs.h" 87 #include "common/t4_regs_values.h" 88 #include "cudbg/cudbg.h" 89 #include "t4_clip.h" 90 #include "t4_ioctl.h" 91 #include "t4_l2t.h" 92 #include "t4_mp_ring.h" 93 #include "t4_if.h" 94 #include "t4_smt.h" 95 96 /* T4 bus driver interface */ 97 static int t4_probe(device_t); 98 static int t4_attach(device_t); 99 static int t4_detach(device_t); 100 static int t4_child_location(device_t, device_t, struct sbuf *); 101 static int t4_ready(device_t); 102 static int t4_read_port_device(device_t, int, device_t *); 103 static int t4_suspend(device_t); 104 static int t4_resume(device_t); 105 static int t4_reset_prepare(device_t, device_t); 106 static int t4_reset_post(device_t, device_t); 107 static device_method_t t4_methods[] = { 108 DEVMETHOD(device_probe, t4_probe), 109 DEVMETHOD(device_attach, t4_attach), 110 DEVMETHOD(device_detach, t4_detach), 111 DEVMETHOD(device_suspend, t4_suspend), 112 DEVMETHOD(device_resume, t4_resume), 113 114 DEVMETHOD(bus_child_location, t4_child_location), 115 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 116 DEVMETHOD(bus_reset_post, t4_reset_post), 117 118 DEVMETHOD(t4_is_main_ready, t4_ready), 119 DEVMETHOD(t4_read_port_device, t4_read_port_device), 120 121 DEVMETHOD_END 122 }; 123 static driver_t t4_driver = { 124 "t4nex", 125 t4_methods, 126 sizeof(struct adapter) 127 }; 128 129 130 /* T4 port (cxgbe) interface */ 131 static int cxgbe_probe(device_t); 132 static int cxgbe_attach(device_t); 133 static int cxgbe_detach(device_t); 134 device_method_t cxgbe_methods[] = { 135 DEVMETHOD(device_probe, cxgbe_probe), 136 DEVMETHOD(device_attach, cxgbe_attach), 137 DEVMETHOD(device_detach, cxgbe_detach), 138 { 0, 0 } 139 }; 140 static driver_t cxgbe_driver = { 141 "cxgbe", 142 cxgbe_methods, 143 sizeof(struct port_info) 144 }; 145 146 /* T4 VI (vcxgbe) interface */ 147 static int vcxgbe_probe(device_t); 148 static int vcxgbe_attach(device_t); 149 static int vcxgbe_detach(device_t); 150 static device_method_t vcxgbe_methods[] = { 151 DEVMETHOD(device_probe, vcxgbe_probe), 152 DEVMETHOD(device_attach, vcxgbe_attach), 153 DEVMETHOD(device_detach, vcxgbe_detach), 154 { 0, 0 } 155 }; 156 static driver_t vcxgbe_driver = { 157 "vcxgbe", 158 vcxgbe_methods, 159 sizeof(struct vi_info) 160 }; 161 162 static d_ioctl_t t4_ioctl; 163 164 static struct cdevsw t4_cdevsw = { 165 .d_version = D_VERSION, 166 .d_ioctl = t4_ioctl, 167 .d_name = "t4nex", 168 }; 169 170 /* T5 bus driver interface */ 171 static int t5_probe(device_t); 172 static device_method_t t5_methods[] = { 173 DEVMETHOD(device_probe, t5_probe), 174 DEVMETHOD(device_attach, t4_attach), 175 DEVMETHOD(device_detach, t4_detach), 176 DEVMETHOD(device_suspend, t4_suspend), 177 DEVMETHOD(device_resume, t4_resume), 178 179 DEVMETHOD(bus_child_location, t4_child_location), 180 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 181 DEVMETHOD(bus_reset_post, t4_reset_post), 182 183 DEVMETHOD(t4_is_main_ready, t4_ready), 184 DEVMETHOD(t4_read_port_device, t4_read_port_device), 185 186 DEVMETHOD_END 187 }; 188 static driver_t t5_driver = { 189 "t5nex", 190 t5_methods, 191 sizeof(struct adapter) 192 }; 193 194 195 /* T5 port (cxl) interface */ 196 static driver_t cxl_driver = { 197 "cxl", 198 cxgbe_methods, 199 sizeof(struct port_info) 200 }; 201 202 /* T5 VI (vcxl) interface */ 203 static driver_t vcxl_driver = { 204 "vcxl", 205 vcxgbe_methods, 206 sizeof(struct vi_info) 207 }; 208 209 /* T6 bus driver interface */ 210 static int t6_probe(device_t); 211 static device_method_t t6_methods[] = { 212 DEVMETHOD(device_probe, t6_probe), 213 DEVMETHOD(device_attach, t4_attach), 214 DEVMETHOD(device_detach, t4_detach), 215 DEVMETHOD(device_suspend, t4_suspend), 216 DEVMETHOD(device_resume, t4_resume), 217 218 DEVMETHOD(bus_child_location, t4_child_location), 219 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 220 DEVMETHOD(bus_reset_post, t4_reset_post), 221 222 DEVMETHOD(t4_is_main_ready, t4_ready), 223 DEVMETHOD(t4_read_port_device, t4_read_port_device), 224 225 DEVMETHOD_END 226 }; 227 static driver_t t6_driver = { 228 "t6nex", 229 t6_methods, 230 sizeof(struct adapter) 231 }; 232 233 234 /* T6 port (cc) interface */ 235 static driver_t cc_driver = { 236 "cc", 237 cxgbe_methods, 238 sizeof(struct port_info) 239 }; 240 241 /* T6 VI (vcc) interface */ 242 static driver_t vcc_driver = { 243 "vcc", 244 vcxgbe_methods, 245 sizeof(struct vi_info) 246 }; 247 248 /* ifnet interface */ 249 static void cxgbe_init(void *); 250 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 251 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 252 static void cxgbe_qflush(struct ifnet *); 253 #if defined(KERN_TLS) || defined(RATELIMIT) 254 static int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 255 struct m_snd_tag **); 256 #endif 257 258 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 259 260 /* 261 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 262 * then ADAPTER_LOCK, then t4_uld_list_lock. 263 */ 264 static struct sx t4_list_lock; 265 SLIST_HEAD(, adapter) t4_list; 266 #ifdef TCP_OFFLOAD 267 static struct sx t4_uld_list_lock; 268 SLIST_HEAD(, uld_info) t4_uld_list; 269 #endif 270 271 /* 272 * Tunables. See tweak_tunables() too. 273 * 274 * Each tunable is set to a default value here if it's known at compile-time. 275 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 276 * provide a reasonable default (upto n) when the driver is loaded. 277 * 278 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 279 * T5 are under hw.cxl. 280 */ 281 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 282 "cxgbe(4) parameters"); 283 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 284 "cxgbe(4) T5+ parameters"); 285 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 286 "cxgbe(4) TOE parameters"); 287 288 /* 289 * Number of queues for tx and rx, NIC and offload. 290 */ 291 #define NTXQ 16 292 int t4_ntxq = -NTXQ; 293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 294 "Number of TX queues per port"); 295 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 296 297 #define NRXQ 8 298 int t4_nrxq = -NRXQ; 299 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 300 "Number of RX queues per port"); 301 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 302 303 #define NTXQ_VI 1 304 static int t4_ntxq_vi = -NTXQ_VI; 305 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 306 "Number of TX queues per VI"); 307 308 #define NRXQ_VI 1 309 static int t4_nrxq_vi = -NRXQ_VI; 310 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 311 "Number of RX queues per VI"); 312 313 static int t4_rsrv_noflowq = 0; 314 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 315 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 316 317 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 318 #define NOFLDTXQ 8 319 static int t4_nofldtxq = -NOFLDTXQ; 320 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 321 "Number of offload TX queues per port"); 322 323 #define NOFLDRXQ 2 324 static int t4_nofldrxq = -NOFLDRXQ; 325 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 326 "Number of offload RX queues per port"); 327 328 #define NOFLDTXQ_VI 1 329 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 330 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 331 "Number of offload TX queues per VI"); 332 333 #define NOFLDRXQ_VI 1 334 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 335 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 336 "Number of offload RX queues per VI"); 337 338 #define TMR_IDX_OFLD 1 339 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 340 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 341 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 342 343 #define PKTC_IDX_OFLD (-1) 344 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 345 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 346 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 347 348 /* 0 means chip/fw default, non-zero number is value in microseconds */ 349 static u_long t4_toe_keepalive_idle = 0; 350 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 351 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 352 353 /* 0 means chip/fw default, non-zero number is value in microseconds */ 354 static u_long t4_toe_keepalive_interval = 0; 355 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 356 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 357 358 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 359 static int t4_toe_keepalive_count = 0; 360 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 361 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 362 363 /* 0 means chip/fw default, non-zero number is value in microseconds */ 364 static u_long t4_toe_rexmt_min = 0; 365 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 367 368 /* 0 means chip/fw default, non-zero number is value in microseconds */ 369 static u_long t4_toe_rexmt_max = 0; 370 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 371 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 372 373 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 374 static int t4_toe_rexmt_count = 0; 375 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 377 378 /* -1 means chip/fw default, other values are raw backoff values to use */ 379 static int t4_toe_rexmt_backoff[16] = { 380 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 381 }; 382 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, 383 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 384 "cxgbe(4) TOE retransmit backoff values"); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[0], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[1], 0, ""); 389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 390 &t4_toe_rexmt_backoff[2], 0, ""); 391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 392 &t4_toe_rexmt_backoff[3], 0, ""); 393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 394 &t4_toe_rexmt_backoff[4], 0, ""); 395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 396 &t4_toe_rexmt_backoff[5], 0, ""); 397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 398 &t4_toe_rexmt_backoff[6], 0, ""); 399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 400 &t4_toe_rexmt_backoff[7], 0, ""); 401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 402 &t4_toe_rexmt_backoff[8], 0, ""); 403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 404 &t4_toe_rexmt_backoff[9], 0, ""); 405 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 406 &t4_toe_rexmt_backoff[10], 0, ""); 407 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 408 &t4_toe_rexmt_backoff[11], 0, ""); 409 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 410 &t4_toe_rexmt_backoff[12], 0, ""); 411 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 412 &t4_toe_rexmt_backoff[13], 0, ""); 413 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 414 &t4_toe_rexmt_backoff[14], 0, ""); 415 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 416 &t4_toe_rexmt_backoff[15], 0, ""); 417 418 static int t4_toe_tls_rx_timeout = 5; 419 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, tls_rx_timeout, CTLFLAG_RDTUN, 420 &t4_toe_tls_rx_timeout, 0, 421 "Timeout in seconds to downgrade TLS sockets to plain TOE"); 422 #endif 423 424 #ifdef DEV_NETMAP 425 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */ 426 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */ 427 static int t4_native_netmap = NN_EXTRA_VI; 428 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap, 429 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs"); 430 431 #define NNMTXQ 8 432 static int t4_nnmtxq = -NNMTXQ; 433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0, 434 "Number of netmap TX queues"); 435 436 #define NNMRXQ 8 437 static int t4_nnmrxq = -NNMRXQ; 438 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0, 439 "Number of netmap RX queues"); 440 441 #define NNMTXQ_VI 2 442 static int t4_nnmtxq_vi = -NNMTXQ_VI; 443 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 444 "Number of netmap TX queues per VI"); 445 446 #define NNMRXQ_VI 2 447 static int t4_nnmrxq_vi = -NNMRXQ_VI; 448 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 449 "Number of netmap RX queues per VI"); 450 #endif 451 452 /* 453 * Holdoff parameters for ports. 454 */ 455 #define TMR_IDX 1 456 int t4_tmr_idx = TMR_IDX; 457 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 458 0, "Holdoff timer index"); 459 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 460 461 #define PKTC_IDX (-1) 462 int t4_pktc_idx = PKTC_IDX; 463 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 464 0, "Holdoff packet counter index"); 465 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 466 467 /* 468 * Size (# of entries) of each tx and rx queue. 469 */ 470 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 471 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 472 "Number of descriptors in each TX queue"); 473 474 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 475 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 476 "Number of descriptors in each RX queue"); 477 478 /* 479 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 480 */ 481 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 482 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 483 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 484 485 /* 486 * Configuration file. All the _CF names here are special. 487 */ 488 #define DEFAULT_CF "default" 489 #define BUILTIN_CF "built-in" 490 #define FLASH_CF "flash" 491 #define UWIRE_CF "uwire" 492 #define FPGA_CF "fpga" 493 static char t4_cfg_file[32] = DEFAULT_CF; 494 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 495 sizeof(t4_cfg_file), "Firmware configuration file"); 496 497 /* 498 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 499 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 500 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 501 * mark or when signalled to do so, 0 to never emit PAUSE. 502 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 503 * negotiated settings will override rx_pause/tx_pause. 504 * Otherwise rx_pause/tx_pause are applied forcibly. 505 */ 506 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 507 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 508 &t4_pause_settings, 0, 509 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 510 511 /* 512 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 513 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 514 * 0 to disable FEC. 515 */ 516 static int t4_fec = -1; 517 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 518 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 519 520 /* 521 * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it 522 * issues to the firmware. If the firmware doesn't support FORCE_FEC then the 523 * driver runs as if this is set to 0. 524 * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay. 525 * 0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the 526 * transceiver. Multiple FEC bits may not be okay but will be passed on to 527 * the firmware anyway (may result in l1cfg errors with old firmwares). 528 * 1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO 529 * means set all FEC bits that are valid for the speed. 530 */ 531 static int t4_force_fec = -1; 532 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0, 533 "Controls the use of FORCE_FEC bit in L1 configuration."); 534 535 /* 536 * Link autonegotiation. 537 * -1 to run with the firmware default. 538 * 0 to disable. 539 * 1 to enable. 540 */ 541 static int t4_autoneg = -1; 542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 543 "Link autonegotiation"); 544 545 /* 546 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 547 * encouraged respectively). '-n' is the same as 'n' except the firmware 548 * version used in the checks is read from the firmware bundled with the driver. 549 */ 550 static int t4_fw_install = 1; 551 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 552 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 553 554 /* 555 * ASIC features that will be used. Disable the ones you don't want so that the 556 * chip resources aren't wasted on features that will not be used. 557 */ 558 static int t4_nbmcaps_allowed = 0; 559 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 560 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 561 562 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 563 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 564 &t4_linkcaps_allowed, 0, "Default link capabilities"); 565 566 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 567 FW_CAPS_CONFIG_SWITCH_EGRESS; 568 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 569 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 570 571 #ifdef RATELIMIT 572 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 573 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 574 #else 575 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 576 FW_CAPS_CONFIG_NIC_HASHFILTER; 577 #endif 578 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 579 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 580 581 static int t4_toecaps_allowed = -1; 582 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 583 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 584 585 static int t4_rdmacaps_allowed = -1; 586 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 587 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 588 589 static int t4_cryptocaps_allowed = -1; 590 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 591 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 592 593 static int t4_iscsicaps_allowed = -1; 594 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 595 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 596 597 static int t4_fcoecaps_allowed = 0; 598 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 599 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 600 601 static int t5_write_combine = 0; 602 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 603 0, "Use WC instead of UC for BAR2"); 604 605 static int t4_num_vis = 1; 606 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 607 "Number of VIs per port"); 608 609 /* 610 * PCIe Relaxed Ordering. 611 * -1: driver should figure out a good value. 612 * 0: disable RO. 613 * 1: enable RO. 614 * 2: leave RO alone. 615 */ 616 static int pcie_relaxed_ordering = -1; 617 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 618 &pcie_relaxed_ordering, 0, 619 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 620 621 static int t4_panic_on_fatal_err = 0; 622 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN, 623 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 624 625 static int t4_reset_on_fatal_err = 0; 626 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN, 627 &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors"); 628 629 static int t4_clock_gate_on_suspend = 0; 630 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN, 631 &t4_clock_gate_on_suspend, 0, "gate the clock on suspend"); 632 633 static int t4_tx_vm_wr = 0; 634 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0, 635 "Use VM work requests to transmit packets."); 636 637 /* 638 * Set to non-zero to enable the attack filter. A packet that matches any of 639 * these conditions will get dropped on ingress: 640 * 1) IP && source address == destination address. 641 * 2) TCP/IP && source address is not a unicast address. 642 * 3) TCP/IP && destination address is not a unicast address. 643 * 4) IP && source address is loopback (127.x.y.z). 644 * 5) IP && destination address is loopback (127.x.y.z). 645 * 6) IPv6 && source address == destination address. 646 * 7) IPv6 && source address is not a unicast address. 647 * 8) IPv6 && source address is loopback (::1/128). 648 * 9) IPv6 && destination address is loopback (::1/128). 649 * 10) IPv6 && source address is unspecified (::/128). 650 * 11) IPv6 && destination address is unspecified (::/128). 651 * 12) TCP/IPv6 && source address is multicast (ff00::/8). 652 * 13) TCP/IPv6 && destination address is multicast (ff00::/8). 653 */ 654 static int t4_attack_filter = 0; 655 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN, 656 &t4_attack_filter, 0, "Drop suspicious traffic"); 657 658 static int t4_drop_ip_fragments = 0; 659 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN, 660 &t4_drop_ip_fragments, 0, "Drop IP fragments"); 661 662 static int t4_drop_pkts_with_l2_errors = 1; 663 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN, 664 &t4_drop_pkts_with_l2_errors, 0, 665 "Drop all frames with Layer 2 length or checksum errors"); 666 667 static int t4_drop_pkts_with_l3_errors = 0; 668 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN, 669 &t4_drop_pkts_with_l3_errors, 0, 670 "Drop all frames with IP version, length, or checksum errors"); 671 672 static int t4_drop_pkts_with_l4_errors = 0; 673 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN, 674 &t4_drop_pkts_with_l4_errors, 0, 675 "Drop all frames with Layer 4 length, checksum, or other errors"); 676 677 #ifdef TCP_OFFLOAD 678 /* 679 * TOE tunables. 680 */ 681 static int t4_cop_managed_offloading = 0; 682 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 683 &t4_cop_managed_offloading, 0, 684 "COP (Connection Offload Policy) controls all TOE offload"); 685 #endif 686 687 #ifdef KERN_TLS 688 /* 689 * This enables KERN_TLS for all adapters if set. 690 */ 691 static int t4_kern_tls = 0; 692 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0, 693 "Enable KERN_TLS mode for T6 adapters"); 694 695 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 696 "cxgbe(4) KERN_TLS parameters"); 697 698 static int t4_tls_inline_keys = 0; 699 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN, 700 &t4_tls_inline_keys, 0, 701 "Always pass TLS keys in work requests (1) or attempt to store TLS keys " 702 "in card memory."); 703 704 static int t4_tls_combo_wrs = 0; 705 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs, 706 0, "Attempt to combine TCB field updates with TLS record work requests."); 707 #endif 708 709 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 710 static int vi_mac_funcs[] = { 711 FW_VI_FUNC_ETH, 712 FW_VI_FUNC_OFLD, 713 FW_VI_FUNC_IWARP, 714 FW_VI_FUNC_OPENISCSI, 715 FW_VI_FUNC_OPENFCOE, 716 FW_VI_FUNC_FOISCSI, 717 FW_VI_FUNC_FOFCOE, 718 }; 719 720 struct intrs_and_queues { 721 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 722 uint16_t num_vis; /* number of VIs for each port */ 723 uint16_t nirq; /* Total # of vectors */ 724 uint16_t ntxq; /* # of NIC txq's for each port */ 725 uint16_t nrxq; /* # of NIC rxq's for each port */ 726 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 727 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 728 uint16_t nnmtxq; /* # of netmap txq's */ 729 uint16_t nnmrxq; /* # of netmap rxq's */ 730 731 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 732 uint16_t ntxq_vi; /* # of NIC txq's */ 733 uint16_t nrxq_vi; /* # of NIC rxq's */ 734 uint16_t nofldtxq_vi; /* # of TOE txq's */ 735 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 736 uint16_t nnmtxq_vi; /* # of netmap txq's */ 737 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 738 }; 739 740 static void setup_memwin(struct adapter *); 741 static void position_memwin(struct adapter *, int, uint32_t); 742 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 743 static int fwmtype_to_hwmtype(int); 744 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 745 uint32_t *); 746 static int fixup_devlog_params(struct adapter *); 747 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 748 static int contact_firmware(struct adapter *); 749 static int partition_resources(struct adapter *); 750 static int get_params__pre_init(struct adapter *); 751 static int set_params__pre_init(struct adapter *); 752 static int get_params__post_init(struct adapter *); 753 static int set_params__post_init(struct adapter *); 754 static void t4_set_desc(struct adapter *); 755 static bool fixed_ifmedia(struct port_info *); 756 static void build_medialist(struct port_info *); 757 static void init_link_config(struct port_info *); 758 static int fixup_link_config(struct port_info *); 759 static int apply_link_config(struct port_info *); 760 static int cxgbe_init_synchronized(struct vi_info *); 761 static int cxgbe_uninit_synchronized(struct vi_info *); 762 static int adapter_full_init(struct adapter *); 763 static void adapter_full_uninit(struct adapter *); 764 static int vi_full_init(struct vi_info *); 765 static void vi_full_uninit(struct vi_info *); 766 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *); 767 static void quiesce_txq(struct sge_txq *); 768 static void quiesce_wrq(struct sge_wrq *); 769 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 770 static void quiesce_vi(struct vi_info *); 771 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 772 driver_intr_t *, void *, char *); 773 static int t4_free_irq(struct adapter *, struct irq *); 774 static void t4_init_atid_table(struct adapter *); 775 static void t4_free_atid_table(struct adapter *); 776 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 777 static void vi_refresh_stats(struct vi_info *); 778 static void cxgbe_refresh_stats(struct vi_info *); 779 static void cxgbe_tick(void *); 780 static void vi_tick(void *); 781 static void cxgbe_sysctls(struct port_info *); 782 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 783 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 784 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 785 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 786 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 787 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS); 788 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 789 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 790 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 791 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 792 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 793 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS); 794 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS); 795 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS); 796 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 797 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS); 798 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 799 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 800 static int sysctl_vdd(SYSCTL_HANDLER_ARGS); 801 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS); 802 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 803 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 804 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 805 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 806 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 807 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 808 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 809 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 810 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 811 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS); 812 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 813 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 814 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 815 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 816 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 817 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 818 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 819 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 820 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 821 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 822 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 823 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 824 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 825 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 826 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS); 827 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 828 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 829 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 830 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 831 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 832 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 833 static int sysctl_reset(SYSCTL_HANDLER_ARGS); 834 #ifdef TCP_OFFLOAD 835 static int sysctl_tls(SYSCTL_HANDLER_ARGS); 836 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 837 static int sysctl_tls_rx_timeout(SYSCTL_HANDLER_ARGS); 838 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 839 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 840 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 841 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 842 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 843 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 844 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 845 #endif 846 static int get_sge_context(struct adapter *, struct t4_sge_context *); 847 static int load_fw(struct adapter *, struct t4_data *); 848 static int load_cfg(struct adapter *, struct t4_data *); 849 static int load_boot(struct adapter *, struct t4_bootrom *); 850 static int load_bootcfg(struct adapter *, struct t4_data *); 851 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 852 static void free_offload_policy(struct t4_offload_policy *); 853 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 854 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 855 static int read_i2c(struct adapter *, struct t4_i2c_data *); 856 static int clear_stats(struct adapter *, u_int); 857 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *); 858 static int release_clip_addr(struct adapter *, struct t4_clip_addr *); 859 #ifdef TCP_OFFLOAD 860 static int toe_capability(struct vi_info *, bool); 861 static int t4_deactivate_all_uld(struct adapter *); 862 static void t4_async_event(struct adapter *); 863 #endif 864 #ifdef KERN_TLS 865 static int ktls_capability(struct adapter *, bool); 866 #endif 867 static int mod_event(module_t, int, void *); 868 static int notify_siblings(device_t, int); 869 static uint64_t vi_get_counter(struct ifnet *, ift_counter); 870 static uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 871 static void enable_vxlan_rx(struct adapter *); 872 static void reset_adapter_task(void *, int); 873 static void fatal_error_task(void *, int); 874 static void dump_devlog(struct adapter *); 875 static void dump_cim_regs(struct adapter *); 876 static void dump_cimla(struct adapter *); 877 878 struct { 879 uint16_t device; 880 char *desc; 881 } t4_pciids[] = { 882 {0xa000, "Chelsio Terminator 4 FPGA"}, 883 {0x4400, "Chelsio T440-dbg"}, 884 {0x4401, "Chelsio T420-CR"}, 885 {0x4402, "Chelsio T422-CR"}, 886 {0x4403, "Chelsio T440-CR"}, 887 {0x4404, "Chelsio T420-BCH"}, 888 {0x4405, "Chelsio T440-BCH"}, 889 {0x4406, "Chelsio T440-CH"}, 890 {0x4407, "Chelsio T420-SO"}, 891 {0x4408, "Chelsio T420-CX"}, 892 {0x4409, "Chelsio T420-BT"}, 893 {0x440a, "Chelsio T404-BT"}, 894 {0x440e, "Chelsio T440-LP-CR"}, 895 }, t5_pciids[] = { 896 {0xb000, "Chelsio Terminator 5 FPGA"}, 897 {0x5400, "Chelsio T580-dbg"}, 898 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 899 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 900 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 901 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 902 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 903 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 904 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 905 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 906 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 907 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 908 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 909 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 910 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 911 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 912 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 913 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 914 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 915 916 /* Custom */ 917 {0x5483, "Custom T540-CR"}, 918 {0x5484, "Custom T540-BT"}, 919 }, t6_pciids[] = { 920 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 921 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 922 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 923 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 924 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 925 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 926 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 927 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 928 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 929 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 930 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 931 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 932 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 933 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 934 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 935 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 936 937 /* Custom */ 938 {0x6480, "Custom T6225-CR"}, 939 {0x6481, "Custom T62100-CR"}, 940 {0x6482, "Custom T6225-CR"}, 941 {0x6483, "Custom T62100-CR"}, 942 {0x6484, "Custom T64100-CR"}, 943 {0x6485, "Custom T6240-SO"}, 944 {0x6486, "Custom T6225-SO-CR"}, 945 {0x6487, "Custom T6225-CR"}, 946 }; 947 948 #ifdef TCP_OFFLOAD 949 /* 950 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 951 * be exactly the same for both rxq and ofld_rxq. 952 */ 953 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 954 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 955 #endif 956 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 957 958 static int 959 t4_probe(device_t dev) 960 { 961 int i; 962 uint16_t v = pci_get_vendor(dev); 963 uint16_t d = pci_get_device(dev); 964 uint8_t f = pci_get_function(dev); 965 966 if (v != PCI_VENDOR_ID_CHELSIO) 967 return (ENXIO); 968 969 /* Attach only to PF0 of the FPGA */ 970 if (d == 0xa000 && f != 0) 971 return (ENXIO); 972 973 for (i = 0; i < nitems(t4_pciids); i++) { 974 if (d == t4_pciids[i].device) { 975 device_set_desc(dev, t4_pciids[i].desc); 976 return (BUS_PROBE_DEFAULT); 977 } 978 } 979 980 return (ENXIO); 981 } 982 983 static int 984 t5_probe(device_t dev) 985 { 986 int i; 987 uint16_t v = pci_get_vendor(dev); 988 uint16_t d = pci_get_device(dev); 989 uint8_t f = pci_get_function(dev); 990 991 if (v != PCI_VENDOR_ID_CHELSIO) 992 return (ENXIO); 993 994 /* Attach only to PF0 of the FPGA */ 995 if (d == 0xb000 && f != 0) 996 return (ENXIO); 997 998 for (i = 0; i < nitems(t5_pciids); i++) { 999 if (d == t5_pciids[i].device) { 1000 device_set_desc(dev, t5_pciids[i].desc); 1001 return (BUS_PROBE_DEFAULT); 1002 } 1003 } 1004 1005 return (ENXIO); 1006 } 1007 1008 static int 1009 t6_probe(device_t dev) 1010 { 1011 int i; 1012 uint16_t v = pci_get_vendor(dev); 1013 uint16_t d = pci_get_device(dev); 1014 1015 if (v != PCI_VENDOR_ID_CHELSIO) 1016 return (ENXIO); 1017 1018 for (i = 0; i < nitems(t6_pciids); i++) { 1019 if (d == t6_pciids[i].device) { 1020 device_set_desc(dev, t6_pciids[i].desc); 1021 return (BUS_PROBE_DEFAULT); 1022 } 1023 } 1024 1025 return (ENXIO); 1026 } 1027 1028 static void 1029 t5_attribute_workaround(device_t dev) 1030 { 1031 device_t root_port; 1032 uint32_t v; 1033 1034 /* 1035 * The T5 chips do not properly echo the No Snoop and Relaxed 1036 * Ordering attributes when replying to a TLP from a Root 1037 * Port. As a workaround, find the parent Root Port and 1038 * disable No Snoop and Relaxed Ordering. Note that this 1039 * affects all devices under this root port. 1040 */ 1041 root_port = pci_find_pcie_root_port(dev); 1042 if (root_port == NULL) { 1043 device_printf(dev, "Unable to find parent root port\n"); 1044 return; 1045 } 1046 1047 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 1048 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 1049 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 1050 0) 1051 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 1052 device_get_nameunit(root_port)); 1053 } 1054 1055 static const struct devnames devnames[] = { 1056 { 1057 .nexus_name = "t4nex", 1058 .ifnet_name = "cxgbe", 1059 .vi_ifnet_name = "vcxgbe", 1060 .pf03_drv_name = "t4iov", 1061 .vf_nexus_name = "t4vf", 1062 .vf_ifnet_name = "cxgbev" 1063 }, { 1064 .nexus_name = "t5nex", 1065 .ifnet_name = "cxl", 1066 .vi_ifnet_name = "vcxl", 1067 .pf03_drv_name = "t5iov", 1068 .vf_nexus_name = "t5vf", 1069 .vf_ifnet_name = "cxlv" 1070 }, { 1071 .nexus_name = "t6nex", 1072 .ifnet_name = "cc", 1073 .vi_ifnet_name = "vcc", 1074 .pf03_drv_name = "t6iov", 1075 .vf_nexus_name = "t6vf", 1076 .vf_ifnet_name = "ccv" 1077 } 1078 }; 1079 1080 void 1081 t4_init_devnames(struct adapter *sc) 1082 { 1083 int id; 1084 1085 id = chip_id(sc); 1086 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 1087 sc->names = &devnames[id - CHELSIO_T4]; 1088 else { 1089 device_printf(sc->dev, "chip id %d is not supported.\n", id); 1090 sc->names = NULL; 1091 } 1092 } 1093 1094 static int 1095 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 1096 { 1097 const char *parent, *name; 1098 long value; 1099 int line, unit; 1100 1101 line = 0; 1102 parent = device_get_nameunit(sc->dev); 1103 name = sc->names->ifnet_name; 1104 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 1105 if (resource_long_value(name, unit, "port", &value) == 0 && 1106 value == pi->port_id) 1107 return (unit); 1108 } 1109 return (-1); 1110 } 1111 1112 static void 1113 t4_calibration(void *arg) 1114 { 1115 struct adapter *sc; 1116 struct clock_sync *cur, *nex; 1117 uint64_t hw; 1118 sbintime_t sbt; 1119 int next_up; 1120 1121 sc = (struct adapter *)arg; 1122 1123 KASSERT((hw_off_limits(sc) == 0), ("hw_off_limits at t4_calibration")); 1124 hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO); 1125 sbt = sbinuptime(); 1126 1127 cur = &sc->cal_info[sc->cal_current]; 1128 next_up = (sc->cal_current + 1) % CNT_CAL_INFO; 1129 nex = &sc->cal_info[next_up]; 1130 if (__predict_false(sc->cal_count == 0)) { 1131 /* First time in, just get the values in */ 1132 cur->hw_cur = hw; 1133 cur->sbt_cur = sbt; 1134 sc->cal_count++; 1135 goto done; 1136 } 1137 1138 if (cur->hw_cur == hw) { 1139 /* The clock is not advancing? */ 1140 sc->cal_count = 0; 1141 atomic_store_rel_int(&cur->gen, 0); 1142 goto done; 1143 } 1144 1145 seqc_write_begin(&nex->gen); 1146 nex->hw_prev = cur->hw_cur; 1147 nex->sbt_prev = cur->sbt_cur; 1148 nex->hw_cur = hw; 1149 nex->sbt_cur = sbt; 1150 seqc_write_end(&nex->gen); 1151 sc->cal_current = next_up; 1152 done: 1153 callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration, 1154 sc, C_DIRECT_EXEC); 1155 } 1156 1157 static void 1158 t4_calibration_start(struct adapter *sc) 1159 { 1160 /* 1161 * Here if we have not done a calibration 1162 * then do so otherwise start the appropriate 1163 * timer. 1164 */ 1165 int i; 1166 1167 for (i = 0; i < CNT_CAL_INFO; i++) { 1168 sc->cal_info[i].gen = 0; 1169 } 1170 sc->cal_current = 0; 1171 sc->cal_count = 0; 1172 sc->cal_gen = 0; 1173 t4_calibration(sc); 1174 } 1175 1176 static int 1177 t4_attach(device_t dev) 1178 { 1179 struct adapter *sc; 1180 int rc = 0, i, j, rqidx, tqidx, nports; 1181 struct make_dev_args mda; 1182 struct intrs_and_queues iaq; 1183 struct sge *s; 1184 uint32_t *buf; 1185 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1186 int ofld_tqidx; 1187 #endif 1188 #ifdef TCP_OFFLOAD 1189 int ofld_rqidx; 1190 #endif 1191 #ifdef DEV_NETMAP 1192 int nm_rqidx, nm_tqidx; 1193 #endif 1194 int num_vis; 1195 1196 sc = device_get_softc(dev); 1197 sc->dev = dev; 1198 sysctl_ctx_init(&sc->ctx); 1199 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 1200 1201 if ((pci_get_device(dev) & 0xff00) == 0x5400) 1202 t5_attribute_workaround(dev); 1203 pci_enable_busmaster(dev); 1204 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 1205 uint32_t v; 1206 1207 pci_set_max_read_req(dev, 4096); 1208 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 1209 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 1210 if (pcie_relaxed_ordering == 0 && 1211 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 1212 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 1213 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1214 } else if (pcie_relaxed_ordering == 1 && 1215 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 1216 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 1217 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1218 } 1219 } 1220 1221 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 1222 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 1223 sc->traceq = -1; 1224 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 1225 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 1226 device_get_nameunit(dev)); 1227 1228 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 1229 device_get_nameunit(dev)); 1230 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 1231 t4_add_adapter(sc); 1232 1233 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 1234 TAILQ_INIT(&sc->sfl); 1235 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 1236 1237 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 1238 1239 sc->policy = NULL; 1240 rw_init(&sc->policy_lock, "connection offload policy"); 1241 1242 callout_init(&sc->ktls_tick, 1); 1243 1244 callout_init(&sc->cal_callout, 1); 1245 1246 refcount_init(&sc->vxlan_refcount, 0); 1247 1248 TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc); 1249 TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc); 1250 1251 sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1252 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq", 1253 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 1254 sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1255 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq", 1256 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 1257 1258 rc = t4_map_bars_0_and_4(sc); 1259 if (rc != 0) 1260 goto done; /* error message displayed already */ 1261 1262 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1263 1264 /* Prepare the adapter for operation. */ 1265 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1266 rc = -t4_prep_adapter(sc, buf); 1267 free(buf, M_CXGBE); 1268 if (rc != 0) { 1269 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1270 goto done; 1271 } 1272 1273 /* 1274 * This is the real PF# to which we're attaching. Works from within PCI 1275 * passthrough environments too, where pci_get_function() could return a 1276 * different PF# depending on the passthrough configuration. We need to 1277 * use the real PF# in all our communication with the firmware. 1278 */ 1279 j = t4_read_reg(sc, A_PL_WHOAMI); 1280 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1281 sc->mbox = sc->pf; 1282 1283 t4_init_devnames(sc); 1284 if (sc->names == NULL) { 1285 rc = ENOTSUP; 1286 goto done; /* error message displayed already */ 1287 } 1288 1289 /* 1290 * Do this really early, with the memory windows set up even before the 1291 * character device. The userland tool's register i/o and mem read 1292 * will work even in "recovery mode". 1293 */ 1294 setup_memwin(sc); 1295 if (t4_init_devlog_params(sc, 0) == 0) 1296 fixup_devlog_params(sc); 1297 make_dev_args_init(&mda); 1298 mda.mda_devsw = &t4_cdevsw; 1299 mda.mda_uid = UID_ROOT; 1300 mda.mda_gid = GID_WHEEL; 1301 mda.mda_mode = 0600; 1302 mda.mda_si_drv1 = sc; 1303 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1304 if (rc != 0) 1305 device_printf(dev, "failed to create nexus char device: %d.\n", 1306 rc); 1307 1308 /* Go no further if recovery mode has been requested. */ 1309 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1310 device_printf(dev, "recovery mode.\n"); 1311 goto done; 1312 } 1313 1314 #if defined(__i386__) 1315 if ((cpu_feature & CPUID_CX8) == 0) { 1316 device_printf(dev, "64 bit atomics not available.\n"); 1317 rc = ENOTSUP; 1318 goto done; 1319 } 1320 #endif 1321 1322 /* Contact the firmware and try to become the master driver. */ 1323 rc = contact_firmware(sc); 1324 if (rc != 0) 1325 goto done; /* error message displayed already */ 1326 MPASS(sc->flags & FW_OK); 1327 1328 rc = get_params__pre_init(sc); 1329 if (rc != 0) 1330 goto done; /* error message displayed already */ 1331 1332 if (sc->flags & MASTER_PF) { 1333 rc = partition_resources(sc); 1334 if (rc != 0) 1335 goto done; /* error message displayed already */ 1336 t4_intr_clear(sc); 1337 } 1338 1339 rc = get_params__post_init(sc); 1340 if (rc != 0) 1341 goto done; /* error message displayed already */ 1342 1343 rc = set_params__post_init(sc); 1344 if (rc != 0) 1345 goto done; /* error message displayed already */ 1346 1347 rc = t4_map_bar_2(sc); 1348 if (rc != 0) 1349 goto done; /* error message displayed already */ 1350 1351 rc = t4_create_dma_tag(sc); 1352 if (rc != 0) 1353 goto done; /* error message displayed already */ 1354 1355 /* 1356 * First pass over all the ports - allocate VIs and initialize some 1357 * basic parameters like mac address, port type, etc. 1358 */ 1359 for_each_port(sc, i) { 1360 struct port_info *pi; 1361 1362 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1363 sc->port[i] = pi; 1364 1365 /* These must be set before t4_port_init */ 1366 pi->adapter = sc; 1367 pi->port_id = i; 1368 /* 1369 * XXX: vi[0] is special so we can't delay this allocation until 1370 * pi->nvi's final value is known. 1371 */ 1372 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1373 M_ZERO | M_WAITOK); 1374 1375 /* 1376 * Allocate the "main" VI and initialize parameters 1377 * like mac addr. 1378 */ 1379 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1380 if (rc != 0) { 1381 device_printf(dev, "unable to initialize port %d: %d\n", 1382 i, rc); 1383 free(pi->vi, M_CXGBE); 1384 free(pi, M_CXGBE); 1385 sc->port[i] = NULL; 1386 goto done; 1387 } 1388 1389 if (is_bt(pi->port_type)) 1390 setbit(&sc->bt_map, pi->tx_chan); 1391 else 1392 MPASS(!isset(&sc->bt_map, pi->tx_chan)); 1393 1394 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1395 device_get_nameunit(dev), i); 1396 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1397 sc->chan_map[pi->tx_chan] = i; 1398 1399 /* 1400 * The MPS counter for FCS errors doesn't work correctly on the 1401 * T6 so we use the MAC counter here. Which MAC is in use 1402 * depends on the link settings which will be known when the 1403 * link comes up. 1404 */ 1405 if (is_t6(sc)) { 1406 pi->fcs_reg = -1; 1407 } else if (is_t4(sc)) { 1408 pi->fcs_reg = PORT_REG(pi->tx_chan, 1409 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1410 } else { 1411 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 1412 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1413 } 1414 pi->fcs_base = 0; 1415 1416 /* All VIs on this port share this media. */ 1417 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1418 cxgbe_media_status); 1419 1420 PORT_LOCK(pi); 1421 init_link_config(pi); 1422 fixup_link_config(pi); 1423 build_medialist(pi); 1424 if (fixed_ifmedia(pi)) 1425 pi->flags |= FIXED_IFMEDIA; 1426 PORT_UNLOCK(pi); 1427 1428 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1429 t4_ifnet_unit(sc, pi)); 1430 if (pi->dev == NULL) { 1431 device_printf(dev, 1432 "failed to add device for port %d.\n", i); 1433 rc = ENXIO; 1434 goto done; 1435 } 1436 pi->vi[0].dev = pi->dev; 1437 device_set_softc(pi->dev, pi); 1438 } 1439 1440 /* 1441 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1442 */ 1443 nports = sc->params.nports; 1444 rc = cfg_itype_and_nqueues(sc, &iaq); 1445 if (rc != 0) 1446 goto done; /* error message displayed already */ 1447 1448 num_vis = iaq.num_vis; 1449 sc->intr_type = iaq.intr_type; 1450 sc->intr_count = iaq.nirq; 1451 1452 s = &sc->sge; 1453 s->nrxq = nports * iaq.nrxq; 1454 s->ntxq = nports * iaq.ntxq; 1455 if (num_vis > 1) { 1456 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1457 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1458 } 1459 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1460 s->neq += nports; /* ctrl queues: 1 per port */ 1461 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1462 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1463 if (is_offload(sc) || is_ethoffload(sc)) { 1464 s->nofldtxq = nports * iaq.nofldtxq; 1465 if (num_vis > 1) 1466 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1467 s->neq += s->nofldtxq; 1468 1469 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq), 1470 M_CXGBE, M_ZERO | M_WAITOK); 1471 } 1472 #endif 1473 #ifdef TCP_OFFLOAD 1474 if (is_offload(sc)) { 1475 s->nofldrxq = nports * iaq.nofldrxq; 1476 if (num_vis > 1) 1477 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1478 s->neq += s->nofldrxq; /* free list */ 1479 s->niq += s->nofldrxq; 1480 1481 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1482 M_CXGBE, M_ZERO | M_WAITOK); 1483 } 1484 #endif 1485 #ifdef DEV_NETMAP 1486 s->nnmrxq = 0; 1487 s->nnmtxq = 0; 1488 if (t4_native_netmap & NN_MAIN_VI) { 1489 s->nnmrxq += nports * iaq.nnmrxq; 1490 s->nnmtxq += nports * iaq.nnmtxq; 1491 } 1492 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) { 1493 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi; 1494 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi; 1495 } 1496 s->neq += s->nnmtxq + s->nnmrxq; 1497 s->niq += s->nnmrxq; 1498 1499 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1500 M_CXGBE, M_ZERO | M_WAITOK); 1501 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1502 M_CXGBE, M_ZERO | M_WAITOK); 1503 #endif 1504 MPASS(s->niq <= s->iqmap_sz); 1505 MPASS(s->neq <= s->eqmap_sz); 1506 1507 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1508 M_ZERO | M_WAITOK); 1509 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1510 M_ZERO | M_WAITOK); 1511 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1512 M_ZERO | M_WAITOK); 1513 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE, 1514 M_ZERO | M_WAITOK); 1515 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE, 1516 M_ZERO | M_WAITOK); 1517 1518 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1519 M_ZERO | M_WAITOK); 1520 1521 t4_init_l2t(sc, M_WAITOK); 1522 t4_init_smt(sc, M_WAITOK); 1523 t4_init_tx_sched(sc); 1524 t4_init_atid_table(sc); 1525 #ifdef RATELIMIT 1526 t4_init_etid_table(sc); 1527 #endif 1528 #ifdef INET6 1529 t4_init_clip_table(sc); 1530 #endif 1531 if (sc->vres.key.size != 0) 1532 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1533 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1534 1535 /* 1536 * Second pass over the ports. This time we know the number of rx and 1537 * tx queues that each port should get. 1538 */ 1539 rqidx = tqidx = 0; 1540 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1541 ofld_tqidx = 0; 1542 #endif 1543 #ifdef TCP_OFFLOAD 1544 ofld_rqidx = 0; 1545 #endif 1546 #ifdef DEV_NETMAP 1547 nm_rqidx = nm_tqidx = 0; 1548 #endif 1549 for_each_port(sc, i) { 1550 struct port_info *pi = sc->port[i]; 1551 struct vi_info *vi; 1552 1553 if (pi == NULL) 1554 continue; 1555 1556 pi->nvi = num_vis; 1557 for_each_vi(pi, j, vi) { 1558 vi->pi = pi; 1559 vi->adapter = sc; 1560 vi->first_intr = -1; 1561 vi->qsize_rxq = t4_qsize_rxq; 1562 vi->qsize_txq = t4_qsize_txq; 1563 1564 vi->first_rxq = rqidx; 1565 vi->first_txq = tqidx; 1566 vi->tmr_idx = t4_tmr_idx; 1567 vi->pktc_idx = t4_pktc_idx; 1568 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1569 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1570 1571 rqidx += vi->nrxq; 1572 tqidx += vi->ntxq; 1573 1574 if (j == 0 && vi->ntxq > 1) 1575 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1576 else 1577 vi->rsrv_noflowq = 0; 1578 1579 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1580 vi->first_ofld_txq = ofld_tqidx; 1581 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1582 ofld_tqidx += vi->nofldtxq; 1583 #endif 1584 #ifdef TCP_OFFLOAD 1585 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1586 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1587 vi->first_ofld_rxq = ofld_rqidx; 1588 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1589 1590 ofld_rqidx += vi->nofldrxq; 1591 #endif 1592 #ifdef DEV_NETMAP 1593 vi->first_nm_rxq = nm_rqidx; 1594 vi->first_nm_txq = nm_tqidx; 1595 if (j == 0) { 1596 vi->nnmrxq = iaq.nnmrxq; 1597 vi->nnmtxq = iaq.nnmtxq; 1598 } else { 1599 vi->nnmrxq = iaq.nnmrxq_vi; 1600 vi->nnmtxq = iaq.nnmtxq_vi; 1601 } 1602 nm_rqidx += vi->nnmrxq; 1603 nm_tqidx += vi->nnmtxq; 1604 #endif 1605 } 1606 } 1607 1608 rc = t4_setup_intr_handlers(sc); 1609 if (rc != 0) { 1610 device_printf(dev, 1611 "failed to setup interrupt handlers: %d\n", rc); 1612 goto done; 1613 } 1614 1615 rc = bus_generic_probe(dev); 1616 if (rc != 0) { 1617 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1618 goto done; 1619 } 1620 1621 /* 1622 * Ensure thread-safe mailbox access (in debug builds). 1623 * 1624 * So far this was the only thread accessing the mailbox but various 1625 * ifnets and sysctls are about to be created and their handlers/ioctls 1626 * will access the mailbox from different threads. 1627 */ 1628 sc->flags |= CHK_MBOX_ACCESS; 1629 1630 rc = bus_generic_attach(dev); 1631 if (rc != 0) { 1632 device_printf(dev, 1633 "failed to attach all child ports: %d\n", rc); 1634 goto done; 1635 } 1636 t4_calibration_start(sc); 1637 1638 device_printf(dev, 1639 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1640 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1641 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1642 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1643 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1644 1645 t4_set_desc(sc); 1646 1647 notify_siblings(dev, 0); 1648 1649 done: 1650 if (rc != 0 && sc->cdev) { 1651 /* cdev was created and so cxgbetool works; recover that way. */ 1652 device_printf(dev, 1653 "error during attach, adapter is now in recovery mode.\n"); 1654 rc = 0; 1655 } 1656 1657 if (rc != 0) 1658 t4_detach_common(dev); 1659 else 1660 t4_sysctls(sc); 1661 1662 return (rc); 1663 } 1664 1665 static int 1666 t4_child_location(device_t bus, device_t dev, struct sbuf *sb) 1667 { 1668 struct adapter *sc; 1669 struct port_info *pi; 1670 int i; 1671 1672 sc = device_get_softc(bus); 1673 for_each_port(sc, i) { 1674 pi = sc->port[i]; 1675 if (pi != NULL && pi->dev == dev) { 1676 sbuf_printf(sb, "port=%d", pi->port_id); 1677 break; 1678 } 1679 } 1680 return (0); 1681 } 1682 1683 static int 1684 t4_ready(device_t dev) 1685 { 1686 struct adapter *sc; 1687 1688 sc = device_get_softc(dev); 1689 if (sc->flags & FW_OK) 1690 return (0); 1691 return (ENXIO); 1692 } 1693 1694 static int 1695 t4_read_port_device(device_t dev, int port, device_t *child) 1696 { 1697 struct adapter *sc; 1698 struct port_info *pi; 1699 1700 sc = device_get_softc(dev); 1701 if (port < 0 || port >= MAX_NPORTS) 1702 return (EINVAL); 1703 pi = sc->port[port]; 1704 if (pi == NULL || pi->dev == NULL) 1705 return (ENXIO); 1706 *child = pi->dev; 1707 return (0); 1708 } 1709 1710 static int 1711 notify_siblings(device_t dev, int detaching) 1712 { 1713 device_t sibling; 1714 int error, i; 1715 1716 error = 0; 1717 for (i = 0; i < PCI_FUNCMAX; i++) { 1718 if (i == pci_get_function(dev)) 1719 continue; 1720 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1721 pci_get_slot(dev), i); 1722 if (sibling == NULL || !device_is_attached(sibling)) 1723 continue; 1724 if (detaching) 1725 error = T4_DETACH_CHILD(sibling); 1726 else 1727 (void)T4_ATTACH_CHILD(sibling); 1728 if (error) 1729 break; 1730 } 1731 return (error); 1732 } 1733 1734 /* 1735 * Idempotent 1736 */ 1737 static int 1738 t4_detach(device_t dev) 1739 { 1740 int rc; 1741 1742 rc = notify_siblings(dev, 1); 1743 if (rc) { 1744 device_printf(dev, 1745 "failed to detach sibling devices: %d\n", rc); 1746 return (rc); 1747 } 1748 1749 return (t4_detach_common(dev)); 1750 } 1751 1752 int 1753 t4_detach_common(device_t dev) 1754 { 1755 struct adapter *sc; 1756 struct port_info *pi; 1757 int i, rc; 1758 1759 sc = device_get_softc(dev); 1760 1761 #ifdef TCP_OFFLOAD 1762 rc = t4_deactivate_all_uld(sc); 1763 if (rc) { 1764 device_printf(dev, 1765 "failed to detach upper layer drivers: %d\n", rc); 1766 return (rc); 1767 } 1768 #endif 1769 1770 if (sc->cdev) { 1771 destroy_dev(sc->cdev); 1772 sc->cdev = NULL; 1773 } 1774 1775 sx_xlock(&t4_list_lock); 1776 SLIST_REMOVE(&t4_list, sc, adapter, link); 1777 sx_xunlock(&t4_list_lock); 1778 1779 sc->flags &= ~CHK_MBOX_ACCESS; 1780 if (sc->flags & FULL_INIT_DONE) { 1781 if (!(sc->flags & IS_VF)) 1782 t4_intr_disable(sc); 1783 } 1784 1785 if (device_is_attached(dev)) { 1786 rc = bus_generic_detach(dev); 1787 if (rc) { 1788 device_printf(dev, 1789 "failed to detach child devices: %d\n", rc); 1790 return (rc); 1791 } 1792 } 1793 1794 for (i = 0; i < sc->intr_count; i++) 1795 t4_free_irq(sc, &sc->irq[i]); 1796 1797 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1798 t4_free_tx_sched(sc); 1799 1800 for (i = 0; i < MAX_NPORTS; i++) { 1801 pi = sc->port[i]; 1802 if (pi) { 1803 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1804 if (pi->dev) 1805 device_delete_child(dev, pi->dev); 1806 1807 mtx_destroy(&pi->pi_lock); 1808 free(pi->vi, M_CXGBE); 1809 free(pi, M_CXGBE); 1810 } 1811 } 1812 callout_stop(&sc->cal_callout); 1813 callout_drain(&sc->cal_callout); 1814 device_delete_children(dev); 1815 sysctl_ctx_free(&sc->ctx); 1816 adapter_full_uninit(sc); 1817 1818 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1819 t4_fw_bye(sc, sc->mbox); 1820 1821 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1822 pci_release_msi(dev); 1823 1824 if (sc->regs_res) 1825 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1826 sc->regs_res); 1827 1828 if (sc->udbs_res) 1829 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1830 sc->udbs_res); 1831 1832 if (sc->msix_res) 1833 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1834 sc->msix_res); 1835 1836 if (sc->l2t) 1837 t4_free_l2t(sc->l2t); 1838 if (sc->smt) 1839 t4_free_smt(sc->smt); 1840 t4_free_atid_table(sc); 1841 #ifdef RATELIMIT 1842 t4_free_etid_table(sc); 1843 #endif 1844 if (sc->key_map) 1845 vmem_destroy(sc->key_map); 1846 #ifdef INET6 1847 t4_destroy_clip_table(sc); 1848 #endif 1849 1850 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1851 free(sc->sge.ofld_txq, M_CXGBE); 1852 #endif 1853 #ifdef TCP_OFFLOAD 1854 free(sc->sge.ofld_rxq, M_CXGBE); 1855 #endif 1856 #ifdef DEV_NETMAP 1857 free(sc->sge.nm_rxq, M_CXGBE); 1858 free(sc->sge.nm_txq, M_CXGBE); 1859 #endif 1860 free(sc->irq, M_CXGBE); 1861 free(sc->sge.rxq, M_CXGBE); 1862 free(sc->sge.txq, M_CXGBE); 1863 free(sc->sge.ctrlq, M_CXGBE); 1864 free(sc->sge.iqmap, M_CXGBE); 1865 free(sc->sge.eqmap, M_CXGBE); 1866 free(sc->tids.ftid_tab, M_CXGBE); 1867 free(sc->tids.hpftid_tab, M_CXGBE); 1868 free_hftid_hash(&sc->tids); 1869 free(sc->tids.tid_tab, M_CXGBE); 1870 free(sc->tt.tls_rx_ports, M_CXGBE); 1871 t4_destroy_dma_tag(sc); 1872 1873 callout_drain(&sc->ktls_tick); 1874 callout_drain(&sc->sfl_callout); 1875 if (mtx_initialized(&sc->tids.ftid_lock)) { 1876 mtx_destroy(&sc->tids.ftid_lock); 1877 cv_destroy(&sc->tids.ftid_cv); 1878 } 1879 if (mtx_initialized(&sc->tids.atid_lock)) 1880 mtx_destroy(&sc->tids.atid_lock); 1881 if (mtx_initialized(&sc->ifp_lock)) 1882 mtx_destroy(&sc->ifp_lock); 1883 1884 if (rw_initialized(&sc->policy_lock)) { 1885 rw_destroy(&sc->policy_lock); 1886 #ifdef TCP_OFFLOAD 1887 if (sc->policy != NULL) 1888 free_offload_policy(sc->policy); 1889 #endif 1890 } 1891 1892 for (i = 0; i < NUM_MEMWIN; i++) { 1893 struct memwin *mw = &sc->memwin[i]; 1894 1895 if (rw_initialized(&mw->mw_lock)) 1896 rw_destroy(&mw->mw_lock); 1897 } 1898 1899 mtx_destroy(&sc->sfl_lock); 1900 mtx_destroy(&sc->reg_lock); 1901 mtx_destroy(&sc->sc_lock); 1902 1903 bzero(sc, sizeof(*sc)); 1904 1905 return (0); 1906 } 1907 1908 static inline bool 1909 ok_to_reset(struct adapter *sc) 1910 { 1911 struct tid_info *t = &sc->tids; 1912 struct port_info *pi; 1913 struct vi_info *vi; 1914 int i, j; 1915 int caps = IFCAP_TOE | IFCAP_NETMAP | IFCAP_TXRTLMT; 1916 1917 if (is_t6(sc)) 1918 caps |= IFCAP_TXTLS; 1919 1920 ASSERT_SYNCHRONIZED_OP(sc); 1921 MPASS(!(sc->flags & IS_VF)); 1922 1923 for_each_port(sc, i) { 1924 pi = sc->port[i]; 1925 for_each_vi(pi, j, vi) { 1926 if (vi->ifp->if_capenable & caps) 1927 return (false); 1928 } 1929 } 1930 1931 if (atomic_load_int(&t->tids_in_use) > 0) 1932 return (false); 1933 if (atomic_load_int(&t->stids_in_use) > 0) 1934 return (false); 1935 if (atomic_load_int(&t->atids_in_use) > 0) 1936 return (false); 1937 if (atomic_load_int(&t->ftids_in_use) > 0) 1938 return (false); 1939 if (atomic_load_int(&t->hpftids_in_use) > 0) 1940 return (false); 1941 if (atomic_load_int(&t->etids_in_use) > 0) 1942 return (false); 1943 1944 return (true); 1945 } 1946 1947 static inline int 1948 stop_adapter(struct adapter *sc) 1949 { 1950 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) 1951 return (1); /* Already stopped. */ 1952 return (t4_shutdown_adapter(sc)); 1953 } 1954 1955 static int 1956 t4_suspend(device_t dev) 1957 { 1958 struct adapter *sc = device_get_softc(dev); 1959 struct port_info *pi; 1960 struct vi_info *vi; 1961 struct ifnet *ifp; 1962 struct sge_rxq *rxq; 1963 struct sge_txq *txq; 1964 struct sge_wrq *wrq; 1965 #ifdef TCP_OFFLOAD 1966 struct sge_ofld_rxq *ofld_rxq; 1967 #endif 1968 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1969 struct sge_ofld_txq *ofld_txq; 1970 #endif 1971 int rc, i, j, k; 1972 1973 CH_ALERT(sc, "suspend requested\n"); 1974 1975 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4sus"); 1976 if (rc != 0) 1977 return (ENXIO); 1978 1979 /* XXX: Can the kernel call suspend repeatedly without resume? */ 1980 MPASS(!hw_off_limits(sc)); 1981 1982 if (!ok_to_reset(sc)) { 1983 /* XXX: should list what resource is preventing suspend. */ 1984 CH_ERR(sc, "not safe to suspend.\n"); 1985 rc = EBUSY; 1986 goto done; 1987 } 1988 1989 /* No more DMA or interrupts. */ 1990 stop_adapter(sc); 1991 /* Quiesce all activity. */ 1992 for_each_port(sc, i) { 1993 pi = sc->port[i]; 1994 pi->vxlan_tcam_entry = false; 1995 1996 PORT_LOCK(pi); 1997 if (pi->up_vis > 0) { 1998 /* 1999 * t4_shutdown_adapter has already shut down all the 2000 * PHYs but it also disables interrupts and DMA so there 2001 * won't be a link interrupt. So we update the state 2002 * manually and inform the kernel. 2003 */ 2004 pi->link_cfg.link_ok = false; 2005 t4_os_link_changed(pi); 2006 } 2007 PORT_UNLOCK(pi); 2008 2009 for_each_vi(pi, j, vi) { 2010 vi->xact_addr_filt = -1; 2011 mtx_lock(&vi->tick_mtx); 2012 vi->flags |= VI_SKIP_STATS; 2013 mtx_unlock(&vi->tick_mtx); 2014 if (!(vi->flags & VI_INIT_DONE)) 2015 continue; 2016 2017 ifp = vi->ifp; 2018 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2019 mtx_lock(&vi->tick_mtx); 2020 callout_stop(&vi->tick); 2021 mtx_unlock(&vi->tick_mtx); 2022 callout_drain(&vi->tick); 2023 } 2024 2025 /* 2026 * Note that the HW is not available. 2027 */ 2028 for_each_txq(vi, k, txq) { 2029 TXQ_LOCK(txq); 2030 txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED); 2031 TXQ_UNLOCK(txq); 2032 } 2033 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2034 for_each_ofld_txq(vi, k, ofld_txq) { 2035 ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED; 2036 } 2037 #endif 2038 for_each_rxq(vi, k, rxq) { 2039 rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2040 } 2041 #if defined(TCP_OFFLOAD) 2042 for_each_ofld_rxq(vi, k, ofld_rxq) { 2043 ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2044 } 2045 #endif 2046 2047 quiesce_vi(vi); 2048 } 2049 2050 if (sc->flags & FULL_INIT_DONE) { 2051 /* Control queue */ 2052 wrq = &sc->sge.ctrlq[i]; 2053 wrq->eq.flags &= ~EQ_HW_ALLOCATED; 2054 quiesce_wrq(wrq); 2055 } 2056 } 2057 if (sc->flags & FULL_INIT_DONE) { 2058 /* Firmware event queue */ 2059 sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED; 2060 quiesce_iq_fl(sc, &sc->sge.fwq, NULL); 2061 } 2062 2063 /* Stop calibration */ 2064 callout_stop(&sc->cal_callout); 2065 callout_drain(&sc->cal_callout); 2066 2067 /* Mark the adapter totally off limits. */ 2068 mtx_lock(&sc->reg_lock); 2069 atomic_set_int(&sc->error_flags, HW_OFF_LIMITS); 2070 sc->flags &= ~(FW_OK | MASTER_PF); 2071 sc->reset_thread = NULL; 2072 mtx_unlock(&sc->reg_lock); 2073 2074 if (t4_clock_gate_on_suspend) { 2075 t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN | 2076 F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN | 2077 F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0); 2078 } 2079 2080 CH_ALERT(sc, "suspend completed.\n"); 2081 done: 2082 end_synchronized_op(sc, 0); 2083 return (rc); 2084 } 2085 2086 struct adapter_pre_reset_state { 2087 u_int flags; 2088 uint16_t nbmcaps; 2089 uint16_t linkcaps; 2090 uint16_t switchcaps; 2091 uint16_t niccaps; 2092 uint16_t toecaps; 2093 uint16_t rdmacaps; 2094 uint16_t cryptocaps; 2095 uint16_t iscsicaps; 2096 uint16_t fcoecaps; 2097 2098 u_int cfcsum; 2099 char cfg_file[32]; 2100 2101 struct adapter_params params; 2102 struct t4_virt_res vres; 2103 struct tid_info tids; 2104 struct sge sge; 2105 2106 int rawf_base; 2107 int nrawf; 2108 2109 }; 2110 2111 static void 2112 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2113 { 2114 2115 ASSERT_SYNCHRONIZED_OP(sc); 2116 2117 o->flags = sc->flags; 2118 2119 o->nbmcaps = sc->nbmcaps; 2120 o->linkcaps = sc->linkcaps; 2121 o->switchcaps = sc->switchcaps; 2122 o->niccaps = sc->niccaps; 2123 o->toecaps = sc->toecaps; 2124 o->rdmacaps = sc->rdmacaps; 2125 o->cryptocaps = sc->cryptocaps; 2126 o->iscsicaps = sc->iscsicaps; 2127 o->fcoecaps = sc->fcoecaps; 2128 2129 o->cfcsum = sc->cfcsum; 2130 MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file)); 2131 memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file)); 2132 2133 o->params = sc->params; 2134 o->vres = sc->vres; 2135 o->tids = sc->tids; 2136 o->sge = sc->sge; 2137 2138 o->rawf_base = sc->rawf_base; 2139 o->nrawf = sc->nrawf; 2140 } 2141 2142 static int 2143 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2144 { 2145 int rc = 0; 2146 2147 ASSERT_SYNCHRONIZED_OP(sc); 2148 2149 /* Capabilities */ 2150 #define COMPARE_CAPS(c) do { \ 2151 if (o->c##caps != sc->c##caps) { \ 2152 CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \ 2153 sc->c##caps); \ 2154 rc = EINVAL; \ 2155 } \ 2156 } while (0) 2157 COMPARE_CAPS(nbm); 2158 COMPARE_CAPS(link); 2159 COMPARE_CAPS(switch); 2160 COMPARE_CAPS(nic); 2161 COMPARE_CAPS(toe); 2162 COMPARE_CAPS(rdma); 2163 COMPARE_CAPS(crypto); 2164 COMPARE_CAPS(iscsi); 2165 COMPARE_CAPS(fcoe); 2166 #undef COMPARE_CAPS 2167 2168 /* Firmware config file */ 2169 if (o->cfcsum != sc->cfcsum) { 2170 CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file, 2171 o->cfcsum, sc->cfg_file, sc->cfcsum); 2172 rc = EINVAL; 2173 } 2174 2175 #define COMPARE_PARAM(p, name) do { \ 2176 if (o->p != sc->p) { \ 2177 CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \ 2178 rc = EINVAL; \ 2179 } \ 2180 } while (0) 2181 COMPARE_PARAM(sge.iq_start, iq_start); 2182 COMPARE_PARAM(sge.eq_start, eq_start); 2183 COMPARE_PARAM(tids.ftid_base, ftid_base); 2184 COMPARE_PARAM(tids.ftid_end, ftid_end); 2185 COMPARE_PARAM(tids.nftids, nftids); 2186 COMPARE_PARAM(vres.l2t.start, l2t_start); 2187 COMPARE_PARAM(vres.l2t.size, l2t_size); 2188 COMPARE_PARAM(sge.iqmap_sz, iqmap_sz); 2189 COMPARE_PARAM(sge.eqmap_sz, eqmap_sz); 2190 COMPARE_PARAM(tids.tid_base, tid_base); 2191 COMPARE_PARAM(tids.hpftid_base, hpftid_base); 2192 COMPARE_PARAM(tids.hpftid_end, hpftid_end); 2193 COMPARE_PARAM(tids.nhpftids, nhpftids); 2194 COMPARE_PARAM(rawf_base, rawf_base); 2195 COMPARE_PARAM(nrawf, nrawf); 2196 COMPARE_PARAM(params.mps_bg_map, mps_bg_map); 2197 COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support); 2198 COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl); 2199 COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support); 2200 COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr); 2201 COMPARE_PARAM(tids.ntids, ntids); 2202 COMPARE_PARAM(tids.etid_base, etid_base); 2203 COMPARE_PARAM(tids.etid_end, etid_end); 2204 COMPARE_PARAM(tids.netids, netids); 2205 COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred); 2206 COMPARE_PARAM(params.ethoffload, ethoffload); 2207 COMPARE_PARAM(tids.natids, natids); 2208 COMPARE_PARAM(tids.stid_base, stid_base); 2209 COMPARE_PARAM(vres.ddp.start, ddp_start); 2210 COMPARE_PARAM(vres.ddp.size, ddp_size); 2211 COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred); 2212 COMPARE_PARAM(vres.stag.start, stag_start); 2213 COMPARE_PARAM(vres.stag.size, stag_size); 2214 COMPARE_PARAM(vres.rq.start, rq_start); 2215 COMPARE_PARAM(vres.rq.size, rq_size); 2216 COMPARE_PARAM(vres.pbl.start, pbl_start); 2217 COMPARE_PARAM(vres.pbl.size, pbl_size); 2218 COMPARE_PARAM(vres.qp.start, qp_start); 2219 COMPARE_PARAM(vres.qp.size, qp_size); 2220 COMPARE_PARAM(vres.cq.start, cq_start); 2221 COMPARE_PARAM(vres.cq.size, cq_size); 2222 COMPARE_PARAM(vres.ocq.start, ocq_start); 2223 COMPARE_PARAM(vres.ocq.size, ocq_size); 2224 COMPARE_PARAM(vres.srq.start, srq_start); 2225 COMPARE_PARAM(vres.srq.size, srq_size); 2226 COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp); 2227 COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter); 2228 COMPARE_PARAM(vres.iscsi.start, iscsi_start); 2229 COMPARE_PARAM(vres.iscsi.size, iscsi_size); 2230 COMPARE_PARAM(vres.key.start, key_start); 2231 COMPARE_PARAM(vres.key.size, key_size); 2232 #undef COMPARE_PARAM 2233 2234 return (rc); 2235 } 2236 2237 static int 2238 t4_resume(device_t dev) 2239 { 2240 struct adapter *sc = device_get_softc(dev); 2241 struct adapter_pre_reset_state *old_state = NULL; 2242 struct port_info *pi; 2243 struct vi_info *vi; 2244 struct ifnet *ifp; 2245 struct sge_txq *txq; 2246 int rc, i, j, k; 2247 2248 CH_ALERT(sc, "resume requested.\n"); 2249 2250 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4res"); 2251 if (rc != 0) 2252 return (ENXIO); 2253 MPASS(hw_off_limits(sc)); 2254 MPASS((sc->flags & FW_OK) == 0); 2255 MPASS((sc->flags & MASTER_PF) == 0); 2256 MPASS(sc->reset_thread == NULL); 2257 sc->reset_thread = curthread; 2258 2259 /* Register access is expected to work by the time we're here. */ 2260 if (t4_read_reg(sc, A_PL_WHOAMI) == 0xffffffff) { 2261 CH_ERR(sc, "%s: can't read device registers\n", __func__); 2262 rc = ENXIO; 2263 goto done; 2264 } 2265 2266 /* Note that HW_OFF_LIMITS is cleared a bit later. */ 2267 atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR | ADAP_STOPPED); 2268 2269 /* Restore memory window. */ 2270 setup_memwin(sc); 2271 2272 /* Go no further if recovery mode has been requested. */ 2273 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 2274 CH_ALERT(sc, "recovery mode on resume.\n"); 2275 rc = 0; 2276 mtx_lock(&sc->reg_lock); 2277 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 2278 mtx_unlock(&sc->reg_lock); 2279 goto done; 2280 } 2281 2282 old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK); 2283 save_caps_and_params(sc, old_state); 2284 2285 /* Reestablish contact with firmware and become the primary PF. */ 2286 rc = contact_firmware(sc); 2287 if (rc != 0) 2288 goto done; /* error message displayed already */ 2289 MPASS(sc->flags & FW_OK); 2290 2291 if (sc->flags & MASTER_PF) { 2292 rc = partition_resources(sc); 2293 if (rc != 0) 2294 goto done; /* error message displayed already */ 2295 t4_intr_clear(sc); 2296 } 2297 2298 rc = get_params__post_init(sc); 2299 if (rc != 0) 2300 goto done; /* error message displayed already */ 2301 2302 rc = set_params__post_init(sc); 2303 if (rc != 0) 2304 goto done; /* error message displayed already */ 2305 2306 rc = compare_caps_and_params(sc, old_state); 2307 if (rc != 0) 2308 goto done; /* error message displayed already */ 2309 2310 for_each_port(sc, i) { 2311 pi = sc->port[i]; 2312 MPASS(pi != NULL); 2313 MPASS(pi->vi != NULL); 2314 MPASS(pi->vi[0].dev == pi->dev); 2315 2316 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 2317 if (rc != 0) { 2318 CH_ERR(sc, 2319 "failed to re-initialize port %d: %d\n", i, rc); 2320 goto done; 2321 } 2322 MPASS(sc->chan_map[pi->tx_chan] == i); 2323 2324 PORT_LOCK(pi); 2325 fixup_link_config(pi); 2326 build_medialist(pi); 2327 PORT_UNLOCK(pi); 2328 for_each_vi(pi, j, vi) { 2329 if (IS_MAIN_VI(vi)) 2330 continue; 2331 rc = alloc_extra_vi(sc, pi, vi); 2332 if (rc != 0) { 2333 CH_ERR(vi, 2334 "failed to re-allocate extra VI: %d\n", rc); 2335 goto done; 2336 } 2337 } 2338 } 2339 2340 /* 2341 * Interrupts and queues are about to be enabled and other threads will 2342 * want to access the hardware too. It is safe to do so. Note that 2343 * this thread is still in the middle of a synchronized_op. 2344 */ 2345 mtx_lock(&sc->reg_lock); 2346 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 2347 mtx_unlock(&sc->reg_lock); 2348 2349 if (sc->flags & FULL_INIT_DONE) { 2350 rc = adapter_full_init(sc); 2351 if (rc != 0) { 2352 CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc); 2353 goto done; 2354 } 2355 2356 if (sc->vxlan_refcount > 0) 2357 enable_vxlan_rx(sc); 2358 2359 for_each_port(sc, i) { 2360 pi = sc->port[i]; 2361 for_each_vi(pi, j, vi) { 2362 mtx_lock(&vi->tick_mtx); 2363 vi->flags &= ~VI_SKIP_STATS; 2364 mtx_unlock(&vi->tick_mtx); 2365 if (!(vi->flags & VI_INIT_DONE)) 2366 continue; 2367 rc = vi_full_init(vi); 2368 if (rc != 0) { 2369 CH_ERR(vi, "failed to re-initialize " 2370 "interface: %d\n", rc); 2371 goto done; 2372 } 2373 2374 ifp = vi->ifp; 2375 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2376 continue; 2377 /* 2378 * Note that we do not setup multicast addresses 2379 * in the first pass. This ensures that the 2380 * unicast DMACs for all VIs on all ports get an 2381 * MPS TCAM entry. 2382 */ 2383 rc = update_mac_settings(ifp, XGMAC_ALL & 2384 ~XGMAC_MCADDRS); 2385 if (rc != 0) { 2386 CH_ERR(vi, "failed to re-configure MAC: %d\n", rc); 2387 goto done; 2388 } 2389 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, 2390 true); 2391 if (rc != 0) { 2392 CH_ERR(vi, "failed to re-enable VI: %d\n", rc); 2393 goto done; 2394 } 2395 for_each_txq(vi, k, txq) { 2396 TXQ_LOCK(txq); 2397 txq->eq.flags |= EQ_ENABLED; 2398 TXQ_UNLOCK(txq); 2399 } 2400 mtx_lock(&vi->tick_mtx); 2401 callout_schedule(&vi->tick, hz); 2402 mtx_unlock(&vi->tick_mtx); 2403 } 2404 PORT_LOCK(pi); 2405 if (pi->up_vis > 0) { 2406 t4_update_port_info(pi); 2407 fixup_link_config(pi); 2408 build_medialist(pi); 2409 apply_link_config(pi); 2410 if (pi->link_cfg.link_ok) 2411 t4_os_link_changed(pi); 2412 } 2413 PORT_UNLOCK(pi); 2414 } 2415 2416 /* Now reprogram the L2 multicast addresses. */ 2417 for_each_port(sc, i) { 2418 pi = sc->port[i]; 2419 for_each_vi(pi, j, vi) { 2420 if (!(vi->flags & VI_INIT_DONE)) 2421 continue; 2422 ifp = vi->ifp; 2423 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2424 continue; 2425 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2426 if (rc != 0) { 2427 CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc); 2428 rc = 0; /* carry on */ 2429 } 2430 } 2431 } 2432 } 2433 2434 /* Reset all calibration */ 2435 t4_calibration_start(sc); 2436 2437 done: 2438 if (rc == 0) { 2439 sc->incarnation++; 2440 CH_ALERT(sc, "resume completed.\n"); 2441 } 2442 end_synchronized_op(sc, 0); 2443 free(old_state, M_CXGBE); 2444 return (rc); 2445 } 2446 2447 static int 2448 t4_reset_prepare(device_t dev, device_t child) 2449 { 2450 struct adapter *sc = device_get_softc(dev); 2451 2452 CH_ALERT(sc, "reset_prepare.\n"); 2453 return (0); 2454 } 2455 2456 static int 2457 t4_reset_post(device_t dev, device_t child) 2458 { 2459 struct adapter *sc = device_get_softc(dev); 2460 2461 CH_ALERT(sc, "reset_post.\n"); 2462 return (0); 2463 } 2464 2465 static int 2466 reset_adapter(struct adapter *sc) 2467 { 2468 int rc, oldinc, error_flags; 2469 2470 CH_ALERT(sc, "reset requested.\n"); 2471 2472 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst1"); 2473 if (rc != 0) 2474 return (EBUSY); 2475 2476 if (hw_off_limits(sc)) { 2477 CH_ERR(sc, "adapter is suspended, use resume (not reset).\n"); 2478 rc = ENXIO; 2479 goto done; 2480 } 2481 2482 if (!ok_to_reset(sc)) { 2483 /* XXX: should list what resource is preventing reset. */ 2484 CH_ERR(sc, "not safe to reset.\n"); 2485 rc = EBUSY; 2486 goto done; 2487 } 2488 2489 done: 2490 oldinc = sc->incarnation; 2491 end_synchronized_op(sc, 0); 2492 if (rc != 0) 2493 return (rc); /* Error logged already. */ 2494 2495 atomic_add_int(&sc->num_resets, 1); 2496 mtx_lock(&Giant); 2497 rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0); 2498 mtx_unlock(&Giant); 2499 if (rc != 0) 2500 CH_ERR(sc, "bus_reset_child failed: %d.\n", rc); 2501 else { 2502 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst2"); 2503 if (rc != 0) 2504 return (EBUSY); 2505 error_flags = atomic_load_int(&sc->error_flags); 2506 if (sc->incarnation > oldinc && error_flags == 0) { 2507 CH_ALERT(sc, "bus_reset_child succeeded.\n"); 2508 } else { 2509 CH_ERR(sc, "adapter did not reset properly, flags " 2510 "0x%08x, error_flags 0x%08x.\n", sc->flags, 2511 error_flags); 2512 rc = ENXIO; 2513 } 2514 end_synchronized_op(sc, 0); 2515 } 2516 2517 return (rc); 2518 } 2519 2520 static void 2521 reset_adapter_task(void *arg, int pending) 2522 { 2523 /* XXX: t4_async_event here? */ 2524 reset_adapter(arg); 2525 } 2526 2527 static int 2528 cxgbe_probe(device_t dev) 2529 { 2530 char buf[128]; 2531 struct port_info *pi = device_get_softc(dev); 2532 2533 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 2534 device_set_desc_copy(dev, buf); 2535 2536 return (BUS_PROBE_DEFAULT); 2537 } 2538 2539 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 2540 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 2541 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 2542 IFCAP_HWRXTSTMP | IFCAP_MEXTPG) 2543 #define T4_CAP_ENABLE (T4_CAP) 2544 2545 static int 2546 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 2547 { 2548 struct ifnet *ifp; 2549 struct sbuf *sb; 2550 struct sysctl_ctx_list *ctx = &vi->ctx; 2551 struct sysctl_oid_list *children; 2552 struct pfil_head_args pa; 2553 struct adapter *sc = vi->adapter; 2554 2555 sysctl_ctx_init(ctx); 2556 children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev)); 2557 vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq", 2558 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues"); 2559 vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq", 2560 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues"); 2561 #ifdef DEV_NETMAP 2562 vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq", 2563 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues"); 2564 vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq", 2565 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues"); 2566 #endif 2567 #ifdef TCP_OFFLOAD 2568 vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq", 2569 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues"); 2570 #endif 2571 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2572 vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq", 2573 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues"); 2574 #endif 2575 2576 vi->xact_addr_filt = -1; 2577 mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF); 2578 callout_init_mtx(&vi->tick, &vi->tick_mtx, 0); 2579 if (sc->flags & IS_VF || t4_tx_vm_wr != 0) 2580 vi->flags |= TX_USES_VM_WR; 2581 2582 /* Allocate an ifnet and set it up */ 2583 ifp = if_alloc_dev(IFT_ETHER, dev); 2584 if (ifp == NULL) { 2585 device_printf(dev, "Cannot allocate ifnet\n"); 2586 return (ENOMEM); 2587 } 2588 vi->ifp = ifp; 2589 ifp->if_softc = vi; 2590 2591 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2592 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2593 2594 ifp->if_init = cxgbe_init; 2595 ifp->if_ioctl = cxgbe_ioctl; 2596 ifp->if_transmit = cxgbe_transmit; 2597 ifp->if_qflush = cxgbe_qflush; 2598 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 2599 ifp->if_get_counter = vi_get_counter; 2600 else 2601 ifp->if_get_counter = cxgbe_get_counter; 2602 #if defined(KERN_TLS) || defined(RATELIMIT) 2603 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 2604 #endif 2605 #ifdef RATELIMIT 2606 ifp->if_ratelimit_query = cxgbe_ratelimit_query; 2607 #endif 2608 2609 ifp->if_capabilities = T4_CAP; 2610 ifp->if_capenable = T4_CAP_ENABLE; 2611 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 2612 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 2613 if (chip_id(sc) >= CHELSIO_T6) { 2614 ifp->if_capabilities |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 2615 ifp->if_capenable |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 2616 ifp->if_hwassist |= CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 2617 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2618 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN; 2619 } 2620 2621 #ifdef TCP_OFFLOAD 2622 if (vi->nofldrxq != 0) 2623 ifp->if_capabilities |= IFCAP_TOE; 2624 #endif 2625 #ifdef RATELIMIT 2626 if (is_ethoffload(sc) && vi->nofldtxq != 0) { 2627 ifp->if_capabilities |= IFCAP_TXRTLMT; 2628 ifp->if_capenable |= IFCAP_TXRTLMT; 2629 } 2630 #endif 2631 2632 ifp->if_hw_tsomax = IP_MAXPACKET; 2633 if (vi->flags & TX_USES_VM_WR) 2634 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_VM_TSO; 2635 else 2636 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 2637 #ifdef RATELIMIT 2638 if (is_ethoffload(sc) && vi->nofldtxq != 0) 2639 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO; 2640 #endif 2641 ifp->if_hw_tsomaxsegsize = 65536; 2642 #ifdef KERN_TLS 2643 if (is_ktls(sc)) { 2644 ifp->if_capabilities |= IFCAP_TXTLS; 2645 if (sc->flags & KERN_TLS_ON || !is_t6(sc)) 2646 ifp->if_capenable |= IFCAP_TXTLS; 2647 } 2648 #endif 2649 2650 ether_ifattach(ifp, vi->hw_addr); 2651 #ifdef DEV_NETMAP 2652 if (vi->nnmrxq != 0) 2653 cxgbe_nm_attach(vi); 2654 #endif 2655 sb = sbuf_new_auto(); 2656 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 2657 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2658 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 2659 case IFCAP_TOE: 2660 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 2661 break; 2662 case IFCAP_TOE | IFCAP_TXRTLMT: 2663 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 2664 break; 2665 case IFCAP_TXRTLMT: 2666 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 2667 break; 2668 } 2669 #endif 2670 #ifdef TCP_OFFLOAD 2671 if (ifp->if_capabilities & IFCAP_TOE) 2672 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 2673 #endif 2674 #ifdef DEV_NETMAP 2675 if (ifp->if_capabilities & IFCAP_NETMAP) 2676 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 2677 vi->nnmtxq, vi->nnmrxq); 2678 #endif 2679 sbuf_finish(sb); 2680 device_printf(dev, "%s\n", sbuf_data(sb)); 2681 sbuf_delete(sb); 2682 2683 vi_sysctls(vi); 2684 2685 pa.pa_version = PFIL_VERSION; 2686 pa.pa_flags = PFIL_IN; 2687 pa.pa_type = PFIL_TYPE_ETHERNET; 2688 pa.pa_headname = ifp->if_xname; 2689 vi->pfil = pfil_head_register(&pa); 2690 2691 return (0); 2692 } 2693 2694 static int 2695 cxgbe_attach(device_t dev) 2696 { 2697 struct port_info *pi = device_get_softc(dev); 2698 struct adapter *sc = pi->adapter; 2699 struct vi_info *vi; 2700 int i, rc; 2701 2702 sysctl_ctx_init(&pi->ctx); 2703 2704 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 2705 if (rc) 2706 return (rc); 2707 2708 for_each_vi(pi, i, vi) { 2709 if (i == 0) 2710 continue; 2711 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 2712 if (vi->dev == NULL) { 2713 device_printf(dev, "failed to add VI %d\n", i); 2714 continue; 2715 } 2716 device_set_softc(vi->dev, vi); 2717 } 2718 2719 cxgbe_sysctls(pi); 2720 2721 bus_generic_attach(dev); 2722 2723 return (0); 2724 } 2725 2726 static void 2727 cxgbe_vi_detach(struct vi_info *vi) 2728 { 2729 struct ifnet *ifp = vi->ifp; 2730 2731 if (vi->pfil != NULL) { 2732 pfil_head_unregister(vi->pfil); 2733 vi->pfil = NULL; 2734 } 2735 2736 ether_ifdetach(ifp); 2737 2738 /* Let detach proceed even if these fail. */ 2739 #ifdef DEV_NETMAP 2740 if (ifp->if_capabilities & IFCAP_NETMAP) 2741 cxgbe_nm_detach(vi); 2742 #endif 2743 cxgbe_uninit_synchronized(vi); 2744 callout_drain(&vi->tick); 2745 sysctl_ctx_free(&vi->ctx); 2746 vi_full_uninit(vi); 2747 2748 if_free(vi->ifp); 2749 vi->ifp = NULL; 2750 } 2751 2752 static int 2753 cxgbe_detach(device_t dev) 2754 { 2755 struct port_info *pi = device_get_softc(dev); 2756 struct adapter *sc = pi->adapter; 2757 int rc; 2758 2759 /* Detach the extra VIs first. */ 2760 rc = bus_generic_detach(dev); 2761 if (rc) 2762 return (rc); 2763 device_delete_children(dev); 2764 2765 sysctl_ctx_free(&pi->ctx); 2766 doom_vi(sc, &pi->vi[0]); 2767 2768 if (pi->flags & HAS_TRACEQ) { 2769 sc->traceq = -1; /* cloner should not create ifnet */ 2770 t4_tracer_port_detach(sc); 2771 } 2772 2773 cxgbe_vi_detach(&pi->vi[0]); 2774 ifmedia_removeall(&pi->media); 2775 2776 end_synchronized_op(sc, 0); 2777 2778 return (0); 2779 } 2780 2781 static void 2782 cxgbe_init(void *arg) 2783 { 2784 struct vi_info *vi = arg; 2785 struct adapter *sc = vi->adapter; 2786 2787 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 2788 return; 2789 cxgbe_init_synchronized(vi); 2790 end_synchronized_op(sc, 0); 2791 } 2792 2793 static int 2794 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 2795 { 2796 int rc = 0, mtu, flags; 2797 struct vi_info *vi = ifp->if_softc; 2798 struct port_info *pi = vi->pi; 2799 struct adapter *sc = pi->adapter; 2800 struct ifreq *ifr = (struct ifreq *)data; 2801 uint32_t mask; 2802 2803 switch (cmd) { 2804 case SIOCSIFMTU: 2805 mtu = ifr->ifr_mtu; 2806 if (mtu < ETHERMIN || mtu > MAX_MTU) 2807 return (EINVAL); 2808 2809 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 2810 if (rc) 2811 return (rc); 2812 ifp->if_mtu = mtu; 2813 if (vi->flags & VI_INIT_DONE) { 2814 t4_update_fl_bufsize(ifp); 2815 if (!hw_off_limits(sc) && 2816 ifp->if_drv_flags & IFF_DRV_RUNNING) 2817 rc = update_mac_settings(ifp, XGMAC_MTU); 2818 } 2819 end_synchronized_op(sc, 0); 2820 break; 2821 2822 case SIOCSIFFLAGS: 2823 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 2824 if (rc) 2825 return (rc); 2826 2827 if (hw_off_limits(sc)) { 2828 rc = ENXIO; 2829 goto fail; 2830 } 2831 2832 if (ifp->if_flags & IFF_UP) { 2833 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2834 flags = vi->if_flags; 2835 if ((ifp->if_flags ^ flags) & 2836 (IFF_PROMISC | IFF_ALLMULTI)) { 2837 rc = update_mac_settings(ifp, 2838 XGMAC_PROMISC | XGMAC_ALLMULTI); 2839 } 2840 } else { 2841 rc = cxgbe_init_synchronized(vi); 2842 } 2843 vi->if_flags = ifp->if_flags; 2844 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2845 rc = cxgbe_uninit_synchronized(vi); 2846 } 2847 end_synchronized_op(sc, 0); 2848 break; 2849 2850 case SIOCADDMULTI: 2851 case SIOCDELMULTI: 2852 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 2853 if (rc) 2854 return (rc); 2855 if (!hw_off_limits(sc) && ifp->if_drv_flags & IFF_DRV_RUNNING) 2856 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2857 end_synchronized_op(sc, 0); 2858 break; 2859 2860 case SIOCSIFCAP: 2861 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 2862 if (rc) 2863 return (rc); 2864 2865 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2866 if (mask & IFCAP_TXCSUM) { 2867 ifp->if_capenable ^= IFCAP_TXCSUM; 2868 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2869 2870 if (IFCAP_TSO4 & ifp->if_capenable && 2871 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2872 mask &= ~IFCAP_TSO4; 2873 ifp->if_capenable &= ~IFCAP_TSO4; 2874 if_printf(ifp, 2875 "tso4 disabled due to -txcsum.\n"); 2876 } 2877 } 2878 if (mask & IFCAP_TXCSUM_IPV6) { 2879 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 2880 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2881 2882 if (IFCAP_TSO6 & ifp->if_capenable && 2883 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2884 mask &= ~IFCAP_TSO6; 2885 ifp->if_capenable &= ~IFCAP_TSO6; 2886 if_printf(ifp, 2887 "tso6 disabled due to -txcsum6.\n"); 2888 } 2889 } 2890 if (mask & IFCAP_RXCSUM) 2891 ifp->if_capenable ^= IFCAP_RXCSUM; 2892 if (mask & IFCAP_RXCSUM_IPV6) 2893 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 2894 2895 /* 2896 * Note that we leave CSUM_TSO alone (it is always set). The 2897 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 2898 * sending a TSO request our way, so it's sufficient to toggle 2899 * IFCAP_TSOx only. 2900 */ 2901 if (mask & IFCAP_TSO4) { 2902 if (!(IFCAP_TSO4 & ifp->if_capenable) && 2903 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2904 if_printf(ifp, "enable txcsum first.\n"); 2905 rc = EAGAIN; 2906 goto fail; 2907 } 2908 ifp->if_capenable ^= IFCAP_TSO4; 2909 } 2910 if (mask & IFCAP_TSO6) { 2911 if (!(IFCAP_TSO6 & ifp->if_capenable) && 2912 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2913 if_printf(ifp, "enable txcsum6 first.\n"); 2914 rc = EAGAIN; 2915 goto fail; 2916 } 2917 ifp->if_capenable ^= IFCAP_TSO6; 2918 } 2919 if (mask & IFCAP_LRO) { 2920 #if defined(INET) || defined(INET6) 2921 int i; 2922 struct sge_rxq *rxq; 2923 2924 ifp->if_capenable ^= IFCAP_LRO; 2925 for_each_rxq(vi, i, rxq) { 2926 if (ifp->if_capenable & IFCAP_LRO) 2927 rxq->iq.flags |= IQ_LRO_ENABLED; 2928 else 2929 rxq->iq.flags &= ~IQ_LRO_ENABLED; 2930 } 2931 #endif 2932 } 2933 #ifdef TCP_OFFLOAD 2934 if (mask & IFCAP_TOE) { 2935 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 2936 2937 rc = toe_capability(vi, enable); 2938 if (rc != 0) 2939 goto fail; 2940 2941 ifp->if_capenable ^= mask; 2942 } 2943 #endif 2944 if (mask & IFCAP_VLAN_HWTAGGING) { 2945 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2946 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2947 rc = update_mac_settings(ifp, XGMAC_VLANEX); 2948 } 2949 if (mask & IFCAP_VLAN_MTU) { 2950 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2951 2952 /* Need to find out how to disable auto-mtu-inflation */ 2953 } 2954 if (mask & IFCAP_VLAN_HWTSO) 2955 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2956 if (mask & IFCAP_VLAN_HWCSUM) 2957 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2958 #ifdef RATELIMIT 2959 if (mask & IFCAP_TXRTLMT) 2960 ifp->if_capenable ^= IFCAP_TXRTLMT; 2961 #endif 2962 if (mask & IFCAP_HWRXTSTMP) { 2963 int i; 2964 struct sge_rxq *rxq; 2965 2966 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 2967 for_each_rxq(vi, i, rxq) { 2968 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 2969 rxq->iq.flags |= IQ_RX_TIMESTAMP; 2970 else 2971 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 2972 } 2973 } 2974 if (mask & IFCAP_MEXTPG) 2975 ifp->if_capenable ^= IFCAP_MEXTPG; 2976 2977 #ifdef KERN_TLS 2978 if (mask & IFCAP_TXTLS) { 2979 int enable = (ifp->if_capenable ^ mask) & IFCAP_TXTLS; 2980 2981 rc = ktls_capability(sc, enable); 2982 if (rc != 0) 2983 goto fail; 2984 2985 ifp->if_capenable ^= (mask & IFCAP_TXTLS); 2986 } 2987 #endif 2988 if (mask & IFCAP_VXLAN_HWCSUM) { 2989 ifp->if_capenable ^= IFCAP_VXLAN_HWCSUM; 2990 ifp->if_hwassist ^= CSUM_INNER_IP6_UDP | 2991 CSUM_INNER_IP6_TCP | CSUM_INNER_IP | 2992 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP; 2993 } 2994 if (mask & IFCAP_VXLAN_HWTSO) { 2995 ifp->if_capenable ^= IFCAP_VXLAN_HWTSO; 2996 ifp->if_hwassist ^= CSUM_INNER_IP6_TSO | 2997 CSUM_INNER_IP_TSO; 2998 } 2999 3000 #ifdef VLAN_CAPABILITIES 3001 VLAN_CAPABILITIES(ifp); 3002 #endif 3003 fail: 3004 end_synchronized_op(sc, 0); 3005 break; 3006 3007 case SIOCSIFMEDIA: 3008 case SIOCGIFMEDIA: 3009 case SIOCGIFXMEDIA: 3010 rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 3011 break; 3012 3013 case SIOCGI2C: { 3014 struct ifi2creq i2c; 3015 3016 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3017 if (rc != 0) 3018 break; 3019 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3020 rc = EPERM; 3021 break; 3022 } 3023 if (i2c.len > sizeof(i2c.data)) { 3024 rc = EINVAL; 3025 break; 3026 } 3027 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 3028 if (rc) 3029 return (rc); 3030 if (hw_off_limits(sc)) 3031 rc = ENXIO; 3032 else 3033 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 3034 i2c.offset, i2c.len, &i2c.data[0]); 3035 end_synchronized_op(sc, 0); 3036 if (rc == 0) 3037 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3038 break; 3039 } 3040 3041 default: 3042 rc = ether_ioctl(ifp, cmd, data); 3043 } 3044 3045 return (rc); 3046 } 3047 3048 static int 3049 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 3050 { 3051 struct vi_info *vi = ifp->if_softc; 3052 struct port_info *pi = vi->pi; 3053 struct adapter *sc; 3054 struct sge_txq *txq; 3055 void *items[1]; 3056 int rc; 3057 3058 M_ASSERTPKTHDR(m); 3059 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 3060 #if defined(KERN_TLS) || defined(RATELIMIT) 3061 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) 3062 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 3063 #endif 3064 3065 if (__predict_false(pi->link_cfg.link_ok == false)) { 3066 m_freem(m); 3067 return (ENETDOWN); 3068 } 3069 3070 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR); 3071 if (__predict_false(rc != 0)) { 3072 MPASS(m == NULL); /* was freed already */ 3073 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 3074 return (rc); 3075 } 3076 #ifdef RATELIMIT 3077 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) { 3078 if (m->m_pkthdr.snd_tag->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT) 3079 return (ethofld_transmit(ifp, m)); 3080 } 3081 #endif 3082 3083 /* Select a txq. */ 3084 sc = vi->adapter; 3085 txq = &sc->sge.txq[vi->first_txq]; 3086 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 3087 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 3088 vi->rsrv_noflowq); 3089 3090 items[0] = m; 3091 rc = mp_ring_enqueue(txq->r, items, 1, 256); 3092 if (__predict_false(rc != 0)) 3093 m_freem(m); 3094 3095 return (rc); 3096 } 3097 3098 static void 3099 cxgbe_qflush(struct ifnet *ifp) 3100 { 3101 struct vi_info *vi = ifp->if_softc; 3102 struct sge_txq *txq; 3103 int i; 3104 3105 /* queues do not exist if !VI_INIT_DONE. */ 3106 if (vi->flags & VI_INIT_DONE) { 3107 for_each_txq(vi, i, txq) { 3108 TXQ_LOCK(txq); 3109 txq->eq.flags |= EQ_QFLUSH; 3110 TXQ_UNLOCK(txq); 3111 while (!mp_ring_is_idle(txq->r)) { 3112 mp_ring_check_drainage(txq->r, 4096); 3113 pause("qflush", 1); 3114 } 3115 TXQ_LOCK(txq); 3116 txq->eq.flags &= ~EQ_QFLUSH; 3117 TXQ_UNLOCK(txq); 3118 } 3119 } 3120 if_qflush(ifp); 3121 } 3122 3123 static uint64_t 3124 vi_get_counter(struct ifnet *ifp, ift_counter c) 3125 { 3126 struct vi_info *vi = ifp->if_softc; 3127 struct fw_vi_stats_vf *s = &vi->stats; 3128 3129 mtx_lock(&vi->tick_mtx); 3130 vi_refresh_stats(vi); 3131 mtx_unlock(&vi->tick_mtx); 3132 3133 switch (c) { 3134 case IFCOUNTER_IPACKETS: 3135 return (s->rx_bcast_frames + s->rx_mcast_frames + 3136 s->rx_ucast_frames); 3137 case IFCOUNTER_IERRORS: 3138 return (s->rx_err_frames); 3139 case IFCOUNTER_OPACKETS: 3140 return (s->tx_bcast_frames + s->tx_mcast_frames + 3141 s->tx_ucast_frames + s->tx_offload_frames); 3142 case IFCOUNTER_OERRORS: 3143 return (s->tx_drop_frames); 3144 case IFCOUNTER_IBYTES: 3145 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 3146 s->rx_ucast_bytes); 3147 case IFCOUNTER_OBYTES: 3148 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 3149 s->tx_ucast_bytes + s->tx_offload_bytes); 3150 case IFCOUNTER_IMCASTS: 3151 return (s->rx_mcast_frames); 3152 case IFCOUNTER_OMCASTS: 3153 return (s->tx_mcast_frames); 3154 case IFCOUNTER_OQDROPS: { 3155 uint64_t drops; 3156 3157 drops = 0; 3158 if (vi->flags & VI_INIT_DONE) { 3159 int i; 3160 struct sge_txq *txq; 3161 3162 for_each_txq(vi, i, txq) 3163 drops += counter_u64_fetch(txq->r->dropped); 3164 } 3165 3166 return (drops); 3167 3168 } 3169 3170 default: 3171 return (if_get_counter_default(ifp, c)); 3172 } 3173 } 3174 3175 static uint64_t 3176 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 3177 { 3178 struct vi_info *vi = ifp->if_softc; 3179 struct port_info *pi = vi->pi; 3180 struct port_stats *s = &pi->stats; 3181 3182 mtx_lock(&vi->tick_mtx); 3183 cxgbe_refresh_stats(vi); 3184 mtx_unlock(&vi->tick_mtx); 3185 3186 switch (c) { 3187 case IFCOUNTER_IPACKETS: 3188 return (s->rx_frames); 3189 3190 case IFCOUNTER_IERRORS: 3191 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 3192 s->rx_fcs_err + s->rx_len_err); 3193 3194 case IFCOUNTER_OPACKETS: 3195 return (s->tx_frames); 3196 3197 case IFCOUNTER_OERRORS: 3198 return (s->tx_error_frames); 3199 3200 case IFCOUNTER_IBYTES: 3201 return (s->rx_octets); 3202 3203 case IFCOUNTER_OBYTES: 3204 return (s->tx_octets); 3205 3206 case IFCOUNTER_IMCASTS: 3207 return (s->rx_mcast_frames); 3208 3209 case IFCOUNTER_OMCASTS: 3210 return (s->tx_mcast_frames); 3211 3212 case IFCOUNTER_IQDROPS: 3213 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 3214 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 3215 s->rx_trunc3 + pi->tnl_cong_drops); 3216 3217 case IFCOUNTER_OQDROPS: { 3218 uint64_t drops; 3219 3220 drops = s->tx_drop; 3221 if (vi->flags & VI_INIT_DONE) { 3222 int i; 3223 struct sge_txq *txq; 3224 3225 for_each_txq(vi, i, txq) 3226 drops += counter_u64_fetch(txq->r->dropped); 3227 } 3228 3229 return (drops); 3230 3231 } 3232 3233 default: 3234 return (if_get_counter_default(ifp, c)); 3235 } 3236 } 3237 3238 #if defined(KERN_TLS) || defined(RATELIMIT) 3239 static int 3240 cxgbe_snd_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params, 3241 struct m_snd_tag **pt) 3242 { 3243 int error; 3244 3245 switch (params->hdr.type) { 3246 #ifdef RATELIMIT 3247 case IF_SND_TAG_TYPE_RATE_LIMIT: 3248 error = cxgbe_rate_tag_alloc(ifp, params, pt); 3249 break; 3250 #endif 3251 #ifdef KERN_TLS 3252 case IF_SND_TAG_TYPE_TLS: 3253 { 3254 struct vi_info *vi = ifp->if_softc; 3255 3256 if (is_t6(vi->pi->adapter)) 3257 error = t6_tls_tag_alloc(ifp, params, pt); 3258 else 3259 error = EOPNOTSUPP; 3260 break; 3261 } 3262 #endif 3263 default: 3264 error = EOPNOTSUPP; 3265 } 3266 return (error); 3267 } 3268 #endif 3269 3270 /* 3271 * The kernel picks a media from the list we had provided but we still validate 3272 * the requeste. 3273 */ 3274 int 3275 cxgbe_media_change(struct ifnet *ifp) 3276 { 3277 struct vi_info *vi = ifp->if_softc; 3278 struct port_info *pi = vi->pi; 3279 struct ifmedia *ifm = &pi->media; 3280 struct link_config *lc = &pi->link_cfg; 3281 struct adapter *sc = pi->adapter; 3282 int rc; 3283 3284 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 3285 if (rc != 0) 3286 return (rc); 3287 PORT_LOCK(pi); 3288 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 3289 /* ifconfig .. media autoselect */ 3290 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { 3291 rc = ENOTSUP; /* AN not supported by transceiver */ 3292 goto done; 3293 } 3294 lc->requested_aneg = AUTONEG_ENABLE; 3295 lc->requested_speed = 0; 3296 lc->requested_fc |= PAUSE_AUTONEG; 3297 } else { 3298 lc->requested_aneg = AUTONEG_DISABLE; 3299 lc->requested_speed = 3300 ifmedia_baudrate(ifm->ifm_media) / 1000000; 3301 lc->requested_fc = 0; 3302 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 3303 lc->requested_fc |= PAUSE_RX; 3304 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 3305 lc->requested_fc |= PAUSE_TX; 3306 } 3307 if (pi->up_vis > 0 && !hw_off_limits(sc)) { 3308 fixup_link_config(pi); 3309 rc = apply_link_config(pi); 3310 } 3311 done: 3312 PORT_UNLOCK(pi); 3313 end_synchronized_op(sc, 0); 3314 return (rc); 3315 } 3316 3317 /* 3318 * Base media word (without ETHER, pause, link active, etc.) for the port at the 3319 * given speed. 3320 */ 3321 static int 3322 port_mword(struct port_info *pi, uint32_t speed) 3323 { 3324 3325 MPASS(speed & M_FW_PORT_CAP32_SPEED); 3326 MPASS(powerof2(speed)); 3327 3328 switch(pi->port_type) { 3329 case FW_PORT_TYPE_BT_SGMII: 3330 case FW_PORT_TYPE_BT_XFI: 3331 case FW_PORT_TYPE_BT_XAUI: 3332 /* BaseT */ 3333 switch (speed) { 3334 case FW_PORT_CAP32_SPEED_100M: 3335 return (IFM_100_T); 3336 case FW_PORT_CAP32_SPEED_1G: 3337 return (IFM_1000_T); 3338 case FW_PORT_CAP32_SPEED_10G: 3339 return (IFM_10G_T); 3340 } 3341 break; 3342 case FW_PORT_TYPE_KX4: 3343 if (speed == FW_PORT_CAP32_SPEED_10G) 3344 return (IFM_10G_KX4); 3345 break; 3346 case FW_PORT_TYPE_CX4: 3347 if (speed == FW_PORT_CAP32_SPEED_10G) 3348 return (IFM_10G_CX4); 3349 break; 3350 case FW_PORT_TYPE_KX: 3351 if (speed == FW_PORT_CAP32_SPEED_1G) 3352 return (IFM_1000_KX); 3353 break; 3354 case FW_PORT_TYPE_KR: 3355 case FW_PORT_TYPE_BP_AP: 3356 case FW_PORT_TYPE_BP4_AP: 3357 case FW_PORT_TYPE_BP40_BA: 3358 case FW_PORT_TYPE_KR4_100G: 3359 case FW_PORT_TYPE_KR_SFP28: 3360 case FW_PORT_TYPE_KR_XLAUI: 3361 switch (speed) { 3362 case FW_PORT_CAP32_SPEED_1G: 3363 return (IFM_1000_KX); 3364 case FW_PORT_CAP32_SPEED_10G: 3365 return (IFM_10G_KR); 3366 case FW_PORT_CAP32_SPEED_25G: 3367 return (IFM_25G_KR); 3368 case FW_PORT_CAP32_SPEED_40G: 3369 return (IFM_40G_KR4); 3370 case FW_PORT_CAP32_SPEED_50G: 3371 return (IFM_50G_KR2); 3372 case FW_PORT_CAP32_SPEED_100G: 3373 return (IFM_100G_KR4); 3374 } 3375 break; 3376 case FW_PORT_TYPE_FIBER_XFI: 3377 case FW_PORT_TYPE_FIBER_XAUI: 3378 case FW_PORT_TYPE_SFP: 3379 case FW_PORT_TYPE_QSFP_10G: 3380 case FW_PORT_TYPE_QSA: 3381 case FW_PORT_TYPE_QSFP: 3382 case FW_PORT_TYPE_CR4_QSFP: 3383 case FW_PORT_TYPE_CR_QSFP: 3384 case FW_PORT_TYPE_CR2_QSFP: 3385 case FW_PORT_TYPE_SFP28: 3386 /* Pluggable transceiver */ 3387 switch (pi->mod_type) { 3388 case FW_PORT_MOD_TYPE_LR: 3389 switch (speed) { 3390 case FW_PORT_CAP32_SPEED_1G: 3391 return (IFM_1000_LX); 3392 case FW_PORT_CAP32_SPEED_10G: 3393 return (IFM_10G_LR); 3394 case FW_PORT_CAP32_SPEED_25G: 3395 return (IFM_25G_LR); 3396 case FW_PORT_CAP32_SPEED_40G: 3397 return (IFM_40G_LR4); 3398 case FW_PORT_CAP32_SPEED_50G: 3399 return (IFM_50G_LR2); 3400 case FW_PORT_CAP32_SPEED_100G: 3401 return (IFM_100G_LR4); 3402 } 3403 break; 3404 case FW_PORT_MOD_TYPE_SR: 3405 switch (speed) { 3406 case FW_PORT_CAP32_SPEED_1G: 3407 return (IFM_1000_SX); 3408 case FW_PORT_CAP32_SPEED_10G: 3409 return (IFM_10G_SR); 3410 case FW_PORT_CAP32_SPEED_25G: 3411 return (IFM_25G_SR); 3412 case FW_PORT_CAP32_SPEED_40G: 3413 return (IFM_40G_SR4); 3414 case FW_PORT_CAP32_SPEED_50G: 3415 return (IFM_50G_SR2); 3416 case FW_PORT_CAP32_SPEED_100G: 3417 return (IFM_100G_SR4); 3418 } 3419 break; 3420 case FW_PORT_MOD_TYPE_ER: 3421 if (speed == FW_PORT_CAP32_SPEED_10G) 3422 return (IFM_10G_ER); 3423 break; 3424 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3425 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3426 switch (speed) { 3427 case FW_PORT_CAP32_SPEED_1G: 3428 return (IFM_1000_CX); 3429 case FW_PORT_CAP32_SPEED_10G: 3430 return (IFM_10G_TWINAX); 3431 case FW_PORT_CAP32_SPEED_25G: 3432 return (IFM_25G_CR); 3433 case FW_PORT_CAP32_SPEED_40G: 3434 return (IFM_40G_CR4); 3435 case FW_PORT_CAP32_SPEED_50G: 3436 return (IFM_50G_CR2); 3437 case FW_PORT_CAP32_SPEED_100G: 3438 return (IFM_100G_CR4); 3439 } 3440 break; 3441 case FW_PORT_MOD_TYPE_LRM: 3442 if (speed == FW_PORT_CAP32_SPEED_10G) 3443 return (IFM_10G_LRM); 3444 break; 3445 case FW_PORT_MOD_TYPE_NA: 3446 MPASS(0); /* Not pluggable? */ 3447 /* fall throough */ 3448 case FW_PORT_MOD_TYPE_ERROR: 3449 case FW_PORT_MOD_TYPE_UNKNOWN: 3450 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 3451 break; 3452 case FW_PORT_MOD_TYPE_NONE: 3453 return (IFM_NONE); 3454 } 3455 break; 3456 case FW_PORT_TYPE_NONE: 3457 return (IFM_NONE); 3458 } 3459 3460 return (IFM_UNKNOWN); 3461 } 3462 3463 void 3464 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 3465 { 3466 struct vi_info *vi = ifp->if_softc; 3467 struct port_info *pi = vi->pi; 3468 struct adapter *sc = pi->adapter; 3469 struct link_config *lc = &pi->link_cfg; 3470 3471 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 3472 return; 3473 PORT_LOCK(pi); 3474 3475 if (pi->up_vis == 0 && !hw_off_limits(sc)) { 3476 /* 3477 * If all the interfaces are administratively down the firmware 3478 * does not report transceiver changes. Refresh port info here 3479 * so that ifconfig displays accurate ifmedia at all times. 3480 * This is the only reason we have a synchronized op in this 3481 * function. Just PORT_LOCK would have been enough otherwise. 3482 */ 3483 t4_update_port_info(pi); 3484 build_medialist(pi); 3485 } 3486 3487 /* ifm_status */ 3488 ifmr->ifm_status = IFM_AVALID; 3489 if (lc->link_ok == false) 3490 goto done; 3491 ifmr->ifm_status |= IFM_ACTIVE; 3492 3493 /* ifm_active */ 3494 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 3495 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 3496 if (lc->fc & PAUSE_RX) 3497 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3498 if (lc->fc & PAUSE_TX) 3499 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3500 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 3501 done: 3502 PORT_UNLOCK(pi); 3503 end_synchronized_op(sc, 0); 3504 } 3505 3506 static int 3507 vcxgbe_probe(device_t dev) 3508 { 3509 char buf[128]; 3510 struct vi_info *vi = device_get_softc(dev); 3511 3512 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 3513 vi - vi->pi->vi); 3514 device_set_desc_copy(dev, buf); 3515 3516 return (BUS_PROBE_DEFAULT); 3517 } 3518 3519 static int 3520 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 3521 { 3522 int func, index, rc; 3523 uint32_t param, val; 3524 3525 ASSERT_SYNCHRONIZED_OP(sc); 3526 3527 index = vi - pi->vi; 3528 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 3529 KASSERT(index < nitems(vi_mac_funcs), 3530 ("%s: VI %s doesn't have a MAC func", __func__, 3531 device_get_nameunit(vi->dev))); 3532 func = vi_mac_funcs[index]; 3533 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 3534 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 3535 if (rc < 0) { 3536 CH_ERR(vi, "failed to allocate virtual interface %d" 3537 "for port %d: %d\n", index, pi->port_id, -rc); 3538 return (-rc); 3539 } 3540 vi->viid = rc; 3541 3542 if (vi->rss_size == 1) { 3543 /* 3544 * This VI didn't get a slice of the RSS table. Reduce the 3545 * number of VIs being created (hw.cxgbe.num_vis) or modify the 3546 * configuration file (nvi, rssnvi for this PF) if this is a 3547 * problem. 3548 */ 3549 device_printf(vi->dev, "RSS table not available.\n"); 3550 vi->rss_base = 0xffff; 3551 3552 return (0); 3553 } 3554 3555 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3556 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 3557 V_FW_PARAMS_PARAM_YZ(vi->viid); 3558 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3559 if (rc) 3560 vi->rss_base = 0xffff; 3561 else { 3562 MPASS((val >> 16) == vi->rss_size); 3563 vi->rss_base = val & 0xffff; 3564 } 3565 3566 return (0); 3567 } 3568 3569 static int 3570 vcxgbe_attach(device_t dev) 3571 { 3572 struct vi_info *vi; 3573 struct port_info *pi; 3574 struct adapter *sc; 3575 int rc; 3576 3577 vi = device_get_softc(dev); 3578 pi = vi->pi; 3579 sc = pi->adapter; 3580 3581 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 3582 if (rc) 3583 return (rc); 3584 rc = alloc_extra_vi(sc, pi, vi); 3585 end_synchronized_op(sc, 0); 3586 if (rc) 3587 return (rc); 3588 3589 rc = cxgbe_vi_attach(dev, vi); 3590 if (rc) { 3591 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3592 return (rc); 3593 } 3594 return (0); 3595 } 3596 3597 static int 3598 vcxgbe_detach(device_t dev) 3599 { 3600 struct vi_info *vi; 3601 struct adapter *sc; 3602 3603 vi = device_get_softc(dev); 3604 sc = vi->adapter; 3605 3606 doom_vi(sc, vi); 3607 3608 cxgbe_vi_detach(vi); 3609 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3610 3611 end_synchronized_op(sc, 0); 3612 3613 return (0); 3614 } 3615 3616 static struct callout fatal_callout; 3617 static struct taskqueue *reset_tq; 3618 3619 static void 3620 delayed_panic(void *arg) 3621 { 3622 struct adapter *sc = arg; 3623 3624 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 3625 } 3626 3627 static void 3628 fatal_error_task(void *arg, int pending) 3629 { 3630 struct adapter *sc = arg; 3631 int rc; 3632 3633 #ifdef TCP_OFFLOAD 3634 t4_async_event(sc); 3635 #endif 3636 if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) { 3637 dump_cim_regs(sc); 3638 dump_cimla(sc); 3639 dump_devlog(sc); 3640 } 3641 3642 if (t4_reset_on_fatal_err) { 3643 CH_ALERT(sc, "resetting on fatal error.\n"); 3644 rc = reset_adapter(sc); 3645 if (rc == 0 && t4_panic_on_fatal_err) { 3646 CH_ALERT(sc, "reset was successful, " 3647 "system will NOT panic.\n"); 3648 return; 3649 } 3650 } 3651 3652 if (t4_panic_on_fatal_err) { 3653 CH_ALERT(sc, "panicking on fatal error (after 30s).\n"); 3654 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 3655 } 3656 } 3657 3658 void 3659 t4_fatal_err(struct adapter *sc, bool fw_error) 3660 { 3661 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 3662 3663 stop_adapter(sc); 3664 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR))) 3665 return; 3666 if (fw_error) { 3667 /* 3668 * We are here because of a firmware error/timeout and not 3669 * because of a hardware interrupt. It is possible (although 3670 * not very likely) that an error interrupt was also raised but 3671 * this thread ran first and inhibited t4_intr_err. We walk the 3672 * main INT_CAUSE registers here to make sure we haven't missed 3673 * anything interesting. 3674 */ 3675 t4_slow_intr_handler(sc, verbose); 3676 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 3677 } 3678 t4_report_fw_error(sc); 3679 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n", 3680 device_get_nameunit(sc->dev), fw_error); 3681 taskqueue_enqueue(reset_tq, &sc->fatal_error_task); 3682 } 3683 3684 void 3685 t4_add_adapter(struct adapter *sc) 3686 { 3687 sx_xlock(&t4_list_lock); 3688 SLIST_INSERT_HEAD(&t4_list, sc, link); 3689 sx_xunlock(&t4_list_lock); 3690 } 3691 3692 int 3693 t4_map_bars_0_and_4(struct adapter *sc) 3694 { 3695 sc->regs_rid = PCIR_BAR(0); 3696 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3697 &sc->regs_rid, RF_ACTIVE); 3698 if (sc->regs_res == NULL) { 3699 device_printf(sc->dev, "cannot map registers.\n"); 3700 return (ENXIO); 3701 } 3702 sc->bt = rman_get_bustag(sc->regs_res); 3703 sc->bh = rman_get_bushandle(sc->regs_res); 3704 sc->mmio_len = rman_get_size(sc->regs_res); 3705 setbit(&sc->doorbells, DOORBELL_KDB); 3706 3707 sc->msix_rid = PCIR_BAR(4); 3708 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3709 &sc->msix_rid, RF_ACTIVE); 3710 if (sc->msix_res == NULL) { 3711 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 3712 return (ENXIO); 3713 } 3714 3715 return (0); 3716 } 3717 3718 int 3719 t4_map_bar_2(struct adapter *sc) 3720 { 3721 3722 /* 3723 * T4: only iWARP driver uses the userspace doorbells. There is no need 3724 * to map it if RDMA is disabled. 3725 */ 3726 if (is_t4(sc) && sc->rdmacaps == 0) 3727 return (0); 3728 3729 sc->udbs_rid = PCIR_BAR(2); 3730 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3731 &sc->udbs_rid, RF_ACTIVE); 3732 if (sc->udbs_res == NULL) { 3733 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 3734 return (ENXIO); 3735 } 3736 sc->udbs_base = rman_get_virtual(sc->udbs_res); 3737 3738 if (chip_id(sc) >= CHELSIO_T5) { 3739 setbit(&sc->doorbells, DOORBELL_UDB); 3740 #if defined(__i386__) || defined(__amd64__) 3741 if (t5_write_combine) { 3742 int rc, mode; 3743 3744 /* 3745 * Enable write combining on BAR2. This is the 3746 * userspace doorbell BAR and is split into 128B 3747 * (UDBS_SEG_SIZE) doorbell regions, each associated 3748 * with an egress queue. The first 64B has the doorbell 3749 * and the second 64B can be used to submit a tx work 3750 * request with an implicit doorbell. 3751 */ 3752 3753 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 3754 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 3755 if (rc == 0) { 3756 clrbit(&sc->doorbells, DOORBELL_UDB); 3757 setbit(&sc->doorbells, DOORBELL_WCWR); 3758 setbit(&sc->doorbells, DOORBELL_UDBWC); 3759 } else { 3760 device_printf(sc->dev, 3761 "couldn't enable write combining: %d\n", 3762 rc); 3763 } 3764 3765 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 3766 t4_write_reg(sc, A_SGE_STAT_CFG, 3767 V_STATSOURCE_T5(7) | mode); 3768 } 3769 #endif 3770 } 3771 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 3772 3773 return (0); 3774 } 3775 3776 struct memwin_init { 3777 uint32_t base; 3778 uint32_t aperture; 3779 }; 3780 3781 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 3782 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3783 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3784 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 3785 }; 3786 3787 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 3788 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3789 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3790 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 3791 }; 3792 3793 static void 3794 setup_memwin(struct adapter *sc) 3795 { 3796 const struct memwin_init *mw_init; 3797 struct memwin *mw; 3798 int i; 3799 uint32_t bar0; 3800 3801 if (is_t4(sc)) { 3802 /* 3803 * Read low 32b of bar0 indirectly via the hardware backdoor 3804 * mechanism. Works from within PCI passthrough environments 3805 * too, where rman_get_start() can return a different value. We 3806 * need to program the T4 memory window decoders with the actual 3807 * addresses that will be coming across the PCIe link. 3808 */ 3809 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 3810 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 3811 3812 mw_init = &t4_memwin[0]; 3813 } else { 3814 /* T5+ use the relative offset inside the PCIe BAR */ 3815 bar0 = 0; 3816 3817 mw_init = &t5_memwin[0]; 3818 } 3819 3820 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 3821 if (!rw_initialized(&mw->mw_lock)) { 3822 rw_init(&mw->mw_lock, "memory window access"); 3823 mw->mw_base = mw_init->base; 3824 mw->mw_aperture = mw_init->aperture; 3825 mw->mw_curpos = 0; 3826 } 3827 t4_write_reg(sc, 3828 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 3829 (mw->mw_base + bar0) | V_BIR(0) | 3830 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 3831 rw_wlock(&mw->mw_lock); 3832 position_memwin(sc, i, mw->mw_curpos); 3833 rw_wunlock(&mw->mw_lock); 3834 } 3835 3836 /* flush */ 3837 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 3838 } 3839 3840 /* 3841 * Positions the memory window at the given address in the card's address space. 3842 * There are some alignment requirements and the actual position may be at an 3843 * address prior to the requested address. mw->mw_curpos always has the actual 3844 * position of the window. 3845 */ 3846 static void 3847 position_memwin(struct adapter *sc, int idx, uint32_t addr) 3848 { 3849 struct memwin *mw; 3850 uint32_t pf; 3851 uint32_t reg; 3852 3853 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3854 mw = &sc->memwin[idx]; 3855 rw_assert(&mw->mw_lock, RA_WLOCKED); 3856 3857 if (is_t4(sc)) { 3858 pf = 0; 3859 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 3860 } else { 3861 pf = V_PFNUM(sc->pf); 3862 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 3863 } 3864 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 3865 t4_write_reg(sc, reg, mw->mw_curpos | pf); 3866 t4_read_reg(sc, reg); /* flush */ 3867 } 3868 3869 int 3870 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 3871 int len, int rw) 3872 { 3873 struct memwin *mw; 3874 uint32_t mw_end, v; 3875 3876 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3877 3878 /* Memory can only be accessed in naturally aligned 4 byte units */ 3879 if (addr & 3 || len & 3 || len <= 0) 3880 return (EINVAL); 3881 3882 mw = &sc->memwin[idx]; 3883 while (len > 0) { 3884 rw_rlock(&mw->mw_lock); 3885 mw_end = mw->mw_curpos + mw->mw_aperture; 3886 if (addr >= mw_end || addr < mw->mw_curpos) { 3887 /* Will need to reposition the window */ 3888 if (!rw_try_upgrade(&mw->mw_lock)) { 3889 rw_runlock(&mw->mw_lock); 3890 rw_wlock(&mw->mw_lock); 3891 } 3892 rw_assert(&mw->mw_lock, RA_WLOCKED); 3893 position_memwin(sc, idx, addr); 3894 rw_downgrade(&mw->mw_lock); 3895 mw_end = mw->mw_curpos + mw->mw_aperture; 3896 } 3897 rw_assert(&mw->mw_lock, RA_RLOCKED); 3898 while (addr < mw_end && len > 0) { 3899 if (rw == 0) { 3900 v = t4_read_reg(sc, mw->mw_base + addr - 3901 mw->mw_curpos); 3902 *val++ = le32toh(v); 3903 } else { 3904 v = *val++; 3905 t4_write_reg(sc, mw->mw_base + addr - 3906 mw->mw_curpos, htole32(v)); 3907 } 3908 addr += 4; 3909 len -= 4; 3910 } 3911 rw_runlock(&mw->mw_lock); 3912 } 3913 3914 return (0); 3915 } 3916 3917 static void 3918 t4_init_atid_table(struct adapter *sc) 3919 { 3920 struct tid_info *t; 3921 int i; 3922 3923 t = &sc->tids; 3924 if (t->natids == 0) 3925 return; 3926 3927 MPASS(t->atid_tab == NULL); 3928 3929 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 3930 M_ZERO | M_WAITOK); 3931 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 3932 t->afree = t->atid_tab; 3933 t->atids_in_use = 0; 3934 for (i = 1; i < t->natids; i++) 3935 t->atid_tab[i - 1].next = &t->atid_tab[i]; 3936 t->atid_tab[t->natids - 1].next = NULL; 3937 } 3938 3939 static void 3940 t4_free_atid_table(struct adapter *sc) 3941 { 3942 struct tid_info *t; 3943 3944 t = &sc->tids; 3945 3946 KASSERT(t->atids_in_use == 0, 3947 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 3948 3949 if (mtx_initialized(&t->atid_lock)) 3950 mtx_destroy(&t->atid_lock); 3951 free(t->atid_tab, M_CXGBE); 3952 t->atid_tab = NULL; 3953 } 3954 3955 int 3956 alloc_atid(struct adapter *sc, void *ctx) 3957 { 3958 struct tid_info *t = &sc->tids; 3959 int atid = -1; 3960 3961 mtx_lock(&t->atid_lock); 3962 if (t->afree) { 3963 union aopen_entry *p = t->afree; 3964 3965 atid = p - t->atid_tab; 3966 MPASS(atid <= M_TID_TID); 3967 t->afree = p->next; 3968 p->data = ctx; 3969 t->atids_in_use++; 3970 } 3971 mtx_unlock(&t->atid_lock); 3972 return (atid); 3973 } 3974 3975 void * 3976 lookup_atid(struct adapter *sc, int atid) 3977 { 3978 struct tid_info *t = &sc->tids; 3979 3980 return (t->atid_tab[atid].data); 3981 } 3982 3983 void 3984 free_atid(struct adapter *sc, int atid) 3985 { 3986 struct tid_info *t = &sc->tids; 3987 union aopen_entry *p = &t->atid_tab[atid]; 3988 3989 mtx_lock(&t->atid_lock); 3990 p->next = t->afree; 3991 t->afree = p; 3992 t->atids_in_use--; 3993 mtx_unlock(&t->atid_lock); 3994 } 3995 3996 static void 3997 queue_tid_release(struct adapter *sc, int tid) 3998 { 3999 4000 CXGBE_UNIMPLEMENTED("deferred tid release"); 4001 } 4002 4003 void 4004 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 4005 { 4006 struct wrqe *wr; 4007 struct cpl_tid_release *req; 4008 4009 wr = alloc_wrqe(sizeof(*req), ctrlq); 4010 if (wr == NULL) { 4011 queue_tid_release(sc, tid); /* defer */ 4012 return; 4013 } 4014 req = wrtod(wr); 4015 4016 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 4017 4018 t4_wrq_tx(sc, wr); 4019 } 4020 4021 static int 4022 t4_range_cmp(const void *a, const void *b) 4023 { 4024 return ((const struct t4_range *)a)->start - 4025 ((const struct t4_range *)b)->start; 4026 } 4027 4028 /* 4029 * Verify that the memory range specified by the addr/len pair is valid within 4030 * the card's address space. 4031 */ 4032 static int 4033 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 4034 { 4035 struct t4_range mem_ranges[4], *r, *next; 4036 uint32_t em, addr_len; 4037 int i, n, remaining; 4038 4039 /* Memory can only be accessed in naturally aligned 4 byte units */ 4040 if (addr & 3 || len & 3 || len == 0) 4041 return (EINVAL); 4042 4043 /* Enabled memories */ 4044 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4045 4046 r = &mem_ranges[0]; 4047 n = 0; 4048 bzero(r, sizeof(mem_ranges)); 4049 if (em & F_EDRAM0_ENABLE) { 4050 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4051 r->size = G_EDRAM0_SIZE(addr_len) << 20; 4052 if (r->size > 0) { 4053 r->start = G_EDRAM0_BASE(addr_len) << 20; 4054 if (addr >= r->start && 4055 addr + len <= r->start + r->size) 4056 return (0); 4057 r++; 4058 n++; 4059 } 4060 } 4061 if (em & F_EDRAM1_ENABLE) { 4062 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4063 r->size = G_EDRAM1_SIZE(addr_len) << 20; 4064 if (r->size > 0) { 4065 r->start = G_EDRAM1_BASE(addr_len) << 20; 4066 if (addr >= r->start && 4067 addr + len <= r->start + r->size) 4068 return (0); 4069 r++; 4070 n++; 4071 } 4072 } 4073 if (em & F_EXT_MEM_ENABLE) { 4074 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4075 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 4076 if (r->size > 0) { 4077 r->start = G_EXT_MEM_BASE(addr_len) << 20; 4078 if (addr >= r->start && 4079 addr + len <= r->start + r->size) 4080 return (0); 4081 r++; 4082 n++; 4083 } 4084 } 4085 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 4086 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4087 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 4088 if (r->size > 0) { 4089 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 4090 if (addr >= r->start && 4091 addr + len <= r->start + r->size) 4092 return (0); 4093 r++; 4094 n++; 4095 } 4096 } 4097 MPASS(n <= nitems(mem_ranges)); 4098 4099 if (n > 1) { 4100 /* Sort and merge the ranges. */ 4101 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 4102 4103 /* Start from index 0 and examine the next n - 1 entries. */ 4104 r = &mem_ranges[0]; 4105 for (remaining = n - 1; remaining > 0; remaining--, r++) { 4106 4107 MPASS(r->size > 0); /* r is a valid entry. */ 4108 next = r + 1; 4109 MPASS(next->size > 0); /* and so is the next one. */ 4110 4111 while (r->start + r->size >= next->start) { 4112 /* Merge the next one into the current entry. */ 4113 r->size = max(r->start + r->size, 4114 next->start + next->size) - r->start; 4115 n--; /* One fewer entry in total. */ 4116 if (--remaining == 0) 4117 goto done; /* short circuit */ 4118 next++; 4119 } 4120 if (next != r + 1) { 4121 /* 4122 * Some entries were merged into r and next 4123 * points to the first valid entry that couldn't 4124 * be merged. 4125 */ 4126 MPASS(next->size > 0); /* must be valid */ 4127 memcpy(r + 1, next, remaining * sizeof(*r)); 4128 #ifdef INVARIANTS 4129 /* 4130 * This so that the foo->size assertion in the 4131 * next iteration of the loop do the right 4132 * thing for entries that were pulled up and are 4133 * no longer valid. 4134 */ 4135 MPASS(n < nitems(mem_ranges)); 4136 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 4137 sizeof(struct t4_range)); 4138 #endif 4139 } 4140 } 4141 done: 4142 /* Done merging the ranges. */ 4143 MPASS(n > 0); 4144 r = &mem_ranges[0]; 4145 for (i = 0; i < n; i++, r++) { 4146 if (addr >= r->start && 4147 addr + len <= r->start + r->size) 4148 return (0); 4149 } 4150 } 4151 4152 return (EFAULT); 4153 } 4154 4155 static int 4156 fwmtype_to_hwmtype(int mtype) 4157 { 4158 4159 switch (mtype) { 4160 case FW_MEMTYPE_EDC0: 4161 return (MEM_EDC0); 4162 case FW_MEMTYPE_EDC1: 4163 return (MEM_EDC1); 4164 case FW_MEMTYPE_EXTMEM: 4165 return (MEM_MC0); 4166 case FW_MEMTYPE_EXTMEM1: 4167 return (MEM_MC1); 4168 default: 4169 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 4170 } 4171 } 4172 4173 /* 4174 * Verify that the memory range specified by the memtype/offset/len pair is 4175 * valid and lies entirely within the memtype specified. The global address of 4176 * the start of the range is returned in addr. 4177 */ 4178 static int 4179 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 4180 uint32_t *addr) 4181 { 4182 uint32_t em, addr_len, maddr; 4183 4184 /* Memory can only be accessed in naturally aligned 4 byte units */ 4185 if (off & 3 || len & 3 || len == 0) 4186 return (EINVAL); 4187 4188 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4189 switch (fwmtype_to_hwmtype(mtype)) { 4190 case MEM_EDC0: 4191 if (!(em & F_EDRAM0_ENABLE)) 4192 return (EINVAL); 4193 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4194 maddr = G_EDRAM0_BASE(addr_len) << 20; 4195 break; 4196 case MEM_EDC1: 4197 if (!(em & F_EDRAM1_ENABLE)) 4198 return (EINVAL); 4199 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4200 maddr = G_EDRAM1_BASE(addr_len) << 20; 4201 break; 4202 case MEM_MC: 4203 if (!(em & F_EXT_MEM_ENABLE)) 4204 return (EINVAL); 4205 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4206 maddr = G_EXT_MEM_BASE(addr_len) << 20; 4207 break; 4208 case MEM_MC1: 4209 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 4210 return (EINVAL); 4211 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4212 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 4213 break; 4214 default: 4215 return (EINVAL); 4216 } 4217 4218 *addr = maddr + off; /* global address */ 4219 return (validate_mem_range(sc, *addr, len)); 4220 } 4221 4222 static int 4223 fixup_devlog_params(struct adapter *sc) 4224 { 4225 struct devlog_params *dparams = &sc->params.devlog; 4226 int rc; 4227 4228 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 4229 dparams->size, &dparams->addr); 4230 4231 return (rc); 4232 } 4233 4234 static void 4235 update_nirq(struct intrs_and_queues *iaq, int nports) 4236 { 4237 4238 iaq->nirq = T4_EXTRA_INTR; 4239 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq); 4240 iaq->nirq += nports * iaq->nofldrxq; 4241 iaq->nirq += nports * (iaq->num_vis - 1) * 4242 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 4243 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 4244 } 4245 4246 /* 4247 * Adjust requirements to fit the number of interrupts available. 4248 */ 4249 static void 4250 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 4251 int navail) 4252 { 4253 int old_nirq; 4254 const int nports = sc->params.nports; 4255 4256 MPASS(nports > 0); 4257 MPASS(navail > 0); 4258 4259 bzero(iaq, sizeof(*iaq)); 4260 iaq->intr_type = itype; 4261 iaq->num_vis = t4_num_vis; 4262 iaq->ntxq = t4_ntxq; 4263 iaq->ntxq_vi = t4_ntxq_vi; 4264 iaq->nrxq = t4_nrxq; 4265 iaq->nrxq_vi = t4_nrxq_vi; 4266 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4267 if (is_offload(sc) || is_ethoffload(sc)) { 4268 iaq->nofldtxq = t4_nofldtxq; 4269 iaq->nofldtxq_vi = t4_nofldtxq_vi; 4270 } 4271 #endif 4272 #ifdef TCP_OFFLOAD 4273 if (is_offload(sc)) { 4274 iaq->nofldrxq = t4_nofldrxq; 4275 iaq->nofldrxq_vi = t4_nofldrxq_vi; 4276 } 4277 #endif 4278 #ifdef DEV_NETMAP 4279 if (t4_native_netmap & NN_MAIN_VI) { 4280 iaq->nnmtxq = t4_nnmtxq; 4281 iaq->nnmrxq = t4_nnmrxq; 4282 } 4283 if (t4_native_netmap & NN_EXTRA_VI) { 4284 iaq->nnmtxq_vi = t4_nnmtxq_vi; 4285 iaq->nnmrxq_vi = t4_nnmrxq_vi; 4286 } 4287 #endif 4288 4289 update_nirq(iaq, nports); 4290 if (iaq->nirq <= navail && 4291 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4292 /* 4293 * This is the normal case -- there are enough interrupts for 4294 * everything. 4295 */ 4296 goto done; 4297 } 4298 4299 /* 4300 * If extra VIs have been configured try reducing their count and see if 4301 * that works. 4302 */ 4303 while (iaq->num_vis > 1) { 4304 iaq->num_vis--; 4305 update_nirq(iaq, nports); 4306 if (iaq->nirq <= navail && 4307 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4308 device_printf(sc->dev, "virtual interfaces per port " 4309 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 4310 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 4311 "itype %d, navail %u, nirq %d.\n", 4312 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 4313 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 4314 itype, navail, iaq->nirq); 4315 goto done; 4316 } 4317 } 4318 4319 /* 4320 * Extra VIs will not be created. Log a message if they were requested. 4321 */ 4322 MPASS(iaq->num_vis == 1); 4323 iaq->ntxq_vi = iaq->nrxq_vi = 0; 4324 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 4325 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 4326 if (iaq->num_vis != t4_num_vis) { 4327 device_printf(sc->dev, "extra virtual interfaces disabled. " 4328 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 4329 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 4330 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 4331 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 4332 } 4333 4334 /* 4335 * Keep reducing the number of NIC rx queues to the next lower power of 4336 * 2 (for even RSS distribution) and halving the TOE rx queues and see 4337 * if that works. 4338 */ 4339 do { 4340 if (iaq->nrxq > 1) { 4341 do { 4342 iaq->nrxq--; 4343 } while (!powerof2(iaq->nrxq)); 4344 if (iaq->nnmrxq > iaq->nrxq) 4345 iaq->nnmrxq = iaq->nrxq; 4346 } 4347 if (iaq->nofldrxq > 1) 4348 iaq->nofldrxq >>= 1; 4349 4350 old_nirq = iaq->nirq; 4351 update_nirq(iaq, nports); 4352 if (iaq->nirq <= navail && 4353 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4354 device_printf(sc->dev, "running with reduced number of " 4355 "rx queues because of shortage of interrupts. " 4356 "nrxq=%u, nofldrxq=%u. " 4357 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 4358 iaq->nofldrxq, itype, navail, iaq->nirq); 4359 goto done; 4360 } 4361 } while (old_nirq != iaq->nirq); 4362 4363 /* One interrupt for everything. Ugh. */ 4364 device_printf(sc->dev, "running with minimal number of queues. " 4365 "itype %d, navail %u.\n", itype, navail); 4366 iaq->nirq = 1; 4367 iaq->nrxq = 1; 4368 iaq->ntxq = 1; 4369 if (iaq->nofldrxq > 0) { 4370 iaq->nofldrxq = 1; 4371 iaq->nofldtxq = 1; 4372 } 4373 iaq->nnmtxq = 0; 4374 iaq->nnmrxq = 0; 4375 done: 4376 MPASS(iaq->num_vis > 0); 4377 if (iaq->num_vis > 1) { 4378 MPASS(iaq->nrxq_vi > 0); 4379 MPASS(iaq->ntxq_vi > 0); 4380 } 4381 MPASS(iaq->nirq > 0); 4382 MPASS(iaq->nrxq > 0); 4383 MPASS(iaq->ntxq > 0); 4384 if (itype == INTR_MSI) { 4385 MPASS(powerof2(iaq->nirq)); 4386 } 4387 } 4388 4389 static int 4390 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 4391 { 4392 int rc, itype, navail, nalloc; 4393 4394 for (itype = INTR_MSIX; itype; itype >>= 1) { 4395 4396 if ((itype & t4_intr_types) == 0) 4397 continue; /* not allowed */ 4398 4399 if (itype == INTR_MSIX) 4400 navail = pci_msix_count(sc->dev); 4401 else if (itype == INTR_MSI) 4402 navail = pci_msi_count(sc->dev); 4403 else 4404 navail = 1; 4405 restart: 4406 if (navail == 0) 4407 continue; 4408 4409 calculate_iaq(sc, iaq, itype, navail); 4410 nalloc = iaq->nirq; 4411 rc = 0; 4412 if (itype == INTR_MSIX) 4413 rc = pci_alloc_msix(sc->dev, &nalloc); 4414 else if (itype == INTR_MSI) 4415 rc = pci_alloc_msi(sc->dev, &nalloc); 4416 4417 if (rc == 0 && nalloc > 0) { 4418 if (nalloc == iaq->nirq) 4419 return (0); 4420 4421 /* 4422 * Didn't get the number requested. Use whatever number 4423 * the kernel is willing to allocate. 4424 */ 4425 device_printf(sc->dev, "fewer vectors than requested, " 4426 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 4427 itype, iaq->nirq, nalloc); 4428 pci_release_msi(sc->dev); 4429 navail = nalloc; 4430 goto restart; 4431 } 4432 4433 device_printf(sc->dev, 4434 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 4435 itype, rc, iaq->nirq, nalloc); 4436 } 4437 4438 device_printf(sc->dev, 4439 "failed to find a usable interrupt type. " 4440 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 4441 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 4442 4443 return (ENXIO); 4444 } 4445 4446 #define FW_VERSION(chip) ( \ 4447 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 4448 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 4449 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 4450 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 4451 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 4452 4453 /* Just enough of fw_hdr to cover all version info. */ 4454 struct fw_h { 4455 __u8 ver; 4456 __u8 chip; 4457 __be16 len512; 4458 __be32 fw_ver; 4459 __be32 tp_microcode_ver; 4460 __u8 intfver_nic; 4461 __u8 intfver_vnic; 4462 __u8 intfver_ofld; 4463 __u8 intfver_ri; 4464 __u8 intfver_iscsipdu; 4465 __u8 intfver_iscsi; 4466 __u8 intfver_fcoepdu; 4467 __u8 intfver_fcoe; 4468 }; 4469 /* Spot check a couple of fields. */ 4470 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 4471 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 4472 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 4473 4474 struct fw_info { 4475 uint8_t chip; 4476 char *kld_name; 4477 char *fw_mod_name; 4478 struct fw_h fw_h; 4479 } fw_info[] = { 4480 { 4481 .chip = CHELSIO_T4, 4482 .kld_name = "t4fw_cfg", 4483 .fw_mod_name = "t4fw", 4484 .fw_h = { 4485 .chip = FW_HDR_CHIP_T4, 4486 .fw_ver = htobe32(FW_VERSION(T4)), 4487 .intfver_nic = FW_INTFVER(T4, NIC), 4488 .intfver_vnic = FW_INTFVER(T4, VNIC), 4489 .intfver_ofld = FW_INTFVER(T4, OFLD), 4490 .intfver_ri = FW_INTFVER(T4, RI), 4491 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 4492 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4493 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 4494 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4495 }, 4496 }, { 4497 .chip = CHELSIO_T5, 4498 .kld_name = "t5fw_cfg", 4499 .fw_mod_name = "t5fw", 4500 .fw_h = { 4501 .chip = FW_HDR_CHIP_T5, 4502 .fw_ver = htobe32(FW_VERSION(T5)), 4503 .intfver_nic = FW_INTFVER(T5, NIC), 4504 .intfver_vnic = FW_INTFVER(T5, VNIC), 4505 .intfver_ofld = FW_INTFVER(T5, OFLD), 4506 .intfver_ri = FW_INTFVER(T5, RI), 4507 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 4508 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4509 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 4510 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4511 }, 4512 }, { 4513 .chip = CHELSIO_T6, 4514 .kld_name = "t6fw_cfg", 4515 .fw_mod_name = "t6fw", 4516 .fw_h = { 4517 .chip = FW_HDR_CHIP_T6, 4518 .fw_ver = htobe32(FW_VERSION(T6)), 4519 .intfver_nic = FW_INTFVER(T6, NIC), 4520 .intfver_vnic = FW_INTFVER(T6, VNIC), 4521 .intfver_ofld = FW_INTFVER(T6, OFLD), 4522 .intfver_ri = FW_INTFVER(T6, RI), 4523 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4524 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4525 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4526 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4527 }, 4528 } 4529 }; 4530 4531 static struct fw_info * 4532 find_fw_info(int chip) 4533 { 4534 int i; 4535 4536 for (i = 0; i < nitems(fw_info); i++) { 4537 if (fw_info[i].chip == chip) 4538 return (&fw_info[i]); 4539 } 4540 return (NULL); 4541 } 4542 4543 /* 4544 * Is the given firmware API compatible with the one the driver was compiled 4545 * with? 4546 */ 4547 static int 4548 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 4549 { 4550 4551 /* short circuit if it's the exact same firmware version */ 4552 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 4553 return (1); 4554 4555 /* 4556 * XXX: Is this too conservative? Perhaps I should limit this to the 4557 * features that are supported in the driver. 4558 */ 4559 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 4560 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 4561 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 4562 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 4563 return (1); 4564 #undef SAME_INTF 4565 4566 return (0); 4567 } 4568 4569 static int 4570 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 4571 const struct firmware **fw) 4572 { 4573 struct fw_info *fw_info; 4574 4575 *dcfg = NULL; 4576 if (fw != NULL) 4577 *fw = NULL; 4578 4579 fw_info = find_fw_info(chip_id(sc)); 4580 if (fw_info == NULL) { 4581 device_printf(sc->dev, 4582 "unable to look up firmware information for chip %d.\n", 4583 chip_id(sc)); 4584 return (EINVAL); 4585 } 4586 4587 *dcfg = firmware_get(fw_info->kld_name); 4588 if (*dcfg != NULL) { 4589 if (fw != NULL) 4590 *fw = firmware_get(fw_info->fw_mod_name); 4591 return (0); 4592 } 4593 4594 return (ENOENT); 4595 } 4596 4597 static void 4598 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 4599 const struct firmware *fw) 4600 { 4601 4602 if (fw != NULL) 4603 firmware_put(fw, FIRMWARE_UNLOAD); 4604 if (dcfg != NULL) 4605 firmware_put(dcfg, FIRMWARE_UNLOAD); 4606 } 4607 4608 /* 4609 * Return values: 4610 * 0 means no firmware install attempted. 4611 * ERESTART means a firmware install was attempted and was successful. 4612 * +ve errno means a firmware install was attempted but failed. 4613 */ 4614 static int 4615 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 4616 const struct fw_h *drv_fw, const char *reason, int *already) 4617 { 4618 const struct firmware *cfg, *fw; 4619 const uint32_t c = be32toh(card_fw->fw_ver); 4620 uint32_t d, k; 4621 int rc, fw_install; 4622 struct fw_h bundled_fw; 4623 bool load_attempted; 4624 4625 cfg = fw = NULL; 4626 load_attempted = false; 4627 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 4628 4629 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 4630 if (t4_fw_install < 0) { 4631 rc = load_fw_module(sc, &cfg, &fw); 4632 if (rc != 0 || fw == NULL) { 4633 device_printf(sc->dev, 4634 "failed to load firmware module: %d. cfg %p, fw %p;" 4635 " will use compiled-in firmware version for" 4636 "hw.cxgbe.fw_install checks.\n", 4637 rc, cfg, fw); 4638 } else { 4639 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 4640 } 4641 load_attempted = true; 4642 } 4643 d = be32toh(bundled_fw.fw_ver); 4644 4645 if (reason != NULL) 4646 goto install; 4647 4648 if ((sc->flags & FW_OK) == 0) { 4649 4650 if (c == 0xffffffff) { 4651 reason = "missing"; 4652 goto install; 4653 } 4654 4655 rc = 0; 4656 goto done; 4657 } 4658 4659 if (!fw_compatible(card_fw, &bundled_fw)) { 4660 reason = "incompatible or unusable"; 4661 goto install; 4662 } 4663 4664 if (d > c) { 4665 reason = "older than the version bundled with this driver"; 4666 goto install; 4667 } 4668 4669 if (fw_install == 2 && d != c) { 4670 reason = "different than the version bundled with this driver"; 4671 goto install; 4672 } 4673 4674 /* No reason to do anything to the firmware already on the card. */ 4675 rc = 0; 4676 goto done; 4677 4678 install: 4679 rc = 0; 4680 if ((*already)++) 4681 goto done; 4682 4683 if (fw_install == 0) { 4684 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4685 "but the driver is prohibited from installing a firmware " 4686 "on the card.\n", 4687 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4688 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4689 4690 goto done; 4691 } 4692 4693 /* 4694 * We'll attempt to install a firmware. Load the module first (if it 4695 * hasn't been loaded already). 4696 */ 4697 if (!load_attempted) { 4698 rc = load_fw_module(sc, &cfg, &fw); 4699 if (rc != 0 || fw == NULL) { 4700 device_printf(sc->dev, 4701 "failed to load firmware module: %d. cfg %p, fw %p\n", 4702 rc, cfg, fw); 4703 /* carry on */ 4704 } 4705 } 4706 if (fw == NULL) { 4707 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4708 "but the driver cannot take corrective action because it " 4709 "is unable to load the firmware module.\n", 4710 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4711 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4712 rc = sc->flags & FW_OK ? 0 : ENOENT; 4713 goto done; 4714 } 4715 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 4716 if (k != d) { 4717 MPASS(t4_fw_install > 0); 4718 device_printf(sc->dev, 4719 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 4720 "expecting (%u.%u.%u.%u) and will not be used.\n", 4721 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 4722 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 4723 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4724 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4725 rc = sc->flags & FW_OK ? 0 : EINVAL; 4726 goto done; 4727 } 4728 4729 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4730 "installing firmware %u.%u.%u.%u on card.\n", 4731 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4732 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 4733 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4734 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4735 4736 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 4737 if (rc != 0) { 4738 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 4739 } else { 4740 /* Installed successfully, update the cached header too. */ 4741 rc = ERESTART; 4742 memcpy(card_fw, fw->data, sizeof(*card_fw)); 4743 } 4744 done: 4745 unload_fw_module(sc, cfg, fw); 4746 4747 return (rc); 4748 } 4749 4750 /* 4751 * Establish contact with the firmware and attempt to become the master driver. 4752 * 4753 * A firmware will be installed to the card if needed (if the driver is allowed 4754 * to do so). 4755 */ 4756 static int 4757 contact_firmware(struct adapter *sc) 4758 { 4759 int rc, already = 0; 4760 enum dev_state state; 4761 struct fw_info *fw_info; 4762 struct fw_hdr *card_fw; /* fw on the card */ 4763 const struct fw_h *drv_fw; 4764 4765 fw_info = find_fw_info(chip_id(sc)); 4766 if (fw_info == NULL) { 4767 device_printf(sc->dev, 4768 "unable to look up firmware information for chip %d.\n", 4769 chip_id(sc)); 4770 return (EINVAL); 4771 } 4772 drv_fw = &fw_info->fw_h; 4773 4774 /* Read the header of the firmware on the card */ 4775 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 4776 restart: 4777 rc = -t4_get_fw_hdr(sc, card_fw); 4778 if (rc != 0) { 4779 device_printf(sc->dev, 4780 "unable to read firmware header from card's flash: %d\n", 4781 rc); 4782 goto done; 4783 } 4784 4785 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 4786 &already); 4787 if (rc == ERESTART) 4788 goto restart; 4789 if (rc != 0) 4790 goto done; 4791 4792 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 4793 if (rc < 0 || state == DEV_STATE_ERR) { 4794 rc = -rc; 4795 device_printf(sc->dev, 4796 "failed to connect to the firmware: %d, %d. " 4797 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4798 #if 0 4799 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4800 "not responding properly to HELLO", &already) == ERESTART) 4801 goto restart; 4802 #endif 4803 goto done; 4804 } 4805 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 4806 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 4807 4808 if (rc == sc->pf) { 4809 sc->flags |= MASTER_PF; 4810 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4811 NULL, &already); 4812 if (rc == ERESTART) 4813 rc = 0; 4814 else if (rc != 0) 4815 goto done; 4816 } else if (state == DEV_STATE_UNINIT) { 4817 /* 4818 * We didn't get to be the master so we definitely won't be 4819 * configuring the chip. It's a bug if someone else hasn't 4820 * configured it already. 4821 */ 4822 device_printf(sc->dev, "couldn't be master(%d), " 4823 "device not already initialized either(%d). " 4824 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4825 rc = EPROTO; 4826 goto done; 4827 } else { 4828 /* 4829 * Some other PF is the master and has configured the chip. 4830 * This is allowed but untested. 4831 */ 4832 device_printf(sc->dev, "PF%d is master, device state %d. " 4833 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4834 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 4835 sc->cfcsum = 0; 4836 rc = 0; 4837 } 4838 done: 4839 if (rc != 0 && sc->flags & FW_OK) { 4840 t4_fw_bye(sc, sc->mbox); 4841 sc->flags &= ~FW_OK; 4842 } 4843 free(card_fw, M_CXGBE); 4844 return (rc); 4845 } 4846 4847 static int 4848 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 4849 uint32_t mtype, uint32_t moff) 4850 { 4851 struct fw_info *fw_info; 4852 const struct firmware *dcfg, *rcfg = NULL; 4853 const uint32_t *cfdata; 4854 uint32_t cflen, addr; 4855 int rc; 4856 4857 load_fw_module(sc, &dcfg, NULL); 4858 4859 /* Card specific interpretation of "default". */ 4860 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4861 if (pci_get_device(sc->dev) == 0x440a) 4862 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 4863 if (is_fpga(sc)) 4864 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 4865 } 4866 4867 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4868 if (dcfg == NULL) { 4869 device_printf(sc->dev, 4870 "KLD with default config is not available.\n"); 4871 rc = ENOENT; 4872 goto done; 4873 } 4874 cfdata = dcfg->data; 4875 cflen = dcfg->datasize & ~3; 4876 } else { 4877 char s[32]; 4878 4879 fw_info = find_fw_info(chip_id(sc)); 4880 if (fw_info == NULL) { 4881 device_printf(sc->dev, 4882 "unable to look up firmware information for chip %d.\n", 4883 chip_id(sc)); 4884 rc = EINVAL; 4885 goto done; 4886 } 4887 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 4888 4889 rcfg = firmware_get(s); 4890 if (rcfg == NULL) { 4891 device_printf(sc->dev, 4892 "unable to load module \"%s\" for configuration " 4893 "profile \"%s\".\n", s, cfg_file); 4894 rc = ENOENT; 4895 goto done; 4896 } 4897 cfdata = rcfg->data; 4898 cflen = rcfg->datasize & ~3; 4899 } 4900 4901 if (cflen > FLASH_CFG_MAX_SIZE) { 4902 device_printf(sc->dev, 4903 "config file too long (%d, max allowed is %d).\n", 4904 cflen, FLASH_CFG_MAX_SIZE); 4905 rc = EINVAL; 4906 goto done; 4907 } 4908 4909 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 4910 if (rc != 0) { 4911 device_printf(sc->dev, 4912 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 4913 __func__, mtype, moff, cflen, rc); 4914 rc = EINVAL; 4915 goto done; 4916 } 4917 write_via_memwin(sc, 2, addr, cfdata, cflen); 4918 done: 4919 if (rcfg != NULL) 4920 firmware_put(rcfg, FIRMWARE_UNLOAD); 4921 unload_fw_module(sc, dcfg, NULL); 4922 return (rc); 4923 } 4924 4925 struct caps_allowed { 4926 uint16_t nbmcaps; 4927 uint16_t linkcaps; 4928 uint16_t switchcaps; 4929 uint16_t niccaps; 4930 uint16_t toecaps; 4931 uint16_t rdmacaps; 4932 uint16_t cryptocaps; 4933 uint16_t iscsicaps; 4934 uint16_t fcoecaps; 4935 }; 4936 4937 #define FW_PARAM_DEV(param) \ 4938 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 4939 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 4940 #define FW_PARAM_PFVF(param) \ 4941 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 4942 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 4943 4944 /* 4945 * Provide a configuration profile to the firmware and have it initialize the 4946 * chip accordingly. This may involve uploading a configuration file to the 4947 * card. 4948 */ 4949 static int 4950 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 4951 const struct caps_allowed *caps_allowed) 4952 { 4953 int rc; 4954 struct fw_caps_config_cmd caps; 4955 uint32_t mtype, moff, finicsum, cfcsum, param, val; 4956 4957 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 4958 if (rc != 0) { 4959 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 4960 return (rc); 4961 } 4962 4963 bzero(&caps, sizeof(caps)); 4964 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4965 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4966 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 4967 mtype = 0; 4968 moff = 0; 4969 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4970 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 4971 mtype = FW_MEMTYPE_FLASH; 4972 moff = t4_flash_cfg_addr(sc); 4973 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4974 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4975 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4976 FW_LEN16(caps)); 4977 } else { 4978 /* 4979 * Ask the firmware where it wants us to upload the config file. 4980 */ 4981 param = FW_PARAM_DEV(CF); 4982 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4983 if (rc != 0) { 4984 /* No support for config file? Shouldn't happen. */ 4985 device_printf(sc->dev, 4986 "failed to query config file location: %d.\n", rc); 4987 goto done; 4988 } 4989 mtype = G_FW_PARAMS_PARAM_Y(val); 4990 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 4991 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4992 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4993 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4994 FW_LEN16(caps)); 4995 4996 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 4997 if (rc != 0) { 4998 device_printf(sc->dev, 4999 "failed to upload config file to card: %d.\n", rc); 5000 goto done; 5001 } 5002 } 5003 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5004 if (rc != 0) { 5005 device_printf(sc->dev, "failed to pre-process config file: %d " 5006 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 5007 goto done; 5008 } 5009 5010 finicsum = be32toh(caps.finicsum); 5011 cfcsum = be32toh(caps.cfcsum); /* actual */ 5012 if (finicsum != cfcsum) { 5013 device_printf(sc->dev, 5014 "WARNING: config file checksum mismatch: %08x %08x\n", 5015 finicsum, cfcsum); 5016 } 5017 sc->cfcsum = cfcsum; 5018 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 5019 5020 /* 5021 * Let the firmware know what features will (not) be used so it can tune 5022 * things accordingly. 5023 */ 5024 #define LIMIT_CAPS(x) do { \ 5025 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 5026 } while (0) 5027 LIMIT_CAPS(nbm); 5028 LIMIT_CAPS(link); 5029 LIMIT_CAPS(switch); 5030 LIMIT_CAPS(nic); 5031 LIMIT_CAPS(toe); 5032 LIMIT_CAPS(rdma); 5033 LIMIT_CAPS(crypto); 5034 LIMIT_CAPS(iscsi); 5035 LIMIT_CAPS(fcoe); 5036 #undef LIMIT_CAPS 5037 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 5038 /* 5039 * TOE and hashfilters are mutually exclusive. It is a config 5040 * file or firmware bug if both are reported as available. Try 5041 * to cope with the situation in non-debug builds by disabling 5042 * TOE. 5043 */ 5044 MPASS(caps.toecaps == 0); 5045 5046 caps.toecaps = 0; 5047 caps.rdmacaps = 0; 5048 caps.iscsicaps = 0; 5049 } 5050 5051 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5052 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5053 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5054 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 5055 if (rc != 0) { 5056 device_printf(sc->dev, 5057 "failed to process config file: %d.\n", rc); 5058 goto done; 5059 } 5060 5061 t4_tweak_chip_settings(sc); 5062 set_params__pre_init(sc); 5063 5064 /* get basic stuff going */ 5065 rc = -t4_fw_initialize(sc, sc->mbox); 5066 if (rc != 0) { 5067 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 5068 goto done; 5069 } 5070 done: 5071 return (rc); 5072 } 5073 5074 /* 5075 * Partition chip resources for use between various PFs, VFs, etc. 5076 */ 5077 static int 5078 partition_resources(struct adapter *sc) 5079 { 5080 char cfg_file[sizeof(t4_cfg_file)]; 5081 struct caps_allowed caps_allowed; 5082 int rc; 5083 bool fallback; 5084 5085 /* Only the master driver gets to configure the chip resources. */ 5086 MPASS(sc->flags & MASTER_PF); 5087 5088 #define COPY_CAPS(x) do { \ 5089 caps_allowed.x##caps = t4_##x##caps_allowed; \ 5090 } while (0) 5091 bzero(&caps_allowed, sizeof(caps_allowed)); 5092 COPY_CAPS(nbm); 5093 COPY_CAPS(link); 5094 COPY_CAPS(switch); 5095 COPY_CAPS(nic); 5096 COPY_CAPS(toe); 5097 COPY_CAPS(rdma); 5098 COPY_CAPS(crypto); 5099 COPY_CAPS(iscsi); 5100 COPY_CAPS(fcoe); 5101 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 5102 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 5103 retry: 5104 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 5105 if (rc != 0 && fallback) { 5106 device_printf(sc->dev, 5107 "failed (%d) to configure card with \"%s\" profile, " 5108 "will fall back to a basic configuration and retry.\n", 5109 rc, cfg_file); 5110 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 5111 bzero(&caps_allowed, sizeof(caps_allowed)); 5112 COPY_CAPS(switch); 5113 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 5114 fallback = false; 5115 goto retry; 5116 } 5117 #undef COPY_CAPS 5118 return (rc); 5119 } 5120 5121 /* 5122 * Retrieve parameters that are needed (or nice to have) very early. 5123 */ 5124 static int 5125 get_params__pre_init(struct adapter *sc) 5126 { 5127 int rc; 5128 uint32_t param[2], val[2]; 5129 5130 t4_get_version_info(sc); 5131 5132 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 5133 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 5134 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 5135 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 5136 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 5137 5138 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 5139 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 5140 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 5141 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 5142 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 5143 5144 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 5145 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 5146 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 5147 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 5148 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 5149 5150 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 5151 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 5152 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 5153 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 5154 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 5155 5156 param[0] = FW_PARAM_DEV(PORTVEC); 5157 param[1] = FW_PARAM_DEV(CCLK); 5158 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5159 if (rc != 0) { 5160 device_printf(sc->dev, 5161 "failed to query parameters (pre_init): %d.\n", rc); 5162 return (rc); 5163 } 5164 5165 sc->params.portvec = val[0]; 5166 sc->params.nports = bitcount32(val[0]); 5167 sc->params.vpd.cclk = val[1]; 5168 5169 /* Read device log parameters. */ 5170 rc = -t4_init_devlog_params(sc, 1); 5171 if (rc == 0) 5172 fixup_devlog_params(sc); 5173 else { 5174 device_printf(sc->dev, 5175 "failed to get devlog parameters: %d.\n", rc); 5176 rc = 0; /* devlog isn't critical for device operation */ 5177 } 5178 5179 return (rc); 5180 } 5181 5182 /* 5183 * Any params that need to be set before FW_INITIALIZE. 5184 */ 5185 static int 5186 set_params__pre_init(struct adapter *sc) 5187 { 5188 int rc = 0; 5189 uint32_t param, val; 5190 5191 if (chip_id(sc) >= CHELSIO_T6) { 5192 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 5193 val = 1; 5194 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5195 /* firmwares < 1.20.1.0 do not have this param. */ 5196 if (rc == FW_EINVAL && 5197 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) { 5198 rc = 0; 5199 } 5200 if (rc != 0) { 5201 device_printf(sc->dev, 5202 "failed to enable high priority filters :%d.\n", 5203 rc); 5204 } 5205 5206 param = FW_PARAM_DEV(PPOD_EDRAM); 5207 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5208 if (rc == 0 && val == 1) { 5209 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, 5210 &val); 5211 if (rc != 0) { 5212 device_printf(sc->dev, 5213 "failed to set PPOD_EDRAM: %d.\n", rc); 5214 } 5215 } 5216 } 5217 5218 /* Enable opaque VIIDs with firmwares that support it. */ 5219 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 5220 val = 1; 5221 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5222 if (rc == 0 && val == 1) 5223 sc->params.viid_smt_extn_support = true; 5224 else 5225 sc->params.viid_smt_extn_support = false; 5226 5227 return (rc); 5228 } 5229 5230 /* 5231 * Retrieve various parameters that are of interest to the driver. The device 5232 * has been initialized by the firmware at this point. 5233 */ 5234 static int 5235 get_params__post_init(struct adapter *sc) 5236 { 5237 int rc; 5238 uint32_t param[7], val[7]; 5239 struct fw_caps_config_cmd caps; 5240 5241 param[0] = FW_PARAM_PFVF(IQFLINT_START); 5242 param[1] = FW_PARAM_PFVF(EQ_START); 5243 param[2] = FW_PARAM_PFVF(FILTER_START); 5244 param[3] = FW_PARAM_PFVF(FILTER_END); 5245 param[4] = FW_PARAM_PFVF(L2T_START); 5246 param[5] = FW_PARAM_PFVF(L2T_END); 5247 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5248 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5249 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 5250 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 5251 if (rc != 0) { 5252 device_printf(sc->dev, 5253 "failed to query parameters (post_init): %d.\n", rc); 5254 return (rc); 5255 } 5256 5257 sc->sge.iq_start = val[0]; 5258 sc->sge.eq_start = val[1]; 5259 if ((int)val[3] > (int)val[2]) { 5260 sc->tids.ftid_base = val[2]; 5261 sc->tids.ftid_end = val[3]; 5262 sc->tids.nftids = val[3] - val[2] + 1; 5263 } 5264 sc->vres.l2t.start = val[4]; 5265 sc->vres.l2t.size = val[5] - val[4] + 1; 5266 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 5267 ("%s: L2 table size (%u) larger than expected (%u)", 5268 __func__, sc->vres.l2t.size, L2T_SIZE)); 5269 sc->params.core_vdd = val[6]; 5270 5271 param[0] = FW_PARAM_PFVF(IQFLINT_END); 5272 param[1] = FW_PARAM_PFVF(EQ_END); 5273 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5274 if (rc != 0) { 5275 device_printf(sc->dev, 5276 "failed to query parameters (post_init2): %d.\n", rc); 5277 return (rc); 5278 } 5279 MPASS((int)val[0] >= sc->sge.iq_start); 5280 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1; 5281 MPASS((int)val[1] >= sc->sge.eq_start); 5282 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1; 5283 5284 if (chip_id(sc) >= CHELSIO_T6) { 5285 5286 sc->tids.tid_base = t4_read_reg(sc, 5287 A_LE_DB_ACTIVE_TABLE_START_INDEX); 5288 5289 param[0] = FW_PARAM_PFVF(HPFILTER_START); 5290 param[1] = FW_PARAM_PFVF(HPFILTER_END); 5291 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5292 if (rc != 0) { 5293 device_printf(sc->dev, 5294 "failed to query hpfilter parameters: %d.\n", rc); 5295 return (rc); 5296 } 5297 if ((int)val[1] > (int)val[0]) { 5298 sc->tids.hpftid_base = val[0]; 5299 sc->tids.hpftid_end = val[1]; 5300 sc->tids.nhpftids = val[1] - val[0] + 1; 5301 5302 /* 5303 * These should go off if the layout changes and the 5304 * driver needs to catch up. 5305 */ 5306 MPASS(sc->tids.hpftid_base == 0); 5307 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 5308 } 5309 5310 param[0] = FW_PARAM_PFVF(RAWF_START); 5311 param[1] = FW_PARAM_PFVF(RAWF_END); 5312 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5313 if (rc != 0) { 5314 device_printf(sc->dev, 5315 "failed to query rawf parameters: %d.\n", rc); 5316 return (rc); 5317 } 5318 if ((int)val[1] > (int)val[0]) { 5319 sc->rawf_base = val[0]; 5320 sc->nrawf = val[1] - val[0] + 1; 5321 } 5322 } 5323 5324 /* 5325 * MPSBGMAP is queried separately because only recent firmwares support 5326 * it as a parameter and we don't want the compound query above to fail 5327 * on older firmwares. 5328 */ 5329 param[0] = FW_PARAM_DEV(MPSBGMAP); 5330 val[0] = 0; 5331 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5332 if (rc == 0) 5333 sc->params.mps_bg_map = val[0]; 5334 else 5335 sc->params.mps_bg_map = 0; 5336 5337 /* 5338 * Determine whether the firmware supports the filter2 work request. 5339 * This is queried separately for the same reason as MPSBGMAP above. 5340 */ 5341 param[0] = FW_PARAM_DEV(FILTER2_WR); 5342 val[0] = 0; 5343 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5344 if (rc == 0) 5345 sc->params.filter2_wr_support = val[0] != 0; 5346 else 5347 sc->params.filter2_wr_support = 0; 5348 5349 /* 5350 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 5351 * This is queried separately for the same reason as other params above. 5352 */ 5353 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 5354 val[0] = 0; 5355 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5356 if (rc == 0) 5357 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 5358 else 5359 sc->params.ulptx_memwrite_dsgl = false; 5360 5361 /* FW_RI_FR_NSMR_TPTE_WR support */ 5362 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 5363 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5364 if (rc == 0) 5365 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0; 5366 else 5367 sc->params.fr_nsmr_tpte_wr_support = false; 5368 5369 /* Support for 512 SGL entries per FR MR. */ 5370 param[0] = FW_PARAM_DEV(DEV_512SGL_MR); 5371 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5372 if (rc == 0) 5373 sc->params.dev_512sgl_mr = val[0] != 0; 5374 else 5375 sc->params.dev_512sgl_mr = false; 5376 5377 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 5378 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5379 if (rc == 0) 5380 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0]; 5381 else 5382 sc->params.max_pkts_per_eth_tx_pkts_wr = 15; 5383 5384 param[0] = FW_PARAM_DEV(NUM_TM_CLASS); 5385 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5386 if (rc == 0) { 5387 MPASS(val[0] > 0 && val[0] < 256); /* nsched_cls is 8b */ 5388 sc->params.nsched_cls = val[0]; 5389 } else 5390 sc->params.nsched_cls = sc->chip_params->nsched_cls; 5391 5392 /* get capabilites */ 5393 bzero(&caps, sizeof(caps)); 5394 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5395 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5396 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5397 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5398 if (rc != 0) { 5399 device_printf(sc->dev, 5400 "failed to get card capabilities: %d.\n", rc); 5401 return (rc); 5402 } 5403 5404 #define READ_CAPS(x) do { \ 5405 sc->x = htobe16(caps.x); \ 5406 } while (0) 5407 READ_CAPS(nbmcaps); 5408 READ_CAPS(linkcaps); 5409 READ_CAPS(switchcaps); 5410 READ_CAPS(niccaps); 5411 READ_CAPS(toecaps); 5412 READ_CAPS(rdmacaps); 5413 READ_CAPS(cryptocaps); 5414 READ_CAPS(iscsicaps); 5415 READ_CAPS(fcoecaps); 5416 5417 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 5418 MPASS(chip_id(sc) > CHELSIO_T4); 5419 MPASS(sc->toecaps == 0); 5420 sc->toecaps = 0; 5421 5422 param[0] = FW_PARAM_DEV(NTID); 5423 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5424 if (rc != 0) { 5425 device_printf(sc->dev, 5426 "failed to query HASHFILTER parameters: %d.\n", rc); 5427 return (rc); 5428 } 5429 sc->tids.ntids = val[0]; 5430 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5431 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5432 sc->tids.ntids -= sc->tids.nhpftids; 5433 } 5434 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5435 sc->params.hash_filter = 1; 5436 } 5437 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 5438 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 5439 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 5440 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5441 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 5442 if (rc != 0) { 5443 device_printf(sc->dev, 5444 "failed to query NIC parameters: %d.\n", rc); 5445 return (rc); 5446 } 5447 if ((int)val[1] > (int)val[0]) { 5448 sc->tids.etid_base = val[0]; 5449 sc->tids.etid_end = val[1]; 5450 sc->tids.netids = val[1] - val[0] + 1; 5451 sc->params.eo_wr_cred = val[2]; 5452 sc->params.ethoffload = 1; 5453 } 5454 } 5455 if (sc->toecaps) { 5456 /* query offload-related parameters */ 5457 param[0] = FW_PARAM_DEV(NTID); 5458 param[1] = FW_PARAM_PFVF(SERVER_START); 5459 param[2] = FW_PARAM_PFVF(SERVER_END); 5460 param[3] = FW_PARAM_PFVF(TDDP_START); 5461 param[4] = FW_PARAM_PFVF(TDDP_END); 5462 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5463 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5464 if (rc != 0) { 5465 device_printf(sc->dev, 5466 "failed to query TOE parameters: %d.\n", rc); 5467 return (rc); 5468 } 5469 sc->tids.ntids = val[0]; 5470 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5471 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5472 sc->tids.ntids -= sc->tids.nhpftids; 5473 } 5474 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5475 if ((int)val[2] > (int)val[1]) { 5476 sc->tids.stid_base = val[1]; 5477 sc->tids.nstids = val[2] - val[1] + 1; 5478 } 5479 sc->vres.ddp.start = val[3]; 5480 sc->vres.ddp.size = val[4] - val[3] + 1; 5481 sc->params.ofldq_wr_cred = val[5]; 5482 sc->params.offload = 1; 5483 } else { 5484 /* 5485 * The firmware attempts memfree TOE configuration for -SO cards 5486 * and will report toecaps=0 if it runs out of resources (this 5487 * depends on the config file). It may not report 0 for other 5488 * capabilities dependent on the TOE in this case. Set them to 5489 * 0 here so that the driver doesn't bother tracking resources 5490 * that will never be used. 5491 */ 5492 sc->iscsicaps = 0; 5493 sc->rdmacaps = 0; 5494 } 5495 if (sc->rdmacaps) { 5496 param[0] = FW_PARAM_PFVF(STAG_START); 5497 param[1] = FW_PARAM_PFVF(STAG_END); 5498 param[2] = FW_PARAM_PFVF(RQ_START); 5499 param[3] = FW_PARAM_PFVF(RQ_END); 5500 param[4] = FW_PARAM_PFVF(PBL_START); 5501 param[5] = FW_PARAM_PFVF(PBL_END); 5502 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5503 if (rc != 0) { 5504 device_printf(sc->dev, 5505 "failed to query RDMA parameters(1): %d.\n", rc); 5506 return (rc); 5507 } 5508 sc->vres.stag.start = val[0]; 5509 sc->vres.stag.size = val[1] - val[0] + 1; 5510 sc->vres.rq.start = val[2]; 5511 sc->vres.rq.size = val[3] - val[2] + 1; 5512 sc->vres.pbl.start = val[4]; 5513 sc->vres.pbl.size = val[5] - val[4] + 1; 5514 5515 param[0] = FW_PARAM_PFVF(SQRQ_START); 5516 param[1] = FW_PARAM_PFVF(SQRQ_END); 5517 param[2] = FW_PARAM_PFVF(CQ_START); 5518 param[3] = FW_PARAM_PFVF(CQ_END); 5519 param[4] = FW_PARAM_PFVF(OCQ_START); 5520 param[5] = FW_PARAM_PFVF(OCQ_END); 5521 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5522 if (rc != 0) { 5523 device_printf(sc->dev, 5524 "failed to query RDMA parameters(2): %d.\n", rc); 5525 return (rc); 5526 } 5527 sc->vres.qp.start = val[0]; 5528 sc->vres.qp.size = val[1] - val[0] + 1; 5529 sc->vres.cq.start = val[2]; 5530 sc->vres.cq.size = val[3] - val[2] + 1; 5531 sc->vres.ocq.start = val[4]; 5532 sc->vres.ocq.size = val[5] - val[4] + 1; 5533 5534 param[0] = FW_PARAM_PFVF(SRQ_START); 5535 param[1] = FW_PARAM_PFVF(SRQ_END); 5536 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 5537 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 5538 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 5539 if (rc != 0) { 5540 device_printf(sc->dev, 5541 "failed to query RDMA parameters(3): %d.\n", rc); 5542 return (rc); 5543 } 5544 sc->vres.srq.start = val[0]; 5545 sc->vres.srq.size = val[1] - val[0] + 1; 5546 sc->params.max_ordird_qp = val[2]; 5547 sc->params.max_ird_adapter = val[3]; 5548 } 5549 if (sc->iscsicaps) { 5550 param[0] = FW_PARAM_PFVF(ISCSI_START); 5551 param[1] = FW_PARAM_PFVF(ISCSI_END); 5552 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5553 if (rc != 0) { 5554 device_printf(sc->dev, 5555 "failed to query iSCSI parameters: %d.\n", rc); 5556 return (rc); 5557 } 5558 sc->vres.iscsi.start = val[0]; 5559 sc->vres.iscsi.size = val[1] - val[0] + 1; 5560 } 5561 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 5562 param[0] = FW_PARAM_PFVF(TLS_START); 5563 param[1] = FW_PARAM_PFVF(TLS_END); 5564 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5565 if (rc != 0) { 5566 device_printf(sc->dev, 5567 "failed to query TLS parameters: %d.\n", rc); 5568 return (rc); 5569 } 5570 sc->vres.key.start = val[0]; 5571 sc->vres.key.size = val[1] - val[0] + 1; 5572 } 5573 5574 /* 5575 * We've got the params we wanted to query directly from the firmware. 5576 * Grab some others via other means. 5577 */ 5578 t4_init_sge_params(sc); 5579 t4_init_tp_params(sc); 5580 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 5581 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 5582 5583 rc = t4_verify_chip_settings(sc); 5584 if (rc != 0) 5585 return (rc); 5586 t4_init_rx_buf_info(sc); 5587 5588 return (rc); 5589 } 5590 5591 #ifdef KERN_TLS 5592 static void 5593 ktls_tick(void *arg) 5594 { 5595 struct adapter *sc; 5596 uint32_t tstamp; 5597 5598 sc = arg; 5599 tstamp = tcp_ts_getticks(); 5600 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1); 5601 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31); 5602 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK); 5603 } 5604 5605 static int 5606 t6_config_kern_tls(struct adapter *sc, bool enable) 5607 { 5608 int rc; 5609 uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5610 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) | 5611 V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) | 5612 V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE); 5613 5614 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, ¶m); 5615 if (rc != 0) { 5616 CH_ERR(sc, "failed to %s NIC TLS: %d\n", 5617 enable ? "enable" : "disable", rc); 5618 return (rc); 5619 } 5620 5621 if (enable) { 5622 sc->flags |= KERN_TLS_ON; 5623 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc, 5624 C_HARDCLOCK); 5625 } else { 5626 sc->flags &= ~KERN_TLS_ON; 5627 callout_stop(&sc->ktls_tick); 5628 } 5629 5630 return (rc); 5631 } 5632 #endif 5633 5634 static int 5635 set_params__post_init(struct adapter *sc) 5636 { 5637 uint32_t mask, param, val; 5638 #ifdef TCP_OFFLOAD 5639 int i, v, shift; 5640 #endif 5641 5642 /* ask for encapsulated CPLs */ 5643 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 5644 val = 1; 5645 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5646 5647 /* Enable 32b port caps if the firmware supports it. */ 5648 param = FW_PARAM_PFVF(PORT_CAPS32); 5649 val = 1; 5650 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 5651 sc->params.port_caps32 = 1; 5652 5653 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 5654 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 5655 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 5656 V_MASKFILTER(val - 1)); 5657 5658 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER | 5659 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN | 5660 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5661 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM; 5662 val = 0; 5663 if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) { 5664 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE, 5665 F_ATTACKFILTERENABLE); 5666 val |= F_DROPERRORATTACK; 5667 } 5668 if (t4_drop_ip_fragments != 0) { 5669 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP, 5670 F_FRAGMENTDROP); 5671 val |= F_DROPERRORFRAG; 5672 } 5673 if (t4_drop_pkts_with_l2_errors != 0) 5674 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN; 5675 if (t4_drop_pkts_with_l3_errors != 0) { 5676 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN | 5677 F_DROPERRORCSUMIP; 5678 } 5679 if (t4_drop_pkts_with_l4_errors != 0) { 5680 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5681 F_DROPERRORTCPOPT | F_DROPERRORCSUM; 5682 } 5683 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val); 5684 5685 #ifdef TCP_OFFLOAD 5686 /* 5687 * Override the TOE timers with user provided tunables. This is not the 5688 * recommended way to change the timers (the firmware config file is) so 5689 * these tunables are not documented. 5690 * 5691 * All the timer tunables are in microseconds. 5692 */ 5693 if (t4_toe_keepalive_idle != 0) { 5694 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 5695 v &= M_KEEPALIVEIDLE; 5696 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 5697 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 5698 } 5699 if (t4_toe_keepalive_interval != 0) { 5700 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 5701 v &= M_KEEPALIVEINTVL; 5702 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 5703 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 5704 } 5705 if (t4_toe_keepalive_count != 0) { 5706 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 5707 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5708 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 5709 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 5710 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 5711 } 5712 if (t4_toe_rexmt_min != 0) { 5713 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 5714 v &= M_RXTMIN; 5715 t4_set_reg_field(sc, A_TP_RXT_MIN, 5716 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 5717 } 5718 if (t4_toe_rexmt_max != 0) { 5719 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 5720 v &= M_RXTMAX; 5721 t4_set_reg_field(sc, A_TP_RXT_MAX, 5722 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 5723 } 5724 if (t4_toe_rexmt_count != 0) { 5725 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 5726 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5727 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 5728 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 5729 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 5730 } 5731 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 5732 if (t4_toe_rexmt_backoff[i] != -1) { 5733 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 5734 shift = (i & 3) << 3; 5735 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 5736 M_TIMERBACKOFFINDEX0 << shift, v << shift); 5737 } 5738 } 5739 #endif 5740 5741 #ifdef KERN_TLS 5742 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 5743 sc->toecaps & FW_CAPS_CONFIG_TOE) { 5744 /* 5745 * Limit TOE connections to 2 reassembly "islands". This is 5746 * required for TOE TLS connections to downgrade to plain TOE 5747 * connections if an unsupported TLS version or ciphersuite is 5748 * used. 5749 */ 5750 t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, 5751 V_PASSMODE(M_PASSMODE), V_PASSMODE(2)); 5752 } 5753 5754 if (is_ktls(sc)) { 5755 sc->tlst.inline_keys = t4_tls_inline_keys; 5756 sc->tlst.combo_wrs = t4_tls_combo_wrs; 5757 if (t4_kern_tls != 0 && is_t6(sc)) 5758 t6_config_kern_tls(sc, true); 5759 } 5760 #endif 5761 return (0); 5762 } 5763 5764 #undef FW_PARAM_PFVF 5765 #undef FW_PARAM_DEV 5766 5767 static void 5768 t4_set_desc(struct adapter *sc) 5769 { 5770 char buf[128]; 5771 struct adapter_params *p = &sc->params; 5772 5773 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 5774 5775 device_set_desc_copy(sc->dev, buf); 5776 } 5777 5778 static inline void 5779 ifmedia_add4(struct ifmedia *ifm, int m) 5780 { 5781 5782 ifmedia_add(ifm, m, 0, NULL); 5783 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 5784 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 5785 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 5786 } 5787 5788 /* 5789 * This is the selected media, which is not quite the same as the active media. 5790 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 5791 * and active are not the same, and "media: Ethernet selected" otherwise. 5792 */ 5793 static void 5794 set_current_media(struct port_info *pi) 5795 { 5796 struct link_config *lc; 5797 struct ifmedia *ifm; 5798 int mword; 5799 u_int speed; 5800 5801 PORT_LOCK_ASSERT_OWNED(pi); 5802 5803 /* Leave current media alone if it's already set to IFM_NONE. */ 5804 ifm = &pi->media; 5805 if (ifm->ifm_cur != NULL && 5806 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 5807 return; 5808 5809 lc = &pi->link_cfg; 5810 if (lc->requested_aneg != AUTONEG_DISABLE && 5811 lc->pcaps & FW_PORT_CAP32_ANEG) { 5812 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 5813 return; 5814 } 5815 mword = IFM_ETHER | IFM_FDX; 5816 if (lc->requested_fc & PAUSE_TX) 5817 mword |= IFM_ETH_TXPAUSE; 5818 if (lc->requested_fc & PAUSE_RX) 5819 mword |= IFM_ETH_RXPAUSE; 5820 if (lc->requested_speed == 0) 5821 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 5822 else 5823 speed = lc->requested_speed; 5824 mword |= port_mword(pi, speed_to_fwcap(speed)); 5825 ifmedia_set(ifm, mword); 5826 } 5827 5828 /* 5829 * Returns true if the ifmedia list for the port cannot change. 5830 */ 5831 static bool 5832 fixed_ifmedia(struct port_info *pi) 5833 { 5834 5835 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 5836 pi->port_type == FW_PORT_TYPE_BT_XFI || 5837 pi->port_type == FW_PORT_TYPE_BT_XAUI || 5838 pi->port_type == FW_PORT_TYPE_KX4 || 5839 pi->port_type == FW_PORT_TYPE_KX || 5840 pi->port_type == FW_PORT_TYPE_KR || 5841 pi->port_type == FW_PORT_TYPE_BP_AP || 5842 pi->port_type == FW_PORT_TYPE_BP4_AP || 5843 pi->port_type == FW_PORT_TYPE_BP40_BA || 5844 pi->port_type == FW_PORT_TYPE_KR4_100G || 5845 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 5846 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 5847 } 5848 5849 static void 5850 build_medialist(struct port_info *pi) 5851 { 5852 uint32_t ss, speed; 5853 int unknown, mword, bit; 5854 struct link_config *lc; 5855 struct ifmedia *ifm; 5856 5857 PORT_LOCK_ASSERT_OWNED(pi); 5858 5859 if (pi->flags & FIXED_IFMEDIA) 5860 return; 5861 5862 /* 5863 * Rebuild the ifmedia list. 5864 */ 5865 ifm = &pi->media; 5866 ifmedia_removeall(ifm); 5867 lc = &pi->link_cfg; 5868 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */ 5869 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 5870 MPASS(ss != 0); 5871 no_media: 5872 MPASS(LIST_EMPTY(&ifm->ifm_list)); 5873 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 5874 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 5875 return; 5876 } 5877 5878 unknown = 0; 5879 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 5880 speed = 1 << bit; 5881 MPASS(speed & M_FW_PORT_CAP32_SPEED); 5882 if (ss & speed) { 5883 mword = port_mword(pi, speed); 5884 if (mword == IFM_NONE) { 5885 goto no_media; 5886 } else if (mword == IFM_UNKNOWN) 5887 unknown++; 5888 else 5889 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 5890 } 5891 } 5892 if (unknown > 0) /* Add one unknown for all unknown media types. */ 5893 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 5894 if (lc->pcaps & FW_PORT_CAP32_ANEG) 5895 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 5896 5897 set_current_media(pi); 5898 } 5899 5900 /* 5901 * Initialize the requested fields in the link config based on driver tunables. 5902 */ 5903 static void 5904 init_link_config(struct port_info *pi) 5905 { 5906 struct link_config *lc = &pi->link_cfg; 5907 5908 PORT_LOCK_ASSERT_OWNED(pi); 5909 5910 lc->requested_caps = 0; 5911 lc->requested_speed = 0; 5912 5913 if (t4_autoneg == 0) 5914 lc->requested_aneg = AUTONEG_DISABLE; 5915 else if (t4_autoneg == 1) 5916 lc->requested_aneg = AUTONEG_ENABLE; 5917 else 5918 lc->requested_aneg = AUTONEG_AUTO; 5919 5920 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 5921 PAUSE_AUTONEG); 5922 5923 if (t4_fec & FEC_AUTO) 5924 lc->requested_fec = FEC_AUTO; 5925 else if (t4_fec == 0) 5926 lc->requested_fec = FEC_NONE; 5927 else { 5928 /* -1 is handled by the FEC_AUTO block above and not here. */ 5929 lc->requested_fec = t4_fec & 5930 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE); 5931 if (lc->requested_fec == 0) 5932 lc->requested_fec = FEC_AUTO; 5933 } 5934 if (t4_force_fec < 0) 5935 lc->force_fec = -1; 5936 else if (t4_force_fec > 0) 5937 lc->force_fec = 1; 5938 else 5939 lc->force_fec = 0; 5940 } 5941 5942 /* 5943 * Makes sure that all requested settings comply with what's supported by the 5944 * port. Returns the number of settings that were invalid and had to be fixed. 5945 */ 5946 static int 5947 fixup_link_config(struct port_info *pi) 5948 { 5949 int n = 0; 5950 struct link_config *lc = &pi->link_cfg; 5951 uint32_t fwspeed; 5952 5953 PORT_LOCK_ASSERT_OWNED(pi); 5954 5955 /* Speed (when not autonegotiating) */ 5956 if (lc->requested_speed != 0) { 5957 fwspeed = speed_to_fwcap(lc->requested_speed); 5958 if ((fwspeed & lc->pcaps) == 0) { 5959 n++; 5960 lc->requested_speed = 0; 5961 } 5962 } 5963 5964 /* Link autonegotiation */ 5965 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 5966 lc->requested_aneg == AUTONEG_DISABLE || 5967 lc->requested_aneg == AUTONEG_AUTO); 5968 if (lc->requested_aneg == AUTONEG_ENABLE && 5969 !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 5970 n++; 5971 lc->requested_aneg = AUTONEG_AUTO; 5972 } 5973 5974 /* Flow control */ 5975 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 5976 if (lc->requested_fc & PAUSE_TX && 5977 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) { 5978 n++; 5979 lc->requested_fc &= ~PAUSE_TX; 5980 } 5981 if (lc->requested_fc & PAUSE_RX && 5982 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) { 5983 n++; 5984 lc->requested_fc &= ~PAUSE_RX; 5985 } 5986 if (!(lc->requested_fc & PAUSE_AUTONEG) && 5987 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) { 5988 n++; 5989 lc->requested_fc |= PAUSE_AUTONEG; 5990 } 5991 5992 /* FEC */ 5993 if ((lc->requested_fec & FEC_RS && 5994 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) || 5995 (lc->requested_fec & FEC_BASER_RS && 5996 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) { 5997 n++; 5998 lc->requested_fec = FEC_AUTO; 5999 } 6000 6001 return (n); 6002 } 6003 6004 /* 6005 * Apply the requested L1 settings, which are expected to be valid, to the 6006 * hardware. 6007 */ 6008 static int 6009 apply_link_config(struct port_info *pi) 6010 { 6011 struct adapter *sc = pi->adapter; 6012 struct link_config *lc = &pi->link_cfg; 6013 int rc; 6014 6015 #ifdef INVARIANTS 6016 ASSERT_SYNCHRONIZED_OP(sc); 6017 PORT_LOCK_ASSERT_OWNED(pi); 6018 6019 if (lc->requested_aneg == AUTONEG_ENABLE) 6020 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG); 6021 if (!(lc->requested_fc & PAUSE_AUTONEG)) 6022 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE); 6023 if (lc->requested_fc & PAUSE_TX) 6024 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX); 6025 if (lc->requested_fc & PAUSE_RX) 6026 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX); 6027 if (lc->requested_fec & FEC_RS) 6028 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS); 6029 if (lc->requested_fec & FEC_BASER_RS) 6030 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS); 6031 #endif 6032 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6033 if (rc != 0) { 6034 /* Don't complain if the VF driver gets back an EPERM. */ 6035 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 6036 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 6037 } else { 6038 /* 6039 * An L1_CFG will almost always result in a link-change event if 6040 * the link is up, and the driver will refresh the actual 6041 * fec/fc/etc. when the notification is processed. If the link 6042 * is down then the actual settings are meaningless. 6043 * 6044 * This takes care of the case where a change in the L1 settings 6045 * may not result in a notification. 6046 */ 6047 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 6048 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 6049 } 6050 return (rc); 6051 } 6052 6053 #define FW_MAC_EXACT_CHUNK 7 6054 struct mcaddr_ctx { 6055 struct ifnet *ifp; 6056 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 6057 uint64_t hash; 6058 int i; 6059 int del; 6060 int rc; 6061 }; 6062 6063 static u_int 6064 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 6065 { 6066 struct mcaddr_ctx *ctx = arg; 6067 struct vi_info *vi = ctx->ifp->if_softc; 6068 struct port_info *pi = vi->pi; 6069 struct adapter *sc = pi->adapter; 6070 6071 if (ctx->rc < 0) 6072 return (0); 6073 6074 ctx->mcaddr[ctx->i] = LLADDR(sdl); 6075 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i])); 6076 ctx->i++; 6077 6078 if (ctx->i == FW_MAC_EXACT_CHUNK) { 6079 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del, 6080 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0); 6081 if (ctx->rc < 0) { 6082 int j; 6083 6084 for (j = 0; j < ctx->i; j++) { 6085 if_printf(ctx->ifp, 6086 "failed to add mc address" 6087 " %02x:%02x:%02x:" 6088 "%02x:%02x:%02x rc=%d\n", 6089 ctx->mcaddr[j][0], ctx->mcaddr[j][1], 6090 ctx->mcaddr[j][2], ctx->mcaddr[j][3], 6091 ctx->mcaddr[j][4], ctx->mcaddr[j][5], 6092 -ctx->rc); 6093 } 6094 return (0); 6095 } 6096 ctx->del = 0; 6097 ctx->i = 0; 6098 } 6099 6100 return (1); 6101 } 6102 6103 /* 6104 * Program the port's XGMAC based on parameters in ifnet. The caller also 6105 * indicates which parameters should be programmed (the rest are left alone). 6106 */ 6107 int 6108 update_mac_settings(struct ifnet *ifp, int flags) 6109 { 6110 int rc = 0; 6111 struct vi_info *vi = ifp->if_softc; 6112 struct port_info *pi = vi->pi; 6113 struct adapter *sc = pi->adapter; 6114 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 6115 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 6116 6117 ASSERT_SYNCHRONIZED_OP(sc); 6118 KASSERT(flags, ("%s: not told what to update.", __func__)); 6119 6120 if (flags & XGMAC_MTU) 6121 mtu = ifp->if_mtu; 6122 6123 if (flags & XGMAC_PROMISC) 6124 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 6125 6126 if (flags & XGMAC_ALLMULTI) 6127 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 6128 6129 if (flags & XGMAC_VLANEX) 6130 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 6131 6132 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 6133 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 6134 allmulti, 1, vlanex, false); 6135 if (rc) { 6136 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 6137 rc); 6138 return (rc); 6139 } 6140 } 6141 6142 if (flags & XGMAC_UCADDR) { 6143 uint8_t ucaddr[ETHER_ADDR_LEN]; 6144 6145 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 6146 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 6147 ucaddr, true, &vi->smt_idx); 6148 if (rc < 0) { 6149 rc = -rc; 6150 if_printf(ifp, "change_mac failed: %d\n", rc); 6151 return (rc); 6152 } else { 6153 vi->xact_addr_filt = rc; 6154 rc = 0; 6155 } 6156 } 6157 6158 if (flags & XGMAC_MCADDRS) { 6159 struct epoch_tracker et; 6160 struct mcaddr_ctx ctx; 6161 int j; 6162 6163 ctx.ifp = ifp; 6164 ctx.hash = 0; 6165 ctx.i = 0; 6166 ctx.del = 1; 6167 ctx.rc = 0; 6168 /* 6169 * Unlike other drivers, we accumulate list of pointers into 6170 * interface address lists and we need to keep it safe even 6171 * after if_foreach_llmaddr() returns, thus we must enter the 6172 * network epoch. 6173 */ 6174 NET_EPOCH_ENTER(et); 6175 if_foreach_llmaddr(ifp, add_maddr, &ctx); 6176 if (ctx.rc < 0) { 6177 NET_EPOCH_EXIT(et); 6178 rc = -ctx.rc; 6179 return (rc); 6180 } 6181 if (ctx.i > 0) { 6182 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 6183 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0); 6184 NET_EPOCH_EXIT(et); 6185 if (rc < 0) { 6186 rc = -rc; 6187 for (j = 0; j < ctx.i; j++) { 6188 if_printf(ifp, 6189 "failed to add mcast address" 6190 " %02x:%02x:%02x:" 6191 "%02x:%02x:%02x rc=%d\n", 6192 ctx.mcaddr[j][0], ctx.mcaddr[j][1], 6193 ctx.mcaddr[j][2], ctx.mcaddr[j][3], 6194 ctx.mcaddr[j][4], ctx.mcaddr[j][5], 6195 rc); 6196 } 6197 return (rc); 6198 } 6199 ctx.del = 0; 6200 } else 6201 NET_EPOCH_EXIT(et); 6202 6203 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0); 6204 if (rc != 0) 6205 if_printf(ifp, "failed to set mcast address hash: %d\n", 6206 rc); 6207 if (ctx.del == 0) { 6208 /* We clobbered the VXLAN entry if there was one. */ 6209 pi->vxlan_tcam_entry = false; 6210 } 6211 } 6212 6213 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 && 6214 pi->vxlan_tcam_entry == false) { 6215 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac, 6216 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 6217 true); 6218 if (rc < 0) { 6219 rc = -rc; 6220 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n", 6221 rc); 6222 } else { 6223 MPASS(rc == sc->rawf_base + pi->port_id); 6224 rc = 0; 6225 pi->vxlan_tcam_entry = true; 6226 } 6227 } 6228 6229 return (rc); 6230 } 6231 6232 /* 6233 * {begin|end}_synchronized_op must be called from the same thread. 6234 */ 6235 int 6236 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 6237 char *wmesg) 6238 { 6239 int rc, pri; 6240 6241 #ifdef WITNESS 6242 /* the caller thinks it's ok to sleep, but is it really? */ 6243 if (flags & SLEEP_OK) 6244 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 6245 "begin_synchronized_op"); 6246 #endif 6247 6248 if (INTR_OK) 6249 pri = PCATCH; 6250 else 6251 pri = 0; 6252 6253 ADAPTER_LOCK(sc); 6254 for (;;) { 6255 6256 if (vi && IS_DOOMED(vi)) { 6257 rc = ENXIO; 6258 goto done; 6259 } 6260 6261 if (!IS_BUSY(sc)) { 6262 rc = 0; 6263 break; 6264 } 6265 6266 if (!(flags & SLEEP_OK)) { 6267 rc = EBUSY; 6268 goto done; 6269 } 6270 6271 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 6272 rc = EINTR; 6273 goto done; 6274 } 6275 } 6276 6277 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 6278 SET_BUSY(sc); 6279 #ifdef INVARIANTS 6280 sc->last_op = wmesg; 6281 sc->last_op_thr = curthread; 6282 sc->last_op_flags = flags; 6283 #endif 6284 6285 done: 6286 if (!(flags & HOLD_LOCK) || rc) 6287 ADAPTER_UNLOCK(sc); 6288 6289 return (rc); 6290 } 6291 6292 /* 6293 * Tell if_ioctl and if_init that the VI is going away. This is 6294 * special variant of begin_synchronized_op and must be paired with a 6295 * call to end_synchronized_op. 6296 */ 6297 void 6298 doom_vi(struct adapter *sc, struct vi_info *vi) 6299 { 6300 6301 ADAPTER_LOCK(sc); 6302 SET_DOOMED(vi); 6303 wakeup(&sc->flags); 6304 while (IS_BUSY(sc)) 6305 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 6306 SET_BUSY(sc); 6307 #ifdef INVARIANTS 6308 sc->last_op = "t4detach"; 6309 sc->last_op_thr = curthread; 6310 sc->last_op_flags = 0; 6311 #endif 6312 ADAPTER_UNLOCK(sc); 6313 } 6314 6315 /* 6316 * {begin|end}_synchronized_op must be called from the same thread. 6317 */ 6318 void 6319 end_synchronized_op(struct adapter *sc, int flags) 6320 { 6321 6322 if (flags & LOCK_HELD) 6323 ADAPTER_LOCK_ASSERT_OWNED(sc); 6324 else 6325 ADAPTER_LOCK(sc); 6326 6327 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6328 CLR_BUSY(sc); 6329 wakeup(&sc->flags); 6330 ADAPTER_UNLOCK(sc); 6331 } 6332 6333 static int 6334 cxgbe_init_synchronized(struct vi_info *vi) 6335 { 6336 struct port_info *pi = vi->pi; 6337 struct adapter *sc = pi->adapter; 6338 struct ifnet *ifp = vi->ifp; 6339 int rc = 0, i; 6340 struct sge_txq *txq; 6341 6342 ASSERT_SYNCHRONIZED_OP(sc); 6343 6344 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6345 return (0); /* already running */ 6346 6347 if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0)) 6348 return (rc); /* error message displayed already */ 6349 6350 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 6351 return (rc); /* error message displayed already */ 6352 6353 rc = update_mac_settings(ifp, XGMAC_ALL); 6354 if (rc) 6355 goto done; /* error message displayed already */ 6356 6357 PORT_LOCK(pi); 6358 if (pi->up_vis == 0) { 6359 t4_update_port_info(pi); 6360 fixup_link_config(pi); 6361 build_medialist(pi); 6362 apply_link_config(pi); 6363 } 6364 6365 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 6366 if (rc != 0) { 6367 if_printf(ifp, "enable_vi failed: %d\n", rc); 6368 PORT_UNLOCK(pi); 6369 goto done; 6370 } 6371 6372 /* 6373 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 6374 * if this changes. 6375 */ 6376 6377 for_each_txq(vi, i, txq) { 6378 TXQ_LOCK(txq); 6379 txq->eq.flags |= EQ_ENABLED; 6380 TXQ_UNLOCK(txq); 6381 } 6382 6383 /* 6384 * The first iq of the first port to come up is used for tracing. 6385 */ 6386 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 6387 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 6388 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 6389 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 6390 V_QUEUENUMBER(sc->traceq)); 6391 pi->flags |= HAS_TRACEQ; 6392 } 6393 6394 /* all ok */ 6395 pi->up_vis++; 6396 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6397 if (pi->link_cfg.link_ok) 6398 t4_os_link_changed(pi); 6399 PORT_UNLOCK(pi); 6400 6401 mtx_lock(&vi->tick_mtx); 6402 if (ifp->if_get_counter == vi_get_counter) 6403 callout_reset(&vi->tick, hz, vi_tick, vi); 6404 else 6405 callout_reset(&vi->tick, hz, cxgbe_tick, vi); 6406 mtx_unlock(&vi->tick_mtx); 6407 done: 6408 if (rc != 0) 6409 cxgbe_uninit_synchronized(vi); 6410 6411 return (rc); 6412 } 6413 6414 /* 6415 * Idempotent. 6416 */ 6417 static int 6418 cxgbe_uninit_synchronized(struct vi_info *vi) 6419 { 6420 struct port_info *pi = vi->pi; 6421 struct adapter *sc = pi->adapter; 6422 struct ifnet *ifp = vi->ifp; 6423 int rc, i; 6424 struct sge_txq *txq; 6425 6426 ASSERT_SYNCHRONIZED_OP(sc); 6427 6428 if (!(vi->flags & VI_INIT_DONE)) { 6429 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 6430 KASSERT(0, ("uninited VI is running")); 6431 if_printf(ifp, "uninited VI with running ifnet. " 6432 "vi->flags 0x%016lx, if_flags 0x%08x, " 6433 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 6434 ifp->if_drv_flags); 6435 } 6436 return (0); 6437 } 6438 6439 /* 6440 * Disable the VI so that all its data in either direction is discarded 6441 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 6442 * tick) intact as the TP can deliver negative advice or data that it's 6443 * holding in its RAM (for an offloaded connection) even after the VI is 6444 * disabled. 6445 */ 6446 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 6447 if (rc) { 6448 if_printf(ifp, "disable_vi failed: %d\n", rc); 6449 return (rc); 6450 } 6451 6452 for_each_txq(vi, i, txq) { 6453 TXQ_LOCK(txq); 6454 txq->eq.flags &= ~EQ_ENABLED; 6455 TXQ_UNLOCK(txq); 6456 } 6457 6458 mtx_lock(&vi->tick_mtx); 6459 callout_stop(&vi->tick); 6460 mtx_unlock(&vi->tick_mtx); 6461 6462 PORT_LOCK(pi); 6463 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 6464 PORT_UNLOCK(pi); 6465 return (0); 6466 } 6467 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 6468 pi->up_vis--; 6469 if (pi->up_vis > 0) { 6470 PORT_UNLOCK(pi); 6471 return (0); 6472 } 6473 6474 pi->link_cfg.link_ok = false; 6475 pi->link_cfg.speed = 0; 6476 pi->link_cfg.link_down_rc = 255; 6477 t4_os_link_changed(pi); 6478 PORT_UNLOCK(pi); 6479 6480 return (0); 6481 } 6482 6483 /* 6484 * It is ok for this function to fail midway and return right away. t4_detach 6485 * will walk the entire sc->irq list and clean up whatever is valid. 6486 */ 6487 int 6488 t4_setup_intr_handlers(struct adapter *sc) 6489 { 6490 int rc, rid, p, q, v; 6491 char s[8]; 6492 struct irq *irq; 6493 struct port_info *pi; 6494 struct vi_info *vi; 6495 struct sge *sge = &sc->sge; 6496 struct sge_rxq *rxq; 6497 #ifdef TCP_OFFLOAD 6498 struct sge_ofld_rxq *ofld_rxq; 6499 #endif 6500 #ifdef DEV_NETMAP 6501 struct sge_nm_rxq *nm_rxq; 6502 #endif 6503 #ifdef RSS 6504 int nbuckets = rss_getnumbuckets(); 6505 #endif 6506 6507 /* 6508 * Setup interrupts. 6509 */ 6510 irq = &sc->irq[0]; 6511 rid = sc->intr_type == INTR_INTX ? 0 : 1; 6512 if (forwarding_intr_to_fwq(sc)) 6513 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 6514 6515 /* Multiple interrupts. */ 6516 if (sc->flags & IS_VF) 6517 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 6518 ("%s: too few intr.", __func__)); 6519 else 6520 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 6521 ("%s: too few intr.", __func__)); 6522 6523 /* The first one is always error intr on PFs */ 6524 if (!(sc->flags & IS_VF)) { 6525 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 6526 if (rc != 0) 6527 return (rc); 6528 irq++; 6529 rid++; 6530 } 6531 6532 /* The second one is always the firmware event queue (first on VFs) */ 6533 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 6534 if (rc != 0) 6535 return (rc); 6536 irq++; 6537 rid++; 6538 6539 for_each_port(sc, p) { 6540 pi = sc->port[p]; 6541 for_each_vi(pi, v, vi) { 6542 vi->first_intr = rid - 1; 6543 6544 if (vi->nnmrxq > 0) { 6545 int n = max(vi->nrxq, vi->nnmrxq); 6546 6547 rxq = &sge->rxq[vi->first_rxq]; 6548 #ifdef DEV_NETMAP 6549 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 6550 #endif 6551 for (q = 0; q < n; q++) { 6552 snprintf(s, sizeof(s), "%x%c%x", p, 6553 'a' + v, q); 6554 if (q < vi->nrxq) 6555 irq->rxq = rxq++; 6556 #ifdef DEV_NETMAP 6557 if (q < vi->nnmrxq) 6558 irq->nm_rxq = nm_rxq++; 6559 6560 if (irq->nm_rxq != NULL && 6561 irq->rxq == NULL) { 6562 /* Netmap rx only */ 6563 rc = t4_alloc_irq(sc, irq, rid, 6564 t4_nm_intr, irq->nm_rxq, s); 6565 } 6566 if (irq->nm_rxq != NULL && 6567 irq->rxq != NULL) { 6568 /* NIC and Netmap rx */ 6569 rc = t4_alloc_irq(sc, irq, rid, 6570 t4_vi_intr, irq, s); 6571 } 6572 #endif 6573 if (irq->rxq != NULL && 6574 irq->nm_rxq == NULL) { 6575 /* NIC rx only */ 6576 rc = t4_alloc_irq(sc, irq, rid, 6577 t4_intr, irq->rxq, s); 6578 } 6579 if (rc != 0) 6580 return (rc); 6581 #ifdef RSS 6582 if (q < vi->nrxq) { 6583 bus_bind_intr(sc->dev, irq->res, 6584 rss_getcpu(q % nbuckets)); 6585 } 6586 #endif 6587 irq++; 6588 rid++; 6589 vi->nintr++; 6590 } 6591 } else { 6592 for_each_rxq(vi, q, rxq) { 6593 snprintf(s, sizeof(s), "%x%c%x", p, 6594 'a' + v, q); 6595 rc = t4_alloc_irq(sc, irq, rid, 6596 t4_intr, rxq, s); 6597 if (rc != 0) 6598 return (rc); 6599 #ifdef RSS 6600 bus_bind_intr(sc->dev, irq->res, 6601 rss_getcpu(q % nbuckets)); 6602 #endif 6603 irq++; 6604 rid++; 6605 vi->nintr++; 6606 } 6607 } 6608 #ifdef TCP_OFFLOAD 6609 for_each_ofld_rxq(vi, q, ofld_rxq) { 6610 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 6611 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 6612 ofld_rxq, s); 6613 if (rc != 0) 6614 return (rc); 6615 irq++; 6616 rid++; 6617 vi->nintr++; 6618 } 6619 #endif 6620 } 6621 } 6622 MPASS(irq == &sc->irq[sc->intr_count]); 6623 6624 return (0); 6625 } 6626 6627 static void 6628 write_global_rss_key(struct adapter *sc) 6629 { 6630 #ifdef RSS 6631 int i; 6632 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6633 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6634 6635 CTASSERT(RSS_KEYSIZE == 40); 6636 6637 rss_getkey((void *)&raw_rss_key[0]); 6638 for (i = 0; i < nitems(rss_key); i++) { 6639 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 6640 } 6641 t4_write_rss_key(sc, &rss_key[0], -1, 1); 6642 #endif 6643 } 6644 6645 /* 6646 * Idempotent. 6647 */ 6648 static int 6649 adapter_full_init(struct adapter *sc) 6650 { 6651 int rc, i; 6652 6653 ASSERT_SYNCHRONIZED_OP(sc); 6654 6655 /* 6656 * queues that belong to the adapter (not any particular port). 6657 */ 6658 rc = t4_setup_adapter_queues(sc); 6659 if (rc != 0) 6660 return (rc); 6661 6662 for (i = 0; i < nitems(sc->tq); i++) { 6663 if (sc->tq[i] != NULL) 6664 continue; 6665 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 6666 taskqueue_thread_enqueue, &sc->tq[i]); 6667 if (sc->tq[i] == NULL) { 6668 CH_ERR(sc, "failed to allocate task queue %d\n", i); 6669 return (ENOMEM); 6670 } 6671 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 6672 device_get_nameunit(sc->dev), i); 6673 } 6674 6675 if (!(sc->flags & IS_VF)) { 6676 write_global_rss_key(sc); 6677 t4_intr_enable(sc); 6678 } 6679 return (0); 6680 } 6681 6682 int 6683 adapter_init(struct adapter *sc) 6684 { 6685 int rc; 6686 6687 ASSERT_SYNCHRONIZED_OP(sc); 6688 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 6689 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 6690 ("%s: FULL_INIT_DONE already", __func__)); 6691 6692 rc = adapter_full_init(sc); 6693 if (rc != 0) 6694 adapter_full_uninit(sc); 6695 else 6696 sc->flags |= FULL_INIT_DONE; 6697 6698 return (rc); 6699 } 6700 6701 /* 6702 * Idempotent. 6703 */ 6704 static void 6705 adapter_full_uninit(struct adapter *sc) 6706 { 6707 int i; 6708 6709 t4_teardown_adapter_queues(sc); 6710 6711 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 6712 taskqueue_free(sc->tq[i]); 6713 sc->tq[i] = NULL; 6714 } 6715 6716 sc->flags &= ~FULL_INIT_DONE; 6717 } 6718 6719 #ifdef RSS 6720 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 6721 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 6722 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 6723 RSS_HASHTYPE_RSS_UDP_IPV6) 6724 6725 /* Translates kernel hash types to hardware. */ 6726 static int 6727 hashconfig_to_hashen(int hashconfig) 6728 { 6729 int hashen = 0; 6730 6731 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 6732 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 6733 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 6734 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 6735 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 6736 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6737 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6738 } 6739 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 6740 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6741 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6742 } 6743 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 6744 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6745 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 6746 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6747 6748 return (hashen); 6749 } 6750 6751 /* Translates hardware hash types to kernel. */ 6752 static int 6753 hashen_to_hashconfig(int hashen) 6754 { 6755 int hashconfig = 0; 6756 6757 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 6758 /* 6759 * If UDP hashing was enabled it must have been enabled for 6760 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 6761 * enabling any 4-tuple hash is nonsense configuration. 6762 */ 6763 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6764 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 6765 6766 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6767 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 6768 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6769 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 6770 } 6771 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6772 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 6773 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6774 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 6775 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6776 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 6777 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6778 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 6779 6780 return (hashconfig); 6781 } 6782 #endif 6783 6784 /* 6785 * Idempotent. 6786 */ 6787 static int 6788 vi_full_init(struct vi_info *vi) 6789 { 6790 struct adapter *sc = vi->adapter; 6791 struct sge_rxq *rxq; 6792 int rc, i, j; 6793 #ifdef RSS 6794 int nbuckets = rss_getnumbuckets(); 6795 int hashconfig = rss_gethashconfig(); 6796 int extra; 6797 #endif 6798 6799 ASSERT_SYNCHRONIZED_OP(sc); 6800 6801 /* 6802 * Allocate tx/rx/fl queues for this VI. 6803 */ 6804 rc = t4_setup_vi_queues(vi); 6805 if (rc != 0) 6806 return (rc); 6807 6808 /* 6809 * Setup RSS for this VI. Save a copy of the RSS table for later use. 6810 */ 6811 if (vi->nrxq > vi->rss_size) { 6812 CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); " 6813 "some queues will never receive traffic.\n", vi->nrxq, 6814 vi->rss_size); 6815 } else if (vi->rss_size % vi->nrxq) { 6816 CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); " 6817 "expect uneven traffic distribution.\n", vi->nrxq, 6818 vi->rss_size); 6819 } 6820 #ifdef RSS 6821 if (vi->nrxq != nbuckets) { 6822 CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);" 6823 "performance will be impacted.\n", vi->nrxq, nbuckets); 6824 } 6825 #endif 6826 if (vi->rss == NULL) 6827 vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE, 6828 M_ZERO | M_WAITOK); 6829 for (i = 0; i < vi->rss_size;) { 6830 #ifdef RSS 6831 j = rss_get_indirection_to_bucket(i); 6832 j %= vi->nrxq; 6833 rxq = &sc->sge.rxq[vi->first_rxq + j]; 6834 vi->rss[i++] = rxq->iq.abs_id; 6835 #else 6836 for_each_rxq(vi, j, rxq) { 6837 vi->rss[i++] = rxq->iq.abs_id; 6838 if (i == vi->rss_size) 6839 break; 6840 } 6841 #endif 6842 } 6843 6844 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 6845 vi->rss, vi->rss_size); 6846 if (rc != 0) { 6847 CH_ERR(vi, "rss_config failed: %d\n", rc); 6848 return (rc); 6849 } 6850 6851 #ifdef RSS 6852 vi->hashen = hashconfig_to_hashen(hashconfig); 6853 6854 /* 6855 * We may have had to enable some hashes even though the global config 6856 * wants them disabled. This is a potential problem that must be 6857 * reported to the user. 6858 */ 6859 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 6860 6861 /* 6862 * If we consider only the supported hash types, then the enabled hashes 6863 * are a superset of the requested hashes. In other words, there cannot 6864 * be any supported hash that was requested but not enabled, but there 6865 * can be hashes that were not requested but had to be enabled. 6866 */ 6867 extra &= SUPPORTED_RSS_HASHTYPES; 6868 MPASS((extra & hashconfig) == 0); 6869 6870 if (extra) { 6871 CH_ALERT(vi, 6872 "global RSS config (0x%x) cannot be accommodated.\n", 6873 hashconfig); 6874 } 6875 if (extra & RSS_HASHTYPE_RSS_IPV4) 6876 CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n"); 6877 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 6878 CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n"); 6879 if (extra & RSS_HASHTYPE_RSS_IPV6) 6880 CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n"); 6881 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 6882 CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n"); 6883 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 6884 CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n"); 6885 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 6886 CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n"); 6887 #else 6888 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 6889 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 6890 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6891 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 6892 #endif 6893 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 6894 0, 0); 6895 if (rc != 0) { 6896 CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc); 6897 return (rc); 6898 } 6899 6900 return (0); 6901 } 6902 6903 int 6904 vi_init(struct vi_info *vi) 6905 { 6906 int rc; 6907 6908 ASSERT_SYNCHRONIZED_OP(vi->adapter); 6909 KASSERT((vi->flags & VI_INIT_DONE) == 0, 6910 ("%s: VI_INIT_DONE already", __func__)); 6911 6912 rc = vi_full_init(vi); 6913 if (rc != 0) 6914 vi_full_uninit(vi); 6915 else 6916 vi->flags |= VI_INIT_DONE; 6917 6918 return (rc); 6919 } 6920 6921 /* 6922 * Idempotent. 6923 */ 6924 static void 6925 vi_full_uninit(struct vi_info *vi) 6926 { 6927 6928 if (vi->flags & VI_INIT_DONE) { 6929 quiesce_vi(vi); 6930 free(vi->rss, M_CXGBE); 6931 free(vi->nm_rss, M_CXGBE); 6932 } 6933 6934 t4_teardown_vi_queues(vi); 6935 vi->flags &= ~VI_INIT_DONE; 6936 } 6937 6938 static void 6939 quiesce_txq(struct sge_txq *txq) 6940 { 6941 struct sge_eq *eq = &txq->eq; 6942 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6943 6944 MPASS(eq->flags & EQ_SW_ALLOCATED); 6945 MPASS(!(eq->flags & EQ_ENABLED)); 6946 6947 /* Wait for the mp_ring to empty. */ 6948 while (!mp_ring_is_idle(txq->r)) { 6949 mp_ring_check_drainage(txq->r, 4096); 6950 pause("rquiesce", 1); 6951 } 6952 MPASS(txq->txp.npkt == 0); 6953 6954 if (eq->flags & EQ_HW_ALLOCATED) { 6955 /* 6956 * Hardware is alive and working normally. Wait for it to 6957 * finish and then wait for the driver to catch up and reclaim 6958 * all descriptors. 6959 */ 6960 while (spg->cidx != htobe16(eq->pidx)) 6961 pause("equiesce", 1); 6962 while (eq->cidx != eq->pidx) 6963 pause("dquiesce", 1); 6964 } else { 6965 /* 6966 * Hardware is unavailable. Discard all pending tx and reclaim 6967 * descriptors directly. 6968 */ 6969 TXQ_LOCK(txq); 6970 while (eq->cidx != eq->pidx) { 6971 struct mbuf *m, *nextpkt; 6972 struct tx_sdesc *txsd; 6973 6974 txsd = &txq->sdesc[eq->cidx]; 6975 for (m = txsd->m; m != NULL; m = nextpkt) { 6976 nextpkt = m->m_nextpkt; 6977 m->m_nextpkt = NULL; 6978 m_freem(m); 6979 } 6980 IDXINCR(eq->cidx, txsd->desc_used, eq->sidx); 6981 } 6982 spg->pidx = spg->cidx = htobe16(eq->cidx); 6983 TXQ_UNLOCK(txq); 6984 } 6985 } 6986 6987 static void 6988 quiesce_wrq(struct sge_wrq *wrq) 6989 { 6990 6991 /* XXXTX */ 6992 } 6993 6994 static void 6995 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 6996 { 6997 /* Synchronize with the interrupt handler */ 6998 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 6999 pause("iqfree", 1); 7000 7001 if (fl != NULL) { 7002 MPASS(iq->flags & IQ_HAS_FL); 7003 7004 mtx_lock(&sc->sfl_lock); 7005 FL_LOCK(fl); 7006 fl->flags |= FL_DOOMED; 7007 FL_UNLOCK(fl); 7008 callout_stop(&sc->sfl_callout); 7009 mtx_unlock(&sc->sfl_lock); 7010 7011 KASSERT((fl->flags & FL_STARVING) == 0, 7012 ("%s: still starving", __func__)); 7013 7014 /* Release all buffers if hardware is no longer available. */ 7015 if (!(iq->flags & IQ_HW_ALLOCATED)) 7016 free_fl_buffers(sc, fl); 7017 } 7018 } 7019 7020 /* 7021 * Wait for all activity on all the queues of the VI to complete. It is assumed 7022 * that no new work is being enqueued by the hardware or the driver. That part 7023 * should be arranged before calling this function. 7024 */ 7025 static void 7026 quiesce_vi(struct vi_info *vi) 7027 { 7028 int i; 7029 struct adapter *sc = vi->adapter; 7030 struct sge_rxq *rxq; 7031 struct sge_txq *txq; 7032 #ifdef TCP_OFFLOAD 7033 struct sge_ofld_rxq *ofld_rxq; 7034 #endif 7035 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7036 struct sge_ofld_txq *ofld_txq; 7037 #endif 7038 7039 if (!(vi->flags & VI_INIT_DONE)) 7040 return; 7041 7042 for_each_txq(vi, i, txq) { 7043 quiesce_txq(txq); 7044 } 7045 7046 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7047 for_each_ofld_txq(vi, i, ofld_txq) { 7048 quiesce_wrq(&ofld_txq->wrq); 7049 } 7050 #endif 7051 7052 for_each_rxq(vi, i, rxq) { 7053 quiesce_iq_fl(sc, &rxq->iq, &rxq->fl); 7054 } 7055 7056 #ifdef TCP_OFFLOAD 7057 for_each_ofld_rxq(vi, i, ofld_rxq) { 7058 quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl); 7059 } 7060 #endif 7061 } 7062 7063 static int 7064 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 7065 driver_intr_t *handler, void *arg, char *name) 7066 { 7067 int rc; 7068 7069 irq->rid = rid; 7070 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 7071 RF_SHAREABLE | RF_ACTIVE); 7072 if (irq->res == NULL) { 7073 device_printf(sc->dev, 7074 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 7075 return (ENOMEM); 7076 } 7077 7078 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 7079 NULL, handler, arg, &irq->tag); 7080 if (rc != 0) { 7081 device_printf(sc->dev, 7082 "failed to setup interrupt for rid %d, name %s: %d\n", 7083 rid, name, rc); 7084 } else if (name) 7085 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 7086 7087 return (rc); 7088 } 7089 7090 static int 7091 t4_free_irq(struct adapter *sc, struct irq *irq) 7092 { 7093 if (irq->tag) 7094 bus_teardown_intr(sc->dev, irq->res, irq->tag); 7095 if (irq->res) 7096 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 7097 7098 bzero(irq, sizeof(*irq)); 7099 7100 return (0); 7101 } 7102 7103 static void 7104 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 7105 { 7106 7107 regs->version = chip_id(sc) | chip_rev(sc) << 10; 7108 t4_get_regs(sc, buf, regs->len); 7109 } 7110 7111 #define A_PL_INDIR_CMD 0x1f8 7112 7113 #define S_PL_AUTOINC 31 7114 #define M_PL_AUTOINC 0x1U 7115 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 7116 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 7117 7118 #define S_PL_VFID 20 7119 #define M_PL_VFID 0xffU 7120 #define V_PL_VFID(x) ((x) << S_PL_VFID) 7121 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 7122 7123 #define S_PL_ADDR 0 7124 #define M_PL_ADDR 0xfffffU 7125 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 7126 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 7127 7128 #define A_PL_INDIR_DATA 0x1fc 7129 7130 static uint64_t 7131 read_vf_stat(struct adapter *sc, u_int vin, int reg) 7132 { 7133 u32 stats[2]; 7134 7135 if (sc->flags & IS_VF) { 7136 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 7137 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 7138 } else { 7139 mtx_assert(&sc->reg_lock, MA_OWNED); 7140 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 7141 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 7142 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 7143 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 7144 } 7145 return (((uint64_t)stats[1]) << 32 | stats[0]); 7146 } 7147 7148 static void 7149 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 7150 { 7151 7152 #define GET_STAT(name) \ 7153 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 7154 7155 if (!(sc->flags & IS_VF)) 7156 mtx_lock(&sc->reg_lock); 7157 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 7158 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 7159 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 7160 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 7161 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 7162 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 7163 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 7164 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 7165 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 7166 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 7167 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 7168 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 7169 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 7170 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 7171 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 7172 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 7173 if (!(sc->flags & IS_VF)) 7174 mtx_unlock(&sc->reg_lock); 7175 7176 #undef GET_STAT 7177 } 7178 7179 static void 7180 t4_clr_vi_stats(struct adapter *sc, u_int vin) 7181 { 7182 int reg; 7183 7184 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 7185 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 7186 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 7187 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 7188 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 7189 } 7190 7191 static void 7192 vi_refresh_stats(struct vi_info *vi) 7193 { 7194 struct timeval tv; 7195 const struct timeval interval = {0, 250000}; /* 250ms */ 7196 7197 mtx_assert(&vi->tick_mtx, MA_OWNED); 7198 7199 if (vi->flags & VI_SKIP_STATS) 7200 return; 7201 7202 getmicrotime(&tv); 7203 timevalsub(&tv, &interval); 7204 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7205 return; 7206 7207 t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats); 7208 getmicrotime(&vi->last_refreshed); 7209 } 7210 7211 static void 7212 cxgbe_refresh_stats(struct vi_info *vi) 7213 { 7214 u_int i, v, tnl_cong_drops, chan_map; 7215 struct timeval tv; 7216 const struct timeval interval = {0, 250000}; /* 250ms */ 7217 struct port_info *pi; 7218 struct adapter *sc; 7219 7220 mtx_assert(&vi->tick_mtx, MA_OWNED); 7221 7222 if (vi->flags & VI_SKIP_STATS) 7223 return; 7224 7225 getmicrotime(&tv); 7226 timevalsub(&tv, &interval); 7227 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7228 return; 7229 7230 pi = vi->pi; 7231 sc = vi->adapter; 7232 tnl_cong_drops = 0; 7233 t4_get_port_stats(sc, pi->port_id, &pi->stats); 7234 chan_map = pi->rx_e_chan_map; 7235 while (chan_map) { 7236 i = ffs(chan_map) - 1; 7237 mtx_lock(&sc->reg_lock); 7238 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 7239 A_TP_MIB_TNL_CNG_DROP_0 + i); 7240 mtx_unlock(&sc->reg_lock); 7241 tnl_cong_drops += v; 7242 chan_map &= ~(1 << i); 7243 } 7244 pi->tnl_cong_drops = tnl_cong_drops; 7245 getmicrotime(&vi->last_refreshed); 7246 } 7247 7248 static void 7249 cxgbe_tick(void *arg) 7250 { 7251 struct vi_info *vi = arg; 7252 7253 MPASS(IS_MAIN_VI(vi)); 7254 mtx_assert(&vi->tick_mtx, MA_OWNED); 7255 7256 cxgbe_refresh_stats(vi); 7257 callout_schedule(&vi->tick, hz); 7258 } 7259 7260 static void 7261 vi_tick(void *arg) 7262 { 7263 struct vi_info *vi = arg; 7264 7265 mtx_assert(&vi->tick_mtx, MA_OWNED); 7266 7267 vi_refresh_stats(vi); 7268 callout_schedule(&vi->tick, hz); 7269 } 7270 7271 /* 7272 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 7273 */ 7274 static char *caps_decoder[] = { 7275 "\20\001IPMI\002NCSI", /* 0: NBM */ 7276 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 7277 "\20\001INGRESS\002EGRESS", /* 2: switch */ 7278 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 7279 "\006HASHFILTER\007ETHOFLD", 7280 "\20\001TOE", /* 4: TOE */ 7281 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 7282 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 7283 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 7284 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 7285 "\007T10DIF" 7286 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 7287 "\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE" /* 7: Crypto */ 7288 "\004TLS_HW", 7289 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 7290 "\004PO_INITIATOR\005PO_TARGET", 7291 }; 7292 7293 void 7294 t4_sysctls(struct adapter *sc) 7295 { 7296 struct sysctl_ctx_list *ctx = &sc->ctx; 7297 struct sysctl_oid *oid; 7298 struct sysctl_oid_list *children, *c0; 7299 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 7300 7301 /* 7302 * dev.t4nex.X. 7303 */ 7304 oid = device_get_sysctl_tree(sc->dev); 7305 c0 = children = SYSCTL_CHILDREN(oid); 7306 7307 sc->sc_do_rxcopy = 1; 7308 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 7309 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 7310 7311 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 7312 sc->params.nports, "# of ports"); 7313 7314 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 7315 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells, 7316 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A", 7317 "available doorbells"); 7318 7319 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 7320 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 7321 7322 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 7323 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7324 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val), 7325 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 7326 7327 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 7328 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7329 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val), 7330 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 7331 7332 t4_sge_sysctls(sc, ctx, children); 7333 7334 sc->lro_timeout = 100; 7335 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 7336 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 7337 7338 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 7339 &sc->debug_flags, 0, "flags to enable runtime debugging"); 7340 7341 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 7342 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 7343 7344 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 7345 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 7346 7347 if (sc->flags & IS_VF) 7348 return; 7349 7350 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 7351 NULL, chip_rev(sc), "chip hardware revision"); 7352 7353 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 7354 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 7355 7356 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 7357 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 7358 7359 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 7360 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 7361 7362 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 7363 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 7364 7365 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 7366 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 7367 7368 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 7369 sc->er_version, 0, "expansion ROM version"); 7370 7371 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 7372 sc->bs_version, 0, "bootstrap firmware version"); 7373 7374 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 7375 NULL, sc->params.scfg_vers, "serial config version"); 7376 7377 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 7378 NULL, sc->params.vpd_vers, "VPD version"); 7379 7380 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 7381 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 7382 7383 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 7384 sc->cfcsum, "config file checksum"); 7385 7386 #define SYSCTL_CAP(name, n, text) \ 7387 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 7388 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \ 7389 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \ 7390 "available " text " capabilities") 7391 7392 SYSCTL_CAP(nbmcaps, 0, "NBM"); 7393 SYSCTL_CAP(linkcaps, 1, "link"); 7394 SYSCTL_CAP(switchcaps, 2, "switch"); 7395 SYSCTL_CAP(niccaps, 3, "NIC"); 7396 SYSCTL_CAP(toecaps, 4, "TCP offload"); 7397 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 7398 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 7399 SYSCTL_CAP(cryptocaps, 7, "crypto"); 7400 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 7401 #undef SYSCTL_CAP 7402 7403 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 7404 NULL, sc->tids.nftids, "number of filters"); 7405 7406 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7407 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7408 sysctl_temperature, "I", "chip temperature (in Celsius)"); 7409 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", 7410 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7411 sysctl_reset_sensor, "I", "reset the chip's temperature sensor."); 7412 7413 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", 7414 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7415 sysctl_loadavg, "A", 7416 "microprocessor load averages (debug firmwares only)"); 7417 7418 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", 7419 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd, 7420 "I", "core Vdd (in mV)"); 7421 7422 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 7423 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS, 7424 sysctl_cpus, "A", "local CPUs"); 7425 7426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 7427 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS, 7428 sysctl_cpus, "A", "preferred CPUs for interrupts"); 7429 7430 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 7431 &sc->swintr, 0, "software triggered interrupts"); 7432 7433 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset", 7434 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I", 7435 "1 = reset adapter, 0 = zero reset counter"); 7436 7437 /* 7438 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 7439 */ 7440 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 7441 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL, 7442 "logs and miscellaneous information"); 7443 children = SYSCTL_CHILDREN(oid); 7444 7445 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 7446 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7447 sysctl_cctrl, "A", "congestion control"); 7448 7449 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 7450 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7451 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 7452 7453 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 7454 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7455 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 7456 7457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 7458 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7459 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 7460 7461 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 7462 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3, 7463 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 7464 7465 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 7466 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4, 7467 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 7468 7469 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 7470 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5, 7471 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 7472 7473 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 7474 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7475 sysctl_cim_la, "A", "CIM logic analyzer"); 7476 7477 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 7478 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7479 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 7480 7481 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 7482 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7483 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 7484 7485 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 7486 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7487 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 7488 7489 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 7490 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7491 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 7492 7493 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 7494 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7495 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 7496 7497 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 7498 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7499 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 7500 7501 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 7502 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7503 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 7504 7505 if (chip_id(sc) > CHELSIO_T4) { 7506 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 7507 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7508 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7509 "CIM OBQ 6 (SGE0-RX)"); 7510 7511 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 7512 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7513 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7514 "CIM OBQ 7 (SGE1-RX)"); 7515 } 7516 7517 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 7518 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7519 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 7520 7521 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 7522 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7523 sysctl_cim_qcfg, "A", "CIM queue configuration"); 7524 7525 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 7526 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7527 sysctl_cpl_stats, "A", "CPL statistics"); 7528 7529 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 7530 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7531 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 7532 7533 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats", 7534 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7535 sysctl_tid_stats, "A", "tid stats"); 7536 7537 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 7538 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7539 sysctl_devlog, "A", "firmware's device log"); 7540 7541 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 7542 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7543 sysctl_fcoe_stats, "A", "FCoE statistics"); 7544 7545 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 7546 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7547 sysctl_hw_sched, "A", "hardware scheduler "); 7548 7549 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 7550 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7551 sysctl_l2t, "A", "hardware L2 table"); 7552 7553 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 7554 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7555 sysctl_smt, "A", "hardware source MAC table"); 7556 7557 #ifdef INET6 7558 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 7559 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7560 sysctl_clip, "A", "active CLIP table entries"); 7561 #endif 7562 7563 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 7564 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7565 sysctl_lb_stats, "A", "loopback statistics"); 7566 7567 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 7568 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7569 sysctl_meminfo, "A", "memory regions"); 7570 7571 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 7572 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7573 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 7574 "A", "MPS TCAM entries"); 7575 7576 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 7577 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7578 sysctl_path_mtus, "A", "path MTUs"); 7579 7580 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 7581 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7582 sysctl_pm_stats, "A", "PM statistics"); 7583 7584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 7585 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7586 sysctl_rdma_stats, "A", "RDMA statistics"); 7587 7588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 7589 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7590 sysctl_tcp_stats, "A", "TCP statistics"); 7591 7592 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 7593 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7594 sysctl_tids, "A", "TID information"); 7595 7596 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 7597 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7598 sysctl_tp_err_stats, "A", "TP error statistics"); 7599 7600 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats", 7601 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7602 sysctl_tnl_stats, "A", "TP tunnel statistics"); 7603 7604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 7605 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7606 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask"); 7607 7608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 7609 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7610 sysctl_tp_la, "A", "TP logic analyzer"); 7611 7612 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 7613 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7614 sysctl_tx_rate, "A", "Tx rate"); 7615 7616 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 7617 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7618 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 7619 7620 if (chip_id(sc) >= CHELSIO_T5) { 7621 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 7622 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7623 sysctl_wcwr_stats, "A", "write combined work requests"); 7624 } 7625 7626 #ifdef KERN_TLS 7627 if (is_ktls(sc)) { 7628 /* 7629 * dev.t4nex.0.tls. 7630 */ 7631 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", 7632 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters"); 7633 children = SYSCTL_CHILDREN(oid); 7634 7635 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys", 7636 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS " 7637 "keys in work requests (1) or attempt to store TLS keys " 7638 "in card memory."); 7639 7640 if (is_t6(sc)) 7641 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs", 7642 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to " 7643 "combine TCB field updates with TLS record work " 7644 "requests."); 7645 } 7646 #endif 7647 7648 #ifdef TCP_OFFLOAD 7649 if (is_offload(sc)) { 7650 int i; 7651 char s[4]; 7652 7653 /* 7654 * dev.t4nex.X.toe. 7655 */ 7656 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", 7657 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters"); 7658 children = SYSCTL_CHILDREN(oid); 7659 7660 sc->tt.cong_algorithm = -1; 7661 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 7662 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 7663 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 7664 "3 = highspeed)"); 7665 7666 sc->tt.sndbuf = -1; 7667 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 7668 &sc->tt.sndbuf, 0, "hardware send buffer"); 7669 7670 sc->tt.ddp = 0; 7671 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", 7672 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, ""); 7673 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW, 7674 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)"); 7675 7676 sc->tt.rx_coalesce = -1; 7677 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 7678 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 7679 7680 sc->tt.tls = 0; 7681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT | 7682 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I", 7683 "Inline TLS allowed"); 7684 7685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 7686 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7687 sysctl_tls_rx_ports, "I", 7688 "TCP ports that use inline TLS+TOE RX"); 7689 7690 sc->tt.tls_rx_timeout = t4_toe_tls_rx_timeout; 7691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_timeout", 7692 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7693 sysctl_tls_rx_timeout, "I", 7694 "Timeout in seconds to downgrade TLS sockets to plain TOE"); 7695 7696 sc->tt.tx_align = -1; 7697 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 7698 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 7699 7700 sc->tt.tx_zcopy = 0; 7701 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 7702 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 7703 "Enable zero-copy aio_write(2)"); 7704 7705 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 7706 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7707 "cop_managed_offloading", CTLFLAG_RW, 7708 &sc->tt.cop_managed_offloading, 0, 7709 "COP (Connection Offload Policy) controls all TOE offload"); 7710 7711 sc->tt.autorcvbuf_inc = 16 * 1024; 7712 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 7713 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 7714 "autorcvbuf increment"); 7715 7716 sc->tt.update_hc_on_pmtu_change = 1; 7717 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7718 "update_hc_on_pmtu_change", CTLFLAG_RW, 7719 &sc->tt.update_hc_on_pmtu_change, 0, 7720 "Update hostcache entry if the PMTU changes"); 7721 7722 sc->tt.iso = 1; 7723 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW, 7724 &sc->tt.iso, 0, "Enable iSCSI segmentation offload"); 7725 7726 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 7727 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7728 sysctl_tp_tick, "A", "TP timer tick (us)"); 7729 7730 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 7731 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7732 sysctl_tp_tick, "A", "TCP timestamp tick (us)"); 7733 7734 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 7735 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7736 sysctl_tp_tick, "A", "DACK tick (us)"); 7737 7738 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 7739 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7740 sysctl_tp_dack_timer, "IU", "DACK timer (us)"); 7741 7742 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 7743 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7744 A_TP_RXT_MIN, sysctl_tp_timer, "LU", 7745 "Minimum retransmit interval (us)"); 7746 7747 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 7748 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7749 A_TP_RXT_MAX, sysctl_tp_timer, "LU", 7750 "Maximum retransmit interval (us)"); 7751 7752 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 7753 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7754 A_TP_PERS_MIN, sysctl_tp_timer, "LU", 7755 "Persist timer min (us)"); 7756 7757 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 7758 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7759 A_TP_PERS_MAX, sysctl_tp_timer, "LU", 7760 "Persist timer max (us)"); 7761 7762 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 7763 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7764 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU", 7765 "Keepalive idle timer (us)"); 7766 7767 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 7768 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7769 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU", 7770 "Keepalive interval timer (us)"); 7771 7772 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 7773 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7774 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)"); 7775 7776 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 7777 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7778 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU", 7779 "FINWAIT2 timer (us)"); 7780 7781 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 7782 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7783 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU", 7784 "Number of SYN retransmissions before abort"); 7785 7786 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 7787 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7788 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU", 7789 "Number of retransmissions before abort"); 7790 7791 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 7792 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7793 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU", 7794 "Number of keepalive probes before abort"); 7795 7796 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 7797 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7798 "TOE retransmit backoffs"); 7799 children = SYSCTL_CHILDREN(oid); 7800 for (i = 0; i < 16; i++) { 7801 snprintf(s, sizeof(s), "%u", i); 7802 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 7803 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7804 i, sysctl_tp_backoff, "IU", 7805 "TOE retransmit backoff"); 7806 } 7807 } 7808 #endif 7809 } 7810 7811 void 7812 vi_sysctls(struct vi_info *vi) 7813 { 7814 struct sysctl_ctx_list *ctx = &vi->ctx; 7815 struct sysctl_oid *oid; 7816 struct sysctl_oid_list *children; 7817 7818 /* 7819 * dev.v?(cxgbe|cxl).X. 7820 */ 7821 oid = device_get_sysctl_tree(vi->dev); 7822 children = SYSCTL_CHILDREN(oid); 7823 7824 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 7825 vi->viid, "VI identifer"); 7826 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 7827 &vi->nrxq, 0, "# of rx queues"); 7828 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 7829 &vi->ntxq, 0, "# of tx queues"); 7830 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 7831 &vi->first_rxq, 0, "index of first rx queue"); 7832 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 7833 &vi->first_txq, 0, "index of first tx queue"); 7834 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 7835 vi->rss_base, "start of RSS indirection table"); 7836 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 7837 vi->rss_size, "size of RSS indirection table"); 7838 7839 if (IS_MAIN_VI(vi)) { 7840 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 7841 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7842 sysctl_noflowq, "IU", 7843 "Reserve queue 0 for non-flowid packets"); 7844 } 7845 7846 if (vi->adapter->flags & IS_VF) { 7847 MPASS(vi->flags & TX_USES_VM_WR); 7848 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD, 7849 NULL, 1, "use VM work requests for transmit"); 7850 } else { 7851 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr", 7852 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7853 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit"); 7854 } 7855 7856 #ifdef TCP_OFFLOAD 7857 if (vi->nofldrxq != 0) { 7858 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 7859 &vi->nofldrxq, 0, 7860 "# of rx queues for offloaded TCP connections"); 7861 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 7862 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 7863 "index of first TOE rx queue"); 7864 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 7865 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7866 sysctl_holdoff_tmr_idx_ofld, "I", 7867 "holdoff timer index for TOE queues"); 7868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 7869 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7870 sysctl_holdoff_pktc_idx_ofld, "I", 7871 "holdoff packet counter index for TOE queues"); 7872 } 7873 #endif 7874 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7875 if (vi->nofldtxq != 0) { 7876 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 7877 &vi->nofldtxq, 0, 7878 "# of tx queues for TOE/ETHOFLD"); 7879 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 7880 CTLFLAG_RD, &vi->first_ofld_txq, 0, 7881 "index of first TOE/ETHOFLD tx queue"); 7882 } 7883 #endif 7884 #ifdef DEV_NETMAP 7885 if (vi->nnmrxq != 0) { 7886 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 7887 &vi->nnmrxq, 0, "# of netmap rx queues"); 7888 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 7889 &vi->nnmtxq, 0, "# of netmap tx queues"); 7890 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 7891 CTLFLAG_RD, &vi->first_nm_rxq, 0, 7892 "index of first netmap rx queue"); 7893 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 7894 CTLFLAG_RD, &vi->first_nm_txq, 0, 7895 "index of first netmap tx queue"); 7896 } 7897 #endif 7898 7899 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 7900 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7901 sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); 7902 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 7903 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7904 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); 7905 7906 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 7907 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7908 sysctl_qsize_rxq, "I", "rx queue size"); 7909 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 7910 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7911 sysctl_qsize_txq, "I", "tx queue size"); 7912 } 7913 7914 static void 7915 cxgbe_sysctls(struct port_info *pi) 7916 { 7917 struct sysctl_ctx_list *ctx = &pi->ctx; 7918 struct sysctl_oid *oid; 7919 struct sysctl_oid_list *children, *children2; 7920 struct adapter *sc = pi->adapter; 7921 int i; 7922 char name[16]; 7923 static char *tc_flags = {"\20\1USER"}; 7924 7925 /* 7926 * dev.cxgbe.X. 7927 */ 7928 oid = device_get_sysctl_tree(pi->dev); 7929 children = SYSCTL_CHILDREN(oid); 7930 7931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", 7932 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 7933 sysctl_linkdnrc, "A", "reason why link is down"); 7934 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 7935 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7936 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 7937 sysctl_btphy, "I", "PHY temperature (in Celsius)"); 7938 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 7939 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1, 7940 sysctl_btphy, "I", "PHY firmware version"); 7941 } 7942 7943 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 7944 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7945 sysctl_pause_settings, "A", 7946 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 7947 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec", 7948 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A", 7949 "FEC in use on the link"); 7950 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec", 7951 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7952 sysctl_requested_fec, "A", 7953 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)"); 7954 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec", 7955 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A", 7956 "FEC recommended by the cable/transceiver"); 7957 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 7958 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7959 sysctl_autoneg, "I", 7960 "autonegotiation (-1 = not supported)"); 7961 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec", 7962 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7963 sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config"); 7964 7965 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD, 7966 &pi->link_cfg.requested_caps, 0, "L1 config requested by driver"); 7967 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD, 7968 &pi->link_cfg.pcaps, 0, "port capabilities"); 7969 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD, 7970 &pi->link_cfg.acaps, 0, "advertised capabilities"); 7971 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD, 7972 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities"); 7973 7974 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 7975 port_top_speed(pi), "max speed (in Gbps)"); 7976 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 7977 pi->mps_bg_map, "MPS buffer group map"); 7978 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 7979 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 7980 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_c_chan", CTLFLAG_RD, NULL, 7981 pi->rx_c_chan, "TP rx c-channel"); 7982 7983 if (sc->flags & IS_VF) 7984 return; 7985 7986 /* 7987 * dev.(cxgbe|cxl).X.tc. 7988 */ 7989 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", 7990 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7991 "Tx scheduler traffic classes (cl_rl)"); 7992 children2 = SYSCTL_CHILDREN(oid); 7993 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 7994 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 7995 "pktsize for per-flow cl-rl (0 means up to the driver )"); 7996 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 7997 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 7998 "burstsize for per-flow cl-rl (0 means up to the driver)"); 7999 for (i = 0; i < sc->params.nsched_cls; i++) { 8000 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 8001 8002 snprintf(name, sizeof(name), "%d", i); 8003 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 8004 SYSCTL_CHILDREN(oid), OID_AUTO, name, 8005 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class")); 8006 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state", 8007 CTLFLAG_RD, &tc->state, 0, "current state"); 8008 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 8009 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags, 8010 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags"); 8011 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 8012 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 8013 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 8014 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 8015 (pi->port_id << 16) | i, sysctl_tc_params, "A", 8016 "traffic class parameters"); 8017 } 8018 8019 /* 8020 * dev.cxgbe.X.stats. 8021 */ 8022 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 8023 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics"); 8024 children = SYSCTL_CHILDREN(oid); 8025 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 8026 &pi->tx_parse_error, 0, 8027 "# of tx packets with invalid length or # of segments"); 8028 8029 #define T4_REGSTAT(name, stat, desc) \ 8030 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \ 8031 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \ 8032 (is_t4(sc) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L) : \ 8033 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L)), \ 8034 sysctl_handle_t4_reg64, "QU", desc) 8035 8036 /* We get these from port_stats and they may be stale by up to 1s */ 8037 #define T4_PORTSTAT(name, desc) \ 8038 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 8039 &pi->stats.name, desc) 8040 8041 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames"); 8042 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames"); 8043 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames"); 8044 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames"); 8045 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames"); 8046 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames"); 8047 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range"); 8048 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range"); 8049 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range"); 8050 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range"); 8051 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range"); 8052 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range"); 8053 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range"); 8054 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames"); 8055 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted"); 8056 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted"); 8057 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted"); 8058 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted"); 8059 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted"); 8060 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted"); 8061 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted"); 8062 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted"); 8063 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted"); 8064 8065 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames"); 8066 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames"); 8067 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames"); 8068 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames"); 8069 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames"); 8070 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU"); 8071 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames"); 8072 if (is_t6(sc)) { 8073 T4_PORTSTAT(rx_fcs_err, 8074 "# of frames received with bad FCS since last link up"); 8075 } else { 8076 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR, 8077 "# of frames received with bad FCS"); 8078 } 8079 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error"); 8080 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors"); 8081 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received"); 8082 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range"); 8083 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range"); 8084 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range"); 8085 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range"); 8086 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range"); 8087 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range"); 8088 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range"); 8089 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received"); 8090 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received"); 8091 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received"); 8092 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received"); 8093 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received"); 8094 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received"); 8095 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received"); 8096 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received"); 8097 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received"); 8098 8099 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows"); 8100 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows"); 8101 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows"); 8102 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows"); 8103 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets"); 8104 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets"); 8105 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets"); 8106 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets"); 8107 8108 #undef T4_REGSTAT 8109 #undef T4_PORTSTAT 8110 } 8111 8112 static int 8113 sysctl_int_array(SYSCTL_HANDLER_ARGS) 8114 { 8115 int rc, *i, space = 0; 8116 struct sbuf sb; 8117 8118 sbuf_new_for_sysctl(&sb, NULL, 64, req); 8119 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 8120 if (space) 8121 sbuf_printf(&sb, " "); 8122 sbuf_printf(&sb, "%d", *i); 8123 space = 1; 8124 } 8125 rc = sbuf_finish(&sb); 8126 sbuf_delete(&sb); 8127 return (rc); 8128 } 8129 8130 static int 8131 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 8132 { 8133 int rc; 8134 struct sbuf *sb; 8135 8136 rc = sysctl_wire_old_buffer(req, 0); 8137 if (rc != 0) 8138 return(rc); 8139 8140 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8141 if (sb == NULL) 8142 return (ENOMEM); 8143 8144 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 8145 rc = sbuf_finish(sb); 8146 sbuf_delete(sb); 8147 8148 return (rc); 8149 } 8150 8151 static int 8152 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 8153 { 8154 int rc; 8155 struct sbuf *sb; 8156 8157 rc = sysctl_wire_old_buffer(req, 0); 8158 if (rc != 0) 8159 return(rc); 8160 8161 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8162 if (sb == NULL) 8163 return (ENOMEM); 8164 8165 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 8166 rc = sbuf_finish(sb); 8167 sbuf_delete(sb); 8168 8169 return (rc); 8170 } 8171 8172 static int 8173 sysctl_btphy(SYSCTL_HANDLER_ARGS) 8174 { 8175 struct port_info *pi = arg1; 8176 int op = arg2; 8177 struct adapter *sc = pi->adapter; 8178 u_int v; 8179 int rc; 8180 8181 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 8182 if (rc) 8183 return (rc); 8184 if (hw_off_limits(sc)) 8185 rc = ENXIO; 8186 else { 8187 /* XXX: magic numbers */ 8188 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, 8189 op ? 0x20 : 0xc820, &v); 8190 } 8191 end_synchronized_op(sc, 0); 8192 if (rc) 8193 return (rc); 8194 if (op == 0) 8195 v /= 256; 8196 8197 rc = sysctl_handle_int(oidp, &v, 0, req); 8198 return (rc); 8199 } 8200 8201 static int 8202 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 8203 { 8204 struct vi_info *vi = arg1; 8205 int rc, val; 8206 8207 val = vi->rsrv_noflowq; 8208 rc = sysctl_handle_int(oidp, &val, 0, req); 8209 if (rc != 0 || req->newptr == NULL) 8210 return (rc); 8211 8212 if ((val >= 1) && (vi->ntxq > 1)) 8213 vi->rsrv_noflowq = 1; 8214 else 8215 vi->rsrv_noflowq = 0; 8216 8217 return (rc); 8218 } 8219 8220 static int 8221 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS) 8222 { 8223 struct vi_info *vi = arg1; 8224 struct adapter *sc = vi->adapter; 8225 int rc, val, i; 8226 8227 MPASS(!(sc->flags & IS_VF)); 8228 8229 val = vi->flags & TX_USES_VM_WR ? 1 : 0; 8230 rc = sysctl_handle_int(oidp, &val, 0, req); 8231 if (rc != 0 || req->newptr == NULL) 8232 return (rc); 8233 8234 if (val != 0 && val != 1) 8235 return (EINVAL); 8236 8237 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8238 "t4txvm"); 8239 if (rc) 8240 return (rc); 8241 if (hw_off_limits(sc)) 8242 rc = ENXIO; 8243 else if (vi->ifp->if_drv_flags & IFF_DRV_RUNNING) { 8244 /* 8245 * We don't want parse_pkt to run with one setting (VF or PF) 8246 * and then eth_tx to see a different setting but still use 8247 * stale information calculated by parse_pkt. 8248 */ 8249 rc = EBUSY; 8250 } else { 8251 struct port_info *pi = vi->pi; 8252 struct sge_txq *txq; 8253 uint32_t ctrl0; 8254 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr; 8255 8256 if (val) { 8257 vi->flags |= TX_USES_VM_WR; 8258 vi->ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_VM_TSO; 8259 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8260 V_TXPKT_INTF(pi->tx_chan)); 8261 if (!(sc->flags & IS_VF)) 8262 npkt--; 8263 } else { 8264 vi->flags &= ~TX_USES_VM_WR; 8265 vi->ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 8266 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8267 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 8268 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 8269 } 8270 for_each_txq(vi, i, txq) { 8271 txq->cpl_ctrl0 = ctrl0; 8272 txq->txp.max_npkt = npkt; 8273 } 8274 } 8275 end_synchronized_op(sc, LOCK_HELD); 8276 return (rc); 8277 } 8278 8279 static int 8280 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 8281 { 8282 struct vi_info *vi = arg1; 8283 struct adapter *sc = vi->adapter; 8284 int idx, rc, i; 8285 struct sge_rxq *rxq; 8286 uint8_t v; 8287 8288 idx = vi->tmr_idx; 8289 8290 rc = sysctl_handle_int(oidp, &idx, 0, req); 8291 if (rc != 0 || req->newptr == NULL) 8292 return (rc); 8293 8294 if (idx < 0 || idx >= SGE_NTIMERS) 8295 return (EINVAL); 8296 8297 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8298 "t4tmr"); 8299 if (rc) 8300 return (rc); 8301 8302 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 8303 for_each_rxq(vi, i, rxq) { 8304 #ifdef atomic_store_rel_8 8305 atomic_store_rel_8(&rxq->iq.intr_params, v); 8306 #else 8307 rxq->iq.intr_params = v; 8308 #endif 8309 } 8310 vi->tmr_idx = idx; 8311 8312 end_synchronized_op(sc, LOCK_HELD); 8313 return (0); 8314 } 8315 8316 static int 8317 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 8318 { 8319 struct vi_info *vi = arg1; 8320 struct adapter *sc = vi->adapter; 8321 int idx, rc; 8322 8323 idx = vi->pktc_idx; 8324 8325 rc = sysctl_handle_int(oidp, &idx, 0, req); 8326 if (rc != 0 || req->newptr == NULL) 8327 return (rc); 8328 8329 if (idx < -1 || idx >= SGE_NCOUNTERS) 8330 return (EINVAL); 8331 8332 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8333 "t4pktc"); 8334 if (rc) 8335 return (rc); 8336 8337 if (vi->flags & VI_INIT_DONE) 8338 rc = EBUSY; /* cannot be changed once the queues are created */ 8339 else 8340 vi->pktc_idx = idx; 8341 8342 end_synchronized_op(sc, LOCK_HELD); 8343 return (rc); 8344 } 8345 8346 static int 8347 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 8348 { 8349 struct vi_info *vi = arg1; 8350 struct adapter *sc = vi->adapter; 8351 int qsize, rc; 8352 8353 qsize = vi->qsize_rxq; 8354 8355 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8356 if (rc != 0 || req->newptr == NULL) 8357 return (rc); 8358 8359 if (qsize < 128 || (qsize & 7)) 8360 return (EINVAL); 8361 8362 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8363 "t4rxqs"); 8364 if (rc) 8365 return (rc); 8366 8367 if (vi->flags & VI_INIT_DONE) 8368 rc = EBUSY; /* cannot be changed once the queues are created */ 8369 else 8370 vi->qsize_rxq = qsize; 8371 8372 end_synchronized_op(sc, LOCK_HELD); 8373 return (rc); 8374 } 8375 8376 static int 8377 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 8378 { 8379 struct vi_info *vi = arg1; 8380 struct adapter *sc = vi->adapter; 8381 int qsize, rc; 8382 8383 qsize = vi->qsize_txq; 8384 8385 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8386 if (rc != 0 || req->newptr == NULL) 8387 return (rc); 8388 8389 if (qsize < 128 || qsize > 65536) 8390 return (EINVAL); 8391 8392 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8393 "t4txqs"); 8394 if (rc) 8395 return (rc); 8396 8397 if (vi->flags & VI_INIT_DONE) 8398 rc = EBUSY; /* cannot be changed once the queues are created */ 8399 else 8400 vi->qsize_txq = qsize; 8401 8402 end_synchronized_op(sc, LOCK_HELD); 8403 return (rc); 8404 } 8405 8406 static int 8407 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 8408 { 8409 struct port_info *pi = arg1; 8410 struct adapter *sc = pi->adapter; 8411 struct link_config *lc = &pi->link_cfg; 8412 int rc; 8413 8414 if (req->newptr == NULL) { 8415 struct sbuf *sb; 8416 static char *bits = "\20\1RX\2TX\3AUTO"; 8417 8418 rc = sysctl_wire_old_buffer(req, 0); 8419 if (rc != 0) 8420 return(rc); 8421 8422 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8423 if (sb == NULL) 8424 return (ENOMEM); 8425 8426 if (lc->link_ok) { 8427 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 8428 (lc->requested_fc & PAUSE_AUTONEG), bits); 8429 } else { 8430 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 8431 PAUSE_RX | PAUSE_AUTONEG), bits); 8432 } 8433 rc = sbuf_finish(sb); 8434 sbuf_delete(sb); 8435 } else { 8436 char s[2]; 8437 int n; 8438 8439 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 8440 PAUSE_AUTONEG)); 8441 s[1] = 0; 8442 8443 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8444 if (rc != 0) 8445 return(rc); 8446 8447 if (s[1] != 0) 8448 return (EINVAL); 8449 if (s[0] < '0' || s[0] > '9') 8450 return (EINVAL); /* not a number */ 8451 n = s[0] - '0'; 8452 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 8453 return (EINVAL); /* some other bit is set too */ 8454 8455 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8456 "t4PAUSE"); 8457 if (rc) 8458 return (rc); 8459 if (!hw_off_limits(sc)) { 8460 PORT_LOCK(pi); 8461 lc->requested_fc = n; 8462 fixup_link_config(pi); 8463 if (pi->up_vis > 0) 8464 rc = apply_link_config(pi); 8465 set_current_media(pi); 8466 PORT_UNLOCK(pi); 8467 } 8468 end_synchronized_op(sc, 0); 8469 } 8470 8471 return (rc); 8472 } 8473 8474 static int 8475 sysctl_link_fec(SYSCTL_HANDLER_ARGS) 8476 { 8477 struct port_info *pi = arg1; 8478 struct link_config *lc = &pi->link_cfg; 8479 int rc; 8480 struct sbuf *sb; 8481 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2"; 8482 8483 rc = sysctl_wire_old_buffer(req, 0); 8484 if (rc != 0) 8485 return(rc); 8486 8487 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8488 if (sb == NULL) 8489 return (ENOMEM); 8490 if (lc->link_ok) 8491 sbuf_printf(sb, "%b", lc->fec, bits); 8492 else 8493 sbuf_printf(sb, "no link"); 8494 rc = sbuf_finish(sb); 8495 sbuf_delete(sb); 8496 8497 return (rc); 8498 } 8499 8500 static int 8501 sysctl_requested_fec(SYSCTL_HANDLER_ARGS) 8502 { 8503 struct port_info *pi = arg1; 8504 struct adapter *sc = pi->adapter; 8505 struct link_config *lc = &pi->link_cfg; 8506 int rc; 8507 int8_t old; 8508 8509 if (req->newptr == NULL) { 8510 struct sbuf *sb; 8511 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2" 8512 "\5RSVD3\6auto\7module"; 8513 8514 rc = sysctl_wire_old_buffer(req, 0); 8515 if (rc != 0) 8516 return(rc); 8517 8518 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8519 if (sb == NULL) 8520 return (ENOMEM); 8521 8522 sbuf_printf(sb, "%b", lc->requested_fec, bits); 8523 rc = sbuf_finish(sb); 8524 sbuf_delete(sb); 8525 } else { 8526 char s[8]; 8527 int n; 8528 8529 snprintf(s, sizeof(s), "%d", 8530 lc->requested_fec == FEC_AUTO ? -1 : 8531 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE)); 8532 8533 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8534 if (rc != 0) 8535 return(rc); 8536 8537 n = strtol(&s[0], NULL, 0); 8538 if (n < 0 || n & FEC_AUTO) 8539 n = FEC_AUTO; 8540 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE)) 8541 return (EINVAL);/* some other bit is set too */ 8542 8543 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8544 "t4reqf"); 8545 if (rc) 8546 return (rc); 8547 PORT_LOCK(pi); 8548 old = lc->requested_fec; 8549 if (n == FEC_AUTO) 8550 lc->requested_fec = FEC_AUTO; 8551 else if (n == 0 || n == FEC_NONE) 8552 lc->requested_fec = FEC_NONE; 8553 else { 8554 if ((lc->pcaps | 8555 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) != 8556 lc->pcaps) { 8557 rc = ENOTSUP; 8558 goto done; 8559 } 8560 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC | 8561 FEC_MODULE); 8562 } 8563 if (!hw_off_limits(sc)) { 8564 fixup_link_config(pi); 8565 if (pi->up_vis > 0) { 8566 rc = apply_link_config(pi); 8567 if (rc != 0) { 8568 lc->requested_fec = old; 8569 if (rc == FW_EPROTO) 8570 rc = ENOTSUP; 8571 } 8572 } 8573 } 8574 done: 8575 PORT_UNLOCK(pi); 8576 end_synchronized_op(sc, 0); 8577 } 8578 8579 return (rc); 8580 } 8581 8582 static int 8583 sysctl_module_fec(SYSCTL_HANDLER_ARGS) 8584 { 8585 struct port_info *pi = arg1; 8586 struct adapter *sc = pi->adapter; 8587 struct link_config *lc = &pi->link_cfg; 8588 int rc; 8589 int8_t fec; 8590 struct sbuf *sb; 8591 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3"; 8592 8593 rc = sysctl_wire_old_buffer(req, 0); 8594 if (rc != 0) 8595 return (rc); 8596 8597 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8598 if (sb == NULL) 8599 return (ENOMEM); 8600 8601 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) { 8602 rc = EBUSY; 8603 goto done; 8604 } 8605 if (hw_off_limits(sc)) { 8606 rc = ENXIO; 8607 goto done; 8608 } 8609 PORT_LOCK(pi); 8610 if (pi->up_vis == 0) { 8611 /* 8612 * If all the interfaces are administratively down the firmware 8613 * does not report transceiver changes. Refresh port info here. 8614 * This is the only reason we have a synchronized op in this 8615 * function. Just PORT_LOCK would have been enough otherwise. 8616 */ 8617 t4_update_port_info(pi); 8618 } 8619 8620 fec = lc->fec_hint; 8621 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE || 8622 !fec_supported(lc->pcaps)) { 8623 sbuf_printf(sb, "n/a"); 8624 } else { 8625 if (fec == 0) 8626 fec = FEC_NONE; 8627 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits); 8628 } 8629 rc = sbuf_finish(sb); 8630 PORT_UNLOCK(pi); 8631 done: 8632 sbuf_delete(sb); 8633 end_synchronized_op(sc, 0); 8634 8635 return (rc); 8636 } 8637 8638 static int 8639 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 8640 { 8641 struct port_info *pi = arg1; 8642 struct adapter *sc = pi->adapter; 8643 struct link_config *lc = &pi->link_cfg; 8644 int rc, val; 8645 8646 if (lc->pcaps & FW_PORT_CAP32_ANEG) 8647 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 8648 else 8649 val = -1; 8650 rc = sysctl_handle_int(oidp, &val, 0, req); 8651 if (rc != 0 || req->newptr == NULL) 8652 return (rc); 8653 if (val == 0) 8654 val = AUTONEG_DISABLE; 8655 else if (val == 1) 8656 val = AUTONEG_ENABLE; 8657 else 8658 val = AUTONEG_AUTO; 8659 8660 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8661 "t4aneg"); 8662 if (rc) 8663 return (rc); 8664 PORT_LOCK(pi); 8665 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 8666 rc = ENOTSUP; 8667 goto done; 8668 } 8669 lc->requested_aneg = val; 8670 if (!hw_off_limits(sc)) { 8671 fixup_link_config(pi); 8672 if (pi->up_vis > 0) 8673 rc = apply_link_config(pi); 8674 set_current_media(pi); 8675 } 8676 done: 8677 PORT_UNLOCK(pi); 8678 end_synchronized_op(sc, 0); 8679 return (rc); 8680 } 8681 8682 static int 8683 sysctl_force_fec(SYSCTL_HANDLER_ARGS) 8684 { 8685 struct port_info *pi = arg1; 8686 struct adapter *sc = pi->adapter; 8687 struct link_config *lc = &pi->link_cfg; 8688 int rc, val; 8689 8690 val = lc->force_fec; 8691 MPASS(val >= -1 && val <= 1); 8692 rc = sysctl_handle_int(oidp, &val, 0, req); 8693 if (rc != 0 || req->newptr == NULL) 8694 return (rc); 8695 if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC)) 8696 return (ENOTSUP); 8697 if (val < -1 || val > 1) 8698 return (EINVAL); 8699 8700 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff"); 8701 if (rc) 8702 return (rc); 8703 PORT_LOCK(pi); 8704 lc->force_fec = val; 8705 if (!hw_off_limits(sc)) { 8706 fixup_link_config(pi); 8707 if (pi->up_vis > 0) 8708 rc = apply_link_config(pi); 8709 } 8710 PORT_UNLOCK(pi); 8711 end_synchronized_op(sc, 0); 8712 return (rc); 8713 } 8714 8715 static int 8716 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 8717 { 8718 struct adapter *sc = arg1; 8719 int rc, reg = arg2; 8720 uint64_t val; 8721 8722 mtx_lock(&sc->reg_lock); 8723 if (hw_off_limits(sc)) 8724 rc = ENXIO; 8725 else { 8726 rc = 0; 8727 val = t4_read_reg64(sc, reg); 8728 } 8729 mtx_unlock(&sc->reg_lock); 8730 if (rc == 0) 8731 rc = sysctl_handle_64(oidp, &val, 0, req); 8732 return (rc); 8733 } 8734 8735 static int 8736 sysctl_temperature(SYSCTL_HANDLER_ARGS) 8737 { 8738 struct adapter *sc = arg1; 8739 int rc, t; 8740 uint32_t param, val; 8741 8742 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 8743 if (rc) 8744 return (rc); 8745 if (hw_off_limits(sc)) 8746 rc = ENXIO; 8747 else { 8748 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8749 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8750 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 8751 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8752 } 8753 end_synchronized_op(sc, 0); 8754 if (rc) 8755 return (rc); 8756 8757 /* unknown is returned as 0 but we display -1 in that case */ 8758 t = val == 0 ? -1 : val; 8759 8760 rc = sysctl_handle_int(oidp, &t, 0, req); 8761 return (rc); 8762 } 8763 8764 static int 8765 sysctl_vdd(SYSCTL_HANDLER_ARGS) 8766 { 8767 struct adapter *sc = arg1; 8768 int rc; 8769 uint32_t param, val; 8770 8771 if (sc->params.core_vdd == 0) { 8772 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8773 "t4vdd"); 8774 if (rc) 8775 return (rc); 8776 if (hw_off_limits(sc)) 8777 rc = ENXIO; 8778 else { 8779 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8780 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8781 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 8782 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, 8783 ¶m, &val); 8784 } 8785 end_synchronized_op(sc, 0); 8786 if (rc) 8787 return (rc); 8788 sc->params.core_vdd = val; 8789 } 8790 8791 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req)); 8792 } 8793 8794 static int 8795 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS) 8796 { 8797 struct adapter *sc = arg1; 8798 int rc, v; 8799 uint32_t param, val; 8800 8801 v = sc->sensor_resets; 8802 rc = sysctl_handle_int(oidp, &v, 0, req); 8803 if (rc != 0 || req->newptr == NULL || v <= 0) 8804 return (rc); 8805 8806 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) || 8807 chip_id(sc) < CHELSIO_T5) 8808 return (ENOTSUP); 8809 8810 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst"); 8811 if (rc) 8812 return (rc); 8813 if (hw_off_limits(sc)) 8814 rc = ENXIO; 8815 else { 8816 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8817 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8818 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR)); 8819 val = 1; 8820 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8821 } 8822 end_synchronized_op(sc, 0); 8823 if (rc == 0) 8824 sc->sensor_resets++; 8825 return (rc); 8826 } 8827 8828 static int 8829 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 8830 { 8831 struct adapter *sc = arg1; 8832 struct sbuf *sb; 8833 int rc; 8834 uint32_t param, val; 8835 8836 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 8837 if (rc) 8838 return (rc); 8839 if (hw_off_limits(sc)) 8840 rc = ENXIO; 8841 else { 8842 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8843 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 8844 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8845 } 8846 end_synchronized_op(sc, 0); 8847 if (rc) 8848 return (rc); 8849 8850 rc = sysctl_wire_old_buffer(req, 0); 8851 if (rc != 0) 8852 return (rc); 8853 8854 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8855 if (sb == NULL) 8856 return (ENOMEM); 8857 8858 if (val == 0xffffffff) { 8859 /* Only debug and custom firmwares report load averages. */ 8860 sbuf_printf(sb, "not available"); 8861 } else { 8862 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 8863 (val >> 16) & 0xff); 8864 } 8865 rc = sbuf_finish(sb); 8866 sbuf_delete(sb); 8867 8868 return (rc); 8869 } 8870 8871 static int 8872 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 8873 { 8874 struct adapter *sc = arg1; 8875 struct sbuf *sb; 8876 int rc, i; 8877 uint16_t incr[NMTUS][NCCTRL_WIN]; 8878 static const char *dec_fac[] = { 8879 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 8880 "0.9375" 8881 }; 8882 8883 rc = sysctl_wire_old_buffer(req, 0); 8884 if (rc != 0) 8885 return (rc); 8886 8887 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8888 if (sb == NULL) 8889 return (ENOMEM); 8890 8891 mtx_lock(&sc->reg_lock); 8892 if (hw_off_limits(sc)) 8893 rc = ENXIO; 8894 else 8895 t4_read_cong_tbl(sc, incr); 8896 mtx_unlock(&sc->reg_lock); 8897 if (rc) 8898 goto done; 8899 8900 for (i = 0; i < NCCTRL_WIN; ++i) { 8901 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 8902 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 8903 incr[5][i], incr[6][i], incr[7][i]); 8904 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 8905 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 8906 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 8907 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 8908 } 8909 8910 rc = sbuf_finish(sb); 8911 done: 8912 sbuf_delete(sb); 8913 return (rc); 8914 } 8915 8916 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 8917 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 8918 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 8919 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 8920 }; 8921 8922 static int 8923 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 8924 { 8925 struct adapter *sc = arg1; 8926 struct sbuf *sb; 8927 int rc, i, n, qid = arg2; 8928 uint32_t *buf, *p; 8929 char *qtype; 8930 u_int cim_num_obq = sc->chip_params->cim_num_obq; 8931 8932 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 8933 ("%s: bad qid %d\n", __func__, qid)); 8934 8935 if (qid < CIM_NUM_IBQ) { 8936 /* inbound queue */ 8937 qtype = "IBQ"; 8938 n = 4 * CIM_IBQ_SIZE; 8939 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 8940 mtx_lock(&sc->reg_lock); 8941 if (hw_off_limits(sc)) 8942 rc = -ENXIO; 8943 else 8944 rc = t4_read_cim_ibq(sc, qid, buf, n); 8945 mtx_unlock(&sc->reg_lock); 8946 } else { 8947 /* outbound queue */ 8948 qtype = "OBQ"; 8949 qid -= CIM_NUM_IBQ; 8950 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 8951 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 8952 mtx_lock(&sc->reg_lock); 8953 if (hw_off_limits(sc)) 8954 rc = -ENXIO; 8955 else 8956 rc = t4_read_cim_obq(sc, qid, buf, n); 8957 mtx_unlock(&sc->reg_lock); 8958 } 8959 8960 if (rc < 0) { 8961 rc = -rc; 8962 goto done; 8963 } 8964 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 8965 8966 rc = sysctl_wire_old_buffer(req, 0); 8967 if (rc != 0) 8968 goto done; 8969 8970 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 8971 if (sb == NULL) { 8972 rc = ENOMEM; 8973 goto done; 8974 } 8975 8976 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 8977 for (i = 0, p = buf; i < n; i += 16, p += 4) 8978 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 8979 p[2], p[3]); 8980 8981 rc = sbuf_finish(sb); 8982 sbuf_delete(sb); 8983 done: 8984 free(buf, M_CXGBE); 8985 return (rc); 8986 } 8987 8988 static void 8989 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 8990 { 8991 uint32_t *p; 8992 8993 sbuf_printf(sb, "Status Data PC%s", 8994 cfg & F_UPDBGLACAPTPCONLY ? "" : 8995 " LS0Stat LS0Addr LS0Data"); 8996 8997 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 8998 if (cfg & F_UPDBGLACAPTPCONLY) { 8999 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 9000 p[6], p[7]); 9001 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 9002 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 9003 p[4] & 0xff, p[5] >> 8); 9004 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 9005 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9006 p[1] & 0xf, p[2] >> 4); 9007 } else { 9008 sbuf_printf(sb, 9009 "\n %02x %x%07x %x%07x %08x %08x " 9010 "%08x%08x%08x%08x", 9011 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9012 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 9013 p[6], p[7]); 9014 } 9015 } 9016 } 9017 9018 static void 9019 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9020 { 9021 uint32_t *p; 9022 9023 sbuf_printf(sb, "Status Inst Data PC%s", 9024 cfg & F_UPDBGLACAPTPCONLY ? "" : 9025 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 9026 9027 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 9028 if (cfg & F_UPDBGLACAPTPCONLY) { 9029 sbuf_printf(sb, "\n %02x %08x %08x %08x", 9030 p[3] & 0xff, p[2], p[1], p[0]); 9031 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 9032 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 9033 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 9034 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 9035 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 9036 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 9037 p[6] >> 16); 9038 } else { 9039 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 9040 "%08x %08x %08x %08x %08x %08x", 9041 (p[9] >> 16) & 0xff, 9042 p[9] & 0xffff, p[8] >> 16, 9043 p[8] & 0xffff, p[7] >> 16, 9044 p[7] & 0xffff, p[6] >> 16, 9045 p[2], p[1], p[0], p[5], p[4], p[3]); 9046 } 9047 } 9048 } 9049 9050 static int 9051 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 9052 { 9053 uint32_t cfg, *buf; 9054 int rc; 9055 9056 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9057 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 9058 M_ZERO | flags); 9059 if (buf == NULL) 9060 return (ENOMEM); 9061 9062 mtx_lock(&sc->reg_lock); 9063 if (hw_off_limits(sc)) 9064 rc = ENXIO; 9065 else { 9066 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9067 if (rc == 0) 9068 rc = -t4_cim_read_la(sc, buf, NULL); 9069 } 9070 mtx_unlock(&sc->reg_lock); 9071 if (rc == 0) { 9072 if (chip_id(sc) < CHELSIO_T6) 9073 sbuf_cim_la4(sc, sb, buf, cfg); 9074 else 9075 sbuf_cim_la6(sc, sb, buf, cfg); 9076 } 9077 free(buf, M_CXGBE); 9078 return (rc); 9079 } 9080 9081 static int 9082 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 9083 { 9084 struct adapter *sc = arg1; 9085 struct sbuf *sb; 9086 int rc; 9087 9088 rc = sysctl_wire_old_buffer(req, 0); 9089 if (rc != 0) 9090 return (rc); 9091 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9092 if (sb == NULL) 9093 return (ENOMEM); 9094 9095 rc = sbuf_cim_la(sc, sb, M_WAITOK); 9096 if (rc == 0) 9097 rc = sbuf_finish(sb); 9098 sbuf_delete(sb); 9099 return (rc); 9100 } 9101 9102 static void 9103 dump_cim_regs(struct adapter *sc) 9104 { 9105 log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n", 9106 device_get_nameunit(sc->dev), 9107 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9108 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9109 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2), 9110 t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN), 9111 t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA)); 9112 log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n", 9113 device_get_nameunit(sc->dev), 9114 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9115 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9116 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800), 9117 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800), 9118 t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN)); 9119 } 9120 9121 static void 9122 dump_cimla(struct adapter *sc) 9123 { 9124 struct sbuf sb; 9125 int rc; 9126 9127 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9128 log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n", 9129 device_get_nameunit(sc->dev)); 9130 return; 9131 } 9132 rc = sbuf_cim_la(sc, &sb, M_WAITOK); 9133 if (rc == 0) { 9134 rc = sbuf_finish(&sb); 9135 if (rc == 0) { 9136 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n", 9137 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9138 } 9139 } 9140 sbuf_delete(&sb); 9141 } 9142 9143 void 9144 t4_os_cim_err(struct adapter *sc) 9145 { 9146 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 9147 } 9148 9149 static int 9150 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 9151 { 9152 struct adapter *sc = arg1; 9153 u_int i; 9154 struct sbuf *sb; 9155 uint32_t *buf, *p; 9156 int rc; 9157 9158 rc = sysctl_wire_old_buffer(req, 0); 9159 if (rc != 0) 9160 return (rc); 9161 9162 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9163 if (sb == NULL) 9164 return (ENOMEM); 9165 9166 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 9167 M_ZERO | M_WAITOK); 9168 9169 mtx_lock(&sc->reg_lock); 9170 if (hw_off_limits(sc)) 9171 rc = ENXIO; 9172 else 9173 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 9174 mtx_unlock(&sc->reg_lock); 9175 if (rc) 9176 goto done; 9177 9178 p = buf; 9179 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9180 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 9181 p[1], p[0]); 9182 } 9183 9184 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 9185 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9186 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 9187 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 9188 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 9189 (p[1] >> 2) | ((p[2] & 3) << 30), 9190 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 9191 p[0] & 1); 9192 } 9193 rc = sbuf_finish(sb); 9194 done: 9195 sbuf_delete(sb); 9196 free(buf, M_CXGBE); 9197 return (rc); 9198 } 9199 9200 static int 9201 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 9202 { 9203 struct adapter *sc = arg1; 9204 u_int i; 9205 struct sbuf *sb; 9206 uint32_t *buf, *p; 9207 int rc; 9208 9209 rc = sysctl_wire_old_buffer(req, 0); 9210 if (rc != 0) 9211 return (rc); 9212 9213 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9214 if (sb == NULL) 9215 return (ENOMEM); 9216 9217 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 9218 M_ZERO | M_WAITOK); 9219 9220 mtx_lock(&sc->reg_lock); 9221 if (hw_off_limits(sc)) 9222 rc = ENXIO; 9223 else 9224 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 9225 mtx_unlock(&sc->reg_lock); 9226 if (rc) 9227 goto done; 9228 9229 p = buf; 9230 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 9231 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9232 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 9233 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 9234 p[4], p[3], p[2], p[1], p[0]); 9235 } 9236 9237 sbuf_printf(sb, "\n\nCntl ID Data"); 9238 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9239 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 9240 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 9241 } 9242 9243 rc = sbuf_finish(sb); 9244 done: 9245 sbuf_delete(sb); 9246 free(buf, M_CXGBE); 9247 return (rc); 9248 } 9249 9250 static int 9251 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 9252 { 9253 struct adapter *sc = arg1; 9254 struct sbuf *sb; 9255 int rc, i; 9256 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9257 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9258 uint16_t thres[CIM_NUM_IBQ]; 9259 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 9260 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 9261 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 9262 9263 cim_num_obq = sc->chip_params->cim_num_obq; 9264 if (is_t4(sc)) { 9265 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 9266 obq_rdaddr = A_UP_OBQ_0_REALADDR; 9267 } else { 9268 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 9269 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 9270 } 9271 nq = CIM_NUM_IBQ + cim_num_obq; 9272 9273 mtx_lock(&sc->reg_lock); 9274 if (hw_off_limits(sc)) 9275 rc = ENXIO; 9276 else { 9277 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 9278 if (rc == 0) { 9279 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, 9280 obq_wr); 9281 if (rc == 0) 9282 t4_read_cimq_cfg(sc, base, size, thres); 9283 } 9284 } 9285 mtx_unlock(&sc->reg_lock); 9286 if (rc) 9287 return (rc); 9288 9289 rc = sysctl_wire_old_buffer(req, 0); 9290 if (rc != 0) 9291 return (rc); 9292 9293 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9294 if (sb == NULL) 9295 return (ENOMEM); 9296 9297 sbuf_printf(sb, 9298 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 9299 9300 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 9301 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 9302 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 9303 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9304 G_QUEREMFLITS(p[2]) * 16); 9305 for ( ; i < nq; i++, p += 4, wr += 2) 9306 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 9307 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 9308 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9309 G_QUEREMFLITS(p[2]) * 16); 9310 9311 rc = sbuf_finish(sb); 9312 sbuf_delete(sb); 9313 9314 return (rc); 9315 } 9316 9317 static int 9318 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 9319 { 9320 struct adapter *sc = arg1; 9321 struct sbuf *sb; 9322 int rc; 9323 struct tp_cpl_stats stats; 9324 9325 rc = sysctl_wire_old_buffer(req, 0); 9326 if (rc != 0) 9327 return (rc); 9328 9329 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9330 if (sb == NULL) 9331 return (ENOMEM); 9332 9333 mtx_lock(&sc->reg_lock); 9334 if (hw_off_limits(sc)) 9335 rc = ENXIO; 9336 else 9337 t4_tp_get_cpl_stats(sc, &stats, 0); 9338 mtx_unlock(&sc->reg_lock); 9339 if (rc) 9340 goto done; 9341 9342 if (sc->chip_params->nchan > 2) { 9343 sbuf_printf(sb, " channel 0 channel 1" 9344 " channel 2 channel 3"); 9345 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 9346 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 9347 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 9348 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 9349 } else { 9350 sbuf_printf(sb, " channel 0 channel 1"); 9351 sbuf_printf(sb, "\nCPL requests: %10u %10u", 9352 stats.req[0], stats.req[1]); 9353 sbuf_printf(sb, "\nCPL responses: %10u %10u", 9354 stats.rsp[0], stats.rsp[1]); 9355 } 9356 9357 rc = sbuf_finish(sb); 9358 done: 9359 sbuf_delete(sb); 9360 return (rc); 9361 } 9362 9363 static int 9364 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 9365 { 9366 struct adapter *sc = arg1; 9367 struct sbuf *sb; 9368 int rc; 9369 struct tp_usm_stats stats; 9370 9371 rc = sysctl_wire_old_buffer(req, 0); 9372 if (rc != 0) 9373 return(rc); 9374 9375 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9376 if (sb == NULL) 9377 return (ENOMEM); 9378 9379 mtx_lock(&sc->reg_lock); 9380 if (hw_off_limits(sc)) 9381 rc = ENXIO; 9382 else 9383 t4_get_usm_stats(sc, &stats, 1); 9384 mtx_unlock(&sc->reg_lock); 9385 if (rc == 0) { 9386 sbuf_printf(sb, "Frames: %u\n", stats.frames); 9387 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 9388 sbuf_printf(sb, "Drops: %u", stats.drops); 9389 rc = sbuf_finish(sb); 9390 } 9391 sbuf_delete(sb); 9392 9393 return (rc); 9394 } 9395 9396 static int 9397 sysctl_tid_stats(SYSCTL_HANDLER_ARGS) 9398 { 9399 struct adapter *sc = arg1; 9400 struct sbuf *sb; 9401 int rc; 9402 struct tp_tid_stats stats; 9403 9404 rc = sysctl_wire_old_buffer(req, 0); 9405 if (rc != 0) 9406 return(rc); 9407 9408 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9409 if (sb == NULL) 9410 return (ENOMEM); 9411 9412 mtx_lock(&sc->reg_lock); 9413 if (hw_off_limits(sc)) 9414 rc = ENXIO; 9415 else 9416 t4_tp_get_tid_stats(sc, &stats, 1); 9417 mtx_unlock(&sc->reg_lock); 9418 if (rc == 0) { 9419 sbuf_printf(sb, "Delete: %u\n", stats.del); 9420 sbuf_printf(sb, "Invalidate: %u\n", stats.inv); 9421 sbuf_printf(sb, "Active: %u\n", stats.act); 9422 sbuf_printf(sb, "Passive: %u", stats.pas); 9423 rc = sbuf_finish(sb); 9424 } 9425 sbuf_delete(sb); 9426 9427 return (rc); 9428 } 9429 9430 static const char * const devlog_level_strings[] = { 9431 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 9432 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 9433 [FW_DEVLOG_LEVEL_ERR] = "ERR", 9434 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 9435 [FW_DEVLOG_LEVEL_INFO] = "INFO", 9436 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 9437 }; 9438 9439 static const char * const devlog_facility_strings[] = { 9440 [FW_DEVLOG_FACILITY_CORE] = "CORE", 9441 [FW_DEVLOG_FACILITY_CF] = "CF", 9442 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 9443 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 9444 [FW_DEVLOG_FACILITY_RES] = "RES", 9445 [FW_DEVLOG_FACILITY_HW] = "HW", 9446 [FW_DEVLOG_FACILITY_FLR] = "FLR", 9447 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 9448 [FW_DEVLOG_FACILITY_PHY] = "PHY", 9449 [FW_DEVLOG_FACILITY_MAC] = "MAC", 9450 [FW_DEVLOG_FACILITY_PORT] = "PORT", 9451 [FW_DEVLOG_FACILITY_VI] = "VI", 9452 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 9453 [FW_DEVLOG_FACILITY_ACL] = "ACL", 9454 [FW_DEVLOG_FACILITY_TM] = "TM", 9455 [FW_DEVLOG_FACILITY_QFC] = "QFC", 9456 [FW_DEVLOG_FACILITY_DCB] = "DCB", 9457 [FW_DEVLOG_FACILITY_ETH] = "ETH", 9458 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 9459 [FW_DEVLOG_FACILITY_RI] = "RI", 9460 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 9461 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 9462 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 9463 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 9464 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 9465 }; 9466 9467 static int 9468 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 9469 { 9470 int i, j, rc, nentries, first = 0; 9471 struct devlog_params *dparams = &sc->params.devlog; 9472 struct fw_devlog_e *buf, *e; 9473 uint64_t ftstamp = UINT64_MAX; 9474 9475 if (dparams->addr == 0) 9476 return (ENXIO); 9477 9478 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9479 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 9480 if (buf == NULL) 9481 return (ENOMEM); 9482 9483 mtx_lock(&sc->reg_lock); 9484 if (hw_off_limits(sc)) 9485 rc = ENXIO; 9486 else 9487 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, 9488 dparams->size); 9489 mtx_unlock(&sc->reg_lock); 9490 if (rc != 0) 9491 goto done; 9492 9493 nentries = dparams->size / sizeof(struct fw_devlog_e); 9494 for (i = 0; i < nentries; i++) { 9495 e = &buf[i]; 9496 9497 if (e->timestamp == 0) 9498 break; /* end */ 9499 9500 e->timestamp = be64toh(e->timestamp); 9501 e->seqno = be32toh(e->seqno); 9502 for (j = 0; j < 8; j++) 9503 e->params[j] = be32toh(e->params[j]); 9504 9505 if (e->timestamp < ftstamp) { 9506 ftstamp = e->timestamp; 9507 first = i; 9508 } 9509 } 9510 9511 if (buf[first].timestamp == 0) 9512 goto done; /* nothing in the log */ 9513 9514 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 9515 "Seq#", "Tstamp", "Level", "Facility", "Message"); 9516 9517 i = first; 9518 do { 9519 e = &buf[i]; 9520 if (e->timestamp == 0) 9521 break; /* end */ 9522 9523 sbuf_printf(sb, "%10d %15ju %8s %8s ", 9524 e->seqno, e->timestamp, 9525 (e->level < nitems(devlog_level_strings) ? 9526 devlog_level_strings[e->level] : "UNKNOWN"), 9527 (e->facility < nitems(devlog_facility_strings) ? 9528 devlog_facility_strings[e->facility] : "UNKNOWN")); 9529 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 9530 e->params[2], e->params[3], e->params[4], 9531 e->params[5], e->params[6], e->params[7]); 9532 9533 if (++i == nentries) 9534 i = 0; 9535 } while (i != first); 9536 done: 9537 free(buf, M_CXGBE); 9538 return (rc); 9539 } 9540 9541 static int 9542 sysctl_devlog(SYSCTL_HANDLER_ARGS) 9543 { 9544 struct adapter *sc = arg1; 9545 int rc; 9546 struct sbuf *sb; 9547 9548 rc = sysctl_wire_old_buffer(req, 0); 9549 if (rc != 0) 9550 return (rc); 9551 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9552 if (sb == NULL) 9553 return (ENOMEM); 9554 9555 rc = sbuf_devlog(sc, sb, M_WAITOK); 9556 if (rc == 0) 9557 rc = sbuf_finish(sb); 9558 sbuf_delete(sb); 9559 return (rc); 9560 } 9561 9562 static void 9563 dump_devlog(struct adapter *sc) 9564 { 9565 int rc; 9566 struct sbuf sb; 9567 9568 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9569 log(LOG_DEBUG, "%s: failed to generate devlog dump.\n", 9570 device_get_nameunit(sc->dev)); 9571 return; 9572 } 9573 rc = sbuf_devlog(sc, &sb, M_WAITOK); 9574 if (rc == 0) { 9575 rc = sbuf_finish(&sb); 9576 if (rc == 0) { 9577 log(LOG_DEBUG, "%s: device log follows.\n%s", 9578 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9579 } 9580 } 9581 sbuf_delete(&sb); 9582 } 9583 9584 static int 9585 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 9586 { 9587 struct adapter *sc = arg1; 9588 struct sbuf *sb; 9589 int rc; 9590 struct tp_fcoe_stats stats[MAX_NCHAN]; 9591 int i, nchan = sc->chip_params->nchan; 9592 9593 rc = sysctl_wire_old_buffer(req, 0); 9594 if (rc != 0) 9595 return (rc); 9596 9597 mtx_lock(&sc->reg_lock); 9598 if (hw_off_limits(sc)) 9599 rc = ENXIO; 9600 else { 9601 for (i = 0; i < nchan; i++) 9602 t4_get_fcoe_stats(sc, i, &stats[i], 1); 9603 } 9604 mtx_unlock(&sc->reg_lock); 9605 if (rc != 0) 9606 return (rc); 9607 9608 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9609 if (sb == NULL) 9610 return (ENOMEM); 9611 9612 if (nchan > 2) { 9613 sbuf_printf(sb, " channel 0 channel 1" 9614 " channel 2 channel 3"); 9615 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 9616 stats[0].octets_ddp, stats[1].octets_ddp, 9617 stats[2].octets_ddp, stats[3].octets_ddp); 9618 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 9619 stats[0].frames_ddp, stats[1].frames_ddp, 9620 stats[2].frames_ddp, stats[3].frames_ddp); 9621 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 9622 stats[0].frames_drop, stats[1].frames_drop, 9623 stats[2].frames_drop, stats[3].frames_drop); 9624 } else { 9625 sbuf_printf(sb, " channel 0 channel 1"); 9626 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 9627 stats[0].octets_ddp, stats[1].octets_ddp); 9628 sbuf_printf(sb, "\nframesDDP: %16u %16u", 9629 stats[0].frames_ddp, stats[1].frames_ddp); 9630 sbuf_printf(sb, "\nframesDrop: %16u %16u", 9631 stats[0].frames_drop, stats[1].frames_drop); 9632 } 9633 9634 rc = sbuf_finish(sb); 9635 sbuf_delete(sb); 9636 9637 return (rc); 9638 } 9639 9640 static int 9641 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 9642 { 9643 struct adapter *sc = arg1; 9644 struct sbuf *sb; 9645 int rc, i; 9646 unsigned int map, kbps, ipg, mode; 9647 unsigned int pace_tab[NTX_SCHED]; 9648 9649 rc = sysctl_wire_old_buffer(req, 0); 9650 if (rc != 0) 9651 return (rc); 9652 9653 sb = sbuf_new_for_sysctl(NULL, NULL, 512, req); 9654 if (sb == NULL) 9655 return (ENOMEM); 9656 9657 mtx_lock(&sc->reg_lock); 9658 if (hw_off_limits(sc)) { 9659 rc = ENXIO; 9660 goto done; 9661 } 9662 9663 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 9664 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 9665 t4_read_pace_tbl(sc, pace_tab); 9666 9667 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 9668 "Class IPG (0.1 ns) Flow IPG (us)"); 9669 9670 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 9671 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 9672 sbuf_printf(sb, "\n %u %-5s %u ", i, 9673 (mode & (1 << i)) ? "flow" : "class", map & 3); 9674 if (kbps) 9675 sbuf_printf(sb, "%9u ", kbps); 9676 else 9677 sbuf_printf(sb, " disabled "); 9678 9679 if (ipg) 9680 sbuf_printf(sb, "%13u ", ipg); 9681 else 9682 sbuf_printf(sb, " disabled "); 9683 9684 if (pace_tab[i]) 9685 sbuf_printf(sb, "%10u", pace_tab[i]); 9686 else 9687 sbuf_printf(sb, " disabled"); 9688 } 9689 rc = sbuf_finish(sb); 9690 done: 9691 mtx_unlock(&sc->reg_lock); 9692 sbuf_delete(sb); 9693 return (rc); 9694 } 9695 9696 static int 9697 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 9698 { 9699 struct adapter *sc = arg1; 9700 struct sbuf *sb; 9701 int rc, i, j; 9702 uint64_t *p0, *p1; 9703 struct lb_port_stats s[2]; 9704 static const char *stat_name[] = { 9705 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 9706 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 9707 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 9708 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 9709 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 9710 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 9711 "BG2FramesTrunc:", "BG3FramesTrunc:" 9712 }; 9713 9714 rc = sysctl_wire_old_buffer(req, 0); 9715 if (rc != 0) 9716 return (rc); 9717 9718 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9719 if (sb == NULL) 9720 return (ENOMEM); 9721 9722 memset(s, 0, sizeof(s)); 9723 9724 for (i = 0; i < sc->chip_params->nchan; i += 2) { 9725 mtx_lock(&sc->reg_lock); 9726 if (hw_off_limits(sc)) 9727 rc = ENXIO; 9728 else { 9729 t4_get_lb_stats(sc, i, &s[0]); 9730 t4_get_lb_stats(sc, i + 1, &s[1]); 9731 } 9732 mtx_unlock(&sc->reg_lock); 9733 if (rc != 0) 9734 break; 9735 9736 p0 = &s[0].octets; 9737 p1 = &s[1].octets; 9738 sbuf_printf(sb, "%s Loopback %u" 9739 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 9740 9741 for (j = 0; j < nitems(stat_name); j++) 9742 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 9743 *p0++, *p1++); 9744 } 9745 9746 rc = sbuf_finish(sb); 9747 sbuf_delete(sb); 9748 9749 return (rc); 9750 } 9751 9752 static int 9753 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 9754 { 9755 int rc = 0; 9756 struct port_info *pi = arg1; 9757 struct link_config *lc = &pi->link_cfg; 9758 struct sbuf *sb; 9759 9760 rc = sysctl_wire_old_buffer(req, 0); 9761 if (rc != 0) 9762 return(rc); 9763 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 9764 if (sb == NULL) 9765 return (ENOMEM); 9766 9767 if (lc->link_ok || lc->link_down_rc == 255) 9768 sbuf_printf(sb, "n/a"); 9769 else 9770 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 9771 9772 rc = sbuf_finish(sb); 9773 sbuf_delete(sb); 9774 9775 return (rc); 9776 } 9777 9778 struct mem_desc { 9779 u_int base; 9780 u_int limit; 9781 u_int idx; 9782 }; 9783 9784 static int 9785 mem_desc_cmp(const void *a, const void *b) 9786 { 9787 const u_int v1 = ((const struct mem_desc *)a)->base; 9788 const u_int v2 = ((const struct mem_desc *)b)->base; 9789 9790 if (v1 < v2) 9791 return (-1); 9792 else if (v1 > v2) 9793 return (1); 9794 9795 return (0); 9796 } 9797 9798 static void 9799 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 9800 unsigned int to) 9801 { 9802 unsigned int size; 9803 9804 if (from == to) 9805 return; 9806 9807 size = to - from + 1; 9808 if (size == 0) 9809 return; 9810 9811 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 9812 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 9813 } 9814 9815 static int 9816 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 9817 { 9818 struct adapter *sc = arg1; 9819 struct sbuf *sb; 9820 int rc, i, n; 9821 uint32_t lo, hi, used, free, alloc; 9822 static const char *memory[] = { 9823 "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:" 9824 }; 9825 static const char *region[] = { 9826 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 9827 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 9828 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 9829 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 9830 "RQUDP region:", "PBL region:", "TXPBL region:", 9831 "TLSKey region:", "DBVFIFO region:", "ULPRX state:", 9832 "ULPTX state:", "On-chip queues:", 9833 }; 9834 struct mem_desc avail[4]; 9835 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 9836 struct mem_desc *md = mem; 9837 9838 rc = sysctl_wire_old_buffer(req, 0); 9839 if (rc != 0) 9840 return (rc); 9841 9842 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9843 if (sb == NULL) 9844 return (ENOMEM); 9845 9846 for (i = 0; i < nitems(mem); i++) { 9847 mem[i].limit = 0; 9848 mem[i].idx = i; 9849 } 9850 9851 mtx_lock(&sc->reg_lock); 9852 if (hw_off_limits(sc)) { 9853 rc = ENXIO; 9854 goto done; 9855 } 9856 9857 /* Find and sort the populated memory ranges */ 9858 i = 0; 9859 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 9860 if (lo & F_EDRAM0_ENABLE) { 9861 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 9862 avail[i].base = G_EDRAM0_BASE(hi) << 20; 9863 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 9864 avail[i].idx = 0; 9865 i++; 9866 } 9867 if (lo & F_EDRAM1_ENABLE) { 9868 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 9869 avail[i].base = G_EDRAM1_BASE(hi) << 20; 9870 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 9871 avail[i].idx = 1; 9872 i++; 9873 } 9874 if (lo & F_EXT_MEM_ENABLE) { 9875 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 9876 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 9877 avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20); 9878 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 9879 i++; 9880 } 9881 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 9882 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9883 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9884 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9885 avail[i].idx = 4; 9886 i++; 9887 } 9888 if (is_t6(sc) && lo & F_HMA_MUX) { 9889 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9890 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9891 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9892 avail[i].idx = 5; 9893 i++; 9894 } 9895 MPASS(i <= nitems(avail)); 9896 if (!i) /* no memory available */ 9897 goto done; 9898 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 9899 9900 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 9901 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 9902 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 9903 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9904 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 9905 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 9906 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 9907 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 9908 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 9909 9910 /* the next few have explicit upper bounds */ 9911 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 9912 md->limit = md->base - 1 + 9913 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 9914 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 9915 md++; 9916 9917 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 9918 md->limit = md->base - 1 + 9919 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 9920 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 9921 md++; 9922 9923 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 9924 if (chip_id(sc) <= CHELSIO_T5) 9925 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 9926 else 9927 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 9928 md->limit = 0; 9929 } else { 9930 md->base = 0; 9931 md->idx = nitems(region); /* hide it */ 9932 } 9933 md++; 9934 9935 #define ulp_region(reg) \ 9936 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 9937 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 9938 9939 ulp_region(RX_ISCSI); 9940 ulp_region(RX_TDDP); 9941 ulp_region(TX_TPT); 9942 ulp_region(RX_STAG); 9943 ulp_region(RX_RQ); 9944 ulp_region(RX_RQUDP); 9945 ulp_region(RX_PBL); 9946 ulp_region(TX_PBL); 9947 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 9948 ulp_region(RX_TLS_KEY); 9949 } 9950 #undef ulp_region 9951 9952 md->base = 0; 9953 if (is_t4(sc)) 9954 md->idx = nitems(region); 9955 else { 9956 uint32_t size = 0; 9957 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 9958 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 9959 9960 if (is_t5(sc)) { 9961 if (sge_ctrl & F_VFIFO_ENABLE) 9962 size = fifo_size << 2; 9963 } else 9964 size = G_T6_DBVFIFO_SIZE(fifo_size) << 6; 9965 9966 if (size) { 9967 md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR); 9968 md->limit = md->base + size - 1; 9969 } else 9970 md->idx = nitems(region); 9971 } 9972 md++; 9973 9974 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 9975 md->limit = 0; 9976 md++; 9977 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 9978 md->limit = 0; 9979 md++; 9980 9981 md->base = sc->vres.ocq.start; 9982 if (sc->vres.ocq.size) 9983 md->limit = md->base + sc->vres.ocq.size - 1; 9984 else 9985 md->idx = nitems(region); /* hide it */ 9986 md++; 9987 9988 /* add any address-space holes, there can be up to 3 */ 9989 for (n = 0; n < i - 1; n++) 9990 if (avail[n].limit < avail[n + 1].base) 9991 (md++)->base = avail[n].limit; 9992 if (avail[n].limit) 9993 (md++)->base = avail[n].limit; 9994 9995 n = md - mem; 9996 MPASS(n <= nitems(mem)); 9997 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 9998 9999 for (lo = 0; lo < i; lo++) 10000 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 10001 avail[lo].limit - 1); 10002 10003 sbuf_printf(sb, "\n"); 10004 for (i = 0; i < n; i++) { 10005 if (mem[i].idx >= nitems(region)) 10006 continue; /* skip holes */ 10007 if (!mem[i].limit) 10008 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 10009 mem_region_show(sb, region[mem[i].idx], mem[i].base, 10010 mem[i].limit); 10011 } 10012 10013 sbuf_printf(sb, "\n"); 10014 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 10015 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 10016 mem_region_show(sb, "uP RAM:", lo, hi); 10017 10018 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 10019 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 10020 mem_region_show(sb, "uP Extmem2:", lo, hi); 10021 10022 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 10023 for (i = 0, free = 0; i < 2; i++) 10024 free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT)); 10025 sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n", 10026 G_PMRXMAXPAGE(lo), free, 10027 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 10028 (lo & F_PMRXNUMCHN) ? 2 : 1); 10029 10030 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 10031 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 10032 for (i = 0, free = 0; i < 4; i++) 10033 free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT)); 10034 sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n", 10035 G_PMTXMAXPAGE(lo), free, 10036 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 10037 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 10038 sbuf_printf(sb, "%u p-structs (%u free)\n", 10039 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT), 10040 G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT))); 10041 10042 for (i = 0; i < 4; i++) { 10043 if (chip_id(sc) > CHELSIO_T5) 10044 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 10045 else 10046 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 10047 if (is_t5(sc)) { 10048 used = G_T5_USED(lo); 10049 alloc = G_T5_ALLOC(lo); 10050 } else { 10051 used = G_USED(lo); 10052 alloc = G_ALLOC(lo); 10053 } 10054 /* For T6 these are MAC buffer groups */ 10055 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 10056 i, used, alloc); 10057 } 10058 for (i = 0; i < sc->chip_params->nchan; i++) { 10059 if (chip_id(sc) > CHELSIO_T5) 10060 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 10061 else 10062 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 10063 if (is_t5(sc)) { 10064 used = G_T5_USED(lo); 10065 alloc = G_T5_ALLOC(lo); 10066 } else { 10067 used = G_USED(lo); 10068 alloc = G_ALLOC(lo); 10069 } 10070 /* For T6 these are MAC buffer groups */ 10071 sbuf_printf(sb, 10072 "\nLoopback %d using %u pages out of %u allocated", 10073 i, used, alloc); 10074 } 10075 done: 10076 mtx_unlock(&sc->reg_lock); 10077 if (rc == 0) 10078 rc = sbuf_finish(sb); 10079 sbuf_delete(sb); 10080 return (rc); 10081 } 10082 10083 static inline void 10084 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 10085 { 10086 *mask = x | y; 10087 y = htobe64(y); 10088 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 10089 } 10090 10091 static int 10092 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 10093 { 10094 struct adapter *sc = arg1; 10095 struct sbuf *sb; 10096 int rc, i; 10097 10098 MPASS(chip_id(sc) <= CHELSIO_T5); 10099 10100 rc = sysctl_wire_old_buffer(req, 0); 10101 if (rc != 0) 10102 return (rc); 10103 10104 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10105 if (sb == NULL) 10106 return (ENOMEM); 10107 10108 sbuf_printf(sb, 10109 "Idx Ethernet address Mask Vld Ports PF" 10110 " VF Replication P0 P1 P2 P3 ML"); 10111 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10112 uint64_t tcamx, tcamy, mask; 10113 uint32_t cls_lo, cls_hi; 10114 uint8_t addr[ETHER_ADDR_LEN]; 10115 10116 mtx_lock(&sc->reg_lock); 10117 if (hw_off_limits(sc)) 10118 rc = ENXIO; 10119 else { 10120 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 10121 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 10122 } 10123 mtx_unlock(&sc->reg_lock); 10124 if (rc != 0) 10125 break; 10126 if (tcamx & tcamy) 10127 continue; 10128 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10129 mtx_lock(&sc->reg_lock); 10130 if (hw_off_limits(sc)) 10131 rc = ENXIO; 10132 else { 10133 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10134 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10135 } 10136 mtx_unlock(&sc->reg_lock); 10137 if (rc != 0) 10138 break; 10139 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 10140 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 10141 addr[3], addr[4], addr[5], (uintmax_t)mask, 10142 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 10143 G_PORTMAP(cls_hi), G_PF(cls_lo), 10144 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 10145 10146 if (cls_lo & F_REPLICATE) { 10147 struct fw_ldst_cmd ldst_cmd; 10148 10149 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10150 ldst_cmd.op_to_addrspace = 10151 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10152 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10153 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10154 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10155 ldst_cmd.u.mps.rplc.fid_idx = 10156 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10157 V_FW_LDST_CMD_IDX(i)); 10158 10159 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10160 "t4mps"); 10161 if (rc) 10162 break; 10163 if (hw_off_limits(sc)) 10164 rc = ENXIO; 10165 else 10166 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10167 sizeof(ldst_cmd), &ldst_cmd); 10168 end_synchronized_op(sc, 0); 10169 if (rc != 0) 10170 break; 10171 else { 10172 sbuf_printf(sb, " %08x %08x %08x %08x", 10173 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10174 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10175 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10176 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10177 } 10178 } else 10179 sbuf_printf(sb, "%36s", ""); 10180 10181 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 10182 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 10183 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 10184 } 10185 10186 if (rc) 10187 (void) sbuf_finish(sb); 10188 else 10189 rc = sbuf_finish(sb); 10190 sbuf_delete(sb); 10191 10192 return (rc); 10193 } 10194 10195 static int 10196 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 10197 { 10198 struct adapter *sc = arg1; 10199 struct sbuf *sb; 10200 int rc, i; 10201 10202 MPASS(chip_id(sc) > CHELSIO_T5); 10203 10204 rc = sysctl_wire_old_buffer(req, 0); 10205 if (rc != 0) 10206 return (rc); 10207 10208 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10209 if (sb == NULL) 10210 return (ENOMEM); 10211 10212 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 10213 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 10214 " Replication" 10215 " P0 P1 P2 P3 ML\n"); 10216 10217 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10218 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 10219 uint16_t ivlan; 10220 uint64_t tcamx, tcamy, val, mask; 10221 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 10222 uint8_t addr[ETHER_ADDR_LEN]; 10223 10224 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 10225 if (i < 256) 10226 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 10227 else 10228 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 10229 mtx_lock(&sc->reg_lock); 10230 if (hw_off_limits(sc)) 10231 rc = ENXIO; 10232 else { 10233 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10234 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10235 tcamy = G_DMACH(val) << 32; 10236 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10237 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10238 } 10239 mtx_unlock(&sc->reg_lock); 10240 if (rc != 0) 10241 break; 10242 10243 lookup_type = G_DATALKPTYPE(data2); 10244 port_num = G_DATAPORTNUM(data2); 10245 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10246 /* Inner header VNI */ 10247 vniy = ((data2 & F_DATAVIDH2) << 23) | 10248 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10249 dip_hit = data2 & F_DATADIPHIT; 10250 vlan_vld = 0; 10251 } else { 10252 vniy = 0; 10253 dip_hit = 0; 10254 vlan_vld = data2 & F_DATAVIDH2; 10255 ivlan = G_VIDL(val); 10256 } 10257 10258 ctl |= V_CTLXYBITSEL(1); 10259 mtx_lock(&sc->reg_lock); 10260 if (hw_off_limits(sc)) 10261 rc = ENXIO; 10262 else { 10263 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10264 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10265 tcamx = G_DMACH(val) << 32; 10266 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10267 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10268 } 10269 mtx_unlock(&sc->reg_lock); 10270 if (rc != 0) 10271 break; 10272 10273 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10274 /* Inner header VNI mask */ 10275 vnix = ((data2 & F_DATAVIDH2) << 23) | 10276 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10277 } else 10278 vnix = 0; 10279 10280 if (tcamx & tcamy) 10281 continue; 10282 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10283 10284 mtx_lock(&sc->reg_lock); 10285 if (hw_off_limits(sc)) 10286 rc = ENXIO; 10287 else { 10288 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10289 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10290 } 10291 mtx_unlock(&sc->reg_lock); 10292 if (rc != 0) 10293 break; 10294 10295 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10296 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10297 "%012jx %06x %06x - - %3c" 10298 " I %4x %3c %#x%4u%4d", i, addr[0], 10299 addr[1], addr[2], addr[3], addr[4], addr[5], 10300 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 10301 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10302 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10303 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10304 } else { 10305 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10306 "%012jx - - ", i, addr[0], addr[1], 10307 addr[2], addr[3], addr[4], addr[5], 10308 (uintmax_t)mask); 10309 10310 if (vlan_vld) 10311 sbuf_printf(sb, "%4u Y ", ivlan); 10312 else 10313 sbuf_printf(sb, " - N "); 10314 10315 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 10316 lookup_type ? 'I' : 'O', port_num, 10317 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10318 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10319 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10320 } 10321 10322 10323 if (cls_lo & F_T6_REPLICATE) { 10324 struct fw_ldst_cmd ldst_cmd; 10325 10326 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10327 ldst_cmd.op_to_addrspace = 10328 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10329 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10330 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10331 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10332 ldst_cmd.u.mps.rplc.fid_idx = 10333 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10334 V_FW_LDST_CMD_IDX(i)); 10335 10336 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10337 "t6mps"); 10338 if (rc) 10339 break; 10340 if (hw_off_limits(sc)) 10341 rc = ENXIO; 10342 else 10343 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10344 sizeof(ldst_cmd), &ldst_cmd); 10345 end_synchronized_op(sc, 0); 10346 if (rc != 0) 10347 break; 10348 else { 10349 sbuf_printf(sb, " %08x %08x %08x %08x" 10350 " %08x %08x %08x %08x", 10351 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 10352 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 10353 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 10354 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 10355 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10356 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10357 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10358 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10359 } 10360 } else 10361 sbuf_printf(sb, "%72s", ""); 10362 10363 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 10364 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 10365 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 10366 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 10367 } 10368 10369 if (rc) 10370 (void) sbuf_finish(sb); 10371 else 10372 rc = sbuf_finish(sb); 10373 sbuf_delete(sb); 10374 10375 return (rc); 10376 } 10377 10378 static int 10379 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 10380 { 10381 struct adapter *sc = arg1; 10382 struct sbuf *sb; 10383 int rc; 10384 uint16_t mtus[NMTUS]; 10385 10386 rc = sysctl_wire_old_buffer(req, 0); 10387 if (rc != 0) 10388 return (rc); 10389 10390 mtx_lock(&sc->reg_lock); 10391 if (hw_off_limits(sc)) 10392 rc = ENXIO; 10393 else 10394 t4_read_mtu_tbl(sc, mtus, NULL); 10395 mtx_unlock(&sc->reg_lock); 10396 if (rc != 0) 10397 return (rc); 10398 10399 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10400 if (sb == NULL) 10401 return (ENOMEM); 10402 10403 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 10404 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 10405 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 10406 mtus[14], mtus[15]); 10407 10408 rc = sbuf_finish(sb); 10409 sbuf_delete(sb); 10410 10411 return (rc); 10412 } 10413 10414 static int 10415 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 10416 { 10417 struct adapter *sc = arg1; 10418 struct sbuf *sb; 10419 int rc, i; 10420 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 10421 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 10422 static const char *tx_stats[MAX_PM_NSTATS] = { 10423 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 10424 "Tx FIFO wait", NULL, "Tx latency" 10425 }; 10426 static const char *rx_stats[MAX_PM_NSTATS] = { 10427 "Read:", "Write bypass:", "Write mem:", "Flush:", 10428 "Rx FIFO wait", NULL, "Rx latency" 10429 }; 10430 10431 rc = sysctl_wire_old_buffer(req, 0); 10432 if (rc != 0) 10433 return (rc); 10434 10435 mtx_lock(&sc->reg_lock); 10436 if (hw_off_limits(sc)) 10437 rc = ENXIO; 10438 else { 10439 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 10440 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 10441 } 10442 mtx_unlock(&sc->reg_lock); 10443 if (rc != 0) 10444 return (rc); 10445 10446 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10447 if (sb == NULL) 10448 return (ENOMEM); 10449 10450 sbuf_printf(sb, " Tx pcmds Tx bytes"); 10451 for (i = 0; i < 4; i++) { 10452 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10453 tx_cyc[i]); 10454 } 10455 10456 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 10457 for (i = 0; i < 4; i++) { 10458 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10459 rx_cyc[i]); 10460 } 10461 10462 if (chip_id(sc) > CHELSIO_T5) { 10463 sbuf_printf(sb, 10464 "\n Total wait Total occupancy"); 10465 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10466 tx_cyc[i]); 10467 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10468 rx_cyc[i]); 10469 10470 i += 2; 10471 MPASS(i < nitems(tx_stats)); 10472 10473 sbuf_printf(sb, 10474 "\n Reads Total wait"); 10475 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10476 tx_cyc[i]); 10477 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10478 rx_cyc[i]); 10479 } 10480 10481 rc = sbuf_finish(sb); 10482 sbuf_delete(sb); 10483 10484 return (rc); 10485 } 10486 10487 static int 10488 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 10489 { 10490 struct adapter *sc = arg1; 10491 struct sbuf *sb; 10492 int rc; 10493 struct tp_rdma_stats stats; 10494 10495 rc = sysctl_wire_old_buffer(req, 0); 10496 if (rc != 0) 10497 return (rc); 10498 10499 mtx_lock(&sc->reg_lock); 10500 if (hw_off_limits(sc)) 10501 rc = ENXIO; 10502 else 10503 t4_tp_get_rdma_stats(sc, &stats, 0); 10504 mtx_unlock(&sc->reg_lock); 10505 if (rc != 0) 10506 return (rc); 10507 10508 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10509 if (sb == NULL) 10510 return (ENOMEM); 10511 10512 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 10513 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 10514 10515 rc = sbuf_finish(sb); 10516 sbuf_delete(sb); 10517 10518 return (rc); 10519 } 10520 10521 static int 10522 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 10523 { 10524 struct adapter *sc = arg1; 10525 struct sbuf *sb; 10526 int rc; 10527 struct tp_tcp_stats v4, v6; 10528 10529 rc = sysctl_wire_old_buffer(req, 0); 10530 if (rc != 0) 10531 return (rc); 10532 10533 mtx_lock(&sc->reg_lock); 10534 if (hw_off_limits(sc)) 10535 rc = ENXIO; 10536 else 10537 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 10538 mtx_unlock(&sc->reg_lock); 10539 if (rc != 0) 10540 return (rc); 10541 10542 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10543 if (sb == NULL) 10544 return (ENOMEM); 10545 10546 sbuf_printf(sb, 10547 " IP IPv6\n"); 10548 sbuf_printf(sb, "OutRsts: %20u %20u\n", 10549 v4.tcp_out_rsts, v6.tcp_out_rsts); 10550 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 10551 v4.tcp_in_segs, v6.tcp_in_segs); 10552 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 10553 v4.tcp_out_segs, v6.tcp_out_segs); 10554 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 10555 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 10556 10557 rc = sbuf_finish(sb); 10558 sbuf_delete(sb); 10559 10560 return (rc); 10561 } 10562 10563 static int 10564 sysctl_tids(SYSCTL_HANDLER_ARGS) 10565 { 10566 struct adapter *sc = arg1; 10567 struct sbuf *sb; 10568 int rc; 10569 uint32_t x, y; 10570 struct tid_info *t = &sc->tids; 10571 10572 rc = sysctl_wire_old_buffer(req, 0); 10573 if (rc != 0) 10574 return (rc); 10575 10576 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10577 if (sb == NULL) 10578 return (ENOMEM); 10579 10580 if (t->natids) { 10581 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 10582 t->atids_in_use); 10583 } 10584 10585 if (t->nhpftids) { 10586 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 10587 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 10588 } 10589 10590 if (t->ntids) { 10591 bool hashen = false; 10592 10593 mtx_lock(&sc->reg_lock); 10594 if (hw_off_limits(sc)) 10595 rc = ENXIO; 10596 else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 10597 hashen = true; 10598 if (chip_id(sc) <= CHELSIO_T5) { 10599 x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 10600 y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 10601 } else { 10602 x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 10603 y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 10604 } 10605 } 10606 mtx_unlock(&sc->reg_lock); 10607 if (rc != 0) 10608 goto done; 10609 10610 sbuf_printf(sb, "TID range: "); 10611 if (hashen) { 10612 if (x) 10613 sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1); 10614 sbuf_printf(sb, "%u-%u", y, t->ntids - 1); 10615 } else { 10616 sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base + 10617 t->ntids - 1); 10618 } 10619 sbuf_printf(sb, ", in use: %u\n", 10620 atomic_load_acq_int(&t->tids_in_use)); 10621 } 10622 10623 if (t->nstids) { 10624 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 10625 t->stid_base + t->nstids - 1, t->stids_in_use); 10626 } 10627 10628 if (t->nftids) { 10629 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 10630 t->ftid_end, t->ftids_in_use); 10631 } 10632 10633 if (t->netids) { 10634 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 10635 t->etid_base + t->netids - 1, t->etids_in_use); 10636 } 10637 10638 mtx_lock(&sc->reg_lock); 10639 if (hw_off_limits(sc)) 10640 rc = ENXIO; 10641 else { 10642 x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4); 10643 y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6); 10644 } 10645 mtx_unlock(&sc->reg_lock); 10646 if (rc != 0) 10647 goto done; 10648 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y); 10649 done: 10650 if (rc == 0) 10651 rc = sbuf_finish(sb); 10652 else 10653 (void)sbuf_finish(sb); 10654 sbuf_delete(sb); 10655 10656 return (rc); 10657 } 10658 10659 static int 10660 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 10661 { 10662 struct adapter *sc = arg1; 10663 struct sbuf *sb; 10664 int rc; 10665 struct tp_err_stats stats; 10666 10667 rc = sysctl_wire_old_buffer(req, 0); 10668 if (rc != 0) 10669 return (rc); 10670 10671 mtx_lock(&sc->reg_lock); 10672 if (hw_off_limits(sc)) 10673 rc = ENXIO; 10674 else 10675 t4_tp_get_err_stats(sc, &stats, 0); 10676 mtx_unlock(&sc->reg_lock); 10677 if (rc != 0) 10678 return (rc); 10679 10680 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10681 if (sb == NULL) 10682 return (ENOMEM); 10683 10684 if (sc->chip_params->nchan > 2) { 10685 sbuf_printf(sb, " channel 0 channel 1" 10686 " channel 2 channel 3\n"); 10687 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 10688 stats.mac_in_errs[0], stats.mac_in_errs[1], 10689 stats.mac_in_errs[2], stats.mac_in_errs[3]); 10690 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 10691 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 10692 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 10693 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 10694 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 10695 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 10696 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 10697 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 10698 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 10699 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 10700 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 10701 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 10702 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 10703 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 10704 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 10705 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 10706 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 10707 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 10708 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 10709 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 10710 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 10711 } else { 10712 sbuf_printf(sb, " channel 0 channel 1\n"); 10713 sbuf_printf(sb, "macInErrs: %10u %10u\n", 10714 stats.mac_in_errs[0], stats.mac_in_errs[1]); 10715 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 10716 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 10717 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 10718 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 10719 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 10720 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 10721 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 10722 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 10723 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 10724 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 10725 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 10726 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 10727 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 10728 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 10729 } 10730 10731 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 10732 stats.ofld_no_neigh, stats.ofld_cong_defer); 10733 10734 rc = sbuf_finish(sb); 10735 sbuf_delete(sb); 10736 10737 return (rc); 10738 } 10739 10740 static int 10741 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS) 10742 { 10743 struct adapter *sc = arg1; 10744 struct sbuf *sb; 10745 int rc; 10746 struct tp_tnl_stats stats; 10747 10748 rc = sysctl_wire_old_buffer(req, 0); 10749 if (rc != 0) 10750 return(rc); 10751 10752 mtx_lock(&sc->reg_lock); 10753 if (hw_off_limits(sc)) 10754 rc = ENXIO; 10755 else 10756 t4_tp_get_tnl_stats(sc, &stats, 1); 10757 mtx_unlock(&sc->reg_lock); 10758 if (rc != 0) 10759 return (rc); 10760 10761 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10762 if (sb == NULL) 10763 return (ENOMEM); 10764 10765 if (sc->chip_params->nchan > 2) { 10766 sbuf_printf(sb, " channel 0 channel 1" 10767 " channel 2 channel 3\n"); 10768 sbuf_printf(sb, "OutPkts: %10u %10u %10u %10u\n", 10769 stats.out_pkt[0], stats.out_pkt[1], 10770 stats.out_pkt[2], stats.out_pkt[3]); 10771 sbuf_printf(sb, "InPkts: %10u %10u %10u %10u", 10772 stats.in_pkt[0], stats.in_pkt[1], 10773 stats.in_pkt[2], stats.in_pkt[3]); 10774 } else { 10775 sbuf_printf(sb, " channel 0 channel 1\n"); 10776 sbuf_printf(sb, "OutPkts: %10u %10u\n", 10777 stats.out_pkt[0], stats.out_pkt[1]); 10778 sbuf_printf(sb, "InPkts: %10u %10u", 10779 stats.in_pkt[0], stats.in_pkt[1]); 10780 } 10781 10782 rc = sbuf_finish(sb); 10783 sbuf_delete(sb); 10784 10785 return (rc); 10786 } 10787 10788 static int 10789 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 10790 { 10791 struct adapter *sc = arg1; 10792 struct tp_params *tpp = &sc->params.tp; 10793 u_int mask; 10794 int rc; 10795 10796 mask = tpp->la_mask >> 16; 10797 rc = sysctl_handle_int(oidp, &mask, 0, req); 10798 if (rc != 0 || req->newptr == NULL) 10799 return (rc); 10800 if (mask > 0xffff) 10801 return (EINVAL); 10802 mtx_lock(&sc->reg_lock); 10803 if (hw_off_limits(sc)) 10804 rc = ENXIO; 10805 else { 10806 tpp->la_mask = mask << 16; 10807 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, 10808 tpp->la_mask); 10809 } 10810 mtx_unlock(&sc->reg_lock); 10811 10812 return (rc); 10813 } 10814 10815 struct field_desc { 10816 const char *name; 10817 u_int start; 10818 u_int width; 10819 }; 10820 10821 static void 10822 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 10823 { 10824 char buf[32]; 10825 int line_size = 0; 10826 10827 while (f->name) { 10828 uint64_t mask = (1ULL << f->width) - 1; 10829 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 10830 ((uintmax_t)v >> f->start) & mask); 10831 10832 if (line_size + len >= 79) { 10833 line_size = 8; 10834 sbuf_printf(sb, "\n "); 10835 } 10836 sbuf_printf(sb, "%s ", buf); 10837 line_size += len + 1; 10838 f++; 10839 } 10840 sbuf_printf(sb, "\n"); 10841 } 10842 10843 static const struct field_desc tp_la0[] = { 10844 { "RcfOpCodeOut", 60, 4 }, 10845 { "State", 56, 4 }, 10846 { "WcfState", 52, 4 }, 10847 { "RcfOpcSrcOut", 50, 2 }, 10848 { "CRxError", 49, 1 }, 10849 { "ERxError", 48, 1 }, 10850 { "SanityFailed", 47, 1 }, 10851 { "SpuriousMsg", 46, 1 }, 10852 { "FlushInputMsg", 45, 1 }, 10853 { "FlushInputCpl", 44, 1 }, 10854 { "RssUpBit", 43, 1 }, 10855 { "RssFilterHit", 42, 1 }, 10856 { "Tid", 32, 10 }, 10857 { "InitTcb", 31, 1 }, 10858 { "LineNumber", 24, 7 }, 10859 { "Emsg", 23, 1 }, 10860 { "EdataOut", 22, 1 }, 10861 { "Cmsg", 21, 1 }, 10862 { "CdataOut", 20, 1 }, 10863 { "EreadPdu", 19, 1 }, 10864 { "CreadPdu", 18, 1 }, 10865 { "TunnelPkt", 17, 1 }, 10866 { "RcfPeerFin", 16, 1 }, 10867 { "RcfReasonOut", 12, 4 }, 10868 { "TxCchannel", 10, 2 }, 10869 { "RcfTxChannel", 8, 2 }, 10870 { "RxEchannel", 6, 2 }, 10871 { "RcfRxChannel", 5, 1 }, 10872 { "RcfDataOutSrdy", 4, 1 }, 10873 { "RxDvld", 3, 1 }, 10874 { "RxOoDvld", 2, 1 }, 10875 { "RxCongestion", 1, 1 }, 10876 { "TxCongestion", 0, 1 }, 10877 { NULL } 10878 }; 10879 10880 static const struct field_desc tp_la1[] = { 10881 { "CplCmdIn", 56, 8 }, 10882 { "CplCmdOut", 48, 8 }, 10883 { "ESynOut", 47, 1 }, 10884 { "EAckOut", 46, 1 }, 10885 { "EFinOut", 45, 1 }, 10886 { "ERstOut", 44, 1 }, 10887 { "SynIn", 43, 1 }, 10888 { "AckIn", 42, 1 }, 10889 { "FinIn", 41, 1 }, 10890 { "RstIn", 40, 1 }, 10891 { "DataIn", 39, 1 }, 10892 { "DataInVld", 38, 1 }, 10893 { "PadIn", 37, 1 }, 10894 { "RxBufEmpty", 36, 1 }, 10895 { "RxDdp", 35, 1 }, 10896 { "RxFbCongestion", 34, 1 }, 10897 { "TxFbCongestion", 33, 1 }, 10898 { "TxPktSumSrdy", 32, 1 }, 10899 { "RcfUlpType", 28, 4 }, 10900 { "Eread", 27, 1 }, 10901 { "Ebypass", 26, 1 }, 10902 { "Esave", 25, 1 }, 10903 { "Static0", 24, 1 }, 10904 { "Cread", 23, 1 }, 10905 { "Cbypass", 22, 1 }, 10906 { "Csave", 21, 1 }, 10907 { "CPktOut", 20, 1 }, 10908 { "RxPagePoolFull", 18, 2 }, 10909 { "RxLpbkPkt", 17, 1 }, 10910 { "TxLpbkPkt", 16, 1 }, 10911 { "RxVfValid", 15, 1 }, 10912 { "SynLearned", 14, 1 }, 10913 { "SetDelEntry", 13, 1 }, 10914 { "SetInvEntry", 12, 1 }, 10915 { "CpcmdDvld", 11, 1 }, 10916 { "CpcmdSave", 10, 1 }, 10917 { "RxPstructsFull", 8, 2 }, 10918 { "EpcmdDvld", 7, 1 }, 10919 { "EpcmdFlush", 6, 1 }, 10920 { "EpcmdTrimPrefix", 5, 1 }, 10921 { "EpcmdTrimPostfix", 4, 1 }, 10922 { "ERssIp4Pkt", 3, 1 }, 10923 { "ERssIp6Pkt", 2, 1 }, 10924 { "ERssTcpUdpPkt", 1, 1 }, 10925 { "ERssFceFipPkt", 0, 1 }, 10926 { NULL } 10927 }; 10928 10929 static const struct field_desc tp_la2[] = { 10930 { "CplCmdIn", 56, 8 }, 10931 { "MpsVfVld", 55, 1 }, 10932 { "MpsPf", 52, 3 }, 10933 { "MpsVf", 44, 8 }, 10934 { "SynIn", 43, 1 }, 10935 { "AckIn", 42, 1 }, 10936 { "FinIn", 41, 1 }, 10937 { "RstIn", 40, 1 }, 10938 { "DataIn", 39, 1 }, 10939 { "DataInVld", 38, 1 }, 10940 { "PadIn", 37, 1 }, 10941 { "RxBufEmpty", 36, 1 }, 10942 { "RxDdp", 35, 1 }, 10943 { "RxFbCongestion", 34, 1 }, 10944 { "TxFbCongestion", 33, 1 }, 10945 { "TxPktSumSrdy", 32, 1 }, 10946 { "RcfUlpType", 28, 4 }, 10947 { "Eread", 27, 1 }, 10948 { "Ebypass", 26, 1 }, 10949 { "Esave", 25, 1 }, 10950 { "Static0", 24, 1 }, 10951 { "Cread", 23, 1 }, 10952 { "Cbypass", 22, 1 }, 10953 { "Csave", 21, 1 }, 10954 { "CPktOut", 20, 1 }, 10955 { "RxPagePoolFull", 18, 2 }, 10956 { "RxLpbkPkt", 17, 1 }, 10957 { "TxLpbkPkt", 16, 1 }, 10958 { "RxVfValid", 15, 1 }, 10959 { "SynLearned", 14, 1 }, 10960 { "SetDelEntry", 13, 1 }, 10961 { "SetInvEntry", 12, 1 }, 10962 { "CpcmdDvld", 11, 1 }, 10963 { "CpcmdSave", 10, 1 }, 10964 { "RxPstructsFull", 8, 2 }, 10965 { "EpcmdDvld", 7, 1 }, 10966 { "EpcmdFlush", 6, 1 }, 10967 { "EpcmdTrimPrefix", 5, 1 }, 10968 { "EpcmdTrimPostfix", 4, 1 }, 10969 { "ERssIp4Pkt", 3, 1 }, 10970 { "ERssIp6Pkt", 2, 1 }, 10971 { "ERssTcpUdpPkt", 1, 1 }, 10972 { "ERssFceFipPkt", 0, 1 }, 10973 { NULL } 10974 }; 10975 10976 static void 10977 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 10978 { 10979 10980 field_desc_show(sb, *p, tp_la0); 10981 } 10982 10983 static void 10984 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 10985 { 10986 10987 if (idx) 10988 sbuf_printf(sb, "\n"); 10989 field_desc_show(sb, p[0], tp_la0); 10990 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10991 field_desc_show(sb, p[1], tp_la0); 10992 } 10993 10994 static void 10995 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 10996 { 10997 10998 if (idx) 10999 sbuf_printf(sb, "\n"); 11000 field_desc_show(sb, p[0], tp_la0); 11001 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 11002 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 11003 } 11004 11005 static int 11006 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 11007 { 11008 struct adapter *sc = arg1; 11009 struct sbuf *sb; 11010 uint64_t *buf, *p; 11011 int rc; 11012 u_int i, inc; 11013 void (*show_func)(struct sbuf *, uint64_t *, int); 11014 11015 rc = sysctl_wire_old_buffer(req, 0); 11016 if (rc != 0) 11017 return (rc); 11018 11019 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11020 if (sb == NULL) 11021 return (ENOMEM); 11022 11023 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 11024 11025 mtx_lock(&sc->reg_lock); 11026 if (hw_off_limits(sc)) 11027 rc = ENXIO; 11028 else { 11029 t4_tp_read_la(sc, buf, NULL); 11030 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 11031 case 2: 11032 inc = 2; 11033 show_func = tp_la_show2; 11034 break; 11035 case 3: 11036 inc = 2; 11037 show_func = tp_la_show3; 11038 break; 11039 default: 11040 inc = 1; 11041 show_func = tp_la_show; 11042 } 11043 } 11044 mtx_unlock(&sc->reg_lock); 11045 if (rc != 0) 11046 goto done; 11047 11048 p = buf; 11049 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 11050 (*show_func)(sb, p, i); 11051 rc = sbuf_finish(sb); 11052 done: 11053 sbuf_delete(sb); 11054 free(buf, M_CXGBE); 11055 return (rc); 11056 } 11057 11058 static int 11059 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 11060 { 11061 struct adapter *sc = arg1; 11062 struct sbuf *sb; 11063 int rc; 11064 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 11065 11066 rc = sysctl_wire_old_buffer(req, 0); 11067 if (rc != 0) 11068 return (rc); 11069 11070 mtx_lock(&sc->reg_lock); 11071 if (hw_off_limits(sc)) 11072 rc = ENXIO; 11073 else 11074 t4_get_chan_txrate(sc, nrate, orate); 11075 mtx_unlock(&sc->reg_lock); 11076 if (rc != 0) 11077 return (rc); 11078 11079 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 11080 if (sb == NULL) 11081 return (ENOMEM); 11082 11083 if (sc->chip_params->nchan > 2) { 11084 sbuf_printf(sb, " channel 0 channel 1" 11085 " channel 2 channel 3\n"); 11086 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 11087 nrate[0], nrate[1], nrate[2], nrate[3]); 11088 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 11089 orate[0], orate[1], orate[2], orate[3]); 11090 } else { 11091 sbuf_printf(sb, " channel 0 channel 1\n"); 11092 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 11093 nrate[0], nrate[1]); 11094 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 11095 orate[0], orate[1]); 11096 } 11097 11098 rc = sbuf_finish(sb); 11099 sbuf_delete(sb); 11100 11101 return (rc); 11102 } 11103 11104 static int 11105 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 11106 { 11107 struct adapter *sc = arg1; 11108 struct sbuf *sb; 11109 uint32_t *buf, *p; 11110 int rc, i; 11111 11112 rc = sysctl_wire_old_buffer(req, 0); 11113 if (rc != 0) 11114 return (rc); 11115 11116 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11117 if (sb == NULL) 11118 return (ENOMEM); 11119 11120 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 11121 M_ZERO | M_WAITOK); 11122 11123 mtx_lock(&sc->reg_lock); 11124 if (hw_off_limits(sc)) 11125 rc = ENXIO; 11126 else 11127 t4_ulprx_read_la(sc, buf); 11128 mtx_unlock(&sc->reg_lock); 11129 if (rc != 0) 11130 goto done; 11131 11132 p = buf; 11133 sbuf_printf(sb, " Pcmd Type Message" 11134 " Data"); 11135 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 11136 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 11137 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 11138 } 11139 rc = sbuf_finish(sb); 11140 done: 11141 sbuf_delete(sb); 11142 free(buf, M_CXGBE); 11143 return (rc); 11144 } 11145 11146 static int 11147 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 11148 { 11149 struct adapter *sc = arg1; 11150 struct sbuf *sb; 11151 int rc; 11152 uint32_t cfg, s1, s2; 11153 11154 MPASS(chip_id(sc) >= CHELSIO_T5); 11155 11156 rc = sysctl_wire_old_buffer(req, 0); 11157 if (rc != 0) 11158 return (rc); 11159 11160 mtx_lock(&sc->reg_lock); 11161 if (hw_off_limits(sc)) 11162 rc = ENXIO; 11163 else { 11164 cfg = t4_read_reg(sc, A_SGE_STAT_CFG); 11165 s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL); 11166 s2 = t4_read_reg(sc, A_SGE_STAT_MATCH); 11167 } 11168 mtx_unlock(&sc->reg_lock); 11169 if (rc != 0) 11170 return (rc); 11171 11172 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11173 if (sb == NULL) 11174 return (ENOMEM); 11175 11176 if (G_STATSOURCE_T5(cfg) == 7) { 11177 int mode; 11178 11179 mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg); 11180 if (mode == 0) 11181 sbuf_printf(sb, "total %d, incomplete %d", s1, s2); 11182 else if (mode == 1) 11183 sbuf_printf(sb, "total %d, data overflow %d", s1, s2); 11184 else 11185 sbuf_printf(sb, "unknown mode %d", mode); 11186 } 11187 rc = sbuf_finish(sb); 11188 sbuf_delete(sb); 11189 11190 return (rc); 11191 } 11192 11193 static int 11194 sysctl_cpus(SYSCTL_HANDLER_ARGS) 11195 { 11196 struct adapter *sc = arg1; 11197 enum cpu_sets op = arg2; 11198 cpuset_t cpuset; 11199 struct sbuf *sb; 11200 int i, rc; 11201 11202 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 11203 11204 CPU_ZERO(&cpuset); 11205 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 11206 if (rc != 0) 11207 return (rc); 11208 11209 rc = sysctl_wire_old_buffer(req, 0); 11210 if (rc != 0) 11211 return (rc); 11212 11213 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11214 if (sb == NULL) 11215 return (ENOMEM); 11216 11217 CPU_FOREACH(i) 11218 sbuf_printf(sb, "%d ", i); 11219 rc = sbuf_finish(sb); 11220 sbuf_delete(sb); 11221 11222 return (rc); 11223 } 11224 11225 static int 11226 sysctl_reset(SYSCTL_HANDLER_ARGS) 11227 { 11228 struct adapter *sc = arg1; 11229 u_int val; 11230 int rc; 11231 11232 val = atomic_load_int(&sc->num_resets); 11233 rc = sysctl_handle_int(oidp, &val, 0, req); 11234 if (rc != 0 || req->newptr == NULL) 11235 return (rc); 11236 11237 if (val == 0) { 11238 /* Zero out the counter that tracks reset. */ 11239 atomic_store_int(&sc->num_resets, 0); 11240 return (0); 11241 } 11242 11243 if (val != 1) 11244 return (EINVAL); /* 0 or 1 are the only legal values */ 11245 11246 if (hw_off_limits(sc)) /* harmless race */ 11247 return (EALREADY); 11248 11249 taskqueue_enqueue(reset_tq, &sc->reset_task); 11250 return (0); 11251 } 11252 11253 #ifdef TCP_OFFLOAD 11254 static int 11255 sysctl_tls(SYSCTL_HANDLER_ARGS) 11256 { 11257 struct adapter *sc = arg1; 11258 int i, j, v, rc; 11259 struct vi_info *vi; 11260 11261 v = sc->tt.tls; 11262 rc = sysctl_handle_int(oidp, &v, 0, req); 11263 if (rc != 0 || req->newptr == NULL) 11264 return (rc); 11265 11266 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 11267 return (ENOTSUP); 11268 11269 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls"); 11270 if (rc) 11271 return (rc); 11272 if (hw_off_limits(sc)) 11273 rc = ENXIO; 11274 else { 11275 sc->tt.tls = !!v; 11276 for_each_port(sc, i) { 11277 for_each_vi(sc->port[i], j, vi) { 11278 if (vi->flags & VI_INIT_DONE) 11279 t4_update_fl_bufsize(vi->ifp); 11280 } 11281 } 11282 } 11283 end_synchronized_op(sc, 0); 11284 11285 return (rc); 11286 11287 } 11288 11289 static int 11290 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 11291 { 11292 struct adapter *sc = arg1; 11293 int *old_ports, *new_ports; 11294 int i, new_count, rc; 11295 11296 if (req->newptr == NULL && req->oldptr == NULL) 11297 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 11298 sizeof(sc->tt.tls_rx_ports[0]))); 11299 11300 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 11301 if (rc) 11302 return (rc); 11303 11304 if (hw_off_limits(sc)) { 11305 rc = ENXIO; 11306 goto done; 11307 } 11308 11309 if (sc->tt.num_tls_rx_ports == 0) { 11310 i = -1; 11311 rc = SYSCTL_OUT(req, &i, sizeof(i)); 11312 } else 11313 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 11314 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 11315 if (rc == 0 && req->newptr != NULL) { 11316 new_count = req->newlen / sizeof(new_ports[0]); 11317 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 11318 M_WAITOK); 11319 rc = SYSCTL_IN(req, new_ports, new_count * 11320 sizeof(new_ports[0])); 11321 if (rc) 11322 goto err; 11323 11324 /* Allow setting to a single '-1' to clear the list. */ 11325 if (new_count == 1 && new_ports[0] == -1) { 11326 ADAPTER_LOCK(sc); 11327 old_ports = sc->tt.tls_rx_ports; 11328 sc->tt.tls_rx_ports = NULL; 11329 sc->tt.num_tls_rx_ports = 0; 11330 ADAPTER_UNLOCK(sc); 11331 free(old_ports, M_CXGBE); 11332 } else { 11333 for (i = 0; i < new_count; i++) { 11334 if (new_ports[i] < 1 || 11335 new_ports[i] > IPPORT_MAX) { 11336 rc = EINVAL; 11337 goto err; 11338 } 11339 } 11340 11341 ADAPTER_LOCK(sc); 11342 old_ports = sc->tt.tls_rx_ports; 11343 sc->tt.tls_rx_ports = new_ports; 11344 sc->tt.num_tls_rx_ports = new_count; 11345 ADAPTER_UNLOCK(sc); 11346 free(old_ports, M_CXGBE); 11347 new_ports = NULL; 11348 } 11349 err: 11350 free(new_ports, M_CXGBE); 11351 } 11352 done: 11353 end_synchronized_op(sc, 0); 11354 return (rc); 11355 } 11356 11357 static int 11358 sysctl_tls_rx_timeout(SYSCTL_HANDLER_ARGS) 11359 { 11360 struct adapter *sc = arg1; 11361 int v, rc; 11362 11363 v = sc->tt.tls_rx_timeout; 11364 rc = sysctl_handle_int(oidp, &v, 0, req); 11365 if (rc != 0 || req->newptr == NULL) 11366 return (rc); 11367 11368 if (v < 0) 11369 return (EINVAL); 11370 11371 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 11372 return (ENOTSUP); 11373 11374 sc->tt.tls_rx_timeout = v; 11375 11376 return (0); 11377 11378 } 11379 11380 static void 11381 unit_conv(char *buf, size_t len, u_int val, u_int factor) 11382 { 11383 u_int rem = val % factor; 11384 11385 if (rem == 0) 11386 snprintf(buf, len, "%u", val / factor); 11387 else { 11388 while (rem % 10 == 0) 11389 rem /= 10; 11390 snprintf(buf, len, "%u.%u", val / factor, rem); 11391 } 11392 } 11393 11394 static int 11395 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 11396 { 11397 struct adapter *sc = arg1; 11398 char buf[16]; 11399 u_int res, re; 11400 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11401 11402 mtx_lock(&sc->reg_lock); 11403 if (hw_off_limits(sc)) 11404 res = (u_int)-1; 11405 else 11406 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 11407 mtx_unlock(&sc->reg_lock); 11408 if (res == (u_int)-1) 11409 return (ENXIO); 11410 11411 switch (arg2) { 11412 case 0: 11413 /* timer_tick */ 11414 re = G_TIMERRESOLUTION(res); 11415 break; 11416 case 1: 11417 /* TCP timestamp tick */ 11418 re = G_TIMESTAMPRESOLUTION(res); 11419 break; 11420 case 2: 11421 /* DACK tick */ 11422 re = G_DELAYEDACKRESOLUTION(res); 11423 break; 11424 default: 11425 return (EDOOFUS); 11426 } 11427 11428 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 11429 11430 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 11431 } 11432 11433 static int 11434 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 11435 { 11436 struct adapter *sc = arg1; 11437 int rc; 11438 u_int dack_tmr, dack_re, v; 11439 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11440 11441 mtx_lock(&sc->reg_lock); 11442 if (hw_off_limits(sc)) 11443 rc = ENXIO; 11444 else { 11445 rc = 0; 11446 dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc, 11447 A_TP_TIMER_RESOLUTION)); 11448 dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER); 11449 } 11450 mtx_unlock(&sc->reg_lock); 11451 if (rc != 0) 11452 return (rc); 11453 11454 v = ((cclk_ps << dack_re) / 1000000) * dack_tmr; 11455 11456 return (sysctl_handle_int(oidp, &v, 0, req)); 11457 } 11458 11459 static int 11460 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 11461 { 11462 struct adapter *sc = arg1; 11463 int rc, reg = arg2; 11464 u_int tre; 11465 u_long tp_tick_us, v; 11466 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11467 11468 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 11469 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 11470 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 11471 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 11472 11473 mtx_lock(&sc->reg_lock); 11474 if (hw_off_limits(sc)) 11475 rc = ENXIO; 11476 else { 11477 rc = 0; 11478 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 11479 tp_tick_us = (cclk_ps << tre) / 1000000; 11480 if (reg == A_TP_INIT_SRTT) 11481 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 11482 else 11483 v = tp_tick_us * t4_read_reg(sc, reg); 11484 } 11485 mtx_unlock(&sc->reg_lock); 11486 if (rc != 0) 11487 return (rc); 11488 else 11489 return (sysctl_handle_long(oidp, &v, 0, req)); 11490 } 11491 11492 /* 11493 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 11494 * passed to this function. 11495 */ 11496 static int 11497 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 11498 { 11499 struct adapter *sc = arg1; 11500 int rc, idx = arg2; 11501 u_int v; 11502 11503 MPASS(idx >= 0 && idx <= 24); 11504 11505 mtx_lock(&sc->reg_lock); 11506 if (hw_off_limits(sc)) 11507 rc = ENXIO; 11508 else { 11509 rc = 0; 11510 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 11511 } 11512 mtx_unlock(&sc->reg_lock); 11513 if (rc != 0) 11514 return (rc); 11515 else 11516 return (sysctl_handle_int(oidp, &v, 0, req)); 11517 } 11518 11519 static int 11520 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 11521 { 11522 struct adapter *sc = arg1; 11523 int rc, idx = arg2; 11524 u_int shift, v, r; 11525 11526 MPASS(idx >= 0 && idx < 16); 11527 11528 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 11529 shift = (idx & 3) << 3; 11530 mtx_lock(&sc->reg_lock); 11531 if (hw_off_limits(sc)) 11532 rc = ENXIO; 11533 else { 11534 rc = 0; 11535 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 11536 } 11537 mtx_unlock(&sc->reg_lock); 11538 if (rc != 0) 11539 return (rc); 11540 else 11541 return (sysctl_handle_int(oidp, &v, 0, req)); 11542 } 11543 11544 static int 11545 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 11546 { 11547 struct vi_info *vi = arg1; 11548 struct adapter *sc = vi->adapter; 11549 int idx, rc, i; 11550 struct sge_ofld_rxq *ofld_rxq; 11551 uint8_t v; 11552 11553 idx = vi->ofld_tmr_idx; 11554 11555 rc = sysctl_handle_int(oidp, &idx, 0, req); 11556 if (rc != 0 || req->newptr == NULL) 11557 return (rc); 11558 11559 if (idx < 0 || idx >= SGE_NTIMERS) 11560 return (EINVAL); 11561 11562 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11563 "t4otmr"); 11564 if (rc) 11565 return (rc); 11566 11567 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 11568 for_each_ofld_rxq(vi, i, ofld_rxq) { 11569 #ifdef atomic_store_rel_8 11570 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 11571 #else 11572 ofld_rxq->iq.intr_params = v; 11573 #endif 11574 } 11575 vi->ofld_tmr_idx = idx; 11576 11577 end_synchronized_op(sc, LOCK_HELD); 11578 return (0); 11579 } 11580 11581 static int 11582 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 11583 { 11584 struct vi_info *vi = arg1; 11585 struct adapter *sc = vi->adapter; 11586 int idx, rc; 11587 11588 idx = vi->ofld_pktc_idx; 11589 11590 rc = sysctl_handle_int(oidp, &idx, 0, req); 11591 if (rc != 0 || req->newptr == NULL) 11592 return (rc); 11593 11594 if (idx < -1 || idx >= SGE_NCOUNTERS) 11595 return (EINVAL); 11596 11597 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11598 "t4opktc"); 11599 if (rc) 11600 return (rc); 11601 11602 if (vi->flags & VI_INIT_DONE) 11603 rc = EBUSY; /* cannot be changed once the queues are created */ 11604 else 11605 vi->ofld_pktc_idx = idx; 11606 11607 end_synchronized_op(sc, LOCK_HELD); 11608 return (rc); 11609 } 11610 #endif 11611 11612 static int 11613 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 11614 { 11615 int rc; 11616 11617 if (cntxt->cid > M_CTXTQID) 11618 return (EINVAL); 11619 11620 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 11621 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 11622 return (EINVAL); 11623 11624 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 11625 if (rc) 11626 return (rc); 11627 11628 if (hw_off_limits(sc)) { 11629 rc = ENXIO; 11630 goto done; 11631 } 11632 11633 if (sc->flags & FW_OK) { 11634 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 11635 &cntxt->data[0]); 11636 if (rc == 0) 11637 goto done; 11638 } 11639 11640 /* 11641 * Read via firmware failed or wasn't even attempted. Read directly via 11642 * the backdoor. 11643 */ 11644 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 11645 done: 11646 end_synchronized_op(sc, 0); 11647 return (rc); 11648 } 11649 11650 static int 11651 load_fw(struct adapter *sc, struct t4_data *fw) 11652 { 11653 int rc; 11654 uint8_t *fw_data; 11655 11656 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 11657 if (rc) 11658 return (rc); 11659 11660 if (hw_off_limits(sc)) { 11661 rc = ENXIO; 11662 goto done; 11663 } 11664 11665 /* 11666 * The firmware, with the sole exception of the memory parity error 11667 * handler, runs from memory and not flash. It is almost always safe to 11668 * install a new firmware on a running system. Just set bit 1 in 11669 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 11670 */ 11671 if (sc->flags & FULL_INIT_DONE && 11672 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 11673 rc = EBUSY; 11674 goto done; 11675 } 11676 11677 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 11678 11679 rc = copyin(fw->data, fw_data, fw->len); 11680 if (rc == 0) 11681 rc = -t4_load_fw(sc, fw_data, fw->len); 11682 11683 free(fw_data, M_CXGBE); 11684 done: 11685 end_synchronized_op(sc, 0); 11686 return (rc); 11687 } 11688 11689 static int 11690 load_cfg(struct adapter *sc, struct t4_data *cfg) 11691 { 11692 int rc; 11693 uint8_t *cfg_data = NULL; 11694 11695 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11696 if (rc) 11697 return (rc); 11698 11699 if (hw_off_limits(sc)) { 11700 rc = ENXIO; 11701 goto done; 11702 } 11703 11704 if (cfg->len == 0) { 11705 /* clear */ 11706 rc = -t4_load_cfg(sc, NULL, 0); 11707 goto done; 11708 } 11709 11710 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 11711 11712 rc = copyin(cfg->data, cfg_data, cfg->len); 11713 if (rc == 0) 11714 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 11715 11716 free(cfg_data, M_CXGBE); 11717 done: 11718 end_synchronized_op(sc, 0); 11719 return (rc); 11720 } 11721 11722 static int 11723 load_boot(struct adapter *sc, struct t4_bootrom *br) 11724 { 11725 int rc; 11726 uint8_t *br_data = NULL; 11727 u_int offset; 11728 11729 if (br->len > 1024 * 1024) 11730 return (EFBIG); 11731 11732 if (br->pf_offset == 0) { 11733 /* pfidx */ 11734 if (br->pfidx_addr > 7) 11735 return (EINVAL); 11736 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 11737 A_PCIE_PF_EXPROM_OFST))); 11738 } else if (br->pf_offset == 1) { 11739 /* offset */ 11740 offset = G_OFFSET(br->pfidx_addr); 11741 } else { 11742 return (EINVAL); 11743 } 11744 11745 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 11746 if (rc) 11747 return (rc); 11748 11749 if (hw_off_limits(sc)) { 11750 rc = ENXIO; 11751 goto done; 11752 } 11753 11754 if (br->len == 0) { 11755 /* clear */ 11756 rc = -t4_load_boot(sc, NULL, offset, 0); 11757 goto done; 11758 } 11759 11760 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 11761 11762 rc = copyin(br->data, br_data, br->len); 11763 if (rc == 0) 11764 rc = -t4_load_boot(sc, br_data, offset, br->len); 11765 11766 free(br_data, M_CXGBE); 11767 done: 11768 end_synchronized_op(sc, 0); 11769 return (rc); 11770 } 11771 11772 static int 11773 load_bootcfg(struct adapter *sc, struct t4_data *bc) 11774 { 11775 int rc; 11776 uint8_t *bc_data = NULL; 11777 11778 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11779 if (rc) 11780 return (rc); 11781 11782 if (hw_off_limits(sc)) { 11783 rc = ENXIO; 11784 goto done; 11785 } 11786 11787 if (bc->len == 0) { 11788 /* clear */ 11789 rc = -t4_load_bootcfg(sc, NULL, 0); 11790 goto done; 11791 } 11792 11793 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 11794 11795 rc = copyin(bc->data, bc_data, bc->len); 11796 if (rc == 0) 11797 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 11798 11799 free(bc_data, M_CXGBE); 11800 done: 11801 end_synchronized_op(sc, 0); 11802 return (rc); 11803 } 11804 11805 static int 11806 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 11807 { 11808 int rc; 11809 struct cudbg_init *cudbg; 11810 void *handle, *buf; 11811 11812 /* buf is large, don't block if no memory is available */ 11813 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 11814 if (buf == NULL) 11815 return (ENOMEM); 11816 11817 handle = cudbg_alloc_handle(); 11818 if (handle == NULL) { 11819 rc = ENOMEM; 11820 goto done; 11821 } 11822 11823 cudbg = cudbg_get_init(handle); 11824 cudbg->adap = sc; 11825 cudbg->print = (cudbg_print_cb)printf; 11826 11827 #ifndef notyet 11828 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 11829 __func__, dump->wr_flash, dump->len, dump->data); 11830 #endif 11831 11832 if (dump->wr_flash) 11833 cudbg->use_flash = 1; 11834 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 11835 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 11836 11837 rc = cudbg_collect(handle, buf, &dump->len); 11838 if (rc != 0) 11839 goto done; 11840 11841 rc = copyout(buf, dump->data, dump->len); 11842 done: 11843 cudbg_free_handle(handle); 11844 free(buf, M_CXGBE); 11845 return (rc); 11846 } 11847 11848 static void 11849 free_offload_policy(struct t4_offload_policy *op) 11850 { 11851 struct offload_rule *r; 11852 int i; 11853 11854 if (op == NULL) 11855 return; 11856 11857 r = &op->rule[0]; 11858 for (i = 0; i < op->nrules; i++, r++) { 11859 free(r->bpf_prog.bf_insns, M_CXGBE); 11860 } 11861 free(op->rule, M_CXGBE); 11862 free(op, M_CXGBE); 11863 } 11864 11865 static int 11866 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 11867 { 11868 int i, rc, len; 11869 struct t4_offload_policy *op, *old; 11870 struct bpf_program *bf; 11871 const struct offload_settings *s; 11872 struct offload_rule *r; 11873 void *u; 11874 11875 if (!is_offload(sc)) 11876 return (ENODEV); 11877 11878 if (uop->nrules == 0) { 11879 /* Delete installed policies. */ 11880 op = NULL; 11881 goto set_policy; 11882 } else if (uop->nrules > 256) { /* arbitrary */ 11883 return (E2BIG); 11884 } 11885 11886 /* Copy userspace offload policy to kernel */ 11887 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 11888 op->nrules = uop->nrules; 11889 len = op->nrules * sizeof(struct offload_rule); 11890 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11891 rc = copyin(uop->rule, op->rule, len); 11892 if (rc) { 11893 free(op->rule, M_CXGBE); 11894 free(op, M_CXGBE); 11895 return (rc); 11896 } 11897 11898 r = &op->rule[0]; 11899 for (i = 0; i < op->nrules; i++, r++) { 11900 11901 /* Validate open_type */ 11902 if (r->open_type != OPEN_TYPE_LISTEN && 11903 r->open_type != OPEN_TYPE_ACTIVE && 11904 r->open_type != OPEN_TYPE_PASSIVE && 11905 r->open_type != OPEN_TYPE_DONTCARE) { 11906 error: 11907 /* 11908 * Rules 0 to i have malloc'd filters that need to be 11909 * freed. Rules i+1 to nrules have userspace pointers 11910 * and should be left alone. 11911 */ 11912 op->nrules = i; 11913 free_offload_policy(op); 11914 return (rc); 11915 } 11916 11917 /* Validate settings */ 11918 s = &r->settings; 11919 if ((s->offload != 0 && s->offload != 1) || 11920 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 11921 s->sched_class < -1 || 11922 s->sched_class >= sc->params.nsched_cls) { 11923 rc = EINVAL; 11924 goto error; 11925 } 11926 11927 bf = &r->bpf_prog; 11928 u = bf->bf_insns; /* userspace ptr */ 11929 bf->bf_insns = NULL; 11930 if (bf->bf_len == 0) { 11931 /* legal, matches everything */ 11932 continue; 11933 } 11934 len = bf->bf_len * sizeof(*bf->bf_insns); 11935 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11936 rc = copyin(u, bf->bf_insns, len); 11937 if (rc != 0) 11938 goto error; 11939 11940 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 11941 rc = EINVAL; 11942 goto error; 11943 } 11944 } 11945 set_policy: 11946 rw_wlock(&sc->policy_lock); 11947 old = sc->policy; 11948 sc->policy = op; 11949 rw_wunlock(&sc->policy_lock); 11950 free_offload_policy(old); 11951 11952 return (0); 11953 } 11954 11955 #define MAX_READ_BUF_SIZE (128 * 1024) 11956 static int 11957 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 11958 { 11959 uint32_t addr, remaining, n; 11960 uint32_t *buf; 11961 int rc; 11962 uint8_t *dst; 11963 11964 mtx_lock(&sc->reg_lock); 11965 if (hw_off_limits(sc)) 11966 rc = ENXIO; 11967 else 11968 rc = validate_mem_range(sc, mr->addr, mr->len); 11969 mtx_unlock(&sc->reg_lock); 11970 if (rc != 0) 11971 return (rc); 11972 11973 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 11974 addr = mr->addr; 11975 remaining = mr->len; 11976 dst = (void *)mr->data; 11977 11978 while (remaining) { 11979 n = min(remaining, MAX_READ_BUF_SIZE); 11980 mtx_lock(&sc->reg_lock); 11981 if (hw_off_limits(sc)) 11982 rc = ENXIO; 11983 else 11984 read_via_memwin(sc, 2, addr, buf, n); 11985 mtx_unlock(&sc->reg_lock); 11986 if (rc != 0) 11987 break; 11988 11989 rc = copyout(buf, dst, n); 11990 if (rc != 0) 11991 break; 11992 11993 dst += n; 11994 remaining -= n; 11995 addr += n; 11996 } 11997 11998 free(buf, M_CXGBE); 11999 return (rc); 12000 } 12001 #undef MAX_READ_BUF_SIZE 12002 12003 static int 12004 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 12005 { 12006 int rc; 12007 12008 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 12009 return (EINVAL); 12010 12011 if (i2cd->len > sizeof(i2cd->data)) 12012 return (EFBIG); 12013 12014 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 12015 if (rc) 12016 return (rc); 12017 if (hw_off_limits(sc)) 12018 rc = ENXIO; 12019 else 12020 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 12021 i2cd->offset, i2cd->len, &i2cd->data[0]); 12022 end_synchronized_op(sc, 0); 12023 12024 return (rc); 12025 } 12026 12027 static int 12028 clear_stats(struct adapter *sc, u_int port_id) 12029 { 12030 int i, v, chan_map; 12031 struct port_info *pi; 12032 struct vi_info *vi; 12033 struct sge_rxq *rxq; 12034 struct sge_txq *txq; 12035 struct sge_wrq *wrq; 12036 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12037 struct sge_ofld_txq *ofld_txq; 12038 #endif 12039 #ifdef TCP_OFFLOAD 12040 struct sge_ofld_rxq *ofld_rxq; 12041 #endif 12042 12043 if (port_id >= sc->params.nports) 12044 return (EINVAL); 12045 pi = sc->port[port_id]; 12046 if (pi == NULL) 12047 return (EIO); 12048 12049 mtx_lock(&sc->reg_lock); 12050 if (!hw_off_limits(sc)) { 12051 /* MAC stats */ 12052 t4_clr_port_stats(sc, pi->tx_chan); 12053 if (is_t6(sc)) { 12054 if (pi->fcs_reg != -1) 12055 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 12056 else 12057 pi->stats.rx_fcs_err = 0; 12058 } 12059 for_each_vi(pi, v, vi) { 12060 if (vi->flags & VI_INIT_DONE) 12061 t4_clr_vi_stats(sc, vi->vin); 12062 } 12063 chan_map = pi->rx_e_chan_map; 12064 v = 0; /* reuse */ 12065 while (chan_map) { 12066 i = ffs(chan_map) - 1; 12067 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 12068 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 12069 chan_map &= ~(1 << i); 12070 } 12071 } 12072 mtx_unlock(&sc->reg_lock); 12073 pi->tx_parse_error = 0; 12074 pi->tnl_cong_drops = 0; 12075 12076 /* 12077 * Since this command accepts a port, clear stats for 12078 * all VIs on this port. 12079 */ 12080 for_each_vi(pi, v, vi) { 12081 if (vi->flags & VI_INIT_DONE) { 12082 12083 for_each_rxq(vi, i, rxq) { 12084 #if defined(INET) || defined(INET6) 12085 rxq->lro.lro_queued = 0; 12086 rxq->lro.lro_flushed = 0; 12087 #endif 12088 rxq->rxcsum = 0; 12089 rxq->vlan_extraction = 0; 12090 rxq->vxlan_rxcsum = 0; 12091 12092 rxq->fl.cl_allocated = 0; 12093 rxq->fl.cl_recycled = 0; 12094 rxq->fl.cl_fast_recycled = 0; 12095 } 12096 12097 for_each_txq(vi, i, txq) { 12098 txq->txcsum = 0; 12099 txq->tso_wrs = 0; 12100 txq->vlan_insertion = 0; 12101 txq->imm_wrs = 0; 12102 txq->sgl_wrs = 0; 12103 txq->txpkt_wrs = 0; 12104 txq->txpkts0_wrs = 0; 12105 txq->txpkts1_wrs = 0; 12106 txq->txpkts0_pkts = 0; 12107 txq->txpkts1_pkts = 0; 12108 txq->txpkts_flush = 0; 12109 txq->raw_wrs = 0; 12110 txq->vxlan_tso_wrs = 0; 12111 txq->vxlan_txcsum = 0; 12112 txq->kern_tls_records = 0; 12113 txq->kern_tls_short = 0; 12114 txq->kern_tls_partial = 0; 12115 txq->kern_tls_full = 0; 12116 txq->kern_tls_octets = 0; 12117 txq->kern_tls_waste = 0; 12118 txq->kern_tls_options = 0; 12119 txq->kern_tls_header = 0; 12120 txq->kern_tls_fin = 0; 12121 txq->kern_tls_fin_short = 0; 12122 txq->kern_tls_cbc = 0; 12123 txq->kern_tls_gcm = 0; 12124 mp_ring_reset_stats(txq->r); 12125 } 12126 12127 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12128 for_each_ofld_txq(vi, i, ofld_txq) { 12129 ofld_txq->wrq.tx_wrs_direct = 0; 12130 ofld_txq->wrq.tx_wrs_copied = 0; 12131 counter_u64_zero(ofld_txq->tx_iscsi_pdus); 12132 counter_u64_zero(ofld_txq->tx_iscsi_octets); 12133 counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs); 12134 counter_u64_zero(ofld_txq->tx_toe_tls_records); 12135 counter_u64_zero(ofld_txq->tx_toe_tls_octets); 12136 } 12137 #endif 12138 #ifdef TCP_OFFLOAD 12139 for_each_ofld_rxq(vi, i, ofld_rxq) { 12140 ofld_rxq->fl.cl_allocated = 0; 12141 ofld_rxq->fl.cl_recycled = 0; 12142 ofld_rxq->fl.cl_fast_recycled = 0; 12143 counter_u64_zero( 12144 ofld_rxq->rx_iscsi_ddp_setup_ok); 12145 counter_u64_zero( 12146 ofld_rxq->rx_iscsi_ddp_setup_error); 12147 ofld_rxq->rx_iscsi_ddp_pdus = 0; 12148 ofld_rxq->rx_iscsi_ddp_octets = 0; 12149 ofld_rxq->rx_iscsi_fl_pdus = 0; 12150 ofld_rxq->rx_iscsi_fl_octets = 0; 12151 ofld_rxq->rx_toe_tls_records = 0; 12152 ofld_rxq->rx_toe_tls_octets = 0; 12153 } 12154 #endif 12155 12156 if (IS_MAIN_VI(vi)) { 12157 wrq = &sc->sge.ctrlq[pi->port_id]; 12158 wrq->tx_wrs_direct = 0; 12159 wrq->tx_wrs_copied = 0; 12160 } 12161 } 12162 } 12163 12164 return (0); 12165 } 12166 12167 static int 12168 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12169 { 12170 #ifdef INET6 12171 struct in6_addr in6; 12172 12173 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12174 if (t4_get_clip_entry(sc, &in6, true) != NULL) 12175 return (0); 12176 else 12177 return (EIO); 12178 #else 12179 return (ENOTSUP); 12180 #endif 12181 } 12182 12183 static int 12184 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12185 { 12186 #ifdef INET6 12187 struct in6_addr in6; 12188 12189 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12190 return (t4_release_clip_addr(sc, &in6)); 12191 #else 12192 return (ENOTSUP); 12193 #endif 12194 } 12195 12196 int 12197 t4_os_find_pci_capability(struct adapter *sc, int cap) 12198 { 12199 int i; 12200 12201 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 12202 } 12203 12204 int 12205 t4_os_pci_save_state(struct adapter *sc) 12206 { 12207 device_t dev; 12208 struct pci_devinfo *dinfo; 12209 12210 dev = sc->dev; 12211 dinfo = device_get_ivars(dev); 12212 12213 pci_cfg_save(dev, dinfo, 0); 12214 return (0); 12215 } 12216 12217 int 12218 t4_os_pci_restore_state(struct adapter *sc) 12219 { 12220 device_t dev; 12221 struct pci_devinfo *dinfo; 12222 12223 dev = sc->dev; 12224 dinfo = device_get_ivars(dev); 12225 12226 pci_cfg_restore(dev, dinfo); 12227 return (0); 12228 } 12229 12230 void 12231 t4_os_portmod_changed(struct port_info *pi) 12232 { 12233 struct adapter *sc = pi->adapter; 12234 struct vi_info *vi; 12235 struct ifnet *ifp; 12236 static const char *mod_str[] = { 12237 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 12238 }; 12239 12240 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 12241 ("%s: port_type %u", __func__, pi->port_type)); 12242 12243 vi = &pi->vi[0]; 12244 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 12245 PORT_LOCK(pi); 12246 build_medialist(pi); 12247 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 12248 fixup_link_config(pi); 12249 apply_link_config(pi); 12250 } 12251 PORT_UNLOCK(pi); 12252 end_synchronized_op(sc, LOCK_HELD); 12253 } 12254 12255 ifp = vi->ifp; 12256 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 12257 if_printf(ifp, "transceiver unplugged.\n"); 12258 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 12259 if_printf(ifp, "unknown transceiver inserted.\n"); 12260 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 12261 if_printf(ifp, "unsupported transceiver inserted.\n"); 12262 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 12263 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 12264 port_top_speed(pi), mod_str[pi->mod_type]); 12265 } else { 12266 if_printf(ifp, "transceiver (type %d) inserted.\n", 12267 pi->mod_type); 12268 } 12269 } 12270 12271 void 12272 t4_os_link_changed(struct port_info *pi) 12273 { 12274 struct vi_info *vi; 12275 struct ifnet *ifp; 12276 struct link_config *lc = &pi->link_cfg; 12277 struct adapter *sc = pi->adapter; 12278 int v; 12279 12280 PORT_LOCK_ASSERT_OWNED(pi); 12281 12282 if (is_t6(sc)) { 12283 if (lc->link_ok) { 12284 if (lc->speed > 25000 || 12285 (lc->speed == 25000 && lc->fec == FEC_RS)) { 12286 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12287 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS); 12288 } else { 12289 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12290 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS); 12291 } 12292 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 12293 pi->stats.rx_fcs_err = 0; 12294 } else { 12295 pi->fcs_reg = -1; 12296 } 12297 } else { 12298 MPASS(pi->fcs_reg != -1); 12299 MPASS(pi->fcs_base == 0); 12300 } 12301 12302 for_each_vi(pi, v, vi) { 12303 ifp = vi->ifp; 12304 if (ifp == NULL) 12305 continue; 12306 12307 if (lc->link_ok) { 12308 ifp->if_baudrate = IF_Mbps(lc->speed); 12309 if_link_state_change(ifp, LINK_STATE_UP); 12310 } else { 12311 if_link_state_change(ifp, LINK_STATE_DOWN); 12312 } 12313 } 12314 } 12315 12316 void 12317 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 12318 { 12319 struct adapter *sc; 12320 12321 sx_slock(&t4_list_lock); 12322 SLIST_FOREACH(sc, &t4_list, link) { 12323 /* 12324 * func should not make any assumptions about what state sc is 12325 * in - the only guarantee is that sc->sc_lock is a valid lock. 12326 */ 12327 func(sc, arg); 12328 } 12329 sx_sunlock(&t4_list_lock); 12330 } 12331 12332 static int 12333 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 12334 struct thread *td) 12335 { 12336 int rc; 12337 struct adapter *sc = dev->si_drv1; 12338 12339 rc = priv_check(td, PRIV_DRIVER); 12340 if (rc != 0) 12341 return (rc); 12342 12343 switch (cmd) { 12344 case CHELSIO_T4_GETREG: { 12345 struct t4_reg *edata = (struct t4_reg *)data; 12346 12347 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12348 return (EFAULT); 12349 12350 mtx_lock(&sc->reg_lock); 12351 if (hw_off_limits(sc)) 12352 rc = ENXIO; 12353 else if (edata->size == 4) 12354 edata->val = t4_read_reg(sc, edata->addr); 12355 else if (edata->size == 8) 12356 edata->val = t4_read_reg64(sc, edata->addr); 12357 else 12358 rc = EINVAL; 12359 mtx_unlock(&sc->reg_lock); 12360 12361 break; 12362 } 12363 case CHELSIO_T4_SETREG: { 12364 struct t4_reg *edata = (struct t4_reg *)data; 12365 12366 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12367 return (EFAULT); 12368 12369 mtx_lock(&sc->reg_lock); 12370 if (hw_off_limits(sc)) 12371 rc = ENXIO; 12372 else if (edata->size == 4) { 12373 if (edata->val & 0xffffffff00000000) 12374 rc = EINVAL; 12375 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 12376 } else if (edata->size == 8) 12377 t4_write_reg64(sc, edata->addr, edata->val); 12378 else 12379 rc = EINVAL; 12380 mtx_unlock(&sc->reg_lock); 12381 12382 break; 12383 } 12384 case CHELSIO_T4_REGDUMP: { 12385 struct t4_regdump *regs = (struct t4_regdump *)data; 12386 int reglen = t4_get_regs_len(sc); 12387 uint8_t *buf; 12388 12389 if (regs->len < reglen) { 12390 regs->len = reglen; /* hint to the caller */ 12391 return (ENOBUFS); 12392 } 12393 12394 regs->len = reglen; 12395 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 12396 mtx_lock(&sc->reg_lock); 12397 if (hw_off_limits(sc)) 12398 rc = ENXIO; 12399 else 12400 get_regs(sc, regs, buf); 12401 mtx_unlock(&sc->reg_lock); 12402 if (rc == 0) 12403 rc = copyout(buf, regs->data, reglen); 12404 free(buf, M_CXGBE); 12405 break; 12406 } 12407 case CHELSIO_T4_GET_FILTER_MODE: 12408 rc = get_filter_mode(sc, (uint32_t *)data); 12409 break; 12410 case CHELSIO_T4_SET_FILTER_MODE: 12411 rc = set_filter_mode(sc, *(uint32_t *)data); 12412 break; 12413 case CHELSIO_T4_SET_FILTER_MASK: 12414 rc = set_filter_mask(sc, *(uint32_t *)data); 12415 break; 12416 case CHELSIO_T4_GET_FILTER: 12417 rc = get_filter(sc, (struct t4_filter *)data); 12418 break; 12419 case CHELSIO_T4_SET_FILTER: 12420 rc = set_filter(sc, (struct t4_filter *)data); 12421 break; 12422 case CHELSIO_T4_DEL_FILTER: 12423 rc = del_filter(sc, (struct t4_filter *)data); 12424 break; 12425 case CHELSIO_T4_GET_SGE_CONTEXT: 12426 rc = get_sge_context(sc, (struct t4_sge_context *)data); 12427 break; 12428 case CHELSIO_T4_LOAD_FW: 12429 rc = load_fw(sc, (struct t4_data *)data); 12430 break; 12431 case CHELSIO_T4_GET_MEM: 12432 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 12433 break; 12434 case CHELSIO_T4_GET_I2C: 12435 rc = read_i2c(sc, (struct t4_i2c_data *)data); 12436 break; 12437 case CHELSIO_T4_CLEAR_STATS: 12438 rc = clear_stats(sc, *(uint32_t *)data); 12439 break; 12440 case CHELSIO_T4_SCHED_CLASS: 12441 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 12442 break; 12443 case CHELSIO_T4_SCHED_QUEUE: 12444 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 12445 break; 12446 case CHELSIO_T4_GET_TRACER: 12447 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 12448 break; 12449 case CHELSIO_T4_SET_TRACER: 12450 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 12451 break; 12452 case CHELSIO_T4_LOAD_CFG: 12453 rc = load_cfg(sc, (struct t4_data *)data); 12454 break; 12455 case CHELSIO_T4_LOAD_BOOT: 12456 rc = load_boot(sc, (struct t4_bootrom *)data); 12457 break; 12458 case CHELSIO_T4_LOAD_BOOTCFG: 12459 rc = load_bootcfg(sc, (struct t4_data *)data); 12460 break; 12461 case CHELSIO_T4_CUDBG_DUMP: 12462 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 12463 break; 12464 case CHELSIO_T4_SET_OFLD_POLICY: 12465 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 12466 break; 12467 case CHELSIO_T4_HOLD_CLIP_ADDR: 12468 rc = hold_clip_addr(sc, (struct t4_clip_addr *)data); 12469 break; 12470 case CHELSIO_T4_RELEASE_CLIP_ADDR: 12471 rc = release_clip_addr(sc, (struct t4_clip_addr *)data); 12472 break; 12473 default: 12474 rc = ENOTTY; 12475 } 12476 12477 return (rc); 12478 } 12479 12480 #ifdef TCP_OFFLOAD 12481 static int 12482 toe_capability(struct vi_info *vi, bool enable) 12483 { 12484 int rc; 12485 struct port_info *pi = vi->pi; 12486 struct adapter *sc = pi->adapter; 12487 12488 ASSERT_SYNCHRONIZED_OP(sc); 12489 12490 if (!is_offload(sc)) 12491 return (ENODEV); 12492 if (hw_off_limits(sc)) 12493 return (ENXIO); 12494 12495 if (enable) { 12496 #ifdef KERN_TLS 12497 if (sc->flags & KERN_TLS_ON && is_t6(sc)) { 12498 int i, j, n; 12499 struct port_info *p; 12500 struct vi_info *v; 12501 12502 /* 12503 * Reconfigure hardware for TOE if TXTLS is not enabled 12504 * on any ifnet. 12505 */ 12506 n = 0; 12507 for_each_port(sc, i) { 12508 p = sc->port[i]; 12509 for_each_vi(p, j, v) { 12510 if (v->ifp->if_capenable & IFCAP_TXTLS) { 12511 CH_WARN(sc, 12512 "%s has NIC TLS enabled.\n", 12513 device_get_nameunit(v->dev)); 12514 n++; 12515 } 12516 } 12517 } 12518 if (n > 0) { 12519 CH_WARN(sc, "Disable NIC TLS on all interfaces " 12520 "associated with this adapter before " 12521 "trying to enable TOE.\n"); 12522 return (EAGAIN); 12523 } 12524 rc = t6_config_kern_tls(sc, false); 12525 if (rc) 12526 return (rc); 12527 } 12528 #endif 12529 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 12530 /* TOE is already enabled. */ 12531 return (0); 12532 } 12533 12534 /* 12535 * We need the port's queues around so that we're able to send 12536 * and receive CPLs to/from the TOE even if the ifnet for this 12537 * port has never been UP'd administratively. 12538 */ 12539 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 12540 return (rc); 12541 if (!(pi->vi[0].flags & VI_INIT_DONE) && 12542 ((rc = vi_init(&pi->vi[0])) != 0)) 12543 return (rc); 12544 12545 if (isset(&sc->offload_map, pi->port_id)) { 12546 /* TOE is enabled on another VI of this port. */ 12547 pi->uld_vis++; 12548 return (0); 12549 } 12550 12551 if (!uld_active(sc, ULD_TOM)) { 12552 rc = t4_activate_uld(sc, ULD_TOM); 12553 if (rc == EAGAIN) { 12554 log(LOG_WARNING, 12555 "You must kldload t4_tom.ko before trying " 12556 "to enable TOE on a cxgbe interface.\n"); 12557 } 12558 if (rc != 0) 12559 return (rc); 12560 KASSERT(sc->tom_softc != NULL, 12561 ("%s: TOM activated but softc NULL", __func__)); 12562 KASSERT(uld_active(sc, ULD_TOM), 12563 ("%s: TOM activated but flag not set", __func__)); 12564 } 12565 12566 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 12567 if (!uld_active(sc, ULD_IWARP)) 12568 (void) t4_activate_uld(sc, ULD_IWARP); 12569 if (!uld_active(sc, ULD_ISCSI)) 12570 (void) t4_activate_uld(sc, ULD_ISCSI); 12571 12572 pi->uld_vis++; 12573 setbit(&sc->offload_map, pi->port_id); 12574 } else { 12575 pi->uld_vis--; 12576 12577 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 12578 return (0); 12579 12580 KASSERT(uld_active(sc, ULD_TOM), 12581 ("%s: TOM never initialized?", __func__)); 12582 clrbit(&sc->offload_map, pi->port_id); 12583 } 12584 12585 return (0); 12586 } 12587 12588 /* 12589 * Add an upper layer driver to the global list. 12590 */ 12591 int 12592 t4_register_uld(struct uld_info *ui) 12593 { 12594 int rc = 0; 12595 struct uld_info *u; 12596 12597 sx_xlock(&t4_uld_list_lock); 12598 SLIST_FOREACH(u, &t4_uld_list, link) { 12599 if (u->uld_id == ui->uld_id) { 12600 rc = EEXIST; 12601 goto done; 12602 } 12603 } 12604 12605 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 12606 ui->refcount = 0; 12607 done: 12608 sx_xunlock(&t4_uld_list_lock); 12609 return (rc); 12610 } 12611 12612 int 12613 t4_unregister_uld(struct uld_info *ui) 12614 { 12615 int rc = EINVAL; 12616 struct uld_info *u; 12617 12618 sx_xlock(&t4_uld_list_lock); 12619 12620 SLIST_FOREACH(u, &t4_uld_list, link) { 12621 if (u == ui) { 12622 if (ui->refcount > 0) { 12623 rc = EBUSY; 12624 goto done; 12625 } 12626 12627 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 12628 rc = 0; 12629 goto done; 12630 } 12631 } 12632 done: 12633 sx_xunlock(&t4_uld_list_lock); 12634 return (rc); 12635 } 12636 12637 int 12638 t4_activate_uld(struct adapter *sc, int id) 12639 { 12640 int rc; 12641 struct uld_info *ui; 12642 12643 ASSERT_SYNCHRONIZED_OP(sc); 12644 12645 if (id < 0 || id > ULD_MAX) 12646 return (EINVAL); 12647 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 12648 12649 sx_slock(&t4_uld_list_lock); 12650 12651 SLIST_FOREACH(ui, &t4_uld_list, link) { 12652 if (ui->uld_id == id) { 12653 if (!(sc->flags & FULL_INIT_DONE)) { 12654 rc = adapter_init(sc); 12655 if (rc != 0) 12656 break; 12657 } 12658 12659 rc = ui->activate(sc); 12660 if (rc == 0) { 12661 setbit(&sc->active_ulds, id); 12662 ui->refcount++; 12663 } 12664 break; 12665 } 12666 } 12667 12668 sx_sunlock(&t4_uld_list_lock); 12669 12670 return (rc); 12671 } 12672 12673 int 12674 t4_deactivate_uld(struct adapter *sc, int id) 12675 { 12676 int rc; 12677 struct uld_info *ui; 12678 12679 ASSERT_SYNCHRONIZED_OP(sc); 12680 12681 if (id < 0 || id > ULD_MAX) 12682 return (EINVAL); 12683 rc = ENXIO; 12684 12685 sx_slock(&t4_uld_list_lock); 12686 12687 SLIST_FOREACH(ui, &t4_uld_list, link) { 12688 if (ui->uld_id == id) { 12689 rc = ui->deactivate(sc); 12690 if (rc == 0) { 12691 clrbit(&sc->active_ulds, id); 12692 ui->refcount--; 12693 } 12694 break; 12695 } 12696 } 12697 12698 sx_sunlock(&t4_uld_list_lock); 12699 12700 return (rc); 12701 } 12702 12703 static int 12704 t4_deactivate_all_uld(struct adapter *sc) 12705 { 12706 int rc; 12707 struct uld_info *ui; 12708 12709 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld"); 12710 if (rc != 0) 12711 return (ENXIO); 12712 12713 sx_slock(&t4_uld_list_lock); 12714 12715 SLIST_FOREACH(ui, &t4_uld_list, link) { 12716 if (isset(&sc->active_ulds, ui->uld_id)) { 12717 rc = ui->deactivate(sc); 12718 if (rc != 0) 12719 break; 12720 clrbit(&sc->active_ulds, ui->uld_id); 12721 ui->refcount--; 12722 } 12723 } 12724 12725 sx_sunlock(&t4_uld_list_lock); 12726 end_synchronized_op(sc, 0); 12727 12728 return (rc); 12729 } 12730 12731 static void 12732 t4_async_event(struct adapter *sc) 12733 { 12734 struct uld_info *ui; 12735 12736 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4async") != 0) 12737 return; 12738 sx_slock(&t4_uld_list_lock); 12739 SLIST_FOREACH(ui, &t4_uld_list, link) { 12740 if (ui->uld_id == ULD_IWARP) { 12741 ui->async_event(sc); 12742 break; 12743 } 12744 } 12745 sx_sunlock(&t4_uld_list_lock); 12746 end_synchronized_op(sc, 0); 12747 } 12748 12749 int 12750 uld_active(struct adapter *sc, int uld_id) 12751 { 12752 12753 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 12754 12755 return (isset(&sc->active_ulds, uld_id)); 12756 } 12757 #endif 12758 12759 #ifdef KERN_TLS 12760 static int 12761 ktls_capability(struct adapter *sc, bool enable) 12762 { 12763 ASSERT_SYNCHRONIZED_OP(sc); 12764 12765 if (!is_ktls(sc)) 12766 return (ENODEV); 12767 if (!is_t6(sc)) 12768 return (0); 12769 if (hw_off_limits(sc)) 12770 return (ENXIO); 12771 12772 if (enable) { 12773 if (sc->flags & KERN_TLS_ON) 12774 return (0); /* already on */ 12775 if (sc->offload_map != 0) { 12776 CH_WARN(sc, 12777 "Disable TOE on all interfaces associated with " 12778 "this adapter before trying to enable NIC TLS.\n"); 12779 return (EAGAIN); 12780 } 12781 return (t6_config_kern_tls(sc, true)); 12782 } else { 12783 /* 12784 * Nothing to do for disable. If TOE is enabled sometime later 12785 * then toe_capability will reconfigure the hardware. 12786 */ 12787 return (0); 12788 } 12789 } 12790 #endif 12791 12792 /* 12793 * t = ptr to tunable. 12794 * nc = number of CPUs. 12795 * c = compiled in default for that tunable. 12796 */ 12797 static void 12798 calculate_nqueues(int *t, int nc, const int c) 12799 { 12800 int nq; 12801 12802 if (*t > 0) 12803 return; 12804 nq = *t < 0 ? -*t : c; 12805 *t = min(nc, nq); 12806 } 12807 12808 /* 12809 * Come up with reasonable defaults for some of the tunables, provided they're 12810 * not set by the user (in which case we'll use the values as is). 12811 */ 12812 static void 12813 tweak_tunables(void) 12814 { 12815 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 12816 12817 if (t4_ntxq < 1) { 12818 #ifdef RSS 12819 t4_ntxq = rss_getnumbuckets(); 12820 #else 12821 calculate_nqueues(&t4_ntxq, nc, NTXQ); 12822 #endif 12823 } 12824 12825 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 12826 12827 if (t4_nrxq < 1) { 12828 #ifdef RSS 12829 t4_nrxq = rss_getnumbuckets(); 12830 #else 12831 calculate_nqueues(&t4_nrxq, nc, NRXQ); 12832 #endif 12833 } 12834 12835 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 12836 12837 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12838 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 12839 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 12840 #endif 12841 #ifdef TCP_OFFLOAD 12842 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 12843 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 12844 #endif 12845 12846 #if defined(TCP_OFFLOAD) || defined(KERN_TLS) 12847 if (t4_toecaps_allowed == -1) 12848 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 12849 #else 12850 if (t4_toecaps_allowed == -1) 12851 t4_toecaps_allowed = 0; 12852 #endif 12853 12854 #ifdef TCP_OFFLOAD 12855 if (t4_rdmacaps_allowed == -1) { 12856 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 12857 FW_CAPS_CONFIG_RDMA_RDMAC; 12858 } 12859 12860 if (t4_iscsicaps_allowed == -1) { 12861 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 12862 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 12863 FW_CAPS_CONFIG_ISCSI_T10DIF; 12864 } 12865 12866 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 12867 t4_tmr_idx_ofld = TMR_IDX_OFLD; 12868 12869 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 12870 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 12871 12872 if (t4_toe_tls_rx_timeout < 0) 12873 t4_toe_tls_rx_timeout = 0; 12874 #else 12875 if (t4_rdmacaps_allowed == -1) 12876 t4_rdmacaps_allowed = 0; 12877 12878 if (t4_iscsicaps_allowed == -1) 12879 t4_iscsicaps_allowed = 0; 12880 #endif 12881 12882 #ifdef DEV_NETMAP 12883 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ); 12884 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ); 12885 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 12886 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 12887 #endif 12888 12889 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 12890 t4_tmr_idx = TMR_IDX; 12891 12892 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 12893 t4_pktc_idx = PKTC_IDX; 12894 12895 if (t4_qsize_txq < 128) 12896 t4_qsize_txq = 128; 12897 12898 if (t4_qsize_rxq < 128) 12899 t4_qsize_rxq = 128; 12900 while (t4_qsize_rxq & 7) 12901 t4_qsize_rxq++; 12902 12903 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 12904 12905 /* 12906 * Number of VIs to create per-port. The first VI is the "main" regular 12907 * VI for the port. The rest are additional virtual interfaces on the 12908 * same physical port. Note that the main VI does not have native 12909 * netmap support but the extra VIs do. 12910 * 12911 * Limit the number of VIs per port to the number of available 12912 * MAC addresses per port. 12913 */ 12914 if (t4_num_vis < 1) 12915 t4_num_vis = 1; 12916 if (t4_num_vis > nitems(vi_mac_funcs)) { 12917 t4_num_vis = nitems(vi_mac_funcs); 12918 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 12919 } 12920 12921 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 12922 pcie_relaxed_ordering = 1; 12923 #if defined(__i386__) || defined(__amd64__) 12924 if (cpu_vendor_id == CPU_VENDOR_INTEL) 12925 pcie_relaxed_ordering = 0; 12926 #endif 12927 } 12928 } 12929 12930 #ifdef DDB 12931 static void 12932 t4_dump_tcb(struct adapter *sc, int tid) 12933 { 12934 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 12935 12936 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 12937 save = t4_read_reg(sc, reg); 12938 base = sc->memwin[2].mw_base; 12939 12940 /* Dump TCB for the tid */ 12941 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 12942 tcb_addr += tid * TCB_SIZE; 12943 12944 if (is_t4(sc)) { 12945 pf = 0; 12946 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 12947 } else { 12948 pf = V_PFNUM(sc->pf); 12949 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 12950 } 12951 t4_write_reg(sc, reg, win_pos | pf); 12952 t4_read_reg(sc, reg); 12953 12954 off = tcb_addr - win_pos; 12955 for (i = 0; i < 4; i++) { 12956 uint32_t buf[8]; 12957 for (j = 0; j < 8; j++, off += 4) 12958 buf[j] = htonl(t4_read_reg(sc, base + off)); 12959 12960 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 12961 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 12962 buf[7]); 12963 } 12964 12965 t4_write_reg(sc, reg, save); 12966 t4_read_reg(sc, reg); 12967 } 12968 12969 static void 12970 t4_dump_devlog(struct adapter *sc) 12971 { 12972 struct devlog_params *dparams = &sc->params.devlog; 12973 struct fw_devlog_e e; 12974 int i, first, j, m, nentries, rc; 12975 uint64_t ftstamp = UINT64_MAX; 12976 12977 if (dparams->start == 0) { 12978 db_printf("devlog params not valid\n"); 12979 return; 12980 } 12981 12982 nentries = dparams->size / sizeof(struct fw_devlog_e); 12983 m = fwmtype_to_hwmtype(dparams->memtype); 12984 12985 /* Find the first entry. */ 12986 first = -1; 12987 for (i = 0; i < nentries && !db_pager_quit; i++) { 12988 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12989 sizeof(e), (void *)&e); 12990 if (rc != 0) 12991 break; 12992 12993 if (e.timestamp == 0) 12994 break; 12995 12996 e.timestamp = be64toh(e.timestamp); 12997 if (e.timestamp < ftstamp) { 12998 ftstamp = e.timestamp; 12999 first = i; 13000 } 13001 } 13002 13003 if (first == -1) 13004 return; 13005 13006 i = first; 13007 do { 13008 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 13009 sizeof(e), (void *)&e); 13010 if (rc != 0) 13011 return; 13012 13013 if (e.timestamp == 0) 13014 return; 13015 13016 e.timestamp = be64toh(e.timestamp); 13017 e.seqno = be32toh(e.seqno); 13018 for (j = 0; j < 8; j++) 13019 e.params[j] = be32toh(e.params[j]); 13020 13021 db_printf("%10d %15ju %8s %8s ", 13022 e.seqno, e.timestamp, 13023 (e.level < nitems(devlog_level_strings) ? 13024 devlog_level_strings[e.level] : "UNKNOWN"), 13025 (e.facility < nitems(devlog_facility_strings) ? 13026 devlog_facility_strings[e.facility] : "UNKNOWN")); 13027 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 13028 e.params[3], e.params[4], e.params[5], e.params[6], 13029 e.params[7]); 13030 13031 if (++i == nentries) 13032 i = 0; 13033 } while (i != first && !db_pager_quit); 13034 } 13035 13036 static struct db_command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 13037 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 13038 13039 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 13040 { 13041 device_t dev; 13042 int t; 13043 bool valid; 13044 13045 valid = false; 13046 t = db_read_token(); 13047 if (t == tIDENT) { 13048 dev = device_lookup_by_name(db_tok_string); 13049 valid = true; 13050 } 13051 db_skip_to_eol(); 13052 if (!valid) { 13053 db_printf("usage: show t4 devlog <nexus>\n"); 13054 return; 13055 } 13056 13057 if (dev == NULL) { 13058 db_printf("device not found\n"); 13059 return; 13060 } 13061 13062 t4_dump_devlog(device_get_softc(dev)); 13063 } 13064 13065 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 13066 { 13067 device_t dev; 13068 int radix, tid, t; 13069 bool valid; 13070 13071 valid = false; 13072 radix = db_radix; 13073 db_radix = 10; 13074 t = db_read_token(); 13075 if (t == tIDENT) { 13076 dev = device_lookup_by_name(db_tok_string); 13077 t = db_read_token(); 13078 if (t == tNUMBER) { 13079 tid = db_tok_number; 13080 valid = true; 13081 } 13082 } 13083 db_radix = radix; 13084 db_skip_to_eol(); 13085 if (!valid) { 13086 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 13087 return; 13088 } 13089 13090 if (dev == NULL) { 13091 db_printf("device not found\n"); 13092 return; 13093 } 13094 if (tid < 0) { 13095 db_printf("invalid tid\n"); 13096 return; 13097 } 13098 13099 t4_dump_tcb(device_get_softc(dev), tid); 13100 } 13101 #endif 13102 13103 static eventhandler_tag vxlan_start_evtag; 13104 static eventhandler_tag vxlan_stop_evtag; 13105 13106 struct vxlan_evargs { 13107 struct ifnet *ifp; 13108 uint16_t port; 13109 }; 13110 13111 static void 13112 enable_vxlan_rx(struct adapter *sc) 13113 { 13114 int i, rc; 13115 struct port_info *pi; 13116 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 13117 13118 ASSERT_SYNCHRONIZED_OP(sc); 13119 13120 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) | 13121 F_VXLAN_EN); 13122 for_each_port(sc, i) { 13123 pi = sc->port[i]; 13124 if (pi->vxlan_tcam_entry == true) 13125 continue; 13126 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac, 13127 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 13128 true); 13129 if (rc < 0) { 13130 rc = -rc; 13131 CH_ERR(&pi->vi[0], 13132 "failed to add VXLAN TCAM entry: %d.\n", rc); 13133 } else { 13134 MPASS(rc == sc->rawf_base + pi->port_id); 13135 pi->vxlan_tcam_entry = true; 13136 } 13137 } 13138 } 13139 13140 static void 13141 t4_vxlan_start(struct adapter *sc, void *arg) 13142 { 13143 struct vxlan_evargs *v = arg; 13144 13145 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13146 return; 13147 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0) 13148 return; 13149 13150 if (sc->vxlan_refcount == 0) { 13151 sc->vxlan_port = v->port; 13152 sc->vxlan_refcount = 1; 13153 if (!hw_off_limits(sc)) 13154 enable_vxlan_rx(sc); 13155 } else if (sc->vxlan_port == v->port) { 13156 sc->vxlan_refcount++; 13157 } else { 13158 CH_ERR(sc, "VXLAN already configured on port %d; " 13159 "ignoring attempt to configure it on port %d\n", 13160 sc->vxlan_port, v->port); 13161 } 13162 end_synchronized_op(sc, 0); 13163 } 13164 13165 static void 13166 t4_vxlan_stop(struct adapter *sc, void *arg) 13167 { 13168 struct vxlan_evargs *v = arg; 13169 13170 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13171 return; 13172 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0) 13173 return; 13174 13175 /* 13176 * VXLANs may have been configured before the driver was loaded so we 13177 * may see more stops than starts. This is not handled cleanly but at 13178 * least we keep the refcount sane. 13179 */ 13180 if (sc->vxlan_port != v->port) 13181 goto done; 13182 if (sc->vxlan_refcount == 0) { 13183 CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; " 13184 "ignoring attempt to stop it again.\n", sc->vxlan_port); 13185 } else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc)) 13186 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0); 13187 done: 13188 end_synchronized_op(sc, 0); 13189 } 13190 13191 static void 13192 t4_vxlan_start_handler(void *arg __unused, struct ifnet *ifp, 13193 sa_family_t family, u_int port) 13194 { 13195 struct vxlan_evargs v; 13196 13197 MPASS(family == AF_INET || family == AF_INET6); 13198 v.ifp = ifp; 13199 v.port = port; 13200 13201 t4_iterate(t4_vxlan_start, &v); 13202 } 13203 13204 static void 13205 t4_vxlan_stop_handler(void *arg __unused, struct ifnet *ifp, sa_family_t family, 13206 u_int port) 13207 { 13208 struct vxlan_evargs v; 13209 13210 MPASS(family == AF_INET || family == AF_INET6); 13211 v.ifp = ifp; 13212 v.port = port; 13213 13214 t4_iterate(t4_vxlan_stop, &v); 13215 } 13216 13217 13218 static struct sx mlu; /* mod load unload */ 13219 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 13220 13221 static int 13222 mod_event(module_t mod, int cmd, void *arg) 13223 { 13224 int rc = 0; 13225 static int loaded = 0; 13226 13227 switch (cmd) { 13228 case MOD_LOAD: 13229 sx_xlock(&mlu); 13230 if (loaded++ == 0) { 13231 t4_sge_modload(); 13232 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13233 t4_filter_rpl, CPL_COOKIE_FILTER); 13234 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 13235 do_l2t_write_rpl, CPL_COOKIE_FILTER); 13236 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 13237 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 13238 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13239 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 13240 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 13241 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 13242 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 13243 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 13244 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 13245 do_smt_write_rpl); 13246 sx_init(&t4_list_lock, "T4/T5 adapters"); 13247 SLIST_INIT(&t4_list); 13248 callout_init(&fatal_callout, 1); 13249 #ifdef TCP_OFFLOAD 13250 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 13251 SLIST_INIT(&t4_uld_list); 13252 #endif 13253 #ifdef INET6 13254 t4_clip_modload(); 13255 #endif 13256 #ifdef KERN_TLS 13257 t6_ktls_modload(); 13258 #endif 13259 t4_tracer_modload(); 13260 tweak_tunables(); 13261 vxlan_start_evtag = 13262 EVENTHANDLER_REGISTER(vxlan_start, 13263 t4_vxlan_start_handler, NULL, 13264 EVENTHANDLER_PRI_ANY); 13265 vxlan_stop_evtag = 13266 EVENTHANDLER_REGISTER(vxlan_stop, 13267 t4_vxlan_stop_handler, NULL, 13268 EVENTHANDLER_PRI_ANY); 13269 reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK, 13270 taskqueue_thread_enqueue, &reset_tq); 13271 taskqueue_start_threads(&reset_tq, 1, PI_SOFT, 13272 "t4_rst_thr"); 13273 } 13274 sx_xunlock(&mlu); 13275 break; 13276 13277 case MOD_UNLOAD: 13278 sx_xlock(&mlu); 13279 if (--loaded == 0) { 13280 int tries; 13281 13282 taskqueue_free(reset_tq); 13283 sx_slock(&t4_list_lock); 13284 if (!SLIST_EMPTY(&t4_list)) { 13285 rc = EBUSY; 13286 sx_sunlock(&t4_list_lock); 13287 goto done_unload; 13288 } 13289 #ifdef TCP_OFFLOAD 13290 sx_slock(&t4_uld_list_lock); 13291 if (!SLIST_EMPTY(&t4_uld_list)) { 13292 rc = EBUSY; 13293 sx_sunlock(&t4_uld_list_lock); 13294 sx_sunlock(&t4_list_lock); 13295 goto done_unload; 13296 } 13297 #endif 13298 tries = 0; 13299 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 13300 uprintf("%ju clusters with custom free routine " 13301 "still is use.\n", t4_sge_extfree_refs()); 13302 pause("t4unload", 2 * hz); 13303 } 13304 #ifdef TCP_OFFLOAD 13305 sx_sunlock(&t4_uld_list_lock); 13306 #endif 13307 sx_sunlock(&t4_list_lock); 13308 13309 if (t4_sge_extfree_refs() == 0) { 13310 EVENTHANDLER_DEREGISTER(vxlan_start, 13311 vxlan_start_evtag); 13312 EVENTHANDLER_DEREGISTER(vxlan_stop, 13313 vxlan_stop_evtag); 13314 t4_tracer_modunload(); 13315 #ifdef KERN_TLS 13316 t6_ktls_modunload(); 13317 #endif 13318 #ifdef INET6 13319 t4_clip_modunload(); 13320 #endif 13321 #ifdef TCP_OFFLOAD 13322 sx_destroy(&t4_uld_list_lock); 13323 #endif 13324 sx_destroy(&t4_list_lock); 13325 t4_sge_modunload(); 13326 loaded = 0; 13327 } else { 13328 rc = EBUSY; 13329 loaded++; /* undo earlier decrement */ 13330 } 13331 } 13332 done_unload: 13333 sx_xunlock(&mlu); 13334 break; 13335 } 13336 13337 return (rc); 13338 } 13339 13340 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0); 13341 MODULE_VERSION(t4nex, 1); 13342 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 13343 #ifdef DEV_NETMAP 13344 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 13345 #endif /* DEV_NETMAP */ 13346 13347 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0); 13348 MODULE_VERSION(t5nex, 1); 13349 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 13350 #ifdef DEV_NETMAP 13351 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 13352 #endif /* DEV_NETMAP */ 13353 13354 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0); 13355 MODULE_VERSION(t6nex, 1); 13356 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 13357 #ifdef DEV_NETMAP 13358 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 13359 #endif /* DEV_NETMAP */ 13360 13361 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0); 13362 MODULE_VERSION(cxgbe, 1); 13363 13364 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0); 13365 MODULE_VERSION(cxl, 1); 13366 13367 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0); 13368 MODULE_VERSION(cc, 1); 13369 13370 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0); 13371 MODULE_VERSION(vcxgbe, 1); 13372 13373 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0); 13374 MODULE_VERSION(vcxl, 1); 13375 13376 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0); 13377 MODULE_VERSION(vcc, 1); 13378