1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_ratelimit.h" 37 #include "opt_rss.h" 38 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/priv.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #if defined(__i386__) || defined(__amd64__) 69 #include <machine/md_var.h> 70 #include <machine/cputypes.h> 71 #include <vm/vm.h> 72 #include <vm/pmap.h> 73 #endif 74 #include <crypto/rijndael/rijndael.h> 75 #ifdef DDB 76 #include <ddb/ddb.h> 77 #include <ddb/db_lex.h> 78 #endif 79 80 #include "common/common.h" 81 #include "common/t4_msg.h" 82 #include "common/t4_regs.h" 83 #include "common/t4_regs_values.h" 84 #include "cudbg/cudbg.h" 85 #include "t4_clip.h" 86 #include "t4_ioctl.h" 87 #include "t4_l2t.h" 88 #include "t4_mp_ring.h" 89 #include "t4_if.h" 90 #include "t4_smt.h" 91 92 /* T4 bus driver interface */ 93 static int t4_probe(device_t); 94 static int t4_attach(device_t); 95 static int t4_detach(device_t); 96 static int t4_child_location_str(device_t, device_t, char *, size_t); 97 static int t4_ready(device_t); 98 static int t4_read_port_device(device_t, int, device_t *); 99 static device_method_t t4_methods[] = { 100 DEVMETHOD(device_probe, t4_probe), 101 DEVMETHOD(device_attach, t4_attach), 102 DEVMETHOD(device_detach, t4_detach), 103 104 DEVMETHOD(bus_child_location_str, t4_child_location_str), 105 106 DEVMETHOD(t4_is_main_ready, t4_ready), 107 DEVMETHOD(t4_read_port_device, t4_read_port_device), 108 109 DEVMETHOD_END 110 }; 111 static driver_t t4_driver = { 112 "t4nex", 113 t4_methods, 114 sizeof(struct adapter) 115 }; 116 117 118 /* T4 port (cxgbe) interface */ 119 static int cxgbe_probe(device_t); 120 static int cxgbe_attach(device_t); 121 static int cxgbe_detach(device_t); 122 device_method_t cxgbe_methods[] = { 123 DEVMETHOD(device_probe, cxgbe_probe), 124 DEVMETHOD(device_attach, cxgbe_attach), 125 DEVMETHOD(device_detach, cxgbe_detach), 126 { 0, 0 } 127 }; 128 static driver_t cxgbe_driver = { 129 "cxgbe", 130 cxgbe_methods, 131 sizeof(struct port_info) 132 }; 133 134 /* T4 VI (vcxgbe) interface */ 135 static int vcxgbe_probe(device_t); 136 static int vcxgbe_attach(device_t); 137 static int vcxgbe_detach(device_t); 138 static device_method_t vcxgbe_methods[] = { 139 DEVMETHOD(device_probe, vcxgbe_probe), 140 DEVMETHOD(device_attach, vcxgbe_attach), 141 DEVMETHOD(device_detach, vcxgbe_detach), 142 { 0, 0 } 143 }; 144 static driver_t vcxgbe_driver = { 145 "vcxgbe", 146 vcxgbe_methods, 147 sizeof(struct vi_info) 148 }; 149 150 static d_ioctl_t t4_ioctl; 151 152 static struct cdevsw t4_cdevsw = { 153 .d_version = D_VERSION, 154 .d_ioctl = t4_ioctl, 155 .d_name = "t4nex", 156 }; 157 158 /* T5 bus driver interface */ 159 static int t5_probe(device_t); 160 static device_method_t t5_methods[] = { 161 DEVMETHOD(device_probe, t5_probe), 162 DEVMETHOD(device_attach, t4_attach), 163 DEVMETHOD(device_detach, t4_detach), 164 165 DEVMETHOD(bus_child_location_str, t4_child_location_str), 166 167 DEVMETHOD(t4_is_main_ready, t4_ready), 168 DEVMETHOD(t4_read_port_device, t4_read_port_device), 169 170 DEVMETHOD_END 171 }; 172 static driver_t t5_driver = { 173 "t5nex", 174 t5_methods, 175 sizeof(struct adapter) 176 }; 177 178 179 /* T5 port (cxl) interface */ 180 static driver_t cxl_driver = { 181 "cxl", 182 cxgbe_methods, 183 sizeof(struct port_info) 184 }; 185 186 /* T5 VI (vcxl) interface */ 187 static driver_t vcxl_driver = { 188 "vcxl", 189 vcxgbe_methods, 190 sizeof(struct vi_info) 191 }; 192 193 /* T6 bus driver interface */ 194 static int t6_probe(device_t); 195 static device_method_t t6_methods[] = { 196 DEVMETHOD(device_probe, t6_probe), 197 DEVMETHOD(device_attach, t4_attach), 198 DEVMETHOD(device_detach, t4_detach), 199 200 DEVMETHOD(bus_child_location_str, t4_child_location_str), 201 202 DEVMETHOD(t4_is_main_ready, t4_ready), 203 DEVMETHOD(t4_read_port_device, t4_read_port_device), 204 205 DEVMETHOD_END 206 }; 207 static driver_t t6_driver = { 208 "t6nex", 209 t6_methods, 210 sizeof(struct adapter) 211 }; 212 213 214 /* T6 port (cc) interface */ 215 static driver_t cc_driver = { 216 "cc", 217 cxgbe_methods, 218 sizeof(struct port_info) 219 }; 220 221 /* T6 VI (vcc) interface */ 222 static driver_t vcc_driver = { 223 "vcc", 224 vcxgbe_methods, 225 sizeof(struct vi_info) 226 }; 227 228 /* ifnet interface */ 229 static void cxgbe_init(void *); 230 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 231 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 232 static void cxgbe_qflush(struct ifnet *); 233 234 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 235 236 /* 237 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 238 * then ADAPTER_LOCK, then t4_uld_list_lock. 239 */ 240 static struct sx t4_list_lock; 241 SLIST_HEAD(, adapter) t4_list; 242 #ifdef TCP_OFFLOAD 243 static struct sx t4_uld_list_lock; 244 SLIST_HEAD(, uld_info) t4_uld_list; 245 #endif 246 247 /* 248 * Tunables. See tweak_tunables() too. 249 * 250 * Each tunable is set to a default value here if it's known at compile-time. 251 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 252 * provide a reasonable default (upto n) when the driver is loaded. 253 * 254 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 255 * T5 are under hw.cxl. 256 */ 257 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters"); 258 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters"); 259 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters"); 260 261 /* 262 * Number of queues for tx and rx, NIC and offload. 263 */ 264 #define NTXQ 16 265 int t4_ntxq = -NTXQ; 266 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 267 "Number of TX queues per port"); 268 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 269 270 #define NRXQ 8 271 int t4_nrxq = -NRXQ; 272 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 273 "Number of RX queues per port"); 274 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 275 276 #define NTXQ_VI 1 277 static int t4_ntxq_vi = -NTXQ_VI; 278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 279 "Number of TX queues per VI"); 280 281 #define NRXQ_VI 1 282 static int t4_nrxq_vi = -NRXQ_VI; 283 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 284 "Number of RX queues per VI"); 285 286 static int t4_rsrv_noflowq = 0; 287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 288 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 289 290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 291 #define NOFLDTXQ 8 292 static int t4_nofldtxq = -NOFLDTXQ; 293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 294 "Number of offload TX queues per port"); 295 296 #define NOFLDRXQ 2 297 static int t4_nofldrxq = -NOFLDRXQ; 298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 299 "Number of offload RX queues per port"); 300 301 #define NOFLDTXQ_VI 1 302 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 304 "Number of offload TX queues per VI"); 305 306 #define NOFLDRXQ_VI 1 307 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 309 "Number of offload RX queues per VI"); 310 311 #define TMR_IDX_OFLD 1 312 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 314 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 315 316 #define PKTC_IDX_OFLD (-1) 317 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 319 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 320 321 /* 0 means chip/fw default, non-zero number is value in microseconds */ 322 static u_long t4_toe_keepalive_idle = 0; 323 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 324 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 325 326 /* 0 means chip/fw default, non-zero number is value in microseconds */ 327 static u_long t4_toe_keepalive_interval = 0; 328 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 329 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 330 331 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 332 static int t4_toe_keepalive_count = 0; 333 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 334 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 335 336 /* 0 means chip/fw default, non-zero number is value in microseconds */ 337 static u_long t4_toe_rexmt_min = 0; 338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 339 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 340 341 /* 0 means chip/fw default, non-zero number is value in microseconds */ 342 static u_long t4_toe_rexmt_max = 0; 343 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 344 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 345 346 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 347 static int t4_toe_rexmt_count = 0; 348 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 349 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 350 351 /* -1 means chip/fw default, other values are raw backoff values to use */ 352 static int t4_toe_rexmt_backoff[16] = { 353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 354 }; 355 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0, 356 "cxgbe(4) TOE retransmit backoff values"); 357 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 358 &t4_toe_rexmt_backoff[0], 0, ""); 359 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 360 &t4_toe_rexmt_backoff[1], 0, ""); 361 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 362 &t4_toe_rexmt_backoff[2], 0, ""); 363 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_backoff[3], 0, ""); 365 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_backoff[4], 0, ""); 367 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 368 &t4_toe_rexmt_backoff[5], 0, ""); 369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 370 &t4_toe_rexmt_backoff[6], 0, ""); 371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 372 &t4_toe_rexmt_backoff[7], 0, ""); 373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_backoff[8], 0, ""); 375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_backoff[9], 0, ""); 377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 378 &t4_toe_rexmt_backoff[10], 0, ""); 379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 380 &t4_toe_rexmt_backoff[11], 0, ""); 381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 382 &t4_toe_rexmt_backoff[12], 0, ""); 383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[13], 0, ""); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[14], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[15], 0, ""); 389 #endif 390 391 #ifdef DEV_NETMAP 392 #define NNMTXQ_VI 2 393 static int t4_nnmtxq_vi = -NNMTXQ_VI; 394 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 395 "Number of netmap TX queues per VI"); 396 397 #define NNMRXQ_VI 2 398 static int t4_nnmrxq_vi = -NNMRXQ_VI; 399 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 400 "Number of netmap RX queues per VI"); 401 #endif 402 403 /* 404 * Holdoff parameters for ports. 405 */ 406 #define TMR_IDX 1 407 int t4_tmr_idx = TMR_IDX; 408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 409 0, "Holdoff timer index"); 410 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 411 412 #define PKTC_IDX (-1) 413 int t4_pktc_idx = PKTC_IDX; 414 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 415 0, "Holdoff packet counter index"); 416 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 417 418 /* 419 * Size (# of entries) of each tx and rx queue. 420 */ 421 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 423 "Number of descriptors in each TX queue"); 424 425 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 427 "Number of descriptors in each RX queue"); 428 429 /* 430 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 431 */ 432 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 434 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 435 436 /* 437 * Configuration file. All the _CF names here are special. 438 */ 439 #define DEFAULT_CF "default" 440 #define BUILTIN_CF "built-in" 441 #define FLASH_CF "flash" 442 #define UWIRE_CF "uwire" 443 #define FPGA_CF "fpga" 444 static char t4_cfg_file[32] = DEFAULT_CF; 445 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 446 sizeof(t4_cfg_file), "Firmware configuration file"); 447 448 /* 449 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 450 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 451 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 452 * mark or when signalled to do so, 0 to never emit PAUSE. 453 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 454 * negotiated settings will override rx_pause/tx_pause. 455 * Otherwise rx_pause/tx_pause are applied forcibly. 456 */ 457 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 459 &t4_pause_settings, 0, 460 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 461 462 /* 463 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 464 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 465 * 0 to disable FEC. 466 */ 467 static int t4_fec = -1; 468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 469 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 470 471 /* 472 * Link autonegotiation. 473 * -1 to run with the firmware default. 474 * 0 to disable. 475 * 1 to enable. 476 */ 477 static int t4_autoneg = -1; 478 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 479 "Link autonegotiation"); 480 481 /* 482 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 483 * encouraged respectively). '-n' is the same as 'n' except the firmware 484 * version used in the checks is read from the firmware bundled with the driver. 485 */ 486 static int t4_fw_install = 1; 487 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 488 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 489 490 /* 491 * ASIC features that will be used. Disable the ones you don't want so that the 492 * chip resources aren't wasted on features that will not be used. 493 */ 494 static int t4_nbmcaps_allowed = 0; 495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 496 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 497 498 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 499 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 500 &t4_linkcaps_allowed, 0, "Default link capabilities"); 501 502 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 503 FW_CAPS_CONFIG_SWITCH_EGRESS; 504 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 505 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 506 507 #ifdef RATELIMIT 508 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 509 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 510 #else 511 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 512 FW_CAPS_CONFIG_NIC_HASHFILTER; 513 #endif 514 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 515 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 516 517 static int t4_toecaps_allowed = -1; 518 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 519 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 520 521 static int t4_rdmacaps_allowed = -1; 522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 523 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 524 525 static int t4_cryptocaps_allowed = -1; 526 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 527 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 528 529 static int t4_iscsicaps_allowed = -1; 530 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 531 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 532 533 static int t4_fcoecaps_allowed = 0; 534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 535 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 536 537 static int t5_write_combine = 0; 538 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 539 0, "Use WC instead of UC for BAR2"); 540 541 static int t4_num_vis = 1; 542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 543 "Number of VIs per port"); 544 545 /* 546 * PCIe Relaxed Ordering. 547 * -1: driver should figure out a good value. 548 * 0: disable RO. 549 * 1: enable RO. 550 * 2: leave RO alone. 551 */ 552 static int pcie_relaxed_ordering = -1; 553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 554 &pcie_relaxed_ordering, 0, 555 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 556 557 static int t4_panic_on_fatal_err = 0; 558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN, 559 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 560 561 #ifdef TCP_OFFLOAD 562 /* 563 * TOE tunables. 564 */ 565 static int t4_cop_managed_offloading = 0; 566 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 567 &t4_cop_managed_offloading, 0, 568 "COP (Connection Offload Policy) controls all TOE offload"); 569 #endif 570 571 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 572 static int vi_mac_funcs[] = { 573 FW_VI_FUNC_ETH, 574 FW_VI_FUNC_OFLD, 575 FW_VI_FUNC_IWARP, 576 FW_VI_FUNC_OPENISCSI, 577 FW_VI_FUNC_OPENFCOE, 578 FW_VI_FUNC_FOISCSI, 579 FW_VI_FUNC_FOFCOE, 580 }; 581 582 struct intrs_and_queues { 583 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 584 uint16_t num_vis; /* number of VIs for each port */ 585 uint16_t nirq; /* Total # of vectors */ 586 uint16_t ntxq; /* # of NIC txq's for each port */ 587 uint16_t nrxq; /* # of NIC rxq's for each port */ 588 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 589 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 590 591 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 592 uint16_t ntxq_vi; /* # of NIC txq's */ 593 uint16_t nrxq_vi; /* # of NIC rxq's */ 594 uint16_t nofldtxq_vi; /* # of TOE txq's */ 595 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 596 uint16_t nnmtxq_vi; /* # of netmap txq's */ 597 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 598 }; 599 600 static void setup_memwin(struct adapter *); 601 static void position_memwin(struct adapter *, int, uint32_t); 602 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 603 static int fwmtype_to_hwmtype(int); 604 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 605 uint32_t *); 606 static int fixup_devlog_params(struct adapter *); 607 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 608 static int contact_firmware(struct adapter *); 609 static int partition_resources(struct adapter *); 610 static int get_params__pre_init(struct adapter *); 611 static int set_params__pre_init(struct adapter *); 612 static int get_params__post_init(struct adapter *); 613 static int set_params__post_init(struct adapter *); 614 static void t4_set_desc(struct adapter *); 615 static bool fixed_ifmedia(struct port_info *); 616 static void build_medialist(struct port_info *); 617 static void init_link_config(struct port_info *); 618 static int fixup_link_config(struct port_info *); 619 static int apply_link_config(struct port_info *); 620 static int cxgbe_init_synchronized(struct vi_info *); 621 static int cxgbe_uninit_synchronized(struct vi_info *); 622 static void quiesce_txq(struct adapter *, struct sge_txq *); 623 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 624 static void quiesce_iq(struct adapter *, struct sge_iq *); 625 static void quiesce_fl(struct adapter *, struct sge_fl *); 626 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 627 driver_intr_t *, void *, char *); 628 static int t4_free_irq(struct adapter *, struct irq *); 629 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 630 static void vi_refresh_stats(struct adapter *, struct vi_info *); 631 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 632 static void cxgbe_tick(void *); 633 static void cxgbe_sysctls(struct port_info *); 634 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 635 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 636 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 637 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 638 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 639 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 640 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 641 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 642 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 643 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 644 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 645 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 646 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 647 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 648 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 649 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 650 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 651 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 652 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 653 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 654 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 655 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 656 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 657 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 658 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 659 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 660 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 661 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 662 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 663 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 664 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 665 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 666 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 667 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 668 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 669 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 670 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 671 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 672 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 673 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 674 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 675 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 676 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 677 #ifdef TCP_OFFLOAD 678 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 679 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 680 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 681 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 682 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 683 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 684 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 685 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 686 #endif 687 static int get_sge_context(struct adapter *, struct t4_sge_context *); 688 static int load_fw(struct adapter *, struct t4_data *); 689 static int load_cfg(struct adapter *, struct t4_data *); 690 static int load_boot(struct adapter *, struct t4_bootrom *); 691 static int load_bootcfg(struct adapter *, struct t4_data *); 692 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 693 static void free_offload_policy(struct t4_offload_policy *); 694 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 695 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 696 static int read_i2c(struct adapter *, struct t4_i2c_data *); 697 #ifdef TCP_OFFLOAD 698 static int toe_capability(struct vi_info *, int); 699 #endif 700 static int mod_event(module_t, int, void *); 701 static int notify_siblings(device_t, int); 702 703 struct { 704 uint16_t device; 705 char *desc; 706 } t4_pciids[] = { 707 {0xa000, "Chelsio Terminator 4 FPGA"}, 708 {0x4400, "Chelsio T440-dbg"}, 709 {0x4401, "Chelsio T420-CR"}, 710 {0x4402, "Chelsio T422-CR"}, 711 {0x4403, "Chelsio T440-CR"}, 712 {0x4404, "Chelsio T420-BCH"}, 713 {0x4405, "Chelsio T440-BCH"}, 714 {0x4406, "Chelsio T440-CH"}, 715 {0x4407, "Chelsio T420-SO"}, 716 {0x4408, "Chelsio T420-CX"}, 717 {0x4409, "Chelsio T420-BT"}, 718 {0x440a, "Chelsio T404-BT"}, 719 {0x440e, "Chelsio T440-LP-CR"}, 720 }, t5_pciids[] = { 721 {0xb000, "Chelsio Terminator 5 FPGA"}, 722 {0x5400, "Chelsio T580-dbg"}, 723 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 724 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 725 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 726 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 727 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 728 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 729 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 730 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 731 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 732 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 733 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 734 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 735 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 736 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 737 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 738 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 739 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 740 741 /* Custom */ 742 {0x5483, "Custom T540-CR"}, 743 {0x5484, "Custom T540-BT"}, 744 }, t6_pciids[] = { 745 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 746 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 747 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 748 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 749 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 750 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 751 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 752 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 753 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 754 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 755 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 756 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 757 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 758 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 759 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 760 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 761 762 /* Custom */ 763 {0x6480, "Custom T6225-CR"}, 764 {0x6481, "Custom T62100-CR"}, 765 {0x6482, "Custom T6225-CR"}, 766 {0x6483, "Custom T62100-CR"}, 767 {0x6484, "Custom T64100-CR"}, 768 {0x6485, "Custom T6240-SO"}, 769 {0x6486, "Custom T6225-SO-CR"}, 770 {0x6487, "Custom T6225-CR"}, 771 }; 772 773 #ifdef TCP_OFFLOAD 774 /* 775 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 776 * be exactly the same for both rxq and ofld_rxq. 777 */ 778 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 779 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 780 #endif 781 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 782 783 static int 784 t4_probe(device_t dev) 785 { 786 int i; 787 uint16_t v = pci_get_vendor(dev); 788 uint16_t d = pci_get_device(dev); 789 uint8_t f = pci_get_function(dev); 790 791 if (v != PCI_VENDOR_ID_CHELSIO) 792 return (ENXIO); 793 794 /* Attach only to PF0 of the FPGA */ 795 if (d == 0xa000 && f != 0) 796 return (ENXIO); 797 798 for (i = 0; i < nitems(t4_pciids); i++) { 799 if (d == t4_pciids[i].device) { 800 device_set_desc(dev, t4_pciids[i].desc); 801 return (BUS_PROBE_DEFAULT); 802 } 803 } 804 805 return (ENXIO); 806 } 807 808 static int 809 t5_probe(device_t dev) 810 { 811 int i; 812 uint16_t v = pci_get_vendor(dev); 813 uint16_t d = pci_get_device(dev); 814 uint8_t f = pci_get_function(dev); 815 816 if (v != PCI_VENDOR_ID_CHELSIO) 817 return (ENXIO); 818 819 /* Attach only to PF0 of the FPGA */ 820 if (d == 0xb000 && f != 0) 821 return (ENXIO); 822 823 for (i = 0; i < nitems(t5_pciids); i++) { 824 if (d == t5_pciids[i].device) { 825 device_set_desc(dev, t5_pciids[i].desc); 826 return (BUS_PROBE_DEFAULT); 827 } 828 } 829 830 return (ENXIO); 831 } 832 833 static int 834 t6_probe(device_t dev) 835 { 836 int i; 837 uint16_t v = pci_get_vendor(dev); 838 uint16_t d = pci_get_device(dev); 839 840 if (v != PCI_VENDOR_ID_CHELSIO) 841 return (ENXIO); 842 843 for (i = 0; i < nitems(t6_pciids); i++) { 844 if (d == t6_pciids[i].device) { 845 device_set_desc(dev, t6_pciids[i].desc); 846 return (BUS_PROBE_DEFAULT); 847 } 848 } 849 850 return (ENXIO); 851 } 852 853 static void 854 t5_attribute_workaround(device_t dev) 855 { 856 device_t root_port; 857 uint32_t v; 858 859 /* 860 * The T5 chips do not properly echo the No Snoop and Relaxed 861 * Ordering attributes when replying to a TLP from a Root 862 * Port. As a workaround, find the parent Root Port and 863 * disable No Snoop and Relaxed Ordering. Note that this 864 * affects all devices under this root port. 865 */ 866 root_port = pci_find_pcie_root_port(dev); 867 if (root_port == NULL) { 868 device_printf(dev, "Unable to find parent root port\n"); 869 return; 870 } 871 872 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 873 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 874 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 875 0) 876 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 877 device_get_nameunit(root_port)); 878 } 879 880 static const struct devnames devnames[] = { 881 { 882 .nexus_name = "t4nex", 883 .ifnet_name = "cxgbe", 884 .vi_ifnet_name = "vcxgbe", 885 .pf03_drv_name = "t4iov", 886 .vf_nexus_name = "t4vf", 887 .vf_ifnet_name = "cxgbev" 888 }, { 889 .nexus_name = "t5nex", 890 .ifnet_name = "cxl", 891 .vi_ifnet_name = "vcxl", 892 .pf03_drv_name = "t5iov", 893 .vf_nexus_name = "t5vf", 894 .vf_ifnet_name = "cxlv" 895 }, { 896 .nexus_name = "t6nex", 897 .ifnet_name = "cc", 898 .vi_ifnet_name = "vcc", 899 .pf03_drv_name = "t6iov", 900 .vf_nexus_name = "t6vf", 901 .vf_ifnet_name = "ccv" 902 } 903 }; 904 905 void 906 t4_init_devnames(struct adapter *sc) 907 { 908 int id; 909 910 id = chip_id(sc); 911 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 912 sc->names = &devnames[id - CHELSIO_T4]; 913 else { 914 device_printf(sc->dev, "chip id %d is not supported.\n", id); 915 sc->names = NULL; 916 } 917 } 918 919 static int 920 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 921 { 922 const char *parent, *name; 923 long value; 924 int line, unit; 925 926 line = 0; 927 parent = device_get_nameunit(sc->dev); 928 name = sc->names->ifnet_name; 929 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 930 if (resource_long_value(name, unit, "port", &value) == 0 && 931 value == pi->port_id) 932 return (unit); 933 } 934 return (-1); 935 } 936 937 static int 938 t4_attach(device_t dev) 939 { 940 struct adapter *sc; 941 int rc = 0, i, j, rqidx, tqidx, nports; 942 struct make_dev_args mda; 943 struct intrs_and_queues iaq; 944 struct sge *s; 945 uint32_t *buf; 946 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 947 int ofld_tqidx; 948 #endif 949 #ifdef TCP_OFFLOAD 950 int ofld_rqidx; 951 #endif 952 #ifdef DEV_NETMAP 953 int nm_rqidx, nm_tqidx; 954 #endif 955 int num_vis; 956 957 sc = device_get_softc(dev); 958 sc->dev = dev; 959 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 960 961 if ((pci_get_device(dev) & 0xff00) == 0x5400) 962 t5_attribute_workaround(dev); 963 pci_enable_busmaster(dev); 964 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 965 uint32_t v; 966 967 pci_set_max_read_req(dev, 4096); 968 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 969 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 970 if (pcie_relaxed_ordering == 0 && 971 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 972 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 973 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 974 } else if (pcie_relaxed_ordering == 1 && 975 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 976 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 977 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 978 } 979 } 980 981 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 982 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 983 sc->traceq = -1; 984 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 985 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 986 device_get_nameunit(dev)); 987 988 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 989 device_get_nameunit(dev)); 990 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 991 t4_add_adapter(sc); 992 993 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 994 TAILQ_INIT(&sc->sfl); 995 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 996 997 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 998 999 sc->policy = NULL; 1000 rw_init(&sc->policy_lock, "connection offload policy"); 1001 1002 rc = t4_map_bars_0_and_4(sc); 1003 if (rc != 0) 1004 goto done; /* error message displayed already */ 1005 1006 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1007 1008 /* Prepare the adapter for operation. */ 1009 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1010 rc = -t4_prep_adapter(sc, buf); 1011 free(buf, M_CXGBE); 1012 if (rc != 0) { 1013 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1014 goto done; 1015 } 1016 1017 /* 1018 * This is the real PF# to which we're attaching. Works from within PCI 1019 * passthrough environments too, where pci_get_function() could return a 1020 * different PF# depending on the passthrough configuration. We need to 1021 * use the real PF# in all our communication with the firmware. 1022 */ 1023 j = t4_read_reg(sc, A_PL_WHOAMI); 1024 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1025 sc->mbox = sc->pf; 1026 1027 t4_init_devnames(sc); 1028 if (sc->names == NULL) { 1029 rc = ENOTSUP; 1030 goto done; /* error message displayed already */ 1031 } 1032 1033 /* 1034 * Do this really early, with the memory windows set up even before the 1035 * character device. The userland tool's register i/o and mem read 1036 * will work even in "recovery mode". 1037 */ 1038 setup_memwin(sc); 1039 if (t4_init_devlog_params(sc, 0) == 0) 1040 fixup_devlog_params(sc); 1041 make_dev_args_init(&mda); 1042 mda.mda_devsw = &t4_cdevsw; 1043 mda.mda_uid = UID_ROOT; 1044 mda.mda_gid = GID_WHEEL; 1045 mda.mda_mode = 0600; 1046 mda.mda_si_drv1 = sc; 1047 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1048 if (rc != 0) 1049 device_printf(dev, "failed to create nexus char device: %d.\n", 1050 rc); 1051 1052 /* Go no further if recovery mode has been requested. */ 1053 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1054 device_printf(dev, "recovery mode.\n"); 1055 goto done; 1056 } 1057 1058 #if defined(__i386__) 1059 if ((cpu_feature & CPUID_CX8) == 0) { 1060 device_printf(dev, "64 bit atomics not available.\n"); 1061 rc = ENOTSUP; 1062 goto done; 1063 } 1064 #endif 1065 1066 /* Contact the firmware and try to become the master driver. */ 1067 rc = contact_firmware(sc); 1068 if (rc != 0) 1069 goto done; /* error message displayed already */ 1070 MPASS(sc->flags & FW_OK); 1071 1072 rc = get_params__pre_init(sc); 1073 if (rc != 0) 1074 goto done; /* error message displayed already */ 1075 1076 if (sc->flags & MASTER_PF) { 1077 rc = partition_resources(sc); 1078 if (rc != 0) 1079 goto done; /* error message displayed already */ 1080 t4_intr_clear(sc); 1081 } 1082 1083 rc = get_params__post_init(sc); 1084 if (rc != 0) 1085 goto done; /* error message displayed already */ 1086 1087 rc = set_params__post_init(sc); 1088 if (rc != 0) 1089 goto done; /* error message displayed already */ 1090 1091 rc = t4_map_bar_2(sc); 1092 if (rc != 0) 1093 goto done; /* error message displayed already */ 1094 1095 rc = t4_create_dma_tag(sc); 1096 if (rc != 0) 1097 goto done; /* error message displayed already */ 1098 1099 /* 1100 * First pass over all the ports - allocate VIs and initialize some 1101 * basic parameters like mac address, port type, etc. 1102 */ 1103 for_each_port(sc, i) { 1104 struct port_info *pi; 1105 1106 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1107 sc->port[i] = pi; 1108 1109 /* These must be set before t4_port_init */ 1110 pi->adapter = sc; 1111 pi->port_id = i; 1112 /* 1113 * XXX: vi[0] is special so we can't delay this allocation until 1114 * pi->nvi's final value is known. 1115 */ 1116 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1117 M_ZERO | M_WAITOK); 1118 1119 /* 1120 * Allocate the "main" VI and initialize parameters 1121 * like mac addr. 1122 */ 1123 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1124 if (rc != 0) { 1125 device_printf(dev, "unable to initialize port %d: %d\n", 1126 i, rc); 1127 free(pi->vi, M_CXGBE); 1128 free(pi, M_CXGBE); 1129 sc->port[i] = NULL; 1130 goto done; 1131 } 1132 1133 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1134 device_get_nameunit(dev), i); 1135 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1136 sc->chan_map[pi->tx_chan] = i; 1137 1138 /* All VIs on this port share this media. */ 1139 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1140 cxgbe_media_status); 1141 1142 PORT_LOCK(pi); 1143 init_link_config(pi); 1144 fixup_link_config(pi); 1145 build_medialist(pi); 1146 if (fixed_ifmedia(pi)) 1147 pi->flags |= FIXED_IFMEDIA; 1148 PORT_UNLOCK(pi); 1149 1150 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1151 t4_ifnet_unit(sc, pi)); 1152 if (pi->dev == NULL) { 1153 device_printf(dev, 1154 "failed to add device for port %d.\n", i); 1155 rc = ENXIO; 1156 goto done; 1157 } 1158 pi->vi[0].dev = pi->dev; 1159 device_set_softc(pi->dev, pi); 1160 } 1161 1162 /* 1163 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1164 */ 1165 nports = sc->params.nports; 1166 rc = cfg_itype_and_nqueues(sc, &iaq); 1167 if (rc != 0) 1168 goto done; /* error message displayed already */ 1169 1170 num_vis = iaq.num_vis; 1171 sc->intr_type = iaq.intr_type; 1172 sc->intr_count = iaq.nirq; 1173 1174 s = &sc->sge; 1175 s->nrxq = nports * iaq.nrxq; 1176 s->ntxq = nports * iaq.ntxq; 1177 if (num_vis > 1) { 1178 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1179 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1180 } 1181 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1182 s->neq += nports; /* ctrl queues: 1 per port */ 1183 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1184 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1185 if (is_offload(sc) || is_ethoffload(sc)) { 1186 s->nofldtxq = nports * iaq.nofldtxq; 1187 if (num_vis > 1) 1188 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1189 s->neq += s->nofldtxq; 1190 1191 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1192 M_CXGBE, M_ZERO | M_WAITOK); 1193 } 1194 #endif 1195 #ifdef TCP_OFFLOAD 1196 if (is_offload(sc)) { 1197 s->nofldrxq = nports * iaq.nofldrxq; 1198 if (num_vis > 1) 1199 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1200 s->neq += s->nofldrxq; /* free list */ 1201 s->niq += s->nofldrxq; 1202 1203 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1204 M_CXGBE, M_ZERO | M_WAITOK); 1205 } 1206 #endif 1207 #ifdef DEV_NETMAP 1208 if (num_vis > 1) { 1209 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1210 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1211 } 1212 s->neq += s->nnmtxq + s->nnmrxq; 1213 s->niq += s->nnmrxq; 1214 1215 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1216 M_CXGBE, M_ZERO | M_WAITOK); 1217 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1218 M_CXGBE, M_ZERO | M_WAITOK); 1219 #endif 1220 1221 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1222 M_ZERO | M_WAITOK); 1223 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1224 M_ZERO | M_WAITOK); 1225 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1226 M_ZERO | M_WAITOK); 1227 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1228 M_ZERO | M_WAITOK); 1229 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1230 M_ZERO | M_WAITOK); 1231 1232 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1233 M_ZERO | M_WAITOK); 1234 1235 t4_init_l2t(sc, M_WAITOK); 1236 t4_init_smt(sc, M_WAITOK); 1237 t4_init_tx_sched(sc); 1238 #ifdef RATELIMIT 1239 t4_init_etid_table(sc); 1240 #endif 1241 #ifdef INET6 1242 t4_init_clip_table(sc); 1243 #endif 1244 if (sc->vres.key.size != 0) 1245 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1246 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1247 1248 /* 1249 * Second pass over the ports. This time we know the number of rx and 1250 * tx queues that each port should get. 1251 */ 1252 rqidx = tqidx = 0; 1253 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1254 ofld_tqidx = 0; 1255 #endif 1256 #ifdef TCP_OFFLOAD 1257 ofld_rqidx = 0; 1258 #endif 1259 #ifdef DEV_NETMAP 1260 nm_rqidx = nm_tqidx = 0; 1261 #endif 1262 for_each_port(sc, i) { 1263 struct port_info *pi = sc->port[i]; 1264 struct vi_info *vi; 1265 1266 if (pi == NULL) 1267 continue; 1268 1269 pi->nvi = num_vis; 1270 for_each_vi(pi, j, vi) { 1271 vi->pi = pi; 1272 vi->qsize_rxq = t4_qsize_rxq; 1273 vi->qsize_txq = t4_qsize_txq; 1274 1275 vi->first_rxq = rqidx; 1276 vi->first_txq = tqidx; 1277 vi->tmr_idx = t4_tmr_idx; 1278 vi->pktc_idx = t4_pktc_idx; 1279 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1280 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1281 1282 rqidx += vi->nrxq; 1283 tqidx += vi->ntxq; 1284 1285 if (j == 0 && vi->ntxq > 1) 1286 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1287 else 1288 vi->rsrv_noflowq = 0; 1289 1290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1291 vi->first_ofld_txq = ofld_tqidx; 1292 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1293 ofld_tqidx += vi->nofldtxq; 1294 #endif 1295 #ifdef TCP_OFFLOAD 1296 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1297 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1298 vi->first_ofld_rxq = ofld_rqidx; 1299 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1300 1301 ofld_rqidx += vi->nofldrxq; 1302 #endif 1303 #ifdef DEV_NETMAP 1304 if (j > 0) { 1305 vi->first_nm_rxq = nm_rqidx; 1306 vi->first_nm_txq = nm_tqidx; 1307 vi->nnmrxq = iaq.nnmrxq_vi; 1308 vi->nnmtxq = iaq.nnmtxq_vi; 1309 nm_rqidx += vi->nnmrxq; 1310 nm_tqidx += vi->nnmtxq; 1311 } 1312 #endif 1313 } 1314 } 1315 1316 rc = t4_setup_intr_handlers(sc); 1317 if (rc != 0) { 1318 device_printf(dev, 1319 "failed to setup interrupt handlers: %d\n", rc); 1320 goto done; 1321 } 1322 1323 rc = bus_generic_probe(dev); 1324 if (rc != 0) { 1325 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1326 goto done; 1327 } 1328 1329 /* 1330 * Ensure thread-safe mailbox access (in debug builds). 1331 * 1332 * So far this was the only thread accessing the mailbox but various 1333 * ifnets and sysctls are about to be created and their handlers/ioctls 1334 * will access the mailbox from different threads. 1335 */ 1336 sc->flags |= CHK_MBOX_ACCESS; 1337 1338 rc = bus_generic_attach(dev); 1339 if (rc != 0) { 1340 device_printf(dev, 1341 "failed to attach all child ports: %d\n", rc); 1342 goto done; 1343 } 1344 1345 device_printf(dev, 1346 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1347 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1348 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1349 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1350 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1351 1352 t4_set_desc(sc); 1353 1354 notify_siblings(dev, 0); 1355 1356 done: 1357 if (rc != 0 && sc->cdev) { 1358 /* cdev was created and so cxgbetool works; recover that way. */ 1359 device_printf(dev, 1360 "error during attach, adapter is now in recovery mode.\n"); 1361 rc = 0; 1362 } 1363 1364 if (rc != 0) 1365 t4_detach_common(dev); 1366 else 1367 t4_sysctls(sc); 1368 1369 return (rc); 1370 } 1371 1372 static int 1373 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen) 1374 { 1375 struct adapter *sc; 1376 struct port_info *pi; 1377 int i; 1378 1379 sc = device_get_softc(bus); 1380 buf[0] = '\0'; 1381 for_each_port(sc, i) { 1382 pi = sc->port[i]; 1383 if (pi != NULL && pi->dev == dev) { 1384 snprintf(buf, buflen, "port=%d", pi->port_id); 1385 break; 1386 } 1387 } 1388 return (0); 1389 } 1390 1391 static int 1392 t4_ready(device_t dev) 1393 { 1394 struct adapter *sc; 1395 1396 sc = device_get_softc(dev); 1397 if (sc->flags & FW_OK) 1398 return (0); 1399 return (ENXIO); 1400 } 1401 1402 static int 1403 t4_read_port_device(device_t dev, int port, device_t *child) 1404 { 1405 struct adapter *sc; 1406 struct port_info *pi; 1407 1408 sc = device_get_softc(dev); 1409 if (port < 0 || port >= MAX_NPORTS) 1410 return (EINVAL); 1411 pi = sc->port[port]; 1412 if (pi == NULL || pi->dev == NULL) 1413 return (ENXIO); 1414 *child = pi->dev; 1415 return (0); 1416 } 1417 1418 static int 1419 notify_siblings(device_t dev, int detaching) 1420 { 1421 device_t sibling; 1422 int error, i; 1423 1424 error = 0; 1425 for (i = 0; i < PCI_FUNCMAX; i++) { 1426 if (i == pci_get_function(dev)) 1427 continue; 1428 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1429 pci_get_slot(dev), i); 1430 if (sibling == NULL || !device_is_attached(sibling)) 1431 continue; 1432 if (detaching) 1433 error = T4_DETACH_CHILD(sibling); 1434 else 1435 (void)T4_ATTACH_CHILD(sibling); 1436 if (error) 1437 break; 1438 } 1439 return (error); 1440 } 1441 1442 /* 1443 * Idempotent 1444 */ 1445 static int 1446 t4_detach(device_t dev) 1447 { 1448 struct adapter *sc; 1449 int rc; 1450 1451 sc = device_get_softc(dev); 1452 1453 rc = notify_siblings(dev, 1); 1454 if (rc) { 1455 device_printf(dev, 1456 "failed to detach sibling devices: %d\n", rc); 1457 return (rc); 1458 } 1459 1460 return (t4_detach_common(dev)); 1461 } 1462 1463 int 1464 t4_detach_common(device_t dev) 1465 { 1466 struct adapter *sc; 1467 struct port_info *pi; 1468 int i, rc; 1469 1470 sc = device_get_softc(dev); 1471 1472 if (sc->cdev) { 1473 destroy_dev(sc->cdev); 1474 sc->cdev = NULL; 1475 } 1476 1477 sc->flags &= ~CHK_MBOX_ACCESS; 1478 if (sc->flags & FULL_INIT_DONE) { 1479 if (!(sc->flags & IS_VF)) 1480 t4_intr_disable(sc); 1481 } 1482 1483 if (device_is_attached(dev)) { 1484 rc = bus_generic_detach(dev); 1485 if (rc) { 1486 device_printf(dev, 1487 "failed to detach child devices: %d\n", rc); 1488 return (rc); 1489 } 1490 } 1491 1492 for (i = 0; i < sc->intr_count; i++) 1493 t4_free_irq(sc, &sc->irq[i]); 1494 1495 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1496 t4_free_tx_sched(sc); 1497 1498 for (i = 0; i < MAX_NPORTS; i++) { 1499 pi = sc->port[i]; 1500 if (pi) { 1501 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1502 if (pi->dev) 1503 device_delete_child(dev, pi->dev); 1504 1505 mtx_destroy(&pi->pi_lock); 1506 free(pi->vi, M_CXGBE); 1507 free(pi, M_CXGBE); 1508 } 1509 } 1510 1511 device_delete_children(dev); 1512 1513 if (sc->flags & FULL_INIT_DONE) 1514 adapter_full_uninit(sc); 1515 1516 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1517 t4_fw_bye(sc, sc->mbox); 1518 1519 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1520 pci_release_msi(dev); 1521 1522 if (sc->regs_res) 1523 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1524 sc->regs_res); 1525 1526 if (sc->udbs_res) 1527 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1528 sc->udbs_res); 1529 1530 if (sc->msix_res) 1531 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1532 sc->msix_res); 1533 1534 if (sc->l2t) 1535 t4_free_l2t(sc->l2t); 1536 if (sc->smt) 1537 t4_free_smt(sc->smt); 1538 #ifdef RATELIMIT 1539 t4_free_etid_table(sc); 1540 #endif 1541 if (sc->key_map) 1542 vmem_destroy(sc->key_map); 1543 #ifdef INET6 1544 t4_destroy_clip_table(sc); 1545 #endif 1546 1547 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1548 free(sc->sge.ofld_txq, M_CXGBE); 1549 #endif 1550 #ifdef TCP_OFFLOAD 1551 free(sc->sge.ofld_rxq, M_CXGBE); 1552 #endif 1553 #ifdef DEV_NETMAP 1554 free(sc->sge.nm_rxq, M_CXGBE); 1555 free(sc->sge.nm_txq, M_CXGBE); 1556 #endif 1557 free(sc->irq, M_CXGBE); 1558 free(sc->sge.rxq, M_CXGBE); 1559 free(sc->sge.txq, M_CXGBE); 1560 free(sc->sge.ctrlq, M_CXGBE); 1561 free(sc->sge.iqmap, M_CXGBE); 1562 free(sc->sge.eqmap, M_CXGBE); 1563 free(sc->tids.ftid_tab, M_CXGBE); 1564 free(sc->tids.hpftid_tab, M_CXGBE); 1565 free_hftid_hash(&sc->tids); 1566 free(sc->tids.atid_tab, M_CXGBE); 1567 free(sc->tids.tid_tab, M_CXGBE); 1568 free(sc->tt.tls_rx_ports, M_CXGBE); 1569 t4_destroy_dma_tag(sc); 1570 if (mtx_initialized(&sc->sc_lock)) { 1571 sx_xlock(&t4_list_lock); 1572 SLIST_REMOVE(&t4_list, sc, adapter, link); 1573 sx_xunlock(&t4_list_lock); 1574 mtx_destroy(&sc->sc_lock); 1575 } 1576 1577 callout_drain(&sc->sfl_callout); 1578 if (mtx_initialized(&sc->tids.ftid_lock)) { 1579 mtx_destroy(&sc->tids.ftid_lock); 1580 cv_destroy(&sc->tids.ftid_cv); 1581 } 1582 if (mtx_initialized(&sc->tids.atid_lock)) 1583 mtx_destroy(&sc->tids.atid_lock); 1584 if (mtx_initialized(&sc->sfl_lock)) 1585 mtx_destroy(&sc->sfl_lock); 1586 if (mtx_initialized(&sc->ifp_lock)) 1587 mtx_destroy(&sc->ifp_lock); 1588 if (mtx_initialized(&sc->reg_lock)) 1589 mtx_destroy(&sc->reg_lock); 1590 1591 if (rw_initialized(&sc->policy_lock)) { 1592 rw_destroy(&sc->policy_lock); 1593 #ifdef TCP_OFFLOAD 1594 if (sc->policy != NULL) 1595 free_offload_policy(sc->policy); 1596 #endif 1597 } 1598 1599 for (i = 0; i < NUM_MEMWIN; i++) { 1600 struct memwin *mw = &sc->memwin[i]; 1601 1602 if (rw_initialized(&mw->mw_lock)) 1603 rw_destroy(&mw->mw_lock); 1604 } 1605 1606 bzero(sc, sizeof(*sc)); 1607 1608 return (0); 1609 } 1610 1611 static int 1612 cxgbe_probe(device_t dev) 1613 { 1614 char buf[128]; 1615 struct port_info *pi = device_get_softc(dev); 1616 1617 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1618 device_set_desc_copy(dev, buf); 1619 1620 return (BUS_PROBE_DEFAULT); 1621 } 1622 1623 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1624 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1625 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 1626 IFCAP_HWRXTSTMP) 1627 #define T4_CAP_ENABLE (T4_CAP) 1628 1629 static int 1630 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1631 { 1632 struct ifnet *ifp; 1633 struct sbuf *sb; 1634 1635 vi->xact_addr_filt = -1; 1636 callout_init(&vi->tick, 1); 1637 1638 /* Allocate an ifnet and set it up */ 1639 ifp = if_alloc(IFT_ETHER); 1640 if (ifp == NULL) { 1641 device_printf(dev, "Cannot allocate ifnet\n"); 1642 return (ENOMEM); 1643 } 1644 vi->ifp = ifp; 1645 ifp->if_softc = vi; 1646 1647 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1648 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1649 1650 ifp->if_init = cxgbe_init; 1651 ifp->if_ioctl = cxgbe_ioctl; 1652 ifp->if_transmit = cxgbe_transmit; 1653 ifp->if_qflush = cxgbe_qflush; 1654 ifp->if_get_counter = cxgbe_get_counter; 1655 #ifdef RATELIMIT 1656 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 1657 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify; 1658 ifp->if_snd_tag_query = cxgbe_snd_tag_query; 1659 ifp->if_snd_tag_free = cxgbe_snd_tag_free; 1660 #endif 1661 1662 ifp->if_capabilities = T4_CAP; 1663 ifp->if_capenable = T4_CAP_ENABLE; 1664 #ifdef TCP_OFFLOAD 1665 if (vi->nofldrxq != 0) 1666 ifp->if_capabilities |= IFCAP_TOE; 1667 #endif 1668 #ifdef RATELIMIT 1669 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) { 1670 ifp->if_capabilities |= IFCAP_TXRTLMT; 1671 ifp->if_capenable |= IFCAP_TXRTLMT; 1672 } 1673 #endif 1674 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1675 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1676 1677 ifp->if_hw_tsomax = IP_MAXPACKET; 1678 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 1679 #ifdef RATELIMIT 1680 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) 1681 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO; 1682 #endif 1683 ifp->if_hw_tsomaxsegsize = 65536; 1684 1685 ether_ifattach(ifp, vi->hw_addr); 1686 #ifdef DEV_NETMAP 1687 if (vi->nnmrxq != 0) 1688 cxgbe_nm_attach(vi); 1689 #endif 1690 sb = sbuf_new_auto(); 1691 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1692 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1693 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 1694 case IFCAP_TOE: 1695 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 1696 break; 1697 case IFCAP_TOE | IFCAP_TXRTLMT: 1698 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 1699 break; 1700 case IFCAP_TXRTLMT: 1701 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 1702 break; 1703 } 1704 #endif 1705 #ifdef TCP_OFFLOAD 1706 if (ifp->if_capabilities & IFCAP_TOE) 1707 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 1708 #endif 1709 #ifdef DEV_NETMAP 1710 if (ifp->if_capabilities & IFCAP_NETMAP) 1711 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1712 vi->nnmtxq, vi->nnmrxq); 1713 #endif 1714 sbuf_finish(sb); 1715 device_printf(dev, "%s\n", sbuf_data(sb)); 1716 sbuf_delete(sb); 1717 1718 vi_sysctls(vi); 1719 1720 return (0); 1721 } 1722 1723 static int 1724 cxgbe_attach(device_t dev) 1725 { 1726 struct port_info *pi = device_get_softc(dev); 1727 struct adapter *sc = pi->adapter; 1728 struct vi_info *vi; 1729 int i, rc; 1730 1731 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1732 1733 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1734 if (rc) 1735 return (rc); 1736 1737 for_each_vi(pi, i, vi) { 1738 if (i == 0) 1739 continue; 1740 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1741 if (vi->dev == NULL) { 1742 device_printf(dev, "failed to add VI %d\n", i); 1743 continue; 1744 } 1745 device_set_softc(vi->dev, vi); 1746 } 1747 1748 cxgbe_sysctls(pi); 1749 1750 bus_generic_attach(dev); 1751 1752 return (0); 1753 } 1754 1755 static void 1756 cxgbe_vi_detach(struct vi_info *vi) 1757 { 1758 struct ifnet *ifp = vi->ifp; 1759 1760 ether_ifdetach(ifp); 1761 1762 /* Let detach proceed even if these fail. */ 1763 #ifdef DEV_NETMAP 1764 if (ifp->if_capabilities & IFCAP_NETMAP) 1765 cxgbe_nm_detach(vi); 1766 #endif 1767 cxgbe_uninit_synchronized(vi); 1768 callout_drain(&vi->tick); 1769 vi_full_uninit(vi); 1770 1771 if_free(vi->ifp); 1772 vi->ifp = NULL; 1773 } 1774 1775 static int 1776 cxgbe_detach(device_t dev) 1777 { 1778 struct port_info *pi = device_get_softc(dev); 1779 struct adapter *sc = pi->adapter; 1780 int rc; 1781 1782 /* Detach the extra VIs first. */ 1783 rc = bus_generic_detach(dev); 1784 if (rc) 1785 return (rc); 1786 device_delete_children(dev); 1787 1788 doom_vi(sc, &pi->vi[0]); 1789 1790 if (pi->flags & HAS_TRACEQ) { 1791 sc->traceq = -1; /* cloner should not create ifnet */ 1792 t4_tracer_port_detach(sc); 1793 } 1794 1795 cxgbe_vi_detach(&pi->vi[0]); 1796 callout_drain(&pi->tick); 1797 ifmedia_removeall(&pi->media); 1798 1799 end_synchronized_op(sc, 0); 1800 1801 return (0); 1802 } 1803 1804 static void 1805 cxgbe_init(void *arg) 1806 { 1807 struct vi_info *vi = arg; 1808 struct adapter *sc = vi->pi->adapter; 1809 1810 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1811 return; 1812 cxgbe_init_synchronized(vi); 1813 end_synchronized_op(sc, 0); 1814 } 1815 1816 static int 1817 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1818 { 1819 int rc = 0, mtu, flags; 1820 struct vi_info *vi = ifp->if_softc; 1821 struct port_info *pi = vi->pi; 1822 struct adapter *sc = pi->adapter; 1823 struct ifreq *ifr = (struct ifreq *)data; 1824 uint32_t mask; 1825 1826 switch (cmd) { 1827 case SIOCSIFMTU: 1828 mtu = ifr->ifr_mtu; 1829 if (mtu < ETHERMIN || mtu > MAX_MTU) 1830 return (EINVAL); 1831 1832 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1833 if (rc) 1834 return (rc); 1835 ifp->if_mtu = mtu; 1836 if (vi->flags & VI_INIT_DONE) { 1837 t4_update_fl_bufsize(ifp); 1838 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1839 rc = update_mac_settings(ifp, XGMAC_MTU); 1840 } 1841 end_synchronized_op(sc, 0); 1842 break; 1843 1844 case SIOCSIFFLAGS: 1845 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 1846 if (rc) 1847 return (rc); 1848 1849 if (ifp->if_flags & IFF_UP) { 1850 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1851 flags = vi->if_flags; 1852 if ((ifp->if_flags ^ flags) & 1853 (IFF_PROMISC | IFF_ALLMULTI)) { 1854 rc = update_mac_settings(ifp, 1855 XGMAC_PROMISC | XGMAC_ALLMULTI); 1856 } 1857 } else { 1858 rc = cxgbe_init_synchronized(vi); 1859 } 1860 vi->if_flags = ifp->if_flags; 1861 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1862 rc = cxgbe_uninit_synchronized(vi); 1863 } 1864 end_synchronized_op(sc, 0); 1865 break; 1866 1867 case SIOCADDMULTI: 1868 case SIOCDELMULTI: 1869 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 1870 if (rc) 1871 return (rc); 1872 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1873 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1874 end_synchronized_op(sc, 0); 1875 break; 1876 1877 case SIOCSIFCAP: 1878 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1879 if (rc) 1880 return (rc); 1881 1882 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1883 if (mask & IFCAP_TXCSUM) { 1884 ifp->if_capenable ^= IFCAP_TXCSUM; 1885 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1886 1887 if (IFCAP_TSO4 & ifp->if_capenable && 1888 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1889 ifp->if_capenable &= ~IFCAP_TSO4; 1890 if_printf(ifp, 1891 "tso4 disabled due to -txcsum.\n"); 1892 } 1893 } 1894 if (mask & IFCAP_TXCSUM_IPV6) { 1895 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1896 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1897 1898 if (IFCAP_TSO6 & ifp->if_capenable && 1899 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1900 ifp->if_capenable &= ~IFCAP_TSO6; 1901 if_printf(ifp, 1902 "tso6 disabled due to -txcsum6.\n"); 1903 } 1904 } 1905 if (mask & IFCAP_RXCSUM) 1906 ifp->if_capenable ^= IFCAP_RXCSUM; 1907 if (mask & IFCAP_RXCSUM_IPV6) 1908 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1909 1910 /* 1911 * Note that we leave CSUM_TSO alone (it is always set). The 1912 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1913 * sending a TSO request our way, so it's sufficient to toggle 1914 * IFCAP_TSOx only. 1915 */ 1916 if (mask & IFCAP_TSO4) { 1917 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1918 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1919 if_printf(ifp, "enable txcsum first.\n"); 1920 rc = EAGAIN; 1921 goto fail; 1922 } 1923 ifp->if_capenable ^= IFCAP_TSO4; 1924 } 1925 if (mask & IFCAP_TSO6) { 1926 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1927 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1928 if_printf(ifp, "enable txcsum6 first.\n"); 1929 rc = EAGAIN; 1930 goto fail; 1931 } 1932 ifp->if_capenable ^= IFCAP_TSO6; 1933 } 1934 if (mask & IFCAP_LRO) { 1935 #if defined(INET) || defined(INET6) 1936 int i; 1937 struct sge_rxq *rxq; 1938 1939 ifp->if_capenable ^= IFCAP_LRO; 1940 for_each_rxq(vi, i, rxq) { 1941 if (ifp->if_capenable & IFCAP_LRO) 1942 rxq->iq.flags |= IQ_LRO_ENABLED; 1943 else 1944 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1945 } 1946 #endif 1947 } 1948 #ifdef TCP_OFFLOAD 1949 if (mask & IFCAP_TOE) { 1950 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1951 1952 rc = toe_capability(vi, enable); 1953 if (rc != 0) 1954 goto fail; 1955 1956 ifp->if_capenable ^= mask; 1957 } 1958 #endif 1959 if (mask & IFCAP_VLAN_HWTAGGING) { 1960 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1961 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1962 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1963 } 1964 if (mask & IFCAP_VLAN_MTU) { 1965 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1966 1967 /* Need to find out how to disable auto-mtu-inflation */ 1968 } 1969 if (mask & IFCAP_VLAN_HWTSO) 1970 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1971 if (mask & IFCAP_VLAN_HWCSUM) 1972 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1973 #ifdef RATELIMIT 1974 if (mask & IFCAP_TXRTLMT) 1975 ifp->if_capenable ^= IFCAP_TXRTLMT; 1976 #endif 1977 if (mask & IFCAP_HWRXTSTMP) { 1978 int i; 1979 struct sge_rxq *rxq; 1980 1981 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 1982 for_each_rxq(vi, i, rxq) { 1983 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 1984 rxq->iq.flags |= IQ_RX_TIMESTAMP; 1985 else 1986 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 1987 } 1988 } 1989 1990 #ifdef VLAN_CAPABILITIES 1991 VLAN_CAPABILITIES(ifp); 1992 #endif 1993 fail: 1994 end_synchronized_op(sc, 0); 1995 break; 1996 1997 case SIOCSIFMEDIA: 1998 case SIOCGIFMEDIA: 1999 case SIOCGIFXMEDIA: 2000 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 2001 break; 2002 2003 case SIOCGI2C: { 2004 struct ifi2creq i2c; 2005 2006 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 2007 if (rc != 0) 2008 break; 2009 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 2010 rc = EPERM; 2011 break; 2012 } 2013 if (i2c.len > sizeof(i2c.data)) { 2014 rc = EINVAL; 2015 break; 2016 } 2017 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 2018 if (rc) 2019 return (rc); 2020 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 2021 i2c.offset, i2c.len, &i2c.data[0]); 2022 end_synchronized_op(sc, 0); 2023 if (rc == 0) 2024 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 2025 break; 2026 } 2027 2028 default: 2029 rc = ether_ioctl(ifp, cmd, data); 2030 } 2031 2032 return (rc); 2033 } 2034 2035 static int 2036 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 2037 { 2038 struct vi_info *vi = ifp->if_softc; 2039 struct port_info *pi = vi->pi; 2040 struct adapter *sc = pi->adapter; 2041 struct sge_txq *txq; 2042 void *items[1]; 2043 int rc; 2044 2045 M_ASSERTPKTHDR(m); 2046 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 2047 2048 if (__predict_false(pi->link_cfg.link_ok == false)) { 2049 m_freem(m); 2050 return (ENETDOWN); 2051 } 2052 2053 rc = parse_pkt(sc, &m); 2054 if (__predict_false(rc != 0)) { 2055 MPASS(m == NULL); /* was freed already */ 2056 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 2057 return (rc); 2058 } 2059 #ifdef RATELIMIT 2060 if (m->m_pkthdr.snd_tag != NULL) { 2061 /* EAGAIN tells the stack we are not the correct interface. */ 2062 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) { 2063 m_freem(m); 2064 return (EAGAIN); 2065 } 2066 2067 return (ethofld_transmit(ifp, m)); 2068 } 2069 #endif 2070 2071 /* Select a txq. */ 2072 txq = &sc->sge.txq[vi->first_txq]; 2073 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2074 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 2075 vi->rsrv_noflowq); 2076 2077 items[0] = m; 2078 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 2079 if (__predict_false(rc != 0)) 2080 m_freem(m); 2081 2082 return (rc); 2083 } 2084 2085 static void 2086 cxgbe_qflush(struct ifnet *ifp) 2087 { 2088 struct vi_info *vi = ifp->if_softc; 2089 struct sge_txq *txq; 2090 int i; 2091 2092 /* queues do not exist if !VI_INIT_DONE. */ 2093 if (vi->flags & VI_INIT_DONE) { 2094 for_each_txq(vi, i, txq) { 2095 TXQ_LOCK(txq); 2096 txq->eq.flags |= EQ_QFLUSH; 2097 TXQ_UNLOCK(txq); 2098 while (!mp_ring_is_idle(txq->r)) { 2099 mp_ring_check_drainage(txq->r, 0); 2100 pause("qflush", 1); 2101 } 2102 TXQ_LOCK(txq); 2103 txq->eq.flags &= ~EQ_QFLUSH; 2104 TXQ_UNLOCK(txq); 2105 } 2106 } 2107 if_qflush(ifp); 2108 } 2109 2110 static uint64_t 2111 vi_get_counter(struct ifnet *ifp, ift_counter c) 2112 { 2113 struct vi_info *vi = ifp->if_softc; 2114 struct fw_vi_stats_vf *s = &vi->stats; 2115 2116 vi_refresh_stats(vi->pi->adapter, vi); 2117 2118 switch (c) { 2119 case IFCOUNTER_IPACKETS: 2120 return (s->rx_bcast_frames + s->rx_mcast_frames + 2121 s->rx_ucast_frames); 2122 case IFCOUNTER_IERRORS: 2123 return (s->rx_err_frames); 2124 case IFCOUNTER_OPACKETS: 2125 return (s->tx_bcast_frames + s->tx_mcast_frames + 2126 s->tx_ucast_frames + s->tx_offload_frames); 2127 case IFCOUNTER_OERRORS: 2128 return (s->tx_drop_frames); 2129 case IFCOUNTER_IBYTES: 2130 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 2131 s->rx_ucast_bytes); 2132 case IFCOUNTER_OBYTES: 2133 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 2134 s->tx_ucast_bytes + s->tx_offload_bytes); 2135 case IFCOUNTER_IMCASTS: 2136 return (s->rx_mcast_frames); 2137 case IFCOUNTER_OMCASTS: 2138 return (s->tx_mcast_frames); 2139 case IFCOUNTER_OQDROPS: { 2140 uint64_t drops; 2141 2142 drops = 0; 2143 if (vi->flags & VI_INIT_DONE) { 2144 int i; 2145 struct sge_txq *txq; 2146 2147 for_each_txq(vi, i, txq) 2148 drops += counter_u64_fetch(txq->r->drops); 2149 } 2150 2151 return (drops); 2152 2153 } 2154 2155 default: 2156 return (if_get_counter_default(ifp, c)); 2157 } 2158 } 2159 2160 uint64_t 2161 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2162 { 2163 struct vi_info *vi = ifp->if_softc; 2164 struct port_info *pi = vi->pi; 2165 struct adapter *sc = pi->adapter; 2166 struct port_stats *s = &pi->stats; 2167 2168 if (pi->nvi > 1 || sc->flags & IS_VF) 2169 return (vi_get_counter(ifp, c)); 2170 2171 cxgbe_refresh_stats(sc, pi); 2172 2173 switch (c) { 2174 case IFCOUNTER_IPACKETS: 2175 return (s->rx_frames); 2176 2177 case IFCOUNTER_IERRORS: 2178 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2179 s->rx_fcs_err + s->rx_len_err); 2180 2181 case IFCOUNTER_OPACKETS: 2182 return (s->tx_frames); 2183 2184 case IFCOUNTER_OERRORS: 2185 return (s->tx_error_frames); 2186 2187 case IFCOUNTER_IBYTES: 2188 return (s->rx_octets); 2189 2190 case IFCOUNTER_OBYTES: 2191 return (s->tx_octets); 2192 2193 case IFCOUNTER_IMCASTS: 2194 return (s->rx_mcast_frames); 2195 2196 case IFCOUNTER_OMCASTS: 2197 return (s->tx_mcast_frames); 2198 2199 case IFCOUNTER_IQDROPS: 2200 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2201 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2202 s->rx_trunc3 + pi->tnl_cong_drops); 2203 2204 case IFCOUNTER_OQDROPS: { 2205 uint64_t drops; 2206 2207 drops = s->tx_drop; 2208 if (vi->flags & VI_INIT_DONE) { 2209 int i; 2210 struct sge_txq *txq; 2211 2212 for_each_txq(vi, i, txq) 2213 drops += counter_u64_fetch(txq->r->drops); 2214 } 2215 2216 return (drops); 2217 2218 } 2219 2220 default: 2221 return (if_get_counter_default(ifp, c)); 2222 } 2223 } 2224 2225 /* 2226 * The kernel picks a media from the list we had provided but we still validate 2227 * the requeste. 2228 */ 2229 int 2230 cxgbe_media_change(struct ifnet *ifp) 2231 { 2232 struct vi_info *vi = ifp->if_softc; 2233 struct port_info *pi = vi->pi; 2234 struct ifmedia *ifm = &pi->media; 2235 struct link_config *lc = &pi->link_cfg; 2236 struct adapter *sc = pi->adapter; 2237 int rc; 2238 2239 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2240 if (rc != 0) 2241 return (rc); 2242 PORT_LOCK(pi); 2243 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2244 /* ifconfig .. media autoselect */ 2245 if (!(lc->supported & FW_PORT_CAP32_ANEG)) { 2246 rc = ENOTSUP; /* AN not supported by transceiver */ 2247 goto done; 2248 } 2249 lc->requested_aneg = AUTONEG_ENABLE; 2250 lc->requested_speed = 0; 2251 lc->requested_fc |= PAUSE_AUTONEG; 2252 } else { 2253 lc->requested_aneg = AUTONEG_DISABLE; 2254 lc->requested_speed = 2255 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2256 lc->requested_fc = 0; 2257 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2258 lc->requested_fc |= PAUSE_RX; 2259 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2260 lc->requested_fc |= PAUSE_TX; 2261 } 2262 if (pi->up_vis > 0) { 2263 fixup_link_config(pi); 2264 rc = apply_link_config(pi); 2265 } 2266 done: 2267 PORT_UNLOCK(pi); 2268 end_synchronized_op(sc, 0); 2269 return (rc); 2270 } 2271 2272 /* 2273 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2274 * given speed. 2275 */ 2276 static int 2277 port_mword(struct port_info *pi, uint32_t speed) 2278 { 2279 2280 MPASS(speed & M_FW_PORT_CAP32_SPEED); 2281 MPASS(powerof2(speed)); 2282 2283 switch(pi->port_type) { 2284 case FW_PORT_TYPE_BT_SGMII: 2285 case FW_PORT_TYPE_BT_XFI: 2286 case FW_PORT_TYPE_BT_XAUI: 2287 /* BaseT */ 2288 switch (speed) { 2289 case FW_PORT_CAP32_SPEED_100M: 2290 return (IFM_100_T); 2291 case FW_PORT_CAP32_SPEED_1G: 2292 return (IFM_1000_T); 2293 case FW_PORT_CAP32_SPEED_10G: 2294 return (IFM_10G_T); 2295 } 2296 break; 2297 case FW_PORT_TYPE_KX4: 2298 if (speed == FW_PORT_CAP32_SPEED_10G) 2299 return (IFM_10G_KX4); 2300 break; 2301 case FW_PORT_TYPE_CX4: 2302 if (speed == FW_PORT_CAP32_SPEED_10G) 2303 return (IFM_10G_CX4); 2304 break; 2305 case FW_PORT_TYPE_KX: 2306 if (speed == FW_PORT_CAP32_SPEED_1G) 2307 return (IFM_1000_KX); 2308 break; 2309 case FW_PORT_TYPE_KR: 2310 case FW_PORT_TYPE_BP_AP: 2311 case FW_PORT_TYPE_BP4_AP: 2312 case FW_PORT_TYPE_BP40_BA: 2313 case FW_PORT_TYPE_KR4_100G: 2314 case FW_PORT_TYPE_KR_SFP28: 2315 case FW_PORT_TYPE_KR_XLAUI: 2316 switch (speed) { 2317 case FW_PORT_CAP32_SPEED_1G: 2318 return (IFM_1000_KX); 2319 case FW_PORT_CAP32_SPEED_10G: 2320 return (IFM_10G_KR); 2321 case FW_PORT_CAP32_SPEED_25G: 2322 return (IFM_25G_KR); 2323 case FW_PORT_CAP32_SPEED_40G: 2324 return (IFM_40G_KR4); 2325 case FW_PORT_CAP32_SPEED_50G: 2326 return (IFM_50G_KR2); 2327 case FW_PORT_CAP32_SPEED_100G: 2328 return (IFM_100G_KR4); 2329 } 2330 break; 2331 case FW_PORT_TYPE_FIBER_XFI: 2332 case FW_PORT_TYPE_FIBER_XAUI: 2333 case FW_PORT_TYPE_SFP: 2334 case FW_PORT_TYPE_QSFP_10G: 2335 case FW_PORT_TYPE_QSA: 2336 case FW_PORT_TYPE_QSFP: 2337 case FW_PORT_TYPE_CR4_QSFP: 2338 case FW_PORT_TYPE_CR_QSFP: 2339 case FW_PORT_TYPE_CR2_QSFP: 2340 case FW_PORT_TYPE_SFP28: 2341 /* Pluggable transceiver */ 2342 switch (pi->mod_type) { 2343 case FW_PORT_MOD_TYPE_LR: 2344 switch (speed) { 2345 case FW_PORT_CAP32_SPEED_1G: 2346 return (IFM_1000_LX); 2347 case FW_PORT_CAP32_SPEED_10G: 2348 return (IFM_10G_LR); 2349 case FW_PORT_CAP32_SPEED_25G: 2350 return (IFM_25G_LR); 2351 case FW_PORT_CAP32_SPEED_40G: 2352 return (IFM_40G_LR4); 2353 case FW_PORT_CAP32_SPEED_50G: 2354 return (IFM_50G_LR2); 2355 case FW_PORT_CAP32_SPEED_100G: 2356 return (IFM_100G_LR4); 2357 } 2358 break; 2359 case FW_PORT_MOD_TYPE_SR: 2360 switch (speed) { 2361 case FW_PORT_CAP32_SPEED_1G: 2362 return (IFM_1000_SX); 2363 case FW_PORT_CAP32_SPEED_10G: 2364 return (IFM_10G_SR); 2365 case FW_PORT_CAP32_SPEED_25G: 2366 return (IFM_25G_SR); 2367 case FW_PORT_CAP32_SPEED_40G: 2368 return (IFM_40G_SR4); 2369 case FW_PORT_CAP32_SPEED_50G: 2370 return (IFM_50G_SR2); 2371 case FW_PORT_CAP32_SPEED_100G: 2372 return (IFM_100G_SR4); 2373 } 2374 break; 2375 case FW_PORT_MOD_TYPE_ER: 2376 if (speed == FW_PORT_CAP32_SPEED_10G) 2377 return (IFM_10G_ER); 2378 break; 2379 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2380 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2381 switch (speed) { 2382 case FW_PORT_CAP32_SPEED_1G: 2383 return (IFM_1000_CX); 2384 case FW_PORT_CAP32_SPEED_10G: 2385 return (IFM_10G_TWINAX); 2386 case FW_PORT_CAP32_SPEED_25G: 2387 return (IFM_25G_CR); 2388 case FW_PORT_CAP32_SPEED_40G: 2389 return (IFM_40G_CR4); 2390 case FW_PORT_CAP32_SPEED_50G: 2391 return (IFM_50G_CR2); 2392 case FW_PORT_CAP32_SPEED_100G: 2393 return (IFM_100G_CR4); 2394 } 2395 break; 2396 case FW_PORT_MOD_TYPE_LRM: 2397 if (speed == FW_PORT_CAP32_SPEED_10G) 2398 return (IFM_10G_LRM); 2399 break; 2400 case FW_PORT_MOD_TYPE_NA: 2401 MPASS(0); /* Not pluggable? */ 2402 /* fall throough */ 2403 case FW_PORT_MOD_TYPE_ERROR: 2404 case FW_PORT_MOD_TYPE_UNKNOWN: 2405 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2406 break; 2407 case FW_PORT_MOD_TYPE_NONE: 2408 return (IFM_NONE); 2409 } 2410 break; 2411 case FW_PORT_TYPE_NONE: 2412 return (IFM_NONE); 2413 } 2414 2415 return (IFM_UNKNOWN); 2416 } 2417 2418 void 2419 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2420 { 2421 struct vi_info *vi = ifp->if_softc; 2422 struct port_info *pi = vi->pi; 2423 struct adapter *sc = pi->adapter; 2424 struct link_config *lc = &pi->link_cfg; 2425 2426 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2427 return; 2428 PORT_LOCK(pi); 2429 2430 if (pi->up_vis == 0) { 2431 /* 2432 * If all the interfaces are administratively down the firmware 2433 * does not report transceiver changes. Refresh port info here 2434 * so that ifconfig displays accurate ifmedia at all times. 2435 * This is the only reason we have a synchronized op in this 2436 * function. Just PORT_LOCK would have been enough otherwise. 2437 */ 2438 t4_update_port_info(pi); 2439 build_medialist(pi); 2440 } 2441 2442 /* ifm_status */ 2443 ifmr->ifm_status = IFM_AVALID; 2444 if (lc->link_ok == false) 2445 goto done; 2446 ifmr->ifm_status |= IFM_ACTIVE; 2447 2448 /* ifm_active */ 2449 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2450 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2451 if (lc->fc & PAUSE_RX) 2452 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2453 if (lc->fc & PAUSE_TX) 2454 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2455 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 2456 done: 2457 PORT_UNLOCK(pi); 2458 end_synchronized_op(sc, 0); 2459 } 2460 2461 static int 2462 vcxgbe_probe(device_t dev) 2463 { 2464 char buf[128]; 2465 struct vi_info *vi = device_get_softc(dev); 2466 2467 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2468 vi - vi->pi->vi); 2469 device_set_desc_copy(dev, buf); 2470 2471 return (BUS_PROBE_DEFAULT); 2472 } 2473 2474 static int 2475 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2476 { 2477 int func, index, rc; 2478 uint32_t param, val; 2479 2480 ASSERT_SYNCHRONIZED_OP(sc); 2481 2482 index = vi - pi->vi; 2483 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2484 KASSERT(index < nitems(vi_mac_funcs), 2485 ("%s: VI %s doesn't have a MAC func", __func__, 2486 device_get_nameunit(vi->dev))); 2487 func = vi_mac_funcs[index]; 2488 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2489 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 2490 if (rc < 0) { 2491 device_printf(vi->dev, "failed to allocate virtual interface %d" 2492 "for port %d: %d\n", index, pi->port_id, -rc); 2493 return (-rc); 2494 } 2495 vi->viid = rc; 2496 2497 if (vi->rss_size == 1) { 2498 /* 2499 * This VI didn't get a slice of the RSS table. Reduce the 2500 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2501 * configuration file (nvi, rssnvi for this PF) if this is a 2502 * problem. 2503 */ 2504 device_printf(vi->dev, "RSS table not available.\n"); 2505 vi->rss_base = 0xffff; 2506 2507 return (0); 2508 } 2509 2510 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2511 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2512 V_FW_PARAMS_PARAM_YZ(vi->viid); 2513 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2514 if (rc) 2515 vi->rss_base = 0xffff; 2516 else { 2517 MPASS((val >> 16) == vi->rss_size); 2518 vi->rss_base = val & 0xffff; 2519 } 2520 2521 return (0); 2522 } 2523 2524 static int 2525 vcxgbe_attach(device_t dev) 2526 { 2527 struct vi_info *vi; 2528 struct port_info *pi; 2529 struct adapter *sc; 2530 int rc; 2531 2532 vi = device_get_softc(dev); 2533 pi = vi->pi; 2534 sc = pi->adapter; 2535 2536 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2537 if (rc) 2538 return (rc); 2539 rc = alloc_extra_vi(sc, pi, vi); 2540 end_synchronized_op(sc, 0); 2541 if (rc) 2542 return (rc); 2543 2544 rc = cxgbe_vi_attach(dev, vi); 2545 if (rc) { 2546 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2547 return (rc); 2548 } 2549 return (0); 2550 } 2551 2552 static int 2553 vcxgbe_detach(device_t dev) 2554 { 2555 struct vi_info *vi; 2556 struct adapter *sc; 2557 2558 vi = device_get_softc(dev); 2559 sc = vi->pi->adapter; 2560 2561 doom_vi(sc, vi); 2562 2563 cxgbe_vi_detach(vi); 2564 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2565 2566 end_synchronized_op(sc, 0); 2567 2568 return (0); 2569 } 2570 2571 static struct callout fatal_callout; 2572 2573 static void 2574 delayed_panic(void *arg) 2575 { 2576 struct adapter *sc = arg; 2577 2578 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 2579 } 2580 2581 void 2582 t4_fatal_err(struct adapter *sc, bool fw_error) 2583 { 2584 2585 t4_shutdown_adapter(sc); 2586 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n", 2587 device_get_nameunit(sc->dev)); 2588 if (fw_error) { 2589 ASSERT_SYNCHRONIZED_OP(sc); 2590 sc->flags |= ADAP_ERR; 2591 } else { 2592 ADAPTER_LOCK(sc); 2593 sc->flags |= ADAP_ERR; 2594 ADAPTER_UNLOCK(sc); 2595 } 2596 2597 if (t4_panic_on_fatal_err) { 2598 log(LOG_ALERT, "%s: panic on fatal error after 30s", 2599 device_get_nameunit(sc->dev)); 2600 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 2601 } 2602 } 2603 2604 void 2605 t4_add_adapter(struct adapter *sc) 2606 { 2607 sx_xlock(&t4_list_lock); 2608 SLIST_INSERT_HEAD(&t4_list, sc, link); 2609 sx_xunlock(&t4_list_lock); 2610 } 2611 2612 int 2613 t4_map_bars_0_and_4(struct adapter *sc) 2614 { 2615 sc->regs_rid = PCIR_BAR(0); 2616 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2617 &sc->regs_rid, RF_ACTIVE); 2618 if (sc->regs_res == NULL) { 2619 device_printf(sc->dev, "cannot map registers.\n"); 2620 return (ENXIO); 2621 } 2622 sc->bt = rman_get_bustag(sc->regs_res); 2623 sc->bh = rman_get_bushandle(sc->regs_res); 2624 sc->mmio_len = rman_get_size(sc->regs_res); 2625 setbit(&sc->doorbells, DOORBELL_KDB); 2626 2627 sc->msix_rid = PCIR_BAR(4); 2628 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2629 &sc->msix_rid, RF_ACTIVE); 2630 if (sc->msix_res == NULL) { 2631 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2632 return (ENXIO); 2633 } 2634 2635 return (0); 2636 } 2637 2638 int 2639 t4_map_bar_2(struct adapter *sc) 2640 { 2641 2642 /* 2643 * T4: only iWARP driver uses the userspace doorbells. There is no need 2644 * to map it if RDMA is disabled. 2645 */ 2646 if (is_t4(sc) && sc->rdmacaps == 0) 2647 return (0); 2648 2649 sc->udbs_rid = PCIR_BAR(2); 2650 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2651 &sc->udbs_rid, RF_ACTIVE); 2652 if (sc->udbs_res == NULL) { 2653 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2654 return (ENXIO); 2655 } 2656 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2657 2658 if (chip_id(sc) >= CHELSIO_T5) { 2659 setbit(&sc->doorbells, DOORBELL_UDB); 2660 #if defined(__i386__) || defined(__amd64__) 2661 if (t5_write_combine) { 2662 int rc, mode; 2663 2664 /* 2665 * Enable write combining on BAR2. This is the 2666 * userspace doorbell BAR and is split into 128B 2667 * (UDBS_SEG_SIZE) doorbell regions, each associated 2668 * with an egress queue. The first 64B has the doorbell 2669 * and the second 64B can be used to submit a tx work 2670 * request with an implicit doorbell. 2671 */ 2672 2673 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2674 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2675 if (rc == 0) { 2676 clrbit(&sc->doorbells, DOORBELL_UDB); 2677 setbit(&sc->doorbells, DOORBELL_WCWR); 2678 setbit(&sc->doorbells, DOORBELL_UDBWC); 2679 } else { 2680 device_printf(sc->dev, 2681 "couldn't enable write combining: %d\n", 2682 rc); 2683 } 2684 2685 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2686 t4_write_reg(sc, A_SGE_STAT_CFG, 2687 V_STATSOURCE_T5(7) | mode); 2688 } 2689 #endif 2690 } 2691 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2692 2693 return (0); 2694 } 2695 2696 struct memwin_init { 2697 uint32_t base; 2698 uint32_t aperture; 2699 }; 2700 2701 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2702 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2703 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2704 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2705 }; 2706 2707 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2708 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2709 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2710 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2711 }; 2712 2713 static void 2714 setup_memwin(struct adapter *sc) 2715 { 2716 const struct memwin_init *mw_init; 2717 struct memwin *mw; 2718 int i; 2719 uint32_t bar0; 2720 2721 if (is_t4(sc)) { 2722 /* 2723 * Read low 32b of bar0 indirectly via the hardware backdoor 2724 * mechanism. Works from within PCI passthrough environments 2725 * too, where rman_get_start() can return a different value. We 2726 * need to program the T4 memory window decoders with the actual 2727 * addresses that will be coming across the PCIe link. 2728 */ 2729 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2730 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2731 2732 mw_init = &t4_memwin[0]; 2733 } else { 2734 /* T5+ use the relative offset inside the PCIe BAR */ 2735 bar0 = 0; 2736 2737 mw_init = &t5_memwin[0]; 2738 } 2739 2740 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2741 rw_init(&mw->mw_lock, "memory window access"); 2742 mw->mw_base = mw_init->base; 2743 mw->mw_aperture = mw_init->aperture; 2744 mw->mw_curpos = 0; 2745 t4_write_reg(sc, 2746 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2747 (mw->mw_base + bar0) | V_BIR(0) | 2748 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2749 rw_wlock(&mw->mw_lock); 2750 position_memwin(sc, i, 0); 2751 rw_wunlock(&mw->mw_lock); 2752 } 2753 2754 /* flush */ 2755 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2756 } 2757 2758 /* 2759 * Positions the memory window at the given address in the card's address space. 2760 * There are some alignment requirements and the actual position may be at an 2761 * address prior to the requested address. mw->mw_curpos always has the actual 2762 * position of the window. 2763 */ 2764 static void 2765 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2766 { 2767 struct memwin *mw; 2768 uint32_t pf; 2769 uint32_t reg; 2770 2771 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2772 mw = &sc->memwin[idx]; 2773 rw_assert(&mw->mw_lock, RA_WLOCKED); 2774 2775 if (is_t4(sc)) { 2776 pf = 0; 2777 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2778 } else { 2779 pf = V_PFNUM(sc->pf); 2780 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2781 } 2782 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2783 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2784 t4_read_reg(sc, reg); /* flush */ 2785 } 2786 2787 int 2788 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2789 int len, int rw) 2790 { 2791 struct memwin *mw; 2792 uint32_t mw_end, v; 2793 2794 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2795 2796 /* Memory can only be accessed in naturally aligned 4 byte units */ 2797 if (addr & 3 || len & 3 || len <= 0) 2798 return (EINVAL); 2799 2800 mw = &sc->memwin[idx]; 2801 while (len > 0) { 2802 rw_rlock(&mw->mw_lock); 2803 mw_end = mw->mw_curpos + mw->mw_aperture; 2804 if (addr >= mw_end || addr < mw->mw_curpos) { 2805 /* Will need to reposition the window */ 2806 if (!rw_try_upgrade(&mw->mw_lock)) { 2807 rw_runlock(&mw->mw_lock); 2808 rw_wlock(&mw->mw_lock); 2809 } 2810 rw_assert(&mw->mw_lock, RA_WLOCKED); 2811 position_memwin(sc, idx, addr); 2812 rw_downgrade(&mw->mw_lock); 2813 mw_end = mw->mw_curpos + mw->mw_aperture; 2814 } 2815 rw_assert(&mw->mw_lock, RA_RLOCKED); 2816 while (addr < mw_end && len > 0) { 2817 if (rw == 0) { 2818 v = t4_read_reg(sc, mw->mw_base + addr - 2819 mw->mw_curpos); 2820 *val++ = le32toh(v); 2821 } else { 2822 v = *val++; 2823 t4_write_reg(sc, mw->mw_base + addr - 2824 mw->mw_curpos, htole32(v)); 2825 } 2826 addr += 4; 2827 len -= 4; 2828 } 2829 rw_runlock(&mw->mw_lock); 2830 } 2831 2832 return (0); 2833 } 2834 2835 int 2836 alloc_atid_tab(struct tid_info *t, int flags) 2837 { 2838 int i; 2839 2840 MPASS(t->natids > 0); 2841 MPASS(t->atid_tab == NULL); 2842 2843 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2844 M_ZERO | flags); 2845 if (t->atid_tab == NULL) 2846 return (ENOMEM); 2847 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2848 t->afree = t->atid_tab; 2849 t->atids_in_use = 0; 2850 for (i = 1; i < t->natids; i++) 2851 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2852 t->atid_tab[t->natids - 1].next = NULL; 2853 2854 return (0); 2855 } 2856 2857 void 2858 free_atid_tab(struct tid_info *t) 2859 { 2860 2861 KASSERT(t->atids_in_use == 0, 2862 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2863 2864 if (mtx_initialized(&t->atid_lock)) 2865 mtx_destroy(&t->atid_lock); 2866 free(t->atid_tab, M_CXGBE); 2867 t->atid_tab = NULL; 2868 } 2869 2870 int 2871 alloc_atid(struct adapter *sc, void *ctx) 2872 { 2873 struct tid_info *t = &sc->tids; 2874 int atid = -1; 2875 2876 mtx_lock(&t->atid_lock); 2877 if (t->afree) { 2878 union aopen_entry *p = t->afree; 2879 2880 atid = p - t->atid_tab; 2881 MPASS(atid <= M_TID_TID); 2882 t->afree = p->next; 2883 p->data = ctx; 2884 t->atids_in_use++; 2885 } 2886 mtx_unlock(&t->atid_lock); 2887 return (atid); 2888 } 2889 2890 void * 2891 lookup_atid(struct adapter *sc, int atid) 2892 { 2893 struct tid_info *t = &sc->tids; 2894 2895 return (t->atid_tab[atid].data); 2896 } 2897 2898 void 2899 free_atid(struct adapter *sc, int atid) 2900 { 2901 struct tid_info *t = &sc->tids; 2902 union aopen_entry *p = &t->atid_tab[atid]; 2903 2904 mtx_lock(&t->atid_lock); 2905 p->next = t->afree; 2906 t->afree = p; 2907 t->atids_in_use--; 2908 mtx_unlock(&t->atid_lock); 2909 } 2910 2911 static void 2912 queue_tid_release(struct adapter *sc, int tid) 2913 { 2914 2915 CXGBE_UNIMPLEMENTED("deferred tid release"); 2916 } 2917 2918 void 2919 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2920 { 2921 struct wrqe *wr; 2922 struct cpl_tid_release *req; 2923 2924 wr = alloc_wrqe(sizeof(*req), ctrlq); 2925 if (wr == NULL) { 2926 queue_tid_release(sc, tid); /* defer */ 2927 return; 2928 } 2929 req = wrtod(wr); 2930 2931 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2932 2933 t4_wrq_tx(sc, wr); 2934 } 2935 2936 static int 2937 t4_range_cmp(const void *a, const void *b) 2938 { 2939 return ((const struct t4_range *)a)->start - 2940 ((const struct t4_range *)b)->start; 2941 } 2942 2943 /* 2944 * Verify that the memory range specified by the addr/len pair is valid within 2945 * the card's address space. 2946 */ 2947 static int 2948 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 2949 { 2950 struct t4_range mem_ranges[4], *r, *next; 2951 uint32_t em, addr_len; 2952 int i, n, remaining; 2953 2954 /* Memory can only be accessed in naturally aligned 4 byte units */ 2955 if (addr & 3 || len & 3 || len == 0) 2956 return (EINVAL); 2957 2958 /* Enabled memories */ 2959 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2960 2961 r = &mem_ranges[0]; 2962 n = 0; 2963 bzero(r, sizeof(mem_ranges)); 2964 if (em & F_EDRAM0_ENABLE) { 2965 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2966 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2967 if (r->size > 0) { 2968 r->start = G_EDRAM0_BASE(addr_len) << 20; 2969 if (addr >= r->start && 2970 addr + len <= r->start + r->size) 2971 return (0); 2972 r++; 2973 n++; 2974 } 2975 } 2976 if (em & F_EDRAM1_ENABLE) { 2977 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2978 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2979 if (r->size > 0) { 2980 r->start = G_EDRAM1_BASE(addr_len) << 20; 2981 if (addr >= r->start && 2982 addr + len <= r->start + r->size) 2983 return (0); 2984 r++; 2985 n++; 2986 } 2987 } 2988 if (em & F_EXT_MEM_ENABLE) { 2989 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2990 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2991 if (r->size > 0) { 2992 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2993 if (addr >= r->start && 2994 addr + len <= r->start + r->size) 2995 return (0); 2996 r++; 2997 n++; 2998 } 2999 } 3000 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 3001 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3002 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 3003 if (r->size > 0) { 3004 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 3005 if (addr >= r->start && 3006 addr + len <= r->start + r->size) 3007 return (0); 3008 r++; 3009 n++; 3010 } 3011 } 3012 MPASS(n <= nitems(mem_ranges)); 3013 3014 if (n > 1) { 3015 /* Sort and merge the ranges. */ 3016 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 3017 3018 /* Start from index 0 and examine the next n - 1 entries. */ 3019 r = &mem_ranges[0]; 3020 for (remaining = n - 1; remaining > 0; remaining--, r++) { 3021 3022 MPASS(r->size > 0); /* r is a valid entry. */ 3023 next = r + 1; 3024 MPASS(next->size > 0); /* and so is the next one. */ 3025 3026 while (r->start + r->size >= next->start) { 3027 /* Merge the next one into the current entry. */ 3028 r->size = max(r->start + r->size, 3029 next->start + next->size) - r->start; 3030 n--; /* One fewer entry in total. */ 3031 if (--remaining == 0) 3032 goto done; /* short circuit */ 3033 next++; 3034 } 3035 if (next != r + 1) { 3036 /* 3037 * Some entries were merged into r and next 3038 * points to the first valid entry that couldn't 3039 * be merged. 3040 */ 3041 MPASS(next->size > 0); /* must be valid */ 3042 memcpy(r + 1, next, remaining * sizeof(*r)); 3043 #ifdef INVARIANTS 3044 /* 3045 * This so that the foo->size assertion in the 3046 * next iteration of the loop do the right 3047 * thing for entries that were pulled up and are 3048 * no longer valid. 3049 */ 3050 MPASS(n < nitems(mem_ranges)); 3051 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 3052 sizeof(struct t4_range)); 3053 #endif 3054 } 3055 } 3056 done: 3057 /* Done merging the ranges. */ 3058 MPASS(n > 0); 3059 r = &mem_ranges[0]; 3060 for (i = 0; i < n; i++, r++) { 3061 if (addr >= r->start && 3062 addr + len <= r->start + r->size) 3063 return (0); 3064 } 3065 } 3066 3067 return (EFAULT); 3068 } 3069 3070 static int 3071 fwmtype_to_hwmtype(int mtype) 3072 { 3073 3074 switch (mtype) { 3075 case FW_MEMTYPE_EDC0: 3076 return (MEM_EDC0); 3077 case FW_MEMTYPE_EDC1: 3078 return (MEM_EDC1); 3079 case FW_MEMTYPE_EXTMEM: 3080 return (MEM_MC0); 3081 case FW_MEMTYPE_EXTMEM1: 3082 return (MEM_MC1); 3083 default: 3084 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 3085 } 3086 } 3087 3088 /* 3089 * Verify that the memory range specified by the memtype/offset/len pair is 3090 * valid and lies entirely within the memtype specified. The global address of 3091 * the start of the range is returned in addr. 3092 */ 3093 static int 3094 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 3095 uint32_t *addr) 3096 { 3097 uint32_t em, addr_len, maddr; 3098 3099 /* Memory can only be accessed in naturally aligned 4 byte units */ 3100 if (off & 3 || len & 3 || len == 0) 3101 return (EINVAL); 3102 3103 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3104 switch (fwmtype_to_hwmtype(mtype)) { 3105 case MEM_EDC0: 3106 if (!(em & F_EDRAM0_ENABLE)) 3107 return (EINVAL); 3108 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3109 maddr = G_EDRAM0_BASE(addr_len) << 20; 3110 break; 3111 case MEM_EDC1: 3112 if (!(em & F_EDRAM1_ENABLE)) 3113 return (EINVAL); 3114 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3115 maddr = G_EDRAM1_BASE(addr_len) << 20; 3116 break; 3117 case MEM_MC: 3118 if (!(em & F_EXT_MEM_ENABLE)) 3119 return (EINVAL); 3120 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3121 maddr = G_EXT_MEM_BASE(addr_len) << 20; 3122 break; 3123 case MEM_MC1: 3124 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 3125 return (EINVAL); 3126 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3127 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 3128 break; 3129 default: 3130 return (EINVAL); 3131 } 3132 3133 *addr = maddr + off; /* global address */ 3134 return (validate_mem_range(sc, *addr, len)); 3135 } 3136 3137 static int 3138 fixup_devlog_params(struct adapter *sc) 3139 { 3140 struct devlog_params *dparams = &sc->params.devlog; 3141 int rc; 3142 3143 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 3144 dparams->size, &dparams->addr); 3145 3146 return (rc); 3147 } 3148 3149 static void 3150 update_nirq(struct intrs_and_queues *iaq, int nports) 3151 { 3152 int extra = T4_EXTRA_INTR; 3153 3154 iaq->nirq = extra; 3155 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 3156 iaq->nirq += nports * (iaq->num_vis - 1) * 3157 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 3158 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 3159 } 3160 3161 /* 3162 * Adjust requirements to fit the number of interrupts available. 3163 */ 3164 static void 3165 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 3166 int navail) 3167 { 3168 int old_nirq; 3169 const int nports = sc->params.nports; 3170 3171 MPASS(nports > 0); 3172 MPASS(navail > 0); 3173 3174 bzero(iaq, sizeof(*iaq)); 3175 iaq->intr_type = itype; 3176 iaq->num_vis = t4_num_vis; 3177 iaq->ntxq = t4_ntxq; 3178 iaq->ntxq_vi = t4_ntxq_vi; 3179 iaq->nrxq = t4_nrxq; 3180 iaq->nrxq_vi = t4_nrxq_vi; 3181 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3182 if (is_offload(sc) || is_ethoffload(sc)) { 3183 iaq->nofldtxq = t4_nofldtxq; 3184 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3185 } 3186 #endif 3187 #ifdef TCP_OFFLOAD 3188 if (is_offload(sc)) { 3189 iaq->nofldrxq = t4_nofldrxq; 3190 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3191 } 3192 #endif 3193 #ifdef DEV_NETMAP 3194 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3195 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3196 #endif 3197 3198 update_nirq(iaq, nports); 3199 if (iaq->nirq <= navail && 3200 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3201 /* 3202 * This is the normal case -- there are enough interrupts for 3203 * everything. 3204 */ 3205 goto done; 3206 } 3207 3208 /* 3209 * If extra VIs have been configured try reducing their count and see if 3210 * that works. 3211 */ 3212 while (iaq->num_vis > 1) { 3213 iaq->num_vis--; 3214 update_nirq(iaq, nports); 3215 if (iaq->nirq <= navail && 3216 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3217 device_printf(sc->dev, "virtual interfaces per port " 3218 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3219 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3220 "itype %d, navail %u, nirq %d.\n", 3221 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3222 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3223 itype, navail, iaq->nirq); 3224 goto done; 3225 } 3226 } 3227 3228 /* 3229 * Extra VIs will not be created. Log a message if they were requested. 3230 */ 3231 MPASS(iaq->num_vis == 1); 3232 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3233 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3234 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3235 if (iaq->num_vis != t4_num_vis) { 3236 device_printf(sc->dev, "extra virtual interfaces disabled. " 3237 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3238 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3239 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3240 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3241 } 3242 3243 /* 3244 * Keep reducing the number of NIC rx queues to the next lower power of 3245 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3246 * if that works. 3247 */ 3248 do { 3249 if (iaq->nrxq > 1) { 3250 do { 3251 iaq->nrxq--; 3252 } while (!powerof2(iaq->nrxq)); 3253 } 3254 if (iaq->nofldrxq > 1) 3255 iaq->nofldrxq >>= 1; 3256 3257 old_nirq = iaq->nirq; 3258 update_nirq(iaq, nports); 3259 if (iaq->nirq <= navail && 3260 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3261 device_printf(sc->dev, "running with reduced number of " 3262 "rx queues because of shortage of interrupts. " 3263 "nrxq=%u, nofldrxq=%u. " 3264 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3265 iaq->nofldrxq, itype, navail, iaq->nirq); 3266 goto done; 3267 } 3268 } while (old_nirq != iaq->nirq); 3269 3270 /* One interrupt for everything. Ugh. */ 3271 device_printf(sc->dev, "running with minimal number of queues. " 3272 "itype %d, navail %u.\n", itype, navail); 3273 iaq->nirq = 1; 3274 MPASS(iaq->nrxq == 1); 3275 iaq->ntxq = 1; 3276 if (iaq->nofldrxq > 1) 3277 iaq->nofldtxq = 1; 3278 done: 3279 MPASS(iaq->num_vis > 0); 3280 if (iaq->num_vis > 1) { 3281 MPASS(iaq->nrxq_vi > 0); 3282 MPASS(iaq->ntxq_vi > 0); 3283 } 3284 MPASS(iaq->nirq > 0); 3285 MPASS(iaq->nrxq > 0); 3286 MPASS(iaq->ntxq > 0); 3287 if (itype == INTR_MSI) { 3288 MPASS(powerof2(iaq->nirq)); 3289 } 3290 } 3291 3292 static int 3293 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3294 { 3295 int rc, itype, navail, nalloc; 3296 3297 for (itype = INTR_MSIX; itype; itype >>= 1) { 3298 3299 if ((itype & t4_intr_types) == 0) 3300 continue; /* not allowed */ 3301 3302 if (itype == INTR_MSIX) 3303 navail = pci_msix_count(sc->dev); 3304 else if (itype == INTR_MSI) 3305 navail = pci_msi_count(sc->dev); 3306 else 3307 navail = 1; 3308 restart: 3309 if (navail == 0) 3310 continue; 3311 3312 calculate_iaq(sc, iaq, itype, navail); 3313 nalloc = iaq->nirq; 3314 rc = 0; 3315 if (itype == INTR_MSIX) 3316 rc = pci_alloc_msix(sc->dev, &nalloc); 3317 else if (itype == INTR_MSI) 3318 rc = pci_alloc_msi(sc->dev, &nalloc); 3319 3320 if (rc == 0 && nalloc > 0) { 3321 if (nalloc == iaq->nirq) 3322 return (0); 3323 3324 /* 3325 * Didn't get the number requested. Use whatever number 3326 * the kernel is willing to allocate. 3327 */ 3328 device_printf(sc->dev, "fewer vectors than requested, " 3329 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3330 itype, iaq->nirq, nalloc); 3331 pci_release_msi(sc->dev); 3332 navail = nalloc; 3333 goto restart; 3334 } 3335 3336 device_printf(sc->dev, 3337 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3338 itype, rc, iaq->nirq, nalloc); 3339 } 3340 3341 device_printf(sc->dev, 3342 "failed to find a usable interrupt type. " 3343 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3344 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3345 3346 return (ENXIO); 3347 } 3348 3349 #define FW_VERSION(chip) ( \ 3350 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3351 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3352 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3353 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3354 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3355 3356 /* Just enough of fw_hdr to cover all version info. */ 3357 struct fw_h { 3358 __u8 ver; 3359 __u8 chip; 3360 __be16 len512; 3361 __be32 fw_ver; 3362 __be32 tp_microcode_ver; 3363 __u8 intfver_nic; 3364 __u8 intfver_vnic; 3365 __u8 intfver_ofld; 3366 __u8 intfver_ri; 3367 __u8 intfver_iscsipdu; 3368 __u8 intfver_iscsi; 3369 __u8 intfver_fcoepdu; 3370 __u8 intfver_fcoe; 3371 }; 3372 /* Spot check a couple of fields. */ 3373 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 3374 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 3375 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 3376 3377 struct fw_info { 3378 uint8_t chip; 3379 char *kld_name; 3380 char *fw_mod_name; 3381 struct fw_h fw_h; 3382 } fw_info[] = { 3383 { 3384 .chip = CHELSIO_T4, 3385 .kld_name = "t4fw_cfg", 3386 .fw_mod_name = "t4fw", 3387 .fw_h = { 3388 .chip = FW_HDR_CHIP_T4, 3389 .fw_ver = htobe32(FW_VERSION(T4)), 3390 .intfver_nic = FW_INTFVER(T4, NIC), 3391 .intfver_vnic = FW_INTFVER(T4, VNIC), 3392 .intfver_ofld = FW_INTFVER(T4, OFLD), 3393 .intfver_ri = FW_INTFVER(T4, RI), 3394 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3395 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3396 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3397 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3398 }, 3399 }, { 3400 .chip = CHELSIO_T5, 3401 .kld_name = "t5fw_cfg", 3402 .fw_mod_name = "t5fw", 3403 .fw_h = { 3404 .chip = FW_HDR_CHIP_T5, 3405 .fw_ver = htobe32(FW_VERSION(T5)), 3406 .intfver_nic = FW_INTFVER(T5, NIC), 3407 .intfver_vnic = FW_INTFVER(T5, VNIC), 3408 .intfver_ofld = FW_INTFVER(T5, OFLD), 3409 .intfver_ri = FW_INTFVER(T5, RI), 3410 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3411 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3412 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3413 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3414 }, 3415 }, { 3416 .chip = CHELSIO_T6, 3417 .kld_name = "t6fw_cfg", 3418 .fw_mod_name = "t6fw", 3419 .fw_h = { 3420 .chip = FW_HDR_CHIP_T6, 3421 .fw_ver = htobe32(FW_VERSION(T6)), 3422 .intfver_nic = FW_INTFVER(T6, NIC), 3423 .intfver_vnic = FW_INTFVER(T6, VNIC), 3424 .intfver_ofld = FW_INTFVER(T6, OFLD), 3425 .intfver_ri = FW_INTFVER(T6, RI), 3426 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3427 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3428 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3429 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3430 }, 3431 } 3432 }; 3433 3434 static struct fw_info * 3435 find_fw_info(int chip) 3436 { 3437 int i; 3438 3439 for (i = 0; i < nitems(fw_info); i++) { 3440 if (fw_info[i].chip == chip) 3441 return (&fw_info[i]); 3442 } 3443 return (NULL); 3444 } 3445 3446 /* 3447 * Is the given firmware API compatible with the one the driver was compiled 3448 * with? 3449 */ 3450 static int 3451 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 3452 { 3453 3454 /* short circuit if it's the exact same firmware version */ 3455 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3456 return (1); 3457 3458 /* 3459 * XXX: Is this too conservative? Perhaps I should limit this to the 3460 * features that are supported in the driver. 3461 */ 3462 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3463 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3464 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3465 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3466 return (1); 3467 #undef SAME_INTF 3468 3469 return (0); 3470 } 3471 3472 static int 3473 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 3474 const struct firmware **fw) 3475 { 3476 struct fw_info *fw_info; 3477 3478 *dcfg = NULL; 3479 if (fw != NULL) 3480 *fw = NULL; 3481 3482 fw_info = find_fw_info(chip_id(sc)); 3483 if (fw_info == NULL) { 3484 device_printf(sc->dev, 3485 "unable to look up firmware information for chip %d.\n", 3486 chip_id(sc)); 3487 return (EINVAL); 3488 } 3489 3490 *dcfg = firmware_get(fw_info->kld_name); 3491 if (*dcfg != NULL) { 3492 if (fw != NULL) 3493 *fw = firmware_get(fw_info->fw_mod_name); 3494 return (0); 3495 } 3496 3497 return (ENOENT); 3498 } 3499 3500 static void 3501 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 3502 const struct firmware *fw) 3503 { 3504 3505 if (fw != NULL) 3506 firmware_put(fw, FIRMWARE_UNLOAD); 3507 if (dcfg != NULL) 3508 firmware_put(dcfg, FIRMWARE_UNLOAD); 3509 } 3510 3511 /* 3512 * Return values: 3513 * 0 means no firmware install attempted. 3514 * ERESTART means a firmware install was attempted and was successful. 3515 * +ve errno means a firmware install was attempted but failed. 3516 */ 3517 static int 3518 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 3519 const struct fw_h *drv_fw, const char *reason, int *already) 3520 { 3521 const struct firmware *cfg, *fw; 3522 const uint32_t c = be32toh(card_fw->fw_ver); 3523 uint32_t d, k; 3524 int rc, fw_install; 3525 struct fw_h bundled_fw; 3526 bool load_attempted; 3527 3528 cfg = fw = NULL; 3529 load_attempted = false; 3530 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 3531 3532 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 3533 if (t4_fw_install < 0) { 3534 rc = load_fw_module(sc, &cfg, &fw); 3535 if (rc != 0 || fw == NULL) { 3536 device_printf(sc->dev, 3537 "failed to load firmware module: %d. cfg %p, fw %p;" 3538 " will use compiled-in firmware version for" 3539 "hw.cxgbe.fw_install checks.\n", 3540 rc, cfg, fw); 3541 } else { 3542 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 3543 } 3544 load_attempted = true; 3545 } 3546 d = be32toh(bundled_fw.fw_ver); 3547 3548 if (reason != NULL) 3549 goto install; 3550 3551 if ((sc->flags & FW_OK) == 0) { 3552 3553 if (c == 0xffffffff) { 3554 reason = "missing"; 3555 goto install; 3556 } 3557 3558 rc = 0; 3559 goto done; 3560 } 3561 3562 if (!fw_compatible(card_fw, &bundled_fw)) { 3563 reason = "incompatible or unusable"; 3564 goto install; 3565 } 3566 3567 if (d > c) { 3568 reason = "older than the version bundled with this driver"; 3569 goto install; 3570 } 3571 3572 if (fw_install == 2 && d != c) { 3573 reason = "different than the version bundled with this driver"; 3574 goto install; 3575 } 3576 3577 /* No reason to do anything to the firmware already on the card. */ 3578 rc = 0; 3579 goto done; 3580 3581 install: 3582 rc = 0; 3583 if ((*already)++) 3584 goto done; 3585 3586 if (fw_install == 0) { 3587 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3588 "but the driver is prohibited from installing a firmware " 3589 "on the card.\n", 3590 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3591 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3592 3593 goto done; 3594 } 3595 3596 /* 3597 * We'll attempt to install a firmware. Load the module first (if it 3598 * hasn't been loaded already). 3599 */ 3600 if (!load_attempted) { 3601 rc = load_fw_module(sc, &cfg, &fw); 3602 if (rc != 0 || fw == NULL) { 3603 device_printf(sc->dev, 3604 "failed to load firmware module: %d. cfg %p, fw %p\n", 3605 rc, cfg, fw); 3606 /* carry on */ 3607 } 3608 } 3609 if (fw == NULL) { 3610 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3611 "but the driver cannot take corrective action because it " 3612 "is unable to load the firmware module.\n", 3613 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3614 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3615 rc = sc->flags & FW_OK ? 0 : ENOENT; 3616 goto done; 3617 } 3618 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 3619 if (k != d) { 3620 MPASS(t4_fw_install > 0); 3621 device_printf(sc->dev, 3622 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 3623 "expecting (%u.%u.%u.%u) and will not be used.\n", 3624 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3625 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 3626 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3627 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3628 rc = sc->flags & FW_OK ? 0 : EINVAL; 3629 goto done; 3630 } 3631 3632 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3633 "installing firmware %u.%u.%u.%u on card.\n", 3634 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3635 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3636 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3637 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3638 3639 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3640 if (rc != 0) { 3641 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 3642 } else { 3643 /* Installed successfully, update the cached header too. */ 3644 rc = ERESTART; 3645 memcpy(card_fw, fw->data, sizeof(*card_fw)); 3646 } 3647 done: 3648 unload_fw_module(sc, cfg, fw); 3649 3650 return (rc); 3651 } 3652 3653 /* 3654 * Establish contact with the firmware and attempt to become the master driver. 3655 * 3656 * A firmware will be installed to the card if needed (if the driver is allowed 3657 * to do so). 3658 */ 3659 static int 3660 contact_firmware(struct adapter *sc) 3661 { 3662 int rc, already = 0; 3663 enum dev_state state; 3664 struct fw_info *fw_info; 3665 struct fw_hdr *card_fw; /* fw on the card */ 3666 const struct fw_h *drv_fw; 3667 3668 fw_info = find_fw_info(chip_id(sc)); 3669 if (fw_info == NULL) { 3670 device_printf(sc->dev, 3671 "unable to look up firmware information for chip %d.\n", 3672 chip_id(sc)); 3673 return (EINVAL); 3674 } 3675 drv_fw = &fw_info->fw_h; 3676 3677 /* Read the header of the firmware on the card */ 3678 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3679 restart: 3680 rc = -t4_get_fw_hdr(sc, card_fw); 3681 if (rc != 0) { 3682 device_printf(sc->dev, 3683 "unable to read firmware header from card's flash: %d\n", 3684 rc); 3685 goto done; 3686 } 3687 3688 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 3689 &already); 3690 if (rc == ERESTART) 3691 goto restart; 3692 if (rc != 0) 3693 goto done; 3694 3695 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3696 if (rc < 0 || state == DEV_STATE_ERR) { 3697 rc = -rc; 3698 device_printf(sc->dev, 3699 "failed to connect to the firmware: %d, %d. " 3700 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3701 #if 0 3702 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3703 "not responding properly to HELLO", &already) == ERESTART) 3704 goto restart; 3705 #endif 3706 goto done; 3707 } 3708 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 3709 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 3710 3711 if (rc == sc->pf) { 3712 sc->flags |= MASTER_PF; 3713 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3714 NULL, &already); 3715 if (rc == ERESTART) 3716 rc = 0; 3717 else if (rc != 0) 3718 goto done; 3719 } else if (state == DEV_STATE_UNINIT) { 3720 /* 3721 * We didn't get to be the master so we definitely won't be 3722 * configuring the chip. It's a bug if someone else hasn't 3723 * configured it already. 3724 */ 3725 device_printf(sc->dev, "couldn't be master(%d), " 3726 "device not already initialized either(%d). " 3727 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3728 rc = EPROTO; 3729 goto done; 3730 } else { 3731 /* 3732 * Some other PF is the master and has configured the chip. 3733 * This is allowed but untested. 3734 */ 3735 device_printf(sc->dev, "PF%d is master, device state %d. " 3736 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3737 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 3738 sc->cfcsum = 0; 3739 rc = 0; 3740 } 3741 done: 3742 if (rc != 0 && sc->flags & FW_OK) { 3743 t4_fw_bye(sc, sc->mbox); 3744 sc->flags &= ~FW_OK; 3745 } 3746 free(card_fw, M_CXGBE); 3747 return (rc); 3748 } 3749 3750 static int 3751 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 3752 uint32_t mtype, uint32_t moff) 3753 { 3754 struct fw_info *fw_info; 3755 const struct firmware *dcfg, *rcfg = NULL; 3756 const uint32_t *cfdata; 3757 uint32_t cflen, addr; 3758 int rc; 3759 3760 load_fw_module(sc, &dcfg, NULL); 3761 3762 /* Card specific interpretation of "default". */ 3763 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3764 if (pci_get_device(sc->dev) == 0x440a) 3765 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 3766 if (is_fpga(sc)) 3767 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 3768 } 3769 3770 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3771 if (dcfg == NULL) { 3772 device_printf(sc->dev, 3773 "KLD with default config is not available.\n"); 3774 rc = ENOENT; 3775 goto done; 3776 } 3777 cfdata = dcfg->data; 3778 cflen = dcfg->datasize & ~3; 3779 } else { 3780 char s[32]; 3781 3782 fw_info = find_fw_info(chip_id(sc)); 3783 if (fw_info == NULL) { 3784 device_printf(sc->dev, 3785 "unable to look up firmware information for chip %d.\n", 3786 chip_id(sc)); 3787 rc = EINVAL; 3788 goto done; 3789 } 3790 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 3791 3792 rcfg = firmware_get(s); 3793 if (rcfg == NULL) { 3794 device_printf(sc->dev, 3795 "unable to load module \"%s\" for configuration " 3796 "profile \"%s\".\n", s, cfg_file); 3797 rc = ENOENT; 3798 goto done; 3799 } 3800 cfdata = rcfg->data; 3801 cflen = rcfg->datasize & ~3; 3802 } 3803 3804 if (cflen > FLASH_CFG_MAX_SIZE) { 3805 device_printf(sc->dev, 3806 "config file too long (%d, max allowed is %d).\n", 3807 cflen, FLASH_CFG_MAX_SIZE); 3808 rc = EINVAL; 3809 goto done; 3810 } 3811 3812 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3813 if (rc != 0) { 3814 device_printf(sc->dev, 3815 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 3816 __func__, mtype, moff, cflen, rc); 3817 rc = EINVAL; 3818 goto done; 3819 } 3820 write_via_memwin(sc, 2, addr, cfdata, cflen); 3821 done: 3822 if (rcfg != NULL) 3823 firmware_put(rcfg, FIRMWARE_UNLOAD); 3824 unload_fw_module(sc, dcfg, NULL); 3825 return (rc); 3826 } 3827 3828 struct caps_allowed { 3829 uint16_t nbmcaps; 3830 uint16_t linkcaps; 3831 uint16_t switchcaps; 3832 uint16_t niccaps; 3833 uint16_t toecaps; 3834 uint16_t rdmacaps; 3835 uint16_t cryptocaps; 3836 uint16_t iscsicaps; 3837 uint16_t fcoecaps; 3838 }; 3839 3840 #define FW_PARAM_DEV(param) \ 3841 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3842 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3843 #define FW_PARAM_PFVF(param) \ 3844 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3845 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3846 3847 /* 3848 * Provide a configuration profile to the firmware and have it initialize the 3849 * chip accordingly. This may involve uploading a configuration file to the 3850 * card. 3851 */ 3852 static int 3853 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 3854 const struct caps_allowed *caps_allowed) 3855 { 3856 int rc; 3857 struct fw_caps_config_cmd caps; 3858 uint32_t mtype, moff, finicsum, cfcsum, param, val; 3859 3860 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3861 if (rc != 0) { 3862 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3863 return (rc); 3864 } 3865 3866 bzero(&caps, sizeof(caps)); 3867 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3868 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3869 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 3870 mtype = 0; 3871 moff = 0; 3872 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3873 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 3874 mtype = FW_MEMTYPE_FLASH; 3875 moff = t4_flash_cfg_addr(sc); 3876 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3877 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3878 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3879 FW_LEN16(caps)); 3880 } else { 3881 /* 3882 * Ask the firmware where it wants us to upload the config file. 3883 */ 3884 param = FW_PARAM_DEV(CF); 3885 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3886 if (rc != 0) { 3887 /* No support for config file? Shouldn't happen. */ 3888 device_printf(sc->dev, 3889 "failed to query config file location: %d.\n", rc); 3890 goto done; 3891 } 3892 mtype = G_FW_PARAMS_PARAM_Y(val); 3893 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3894 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3895 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3896 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3897 FW_LEN16(caps)); 3898 3899 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 3900 if (rc != 0) { 3901 device_printf(sc->dev, 3902 "failed to upload config file to card: %d.\n", rc); 3903 goto done; 3904 } 3905 } 3906 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3907 if (rc != 0) { 3908 device_printf(sc->dev, "failed to pre-process config file: %d " 3909 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3910 goto done; 3911 } 3912 3913 finicsum = be32toh(caps.finicsum); 3914 cfcsum = be32toh(caps.cfcsum); /* actual */ 3915 if (finicsum != cfcsum) { 3916 device_printf(sc->dev, 3917 "WARNING: config file checksum mismatch: %08x %08x\n", 3918 finicsum, cfcsum); 3919 } 3920 sc->cfcsum = cfcsum; 3921 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 3922 3923 /* 3924 * Let the firmware know what features will (not) be used so it can tune 3925 * things accordingly. 3926 */ 3927 #define LIMIT_CAPS(x) do { \ 3928 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 3929 } while (0) 3930 LIMIT_CAPS(nbm); 3931 LIMIT_CAPS(link); 3932 LIMIT_CAPS(switch); 3933 LIMIT_CAPS(nic); 3934 LIMIT_CAPS(toe); 3935 LIMIT_CAPS(rdma); 3936 LIMIT_CAPS(crypto); 3937 LIMIT_CAPS(iscsi); 3938 LIMIT_CAPS(fcoe); 3939 #undef LIMIT_CAPS 3940 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3941 /* 3942 * TOE and hashfilters are mutually exclusive. It is a config 3943 * file or firmware bug if both are reported as available. Try 3944 * to cope with the situation in non-debug builds by disabling 3945 * TOE. 3946 */ 3947 MPASS(caps.toecaps == 0); 3948 3949 caps.toecaps = 0; 3950 caps.rdmacaps = 0; 3951 caps.iscsicaps = 0; 3952 } 3953 3954 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3955 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3956 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3957 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3958 if (rc != 0) { 3959 device_printf(sc->dev, 3960 "failed to process config file: %d.\n", rc); 3961 goto done; 3962 } 3963 3964 t4_tweak_chip_settings(sc); 3965 set_params__pre_init(sc); 3966 3967 /* get basic stuff going */ 3968 rc = -t4_fw_initialize(sc, sc->mbox); 3969 if (rc != 0) { 3970 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 3971 goto done; 3972 } 3973 done: 3974 return (rc); 3975 } 3976 3977 /* 3978 * Partition chip resources for use between various PFs, VFs, etc. 3979 */ 3980 static int 3981 partition_resources(struct adapter *sc) 3982 { 3983 char cfg_file[sizeof(t4_cfg_file)]; 3984 struct caps_allowed caps_allowed; 3985 int rc; 3986 bool fallback; 3987 3988 /* Only the master driver gets to configure the chip resources. */ 3989 MPASS(sc->flags & MASTER_PF); 3990 3991 #define COPY_CAPS(x) do { \ 3992 caps_allowed.x##caps = t4_##x##caps_allowed; \ 3993 } while (0) 3994 bzero(&caps_allowed, sizeof(caps_allowed)); 3995 COPY_CAPS(nbm); 3996 COPY_CAPS(link); 3997 COPY_CAPS(switch); 3998 COPY_CAPS(nic); 3999 COPY_CAPS(toe); 4000 COPY_CAPS(rdma); 4001 COPY_CAPS(crypto); 4002 COPY_CAPS(iscsi); 4003 COPY_CAPS(fcoe); 4004 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 4005 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 4006 retry: 4007 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 4008 if (rc != 0 && fallback) { 4009 device_printf(sc->dev, 4010 "failed (%d) to configure card with \"%s\" profile, " 4011 "will fall back to a basic configuration and retry.\n", 4012 rc, cfg_file); 4013 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 4014 bzero(&caps_allowed, sizeof(caps_allowed)); 4015 COPY_CAPS(nbm); 4016 COPY_CAPS(link); 4017 COPY_CAPS(switch); 4018 COPY_CAPS(nic); 4019 fallback = false; 4020 goto retry; 4021 } 4022 #undef COPY_CAPS 4023 return (rc); 4024 } 4025 4026 /* 4027 * Retrieve parameters that are needed (or nice to have) very early. 4028 */ 4029 static int 4030 get_params__pre_init(struct adapter *sc) 4031 { 4032 int rc; 4033 uint32_t param[2], val[2]; 4034 4035 t4_get_version_info(sc); 4036 4037 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 4038 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 4039 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 4040 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 4041 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 4042 4043 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 4044 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 4045 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 4046 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 4047 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 4048 4049 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 4050 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 4051 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 4052 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 4053 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 4054 4055 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 4056 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 4057 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 4058 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 4059 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 4060 4061 param[0] = FW_PARAM_DEV(PORTVEC); 4062 param[1] = FW_PARAM_DEV(CCLK); 4063 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4064 if (rc != 0) { 4065 device_printf(sc->dev, 4066 "failed to query parameters (pre_init): %d.\n", rc); 4067 return (rc); 4068 } 4069 4070 sc->params.portvec = val[0]; 4071 sc->params.nports = bitcount32(val[0]); 4072 sc->params.vpd.cclk = val[1]; 4073 4074 /* Read device log parameters. */ 4075 rc = -t4_init_devlog_params(sc, 1); 4076 if (rc == 0) 4077 fixup_devlog_params(sc); 4078 else { 4079 device_printf(sc->dev, 4080 "failed to get devlog parameters: %d.\n", rc); 4081 rc = 0; /* devlog isn't critical for device operation */ 4082 } 4083 4084 return (rc); 4085 } 4086 4087 /* 4088 * Any params that need to be set before FW_INITIALIZE. 4089 */ 4090 static int 4091 set_params__pre_init(struct adapter *sc) 4092 { 4093 int rc = 0; 4094 uint32_t param, val; 4095 4096 if (chip_id(sc) >= CHELSIO_T6) { 4097 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 4098 val = 1; 4099 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4100 /* firmwares < 1.20.1.0 do not have this param. */ 4101 if (rc == FW_EINVAL && sc->params.fw_vers < 4102 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4103 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) { 4104 rc = 0; 4105 } 4106 if (rc != 0) { 4107 device_printf(sc->dev, 4108 "failed to enable high priority filters :%d.\n", 4109 rc); 4110 } 4111 } 4112 4113 /* Enable opaque VIIDs with firmwares that support it. */ 4114 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 4115 val = 1; 4116 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4117 if (rc == 0 && val == 1) 4118 sc->params.viid_smt_extn_support = true; 4119 else 4120 sc->params.viid_smt_extn_support = false; 4121 4122 return (rc); 4123 } 4124 4125 /* 4126 * Retrieve various parameters that are of interest to the driver. The device 4127 * has been initialized by the firmware at this point. 4128 */ 4129 static int 4130 get_params__post_init(struct adapter *sc) 4131 { 4132 int rc; 4133 uint32_t param[7], val[7]; 4134 struct fw_caps_config_cmd caps; 4135 4136 param[0] = FW_PARAM_PFVF(IQFLINT_START); 4137 param[1] = FW_PARAM_PFVF(EQ_START); 4138 param[2] = FW_PARAM_PFVF(FILTER_START); 4139 param[3] = FW_PARAM_PFVF(FILTER_END); 4140 param[4] = FW_PARAM_PFVF(L2T_START); 4141 param[5] = FW_PARAM_PFVF(L2T_END); 4142 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 4143 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 4144 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 4145 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 4146 if (rc != 0) { 4147 device_printf(sc->dev, 4148 "failed to query parameters (post_init): %d.\n", rc); 4149 return (rc); 4150 } 4151 4152 sc->sge.iq_start = val[0]; 4153 sc->sge.eq_start = val[1]; 4154 if ((int)val[3] > (int)val[2]) { 4155 sc->tids.ftid_base = val[2]; 4156 sc->tids.ftid_end = val[3]; 4157 sc->tids.nftids = val[3] - val[2] + 1; 4158 } 4159 sc->vres.l2t.start = val[4]; 4160 sc->vres.l2t.size = val[5] - val[4] + 1; 4161 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 4162 ("%s: L2 table size (%u) larger than expected (%u)", 4163 __func__, sc->vres.l2t.size, L2T_SIZE)); 4164 sc->params.core_vdd = val[6]; 4165 4166 if (chip_id(sc) >= CHELSIO_T6) { 4167 4168 sc->tids.tid_base = t4_read_reg(sc, 4169 A_LE_DB_ACTIVE_TABLE_START_INDEX); 4170 4171 param[0] = FW_PARAM_PFVF(HPFILTER_START); 4172 param[1] = FW_PARAM_PFVF(HPFILTER_END); 4173 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4174 if (rc != 0) { 4175 device_printf(sc->dev, 4176 "failed to query hpfilter parameters: %d.\n", rc); 4177 return (rc); 4178 } 4179 if ((int)val[1] > (int)val[0]) { 4180 sc->tids.hpftid_base = val[0]; 4181 sc->tids.hpftid_end = val[1]; 4182 sc->tids.nhpftids = val[1] - val[0] + 1; 4183 4184 /* 4185 * These should go off if the layout changes and the 4186 * driver needs to catch up. 4187 */ 4188 MPASS(sc->tids.hpftid_base == 0); 4189 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 4190 } 4191 } 4192 4193 /* 4194 * MPSBGMAP is queried separately because only recent firmwares support 4195 * it as a parameter and we don't want the compound query above to fail 4196 * on older firmwares. 4197 */ 4198 param[0] = FW_PARAM_DEV(MPSBGMAP); 4199 val[0] = 0; 4200 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4201 if (rc == 0) 4202 sc->params.mps_bg_map = val[0]; 4203 else 4204 sc->params.mps_bg_map = 0; 4205 4206 /* 4207 * Determine whether the firmware supports the filter2 work request. 4208 * This is queried separately for the same reason as MPSBGMAP above. 4209 */ 4210 param[0] = FW_PARAM_DEV(FILTER2_WR); 4211 val[0] = 0; 4212 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4213 if (rc == 0) 4214 sc->params.filter2_wr_support = val[0] != 0; 4215 else 4216 sc->params.filter2_wr_support = 0; 4217 4218 /* 4219 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 4220 * This is queried separately for the same reason as other params above. 4221 */ 4222 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4223 val[0] = 0; 4224 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4225 if (rc == 0) 4226 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 4227 else 4228 sc->params.ulptx_memwrite_dsgl = false; 4229 4230 /* get capabilites */ 4231 bzero(&caps, sizeof(caps)); 4232 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4233 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4234 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4235 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4236 if (rc != 0) { 4237 device_printf(sc->dev, 4238 "failed to get card capabilities: %d.\n", rc); 4239 return (rc); 4240 } 4241 4242 #define READ_CAPS(x) do { \ 4243 sc->x = htobe16(caps.x); \ 4244 } while (0) 4245 READ_CAPS(nbmcaps); 4246 READ_CAPS(linkcaps); 4247 READ_CAPS(switchcaps); 4248 READ_CAPS(niccaps); 4249 READ_CAPS(toecaps); 4250 READ_CAPS(rdmacaps); 4251 READ_CAPS(cryptocaps); 4252 READ_CAPS(iscsicaps); 4253 READ_CAPS(fcoecaps); 4254 4255 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 4256 MPASS(chip_id(sc) > CHELSIO_T4); 4257 MPASS(sc->toecaps == 0); 4258 sc->toecaps = 0; 4259 4260 param[0] = FW_PARAM_DEV(NTID); 4261 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4262 if (rc != 0) { 4263 device_printf(sc->dev, 4264 "failed to query HASHFILTER parameters: %d.\n", rc); 4265 return (rc); 4266 } 4267 sc->tids.ntids = val[0]; 4268 if (sc->params.fw_vers < 4269 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4270 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4271 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4272 sc->tids.ntids -= sc->tids.nhpftids; 4273 } 4274 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4275 sc->params.hash_filter = 1; 4276 } 4277 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 4278 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 4279 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 4280 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4281 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 4282 if (rc != 0) { 4283 device_printf(sc->dev, 4284 "failed to query NIC parameters: %d.\n", rc); 4285 return (rc); 4286 } 4287 if ((int)val[1] > (int)val[0]) { 4288 sc->tids.etid_base = val[0]; 4289 sc->tids.etid_end = val[1]; 4290 sc->tids.netids = val[1] - val[0] + 1; 4291 sc->params.eo_wr_cred = val[2]; 4292 sc->params.ethoffload = 1; 4293 } 4294 } 4295 if (sc->toecaps) { 4296 /* query offload-related parameters */ 4297 param[0] = FW_PARAM_DEV(NTID); 4298 param[1] = FW_PARAM_PFVF(SERVER_START); 4299 param[2] = FW_PARAM_PFVF(SERVER_END); 4300 param[3] = FW_PARAM_PFVF(TDDP_START); 4301 param[4] = FW_PARAM_PFVF(TDDP_END); 4302 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4303 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4304 if (rc != 0) { 4305 device_printf(sc->dev, 4306 "failed to query TOE parameters: %d.\n", rc); 4307 return (rc); 4308 } 4309 sc->tids.ntids = val[0]; 4310 if (sc->params.fw_vers < 4311 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4312 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4313 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4314 sc->tids.ntids -= sc->tids.nhpftids; 4315 } 4316 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4317 if ((int)val[2] > (int)val[1]) { 4318 sc->tids.stid_base = val[1]; 4319 sc->tids.nstids = val[2] - val[1] + 1; 4320 } 4321 sc->vres.ddp.start = val[3]; 4322 sc->vres.ddp.size = val[4] - val[3] + 1; 4323 sc->params.ofldq_wr_cred = val[5]; 4324 sc->params.offload = 1; 4325 } else { 4326 /* 4327 * The firmware attempts memfree TOE configuration for -SO cards 4328 * and will report toecaps=0 if it runs out of resources (this 4329 * depends on the config file). It may not report 0 for other 4330 * capabilities dependent on the TOE in this case. Set them to 4331 * 0 here so that the driver doesn't bother tracking resources 4332 * that will never be used. 4333 */ 4334 sc->iscsicaps = 0; 4335 sc->rdmacaps = 0; 4336 } 4337 if (sc->rdmacaps) { 4338 param[0] = FW_PARAM_PFVF(STAG_START); 4339 param[1] = FW_PARAM_PFVF(STAG_END); 4340 param[2] = FW_PARAM_PFVF(RQ_START); 4341 param[3] = FW_PARAM_PFVF(RQ_END); 4342 param[4] = FW_PARAM_PFVF(PBL_START); 4343 param[5] = FW_PARAM_PFVF(PBL_END); 4344 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4345 if (rc != 0) { 4346 device_printf(sc->dev, 4347 "failed to query RDMA parameters(1): %d.\n", rc); 4348 return (rc); 4349 } 4350 sc->vres.stag.start = val[0]; 4351 sc->vres.stag.size = val[1] - val[0] + 1; 4352 sc->vres.rq.start = val[2]; 4353 sc->vres.rq.size = val[3] - val[2] + 1; 4354 sc->vres.pbl.start = val[4]; 4355 sc->vres.pbl.size = val[5] - val[4] + 1; 4356 4357 param[0] = FW_PARAM_PFVF(SQRQ_START); 4358 param[1] = FW_PARAM_PFVF(SQRQ_END); 4359 param[2] = FW_PARAM_PFVF(CQ_START); 4360 param[3] = FW_PARAM_PFVF(CQ_END); 4361 param[4] = FW_PARAM_PFVF(OCQ_START); 4362 param[5] = FW_PARAM_PFVF(OCQ_END); 4363 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4364 if (rc != 0) { 4365 device_printf(sc->dev, 4366 "failed to query RDMA parameters(2): %d.\n", rc); 4367 return (rc); 4368 } 4369 sc->vres.qp.start = val[0]; 4370 sc->vres.qp.size = val[1] - val[0] + 1; 4371 sc->vres.cq.start = val[2]; 4372 sc->vres.cq.size = val[3] - val[2] + 1; 4373 sc->vres.ocq.start = val[4]; 4374 sc->vres.ocq.size = val[5] - val[4] + 1; 4375 4376 param[0] = FW_PARAM_PFVF(SRQ_START); 4377 param[1] = FW_PARAM_PFVF(SRQ_END); 4378 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4379 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4380 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4381 if (rc != 0) { 4382 device_printf(sc->dev, 4383 "failed to query RDMA parameters(3): %d.\n", rc); 4384 return (rc); 4385 } 4386 sc->vres.srq.start = val[0]; 4387 sc->vres.srq.size = val[1] - val[0] + 1; 4388 sc->params.max_ordird_qp = val[2]; 4389 sc->params.max_ird_adapter = val[3]; 4390 } 4391 if (sc->iscsicaps) { 4392 param[0] = FW_PARAM_PFVF(ISCSI_START); 4393 param[1] = FW_PARAM_PFVF(ISCSI_END); 4394 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4395 if (rc != 0) { 4396 device_printf(sc->dev, 4397 "failed to query iSCSI parameters: %d.\n", rc); 4398 return (rc); 4399 } 4400 sc->vres.iscsi.start = val[0]; 4401 sc->vres.iscsi.size = val[1] - val[0] + 1; 4402 } 4403 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4404 param[0] = FW_PARAM_PFVF(TLS_START); 4405 param[1] = FW_PARAM_PFVF(TLS_END); 4406 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4407 if (rc != 0) { 4408 device_printf(sc->dev, 4409 "failed to query TLS parameters: %d.\n", rc); 4410 return (rc); 4411 } 4412 sc->vres.key.start = val[0]; 4413 sc->vres.key.size = val[1] - val[0] + 1; 4414 } 4415 4416 t4_init_sge_params(sc); 4417 4418 /* 4419 * We've got the params we wanted to query via the firmware. Now grab 4420 * some others directly from the chip. 4421 */ 4422 rc = t4_read_chip_settings(sc); 4423 4424 return (rc); 4425 } 4426 4427 static int 4428 set_params__post_init(struct adapter *sc) 4429 { 4430 uint32_t param, val; 4431 #ifdef TCP_OFFLOAD 4432 int i, v, shift; 4433 #endif 4434 4435 /* ask for encapsulated CPLs */ 4436 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4437 val = 1; 4438 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4439 4440 /* Enable 32b port caps if the firmware supports it. */ 4441 param = FW_PARAM_PFVF(PORT_CAPS32); 4442 val = 1; 4443 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 4444 sc->params.port_caps32 = 1; 4445 4446 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 4447 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 4448 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 4449 V_MASKFILTER(val - 1)); 4450 4451 #ifdef TCP_OFFLOAD 4452 /* 4453 * Override the TOE timers with user provided tunables. This is not the 4454 * recommended way to change the timers (the firmware config file is) so 4455 * these tunables are not documented. 4456 * 4457 * All the timer tunables are in microseconds. 4458 */ 4459 if (t4_toe_keepalive_idle != 0) { 4460 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4461 v &= M_KEEPALIVEIDLE; 4462 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4463 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4464 } 4465 if (t4_toe_keepalive_interval != 0) { 4466 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4467 v &= M_KEEPALIVEINTVL; 4468 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4469 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4470 } 4471 if (t4_toe_keepalive_count != 0) { 4472 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4473 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4474 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4475 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4476 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4477 } 4478 if (t4_toe_rexmt_min != 0) { 4479 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4480 v &= M_RXTMIN; 4481 t4_set_reg_field(sc, A_TP_RXT_MIN, 4482 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4483 } 4484 if (t4_toe_rexmt_max != 0) { 4485 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4486 v &= M_RXTMAX; 4487 t4_set_reg_field(sc, A_TP_RXT_MAX, 4488 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4489 } 4490 if (t4_toe_rexmt_count != 0) { 4491 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4492 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4493 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4494 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4495 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4496 } 4497 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4498 if (t4_toe_rexmt_backoff[i] != -1) { 4499 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4500 shift = (i & 3) << 3; 4501 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4502 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4503 } 4504 } 4505 #endif 4506 return (0); 4507 } 4508 4509 #undef FW_PARAM_PFVF 4510 #undef FW_PARAM_DEV 4511 4512 static void 4513 t4_set_desc(struct adapter *sc) 4514 { 4515 char buf[128]; 4516 struct adapter_params *p = &sc->params; 4517 4518 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4519 4520 device_set_desc_copy(sc->dev, buf); 4521 } 4522 4523 static inline void 4524 ifmedia_add4(struct ifmedia *ifm, int m) 4525 { 4526 4527 ifmedia_add(ifm, m, 0, NULL); 4528 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4529 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4530 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4531 } 4532 4533 /* 4534 * This is the selected media, which is not quite the same as the active media. 4535 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 4536 * and active are not the same, and "media: Ethernet selected" otherwise. 4537 */ 4538 static void 4539 set_current_media(struct port_info *pi) 4540 { 4541 struct link_config *lc; 4542 struct ifmedia *ifm; 4543 int mword; 4544 u_int speed; 4545 4546 PORT_LOCK_ASSERT_OWNED(pi); 4547 4548 /* Leave current media alone if it's already set to IFM_NONE. */ 4549 ifm = &pi->media; 4550 if (ifm->ifm_cur != NULL && 4551 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4552 return; 4553 4554 lc = &pi->link_cfg; 4555 if (lc->requested_aneg != AUTONEG_DISABLE && 4556 lc->supported & FW_PORT_CAP32_ANEG) { 4557 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4558 return; 4559 } 4560 mword = IFM_ETHER | IFM_FDX; 4561 if (lc->requested_fc & PAUSE_TX) 4562 mword |= IFM_ETH_TXPAUSE; 4563 if (lc->requested_fc & PAUSE_RX) 4564 mword |= IFM_ETH_RXPAUSE; 4565 if (lc->requested_speed == 0) 4566 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 4567 else 4568 speed = lc->requested_speed; 4569 mword |= port_mword(pi, speed_to_fwcap(speed)); 4570 ifmedia_set(ifm, mword); 4571 } 4572 4573 /* 4574 * Returns true if the ifmedia list for the port cannot change. 4575 */ 4576 static bool 4577 fixed_ifmedia(struct port_info *pi) 4578 { 4579 4580 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 4581 pi->port_type == FW_PORT_TYPE_BT_XFI || 4582 pi->port_type == FW_PORT_TYPE_BT_XAUI || 4583 pi->port_type == FW_PORT_TYPE_KX4 || 4584 pi->port_type == FW_PORT_TYPE_KX || 4585 pi->port_type == FW_PORT_TYPE_KR || 4586 pi->port_type == FW_PORT_TYPE_BP_AP || 4587 pi->port_type == FW_PORT_TYPE_BP4_AP || 4588 pi->port_type == FW_PORT_TYPE_BP40_BA || 4589 pi->port_type == FW_PORT_TYPE_KR4_100G || 4590 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 4591 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 4592 } 4593 4594 static void 4595 build_medialist(struct port_info *pi) 4596 { 4597 uint32_t ss, speed; 4598 int unknown, mword, bit; 4599 struct link_config *lc; 4600 struct ifmedia *ifm; 4601 4602 PORT_LOCK_ASSERT_OWNED(pi); 4603 4604 if (pi->flags & FIXED_IFMEDIA) 4605 return; 4606 4607 /* 4608 * Rebuild the ifmedia list. 4609 */ 4610 ifm = &pi->media; 4611 ifmedia_removeall(ifm); 4612 lc = &pi->link_cfg; 4613 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */ 4614 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 4615 MPASS(ss != 0); 4616 no_media: 4617 MPASS(LIST_EMPTY(&ifm->ifm_list)); 4618 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 4619 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 4620 return; 4621 } 4622 4623 unknown = 0; 4624 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 4625 speed = 1 << bit; 4626 MPASS(speed & M_FW_PORT_CAP32_SPEED); 4627 if (ss & speed) { 4628 mword = port_mword(pi, speed); 4629 if (mword == IFM_NONE) { 4630 goto no_media; 4631 } else if (mword == IFM_UNKNOWN) 4632 unknown++; 4633 else 4634 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 4635 } 4636 } 4637 if (unknown > 0) /* Add one unknown for all unknown media types. */ 4638 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 4639 if (lc->supported & FW_PORT_CAP32_ANEG) 4640 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 4641 4642 set_current_media(pi); 4643 } 4644 4645 /* 4646 * Initialize the requested fields in the link config based on driver tunables. 4647 */ 4648 static void 4649 init_link_config(struct port_info *pi) 4650 { 4651 struct link_config *lc = &pi->link_cfg; 4652 4653 PORT_LOCK_ASSERT_OWNED(pi); 4654 4655 lc->requested_speed = 0; 4656 4657 if (t4_autoneg == 0) 4658 lc->requested_aneg = AUTONEG_DISABLE; 4659 else if (t4_autoneg == 1) 4660 lc->requested_aneg = AUTONEG_ENABLE; 4661 else 4662 lc->requested_aneg = AUTONEG_AUTO; 4663 4664 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 4665 PAUSE_AUTONEG); 4666 4667 if (t4_fec == -1 || t4_fec & FEC_AUTO) 4668 lc->requested_fec = FEC_AUTO; 4669 else { 4670 lc->requested_fec = FEC_NONE; 4671 if (t4_fec & FEC_RS) 4672 lc->requested_fec |= FEC_RS; 4673 if (t4_fec & FEC_BASER_RS) 4674 lc->requested_fec |= FEC_BASER_RS; 4675 } 4676 } 4677 4678 /* 4679 * Makes sure that all requested settings comply with what's supported by the 4680 * port. Returns the number of settings that were invalid and had to be fixed. 4681 */ 4682 static int 4683 fixup_link_config(struct port_info *pi) 4684 { 4685 int n = 0; 4686 struct link_config *lc = &pi->link_cfg; 4687 uint32_t fwspeed; 4688 4689 PORT_LOCK_ASSERT_OWNED(pi); 4690 4691 /* Speed (when not autonegotiating) */ 4692 if (lc->requested_speed != 0) { 4693 fwspeed = speed_to_fwcap(lc->requested_speed); 4694 if ((fwspeed & lc->supported) == 0) { 4695 n++; 4696 lc->requested_speed = 0; 4697 } 4698 } 4699 4700 /* Link autonegotiation */ 4701 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 4702 lc->requested_aneg == AUTONEG_DISABLE || 4703 lc->requested_aneg == AUTONEG_AUTO); 4704 if (lc->requested_aneg == AUTONEG_ENABLE && 4705 !(lc->supported & FW_PORT_CAP32_ANEG)) { 4706 n++; 4707 lc->requested_aneg = AUTONEG_AUTO; 4708 } 4709 4710 /* Flow control */ 4711 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 4712 if (lc->requested_fc & PAUSE_TX && 4713 !(lc->supported & FW_PORT_CAP32_FC_TX)) { 4714 n++; 4715 lc->requested_fc &= ~PAUSE_TX; 4716 } 4717 if (lc->requested_fc & PAUSE_RX && 4718 !(lc->supported & FW_PORT_CAP32_FC_RX)) { 4719 n++; 4720 lc->requested_fc &= ~PAUSE_RX; 4721 } 4722 if (!(lc->requested_fc & PAUSE_AUTONEG) && 4723 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) { 4724 n++; 4725 lc->requested_fc |= PAUSE_AUTONEG; 4726 } 4727 4728 /* FEC */ 4729 if ((lc->requested_fec & FEC_RS && 4730 !(lc->supported & FW_PORT_CAP32_FEC_RS)) || 4731 (lc->requested_fec & FEC_BASER_RS && 4732 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) { 4733 n++; 4734 lc->requested_fec = FEC_AUTO; 4735 } 4736 4737 return (n); 4738 } 4739 4740 /* 4741 * Apply the requested L1 settings, which are expected to be valid, to the 4742 * hardware. 4743 */ 4744 static int 4745 apply_link_config(struct port_info *pi) 4746 { 4747 struct adapter *sc = pi->adapter; 4748 struct link_config *lc = &pi->link_cfg; 4749 int rc; 4750 4751 #ifdef INVARIANTS 4752 ASSERT_SYNCHRONIZED_OP(sc); 4753 PORT_LOCK_ASSERT_OWNED(pi); 4754 4755 if (lc->requested_aneg == AUTONEG_ENABLE) 4756 MPASS(lc->supported & FW_PORT_CAP32_ANEG); 4757 if (!(lc->requested_fc & PAUSE_AUTONEG)) 4758 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE); 4759 if (lc->requested_fc & PAUSE_TX) 4760 MPASS(lc->supported & FW_PORT_CAP32_FC_TX); 4761 if (lc->requested_fc & PAUSE_RX) 4762 MPASS(lc->supported & FW_PORT_CAP32_FC_RX); 4763 if (lc->requested_fec & FEC_RS) 4764 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS); 4765 if (lc->requested_fec & FEC_BASER_RS) 4766 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS); 4767 #endif 4768 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4769 if (rc != 0) { 4770 /* Don't complain if the VF driver gets back an EPERM. */ 4771 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 4772 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4773 } else { 4774 /* 4775 * An L1_CFG will almost always result in a link-change event if 4776 * the link is up, and the driver will refresh the actual 4777 * fec/fc/etc. when the notification is processed. If the link 4778 * is down then the actual settings are meaningless. 4779 * 4780 * This takes care of the case where a change in the L1 settings 4781 * may not result in a notification. 4782 */ 4783 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 4784 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 4785 } 4786 return (rc); 4787 } 4788 4789 #define FW_MAC_EXACT_CHUNK 7 4790 4791 /* 4792 * Program the port's XGMAC based on parameters in ifnet. The caller also 4793 * indicates which parameters should be programmed (the rest are left alone). 4794 */ 4795 int 4796 update_mac_settings(struct ifnet *ifp, int flags) 4797 { 4798 int rc = 0; 4799 struct vi_info *vi = ifp->if_softc; 4800 struct port_info *pi = vi->pi; 4801 struct adapter *sc = pi->adapter; 4802 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4803 4804 ASSERT_SYNCHRONIZED_OP(sc); 4805 KASSERT(flags, ("%s: not told what to update.", __func__)); 4806 4807 if (flags & XGMAC_MTU) 4808 mtu = ifp->if_mtu; 4809 4810 if (flags & XGMAC_PROMISC) 4811 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4812 4813 if (flags & XGMAC_ALLMULTI) 4814 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4815 4816 if (flags & XGMAC_VLANEX) 4817 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4818 4819 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4820 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4821 allmulti, 1, vlanex, false); 4822 if (rc) { 4823 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4824 rc); 4825 return (rc); 4826 } 4827 } 4828 4829 if (flags & XGMAC_UCADDR) { 4830 uint8_t ucaddr[ETHER_ADDR_LEN]; 4831 4832 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4833 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4834 ucaddr, true, &vi->smt_idx); 4835 if (rc < 0) { 4836 rc = -rc; 4837 if_printf(ifp, "change_mac failed: %d\n", rc); 4838 return (rc); 4839 } else { 4840 vi->xact_addr_filt = rc; 4841 rc = 0; 4842 } 4843 } 4844 4845 if (flags & XGMAC_MCADDRS) { 4846 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4847 int del = 1; 4848 uint64_t hash = 0; 4849 struct ifmultiaddr *ifma; 4850 int i = 0, j; 4851 4852 if_maddr_rlock(ifp); 4853 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4854 if (ifma->ifma_addr->sa_family != AF_LINK) 4855 continue; 4856 mcaddr[i] = 4857 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4858 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4859 i++; 4860 4861 if (i == FW_MAC_EXACT_CHUNK) { 4862 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4863 del, i, mcaddr, NULL, &hash, 0); 4864 if (rc < 0) { 4865 rc = -rc; 4866 for (j = 0; j < i; j++) { 4867 if_printf(ifp, 4868 "failed to add mc address" 4869 " %02x:%02x:%02x:" 4870 "%02x:%02x:%02x rc=%d\n", 4871 mcaddr[j][0], mcaddr[j][1], 4872 mcaddr[j][2], mcaddr[j][3], 4873 mcaddr[j][4], mcaddr[j][5], 4874 rc); 4875 } 4876 goto mcfail; 4877 } 4878 del = 0; 4879 i = 0; 4880 } 4881 } 4882 if (i > 0) { 4883 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4884 mcaddr, NULL, &hash, 0); 4885 if (rc < 0) { 4886 rc = -rc; 4887 for (j = 0; j < i; j++) { 4888 if_printf(ifp, 4889 "failed to add mc address" 4890 " %02x:%02x:%02x:" 4891 "%02x:%02x:%02x rc=%d\n", 4892 mcaddr[j][0], mcaddr[j][1], 4893 mcaddr[j][2], mcaddr[j][3], 4894 mcaddr[j][4], mcaddr[j][5], 4895 rc); 4896 } 4897 goto mcfail; 4898 } 4899 } 4900 4901 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4902 if (rc != 0) 4903 if_printf(ifp, "failed to set mc address hash: %d", rc); 4904 mcfail: 4905 if_maddr_runlock(ifp); 4906 } 4907 4908 return (rc); 4909 } 4910 4911 /* 4912 * {begin|end}_synchronized_op must be called from the same thread. 4913 */ 4914 int 4915 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4916 char *wmesg) 4917 { 4918 int rc, pri; 4919 4920 #ifdef WITNESS 4921 /* the caller thinks it's ok to sleep, but is it really? */ 4922 if (flags & SLEEP_OK) 4923 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4924 "begin_synchronized_op"); 4925 #endif 4926 4927 if (INTR_OK) 4928 pri = PCATCH; 4929 else 4930 pri = 0; 4931 4932 ADAPTER_LOCK(sc); 4933 for (;;) { 4934 4935 if (vi && IS_DOOMED(vi)) { 4936 rc = ENXIO; 4937 goto done; 4938 } 4939 4940 if (!IS_BUSY(sc)) { 4941 rc = 0; 4942 break; 4943 } 4944 4945 if (!(flags & SLEEP_OK)) { 4946 rc = EBUSY; 4947 goto done; 4948 } 4949 4950 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4951 rc = EINTR; 4952 goto done; 4953 } 4954 } 4955 4956 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4957 SET_BUSY(sc); 4958 #ifdef INVARIANTS 4959 sc->last_op = wmesg; 4960 sc->last_op_thr = curthread; 4961 sc->last_op_flags = flags; 4962 #endif 4963 4964 done: 4965 if (!(flags & HOLD_LOCK) || rc) 4966 ADAPTER_UNLOCK(sc); 4967 4968 return (rc); 4969 } 4970 4971 /* 4972 * Tell if_ioctl and if_init that the VI is going away. This is 4973 * special variant of begin_synchronized_op and must be paired with a 4974 * call to end_synchronized_op. 4975 */ 4976 void 4977 doom_vi(struct adapter *sc, struct vi_info *vi) 4978 { 4979 4980 ADAPTER_LOCK(sc); 4981 SET_DOOMED(vi); 4982 wakeup(&sc->flags); 4983 while (IS_BUSY(sc)) 4984 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4985 SET_BUSY(sc); 4986 #ifdef INVARIANTS 4987 sc->last_op = "t4detach"; 4988 sc->last_op_thr = curthread; 4989 sc->last_op_flags = 0; 4990 #endif 4991 ADAPTER_UNLOCK(sc); 4992 } 4993 4994 /* 4995 * {begin|end}_synchronized_op must be called from the same thread. 4996 */ 4997 void 4998 end_synchronized_op(struct adapter *sc, int flags) 4999 { 5000 5001 if (flags & LOCK_HELD) 5002 ADAPTER_LOCK_ASSERT_OWNED(sc); 5003 else 5004 ADAPTER_LOCK(sc); 5005 5006 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 5007 CLR_BUSY(sc); 5008 wakeup(&sc->flags); 5009 ADAPTER_UNLOCK(sc); 5010 } 5011 5012 static int 5013 cxgbe_init_synchronized(struct vi_info *vi) 5014 { 5015 struct port_info *pi = vi->pi; 5016 struct adapter *sc = pi->adapter; 5017 struct ifnet *ifp = vi->ifp; 5018 int rc = 0, i; 5019 struct sge_txq *txq; 5020 5021 ASSERT_SYNCHRONIZED_OP(sc); 5022 5023 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5024 return (0); /* already running */ 5025 5026 if (!(sc->flags & FULL_INIT_DONE) && 5027 ((rc = adapter_full_init(sc)) != 0)) 5028 return (rc); /* error message displayed already */ 5029 5030 if (!(vi->flags & VI_INIT_DONE) && 5031 ((rc = vi_full_init(vi)) != 0)) 5032 return (rc); /* error message displayed already */ 5033 5034 rc = update_mac_settings(ifp, XGMAC_ALL); 5035 if (rc) 5036 goto done; /* error message displayed already */ 5037 5038 PORT_LOCK(pi); 5039 if (pi->up_vis == 0) { 5040 t4_update_port_info(pi); 5041 fixup_link_config(pi); 5042 build_medialist(pi); 5043 apply_link_config(pi); 5044 } 5045 5046 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 5047 if (rc != 0) { 5048 if_printf(ifp, "enable_vi failed: %d\n", rc); 5049 PORT_UNLOCK(pi); 5050 goto done; 5051 } 5052 5053 /* 5054 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 5055 * if this changes. 5056 */ 5057 5058 for_each_txq(vi, i, txq) { 5059 TXQ_LOCK(txq); 5060 txq->eq.flags |= EQ_ENABLED; 5061 TXQ_UNLOCK(txq); 5062 } 5063 5064 /* 5065 * The first iq of the first port to come up is used for tracing. 5066 */ 5067 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 5068 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 5069 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 5070 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 5071 V_QUEUENUMBER(sc->traceq)); 5072 pi->flags |= HAS_TRACEQ; 5073 } 5074 5075 /* all ok */ 5076 pi->up_vis++; 5077 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5078 5079 if (pi->nvi > 1 || sc->flags & IS_VF) 5080 callout_reset(&vi->tick, hz, vi_tick, vi); 5081 else 5082 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 5083 if (pi->link_cfg.link_ok) 5084 t4_os_link_changed(pi); 5085 PORT_UNLOCK(pi); 5086 done: 5087 if (rc != 0) 5088 cxgbe_uninit_synchronized(vi); 5089 5090 return (rc); 5091 } 5092 5093 /* 5094 * Idempotent. 5095 */ 5096 static int 5097 cxgbe_uninit_synchronized(struct vi_info *vi) 5098 { 5099 struct port_info *pi = vi->pi; 5100 struct adapter *sc = pi->adapter; 5101 struct ifnet *ifp = vi->ifp; 5102 int rc, i; 5103 struct sge_txq *txq; 5104 5105 ASSERT_SYNCHRONIZED_OP(sc); 5106 5107 if (!(vi->flags & VI_INIT_DONE)) { 5108 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5109 KASSERT(0, ("uninited VI is running")); 5110 if_printf(ifp, "uninited VI with running ifnet. " 5111 "vi->flags 0x%016lx, if_flags 0x%08x, " 5112 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 5113 ifp->if_drv_flags); 5114 } 5115 return (0); 5116 } 5117 5118 /* 5119 * Disable the VI so that all its data in either direction is discarded 5120 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 5121 * tick) intact as the TP can deliver negative advice or data that it's 5122 * holding in its RAM (for an offloaded connection) even after the VI is 5123 * disabled. 5124 */ 5125 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 5126 if (rc) { 5127 if_printf(ifp, "disable_vi failed: %d\n", rc); 5128 return (rc); 5129 } 5130 5131 for_each_txq(vi, i, txq) { 5132 TXQ_LOCK(txq); 5133 txq->eq.flags &= ~EQ_ENABLED; 5134 TXQ_UNLOCK(txq); 5135 } 5136 5137 PORT_LOCK(pi); 5138 if (pi->nvi > 1 || sc->flags & IS_VF) 5139 callout_stop(&vi->tick); 5140 else 5141 callout_stop(&pi->tick); 5142 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5143 PORT_UNLOCK(pi); 5144 return (0); 5145 } 5146 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5147 pi->up_vis--; 5148 if (pi->up_vis > 0) { 5149 PORT_UNLOCK(pi); 5150 return (0); 5151 } 5152 5153 pi->link_cfg.link_ok = false; 5154 pi->link_cfg.speed = 0; 5155 pi->link_cfg.link_down_rc = 255; 5156 t4_os_link_changed(pi); 5157 PORT_UNLOCK(pi); 5158 5159 return (0); 5160 } 5161 5162 /* 5163 * It is ok for this function to fail midway and return right away. t4_detach 5164 * will walk the entire sc->irq list and clean up whatever is valid. 5165 */ 5166 int 5167 t4_setup_intr_handlers(struct adapter *sc) 5168 { 5169 int rc, rid, p, q, v; 5170 char s[8]; 5171 struct irq *irq; 5172 struct port_info *pi; 5173 struct vi_info *vi; 5174 struct sge *sge = &sc->sge; 5175 struct sge_rxq *rxq; 5176 #ifdef TCP_OFFLOAD 5177 struct sge_ofld_rxq *ofld_rxq; 5178 #endif 5179 #ifdef DEV_NETMAP 5180 struct sge_nm_rxq *nm_rxq; 5181 #endif 5182 #ifdef RSS 5183 int nbuckets = rss_getnumbuckets(); 5184 #endif 5185 5186 /* 5187 * Setup interrupts. 5188 */ 5189 irq = &sc->irq[0]; 5190 rid = sc->intr_type == INTR_INTX ? 0 : 1; 5191 if (forwarding_intr_to_fwq(sc)) 5192 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 5193 5194 /* Multiple interrupts. */ 5195 if (sc->flags & IS_VF) 5196 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 5197 ("%s: too few intr.", __func__)); 5198 else 5199 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 5200 ("%s: too few intr.", __func__)); 5201 5202 /* The first one is always error intr on PFs */ 5203 if (!(sc->flags & IS_VF)) { 5204 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 5205 if (rc != 0) 5206 return (rc); 5207 irq++; 5208 rid++; 5209 } 5210 5211 /* The second one is always the firmware event queue (first on VFs) */ 5212 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 5213 if (rc != 0) 5214 return (rc); 5215 irq++; 5216 rid++; 5217 5218 for_each_port(sc, p) { 5219 pi = sc->port[p]; 5220 for_each_vi(pi, v, vi) { 5221 vi->first_intr = rid - 1; 5222 5223 if (vi->nnmrxq > 0) { 5224 int n = max(vi->nrxq, vi->nnmrxq); 5225 5226 rxq = &sge->rxq[vi->first_rxq]; 5227 #ifdef DEV_NETMAP 5228 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 5229 #endif 5230 for (q = 0; q < n; q++) { 5231 snprintf(s, sizeof(s), "%x%c%x", p, 5232 'a' + v, q); 5233 if (q < vi->nrxq) 5234 irq->rxq = rxq++; 5235 #ifdef DEV_NETMAP 5236 if (q < vi->nnmrxq) 5237 irq->nm_rxq = nm_rxq++; 5238 5239 if (irq->nm_rxq != NULL && 5240 irq->rxq == NULL) { 5241 /* Netmap rx only */ 5242 rc = t4_alloc_irq(sc, irq, rid, 5243 t4_nm_intr, irq->nm_rxq, s); 5244 } 5245 if (irq->nm_rxq != NULL && 5246 irq->rxq != NULL) { 5247 /* NIC and Netmap rx */ 5248 rc = t4_alloc_irq(sc, irq, rid, 5249 t4_vi_intr, irq, s); 5250 } 5251 #endif 5252 if (irq->rxq != NULL && 5253 irq->nm_rxq == NULL) { 5254 /* NIC rx only */ 5255 rc = t4_alloc_irq(sc, irq, rid, 5256 t4_intr, irq->rxq, s); 5257 } 5258 if (rc != 0) 5259 return (rc); 5260 #ifdef RSS 5261 if (q < vi->nrxq) { 5262 bus_bind_intr(sc->dev, irq->res, 5263 rss_getcpu(q % nbuckets)); 5264 } 5265 #endif 5266 irq++; 5267 rid++; 5268 vi->nintr++; 5269 } 5270 } else { 5271 for_each_rxq(vi, q, rxq) { 5272 snprintf(s, sizeof(s), "%x%c%x", p, 5273 'a' + v, q); 5274 rc = t4_alloc_irq(sc, irq, rid, 5275 t4_intr, rxq, s); 5276 if (rc != 0) 5277 return (rc); 5278 #ifdef RSS 5279 bus_bind_intr(sc->dev, irq->res, 5280 rss_getcpu(q % nbuckets)); 5281 #endif 5282 irq++; 5283 rid++; 5284 vi->nintr++; 5285 } 5286 } 5287 #ifdef TCP_OFFLOAD 5288 for_each_ofld_rxq(vi, q, ofld_rxq) { 5289 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 5290 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 5291 ofld_rxq, s); 5292 if (rc != 0) 5293 return (rc); 5294 irq++; 5295 rid++; 5296 vi->nintr++; 5297 } 5298 #endif 5299 } 5300 } 5301 MPASS(irq == &sc->irq[sc->intr_count]); 5302 5303 return (0); 5304 } 5305 5306 int 5307 adapter_full_init(struct adapter *sc) 5308 { 5309 int rc, i; 5310 #ifdef RSS 5311 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5312 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5313 #endif 5314 5315 ASSERT_SYNCHRONIZED_OP(sc); 5316 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5317 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 5318 ("%s: FULL_INIT_DONE already", __func__)); 5319 5320 /* 5321 * queues that belong to the adapter (not any particular port). 5322 */ 5323 rc = t4_setup_adapter_queues(sc); 5324 if (rc != 0) 5325 goto done; 5326 5327 for (i = 0; i < nitems(sc->tq); i++) { 5328 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 5329 taskqueue_thread_enqueue, &sc->tq[i]); 5330 if (sc->tq[i] == NULL) { 5331 device_printf(sc->dev, 5332 "failed to allocate task queue %d\n", i); 5333 rc = ENOMEM; 5334 goto done; 5335 } 5336 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 5337 device_get_nameunit(sc->dev), i); 5338 } 5339 #ifdef RSS 5340 MPASS(RSS_KEYSIZE == 40); 5341 rss_getkey((void *)&raw_rss_key[0]); 5342 for (i = 0; i < nitems(rss_key); i++) { 5343 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 5344 } 5345 t4_write_rss_key(sc, &rss_key[0], -1, 1); 5346 #endif 5347 5348 if (!(sc->flags & IS_VF)) 5349 t4_intr_enable(sc); 5350 sc->flags |= FULL_INIT_DONE; 5351 done: 5352 if (rc != 0) 5353 adapter_full_uninit(sc); 5354 5355 return (rc); 5356 } 5357 5358 int 5359 adapter_full_uninit(struct adapter *sc) 5360 { 5361 int i; 5362 5363 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5364 5365 t4_teardown_adapter_queues(sc); 5366 5367 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 5368 taskqueue_free(sc->tq[i]); 5369 sc->tq[i] = NULL; 5370 } 5371 5372 sc->flags &= ~FULL_INIT_DONE; 5373 5374 return (0); 5375 } 5376 5377 #ifdef RSS 5378 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 5379 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 5380 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 5381 RSS_HASHTYPE_RSS_UDP_IPV6) 5382 5383 /* Translates kernel hash types to hardware. */ 5384 static int 5385 hashconfig_to_hashen(int hashconfig) 5386 { 5387 int hashen = 0; 5388 5389 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 5390 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 5391 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 5392 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 5393 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 5394 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5395 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5396 } 5397 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 5398 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5399 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5400 } 5401 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 5402 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5403 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 5404 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5405 5406 return (hashen); 5407 } 5408 5409 /* Translates hardware hash types to kernel. */ 5410 static int 5411 hashen_to_hashconfig(int hashen) 5412 { 5413 int hashconfig = 0; 5414 5415 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 5416 /* 5417 * If UDP hashing was enabled it must have been enabled for 5418 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 5419 * enabling any 4-tuple hash is nonsense configuration. 5420 */ 5421 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5422 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 5423 5424 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5425 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 5426 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5427 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 5428 } 5429 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5430 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 5431 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5432 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 5433 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 5434 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 5435 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 5436 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 5437 5438 return (hashconfig); 5439 } 5440 #endif 5441 5442 int 5443 vi_full_init(struct vi_info *vi) 5444 { 5445 struct adapter *sc = vi->pi->adapter; 5446 struct ifnet *ifp = vi->ifp; 5447 uint16_t *rss; 5448 struct sge_rxq *rxq; 5449 int rc, i, j; 5450 #ifdef RSS 5451 int nbuckets = rss_getnumbuckets(); 5452 int hashconfig = rss_gethashconfig(); 5453 int extra; 5454 #endif 5455 5456 ASSERT_SYNCHRONIZED_OP(sc); 5457 KASSERT((vi->flags & VI_INIT_DONE) == 0, 5458 ("%s: VI_INIT_DONE already", __func__)); 5459 5460 sysctl_ctx_init(&vi->ctx); 5461 vi->flags |= VI_SYSCTL_CTX; 5462 5463 /* 5464 * Allocate tx/rx/fl queues for this VI. 5465 */ 5466 rc = t4_setup_vi_queues(vi); 5467 if (rc != 0) 5468 goto done; /* error message displayed already */ 5469 5470 /* 5471 * Setup RSS for this VI. Save a copy of the RSS table for later use. 5472 */ 5473 if (vi->nrxq > vi->rss_size) { 5474 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 5475 "some queues will never receive traffic.\n", vi->nrxq, 5476 vi->rss_size); 5477 } else if (vi->rss_size % vi->nrxq) { 5478 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 5479 "expect uneven traffic distribution.\n", vi->nrxq, 5480 vi->rss_size); 5481 } 5482 #ifdef RSS 5483 if (vi->nrxq != nbuckets) { 5484 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5485 "performance will be impacted.\n", vi->nrxq, nbuckets); 5486 } 5487 #endif 5488 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5489 for (i = 0; i < vi->rss_size;) { 5490 #ifdef RSS 5491 j = rss_get_indirection_to_bucket(i); 5492 j %= vi->nrxq; 5493 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5494 rss[i++] = rxq->iq.abs_id; 5495 #else 5496 for_each_rxq(vi, j, rxq) { 5497 rss[i++] = rxq->iq.abs_id; 5498 if (i == vi->rss_size) 5499 break; 5500 } 5501 #endif 5502 } 5503 5504 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5505 vi->rss_size); 5506 if (rc != 0) { 5507 free(rss, M_CXGBE); 5508 if_printf(ifp, "rss_config failed: %d\n", rc); 5509 goto done; 5510 } 5511 5512 #ifdef RSS 5513 vi->hashen = hashconfig_to_hashen(hashconfig); 5514 5515 /* 5516 * We may have had to enable some hashes even though the global config 5517 * wants them disabled. This is a potential problem that must be 5518 * reported to the user. 5519 */ 5520 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 5521 5522 /* 5523 * If we consider only the supported hash types, then the enabled hashes 5524 * are a superset of the requested hashes. In other words, there cannot 5525 * be any supported hash that was requested but not enabled, but there 5526 * can be hashes that were not requested but had to be enabled. 5527 */ 5528 extra &= SUPPORTED_RSS_HASHTYPES; 5529 MPASS((extra & hashconfig) == 0); 5530 5531 if (extra) { 5532 if_printf(ifp, 5533 "global RSS config (0x%x) cannot be accommodated.\n", 5534 hashconfig); 5535 } 5536 if (extra & RSS_HASHTYPE_RSS_IPV4) 5537 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 5538 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 5539 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 5540 if (extra & RSS_HASHTYPE_RSS_IPV6) 5541 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 5542 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 5543 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 5544 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 5545 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 5546 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 5547 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 5548 #else 5549 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 5550 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 5551 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5552 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 5553 #endif 5554 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0); 5555 if (rc != 0) { 5556 free(rss, M_CXGBE); 5557 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 5558 goto done; 5559 } 5560 5561 vi->rss = rss; 5562 vi->flags |= VI_INIT_DONE; 5563 done: 5564 if (rc != 0) 5565 vi_full_uninit(vi); 5566 5567 return (rc); 5568 } 5569 5570 /* 5571 * Idempotent. 5572 */ 5573 int 5574 vi_full_uninit(struct vi_info *vi) 5575 { 5576 struct port_info *pi = vi->pi; 5577 struct adapter *sc = pi->adapter; 5578 int i; 5579 struct sge_rxq *rxq; 5580 struct sge_txq *txq; 5581 #ifdef TCP_OFFLOAD 5582 struct sge_ofld_rxq *ofld_rxq; 5583 #endif 5584 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5585 struct sge_wrq *ofld_txq; 5586 #endif 5587 5588 if (vi->flags & VI_INIT_DONE) { 5589 5590 /* Need to quiesce queues. */ 5591 5592 /* XXX: Only for the first VI? */ 5593 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5594 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5595 5596 for_each_txq(vi, i, txq) { 5597 quiesce_txq(sc, txq); 5598 } 5599 5600 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5601 for_each_ofld_txq(vi, i, ofld_txq) { 5602 quiesce_wrq(sc, ofld_txq); 5603 } 5604 #endif 5605 5606 for_each_rxq(vi, i, rxq) { 5607 quiesce_iq(sc, &rxq->iq); 5608 quiesce_fl(sc, &rxq->fl); 5609 } 5610 5611 #ifdef TCP_OFFLOAD 5612 for_each_ofld_rxq(vi, i, ofld_rxq) { 5613 quiesce_iq(sc, &ofld_rxq->iq); 5614 quiesce_fl(sc, &ofld_rxq->fl); 5615 } 5616 #endif 5617 free(vi->rss, M_CXGBE); 5618 free(vi->nm_rss, M_CXGBE); 5619 } 5620 5621 t4_teardown_vi_queues(vi); 5622 vi->flags &= ~VI_INIT_DONE; 5623 5624 return (0); 5625 } 5626 5627 static void 5628 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5629 { 5630 struct sge_eq *eq = &txq->eq; 5631 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5632 5633 (void) sc; /* unused */ 5634 5635 #ifdef INVARIANTS 5636 TXQ_LOCK(txq); 5637 MPASS((eq->flags & EQ_ENABLED) == 0); 5638 TXQ_UNLOCK(txq); 5639 #endif 5640 5641 /* Wait for the mp_ring to empty. */ 5642 while (!mp_ring_is_idle(txq->r)) { 5643 mp_ring_check_drainage(txq->r, 0); 5644 pause("rquiesce", 1); 5645 } 5646 5647 /* Then wait for the hardware to finish. */ 5648 while (spg->cidx != htobe16(eq->pidx)) 5649 pause("equiesce", 1); 5650 5651 /* Finally, wait for the driver to reclaim all descriptors. */ 5652 while (eq->cidx != eq->pidx) 5653 pause("dquiesce", 1); 5654 } 5655 5656 static void 5657 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5658 { 5659 5660 /* XXXTX */ 5661 } 5662 5663 static void 5664 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5665 { 5666 (void) sc; /* unused */ 5667 5668 /* Synchronize with the interrupt handler */ 5669 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5670 pause("iqfree", 1); 5671 } 5672 5673 static void 5674 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5675 { 5676 mtx_lock(&sc->sfl_lock); 5677 FL_LOCK(fl); 5678 fl->flags |= FL_DOOMED; 5679 FL_UNLOCK(fl); 5680 callout_stop(&sc->sfl_callout); 5681 mtx_unlock(&sc->sfl_lock); 5682 5683 KASSERT((fl->flags & FL_STARVING) == 0, 5684 ("%s: still starving", __func__)); 5685 } 5686 5687 static int 5688 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5689 driver_intr_t *handler, void *arg, char *name) 5690 { 5691 int rc; 5692 5693 irq->rid = rid; 5694 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5695 RF_SHAREABLE | RF_ACTIVE); 5696 if (irq->res == NULL) { 5697 device_printf(sc->dev, 5698 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5699 return (ENOMEM); 5700 } 5701 5702 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5703 NULL, handler, arg, &irq->tag); 5704 if (rc != 0) { 5705 device_printf(sc->dev, 5706 "failed to setup interrupt for rid %d, name %s: %d\n", 5707 rid, name, rc); 5708 } else if (name) 5709 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5710 5711 return (rc); 5712 } 5713 5714 static int 5715 t4_free_irq(struct adapter *sc, struct irq *irq) 5716 { 5717 if (irq->tag) 5718 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5719 if (irq->res) 5720 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5721 5722 bzero(irq, sizeof(*irq)); 5723 5724 return (0); 5725 } 5726 5727 static void 5728 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5729 { 5730 5731 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5732 t4_get_regs(sc, buf, regs->len); 5733 } 5734 5735 #define A_PL_INDIR_CMD 0x1f8 5736 5737 #define S_PL_AUTOINC 31 5738 #define M_PL_AUTOINC 0x1U 5739 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5740 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5741 5742 #define S_PL_VFID 20 5743 #define M_PL_VFID 0xffU 5744 #define V_PL_VFID(x) ((x) << S_PL_VFID) 5745 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5746 5747 #define S_PL_ADDR 0 5748 #define M_PL_ADDR 0xfffffU 5749 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5750 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5751 5752 #define A_PL_INDIR_DATA 0x1fc 5753 5754 static uint64_t 5755 read_vf_stat(struct adapter *sc, u_int vin, int reg) 5756 { 5757 u32 stats[2]; 5758 5759 mtx_assert(&sc->reg_lock, MA_OWNED); 5760 if (sc->flags & IS_VF) { 5761 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5762 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5763 } else { 5764 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5765 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 5766 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5767 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5768 } 5769 return (((uint64_t)stats[1]) << 32 | stats[0]); 5770 } 5771 5772 static void 5773 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 5774 { 5775 5776 #define GET_STAT(name) \ 5777 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 5778 5779 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5780 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5781 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5782 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5783 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5784 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5785 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5786 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5787 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5788 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5789 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5790 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5791 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5792 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5793 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5794 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5795 5796 #undef GET_STAT 5797 } 5798 5799 static void 5800 t4_clr_vi_stats(struct adapter *sc, u_int vin) 5801 { 5802 int reg; 5803 5804 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 5805 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5806 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5807 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5808 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5809 } 5810 5811 static void 5812 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5813 { 5814 struct timeval tv; 5815 const struct timeval interval = {0, 250000}; /* 250ms */ 5816 5817 if (!(vi->flags & VI_INIT_DONE)) 5818 return; 5819 5820 getmicrotime(&tv); 5821 timevalsub(&tv, &interval); 5822 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5823 return; 5824 5825 mtx_lock(&sc->reg_lock); 5826 t4_get_vi_stats(sc, vi->vin, &vi->stats); 5827 getmicrotime(&vi->last_refreshed); 5828 mtx_unlock(&sc->reg_lock); 5829 } 5830 5831 static void 5832 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5833 { 5834 u_int i, v, tnl_cong_drops, bg_map; 5835 struct timeval tv; 5836 const struct timeval interval = {0, 250000}; /* 250ms */ 5837 5838 getmicrotime(&tv); 5839 timevalsub(&tv, &interval); 5840 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5841 return; 5842 5843 tnl_cong_drops = 0; 5844 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5845 bg_map = pi->mps_bg_map; 5846 while (bg_map) { 5847 i = ffs(bg_map) - 1; 5848 mtx_lock(&sc->reg_lock); 5849 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5850 A_TP_MIB_TNL_CNG_DROP_0 + i); 5851 mtx_unlock(&sc->reg_lock); 5852 tnl_cong_drops += v; 5853 bg_map &= ~(1 << i); 5854 } 5855 pi->tnl_cong_drops = tnl_cong_drops; 5856 getmicrotime(&pi->last_refreshed); 5857 } 5858 5859 static void 5860 cxgbe_tick(void *arg) 5861 { 5862 struct port_info *pi = arg; 5863 struct adapter *sc = pi->adapter; 5864 5865 PORT_LOCK_ASSERT_OWNED(pi); 5866 cxgbe_refresh_stats(sc, pi); 5867 5868 callout_schedule(&pi->tick, hz); 5869 } 5870 5871 void 5872 vi_tick(void *arg) 5873 { 5874 struct vi_info *vi = arg; 5875 struct adapter *sc = vi->pi->adapter; 5876 5877 vi_refresh_stats(sc, vi); 5878 5879 callout_schedule(&vi->tick, hz); 5880 } 5881 5882 /* 5883 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5884 */ 5885 static char *caps_decoder[] = { 5886 "\20\001IPMI\002NCSI", /* 0: NBM */ 5887 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5888 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5889 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5890 "\006HASHFILTER\007ETHOFLD", 5891 "\20\001TOE", /* 4: TOE */ 5892 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5893 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5894 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5895 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5896 "\007T10DIF" 5897 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5898 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5899 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5900 "\004PO_INITIATOR\005PO_TARGET", 5901 }; 5902 5903 void 5904 t4_sysctls(struct adapter *sc) 5905 { 5906 struct sysctl_ctx_list *ctx; 5907 struct sysctl_oid *oid; 5908 struct sysctl_oid_list *children, *c0; 5909 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5910 5911 ctx = device_get_sysctl_ctx(sc->dev); 5912 5913 /* 5914 * dev.t4nex.X. 5915 */ 5916 oid = device_get_sysctl_tree(sc->dev); 5917 c0 = children = SYSCTL_CHILDREN(oid); 5918 5919 sc->sc_do_rxcopy = 1; 5920 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5921 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5922 5923 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5924 sc->params.nports, "# of ports"); 5925 5926 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5927 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells, 5928 sysctl_bitfield_8b, "A", "available doorbells"); 5929 5930 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5931 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5932 5933 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5934 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5935 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5936 "interrupt holdoff timer values (us)"); 5937 5938 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5939 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5940 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5941 "interrupt holdoff packet counter values"); 5942 5943 t4_sge_sysctls(sc, ctx, children); 5944 5945 sc->lro_timeout = 100; 5946 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5947 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5948 5949 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5950 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5951 5952 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5953 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5954 5955 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5956 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5957 5958 if (sc->flags & IS_VF) 5959 return; 5960 5961 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5962 NULL, chip_rev(sc), "chip hardware revision"); 5963 5964 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5965 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5966 5967 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5968 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5969 5970 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5971 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5972 5973 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5974 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5975 5976 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5977 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5978 5979 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5980 sc->er_version, 0, "expansion ROM version"); 5981 5982 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5983 sc->bs_version, 0, "bootstrap firmware version"); 5984 5985 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5986 NULL, sc->params.scfg_vers, "serial config version"); 5987 5988 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5989 NULL, sc->params.vpd_vers, "VPD version"); 5990 5991 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5992 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5993 5994 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5995 sc->cfcsum, "config file checksum"); 5996 5997 #define SYSCTL_CAP(name, n, text) \ 5998 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5999 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \ 6000 sysctl_bitfield_16b, "A", "available " text " capabilities") 6001 6002 SYSCTL_CAP(nbmcaps, 0, "NBM"); 6003 SYSCTL_CAP(linkcaps, 1, "link"); 6004 SYSCTL_CAP(switchcaps, 2, "switch"); 6005 SYSCTL_CAP(niccaps, 3, "NIC"); 6006 SYSCTL_CAP(toecaps, 4, "TCP offload"); 6007 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 6008 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 6009 SYSCTL_CAP(cryptocaps, 7, "crypto"); 6010 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 6011 #undef SYSCTL_CAP 6012 6013 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 6014 NULL, sc->tids.nftids, "number of filters"); 6015 6016 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 6017 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 6018 "chip temperature (in Celsius)"); 6019 6020 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING | 6021 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A", 6022 "microprocessor load averages (debug firmwares only)"); 6023 6024 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 6025 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 6026 6027 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 6028 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS, 6029 sysctl_cpus, "A", "local CPUs"); 6030 6031 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 6032 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS, 6033 sysctl_cpus, "A", "preferred CPUs for interrupts"); 6034 6035 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 6036 &sc->swintr, 0, "software triggered interrupts"); 6037 6038 /* 6039 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 6040 */ 6041 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 6042 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 6043 "logs and miscellaneous information"); 6044 children = SYSCTL_CHILDREN(oid); 6045 6046 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 6047 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6048 sysctl_cctrl, "A", "congestion control"); 6049 6050 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 6051 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6052 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 6053 6054 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 6055 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 6056 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 6057 6058 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 6059 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 6060 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 6061 6062 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 6063 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 6064 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 6065 6066 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 6067 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 6068 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 6069 6070 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 6071 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 6072 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 6073 6074 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 6075 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_la, 6076 "A", "CIM logic analyzer"); 6077 6078 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 6079 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6080 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 6081 6082 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 6083 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 6084 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 6085 6086 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 6087 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 6088 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 6089 6090 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 6091 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 6092 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 6093 6094 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 6095 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 6096 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 6097 6098 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 6099 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 6100 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 6101 6102 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 6103 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 6104 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 6105 6106 if (chip_id(sc) > CHELSIO_T4) { 6107 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 6108 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 6109 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 6110 6111 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 6112 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 6113 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 6114 } 6115 6116 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 6117 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6118 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 6119 6120 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 6121 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6122 sysctl_cim_qcfg, "A", "CIM queue configuration"); 6123 6124 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 6125 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6126 sysctl_cpl_stats, "A", "CPL statistics"); 6127 6128 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 6129 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6130 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 6131 6132 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 6133 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6134 sysctl_devlog, "A", "firmware's device log"); 6135 6136 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 6137 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6138 sysctl_fcoe_stats, "A", "FCoE statistics"); 6139 6140 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 6141 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6142 sysctl_hw_sched, "A", "hardware scheduler "); 6143 6144 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 6145 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6146 sysctl_l2t, "A", "hardware L2 table"); 6147 6148 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 6149 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6150 sysctl_smt, "A", "hardware source MAC table"); 6151 6152 #ifdef INET6 6153 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 6154 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6155 sysctl_clip, "A", "active CLIP table entries"); 6156 #endif 6157 6158 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 6159 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6160 sysctl_lb_stats, "A", "loopback statistics"); 6161 6162 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 6163 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6164 sysctl_meminfo, "A", "memory regions"); 6165 6166 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 6167 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6168 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 6169 "A", "MPS TCAM entries"); 6170 6171 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 6172 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6173 sysctl_path_mtus, "A", "path MTUs"); 6174 6175 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 6176 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6177 sysctl_pm_stats, "A", "PM statistics"); 6178 6179 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 6180 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6181 sysctl_rdma_stats, "A", "RDMA statistics"); 6182 6183 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 6184 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6185 sysctl_tcp_stats, "A", "TCP statistics"); 6186 6187 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 6188 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6189 sysctl_tids, "A", "TID information"); 6190 6191 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 6192 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6193 sysctl_tp_err_stats, "A", "TP error statistics"); 6194 6195 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 6196 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 6197 "TP logic analyzer event capture mask"); 6198 6199 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 6200 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6201 sysctl_tp_la, "A", "TP logic analyzer"); 6202 6203 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 6204 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6205 sysctl_tx_rate, "A", "Tx rate"); 6206 6207 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 6208 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6209 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 6210 6211 if (chip_id(sc) >= CHELSIO_T5) { 6212 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 6213 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6214 sysctl_wcwr_stats, "A", "write combined work requests"); 6215 } 6216 6217 #ifdef TCP_OFFLOAD 6218 if (is_offload(sc)) { 6219 int i; 6220 char s[4]; 6221 6222 /* 6223 * dev.t4nex.X.toe. 6224 */ 6225 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 6226 NULL, "TOE parameters"); 6227 children = SYSCTL_CHILDREN(oid); 6228 6229 sc->tt.cong_algorithm = -1; 6230 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 6231 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 6232 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 6233 "3 = highspeed)"); 6234 6235 sc->tt.sndbuf = 256 * 1024; 6236 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 6237 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 6238 6239 sc->tt.ddp = 0; 6240 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 6241 &sc->tt.ddp, 0, "DDP allowed"); 6242 6243 sc->tt.rx_coalesce = 1; 6244 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 6245 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 6246 6247 sc->tt.tls = 0; 6248 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 6249 &sc->tt.tls, 0, "Inline TLS allowed"); 6250 6251 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 6252 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 6253 "I", "TCP ports that use inline TLS+TOE RX"); 6254 6255 sc->tt.tx_align = 1; 6256 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 6257 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 6258 6259 sc->tt.tx_zcopy = 0; 6260 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 6261 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 6262 "Enable zero-copy aio_write(2)"); 6263 6264 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 6265 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6266 "cop_managed_offloading", CTLFLAG_RW, 6267 &sc->tt.cop_managed_offloading, 0, 6268 "COP (Connection Offload Policy) controls all TOE offload"); 6269 6270 sc->tt.autorcvbuf_inc = 16 * 1024; 6271 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 6272 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 6273 "autorcvbuf increment"); 6274 6275 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 6276 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 6277 "TP timer tick (us)"); 6278 6279 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 6280 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 6281 "TCP timestamp tick (us)"); 6282 6283 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 6284 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 6285 "DACK tick (us)"); 6286 6287 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 6288 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 6289 "IU", "DACK timer (us)"); 6290 6291 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 6292 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 6293 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 6294 6295 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 6296 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 6297 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 6298 6299 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 6300 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 6301 sysctl_tp_timer, "LU", "Persist timer min (us)"); 6302 6303 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 6304 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 6305 sysctl_tp_timer, "LU", "Persist timer max (us)"); 6306 6307 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 6308 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 6309 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 6310 6311 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 6312 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 6313 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 6314 6315 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 6316 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 6317 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 6318 6319 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 6320 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 6321 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 6322 6323 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 6324 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 6325 sysctl_tp_shift_cnt, "IU", 6326 "Number of SYN retransmissions before abort"); 6327 6328 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 6329 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 6330 sysctl_tp_shift_cnt, "IU", 6331 "Number of retransmissions before abort"); 6332 6333 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 6334 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 6335 sysctl_tp_shift_cnt, "IU", 6336 "Number of keepalive probes before abort"); 6337 6338 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 6339 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 6340 children = SYSCTL_CHILDREN(oid); 6341 for (i = 0; i < 16; i++) { 6342 snprintf(s, sizeof(s), "%u", i); 6343 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 6344 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 6345 "IU", "TOE retransmit backoff"); 6346 } 6347 } 6348 #endif 6349 } 6350 6351 void 6352 vi_sysctls(struct vi_info *vi) 6353 { 6354 struct sysctl_ctx_list *ctx; 6355 struct sysctl_oid *oid; 6356 struct sysctl_oid_list *children; 6357 6358 ctx = device_get_sysctl_ctx(vi->dev); 6359 6360 /* 6361 * dev.v?(cxgbe|cxl).X. 6362 */ 6363 oid = device_get_sysctl_tree(vi->dev); 6364 children = SYSCTL_CHILDREN(oid); 6365 6366 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 6367 vi->viid, "VI identifer"); 6368 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 6369 &vi->nrxq, 0, "# of rx queues"); 6370 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 6371 &vi->ntxq, 0, "# of tx queues"); 6372 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 6373 &vi->first_rxq, 0, "index of first rx queue"); 6374 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 6375 &vi->first_txq, 0, "index of first tx queue"); 6376 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 6377 vi->rss_base, "start of RSS indirection table"); 6378 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 6379 vi->rss_size, "size of RSS indirection table"); 6380 6381 if (IS_MAIN_VI(vi)) { 6382 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 6383 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 6384 "Reserve queue 0 for non-flowid packets"); 6385 } 6386 6387 #ifdef TCP_OFFLOAD 6388 if (vi->nofldrxq != 0) { 6389 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 6390 &vi->nofldrxq, 0, 6391 "# of rx queues for offloaded TCP connections"); 6392 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 6393 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 6394 "index of first TOE rx queue"); 6395 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 6396 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6397 sysctl_holdoff_tmr_idx_ofld, "I", 6398 "holdoff timer index for TOE queues"); 6399 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 6400 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6401 sysctl_holdoff_pktc_idx_ofld, "I", 6402 "holdoff packet counter index for TOE queues"); 6403 } 6404 #endif 6405 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 6406 if (vi->nofldtxq != 0) { 6407 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 6408 &vi->nofldtxq, 0, 6409 "# of tx queues for TOE/ETHOFLD"); 6410 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 6411 CTLFLAG_RD, &vi->first_ofld_txq, 0, 6412 "index of first TOE/ETHOFLD tx queue"); 6413 } 6414 #endif 6415 #ifdef DEV_NETMAP 6416 if (vi->nnmrxq != 0) { 6417 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 6418 &vi->nnmrxq, 0, "# of netmap rx queues"); 6419 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 6420 &vi->nnmtxq, 0, "# of netmap tx queues"); 6421 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 6422 CTLFLAG_RD, &vi->first_nm_rxq, 0, 6423 "index of first netmap rx queue"); 6424 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 6425 CTLFLAG_RD, &vi->first_nm_txq, 0, 6426 "index of first netmap tx queue"); 6427 } 6428 #endif 6429 6430 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 6431 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 6432 "holdoff timer index"); 6433 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 6434 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 6435 "holdoff packet counter index"); 6436 6437 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 6438 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 6439 "rx queue size"); 6440 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 6441 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 6442 "tx queue size"); 6443 } 6444 6445 static void 6446 cxgbe_sysctls(struct port_info *pi) 6447 { 6448 struct sysctl_ctx_list *ctx; 6449 struct sysctl_oid *oid; 6450 struct sysctl_oid_list *children, *children2; 6451 struct adapter *sc = pi->adapter; 6452 int i; 6453 char name[16]; 6454 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"}; 6455 6456 ctx = device_get_sysctl_ctx(pi->dev); 6457 6458 /* 6459 * dev.cxgbe.X. 6460 */ 6461 oid = device_get_sysctl_tree(pi->dev); 6462 children = SYSCTL_CHILDREN(oid); 6463 6464 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 6465 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 6466 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 6467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6468 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 6469 "PHY temperature (in Celsius)"); 6470 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 6471 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 6472 "PHY firmware version"); 6473 } 6474 6475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 6476 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 6477 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 6478 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 6479 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 6480 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 6481 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 6482 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 6483 "autonegotiation (-1 = not supported)"); 6484 6485 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 6486 port_top_speed(pi), "max speed (in Gbps)"); 6487 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 6488 pi->mps_bg_map, "MPS buffer group map"); 6489 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 6490 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 6491 6492 if (sc->flags & IS_VF) 6493 return; 6494 6495 /* 6496 * dev.(cxgbe|cxl).X.tc. 6497 */ 6498 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 6499 "Tx scheduler traffic classes (cl_rl)"); 6500 children2 = SYSCTL_CHILDREN(oid); 6501 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 6502 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 6503 "pktsize for per-flow cl-rl (0 means up to the driver )"); 6504 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 6505 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 6506 "burstsize for per-flow cl-rl (0 means up to the driver)"); 6507 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 6508 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 6509 6510 snprintf(name, sizeof(name), "%d", i); 6511 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 6512 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 6513 "traffic class")); 6514 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 6515 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags, 6516 sysctl_bitfield_8b, "A", "flags"); 6517 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 6518 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 6519 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 6520 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 6521 sysctl_tc_params, "A", "traffic class parameters"); 6522 } 6523 6524 /* 6525 * dev.cxgbe.X.stats. 6526 */ 6527 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 6528 NULL, "port statistics"); 6529 children = SYSCTL_CHILDREN(oid); 6530 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 6531 &pi->tx_parse_error, 0, 6532 "# of tx packets with invalid length or # of segments"); 6533 6534 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 6535 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 6536 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 6537 sysctl_handle_t4_reg64, "QU", desc) 6538 6539 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 6540 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 6541 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 6542 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 6543 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 6544 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 6545 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 6546 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 6547 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 6548 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 6549 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 6550 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 6551 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 6552 "# of tx frames in this range", 6553 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 6554 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 6555 "# of tx frames in this range", 6556 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 6557 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 6558 "# of tx frames in this range", 6559 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 6560 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 6561 "# of tx frames in this range", 6562 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 6563 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 6564 "# of tx frames in this range", 6565 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 6566 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 6567 "# of tx frames in this range", 6568 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 6569 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 6570 "# of tx frames in this range", 6571 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 6572 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 6573 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 6574 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 6575 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 6576 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 6577 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 6578 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 6579 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 6580 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 6581 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 6582 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 6583 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 6584 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 6585 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 6586 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 6587 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 6588 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 6589 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 6590 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 6591 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 6592 6593 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 6594 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 6595 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 6596 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 6597 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 6598 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 6599 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 6600 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 6601 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 6602 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 6603 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 6604 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 6605 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 6606 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 6607 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 6608 "# of frames received with bad FCS", 6609 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 6610 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 6611 "# of frames received with length error", 6612 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 6613 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 6614 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 6615 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 6616 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 6617 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 6618 "# of rx frames in this range", 6619 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 6620 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 6621 "# of rx frames in this range", 6622 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 6623 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 6624 "# of rx frames in this range", 6625 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 6626 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 6627 "# of rx frames in this range", 6628 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 6629 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 6630 "# of rx frames in this range", 6631 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 6632 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 6633 "# of rx frames in this range", 6634 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 6635 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 6636 "# of rx frames in this range", 6637 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 6638 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 6639 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 6640 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 6641 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 6642 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 6643 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 6644 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 6645 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 6646 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6647 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6648 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6649 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6650 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6651 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6652 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6653 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6654 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6655 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6656 6657 #undef SYSCTL_ADD_T4_REG64 6658 6659 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6660 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6661 &pi->stats.name, desc) 6662 6663 /* We get these from port_stats and they may be stale by up to 1s */ 6664 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6665 "# drops due to buffer-group 0 overflows"); 6666 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6667 "# drops due to buffer-group 1 overflows"); 6668 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6669 "# drops due to buffer-group 2 overflows"); 6670 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6671 "# drops due to buffer-group 3 overflows"); 6672 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6673 "# of buffer-group 0 truncated packets"); 6674 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6675 "# of buffer-group 1 truncated packets"); 6676 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6677 "# of buffer-group 2 truncated packets"); 6678 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6679 "# of buffer-group 3 truncated packets"); 6680 6681 #undef SYSCTL_ADD_T4_PORTSTAT 6682 6683 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6684 CTLFLAG_RD, &pi->tx_tls_records, 6685 "# of TLS records transmitted"); 6686 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6687 CTLFLAG_RD, &pi->tx_tls_octets, 6688 "# of payload octets in transmitted TLS records"); 6689 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6690 CTLFLAG_RD, &pi->rx_tls_records, 6691 "# of TLS records received"); 6692 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6693 CTLFLAG_RD, &pi->rx_tls_octets, 6694 "# of payload octets in received TLS records"); 6695 } 6696 6697 static int 6698 sysctl_int_array(SYSCTL_HANDLER_ARGS) 6699 { 6700 int rc, *i, space = 0; 6701 struct sbuf sb; 6702 6703 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6704 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6705 if (space) 6706 sbuf_printf(&sb, " "); 6707 sbuf_printf(&sb, "%d", *i); 6708 space = 1; 6709 } 6710 rc = sbuf_finish(&sb); 6711 sbuf_delete(&sb); 6712 return (rc); 6713 } 6714 6715 static int 6716 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 6717 { 6718 int rc; 6719 struct sbuf *sb; 6720 6721 rc = sysctl_wire_old_buffer(req, 0); 6722 if (rc != 0) 6723 return(rc); 6724 6725 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6726 if (sb == NULL) 6727 return (ENOMEM); 6728 6729 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 6730 rc = sbuf_finish(sb); 6731 sbuf_delete(sb); 6732 6733 return (rc); 6734 } 6735 6736 static int 6737 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 6738 { 6739 int rc; 6740 struct sbuf *sb; 6741 6742 rc = sysctl_wire_old_buffer(req, 0); 6743 if (rc != 0) 6744 return(rc); 6745 6746 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6747 if (sb == NULL) 6748 return (ENOMEM); 6749 6750 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 6751 rc = sbuf_finish(sb); 6752 sbuf_delete(sb); 6753 6754 return (rc); 6755 } 6756 6757 static int 6758 sysctl_btphy(SYSCTL_HANDLER_ARGS) 6759 { 6760 struct port_info *pi = arg1; 6761 int op = arg2; 6762 struct adapter *sc = pi->adapter; 6763 u_int v; 6764 int rc; 6765 6766 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6767 if (rc) 6768 return (rc); 6769 /* XXX: magic numbers */ 6770 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6771 &v); 6772 end_synchronized_op(sc, 0); 6773 if (rc) 6774 return (rc); 6775 if (op == 0) 6776 v /= 256; 6777 6778 rc = sysctl_handle_int(oidp, &v, 0, req); 6779 return (rc); 6780 } 6781 6782 static int 6783 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6784 { 6785 struct vi_info *vi = arg1; 6786 int rc, val; 6787 6788 val = vi->rsrv_noflowq; 6789 rc = sysctl_handle_int(oidp, &val, 0, req); 6790 if (rc != 0 || req->newptr == NULL) 6791 return (rc); 6792 6793 if ((val >= 1) && (vi->ntxq > 1)) 6794 vi->rsrv_noflowq = 1; 6795 else 6796 vi->rsrv_noflowq = 0; 6797 6798 return (rc); 6799 } 6800 6801 static int 6802 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6803 { 6804 struct vi_info *vi = arg1; 6805 struct adapter *sc = vi->pi->adapter; 6806 int idx, rc, i; 6807 struct sge_rxq *rxq; 6808 uint8_t v; 6809 6810 idx = vi->tmr_idx; 6811 6812 rc = sysctl_handle_int(oidp, &idx, 0, req); 6813 if (rc != 0 || req->newptr == NULL) 6814 return (rc); 6815 6816 if (idx < 0 || idx >= SGE_NTIMERS) 6817 return (EINVAL); 6818 6819 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6820 "t4tmr"); 6821 if (rc) 6822 return (rc); 6823 6824 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6825 for_each_rxq(vi, i, rxq) { 6826 #ifdef atomic_store_rel_8 6827 atomic_store_rel_8(&rxq->iq.intr_params, v); 6828 #else 6829 rxq->iq.intr_params = v; 6830 #endif 6831 } 6832 vi->tmr_idx = idx; 6833 6834 end_synchronized_op(sc, LOCK_HELD); 6835 return (0); 6836 } 6837 6838 static int 6839 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6840 { 6841 struct vi_info *vi = arg1; 6842 struct adapter *sc = vi->pi->adapter; 6843 int idx, rc; 6844 6845 idx = vi->pktc_idx; 6846 6847 rc = sysctl_handle_int(oidp, &idx, 0, req); 6848 if (rc != 0 || req->newptr == NULL) 6849 return (rc); 6850 6851 if (idx < -1 || idx >= SGE_NCOUNTERS) 6852 return (EINVAL); 6853 6854 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6855 "t4pktc"); 6856 if (rc) 6857 return (rc); 6858 6859 if (vi->flags & VI_INIT_DONE) 6860 rc = EBUSY; /* cannot be changed once the queues are created */ 6861 else 6862 vi->pktc_idx = idx; 6863 6864 end_synchronized_op(sc, LOCK_HELD); 6865 return (rc); 6866 } 6867 6868 static int 6869 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6870 { 6871 struct vi_info *vi = arg1; 6872 struct adapter *sc = vi->pi->adapter; 6873 int qsize, rc; 6874 6875 qsize = vi->qsize_rxq; 6876 6877 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6878 if (rc != 0 || req->newptr == NULL) 6879 return (rc); 6880 6881 if (qsize < 128 || (qsize & 7)) 6882 return (EINVAL); 6883 6884 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6885 "t4rxqs"); 6886 if (rc) 6887 return (rc); 6888 6889 if (vi->flags & VI_INIT_DONE) 6890 rc = EBUSY; /* cannot be changed once the queues are created */ 6891 else 6892 vi->qsize_rxq = qsize; 6893 6894 end_synchronized_op(sc, LOCK_HELD); 6895 return (rc); 6896 } 6897 6898 static int 6899 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6900 { 6901 struct vi_info *vi = arg1; 6902 struct adapter *sc = vi->pi->adapter; 6903 int qsize, rc; 6904 6905 qsize = vi->qsize_txq; 6906 6907 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6908 if (rc != 0 || req->newptr == NULL) 6909 return (rc); 6910 6911 if (qsize < 128 || qsize > 65536) 6912 return (EINVAL); 6913 6914 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6915 "t4txqs"); 6916 if (rc) 6917 return (rc); 6918 6919 if (vi->flags & VI_INIT_DONE) 6920 rc = EBUSY; /* cannot be changed once the queues are created */ 6921 else 6922 vi->qsize_txq = qsize; 6923 6924 end_synchronized_op(sc, LOCK_HELD); 6925 return (rc); 6926 } 6927 6928 static int 6929 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6930 { 6931 struct port_info *pi = arg1; 6932 struct adapter *sc = pi->adapter; 6933 struct link_config *lc = &pi->link_cfg; 6934 int rc; 6935 6936 if (req->newptr == NULL) { 6937 struct sbuf *sb; 6938 static char *bits = "\20\1RX\2TX\3AUTO"; 6939 6940 rc = sysctl_wire_old_buffer(req, 0); 6941 if (rc != 0) 6942 return(rc); 6943 6944 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6945 if (sb == NULL) 6946 return (ENOMEM); 6947 6948 if (lc->link_ok) { 6949 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 6950 (lc->requested_fc & PAUSE_AUTONEG), bits); 6951 } else { 6952 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 6953 PAUSE_RX | PAUSE_AUTONEG), bits); 6954 } 6955 rc = sbuf_finish(sb); 6956 sbuf_delete(sb); 6957 } else { 6958 char s[2]; 6959 int n; 6960 6961 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 6962 PAUSE_AUTONEG)); 6963 s[1] = 0; 6964 6965 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6966 if (rc != 0) 6967 return(rc); 6968 6969 if (s[1] != 0) 6970 return (EINVAL); 6971 if (s[0] < '0' || s[0] > '9') 6972 return (EINVAL); /* not a number */ 6973 n = s[0] - '0'; 6974 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 6975 return (EINVAL); /* some other bit is set too */ 6976 6977 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6978 "t4PAUSE"); 6979 if (rc) 6980 return (rc); 6981 PORT_LOCK(pi); 6982 lc->requested_fc = n; 6983 fixup_link_config(pi); 6984 if (pi->up_vis > 0) 6985 rc = apply_link_config(pi); 6986 set_current_media(pi); 6987 PORT_UNLOCK(pi); 6988 end_synchronized_op(sc, 0); 6989 } 6990 6991 return (rc); 6992 } 6993 6994 static int 6995 sysctl_fec(SYSCTL_HANDLER_ARGS) 6996 { 6997 struct port_info *pi = arg1; 6998 struct adapter *sc = pi->adapter; 6999 struct link_config *lc = &pi->link_cfg; 7000 int rc; 7001 int8_t old; 7002 7003 if (req->newptr == NULL) { 7004 struct sbuf *sb; 7005 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO"; 7006 7007 rc = sysctl_wire_old_buffer(req, 0); 7008 if (rc != 0) 7009 return(rc); 7010 7011 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7012 if (sb == NULL) 7013 return (ENOMEM); 7014 7015 /* 7016 * Display the requested_fec when the link is down -- the actual 7017 * FEC makes sense only when the link is up. 7018 */ 7019 if (lc->link_ok) { 7020 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) | 7021 (lc->requested_fec & FEC_AUTO), bits); 7022 } else { 7023 sbuf_printf(sb, "%b", lc->requested_fec, bits); 7024 } 7025 rc = sbuf_finish(sb); 7026 sbuf_delete(sb); 7027 } else { 7028 char s[3]; 7029 int n; 7030 7031 snprintf(s, sizeof(s), "%d", 7032 lc->requested_fec == FEC_AUTO ? -1 : 7033 lc->requested_fec & M_FW_PORT_CAP32_FEC); 7034 7035 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 7036 if (rc != 0) 7037 return(rc); 7038 7039 n = strtol(&s[0], NULL, 0); 7040 if (n < 0 || n & FEC_AUTO) 7041 n = FEC_AUTO; 7042 else { 7043 if (n & ~M_FW_PORT_CAP32_FEC) 7044 return (EINVAL);/* some other bit is set too */ 7045 if (!powerof2(n)) 7046 return (EINVAL);/* one bit can be set at most */ 7047 } 7048 7049 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7050 "t4fec"); 7051 if (rc) 7052 return (rc); 7053 PORT_LOCK(pi); 7054 old = lc->requested_fec; 7055 if (n == FEC_AUTO) 7056 lc->requested_fec = FEC_AUTO; 7057 else if (n == 0) 7058 lc->requested_fec = FEC_NONE; 7059 else { 7060 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) != 7061 lc->supported) { 7062 rc = ENOTSUP; 7063 goto done; 7064 } 7065 lc->requested_fec = n; 7066 } 7067 fixup_link_config(pi); 7068 if (pi->up_vis > 0) { 7069 rc = apply_link_config(pi); 7070 if (rc != 0) { 7071 lc->requested_fec = old; 7072 if (rc == FW_EPROTO) 7073 rc = ENOTSUP; 7074 } 7075 } 7076 done: 7077 PORT_UNLOCK(pi); 7078 end_synchronized_op(sc, 0); 7079 } 7080 7081 return (rc); 7082 } 7083 7084 static int 7085 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 7086 { 7087 struct port_info *pi = arg1; 7088 struct adapter *sc = pi->adapter; 7089 struct link_config *lc = &pi->link_cfg; 7090 int rc, val; 7091 7092 if (lc->supported & FW_PORT_CAP32_ANEG) 7093 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 7094 else 7095 val = -1; 7096 rc = sysctl_handle_int(oidp, &val, 0, req); 7097 if (rc != 0 || req->newptr == NULL) 7098 return (rc); 7099 if (val == 0) 7100 val = AUTONEG_DISABLE; 7101 else if (val == 1) 7102 val = AUTONEG_ENABLE; 7103 else 7104 val = AUTONEG_AUTO; 7105 7106 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7107 "t4aneg"); 7108 if (rc) 7109 return (rc); 7110 PORT_LOCK(pi); 7111 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) { 7112 rc = ENOTSUP; 7113 goto done; 7114 } 7115 lc->requested_aneg = val; 7116 fixup_link_config(pi); 7117 if (pi->up_vis > 0) 7118 rc = apply_link_config(pi); 7119 set_current_media(pi); 7120 done: 7121 PORT_UNLOCK(pi); 7122 end_synchronized_op(sc, 0); 7123 return (rc); 7124 } 7125 7126 static int 7127 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 7128 { 7129 struct adapter *sc = arg1; 7130 int reg = arg2; 7131 uint64_t val; 7132 7133 val = t4_read_reg64(sc, reg); 7134 7135 return (sysctl_handle_64(oidp, &val, 0, req)); 7136 } 7137 7138 static int 7139 sysctl_temperature(SYSCTL_HANDLER_ARGS) 7140 { 7141 struct adapter *sc = arg1; 7142 int rc, t; 7143 uint32_t param, val; 7144 7145 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 7146 if (rc) 7147 return (rc); 7148 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7149 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7150 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 7151 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7152 end_synchronized_op(sc, 0); 7153 if (rc) 7154 return (rc); 7155 7156 /* unknown is returned as 0 but we display -1 in that case */ 7157 t = val == 0 ? -1 : val; 7158 7159 rc = sysctl_handle_int(oidp, &t, 0, req); 7160 return (rc); 7161 } 7162 7163 static int 7164 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 7165 { 7166 struct adapter *sc = arg1; 7167 struct sbuf *sb; 7168 int rc; 7169 uint32_t param, val; 7170 7171 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 7172 if (rc) 7173 return (rc); 7174 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7175 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 7176 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7177 end_synchronized_op(sc, 0); 7178 if (rc) 7179 return (rc); 7180 7181 rc = sysctl_wire_old_buffer(req, 0); 7182 if (rc != 0) 7183 return (rc); 7184 7185 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7186 if (sb == NULL) 7187 return (ENOMEM); 7188 7189 if (val == 0xffffffff) { 7190 /* Only debug and custom firmwares report load averages. */ 7191 sbuf_printf(sb, "not available"); 7192 } else { 7193 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 7194 (val >> 16) & 0xff); 7195 } 7196 rc = sbuf_finish(sb); 7197 sbuf_delete(sb); 7198 7199 return (rc); 7200 } 7201 7202 static int 7203 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 7204 { 7205 struct adapter *sc = arg1; 7206 struct sbuf *sb; 7207 int rc, i; 7208 uint16_t incr[NMTUS][NCCTRL_WIN]; 7209 static const char *dec_fac[] = { 7210 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 7211 "0.9375" 7212 }; 7213 7214 rc = sysctl_wire_old_buffer(req, 0); 7215 if (rc != 0) 7216 return (rc); 7217 7218 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7219 if (sb == NULL) 7220 return (ENOMEM); 7221 7222 t4_read_cong_tbl(sc, incr); 7223 7224 for (i = 0; i < NCCTRL_WIN; ++i) { 7225 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 7226 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 7227 incr[5][i], incr[6][i], incr[7][i]); 7228 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 7229 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 7230 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 7231 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 7232 } 7233 7234 rc = sbuf_finish(sb); 7235 sbuf_delete(sb); 7236 7237 return (rc); 7238 } 7239 7240 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 7241 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 7242 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 7243 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 7244 }; 7245 7246 static int 7247 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 7248 { 7249 struct adapter *sc = arg1; 7250 struct sbuf *sb; 7251 int rc, i, n, qid = arg2; 7252 uint32_t *buf, *p; 7253 char *qtype; 7254 u_int cim_num_obq = sc->chip_params->cim_num_obq; 7255 7256 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 7257 ("%s: bad qid %d\n", __func__, qid)); 7258 7259 if (qid < CIM_NUM_IBQ) { 7260 /* inbound queue */ 7261 qtype = "IBQ"; 7262 n = 4 * CIM_IBQ_SIZE; 7263 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7264 rc = t4_read_cim_ibq(sc, qid, buf, n); 7265 } else { 7266 /* outbound queue */ 7267 qtype = "OBQ"; 7268 qid -= CIM_NUM_IBQ; 7269 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 7270 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7271 rc = t4_read_cim_obq(sc, qid, buf, n); 7272 } 7273 7274 if (rc < 0) { 7275 rc = -rc; 7276 goto done; 7277 } 7278 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 7279 7280 rc = sysctl_wire_old_buffer(req, 0); 7281 if (rc != 0) 7282 goto done; 7283 7284 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7285 if (sb == NULL) { 7286 rc = ENOMEM; 7287 goto done; 7288 } 7289 7290 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 7291 for (i = 0, p = buf; i < n; i += 16, p += 4) 7292 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 7293 p[2], p[3]); 7294 7295 rc = sbuf_finish(sb); 7296 sbuf_delete(sb); 7297 done: 7298 free(buf, M_CXGBE); 7299 return (rc); 7300 } 7301 7302 static void 7303 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7304 { 7305 uint32_t *p; 7306 7307 sbuf_printf(sb, "Status Data PC%s", 7308 cfg & F_UPDBGLACAPTPCONLY ? "" : 7309 " LS0Stat LS0Addr LS0Data"); 7310 7311 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 7312 if (cfg & F_UPDBGLACAPTPCONLY) { 7313 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 7314 p[6], p[7]); 7315 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 7316 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 7317 p[4] & 0xff, p[5] >> 8); 7318 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 7319 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7320 p[1] & 0xf, p[2] >> 4); 7321 } else { 7322 sbuf_printf(sb, 7323 "\n %02x %x%07x %x%07x %08x %08x " 7324 "%08x%08x%08x%08x", 7325 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7326 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 7327 p[6], p[7]); 7328 } 7329 } 7330 } 7331 7332 static void 7333 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7334 { 7335 uint32_t *p; 7336 7337 sbuf_printf(sb, "Status Inst Data PC%s", 7338 cfg & F_UPDBGLACAPTPCONLY ? "" : 7339 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 7340 7341 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 7342 if (cfg & F_UPDBGLACAPTPCONLY) { 7343 sbuf_printf(sb, "\n %02x %08x %08x %08x", 7344 p[3] & 0xff, p[2], p[1], p[0]); 7345 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 7346 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 7347 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 7348 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 7349 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 7350 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 7351 p[6] >> 16); 7352 } else { 7353 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 7354 "%08x %08x %08x %08x %08x %08x", 7355 (p[9] >> 16) & 0xff, 7356 p[9] & 0xffff, p[8] >> 16, 7357 p[8] & 0xffff, p[7] >> 16, 7358 p[7] & 0xffff, p[6] >> 16, 7359 p[2], p[1], p[0], p[5], p[4], p[3]); 7360 } 7361 } 7362 } 7363 7364 static int 7365 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 7366 { 7367 uint32_t cfg, *buf; 7368 int rc; 7369 7370 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7371 if (rc != 0) 7372 return (rc); 7373 7374 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7375 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7376 M_ZERO | flags); 7377 if (buf == NULL) 7378 return (ENOMEM); 7379 7380 rc = -t4_cim_read_la(sc, buf, NULL); 7381 if (rc != 0) 7382 goto done; 7383 if (chip_id(sc) < CHELSIO_T6) 7384 sbuf_cim_la4(sc, sb, buf, cfg); 7385 else 7386 sbuf_cim_la6(sc, sb, buf, cfg); 7387 7388 done: 7389 free(buf, M_CXGBE); 7390 return (rc); 7391 } 7392 7393 static int 7394 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 7395 { 7396 struct adapter *sc = arg1; 7397 struct sbuf *sb; 7398 int rc; 7399 7400 rc = sysctl_wire_old_buffer(req, 0); 7401 if (rc != 0) 7402 return (rc); 7403 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7404 if (sb == NULL) 7405 return (ENOMEM); 7406 7407 rc = sbuf_cim_la(sc, sb, M_WAITOK); 7408 if (rc == 0) 7409 rc = sbuf_finish(sb); 7410 sbuf_delete(sb); 7411 return (rc); 7412 } 7413 7414 bool 7415 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose) 7416 { 7417 struct sbuf sb; 7418 int rc; 7419 7420 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7421 return (false); 7422 rc = sbuf_cim_la(sc, &sb, M_NOWAIT); 7423 if (rc == 0) { 7424 rc = sbuf_finish(&sb); 7425 if (rc == 0) { 7426 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s", 7427 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7428 } 7429 } 7430 sbuf_delete(&sb); 7431 return (false); 7432 } 7433 7434 static int 7435 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 7436 { 7437 struct adapter *sc = arg1; 7438 u_int i; 7439 struct sbuf *sb; 7440 uint32_t *buf, *p; 7441 int rc; 7442 7443 rc = sysctl_wire_old_buffer(req, 0); 7444 if (rc != 0) 7445 return (rc); 7446 7447 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7448 if (sb == NULL) 7449 return (ENOMEM); 7450 7451 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 7452 M_ZERO | M_WAITOK); 7453 7454 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 7455 p = buf; 7456 7457 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7458 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 7459 p[1], p[0]); 7460 } 7461 7462 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 7463 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7464 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 7465 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 7466 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 7467 (p[1] >> 2) | ((p[2] & 3) << 30), 7468 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 7469 p[0] & 1); 7470 } 7471 7472 rc = sbuf_finish(sb); 7473 sbuf_delete(sb); 7474 free(buf, M_CXGBE); 7475 return (rc); 7476 } 7477 7478 static int 7479 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 7480 { 7481 struct adapter *sc = arg1; 7482 u_int i; 7483 struct sbuf *sb; 7484 uint32_t *buf, *p; 7485 int rc; 7486 7487 rc = sysctl_wire_old_buffer(req, 0); 7488 if (rc != 0) 7489 return (rc); 7490 7491 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7492 if (sb == NULL) 7493 return (ENOMEM); 7494 7495 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 7496 M_ZERO | M_WAITOK); 7497 7498 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 7499 p = buf; 7500 7501 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 7502 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7503 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 7504 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 7505 p[4], p[3], p[2], p[1], p[0]); 7506 } 7507 7508 sbuf_printf(sb, "\n\nCntl ID Data"); 7509 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7510 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 7511 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 7512 } 7513 7514 rc = sbuf_finish(sb); 7515 sbuf_delete(sb); 7516 free(buf, M_CXGBE); 7517 return (rc); 7518 } 7519 7520 static int 7521 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 7522 { 7523 struct adapter *sc = arg1; 7524 struct sbuf *sb; 7525 int rc, i; 7526 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7527 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7528 uint16_t thres[CIM_NUM_IBQ]; 7529 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 7530 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 7531 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 7532 7533 cim_num_obq = sc->chip_params->cim_num_obq; 7534 if (is_t4(sc)) { 7535 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 7536 obq_rdaddr = A_UP_OBQ_0_REALADDR; 7537 } else { 7538 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 7539 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 7540 } 7541 nq = CIM_NUM_IBQ + cim_num_obq; 7542 7543 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 7544 if (rc == 0) 7545 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 7546 if (rc != 0) 7547 return (rc); 7548 7549 t4_read_cimq_cfg(sc, base, size, thres); 7550 7551 rc = sysctl_wire_old_buffer(req, 0); 7552 if (rc != 0) 7553 return (rc); 7554 7555 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7556 if (sb == NULL) 7557 return (ENOMEM); 7558 7559 sbuf_printf(sb, 7560 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 7561 7562 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 7563 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 7564 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 7565 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7566 G_QUEREMFLITS(p[2]) * 16); 7567 for ( ; i < nq; i++, p += 4, wr += 2) 7568 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 7569 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 7570 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7571 G_QUEREMFLITS(p[2]) * 16); 7572 7573 rc = sbuf_finish(sb); 7574 sbuf_delete(sb); 7575 7576 return (rc); 7577 } 7578 7579 static int 7580 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 7581 { 7582 struct adapter *sc = arg1; 7583 struct sbuf *sb; 7584 int rc; 7585 struct tp_cpl_stats stats; 7586 7587 rc = sysctl_wire_old_buffer(req, 0); 7588 if (rc != 0) 7589 return (rc); 7590 7591 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7592 if (sb == NULL) 7593 return (ENOMEM); 7594 7595 mtx_lock(&sc->reg_lock); 7596 t4_tp_get_cpl_stats(sc, &stats, 0); 7597 mtx_unlock(&sc->reg_lock); 7598 7599 if (sc->chip_params->nchan > 2) { 7600 sbuf_printf(sb, " channel 0 channel 1" 7601 " channel 2 channel 3"); 7602 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 7603 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 7604 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 7605 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 7606 } else { 7607 sbuf_printf(sb, " channel 0 channel 1"); 7608 sbuf_printf(sb, "\nCPL requests: %10u %10u", 7609 stats.req[0], stats.req[1]); 7610 sbuf_printf(sb, "\nCPL responses: %10u %10u", 7611 stats.rsp[0], stats.rsp[1]); 7612 } 7613 7614 rc = sbuf_finish(sb); 7615 sbuf_delete(sb); 7616 7617 return (rc); 7618 } 7619 7620 static int 7621 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 7622 { 7623 struct adapter *sc = arg1; 7624 struct sbuf *sb; 7625 int rc; 7626 struct tp_usm_stats stats; 7627 7628 rc = sysctl_wire_old_buffer(req, 0); 7629 if (rc != 0) 7630 return(rc); 7631 7632 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7633 if (sb == NULL) 7634 return (ENOMEM); 7635 7636 t4_get_usm_stats(sc, &stats, 1); 7637 7638 sbuf_printf(sb, "Frames: %u\n", stats.frames); 7639 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 7640 sbuf_printf(sb, "Drops: %u", stats.drops); 7641 7642 rc = sbuf_finish(sb); 7643 sbuf_delete(sb); 7644 7645 return (rc); 7646 } 7647 7648 static const char * const devlog_level_strings[] = { 7649 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 7650 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 7651 [FW_DEVLOG_LEVEL_ERR] = "ERR", 7652 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 7653 [FW_DEVLOG_LEVEL_INFO] = "INFO", 7654 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 7655 }; 7656 7657 static const char * const devlog_facility_strings[] = { 7658 [FW_DEVLOG_FACILITY_CORE] = "CORE", 7659 [FW_DEVLOG_FACILITY_CF] = "CF", 7660 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 7661 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 7662 [FW_DEVLOG_FACILITY_RES] = "RES", 7663 [FW_DEVLOG_FACILITY_HW] = "HW", 7664 [FW_DEVLOG_FACILITY_FLR] = "FLR", 7665 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 7666 [FW_DEVLOG_FACILITY_PHY] = "PHY", 7667 [FW_DEVLOG_FACILITY_MAC] = "MAC", 7668 [FW_DEVLOG_FACILITY_PORT] = "PORT", 7669 [FW_DEVLOG_FACILITY_VI] = "VI", 7670 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 7671 [FW_DEVLOG_FACILITY_ACL] = "ACL", 7672 [FW_DEVLOG_FACILITY_TM] = "TM", 7673 [FW_DEVLOG_FACILITY_QFC] = "QFC", 7674 [FW_DEVLOG_FACILITY_DCB] = "DCB", 7675 [FW_DEVLOG_FACILITY_ETH] = "ETH", 7676 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 7677 [FW_DEVLOG_FACILITY_RI] = "RI", 7678 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 7679 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 7680 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 7681 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 7682 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 7683 }; 7684 7685 static int 7686 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 7687 { 7688 int i, j, rc, nentries, first = 0; 7689 struct devlog_params *dparams = &sc->params.devlog; 7690 struct fw_devlog_e *buf, *e; 7691 uint64_t ftstamp = UINT64_MAX; 7692 7693 if (dparams->addr == 0) 7694 return (ENXIO); 7695 7696 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7697 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 7698 if (buf == NULL) 7699 return (ENOMEM); 7700 7701 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 7702 if (rc != 0) 7703 goto done; 7704 7705 nentries = dparams->size / sizeof(struct fw_devlog_e); 7706 for (i = 0; i < nentries; i++) { 7707 e = &buf[i]; 7708 7709 if (e->timestamp == 0) 7710 break; /* end */ 7711 7712 e->timestamp = be64toh(e->timestamp); 7713 e->seqno = be32toh(e->seqno); 7714 for (j = 0; j < 8; j++) 7715 e->params[j] = be32toh(e->params[j]); 7716 7717 if (e->timestamp < ftstamp) { 7718 ftstamp = e->timestamp; 7719 first = i; 7720 } 7721 } 7722 7723 if (buf[first].timestamp == 0) 7724 goto done; /* nothing in the log */ 7725 7726 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 7727 "Seq#", "Tstamp", "Level", "Facility", "Message"); 7728 7729 i = first; 7730 do { 7731 e = &buf[i]; 7732 if (e->timestamp == 0) 7733 break; /* end */ 7734 7735 sbuf_printf(sb, "%10d %15ju %8s %8s ", 7736 e->seqno, e->timestamp, 7737 (e->level < nitems(devlog_level_strings) ? 7738 devlog_level_strings[e->level] : "UNKNOWN"), 7739 (e->facility < nitems(devlog_facility_strings) ? 7740 devlog_facility_strings[e->facility] : "UNKNOWN")); 7741 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7742 e->params[2], e->params[3], e->params[4], 7743 e->params[5], e->params[6], e->params[7]); 7744 7745 if (++i == nentries) 7746 i = 0; 7747 } while (i != first); 7748 done: 7749 free(buf, M_CXGBE); 7750 return (rc); 7751 } 7752 7753 static int 7754 sysctl_devlog(SYSCTL_HANDLER_ARGS) 7755 { 7756 struct adapter *sc = arg1; 7757 int rc; 7758 struct sbuf *sb; 7759 7760 rc = sysctl_wire_old_buffer(req, 0); 7761 if (rc != 0) 7762 return (rc); 7763 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7764 if (sb == NULL) 7765 return (ENOMEM); 7766 7767 rc = sbuf_devlog(sc, sb, M_WAITOK); 7768 if (rc == 0) 7769 rc = sbuf_finish(sb); 7770 sbuf_delete(sb); 7771 return (rc); 7772 } 7773 7774 void 7775 t4_os_dump_devlog(struct adapter *sc) 7776 { 7777 int rc; 7778 struct sbuf sb; 7779 7780 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7781 return; 7782 rc = sbuf_devlog(sc, &sb, M_NOWAIT); 7783 if (rc == 0) { 7784 rc = sbuf_finish(&sb); 7785 if (rc == 0) { 7786 log(LOG_DEBUG, "%s: device log follows.\n%s", 7787 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7788 } 7789 } 7790 sbuf_delete(&sb); 7791 } 7792 7793 static int 7794 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7795 { 7796 struct adapter *sc = arg1; 7797 struct sbuf *sb; 7798 int rc; 7799 struct tp_fcoe_stats stats[MAX_NCHAN]; 7800 int i, nchan = sc->chip_params->nchan; 7801 7802 rc = sysctl_wire_old_buffer(req, 0); 7803 if (rc != 0) 7804 return (rc); 7805 7806 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7807 if (sb == NULL) 7808 return (ENOMEM); 7809 7810 for (i = 0; i < nchan; i++) 7811 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7812 7813 if (nchan > 2) { 7814 sbuf_printf(sb, " channel 0 channel 1" 7815 " channel 2 channel 3"); 7816 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7817 stats[0].octets_ddp, stats[1].octets_ddp, 7818 stats[2].octets_ddp, stats[3].octets_ddp); 7819 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7820 stats[0].frames_ddp, stats[1].frames_ddp, 7821 stats[2].frames_ddp, stats[3].frames_ddp); 7822 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7823 stats[0].frames_drop, stats[1].frames_drop, 7824 stats[2].frames_drop, stats[3].frames_drop); 7825 } else { 7826 sbuf_printf(sb, " channel 0 channel 1"); 7827 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7828 stats[0].octets_ddp, stats[1].octets_ddp); 7829 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7830 stats[0].frames_ddp, stats[1].frames_ddp); 7831 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7832 stats[0].frames_drop, stats[1].frames_drop); 7833 } 7834 7835 rc = sbuf_finish(sb); 7836 sbuf_delete(sb); 7837 7838 return (rc); 7839 } 7840 7841 static int 7842 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7843 { 7844 struct adapter *sc = arg1; 7845 struct sbuf *sb; 7846 int rc, i; 7847 unsigned int map, kbps, ipg, mode; 7848 unsigned int pace_tab[NTX_SCHED]; 7849 7850 rc = sysctl_wire_old_buffer(req, 0); 7851 if (rc != 0) 7852 return (rc); 7853 7854 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7855 if (sb == NULL) 7856 return (ENOMEM); 7857 7858 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7859 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7860 t4_read_pace_tbl(sc, pace_tab); 7861 7862 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7863 "Class IPG (0.1 ns) Flow IPG (us)"); 7864 7865 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7866 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7867 sbuf_printf(sb, "\n %u %-5s %u ", i, 7868 (mode & (1 << i)) ? "flow" : "class", map & 3); 7869 if (kbps) 7870 sbuf_printf(sb, "%9u ", kbps); 7871 else 7872 sbuf_printf(sb, " disabled "); 7873 7874 if (ipg) 7875 sbuf_printf(sb, "%13u ", ipg); 7876 else 7877 sbuf_printf(sb, " disabled "); 7878 7879 if (pace_tab[i]) 7880 sbuf_printf(sb, "%10u", pace_tab[i]); 7881 else 7882 sbuf_printf(sb, " disabled"); 7883 } 7884 7885 rc = sbuf_finish(sb); 7886 sbuf_delete(sb); 7887 7888 return (rc); 7889 } 7890 7891 static int 7892 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7893 { 7894 struct adapter *sc = arg1; 7895 struct sbuf *sb; 7896 int rc, i, j; 7897 uint64_t *p0, *p1; 7898 struct lb_port_stats s[2]; 7899 static const char *stat_name[] = { 7900 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7901 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7902 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7903 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7904 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7905 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7906 "BG2FramesTrunc:", "BG3FramesTrunc:" 7907 }; 7908 7909 rc = sysctl_wire_old_buffer(req, 0); 7910 if (rc != 0) 7911 return (rc); 7912 7913 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7914 if (sb == NULL) 7915 return (ENOMEM); 7916 7917 memset(s, 0, sizeof(s)); 7918 7919 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7920 t4_get_lb_stats(sc, i, &s[0]); 7921 t4_get_lb_stats(sc, i + 1, &s[1]); 7922 7923 p0 = &s[0].octets; 7924 p1 = &s[1].octets; 7925 sbuf_printf(sb, "%s Loopback %u" 7926 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7927 7928 for (j = 0; j < nitems(stat_name); j++) 7929 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7930 *p0++, *p1++); 7931 } 7932 7933 rc = sbuf_finish(sb); 7934 sbuf_delete(sb); 7935 7936 return (rc); 7937 } 7938 7939 static int 7940 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7941 { 7942 int rc = 0; 7943 struct port_info *pi = arg1; 7944 struct link_config *lc = &pi->link_cfg; 7945 struct sbuf *sb; 7946 7947 rc = sysctl_wire_old_buffer(req, 0); 7948 if (rc != 0) 7949 return(rc); 7950 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7951 if (sb == NULL) 7952 return (ENOMEM); 7953 7954 if (lc->link_ok || lc->link_down_rc == 255) 7955 sbuf_printf(sb, "n/a"); 7956 else 7957 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7958 7959 rc = sbuf_finish(sb); 7960 sbuf_delete(sb); 7961 7962 return (rc); 7963 } 7964 7965 struct mem_desc { 7966 unsigned int base; 7967 unsigned int limit; 7968 unsigned int idx; 7969 }; 7970 7971 static int 7972 mem_desc_cmp(const void *a, const void *b) 7973 { 7974 return ((const struct mem_desc *)a)->base - 7975 ((const struct mem_desc *)b)->base; 7976 } 7977 7978 static void 7979 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7980 unsigned int to) 7981 { 7982 unsigned int size; 7983 7984 if (from == to) 7985 return; 7986 7987 size = to - from + 1; 7988 if (size == 0) 7989 return; 7990 7991 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7992 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7993 } 7994 7995 static int 7996 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7997 { 7998 struct adapter *sc = arg1; 7999 struct sbuf *sb; 8000 int rc, i, n; 8001 uint32_t lo, hi, used, alloc; 8002 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 8003 static const char *region[] = { 8004 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 8005 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 8006 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 8007 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 8008 "RQUDP region:", "PBL region:", "TXPBL region:", 8009 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 8010 "On-chip queues:", "TLS keys:", 8011 }; 8012 struct mem_desc avail[4]; 8013 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 8014 struct mem_desc *md = mem; 8015 8016 rc = sysctl_wire_old_buffer(req, 0); 8017 if (rc != 0) 8018 return (rc); 8019 8020 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8021 if (sb == NULL) 8022 return (ENOMEM); 8023 8024 for (i = 0; i < nitems(mem); i++) { 8025 mem[i].limit = 0; 8026 mem[i].idx = i; 8027 } 8028 8029 /* Find and sort the populated memory ranges */ 8030 i = 0; 8031 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 8032 if (lo & F_EDRAM0_ENABLE) { 8033 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 8034 avail[i].base = G_EDRAM0_BASE(hi) << 20; 8035 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 8036 avail[i].idx = 0; 8037 i++; 8038 } 8039 if (lo & F_EDRAM1_ENABLE) { 8040 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 8041 avail[i].base = G_EDRAM1_BASE(hi) << 20; 8042 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 8043 avail[i].idx = 1; 8044 i++; 8045 } 8046 if (lo & F_EXT_MEM_ENABLE) { 8047 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 8048 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 8049 avail[i].limit = avail[i].base + 8050 (G_EXT_MEM_SIZE(hi) << 20); 8051 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 8052 i++; 8053 } 8054 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 8055 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 8056 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 8057 avail[i].limit = avail[i].base + 8058 (G_EXT_MEM1_SIZE(hi) << 20); 8059 avail[i].idx = 4; 8060 i++; 8061 } 8062 if (!i) /* no memory available */ 8063 return 0; 8064 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 8065 8066 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 8067 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 8068 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 8069 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 8070 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 8071 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 8072 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 8073 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 8074 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 8075 8076 /* the next few have explicit upper bounds */ 8077 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 8078 md->limit = md->base - 1 + 8079 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 8080 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 8081 md++; 8082 8083 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 8084 md->limit = md->base - 1 + 8085 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 8086 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 8087 md++; 8088 8089 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8090 if (chip_id(sc) <= CHELSIO_T5) 8091 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 8092 else 8093 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 8094 md->limit = 0; 8095 } else { 8096 md->base = 0; 8097 md->idx = nitems(region); /* hide it */ 8098 } 8099 md++; 8100 8101 #define ulp_region(reg) \ 8102 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 8103 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 8104 8105 ulp_region(RX_ISCSI); 8106 ulp_region(RX_TDDP); 8107 ulp_region(TX_TPT); 8108 ulp_region(RX_STAG); 8109 ulp_region(RX_RQ); 8110 ulp_region(RX_RQUDP); 8111 ulp_region(RX_PBL); 8112 ulp_region(TX_PBL); 8113 #undef ulp_region 8114 8115 md->base = 0; 8116 md->idx = nitems(region); 8117 if (!is_t4(sc)) { 8118 uint32_t size = 0; 8119 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 8120 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 8121 8122 if (is_t5(sc)) { 8123 if (sge_ctrl & F_VFIFO_ENABLE) 8124 size = G_DBVFIFO_SIZE(fifo_size); 8125 } else 8126 size = G_T6_DBVFIFO_SIZE(fifo_size); 8127 8128 if (size) { 8129 md->base = G_BASEADDR(t4_read_reg(sc, 8130 A_SGE_DBVFIFO_BADDR)); 8131 md->limit = md->base + (size << 2) - 1; 8132 } 8133 } 8134 md++; 8135 8136 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 8137 md->limit = 0; 8138 md++; 8139 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 8140 md->limit = 0; 8141 md++; 8142 8143 md->base = sc->vres.ocq.start; 8144 if (sc->vres.ocq.size) 8145 md->limit = md->base + sc->vres.ocq.size - 1; 8146 else 8147 md->idx = nitems(region); /* hide it */ 8148 md++; 8149 8150 md->base = sc->vres.key.start; 8151 if (sc->vres.key.size) 8152 md->limit = md->base + sc->vres.key.size - 1; 8153 else 8154 md->idx = nitems(region); /* hide it */ 8155 md++; 8156 8157 /* add any address-space holes, there can be up to 3 */ 8158 for (n = 0; n < i - 1; n++) 8159 if (avail[n].limit < avail[n + 1].base) 8160 (md++)->base = avail[n].limit; 8161 if (avail[n].limit) 8162 (md++)->base = avail[n].limit; 8163 8164 n = md - mem; 8165 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 8166 8167 for (lo = 0; lo < i; lo++) 8168 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 8169 avail[lo].limit - 1); 8170 8171 sbuf_printf(sb, "\n"); 8172 for (i = 0; i < n; i++) { 8173 if (mem[i].idx >= nitems(region)) 8174 continue; /* skip holes */ 8175 if (!mem[i].limit) 8176 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 8177 mem_region_show(sb, region[mem[i].idx], mem[i].base, 8178 mem[i].limit); 8179 } 8180 8181 sbuf_printf(sb, "\n"); 8182 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 8183 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 8184 mem_region_show(sb, "uP RAM:", lo, hi); 8185 8186 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 8187 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 8188 mem_region_show(sb, "uP Extmem2:", lo, hi); 8189 8190 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 8191 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 8192 G_PMRXMAXPAGE(lo), 8193 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 8194 (lo & F_PMRXNUMCHN) ? 2 : 1); 8195 8196 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 8197 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 8198 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 8199 G_PMTXMAXPAGE(lo), 8200 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 8201 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 8202 sbuf_printf(sb, "%u p-structs\n", 8203 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 8204 8205 for (i = 0; i < 4; i++) { 8206 if (chip_id(sc) > CHELSIO_T5) 8207 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 8208 else 8209 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 8210 if (is_t5(sc)) { 8211 used = G_T5_USED(lo); 8212 alloc = G_T5_ALLOC(lo); 8213 } else { 8214 used = G_USED(lo); 8215 alloc = G_ALLOC(lo); 8216 } 8217 /* For T6 these are MAC buffer groups */ 8218 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 8219 i, used, alloc); 8220 } 8221 for (i = 0; i < sc->chip_params->nchan; i++) { 8222 if (chip_id(sc) > CHELSIO_T5) 8223 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 8224 else 8225 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 8226 if (is_t5(sc)) { 8227 used = G_T5_USED(lo); 8228 alloc = G_T5_ALLOC(lo); 8229 } else { 8230 used = G_USED(lo); 8231 alloc = G_ALLOC(lo); 8232 } 8233 /* For T6 these are MAC buffer groups */ 8234 sbuf_printf(sb, 8235 "\nLoopback %d using %u pages out of %u allocated", 8236 i, used, alloc); 8237 } 8238 8239 rc = sbuf_finish(sb); 8240 sbuf_delete(sb); 8241 8242 return (rc); 8243 } 8244 8245 static inline void 8246 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 8247 { 8248 *mask = x | y; 8249 y = htobe64(y); 8250 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 8251 } 8252 8253 static int 8254 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 8255 { 8256 struct adapter *sc = arg1; 8257 struct sbuf *sb; 8258 int rc, i; 8259 8260 MPASS(chip_id(sc) <= CHELSIO_T5); 8261 8262 rc = sysctl_wire_old_buffer(req, 0); 8263 if (rc != 0) 8264 return (rc); 8265 8266 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8267 if (sb == NULL) 8268 return (ENOMEM); 8269 8270 sbuf_printf(sb, 8271 "Idx Ethernet address Mask Vld Ports PF" 8272 " VF Replication P0 P1 P2 P3 ML"); 8273 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8274 uint64_t tcamx, tcamy, mask; 8275 uint32_t cls_lo, cls_hi; 8276 uint8_t addr[ETHER_ADDR_LEN]; 8277 8278 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 8279 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 8280 if (tcamx & tcamy) 8281 continue; 8282 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8283 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8284 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8285 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 8286 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 8287 addr[3], addr[4], addr[5], (uintmax_t)mask, 8288 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 8289 G_PORTMAP(cls_hi), G_PF(cls_lo), 8290 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 8291 8292 if (cls_lo & F_REPLICATE) { 8293 struct fw_ldst_cmd ldst_cmd; 8294 8295 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8296 ldst_cmd.op_to_addrspace = 8297 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8298 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8299 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8300 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8301 ldst_cmd.u.mps.rplc.fid_idx = 8302 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8303 V_FW_LDST_CMD_IDX(i)); 8304 8305 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8306 "t4mps"); 8307 if (rc) 8308 break; 8309 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8310 sizeof(ldst_cmd), &ldst_cmd); 8311 end_synchronized_op(sc, 0); 8312 8313 if (rc != 0) { 8314 sbuf_printf(sb, "%36d", rc); 8315 rc = 0; 8316 } else { 8317 sbuf_printf(sb, " %08x %08x %08x %08x", 8318 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8319 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8320 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8321 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8322 } 8323 } else 8324 sbuf_printf(sb, "%36s", ""); 8325 8326 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 8327 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 8328 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 8329 } 8330 8331 if (rc) 8332 (void) sbuf_finish(sb); 8333 else 8334 rc = sbuf_finish(sb); 8335 sbuf_delete(sb); 8336 8337 return (rc); 8338 } 8339 8340 static int 8341 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 8342 { 8343 struct adapter *sc = arg1; 8344 struct sbuf *sb; 8345 int rc, i; 8346 8347 MPASS(chip_id(sc) > CHELSIO_T5); 8348 8349 rc = sysctl_wire_old_buffer(req, 0); 8350 if (rc != 0) 8351 return (rc); 8352 8353 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8354 if (sb == NULL) 8355 return (ENOMEM); 8356 8357 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 8358 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 8359 " Replication" 8360 " P0 P1 P2 P3 ML\n"); 8361 8362 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8363 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 8364 uint16_t ivlan; 8365 uint64_t tcamx, tcamy, val, mask; 8366 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 8367 uint8_t addr[ETHER_ADDR_LEN]; 8368 8369 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 8370 if (i < 256) 8371 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 8372 else 8373 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 8374 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8375 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8376 tcamy = G_DMACH(val) << 32; 8377 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8378 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8379 lookup_type = G_DATALKPTYPE(data2); 8380 port_num = G_DATAPORTNUM(data2); 8381 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8382 /* Inner header VNI */ 8383 vniy = ((data2 & F_DATAVIDH2) << 23) | 8384 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8385 dip_hit = data2 & F_DATADIPHIT; 8386 vlan_vld = 0; 8387 } else { 8388 vniy = 0; 8389 dip_hit = 0; 8390 vlan_vld = data2 & F_DATAVIDH2; 8391 ivlan = G_VIDL(val); 8392 } 8393 8394 ctl |= V_CTLXYBITSEL(1); 8395 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8396 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8397 tcamx = G_DMACH(val) << 32; 8398 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8399 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8400 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8401 /* Inner header VNI mask */ 8402 vnix = ((data2 & F_DATAVIDH2) << 23) | 8403 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8404 } else 8405 vnix = 0; 8406 8407 if (tcamx & tcamy) 8408 continue; 8409 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8410 8411 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8412 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8413 8414 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8415 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8416 "%012jx %06x %06x - - %3c" 8417 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 8418 addr[1], addr[2], addr[3], addr[4], addr[5], 8419 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 8420 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8421 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8422 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8423 } else { 8424 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8425 "%012jx - - ", i, addr[0], addr[1], 8426 addr[2], addr[3], addr[4], addr[5], 8427 (uintmax_t)mask); 8428 8429 if (vlan_vld) 8430 sbuf_printf(sb, "%4u Y ", ivlan); 8431 else 8432 sbuf_printf(sb, " - N "); 8433 8434 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 8435 lookup_type ? 'I' : 'O', port_num, 8436 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8437 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8438 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8439 } 8440 8441 8442 if (cls_lo & F_T6_REPLICATE) { 8443 struct fw_ldst_cmd ldst_cmd; 8444 8445 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8446 ldst_cmd.op_to_addrspace = 8447 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8448 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8449 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8450 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8451 ldst_cmd.u.mps.rplc.fid_idx = 8452 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8453 V_FW_LDST_CMD_IDX(i)); 8454 8455 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8456 "t6mps"); 8457 if (rc) 8458 break; 8459 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8460 sizeof(ldst_cmd), &ldst_cmd); 8461 end_synchronized_op(sc, 0); 8462 8463 if (rc != 0) { 8464 sbuf_printf(sb, "%72d", rc); 8465 rc = 0; 8466 } else { 8467 sbuf_printf(sb, " %08x %08x %08x %08x" 8468 " %08x %08x %08x %08x", 8469 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 8470 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 8471 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 8472 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 8473 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8474 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8475 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8476 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8477 } 8478 } else 8479 sbuf_printf(sb, "%72s", ""); 8480 8481 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 8482 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 8483 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 8484 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 8485 } 8486 8487 if (rc) 8488 (void) sbuf_finish(sb); 8489 else 8490 rc = sbuf_finish(sb); 8491 sbuf_delete(sb); 8492 8493 return (rc); 8494 } 8495 8496 static int 8497 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 8498 { 8499 struct adapter *sc = arg1; 8500 struct sbuf *sb; 8501 int rc; 8502 uint16_t mtus[NMTUS]; 8503 8504 rc = sysctl_wire_old_buffer(req, 0); 8505 if (rc != 0) 8506 return (rc); 8507 8508 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8509 if (sb == NULL) 8510 return (ENOMEM); 8511 8512 t4_read_mtu_tbl(sc, mtus, NULL); 8513 8514 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 8515 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 8516 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 8517 mtus[14], mtus[15]); 8518 8519 rc = sbuf_finish(sb); 8520 sbuf_delete(sb); 8521 8522 return (rc); 8523 } 8524 8525 static int 8526 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 8527 { 8528 struct adapter *sc = arg1; 8529 struct sbuf *sb; 8530 int rc, i; 8531 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 8532 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 8533 static const char *tx_stats[MAX_PM_NSTATS] = { 8534 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 8535 "Tx FIFO wait", NULL, "Tx latency" 8536 }; 8537 static const char *rx_stats[MAX_PM_NSTATS] = { 8538 "Read:", "Write bypass:", "Write mem:", "Flush:", 8539 "Rx FIFO wait", NULL, "Rx latency" 8540 }; 8541 8542 rc = sysctl_wire_old_buffer(req, 0); 8543 if (rc != 0) 8544 return (rc); 8545 8546 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8547 if (sb == NULL) 8548 return (ENOMEM); 8549 8550 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 8551 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 8552 8553 sbuf_printf(sb, " Tx pcmds Tx bytes"); 8554 for (i = 0; i < 4; i++) { 8555 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8556 tx_cyc[i]); 8557 } 8558 8559 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 8560 for (i = 0; i < 4; i++) { 8561 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8562 rx_cyc[i]); 8563 } 8564 8565 if (chip_id(sc) > CHELSIO_T5) { 8566 sbuf_printf(sb, 8567 "\n Total wait Total occupancy"); 8568 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8569 tx_cyc[i]); 8570 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8571 rx_cyc[i]); 8572 8573 i += 2; 8574 MPASS(i < nitems(tx_stats)); 8575 8576 sbuf_printf(sb, 8577 "\n Reads Total wait"); 8578 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8579 tx_cyc[i]); 8580 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8581 rx_cyc[i]); 8582 } 8583 8584 rc = sbuf_finish(sb); 8585 sbuf_delete(sb); 8586 8587 return (rc); 8588 } 8589 8590 static int 8591 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 8592 { 8593 struct adapter *sc = arg1; 8594 struct sbuf *sb; 8595 int rc; 8596 struct tp_rdma_stats stats; 8597 8598 rc = sysctl_wire_old_buffer(req, 0); 8599 if (rc != 0) 8600 return (rc); 8601 8602 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8603 if (sb == NULL) 8604 return (ENOMEM); 8605 8606 mtx_lock(&sc->reg_lock); 8607 t4_tp_get_rdma_stats(sc, &stats, 0); 8608 mtx_unlock(&sc->reg_lock); 8609 8610 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 8611 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 8612 8613 rc = sbuf_finish(sb); 8614 sbuf_delete(sb); 8615 8616 return (rc); 8617 } 8618 8619 static int 8620 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 8621 { 8622 struct adapter *sc = arg1; 8623 struct sbuf *sb; 8624 int rc; 8625 struct tp_tcp_stats v4, v6; 8626 8627 rc = sysctl_wire_old_buffer(req, 0); 8628 if (rc != 0) 8629 return (rc); 8630 8631 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8632 if (sb == NULL) 8633 return (ENOMEM); 8634 8635 mtx_lock(&sc->reg_lock); 8636 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 8637 mtx_unlock(&sc->reg_lock); 8638 8639 sbuf_printf(sb, 8640 " IP IPv6\n"); 8641 sbuf_printf(sb, "OutRsts: %20u %20u\n", 8642 v4.tcp_out_rsts, v6.tcp_out_rsts); 8643 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 8644 v4.tcp_in_segs, v6.tcp_in_segs); 8645 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 8646 v4.tcp_out_segs, v6.tcp_out_segs); 8647 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 8648 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 8649 8650 rc = sbuf_finish(sb); 8651 sbuf_delete(sb); 8652 8653 return (rc); 8654 } 8655 8656 static int 8657 sysctl_tids(SYSCTL_HANDLER_ARGS) 8658 { 8659 struct adapter *sc = arg1; 8660 struct sbuf *sb; 8661 int rc; 8662 struct tid_info *t = &sc->tids; 8663 8664 rc = sysctl_wire_old_buffer(req, 0); 8665 if (rc != 0) 8666 return (rc); 8667 8668 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8669 if (sb == NULL) 8670 return (ENOMEM); 8671 8672 if (t->natids) { 8673 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 8674 t->atids_in_use); 8675 } 8676 8677 if (t->nhpftids) { 8678 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 8679 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 8680 } 8681 8682 if (t->ntids) { 8683 sbuf_printf(sb, "TID range: "); 8684 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8685 uint32_t b, hb; 8686 8687 if (chip_id(sc) <= CHELSIO_T5) { 8688 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 8689 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 8690 } else { 8691 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 8692 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 8693 } 8694 8695 if (b) 8696 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1); 8697 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 8698 } else 8699 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1); 8700 sbuf_printf(sb, ", in use: %u\n", 8701 atomic_load_acq_int(&t->tids_in_use)); 8702 } 8703 8704 if (t->nstids) { 8705 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 8706 t->stid_base + t->nstids - 1, t->stids_in_use); 8707 } 8708 8709 if (t->nftids) { 8710 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 8711 t->ftid_end, t->ftids_in_use); 8712 } 8713 8714 if (t->netids) { 8715 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 8716 t->etid_base + t->netids - 1, t->etids_in_use); 8717 } 8718 8719 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 8720 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 8721 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 8722 8723 rc = sbuf_finish(sb); 8724 sbuf_delete(sb); 8725 8726 return (rc); 8727 } 8728 8729 static int 8730 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 8731 { 8732 struct adapter *sc = arg1; 8733 struct sbuf *sb; 8734 int rc; 8735 struct tp_err_stats stats; 8736 8737 rc = sysctl_wire_old_buffer(req, 0); 8738 if (rc != 0) 8739 return (rc); 8740 8741 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8742 if (sb == NULL) 8743 return (ENOMEM); 8744 8745 mtx_lock(&sc->reg_lock); 8746 t4_tp_get_err_stats(sc, &stats, 0); 8747 mtx_unlock(&sc->reg_lock); 8748 8749 if (sc->chip_params->nchan > 2) { 8750 sbuf_printf(sb, " channel 0 channel 1" 8751 " channel 2 channel 3\n"); 8752 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 8753 stats.mac_in_errs[0], stats.mac_in_errs[1], 8754 stats.mac_in_errs[2], stats.mac_in_errs[3]); 8755 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 8756 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 8757 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 8758 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 8759 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 8760 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 8761 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 8762 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 8763 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 8764 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 8765 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 8766 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 8767 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 8768 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 8769 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 8770 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 8771 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 8772 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 8773 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 8774 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 8775 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 8776 } else { 8777 sbuf_printf(sb, " channel 0 channel 1\n"); 8778 sbuf_printf(sb, "macInErrs: %10u %10u\n", 8779 stats.mac_in_errs[0], stats.mac_in_errs[1]); 8780 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 8781 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 8782 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 8783 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8784 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8785 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8786 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8787 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8788 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8789 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8790 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8791 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8792 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8793 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8794 } 8795 8796 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8797 stats.ofld_no_neigh, stats.ofld_cong_defer); 8798 8799 rc = sbuf_finish(sb); 8800 sbuf_delete(sb); 8801 8802 return (rc); 8803 } 8804 8805 static int 8806 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8807 { 8808 struct adapter *sc = arg1; 8809 struct tp_params *tpp = &sc->params.tp; 8810 u_int mask; 8811 int rc; 8812 8813 mask = tpp->la_mask >> 16; 8814 rc = sysctl_handle_int(oidp, &mask, 0, req); 8815 if (rc != 0 || req->newptr == NULL) 8816 return (rc); 8817 if (mask > 0xffff) 8818 return (EINVAL); 8819 tpp->la_mask = mask << 16; 8820 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8821 8822 return (0); 8823 } 8824 8825 struct field_desc { 8826 const char *name; 8827 u_int start; 8828 u_int width; 8829 }; 8830 8831 static void 8832 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8833 { 8834 char buf[32]; 8835 int line_size = 0; 8836 8837 while (f->name) { 8838 uint64_t mask = (1ULL << f->width) - 1; 8839 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8840 ((uintmax_t)v >> f->start) & mask); 8841 8842 if (line_size + len >= 79) { 8843 line_size = 8; 8844 sbuf_printf(sb, "\n "); 8845 } 8846 sbuf_printf(sb, "%s ", buf); 8847 line_size += len + 1; 8848 f++; 8849 } 8850 sbuf_printf(sb, "\n"); 8851 } 8852 8853 static const struct field_desc tp_la0[] = { 8854 { "RcfOpCodeOut", 60, 4 }, 8855 { "State", 56, 4 }, 8856 { "WcfState", 52, 4 }, 8857 { "RcfOpcSrcOut", 50, 2 }, 8858 { "CRxError", 49, 1 }, 8859 { "ERxError", 48, 1 }, 8860 { "SanityFailed", 47, 1 }, 8861 { "SpuriousMsg", 46, 1 }, 8862 { "FlushInputMsg", 45, 1 }, 8863 { "FlushInputCpl", 44, 1 }, 8864 { "RssUpBit", 43, 1 }, 8865 { "RssFilterHit", 42, 1 }, 8866 { "Tid", 32, 10 }, 8867 { "InitTcb", 31, 1 }, 8868 { "LineNumber", 24, 7 }, 8869 { "Emsg", 23, 1 }, 8870 { "EdataOut", 22, 1 }, 8871 { "Cmsg", 21, 1 }, 8872 { "CdataOut", 20, 1 }, 8873 { "EreadPdu", 19, 1 }, 8874 { "CreadPdu", 18, 1 }, 8875 { "TunnelPkt", 17, 1 }, 8876 { "RcfPeerFin", 16, 1 }, 8877 { "RcfReasonOut", 12, 4 }, 8878 { "TxCchannel", 10, 2 }, 8879 { "RcfTxChannel", 8, 2 }, 8880 { "RxEchannel", 6, 2 }, 8881 { "RcfRxChannel", 5, 1 }, 8882 { "RcfDataOutSrdy", 4, 1 }, 8883 { "RxDvld", 3, 1 }, 8884 { "RxOoDvld", 2, 1 }, 8885 { "RxCongestion", 1, 1 }, 8886 { "TxCongestion", 0, 1 }, 8887 { NULL } 8888 }; 8889 8890 static const struct field_desc tp_la1[] = { 8891 { "CplCmdIn", 56, 8 }, 8892 { "CplCmdOut", 48, 8 }, 8893 { "ESynOut", 47, 1 }, 8894 { "EAckOut", 46, 1 }, 8895 { "EFinOut", 45, 1 }, 8896 { "ERstOut", 44, 1 }, 8897 { "SynIn", 43, 1 }, 8898 { "AckIn", 42, 1 }, 8899 { "FinIn", 41, 1 }, 8900 { "RstIn", 40, 1 }, 8901 { "DataIn", 39, 1 }, 8902 { "DataInVld", 38, 1 }, 8903 { "PadIn", 37, 1 }, 8904 { "RxBufEmpty", 36, 1 }, 8905 { "RxDdp", 35, 1 }, 8906 { "RxFbCongestion", 34, 1 }, 8907 { "TxFbCongestion", 33, 1 }, 8908 { "TxPktSumSrdy", 32, 1 }, 8909 { "RcfUlpType", 28, 4 }, 8910 { "Eread", 27, 1 }, 8911 { "Ebypass", 26, 1 }, 8912 { "Esave", 25, 1 }, 8913 { "Static0", 24, 1 }, 8914 { "Cread", 23, 1 }, 8915 { "Cbypass", 22, 1 }, 8916 { "Csave", 21, 1 }, 8917 { "CPktOut", 20, 1 }, 8918 { "RxPagePoolFull", 18, 2 }, 8919 { "RxLpbkPkt", 17, 1 }, 8920 { "TxLpbkPkt", 16, 1 }, 8921 { "RxVfValid", 15, 1 }, 8922 { "SynLearned", 14, 1 }, 8923 { "SetDelEntry", 13, 1 }, 8924 { "SetInvEntry", 12, 1 }, 8925 { "CpcmdDvld", 11, 1 }, 8926 { "CpcmdSave", 10, 1 }, 8927 { "RxPstructsFull", 8, 2 }, 8928 { "EpcmdDvld", 7, 1 }, 8929 { "EpcmdFlush", 6, 1 }, 8930 { "EpcmdTrimPrefix", 5, 1 }, 8931 { "EpcmdTrimPostfix", 4, 1 }, 8932 { "ERssIp4Pkt", 3, 1 }, 8933 { "ERssIp6Pkt", 2, 1 }, 8934 { "ERssTcpUdpPkt", 1, 1 }, 8935 { "ERssFceFipPkt", 0, 1 }, 8936 { NULL } 8937 }; 8938 8939 static const struct field_desc tp_la2[] = { 8940 { "CplCmdIn", 56, 8 }, 8941 { "MpsVfVld", 55, 1 }, 8942 { "MpsPf", 52, 3 }, 8943 { "MpsVf", 44, 8 }, 8944 { "SynIn", 43, 1 }, 8945 { "AckIn", 42, 1 }, 8946 { "FinIn", 41, 1 }, 8947 { "RstIn", 40, 1 }, 8948 { "DataIn", 39, 1 }, 8949 { "DataInVld", 38, 1 }, 8950 { "PadIn", 37, 1 }, 8951 { "RxBufEmpty", 36, 1 }, 8952 { "RxDdp", 35, 1 }, 8953 { "RxFbCongestion", 34, 1 }, 8954 { "TxFbCongestion", 33, 1 }, 8955 { "TxPktSumSrdy", 32, 1 }, 8956 { "RcfUlpType", 28, 4 }, 8957 { "Eread", 27, 1 }, 8958 { "Ebypass", 26, 1 }, 8959 { "Esave", 25, 1 }, 8960 { "Static0", 24, 1 }, 8961 { "Cread", 23, 1 }, 8962 { "Cbypass", 22, 1 }, 8963 { "Csave", 21, 1 }, 8964 { "CPktOut", 20, 1 }, 8965 { "RxPagePoolFull", 18, 2 }, 8966 { "RxLpbkPkt", 17, 1 }, 8967 { "TxLpbkPkt", 16, 1 }, 8968 { "RxVfValid", 15, 1 }, 8969 { "SynLearned", 14, 1 }, 8970 { "SetDelEntry", 13, 1 }, 8971 { "SetInvEntry", 12, 1 }, 8972 { "CpcmdDvld", 11, 1 }, 8973 { "CpcmdSave", 10, 1 }, 8974 { "RxPstructsFull", 8, 2 }, 8975 { "EpcmdDvld", 7, 1 }, 8976 { "EpcmdFlush", 6, 1 }, 8977 { "EpcmdTrimPrefix", 5, 1 }, 8978 { "EpcmdTrimPostfix", 4, 1 }, 8979 { "ERssIp4Pkt", 3, 1 }, 8980 { "ERssIp6Pkt", 2, 1 }, 8981 { "ERssTcpUdpPkt", 1, 1 }, 8982 { "ERssFceFipPkt", 0, 1 }, 8983 { NULL } 8984 }; 8985 8986 static void 8987 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8988 { 8989 8990 field_desc_show(sb, *p, tp_la0); 8991 } 8992 8993 static void 8994 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8995 { 8996 8997 if (idx) 8998 sbuf_printf(sb, "\n"); 8999 field_desc_show(sb, p[0], tp_la0); 9000 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9001 field_desc_show(sb, p[1], tp_la0); 9002 } 9003 9004 static void 9005 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 9006 { 9007 9008 if (idx) 9009 sbuf_printf(sb, "\n"); 9010 field_desc_show(sb, p[0], tp_la0); 9011 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9012 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 9013 } 9014 9015 static int 9016 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 9017 { 9018 struct adapter *sc = arg1; 9019 struct sbuf *sb; 9020 uint64_t *buf, *p; 9021 int rc; 9022 u_int i, inc; 9023 void (*show_func)(struct sbuf *, uint64_t *, int); 9024 9025 rc = sysctl_wire_old_buffer(req, 0); 9026 if (rc != 0) 9027 return (rc); 9028 9029 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9030 if (sb == NULL) 9031 return (ENOMEM); 9032 9033 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 9034 9035 t4_tp_read_la(sc, buf, NULL); 9036 p = buf; 9037 9038 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 9039 case 2: 9040 inc = 2; 9041 show_func = tp_la_show2; 9042 break; 9043 case 3: 9044 inc = 2; 9045 show_func = tp_la_show3; 9046 break; 9047 default: 9048 inc = 1; 9049 show_func = tp_la_show; 9050 } 9051 9052 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 9053 (*show_func)(sb, p, i); 9054 9055 rc = sbuf_finish(sb); 9056 sbuf_delete(sb); 9057 free(buf, M_CXGBE); 9058 return (rc); 9059 } 9060 9061 static int 9062 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 9063 { 9064 struct adapter *sc = arg1; 9065 struct sbuf *sb; 9066 int rc; 9067 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 9068 9069 rc = sysctl_wire_old_buffer(req, 0); 9070 if (rc != 0) 9071 return (rc); 9072 9073 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9074 if (sb == NULL) 9075 return (ENOMEM); 9076 9077 t4_get_chan_txrate(sc, nrate, orate); 9078 9079 if (sc->chip_params->nchan > 2) { 9080 sbuf_printf(sb, " channel 0 channel 1" 9081 " channel 2 channel 3\n"); 9082 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 9083 nrate[0], nrate[1], nrate[2], nrate[3]); 9084 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 9085 orate[0], orate[1], orate[2], orate[3]); 9086 } else { 9087 sbuf_printf(sb, " channel 0 channel 1\n"); 9088 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 9089 nrate[0], nrate[1]); 9090 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 9091 orate[0], orate[1]); 9092 } 9093 9094 rc = sbuf_finish(sb); 9095 sbuf_delete(sb); 9096 9097 return (rc); 9098 } 9099 9100 static int 9101 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 9102 { 9103 struct adapter *sc = arg1; 9104 struct sbuf *sb; 9105 uint32_t *buf, *p; 9106 int rc, i; 9107 9108 rc = sysctl_wire_old_buffer(req, 0); 9109 if (rc != 0) 9110 return (rc); 9111 9112 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9113 if (sb == NULL) 9114 return (ENOMEM); 9115 9116 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 9117 M_ZERO | M_WAITOK); 9118 9119 t4_ulprx_read_la(sc, buf); 9120 p = buf; 9121 9122 sbuf_printf(sb, " Pcmd Type Message" 9123 " Data"); 9124 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 9125 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 9126 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 9127 } 9128 9129 rc = sbuf_finish(sb); 9130 sbuf_delete(sb); 9131 free(buf, M_CXGBE); 9132 return (rc); 9133 } 9134 9135 static int 9136 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 9137 { 9138 struct adapter *sc = arg1; 9139 struct sbuf *sb; 9140 int rc, v; 9141 9142 MPASS(chip_id(sc) >= CHELSIO_T5); 9143 9144 rc = sysctl_wire_old_buffer(req, 0); 9145 if (rc != 0) 9146 return (rc); 9147 9148 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9149 if (sb == NULL) 9150 return (ENOMEM); 9151 9152 v = t4_read_reg(sc, A_SGE_STAT_CFG); 9153 if (G_STATSOURCE_T5(v) == 7) { 9154 int mode; 9155 9156 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 9157 if (mode == 0) { 9158 sbuf_printf(sb, "total %d, incomplete %d", 9159 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9160 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9161 } else if (mode == 1) { 9162 sbuf_printf(sb, "total %d, data overflow %d", 9163 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9164 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9165 } else { 9166 sbuf_printf(sb, "unknown mode %d", mode); 9167 } 9168 } 9169 rc = sbuf_finish(sb); 9170 sbuf_delete(sb); 9171 9172 return (rc); 9173 } 9174 9175 static int 9176 sysctl_cpus(SYSCTL_HANDLER_ARGS) 9177 { 9178 struct adapter *sc = arg1; 9179 enum cpu_sets op = arg2; 9180 cpuset_t cpuset; 9181 struct sbuf *sb; 9182 int i, rc; 9183 9184 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 9185 9186 CPU_ZERO(&cpuset); 9187 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 9188 if (rc != 0) 9189 return (rc); 9190 9191 rc = sysctl_wire_old_buffer(req, 0); 9192 if (rc != 0) 9193 return (rc); 9194 9195 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9196 if (sb == NULL) 9197 return (ENOMEM); 9198 9199 CPU_FOREACH(i) 9200 sbuf_printf(sb, "%d ", i); 9201 rc = sbuf_finish(sb); 9202 sbuf_delete(sb); 9203 9204 return (rc); 9205 } 9206 9207 #ifdef TCP_OFFLOAD 9208 static int 9209 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 9210 { 9211 struct adapter *sc = arg1; 9212 int *old_ports, *new_ports; 9213 int i, new_count, rc; 9214 9215 if (req->newptr == NULL && req->oldptr == NULL) 9216 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 9217 sizeof(sc->tt.tls_rx_ports[0]))); 9218 9219 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 9220 if (rc) 9221 return (rc); 9222 9223 if (sc->tt.num_tls_rx_ports == 0) { 9224 i = -1; 9225 rc = SYSCTL_OUT(req, &i, sizeof(i)); 9226 } else 9227 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 9228 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 9229 if (rc == 0 && req->newptr != NULL) { 9230 new_count = req->newlen / sizeof(new_ports[0]); 9231 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 9232 M_WAITOK); 9233 rc = SYSCTL_IN(req, new_ports, new_count * 9234 sizeof(new_ports[0])); 9235 if (rc) 9236 goto err; 9237 9238 /* Allow setting to a single '-1' to clear the list. */ 9239 if (new_count == 1 && new_ports[0] == -1) { 9240 ADAPTER_LOCK(sc); 9241 old_ports = sc->tt.tls_rx_ports; 9242 sc->tt.tls_rx_ports = NULL; 9243 sc->tt.num_tls_rx_ports = 0; 9244 ADAPTER_UNLOCK(sc); 9245 free(old_ports, M_CXGBE); 9246 } else { 9247 for (i = 0; i < new_count; i++) { 9248 if (new_ports[i] < 1 || 9249 new_ports[i] > IPPORT_MAX) { 9250 rc = EINVAL; 9251 goto err; 9252 } 9253 } 9254 9255 ADAPTER_LOCK(sc); 9256 old_ports = sc->tt.tls_rx_ports; 9257 sc->tt.tls_rx_ports = new_ports; 9258 sc->tt.num_tls_rx_ports = new_count; 9259 ADAPTER_UNLOCK(sc); 9260 free(old_ports, M_CXGBE); 9261 new_ports = NULL; 9262 } 9263 err: 9264 free(new_ports, M_CXGBE); 9265 } 9266 end_synchronized_op(sc, 0); 9267 return (rc); 9268 } 9269 9270 static void 9271 unit_conv(char *buf, size_t len, u_int val, u_int factor) 9272 { 9273 u_int rem = val % factor; 9274 9275 if (rem == 0) 9276 snprintf(buf, len, "%u", val / factor); 9277 else { 9278 while (rem % 10 == 0) 9279 rem /= 10; 9280 snprintf(buf, len, "%u.%u", val / factor, rem); 9281 } 9282 } 9283 9284 static int 9285 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 9286 { 9287 struct adapter *sc = arg1; 9288 char buf[16]; 9289 u_int res, re; 9290 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9291 9292 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9293 switch (arg2) { 9294 case 0: 9295 /* timer_tick */ 9296 re = G_TIMERRESOLUTION(res); 9297 break; 9298 case 1: 9299 /* TCP timestamp tick */ 9300 re = G_TIMESTAMPRESOLUTION(res); 9301 break; 9302 case 2: 9303 /* DACK tick */ 9304 re = G_DELAYEDACKRESOLUTION(res); 9305 break; 9306 default: 9307 return (EDOOFUS); 9308 } 9309 9310 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 9311 9312 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 9313 } 9314 9315 static int 9316 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 9317 { 9318 struct adapter *sc = arg1; 9319 u_int res, dack_re, v; 9320 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9321 9322 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9323 dack_re = G_DELAYEDACKRESOLUTION(res); 9324 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 9325 9326 return (sysctl_handle_int(oidp, &v, 0, req)); 9327 } 9328 9329 static int 9330 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 9331 { 9332 struct adapter *sc = arg1; 9333 int reg = arg2; 9334 u_int tre; 9335 u_long tp_tick_us, v; 9336 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9337 9338 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 9339 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 9340 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 9341 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 9342 9343 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 9344 tp_tick_us = (cclk_ps << tre) / 1000000; 9345 9346 if (reg == A_TP_INIT_SRTT) 9347 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 9348 else 9349 v = tp_tick_us * t4_read_reg(sc, reg); 9350 9351 return (sysctl_handle_long(oidp, &v, 0, req)); 9352 } 9353 9354 /* 9355 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 9356 * passed to this function. 9357 */ 9358 static int 9359 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 9360 { 9361 struct adapter *sc = arg1; 9362 int idx = arg2; 9363 u_int v; 9364 9365 MPASS(idx >= 0 && idx <= 24); 9366 9367 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 9368 9369 return (sysctl_handle_int(oidp, &v, 0, req)); 9370 } 9371 9372 static int 9373 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 9374 { 9375 struct adapter *sc = arg1; 9376 int idx = arg2; 9377 u_int shift, v, r; 9378 9379 MPASS(idx >= 0 && idx < 16); 9380 9381 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 9382 shift = (idx & 3) << 3; 9383 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 9384 9385 return (sysctl_handle_int(oidp, &v, 0, req)); 9386 } 9387 9388 static int 9389 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 9390 { 9391 struct vi_info *vi = arg1; 9392 struct adapter *sc = vi->pi->adapter; 9393 int idx, rc, i; 9394 struct sge_ofld_rxq *ofld_rxq; 9395 uint8_t v; 9396 9397 idx = vi->ofld_tmr_idx; 9398 9399 rc = sysctl_handle_int(oidp, &idx, 0, req); 9400 if (rc != 0 || req->newptr == NULL) 9401 return (rc); 9402 9403 if (idx < 0 || idx >= SGE_NTIMERS) 9404 return (EINVAL); 9405 9406 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9407 "t4otmr"); 9408 if (rc) 9409 return (rc); 9410 9411 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 9412 for_each_ofld_rxq(vi, i, ofld_rxq) { 9413 #ifdef atomic_store_rel_8 9414 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 9415 #else 9416 ofld_rxq->iq.intr_params = v; 9417 #endif 9418 } 9419 vi->ofld_tmr_idx = idx; 9420 9421 end_synchronized_op(sc, LOCK_HELD); 9422 return (0); 9423 } 9424 9425 static int 9426 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 9427 { 9428 struct vi_info *vi = arg1; 9429 struct adapter *sc = vi->pi->adapter; 9430 int idx, rc; 9431 9432 idx = vi->ofld_pktc_idx; 9433 9434 rc = sysctl_handle_int(oidp, &idx, 0, req); 9435 if (rc != 0 || req->newptr == NULL) 9436 return (rc); 9437 9438 if (idx < -1 || idx >= SGE_NCOUNTERS) 9439 return (EINVAL); 9440 9441 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9442 "t4opktc"); 9443 if (rc) 9444 return (rc); 9445 9446 if (vi->flags & VI_INIT_DONE) 9447 rc = EBUSY; /* cannot be changed once the queues are created */ 9448 else 9449 vi->ofld_pktc_idx = idx; 9450 9451 end_synchronized_op(sc, LOCK_HELD); 9452 return (rc); 9453 } 9454 #endif 9455 9456 static int 9457 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 9458 { 9459 int rc; 9460 9461 if (cntxt->cid > M_CTXTQID) 9462 return (EINVAL); 9463 9464 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 9465 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 9466 return (EINVAL); 9467 9468 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 9469 if (rc) 9470 return (rc); 9471 9472 if (sc->flags & FW_OK) { 9473 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 9474 &cntxt->data[0]); 9475 if (rc == 0) 9476 goto done; 9477 } 9478 9479 /* 9480 * Read via firmware failed or wasn't even attempted. Read directly via 9481 * the backdoor. 9482 */ 9483 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 9484 done: 9485 end_synchronized_op(sc, 0); 9486 return (rc); 9487 } 9488 9489 static int 9490 load_fw(struct adapter *sc, struct t4_data *fw) 9491 { 9492 int rc; 9493 uint8_t *fw_data; 9494 9495 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 9496 if (rc) 9497 return (rc); 9498 9499 /* 9500 * The firmware, with the sole exception of the memory parity error 9501 * handler, runs from memory and not flash. It is almost always safe to 9502 * install a new firmware on a running system. Just set bit 1 in 9503 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 9504 */ 9505 if (sc->flags & FULL_INIT_DONE && 9506 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 9507 rc = EBUSY; 9508 goto done; 9509 } 9510 9511 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9512 if (fw_data == NULL) { 9513 rc = ENOMEM; 9514 goto done; 9515 } 9516 9517 rc = copyin(fw->data, fw_data, fw->len); 9518 if (rc == 0) 9519 rc = -t4_load_fw(sc, fw_data, fw->len); 9520 9521 free(fw_data, M_CXGBE); 9522 done: 9523 end_synchronized_op(sc, 0); 9524 return (rc); 9525 } 9526 9527 static int 9528 load_cfg(struct adapter *sc, struct t4_data *cfg) 9529 { 9530 int rc; 9531 uint8_t *cfg_data = NULL; 9532 9533 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9534 if (rc) 9535 return (rc); 9536 9537 if (cfg->len == 0) { 9538 /* clear */ 9539 rc = -t4_load_cfg(sc, NULL, 0); 9540 goto done; 9541 } 9542 9543 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9544 if (cfg_data == NULL) { 9545 rc = ENOMEM; 9546 goto done; 9547 } 9548 9549 rc = copyin(cfg->data, cfg_data, cfg->len); 9550 if (rc == 0) 9551 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9552 9553 free(cfg_data, M_CXGBE); 9554 done: 9555 end_synchronized_op(sc, 0); 9556 return (rc); 9557 } 9558 9559 static int 9560 load_boot(struct adapter *sc, struct t4_bootrom *br) 9561 { 9562 int rc; 9563 uint8_t *br_data = NULL; 9564 u_int offset; 9565 9566 if (br->len > 1024 * 1024) 9567 return (EFBIG); 9568 9569 if (br->pf_offset == 0) { 9570 /* pfidx */ 9571 if (br->pfidx_addr > 7) 9572 return (EINVAL); 9573 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9574 A_PCIE_PF_EXPROM_OFST))); 9575 } else if (br->pf_offset == 1) { 9576 /* offset */ 9577 offset = G_OFFSET(br->pfidx_addr); 9578 } else { 9579 return (EINVAL); 9580 } 9581 9582 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9583 if (rc) 9584 return (rc); 9585 9586 if (br->len == 0) { 9587 /* clear */ 9588 rc = -t4_load_boot(sc, NULL, offset, 0); 9589 goto done; 9590 } 9591 9592 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9593 if (br_data == NULL) { 9594 rc = ENOMEM; 9595 goto done; 9596 } 9597 9598 rc = copyin(br->data, br_data, br->len); 9599 if (rc == 0) 9600 rc = -t4_load_boot(sc, br_data, offset, br->len); 9601 9602 free(br_data, M_CXGBE); 9603 done: 9604 end_synchronized_op(sc, 0); 9605 return (rc); 9606 } 9607 9608 static int 9609 load_bootcfg(struct adapter *sc, struct t4_data *bc) 9610 { 9611 int rc; 9612 uint8_t *bc_data = NULL; 9613 9614 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9615 if (rc) 9616 return (rc); 9617 9618 if (bc->len == 0) { 9619 /* clear */ 9620 rc = -t4_load_bootcfg(sc, NULL, 0); 9621 goto done; 9622 } 9623 9624 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9625 if (bc_data == NULL) { 9626 rc = ENOMEM; 9627 goto done; 9628 } 9629 9630 rc = copyin(bc->data, bc_data, bc->len); 9631 if (rc == 0) 9632 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9633 9634 free(bc_data, M_CXGBE); 9635 done: 9636 end_synchronized_op(sc, 0); 9637 return (rc); 9638 } 9639 9640 static int 9641 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9642 { 9643 int rc; 9644 struct cudbg_init *cudbg; 9645 void *handle, *buf; 9646 9647 /* buf is large, don't block if no memory is available */ 9648 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9649 if (buf == NULL) 9650 return (ENOMEM); 9651 9652 handle = cudbg_alloc_handle(); 9653 if (handle == NULL) { 9654 rc = ENOMEM; 9655 goto done; 9656 } 9657 9658 cudbg = cudbg_get_init(handle); 9659 cudbg->adap = sc; 9660 cudbg->print = (cudbg_print_cb)printf; 9661 9662 #ifndef notyet 9663 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9664 __func__, dump->wr_flash, dump->len, dump->data); 9665 #endif 9666 9667 if (dump->wr_flash) 9668 cudbg->use_flash = 1; 9669 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9670 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9671 9672 rc = cudbg_collect(handle, buf, &dump->len); 9673 if (rc != 0) 9674 goto done; 9675 9676 rc = copyout(buf, dump->data, dump->len); 9677 done: 9678 cudbg_free_handle(handle); 9679 free(buf, M_CXGBE); 9680 return (rc); 9681 } 9682 9683 static void 9684 free_offload_policy(struct t4_offload_policy *op) 9685 { 9686 struct offload_rule *r; 9687 int i; 9688 9689 if (op == NULL) 9690 return; 9691 9692 r = &op->rule[0]; 9693 for (i = 0; i < op->nrules; i++, r++) { 9694 free(r->bpf_prog.bf_insns, M_CXGBE); 9695 } 9696 free(op->rule, M_CXGBE); 9697 free(op, M_CXGBE); 9698 } 9699 9700 static int 9701 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 9702 { 9703 int i, rc, len; 9704 struct t4_offload_policy *op, *old; 9705 struct bpf_program *bf; 9706 const struct offload_settings *s; 9707 struct offload_rule *r; 9708 void *u; 9709 9710 if (!is_offload(sc)) 9711 return (ENODEV); 9712 9713 if (uop->nrules == 0) { 9714 /* Delete installed policies. */ 9715 op = NULL; 9716 goto set_policy; 9717 } if (uop->nrules > 256) { /* arbitrary */ 9718 return (E2BIG); 9719 } 9720 9721 /* Copy userspace offload policy to kernel */ 9722 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 9723 op->nrules = uop->nrules; 9724 len = op->nrules * sizeof(struct offload_rule); 9725 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9726 rc = copyin(uop->rule, op->rule, len); 9727 if (rc) { 9728 free(op->rule, M_CXGBE); 9729 free(op, M_CXGBE); 9730 return (rc); 9731 } 9732 9733 r = &op->rule[0]; 9734 for (i = 0; i < op->nrules; i++, r++) { 9735 9736 /* Validate open_type */ 9737 if (r->open_type != OPEN_TYPE_LISTEN && 9738 r->open_type != OPEN_TYPE_ACTIVE && 9739 r->open_type != OPEN_TYPE_PASSIVE && 9740 r->open_type != OPEN_TYPE_DONTCARE) { 9741 error: 9742 /* 9743 * Rules 0 to i have malloc'd filters that need to be 9744 * freed. Rules i+1 to nrules have userspace pointers 9745 * and should be left alone. 9746 */ 9747 op->nrules = i; 9748 free_offload_policy(op); 9749 return (rc); 9750 } 9751 9752 /* Validate settings */ 9753 s = &r->settings; 9754 if ((s->offload != 0 && s->offload != 1) || 9755 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9756 s->sched_class < -1 || 9757 s->sched_class >= sc->chip_params->nsched_cls) { 9758 rc = EINVAL; 9759 goto error; 9760 } 9761 9762 bf = &r->bpf_prog; 9763 u = bf->bf_insns; /* userspace ptr */ 9764 bf->bf_insns = NULL; 9765 if (bf->bf_len == 0) { 9766 /* legal, matches everything */ 9767 continue; 9768 } 9769 len = bf->bf_len * sizeof(*bf->bf_insns); 9770 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9771 rc = copyin(u, bf->bf_insns, len); 9772 if (rc != 0) 9773 goto error; 9774 9775 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9776 rc = EINVAL; 9777 goto error; 9778 } 9779 } 9780 set_policy: 9781 rw_wlock(&sc->policy_lock); 9782 old = sc->policy; 9783 sc->policy = op; 9784 rw_wunlock(&sc->policy_lock); 9785 free_offload_policy(old); 9786 9787 return (0); 9788 } 9789 9790 #define MAX_READ_BUF_SIZE (128 * 1024) 9791 static int 9792 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9793 { 9794 uint32_t addr, remaining, n; 9795 uint32_t *buf; 9796 int rc; 9797 uint8_t *dst; 9798 9799 rc = validate_mem_range(sc, mr->addr, mr->len); 9800 if (rc != 0) 9801 return (rc); 9802 9803 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9804 addr = mr->addr; 9805 remaining = mr->len; 9806 dst = (void *)mr->data; 9807 9808 while (remaining) { 9809 n = min(remaining, MAX_READ_BUF_SIZE); 9810 read_via_memwin(sc, 2, addr, buf, n); 9811 9812 rc = copyout(buf, dst, n); 9813 if (rc != 0) 9814 break; 9815 9816 dst += n; 9817 remaining -= n; 9818 addr += n; 9819 } 9820 9821 free(buf, M_CXGBE); 9822 return (rc); 9823 } 9824 #undef MAX_READ_BUF_SIZE 9825 9826 static int 9827 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9828 { 9829 int rc; 9830 9831 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9832 return (EINVAL); 9833 9834 if (i2cd->len > sizeof(i2cd->data)) 9835 return (EFBIG); 9836 9837 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9838 if (rc) 9839 return (rc); 9840 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9841 i2cd->offset, i2cd->len, &i2cd->data[0]); 9842 end_synchronized_op(sc, 0); 9843 9844 return (rc); 9845 } 9846 9847 int 9848 t4_os_find_pci_capability(struct adapter *sc, int cap) 9849 { 9850 int i; 9851 9852 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9853 } 9854 9855 int 9856 t4_os_pci_save_state(struct adapter *sc) 9857 { 9858 device_t dev; 9859 struct pci_devinfo *dinfo; 9860 9861 dev = sc->dev; 9862 dinfo = device_get_ivars(dev); 9863 9864 pci_cfg_save(dev, dinfo, 0); 9865 return (0); 9866 } 9867 9868 int 9869 t4_os_pci_restore_state(struct adapter *sc) 9870 { 9871 device_t dev; 9872 struct pci_devinfo *dinfo; 9873 9874 dev = sc->dev; 9875 dinfo = device_get_ivars(dev); 9876 9877 pci_cfg_restore(dev, dinfo); 9878 return (0); 9879 } 9880 9881 void 9882 t4_os_portmod_changed(struct port_info *pi) 9883 { 9884 struct adapter *sc = pi->adapter; 9885 struct vi_info *vi; 9886 struct ifnet *ifp; 9887 static const char *mod_str[] = { 9888 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9889 }; 9890 9891 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 9892 ("%s: port_type %u", __func__, pi->port_type)); 9893 9894 vi = &pi->vi[0]; 9895 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9896 PORT_LOCK(pi); 9897 build_medialist(pi); 9898 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 9899 fixup_link_config(pi); 9900 apply_link_config(pi); 9901 } 9902 PORT_UNLOCK(pi); 9903 end_synchronized_op(sc, LOCK_HELD); 9904 } 9905 9906 ifp = vi->ifp; 9907 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9908 if_printf(ifp, "transceiver unplugged.\n"); 9909 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9910 if_printf(ifp, "unknown transceiver inserted.\n"); 9911 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9912 if_printf(ifp, "unsupported transceiver inserted.\n"); 9913 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9914 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9915 port_top_speed(pi), mod_str[pi->mod_type]); 9916 } else { 9917 if_printf(ifp, "transceiver (type %d) inserted.\n", 9918 pi->mod_type); 9919 } 9920 } 9921 9922 void 9923 t4_os_link_changed(struct port_info *pi) 9924 { 9925 struct vi_info *vi; 9926 struct ifnet *ifp; 9927 struct link_config *lc; 9928 int v; 9929 9930 PORT_LOCK_ASSERT_OWNED(pi); 9931 9932 for_each_vi(pi, v, vi) { 9933 ifp = vi->ifp; 9934 if (ifp == NULL) 9935 continue; 9936 9937 lc = &pi->link_cfg; 9938 if (lc->link_ok) { 9939 ifp->if_baudrate = IF_Mbps(lc->speed); 9940 if_link_state_change(ifp, LINK_STATE_UP); 9941 } else { 9942 if_link_state_change(ifp, LINK_STATE_DOWN); 9943 } 9944 } 9945 } 9946 9947 void 9948 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9949 { 9950 struct adapter *sc; 9951 9952 sx_slock(&t4_list_lock); 9953 SLIST_FOREACH(sc, &t4_list, link) { 9954 /* 9955 * func should not make any assumptions about what state sc is 9956 * in - the only guarantee is that sc->sc_lock is a valid lock. 9957 */ 9958 func(sc, arg); 9959 } 9960 sx_sunlock(&t4_list_lock); 9961 } 9962 9963 static int 9964 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9965 struct thread *td) 9966 { 9967 int rc; 9968 struct adapter *sc = dev->si_drv1; 9969 9970 rc = priv_check(td, PRIV_DRIVER); 9971 if (rc != 0) 9972 return (rc); 9973 9974 switch (cmd) { 9975 case CHELSIO_T4_GETREG: { 9976 struct t4_reg *edata = (struct t4_reg *)data; 9977 9978 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9979 return (EFAULT); 9980 9981 if (edata->size == 4) 9982 edata->val = t4_read_reg(sc, edata->addr); 9983 else if (edata->size == 8) 9984 edata->val = t4_read_reg64(sc, edata->addr); 9985 else 9986 return (EINVAL); 9987 9988 break; 9989 } 9990 case CHELSIO_T4_SETREG: { 9991 struct t4_reg *edata = (struct t4_reg *)data; 9992 9993 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9994 return (EFAULT); 9995 9996 if (edata->size == 4) { 9997 if (edata->val & 0xffffffff00000000) 9998 return (EINVAL); 9999 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 10000 } else if (edata->size == 8) 10001 t4_write_reg64(sc, edata->addr, edata->val); 10002 else 10003 return (EINVAL); 10004 break; 10005 } 10006 case CHELSIO_T4_REGDUMP: { 10007 struct t4_regdump *regs = (struct t4_regdump *)data; 10008 int reglen = t4_get_regs_len(sc); 10009 uint8_t *buf; 10010 10011 if (regs->len < reglen) { 10012 regs->len = reglen; /* hint to the caller */ 10013 return (ENOBUFS); 10014 } 10015 10016 regs->len = reglen; 10017 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 10018 get_regs(sc, regs, buf); 10019 rc = copyout(buf, regs->data, reglen); 10020 free(buf, M_CXGBE); 10021 break; 10022 } 10023 case CHELSIO_T4_GET_FILTER_MODE: 10024 rc = get_filter_mode(sc, (uint32_t *)data); 10025 break; 10026 case CHELSIO_T4_SET_FILTER_MODE: 10027 rc = set_filter_mode(sc, *(uint32_t *)data); 10028 break; 10029 case CHELSIO_T4_GET_FILTER: 10030 rc = get_filter(sc, (struct t4_filter *)data); 10031 break; 10032 case CHELSIO_T4_SET_FILTER: 10033 rc = set_filter(sc, (struct t4_filter *)data); 10034 break; 10035 case CHELSIO_T4_DEL_FILTER: 10036 rc = del_filter(sc, (struct t4_filter *)data); 10037 break; 10038 case CHELSIO_T4_GET_SGE_CONTEXT: 10039 rc = get_sge_context(sc, (struct t4_sge_context *)data); 10040 break; 10041 case CHELSIO_T4_LOAD_FW: 10042 rc = load_fw(sc, (struct t4_data *)data); 10043 break; 10044 case CHELSIO_T4_GET_MEM: 10045 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 10046 break; 10047 case CHELSIO_T4_GET_I2C: 10048 rc = read_i2c(sc, (struct t4_i2c_data *)data); 10049 break; 10050 case CHELSIO_T4_CLEAR_STATS: { 10051 int i, v, bg_map; 10052 u_int port_id = *(uint32_t *)data; 10053 struct port_info *pi; 10054 struct vi_info *vi; 10055 10056 if (port_id >= sc->params.nports) 10057 return (EINVAL); 10058 pi = sc->port[port_id]; 10059 if (pi == NULL) 10060 return (EIO); 10061 10062 /* MAC stats */ 10063 t4_clr_port_stats(sc, pi->tx_chan); 10064 pi->tx_parse_error = 0; 10065 pi->tnl_cong_drops = 0; 10066 mtx_lock(&sc->reg_lock); 10067 for_each_vi(pi, v, vi) { 10068 if (vi->flags & VI_INIT_DONE) 10069 t4_clr_vi_stats(sc, vi->vin); 10070 } 10071 bg_map = pi->mps_bg_map; 10072 v = 0; /* reuse */ 10073 while (bg_map) { 10074 i = ffs(bg_map) - 1; 10075 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 10076 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 10077 bg_map &= ~(1 << i); 10078 } 10079 mtx_unlock(&sc->reg_lock); 10080 10081 /* 10082 * Since this command accepts a port, clear stats for 10083 * all VIs on this port. 10084 */ 10085 for_each_vi(pi, v, vi) { 10086 if (vi->flags & VI_INIT_DONE) { 10087 struct sge_rxq *rxq; 10088 struct sge_txq *txq; 10089 struct sge_wrq *wrq; 10090 10091 for_each_rxq(vi, i, rxq) { 10092 #if defined(INET) || defined(INET6) 10093 rxq->lro.lro_queued = 0; 10094 rxq->lro.lro_flushed = 0; 10095 #endif 10096 rxq->rxcsum = 0; 10097 rxq->vlan_extraction = 0; 10098 } 10099 10100 for_each_txq(vi, i, txq) { 10101 txq->txcsum = 0; 10102 txq->tso_wrs = 0; 10103 txq->vlan_insertion = 0; 10104 txq->imm_wrs = 0; 10105 txq->sgl_wrs = 0; 10106 txq->txpkt_wrs = 0; 10107 txq->txpkts0_wrs = 0; 10108 txq->txpkts1_wrs = 0; 10109 txq->txpkts0_pkts = 0; 10110 txq->txpkts1_pkts = 0; 10111 txq->raw_wrs = 0; 10112 mp_ring_reset_stats(txq->r); 10113 } 10114 10115 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10116 /* nothing to clear for each ofld_rxq */ 10117 10118 for_each_ofld_txq(vi, i, wrq) { 10119 wrq->tx_wrs_direct = 0; 10120 wrq->tx_wrs_copied = 0; 10121 } 10122 #endif 10123 10124 if (IS_MAIN_VI(vi)) { 10125 wrq = &sc->sge.ctrlq[pi->port_id]; 10126 wrq->tx_wrs_direct = 0; 10127 wrq->tx_wrs_copied = 0; 10128 } 10129 } 10130 } 10131 break; 10132 } 10133 case CHELSIO_T4_SCHED_CLASS: 10134 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 10135 break; 10136 case CHELSIO_T4_SCHED_QUEUE: 10137 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 10138 break; 10139 case CHELSIO_T4_GET_TRACER: 10140 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 10141 break; 10142 case CHELSIO_T4_SET_TRACER: 10143 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 10144 break; 10145 case CHELSIO_T4_LOAD_CFG: 10146 rc = load_cfg(sc, (struct t4_data *)data); 10147 break; 10148 case CHELSIO_T4_LOAD_BOOT: 10149 rc = load_boot(sc, (struct t4_bootrom *)data); 10150 break; 10151 case CHELSIO_T4_LOAD_BOOTCFG: 10152 rc = load_bootcfg(sc, (struct t4_data *)data); 10153 break; 10154 case CHELSIO_T4_CUDBG_DUMP: 10155 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 10156 break; 10157 case CHELSIO_T4_SET_OFLD_POLICY: 10158 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 10159 break; 10160 default: 10161 rc = ENOTTY; 10162 } 10163 10164 return (rc); 10165 } 10166 10167 #ifdef TCP_OFFLOAD 10168 static int 10169 toe_capability(struct vi_info *vi, int enable) 10170 { 10171 int rc; 10172 struct port_info *pi = vi->pi; 10173 struct adapter *sc = pi->adapter; 10174 10175 ASSERT_SYNCHRONIZED_OP(sc); 10176 10177 if (!is_offload(sc)) 10178 return (ENODEV); 10179 10180 if (enable) { 10181 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 10182 /* TOE is already enabled. */ 10183 return (0); 10184 } 10185 10186 /* 10187 * We need the port's queues around so that we're able to send 10188 * and receive CPLs to/from the TOE even if the ifnet for this 10189 * port has never been UP'd administratively. 10190 */ 10191 if (!(vi->flags & VI_INIT_DONE)) { 10192 rc = vi_full_init(vi); 10193 if (rc) 10194 return (rc); 10195 } 10196 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 10197 rc = vi_full_init(&pi->vi[0]); 10198 if (rc) 10199 return (rc); 10200 } 10201 10202 if (isset(&sc->offload_map, pi->port_id)) { 10203 /* TOE is enabled on another VI of this port. */ 10204 pi->uld_vis++; 10205 return (0); 10206 } 10207 10208 if (!uld_active(sc, ULD_TOM)) { 10209 rc = t4_activate_uld(sc, ULD_TOM); 10210 if (rc == EAGAIN) { 10211 log(LOG_WARNING, 10212 "You must kldload t4_tom.ko before trying " 10213 "to enable TOE on a cxgbe interface.\n"); 10214 } 10215 if (rc != 0) 10216 return (rc); 10217 KASSERT(sc->tom_softc != NULL, 10218 ("%s: TOM activated but softc NULL", __func__)); 10219 KASSERT(uld_active(sc, ULD_TOM), 10220 ("%s: TOM activated but flag not set", __func__)); 10221 } 10222 10223 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 10224 if (!uld_active(sc, ULD_IWARP)) 10225 (void) t4_activate_uld(sc, ULD_IWARP); 10226 if (!uld_active(sc, ULD_ISCSI)) 10227 (void) t4_activate_uld(sc, ULD_ISCSI); 10228 10229 pi->uld_vis++; 10230 setbit(&sc->offload_map, pi->port_id); 10231 } else { 10232 pi->uld_vis--; 10233 10234 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 10235 return (0); 10236 10237 KASSERT(uld_active(sc, ULD_TOM), 10238 ("%s: TOM never initialized?", __func__)); 10239 clrbit(&sc->offload_map, pi->port_id); 10240 } 10241 10242 return (0); 10243 } 10244 10245 /* 10246 * Add an upper layer driver to the global list. 10247 */ 10248 int 10249 t4_register_uld(struct uld_info *ui) 10250 { 10251 int rc = 0; 10252 struct uld_info *u; 10253 10254 sx_xlock(&t4_uld_list_lock); 10255 SLIST_FOREACH(u, &t4_uld_list, link) { 10256 if (u->uld_id == ui->uld_id) { 10257 rc = EEXIST; 10258 goto done; 10259 } 10260 } 10261 10262 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 10263 ui->refcount = 0; 10264 done: 10265 sx_xunlock(&t4_uld_list_lock); 10266 return (rc); 10267 } 10268 10269 int 10270 t4_unregister_uld(struct uld_info *ui) 10271 { 10272 int rc = EINVAL; 10273 struct uld_info *u; 10274 10275 sx_xlock(&t4_uld_list_lock); 10276 10277 SLIST_FOREACH(u, &t4_uld_list, link) { 10278 if (u == ui) { 10279 if (ui->refcount > 0) { 10280 rc = EBUSY; 10281 goto done; 10282 } 10283 10284 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 10285 rc = 0; 10286 goto done; 10287 } 10288 } 10289 done: 10290 sx_xunlock(&t4_uld_list_lock); 10291 return (rc); 10292 } 10293 10294 int 10295 t4_activate_uld(struct adapter *sc, int id) 10296 { 10297 int rc; 10298 struct uld_info *ui; 10299 10300 ASSERT_SYNCHRONIZED_OP(sc); 10301 10302 if (id < 0 || id > ULD_MAX) 10303 return (EINVAL); 10304 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 10305 10306 sx_slock(&t4_uld_list_lock); 10307 10308 SLIST_FOREACH(ui, &t4_uld_list, link) { 10309 if (ui->uld_id == id) { 10310 if (!(sc->flags & FULL_INIT_DONE)) { 10311 rc = adapter_full_init(sc); 10312 if (rc != 0) 10313 break; 10314 } 10315 10316 rc = ui->activate(sc); 10317 if (rc == 0) { 10318 setbit(&sc->active_ulds, id); 10319 ui->refcount++; 10320 } 10321 break; 10322 } 10323 } 10324 10325 sx_sunlock(&t4_uld_list_lock); 10326 10327 return (rc); 10328 } 10329 10330 int 10331 t4_deactivate_uld(struct adapter *sc, int id) 10332 { 10333 int rc; 10334 struct uld_info *ui; 10335 10336 ASSERT_SYNCHRONIZED_OP(sc); 10337 10338 if (id < 0 || id > ULD_MAX) 10339 return (EINVAL); 10340 rc = ENXIO; 10341 10342 sx_slock(&t4_uld_list_lock); 10343 10344 SLIST_FOREACH(ui, &t4_uld_list, link) { 10345 if (ui->uld_id == id) { 10346 rc = ui->deactivate(sc); 10347 if (rc == 0) { 10348 clrbit(&sc->active_ulds, id); 10349 ui->refcount--; 10350 } 10351 break; 10352 } 10353 } 10354 10355 sx_sunlock(&t4_uld_list_lock); 10356 10357 return (rc); 10358 } 10359 10360 int 10361 uld_active(struct adapter *sc, int uld_id) 10362 { 10363 10364 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 10365 10366 return (isset(&sc->active_ulds, uld_id)); 10367 } 10368 #endif 10369 10370 /* 10371 * t = ptr to tunable. 10372 * nc = number of CPUs. 10373 * c = compiled in default for that tunable. 10374 */ 10375 static void 10376 calculate_nqueues(int *t, int nc, const int c) 10377 { 10378 int nq; 10379 10380 if (*t > 0) 10381 return; 10382 nq = *t < 0 ? -*t : c; 10383 *t = min(nc, nq); 10384 } 10385 10386 /* 10387 * Come up with reasonable defaults for some of the tunables, provided they're 10388 * not set by the user (in which case we'll use the values as is). 10389 */ 10390 static void 10391 tweak_tunables(void) 10392 { 10393 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 10394 10395 if (t4_ntxq < 1) { 10396 #ifdef RSS 10397 t4_ntxq = rss_getnumbuckets(); 10398 #else 10399 calculate_nqueues(&t4_ntxq, nc, NTXQ); 10400 #endif 10401 } 10402 10403 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 10404 10405 if (t4_nrxq < 1) { 10406 #ifdef RSS 10407 t4_nrxq = rss_getnumbuckets(); 10408 #else 10409 calculate_nqueues(&t4_nrxq, nc, NRXQ); 10410 #endif 10411 } 10412 10413 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 10414 10415 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10416 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 10417 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 10418 #endif 10419 #ifdef TCP_OFFLOAD 10420 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 10421 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 10422 10423 if (t4_toecaps_allowed == -1) 10424 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 10425 10426 if (t4_rdmacaps_allowed == -1) { 10427 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 10428 FW_CAPS_CONFIG_RDMA_RDMAC; 10429 } 10430 10431 if (t4_iscsicaps_allowed == -1) { 10432 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 10433 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 10434 FW_CAPS_CONFIG_ISCSI_T10DIF; 10435 } 10436 10437 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 10438 t4_tmr_idx_ofld = TMR_IDX_OFLD; 10439 10440 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 10441 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 10442 #else 10443 if (t4_toecaps_allowed == -1) 10444 t4_toecaps_allowed = 0; 10445 10446 if (t4_rdmacaps_allowed == -1) 10447 t4_rdmacaps_allowed = 0; 10448 10449 if (t4_iscsicaps_allowed == -1) 10450 t4_iscsicaps_allowed = 0; 10451 #endif 10452 10453 #ifdef DEV_NETMAP 10454 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 10455 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 10456 #endif 10457 10458 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 10459 t4_tmr_idx = TMR_IDX; 10460 10461 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 10462 t4_pktc_idx = PKTC_IDX; 10463 10464 if (t4_qsize_txq < 128) 10465 t4_qsize_txq = 128; 10466 10467 if (t4_qsize_rxq < 128) 10468 t4_qsize_rxq = 128; 10469 while (t4_qsize_rxq & 7) 10470 t4_qsize_rxq++; 10471 10472 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 10473 10474 /* 10475 * Number of VIs to create per-port. The first VI is the "main" regular 10476 * VI for the port. The rest are additional virtual interfaces on the 10477 * same physical port. Note that the main VI does not have native 10478 * netmap support but the extra VIs do. 10479 * 10480 * Limit the number of VIs per port to the number of available 10481 * MAC addresses per port. 10482 */ 10483 if (t4_num_vis < 1) 10484 t4_num_vis = 1; 10485 if (t4_num_vis > nitems(vi_mac_funcs)) { 10486 t4_num_vis = nitems(vi_mac_funcs); 10487 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 10488 } 10489 10490 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 10491 pcie_relaxed_ordering = 1; 10492 #if defined(__i386__) || defined(__amd64__) 10493 if (cpu_vendor_id == CPU_VENDOR_INTEL) 10494 pcie_relaxed_ordering = 0; 10495 #endif 10496 } 10497 } 10498 10499 #ifdef DDB 10500 static void 10501 t4_dump_tcb(struct adapter *sc, int tid) 10502 { 10503 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 10504 10505 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 10506 save = t4_read_reg(sc, reg); 10507 base = sc->memwin[2].mw_base; 10508 10509 /* Dump TCB for the tid */ 10510 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 10511 tcb_addr += tid * TCB_SIZE; 10512 10513 if (is_t4(sc)) { 10514 pf = 0; 10515 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 10516 } else { 10517 pf = V_PFNUM(sc->pf); 10518 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 10519 } 10520 t4_write_reg(sc, reg, win_pos | pf); 10521 t4_read_reg(sc, reg); 10522 10523 off = tcb_addr - win_pos; 10524 for (i = 0; i < 4; i++) { 10525 uint32_t buf[8]; 10526 for (j = 0; j < 8; j++, off += 4) 10527 buf[j] = htonl(t4_read_reg(sc, base + off)); 10528 10529 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 10530 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 10531 buf[7]); 10532 } 10533 10534 t4_write_reg(sc, reg, save); 10535 t4_read_reg(sc, reg); 10536 } 10537 10538 static void 10539 t4_dump_devlog(struct adapter *sc) 10540 { 10541 struct devlog_params *dparams = &sc->params.devlog; 10542 struct fw_devlog_e e; 10543 int i, first, j, m, nentries, rc; 10544 uint64_t ftstamp = UINT64_MAX; 10545 10546 if (dparams->start == 0) { 10547 db_printf("devlog params not valid\n"); 10548 return; 10549 } 10550 10551 nentries = dparams->size / sizeof(struct fw_devlog_e); 10552 m = fwmtype_to_hwmtype(dparams->memtype); 10553 10554 /* Find the first entry. */ 10555 first = -1; 10556 for (i = 0; i < nentries && !db_pager_quit; i++) { 10557 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10558 sizeof(e), (void *)&e); 10559 if (rc != 0) 10560 break; 10561 10562 if (e.timestamp == 0) 10563 break; 10564 10565 e.timestamp = be64toh(e.timestamp); 10566 if (e.timestamp < ftstamp) { 10567 ftstamp = e.timestamp; 10568 first = i; 10569 } 10570 } 10571 10572 if (first == -1) 10573 return; 10574 10575 i = first; 10576 do { 10577 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10578 sizeof(e), (void *)&e); 10579 if (rc != 0) 10580 return; 10581 10582 if (e.timestamp == 0) 10583 return; 10584 10585 e.timestamp = be64toh(e.timestamp); 10586 e.seqno = be32toh(e.seqno); 10587 for (j = 0; j < 8; j++) 10588 e.params[j] = be32toh(e.params[j]); 10589 10590 db_printf("%10d %15ju %8s %8s ", 10591 e.seqno, e.timestamp, 10592 (e.level < nitems(devlog_level_strings) ? 10593 devlog_level_strings[e.level] : "UNKNOWN"), 10594 (e.facility < nitems(devlog_facility_strings) ? 10595 devlog_facility_strings[e.facility] : "UNKNOWN")); 10596 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10597 e.params[3], e.params[4], e.params[5], e.params[6], 10598 e.params[7]); 10599 10600 if (++i == nentries) 10601 i = 0; 10602 } while (i != first && !db_pager_quit); 10603 } 10604 10605 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10606 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10607 10608 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10609 { 10610 device_t dev; 10611 int t; 10612 bool valid; 10613 10614 valid = false; 10615 t = db_read_token(); 10616 if (t == tIDENT) { 10617 dev = device_lookup_by_name(db_tok_string); 10618 valid = true; 10619 } 10620 db_skip_to_eol(); 10621 if (!valid) { 10622 db_printf("usage: show t4 devlog <nexus>\n"); 10623 return; 10624 } 10625 10626 if (dev == NULL) { 10627 db_printf("device not found\n"); 10628 return; 10629 } 10630 10631 t4_dump_devlog(device_get_softc(dev)); 10632 } 10633 10634 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10635 { 10636 device_t dev; 10637 int radix, tid, t; 10638 bool valid; 10639 10640 valid = false; 10641 radix = db_radix; 10642 db_radix = 10; 10643 t = db_read_token(); 10644 if (t == tIDENT) { 10645 dev = device_lookup_by_name(db_tok_string); 10646 t = db_read_token(); 10647 if (t == tNUMBER) { 10648 tid = db_tok_number; 10649 valid = true; 10650 } 10651 } 10652 db_radix = radix; 10653 db_skip_to_eol(); 10654 if (!valid) { 10655 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10656 return; 10657 } 10658 10659 if (dev == NULL) { 10660 db_printf("device not found\n"); 10661 return; 10662 } 10663 if (tid < 0) { 10664 db_printf("invalid tid\n"); 10665 return; 10666 } 10667 10668 t4_dump_tcb(device_get_softc(dev), tid); 10669 } 10670 #endif 10671 10672 /* 10673 * Borrowed from cesa_prep_aes_key(). 10674 * 10675 * NB: The crypto engine wants the words in the decryption key in reverse 10676 * order. 10677 */ 10678 void 10679 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 10680 { 10681 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 10682 uint32_t *dkey; 10683 int i; 10684 10685 rijndaelKeySetupEnc(ek, enc_key, kbits); 10686 dkey = dec_key; 10687 dkey += (kbits / 8) / 4; 10688 10689 switch (kbits) { 10690 case 128: 10691 for (i = 0; i < 4; i++) 10692 *--dkey = htobe32(ek[4 * 10 + i]); 10693 break; 10694 case 192: 10695 for (i = 0; i < 2; i++) 10696 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10697 for (i = 0; i < 4; i++) 10698 *--dkey = htobe32(ek[4 * 12 + i]); 10699 break; 10700 case 256: 10701 for (i = 0; i < 4; i++) 10702 *--dkey = htobe32(ek[4 * 13 + i]); 10703 for (i = 0; i < 4; i++) 10704 *--dkey = htobe32(ek[4 * 14 + i]); 10705 break; 10706 } 10707 MPASS(dkey == dec_key); 10708 } 10709 10710 static struct sx mlu; /* mod load unload */ 10711 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10712 10713 static int 10714 mod_event(module_t mod, int cmd, void *arg) 10715 { 10716 int rc = 0; 10717 static int loaded = 0; 10718 10719 switch (cmd) { 10720 case MOD_LOAD: 10721 sx_xlock(&mlu); 10722 if (loaded++ == 0) { 10723 t4_sge_modload(); 10724 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10725 t4_filter_rpl, CPL_COOKIE_FILTER); 10726 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 10727 do_l2t_write_rpl, CPL_COOKIE_FILTER); 10728 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 10729 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 10730 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10731 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 10732 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 10733 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10734 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10735 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10736 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 10737 do_smt_write_rpl); 10738 sx_init(&t4_list_lock, "T4/T5 adapters"); 10739 SLIST_INIT(&t4_list); 10740 callout_init(&fatal_callout, 1); 10741 #ifdef TCP_OFFLOAD 10742 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10743 SLIST_INIT(&t4_uld_list); 10744 #endif 10745 #ifdef INET6 10746 t4_clip_modload(); 10747 #endif 10748 t4_tracer_modload(); 10749 tweak_tunables(); 10750 } 10751 sx_xunlock(&mlu); 10752 break; 10753 10754 case MOD_UNLOAD: 10755 sx_xlock(&mlu); 10756 if (--loaded == 0) { 10757 int tries; 10758 10759 sx_slock(&t4_list_lock); 10760 if (!SLIST_EMPTY(&t4_list)) { 10761 rc = EBUSY; 10762 sx_sunlock(&t4_list_lock); 10763 goto done_unload; 10764 } 10765 #ifdef TCP_OFFLOAD 10766 sx_slock(&t4_uld_list_lock); 10767 if (!SLIST_EMPTY(&t4_uld_list)) { 10768 rc = EBUSY; 10769 sx_sunlock(&t4_uld_list_lock); 10770 sx_sunlock(&t4_list_lock); 10771 goto done_unload; 10772 } 10773 #endif 10774 tries = 0; 10775 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10776 uprintf("%ju clusters with custom free routine " 10777 "still is use.\n", t4_sge_extfree_refs()); 10778 pause("t4unload", 2 * hz); 10779 } 10780 #ifdef TCP_OFFLOAD 10781 sx_sunlock(&t4_uld_list_lock); 10782 #endif 10783 sx_sunlock(&t4_list_lock); 10784 10785 if (t4_sge_extfree_refs() == 0) { 10786 t4_tracer_modunload(); 10787 #ifdef INET6 10788 t4_clip_modunload(); 10789 #endif 10790 #ifdef TCP_OFFLOAD 10791 sx_destroy(&t4_uld_list_lock); 10792 #endif 10793 sx_destroy(&t4_list_lock); 10794 t4_sge_modunload(); 10795 loaded = 0; 10796 } else { 10797 rc = EBUSY; 10798 loaded++; /* undo earlier decrement */ 10799 } 10800 } 10801 done_unload: 10802 sx_xunlock(&mlu); 10803 break; 10804 } 10805 10806 return (rc); 10807 } 10808 10809 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10810 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10811 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10812 10813 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10814 MODULE_VERSION(t4nex, 1); 10815 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10816 #ifdef DEV_NETMAP 10817 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10818 #endif /* DEV_NETMAP */ 10819 10820 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10821 MODULE_VERSION(t5nex, 1); 10822 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10823 #ifdef DEV_NETMAP 10824 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10825 #endif /* DEV_NETMAP */ 10826 10827 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10828 MODULE_VERSION(t6nex, 1); 10829 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10830 #ifdef DEV_NETMAP 10831 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10832 #endif /* DEV_NETMAP */ 10833 10834 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10835 MODULE_VERSION(cxgbe, 1); 10836 10837 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10838 MODULE_VERSION(cxl, 1); 10839 10840 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10841 MODULE_VERSION(cc, 1); 10842 10843 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10844 MODULE_VERSION(vcxgbe, 1); 10845 10846 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10847 MODULE_VERSION(vcxl, 1); 10848 10849 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10850 MODULE_VERSION(vcc, 1); 10851