1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "opt_ddb.h" 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_kern_tls.h" 35 #include "opt_ratelimit.h" 36 #include "opt_rss.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/priv.h> 41 #include <sys/kernel.h> 42 #include <sys/bus.h> 43 #include <sys/eventhandler.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #ifdef KERN_TLS 69 #include <netinet/tcp_seq.h> 70 #endif 71 #if defined(__i386__) || defined(__amd64__) 72 #include <machine/md_var.h> 73 #include <machine/cputypes.h> 74 #include <vm/vm.h> 75 #include <vm/pmap.h> 76 #endif 77 #ifdef DDB 78 #include <ddb/ddb.h> 79 #include <ddb/db_lex.h> 80 #endif 81 82 #include "common/common.h" 83 #include "common/t4_msg.h" 84 #include "common/t4_regs.h" 85 #include "common/t4_regs_values.h" 86 #include "cudbg/cudbg.h" 87 #include "t4_clip.h" 88 #include "t4_ioctl.h" 89 #include "t4_l2t.h" 90 #include "t4_mp_ring.h" 91 #include "t4_if.h" 92 #include "t4_smt.h" 93 94 /* T4 bus driver interface */ 95 static int t4_probe(device_t); 96 static int t4_attach(device_t); 97 static int t4_detach(device_t); 98 static int t4_child_location(device_t, device_t, struct sbuf *); 99 static int t4_ready(device_t); 100 static int t4_read_port_device(device_t, int, device_t *); 101 static int t4_suspend(device_t); 102 static int t4_resume(device_t); 103 static int t4_reset_prepare(device_t, device_t); 104 static int t4_reset_post(device_t, device_t); 105 static device_method_t t4_methods[] = { 106 DEVMETHOD(device_probe, t4_probe), 107 DEVMETHOD(device_attach, t4_attach), 108 DEVMETHOD(device_detach, t4_detach), 109 DEVMETHOD(device_suspend, t4_suspend), 110 DEVMETHOD(device_resume, t4_resume), 111 112 DEVMETHOD(bus_child_location, t4_child_location), 113 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 114 DEVMETHOD(bus_reset_post, t4_reset_post), 115 116 DEVMETHOD(t4_is_main_ready, t4_ready), 117 DEVMETHOD(t4_read_port_device, t4_read_port_device), 118 119 DEVMETHOD_END 120 }; 121 static driver_t t4_driver = { 122 "t4nex", 123 t4_methods, 124 sizeof(struct adapter) 125 }; 126 127 128 /* T4 port (cxgbe) interface */ 129 static int cxgbe_probe(device_t); 130 static int cxgbe_attach(device_t); 131 static int cxgbe_detach(device_t); 132 device_method_t cxgbe_methods[] = { 133 DEVMETHOD(device_probe, cxgbe_probe), 134 DEVMETHOD(device_attach, cxgbe_attach), 135 DEVMETHOD(device_detach, cxgbe_detach), 136 { 0, 0 } 137 }; 138 static driver_t cxgbe_driver = { 139 "cxgbe", 140 cxgbe_methods, 141 sizeof(struct port_info) 142 }; 143 144 /* T4 VI (vcxgbe) interface */ 145 static int vcxgbe_probe(device_t); 146 static int vcxgbe_attach(device_t); 147 static int vcxgbe_detach(device_t); 148 static device_method_t vcxgbe_methods[] = { 149 DEVMETHOD(device_probe, vcxgbe_probe), 150 DEVMETHOD(device_attach, vcxgbe_attach), 151 DEVMETHOD(device_detach, vcxgbe_detach), 152 { 0, 0 } 153 }; 154 static driver_t vcxgbe_driver = { 155 "vcxgbe", 156 vcxgbe_methods, 157 sizeof(struct vi_info) 158 }; 159 160 static d_ioctl_t t4_ioctl; 161 162 static struct cdevsw t4_cdevsw = { 163 .d_version = D_VERSION, 164 .d_ioctl = t4_ioctl, 165 .d_name = "t4nex", 166 }; 167 168 /* T5 bus driver interface */ 169 static int t5_probe(device_t); 170 static device_method_t t5_methods[] = { 171 DEVMETHOD(device_probe, t5_probe), 172 DEVMETHOD(device_attach, t4_attach), 173 DEVMETHOD(device_detach, t4_detach), 174 DEVMETHOD(device_suspend, t4_suspend), 175 DEVMETHOD(device_resume, t4_resume), 176 177 DEVMETHOD(bus_child_location, t4_child_location), 178 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 179 DEVMETHOD(bus_reset_post, t4_reset_post), 180 181 DEVMETHOD(t4_is_main_ready, t4_ready), 182 DEVMETHOD(t4_read_port_device, t4_read_port_device), 183 184 DEVMETHOD_END 185 }; 186 static driver_t t5_driver = { 187 "t5nex", 188 t5_methods, 189 sizeof(struct adapter) 190 }; 191 192 193 /* T5 port (cxl) interface */ 194 static driver_t cxl_driver = { 195 "cxl", 196 cxgbe_methods, 197 sizeof(struct port_info) 198 }; 199 200 /* T5 VI (vcxl) interface */ 201 static driver_t vcxl_driver = { 202 "vcxl", 203 vcxgbe_methods, 204 sizeof(struct vi_info) 205 }; 206 207 /* T6 bus driver interface */ 208 static int t6_probe(device_t); 209 static device_method_t t6_methods[] = { 210 DEVMETHOD(device_probe, t6_probe), 211 DEVMETHOD(device_attach, t4_attach), 212 DEVMETHOD(device_detach, t4_detach), 213 DEVMETHOD(device_suspend, t4_suspend), 214 DEVMETHOD(device_resume, t4_resume), 215 216 DEVMETHOD(bus_child_location, t4_child_location), 217 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 218 DEVMETHOD(bus_reset_post, t4_reset_post), 219 220 DEVMETHOD(t4_is_main_ready, t4_ready), 221 DEVMETHOD(t4_read_port_device, t4_read_port_device), 222 223 DEVMETHOD_END 224 }; 225 static driver_t t6_driver = { 226 "t6nex", 227 t6_methods, 228 sizeof(struct adapter) 229 }; 230 231 232 /* T6 port (cc) interface */ 233 static driver_t cc_driver = { 234 "cc", 235 cxgbe_methods, 236 sizeof(struct port_info) 237 }; 238 239 /* T6 VI (vcc) interface */ 240 static driver_t vcc_driver = { 241 "vcc", 242 vcxgbe_methods, 243 sizeof(struct vi_info) 244 }; 245 246 /* ifnet interface */ 247 static void cxgbe_init(void *); 248 static int cxgbe_ioctl(if_t, unsigned long, caddr_t); 249 static int cxgbe_transmit(if_t, struct mbuf *); 250 static void cxgbe_qflush(if_t); 251 #if defined(KERN_TLS) || defined(RATELIMIT) 252 static int cxgbe_snd_tag_alloc(if_t, union if_snd_tag_alloc_params *, 253 struct m_snd_tag **); 254 #endif 255 256 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 257 258 /* 259 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 260 * then ADAPTER_LOCK, then t4_uld_list_lock. 261 */ 262 static struct sx t4_list_lock; 263 SLIST_HEAD(, adapter) t4_list; 264 #ifdef TCP_OFFLOAD 265 static struct sx t4_uld_list_lock; 266 struct uld_info *t4_uld_list[ULD_MAX + 1]; 267 #endif 268 269 /* 270 * Tunables. See tweak_tunables() too. 271 * 272 * Each tunable is set to a default value here if it's known at compile-time. 273 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 274 * provide a reasonable default (upto n) when the driver is loaded. 275 * 276 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 277 * T5 are under hw.cxl. 278 */ 279 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 280 "cxgbe(4) parameters"); 281 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 282 "cxgbe(4) T5+ parameters"); 283 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 284 "cxgbe(4) TOE parameters"); 285 286 /* 287 * Number of queues for tx and rx, NIC and offload. 288 */ 289 #define NTXQ 16 290 int t4_ntxq = -NTXQ; 291 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 292 "Number of TX queues per port"); 293 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 294 295 #define NRXQ 8 296 int t4_nrxq = -NRXQ; 297 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 298 "Number of RX queues per port"); 299 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 300 301 #define NTXQ_VI 1 302 static int t4_ntxq_vi = -NTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 304 "Number of TX queues per VI"); 305 306 #define NRXQ_VI 1 307 static int t4_nrxq_vi = -NRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 309 "Number of RX queues per VI"); 310 311 static int t4_rsrv_noflowq = 0; 312 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 313 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 314 315 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 316 #define NOFLDTXQ 8 317 static int t4_nofldtxq = -NOFLDTXQ; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 319 "Number of offload TX queues per port"); 320 321 #define NOFLDRXQ 2 322 static int t4_nofldrxq = -NOFLDRXQ; 323 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 324 "Number of offload RX queues per port"); 325 326 #define NOFLDTXQ_VI 1 327 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 328 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 329 "Number of offload TX queues per VI"); 330 331 #define NOFLDRXQ_VI 1 332 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 333 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 334 "Number of offload RX queues per VI"); 335 336 #define TMR_IDX_OFLD 1 337 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 338 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 339 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 340 341 #define PKTC_IDX_OFLD (-1) 342 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 343 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 344 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 345 346 /* 0 means chip/fw default, non-zero number is value in microseconds */ 347 static u_long t4_toe_keepalive_idle = 0; 348 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 349 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 350 351 /* 0 means chip/fw default, non-zero number is value in microseconds */ 352 static u_long t4_toe_keepalive_interval = 0; 353 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 354 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 355 356 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 357 static int t4_toe_keepalive_count = 0; 358 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 359 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 360 361 /* 0 means chip/fw default, non-zero number is value in microseconds */ 362 static u_long t4_toe_rexmt_min = 0; 363 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 365 366 /* 0 means chip/fw default, non-zero number is value in microseconds */ 367 static u_long t4_toe_rexmt_max = 0; 368 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 369 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 370 371 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 372 static int t4_toe_rexmt_count = 0; 373 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 375 376 /* -1 means chip/fw default, other values are raw backoff values to use */ 377 static int t4_toe_rexmt_backoff[16] = { 378 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 379 }; 380 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, 381 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 382 "cxgbe(4) TOE retransmit backoff values"); 383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[0], 0, ""); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[1], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[2], 0, ""); 389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 390 &t4_toe_rexmt_backoff[3], 0, ""); 391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 392 &t4_toe_rexmt_backoff[4], 0, ""); 393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 394 &t4_toe_rexmt_backoff[5], 0, ""); 395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 396 &t4_toe_rexmt_backoff[6], 0, ""); 397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 398 &t4_toe_rexmt_backoff[7], 0, ""); 399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 400 &t4_toe_rexmt_backoff[8], 0, ""); 401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 402 &t4_toe_rexmt_backoff[9], 0, ""); 403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 404 &t4_toe_rexmt_backoff[10], 0, ""); 405 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 406 &t4_toe_rexmt_backoff[11], 0, ""); 407 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 408 &t4_toe_rexmt_backoff[12], 0, ""); 409 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 410 &t4_toe_rexmt_backoff[13], 0, ""); 411 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 412 &t4_toe_rexmt_backoff[14], 0, ""); 413 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 414 &t4_toe_rexmt_backoff[15], 0, ""); 415 416 int t4_ddp_rcvbuf_len = 256 * 1024; 417 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_len, CTLFLAG_RWTUN, 418 &t4_ddp_rcvbuf_len, 0, "length of each DDP RX buffer"); 419 420 unsigned int t4_ddp_rcvbuf_cache = 4; 421 SYSCTL_UINT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_cache, CTLFLAG_RWTUN, 422 &t4_ddp_rcvbuf_cache, 0, 423 "maximum number of free DDP RX buffers to cache per connection"); 424 #endif 425 426 #ifdef DEV_NETMAP 427 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */ 428 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */ 429 static int t4_native_netmap = NN_EXTRA_VI; 430 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap, 431 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs"); 432 433 #define NNMTXQ 8 434 static int t4_nnmtxq = -NNMTXQ; 435 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0, 436 "Number of netmap TX queues"); 437 438 #define NNMRXQ 8 439 static int t4_nnmrxq = -NNMRXQ; 440 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0, 441 "Number of netmap RX queues"); 442 443 #define NNMTXQ_VI 2 444 static int t4_nnmtxq_vi = -NNMTXQ_VI; 445 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 446 "Number of netmap TX queues per VI"); 447 448 #define NNMRXQ_VI 2 449 static int t4_nnmrxq_vi = -NNMRXQ_VI; 450 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 451 "Number of netmap RX queues per VI"); 452 #endif 453 454 /* 455 * Holdoff parameters for ports. 456 */ 457 #define TMR_IDX 1 458 int t4_tmr_idx = TMR_IDX; 459 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 460 0, "Holdoff timer index"); 461 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 462 463 #define PKTC_IDX (-1) 464 int t4_pktc_idx = PKTC_IDX; 465 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 466 0, "Holdoff packet counter index"); 467 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 468 469 /* 470 * Size (# of entries) of each tx and rx queue. 471 */ 472 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 473 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 474 "Number of descriptors in each TX queue"); 475 476 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 477 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 478 "Number of descriptors in each RX queue"); 479 480 /* 481 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 482 */ 483 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 484 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 485 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 486 487 /* 488 * Configuration file. All the _CF names here are special. 489 */ 490 #define DEFAULT_CF "default" 491 #define BUILTIN_CF "built-in" 492 #define FLASH_CF "flash" 493 #define UWIRE_CF "uwire" 494 #define FPGA_CF "fpga" 495 static char t4_cfg_file[32] = DEFAULT_CF; 496 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 497 sizeof(t4_cfg_file), "Firmware configuration file"); 498 499 /* 500 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 501 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 502 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 503 * mark or when signalled to do so, 0 to never emit PAUSE. 504 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 505 * negotiated settings will override rx_pause/tx_pause. 506 * Otherwise rx_pause/tx_pause are applied forcibly. 507 */ 508 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 509 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 510 &t4_pause_settings, 0, 511 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 512 513 /* 514 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 515 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 516 * 0 to disable FEC. 517 */ 518 static int t4_fec = -1; 519 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 520 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 521 522 /* 523 * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it 524 * issues to the firmware. If the firmware doesn't support FORCE_FEC then the 525 * driver runs as if this is set to 0. 526 * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay. 527 * 0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the 528 * transceiver. Multiple FEC bits may not be okay but will be passed on to 529 * the firmware anyway (may result in l1cfg errors with old firmwares). 530 * 1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO 531 * means set all FEC bits that are valid for the speed. 532 */ 533 static int t4_force_fec = -1; 534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0, 535 "Controls the use of FORCE_FEC bit in L1 configuration."); 536 537 /* 538 * Link autonegotiation. 539 * -1 to run with the firmware default. 540 * 0 to disable. 541 * 1 to enable. 542 */ 543 static int t4_autoneg = -1; 544 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 545 "Link autonegotiation"); 546 547 /* 548 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 549 * encouraged respectively). '-n' is the same as 'n' except the firmware 550 * version used in the checks is read from the firmware bundled with the driver. 551 */ 552 static int t4_fw_install = 1; 553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 554 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 555 556 /* 557 * ASIC features that will be used. Disable the ones you don't want so that the 558 * chip resources aren't wasted on features that will not be used. 559 */ 560 static int t4_nbmcaps_allowed = 0; 561 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 562 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 563 564 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 565 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 566 &t4_linkcaps_allowed, 0, "Default link capabilities"); 567 568 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 569 FW_CAPS_CONFIG_SWITCH_EGRESS; 570 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 571 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 572 573 #ifdef RATELIMIT 574 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 575 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 576 #else 577 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 578 FW_CAPS_CONFIG_NIC_HASHFILTER; 579 #endif 580 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 581 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 582 583 static int t4_toecaps_allowed = -1; 584 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 585 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 586 587 static int t4_rdmacaps_allowed = -1; 588 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 589 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 590 591 static int t4_cryptocaps_allowed = -1; 592 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 593 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 594 595 static int t4_iscsicaps_allowed = -1; 596 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 597 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 598 599 static int t4_fcoecaps_allowed = 0; 600 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 601 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 602 603 static int t5_write_combine = 0; 604 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 605 0, "Use WC instead of UC for BAR2"); 606 607 /* From t4_sysctls: doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"} */ 608 static int t4_doorbells_allowed = 0xf; 609 SYSCTL_INT(_hw_cxgbe, OID_AUTO, doorbells_allowed, CTLFLAG_RDTUN, 610 &t4_doorbells_allowed, 0, "Limit tx queues to these doorbells"); 611 612 static int t4_num_vis = 1; 613 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 614 "Number of VIs per port"); 615 616 /* 617 * PCIe Relaxed Ordering. 618 * -1: driver should figure out a good value. 619 * 0: disable RO. 620 * 1: enable RO. 621 * 2: leave RO alone. 622 */ 623 static int pcie_relaxed_ordering = -1; 624 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 625 &pcie_relaxed_ordering, 0, 626 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 627 628 static int t4_panic_on_fatal_err = 0; 629 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN, 630 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 631 632 static int t4_reset_on_fatal_err = 0; 633 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN, 634 &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors"); 635 636 static int t4_clock_gate_on_suspend = 0; 637 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN, 638 &t4_clock_gate_on_suspend, 0, "gate the clock on suspend"); 639 640 static int t4_tx_vm_wr = 0; 641 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0, 642 "Use VM work requests to transmit packets."); 643 644 /* 645 * Set to non-zero to enable the attack filter. A packet that matches any of 646 * these conditions will get dropped on ingress: 647 * 1) IP && source address == destination address. 648 * 2) TCP/IP && source address is not a unicast address. 649 * 3) TCP/IP && destination address is not a unicast address. 650 * 4) IP && source address is loopback (127.x.y.z). 651 * 5) IP && destination address is loopback (127.x.y.z). 652 * 6) IPv6 && source address == destination address. 653 * 7) IPv6 && source address is not a unicast address. 654 * 8) IPv6 && source address is loopback (::1/128). 655 * 9) IPv6 && destination address is loopback (::1/128). 656 * 10) IPv6 && source address is unspecified (::/128). 657 * 11) IPv6 && destination address is unspecified (::/128). 658 * 12) TCP/IPv6 && source address is multicast (ff00::/8). 659 * 13) TCP/IPv6 && destination address is multicast (ff00::/8). 660 */ 661 static int t4_attack_filter = 0; 662 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN, 663 &t4_attack_filter, 0, "Drop suspicious traffic"); 664 665 static int t4_drop_ip_fragments = 0; 666 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN, 667 &t4_drop_ip_fragments, 0, "Drop IP fragments"); 668 669 static int t4_drop_pkts_with_l2_errors = 1; 670 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN, 671 &t4_drop_pkts_with_l2_errors, 0, 672 "Drop all frames with Layer 2 length or checksum errors"); 673 674 static int t4_drop_pkts_with_l3_errors = 0; 675 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN, 676 &t4_drop_pkts_with_l3_errors, 0, 677 "Drop all frames with IP version, length, or checksum errors"); 678 679 static int t4_drop_pkts_with_l4_errors = 0; 680 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN, 681 &t4_drop_pkts_with_l4_errors, 0, 682 "Drop all frames with Layer 4 length, checksum, or other errors"); 683 684 #ifdef TCP_OFFLOAD 685 /* 686 * TOE tunables. 687 */ 688 static int t4_cop_managed_offloading = 0; 689 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 690 &t4_cop_managed_offloading, 0, 691 "COP (Connection Offload Policy) controls all TOE offload"); 692 #endif 693 694 #ifdef KERN_TLS 695 /* 696 * This enables KERN_TLS for all adapters if set. 697 */ 698 static int t4_kern_tls = 0; 699 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0, 700 "Enable KERN_TLS mode for T6 adapters"); 701 702 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 703 "cxgbe(4) KERN_TLS parameters"); 704 705 static int t4_tls_inline_keys = 0; 706 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN, 707 &t4_tls_inline_keys, 0, 708 "Always pass TLS keys in work requests (1) or attempt to store TLS keys " 709 "in card memory."); 710 711 static int t4_tls_combo_wrs = 0; 712 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs, 713 0, "Attempt to combine TCB field updates with TLS record work requests."); 714 #endif 715 716 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 717 static int vi_mac_funcs[] = { 718 FW_VI_FUNC_ETH, 719 FW_VI_FUNC_OFLD, 720 FW_VI_FUNC_IWARP, 721 FW_VI_FUNC_OPENISCSI, 722 FW_VI_FUNC_OPENFCOE, 723 FW_VI_FUNC_FOISCSI, 724 FW_VI_FUNC_FOFCOE, 725 }; 726 727 struct intrs_and_queues { 728 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 729 uint16_t num_vis; /* number of VIs for each port */ 730 uint16_t nirq; /* Total # of vectors */ 731 uint16_t ntxq; /* # of NIC txq's for each port */ 732 uint16_t nrxq; /* # of NIC rxq's for each port */ 733 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 734 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 735 uint16_t nnmtxq; /* # of netmap txq's */ 736 uint16_t nnmrxq; /* # of netmap rxq's */ 737 738 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 739 uint16_t ntxq_vi; /* # of NIC txq's */ 740 uint16_t nrxq_vi; /* # of NIC rxq's */ 741 uint16_t nofldtxq_vi; /* # of TOE txq's */ 742 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 743 uint16_t nnmtxq_vi; /* # of netmap txq's */ 744 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 745 }; 746 747 static void setup_memwin(struct adapter *); 748 static void position_memwin(struct adapter *, int, uint32_t); 749 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 750 static int fwmtype_to_hwmtype(int); 751 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 752 uint32_t *); 753 static int fixup_devlog_params(struct adapter *); 754 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 755 static int contact_firmware(struct adapter *); 756 static int partition_resources(struct adapter *); 757 static int get_params__pre_init(struct adapter *); 758 static int set_params__pre_init(struct adapter *); 759 static int get_params__post_init(struct adapter *); 760 static int set_params__post_init(struct adapter *); 761 static void t4_set_desc(struct adapter *); 762 static bool fixed_ifmedia(struct port_info *); 763 static void build_medialist(struct port_info *); 764 static void init_link_config(struct port_info *); 765 static int fixup_link_config(struct port_info *); 766 static int apply_link_config(struct port_info *); 767 static int cxgbe_init_synchronized(struct vi_info *); 768 static int cxgbe_uninit_synchronized(struct vi_info *); 769 static int adapter_full_init(struct adapter *); 770 static void adapter_full_uninit(struct adapter *); 771 static int vi_full_init(struct vi_info *); 772 static void vi_full_uninit(struct vi_info *); 773 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *); 774 static void quiesce_txq(struct sge_txq *); 775 static void quiesce_wrq(struct sge_wrq *); 776 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 777 static void quiesce_vi(struct vi_info *); 778 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 779 driver_intr_t *, void *, char *); 780 static int t4_free_irq(struct adapter *, struct irq *); 781 static void t4_init_atid_table(struct adapter *); 782 static void t4_free_atid_table(struct adapter *); 783 static void stop_atid_allocator(struct adapter *); 784 static void restart_atid_allocator(struct adapter *); 785 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 786 static void vi_refresh_stats(struct vi_info *); 787 static void cxgbe_refresh_stats(struct vi_info *); 788 static void cxgbe_tick(void *); 789 static void vi_tick(void *); 790 static void cxgbe_sysctls(struct port_info *); 791 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 792 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 793 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 794 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 795 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 796 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS); 797 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 798 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 799 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 800 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 801 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 802 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS); 803 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS); 804 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS); 805 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 806 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS); 807 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 808 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 809 static int sysctl_vdd(SYSCTL_HANDLER_ARGS); 810 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS); 811 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 812 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 813 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 814 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 815 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 816 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 817 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 818 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 819 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 820 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS); 821 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 822 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 823 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 824 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 825 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 826 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 827 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 828 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 829 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 830 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 831 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 832 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 833 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 834 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 835 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS); 836 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 837 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 838 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 839 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 840 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 841 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 842 static int sysctl_reset(SYSCTL_HANDLER_ARGS); 843 #ifdef TCP_OFFLOAD 844 static int sysctl_tls(SYSCTL_HANDLER_ARGS); 845 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 846 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 847 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 848 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 849 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 850 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 851 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 852 #endif 853 static int get_sge_context(struct adapter *, struct t4_sge_context *); 854 static int load_fw(struct adapter *, struct t4_data *); 855 static int load_cfg(struct adapter *, struct t4_data *); 856 static int load_boot(struct adapter *, struct t4_bootrom *); 857 static int load_bootcfg(struct adapter *, struct t4_data *); 858 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 859 static void free_offload_policy(struct t4_offload_policy *); 860 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 861 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 862 static int read_i2c(struct adapter *, struct t4_i2c_data *); 863 static int clear_stats(struct adapter *, u_int); 864 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *); 865 static int release_clip_addr(struct adapter *, struct t4_clip_addr *); 866 static inline int stop_adapter(struct adapter *); 867 static inline void set_adapter_hwstatus(struct adapter *, const bool); 868 static int stop_lld(struct adapter *); 869 static inline int restart_adapter(struct adapter *); 870 static int restart_lld(struct adapter *); 871 #ifdef TCP_OFFLOAD 872 static int toe_capability(struct vi_info *, bool); 873 static int deactivate_all_uld(struct adapter *); 874 static void stop_all_uld(struct adapter *); 875 static void restart_all_uld(struct adapter *); 876 #endif 877 #ifdef KERN_TLS 878 static int ktls_capability(struct adapter *, bool); 879 #endif 880 static int mod_event(module_t, int, void *); 881 static int notify_siblings(device_t, int); 882 static uint64_t vi_get_counter(if_t, ift_counter); 883 static uint64_t cxgbe_get_counter(if_t, ift_counter); 884 static void enable_vxlan_rx(struct adapter *); 885 static void reset_adapter_task(void *, int); 886 static void fatal_error_task(void *, int); 887 static void dump_devlog(struct adapter *); 888 static void dump_cim_regs(struct adapter *); 889 static void dump_cimla(struct adapter *); 890 891 struct { 892 uint16_t device; 893 char *desc; 894 } t4_pciids[] = { 895 {0xa000, "Chelsio Terminator 4 FPGA"}, 896 {0x4400, "Chelsio T440-dbg"}, 897 {0x4401, "Chelsio T420-CR"}, 898 {0x4402, "Chelsio T422-CR"}, 899 {0x4403, "Chelsio T440-CR"}, 900 {0x4404, "Chelsio T420-BCH"}, 901 {0x4405, "Chelsio T440-BCH"}, 902 {0x4406, "Chelsio T440-CH"}, 903 {0x4407, "Chelsio T420-SO"}, 904 {0x4408, "Chelsio T420-CX"}, 905 {0x4409, "Chelsio T420-BT"}, 906 {0x440a, "Chelsio T404-BT"}, 907 {0x440e, "Chelsio T440-LP-CR"}, 908 }, t5_pciids[] = { 909 {0xb000, "Chelsio Terminator 5 FPGA"}, 910 {0x5400, "Chelsio T580-dbg"}, 911 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 912 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 913 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 914 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 915 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 916 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 917 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 918 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 919 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 920 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 921 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 922 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 923 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 924 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 925 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 926 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 927 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 928 929 /* Custom */ 930 {0x5483, "Custom T540-CR"}, 931 {0x5484, "Custom T540-BT"}, 932 }, t6_pciids[] = { 933 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 934 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 935 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 936 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 937 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 938 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 939 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 940 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 941 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 942 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 943 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 944 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 945 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 946 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 947 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 948 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 949 950 /* Custom */ 951 {0x6480, "Custom T6225-CR"}, 952 {0x6481, "Custom T62100-CR"}, 953 {0x6482, "Custom T6225-CR"}, 954 {0x6483, "Custom T62100-CR"}, 955 {0x6484, "Custom T64100-CR"}, 956 {0x6485, "Custom T6240-SO"}, 957 {0x6486, "Custom T6225-SO-CR"}, 958 {0x6487, "Custom T6225-CR"}, 959 }; 960 961 #ifdef TCP_OFFLOAD 962 /* 963 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 964 * be exactly the same for both rxq and ofld_rxq. 965 */ 966 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 967 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 968 #endif 969 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 970 971 static int 972 t4_probe(device_t dev) 973 { 974 int i; 975 uint16_t v = pci_get_vendor(dev); 976 uint16_t d = pci_get_device(dev); 977 uint8_t f = pci_get_function(dev); 978 979 if (v != PCI_VENDOR_ID_CHELSIO) 980 return (ENXIO); 981 982 /* Attach only to PF0 of the FPGA */ 983 if (d == 0xa000 && f != 0) 984 return (ENXIO); 985 986 for (i = 0; i < nitems(t4_pciids); i++) { 987 if (d == t4_pciids[i].device) { 988 device_set_desc(dev, t4_pciids[i].desc); 989 return (BUS_PROBE_DEFAULT); 990 } 991 } 992 993 return (ENXIO); 994 } 995 996 static int 997 t5_probe(device_t dev) 998 { 999 int i; 1000 uint16_t v = pci_get_vendor(dev); 1001 uint16_t d = pci_get_device(dev); 1002 uint8_t f = pci_get_function(dev); 1003 1004 if (v != PCI_VENDOR_ID_CHELSIO) 1005 return (ENXIO); 1006 1007 /* Attach only to PF0 of the FPGA */ 1008 if (d == 0xb000 && f != 0) 1009 return (ENXIO); 1010 1011 for (i = 0; i < nitems(t5_pciids); i++) { 1012 if (d == t5_pciids[i].device) { 1013 device_set_desc(dev, t5_pciids[i].desc); 1014 return (BUS_PROBE_DEFAULT); 1015 } 1016 } 1017 1018 return (ENXIO); 1019 } 1020 1021 static int 1022 t6_probe(device_t dev) 1023 { 1024 int i; 1025 uint16_t v = pci_get_vendor(dev); 1026 uint16_t d = pci_get_device(dev); 1027 1028 if (v != PCI_VENDOR_ID_CHELSIO) 1029 return (ENXIO); 1030 1031 for (i = 0; i < nitems(t6_pciids); i++) { 1032 if (d == t6_pciids[i].device) { 1033 device_set_desc(dev, t6_pciids[i].desc); 1034 return (BUS_PROBE_DEFAULT); 1035 } 1036 } 1037 1038 return (ENXIO); 1039 } 1040 1041 static void 1042 t5_attribute_workaround(device_t dev) 1043 { 1044 device_t root_port; 1045 uint32_t v; 1046 1047 /* 1048 * The T5 chips do not properly echo the No Snoop and Relaxed 1049 * Ordering attributes when replying to a TLP from a Root 1050 * Port. As a workaround, find the parent Root Port and 1051 * disable No Snoop and Relaxed Ordering. Note that this 1052 * affects all devices under this root port. 1053 */ 1054 root_port = pci_find_pcie_root_port(dev); 1055 if (root_port == NULL) { 1056 device_printf(dev, "Unable to find parent root port\n"); 1057 return; 1058 } 1059 1060 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 1061 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 1062 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 1063 0) 1064 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 1065 device_get_nameunit(root_port)); 1066 } 1067 1068 static const struct devnames devnames[] = { 1069 { 1070 .nexus_name = "t4nex", 1071 .ifnet_name = "cxgbe", 1072 .vi_ifnet_name = "vcxgbe", 1073 .pf03_drv_name = "t4iov", 1074 .vf_nexus_name = "t4vf", 1075 .vf_ifnet_name = "cxgbev" 1076 }, { 1077 .nexus_name = "t5nex", 1078 .ifnet_name = "cxl", 1079 .vi_ifnet_name = "vcxl", 1080 .pf03_drv_name = "t5iov", 1081 .vf_nexus_name = "t5vf", 1082 .vf_ifnet_name = "cxlv" 1083 }, { 1084 .nexus_name = "t6nex", 1085 .ifnet_name = "cc", 1086 .vi_ifnet_name = "vcc", 1087 .pf03_drv_name = "t6iov", 1088 .vf_nexus_name = "t6vf", 1089 .vf_ifnet_name = "ccv" 1090 } 1091 }; 1092 1093 void 1094 t4_init_devnames(struct adapter *sc) 1095 { 1096 int id; 1097 1098 id = chip_id(sc); 1099 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 1100 sc->names = &devnames[id - CHELSIO_T4]; 1101 else { 1102 device_printf(sc->dev, "chip id %d is not supported.\n", id); 1103 sc->names = NULL; 1104 } 1105 } 1106 1107 static int 1108 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 1109 { 1110 const char *parent, *name; 1111 long value; 1112 int line, unit; 1113 1114 line = 0; 1115 parent = device_get_nameunit(sc->dev); 1116 name = sc->names->ifnet_name; 1117 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 1118 if (resource_long_value(name, unit, "port", &value) == 0 && 1119 value == pi->port_id) 1120 return (unit); 1121 } 1122 return (-1); 1123 } 1124 1125 static void 1126 t4_calibration(void *arg) 1127 { 1128 struct adapter *sc; 1129 struct clock_sync *cur, *nex; 1130 uint64_t hw; 1131 sbintime_t sbt; 1132 int next_up; 1133 1134 sc = (struct adapter *)arg; 1135 1136 KASSERT((hw_off_limits(sc) == 0), ("hw_off_limits at t4_calibration")); 1137 hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO); 1138 sbt = sbinuptime(); 1139 1140 cur = &sc->cal_info[sc->cal_current]; 1141 next_up = (sc->cal_current + 1) % CNT_CAL_INFO; 1142 nex = &sc->cal_info[next_up]; 1143 if (__predict_false(sc->cal_count == 0)) { 1144 /* First time in, just get the values in */ 1145 cur->hw_cur = hw; 1146 cur->sbt_cur = sbt; 1147 sc->cal_count++; 1148 goto done; 1149 } 1150 1151 if (cur->hw_cur == hw) { 1152 /* The clock is not advancing? */ 1153 sc->cal_count = 0; 1154 atomic_store_rel_int(&cur->gen, 0); 1155 goto done; 1156 } 1157 1158 seqc_write_begin(&nex->gen); 1159 nex->hw_prev = cur->hw_cur; 1160 nex->sbt_prev = cur->sbt_cur; 1161 nex->hw_cur = hw; 1162 nex->sbt_cur = sbt; 1163 seqc_write_end(&nex->gen); 1164 sc->cal_current = next_up; 1165 done: 1166 callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration, 1167 sc, C_DIRECT_EXEC); 1168 } 1169 1170 static void 1171 t4_calibration_start(struct adapter *sc) 1172 { 1173 /* 1174 * Here if we have not done a calibration 1175 * then do so otherwise start the appropriate 1176 * timer. 1177 */ 1178 int i; 1179 1180 for (i = 0; i < CNT_CAL_INFO; i++) { 1181 sc->cal_info[i].gen = 0; 1182 } 1183 sc->cal_current = 0; 1184 sc->cal_count = 0; 1185 sc->cal_gen = 0; 1186 t4_calibration(sc); 1187 } 1188 1189 static int 1190 t4_attach(device_t dev) 1191 { 1192 struct adapter *sc; 1193 int rc = 0, i, j, rqidx, tqidx, nports; 1194 struct make_dev_args mda; 1195 struct intrs_and_queues iaq; 1196 struct sge *s; 1197 uint32_t *buf; 1198 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1199 int ofld_tqidx; 1200 #endif 1201 #ifdef TCP_OFFLOAD 1202 int ofld_rqidx; 1203 #endif 1204 #ifdef DEV_NETMAP 1205 int nm_rqidx, nm_tqidx; 1206 #endif 1207 int num_vis; 1208 1209 sc = device_get_softc(dev); 1210 sc->dev = dev; 1211 sysctl_ctx_init(&sc->ctx); 1212 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 1213 1214 if ((pci_get_device(dev) & 0xff00) == 0x5400) 1215 t5_attribute_workaround(dev); 1216 pci_enable_busmaster(dev); 1217 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 1218 uint32_t v; 1219 1220 pci_set_max_read_req(dev, 4096); 1221 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 1222 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 1223 if (pcie_relaxed_ordering == 0 && 1224 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 1225 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 1226 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1227 } else if (pcie_relaxed_ordering == 1 && 1228 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 1229 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 1230 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1231 } 1232 } 1233 1234 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 1235 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 1236 sc->traceq = -1; 1237 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 1238 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 1239 device_get_nameunit(dev)); 1240 1241 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 1242 device_get_nameunit(dev)); 1243 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 1244 t4_add_adapter(sc); 1245 1246 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 1247 TAILQ_INIT(&sc->sfl); 1248 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 1249 1250 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 1251 1252 sc->policy = NULL; 1253 rw_init(&sc->policy_lock, "connection offload policy"); 1254 1255 callout_init(&sc->ktls_tick, 1); 1256 1257 callout_init(&sc->cal_callout, 1); 1258 1259 refcount_init(&sc->vxlan_refcount, 0); 1260 1261 TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc); 1262 TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc); 1263 1264 sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1265 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq", 1266 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 1267 sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1268 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq", 1269 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 1270 1271 rc = t4_map_bars_0_and_4(sc); 1272 if (rc != 0) 1273 goto done; /* error message displayed already */ 1274 1275 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1276 1277 /* Prepare the adapter for operation. */ 1278 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1279 rc = -t4_prep_adapter(sc, buf); 1280 free(buf, M_CXGBE); 1281 if (rc != 0) { 1282 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1283 goto done; 1284 } 1285 1286 /* 1287 * This is the real PF# to which we're attaching. Works from within PCI 1288 * passthrough environments too, where pci_get_function() could return a 1289 * different PF# depending on the passthrough configuration. We need to 1290 * use the real PF# in all our communication with the firmware. 1291 */ 1292 j = t4_read_reg(sc, A_PL_WHOAMI); 1293 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1294 sc->mbox = sc->pf; 1295 1296 t4_init_devnames(sc); 1297 if (sc->names == NULL) { 1298 rc = ENOTSUP; 1299 goto done; /* error message displayed already */ 1300 } 1301 1302 /* 1303 * Do this really early, with the memory windows set up even before the 1304 * character device. The userland tool's register i/o and mem read 1305 * will work even in "recovery mode". 1306 */ 1307 setup_memwin(sc); 1308 if (t4_init_devlog_params(sc, 0) == 0) 1309 fixup_devlog_params(sc); 1310 make_dev_args_init(&mda); 1311 mda.mda_devsw = &t4_cdevsw; 1312 mda.mda_uid = UID_ROOT; 1313 mda.mda_gid = GID_WHEEL; 1314 mda.mda_mode = 0600; 1315 mda.mda_si_drv1 = sc; 1316 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1317 if (rc != 0) 1318 device_printf(dev, "failed to create nexus char device: %d.\n", 1319 rc); 1320 1321 /* Go no further if recovery mode has been requested. */ 1322 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1323 device_printf(dev, "recovery mode.\n"); 1324 goto done; 1325 } 1326 1327 #if defined(__i386__) 1328 if ((cpu_feature & CPUID_CX8) == 0) { 1329 device_printf(dev, "64 bit atomics not available.\n"); 1330 rc = ENOTSUP; 1331 goto done; 1332 } 1333 #endif 1334 1335 /* Contact the firmware and try to become the master driver. */ 1336 rc = contact_firmware(sc); 1337 if (rc != 0) 1338 goto done; /* error message displayed already */ 1339 MPASS(sc->flags & FW_OK); 1340 1341 rc = get_params__pre_init(sc); 1342 if (rc != 0) 1343 goto done; /* error message displayed already */ 1344 1345 if (sc->flags & MASTER_PF) { 1346 rc = partition_resources(sc); 1347 if (rc != 0) 1348 goto done; /* error message displayed already */ 1349 } 1350 1351 rc = get_params__post_init(sc); 1352 if (rc != 0) 1353 goto done; /* error message displayed already */ 1354 1355 rc = set_params__post_init(sc); 1356 if (rc != 0) 1357 goto done; /* error message displayed already */ 1358 1359 rc = t4_map_bar_2(sc); 1360 if (rc != 0) 1361 goto done; /* error message displayed already */ 1362 1363 rc = t4_adj_doorbells(sc); 1364 if (rc != 0) 1365 goto done; /* error message displayed already */ 1366 1367 rc = t4_create_dma_tag(sc); 1368 if (rc != 0) 1369 goto done; /* error message displayed already */ 1370 1371 /* 1372 * First pass over all the ports - allocate VIs and initialize some 1373 * basic parameters like mac address, port type, etc. 1374 */ 1375 for_each_port(sc, i) { 1376 struct port_info *pi; 1377 1378 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1379 sc->port[i] = pi; 1380 1381 /* These must be set before t4_port_init */ 1382 pi->adapter = sc; 1383 pi->port_id = i; 1384 /* 1385 * XXX: vi[0] is special so we can't delay this allocation until 1386 * pi->nvi's final value is known. 1387 */ 1388 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1389 M_ZERO | M_WAITOK); 1390 1391 /* 1392 * Allocate the "main" VI and initialize parameters 1393 * like mac addr. 1394 */ 1395 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1396 if (rc != 0) { 1397 device_printf(dev, "unable to initialize port %d: %d\n", 1398 i, rc); 1399 free(pi->vi, M_CXGBE); 1400 free(pi, M_CXGBE); 1401 sc->port[i] = NULL; 1402 goto done; 1403 } 1404 1405 if (is_bt(pi->port_type)) 1406 setbit(&sc->bt_map, pi->tx_chan); 1407 else 1408 MPASS(!isset(&sc->bt_map, pi->tx_chan)); 1409 1410 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1411 device_get_nameunit(dev), i); 1412 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1413 sc->chan_map[pi->tx_chan] = i; 1414 1415 /* 1416 * The MPS counter for FCS errors doesn't work correctly on the 1417 * T6 so we use the MAC counter here. Which MAC is in use 1418 * depends on the link settings which will be known when the 1419 * link comes up. 1420 */ 1421 if (is_t6(sc)) 1422 pi->fcs_reg = -1; 1423 else { 1424 pi->fcs_reg = t4_port_reg(sc, pi->tx_chan, 1425 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1426 } 1427 pi->fcs_base = 0; 1428 1429 /* All VIs on this port share this media. */ 1430 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1431 cxgbe_media_status); 1432 1433 PORT_LOCK(pi); 1434 init_link_config(pi); 1435 fixup_link_config(pi); 1436 build_medialist(pi); 1437 if (fixed_ifmedia(pi)) 1438 pi->flags |= FIXED_IFMEDIA; 1439 PORT_UNLOCK(pi); 1440 1441 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1442 t4_ifnet_unit(sc, pi)); 1443 if (pi->dev == NULL) { 1444 device_printf(dev, 1445 "failed to add device for port %d.\n", i); 1446 rc = ENXIO; 1447 goto done; 1448 } 1449 pi->vi[0].dev = pi->dev; 1450 device_set_softc(pi->dev, pi); 1451 } 1452 1453 /* 1454 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1455 */ 1456 nports = sc->params.nports; 1457 rc = cfg_itype_and_nqueues(sc, &iaq); 1458 if (rc != 0) 1459 goto done; /* error message displayed already */ 1460 1461 num_vis = iaq.num_vis; 1462 sc->intr_type = iaq.intr_type; 1463 sc->intr_count = iaq.nirq; 1464 1465 s = &sc->sge; 1466 s->nrxq = nports * iaq.nrxq; 1467 s->ntxq = nports * iaq.ntxq; 1468 if (num_vis > 1) { 1469 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1470 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1471 } 1472 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1473 s->neq += nports; /* ctrl queues: 1 per port */ 1474 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1475 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1476 if (is_offload(sc) || is_ethoffload(sc)) { 1477 s->nofldtxq = nports * iaq.nofldtxq; 1478 if (num_vis > 1) 1479 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1480 s->neq += s->nofldtxq; 1481 1482 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq), 1483 M_CXGBE, M_ZERO | M_WAITOK); 1484 } 1485 #endif 1486 #ifdef TCP_OFFLOAD 1487 if (is_offload(sc)) { 1488 s->nofldrxq = nports * iaq.nofldrxq; 1489 if (num_vis > 1) 1490 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1491 s->neq += s->nofldrxq; /* free list */ 1492 s->niq += s->nofldrxq; 1493 1494 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1495 M_CXGBE, M_ZERO | M_WAITOK); 1496 } 1497 #endif 1498 #ifdef DEV_NETMAP 1499 s->nnmrxq = 0; 1500 s->nnmtxq = 0; 1501 if (t4_native_netmap & NN_MAIN_VI) { 1502 s->nnmrxq += nports * iaq.nnmrxq; 1503 s->nnmtxq += nports * iaq.nnmtxq; 1504 } 1505 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) { 1506 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi; 1507 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi; 1508 } 1509 s->neq += s->nnmtxq + s->nnmrxq; 1510 s->niq += s->nnmrxq; 1511 1512 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1513 M_CXGBE, M_ZERO | M_WAITOK); 1514 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1515 M_CXGBE, M_ZERO | M_WAITOK); 1516 #endif 1517 MPASS(s->niq <= s->iqmap_sz); 1518 MPASS(s->neq <= s->eqmap_sz); 1519 1520 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1521 M_ZERO | M_WAITOK); 1522 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1523 M_ZERO | M_WAITOK); 1524 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1525 M_ZERO | M_WAITOK); 1526 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE, 1527 M_ZERO | M_WAITOK); 1528 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE, 1529 M_ZERO | M_WAITOK); 1530 1531 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1532 M_ZERO | M_WAITOK); 1533 1534 t4_init_l2t(sc, M_WAITOK); 1535 t4_init_smt(sc, M_WAITOK); 1536 t4_init_tx_sched(sc); 1537 t4_init_atid_table(sc); 1538 #ifdef RATELIMIT 1539 t4_init_etid_table(sc); 1540 #endif 1541 #ifdef INET6 1542 t4_init_clip_table(sc); 1543 #endif 1544 if (sc->vres.key.size != 0) 1545 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1546 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1547 1548 /* 1549 * Second pass over the ports. This time we know the number of rx and 1550 * tx queues that each port should get. 1551 */ 1552 rqidx = tqidx = 0; 1553 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1554 ofld_tqidx = 0; 1555 #endif 1556 #ifdef TCP_OFFLOAD 1557 ofld_rqidx = 0; 1558 #endif 1559 #ifdef DEV_NETMAP 1560 nm_rqidx = nm_tqidx = 0; 1561 #endif 1562 for_each_port(sc, i) { 1563 struct port_info *pi = sc->port[i]; 1564 struct vi_info *vi; 1565 1566 if (pi == NULL) 1567 continue; 1568 1569 pi->nvi = num_vis; 1570 for_each_vi(pi, j, vi) { 1571 vi->pi = pi; 1572 vi->adapter = sc; 1573 vi->first_intr = -1; 1574 vi->qsize_rxq = t4_qsize_rxq; 1575 vi->qsize_txq = t4_qsize_txq; 1576 1577 vi->first_rxq = rqidx; 1578 vi->first_txq = tqidx; 1579 vi->tmr_idx = t4_tmr_idx; 1580 vi->pktc_idx = t4_pktc_idx; 1581 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1582 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1583 1584 rqidx += vi->nrxq; 1585 tqidx += vi->ntxq; 1586 1587 if (j == 0 && vi->ntxq > 1) 1588 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1589 else 1590 vi->rsrv_noflowq = 0; 1591 1592 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1593 vi->first_ofld_txq = ofld_tqidx; 1594 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1595 ofld_tqidx += vi->nofldtxq; 1596 #endif 1597 #ifdef TCP_OFFLOAD 1598 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1599 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1600 vi->first_ofld_rxq = ofld_rqidx; 1601 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1602 1603 ofld_rqidx += vi->nofldrxq; 1604 #endif 1605 #ifdef DEV_NETMAP 1606 vi->first_nm_rxq = nm_rqidx; 1607 vi->first_nm_txq = nm_tqidx; 1608 if (j == 0) { 1609 vi->nnmrxq = iaq.nnmrxq; 1610 vi->nnmtxq = iaq.nnmtxq; 1611 } else { 1612 vi->nnmrxq = iaq.nnmrxq_vi; 1613 vi->nnmtxq = iaq.nnmtxq_vi; 1614 } 1615 nm_rqidx += vi->nnmrxq; 1616 nm_tqidx += vi->nnmtxq; 1617 #endif 1618 } 1619 } 1620 1621 rc = t4_setup_intr_handlers(sc); 1622 if (rc != 0) { 1623 device_printf(dev, 1624 "failed to setup interrupt handlers: %d\n", rc); 1625 goto done; 1626 } 1627 1628 rc = bus_generic_probe(dev); 1629 if (rc != 0) { 1630 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1631 goto done; 1632 } 1633 1634 /* 1635 * Ensure thread-safe mailbox access (in debug builds). 1636 * 1637 * So far this was the only thread accessing the mailbox but various 1638 * ifnets and sysctls are about to be created and their handlers/ioctls 1639 * will access the mailbox from different threads. 1640 */ 1641 sc->flags |= CHK_MBOX_ACCESS; 1642 1643 rc = bus_generic_attach(dev); 1644 if (rc != 0) { 1645 device_printf(dev, 1646 "failed to attach all child ports: %d\n", rc); 1647 goto done; 1648 } 1649 t4_calibration_start(sc); 1650 1651 device_printf(dev, 1652 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1653 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1654 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1655 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1656 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1657 1658 t4_set_desc(sc); 1659 1660 notify_siblings(dev, 0); 1661 1662 done: 1663 if (rc != 0 && sc->cdev) { 1664 /* cdev was created and so cxgbetool works; recover that way. */ 1665 device_printf(dev, 1666 "error during attach, adapter is now in recovery mode.\n"); 1667 rc = 0; 1668 } 1669 1670 if (rc != 0) 1671 t4_detach_common(dev); 1672 else 1673 t4_sysctls(sc); 1674 1675 return (rc); 1676 } 1677 1678 static int 1679 t4_child_location(device_t bus, device_t dev, struct sbuf *sb) 1680 { 1681 struct adapter *sc; 1682 struct port_info *pi; 1683 int i; 1684 1685 sc = device_get_softc(bus); 1686 for_each_port(sc, i) { 1687 pi = sc->port[i]; 1688 if (pi != NULL && pi->dev == dev) { 1689 sbuf_printf(sb, "port=%d", pi->port_id); 1690 break; 1691 } 1692 } 1693 return (0); 1694 } 1695 1696 static int 1697 t4_ready(device_t dev) 1698 { 1699 struct adapter *sc; 1700 1701 sc = device_get_softc(dev); 1702 if (sc->flags & FW_OK) 1703 return (0); 1704 return (ENXIO); 1705 } 1706 1707 static int 1708 t4_read_port_device(device_t dev, int port, device_t *child) 1709 { 1710 struct adapter *sc; 1711 struct port_info *pi; 1712 1713 sc = device_get_softc(dev); 1714 if (port < 0 || port >= MAX_NPORTS) 1715 return (EINVAL); 1716 pi = sc->port[port]; 1717 if (pi == NULL || pi->dev == NULL) 1718 return (ENXIO); 1719 *child = pi->dev; 1720 return (0); 1721 } 1722 1723 static int 1724 notify_siblings(device_t dev, int detaching) 1725 { 1726 device_t sibling; 1727 int error, i; 1728 1729 error = 0; 1730 for (i = 0; i < PCI_FUNCMAX; i++) { 1731 if (i == pci_get_function(dev)) 1732 continue; 1733 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1734 pci_get_slot(dev), i); 1735 if (sibling == NULL || !device_is_attached(sibling)) 1736 continue; 1737 if (detaching) 1738 error = T4_DETACH_CHILD(sibling); 1739 else 1740 (void)T4_ATTACH_CHILD(sibling); 1741 if (error) 1742 break; 1743 } 1744 return (error); 1745 } 1746 1747 /* 1748 * Idempotent 1749 */ 1750 static int 1751 t4_detach(device_t dev) 1752 { 1753 int rc; 1754 1755 rc = notify_siblings(dev, 1); 1756 if (rc) { 1757 device_printf(dev, 1758 "failed to detach sibling devices: %d\n", rc); 1759 return (rc); 1760 } 1761 1762 return (t4_detach_common(dev)); 1763 } 1764 1765 int 1766 t4_detach_common(device_t dev) 1767 { 1768 struct adapter *sc; 1769 struct port_info *pi; 1770 int i, rc; 1771 1772 sc = device_get_softc(dev); 1773 1774 #ifdef TCP_OFFLOAD 1775 rc = deactivate_all_uld(sc); 1776 if (rc) { 1777 device_printf(dev, 1778 "failed to detach upper layer drivers: %d\n", rc); 1779 return (rc); 1780 } 1781 #endif 1782 1783 if (sc->cdev) { 1784 destroy_dev(sc->cdev); 1785 sc->cdev = NULL; 1786 } 1787 1788 sx_xlock(&t4_list_lock); 1789 SLIST_REMOVE(&t4_list, sc, adapter, link); 1790 sx_xunlock(&t4_list_lock); 1791 1792 sc->flags &= ~CHK_MBOX_ACCESS; 1793 if (sc->flags & FULL_INIT_DONE) { 1794 if (!(sc->flags & IS_VF)) 1795 t4_intr_disable(sc); 1796 } 1797 1798 if (device_is_attached(dev)) { 1799 rc = bus_generic_detach(dev); 1800 if (rc) { 1801 device_printf(dev, 1802 "failed to detach child devices: %d\n", rc); 1803 return (rc); 1804 } 1805 } 1806 1807 for (i = 0; i < sc->intr_count; i++) 1808 t4_free_irq(sc, &sc->irq[i]); 1809 1810 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1811 t4_free_tx_sched(sc); 1812 1813 for (i = 0; i < MAX_NPORTS; i++) { 1814 pi = sc->port[i]; 1815 if (pi) { 1816 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1817 if (pi->dev) 1818 device_delete_child(dev, pi->dev); 1819 1820 mtx_destroy(&pi->pi_lock); 1821 free(pi->vi, M_CXGBE); 1822 free(pi, M_CXGBE); 1823 } 1824 } 1825 callout_stop(&sc->cal_callout); 1826 callout_drain(&sc->cal_callout); 1827 device_delete_children(dev); 1828 sysctl_ctx_free(&sc->ctx); 1829 adapter_full_uninit(sc); 1830 1831 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1832 t4_fw_bye(sc, sc->mbox); 1833 1834 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1835 pci_release_msi(dev); 1836 1837 if (sc->regs_res) 1838 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1839 sc->regs_res); 1840 1841 if (sc->udbs_res) 1842 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1843 sc->udbs_res); 1844 1845 if (sc->msix_res) 1846 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1847 sc->msix_res); 1848 1849 if (sc->l2t) 1850 t4_free_l2t(sc); 1851 if (sc->smt) 1852 t4_free_smt(sc->smt); 1853 t4_free_atid_table(sc); 1854 #ifdef RATELIMIT 1855 t4_free_etid_table(sc); 1856 #endif 1857 if (sc->key_map) 1858 vmem_destroy(sc->key_map); 1859 #ifdef INET6 1860 t4_destroy_clip_table(sc); 1861 #endif 1862 1863 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1864 free(sc->sge.ofld_txq, M_CXGBE); 1865 #endif 1866 #ifdef TCP_OFFLOAD 1867 free(sc->sge.ofld_rxq, M_CXGBE); 1868 #endif 1869 #ifdef DEV_NETMAP 1870 free(sc->sge.nm_rxq, M_CXGBE); 1871 free(sc->sge.nm_txq, M_CXGBE); 1872 #endif 1873 free(sc->irq, M_CXGBE); 1874 free(sc->sge.rxq, M_CXGBE); 1875 free(sc->sge.txq, M_CXGBE); 1876 free(sc->sge.ctrlq, M_CXGBE); 1877 free(sc->sge.iqmap, M_CXGBE); 1878 free(sc->sge.eqmap, M_CXGBE); 1879 free(sc->tids.ftid_tab, M_CXGBE); 1880 free(sc->tids.hpftid_tab, M_CXGBE); 1881 free_hftid_hash(&sc->tids); 1882 free(sc->tids.tid_tab, M_CXGBE); 1883 t4_destroy_dma_tag(sc); 1884 1885 callout_drain(&sc->ktls_tick); 1886 callout_drain(&sc->sfl_callout); 1887 if (mtx_initialized(&sc->tids.ftid_lock)) { 1888 mtx_destroy(&sc->tids.ftid_lock); 1889 cv_destroy(&sc->tids.ftid_cv); 1890 } 1891 if (mtx_initialized(&sc->tids.atid_lock)) 1892 mtx_destroy(&sc->tids.atid_lock); 1893 if (mtx_initialized(&sc->ifp_lock)) 1894 mtx_destroy(&sc->ifp_lock); 1895 1896 if (rw_initialized(&sc->policy_lock)) { 1897 rw_destroy(&sc->policy_lock); 1898 #ifdef TCP_OFFLOAD 1899 if (sc->policy != NULL) 1900 free_offload_policy(sc->policy); 1901 #endif 1902 } 1903 1904 for (i = 0; i < NUM_MEMWIN; i++) { 1905 struct memwin *mw = &sc->memwin[i]; 1906 1907 if (rw_initialized(&mw->mw_lock)) 1908 rw_destroy(&mw->mw_lock); 1909 } 1910 1911 mtx_destroy(&sc->sfl_lock); 1912 mtx_destroy(&sc->reg_lock); 1913 mtx_destroy(&sc->sc_lock); 1914 1915 bzero(sc, sizeof(*sc)); 1916 1917 return (0); 1918 } 1919 1920 static inline int 1921 stop_adapter(struct adapter *sc) 1922 { 1923 struct port_info *pi; 1924 int i; 1925 1926 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) { 1927 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n", 1928 __func__, curthread, sc->flags, sc->error_flags); 1929 return (EALREADY); 1930 } 1931 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread, 1932 sc->flags, sc->error_flags); 1933 t4_shutdown_adapter(sc); 1934 for_each_port(sc, i) { 1935 pi = sc->port[i]; 1936 PORT_LOCK(pi); 1937 if (pi->up_vis > 0 && pi->link_cfg.link_ok) { 1938 /* 1939 * t4_shutdown_adapter has already shut down all the 1940 * PHYs but it also disables interrupts and DMA so there 1941 * won't be a link interrupt. Update the state manually 1942 * if the link was up previously and inform the kernel. 1943 */ 1944 pi->link_cfg.link_ok = false; 1945 t4_os_link_changed(pi); 1946 } 1947 PORT_UNLOCK(pi); 1948 } 1949 1950 return (0); 1951 } 1952 1953 static inline int 1954 restart_adapter(struct adapter *sc) 1955 { 1956 uint32_t val; 1957 1958 if (!atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_STOPPED))) { 1959 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n", 1960 __func__, curthread, sc->flags, sc->error_flags); 1961 return (EALREADY); 1962 } 1963 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread, 1964 sc->flags, sc->error_flags); 1965 1966 MPASS(hw_off_limits(sc)); 1967 MPASS((sc->flags & FW_OK) == 0); 1968 MPASS((sc->flags & MASTER_PF) == 0); 1969 MPASS(sc->reset_thread == NULL); 1970 1971 /* 1972 * The adapter is supposed to be back on PCIE with its config space and 1973 * BARs restored to their state before reset. Register access via 1974 * t4_read_reg BAR0 should just work. 1975 */ 1976 sc->reset_thread = curthread; 1977 val = t4_read_reg(sc, A_PL_WHOAMI); 1978 if (val == 0xffffffff || val == 0xeeeeeeee) { 1979 CH_ERR(sc, "%s: device registers not readable.\n", __func__); 1980 sc->reset_thread = NULL; 1981 atomic_set_int(&sc->error_flags, ADAP_STOPPED); 1982 return (ENXIO); 1983 } 1984 atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR); 1985 atomic_add_int(&sc->incarnation, 1); 1986 atomic_add_int(&sc->num_resets, 1); 1987 1988 return (0); 1989 } 1990 1991 static inline void 1992 set_adapter_hwstatus(struct adapter *sc, const bool usable) 1993 { 1994 mtx_lock(&sc->reg_lock); 1995 if (usable) { 1996 /* Must be marked reusable by the designated thread. */ 1997 MPASS(sc->reset_thread == curthread); 1998 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 1999 } else { 2000 /* Mark the adapter totally off limits. */ 2001 atomic_set_int(&sc->error_flags, HW_OFF_LIMITS); 2002 sc->flags &= ~(FW_OK | MASTER_PF); 2003 sc->reset_thread = NULL; 2004 } 2005 mtx_unlock(&sc->reg_lock); 2006 } 2007 2008 static int 2009 stop_lld(struct adapter *sc) 2010 { 2011 struct port_info *pi; 2012 struct vi_info *vi; 2013 if_t ifp; 2014 struct sge_rxq *rxq; 2015 struct sge_txq *txq; 2016 struct sge_wrq *wrq; 2017 #ifdef TCP_OFFLOAD 2018 struct sge_ofld_rxq *ofld_rxq; 2019 #endif 2020 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2021 struct sge_ofld_txq *ofld_txq; 2022 #endif 2023 int rc, i, j, k; 2024 2025 /* 2026 * XXX: Can there be a synch_op in progress that will hang because 2027 * hardware has been stopped? We'll hang too and the solution will be 2028 * to use a version of begin_synch_op that wakes up existing synch_op 2029 * with errors. Maybe stop_adapter should do this wakeup? 2030 * 2031 * I don't think any synch_op could get stranded waiting for DMA or 2032 * interrupt so I think we're okay here. Remove this comment block 2033 * after testing. 2034 */ 2035 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4slld"); 2036 if (rc != 0) 2037 return (ENXIO); 2038 2039 /* Quiesce all activity. */ 2040 for_each_port(sc, i) { 2041 pi = sc->port[i]; 2042 pi->vxlan_tcam_entry = false; 2043 for_each_vi(pi, j, vi) { 2044 vi->xact_addr_filt = -1; 2045 mtx_lock(&vi->tick_mtx); 2046 vi->flags |= VI_SKIP_STATS; 2047 mtx_unlock(&vi->tick_mtx); 2048 if (!(vi->flags & VI_INIT_DONE)) 2049 continue; 2050 2051 ifp = vi->ifp; 2052 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2053 mtx_lock(&vi->tick_mtx); 2054 callout_stop(&vi->tick); 2055 mtx_unlock(&vi->tick_mtx); 2056 callout_drain(&vi->tick); 2057 } 2058 2059 /* 2060 * Note that the HW is not available. 2061 */ 2062 for_each_txq(vi, k, txq) { 2063 TXQ_LOCK(txq); 2064 txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED); 2065 TXQ_UNLOCK(txq); 2066 } 2067 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2068 for_each_ofld_txq(vi, k, ofld_txq) { 2069 TXQ_LOCK(&ofld_txq->wrq); 2070 ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED; 2071 TXQ_UNLOCK(&ofld_txq->wrq); 2072 } 2073 #endif 2074 for_each_rxq(vi, k, rxq) { 2075 rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2076 } 2077 #if defined(TCP_OFFLOAD) 2078 for_each_ofld_rxq(vi, k, ofld_rxq) { 2079 ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2080 } 2081 #endif 2082 2083 quiesce_vi(vi); 2084 } 2085 2086 if (sc->flags & FULL_INIT_DONE) { 2087 /* Control queue */ 2088 wrq = &sc->sge.ctrlq[i]; 2089 TXQ_LOCK(wrq); 2090 wrq->eq.flags &= ~EQ_HW_ALLOCATED; 2091 TXQ_UNLOCK(wrq); 2092 quiesce_wrq(wrq); 2093 } 2094 } 2095 if (sc->flags & FULL_INIT_DONE) { 2096 /* Firmware event queue */ 2097 sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED; 2098 quiesce_iq_fl(sc, &sc->sge.fwq, NULL); 2099 } 2100 2101 /* Stop calibration */ 2102 callout_stop(&sc->cal_callout); 2103 callout_drain(&sc->cal_callout); 2104 2105 if (t4_clock_gate_on_suspend) { 2106 t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN | 2107 F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN | 2108 F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0); 2109 } 2110 2111 end_synchronized_op(sc, 0); 2112 2113 stop_atid_allocator(sc); 2114 t4_stop_l2t(sc); 2115 2116 return (rc); 2117 } 2118 2119 int 2120 suspend_adapter(struct adapter *sc) 2121 { 2122 stop_adapter(sc); 2123 stop_lld(sc); 2124 #ifdef TCP_OFFLOAD 2125 stop_all_uld(sc); 2126 #endif 2127 set_adapter_hwstatus(sc, false); 2128 2129 return (0); 2130 } 2131 2132 static int 2133 t4_suspend(device_t dev) 2134 { 2135 struct adapter *sc = device_get_softc(dev); 2136 int rc; 2137 2138 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2139 rc = suspend_adapter(sc); 2140 CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread); 2141 2142 return (rc); 2143 } 2144 2145 struct adapter_pre_reset_state { 2146 u_int flags; 2147 uint16_t nbmcaps; 2148 uint16_t linkcaps; 2149 uint16_t switchcaps; 2150 uint16_t niccaps; 2151 uint16_t toecaps; 2152 uint16_t rdmacaps; 2153 uint16_t cryptocaps; 2154 uint16_t iscsicaps; 2155 uint16_t fcoecaps; 2156 2157 u_int cfcsum; 2158 char cfg_file[32]; 2159 2160 struct adapter_params params; 2161 struct t4_virt_res vres; 2162 struct tid_info tids; 2163 struct sge sge; 2164 2165 int rawf_base; 2166 int nrawf; 2167 2168 }; 2169 2170 static void 2171 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2172 { 2173 2174 ASSERT_SYNCHRONIZED_OP(sc); 2175 2176 o->flags = sc->flags; 2177 2178 o->nbmcaps = sc->nbmcaps; 2179 o->linkcaps = sc->linkcaps; 2180 o->switchcaps = sc->switchcaps; 2181 o->niccaps = sc->niccaps; 2182 o->toecaps = sc->toecaps; 2183 o->rdmacaps = sc->rdmacaps; 2184 o->cryptocaps = sc->cryptocaps; 2185 o->iscsicaps = sc->iscsicaps; 2186 o->fcoecaps = sc->fcoecaps; 2187 2188 o->cfcsum = sc->cfcsum; 2189 MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file)); 2190 memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file)); 2191 2192 o->params = sc->params; 2193 o->vres = sc->vres; 2194 o->tids = sc->tids; 2195 o->sge = sc->sge; 2196 2197 o->rawf_base = sc->rawf_base; 2198 o->nrawf = sc->nrawf; 2199 } 2200 2201 static int 2202 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2203 { 2204 int rc = 0; 2205 2206 ASSERT_SYNCHRONIZED_OP(sc); 2207 2208 /* Capabilities */ 2209 #define COMPARE_CAPS(c) do { \ 2210 if (o->c##caps != sc->c##caps) { \ 2211 CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \ 2212 sc->c##caps); \ 2213 rc = EINVAL; \ 2214 } \ 2215 } while (0) 2216 COMPARE_CAPS(nbm); 2217 COMPARE_CAPS(link); 2218 COMPARE_CAPS(switch); 2219 COMPARE_CAPS(nic); 2220 COMPARE_CAPS(toe); 2221 COMPARE_CAPS(rdma); 2222 COMPARE_CAPS(crypto); 2223 COMPARE_CAPS(iscsi); 2224 COMPARE_CAPS(fcoe); 2225 #undef COMPARE_CAPS 2226 2227 /* Firmware config file */ 2228 if (o->cfcsum != sc->cfcsum) { 2229 CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file, 2230 o->cfcsum, sc->cfg_file, sc->cfcsum); 2231 rc = EINVAL; 2232 } 2233 2234 #define COMPARE_PARAM(p, name) do { \ 2235 if (o->p != sc->p) { \ 2236 CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \ 2237 rc = EINVAL; \ 2238 } \ 2239 } while (0) 2240 COMPARE_PARAM(sge.iq_start, iq_start); 2241 COMPARE_PARAM(sge.eq_start, eq_start); 2242 COMPARE_PARAM(tids.ftid_base, ftid_base); 2243 COMPARE_PARAM(tids.ftid_end, ftid_end); 2244 COMPARE_PARAM(tids.nftids, nftids); 2245 COMPARE_PARAM(vres.l2t.start, l2t_start); 2246 COMPARE_PARAM(vres.l2t.size, l2t_size); 2247 COMPARE_PARAM(sge.iqmap_sz, iqmap_sz); 2248 COMPARE_PARAM(sge.eqmap_sz, eqmap_sz); 2249 COMPARE_PARAM(tids.tid_base, tid_base); 2250 COMPARE_PARAM(tids.hpftid_base, hpftid_base); 2251 COMPARE_PARAM(tids.hpftid_end, hpftid_end); 2252 COMPARE_PARAM(tids.nhpftids, nhpftids); 2253 COMPARE_PARAM(rawf_base, rawf_base); 2254 COMPARE_PARAM(nrawf, nrawf); 2255 COMPARE_PARAM(params.mps_bg_map, mps_bg_map); 2256 COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support); 2257 COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl); 2258 COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support); 2259 COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr); 2260 COMPARE_PARAM(tids.ntids, ntids); 2261 COMPARE_PARAM(tids.etid_base, etid_base); 2262 COMPARE_PARAM(tids.etid_end, etid_end); 2263 COMPARE_PARAM(tids.netids, netids); 2264 COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred); 2265 COMPARE_PARAM(params.ethoffload, ethoffload); 2266 COMPARE_PARAM(tids.natids, natids); 2267 COMPARE_PARAM(tids.stid_base, stid_base); 2268 COMPARE_PARAM(vres.ddp.start, ddp_start); 2269 COMPARE_PARAM(vres.ddp.size, ddp_size); 2270 COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred); 2271 COMPARE_PARAM(vres.stag.start, stag_start); 2272 COMPARE_PARAM(vres.stag.size, stag_size); 2273 COMPARE_PARAM(vres.rq.start, rq_start); 2274 COMPARE_PARAM(vres.rq.size, rq_size); 2275 COMPARE_PARAM(vres.pbl.start, pbl_start); 2276 COMPARE_PARAM(vres.pbl.size, pbl_size); 2277 COMPARE_PARAM(vres.qp.start, qp_start); 2278 COMPARE_PARAM(vres.qp.size, qp_size); 2279 COMPARE_PARAM(vres.cq.start, cq_start); 2280 COMPARE_PARAM(vres.cq.size, cq_size); 2281 COMPARE_PARAM(vres.ocq.start, ocq_start); 2282 COMPARE_PARAM(vres.ocq.size, ocq_size); 2283 COMPARE_PARAM(vres.srq.start, srq_start); 2284 COMPARE_PARAM(vres.srq.size, srq_size); 2285 COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp); 2286 COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter); 2287 COMPARE_PARAM(vres.iscsi.start, iscsi_start); 2288 COMPARE_PARAM(vres.iscsi.size, iscsi_size); 2289 COMPARE_PARAM(vres.key.start, key_start); 2290 COMPARE_PARAM(vres.key.size, key_size); 2291 #undef COMPARE_PARAM 2292 2293 return (rc); 2294 } 2295 2296 static int 2297 restart_lld(struct adapter *sc) 2298 { 2299 struct adapter_pre_reset_state *old_state = NULL; 2300 struct port_info *pi; 2301 struct vi_info *vi; 2302 if_t ifp; 2303 struct sge_txq *txq; 2304 int rc, i, j, k; 2305 2306 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rlld"); 2307 if (rc != 0) 2308 return (ENXIO); 2309 2310 /* Restore memory window. */ 2311 setup_memwin(sc); 2312 2313 /* Go no further if recovery mode has been requested. */ 2314 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 2315 CH_ALERT(sc, "%s: recovery mode during restart.\n", __func__); 2316 rc = 0; 2317 set_adapter_hwstatus(sc, true); 2318 goto done; 2319 } 2320 2321 old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK); 2322 save_caps_and_params(sc, old_state); 2323 2324 /* Reestablish contact with firmware and become the primary PF. */ 2325 rc = contact_firmware(sc); 2326 if (rc != 0) 2327 goto done; /* error message displayed already */ 2328 MPASS(sc->flags & FW_OK); 2329 2330 if (sc->flags & MASTER_PF) { 2331 rc = partition_resources(sc); 2332 if (rc != 0) 2333 goto done; /* error message displayed already */ 2334 } 2335 2336 rc = get_params__post_init(sc); 2337 if (rc != 0) 2338 goto done; /* error message displayed already */ 2339 2340 rc = set_params__post_init(sc); 2341 if (rc != 0) 2342 goto done; /* error message displayed already */ 2343 2344 rc = compare_caps_and_params(sc, old_state); 2345 if (rc != 0) 2346 goto done; /* error message displayed already */ 2347 2348 for_each_port(sc, i) { 2349 pi = sc->port[i]; 2350 MPASS(pi != NULL); 2351 MPASS(pi->vi != NULL); 2352 MPASS(pi->vi[0].dev == pi->dev); 2353 2354 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 2355 if (rc != 0) { 2356 CH_ERR(sc, 2357 "failed to re-initialize port %d: %d\n", i, rc); 2358 goto done; 2359 } 2360 MPASS(sc->chan_map[pi->tx_chan] == i); 2361 2362 PORT_LOCK(pi); 2363 fixup_link_config(pi); 2364 build_medialist(pi); 2365 PORT_UNLOCK(pi); 2366 for_each_vi(pi, j, vi) { 2367 if (IS_MAIN_VI(vi)) 2368 continue; 2369 rc = alloc_extra_vi(sc, pi, vi); 2370 if (rc != 0) { 2371 CH_ERR(vi, 2372 "failed to re-allocate extra VI: %d\n", rc); 2373 goto done; 2374 } 2375 } 2376 } 2377 2378 /* 2379 * Interrupts and queues are about to be enabled and other threads will 2380 * want to access the hardware too. It is safe to do so. Note that 2381 * this thread is still in the middle of a synchronized_op. 2382 */ 2383 set_adapter_hwstatus(sc, true); 2384 2385 if (sc->flags & FULL_INIT_DONE) { 2386 rc = adapter_full_init(sc); 2387 if (rc != 0) { 2388 CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc); 2389 goto done; 2390 } 2391 2392 if (sc->vxlan_refcount > 0) 2393 enable_vxlan_rx(sc); 2394 2395 for_each_port(sc, i) { 2396 pi = sc->port[i]; 2397 for_each_vi(pi, j, vi) { 2398 mtx_lock(&vi->tick_mtx); 2399 vi->flags &= ~VI_SKIP_STATS; 2400 mtx_unlock(&vi->tick_mtx); 2401 if (!(vi->flags & VI_INIT_DONE)) 2402 continue; 2403 rc = vi_full_init(vi); 2404 if (rc != 0) { 2405 CH_ERR(vi, "failed to re-initialize " 2406 "interface: %d\n", rc); 2407 goto done; 2408 } 2409 2410 ifp = vi->ifp; 2411 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2412 continue; 2413 /* 2414 * Note that we do not setup multicast addresses 2415 * in the first pass. This ensures that the 2416 * unicast DMACs for all VIs on all ports get an 2417 * MPS TCAM entry. 2418 */ 2419 rc = update_mac_settings(ifp, XGMAC_ALL & 2420 ~XGMAC_MCADDRS); 2421 if (rc != 0) { 2422 CH_ERR(vi, "failed to re-configure MAC: %d\n", rc); 2423 goto done; 2424 } 2425 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, 2426 true); 2427 if (rc != 0) { 2428 CH_ERR(vi, "failed to re-enable VI: %d\n", rc); 2429 goto done; 2430 } 2431 for_each_txq(vi, k, txq) { 2432 TXQ_LOCK(txq); 2433 txq->eq.flags |= EQ_ENABLED; 2434 TXQ_UNLOCK(txq); 2435 } 2436 mtx_lock(&vi->tick_mtx); 2437 callout_schedule(&vi->tick, hz); 2438 mtx_unlock(&vi->tick_mtx); 2439 } 2440 PORT_LOCK(pi); 2441 if (pi->up_vis > 0) { 2442 t4_update_port_info(pi); 2443 fixup_link_config(pi); 2444 build_medialist(pi); 2445 apply_link_config(pi); 2446 if (pi->link_cfg.link_ok) 2447 t4_os_link_changed(pi); 2448 } 2449 PORT_UNLOCK(pi); 2450 } 2451 2452 /* Now reprogram the L2 multicast addresses. */ 2453 for_each_port(sc, i) { 2454 pi = sc->port[i]; 2455 for_each_vi(pi, j, vi) { 2456 if (!(vi->flags & VI_INIT_DONE)) 2457 continue; 2458 ifp = vi->ifp; 2459 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2460 continue; 2461 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2462 if (rc != 0) { 2463 CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc); 2464 rc = 0; /* carry on */ 2465 } 2466 } 2467 } 2468 } 2469 2470 /* Reset all calibration */ 2471 t4_calibration_start(sc); 2472 done: 2473 end_synchronized_op(sc, 0); 2474 free(old_state, M_CXGBE); 2475 2476 restart_atid_allocator(sc); 2477 t4_restart_l2t(sc); 2478 2479 return (rc); 2480 } 2481 2482 int 2483 resume_adapter(struct adapter *sc) 2484 { 2485 restart_adapter(sc); 2486 restart_lld(sc); 2487 #ifdef TCP_OFFLOAD 2488 restart_all_uld(sc); 2489 #endif 2490 return (0); 2491 } 2492 2493 static int 2494 t4_resume(device_t dev) 2495 { 2496 struct adapter *sc = device_get_softc(dev); 2497 int rc; 2498 2499 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2500 rc = resume_adapter(sc); 2501 CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread); 2502 2503 return (rc); 2504 } 2505 2506 static int 2507 t4_reset_prepare(device_t dev, device_t child) 2508 { 2509 struct adapter *sc = device_get_softc(dev); 2510 2511 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2512 return (0); 2513 } 2514 2515 static int 2516 t4_reset_post(device_t dev, device_t child) 2517 { 2518 struct adapter *sc = device_get_softc(dev); 2519 2520 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2521 return (0); 2522 } 2523 2524 static int 2525 reset_adapter_with_pci_bus_reset(struct adapter *sc) 2526 { 2527 int rc; 2528 2529 mtx_lock(&Giant); 2530 rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0); 2531 mtx_unlock(&Giant); 2532 return (rc); 2533 } 2534 2535 static int 2536 reset_adapter_with_pl_rst(struct adapter *sc) 2537 { 2538 suspend_adapter(sc); 2539 2540 /* This is a t4_write_reg without the hw_off_limits check. */ 2541 MPASS(sc->error_flags & HW_OFF_LIMITS); 2542 bus_space_write_4(sc->bt, sc->bh, A_PL_RST, 2543 F_PIORSTMODE | F_PIORST | F_AUTOPCIEPAUSE); 2544 pause("pl_rst", 1 * hz); /* Wait 1s for reset */ 2545 2546 resume_adapter(sc); 2547 2548 return (0); 2549 } 2550 2551 static inline int 2552 reset_adapter(struct adapter *sc) 2553 { 2554 if (vm_guest == 0) 2555 return (reset_adapter_with_pci_bus_reset(sc)); 2556 else 2557 return (reset_adapter_with_pl_rst(sc)); 2558 } 2559 2560 static void 2561 reset_adapter_task(void *arg, int pending) 2562 { 2563 struct adapter *sc = arg; 2564 const int flags = sc->flags; 2565 const int eflags = sc->error_flags; 2566 int rc; 2567 2568 if (pending > 1) 2569 CH_ALERT(sc, "%s: pending %d\n", __func__, pending); 2570 rc = reset_adapter(sc); 2571 if (rc != 0) { 2572 CH_ERR(sc, "adapter did not reset properly, rc = %d, " 2573 "flags 0x%08x -> 0x%08x, err_flags 0x%08x -> 0x%08x.\n", 2574 rc, flags, sc->flags, eflags, sc->error_flags); 2575 } 2576 } 2577 2578 static int 2579 cxgbe_probe(device_t dev) 2580 { 2581 struct port_info *pi = device_get_softc(dev); 2582 2583 device_set_descf(dev, "port %d", pi->port_id); 2584 2585 return (BUS_PROBE_DEFAULT); 2586 } 2587 2588 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 2589 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 2590 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 2591 IFCAP_HWRXTSTMP | IFCAP_MEXTPG) 2592 #define T4_CAP_ENABLE (T4_CAP) 2593 2594 static void 2595 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 2596 { 2597 if_t ifp; 2598 struct sbuf *sb; 2599 struct sysctl_ctx_list *ctx = &vi->ctx; 2600 struct sysctl_oid_list *children; 2601 struct pfil_head_args pa; 2602 struct adapter *sc = vi->adapter; 2603 2604 sysctl_ctx_init(ctx); 2605 children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev)); 2606 vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq", 2607 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues"); 2608 vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq", 2609 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues"); 2610 #ifdef DEV_NETMAP 2611 vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq", 2612 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues"); 2613 vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq", 2614 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues"); 2615 #endif 2616 #ifdef TCP_OFFLOAD 2617 vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq", 2618 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues"); 2619 #endif 2620 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2621 vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq", 2622 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues"); 2623 #endif 2624 2625 vi->xact_addr_filt = -1; 2626 mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF); 2627 callout_init_mtx(&vi->tick, &vi->tick_mtx, 0); 2628 if (sc->flags & IS_VF || t4_tx_vm_wr != 0) 2629 vi->flags |= TX_USES_VM_WR; 2630 2631 /* Allocate an ifnet and set it up */ 2632 ifp = if_alloc_dev(IFT_ETHER, dev); 2633 vi->ifp = ifp; 2634 if_setsoftc(ifp, vi); 2635 2636 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2637 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2638 2639 if_setinitfn(ifp, cxgbe_init); 2640 if_setioctlfn(ifp, cxgbe_ioctl); 2641 if_settransmitfn(ifp, cxgbe_transmit); 2642 if_setqflushfn(ifp, cxgbe_qflush); 2643 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 2644 if_setgetcounterfn(ifp, vi_get_counter); 2645 else 2646 if_setgetcounterfn(ifp, cxgbe_get_counter); 2647 #if defined(KERN_TLS) || defined(RATELIMIT) 2648 if_setsndtagallocfn(ifp, cxgbe_snd_tag_alloc); 2649 #endif 2650 #ifdef RATELIMIT 2651 if_setratelimitqueryfn(ifp, cxgbe_ratelimit_query); 2652 #endif 2653 2654 if_setcapabilities(ifp, T4_CAP); 2655 if_setcapenable(ifp, T4_CAP_ENABLE); 2656 if_sethwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 2657 CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2658 if (chip_id(sc) >= CHELSIO_T6) { 2659 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2660 if_setcapenablebit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2661 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 2662 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2663 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN, 0); 2664 } 2665 2666 #ifdef TCP_OFFLOAD 2667 if (vi->nofldrxq != 0) 2668 if_setcapabilitiesbit(ifp, IFCAP_TOE, 0); 2669 #endif 2670 #ifdef RATELIMIT 2671 if (is_ethoffload(sc) && vi->nofldtxq != 0) { 2672 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0); 2673 if_setcapenablebit(ifp, IFCAP_TXRTLMT, 0); 2674 } 2675 #endif 2676 2677 if_sethwtsomax(ifp, IP_MAXPACKET); 2678 if (vi->flags & TX_USES_VM_WR) 2679 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_VM_TSO); 2680 else 2681 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_TSO); 2682 #ifdef RATELIMIT 2683 if (is_ethoffload(sc) && vi->nofldtxq != 0) 2684 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_EO_TSO); 2685 #endif 2686 if_sethwtsomaxsegsize(ifp, 65536); 2687 #ifdef KERN_TLS 2688 if (is_ktls(sc)) { 2689 if_setcapabilitiesbit(ifp, IFCAP_TXTLS, 0); 2690 if (sc->flags & KERN_TLS_ON || !is_t6(sc)) 2691 if_setcapenablebit(ifp, IFCAP_TXTLS, 0); 2692 } 2693 #endif 2694 2695 ether_ifattach(ifp, vi->hw_addr); 2696 #ifdef DEV_NETMAP 2697 if (vi->nnmrxq != 0) 2698 cxgbe_nm_attach(vi); 2699 #endif 2700 sb = sbuf_new_auto(); 2701 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 2702 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2703 switch (if_getcapabilities(ifp) & (IFCAP_TOE | IFCAP_TXRTLMT)) { 2704 case IFCAP_TOE: 2705 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 2706 break; 2707 case IFCAP_TOE | IFCAP_TXRTLMT: 2708 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 2709 break; 2710 case IFCAP_TXRTLMT: 2711 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 2712 break; 2713 } 2714 #endif 2715 #ifdef TCP_OFFLOAD 2716 if (if_getcapabilities(ifp) & IFCAP_TOE) 2717 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 2718 #endif 2719 #ifdef DEV_NETMAP 2720 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2721 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 2722 vi->nnmtxq, vi->nnmrxq); 2723 #endif 2724 sbuf_finish(sb); 2725 device_printf(dev, "%s\n", sbuf_data(sb)); 2726 sbuf_delete(sb); 2727 2728 vi_sysctls(vi); 2729 2730 pa.pa_version = PFIL_VERSION; 2731 pa.pa_flags = PFIL_IN; 2732 pa.pa_type = PFIL_TYPE_ETHERNET; 2733 pa.pa_headname = if_name(ifp); 2734 vi->pfil = pfil_head_register(&pa); 2735 } 2736 2737 static int 2738 cxgbe_attach(device_t dev) 2739 { 2740 struct port_info *pi = device_get_softc(dev); 2741 struct adapter *sc = pi->adapter; 2742 struct vi_info *vi; 2743 int i; 2744 2745 sysctl_ctx_init(&pi->ctx); 2746 2747 cxgbe_vi_attach(dev, &pi->vi[0]); 2748 2749 for_each_vi(pi, i, vi) { 2750 if (i == 0) 2751 continue; 2752 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, DEVICE_UNIT_ANY); 2753 if (vi->dev == NULL) { 2754 device_printf(dev, "failed to add VI %d\n", i); 2755 continue; 2756 } 2757 device_set_softc(vi->dev, vi); 2758 } 2759 2760 cxgbe_sysctls(pi); 2761 2762 bus_generic_attach(dev); 2763 2764 return (0); 2765 } 2766 2767 static void 2768 cxgbe_vi_detach(struct vi_info *vi) 2769 { 2770 if_t ifp = vi->ifp; 2771 2772 if (vi->pfil != NULL) { 2773 pfil_head_unregister(vi->pfil); 2774 vi->pfil = NULL; 2775 } 2776 2777 ether_ifdetach(ifp); 2778 2779 /* Let detach proceed even if these fail. */ 2780 #ifdef DEV_NETMAP 2781 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2782 cxgbe_nm_detach(vi); 2783 #endif 2784 cxgbe_uninit_synchronized(vi); 2785 callout_drain(&vi->tick); 2786 mtx_destroy(&vi->tick_mtx); 2787 sysctl_ctx_free(&vi->ctx); 2788 vi_full_uninit(vi); 2789 2790 if_free(vi->ifp); 2791 vi->ifp = NULL; 2792 } 2793 2794 static int 2795 cxgbe_detach(device_t dev) 2796 { 2797 struct port_info *pi = device_get_softc(dev); 2798 struct adapter *sc = pi->adapter; 2799 int rc; 2800 2801 /* Detach the extra VIs first. */ 2802 rc = bus_generic_detach(dev); 2803 if (rc) 2804 return (rc); 2805 device_delete_children(dev); 2806 2807 sysctl_ctx_free(&pi->ctx); 2808 begin_vi_detach(sc, &pi->vi[0]); 2809 if (pi->flags & HAS_TRACEQ) { 2810 sc->traceq = -1; /* cloner should not create ifnet */ 2811 t4_tracer_port_detach(sc); 2812 } 2813 cxgbe_vi_detach(&pi->vi[0]); 2814 ifmedia_removeall(&pi->media); 2815 end_vi_detach(sc, &pi->vi[0]); 2816 2817 return (0); 2818 } 2819 2820 static void 2821 cxgbe_init(void *arg) 2822 { 2823 struct vi_info *vi = arg; 2824 struct adapter *sc = vi->adapter; 2825 2826 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 2827 return; 2828 cxgbe_init_synchronized(vi); 2829 end_synchronized_op(sc, 0); 2830 } 2831 2832 static int 2833 cxgbe_ioctl(if_t ifp, unsigned long cmd, caddr_t data) 2834 { 2835 int rc = 0, mtu, flags; 2836 struct vi_info *vi = if_getsoftc(ifp); 2837 struct port_info *pi = vi->pi; 2838 struct adapter *sc = pi->adapter; 2839 struct ifreq *ifr = (struct ifreq *)data; 2840 uint32_t mask; 2841 2842 switch (cmd) { 2843 case SIOCSIFMTU: 2844 mtu = ifr->ifr_mtu; 2845 if (mtu < ETHERMIN || mtu > MAX_MTU) 2846 return (EINVAL); 2847 2848 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 2849 if (rc) 2850 return (rc); 2851 if_setmtu(ifp, mtu); 2852 if (vi->flags & VI_INIT_DONE) { 2853 t4_update_fl_bufsize(ifp); 2854 if (!hw_off_limits(sc) && 2855 if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2856 rc = update_mac_settings(ifp, XGMAC_MTU); 2857 } 2858 end_synchronized_op(sc, 0); 2859 break; 2860 2861 case SIOCSIFFLAGS: 2862 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 2863 if (rc) 2864 return (rc); 2865 2866 if (hw_off_limits(sc)) { 2867 rc = ENXIO; 2868 goto fail; 2869 } 2870 2871 if (if_getflags(ifp) & IFF_UP) { 2872 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2873 flags = vi->if_flags; 2874 if ((if_getflags(ifp) ^ flags) & 2875 (IFF_PROMISC | IFF_ALLMULTI)) { 2876 rc = update_mac_settings(ifp, 2877 XGMAC_PROMISC | XGMAC_ALLMULTI); 2878 } 2879 } else { 2880 rc = cxgbe_init_synchronized(vi); 2881 } 2882 vi->if_flags = if_getflags(ifp); 2883 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2884 rc = cxgbe_uninit_synchronized(vi); 2885 } 2886 end_synchronized_op(sc, 0); 2887 break; 2888 2889 case SIOCADDMULTI: 2890 case SIOCDELMULTI: 2891 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 2892 if (rc) 2893 return (rc); 2894 if (!hw_off_limits(sc) && if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2895 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2896 end_synchronized_op(sc, 0); 2897 break; 2898 2899 case SIOCSIFCAP: 2900 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 2901 if (rc) 2902 return (rc); 2903 2904 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2905 if (mask & IFCAP_TXCSUM) { 2906 if_togglecapenable(ifp, IFCAP_TXCSUM); 2907 if_togglehwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP); 2908 2909 if (IFCAP_TSO4 & if_getcapenable(ifp) && 2910 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2911 mask &= ~IFCAP_TSO4; 2912 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 2913 if_printf(ifp, 2914 "tso4 disabled due to -txcsum.\n"); 2915 } 2916 } 2917 if (mask & IFCAP_TXCSUM_IPV6) { 2918 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 2919 if_togglehwassist(ifp, CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2920 2921 if (IFCAP_TSO6 & if_getcapenable(ifp) && 2922 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2923 mask &= ~IFCAP_TSO6; 2924 if_setcapenablebit(ifp, 0, IFCAP_TSO6); 2925 if_printf(ifp, 2926 "tso6 disabled due to -txcsum6.\n"); 2927 } 2928 } 2929 if (mask & IFCAP_RXCSUM) 2930 if_togglecapenable(ifp, IFCAP_RXCSUM); 2931 if (mask & IFCAP_RXCSUM_IPV6) 2932 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 2933 2934 /* 2935 * Note that we leave CSUM_TSO alone (it is always set). The 2936 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 2937 * sending a TSO request our way, so it's sufficient to toggle 2938 * IFCAP_TSOx only. 2939 */ 2940 if (mask & IFCAP_TSO4) { 2941 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) && 2942 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2943 if_printf(ifp, "enable txcsum first.\n"); 2944 rc = EAGAIN; 2945 goto fail; 2946 } 2947 if_togglecapenable(ifp, IFCAP_TSO4); 2948 } 2949 if (mask & IFCAP_TSO6) { 2950 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) && 2951 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2952 if_printf(ifp, "enable txcsum6 first.\n"); 2953 rc = EAGAIN; 2954 goto fail; 2955 } 2956 if_togglecapenable(ifp, IFCAP_TSO6); 2957 } 2958 if (mask & IFCAP_LRO) { 2959 #if defined(INET) || defined(INET6) 2960 int i; 2961 struct sge_rxq *rxq; 2962 2963 if_togglecapenable(ifp, IFCAP_LRO); 2964 for_each_rxq(vi, i, rxq) { 2965 if (if_getcapenable(ifp) & IFCAP_LRO) 2966 rxq->iq.flags |= IQ_LRO_ENABLED; 2967 else 2968 rxq->iq.flags &= ~IQ_LRO_ENABLED; 2969 } 2970 #endif 2971 } 2972 #ifdef TCP_OFFLOAD 2973 if (mask & IFCAP_TOE) { 2974 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TOE; 2975 2976 rc = toe_capability(vi, enable); 2977 if (rc != 0) 2978 goto fail; 2979 2980 if_togglecapenable(ifp, mask); 2981 } 2982 #endif 2983 if (mask & IFCAP_VLAN_HWTAGGING) { 2984 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2985 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2986 rc = update_mac_settings(ifp, XGMAC_VLANEX); 2987 } 2988 if (mask & IFCAP_VLAN_MTU) { 2989 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 2990 2991 /* Need to find out how to disable auto-mtu-inflation */ 2992 } 2993 if (mask & IFCAP_VLAN_HWTSO) 2994 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2995 if (mask & IFCAP_VLAN_HWCSUM) 2996 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2997 #ifdef RATELIMIT 2998 if (mask & IFCAP_TXRTLMT) 2999 if_togglecapenable(ifp, IFCAP_TXRTLMT); 3000 #endif 3001 if (mask & IFCAP_HWRXTSTMP) { 3002 int i; 3003 struct sge_rxq *rxq; 3004 3005 if_togglecapenable(ifp, IFCAP_HWRXTSTMP); 3006 for_each_rxq(vi, i, rxq) { 3007 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) 3008 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3009 else 3010 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 3011 } 3012 } 3013 if (mask & IFCAP_MEXTPG) 3014 if_togglecapenable(ifp, IFCAP_MEXTPG); 3015 3016 #ifdef KERN_TLS 3017 if (mask & IFCAP_TXTLS) { 3018 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TXTLS; 3019 3020 rc = ktls_capability(sc, enable); 3021 if (rc != 0) 3022 goto fail; 3023 3024 if_togglecapenable(ifp, mask & IFCAP_TXTLS); 3025 } 3026 #endif 3027 if (mask & IFCAP_VXLAN_HWCSUM) { 3028 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM); 3029 if_togglehwassist(ifp, CSUM_INNER_IP6_UDP | 3030 CSUM_INNER_IP6_TCP | CSUM_INNER_IP | 3031 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP); 3032 } 3033 if (mask & IFCAP_VXLAN_HWTSO) { 3034 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO); 3035 if_togglehwassist(ifp, CSUM_INNER_IP6_TSO | 3036 CSUM_INNER_IP_TSO); 3037 } 3038 3039 #ifdef VLAN_CAPABILITIES 3040 VLAN_CAPABILITIES(ifp); 3041 #endif 3042 fail: 3043 end_synchronized_op(sc, 0); 3044 break; 3045 3046 case SIOCSIFMEDIA: 3047 case SIOCGIFMEDIA: 3048 case SIOCGIFXMEDIA: 3049 rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 3050 break; 3051 3052 case SIOCGI2C: { 3053 struct ifi2creq i2c; 3054 3055 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3056 if (rc != 0) 3057 break; 3058 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3059 rc = EPERM; 3060 break; 3061 } 3062 if (i2c.len > sizeof(i2c.data)) { 3063 rc = EINVAL; 3064 break; 3065 } 3066 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 3067 if (rc) 3068 return (rc); 3069 if (hw_off_limits(sc)) 3070 rc = ENXIO; 3071 else 3072 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 3073 i2c.offset, i2c.len, &i2c.data[0]); 3074 end_synchronized_op(sc, 0); 3075 if (rc == 0) 3076 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3077 break; 3078 } 3079 3080 default: 3081 rc = ether_ioctl(ifp, cmd, data); 3082 } 3083 3084 return (rc); 3085 } 3086 3087 static int 3088 cxgbe_transmit(if_t ifp, struct mbuf *m) 3089 { 3090 struct vi_info *vi = if_getsoftc(ifp); 3091 struct port_info *pi = vi->pi; 3092 struct adapter *sc; 3093 struct sge_txq *txq; 3094 void *items[1]; 3095 int rc; 3096 3097 M_ASSERTPKTHDR(m); 3098 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 3099 #if defined(KERN_TLS) || defined(RATELIMIT) 3100 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) 3101 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 3102 #endif 3103 3104 if (__predict_false(pi->link_cfg.link_ok == false)) { 3105 m_freem(m); 3106 return (ENETDOWN); 3107 } 3108 3109 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR); 3110 if (__predict_false(rc != 0)) { 3111 if (__predict_true(rc == EINPROGRESS)) { 3112 /* queued by parse_pkt */ 3113 MPASS(m != NULL); 3114 return (0); 3115 } 3116 3117 MPASS(m == NULL); /* was freed already */ 3118 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 3119 return (rc); 3120 } 3121 3122 /* Select a txq. */ 3123 sc = vi->adapter; 3124 txq = &sc->sge.txq[vi->first_txq]; 3125 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 3126 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 3127 vi->rsrv_noflowq); 3128 3129 items[0] = m; 3130 rc = mp_ring_enqueue(txq->r, items, 1, 256); 3131 if (__predict_false(rc != 0)) 3132 m_freem(m); 3133 3134 return (rc); 3135 } 3136 3137 static void 3138 cxgbe_qflush(if_t ifp) 3139 { 3140 struct vi_info *vi = if_getsoftc(ifp); 3141 struct sge_txq *txq; 3142 int i; 3143 3144 /* queues do not exist if !VI_INIT_DONE. */ 3145 if (vi->flags & VI_INIT_DONE) { 3146 for_each_txq(vi, i, txq) { 3147 TXQ_LOCK(txq); 3148 txq->eq.flags |= EQ_QFLUSH; 3149 TXQ_UNLOCK(txq); 3150 while (!mp_ring_is_idle(txq->r)) { 3151 mp_ring_check_drainage(txq->r, 4096); 3152 pause("qflush", 1); 3153 } 3154 TXQ_LOCK(txq); 3155 txq->eq.flags &= ~EQ_QFLUSH; 3156 TXQ_UNLOCK(txq); 3157 } 3158 } 3159 if_qflush(ifp); 3160 } 3161 3162 static uint64_t 3163 vi_get_counter(if_t ifp, ift_counter c) 3164 { 3165 struct vi_info *vi = if_getsoftc(ifp); 3166 struct fw_vi_stats_vf *s = &vi->stats; 3167 3168 mtx_lock(&vi->tick_mtx); 3169 vi_refresh_stats(vi); 3170 mtx_unlock(&vi->tick_mtx); 3171 3172 switch (c) { 3173 case IFCOUNTER_IPACKETS: 3174 return (s->rx_bcast_frames + s->rx_mcast_frames + 3175 s->rx_ucast_frames); 3176 case IFCOUNTER_IERRORS: 3177 return (s->rx_err_frames); 3178 case IFCOUNTER_OPACKETS: 3179 return (s->tx_bcast_frames + s->tx_mcast_frames + 3180 s->tx_ucast_frames + s->tx_offload_frames); 3181 case IFCOUNTER_OERRORS: 3182 return (s->tx_drop_frames); 3183 case IFCOUNTER_IBYTES: 3184 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 3185 s->rx_ucast_bytes); 3186 case IFCOUNTER_OBYTES: 3187 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 3188 s->tx_ucast_bytes + s->tx_offload_bytes); 3189 case IFCOUNTER_IMCASTS: 3190 return (s->rx_mcast_frames); 3191 case IFCOUNTER_OMCASTS: 3192 return (s->tx_mcast_frames); 3193 case IFCOUNTER_OQDROPS: { 3194 uint64_t drops; 3195 3196 drops = 0; 3197 if (vi->flags & VI_INIT_DONE) { 3198 int i; 3199 struct sge_txq *txq; 3200 3201 for_each_txq(vi, i, txq) 3202 drops += counter_u64_fetch(txq->r->dropped); 3203 } 3204 3205 return (drops); 3206 3207 } 3208 3209 default: 3210 return (if_get_counter_default(ifp, c)); 3211 } 3212 } 3213 3214 static uint64_t 3215 cxgbe_get_counter(if_t ifp, ift_counter c) 3216 { 3217 struct vi_info *vi = if_getsoftc(ifp); 3218 struct port_info *pi = vi->pi; 3219 struct port_stats *s = &pi->stats; 3220 3221 mtx_lock(&vi->tick_mtx); 3222 cxgbe_refresh_stats(vi); 3223 mtx_unlock(&vi->tick_mtx); 3224 3225 switch (c) { 3226 case IFCOUNTER_IPACKETS: 3227 return (s->rx_frames); 3228 3229 case IFCOUNTER_IERRORS: 3230 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 3231 s->rx_fcs_err + s->rx_len_err); 3232 3233 case IFCOUNTER_OPACKETS: 3234 return (s->tx_frames); 3235 3236 case IFCOUNTER_OERRORS: 3237 return (s->tx_error_frames); 3238 3239 case IFCOUNTER_IBYTES: 3240 return (s->rx_octets); 3241 3242 case IFCOUNTER_OBYTES: 3243 return (s->tx_octets); 3244 3245 case IFCOUNTER_IMCASTS: 3246 return (s->rx_mcast_frames); 3247 3248 case IFCOUNTER_OMCASTS: 3249 return (s->tx_mcast_frames); 3250 3251 case IFCOUNTER_IQDROPS: 3252 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 3253 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 3254 s->rx_trunc3 + pi->tnl_cong_drops); 3255 3256 case IFCOUNTER_OQDROPS: { 3257 uint64_t drops; 3258 3259 drops = s->tx_drop; 3260 if (vi->flags & VI_INIT_DONE) { 3261 int i; 3262 struct sge_txq *txq; 3263 3264 for_each_txq(vi, i, txq) 3265 drops += counter_u64_fetch(txq->r->dropped); 3266 } 3267 3268 return (drops); 3269 3270 } 3271 3272 default: 3273 return (if_get_counter_default(ifp, c)); 3274 } 3275 } 3276 3277 #if defined(KERN_TLS) || defined(RATELIMIT) 3278 static int 3279 cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params, 3280 struct m_snd_tag **pt) 3281 { 3282 int error; 3283 3284 switch (params->hdr.type) { 3285 #ifdef RATELIMIT 3286 case IF_SND_TAG_TYPE_RATE_LIMIT: 3287 error = cxgbe_rate_tag_alloc(ifp, params, pt); 3288 break; 3289 #endif 3290 #ifdef KERN_TLS 3291 case IF_SND_TAG_TYPE_TLS: 3292 { 3293 struct vi_info *vi = if_getsoftc(ifp); 3294 3295 if (is_t6(vi->pi->adapter)) 3296 error = t6_tls_tag_alloc(ifp, params, pt); 3297 else 3298 error = EOPNOTSUPP; 3299 break; 3300 } 3301 #endif 3302 default: 3303 error = EOPNOTSUPP; 3304 } 3305 return (error); 3306 } 3307 #endif 3308 3309 /* 3310 * The kernel picks a media from the list we had provided but we still validate 3311 * the requeste. 3312 */ 3313 int 3314 cxgbe_media_change(if_t ifp) 3315 { 3316 struct vi_info *vi = if_getsoftc(ifp); 3317 struct port_info *pi = vi->pi; 3318 struct ifmedia *ifm = &pi->media; 3319 struct link_config *lc = &pi->link_cfg; 3320 struct adapter *sc = pi->adapter; 3321 int rc; 3322 3323 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 3324 if (rc != 0) 3325 return (rc); 3326 PORT_LOCK(pi); 3327 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 3328 /* ifconfig .. media autoselect */ 3329 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { 3330 rc = ENOTSUP; /* AN not supported by transceiver */ 3331 goto done; 3332 } 3333 lc->requested_aneg = AUTONEG_ENABLE; 3334 lc->requested_speed = 0; 3335 lc->requested_fc |= PAUSE_AUTONEG; 3336 } else { 3337 lc->requested_aneg = AUTONEG_DISABLE; 3338 lc->requested_speed = 3339 ifmedia_baudrate(ifm->ifm_media) / 1000000; 3340 lc->requested_fc = 0; 3341 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 3342 lc->requested_fc |= PAUSE_RX; 3343 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 3344 lc->requested_fc |= PAUSE_TX; 3345 } 3346 if (pi->up_vis > 0 && !hw_off_limits(sc)) { 3347 fixup_link_config(pi); 3348 rc = apply_link_config(pi); 3349 } 3350 done: 3351 PORT_UNLOCK(pi); 3352 end_synchronized_op(sc, 0); 3353 return (rc); 3354 } 3355 3356 /* 3357 * Base media word (without ETHER, pause, link active, etc.) for the port at the 3358 * given speed. 3359 */ 3360 static int 3361 port_mword(struct port_info *pi, uint32_t speed) 3362 { 3363 3364 MPASS(speed & M_FW_PORT_CAP32_SPEED); 3365 MPASS(powerof2(speed)); 3366 3367 switch(pi->port_type) { 3368 case FW_PORT_TYPE_BT_SGMII: 3369 case FW_PORT_TYPE_BT_XFI: 3370 case FW_PORT_TYPE_BT_XAUI: 3371 /* BaseT */ 3372 switch (speed) { 3373 case FW_PORT_CAP32_SPEED_100M: 3374 return (IFM_100_T); 3375 case FW_PORT_CAP32_SPEED_1G: 3376 return (IFM_1000_T); 3377 case FW_PORT_CAP32_SPEED_10G: 3378 return (IFM_10G_T); 3379 } 3380 break; 3381 case FW_PORT_TYPE_KX4: 3382 if (speed == FW_PORT_CAP32_SPEED_10G) 3383 return (IFM_10G_KX4); 3384 break; 3385 case FW_PORT_TYPE_CX4: 3386 if (speed == FW_PORT_CAP32_SPEED_10G) 3387 return (IFM_10G_CX4); 3388 break; 3389 case FW_PORT_TYPE_KX: 3390 if (speed == FW_PORT_CAP32_SPEED_1G) 3391 return (IFM_1000_KX); 3392 break; 3393 case FW_PORT_TYPE_KR: 3394 case FW_PORT_TYPE_BP_AP: 3395 case FW_PORT_TYPE_BP4_AP: 3396 case FW_PORT_TYPE_BP40_BA: 3397 case FW_PORT_TYPE_KR4_100G: 3398 case FW_PORT_TYPE_KR_SFP28: 3399 case FW_PORT_TYPE_KR_XLAUI: 3400 switch (speed) { 3401 case FW_PORT_CAP32_SPEED_1G: 3402 return (IFM_1000_KX); 3403 case FW_PORT_CAP32_SPEED_10G: 3404 return (IFM_10G_KR); 3405 case FW_PORT_CAP32_SPEED_25G: 3406 return (IFM_25G_KR); 3407 case FW_PORT_CAP32_SPEED_40G: 3408 return (IFM_40G_KR4); 3409 case FW_PORT_CAP32_SPEED_50G: 3410 return (IFM_50G_KR2); 3411 case FW_PORT_CAP32_SPEED_100G: 3412 return (IFM_100G_KR4); 3413 } 3414 break; 3415 case FW_PORT_TYPE_FIBER_XFI: 3416 case FW_PORT_TYPE_FIBER_XAUI: 3417 case FW_PORT_TYPE_SFP: 3418 case FW_PORT_TYPE_QSFP_10G: 3419 case FW_PORT_TYPE_QSA: 3420 case FW_PORT_TYPE_QSFP: 3421 case FW_PORT_TYPE_CR4_QSFP: 3422 case FW_PORT_TYPE_CR_QSFP: 3423 case FW_PORT_TYPE_CR2_QSFP: 3424 case FW_PORT_TYPE_SFP28: 3425 /* Pluggable transceiver */ 3426 switch (pi->mod_type) { 3427 case FW_PORT_MOD_TYPE_LR: 3428 switch (speed) { 3429 case FW_PORT_CAP32_SPEED_1G: 3430 return (IFM_1000_LX); 3431 case FW_PORT_CAP32_SPEED_10G: 3432 return (IFM_10G_LR); 3433 case FW_PORT_CAP32_SPEED_25G: 3434 return (IFM_25G_LR); 3435 case FW_PORT_CAP32_SPEED_40G: 3436 return (IFM_40G_LR4); 3437 case FW_PORT_CAP32_SPEED_50G: 3438 return (IFM_50G_LR2); 3439 case FW_PORT_CAP32_SPEED_100G: 3440 return (IFM_100G_LR4); 3441 } 3442 break; 3443 case FW_PORT_MOD_TYPE_SR: 3444 switch (speed) { 3445 case FW_PORT_CAP32_SPEED_1G: 3446 return (IFM_1000_SX); 3447 case FW_PORT_CAP32_SPEED_10G: 3448 return (IFM_10G_SR); 3449 case FW_PORT_CAP32_SPEED_25G: 3450 return (IFM_25G_SR); 3451 case FW_PORT_CAP32_SPEED_40G: 3452 return (IFM_40G_SR4); 3453 case FW_PORT_CAP32_SPEED_50G: 3454 return (IFM_50G_SR2); 3455 case FW_PORT_CAP32_SPEED_100G: 3456 return (IFM_100G_SR4); 3457 } 3458 break; 3459 case FW_PORT_MOD_TYPE_ER: 3460 if (speed == FW_PORT_CAP32_SPEED_10G) 3461 return (IFM_10G_ER); 3462 break; 3463 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3464 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3465 switch (speed) { 3466 case FW_PORT_CAP32_SPEED_1G: 3467 return (IFM_1000_CX); 3468 case FW_PORT_CAP32_SPEED_10G: 3469 return (IFM_10G_TWINAX); 3470 case FW_PORT_CAP32_SPEED_25G: 3471 return (IFM_25G_CR); 3472 case FW_PORT_CAP32_SPEED_40G: 3473 return (IFM_40G_CR4); 3474 case FW_PORT_CAP32_SPEED_50G: 3475 return (IFM_50G_CR2); 3476 case FW_PORT_CAP32_SPEED_100G: 3477 return (IFM_100G_CR4); 3478 } 3479 break; 3480 case FW_PORT_MOD_TYPE_LRM: 3481 if (speed == FW_PORT_CAP32_SPEED_10G) 3482 return (IFM_10G_LRM); 3483 break; 3484 case FW_PORT_MOD_TYPE_NA: 3485 MPASS(0); /* Not pluggable? */ 3486 /* fall throough */ 3487 case FW_PORT_MOD_TYPE_ERROR: 3488 case FW_PORT_MOD_TYPE_UNKNOWN: 3489 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 3490 break; 3491 case FW_PORT_MOD_TYPE_NONE: 3492 return (IFM_NONE); 3493 } 3494 break; 3495 case FW_PORT_TYPE_NONE: 3496 return (IFM_NONE); 3497 } 3498 3499 return (IFM_UNKNOWN); 3500 } 3501 3502 void 3503 cxgbe_media_status(if_t ifp, struct ifmediareq *ifmr) 3504 { 3505 struct vi_info *vi = if_getsoftc(ifp); 3506 struct port_info *pi = vi->pi; 3507 struct adapter *sc = pi->adapter; 3508 struct link_config *lc = &pi->link_cfg; 3509 3510 if (begin_synchronized_op(sc, vi , SLEEP_OK | INTR_OK, "t4med") != 0) 3511 return; 3512 PORT_LOCK(pi); 3513 3514 if (pi->up_vis == 0 && !hw_off_limits(sc)) { 3515 /* 3516 * If all the interfaces are administratively down the firmware 3517 * does not report transceiver changes. Refresh port info here 3518 * so that ifconfig displays accurate ifmedia at all times. 3519 * This is the only reason we have a synchronized op in this 3520 * function. Just PORT_LOCK would have been enough otherwise. 3521 */ 3522 t4_update_port_info(pi); 3523 build_medialist(pi); 3524 } 3525 3526 /* ifm_status */ 3527 ifmr->ifm_status = IFM_AVALID; 3528 if (lc->link_ok == false) 3529 goto done; 3530 ifmr->ifm_status |= IFM_ACTIVE; 3531 3532 /* ifm_active */ 3533 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 3534 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 3535 if (lc->fc & PAUSE_RX) 3536 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3537 if (lc->fc & PAUSE_TX) 3538 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3539 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 3540 done: 3541 PORT_UNLOCK(pi); 3542 end_synchronized_op(sc, 0); 3543 } 3544 3545 static int 3546 vcxgbe_probe(device_t dev) 3547 { 3548 struct vi_info *vi = device_get_softc(dev); 3549 3550 device_set_descf(dev, "port %d vi %td", vi->pi->port_id, 3551 vi - vi->pi->vi); 3552 3553 return (BUS_PROBE_DEFAULT); 3554 } 3555 3556 static int 3557 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 3558 { 3559 int func, index, rc; 3560 uint32_t param, val; 3561 3562 ASSERT_SYNCHRONIZED_OP(sc); 3563 3564 index = vi - pi->vi; 3565 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 3566 KASSERT(index < nitems(vi_mac_funcs), 3567 ("%s: VI %s doesn't have a MAC func", __func__, 3568 device_get_nameunit(vi->dev))); 3569 func = vi_mac_funcs[index]; 3570 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 3571 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 3572 if (rc < 0) { 3573 CH_ERR(vi, "failed to allocate virtual interface %d" 3574 "for port %d: %d\n", index, pi->port_id, -rc); 3575 return (-rc); 3576 } 3577 vi->viid = rc; 3578 3579 if (vi->rss_size == 1) { 3580 /* 3581 * This VI didn't get a slice of the RSS table. Reduce the 3582 * number of VIs being created (hw.cxgbe.num_vis) or modify the 3583 * configuration file (nvi, rssnvi for this PF) if this is a 3584 * problem. 3585 */ 3586 device_printf(vi->dev, "RSS table not available.\n"); 3587 vi->rss_base = 0xffff; 3588 3589 return (0); 3590 } 3591 3592 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3593 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 3594 V_FW_PARAMS_PARAM_YZ(vi->viid); 3595 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3596 if (rc) 3597 vi->rss_base = 0xffff; 3598 else { 3599 MPASS((val >> 16) == vi->rss_size); 3600 vi->rss_base = val & 0xffff; 3601 } 3602 3603 return (0); 3604 } 3605 3606 static int 3607 vcxgbe_attach(device_t dev) 3608 { 3609 struct vi_info *vi; 3610 struct port_info *pi; 3611 struct adapter *sc; 3612 int rc; 3613 3614 vi = device_get_softc(dev); 3615 pi = vi->pi; 3616 sc = pi->adapter; 3617 3618 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 3619 if (rc) 3620 return (rc); 3621 rc = alloc_extra_vi(sc, pi, vi); 3622 end_synchronized_op(sc, 0); 3623 if (rc) 3624 return (rc); 3625 3626 cxgbe_vi_attach(dev, vi); 3627 3628 return (0); 3629 } 3630 3631 static int 3632 vcxgbe_detach(device_t dev) 3633 { 3634 struct vi_info *vi; 3635 struct adapter *sc; 3636 3637 vi = device_get_softc(dev); 3638 sc = vi->adapter; 3639 3640 begin_vi_detach(sc, vi); 3641 cxgbe_vi_detach(vi); 3642 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3643 end_vi_detach(sc, vi); 3644 3645 return (0); 3646 } 3647 3648 static struct callout fatal_callout; 3649 static struct taskqueue *reset_tq; 3650 3651 static void 3652 delayed_panic(void *arg) 3653 { 3654 struct adapter *sc = arg; 3655 3656 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 3657 } 3658 3659 static void 3660 fatal_error_task(void *arg, int pending) 3661 { 3662 struct adapter *sc = arg; 3663 int rc; 3664 3665 if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) { 3666 dump_cim_regs(sc); 3667 dump_cimla(sc); 3668 dump_devlog(sc); 3669 } 3670 3671 if (t4_reset_on_fatal_err) { 3672 CH_ALERT(sc, "resetting adapter after fatal error.\n"); 3673 rc = reset_adapter(sc); 3674 if (rc == 0 && t4_panic_on_fatal_err) { 3675 CH_ALERT(sc, "reset was successful, " 3676 "system will NOT panic.\n"); 3677 return; 3678 } 3679 } 3680 3681 if (t4_panic_on_fatal_err) { 3682 CH_ALERT(sc, "panicking on fatal error (after 30s).\n"); 3683 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 3684 } 3685 } 3686 3687 void 3688 t4_fatal_err(struct adapter *sc, bool fw_error) 3689 { 3690 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 3691 3692 stop_adapter(sc); 3693 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR))) 3694 return; 3695 if (fw_error) { 3696 /* 3697 * We are here because of a firmware error/timeout and not 3698 * because of a hardware interrupt. It is possible (although 3699 * not very likely) that an error interrupt was also raised but 3700 * this thread ran first and inhibited t4_intr_err. We walk the 3701 * main INT_CAUSE registers here to make sure we haven't missed 3702 * anything interesting. 3703 */ 3704 t4_slow_intr_handler(sc, verbose); 3705 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 3706 } 3707 t4_report_fw_error(sc); 3708 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n", 3709 device_get_nameunit(sc->dev), fw_error); 3710 taskqueue_enqueue(reset_tq, &sc->fatal_error_task); 3711 } 3712 3713 void 3714 t4_add_adapter(struct adapter *sc) 3715 { 3716 sx_xlock(&t4_list_lock); 3717 SLIST_INSERT_HEAD(&t4_list, sc, link); 3718 sx_xunlock(&t4_list_lock); 3719 } 3720 3721 int 3722 t4_map_bars_0_and_4(struct adapter *sc) 3723 { 3724 sc->regs_rid = PCIR_BAR(0); 3725 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3726 &sc->regs_rid, RF_ACTIVE); 3727 if (sc->regs_res == NULL) { 3728 device_printf(sc->dev, "cannot map registers.\n"); 3729 return (ENXIO); 3730 } 3731 sc->bt = rman_get_bustag(sc->regs_res); 3732 sc->bh = rman_get_bushandle(sc->regs_res); 3733 sc->mmio_len = rman_get_size(sc->regs_res); 3734 setbit(&sc->doorbells, DOORBELL_KDB); 3735 3736 sc->msix_rid = PCIR_BAR(4); 3737 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3738 &sc->msix_rid, RF_ACTIVE); 3739 if (sc->msix_res == NULL) { 3740 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 3741 return (ENXIO); 3742 } 3743 3744 return (0); 3745 } 3746 3747 int 3748 t4_map_bar_2(struct adapter *sc) 3749 { 3750 3751 /* 3752 * T4: only iWARP driver uses the userspace doorbells. There is no need 3753 * to map it if RDMA is disabled. 3754 */ 3755 if (is_t4(sc) && sc->rdmacaps == 0) 3756 return (0); 3757 3758 sc->udbs_rid = PCIR_BAR(2); 3759 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3760 &sc->udbs_rid, RF_ACTIVE); 3761 if (sc->udbs_res == NULL) { 3762 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 3763 return (ENXIO); 3764 } 3765 sc->udbs_base = rman_get_virtual(sc->udbs_res); 3766 3767 if (chip_id(sc) >= CHELSIO_T5) { 3768 setbit(&sc->doorbells, DOORBELL_UDB); 3769 #if defined(__i386__) || defined(__amd64__) 3770 if (t5_write_combine) { 3771 int rc, mode; 3772 3773 /* 3774 * Enable write combining on BAR2. This is the 3775 * userspace doorbell BAR and is split into 128B 3776 * (UDBS_SEG_SIZE) doorbell regions, each associated 3777 * with an egress queue. The first 64B has the doorbell 3778 * and the second 64B can be used to submit a tx work 3779 * request with an implicit doorbell. 3780 */ 3781 3782 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 3783 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 3784 if (rc == 0) { 3785 clrbit(&sc->doorbells, DOORBELL_UDB); 3786 setbit(&sc->doorbells, DOORBELL_WCWR); 3787 setbit(&sc->doorbells, DOORBELL_UDBWC); 3788 } else { 3789 device_printf(sc->dev, 3790 "couldn't enable write combining: %d\n", 3791 rc); 3792 } 3793 3794 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 3795 t4_write_reg(sc, A_SGE_STAT_CFG, 3796 V_STATSOURCE_T5(7) | mode); 3797 } 3798 #endif 3799 } 3800 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 3801 3802 return (0); 3803 } 3804 3805 int 3806 t4_adj_doorbells(struct adapter *sc) 3807 { 3808 if ((sc->doorbells & t4_doorbells_allowed) != 0) { 3809 sc->doorbells &= t4_doorbells_allowed; 3810 return (0); 3811 } 3812 CH_ERR(sc, "No usable doorbell (available = 0x%x, allowed = 0x%x).\n", 3813 sc->doorbells, t4_doorbells_allowed); 3814 return (EINVAL); 3815 } 3816 3817 struct memwin_init { 3818 uint32_t base; 3819 uint32_t aperture; 3820 }; 3821 3822 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 3823 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3824 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3825 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 3826 }; 3827 3828 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 3829 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3830 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3831 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 3832 }; 3833 3834 static void 3835 setup_memwin(struct adapter *sc) 3836 { 3837 const struct memwin_init *mw_init; 3838 struct memwin *mw; 3839 int i; 3840 uint32_t bar0; 3841 3842 if (is_t4(sc)) { 3843 /* 3844 * Read low 32b of bar0 indirectly via the hardware backdoor 3845 * mechanism. Works from within PCI passthrough environments 3846 * too, where rman_get_start() can return a different value. We 3847 * need to program the T4 memory window decoders with the actual 3848 * addresses that will be coming across the PCIe link. 3849 */ 3850 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 3851 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 3852 3853 mw_init = &t4_memwin[0]; 3854 } else { 3855 /* T5+ use the relative offset inside the PCIe BAR */ 3856 bar0 = 0; 3857 3858 mw_init = &t5_memwin[0]; 3859 } 3860 3861 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 3862 if (!rw_initialized(&mw->mw_lock)) { 3863 rw_init(&mw->mw_lock, "memory window access"); 3864 mw->mw_base = mw_init->base; 3865 mw->mw_aperture = mw_init->aperture; 3866 mw->mw_curpos = 0; 3867 } 3868 t4_write_reg(sc, 3869 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 3870 (mw->mw_base + bar0) | V_BIR(0) | 3871 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 3872 rw_wlock(&mw->mw_lock); 3873 position_memwin(sc, i, mw->mw_curpos); 3874 rw_wunlock(&mw->mw_lock); 3875 } 3876 3877 /* flush */ 3878 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 3879 } 3880 3881 /* 3882 * Positions the memory window at the given address in the card's address space. 3883 * There are some alignment requirements and the actual position may be at an 3884 * address prior to the requested address. mw->mw_curpos always has the actual 3885 * position of the window. 3886 */ 3887 static void 3888 position_memwin(struct adapter *sc, int idx, uint32_t addr) 3889 { 3890 struct memwin *mw; 3891 uint32_t pf; 3892 uint32_t reg; 3893 3894 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3895 mw = &sc->memwin[idx]; 3896 rw_assert(&mw->mw_lock, RA_WLOCKED); 3897 3898 if (is_t4(sc)) { 3899 pf = 0; 3900 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 3901 } else { 3902 pf = V_PFNUM(sc->pf); 3903 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 3904 } 3905 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 3906 t4_write_reg(sc, reg, mw->mw_curpos | pf); 3907 t4_read_reg(sc, reg); /* flush */ 3908 } 3909 3910 int 3911 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 3912 int len, int rw) 3913 { 3914 struct memwin *mw; 3915 uint32_t mw_end, v; 3916 3917 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3918 3919 /* Memory can only be accessed in naturally aligned 4 byte units */ 3920 if (addr & 3 || len & 3 || len <= 0) 3921 return (EINVAL); 3922 3923 mw = &sc->memwin[idx]; 3924 while (len > 0) { 3925 rw_rlock(&mw->mw_lock); 3926 mw_end = mw->mw_curpos + mw->mw_aperture; 3927 if (addr >= mw_end || addr < mw->mw_curpos) { 3928 /* Will need to reposition the window */ 3929 if (!rw_try_upgrade(&mw->mw_lock)) { 3930 rw_runlock(&mw->mw_lock); 3931 rw_wlock(&mw->mw_lock); 3932 } 3933 rw_assert(&mw->mw_lock, RA_WLOCKED); 3934 position_memwin(sc, idx, addr); 3935 rw_downgrade(&mw->mw_lock); 3936 mw_end = mw->mw_curpos + mw->mw_aperture; 3937 } 3938 rw_assert(&mw->mw_lock, RA_RLOCKED); 3939 while (addr < mw_end && len > 0) { 3940 if (rw == 0) { 3941 v = t4_read_reg(sc, mw->mw_base + addr - 3942 mw->mw_curpos); 3943 *val++ = le32toh(v); 3944 } else { 3945 v = *val++; 3946 t4_write_reg(sc, mw->mw_base + addr - 3947 mw->mw_curpos, htole32(v)); 3948 } 3949 addr += 4; 3950 len -= 4; 3951 } 3952 rw_runlock(&mw->mw_lock); 3953 } 3954 3955 return (0); 3956 } 3957 3958 CTASSERT(M_TID_COOKIE == M_COOKIE); 3959 CTASSERT(MAX_ATIDS <= (M_TID_TID + 1)); 3960 3961 static void 3962 t4_init_atid_table(struct adapter *sc) 3963 { 3964 struct tid_info *t; 3965 int i; 3966 3967 t = &sc->tids; 3968 if (t->natids == 0) 3969 return; 3970 3971 MPASS(t->atid_tab == NULL); 3972 3973 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 3974 M_ZERO | M_WAITOK); 3975 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 3976 t->afree = t->atid_tab; 3977 t->atids_in_use = 0; 3978 t->atid_alloc_stopped = false; 3979 for (i = 1; i < t->natids; i++) 3980 t->atid_tab[i - 1].next = &t->atid_tab[i]; 3981 t->atid_tab[t->natids - 1].next = NULL; 3982 } 3983 3984 static void 3985 t4_free_atid_table(struct adapter *sc) 3986 { 3987 struct tid_info *t; 3988 3989 t = &sc->tids; 3990 3991 KASSERT(t->atids_in_use == 0, 3992 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 3993 3994 if (mtx_initialized(&t->atid_lock)) 3995 mtx_destroy(&t->atid_lock); 3996 free(t->atid_tab, M_CXGBE); 3997 t->atid_tab = NULL; 3998 } 3999 4000 static void 4001 stop_atid_allocator(struct adapter *sc) 4002 { 4003 struct tid_info *t = &sc->tids; 4004 4005 mtx_lock(&t->atid_lock); 4006 t->atid_alloc_stopped = true; 4007 mtx_unlock(&t->atid_lock); 4008 } 4009 4010 static void 4011 restart_atid_allocator(struct adapter *sc) 4012 { 4013 struct tid_info *t = &sc->tids; 4014 4015 mtx_lock(&t->atid_lock); 4016 KASSERT(t->atids_in_use == 0, 4017 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 4018 t->atid_alloc_stopped = false; 4019 mtx_unlock(&t->atid_lock); 4020 } 4021 4022 int 4023 alloc_atid(struct adapter *sc, void *ctx) 4024 { 4025 struct tid_info *t = &sc->tids; 4026 int atid = -1; 4027 4028 mtx_lock(&t->atid_lock); 4029 if (t->afree && !t->atid_alloc_stopped) { 4030 union aopen_entry *p = t->afree; 4031 4032 atid = p - t->atid_tab; 4033 MPASS(atid <= M_TID_TID); 4034 t->afree = p->next; 4035 p->data = ctx; 4036 t->atids_in_use++; 4037 } 4038 mtx_unlock(&t->atid_lock); 4039 return (atid); 4040 } 4041 4042 void * 4043 lookup_atid(struct adapter *sc, int atid) 4044 { 4045 struct tid_info *t = &sc->tids; 4046 4047 return (t->atid_tab[atid].data); 4048 } 4049 4050 void 4051 free_atid(struct adapter *sc, int atid) 4052 { 4053 struct tid_info *t = &sc->tids; 4054 union aopen_entry *p = &t->atid_tab[atid]; 4055 4056 mtx_lock(&t->atid_lock); 4057 p->next = t->afree; 4058 t->afree = p; 4059 t->atids_in_use--; 4060 mtx_unlock(&t->atid_lock); 4061 } 4062 4063 static void 4064 queue_tid_release(struct adapter *sc, int tid) 4065 { 4066 4067 CXGBE_UNIMPLEMENTED("deferred tid release"); 4068 } 4069 4070 void 4071 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 4072 { 4073 struct wrqe *wr; 4074 struct cpl_tid_release *req; 4075 4076 wr = alloc_wrqe(sizeof(*req), ctrlq); 4077 if (wr == NULL) { 4078 queue_tid_release(sc, tid); /* defer */ 4079 return; 4080 } 4081 req = wrtod(wr); 4082 4083 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 4084 4085 t4_wrq_tx(sc, wr); 4086 } 4087 4088 static int 4089 t4_range_cmp(const void *a, const void *b) 4090 { 4091 return ((const struct t4_range *)a)->start - 4092 ((const struct t4_range *)b)->start; 4093 } 4094 4095 /* 4096 * Verify that the memory range specified by the addr/len pair is valid within 4097 * the card's address space. 4098 */ 4099 static int 4100 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 4101 { 4102 struct t4_range mem_ranges[4], *r, *next; 4103 uint32_t em, addr_len; 4104 int i, n, remaining; 4105 4106 /* Memory can only be accessed in naturally aligned 4 byte units */ 4107 if (addr & 3 || len & 3 || len == 0) 4108 return (EINVAL); 4109 4110 /* Enabled memories */ 4111 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4112 4113 r = &mem_ranges[0]; 4114 n = 0; 4115 bzero(r, sizeof(mem_ranges)); 4116 if (em & F_EDRAM0_ENABLE) { 4117 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4118 r->size = G_EDRAM0_SIZE(addr_len) << 20; 4119 if (r->size > 0) { 4120 r->start = G_EDRAM0_BASE(addr_len) << 20; 4121 if (addr >= r->start && 4122 addr + len <= r->start + r->size) 4123 return (0); 4124 r++; 4125 n++; 4126 } 4127 } 4128 if (em & F_EDRAM1_ENABLE) { 4129 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4130 r->size = G_EDRAM1_SIZE(addr_len) << 20; 4131 if (r->size > 0) { 4132 r->start = G_EDRAM1_BASE(addr_len) << 20; 4133 if (addr >= r->start && 4134 addr + len <= r->start + r->size) 4135 return (0); 4136 r++; 4137 n++; 4138 } 4139 } 4140 if (em & F_EXT_MEM_ENABLE) { 4141 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4142 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 4143 if (r->size > 0) { 4144 r->start = G_EXT_MEM_BASE(addr_len) << 20; 4145 if (addr >= r->start && 4146 addr + len <= r->start + r->size) 4147 return (0); 4148 r++; 4149 n++; 4150 } 4151 } 4152 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 4153 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4154 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 4155 if (r->size > 0) { 4156 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 4157 if (addr >= r->start && 4158 addr + len <= r->start + r->size) 4159 return (0); 4160 r++; 4161 n++; 4162 } 4163 } 4164 MPASS(n <= nitems(mem_ranges)); 4165 4166 if (n > 1) { 4167 /* Sort and merge the ranges. */ 4168 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 4169 4170 /* Start from index 0 and examine the next n - 1 entries. */ 4171 r = &mem_ranges[0]; 4172 for (remaining = n - 1; remaining > 0; remaining--, r++) { 4173 4174 MPASS(r->size > 0); /* r is a valid entry. */ 4175 next = r + 1; 4176 MPASS(next->size > 0); /* and so is the next one. */ 4177 4178 while (r->start + r->size >= next->start) { 4179 /* Merge the next one into the current entry. */ 4180 r->size = max(r->start + r->size, 4181 next->start + next->size) - r->start; 4182 n--; /* One fewer entry in total. */ 4183 if (--remaining == 0) 4184 goto done; /* short circuit */ 4185 next++; 4186 } 4187 if (next != r + 1) { 4188 /* 4189 * Some entries were merged into r and next 4190 * points to the first valid entry that couldn't 4191 * be merged. 4192 */ 4193 MPASS(next->size > 0); /* must be valid */ 4194 memcpy(r + 1, next, remaining * sizeof(*r)); 4195 #ifdef INVARIANTS 4196 /* 4197 * This so that the foo->size assertion in the 4198 * next iteration of the loop do the right 4199 * thing for entries that were pulled up and are 4200 * no longer valid. 4201 */ 4202 MPASS(n < nitems(mem_ranges)); 4203 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 4204 sizeof(struct t4_range)); 4205 #endif 4206 } 4207 } 4208 done: 4209 /* Done merging the ranges. */ 4210 MPASS(n > 0); 4211 r = &mem_ranges[0]; 4212 for (i = 0; i < n; i++, r++) { 4213 if (addr >= r->start && 4214 addr + len <= r->start + r->size) 4215 return (0); 4216 } 4217 } 4218 4219 return (EFAULT); 4220 } 4221 4222 static int 4223 fwmtype_to_hwmtype(int mtype) 4224 { 4225 4226 switch (mtype) { 4227 case FW_MEMTYPE_EDC0: 4228 return (MEM_EDC0); 4229 case FW_MEMTYPE_EDC1: 4230 return (MEM_EDC1); 4231 case FW_MEMTYPE_EXTMEM: 4232 return (MEM_MC0); 4233 case FW_MEMTYPE_EXTMEM1: 4234 return (MEM_MC1); 4235 default: 4236 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 4237 } 4238 } 4239 4240 /* 4241 * Verify that the memory range specified by the memtype/offset/len pair is 4242 * valid and lies entirely within the memtype specified. The global address of 4243 * the start of the range is returned in addr. 4244 */ 4245 static int 4246 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 4247 uint32_t *addr) 4248 { 4249 uint32_t em, addr_len, maddr; 4250 4251 /* Memory can only be accessed in naturally aligned 4 byte units */ 4252 if (off & 3 || len & 3 || len == 0) 4253 return (EINVAL); 4254 4255 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4256 switch (fwmtype_to_hwmtype(mtype)) { 4257 case MEM_EDC0: 4258 if (!(em & F_EDRAM0_ENABLE)) 4259 return (EINVAL); 4260 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4261 maddr = G_EDRAM0_BASE(addr_len) << 20; 4262 break; 4263 case MEM_EDC1: 4264 if (!(em & F_EDRAM1_ENABLE)) 4265 return (EINVAL); 4266 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4267 maddr = G_EDRAM1_BASE(addr_len) << 20; 4268 break; 4269 case MEM_MC: 4270 if (!(em & F_EXT_MEM_ENABLE)) 4271 return (EINVAL); 4272 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4273 maddr = G_EXT_MEM_BASE(addr_len) << 20; 4274 break; 4275 case MEM_MC1: 4276 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 4277 return (EINVAL); 4278 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4279 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 4280 break; 4281 default: 4282 return (EINVAL); 4283 } 4284 4285 *addr = maddr + off; /* global address */ 4286 return (validate_mem_range(sc, *addr, len)); 4287 } 4288 4289 static int 4290 fixup_devlog_params(struct adapter *sc) 4291 { 4292 struct devlog_params *dparams = &sc->params.devlog; 4293 int rc; 4294 4295 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 4296 dparams->size, &dparams->addr); 4297 4298 return (rc); 4299 } 4300 4301 static void 4302 update_nirq(struct intrs_and_queues *iaq, int nports) 4303 { 4304 4305 iaq->nirq = T4_EXTRA_INTR; 4306 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq); 4307 iaq->nirq += nports * iaq->nofldrxq; 4308 iaq->nirq += nports * (iaq->num_vis - 1) * 4309 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 4310 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 4311 } 4312 4313 /* 4314 * Adjust requirements to fit the number of interrupts available. 4315 */ 4316 static void 4317 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 4318 int navail) 4319 { 4320 int old_nirq; 4321 const int nports = sc->params.nports; 4322 4323 MPASS(nports > 0); 4324 MPASS(navail > 0); 4325 4326 bzero(iaq, sizeof(*iaq)); 4327 iaq->intr_type = itype; 4328 iaq->num_vis = t4_num_vis; 4329 iaq->ntxq = t4_ntxq; 4330 iaq->ntxq_vi = t4_ntxq_vi; 4331 iaq->nrxq = t4_nrxq; 4332 iaq->nrxq_vi = t4_nrxq_vi; 4333 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4334 if (is_offload(sc) || is_ethoffload(sc)) { 4335 iaq->nofldtxq = t4_nofldtxq; 4336 iaq->nofldtxq_vi = t4_nofldtxq_vi; 4337 } 4338 #endif 4339 #ifdef TCP_OFFLOAD 4340 if (is_offload(sc)) { 4341 iaq->nofldrxq = t4_nofldrxq; 4342 iaq->nofldrxq_vi = t4_nofldrxq_vi; 4343 } 4344 #endif 4345 #ifdef DEV_NETMAP 4346 if (t4_native_netmap & NN_MAIN_VI) { 4347 iaq->nnmtxq = t4_nnmtxq; 4348 iaq->nnmrxq = t4_nnmrxq; 4349 } 4350 if (t4_native_netmap & NN_EXTRA_VI) { 4351 iaq->nnmtxq_vi = t4_nnmtxq_vi; 4352 iaq->nnmrxq_vi = t4_nnmrxq_vi; 4353 } 4354 #endif 4355 4356 update_nirq(iaq, nports); 4357 if (iaq->nirq <= navail && 4358 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4359 /* 4360 * This is the normal case -- there are enough interrupts for 4361 * everything. 4362 */ 4363 goto done; 4364 } 4365 4366 /* 4367 * If extra VIs have been configured try reducing their count and see if 4368 * that works. 4369 */ 4370 while (iaq->num_vis > 1) { 4371 iaq->num_vis--; 4372 update_nirq(iaq, nports); 4373 if (iaq->nirq <= navail && 4374 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4375 device_printf(sc->dev, "virtual interfaces per port " 4376 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 4377 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 4378 "itype %d, navail %u, nirq %d.\n", 4379 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 4380 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 4381 itype, navail, iaq->nirq); 4382 goto done; 4383 } 4384 } 4385 4386 /* 4387 * Extra VIs will not be created. Log a message if they were requested. 4388 */ 4389 MPASS(iaq->num_vis == 1); 4390 iaq->ntxq_vi = iaq->nrxq_vi = 0; 4391 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 4392 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 4393 if (iaq->num_vis != t4_num_vis) { 4394 device_printf(sc->dev, "extra virtual interfaces disabled. " 4395 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 4396 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 4397 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 4398 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 4399 } 4400 4401 /* 4402 * Keep reducing the number of NIC rx queues to the next lower power of 4403 * 2 (for even RSS distribution) and halving the TOE rx queues and see 4404 * if that works. 4405 */ 4406 do { 4407 if (iaq->nrxq > 1) { 4408 iaq->nrxq = rounddown_pow_of_two(iaq->nrxq - 1); 4409 if (iaq->nnmrxq > iaq->nrxq) 4410 iaq->nnmrxq = iaq->nrxq; 4411 } 4412 if (iaq->nofldrxq > 1) 4413 iaq->nofldrxq >>= 1; 4414 4415 old_nirq = iaq->nirq; 4416 update_nirq(iaq, nports); 4417 if (iaq->nirq <= navail && 4418 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4419 device_printf(sc->dev, "running with reduced number of " 4420 "rx queues because of shortage of interrupts. " 4421 "nrxq=%u, nofldrxq=%u. " 4422 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 4423 iaq->nofldrxq, itype, navail, iaq->nirq); 4424 goto done; 4425 } 4426 } while (old_nirq != iaq->nirq); 4427 4428 /* One interrupt for everything. Ugh. */ 4429 device_printf(sc->dev, "running with minimal number of queues. " 4430 "itype %d, navail %u.\n", itype, navail); 4431 iaq->nirq = 1; 4432 iaq->nrxq = 1; 4433 iaq->ntxq = 1; 4434 if (iaq->nofldrxq > 0) { 4435 iaq->nofldrxq = 1; 4436 iaq->nofldtxq = 1; 4437 } 4438 iaq->nnmtxq = 0; 4439 iaq->nnmrxq = 0; 4440 done: 4441 MPASS(iaq->num_vis > 0); 4442 if (iaq->num_vis > 1) { 4443 MPASS(iaq->nrxq_vi > 0); 4444 MPASS(iaq->ntxq_vi > 0); 4445 } 4446 MPASS(iaq->nirq > 0); 4447 MPASS(iaq->nrxq > 0); 4448 MPASS(iaq->ntxq > 0); 4449 if (itype == INTR_MSI) { 4450 MPASS(powerof2(iaq->nirq)); 4451 } 4452 } 4453 4454 static int 4455 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 4456 { 4457 int rc, itype, navail, nalloc; 4458 4459 for (itype = INTR_MSIX; itype; itype >>= 1) { 4460 4461 if ((itype & t4_intr_types) == 0) 4462 continue; /* not allowed */ 4463 4464 if (itype == INTR_MSIX) 4465 navail = pci_msix_count(sc->dev); 4466 else if (itype == INTR_MSI) 4467 navail = pci_msi_count(sc->dev); 4468 else 4469 navail = 1; 4470 restart: 4471 if (navail == 0) 4472 continue; 4473 4474 calculate_iaq(sc, iaq, itype, navail); 4475 nalloc = iaq->nirq; 4476 rc = 0; 4477 if (itype == INTR_MSIX) 4478 rc = pci_alloc_msix(sc->dev, &nalloc); 4479 else if (itype == INTR_MSI) 4480 rc = pci_alloc_msi(sc->dev, &nalloc); 4481 4482 if (rc == 0 && nalloc > 0) { 4483 if (nalloc == iaq->nirq) 4484 return (0); 4485 4486 /* 4487 * Didn't get the number requested. Use whatever number 4488 * the kernel is willing to allocate. 4489 */ 4490 device_printf(sc->dev, "fewer vectors than requested, " 4491 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 4492 itype, iaq->nirq, nalloc); 4493 pci_release_msi(sc->dev); 4494 navail = nalloc; 4495 goto restart; 4496 } 4497 4498 device_printf(sc->dev, 4499 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 4500 itype, rc, iaq->nirq, nalloc); 4501 } 4502 4503 device_printf(sc->dev, 4504 "failed to find a usable interrupt type. " 4505 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 4506 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 4507 4508 return (ENXIO); 4509 } 4510 4511 #define FW_VERSION(chip) ( \ 4512 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 4513 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 4514 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 4515 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 4516 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 4517 4518 /* Just enough of fw_hdr to cover all version info. */ 4519 struct fw_h { 4520 __u8 ver; 4521 __u8 chip; 4522 __be16 len512; 4523 __be32 fw_ver; 4524 __be32 tp_microcode_ver; 4525 __u8 intfver_nic; 4526 __u8 intfver_vnic; 4527 __u8 intfver_ofld; 4528 __u8 intfver_ri; 4529 __u8 intfver_iscsipdu; 4530 __u8 intfver_iscsi; 4531 __u8 intfver_fcoepdu; 4532 __u8 intfver_fcoe; 4533 }; 4534 /* Spot check a couple of fields. */ 4535 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 4536 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 4537 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 4538 4539 struct fw_info { 4540 uint8_t chip; 4541 char *kld_name; 4542 char *fw_mod_name; 4543 struct fw_h fw_h; 4544 } fw_info[] = { 4545 { 4546 .chip = CHELSIO_T4, 4547 .kld_name = "t4fw_cfg", 4548 .fw_mod_name = "t4fw", 4549 .fw_h = { 4550 .chip = FW_HDR_CHIP_T4, 4551 .fw_ver = htobe32(FW_VERSION(T4)), 4552 .intfver_nic = FW_INTFVER(T4, NIC), 4553 .intfver_vnic = FW_INTFVER(T4, VNIC), 4554 .intfver_ofld = FW_INTFVER(T4, OFLD), 4555 .intfver_ri = FW_INTFVER(T4, RI), 4556 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 4557 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4558 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 4559 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4560 }, 4561 }, { 4562 .chip = CHELSIO_T5, 4563 .kld_name = "t5fw_cfg", 4564 .fw_mod_name = "t5fw", 4565 .fw_h = { 4566 .chip = FW_HDR_CHIP_T5, 4567 .fw_ver = htobe32(FW_VERSION(T5)), 4568 .intfver_nic = FW_INTFVER(T5, NIC), 4569 .intfver_vnic = FW_INTFVER(T5, VNIC), 4570 .intfver_ofld = FW_INTFVER(T5, OFLD), 4571 .intfver_ri = FW_INTFVER(T5, RI), 4572 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 4573 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4574 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 4575 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4576 }, 4577 }, { 4578 .chip = CHELSIO_T6, 4579 .kld_name = "t6fw_cfg", 4580 .fw_mod_name = "t6fw", 4581 .fw_h = { 4582 .chip = FW_HDR_CHIP_T6, 4583 .fw_ver = htobe32(FW_VERSION(T6)), 4584 .intfver_nic = FW_INTFVER(T6, NIC), 4585 .intfver_vnic = FW_INTFVER(T6, VNIC), 4586 .intfver_ofld = FW_INTFVER(T6, OFLD), 4587 .intfver_ri = FW_INTFVER(T6, RI), 4588 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4589 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4590 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4591 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4592 }, 4593 } 4594 }; 4595 4596 static struct fw_info * 4597 find_fw_info(int chip) 4598 { 4599 int i; 4600 4601 for (i = 0; i < nitems(fw_info); i++) { 4602 if (fw_info[i].chip == chip) 4603 return (&fw_info[i]); 4604 } 4605 return (NULL); 4606 } 4607 4608 /* 4609 * Is the given firmware API compatible with the one the driver was compiled 4610 * with? 4611 */ 4612 static int 4613 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 4614 { 4615 4616 /* short circuit if it's the exact same firmware version */ 4617 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 4618 return (1); 4619 4620 /* 4621 * XXX: Is this too conservative? Perhaps I should limit this to the 4622 * features that are supported in the driver. 4623 */ 4624 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 4625 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 4626 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 4627 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 4628 return (1); 4629 #undef SAME_INTF 4630 4631 return (0); 4632 } 4633 4634 static int 4635 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 4636 const struct firmware **fw) 4637 { 4638 struct fw_info *fw_info; 4639 4640 *dcfg = NULL; 4641 if (fw != NULL) 4642 *fw = NULL; 4643 4644 fw_info = find_fw_info(chip_id(sc)); 4645 if (fw_info == NULL) { 4646 device_printf(sc->dev, 4647 "unable to look up firmware information for chip %d.\n", 4648 chip_id(sc)); 4649 return (EINVAL); 4650 } 4651 4652 *dcfg = firmware_get(fw_info->kld_name); 4653 if (*dcfg != NULL) { 4654 if (fw != NULL) 4655 *fw = firmware_get(fw_info->fw_mod_name); 4656 return (0); 4657 } 4658 4659 return (ENOENT); 4660 } 4661 4662 static void 4663 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 4664 const struct firmware *fw) 4665 { 4666 4667 if (fw != NULL) 4668 firmware_put(fw, FIRMWARE_UNLOAD); 4669 if (dcfg != NULL) 4670 firmware_put(dcfg, FIRMWARE_UNLOAD); 4671 } 4672 4673 /* 4674 * Return values: 4675 * 0 means no firmware install attempted. 4676 * ERESTART means a firmware install was attempted and was successful. 4677 * +ve errno means a firmware install was attempted but failed. 4678 */ 4679 static int 4680 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 4681 const struct fw_h *drv_fw, const char *reason, int *already) 4682 { 4683 const struct firmware *cfg, *fw; 4684 const uint32_t c = be32toh(card_fw->fw_ver); 4685 uint32_t d, k; 4686 int rc, fw_install; 4687 struct fw_h bundled_fw; 4688 bool load_attempted; 4689 4690 cfg = fw = NULL; 4691 load_attempted = false; 4692 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 4693 4694 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 4695 if (t4_fw_install < 0) { 4696 rc = load_fw_module(sc, &cfg, &fw); 4697 if (rc != 0 || fw == NULL) { 4698 device_printf(sc->dev, 4699 "failed to load firmware module: %d. cfg %p, fw %p;" 4700 " will use compiled-in firmware version for" 4701 "hw.cxgbe.fw_install checks.\n", 4702 rc, cfg, fw); 4703 } else { 4704 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 4705 } 4706 load_attempted = true; 4707 } 4708 d = be32toh(bundled_fw.fw_ver); 4709 4710 if (reason != NULL) 4711 goto install; 4712 4713 if ((sc->flags & FW_OK) == 0) { 4714 4715 if (c == 0xffffffff) { 4716 reason = "missing"; 4717 goto install; 4718 } 4719 4720 rc = 0; 4721 goto done; 4722 } 4723 4724 if (!fw_compatible(card_fw, &bundled_fw)) { 4725 reason = "incompatible or unusable"; 4726 goto install; 4727 } 4728 4729 if (d > c) { 4730 reason = "older than the version bundled with this driver"; 4731 goto install; 4732 } 4733 4734 if (fw_install == 2 && d != c) { 4735 reason = "different than the version bundled with this driver"; 4736 goto install; 4737 } 4738 4739 /* No reason to do anything to the firmware already on the card. */ 4740 rc = 0; 4741 goto done; 4742 4743 install: 4744 rc = 0; 4745 if ((*already)++) 4746 goto done; 4747 4748 if (fw_install == 0) { 4749 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4750 "but the driver is prohibited from installing a firmware " 4751 "on the card.\n", 4752 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4753 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4754 4755 goto done; 4756 } 4757 4758 /* 4759 * We'll attempt to install a firmware. Load the module first (if it 4760 * hasn't been loaded already). 4761 */ 4762 if (!load_attempted) { 4763 rc = load_fw_module(sc, &cfg, &fw); 4764 if (rc != 0 || fw == NULL) { 4765 device_printf(sc->dev, 4766 "failed to load firmware module: %d. cfg %p, fw %p\n", 4767 rc, cfg, fw); 4768 /* carry on */ 4769 } 4770 } 4771 if (fw == NULL) { 4772 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4773 "but the driver cannot take corrective action because it " 4774 "is unable to load the firmware module.\n", 4775 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4776 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4777 rc = sc->flags & FW_OK ? 0 : ENOENT; 4778 goto done; 4779 } 4780 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 4781 if (k != d) { 4782 MPASS(t4_fw_install > 0); 4783 device_printf(sc->dev, 4784 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 4785 "expecting (%u.%u.%u.%u) and will not be used.\n", 4786 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 4787 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 4788 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4789 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4790 rc = sc->flags & FW_OK ? 0 : EINVAL; 4791 goto done; 4792 } 4793 4794 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4795 "installing firmware %u.%u.%u.%u on card.\n", 4796 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4797 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 4798 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4799 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4800 4801 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 4802 if (rc != 0) { 4803 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 4804 } else { 4805 /* Installed successfully, update the cached header too. */ 4806 rc = ERESTART; 4807 memcpy(card_fw, fw->data, sizeof(*card_fw)); 4808 } 4809 done: 4810 unload_fw_module(sc, cfg, fw); 4811 4812 return (rc); 4813 } 4814 4815 /* 4816 * Establish contact with the firmware and attempt to become the master driver. 4817 * 4818 * A firmware will be installed to the card if needed (if the driver is allowed 4819 * to do so). 4820 */ 4821 static int 4822 contact_firmware(struct adapter *sc) 4823 { 4824 int rc, already = 0; 4825 enum dev_state state; 4826 struct fw_info *fw_info; 4827 struct fw_hdr *card_fw; /* fw on the card */ 4828 const struct fw_h *drv_fw; 4829 4830 fw_info = find_fw_info(chip_id(sc)); 4831 if (fw_info == NULL) { 4832 device_printf(sc->dev, 4833 "unable to look up firmware information for chip %d.\n", 4834 chip_id(sc)); 4835 return (EINVAL); 4836 } 4837 drv_fw = &fw_info->fw_h; 4838 4839 /* Read the header of the firmware on the card */ 4840 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 4841 restart: 4842 rc = -t4_get_fw_hdr(sc, card_fw); 4843 if (rc != 0) { 4844 device_printf(sc->dev, 4845 "unable to read firmware header from card's flash: %d\n", 4846 rc); 4847 goto done; 4848 } 4849 4850 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 4851 &already); 4852 if (rc == ERESTART) 4853 goto restart; 4854 if (rc != 0) 4855 goto done; 4856 4857 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 4858 if (rc < 0 || state == DEV_STATE_ERR) { 4859 rc = -rc; 4860 device_printf(sc->dev, 4861 "failed to connect to the firmware: %d, %d. " 4862 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4863 #if 0 4864 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4865 "not responding properly to HELLO", &already) == ERESTART) 4866 goto restart; 4867 #endif 4868 goto done; 4869 } 4870 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 4871 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 4872 4873 if (rc == sc->pf) { 4874 sc->flags |= MASTER_PF; 4875 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4876 NULL, &already); 4877 if (rc == ERESTART) 4878 rc = 0; 4879 else if (rc != 0) 4880 goto done; 4881 } else if (state == DEV_STATE_UNINIT) { 4882 /* 4883 * We didn't get to be the master so we definitely won't be 4884 * configuring the chip. It's a bug if someone else hasn't 4885 * configured it already. 4886 */ 4887 device_printf(sc->dev, "couldn't be master(%d), " 4888 "device not already initialized either(%d). " 4889 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4890 rc = EPROTO; 4891 goto done; 4892 } else { 4893 /* 4894 * Some other PF is the master and has configured the chip. 4895 * This is allowed but untested. 4896 */ 4897 device_printf(sc->dev, "PF%d is master, device state %d. " 4898 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4899 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 4900 sc->cfcsum = 0; 4901 rc = 0; 4902 } 4903 done: 4904 if (rc != 0 && sc->flags & FW_OK) { 4905 t4_fw_bye(sc, sc->mbox); 4906 sc->flags &= ~FW_OK; 4907 } 4908 free(card_fw, M_CXGBE); 4909 return (rc); 4910 } 4911 4912 static int 4913 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 4914 uint32_t mtype, uint32_t moff) 4915 { 4916 struct fw_info *fw_info; 4917 const struct firmware *dcfg, *rcfg = NULL; 4918 const uint32_t *cfdata; 4919 uint32_t cflen, addr; 4920 int rc; 4921 4922 load_fw_module(sc, &dcfg, NULL); 4923 4924 /* Card specific interpretation of "default". */ 4925 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4926 if (pci_get_device(sc->dev) == 0x440a) 4927 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 4928 if (is_fpga(sc)) 4929 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 4930 } 4931 4932 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4933 if (dcfg == NULL) { 4934 device_printf(sc->dev, 4935 "KLD with default config is not available.\n"); 4936 rc = ENOENT; 4937 goto done; 4938 } 4939 cfdata = dcfg->data; 4940 cflen = dcfg->datasize & ~3; 4941 } else { 4942 char s[32]; 4943 4944 fw_info = find_fw_info(chip_id(sc)); 4945 if (fw_info == NULL) { 4946 device_printf(sc->dev, 4947 "unable to look up firmware information for chip %d.\n", 4948 chip_id(sc)); 4949 rc = EINVAL; 4950 goto done; 4951 } 4952 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 4953 4954 rcfg = firmware_get(s); 4955 if (rcfg == NULL) { 4956 device_printf(sc->dev, 4957 "unable to load module \"%s\" for configuration " 4958 "profile \"%s\".\n", s, cfg_file); 4959 rc = ENOENT; 4960 goto done; 4961 } 4962 cfdata = rcfg->data; 4963 cflen = rcfg->datasize & ~3; 4964 } 4965 4966 if (cflen > FLASH_CFG_MAX_SIZE) { 4967 device_printf(sc->dev, 4968 "config file too long (%d, max allowed is %d).\n", 4969 cflen, FLASH_CFG_MAX_SIZE); 4970 rc = EINVAL; 4971 goto done; 4972 } 4973 4974 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 4975 if (rc != 0) { 4976 device_printf(sc->dev, 4977 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 4978 __func__, mtype, moff, cflen, rc); 4979 rc = EINVAL; 4980 goto done; 4981 } 4982 write_via_memwin(sc, 2, addr, cfdata, cflen); 4983 done: 4984 if (rcfg != NULL) 4985 firmware_put(rcfg, FIRMWARE_UNLOAD); 4986 unload_fw_module(sc, dcfg, NULL); 4987 return (rc); 4988 } 4989 4990 struct caps_allowed { 4991 uint16_t nbmcaps; 4992 uint16_t linkcaps; 4993 uint16_t switchcaps; 4994 uint16_t niccaps; 4995 uint16_t toecaps; 4996 uint16_t rdmacaps; 4997 uint16_t cryptocaps; 4998 uint16_t iscsicaps; 4999 uint16_t fcoecaps; 5000 }; 5001 5002 #define FW_PARAM_DEV(param) \ 5003 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 5004 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 5005 #define FW_PARAM_PFVF(param) \ 5006 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 5007 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 5008 5009 /* 5010 * Provide a configuration profile to the firmware and have it initialize the 5011 * chip accordingly. This may involve uploading a configuration file to the 5012 * card. 5013 */ 5014 static int 5015 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 5016 const struct caps_allowed *caps_allowed) 5017 { 5018 int rc; 5019 struct fw_caps_config_cmd caps; 5020 uint32_t mtype, moff, finicsum, cfcsum, param, val; 5021 5022 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 5023 if (rc != 0) { 5024 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 5025 return (rc); 5026 } 5027 5028 bzero(&caps, sizeof(caps)); 5029 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5030 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5031 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 5032 mtype = 0; 5033 moff = 0; 5034 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5035 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 5036 mtype = FW_MEMTYPE_FLASH; 5037 moff = t4_flash_cfg_addr(sc); 5038 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 5039 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 5040 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 5041 FW_LEN16(caps)); 5042 } else { 5043 /* 5044 * Ask the firmware where it wants us to upload the config file. 5045 */ 5046 param = FW_PARAM_DEV(CF); 5047 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5048 if (rc != 0) { 5049 /* No support for config file? Shouldn't happen. */ 5050 device_printf(sc->dev, 5051 "failed to query config file location: %d.\n", rc); 5052 goto done; 5053 } 5054 mtype = G_FW_PARAMS_PARAM_Y(val); 5055 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 5056 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 5057 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 5058 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 5059 FW_LEN16(caps)); 5060 5061 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 5062 if (rc != 0) { 5063 device_printf(sc->dev, 5064 "failed to upload config file to card: %d.\n", rc); 5065 goto done; 5066 } 5067 } 5068 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5069 if (rc != 0) { 5070 device_printf(sc->dev, "failed to pre-process config file: %d " 5071 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 5072 goto done; 5073 } 5074 5075 finicsum = be32toh(caps.finicsum); 5076 cfcsum = be32toh(caps.cfcsum); /* actual */ 5077 if (finicsum != cfcsum) { 5078 device_printf(sc->dev, 5079 "WARNING: config file checksum mismatch: %08x %08x\n", 5080 finicsum, cfcsum); 5081 } 5082 sc->cfcsum = cfcsum; 5083 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 5084 5085 /* 5086 * Let the firmware know what features will (not) be used so it can tune 5087 * things accordingly. 5088 */ 5089 #define LIMIT_CAPS(x) do { \ 5090 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 5091 } while (0) 5092 LIMIT_CAPS(nbm); 5093 LIMIT_CAPS(link); 5094 LIMIT_CAPS(switch); 5095 LIMIT_CAPS(nic); 5096 LIMIT_CAPS(toe); 5097 LIMIT_CAPS(rdma); 5098 LIMIT_CAPS(crypto); 5099 LIMIT_CAPS(iscsi); 5100 LIMIT_CAPS(fcoe); 5101 #undef LIMIT_CAPS 5102 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 5103 /* 5104 * TOE and hashfilters are mutually exclusive. It is a config 5105 * file or firmware bug if both are reported as available. Try 5106 * to cope with the situation in non-debug builds by disabling 5107 * TOE. 5108 */ 5109 MPASS(caps.toecaps == 0); 5110 5111 caps.toecaps = 0; 5112 caps.rdmacaps = 0; 5113 caps.iscsicaps = 0; 5114 } 5115 5116 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5117 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5118 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5119 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 5120 if (rc != 0) { 5121 device_printf(sc->dev, 5122 "failed to process config file: %d.\n", rc); 5123 goto done; 5124 } 5125 5126 t4_tweak_chip_settings(sc); 5127 set_params__pre_init(sc); 5128 5129 /* get basic stuff going */ 5130 rc = -t4_fw_initialize(sc, sc->mbox); 5131 if (rc != 0) { 5132 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 5133 goto done; 5134 } 5135 done: 5136 return (rc); 5137 } 5138 5139 /* 5140 * Partition chip resources for use between various PFs, VFs, etc. 5141 */ 5142 static int 5143 partition_resources(struct adapter *sc) 5144 { 5145 char cfg_file[sizeof(t4_cfg_file)]; 5146 struct caps_allowed caps_allowed; 5147 int rc; 5148 bool fallback; 5149 5150 /* Only the master driver gets to configure the chip resources. */ 5151 MPASS(sc->flags & MASTER_PF); 5152 5153 #define COPY_CAPS(x) do { \ 5154 caps_allowed.x##caps = t4_##x##caps_allowed; \ 5155 } while (0) 5156 bzero(&caps_allowed, sizeof(caps_allowed)); 5157 COPY_CAPS(nbm); 5158 COPY_CAPS(link); 5159 COPY_CAPS(switch); 5160 COPY_CAPS(nic); 5161 COPY_CAPS(toe); 5162 COPY_CAPS(rdma); 5163 COPY_CAPS(crypto); 5164 COPY_CAPS(iscsi); 5165 COPY_CAPS(fcoe); 5166 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 5167 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 5168 retry: 5169 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 5170 if (rc != 0 && fallback) { 5171 dump_devlog(sc); 5172 device_printf(sc->dev, 5173 "failed (%d) to configure card with \"%s\" profile, " 5174 "will fall back to a basic configuration and retry.\n", 5175 rc, cfg_file); 5176 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 5177 bzero(&caps_allowed, sizeof(caps_allowed)); 5178 COPY_CAPS(switch); 5179 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 5180 fallback = false; 5181 goto retry; 5182 } 5183 #undef COPY_CAPS 5184 return (rc); 5185 } 5186 5187 /* 5188 * Retrieve parameters that are needed (or nice to have) very early. 5189 */ 5190 static int 5191 get_params__pre_init(struct adapter *sc) 5192 { 5193 int rc; 5194 uint32_t param[2], val[2]; 5195 5196 t4_get_version_info(sc); 5197 5198 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 5199 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 5200 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 5201 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 5202 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 5203 5204 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 5205 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 5206 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 5207 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 5208 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 5209 5210 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 5211 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 5212 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 5213 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 5214 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 5215 5216 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 5217 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 5218 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 5219 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 5220 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 5221 5222 param[0] = FW_PARAM_DEV(PORTVEC); 5223 param[1] = FW_PARAM_DEV(CCLK); 5224 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5225 if (rc != 0) { 5226 device_printf(sc->dev, 5227 "failed to query parameters (pre_init): %d.\n", rc); 5228 return (rc); 5229 } 5230 5231 sc->params.portvec = val[0]; 5232 sc->params.nports = bitcount32(val[0]); 5233 sc->params.vpd.cclk = val[1]; 5234 5235 /* Read device log parameters. */ 5236 rc = -t4_init_devlog_params(sc, 1); 5237 if (rc == 0) 5238 fixup_devlog_params(sc); 5239 else { 5240 device_printf(sc->dev, 5241 "failed to get devlog parameters: %d.\n", rc); 5242 rc = 0; /* devlog isn't critical for device operation */ 5243 } 5244 5245 return (rc); 5246 } 5247 5248 /* 5249 * Any params that need to be set before FW_INITIALIZE. 5250 */ 5251 static int 5252 set_params__pre_init(struct adapter *sc) 5253 { 5254 int rc = 0; 5255 uint32_t param, val; 5256 5257 if (chip_id(sc) >= CHELSIO_T6) { 5258 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 5259 val = 1; 5260 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5261 /* firmwares < 1.20.1.0 do not have this param. */ 5262 if (rc == FW_EINVAL && 5263 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) { 5264 rc = 0; 5265 } 5266 if (rc != 0) { 5267 device_printf(sc->dev, 5268 "failed to enable high priority filters :%d.\n", 5269 rc); 5270 } 5271 5272 param = FW_PARAM_DEV(PPOD_EDRAM); 5273 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5274 if (rc == 0 && val == 1) { 5275 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, 5276 &val); 5277 if (rc != 0) { 5278 device_printf(sc->dev, 5279 "failed to set PPOD_EDRAM: %d.\n", rc); 5280 } 5281 } 5282 } 5283 5284 /* Enable opaque VIIDs with firmwares that support it. */ 5285 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 5286 val = 1; 5287 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5288 if (rc == 0 && val == 1) 5289 sc->params.viid_smt_extn_support = true; 5290 else 5291 sc->params.viid_smt_extn_support = false; 5292 5293 return (rc); 5294 } 5295 5296 /* 5297 * Retrieve various parameters that are of interest to the driver. The device 5298 * has been initialized by the firmware at this point. 5299 */ 5300 static int 5301 get_params__post_init(struct adapter *sc) 5302 { 5303 int rc; 5304 uint32_t param[7], val[7]; 5305 struct fw_caps_config_cmd caps; 5306 5307 param[0] = FW_PARAM_PFVF(IQFLINT_START); 5308 param[1] = FW_PARAM_PFVF(EQ_START); 5309 param[2] = FW_PARAM_PFVF(FILTER_START); 5310 param[3] = FW_PARAM_PFVF(FILTER_END); 5311 param[4] = FW_PARAM_PFVF(L2T_START); 5312 param[5] = FW_PARAM_PFVF(L2T_END); 5313 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5314 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5315 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 5316 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 5317 if (rc != 0) { 5318 device_printf(sc->dev, 5319 "failed to query parameters (post_init): %d.\n", rc); 5320 return (rc); 5321 } 5322 5323 sc->sge.iq_start = val[0]; 5324 sc->sge.eq_start = val[1]; 5325 if ((int)val[3] > (int)val[2]) { 5326 sc->tids.ftid_base = val[2]; 5327 sc->tids.ftid_end = val[3]; 5328 sc->tids.nftids = val[3] - val[2] + 1; 5329 } 5330 sc->vres.l2t.start = val[4]; 5331 sc->vres.l2t.size = val[5] - val[4] + 1; 5332 /* val[5] is the last hwidx and it must not collide with F_SYNC_WR */ 5333 if (sc->vres.l2t.size > 0) 5334 MPASS(fls(val[5]) <= S_SYNC_WR); 5335 sc->params.core_vdd = val[6]; 5336 5337 param[0] = FW_PARAM_PFVF(IQFLINT_END); 5338 param[1] = FW_PARAM_PFVF(EQ_END); 5339 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5340 if (rc != 0) { 5341 device_printf(sc->dev, 5342 "failed to query parameters (post_init2): %d.\n", rc); 5343 return (rc); 5344 } 5345 MPASS((int)val[0] >= sc->sge.iq_start); 5346 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1; 5347 MPASS((int)val[1] >= sc->sge.eq_start); 5348 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1; 5349 5350 if (chip_id(sc) >= CHELSIO_T6) { 5351 5352 sc->tids.tid_base = t4_read_reg(sc, 5353 A_LE_DB_ACTIVE_TABLE_START_INDEX); 5354 5355 param[0] = FW_PARAM_PFVF(HPFILTER_START); 5356 param[1] = FW_PARAM_PFVF(HPFILTER_END); 5357 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5358 if (rc != 0) { 5359 device_printf(sc->dev, 5360 "failed to query hpfilter parameters: %d.\n", rc); 5361 return (rc); 5362 } 5363 if ((int)val[1] > (int)val[0]) { 5364 sc->tids.hpftid_base = val[0]; 5365 sc->tids.hpftid_end = val[1]; 5366 sc->tids.nhpftids = val[1] - val[0] + 1; 5367 5368 /* 5369 * These should go off if the layout changes and the 5370 * driver needs to catch up. 5371 */ 5372 MPASS(sc->tids.hpftid_base == 0); 5373 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 5374 } 5375 5376 param[0] = FW_PARAM_PFVF(RAWF_START); 5377 param[1] = FW_PARAM_PFVF(RAWF_END); 5378 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5379 if (rc != 0) { 5380 device_printf(sc->dev, 5381 "failed to query rawf parameters: %d.\n", rc); 5382 return (rc); 5383 } 5384 if ((int)val[1] > (int)val[0]) { 5385 sc->rawf_base = val[0]; 5386 sc->nrawf = val[1] - val[0] + 1; 5387 } 5388 } 5389 5390 /* 5391 * The parameters that follow may not be available on all firmwares. We 5392 * query them individually rather than in a compound query because old 5393 * firmwares fail the entire query if an unknown parameter is queried. 5394 */ 5395 5396 /* 5397 * MPS buffer group configuration. 5398 */ 5399 param[0] = FW_PARAM_DEV(MPSBGMAP); 5400 val[0] = 0; 5401 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5402 if (rc == 0) 5403 sc->params.mps_bg_map = val[0]; 5404 else 5405 sc->params.mps_bg_map = UINT32_MAX; /* Not a legal value. */ 5406 5407 param[0] = FW_PARAM_DEV(TPCHMAP); 5408 val[0] = 0; 5409 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5410 if (rc == 0) 5411 sc->params.tp_ch_map = val[0]; 5412 else 5413 sc->params.tp_ch_map = UINT32_MAX; /* Not a legal value. */ 5414 5415 /* 5416 * Determine whether the firmware supports the filter2 work request. 5417 */ 5418 param[0] = FW_PARAM_DEV(FILTER2_WR); 5419 val[0] = 0; 5420 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5421 if (rc == 0) 5422 sc->params.filter2_wr_support = val[0] != 0; 5423 else 5424 sc->params.filter2_wr_support = 0; 5425 5426 /* 5427 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 5428 */ 5429 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 5430 val[0] = 0; 5431 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5432 if (rc == 0) 5433 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 5434 else 5435 sc->params.ulptx_memwrite_dsgl = false; 5436 5437 /* FW_RI_FR_NSMR_TPTE_WR support */ 5438 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 5439 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5440 if (rc == 0) 5441 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0; 5442 else 5443 sc->params.fr_nsmr_tpte_wr_support = false; 5444 5445 /* Support for 512 SGL entries per FR MR. */ 5446 param[0] = FW_PARAM_DEV(DEV_512SGL_MR); 5447 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5448 if (rc == 0) 5449 sc->params.dev_512sgl_mr = val[0] != 0; 5450 else 5451 sc->params.dev_512sgl_mr = false; 5452 5453 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 5454 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5455 if (rc == 0) 5456 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0]; 5457 else 5458 sc->params.max_pkts_per_eth_tx_pkts_wr = 15; 5459 5460 param[0] = FW_PARAM_DEV(NUM_TM_CLASS); 5461 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5462 if (rc == 0) { 5463 MPASS(val[0] > 0 && val[0] < 256); /* nsched_cls is 8b */ 5464 sc->params.nsched_cls = val[0]; 5465 } else 5466 sc->params.nsched_cls = sc->chip_params->nsched_cls; 5467 5468 /* get capabilites */ 5469 bzero(&caps, sizeof(caps)); 5470 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5471 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5472 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5473 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5474 if (rc != 0) { 5475 device_printf(sc->dev, 5476 "failed to get card capabilities: %d.\n", rc); 5477 return (rc); 5478 } 5479 5480 #define READ_CAPS(x) do { \ 5481 sc->x = htobe16(caps.x); \ 5482 } while (0) 5483 READ_CAPS(nbmcaps); 5484 READ_CAPS(linkcaps); 5485 READ_CAPS(switchcaps); 5486 READ_CAPS(niccaps); 5487 READ_CAPS(toecaps); 5488 READ_CAPS(rdmacaps); 5489 READ_CAPS(cryptocaps); 5490 READ_CAPS(iscsicaps); 5491 READ_CAPS(fcoecaps); 5492 5493 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 5494 MPASS(chip_id(sc) > CHELSIO_T4); 5495 MPASS(sc->toecaps == 0); 5496 sc->toecaps = 0; 5497 5498 param[0] = FW_PARAM_DEV(NTID); 5499 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5500 if (rc != 0) { 5501 device_printf(sc->dev, 5502 "failed to query HASHFILTER parameters: %d.\n", rc); 5503 return (rc); 5504 } 5505 sc->tids.ntids = val[0]; 5506 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5507 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5508 sc->tids.ntids -= sc->tids.nhpftids; 5509 } 5510 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5511 sc->params.hash_filter = 1; 5512 } 5513 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 5514 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 5515 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 5516 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5517 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 5518 if (rc != 0) { 5519 device_printf(sc->dev, 5520 "failed to query NIC parameters: %d.\n", rc); 5521 return (rc); 5522 } 5523 if ((int)val[1] > (int)val[0]) { 5524 sc->tids.etid_base = val[0]; 5525 sc->tids.etid_end = val[1]; 5526 sc->tids.netids = val[1] - val[0] + 1; 5527 sc->params.eo_wr_cred = val[2]; 5528 sc->params.ethoffload = 1; 5529 } 5530 } 5531 if (sc->toecaps) { 5532 /* query offload-related parameters */ 5533 param[0] = FW_PARAM_DEV(NTID); 5534 param[1] = FW_PARAM_PFVF(SERVER_START); 5535 param[2] = FW_PARAM_PFVF(SERVER_END); 5536 param[3] = FW_PARAM_PFVF(TDDP_START); 5537 param[4] = FW_PARAM_PFVF(TDDP_END); 5538 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5539 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5540 if (rc != 0) { 5541 device_printf(sc->dev, 5542 "failed to query TOE parameters: %d.\n", rc); 5543 return (rc); 5544 } 5545 sc->tids.ntids = val[0]; 5546 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5547 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5548 sc->tids.ntids -= sc->tids.nhpftids; 5549 } 5550 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5551 if ((int)val[2] > (int)val[1]) { 5552 sc->tids.stid_base = val[1]; 5553 sc->tids.nstids = val[2] - val[1] + 1; 5554 } 5555 sc->vres.ddp.start = val[3]; 5556 sc->vres.ddp.size = val[4] - val[3] + 1; 5557 sc->params.ofldq_wr_cred = val[5]; 5558 sc->params.offload = 1; 5559 } else { 5560 /* 5561 * The firmware attempts memfree TOE configuration for -SO cards 5562 * and will report toecaps=0 if it runs out of resources (this 5563 * depends on the config file). It may not report 0 for other 5564 * capabilities dependent on the TOE in this case. Set them to 5565 * 0 here so that the driver doesn't bother tracking resources 5566 * that will never be used. 5567 */ 5568 sc->iscsicaps = 0; 5569 sc->rdmacaps = 0; 5570 } 5571 if (sc->rdmacaps) { 5572 param[0] = FW_PARAM_PFVF(STAG_START); 5573 param[1] = FW_PARAM_PFVF(STAG_END); 5574 param[2] = FW_PARAM_PFVF(RQ_START); 5575 param[3] = FW_PARAM_PFVF(RQ_END); 5576 param[4] = FW_PARAM_PFVF(PBL_START); 5577 param[5] = FW_PARAM_PFVF(PBL_END); 5578 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5579 if (rc != 0) { 5580 device_printf(sc->dev, 5581 "failed to query RDMA parameters(1): %d.\n", rc); 5582 return (rc); 5583 } 5584 sc->vres.stag.start = val[0]; 5585 sc->vres.stag.size = val[1] - val[0] + 1; 5586 sc->vres.rq.start = val[2]; 5587 sc->vres.rq.size = val[3] - val[2] + 1; 5588 sc->vres.pbl.start = val[4]; 5589 sc->vres.pbl.size = val[5] - val[4] + 1; 5590 5591 param[0] = FW_PARAM_PFVF(SQRQ_START); 5592 param[1] = FW_PARAM_PFVF(SQRQ_END); 5593 param[2] = FW_PARAM_PFVF(CQ_START); 5594 param[3] = FW_PARAM_PFVF(CQ_END); 5595 param[4] = FW_PARAM_PFVF(OCQ_START); 5596 param[5] = FW_PARAM_PFVF(OCQ_END); 5597 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5598 if (rc != 0) { 5599 device_printf(sc->dev, 5600 "failed to query RDMA parameters(2): %d.\n", rc); 5601 return (rc); 5602 } 5603 sc->vres.qp.start = val[0]; 5604 sc->vres.qp.size = val[1] - val[0] + 1; 5605 sc->vres.cq.start = val[2]; 5606 sc->vres.cq.size = val[3] - val[2] + 1; 5607 sc->vres.ocq.start = val[4]; 5608 sc->vres.ocq.size = val[5] - val[4] + 1; 5609 5610 param[0] = FW_PARAM_PFVF(SRQ_START); 5611 param[1] = FW_PARAM_PFVF(SRQ_END); 5612 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 5613 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 5614 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 5615 if (rc != 0) { 5616 device_printf(sc->dev, 5617 "failed to query RDMA parameters(3): %d.\n", rc); 5618 return (rc); 5619 } 5620 sc->vres.srq.start = val[0]; 5621 sc->vres.srq.size = val[1] - val[0] + 1; 5622 sc->params.max_ordird_qp = val[2]; 5623 sc->params.max_ird_adapter = val[3]; 5624 } 5625 if (sc->iscsicaps) { 5626 param[0] = FW_PARAM_PFVF(ISCSI_START); 5627 param[1] = FW_PARAM_PFVF(ISCSI_END); 5628 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5629 if (rc != 0) { 5630 device_printf(sc->dev, 5631 "failed to query iSCSI parameters: %d.\n", rc); 5632 return (rc); 5633 } 5634 sc->vres.iscsi.start = val[0]; 5635 sc->vres.iscsi.size = val[1] - val[0] + 1; 5636 } 5637 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 5638 param[0] = FW_PARAM_PFVF(TLS_START); 5639 param[1] = FW_PARAM_PFVF(TLS_END); 5640 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5641 if (rc != 0) { 5642 device_printf(sc->dev, 5643 "failed to query TLS parameters: %d.\n", rc); 5644 return (rc); 5645 } 5646 sc->vres.key.start = val[0]; 5647 sc->vres.key.size = val[1] - val[0] + 1; 5648 } 5649 5650 /* 5651 * We've got the params we wanted to query directly from the firmware. 5652 * Grab some others via other means. 5653 */ 5654 t4_init_sge_params(sc); 5655 t4_init_tp_params(sc); 5656 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 5657 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 5658 5659 rc = t4_verify_chip_settings(sc); 5660 if (rc != 0) 5661 return (rc); 5662 t4_init_rx_buf_info(sc); 5663 5664 return (rc); 5665 } 5666 5667 #ifdef KERN_TLS 5668 static void 5669 ktls_tick(void *arg) 5670 { 5671 struct adapter *sc; 5672 uint32_t tstamp; 5673 5674 sc = arg; 5675 tstamp = tcp_ts_getticks(); 5676 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1); 5677 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31); 5678 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK); 5679 } 5680 5681 static int 5682 t6_config_kern_tls(struct adapter *sc, bool enable) 5683 { 5684 int rc; 5685 uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5686 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) | 5687 V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) | 5688 V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE); 5689 5690 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, ¶m); 5691 if (rc != 0) { 5692 CH_ERR(sc, "failed to %s NIC TLS: %d\n", 5693 enable ? "enable" : "disable", rc); 5694 return (rc); 5695 } 5696 5697 if (enable) { 5698 sc->flags |= KERN_TLS_ON; 5699 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc, 5700 C_HARDCLOCK); 5701 } else { 5702 sc->flags &= ~KERN_TLS_ON; 5703 callout_stop(&sc->ktls_tick); 5704 } 5705 5706 return (rc); 5707 } 5708 #endif 5709 5710 static int 5711 set_params__post_init(struct adapter *sc) 5712 { 5713 uint32_t mask, param, val; 5714 #ifdef TCP_OFFLOAD 5715 int i, v, shift; 5716 #endif 5717 5718 /* ask for encapsulated CPLs */ 5719 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 5720 val = 1; 5721 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5722 5723 /* Enable 32b port caps if the firmware supports it. */ 5724 param = FW_PARAM_PFVF(PORT_CAPS32); 5725 val = 1; 5726 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 5727 sc->params.port_caps32 = 1; 5728 5729 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 5730 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 5731 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 5732 V_MASKFILTER(val - 1)); 5733 5734 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER | 5735 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN | 5736 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5737 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM; 5738 val = 0; 5739 if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) { 5740 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE, 5741 F_ATTACKFILTERENABLE); 5742 val |= F_DROPERRORATTACK; 5743 } 5744 if (t4_drop_ip_fragments != 0) { 5745 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP, 5746 F_FRAGMENTDROP); 5747 val |= F_DROPERRORFRAG; 5748 } 5749 if (t4_drop_pkts_with_l2_errors != 0) 5750 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN; 5751 if (t4_drop_pkts_with_l3_errors != 0) { 5752 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN | 5753 F_DROPERRORCSUMIP; 5754 } 5755 if (t4_drop_pkts_with_l4_errors != 0) { 5756 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5757 F_DROPERRORTCPOPT | F_DROPERRORCSUM; 5758 } 5759 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val); 5760 5761 #ifdef TCP_OFFLOAD 5762 /* 5763 * Override the TOE timers with user provided tunables. This is not the 5764 * recommended way to change the timers (the firmware config file is) so 5765 * these tunables are not documented. 5766 * 5767 * All the timer tunables are in microseconds. 5768 */ 5769 if (t4_toe_keepalive_idle != 0) { 5770 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 5771 v &= M_KEEPALIVEIDLE; 5772 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 5773 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 5774 } 5775 if (t4_toe_keepalive_interval != 0) { 5776 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 5777 v &= M_KEEPALIVEINTVL; 5778 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 5779 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 5780 } 5781 if (t4_toe_keepalive_count != 0) { 5782 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 5783 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5784 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 5785 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 5786 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 5787 } 5788 if (t4_toe_rexmt_min != 0) { 5789 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 5790 v &= M_RXTMIN; 5791 t4_set_reg_field(sc, A_TP_RXT_MIN, 5792 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 5793 } 5794 if (t4_toe_rexmt_max != 0) { 5795 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 5796 v &= M_RXTMAX; 5797 t4_set_reg_field(sc, A_TP_RXT_MAX, 5798 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 5799 } 5800 if (t4_toe_rexmt_count != 0) { 5801 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 5802 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5803 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 5804 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 5805 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 5806 } 5807 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 5808 if (t4_toe_rexmt_backoff[i] != -1) { 5809 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 5810 shift = (i & 3) << 3; 5811 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 5812 M_TIMERBACKOFFINDEX0 << shift, v << shift); 5813 } 5814 } 5815 #endif 5816 5817 /* 5818 * Limit TOE connections to 2 reassembly "islands". This is 5819 * required to permit migrating TOE connections to either 5820 * ULP_MODE_TCPDDP or UPL_MODE_TLS. 5821 */ 5822 t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, V_PASSMODE(M_PASSMODE), 5823 V_PASSMODE(2)); 5824 5825 #ifdef KERN_TLS 5826 if (is_ktls(sc)) { 5827 sc->tlst.inline_keys = t4_tls_inline_keys; 5828 sc->tlst.combo_wrs = t4_tls_combo_wrs; 5829 if (t4_kern_tls != 0 && is_t6(sc)) 5830 t6_config_kern_tls(sc, true); 5831 } 5832 #endif 5833 return (0); 5834 } 5835 5836 #undef FW_PARAM_PFVF 5837 #undef FW_PARAM_DEV 5838 5839 static void 5840 t4_set_desc(struct adapter *sc) 5841 { 5842 struct adapter_params *p = &sc->params; 5843 5844 device_set_descf(sc->dev, "Chelsio %s", p->vpd.id); 5845 } 5846 5847 static inline void 5848 ifmedia_add4(struct ifmedia *ifm, int m) 5849 { 5850 5851 ifmedia_add(ifm, m, 0, NULL); 5852 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 5853 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 5854 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 5855 } 5856 5857 /* 5858 * This is the selected media, which is not quite the same as the active media. 5859 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 5860 * and active are not the same, and "media: Ethernet selected" otherwise. 5861 */ 5862 static void 5863 set_current_media(struct port_info *pi) 5864 { 5865 struct link_config *lc; 5866 struct ifmedia *ifm; 5867 int mword; 5868 u_int speed; 5869 5870 PORT_LOCK_ASSERT_OWNED(pi); 5871 5872 /* Leave current media alone if it's already set to IFM_NONE. */ 5873 ifm = &pi->media; 5874 if (ifm->ifm_cur != NULL && 5875 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 5876 return; 5877 5878 lc = &pi->link_cfg; 5879 if (lc->requested_aneg != AUTONEG_DISABLE && 5880 lc->pcaps & FW_PORT_CAP32_ANEG) { 5881 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 5882 return; 5883 } 5884 mword = IFM_ETHER | IFM_FDX; 5885 if (lc->requested_fc & PAUSE_TX) 5886 mword |= IFM_ETH_TXPAUSE; 5887 if (lc->requested_fc & PAUSE_RX) 5888 mword |= IFM_ETH_RXPAUSE; 5889 if (lc->requested_speed == 0) 5890 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 5891 else 5892 speed = lc->requested_speed; 5893 mword |= port_mword(pi, speed_to_fwcap(speed)); 5894 ifmedia_set(ifm, mword); 5895 } 5896 5897 /* 5898 * Returns true if the ifmedia list for the port cannot change. 5899 */ 5900 static bool 5901 fixed_ifmedia(struct port_info *pi) 5902 { 5903 5904 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 5905 pi->port_type == FW_PORT_TYPE_BT_XFI || 5906 pi->port_type == FW_PORT_TYPE_BT_XAUI || 5907 pi->port_type == FW_PORT_TYPE_KX4 || 5908 pi->port_type == FW_PORT_TYPE_KX || 5909 pi->port_type == FW_PORT_TYPE_KR || 5910 pi->port_type == FW_PORT_TYPE_BP_AP || 5911 pi->port_type == FW_PORT_TYPE_BP4_AP || 5912 pi->port_type == FW_PORT_TYPE_BP40_BA || 5913 pi->port_type == FW_PORT_TYPE_KR4_100G || 5914 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 5915 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 5916 } 5917 5918 static void 5919 build_medialist(struct port_info *pi) 5920 { 5921 uint32_t ss, speed; 5922 int unknown, mword, bit; 5923 struct link_config *lc; 5924 struct ifmedia *ifm; 5925 5926 PORT_LOCK_ASSERT_OWNED(pi); 5927 5928 if (pi->flags & FIXED_IFMEDIA) 5929 return; 5930 5931 /* 5932 * Rebuild the ifmedia list. 5933 */ 5934 ifm = &pi->media; 5935 ifmedia_removeall(ifm); 5936 lc = &pi->link_cfg; 5937 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */ 5938 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 5939 MPASS(ss != 0); 5940 no_media: 5941 MPASS(LIST_EMPTY(&ifm->ifm_list)); 5942 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 5943 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 5944 return; 5945 } 5946 5947 unknown = 0; 5948 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 5949 speed = 1 << bit; 5950 MPASS(speed & M_FW_PORT_CAP32_SPEED); 5951 if (ss & speed) { 5952 mword = port_mword(pi, speed); 5953 if (mword == IFM_NONE) { 5954 goto no_media; 5955 } else if (mword == IFM_UNKNOWN) 5956 unknown++; 5957 else 5958 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 5959 } 5960 } 5961 if (unknown > 0) /* Add one unknown for all unknown media types. */ 5962 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 5963 if (lc->pcaps & FW_PORT_CAP32_ANEG) 5964 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 5965 5966 set_current_media(pi); 5967 } 5968 5969 /* 5970 * Initialize the requested fields in the link config based on driver tunables. 5971 */ 5972 static void 5973 init_link_config(struct port_info *pi) 5974 { 5975 struct link_config *lc = &pi->link_cfg; 5976 5977 PORT_LOCK_ASSERT_OWNED(pi); 5978 5979 lc->requested_caps = 0; 5980 lc->requested_speed = 0; 5981 5982 if (t4_autoneg == 0) 5983 lc->requested_aneg = AUTONEG_DISABLE; 5984 else if (t4_autoneg == 1) 5985 lc->requested_aneg = AUTONEG_ENABLE; 5986 else 5987 lc->requested_aneg = AUTONEG_AUTO; 5988 5989 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 5990 PAUSE_AUTONEG); 5991 5992 if (t4_fec & FEC_AUTO) 5993 lc->requested_fec = FEC_AUTO; 5994 else if (t4_fec == 0) 5995 lc->requested_fec = FEC_NONE; 5996 else { 5997 /* -1 is handled by the FEC_AUTO block above and not here. */ 5998 lc->requested_fec = t4_fec & 5999 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE); 6000 if (lc->requested_fec == 0) 6001 lc->requested_fec = FEC_AUTO; 6002 } 6003 if (t4_force_fec < 0) 6004 lc->force_fec = -1; 6005 else if (t4_force_fec > 0) 6006 lc->force_fec = 1; 6007 else 6008 lc->force_fec = 0; 6009 } 6010 6011 /* 6012 * Makes sure that all requested settings comply with what's supported by the 6013 * port. Returns the number of settings that were invalid and had to be fixed. 6014 */ 6015 static int 6016 fixup_link_config(struct port_info *pi) 6017 { 6018 int n = 0; 6019 struct link_config *lc = &pi->link_cfg; 6020 uint32_t fwspeed; 6021 6022 PORT_LOCK_ASSERT_OWNED(pi); 6023 6024 /* Speed (when not autonegotiating) */ 6025 if (lc->requested_speed != 0) { 6026 fwspeed = speed_to_fwcap(lc->requested_speed); 6027 if ((fwspeed & lc->pcaps) == 0) { 6028 n++; 6029 lc->requested_speed = 0; 6030 } 6031 } 6032 6033 /* Link autonegotiation */ 6034 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 6035 lc->requested_aneg == AUTONEG_DISABLE || 6036 lc->requested_aneg == AUTONEG_AUTO); 6037 if (lc->requested_aneg == AUTONEG_ENABLE && 6038 !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 6039 n++; 6040 lc->requested_aneg = AUTONEG_AUTO; 6041 } 6042 6043 /* Flow control */ 6044 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 6045 if (lc->requested_fc & PAUSE_TX && 6046 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) { 6047 n++; 6048 lc->requested_fc &= ~PAUSE_TX; 6049 } 6050 if (lc->requested_fc & PAUSE_RX && 6051 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) { 6052 n++; 6053 lc->requested_fc &= ~PAUSE_RX; 6054 } 6055 if (!(lc->requested_fc & PAUSE_AUTONEG) && 6056 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) { 6057 n++; 6058 lc->requested_fc |= PAUSE_AUTONEG; 6059 } 6060 6061 /* FEC */ 6062 if ((lc->requested_fec & FEC_RS && 6063 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) || 6064 (lc->requested_fec & FEC_BASER_RS && 6065 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) { 6066 n++; 6067 lc->requested_fec = FEC_AUTO; 6068 } 6069 6070 return (n); 6071 } 6072 6073 /* 6074 * Apply the requested L1 settings, which are expected to be valid, to the 6075 * hardware. 6076 */ 6077 static int 6078 apply_link_config(struct port_info *pi) 6079 { 6080 struct adapter *sc = pi->adapter; 6081 struct link_config *lc = &pi->link_cfg; 6082 int rc; 6083 6084 #ifdef INVARIANTS 6085 ASSERT_SYNCHRONIZED_OP(sc); 6086 PORT_LOCK_ASSERT_OWNED(pi); 6087 6088 if (lc->requested_aneg == AUTONEG_ENABLE) 6089 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG); 6090 if (!(lc->requested_fc & PAUSE_AUTONEG)) 6091 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE); 6092 if (lc->requested_fc & PAUSE_TX) 6093 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX); 6094 if (lc->requested_fc & PAUSE_RX) 6095 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX); 6096 if (lc->requested_fec & FEC_RS) 6097 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS); 6098 if (lc->requested_fec & FEC_BASER_RS) 6099 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS); 6100 #endif 6101 if (!(sc->flags & IS_VF)) { 6102 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6103 if (rc != 0) { 6104 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 6105 return (rc); 6106 } 6107 } 6108 6109 /* 6110 * An L1_CFG will almost always result in a link-change event if the 6111 * link is up, and the driver will refresh the actual fec/fc/etc. when 6112 * the notification is processed. If the link is down then the actual 6113 * settings are meaningless. 6114 * 6115 * This takes care of the case where a change in the L1 settings may not 6116 * result in a notification. 6117 */ 6118 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 6119 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 6120 6121 return (0); 6122 } 6123 6124 #define FW_MAC_EXACT_CHUNK 7 6125 struct mcaddr_ctx { 6126 if_t ifp; 6127 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 6128 uint64_t hash; 6129 int i; 6130 int del; 6131 int rc; 6132 }; 6133 6134 static u_int 6135 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 6136 { 6137 struct mcaddr_ctx *ctx = arg; 6138 struct vi_info *vi = if_getsoftc(ctx->ifp); 6139 struct port_info *pi = vi->pi; 6140 struct adapter *sc = pi->adapter; 6141 6142 if (ctx->rc < 0) 6143 return (0); 6144 6145 ctx->mcaddr[ctx->i] = LLADDR(sdl); 6146 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i])); 6147 ctx->i++; 6148 6149 if (ctx->i == FW_MAC_EXACT_CHUNK) { 6150 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del, 6151 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0); 6152 if (ctx->rc < 0) { 6153 int j; 6154 6155 for (j = 0; j < ctx->i; j++) { 6156 if_printf(ctx->ifp, 6157 "failed to add mc address" 6158 " %02x:%02x:%02x:" 6159 "%02x:%02x:%02x rc=%d\n", 6160 ctx->mcaddr[j][0], ctx->mcaddr[j][1], 6161 ctx->mcaddr[j][2], ctx->mcaddr[j][3], 6162 ctx->mcaddr[j][4], ctx->mcaddr[j][5], 6163 -ctx->rc); 6164 } 6165 return (0); 6166 } 6167 ctx->del = 0; 6168 ctx->i = 0; 6169 } 6170 6171 return (1); 6172 } 6173 6174 /* 6175 * Program the port's XGMAC based on parameters in ifnet. The caller also 6176 * indicates which parameters should be programmed (the rest are left alone). 6177 */ 6178 int 6179 update_mac_settings(if_t ifp, int flags) 6180 { 6181 int rc = 0; 6182 struct vi_info *vi = if_getsoftc(ifp); 6183 struct port_info *pi = vi->pi; 6184 struct adapter *sc = pi->adapter; 6185 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 6186 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 6187 6188 ASSERT_SYNCHRONIZED_OP(sc); 6189 KASSERT(flags, ("%s: not told what to update.", __func__)); 6190 6191 if (flags & XGMAC_MTU) 6192 mtu = if_getmtu(ifp); 6193 6194 if (flags & XGMAC_PROMISC) 6195 promisc = if_getflags(ifp) & IFF_PROMISC ? 1 : 0; 6196 6197 if (flags & XGMAC_ALLMULTI) 6198 allmulti = if_getflags(ifp) & IFF_ALLMULTI ? 1 : 0; 6199 6200 if (flags & XGMAC_VLANEX) 6201 vlanex = if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING ? 1 : 0; 6202 6203 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 6204 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 6205 allmulti, 1, vlanex, false); 6206 if (rc) { 6207 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 6208 rc); 6209 return (rc); 6210 } 6211 } 6212 6213 if (flags & XGMAC_UCADDR) { 6214 uint8_t ucaddr[ETHER_ADDR_LEN]; 6215 6216 bcopy(if_getlladdr(ifp), ucaddr, sizeof(ucaddr)); 6217 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 6218 ucaddr, true, &vi->smt_idx); 6219 if (rc < 0) { 6220 rc = -rc; 6221 if_printf(ifp, "change_mac failed: %d\n", rc); 6222 return (rc); 6223 } else { 6224 vi->xact_addr_filt = rc; 6225 rc = 0; 6226 } 6227 } 6228 6229 if (flags & XGMAC_MCADDRS) { 6230 struct epoch_tracker et; 6231 struct mcaddr_ctx ctx; 6232 int j; 6233 6234 ctx.ifp = ifp; 6235 ctx.hash = 0; 6236 ctx.i = 0; 6237 ctx.del = 1; 6238 ctx.rc = 0; 6239 /* 6240 * Unlike other drivers, we accumulate list of pointers into 6241 * interface address lists and we need to keep it safe even 6242 * after if_foreach_llmaddr() returns, thus we must enter the 6243 * network epoch. 6244 */ 6245 NET_EPOCH_ENTER(et); 6246 if_foreach_llmaddr(ifp, add_maddr, &ctx); 6247 if (ctx.rc < 0) { 6248 NET_EPOCH_EXIT(et); 6249 rc = -ctx.rc; 6250 return (rc); 6251 } 6252 if (ctx.i > 0) { 6253 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 6254 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0); 6255 NET_EPOCH_EXIT(et); 6256 if (rc < 0) { 6257 rc = -rc; 6258 for (j = 0; j < ctx.i; j++) { 6259 if_printf(ifp, 6260 "failed to add mcast address" 6261 " %02x:%02x:%02x:" 6262 "%02x:%02x:%02x rc=%d\n", 6263 ctx.mcaddr[j][0], ctx.mcaddr[j][1], 6264 ctx.mcaddr[j][2], ctx.mcaddr[j][3], 6265 ctx.mcaddr[j][4], ctx.mcaddr[j][5], 6266 rc); 6267 } 6268 return (rc); 6269 } 6270 ctx.del = 0; 6271 } else 6272 NET_EPOCH_EXIT(et); 6273 6274 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0); 6275 if (rc != 0) 6276 if_printf(ifp, "failed to set mcast address hash: %d\n", 6277 rc); 6278 if (ctx.del == 0) { 6279 /* We clobbered the VXLAN entry if there was one. */ 6280 pi->vxlan_tcam_entry = false; 6281 } 6282 } 6283 6284 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 && 6285 pi->vxlan_tcam_entry == false) { 6286 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac, 6287 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 6288 true); 6289 if (rc < 0) { 6290 rc = -rc; 6291 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n", 6292 rc); 6293 } else { 6294 MPASS(rc == sc->rawf_base + pi->port_id); 6295 rc = 0; 6296 pi->vxlan_tcam_entry = true; 6297 } 6298 } 6299 6300 return (rc); 6301 } 6302 6303 /* 6304 * {begin|end}_synchronized_op must be called from the same thread. 6305 */ 6306 int 6307 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 6308 char *wmesg) 6309 { 6310 int rc, pri; 6311 6312 #ifdef WITNESS 6313 /* the caller thinks it's ok to sleep, but is it really? */ 6314 if (flags & SLEEP_OK) 6315 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 6316 "begin_synchronized_op"); 6317 #endif 6318 6319 if (INTR_OK) 6320 pri = PCATCH; 6321 else 6322 pri = 0; 6323 6324 ADAPTER_LOCK(sc); 6325 for (;;) { 6326 6327 if (vi && IS_DETACHING(vi)) { 6328 rc = ENXIO; 6329 goto done; 6330 } 6331 6332 if (!IS_BUSY(sc)) { 6333 rc = 0; 6334 break; 6335 } 6336 6337 if (!(flags & SLEEP_OK)) { 6338 rc = EBUSY; 6339 goto done; 6340 } 6341 6342 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 6343 rc = EINTR; 6344 goto done; 6345 } 6346 } 6347 6348 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 6349 SET_BUSY(sc); 6350 #ifdef INVARIANTS 6351 sc->last_op = wmesg; 6352 sc->last_op_thr = curthread; 6353 sc->last_op_flags = flags; 6354 #endif 6355 6356 done: 6357 if (!(flags & HOLD_LOCK) || rc) 6358 ADAPTER_UNLOCK(sc); 6359 6360 return (rc); 6361 } 6362 6363 /* 6364 * Tell if_ioctl and if_init that the VI is going away. This is 6365 * special variant of begin_synchronized_op and must be paired with a 6366 * call to end_vi_detach. 6367 */ 6368 void 6369 begin_vi_detach(struct adapter *sc, struct vi_info *vi) 6370 { 6371 ADAPTER_LOCK(sc); 6372 SET_DETACHING(vi); 6373 wakeup(&sc->flags); 6374 while (IS_BUSY(sc)) 6375 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 6376 SET_BUSY(sc); 6377 #ifdef INVARIANTS 6378 sc->last_op = "t4detach"; 6379 sc->last_op_thr = curthread; 6380 sc->last_op_flags = 0; 6381 #endif 6382 ADAPTER_UNLOCK(sc); 6383 } 6384 6385 void 6386 end_vi_detach(struct adapter *sc, struct vi_info *vi) 6387 { 6388 ADAPTER_LOCK(sc); 6389 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6390 CLR_BUSY(sc); 6391 CLR_DETACHING(vi); 6392 wakeup(&sc->flags); 6393 ADAPTER_UNLOCK(sc); 6394 } 6395 6396 /* 6397 * {begin|end}_synchronized_op must be called from the same thread. 6398 */ 6399 void 6400 end_synchronized_op(struct adapter *sc, int flags) 6401 { 6402 6403 if (flags & LOCK_HELD) 6404 ADAPTER_LOCK_ASSERT_OWNED(sc); 6405 else 6406 ADAPTER_LOCK(sc); 6407 6408 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6409 CLR_BUSY(sc); 6410 wakeup(&sc->flags); 6411 ADAPTER_UNLOCK(sc); 6412 } 6413 6414 static int 6415 cxgbe_init_synchronized(struct vi_info *vi) 6416 { 6417 struct port_info *pi = vi->pi; 6418 struct adapter *sc = pi->adapter; 6419 if_t ifp = vi->ifp; 6420 int rc = 0, i; 6421 struct sge_txq *txq; 6422 6423 ASSERT_SYNCHRONIZED_OP(sc); 6424 6425 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6426 return (0); /* already running */ 6427 6428 if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0)) 6429 return (rc); /* error message displayed already */ 6430 6431 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 6432 return (rc); /* error message displayed already */ 6433 6434 rc = update_mac_settings(ifp, XGMAC_ALL); 6435 if (rc) 6436 goto done; /* error message displayed already */ 6437 6438 PORT_LOCK(pi); 6439 if (pi->up_vis == 0) { 6440 t4_update_port_info(pi); 6441 fixup_link_config(pi); 6442 build_medialist(pi); 6443 apply_link_config(pi); 6444 } 6445 6446 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 6447 if (rc != 0) { 6448 if_printf(ifp, "enable_vi failed: %d\n", rc); 6449 PORT_UNLOCK(pi); 6450 goto done; 6451 } 6452 6453 /* 6454 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 6455 * if this changes. 6456 */ 6457 6458 for_each_txq(vi, i, txq) { 6459 TXQ_LOCK(txq); 6460 txq->eq.flags |= EQ_ENABLED; 6461 TXQ_UNLOCK(txq); 6462 } 6463 6464 /* 6465 * The first iq of the first port to come up is used for tracing. 6466 */ 6467 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 6468 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 6469 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 6470 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 6471 V_QUEUENUMBER(sc->traceq)); 6472 pi->flags |= HAS_TRACEQ; 6473 } 6474 6475 /* all ok */ 6476 pi->up_vis++; 6477 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 6478 if (pi->link_cfg.link_ok) 6479 t4_os_link_changed(pi); 6480 PORT_UNLOCK(pi); 6481 6482 mtx_lock(&vi->tick_mtx); 6483 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 6484 callout_reset(&vi->tick, hz, vi_tick, vi); 6485 else 6486 callout_reset(&vi->tick, hz, cxgbe_tick, vi); 6487 mtx_unlock(&vi->tick_mtx); 6488 done: 6489 if (rc != 0) 6490 cxgbe_uninit_synchronized(vi); 6491 6492 return (rc); 6493 } 6494 6495 /* 6496 * Idempotent. 6497 */ 6498 static int 6499 cxgbe_uninit_synchronized(struct vi_info *vi) 6500 { 6501 struct port_info *pi = vi->pi; 6502 struct adapter *sc = pi->adapter; 6503 if_t ifp = vi->ifp; 6504 int rc, i; 6505 struct sge_txq *txq; 6506 6507 ASSERT_SYNCHRONIZED_OP(sc); 6508 6509 if (!(vi->flags & VI_INIT_DONE)) { 6510 if (__predict_false(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6511 KASSERT(0, ("uninited VI is running")); 6512 if_printf(ifp, "uninited VI with running ifnet. " 6513 "vi->flags 0x%016lx, if_flags 0x%08x, " 6514 "if_drv_flags 0x%08x\n", vi->flags, if_getflags(ifp), 6515 if_getdrvflags(ifp)); 6516 } 6517 return (0); 6518 } 6519 6520 /* 6521 * Disable the VI so that all its data in either direction is discarded 6522 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 6523 * tick) intact as the TP can deliver negative advice or data that it's 6524 * holding in its RAM (for an offloaded connection) even after the VI is 6525 * disabled. 6526 */ 6527 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 6528 if (rc) { 6529 if_printf(ifp, "disable_vi failed: %d\n", rc); 6530 return (rc); 6531 } 6532 6533 for_each_txq(vi, i, txq) { 6534 TXQ_LOCK(txq); 6535 txq->eq.flags &= ~EQ_ENABLED; 6536 TXQ_UNLOCK(txq); 6537 } 6538 6539 mtx_lock(&vi->tick_mtx); 6540 callout_stop(&vi->tick); 6541 mtx_unlock(&vi->tick_mtx); 6542 6543 PORT_LOCK(pi); 6544 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6545 PORT_UNLOCK(pi); 6546 return (0); 6547 } 6548 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 6549 pi->up_vis--; 6550 if (pi->up_vis > 0) { 6551 PORT_UNLOCK(pi); 6552 return (0); 6553 } 6554 6555 pi->link_cfg.link_ok = false; 6556 pi->link_cfg.speed = 0; 6557 pi->link_cfg.link_down_rc = 255; 6558 t4_os_link_changed(pi); 6559 PORT_UNLOCK(pi); 6560 6561 return (0); 6562 } 6563 6564 /* 6565 * It is ok for this function to fail midway and return right away. t4_detach 6566 * will walk the entire sc->irq list and clean up whatever is valid. 6567 */ 6568 int 6569 t4_setup_intr_handlers(struct adapter *sc) 6570 { 6571 int rc, rid, p, q, v; 6572 char s[8]; 6573 struct irq *irq; 6574 struct port_info *pi; 6575 struct vi_info *vi; 6576 struct sge *sge = &sc->sge; 6577 struct sge_rxq *rxq; 6578 #ifdef TCP_OFFLOAD 6579 struct sge_ofld_rxq *ofld_rxq; 6580 #endif 6581 #ifdef DEV_NETMAP 6582 struct sge_nm_rxq *nm_rxq; 6583 #endif 6584 #ifdef RSS 6585 int nbuckets = rss_getnumbuckets(); 6586 #endif 6587 6588 /* 6589 * Setup interrupts. 6590 */ 6591 irq = &sc->irq[0]; 6592 rid = sc->intr_type == INTR_INTX ? 0 : 1; 6593 if (forwarding_intr_to_fwq(sc)) 6594 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 6595 6596 /* Multiple interrupts. */ 6597 if (sc->flags & IS_VF) 6598 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 6599 ("%s: too few intr.", __func__)); 6600 else 6601 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 6602 ("%s: too few intr.", __func__)); 6603 6604 /* The first one is always error intr on PFs */ 6605 if (!(sc->flags & IS_VF)) { 6606 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 6607 if (rc != 0) 6608 return (rc); 6609 irq++; 6610 rid++; 6611 } 6612 6613 /* The second one is always the firmware event queue (first on VFs) */ 6614 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 6615 if (rc != 0) 6616 return (rc); 6617 irq++; 6618 rid++; 6619 6620 for_each_port(sc, p) { 6621 pi = sc->port[p]; 6622 for_each_vi(pi, v, vi) { 6623 vi->first_intr = rid - 1; 6624 6625 if (vi->nnmrxq > 0) { 6626 int n = max(vi->nrxq, vi->nnmrxq); 6627 6628 rxq = &sge->rxq[vi->first_rxq]; 6629 #ifdef DEV_NETMAP 6630 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 6631 #endif 6632 for (q = 0; q < n; q++) { 6633 snprintf(s, sizeof(s), "%x%c%x", p, 6634 'a' + v, q); 6635 if (q < vi->nrxq) 6636 irq->rxq = rxq++; 6637 #ifdef DEV_NETMAP 6638 if (q < vi->nnmrxq) 6639 irq->nm_rxq = nm_rxq++; 6640 6641 if (irq->nm_rxq != NULL && 6642 irq->rxq == NULL) { 6643 /* Netmap rx only */ 6644 rc = t4_alloc_irq(sc, irq, rid, 6645 t4_nm_intr, irq->nm_rxq, s); 6646 } 6647 if (irq->nm_rxq != NULL && 6648 irq->rxq != NULL) { 6649 /* NIC and Netmap rx */ 6650 rc = t4_alloc_irq(sc, irq, rid, 6651 t4_vi_intr, irq, s); 6652 } 6653 #endif 6654 if (irq->rxq != NULL && 6655 irq->nm_rxq == NULL) { 6656 /* NIC rx only */ 6657 rc = t4_alloc_irq(sc, irq, rid, 6658 t4_intr, irq->rxq, s); 6659 } 6660 if (rc != 0) 6661 return (rc); 6662 #ifdef RSS 6663 if (q < vi->nrxq) { 6664 bus_bind_intr(sc->dev, irq->res, 6665 rss_getcpu(q % nbuckets)); 6666 } 6667 #endif 6668 irq++; 6669 rid++; 6670 vi->nintr++; 6671 } 6672 } else { 6673 for_each_rxq(vi, q, rxq) { 6674 snprintf(s, sizeof(s), "%x%c%x", p, 6675 'a' + v, q); 6676 rc = t4_alloc_irq(sc, irq, rid, 6677 t4_intr, rxq, s); 6678 if (rc != 0) 6679 return (rc); 6680 #ifdef RSS 6681 bus_bind_intr(sc->dev, irq->res, 6682 rss_getcpu(q % nbuckets)); 6683 #endif 6684 irq++; 6685 rid++; 6686 vi->nintr++; 6687 } 6688 } 6689 #ifdef TCP_OFFLOAD 6690 for_each_ofld_rxq(vi, q, ofld_rxq) { 6691 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 6692 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 6693 ofld_rxq, s); 6694 if (rc != 0) 6695 return (rc); 6696 irq++; 6697 rid++; 6698 vi->nintr++; 6699 } 6700 #endif 6701 } 6702 } 6703 MPASS(irq == &sc->irq[sc->intr_count]); 6704 6705 return (0); 6706 } 6707 6708 static void 6709 write_global_rss_key(struct adapter *sc) 6710 { 6711 #ifdef RSS 6712 int i; 6713 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6714 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6715 6716 CTASSERT(RSS_KEYSIZE == 40); 6717 6718 rss_getkey((void *)&raw_rss_key[0]); 6719 for (i = 0; i < nitems(rss_key); i++) { 6720 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 6721 } 6722 t4_write_rss_key(sc, &rss_key[0], -1, 1); 6723 #endif 6724 } 6725 6726 /* 6727 * Idempotent. 6728 */ 6729 static int 6730 adapter_full_init(struct adapter *sc) 6731 { 6732 int rc, i; 6733 6734 ASSERT_SYNCHRONIZED_OP(sc); 6735 6736 /* 6737 * queues that belong to the adapter (not any particular port). 6738 */ 6739 rc = t4_setup_adapter_queues(sc); 6740 if (rc != 0) 6741 return (rc); 6742 6743 MPASS(sc->params.nports <= nitems(sc->tq)); 6744 for (i = 0; i < sc->params.nports; i++) { 6745 if (sc->tq[i] != NULL) 6746 continue; 6747 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 6748 taskqueue_thread_enqueue, &sc->tq[i]); 6749 if (sc->tq[i] == NULL) { 6750 CH_ERR(sc, "failed to allocate task queue %d\n", i); 6751 return (ENOMEM); 6752 } 6753 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 6754 device_get_nameunit(sc->dev), i); 6755 } 6756 6757 if (!(sc->flags & IS_VF)) { 6758 write_global_rss_key(sc); 6759 t4_intr_enable(sc); 6760 } 6761 return (0); 6762 } 6763 6764 int 6765 adapter_init(struct adapter *sc) 6766 { 6767 int rc; 6768 6769 ASSERT_SYNCHRONIZED_OP(sc); 6770 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 6771 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 6772 ("%s: FULL_INIT_DONE already", __func__)); 6773 6774 rc = adapter_full_init(sc); 6775 if (rc != 0) 6776 adapter_full_uninit(sc); 6777 else 6778 sc->flags |= FULL_INIT_DONE; 6779 6780 return (rc); 6781 } 6782 6783 /* 6784 * Idempotent. 6785 */ 6786 static void 6787 adapter_full_uninit(struct adapter *sc) 6788 { 6789 int i; 6790 6791 t4_teardown_adapter_queues(sc); 6792 6793 for (i = 0; i < nitems(sc->tq); i++) { 6794 if (sc->tq[i] == NULL) 6795 continue; 6796 taskqueue_free(sc->tq[i]); 6797 sc->tq[i] = NULL; 6798 } 6799 6800 sc->flags &= ~FULL_INIT_DONE; 6801 } 6802 6803 #ifdef RSS 6804 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 6805 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 6806 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 6807 RSS_HASHTYPE_RSS_UDP_IPV6) 6808 6809 /* Translates kernel hash types to hardware. */ 6810 static int 6811 hashconfig_to_hashen(int hashconfig) 6812 { 6813 int hashen = 0; 6814 6815 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 6816 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 6817 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 6818 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 6819 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 6820 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6821 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6822 } 6823 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 6824 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6825 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6826 } 6827 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 6828 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6829 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 6830 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6831 6832 return (hashen); 6833 } 6834 6835 /* Translates hardware hash types to kernel. */ 6836 static int 6837 hashen_to_hashconfig(int hashen) 6838 { 6839 int hashconfig = 0; 6840 6841 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 6842 /* 6843 * If UDP hashing was enabled it must have been enabled for 6844 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 6845 * enabling any 4-tuple hash is nonsense configuration. 6846 */ 6847 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6848 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 6849 6850 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6851 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 6852 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6853 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 6854 } 6855 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6856 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 6857 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6858 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 6859 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6860 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 6861 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6862 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 6863 6864 return (hashconfig); 6865 } 6866 #endif 6867 6868 /* 6869 * Idempotent. 6870 */ 6871 static int 6872 vi_full_init(struct vi_info *vi) 6873 { 6874 struct adapter *sc = vi->adapter; 6875 struct sge_rxq *rxq; 6876 int rc, i, j; 6877 #ifdef RSS 6878 int nbuckets = rss_getnumbuckets(); 6879 int hashconfig = rss_gethashconfig(); 6880 int extra; 6881 #endif 6882 6883 ASSERT_SYNCHRONIZED_OP(sc); 6884 6885 /* 6886 * Allocate tx/rx/fl queues for this VI. 6887 */ 6888 rc = t4_setup_vi_queues(vi); 6889 if (rc != 0) 6890 return (rc); 6891 6892 /* 6893 * Setup RSS for this VI. Save a copy of the RSS table for later use. 6894 */ 6895 if (vi->nrxq > vi->rss_size) { 6896 CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); " 6897 "some queues will never receive traffic.\n", vi->nrxq, 6898 vi->rss_size); 6899 } else if (vi->rss_size % vi->nrxq) { 6900 CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); " 6901 "expect uneven traffic distribution.\n", vi->nrxq, 6902 vi->rss_size); 6903 } 6904 #ifdef RSS 6905 if (vi->nrxq != nbuckets) { 6906 CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);" 6907 "performance will be impacted.\n", vi->nrxq, nbuckets); 6908 } 6909 #endif 6910 if (vi->rss == NULL) 6911 vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE, 6912 M_ZERO | M_WAITOK); 6913 for (i = 0; i < vi->rss_size;) { 6914 #ifdef RSS 6915 j = rss_get_indirection_to_bucket(i); 6916 j %= vi->nrxq; 6917 rxq = &sc->sge.rxq[vi->first_rxq + j]; 6918 vi->rss[i++] = rxq->iq.abs_id; 6919 #else 6920 for_each_rxq(vi, j, rxq) { 6921 vi->rss[i++] = rxq->iq.abs_id; 6922 if (i == vi->rss_size) 6923 break; 6924 } 6925 #endif 6926 } 6927 6928 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 6929 vi->rss, vi->rss_size); 6930 if (rc != 0) { 6931 CH_ERR(vi, "rss_config failed: %d\n", rc); 6932 return (rc); 6933 } 6934 6935 #ifdef RSS 6936 vi->hashen = hashconfig_to_hashen(hashconfig); 6937 6938 /* 6939 * We may have had to enable some hashes even though the global config 6940 * wants them disabled. This is a potential problem that must be 6941 * reported to the user. 6942 */ 6943 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 6944 6945 /* 6946 * If we consider only the supported hash types, then the enabled hashes 6947 * are a superset of the requested hashes. In other words, there cannot 6948 * be any supported hash that was requested but not enabled, but there 6949 * can be hashes that were not requested but had to be enabled. 6950 */ 6951 extra &= SUPPORTED_RSS_HASHTYPES; 6952 MPASS((extra & hashconfig) == 0); 6953 6954 if (extra) { 6955 CH_ALERT(vi, 6956 "global RSS config (0x%x) cannot be accommodated.\n", 6957 hashconfig); 6958 } 6959 if (extra & RSS_HASHTYPE_RSS_IPV4) 6960 CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n"); 6961 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 6962 CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n"); 6963 if (extra & RSS_HASHTYPE_RSS_IPV6) 6964 CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n"); 6965 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 6966 CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n"); 6967 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 6968 CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n"); 6969 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 6970 CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n"); 6971 #else 6972 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 6973 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 6974 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6975 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 6976 #endif 6977 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 6978 0, 0); 6979 if (rc != 0) { 6980 CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc); 6981 return (rc); 6982 } 6983 6984 return (0); 6985 } 6986 6987 int 6988 vi_init(struct vi_info *vi) 6989 { 6990 int rc; 6991 6992 ASSERT_SYNCHRONIZED_OP(vi->adapter); 6993 KASSERT((vi->flags & VI_INIT_DONE) == 0, 6994 ("%s: VI_INIT_DONE already", __func__)); 6995 6996 rc = vi_full_init(vi); 6997 if (rc != 0) 6998 vi_full_uninit(vi); 6999 else 7000 vi->flags |= VI_INIT_DONE; 7001 7002 return (rc); 7003 } 7004 7005 /* 7006 * Idempotent. 7007 */ 7008 static void 7009 vi_full_uninit(struct vi_info *vi) 7010 { 7011 7012 if (vi->flags & VI_INIT_DONE) { 7013 quiesce_vi(vi); 7014 free(vi->rss, M_CXGBE); 7015 free(vi->nm_rss, M_CXGBE); 7016 } 7017 7018 t4_teardown_vi_queues(vi); 7019 vi->flags &= ~VI_INIT_DONE; 7020 } 7021 7022 static void 7023 quiesce_txq(struct sge_txq *txq) 7024 { 7025 struct sge_eq *eq = &txq->eq; 7026 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 7027 7028 MPASS(eq->flags & EQ_SW_ALLOCATED); 7029 MPASS(!(eq->flags & EQ_ENABLED)); 7030 7031 /* Wait for the mp_ring to empty. */ 7032 while (!mp_ring_is_idle(txq->r)) { 7033 mp_ring_check_drainage(txq->r, 4096); 7034 pause("rquiesce", 1); 7035 } 7036 MPASS(txq->txp.npkt == 0); 7037 7038 if (eq->flags & EQ_HW_ALLOCATED) { 7039 /* 7040 * Hardware is alive and working normally. Wait for it to 7041 * finish and then wait for the driver to catch up and reclaim 7042 * all descriptors. 7043 */ 7044 while (spg->cidx != htobe16(eq->pidx)) 7045 pause("equiesce", 1); 7046 while (eq->cidx != eq->pidx) 7047 pause("dquiesce", 1); 7048 } else { 7049 /* 7050 * Hardware is unavailable. Discard all pending tx and reclaim 7051 * descriptors directly. 7052 */ 7053 TXQ_LOCK(txq); 7054 while (eq->cidx != eq->pidx) { 7055 struct mbuf *m, *nextpkt; 7056 struct tx_sdesc *txsd; 7057 7058 txsd = &txq->sdesc[eq->cidx]; 7059 for (m = txsd->m; m != NULL; m = nextpkt) { 7060 nextpkt = m->m_nextpkt; 7061 m->m_nextpkt = NULL; 7062 m_freem(m); 7063 } 7064 IDXINCR(eq->cidx, txsd->desc_used, eq->sidx); 7065 } 7066 spg->pidx = spg->cidx = htobe16(eq->cidx); 7067 TXQ_UNLOCK(txq); 7068 } 7069 } 7070 7071 static void 7072 quiesce_wrq(struct sge_wrq *wrq) 7073 { 7074 struct wrqe *wr; 7075 7076 TXQ_LOCK(wrq); 7077 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 7078 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 7079 #ifdef INVARIANTS 7080 wrq->nwr_pending--; 7081 wrq->ndesc_needed -= howmany(wr->wr_len, EQ_ESIZE); 7082 #endif 7083 free(wr, M_CXGBE); 7084 } 7085 MPASS(wrq->nwr_pending == 0); 7086 MPASS(wrq->ndesc_needed == 0); 7087 wrq->nwr_pending = 0; 7088 wrq->ndesc_needed = 0; 7089 TXQ_UNLOCK(wrq); 7090 } 7091 7092 static void 7093 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 7094 { 7095 /* Synchronize with the interrupt handler */ 7096 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 7097 pause("iqfree", 1); 7098 7099 if (fl != NULL) { 7100 MPASS(iq->flags & IQ_HAS_FL); 7101 7102 mtx_lock(&sc->sfl_lock); 7103 FL_LOCK(fl); 7104 fl->flags |= FL_DOOMED; 7105 FL_UNLOCK(fl); 7106 callout_stop(&sc->sfl_callout); 7107 mtx_unlock(&sc->sfl_lock); 7108 7109 KASSERT((fl->flags & FL_STARVING) == 0, 7110 ("%s: still starving", __func__)); 7111 7112 /* Release all buffers if hardware is no longer available. */ 7113 if (!(iq->flags & IQ_HW_ALLOCATED)) 7114 free_fl_buffers(sc, fl); 7115 } 7116 } 7117 7118 /* 7119 * Wait for all activity on all the queues of the VI to complete. It is assumed 7120 * that no new work is being enqueued by the hardware or the driver. That part 7121 * should be arranged before calling this function. 7122 */ 7123 static void 7124 quiesce_vi(struct vi_info *vi) 7125 { 7126 int i; 7127 struct adapter *sc = vi->adapter; 7128 struct sge_rxq *rxq; 7129 struct sge_txq *txq; 7130 #ifdef TCP_OFFLOAD 7131 struct sge_ofld_rxq *ofld_rxq; 7132 #endif 7133 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7134 struct sge_ofld_txq *ofld_txq; 7135 #endif 7136 7137 if (!(vi->flags & VI_INIT_DONE)) 7138 return; 7139 7140 for_each_txq(vi, i, txq) { 7141 quiesce_txq(txq); 7142 } 7143 7144 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7145 for_each_ofld_txq(vi, i, ofld_txq) { 7146 quiesce_wrq(&ofld_txq->wrq); 7147 } 7148 #endif 7149 7150 for_each_rxq(vi, i, rxq) { 7151 quiesce_iq_fl(sc, &rxq->iq, &rxq->fl); 7152 } 7153 7154 #ifdef TCP_OFFLOAD 7155 for_each_ofld_rxq(vi, i, ofld_rxq) { 7156 quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl); 7157 } 7158 #endif 7159 } 7160 7161 static int 7162 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 7163 driver_intr_t *handler, void *arg, char *name) 7164 { 7165 int rc; 7166 7167 irq->rid = rid; 7168 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 7169 RF_SHAREABLE | RF_ACTIVE); 7170 if (irq->res == NULL) { 7171 device_printf(sc->dev, 7172 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 7173 return (ENOMEM); 7174 } 7175 7176 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 7177 NULL, handler, arg, &irq->tag); 7178 if (rc != 0) { 7179 device_printf(sc->dev, 7180 "failed to setup interrupt for rid %d, name %s: %d\n", 7181 rid, name, rc); 7182 } else if (name) 7183 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 7184 7185 return (rc); 7186 } 7187 7188 static int 7189 t4_free_irq(struct adapter *sc, struct irq *irq) 7190 { 7191 if (irq->tag) 7192 bus_teardown_intr(sc->dev, irq->res, irq->tag); 7193 if (irq->res) 7194 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 7195 7196 bzero(irq, sizeof(*irq)); 7197 7198 return (0); 7199 } 7200 7201 static void 7202 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 7203 { 7204 7205 regs->version = chip_id(sc) | chip_rev(sc) << 10; 7206 t4_get_regs(sc, buf, regs->len); 7207 } 7208 7209 #define A_PL_INDIR_CMD 0x1f8 7210 7211 #define S_PL_AUTOINC 31 7212 #define M_PL_AUTOINC 0x1U 7213 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 7214 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 7215 7216 #define S_PL_VFID 20 7217 #define M_PL_VFID 0xffU 7218 #define V_PL_VFID(x) ((x) << S_PL_VFID) 7219 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 7220 7221 #define S_PL_ADDR 0 7222 #define M_PL_ADDR 0xfffffU 7223 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 7224 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 7225 7226 #define A_PL_INDIR_DATA 0x1fc 7227 7228 static uint64_t 7229 read_vf_stat(struct adapter *sc, u_int vin, int reg) 7230 { 7231 u32 stats[2]; 7232 7233 if (sc->flags & IS_VF) { 7234 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 7235 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 7236 } else { 7237 mtx_assert(&sc->reg_lock, MA_OWNED); 7238 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 7239 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 7240 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 7241 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 7242 } 7243 return (((uint64_t)stats[1]) << 32 | stats[0]); 7244 } 7245 7246 static void 7247 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 7248 { 7249 7250 #define GET_STAT(name) \ 7251 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 7252 7253 if (!(sc->flags & IS_VF)) 7254 mtx_lock(&sc->reg_lock); 7255 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 7256 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 7257 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 7258 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 7259 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 7260 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 7261 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 7262 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 7263 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 7264 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 7265 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 7266 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 7267 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 7268 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 7269 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 7270 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 7271 if (!(sc->flags & IS_VF)) 7272 mtx_unlock(&sc->reg_lock); 7273 7274 #undef GET_STAT 7275 } 7276 7277 static void 7278 t4_clr_vi_stats(struct adapter *sc, u_int vin) 7279 { 7280 int reg; 7281 7282 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 7283 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 7284 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 7285 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 7286 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 7287 } 7288 7289 static void 7290 vi_refresh_stats(struct vi_info *vi) 7291 { 7292 struct timeval tv; 7293 const struct timeval interval = {0, 250000}; /* 250ms */ 7294 7295 mtx_assert(&vi->tick_mtx, MA_OWNED); 7296 7297 if (vi->flags & VI_SKIP_STATS) 7298 return; 7299 7300 getmicrotime(&tv); 7301 timevalsub(&tv, &interval); 7302 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7303 return; 7304 7305 t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats); 7306 getmicrotime(&vi->last_refreshed); 7307 } 7308 7309 static void 7310 cxgbe_refresh_stats(struct vi_info *vi) 7311 { 7312 u_int i, v, tnl_cong_drops, chan_map; 7313 struct timeval tv; 7314 const struct timeval interval = {0, 250000}; /* 250ms */ 7315 struct port_info *pi; 7316 struct adapter *sc; 7317 7318 mtx_assert(&vi->tick_mtx, MA_OWNED); 7319 7320 if (vi->flags & VI_SKIP_STATS) 7321 return; 7322 7323 getmicrotime(&tv); 7324 timevalsub(&tv, &interval); 7325 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7326 return; 7327 7328 pi = vi->pi; 7329 sc = vi->adapter; 7330 tnl_cong_drops = 0; 7331 t4_get_port_stats(sc, pi->port_id, &pi->stats); 7332 chan_map = pi->rx_e_chan_map; 7333 while (chan_map) { 7334 i = ffs(chan_map) - 1; 7335 mtx_lock(&sc->reg_lock); 7336 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 7337 A_TP_MIB_TNL_CNG_DROP_0 + i); 7338 mtx_unlock(&sc->reg_lock); 7339 tnl_cong_drops += v; 7340 chan_map &= ~(1 << i); 7341 } 7342 pi->tnl_cong_drops = tnl_cong_drops; 7343 getmicrotime(&vi->last_refreshed); 7344 } 7345 7346 static void 7347 cxgbe_tick(void *arg) 7348 { 7349 struct vi_info *vi = arg; 7350 7351 MPASS(IS_MAIN_VI(vi)); 7352 mtx_assert(&vi->tick_mtx, MA_OWNED); 7353 7354 cxgbe_refresh_stats(vi); 7355 callout_schedule(&vi->tick, hz); 7356 } 7357 7358 static void 7359 vi_tick(void *arg) 7360 { 7361 struct vi_info *vi = arg; 7362 7363 mtx_assert(&vi->tick_mtx, MA_OWNED); 7364 7365 vi_refresh_stats(vi); 7366 callout_schedule(&vi->tick, hz); 7367 } 7368 7369 /* 7370 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 7371 */ 7372 static char *caps_decoder[] = { 7373 "\20\001IPMI\002NCSI", /* 0: NBM */ 7374 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 7375 "\20\001INGRESS\002EGRESS", /* 2: switch */ 7376 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 7377 "\006HASHFILTER\007ETHOFLD", 7378 "\20\001TOE", /* 4: TOE */ 7379 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 7380 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 7381 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 7382 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 7383 "\007T10DIF" 7384 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 7385 "\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE" /* 7: Crypto */ 7386 "\004TLS_HW", 7387 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 7388 "\004PO_INITIATOR\005PO_TARGET", 7389 }; 7390 7391 void 7392 t4_sysctls(struct adapter *sc) 7393 { 7394 struct sysctl_ctx_list *ctx = &sc->ctx; 7395 struct sysctl_oid *oid; 7396 struct sysctl_oid_list *children, *c0; 7397 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 7398 7399 /* 7400 * dev.t4nex.X. 7401 */ 7402 oid = device_get_sysctl_tree(sc->dev); 7403 c0 = children = SYSCTL_CHILDREN(oid); 7404 7405 sc->sc_do_rxcopy = 1; 7406 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 7407 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 7408 7409 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 7410 sc->params.nports, "# of ports"); 7411 7412 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 7413 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells, 7414 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A", 7415 "available doorbells"); 7416 7417 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 7418 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 7419 7420 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 7421 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7422 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val), 7423 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 7424 7425 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 7426 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7427 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val), 7428 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 7429 7430 t4_sge_sysctls(sc, ctx, children); 7431 7432 sc->lro_timeout = 100; 7433 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 7434 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 7435 7436 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 7437 &sc->debug_flags, 0, "flags to enable runtime debugging"); 7438 7439 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 7440 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 7441 7442 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 7443 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 7444 7445 if (sc->flags & IS_VF) 7446 return; 7447 7448 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 7449 NULL, chip_rev(sc), "chip hardware revision"); 7450 7451 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 7452 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 7453 7454 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 7455 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 7456 7457 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 7458 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 7459 7460 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 7461 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 7462 7463 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 7464 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 7465 7466 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 7467 sc->er_version, 0, "expansion ROM version"); 7468 7469 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 7470 sc->bs_version, 0, "bootstrap firmware version"); 7471 7472 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 7473 NULL, sc->params.scfg_vers, "serial config version"); 7474 7475 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 7476 NULL, sc->params.vpd_vers, "VPD version"); 7477 7478 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 7479 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 7480 7481 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 7482 sc->cfcsum, "config file checksum"); 7483 7484 #define SYSCTL_CAP(name, n, text) \ 7485 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 7486 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \ 7487 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \ 7488 "available " text " capabilities") 7489 7490 SYSCTL_CAP(nbmcaps, 0, "NBM"); 7491 SYSCTL_CAP(linkcaps, 1, "link"); 7492 SYSCTL_CAP(switchcaps, 2, "switch"); 7493 SYSCTL_CAP(niccaps, 3, "NIC"); 7494 SYSCTL_CAP(toecaps, 4, "TCP offload"); 7495 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 7496 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 7497 SYSCTL_CAP(cryptocaps, 7, "crypto"); 7498 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 7499 #undef SYSCTL_CAP 7500 7501 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 7502 NULL, sc->tids.nftids, "number of filters"); 7503 7504 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7505 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7506 sysctl_temperature, "I", "chip temperature (in Celsius)"); 7507 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", 7508 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7509 sysctl_reset_sensor, "I", "reset the chip's temperature sensor."); 7510 7511 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", 7512 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7513 sysctl_loadavg, "A", 7514 "microprocessor load averages (debug firmwares only)"); 7515 7516 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", 7517 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd, 7518 "I", "core Vdd (in mV)"); 7519 7520 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 7521 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS, 7522 sysctl_cpus, "A", "local CPUs"); 7523 7524 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 7525 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS, 7526 sysctl_cpus, "A", "preferred CPUs for interrupts"); 7527 7528 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 7529 &sc->swintr, 0, "software triggered interrupts"); 7530 7531 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset", 7532 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I", 7533 "1 = reset adapter, 0 = zero reset counter"); 7534 7535 /* 7536 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 7537 */ 7538 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 7539 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL, 7540 "logs and miscellaneous information"); 7541 children = SYSCTL_CHILDREN(oid); 7542 7543 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 7544 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7545 sysctl_cctrl, "A", "congestion control"); 7546 7547 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 7548 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7549 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 7550 7551 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 7552 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7553 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 7554 7555 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 7556 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7557 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 7558 7559 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 7560 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3, 7561 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 7562 7563 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 7564 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4, 7565 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 7566 7567 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 7568 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5, 7569 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 7570 7571 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 7572 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7573 sysctl_cim_la, "A", "CIM logic analyzer"); 7574 7575 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 7576 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7577 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 7578 7579 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 7580 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7581 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 7582 7583 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 7584 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7585 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 7586 7587 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 7588 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7589 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 7590 7591 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 7592 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7593 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 7594 7595 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 7596 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7597 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 7598 7599 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 7600 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7601 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 7602 7603 if (chip_id(sc) > CHELSIO_T4) { 7604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 7605 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7606 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7607 "CIM OBQ 6 (SGE0-RX)"); 7608 7609 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 7610 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7611 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7612 "CIM OBQ 7 (SGE1-RX)"); 7613 } 7614 7615 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 7616 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7617 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 7618 7619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 7620 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7621 sysctl_cim_qcfg, "A", "CIM queue configuration"); 7622 7623 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 7624 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7625 sysctl_cpl_stats, "A", "CPL statistics"); 7626 7627 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 7628 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7629 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 7630 7631 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats", 7632 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7633 sysctl_tid_stats, "A", "tid stats"); 7634 7635 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 7636 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7637 sysctl_devlog, "A", "firmware's device log"); 7638 7639 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 7640 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7641 sysctl_fcoe_stats, "A", "FCoE statistics"); 7642 7643 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 7644 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7645 sysctl_hw_sched, "A", "hardware scheduler "); 7646 7647 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 7648 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7649 sysctl_l2t, "A", "hardware L2 table"); 7650 7651 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 7652 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7653 sysctl_smt, "A", "hardware source MAC table"); 7654 7655 #ifdef INET6 7656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 7657 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7658 sysctl_clip, "A", "active CLIP table entries"); 7659 #endif 7660 7661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 7662 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7663 sysctl_lb_stats, "A", "loopback statistics"); 7664 7665 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 7666 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7667 sysctl_meminfo, "A", "memory regions"); 7668 7669 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 7670 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7671 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 7672 "A", "MPS TCAM entries"); 7673 7674 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 7675 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7676 sysctl_path_mtus, "A", "path MTUs"); 7677 7678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 7679 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7680 sysctl_pm_stats, "A", "PM statistics"); 7681 7682 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 7683 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7684 sysctl_rdma_stats, "A", "RDMA statistics"); 7685 7686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 7687 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7688 sysctl_tcp_stats, "A", "TCP statistics"); 7689 7690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 7691 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7692 sysctl_tids, "A", "TID information"); 7693 7694 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 7695 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7696 sysctl_tp_err_stats, "A", "TP error statistics"); 7697 7698 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats", 7699 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7700 sysctl_tnl_stats, "A", "TP tunnel statistics"); 7701 7702 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 7703 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7704 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask"); 7705 7706 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 7707 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7708 sysctl_tp_la, "A", "TP logic analyzer"); 7709 7710 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 7711 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7712 sysctl_tx_rate, "A", "Tx rate"); 7713 7714 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 7715 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7716 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 7717 7718 if (chip_id(sc) >= CHELSIO_T5) { 7719 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 7720 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7721 sysctl_wcwr_stats, "A", "write combined work requests"); 7722 } 7723 7724 #ifdef KERN_TLS 7725 if (is_ktls(sc)) { 7726 /* 7727 * dev.t4nex.0.tls. 7728 */ 7729 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", 7730 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters"); 7731 children = SYSCTL_CHILDREN(oid); 7732 7733 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys", 7734 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS " 7735 "keys in work requests (1) or attempt to store TLS keys " 7736 "in card memory."); 7737 7738 if (is_t6(sc)) 7739 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs", 7740 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to " 7741 "combine TCB field updates with TLS record work " 7742 "requests."); 7743 } 7744 #endif 7745 7746 #ifdef TCP_OFFLOAD 7747 if (is_offload(sc)) { 7748 int i; 7749 char s[4]; 7750 7751 /* 7752 * dev.t4nex.X.toe. 7753 */ 7754 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", 7755 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters"); 7756 children = SYSCTL_CHILDREN(oid); 7757 7758 sc->tt.cong_algorithm = -1; 7759 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 7760 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 7761 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 7762 "3 = highspeed)"); 7763 7764 sc->tt.sndbuf = -1; 7765 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 7766 &sc->tt.sndbuf, 0, "hardware send buffer"); 7767 7768 sc->tt.ddp = 0; 7769 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", 7770 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, ""); 7771 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW, 7772 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)"); 7773 7774 sc->tt.rx_coalesce = -1; 7775 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 7776 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 7777 7778 sc->tt.tls = 0; 7779 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT | 7780 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I", 7781 "Inline TLS allowed"); 7782 7783 sc->tt.tx_align = -1; 7784 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 7785 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 7786 7787 sc->tt.tx_zcopy = 0; 7788 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 7789 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 7790 "Enable zero-copy aio_write(2)"); 7791 7792 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 7793 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7794 "cop_managed_offloading", CTLFLAG_RW, 7795 &sc->tt.cop_managed_offloading, 0, 7796 "COP (Connection Offload Policy) controls all TOE offload"); 7797 7798 sc->tt.autorcvbuf_inc = 16 * 1024; 7799 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 7800 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 7801 "autorcvbuf increment"); 7802 7803 sc->tt.update_hc_on_pmtu_change = 1; 7804 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7805 "update_hc_on_pmtu_change", CTLFLAG_RW, 7806 &sc->tt.update_hc_on_pmtu_change, 0, 7807 "Update hostcache entry if the PMTU changes"); 7808 7809 sc->tt.iso = 1; 7810 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW, 7811 &sc->tt.iso, 0, "Enable iSCSI segmentation offload"); 7812 7813 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 7814 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7815 sysctl_tp_tick, "A", "TP timer tick (us)"); 7816 7817 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 7818 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7819 sysctl_tp_tick, "A", "TCP timestamp tick (us)"); 7820 7821 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 7822 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7823 sysctl_tp_tick, "A", "DACK tick (us)"); 7824 7825 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 7826 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7827 sysctl_tp_dack_timer, "IU", "DACK timer (us)"); 7828 7829 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 7830 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7831 A_TP_RXT_MIN, sysctl_tp_timer, "LU", 7832 "Minimum retransmit interval (us)"); 7833 7834 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 7835 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7836 A_TP_RXT_MAX, sysctl_tp_timer, "LU", 7837 "Maximum retransmit interval (us)"); 7838 7839 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 7840 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7841 A_TP_PERS_MIN, sysctl_tp_timer, "LU", 7842 "Persist timer min (us)"); 7843 7844 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 7845 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7846 A_TP_PERS_MAX, sysctl_tp_timer, "LU", 7847 "Persist timer max (us)"); 7848 7849 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 7850 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7851 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU", 7852 "Keepalive idle timer (us)"); 7853 7854 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 7855 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7856 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU", 7857 "Keepalive interval timer (us)"); 7858 7859 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 7860 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7861 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)"); 7862 7863 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 7864 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7865 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU", 7866 "FINWAIT2 timer (us)"); 7867 7868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 7869 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7870 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU", 7871 "Number of SYN retransmissions before abort"); 7872 7873 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 7874 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7875 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU", 7876 "Number of retransmissions before abort"); 7877 7878 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 7879 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7880 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU", 7881 "Number of keepalive probes before abort"); 7882 7883 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 7884 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7885 "TOE retransmit backoffs"); 7886 children = SYSCTL_CHILDREN(oid); 7887 for (i = 0; i < 16; i++) { 7888 snprintf(s, sizeof(s), "%u", i); 7889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 7890 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7891 i, sysctl_tp_backoff, "IU", 7892 "TOE retransmit backoff"); 7893 } 7894 } 7895 #endif 7896 } 7897 7898 void 7899 vi_sysctls(struct vi_info *vi) 7900 { 7901 struct sysctl_ctx_list *ctx = &vi->ctx; 7902 struct sysctl_oid *oid; 7903 struct sysctl_oid_list *children; 7904 7905 /* 7906 * dev.v?(cxgbe|cxl).X. 7907 */ 7908 oid = device_get_sysctl_tree(vi->dev); 7909 children = SYSCTL_CHILDREN(oid); 7910 7911 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 7912 vi->viid, "VI identifer"); 7913 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 7914 &vi->nrxq, 0, "# of rx queues"); 7915 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 7916 &vi->ntxq, 0, "# of tx queues"); 7917 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 7918 &vi->first_rxq, 0, "index of first rx queue"); 7919 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 7920 &vi->first_txq, 0, "index of first tx queue"); 7921 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 7922 vi->rss_base, "start of RSS indirection table"); 7923 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 7924 vi->rss_size, "size of RSS indirection table"); 7925 7926 if (IS_MAIN_VI(vi)) { 7927 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 7928 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7929 sysctl_noflowq, "IU", 7930 "Reserve queue 0 for non-flowid packets"); 7931 } 7932 7933 if (vi->adapter->flags & IS_VF) { 7934 MPASS(vi->flags & TX_USES_VM_WR); 7935 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD, 7936 NULL, 1, "use VM work requests for transmit"); 7937 } else { 7938 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr", 7939 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7940 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit"); 7941 } 7942 7943 #ifdef TCP_OFFLOAD 7944 if (vi->nofldrxq != 0) { 7945 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 7946 &vi->nofldrxq, 0, 7947 "# of rx queues for offloaded TCP connections"); 7948 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 7949 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 7950 "index of first TOE rx queue"); 7951 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 7952 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7953 sysctl_holdoff_tmr_idx_ofld, "I", 7954 "holdoff timer index for TOE queues"); 7955 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 7956 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7957 sysctl_holdoff_pktc_idx_ofld, "I", 7958 "holdoff packet counter index for TOE queues"); 7959 } 7960 #endif 7961 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7962 if (vi->nofldtxq != 0) { 7963 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 7964 &vi->nofldtxq, 0, 7965 "# of tx queues for TOE/ETHOFLD"); 7966 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 7967 CTLFLAG_RD, &vi->first_ofld_txq, 0, 7968 "index of first TOE/ETHOFLD tx queue"); 7969 } 7970 #endif 7971 #ifdef DEV_NETMAP 7972 if (vi->nnmrxq != 0) { 7973 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 7974 &vi->nnmrxq, 0, "# of netmap rx queues"); 7975 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 7976 &vi->nnmtxq, 0, "# of netmap tx queues"); 7977 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 7978 CTLFLAG_RD, &vi->first_nm_rxq, 0, 7979 "index of first netmap rx queue"); 7980 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 7981 CTLFLAG_RD, &vi->first_nm_txq, 0, 7982 "index of first netmap tx queue"); 7983 } 7984 #endif 7985 7986 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 7987 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7988 sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); 7989 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 7990 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7991 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); 7992 7993 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 7994 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7995 sysctl_qsize_rxq, "I", "rx queue size"); 7996 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 7997 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7998 sysctl_qsize_txq, "I", "tx queue size"); 7999 } 8000 8001 static void 8002 cxgbe_sysctls(struct port_info *pi) 8003 { 8004 struct sysctl_ctx_list *ctx = &pi->ctx; 8005 struct sysctl_oid *oid; 8006 struct sysctl_oid_list *children, *children2; 8007 struct adapter *sc = pi->adapter; 8008 int i; 8009 char name[16]; 8010 static char *tc_flags = {"\20\1USER"}; 8011 8012 /* 8013 * dev.cxgbe.X. 8014 */ 8015 oid = device_get_sysctl_tree(pi->dev); 8016 children = SYSCTL_CHILDREN(oid); 8017 8018 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", 8019 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 8020 sysctl_linkdnrc, "A", "reason why link is down"); 8021 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 8022 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 8023 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 8024 sysctl_btphy, "I", "PHY temperature (in Celsius)"); 8025 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 8026 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1, 8027 sysctl_btphy, "I", "PHY firmware version"); 8028 } 8029 8030 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 8031 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8032 sysctl_pause_settings, "A", 8033 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 8034 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec", 8035 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A", 8036 "FEC in use on the link"); 8037 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec", 8038 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8039 sysctl_requested_fec, "A", 8040 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)"); 8041 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec", 8042 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A", 8043 "FEC recommended by the cable/transceiver"); 8044 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 8045 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8046 sysctl_autoneg, "I", 8047 "autonegotiation (-1 = not supported)"); 8048 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec", 8049 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8050 sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config"); 8051 8052 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD, 8053 &pi->link_cfg.requested_caps, 0, "L1 config requested by driver"); 8054 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD, 8055 &pi->link_cfg.pcaps, 0, "port capabilities"); 8056 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD, 8057 &pi->link_cfg.acaps, 0, "advertised capabilities"); 8058 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD, 8059 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities"); 8060 8061 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 8062 port_top_speed(pi), "max speed (in Gbps)"); 8063 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 8064 pi->mps_bg_map, "MPS buffer group map"); 8065 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 8066 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 8067 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_chan", CTLFLAG_RD, NULL, 8068 pi->tx_chan, "TP tx c-channel"); 8069 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_chan", CTLFLAG_RD, NULL, 8070 pi->rx_chan, "TP rx c-channel"); 8071 8072 if (sc->flags & IS_VF) 8073 return; 8074 8075 /* 8076 * dev.(cxgbe|cxl).X.tc. 8077 */ 8078 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", 8079 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 8080 "Tx scheduler traffic classes (cl_rl)"); 8081 children2 = SYSCTL_CHILDREN(oid); 8082 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 8083 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 8084 "pktsize for per-flow cl-rl (0 means up to the driver )"); 8085 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 8086 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 8087 "burstsize for per-flow cl-rl (0 means up to the driver)"); 8088 for (i = 0; i < sc->params.nsched_cls; i++) { 8089 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 8090 8091 snprintf(name, sizeof(name), "%d", i); 8092 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 8093 SYSCTL_CHILDREN(oid), OID_AUTO, name, 8094 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class")); 8095 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state", 8096 CTLFLAG_RD, &tc->state, 0, "current state"); 8097 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 8098 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags, 8099 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags"); 8100 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 8101 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 8102 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 8103 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 8104 (pi->port_id << 16) | i, sysctl_tc_params, "A", 8105 "traffic class parameters"); 8106 } 8107 8108 /* 8109 * dev.cxgbe.X.stats. 8110 */ 8111 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 8112 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics"); 8113 children = SYSCTL_CHILDREN(oid); 8114 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 8115 &pi->tx_parse_error, 0, 8116 "# of tx packets with invalid length or # of segments"); 8117 8118 #define T4_REGSTAT(name, stat, desc) \ 8119 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \ 8120 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \ 8121 t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \ 8122 sysctl_handle_t4_reg64, "QU", desc) 8123 8124 /* We get these from port_stats and they may be stale by up to 1s */ 8125 #define T4_PORTSTAT(name, desc) \ 8126 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 8127 &pi->stats.name, desc) 8128 8129 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames"); 8130 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames"); 8131 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames"); 8132 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames"); 8133 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames"); 8134 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames"); 8135 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range"); 8136 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range"); 8137 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range"); 8138 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range"); 8139 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range"); 8140 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range"); 8141 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range"); 8142 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames"); 8143 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted"); 8144 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted"); 8145 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted"); 8146 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted"); 8147 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted"); 8148 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted"); 8149 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted"); 8150 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted"); 8151 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted"); 8152 8153 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames"); 8154 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames"); 8155 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames"); 8156 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames"); 8157 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames"); 8158 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU"); 8159 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames"); 8160 if (is_t6(sc)) { 8161 T4_PORTSTAT(rx_fcs_err, 8162 "# of frames received with bad FCS since last link up"); 8163 } else { 8164 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR, 8165 "# of frames received with bad FCS"); 8166 } 8167 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error"); 8168 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors"); 8169 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received"); 8170 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range"); 8171 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range"); 8172 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range"); 8173 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range"); 8174 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range"); 8175 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range"); 8176 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range"); 8177 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received"); 8178 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received"); 8179 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received"); 8180 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received"); 8181 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received"); 8182 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received"); 8183 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received"); 8184 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received"); 8185 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received"); 8186 8187 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows"); 8188 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows"); 8189 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows"); 8190 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows"); 8191 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets"); 8192 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets"); 8193 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets"); 8194 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets"); 8195 8196 #undef T4_REGSTAT 8197 #undef T4_PORTSTAT 8198 } 8199 8200 static int 8201 sysctl_int_array(SYSCTL_HANDLER_ARGS) 8202 { 8203 int rc, *i, space = 0; 8204 struct sbuf sb; 8205 8206 sbuf_new_for_sysctl(&sb, NULL, 64, req); 8207 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 8208 if (space) 8209 sbuf_printf(&sb, " "); 8210 sbuf_printf(&sb, "%d", *i); 8211 space = 1; 8212 } 8213 rc = sbuf_finish(&sb); 8214 sbuf_delete(&sb); 8215 return (rc); 8216 } 8217 8218 static int 8219 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 8220 { 8221 int rc; 8222 struct sbuf *sb; 8223 8224 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8225 if (sb == NULL) 8226 return (ENOMEM); 8227 8228 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 8229 rc = sbuf_finish(sb); 8230 sbuf_delete(sb); 8231 8232 return (rc); 8233 } 8234 8235 static int 8236 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 8237 { 8238 int rc; 8239 struct sbuf *sb; 8240 8241 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8242 if (sb == NULL) 8243 return (ENOMEM); 8244 8245 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 8246 rc = sbuf_finish(sb); 8247 sbuf_delete(sb); 8248 8249 return (rc); 8250 } 8251 8252 static int 8253 sysctl_btphy(SYSCTL_HANDLER_ARGS) 8254 { 8255 struct port_info *pi = arg1; 8256 int op = arg2; 8257 struct adapter *sc = pi->adapter; 8258 u_int v; 8259 int rc; 8260 8261 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 8262 if (rc) 8263 return (rc); 8264 if (hw_off_limits(sc)) 8265 rc = ENXIO; 8266 else { 8267 /* XXX: magic numbers */ 8268 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, 8269 op ? 0x20 : 0xc820, &v); 8270 } 8271 end_synchronized_op(sc, 0); 8272 if (rc) 8273 return (rc); 8274 if (op == 0) 8275 v /= 256; 8276 8277 rc = sysctl_handle_int(oidp, &v, 0, req); 8278 return (rc); 8279 } 8280 8281 static int 8282 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 8283 { 8284 struct vi_info *vi = arg1; 8285 int rc, val; 8286 8287 val = vi->rsrv_noflowq; 8288 rc = sysctl_handle_int(oidp, &val, 0, req); 8289 if (rc != 0 || req->newptr == NULL) 8290 return (rc); 8291 8292 if ((val >= 1) && (vi->ntxq > 1)) 8293 vi->rsrv_noflowq = 1; 8294 else 8295 vi->rsrv_noflowq = 0; 8296 8297 return (rc); 8298 } 8299 8300 static int 8301 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS) 8302 { 8303 struct vi_info *vi = arg1; 8304 struct adapter *sc = vi->adapter; 8305 int rc, val, i; 8306 8307 MPASS(!(sc->flags & IS_VF)); 8308 8309 val = vi->flags & TX_USES_VM_WR ? 1 : 0; 8310 rc = sysctl_handle_int(oidp, &val, 0, req); 8311 if (rc != 0 || req->newptr == NULL) 8312 return (rc); 8313 8314 if (val != 0 && val != 1) 8315 return (EINVAL); 8316 8317 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8318 "t4txvm"); 8319 if (rc) 8320 return (rc); 8321 if (hw_off_limits(sc)) 8322 rc = ENXIO; 8323 else if (if_getdrvflags(vi->ifp) & IFF_DRV_RUNNING) { 8324 /* 8325 * We don't want parse_pkt to run with one setting (VF or PF) 8326 * and then eth_tx to see a different setting but still use 8327 * stale information calculated by parse_pkt. 8328 */ 8329 rc = EBUSY; 8330 } else { 8331 struct port_info *pi = vi->pi; 8332 struct sge_txq *txq; 8333 uint32_t ctrl0; 8334 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr; 8335 8336 if (val) { 8337 vi->flags |= TX_USES_VM_WR; 8338 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO); 8339 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8340 V_TXPKT_INTF(pi->tx_chan)); 8341 if (!(sc->flags & IS_VF)) 8342 npkt--; 8343 } else { 8344 vi->flags &= ~TX_USES_VM_WR; 8345 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO); 8346 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8347 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 8348 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 8349 } 8350 for_each_txq(vi, i, txq) { 8351 txq->cpl_ctrl0 = ctrl0; 8352 txq->txp.max_npkt = npkt; 8353 } 8354 } 8355 end_synchronized_op(sc, LOCK_HELD); 8356 return (rc); 8357 } 8358 8359 static int 8360 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 8361 { 8362 struct vi_info *vi = arg1; 8363 struct adapter *sc = vi->adapter; 8364 int idx, rc, i; 8365 struct sge_rxq *rxq; 8366 uint8_t v; 8367 8368 idx = vi->tmr_idx; 8369 8370 rc = sysctl_handle_int(oidp, &idx, 0, req); 8371 if (rc != 0 || req->newptr == NULL) 8372 return (rc); 8373 8374 if (idx < 0 || idx >= SGE_NTIMERS) 8375 return (EINVAL); 8376 8377 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8378 "t4tmr"); 8379 if (rc) 8380 return (rc); 8381 8382 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 8383 for_each_rxq(vi, i, rxq) { 8384 #ifdef atomic_store_rel_8 8385 atomic_store_rel_8(&rxq->iq.intr_params, v); 8386 #else 8387 rxq->iq.intr_params = v; 8388 #endif 8389 } 8390 vi->tmr_idx = idx; 8391 8392 end_synchronized_op(sc, LOCK_HELD); 8393 return (0); 8394 } 8395 8396 static int 8397 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 8398 { 8399 struct vi_info *vi = arg1; 8400 struct adapter *sc = vi->adapter; 8401 int idx, rc; 8402 8403 idx = vi->pktc_idx; 8404 8405 rc = sysctl_handle_int(oidp, &idx, 0, req); 8406 if (rc != 0 || req->newptr == NULL) 8407 return (rc); 8408 8409 if (idx < -1 || idx >= SGE_NCOUNTERS) 8410 return (EINVAL); 8411 8412 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8413 "t4pktc"); 8414 if (rc) 8415 return (rc); 8416 8417 if (vi->flags & VI_INIT_DONE) 8418 rc = EBUSY; /* cannot be changed once the queues are created */ 8419 else 8420 vi->pktc_idx = idx; 8421 8422 end_synchronized_op(sc, LOCK_HELD); 8423 return (rc); 8424 } 8425 8426 static int 8427 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 8428 { 8429 struct vi_info *vi = arg1; 8430 struct adapter *sc = vi->adapter; 8431 int qsize, rc; 8432 8433 qsize = vi->qsize_rxq; 8434 8435 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8436 if (rc != 0 || req->newptr == NULL) 8437 return (rc); 8438 8439 if (qsize < 128 || (qsize & 7)) 8440 return (EINVAL); 8441 8442 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8443 "t4rxqs"); 8444 if (rc) 8445 return (rc); 8446 8447 if (vi->flags & VI_INIT_DONE) 8448 rc = EBUSY; /* cannot be changed once the queues are created */ 8449 else 8450 vi->qsize_rxq = qsize; 8451 8452 end_synchronized_op(sc, LOCK_HELD); 8453 return (rc); 8454 } 8455 8456 static int 8457 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 8458 { 8459 struct vi_info *vi = arg1; 8460 struct adapter *sc = vi->adapter; 8461 int qsize, rc; 8462 8463 qsize = vi->qsize_txq; 8464 8465 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8466 if (rc != 0 || req->newptr == NULL) 8467 return (rc); 8468 8469 if (qsize < 128 || qsize > 65536) 8470 return (EINVAL); 8471 8472 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8473 "t4txqs"); 8474 if (rc) 8475 return (rc); 8476 8477 if (vi->flags & VI_INIT_DONE) 8478 rc = EBUSY; /* cannot be changed once the queues are created */ 8479 else 8480 vi->qsize_txq = qsize; 8481 8482 end_synchronized_op(sc, LOCK_HELD); 8483 return (rc); 8484 } 8485 8486 static int 8487 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 8488 { 8489 struct port_info *pi = arg1; 8490 struct adapter *sc = pi->adapter; 8491 struct link_config *lc = &pi->link_cfg; 8492 int rc; 8493 8494 if (req->newptr == NULL) { 8495 struct sbuf *sb; 8496 static char *bits = "\20\1RX\2TX\3AUTO"; 8497 8498 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8499 if (sb == NULL) 8500 return (ENOMEM); 8501 8502 if (lc->link_ok) { 8503 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 8504 (lc->requested_fc & PAUSE_AUTONEG), bits); 8505 } else { 8506 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 8507 PAUSE_RX | PAUSE_AUTONEG), bits); 8508 } 8509 rc = sbuf_finish(sb); 8510 sbuf_delete(sb); 8511 } else { 8512 char s[2]; 8513 int n; 8514 8515 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 8516 PAUSE_AUTONEG)); 8517 s[1] = 0; 8518 8519 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8520 if (rc != 0) 8521 return(rc); 8522 8523 if (s[1] != 0) 8524 return (EINVAL); 8525 if (s[0] < '0' || s[0] > '9') 8526 return (EINVAL); /* not a number */ 8527 n = s[0] - '0'; 8528 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 8529 return (EINVAL); /* some other bit is set too */ 8530 8531 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8532 "t4PAUSE"); 8533 if (rc) 8534 return (rc); 8535 if (!hw_off_limits(sc)) { 8536 PORT_LOCK(pi); 8537 lc->requested_fc = n; 8538 fixup_link_config(pi); 8539 if (pi->up_vis > 0) 8540 rc = apply_link_config(pi); 8541 set_current_media(pi); 8542 PORT_UNLOCK(pi); 8543 } 8544 end_synchronized_op(sc, 0); 8545 } 8546 8547 return (rc); 8548 } 8549 8550 static int 8551 sysctl_link_fec(SYSCTL_HANDLER_ARGS) 8552 { 8553 struct port_info *pi = arg1; 8554 struct link_config *lc = &pi->link_cfg; 8555 int rc; 8556 struct sbuf *sb; 8557 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2"; 8558 8559 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8560 if (sb == NULL) 8561 return (ENOMEM); 8562 if (lc->link_ok) 8563 sbuf_printf(sb, "%b", lc->fec, bits); 8564 else 8565 sbuf_printf(sb, "no link"); 8566 rc = sbuf_finish(sb); 8567 sbuf_delete(sb); 8568 8569 return (rc); 8570 } 8571 8572 static int 8573 sysctl_requested_fec(SYSCTL_HANDLER_ARGS) 8574 { 8575 struct port_info *pi = arg1; 8576 struct adapter *sc = pi->adapter; 8577 struct link_config *lc = &pi->link_cfg; 8578 int rc; 8579 int8_t old; 8580 8581 if (req->newptr == NULL) { 8582 struct sbuf *sb; 8583 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2" 8584 "\5RSVD3\6auto\7module"; 8585 8586 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8587 if (sb == NULL) 8588 return (ENOMEM); 8589 8590 sbuf_printf(sb, "%b", lc->requested_fec, bits); 8591 rc = sbuf_finish(sb); 8592 sbuf_delete(sb); 8593 } else { 8594 char s[8]; 8595 int n; 8596 8597 snprintf(s, sizeof(s), "%d", 8598 lc->requested_fec == FEC_AUTO ? -1 : 8599 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE)); 8600 8601 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8602 if (rc != 0) 8603 return(rc); 8604 8605 n = strtol(&s[0], NULL, 0); 8606 if (n < 0 || n & FEC_AUTO) 8607 n = FEC_AUTO; 8608 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE)) 8609 return (EINVAL);/* some other bit is set too */ 8610 8611 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8612 "t4reqf"); 8613 if (rc) 8614 return (rc); 8615 PORT_LOCK(pi); 8616 old = lc->requested_fec; 8617 if (n == FEC_AUTO) 8618 lc->requested_fec = FEC_AUTO; 8619 else if (n == 0 || n == FEC_NONE) 8620 lc->requested_fec = FEC_NONE; 8621 else { 8622 if ((lc->pcaps | 8623 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) != 8624 lc->pcaps) { 8625 rc = ENOTSUP; 8626 goto done; 8627 } 8628 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC | 8629 FEC_MODULE); 8630 } 8631 if (!hw_off_limits(sc)) { 8632 fixup_link_config(pi); 8633 if (pi->up_vis > 0) { 8634 rc = apply_link_config(pi); 8635 if (rc != 0) { 8636 lc->requested_fec = old; 8637 if (rc == FW_EPROTO) 8638 rc = ENOTSUP; 8639 } 8640 } 8641 } 8642 done: 8643 PORT_UNLOCK(pi); 8644 end_synchronized_op(sc, 0); 8645 } 8646 8647 return (rc); 8648 } 8649 8650 static int 8651 sysctl_module_fec(SYSCTL_HANDLER_ARGS) 8652 { 8653 struct port_info *pi = arg1; 8654 struct adapter *sc = pi->adapter; 8655 struct link_config *lc = &pi->link_cfg; 8656 int rc; 8657 int8_t fec; 8658 struct sbuf *sb; 8659 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3"; 8660 8661 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8662 if (sb == NULL) 8663 return (ENOMEM); 8664 8665 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) { 8666 rc = EBUSY; 8667 goto done; 8668 } 8669 if (hw_off_limits(sc)) { 8670 rc = ENXIO; 8671 goto done; 8672 } 8673 PORT_LOCK(pi); 8674 if (pi->up_vis == 0) { 8675 /* 8676 * If all the interfaces are administratively down the firmware 8677 * does not report transceiver changes. Refresh port info here. 8678 * This is the only reason we have a synchronized op in this 8679 * function. Just PORT_LOCK would have been enough otherwise. 8680 */ 8681 t4_update_port_info(pi); 8682 } 8683 8684 fec = lc->fec_hint; 8685 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE || 8686 !fec_supported(lc->pcaps)) { 8687 PORT_UNLOCK(pi); 8688 sbuf_printf(sb, "n/a"); 8689 } else { 8690 if (fec == 0) 8691 fec = FEC_NONE; 8692 PORT_UNLOCK(pi); 8693 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits); 8694 } 8695 rc = sbuf_finish(sb); 8696 done: 8697 sbuf_delete(sb); 8698 end_synchronized_op(sc, 0); 8699 8700 return (rc); 8701 } 8702 8703 static int 8704 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 8705 { 8706 struct port_info *pi = arg1; 8707 struct adapter *sc = pi->adapter; 8708 struct link_config *lc = &pi->link_cfg; 8709 int rc, val; 8710 8711 if (lc->pcaps & FW_PORT_CAP32_ANEG) 8712 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 8713 else 8714 val = -1; 8715 rc = sysctl_handle_int(oidp, &val, 0, req); 8716 if (rc != 0 || req->newptr == NULL) 8717 return (rc); 8718 if (val == 0) 8719 val = AUTONEG_DISABLE; 8720 else if (val == 1) 8721 val = AUTONEG_ENABLE; 8722 else 8723 val = AUTONEG_AUTO; 8724 8725 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8726 "t4aneg"); 8727 if (rc) 8728 return (rc); 8729 PORT_LOCK(pi); 8730 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 8731 rc = ENOTSUP; 8732 goto done; 8733 } 8734 lc->requested_aneg = val; 8735 if (!hw_off_limits(sc)) { 8736 fixup_link_config(pi); 8737 if (pi->up_vis > 0) 8738 rc = apply_link_config(pi); 8739 set_current_media(pi); 8740 } 8741 done: 8742 PORT_UNLOCK(pi); 8743 end_synchronized_op(sc, 0); 8744 return (rc); 8745 } 8746 8747 static int 8748 sysctl_force_fec(SYSCTL_HANDLER_ARGS) 8749 { 8750 struct port_info *pi = arg1; 8751 struct adapter *sc = pi->adapter; 8752 struct link_config *lc = &pi->link_cfg; 8753 int rc, val; 8754 8755 val = lc->force_fec; 8756 MPASS(val >= -1 && val <= 1); 8757 rc = sysctl_handle_int(oidp, &val, 0, req); 8758 if (rc != 0 || req->newptr == NULL) 8759 return (rc); 8760 if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC)) 8761 return (ENOTSUP); 8762 if (val < -1 || val > 1) 8763 return (EINVAL); 8764 8765 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff"); 8766 if (rc) 8767 return (rc); 8768 PORT_LOCK(pi); 8769 lc->force_fec = val; 8770 if (!hw_off_limits(sc)) { 8771 fixup_link_config(pi); 8772 if (pi->up_vis > 0) 8773 rc = apply_link_config(pi); 8774 } 8775 PORT_UNLOCK(pi); 8776 end_synchronized_op(sc, 0); 8777 return (rc); 8778 } 8779 8780 static int 8781 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 8782 { 8783 struct adapter *sc = arg1; 8784 int rc, reg = arg2; 8785 uint64_t val; 8786 8787 mtx_lock(&sc->reg_lock); 8788 if (hw_off_limits(sc)) 8789 rc = ENXIO; 8790 else { 8791 rc = 0; 8792 val = t4_read_reg64(sc, reg); 8793 } 8794 mtx_unlock(&sc->reg_lock); 8795 if (rc == 0) 8796 rc = sysctl_handle_64(oidp, &val, 0, req); 8797 return (rc); 8798 } 8799 8800 static int 8801 sysctl_temperature(SYSCTL_HANDLER_ARGS) 8802 { 8803 struct adapter *sc = arg1; 8804 int rc, t; 8805 uint32_t param, val; 8806 8807 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 8808 if (rc) 8809 return (rc); 8810 if (hw_off_limits(sc)) 8811 rc = ENXIO; 8812 else { 8813 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8814 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8815 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 8816 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8817 } 8818 end_synchronized_op(sc, 0); 8819 if (rc) 8820 return (rc); 8821 8822 /* unknown is returned as 0 but we display -1 in that case */ 8823 t = val == 0 ? -1 : val; 8824 8825 rc = sysctl_handle_int(oidp, &t, 0, req); 8826 return (rc); 8827 } 8828 8829 static int 8830 sysctl_vdd(SYSCTL_HANDLER_ARGS) 8831 { 8832 struct adapter *sc = arg1; 8833 int rc; 8834 uint32_t param, val; 8835 8836 if (sc->params.core_vdd == 0) { 8837 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8838 "t4vdd"); 8839 if (rc) 8840 return (rc); 8841 if (hw_off_limits(sc)) 8842 rc = ENXIO; 8843 else { 8844 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8845 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8846 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 8847 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, 8848 ¶m, &val); 8849 } 8850 end_synchronized_op(sc, 0); 8851 if (rc) 8852 return (rc); 8853 sc->params.core_vdd = val; 8854 } 8855 8856 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req)); 8857 } 8858 8859 static int 8860 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS) 8861 { 8862 struct adapter *sc = arg1; 8863 int rc, v; 8864 uint32_t param, val; 8865 8866 v = sc->sensor_resets; 8867 rc = sysctl_handle_int(oidp, &v, 0, req); 8868 if (rc != 0 || req->newptr == NULL || v <= 0) 8869 return (rc); 8870 8871 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) || 8872 chip_id(sc) < CHELSIO_T5) 8873 return (ENOTSUP); 8874 8875 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst"); 8876 if (rc) 8877 return (rc); 8878 if (hw_off_limits(sc)) 8879 rc = ENXIO; 8880 else { 8881 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8882 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8883 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR)); 8884 val = 1; 8885 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8886 } 8887 end_synchronized_op(sc, 0); 8888 if (rc == 0) 8889 sc->sensor_resets++; 8890 return (rc); 8891 } 8892 8893 static int 8894 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 8895 { 8896 struct adapter *sc = arg1; 8897 struct sbuf *sb; 8898 int rc; 8899 uint32_t param, val; 8900 8901 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 8902 if (rc) 8903 return (rc); 8904 if (hw_off_limits(sc)) 8905 rc = ENXIO; 8906 else { 8907 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8908 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 8909 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8910 } 8911 end_synchronized_op(sc, 0); 8912 if (rc) 8913 return (rc); 8914 8915 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8916 if (sb == NULL) 8917 return (ENOMEM); 8918 8919 if (val == 0xffffffff) { 8920 /* Only debug and custom firmwares report load averages. */ 8921 sbuf_printf(sb, "not available"); 8922 } else { 8923 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 8924 (val >> 16) & 0xff); 8925 } 8926 rc = sbuf_finish(sb); 8927 sbuf_delete(sb); 8928 8929 return (rc); 8930 } 8931 8932 static int 8933 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 8934 { 8935 struct adapter *sc = arg1; 8936 struct sbuf *sb; 8937 int rc, i; 8938 uint16_t incr[NMTUS][NCCTRL_WIN]; 8939 static const char *dec_fac[] = { 8940 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 8941 "0.9375" 8942 }; 8943 8944 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8945 if (sb == NULL) 8946 return (ENOMEM); 8947 8948 rc = 0; 8949 mtx_lock(&sc->reg_lock); 8950 if (hw_off_limits(sc)) 8951 rc = ENXIO; 8952 else 8953 t4_read_cong_tbl(sc, incr); 8954 mtx_unlock(&sc->reg_lock); 8955 if (rc) 8956 goto done; 8957 8958 for (i = 0; i < NCCTRL_WIN; ++i) { 8959 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 8960 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 8961 incr[5][i], incr[6][i], incr[7][i]); 8962 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 8963 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 8964 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 8965 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 8966 } 8967 8968 rc = sbuf_finish(sb); 8969 done: 8970 sbuf_delete(sb); 8971 return (rc); 8972 } 8973 8974 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 8975 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 8976 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 8977 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 8978 }; 8979 8980 static int 8981 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 8982 { 8983 struct adapter *sc = arg1; 8984 struct sbuf *sb; 8985 int rc, i, n, qid = arg2; 8986 uint32_t *buf, *p; 8987 char *qtype; 8988 u_int cim_num_obq = sc->chip_params->cim_num_obq; 8989 8990 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 8991 ("%s: bad qid %d\n", __func__, qid)); 8992 8993 if (qid < CIM_NUM_IBQ) { 8994 /* inbound queue */ 8995 qtype = "IBQ"; 8996 n = 4 * CIM_IBQ_SIZE; 8997 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 8998 mtx_lock(&sc->reg_lock); 8999 if (hw_off_limits(sc)) 9000 rc = -ENXIO; 9001 else 9002 rc = t4_read_cim_ibq(sc, qid, buf, n); 9003 mtx_unlock(&sc->reg_lock); 9004 } else { 9005 /* outbound queue */ 9006 qtype = "OBQ"; 9007 qid -= CIM_NUM_IBQ; 9008 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 9009 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 9010 mtx_lock(&sc->reg_lock); 9011 if (hw_off_limits(sc)) 9012 rc = -ENXIO; 9013 else 9014 rc = t4_read_cim_obq(sc, qid, buf, n); 9015 mtx_unlock(&sc->reg_lock); 9016 } 9017 9018 if (rc < 0) { 9019 rc = -rc; 9020 goto done; 9021 } 9022 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 9023 9024 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9025 if (sb == NULL) { 9026 rc = ENOMEM; 9027 goto done; 9028 } 9029 9030 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 9031 for (i = 0, p = buf; i < n; i += 16, p += 4) 9032 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 9033 p[2], p[3]); 9034 9035 rc = sbuf_finish(sb); 9036 sbuf_delete(sb); 9037 done: 9038 free(buf, M_CXGBE); 9039 return (rc); 9040 } 9041 9042 static void 9043 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9044 { 9045 uint32_t *p; 9046 9047 sbuf_printf(sb, "Status Data PC%s", 9048 cfg & F_UPDBGLACAPTPCONLY ? "" : 9049 " LS0Stat LS0Addr LS0Data"); 9050 9051 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 9052 if (cfg & F_UPDBGLACAPTPCONLY) { 9053 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 9054 p[6], p[7]); 9055 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 9056 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 9057 p[4] & 0xff, p[5] >> 8); 9058 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 9059 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9060 p[1] & 0xf, p[2] >> 4); 9061 } else { 9062 sbuf_printf(sb, 9063 "\n %02x %x%07x %x%07x %08x %08x " 9064 "%08x%08x%08x%08x", 9065 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9066 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 9067 p[6], p[7]); 9068 } 9069 } 9070 } 9071 9072 static void 9073 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9074 { 9075 uint32_t *p; 9076 9077 sbuf_printf(sb, "Status Inst Data PC%s", 9078 cfg & F_UPDBGLACAPTPCONLY ? "" : 9079 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 9080 9081 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 9082 if (cfg & F_UPDBGLACAPTPCONLY) { 9083 sbuf_printf(sb, "\n %02x %08x %08x %08x", 9084 p[3] & 0xff, p[2], p[1], p[0]); 9085 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 9086 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 9087 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 9088 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 9089 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 9090 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 9091 p[6] >> 16); 9092 } else { 9093 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 9094 "%08x %08x %08x %08x %08x %08x", 9095 (p[9] >> 16) & 0xff, 9096 p[9] & 0xffff, p[8] >> 16, 9097 p[8] & 0xffff, p[7] >> 16, 9098 p[7] & 0xffff, p[6] >> 16, 9099 p[2], p[1], p[0], p[5], p[4], p[3]); 9100 } 9101 } 9102 } 9103 9104 static int 9105 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 9106 { 9107 uint32_t cfg, *buf; 9108 int rc; 9109 9110 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9111 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 9112 M_ZERO | flags); 9113 if (buf == NULL) 9114 return (ENOMEM); 9115 9116 mtx_lock(&sc->reg_lock); 9117 if (hw_off_limits(sc)) 9118 rc = ENXIO; 9119 else { 9120 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9121 if (rc == 0) 9122 rc = -t4_cim_read_la(sc, buf, NULL); 9123 } 9124 mtx_unlock(&sc->reg_lock); 9125 if (rc == 0) { 9126 if (chip_id(sc) < CHELSIO_T6) 9127 sbuf_cim_la4(sc, sb, buf, cfg); 9128 else 9129 sbuf_cim_la6(sc, sb, buf, cfg); 9130 } 9131 free(buf, M_CXGBE); 9132 return (rc); 9133 } 9134 9135 static int 9136 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 9137 { 9138 struct adapter *sc = arg1; 9139 struct sbuf *sb; 9140 int rc; 9141 9142 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9143 if (sb == NULL) 9144 return (ENOMEM); 9145 9146 rc = sbuf_cim_la(sc, sb, M_WAITOK); 9147 if (rc == 0) 9148 rc = sbuf_finish(sb); 9149 sbuf_delete(sb); 9150 return (rc); 9151 } 9152 9153 static void 9154 dump_cim_regs(struct adapter *sc) 9155 { 9156 log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n", 9157 device_get_nameunit(sc->dev), 9158 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9159 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9160 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2), 9161 t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN), 9162 t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA)); 9163 log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n", 9164 device_get_nameunit(sc->dev), 9165 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9166 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9167 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800), 9168 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800), 9169 t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN)); 9170 } 9171 9172 static void 9173 dump_cimla(struct adapter *sc) 9174 { 9175 struct sbuf sb; 9176 int rc; 9177 9178 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9179 log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n", 9180 device_get_nameunit(sc->dev)); 9181 return; 9182 } 9183 rc = sbuf_cim_la(sc, &sb, M_WAITOK); 9184 if (rc == 0) { 9185 rc = sbuf_finish(&sb); 9186 if (rc == 0) { 9187 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n", 9188 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9189 } 9190 } 9191 sbuf_delete(&sb); 9192 } 9193 9194 void 9195 t4_os_cim_err(struct adapter *sc) 9196 { 9197 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 9198 } 9199 9200 static int 9201 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 9202 { 9203 struct adapter *sc = arg1; 9204 u_int i; 9205 struct sbuf *sb; 9206 uint32_t *buf, *p; 9207 int rc; 9208 9209 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9210 if (sb == NULL) 9211 return (ENOMEM); 9212 9213 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 9214 M_ZERO | M_WAITOK); 9215 9216 rc = 0; 9217 mtx_lock(&sc->reg_lock); 9218 if (hw_off_limits(sc)) 9219 rc = ENXIO; 9220 else 9221 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 9222 mtx_unlock(&sc->reg_lock); 9223 if (rc) 9224 goto done; 9225 9226 p = buf; 9227 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9228 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 9229 p[1], p[0]); 9230 } 9231 9232 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 9233 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9234 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 9235 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 9236 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 9237 (p[1] >> 2) | ((p[2] & 3) << 30), 9238 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 9239 p[0] & 1); 9240 } 9241 rc = sbuf_finish(sb); 9242 done: 9243 sbuf_delete(sb); 9244 free(buf, M_CXGBE); 9245 return (rc); 9246 } 9247 9248 static int 9249 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 9250 { 9251 struct adapter *sc = arg1; 9252 u_int i; 9253 struct sbuf *sb; 9254 uint32_t *buf, *p; 9255 int rc; 9256 9257 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9258 if (sb == NULL) 9259 return (ENOMEM); 9260 9261 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 9262 M_ZERO | M_WAITOK); 9263 9264 rc = 0; 9265 mtx_lock(&sc->reg_lock); 9266 if (hw_off_limits(sc)) 9267 rc = ENXIO; 9268 else 9269 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 9270 mtx_unlock(&sc->reg_lock); 9271 if (rc) 9272 goto done; 9273 9274 p = buf; 9275 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 9276 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9277 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 9278 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 9279 p[4], p[3], p[2], p[1], p[0]); 9280 } 9281 9282 sbuf_printf(sb, "\n\nCntl ID Data"); 9283 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9284 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 9285 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 9286 } 9287 9288 rc = sbuf_finish(sb); 9289 done: 9290 sbuf_delete(sb); 9291 free(buf, M_CXGBE); 9292 return (rc); 9293 } 9294 9295 static int 9296 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 9297 { 9298 struct adapter *sc = arg1; 9299 struct sbuf *sb; 9300 int rc, i; 9301 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9302 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9303 uint16_t thres[CIM_NUM_IBQ]; 9304 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 9305 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 9306 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 9307 9308 cim_num_obq = sc->chip_params->cim_num_obq; 9309 if (is_t4(sc)) { 9310 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 9311 obq_rdaddr = A_UP_OBQ_0_REALADDR; 9312 } else { 9313 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 9314 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 9315 } 9316 nq = CIM_NUM_IBQ + cim_num_obq; 9317 9318 mtx_lock(&sc->reg_lock); 9319 if (hw_off_limits(sc)) 9320 rc = ENXIO; 9321 else { 9322 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 9323 if (rc == 0) { 9324 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, 9325 obq_wr); 9326 if (rc == 0) 9327 t4_read_cimq_cfg(sc, base, size, thres); 9328 } 9329 } 9330 mtx_unlock(&sc->reg_lock); 9331 if (rc) 9332 return (rc); 9333 9334 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9335 if (sb == NULL) 9336 return (ENOMEM); 9337 9338 sbuf_printf(sb, 9339 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 9340 9341 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 9342 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 9343 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 9344 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9345 G_QUEREMFLITS(p[2]) * 16); 9346 for ( ; i < nq; i++, p += 4, wr += 2) 9347 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 9348 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 9349 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9350 G_QUEREMFLITS(p[2]) * 16); 9351 9352 rc = sbuf_finish(sb); 9353 sbuf_delete(sb); 9354 9355 return (rc); 9356 } 9357 9358 static int 9359 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 9360 { 9361 struct adapter *sc = arg1; 9362 struct sbuf *sb; 9363 int rc; 9364 struct tp_cpl_stats stats; 9365 9366 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9367 if (sb == NULL) 9368 return (ENOMEM); 9369 9370 rc = 0; 9371 mtx_lock(&sc->reg_lock); 9372 if (hw_off_limits(sc)) 9373 rc = ENXIO; 9374 else 9375 t4_tp_get_cpl_stats(sc, &stats, 0); 9376 mtx_unlock(&sc->reg_lock); 9377 if (rc) 9378 goto done; 9379 9380 if (sc->chip_params->nchan > 2) { 9381 sbuf_printf(sb, " channel 0 channel 1" 9382 " channel 2 channel 3"); 9383 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 9384 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 9385 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 9386 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 9387 } else { 9388 sbuf_printf(sb, " channel 0 channel 1"); 9389 sbuf_printf(sb, "\nCPL requests: %10u %10u", 9390 stats.req[0], stats.req[1]); 9391 sbuf_printf(sb, "\nCPL responses: %10u %10u", 9392 stats.rsp[0], stats.rsp[1]); 9393 } 9394 9395 rc = sbuf_finish(sb); 9396 done: 9397 sbuf_delete(sb); 9398 return (rc); 9399 } 9400 9401 static int 9402 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 9403 { 9404 struct adapter *sc = arg1; 9405 struct sbuf *sb; 9406 int rc; 9407 struct tp_usm_stats stats; 9408 9409 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9410 if (sb == NULL) 9411 return (ENOMEM); 9412 9413 rc = 0; 9414 mtx_lock(&sc->reg_lock); 9415 if (hw_off_limits(sc)) 9416 rc = ENXIO; 9417 else 9418 t4_get_usm_stats(sc, &stats, 1); 9419 mtx_unlock(&sc->reg_lock); 9420 if (rc == 0) { 9421 sbuf_printf(sb, "Frames: %u\n", stats.frames); 9422 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 9423 sbuf_printf(sb, "Drops: %u", stats.drops); 9424 rc = sbuf_finish(sb); 9425 } 9426 sbuf_delete(sb); 9427 9428 return (rc); 9429 } 9430 9431 static int 9432 sysctl_tid_stats(SYSCTL_HANDLER_ARGS) 9433 { 9434 struct adapter *sc = arg1; 9435 struct sbuf *sb; 9436 int rc; 9437 struct tp_tid_stats stats; 9438 9439 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9440 if (sb == NULL) 9441 return (ENOMEM); 9442 9443 rc = 0; 9444 mtx_lock(&sc->reg_lock); 9445 if (hw_off_limits(sc)) 9446 rc = ENXIO; 9447 else 9448 t4_tp_get_tid_stats(sc, &stats, 1); 9449 mtx_unlock(&sc->reg_lock); 9450 if (rc == 0) { 9451 sbuf_printf(sb, "Delete: %u\n", stats.del); 9452 sbuf_printf(sb, "Invalidate: %u\n", stats.inv); 9453 sbuf_printf(sb, "Active: %u\n", stats.act); 9454 sbuf_printf(sb, "Passive: %u", stats.pas); 9455 rc = sbuf_finish(sb); 9456 } 9457 sbuf_delete(sb); 9458 9459 return (rc); 9460 } 9461 9462 static const char * const devlog_level_strings[] = { 9463 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 9464 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 9465 [FW_DEVLOG_LEVEL_ERR] = "ERR", 9466 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 9467 [FW_DEVLOG_LEVEL_INFO] = "INFO", 9468 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 9469 }; 9470 9471 static const char * const devlog_facility_strings[] = { 9472 [FW_DEVLOG_FACILITY_CORE] = "CORE", 9473 [FW_DEVLOG_FACILITY_CF] = "CF", 9474 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 9475 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 9476 [FW_DEVLOG_FACILITY_RES] = "RES", 9477 [FW_DEVLOG_FACILITY_HW] = "HW", 9478 [FW_DEVLOG_FACILITY_FLR] = "FLR", 9479 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 9480 [FW_DEVLOG_FACILITY_PHY] = "PHY", 9481 [FW_DEVLOG_FACILITY_MAC] = "MAC", 9482 [FW_DEVLOG_FACILITY_PORT] = "PORT", 9483 [FW_DEVLOG_FACILITY_VI] = "VI", 9484 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 9485 [FW_DEVLOG_FACILITY_ACL] = "ACL", 9486 [FW_DEVLOG_FACILITY_TM] = "TM", 9487 [FW_DEVLOG_FACILITY_QFC] = "QFC", 9488 [FW_DEVLOG_FACILITY_DCB] = "DCB", 9489 [FW_DEVLOG_FACILITY_ETH] = "ETH", 9490 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 9491 [FW_DEVLOG_FACILITY_RI] = "RI", 9492 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 9493 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 9494 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 9495 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 9496 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 9497 }; 9498 9499 static int 9500 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 9501 { 9502 int i, j, rc, nentries, first = 0; 9503 struct devlog_params *dparams = &sc->params.devlog; 9504 struct fw_devlog_e *buf, *e; 9505 uint64_t ftstamp = UINT64_MAX; 9506 9507 if (dparams->addr == 0) 9508 return (ENXIO); 9509 9510 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9511 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 9512 if (buf == NULL) 9513 return (ENOMEM); 9514 9515 mtx_lock(&sc->reg_lock); 9516 if (hw_off_limits(sc)) 9517 rc = ENXIO; 9518 else 9519 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, 9520 dparams->size); 9521 mtx_unlock(&sc->reg_lock); 9522 if (rc != 0) 9523 goto done; 9524 9525 nentries = dparams->size / sizeof(struct fw_devlog_e); 9526 for (i = 0; i < nentries; i++) { 9527 e = &buf[i]; 9528 9529 if (e->timestamp == 0) 9530 break; /* end */ 9531 9532 e->timestamp = be64toh(e->timestamp); 9533 e->seqno = be32toh(e->seqno); 9534 for (j = 0; j < 8; j++) 9535 e->params[j] = be32toh(e->params[j]); 9536 9537 if (e->timestamp < ftstamp) { 9538 ftstamp = e->timestamp; 9539 first = i; 9540 } 9541 } 9542 9543 if (buf[first].timestamp == 0) 9544 goto done; /* nothing in the log */ 9545 9546 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 9547 "Seq#", "Tstamp", "Level", "Facility", "Message"); 9548 9549 i = first; 9550 do { 9551 e = &buf[i]; 9552 if (e->timestamp == 0) 9553 break; /* end */ 9554 9555 sbuf_printf(sb, "%10d %15ju %8s %8s ", 9556 e->seqno, e->timestamp, 9557 (e->level < nitems(devlog_level_strings) ? 9558 devlog_level_strings[e->level] : "UNKNOWN"), 9559 (e->facility < nitems(devlog_facility_strings) ? 9560 devlog_facility_strings[e->facility] : "UNKNOWN")); 9561 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 9562 e->params[2], e->params[3], e->params[4], 9563 e->params[5], e->params[6], e->params[7]); 9564 9565 if (++i == nentries) 9566 i = 0; 9567 } while (i != first); 9568 done: 9569 free(buf, M_CXGBE); 9570 return (rc); 9571 } 9572 9573 static int 9574 sysctl_devlog(SYSCTL_HANDLER_ARGS) 9575 { 9576 struct adapter *sc = arg1; 9577 int rc; 9578 struct sbuf *sb; 9579 9580 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9581 if (sb == NULL) 9582 return (ENOMEM); 9583 9584 rc = sbuf_devlog(sc, sb, M_WAITOK); 9585 if (rc == 0) 9586 rc = sbuf_finish(sb); 9587 sbuf_delete(sb); 9588 return (rc); 9589 } 9590 9591 static void 9592 dump_devlog(struct adapter *sc) 9593 { 9594 int rc; 9595 struct sbuf sb; 9596 9597 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9598 log(LOG_DEBUG, "%s: failed to generate devlog dump.\n", 9599 device_get_nameunit(sc->dev)); 9600 return; 9601 } 9602 rc = sbuf_devlog(sc, &sb, M_WAITOK); 9603 if (rc == 0) { 9604 rc = sbuf_finish(&sb); 9605 if (rc == 0) { 9606 log(LOG_DEBUG, "%s: device log follows.\n%s", 9607 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9608 } 9609 } 9610 sbuf_delete(&sb); 9611 } 9612 9613 static int 9614 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 9615 { 9616 struct adapter *sc = arg1; 9617 struct sbuf *sb; 9618 int rc; 9619 struct tp_fcoe_stats stats[MAX_NCHAN]; 9620 int i, nchan = sc->chip_params->nchan; 9621 9622 rc = 0; 9623 mtx_lock(&sc->reg_lock); 9624 if (hw_off_limits(sc)) 9625 rc = ENXIO; 9626 else { 9627 for (i = 0; i < nchan; i++) 9628 t4_get_fcoe_stats(sc, i, &stats[i], 1); 9629 } 9630 mtx_unlock(&sc->reg_lock); 9631 if (rc != 0) 9632 return (rc); 9633 9634 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9635 if (sb == NULL) 9636 return (ENOMEM); 9637 9638 if (nchan > 2) { 9639 sbuf_printf(sb, " channel 0 channel 1" 9640 " channel 2 channel 3"); 9641 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 9642 stats[0].octets_ddp, stats[1].octets_ddp, 9643 stats[2].octets_ddp, stats[3].octets_ddp); 9644 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 9645 stats[0].frames_ddp, stats[1].frames_ddp, 9646 stats[2].frames_ddp, stats[3].frames_ddp); 9647 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 9648 stats[0].frames_drop, stats[1].frames_drop, 9649 stats[2].frames_drop, stats[3].frames_drop); 9650 } else { 9651 sbuf_printf(sb, " channel 0 channel 1"); 9652 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 9653 stats[0].octets_ddp, stats[1].octets_ddp); 9654 sbuf_printf(sb, "\nframesDDP: %16u %16u", 9655 stats[0].frames_ddp, stats[1].frames_ddp); 9656 sbuf_printf(sb, "\nframesDrop: %16u %16u", 9657 stats[0].frames_drop, stats[1].frames_drop); 9658 } 9659 9660 rc = sbuf_finish(sb); 9661 sbuf_delete(sb); 9662 9663 return (rc); 9664 } 9665 9666 static int 9667 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 9668 { 9669 struct adapter *sc = arg1; 9670 struct sbuf *sb; 9671 int rc, i; 9672 unsigned int map, kbps, ipg, mode; 9673 unsigned int pace_tab[NTX_SCHED]; 9674 9675 sb = sbuf_new_for_sysctl(NULL, NULL, 512, req); 9676 if (sb == NULL) 9677 return (ENOMEM); 9678 9679 mtx_lock(&sc->reg_lock); 9680 if (hw_off_limits(sc)) { 9681 mtx_unlock(&sc->reg_lock); 9682 rc = ENXIO; 9683 goto done; 9684 } 9685 9686 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 9687 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 9688 t4_read_pace_tbl(sc, pace_tab); 9689 mtx_unlock(&sc->reg_lock); 9690 9691 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 9692 "Class IPG (0.1 ns) Flow IPG (us)"); 9693 9694 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 9695 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 9696 sbuf_printf(sb, "\n %u %-5s %u ", i, 9697 (mode & (1 << i)) ? "flow" : "class", map & 3); 9698 if (kbps) 9699 sbuf_printf(sb, "%9u ", kbps); 9700 else 9701 sbuf_printf(sb, " disabled "); 9702 9703 if (ipg) 9704 sbuf_printf(sb, "%13u ", ipg); 9705 else 9706 sbuf_printf(sb, " disabled "); 9707 9708 if (pace_tab[i]) 9709 sbuf_printf(sb, "%10u", pace_tab[i]); 9710 else 9711 sbuf_printf(sb, " disabled"); 9712 } 9713 rc = sbuf_finish(sb); 9714 done: 9715 sbuf_delete(sb); 9716 return (rc); 9717 } 9718 9719 static int 9720 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 9721 { 9722 struct adapter *sc = arg1; 9723 struct sbuf *sb; 9724 int rc, i, j; 9725 uint64_t *p0, *p1; 9726 struct lb_port_stats s[2]; 9727 static const char *stat_name[] = { 9728 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 9729 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 9730 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 9731 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 9732 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 9733 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 9734 "BG2FramesTrunc:", "BG3FramesTrunc:" 9735 }; 9736 9737 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9738 if (sb == NULL) 9739 return (ENOMEM); 9740 9741 memset(s, 0, sizeof(s)); 9742 9743 rc = 0; 9744 for (i = 0; i < sc->chip_params->nchan; i += 2) { 9745 mtx_lock(&sc->reg_lock); 9746 if (hw_off_limits(sc)) 9747 rc = ENXIO; 9748 else { 9749 t4_get_lb_stats(sc, i, &s[0]); 9750 t4_get_lb_stats(sc, i + 1, &s[1]); 9751 } 9752 mtx_unlock(&sc->reg_lock); 9753 if (rc != 0) 9754 break; 9755 9756 p0 = &s[0].octets; 9757 p1 = &s[1].octets; 9758 sbuf_printf(sb, "%s Loopback %u" 9759 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 9760 9761 for (j = 0; j < nitems(stat_name); j++) 9762 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 9763 *p0++, *p1++); 9764 } 9765 9766 if (rc == 0) 9767 rc = sbuf_finish(sb); 9768 sbuf_delete(sb); 9769 9770 return (rc); 9771 } 9772 9773 static int 9774 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 9775 { 9776 int rc = 0; 9777 struct port_info *pi = arg1; 9778 struct link_config *lc = &pi->link_cfg; 9779 struct sbuf *sb; 9780 9781 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 9782 if (sb == NULL) 9783 return (ENOMEM); 9784 9785 if (lc->link_ok || lc->link_down_rc == 255) 9786 sbuf_printf(sb, "n/a"); 9787 else 9788 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 9789 9790 rc = sbuf_finish(sb); 9791 sbuf_delete(sb); 9792 9793 return (rc); 9794 } 9795 9796 struct mem_desc { 9797 u_int base; 9798 u_int limit; 9799 u_int idx; 9800 }; 9801 9802 static int 9803 mem_desc_cmp(const void *a, const void *b) 9804 { 9805 const u_int v1 = ((const struct mem_desc *)a)->base; 9806 const u_int v2 = ((const struct mem_desc *)b)->base; 9807 9808 if (v1 < v2) 9809 return (-1); 9810 else if (v1 > v2) 9811 return (1); 9812 9813 return (0); 9814 } 9815 9816 static void 9817 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 9818 unsigned int to) 9819 { 9820 unsigned int size; 9821 9822 if (from == to) 9823 return; 9824 9825 size = to - from + 1; 9826 if (size == 0) 9827 return; 9828 9829 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 9830 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 9831 } 9832 9833 static int 9834 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 9835 { 9836 struct adapter *sc = arg1; 9837 struct sbuf *sb; 9838 int rc, i, n; 9839 uint32_t lo, hi, used, free, alloc; 9840 static const char *memory[] = { 9841 "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:" 9842 }; 9843 static const char *region[] = { 9844 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 9845 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 9846 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 9847 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 9848 "RQUDP region:", "PBL region:", "TXPBL region:", 9849 "TLSKey region:", "DBVFIFO region:", "ULPRX state:", 9850 "ULPTX state:", "On-chip queues:", 9851 }; 9852 struct mem_desc avail[4]; 9853 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 9854 struct mem_desc *md = mem; 9855 9856 rc = sysctl_wire_old_buffer(req, 0); 9857 if (rc != 0) 9858 return (rc); 9859 9860 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9861 if (sb == NULL) 9862 return (ENOMEM); 9863 9864 for (i = 0; i < nitems(mem); i++) { 9865 mem[i].limit = 0; 9866 mem[i].idx = i; 9867 } 9868 9869 mtx_lock(&sc->reg_lock); 9870 if (hw_off_limits(sc)) { 9871 rc = ENXIO; 9872 goto done; 9873 } 9874 9875 /* Find and sort the populated memory ranges */ 9876 i = 0; 9877 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 9878 if (lo & F_EDRAM0_ENABLE) { 9879 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 9880 avail[i].base = G_EDRAM0_BASE(hi) << 20; 9881 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 9882 avail[i].idx = 0; 9883 i++; 9884 } 9885 if (lo & F_EDRAM1_ENABLE) { 9886 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 9887 avail[i].base = G_EDRAM1_BASE(hi) << 20; 9888 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 9889 avail[i].idx = 1; 9890 i++; 9891 } 9892 if (lo & F_EXT_MEM_ENABLE) { 9893 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 9894 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 9895 avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20); 9896 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 9897 i++; 9898 } 9899 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 9900 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9901 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9902 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9903 avail[i].idx = 4; 9904 i++; 9905 } 9906 if (is_t6(sc) && lo & F_HMA_MUX) { 9907 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9908 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9909 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9910 avail[i].idx = 5; 9911 i++; 9912 } 9913 MPASS(i <= nitems(avail)); 9914 if (!i) /* no memory available */ 9915 goto done; 9916 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 9917 9918 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 9919 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 9920 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 9921 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9922 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 9923 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 9924 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 9925 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 9926 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 9927 9928 /* the next few have explicit upper bounds */ 9929 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 9930 md->limit = md->base - 1 + 9931 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 9932 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 9933 md++; 9934 9935 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 9936 md->limit = md->base - 1 + 9937 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 9938 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 9939 md++; 9940 9941 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 9942 if (chip_id(sc) <= CHELSIO_T5) 9943 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 9944 else 9945 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 9946 md->limit = 0; 9947 } else { 9948 md->base = 0; 9949 md->idx = nitems(region); /* hide it */ 9950 } 9951 md++; 9952 9953 #define ulp_region(reg) \ 9954 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 9955 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 9956 9957 ulp_region(RX_ISCSI); 9958 ulp_region(RX_TDDP); 9959 ulp_region(TX_TPT); 9960 ulp_region(RX_STAG); 9961 ulp_region(RX_RQ); 9962 ulp_region(RX_RQUDP); 9963 ulp_region(RX_PBL); 9964 ulp_region(TX_PBL); 9965 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 9966 ulp_region(RX_TLS_KEY); 9967 } 9968 #undef ulp_region 9969 9970 md->base = 0; 9971 if (is_t4(sc)) 9972 md->idx = nitems(region); 9973 else { 9974 uint32_t size = 0; 9975 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 9976 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 9977 9978 if (is_t5(sc)) { 9979 if (sge_ctrl & F_VFIFO_ENABLE) 9980 size = fifo_size << 2; 9981 } else 9982 size = G_T6_DBVFIFO_SIZE(fifo_size) << 6; 9983 9984 if (size) { 9985 md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR); 9986 md->limit = md->base + size - 1; 9987 } else 9988 md->idx = nitems(region); 9989 } 9990 md++; 9991 9992 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 9993 md->limit = 0; 9994 md++; 9995 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 9996 md->limit = 0; 9997 md++; 9998 9999 md->base = sc->vres.ocq.start; 10000 if (sc->vres.ocq.size) 10001 md->limit = md->base + sc->vres.ocq.size - 1; 10002 else 10003 md->idx = nitems(region); /* hide it */ 10004 md++; 10005 10006 /* add any address-space holes, there can be up to 3 */ 10007 for (n = 0; n < i - 1; n++) 10008 if (avail[n].limit < avail[n + 1].base) 10009 (md++)->base = avail[n].limit; 10010 if (avail[n].limit) 10011 (md++)->base = avail[n].limit; 10012 10013 n = md - mem; 10014 MPASS(n <= nitems(mem)); 10015 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 10016 10017 for (lo = 0; lo < i; lo++) 10018 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 10019 avail[lo].limit - 1); 10020 10021 sbuf_printf(sb, "\n"); 10022 for (i = 0; i < n; i++) { 10023 if (mem[i].idx >= nitems(region)) 10024 continue; /* skip holes */ 10025 if (!mem[i].limit) 10026 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 10027 mem_region_show(sb, region[mem[i].idx], mem[i].base, 10028 mem[i].limit); 10029 } 10030 10031 sbuf_printf(sb, "\n"); 10032 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 10033 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 10034 mem_region_show(sb, "uP RAM:", lo, hi); 10035 10036 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 10037 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 10038 mem_region_show(sb, "uP Extmem2:", lo, hi); 10039 10040 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 10041 for (i = 0, free = 0; i < 2; i++) 10042 free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT)); 10043 sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n", 10044 G_PMRXMAXPAGE(lo), free, 10045 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 10046 (lo & F_PMRXNUMCHN) ? 2 : 1); 10047 10048 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 10049 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 10050 for (i = 0, free = 0; i < 4; i++) 10051 free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT)); 10052 sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n", 10053 G_PMTXMAXPAGE(lo), free, 10054 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 10055 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 10056 sbuf_printf(sb, "%u p-structs (%u free)\n", 10057 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT), 10058 G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT))); 10059 10060 for (i = 0; i < 4; i++) { 10061 if (chip_id(sc) > CHELSIO_T5) 10062 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 10063 else 10064 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 10065 if (is_t5(sc)) { 10066 used = G_T5_USED(lo); 10067 alloc = G_T5_ALLOC(lo); 10068 } else { 10069 used = G_USED(lo); 10070 alloc = G_ALLOC(lo); 10071 } 10072 /* For T6 these are MAC buffer groups */ 10073 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 10074 i, used, alloc); 10075 } 10076 for (i = 0; i < sc->chip_params->nchan; i++) { 10077 if (chip_id(sc) > CHELSIO_T5) 10078 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 10079 else 10080 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 10081 if (is_t5(sc)) { 10082 used = G_T5_USED(lo); 10083 alloc = G_T5_ALLOC(lo); 10084 } else { 10085 used = G_USED(lo); 10086 alloc = G_ALLOC(lo); 10087 } 10088 /* For T6 these are MAC buffer groups */ 10089 sbuf_printf(sb, 10090 "\nLoopback %d using %u pages out of %u allocated", 10091 i, used, alloc); 10092 } 10093 done: 10094 mtx_unlock(&sc->reg_lock); 10095 if (rc == 0) 10096 rc = sbuf_finish(sb); 10097 sbuf_delete(sb); 10098 return (rc); 10099 } 10100 10101 static inline void 10102 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 10103 { 10104 *mask = x | y; 10105 y = htobe64(y); 10106 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 10107 } 10108 10109 static int 10110 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 10111 { 10112 struct adapter *sc = arg1; 10113 struct sbuf *sb; 10114 int rc, i; 10115 10116 MPASS(chip_id(sc) <= CHELSIO_T5); 10117 10118 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10119 if (sb == NULL) 10120 return (ENOMEM); 10121 10122 sbuf_printf(sb, 10123 "Idx Ethernet address Mask Vld Ports PF" 10124 " VF Replication P0 P1 P2 P3 ML"); 10125 rc = 0; 10126 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10127 uint64_t tcamx, tcamy, mask; 10128 uint32_t cls_lo, cls_hi; 10129 uint8_t addr[ETHER_ADDR_LEN]; 10130 10131 mtx_lock(&sc->reg_lock); 10132 if (hw_off_limits(sc)) 10133 rc = ENXIO; 10134 else { 10135 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 10136 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 10137 } 10138 mtx_unlock(&sc->reg_lock); 10139 if (rc != 0) 10140 break; 10141 if (tcamx & tcamy) 10142 continue; 10143 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10144 mtx_lock(&sc->reg_lock); 10145 if (hw_off_limits(sc)) 10146 rc = ENXIO; 10147 else { 10148 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10149 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10150 } 10151 mtx_unlock(&sc->reg_lock); 10152 if (rc != 0) 10153 break; 10154 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 10155 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 10156 addr[3], addr[4], addr[5], (uintmax_t)mask, 10157 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 10158 G_PORTMAP(cls_hi), G_PF(cls_lo), 10159 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 10160 10161 if (cls_lo & F_REPLICATE) { 10162 struct fw_ldst_cmd ldst_cmd; 10163 10164 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10165 ldst_cmd.op_to_addrspace = 10166 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10167 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10168 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10169 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10170 ldst_cmd.u.mps.rplc.fid_idx = 10171 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10172 V_FW_LDST_CMD_IDX(i)); 10173 10174 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10175 "t4mps"); 10176 if (rc) 10177 break; 10178 if (hw_off_limits(sc)) 10179 rc = ENXIO; 10180 else 10181 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10182 sizeof(ldst_cmd), &ldst_cmd); 10183 end_synchronized_op(sc, 0); 10184 if (rc != 0) 10185 break; 10186 else { 10187 sbuf_printf(sb, " %08x %08x %08x %08x", 10188 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10189 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10190 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10191 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10192 } 10193 } else 10194 sbuf_printf(sb, "%36s", ""); 10195 10196 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 10197 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 10198 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 10199 } 10200 10201 if (rc) 10202 (void) sbuf_finish(sb); 10203 else 10204 rc = sbuf_finish(sb); 10205 sbuf_delete(sb); 10206 10207 return (rc); 10208 } 10209 10210 static int 10211 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 10212 { 10213 struct adapter *sc = arg1; 10214 struct sbuf *sb; 10215 int rc, i; 10216 10217 MPASS(chip_id(sc) > CHELSIO_T5); 10218 10219 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10220 if (sb == NULL) 10221 return (ENOMEM); 10222 10223 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 10224 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 10225 " Replication" 10226 " P0 P1 P2 P3 ML\n"); 10227 10228 rc = 0; 10229 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10230 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 10231 uint16_t ivlan; 10232 uint64_t tcamx, tcamy, val, mask; 10233 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 10234 uint8_t addr[ETHER_ADDR_LEN]; 10235 10236 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 10237 if (i < 256) 10238 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 10239 else 10240 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 10241 mtx_lock(&sc->reg_lock); 10242 if (hw_off_limits(sc)) 10243 rc = ENXIO; 10244 else { 10245 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10246 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10247 tcamy = G_DMACH(val) << 32; 10248 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10249 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10250 } 10251 mtx_unlock(&sc->reg_lock); 10252 if (rc != 0) 10253 break; 10254 10255 lookup_type = G_DATALKPTYPE(data2); 10256 port_num = G_DATAPORTNUM(data2); 10257 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10258 /* Inner header VNI */ 10259 vniy = ((data2 & F_DATAVIDH2) << 23) | 10260 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10261 dip_hit = data2 & F_DATADIPHIT; 10262 vlan_vld = 0; 10263 } else { 10264 vniy = 0; 10265 dip_hit = 0; 10266 vlan_vld = data2 & F_DATAVIDH2; 10267 ivlan = G_VIDL(val); 10268 } 10269 10270 ctl |= V_CTLXYBITSEL(1); 10271 mtx_lock(&sc->reg_lock); 10272 if (hw_off_limits(sc)) 10273 rc = ENXIO; 10274 else { 10275 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10276 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10277 tcamx = G_DMACH(val) << 32; 10278 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10279 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10280 } 10281 mtx_unlock(&sc->reg_lock); 10282 if (rc != 0) 10283 break; 10284 10285 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10286 /* Inner header VNI mask */ 10287 vnix = ((data2 & F_DATAVIDH2) << 23) | 10288 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10289 } else 10290 vnix = 0; 10291 10292 if (tcamx & tcamy) 10293 continue; 10294 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10295 10296 mtx_lock(&sc->reg_lock); 10297 if (hw_off_limits(sc)) 10298 rc = ENXIO; 10299 else { 10300 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10301 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10302 } 10303 mtx_unlock(&sc->reg_lock); 10304 if (rc != 0) 10305 break; 10306 10307 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10308 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10309 "%012jx %06x %06x - - %3c" 10310 " I %4x %3c %#x%4u%4d", i, addr[0], 10311 addr[1], addr[2], addr[3], addr[4], addr[5], 10312 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 10313 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10314 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10315 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10316 } else { 10317 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10318 "%012jx - - ", i, addr[0], addr[1], 10319 addr[2], addr[3], addr[4], addr[5], 10320 (uintmax_t)mask); 10321 10322 if (vlan_vld) 10323 sbuf_printf(sb, "%4u Y ", ivlan); 10324 else 10325 sbuf_printf(sb, " - N "); 10326 10327 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 10328 lookup_type ? 'I' : 'O', port_num, 10329 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10330 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10331 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10332 } 10333 10334 10335 if (cls_lo & F_T6_REPLICATE) { 10336 struct fw_ldst_cmd ldst_cmd; 10337 10338 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10339 ldst_cmd.op_to_addrspace = 10340 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10341 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10342 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10343 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10344 ldst_cmd.u.mps.rplc.fid_idx = 10345 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10346 V_FW_LDST_CMD_IDX(i)); 10347 10348 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10349 "t6mps"); 10350 if (rc) 10351 break; 10352 if (hw_off_limits(sc)) 10353 rc = ENXIO; 10354 else 10355 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10356 sizeof(ldst_cmd), &ldst_cmd); 10357 end_synchronized_op(sc, 0); 10358 if (rc != 0) 10359 break; 10360 else { 10361 sbuf_printf(sb, " %08x %08x %08x %08x" 10362 " %08x %08x %08x %08x", 10363 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 10364 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 10365 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 10366 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 10367 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10368 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10369 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10370 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10371 } 10372 } else 10373 sbuf_printf(sb, "%72s", ""); 10374 10375 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 10376 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 10377 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 10378 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 10379 } 10380 10381 if (rc) 10382 (void) sbuf_finish(sb); 10383 else 10384 rc = sbuf_finish(sb); 10385 sbuf_delete(sb); 10386 10387 return (rc); 10388 } 10389 10390 static int 10391 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 10392 { 10393 struct adapter *sc = arg1; 10394 struct sbuf *sb; 10395 int rc; 10396 uint16_t mtus[NMTUS]; 10397 10398 rc = 0; 10399 mtx_lock(&sc->reg_lock); 10400 if (hw_off_limits(sc)) 10401 rc = ENXIO; 10402 else 10403 t4_read_mtu_tbl(sc, mtus, NULL); 10404 mtx_unlock(&sc->reg_lock); 10405 if (rc != 0) 10406 return (rc); 10407 10408 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10409 if (sb == NULL) 10410 return (ENOMEM); 10411 10412 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 10413 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 10414 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 10415 mtus[14], mtus[15]); 10416 10417 rc = sbuf_finish(sb); 10418 sbuf_delete(sb); 10419 10420 return (rc); 10421 } 10422 10423 static int 10424 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 10425 { 10426 struct adapter *sc = arg1; 10427 struct sbuf *sb; 10428 int rc, i; 10429 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 10430 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 10431 static const char *tx_stats[MAX_PM_NSTATS] = { 10432 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 10433 "Tx FIFO wait", NULL, "Tx latency" 10434 }; 10435 static const char *rx_stats[MAX_PM_NSTATS] = { 10436 "Read:", "Write bypass:", "Write mem:", "Flush:", 10437 "Rx FIFO wait", NULL, "Rx latency" 10438 }; 10439 10440 rc = 0; 10441 mtx_lock(&sc->reg_lock); 10442 if (hw_off_limits(sc)) 10443 rc = ENXIO; 10444 else { 10445 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 10446 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 10447 } 10448 mtx_unlock(&sc->reg_lock); 10449 if (rc != 0) 10450 return (rc); 10451 10452 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10453 if (sb == NULL) 10454 return (ENOMEM); 10455 10456 sbuf_printf(sb, " Tx pcmds Tx bytes"); 10457 for (i = 0; i < 4; i++) { 10458 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10459 tx_cyc[i]); 10460 } 10461 10462 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 10463 for (i = 0; i < 4; i++) { 10464 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10465 rx_cyc[i]); 10466 } 10467 10468 if (chip_id(sc) > CHELSIO_T5) { 10469 sbuf_printf(sb, 10470 "\n Total wait Total occupancy"); 10471 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10472 tx_cyc[i]); 10473 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10474 rx_cyc[i]); 10475 10476 i += 2; 10477 MPASS(i < nitems(tx_stats)); 10478 10479 sbuf_printf(sb, 10480 "\n Reads Total wait"); 10481 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10482 tx_cyc[i]); 10483 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10484 rx_cyc[i]); 10485 } 10486 10487 rc = sbuf_finish(sb); 10488 sbuf_delete(sb); 10489 10490 return (rc); 10491 } 10492 10493 static int 10494 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 10495 { 10496 struct adapter *sc = arg1; 10497 struct sbuf *sb; 10498 int rc; 10499 struct tp_rdma_stats stats; 10500 10501 rc = 0; 10502 mtx_lock(&sc->reg_lock); 10503 if (hw_off_limits(sc)) 10504 rc = ENXIO; 10505 else 10506 t4_tp_get_rdma_stats(sc, &stats, 0); 10507 mtx_unlock(&sc->reg_lock); 10508 if (rc != 0) 10509 return (rc); 10510 10511 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10512 if (sb == NULL) 10513 return (ENOMEM); 10514 10515 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 10516 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 10517 10518 rc = sbuf_finish(sb); 10519 sbuf_delete(sb); 10520 10521 return (rc); 10522 } 10523 10524 static int 10525 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 10526 { 10527 struct adapter *sc = arg1; 10528 struct sbuf *sb; 10529 int rc; 10530 struct tp_tcp_stats v4, v6; 10531 10532 rc = 0; 10533 mtx_lock(&sc->reg_lock); 10534 if (hw_off_limits(sc)) 10535 rc = ENXIO; 10536 else 10537 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 10538 mtx_unlock(&sc->reg_lock); 10539 if (rc != 0) 10540 return (rc); 10541 10542 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10543 if (sb == NULL) 10544 return (ENOMEM); 10545 10546 sbuf_printf(sb, 10547 " IP IPv6\n"); 10548 sbuf_printf(sb, "OutRsts: %20u %20u\n", 10549 v4.tcp_out_rsts, v6.tcp_out_rsts); 10550 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 10551 v4.tcp_in_segs, v6.tcp_in_segs); 10552 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 10553 v4.tcp_out_segs, v6.tcp_out_segs); 10554 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 10555 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 10556 10557 rc = sbuf_finish(sb); 10558 sbuf_delete(sb); 10559 10560 return (rc); 10561 } 10562 10563 static int 10564 sysctl_tids(SYSCTL_HANDLER_ARGS) 10565 { 10566 struct adapter *sc = arg1; 10567 struct sbuf *sb; 10568 int rc; 10569 uint32_t x, y; 10570 struct tid_info *t = &sc->tids; 10571 10572 rc = 0; 10573 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10574 if (sb == NULL) 10575 return (ENOMEM); 10576 10577 if (t->natids) { 10578 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 10579 t->atids_in_use); 10580 } 10581 10582 if (t->nhpftids) { 10583 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 10584 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 10585 } 10586 10587 if (t->ntids) { 10588 bool hashen = false; 10589 10590 mtx_lock(&sc->reg_lock); 10591 if (hw_off_limits(sc)) 10592 rc = ENXIO; 10593 else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 10594 hashen = true; 10595 if (chip_id(sc) <= CHELSIO_T5) { 10596 x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 10597 y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 10598 } else { 10599 x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 10600 y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 10601 } 10602 } 10603 mtx_unlock(&sc->reg_lock); 10604 if (rc != 0) 10605 goto done; 10606 10607 sbuf_printf(sb, "TID range: "); 10608 if (hashen) { 10609 if (x) 10610 sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1); 10611 sbuf_printf(sb, "%u-%u", y, t->ntids - 1); 10612 } else { 10613 sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base + 10614 t->ntids - 1); 10615 } 10616 sbuf_printf(sb, ", in use: %u\n", 10617 atomic_load_acq_int(&t->tids_in_use)); 10618 } 10619 10620 if (t->nstids) { 10621 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 10622 t->stid_base + t->nstids - 1, t->stids_in_use); 10623 } 10624 10625 if (t->nftids) { 10626 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 10627 t->ftid_end, t->ftids_in_use); 10628 } 10629 10630 if (t->netids) { 10631 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 10632 t->etid_base + t->netids - 1, t->etids_in_use); 10633 } 10634 10635 mtx_lock(&sc->reg_lock); 10636 if (hw_off_limits(sc)) 10637 rc = ENXIO; 10638 else { 10639 x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4); 10640 y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6); 10641 } 10642 mtx_unlock(&sc->reg_lock); 10643 if (rc != 0) 10644 goto done; 10645 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y); 10646 done: 10647 if (rc == 0) 10648 rc = sbuf_finish(sb); 10649 else 10650 (void)sbuf_finish(sb); 10651 sbuf_delete(sb); 10652 10653 return (rc); 10654 } 10655 10656 static int 10657 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 10658 { 10659 struct adapter *sc = arg1; 10660 struct sbuf *sb; 10661 int rc; 10662 struct tp_err_stats stats; 10663 10664 rc = 0; 10665 mtx_lock(&sc->reg_lock); 10666 if (hw_off_limits(sc)) 10667 rc = ENXIO; 10668 else 10669 t4_tp_get_err_stats(sc, &stats, 0); 10670 mtx_unlock(&sc->reg_lock); 10671 if (rc != 0) 10672 return (rc); 10673 10674 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10675 if (sb == NULL) 10676 return (ENOMEM); 10677 10678 if (sc->chip_params->nchan > 2) { 10679 sbuf_printf(sb, " channel 0 channel 1" 10680 " channel 2 channel 3\n"); 10681 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 10682 stats.mac_in_errs[0], stats.mac_in_errs[1], 10683 stats.mac_in_errs[2], stats.mac_in_errs[3]); 10684 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 10685 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 10686 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 10687 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 10688 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 10689 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 10690 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 10691 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 10692 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 10693 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 10694 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 10695 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 10696 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 10697 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 10698 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 10699 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 10700 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 10701 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 10702 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 10703 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 10704 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 10705 } else { 10706 sbuf_printf(sb, " channel 0 channel 1\n"); 10707 sbuf_printf(sb, "macInErrs: %10u %10u\n", 10708 stats.mac_in_errs[0], stats.mac_in_errs[1]); 10709 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 10710 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 10711 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 10712 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 10713 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 10714 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 10715 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 10716 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 10717 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 10718 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 10719 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 10720 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 10721 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 10722 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 10723 } 10724 10725 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 10726 stats.ofld_no_neigh, stats.ofld_cong_defer); 10727 10728 rc = sbuf_finish(sb); 10729 sbuf_delete(sb); 10730 10731 return (rc); 10732 } 10733 10734 static int 10735 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS) 10736 { 10737 struct adapter *sc = arg1; 10738 struct sbuf *sb; 10739 int rc; 10740 struct tp_tnl_stats stats; 10741 10742 rc = 0; 10743 mtx_lock(&sc->reg_lock); 10744 if (hw_off_limits(sc)) 10745 rc = ENXIO; 10746 else 10747 t4_tp_get_tnl_stats(sc, &stats, 1); 10748 mtx_unlock(&sc->reg_lock); 10749 if (rc != 0) 10750 return (rc); 10751 10752 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10753 if (sb == NULL) 10754 return (ENOMEM); 10755 10756 if (sc->chip_params->nchan > 2) { 10757 sbuf_printf(sb, " channel 0 channel 1" 10758 " channel 2 channel 3\n"); 10759 sbuf_printf(sb, "OutPkts: %10u %10u %10u %10u\n", 10760 stats.out_pkt[0], stats.out_pkt[1], 10761 stats.out_pkt[2], stats.out_pkt[3]); 10762 sbuf_printf(sb, "InPkts: %10u %10u %10u %10u", 10763 stats.in_pkt[0], stats.in_pkt[1], 10764 stats.in_pkt[2], stats.in_pkt[3]); 10765 } else { 10766 sbuf_printf(sb, " channel 0 channel 1\n"); 10767 sbuf_printf(sb, "OutPkts: %10u %10u\n", 10768 stats.out_pkt[0], stats.out_pkt[1]); 10769 sbuf_printf(sb, "InPkts: %10u %10u", 10770 stats.in_pkt[0], stats.in_pkt[1]); 10771 } 10772 10773 rc = sbuf_finish(sb); 10774 sbuf_delete(sb); 10775 10776 return (rc); 10777 } 10778 10779 static int 10780 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 10781 { 10782 struct adapter *sc = arg1; 10783 struct tp_params *tpp = &sc->params.tp; 10784 u_int mask; 10785 int rc; 10786 10787 mask = tpp->la_mask >> 16; 10788 rc = sysctl_handle_int(oidp, &mask, 0, req); 10789 if (rc != 0 || req->newptr == NULL) 10790 return (rc); 10791 if (mask > 0xffff) 10792 return (EINVAL); 10793 mtx_lock(&sc->reg_lock); 10794 if (hw_off_limits(sc)) 10795 rc = ENXIO; 10796 else { 10797 tpp->la_mask = mask << 16; 10798 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, 10799 tpp->la_mask); 10800 } 10801 mtx_unlock(&sc->reg_lock); 10802 10803 return (rc); 10804 } 10805 10806 struct field_desc { 10807 const char *name; 10808 u_int start; 10809 u_int width; 10810 }; 10811 10812 static void 10813 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 10814 { 10815 char buf[32]; 10816 int line_size = 0; 10817 10818 while (f->name) { 10819 uint64_t mask = (1ULL << f->width) - 1; 10820 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 10821 ((uintmax_t)v >> f->start) & mask); 10822 10823 if (line_size + len >= 79) { 10824 line_size = 8; 10825 sbuf_printf(sb, "\n "); 10826 } 10827 sbuf_printf(sb, "%s ", buf); 10828 line_size += len + 1; 10829 f++; 10830 } 10831 sbuf_printf(sb, "\n"); 10832 } 10833 10834 static const struct field_desc tp_la0[] = { 10835 { "RcfOpCodeOut", 60, 4 }, 10836 { "State", 56, 4 }, 10837 { "WcfState", 52, 4 }, 10838 { "RcfOpcSrcOut", 50, 2 }, 10839 { "CRxError", 49, 1 }, 10840 { "ERxError", 48, 1 }, 10841 { "SanityFailed", 47, 1 }, 10842 { "SpuriousMsg", 46, 1 }, 10843 { "FlushInputMsg", 45, 1 }, 10844 { "FlushInputCpl", 44, 1 }, 10845 { "RssUpBit", 43, 1 }, 10846 { "RssFilterHit", 42, 1 }, 10847 { "Tid", 32, 10 }, 10848 { "InitTcb", 31, 1 }, 10849 { "LineNumber", 24, 7 }, 10850 { "Emsg", 23, 1 }, 10851 { "EdataOut", 22, 1 }, 10852 { "Cmsg", 21, 1 }, 10853 { "CdataOut", 20, 1 }, 10854 { "EreadPdu", 19, 1 }, 10855 { "CreadPdu", 18, 1 }, 10856 { "TunnelPkt", 17, 1 }, 10857 { "RcfPeerFin", 16, 1 }, 10858 { "RcfReasonOut", 12, 4 }, 10859 { "TxCchannel", 10, 2 }, 10860 { "RcfTxChannel", 8, 2 }, 10861 { "RxEchannel", 6, 2 }, 10862 { "RcfRxChannel", 5, 1 }, 10863 { "RcfDataOutSrdy", 4, 1 }, 10864 { "RxDvld", 3, 1 }, 10865 { "RxOoDvld", 2, 1 }, 10866 { "RxCongestion", 1, 1 }, 10867 { "TxCongestion", 0, 1 }, 10868 { NULL } 10869 }; 10870 10871 static const struct field_desc tp_la1[] = { 10872 { "CplCmdIn", 56, 8 }, 10873 { "CplCmdOut", 48, 8 }, 10874 { "ESynOut", 47, 1 }, 10875 { "EAckOut", 46, 1 }, 10876 { "EFinOut", 45, 1 }, 10877 { "ERstOut", 44, 1 }, 10878 { "SynIn", 43, 1 }, 10879 { "AckIn", 42, 1 }, 10880 { "FinIn", 41, 1 }, 10881 { "RstIn", 40, 1 }, 10882 { "DataIn", 39, 1 }, 10883 { "DataInVld", 38, 1 }, 10884 { "PadIn", 37, 1 }, 10885 { "RxBufEmpty", 36, 1 }, 10886 { "RxDdp", 35, 1 }, 10887 { "RxFbCongestion", 34, 1 }, 10888 { "TxFbCongestion", 33, 1 }, 10889 { "TxPktSumSrdy", 32, 1 }, 10890 { "RcfUlpType", 28, 4 }, 10891 { "Eread", 27, 1 }, 10892 { "Ebypass", 26, 1 }, 10893 { "Esave", 25, 1 }, 10894 { "Static0", 24, 1 }, 10895 { "Cread", 23, 1 }, 10896 { "Cbypass", 22, 1 }, 10897 { "Csave", 21, 1 }, 10898 { "CPktOut", 20, 1 }, 10899 { "RxPagePoolFull", 18, 2 }, 10900 { "RxLpbkPkt", 17, 1 }, 10901 { "TxLpbkPkt", 16, 1 }, 10902 { "RxVfValid", 15, 1 }, 10903 { "SynLearned", 14, 1 }, 10904 { "SetDelEntry", 13, 1 }, 10905 { "SetInvEntry", 12, 1 }, 10906 { "CpcmdDvld", 11, 1 }, 10907 { "CpcmdSave", 10, 1 }, 10908 { "RxPstructsFull", 8, 2 }, 10909 { "EpcmdDvld", 7, 1 }, 10910 { "EpcmdFlush", 6, 1 }, 10911 { "EpcmdTrimPrefix", 5, 1 }, 10912 { "EpcmdTrimPostfix", 4, 1 }, 10913 { "ERssIp4Pkt", 3, 1 }, 10914 { "ERssIp6Pkt", 2, 1 }, 10915 { "ERssTcpUdpPkt", 1, 1 }, 10916 { "ERssFceFipPkt", 0, 1 }, 10917 { NULL } 10918 }; 10919 10920 static const struct field_desc tp_la2[] = { 10921 { "CplCmdIn", 56, 8 }, 10922 { "MpsVfVld", 55, 1 }, 10923 { "MpsPf", 52, 3 }, 10924 { "MpsVf", 44, 8 }, 10925 { "SynIn", 43, 1 }, 10926 { "AckIn", 42, 1 }, 10927 { "FinIn", 41, 1 }, 10928 { "RstIn", 40, 1 }, 10929 { "DataIn", 39, 1 }, 10930 { "DataInVld", 38, 1 }, 10931 { "PadIn", 37, 1 }, 10932 { "RxBufEmpty", 36, 1 }, 10933 { "RxDdp", 35, 1 }, 10934 { "RxFbCongestion", 34, 1 }, 10935 { "TxFbCongestion", 33, 1 }, 10936 { "TxPktSumSrdy", 32, 1 }, 10937 { "RcfUlpType", 28, 4 }, 10938 { "Eread", 27, 1 }, 10939 { "Ebypass", 26, 1 }, 10940 { "Esave", 25, 1 }, 10941 { "Static0", 24, 1 }, 10942 { "Cread", 23, 1 }, 10943 { "Cbypass", 22, 1 }, 10944 { "Csave", 21, 1 }, 10945 { "CPktOut", 20, 1 }, 10946 { "RxPagePoolFull", 18, 2 }, 10947 { "RxLpbkPkt", 17, 1 }, 10948 { "TxLpbkPkt", 16, 1 }, 10949 { "RxVfValid", 15, 1 }, 10950 { "SynLearned", 14, 1 }, 10951 { "SetDelEntry", 13, 1 }, 10952 { "SetInvEntry", 12, 1 }, 10953 { "CpcmdDvld", 11, 1 }, 10954 { "CpcmdSave", 10, 1 }, 10955 { "RxPstructsFull", 8, 2 }, 10956 { "EpcmdDvld", 7, 1 }, 10957 { "EpcmdFlush", 6, 1 }, 10958 { "EpcmdTrimPrefix", 5, 1 }, 10959 { "EpcmdTrimPostfix", 4, 1 }, 10960 { "ERssIp4Pkt", 3, 1 }, 10961 { "ERssIp6Pkt", 2, 1 }, 10962 { "ERssTcpUdpPkt", 1, 1 }, 10963 { "ERssFceFipPkt", 0, 1 }, 10964 { NULL } 10965 }; 10966 10967 static void 10968 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 10969 { 10970 10971 field_desc_show(sb, *p, tp_la0); 10972 } 10973 10974 static void 10975 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 10976 { 10977 10978 if (idx) 10979 sbuf_printf(sb, "\n"); 10980 field_desc_show(sb, p[0], tp_la0); 10981 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10982 field_desc_show(sb, p[1], tp_la0); 10983 } 10984 10985 static void 10986 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 10987 { 10988 10989 if (idx) 10990 sbuf_printf(sb, "\n"); 10991 field_desc_show(sb, p[0], tp_la0); 10992 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10993 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 10994 } 10995 10996 static int 10997 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 10998 { 10999 struct adapter *sc = arg1; 11000 struct sbuf *sb; 11001 uint64_t *buf, *p; 11002 int rc; 11003 u_int i, inc; 11004 void (*show_func)(struct sbuf *, uint64_t *, int); 11005 11006 rc = 0; 11007 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11008 if (sb == NULL) 11009 return (ENOMEM); 11010 11011 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 11012 11013 mtx_lock(&sc->reg_lock); 11014 if (hw_off_limits(sc)) 11015 rc = ENXIO; 11016 else { 11017 t4_tp_read_la(sc, buf, NULL); 11018 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 11019 case 2: 11020 inc = 2; 11021 show_func = tp_la_show2; 11022 break; 11023 case 3: 11024 inc = 2; 11025 show_func = tp_la_show3; 11026 break; 11027 default: 11028 inc = 1; 11029 show_func = tp_la_show; 11030 } 11031 } 11032 mtx_unlock(&sc->reg_lock); 11033 if (rc != 0) 11034 goto done; 11035 11036 p = buf; 11037 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 11038 (*show_func)(sb, p, i); 11039 rc = sbuf_finish(sb); 11040 done: 11041 sbuf_delete(sb); 11042 free(buf, M_CXGBE); 11043 return (rc); 11044 } 11045 11046 static int 11047 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 11048 { 11049 struct adapter *sc = arg1; 11050 struct sbuf *sb; 11051 int rc; 11052 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 11053 11054 rc = 0; 11055 mtx_lock(&sc->reg_lock); 11056 if (hw_off_limits(sc)) 11057 rc = ENXIO; 11058 else 11059 t4_get_chan_txrate(sc, nrate, orate); 11060 mtx_unlock(&sc->reg_lock); 11061 if (rc != 0) 11062 return (rc); 11063 11064 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 11065 if (sb == NULL) 11066 return (ENOMEM); 11067 11068 if (sc->chip_params->nchan > 2) { 11069 sbuf_printf(sb, " channel 0 channel 1" 11070 " channel 2 channel 3\n"); 11071 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 11072 nrate[0], nrate[1], nrate[2], nrate[3]); 11073 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 11074 orate[0], orate[1], orate[2], orate[3]); 11075 } else { 11076 sbuf_printf(sb, " channel 0 channel 1\n"); 11077 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 11078 nrate[0], nrate[1]); 11079 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 11080 orate[0], orate[1]); 11081 } 11082 11083 rc = sbuf_finish(sb); 11084 sbuf_delete(sb); 11085 11086 return (rc); 11087 } 11088 11089 static int 11090 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 11091 { 11092 struct adapter *sc = arg1; 11093 struct sbuf *sb; 11094 uint32_t *buf, *p; 11095 int rc, i; 11096 11097 rc = 0; 11098 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11099 if (sb == NULL) 11100 return (ENOMEM); 11101 11102 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 11103 M_ZERO | M_WAITOK); 11104 11105 mtx_lock(&sc->reg_lock); 11106 if (hw_off_limits(sc)) 11107 rc = ENXIO; 11108 else 11109 t4_ulprx_read_la(sc, buf); 11110 mtx_unlock(&sc->reg_lock); 11111 if (rc != 0) 11112 goto done; 11113 11114 p = buf; 11115 sbuf_printf(sb, " Pcmd Type Message" 11116 " Data"); 11117 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 11118 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 11119 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 11120 } 11121 rc = sbuf_finish(sb); 11122 done: 11123 sbuf_delete(sb); 11124 free(buf, M_CXGBE); 11125 return (rc); 11126 } 11127 11128 static int 11129 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 11130 { 11131 struct adapter *sc = arg1; 11132 struct sbuf *sb; 11133 int rc; 11134 uint32_t cfg, s1, s2; 11135 11136 MPASS(chip_id(sc) >= CHELSIO_T5); 11137 11138 rc = 0; 11139 mtx_lock(&sc->reg_lock); 11140 if (hw_off_limits(sc)) 11141 rc = ENXIO; 11142 else { 11143 cfg = t4_read_reg(sc, A_SGE_STAT_CFG); 11144 s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL); 11145 s2 = t4_read_reg(sc, A_SGE_STAT_MATCH); 11146 } 11147 mtx_unlock(&sc->reg_lock); 11148 if (rc != 0) 11149 return (rc); 11150 11151 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11152 if (sb == NULL) 11153 return (ENOMEM); 11154 11155 if (G_STATSOURCE_T5(cfg) == 7) { 11156 int mode; 11157 11158 mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg); 11159 if (mode == 0) 11160 sbuf_printf(sb, "total %d, incomplete %d", s1, s2); 11161 else if (mode == 1) 11162 sbuf_printf(sb, "total %d, data overflow %d", s1, s2); 11163 else 11164 sbuf_printf(sb, "unknown mode %d", mode); 11165 } 11166 rc = sbuf_finish(sb); 11167 sbuf_delete(sb); 11168 11169 return (rc); 11170 } 11171 11172 static int 11173 sysctl_cpus(SYSCTL_HANDLER_ARGS) 11174 { 11175 struct adapter *sc = arg1; 11176 enum cpu_sets op = arg2; 11177 cpuset_t cpuset; 11178 struct sbuf *sb; 11179 int i, rc; 11180 11181 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 11182 11183 CPU_ZERO(&cpuset); 11184 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 11185 if (rc != 0) 11186 return (rc); 11187 11188 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11189 if (sb == NULL) 11190 return (ENOMEM); 11191 11192 CPU_FOREACH(i) 11193 sbuf_printf(sb, "%d ", i); 11194 rc = sbuf_finish(sb); 11195 sbuf_delete(sb); 11196 11197 return (rc); 11198 } 11199 11200 static int 11201 sysctl_reset(SYSCTL_HANDLER_ARGS) 11202 { 11203 struct adapter *sc = arg1; 11204 u_int val; 11205 int rc; 11206 11207 val = atomic_load_int(&sc->num_resets); 11208 rc = sysctl_handle_int(oidp, &val, 0, req); 11209 if (rc != 0 || req->newptr == NULL) 11210 return (rc); 11211 11212 if (val == 0) { 11213 /* Zero out the counter that tracks reset. */ 11214 atomic_store_int(&sc->num_resets, 0); 11215 return (0); 11216 } 11217 11218 if (val != 1) 11219 return (EINVAL); /* 0 or 1 are the only legal values */ 11220 11221 if (hw_off_limits(sc)) /* harmless race */ 11222 return (EALREADY); 11223 11224 taskqueue_enqueue(reset_tq, &sc->reset_task); 11225 return (0); 11226 } 11227 11228 #ifdef TCP_OFFLOAD 11229 static int 11230 sysctl_tls(SYSCTL_HANDLER_ARGS) 11231 { 11232 struct adapter *sc = arg1; 11233 int i, j, v, rc; 11234 struct vi_info *vi; 11235 11236 v = sc->tt.tls; 11237 rc = sysctl_handle_int(oidp, &v, 0, req); 11238 if (rc != 0 || req->newptr == NULL) 11239 return (rc); 11240 11241 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 11242 return (ENOTSUP); 11243 11244 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls"); 11245 if (rc) 11246 return (rc); 11247 if (hw_off_limits(sc)) 11248 rc = ENXIO; 11249 else { 11250 sc->tt.tls = !!v; 11251 for_each_port(sc, i) { 11252 for_each_vi(sc->port[i], j, vi) { 11253 if (vi->flags & VI_INIT_DONE) 11254 t4_update_fl_bufsize(vi->ifp); 11255 } 11256 } 11257 } 11258 end_synchronized_op(sc, 0); 11259 11260 return (rc); 11261 11262 } 11263 11264 static void 11265 unit_conv(char *buf, size_t len, u_int val, u_int factor) 11266 { 11267 u_int rem = val % factor; 11268 11269 if (rem == 0) 11270 snprintf(buf, len, "%u", val / factor); 11271 else { 11272 while (rem % 10 == 0) 11273 rem /= 10; 11274 snprintf(buf, len, "%u.%u", val / factor, rem); 11275 } 11276 } 11277 11278 static int 11279 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 11280 { 11281 struct adapter *sc = arg1; 11282 char buf[16]; 11283 u_int res, re; 11284 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11285 11286 mtx_lock(&sc->reg_lock); 11287 if (hw_off_limits(sc)) 11288 res = (u_int)-1; 11289 else 11290 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 11291 mtx_unlock(&sc->reg_lock); 11292 if (res == (u_int)-1) 11293 return (ENXIO); 11294 11295 switch (arg2) { 11296 case 0: 11297 /* timer_tick */ 11298 re = G_TIMERRESOLUTION(res); 11299 break; 11300 case 1: 11301 /* TCP timestamp tick */ 11302 re = G_TIMESTAMPRESOLUTION(res); 11303 break; 11304 case 2: 11305 /* DACK tick */ 11306 re = G_DELAYEDACKRESOLUTION(res); 11307 break; 11308 default: 11309 return (EDOOFUS); 11310 } 11311 11312 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 11313 11314 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 11315 } 11316 11317 static int 11318 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 11319 { 11320 struct adapter *sc = arg1; 11321 int rc; 11322 u_int dack_tmr, dack_re, v; 11323 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11324 11325 mtx_lock(&sc->reg_lock); 11326 if (hw_off_limits(sc)) 11327 rc = ENXIO; 11328 else { 11329 rc = 0; 11330 dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc, 11331 A_TP_TIMER_RESOLUTION)); 11332 dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER); 11333 } 11334 mtx_unlock(&sc->reg_lock); 11335 if (rc != 0) 11336 return (rc); 11337 11338 v = ((cclk_ps << dack_re) / 1000000) * dack_tmr; 11339 11340 return (sysctl_handle_int(oidp, &v, 0, req)); 11341 } 11342 11343 static int 11344 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 11345 { 11346 struct adapter *sc = arg1; 11347 int rc, reg = arg2; 11348 u_int tre; 11349 u_long tp_tick_us, v; 11350 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11351 11352 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 11353 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 11354 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 11355 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 11356 11357 mtx_lock(&sc->reg_lock); 11358 if (hw_off_limits(sc)) 11359 rc = ENXIO; 11360 else { 11361 rc = 0; 11362 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 11363 tp_tick_us = (cclk_ps << tre) / 1000000; 11364 if (reg == A_TP_INIT_SRTT) 11365 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 11366 else 11367 v = tp_tick_us * t4_read_reg(sc, reg); 11368 } 11369 mtx_unlock(&sc->reg_lock); 11370 if (rc != 0) 11371 return (rc); 11372 else 11373 return (sysctl_handle_long(oidp, &v, 0, req)); 11374 } 11375 11376 /* 11377 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 11378 * passed to this function. 11379 */ 11380 static int 11381 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 11382 { 11383 struct adapter *sc = arg1; 11384 int rc, idx = arg2; 11385 u_int v; 11386 11387 MPASS(idx >= 0 && idx <= 24); 11388 11389 mtx_lock(&sc->reg_lock); 11390 if (hw_off_limits(sc)) 11391 rc = ENXIO; 11392 else { 11393 rc = 0; 11394 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 11395 } 11396 mtx_unlock(&sc->reg_lock); 11397 if (rc != 0) 11398 return (rc); 11399 else 11400 return (sysctl_handle_int(oidp, &v, 0, req)); 11401 } 11402 11403 static int 11404 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 11405 { 11406 struct adapter *sc = arg1; 11407 int rc, idx = arg2; 11408 u_int shift, v, r; 11409 11410 MPASS(idx >= 0 && idx < 16); 11411 11412 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 11413 shift = (idx & 3) << 3; 11414 mtx_lock(&sc->reg_lock); 11415 if (hw_off_limits(sc)) 11416 rc = ENXIO; 11417 else { 11418 rc = 0; 11419 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 11420 } 11421 mtx_unlock(&sc->reg_lock); 11422 if (rc != 0) 11423 return (rc); 11424 else 11425 return (sysctl_handle_int(oidp, &v, 0, req)); 11426 } 11427 11428 static int 11429 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 11430 { 11431 struct vi_info *vi = arg1; 11432 struct adapter *sc = vi->adapter; 11433 int idx, rc, i; 11434 struct sge_ofld_rxq *ofld_rxq; 11435 uint8_t v; 11436 11437 idx = vi->ofld_tmr_idx; 11438 11439 rc = sysctl_handle_int(oidp, &idx, 0, req); 11440 if (rc != 0 || req->newptr == NULL) 11441 return (rc); 11442 11443 if (idx < 0 || idx >= SGE_NTIMERS) 11444 return (EINVAL); 11445 11446 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11447 "t4otmr"); 11448 if (rc) 11449 return (rc); 11450 11451 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 11452 for_each_ofld_rxq(vi, i, ofld_rxq) { 11453 #ifdef atomic_store_rel_8 11454 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 11455 #else 11456 ofld_rxq->iq.intr_params = v; 11457 #endif 11458 } 11459 vi->ofld_tmr_idx = idx; 11460 11461 end_synchronized_op(sc, LOCK_HELD); 11462 return (0); 11463 } 11464 11465 static int 11466 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 11467 { 11468 struct vi_info *vi = arg1; 11469 struct adapter *sc = vi->adapter; 11470 int idx, rc; 11471 11472 idx = vi->ofld_pktc_idx; 11473 11474 rc = sysctl_handle_int(oidp, &idx, 0, req); 11475 if (rc != 0 || req->newptr == NULL) 11476 return (rc); 11477 11478 if (idx < -1 || idx >= SGE_NCOUNTERS) 11479 return (EINVAL); 11480 11481 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11482 "t4opktc"); 11483 if (rc) 11484 return (rc); 11485 11486 if (vi->flags & VI_INIT_DONE) 11487 rc = EBUSY; /* cannot be changed once the queues are created */ 11488 else 11489 vi->ofld_pktc_idx = idx; 11490 11491 end_synchronized_op(sc, LOCK_HELD); 11492 return (rc); 11493 } 11494 #endif 11495 11496 static int 11497 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 11498 { 11499 int rc; 11500 11501 if (cntxt->cid > M_CTXTQID) 11502 return (EINVAL); 11503 11504 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 11505 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 11506 return (EINVAL); 11507 11508 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 11509 if (rc) 11510 return (rc); 11511 11512 if (hw_off_limits(sc)) { 11513 rc = ENXIO; 11514 goto done; 11515 } 11516 11517 if (sc->flags & FW_OK) { 11518 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 11519 &cntxt->data[0]); 11520 if (rc == 0) 11521 goto done; 11522 } 11523 11524 /* 11525 * Read via firmware failed or wasn't even attempted. Read directly via 11526 * the backdoor. 11527 */ 11528 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 11529 done: 11530 end_synchronized_op(sc, 0); 11531 return (rc); 11532 } 11533 11534 static int 11535 load_fw(struct adapter *sc, struct t4_data *fw) 11536 { 11537 int rc; 11538 uint8_t *fw_data; 11539 11540 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 11541 if (rc) 11542 return (rc); 11543 11544 if (hw_off_limits(sc)) { 11545 rc = ENXIO; 11546 goto done; 11547 } 11548 11549 /* 11550 * The firmware, with the sole exception of the memory parity error 11551 * handler, runs from memory and not flash. It is almost always safe to 11552 * install a new firmware on a running system. Just set bit 1 in 11553 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 11554 */ 11555 if (sc->flags & FULL_INIT_DONE && 11556 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 11557 rc = EBUSY; 11558 goto done; 11559 } 11560 11561 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 11562 11563 rc = copyin(fw->data, fw_data, fw->len); 11564 if (rc == 0) 11565 rc = -t4_load_fw(sc, fw_data, fw->len); 11566 11567 free(fw_data, M_CXGBE); 11568 done: 11569 end_synchronized_op(sc, 0); 11570 return (rc); 11571 } 11572 11573 static int 11574 load_cfg(struct adapter *sc, struct t4_data *cfg) 11575 { 11576 int rc; 11577 uint8_t *cfg_data = NULL; 11578 11579 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11580 if (rc) 11581 return (rc); 11582 11583 if (hw_off_limits(sc)) { 11584 rc = ENXIO; 11585 goto done; 11586 } 11587 11588 if (cfg->len == 0) { 11589 /* clear */ 11590 rc = -t4_load_cfg(sc, NULL, 0); 11591 goto done; 11592 } 11593 11594 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 11595 11596 rc = copyin(cfg->data, cfg_data, cfg->len); 11597 if (rc == 0) 11598 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 11599 11600 free(cfg_data, M_CXGBE); 11601 done: 11602 end_synchronized_op(sc, 0); 11603 return (rc); 11604 } 11605 11606 static int 11607 load_boot(struct adapter *sc, struct t4_bootrom *br) 11608 { 11609 int rc; 11610 uint8_t *br_data = NULL; 11611 u_int offset; 11612 11613 if (br->len > 1024 * 1024) 11614 return (EFBIG); 11615 11616 if (br->pf_offset == 0) { 11617 /* pfidx */ 11618 if (br->pfidx_addr > 7) 11619 return (EINVAL); 11620 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 11621 A_PCIE_PF_EXPROM_OFST))); 11622 } else if (br->pf_offset == 1) { 11623 /* offset */ 11624 offset = G_OFFSET(br->pfidx_addr); 11625 } else { 11626 return (EINVAL); 11627 } 11628 11629 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 11630 if (rc) 11631 return (rc); 11632 11633 if (hw_off_limits(sc)) { 11634 rc = ENXIO; 11635 goto done; 11636 } 11637 11638 if (br->len == 0) { 11639 /* clear */ 11640 rc = -t4_load_boot(sc, NULL, offset, 0); 11641 goto done; 11642 } 11643 11644 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 11645 11646 rc = copyin(br->data, br_data, br->len); 11647 if (rc == 0) 11648 rc = -t4_load_boot(sc, br_data, offset, br->len); 11649 11650 free(br_data, M_CXGBE); 11651 done: 11652 end_synchronized_op(sc, 0); 11653 return (rc); 11654 } 11655 11656 static int 11657 load_bootcfg(struct adapter *sc, struct t4_data *bc) 11658 { 11659 int rc; 11660 uint8_t *bc_data = NULL; 11661 11662 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11663 if (rc) 11664 return (rc); 11665 11666 if (hw_off_limits(sc)) { 11667 rc = ENXIO; 11668 goto done; 11669 } 11670 11671 if (bc->len == 0) { 11672 /* clear */ 11673 rc = -t4_load_bootcfg(sc, NULL, 0); 11674 goto done; 11675 } 11676 11677 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 11678 11679 rc = copyin(bc->data, bc_data, bc->len); 11680 if (rc == 0) 11681 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 11682 11683 free(bc_data, M_CXGBE); 11684 done: 11685 end_synchronized_op(sc, 0); 11686 return (rc); 11687 } 11688 11689 static int 11690 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 11691 { 11692 int rc; 11693 struct cudbg_init *cudbg; 11694 void *handle, *buf; 11695 11696 /* buf is large, don't block if no memory is available */ 11697 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 11698 if (buf == NULL) 11699 return (ENOMEM); 11700 11701 handle = cudbg_alloc_handle(); 11702 if (handle == NULL) { 11703 rc = ENOMEM; 11704 goto done; 11705 } 11706 11707 cudbg = cudbg_get_init(handle); 11708 cudbg->adap = sc; 11709 cudbg->print = (cudbg_print_cb)printf; 11710 11711 #ifndef notyet 11712 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 11713 __func__, dump->wr_flash, dump->len, dump->data); 11714 #endif 11715 11716 if (dump->wr_flash) 11717 cudbg->use_flash = 1; 11718 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 11719 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 11720 11721 rc = cudbg_collect(handle, buf, &dump->len); 11722 if (rc != 0) 11723 goto done; 11724 11725 rc = copyout(buf, dump->data, dump->len); 11726 done: 11727 cudbg_free_handle(handle); 11728 free(buf, M_CXGBE); 11729 return (rc); 11730 } 11731 11732 static void 11733 free_offload_policy(struct t4_offload_policy *op) 11734 { 11735 struct offload_rule *r; 11736 int i; 11737 11738 if (op == NULL) 11739 return; 11740 11741 r = &op->rule[0]; 11742 for (i = 0; i < op->nrules; i++, r++) { 11743 free(r->bpf_prog.bf_insns, M_CXGBE); 11744 } 11745 free(op->rule, M_CXGBE); 11746 free(op, M_CXGBE); 11747 } 11748 11749 static int 11750 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 11751 { 11752 int i, rc, len; 11753 struct t4_offload_policy *op, *old; 11754 struct bpf_program *bf; 11755 const struct offload_settings *s; 11756 struct offload_rule *r; 11757 void *u; 11758 11759 if (!is_offload(sc)) 11760 return (ENODEV); 11761 11762 if (uop->nrules == 0) { 11763 /* Delete installed policies. */ 11764 op = NULL; 11765 goto set_policy; 11766 } else if (uop->nrules > 256) { /* arbitrary */ 11767 return (E2BIG); 11768 } 11769 11770 /* Copy userspace offload policy to kernel */ 11771 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 11772 op->nrules = uop->nrules; 11773 len = op->nrules * sizeof(struct offload_rule); 11774 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11775 rc = copyin(uop->rule, op->rule, len); 11776 if (rc) { 11777 free(op->rule, M_CXGBE); 11778 free(op, M_CXGBE); 11779 return (rc); 11780 } 11781 11782 r = &op->rule[0]; 11783 for (i = 0; i < op->nrules; i++, r++) { 11784 11785 /* Validate open_type */ 11786 if (r->open_type != OPEN_TYPE_LISTEN && 11787 r->open_type != OPEN_TYPE_ACTIVE && 11788 r->open_type != OPEN_TYPE_PASSIVE && 11789 r->open_type != OPEN_TYPE_DONTCARE) { 11790 error: 11791 /* 11792 * Rules 0 to i have malloc'd filters that need to be 11793 * freed. Rules i+1 to nrules have userspace pointers 11794 * and should be left alone. 11795 */ 11796 op->nrules = i; 11797 free_offload_policy(op); 11798 return (rc); 11799 } 11800 11801 /* Validate settings */ 11802 s = &r->settings; 11803 if ((s->offload != 0 && s->offload != 1) || 11804 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 11805 s->sched_class < -1 || 11806 s->sched_class >= sc->params.nsched_cls) { 11807 rc = EINVAL; 11808 goto error; 11809 } 11810 11811 bf = &r->bpf_prog; 11812 u = bf->bf_insns; /* userspace ptr */ 11813 bf->bf_insns = NULL; 11814 if (bf->bf_len == 0) { 11815 /* legal, matches everything */ 11816 continue; 11817 } 11818 len = bf->bf_len * sizeof(*bf->bf_insns); 11819 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11820 rc = copyin(u, bf->bf_insns, len); 11821 if (rc != 0) 11822 goto error; 11823 11824 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 11825 rc = EINVAL; 11826 goto error; 11827 } 11828 } 11829 set_policy: 11830 rw_wlock(&sc->policy_lock); 11831 old = sc->policy; 11832 sc->policy = op; 11833 rw_wunlock(&sc->policy_lock); 11834 free_offload_policy(old); 11835 11836 return (0); 11837 } 11838 11839 #define MAX_READ_BUF_SIZE (128 * 1024) 11840 static int 11841 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 11842 { 11843 uint32_t addr, remaining, n; 11844 uint32_t *buf; 11845 int rc; 11846 uint8_t *dst; 11847 11848 mtx_lock(&sc->reg_lock); 11849 if (hw_off_limits(sc)) 11850 rc = ENXIO; 11851 else 11852 rc = validate_mem_range(sc, mr->addr, mr->len); 11853 mtx_unlock(&sc->reg_lock); 11854 if (rc != 0) 11855 return (rc); 11856 11857 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 11858 addr = mr->addr; 11859 remaining = mr->len; 11860 dst = (void *)mr->data; 11861 11862 while (remaining) { 11863 n = min(remaining, MAX_READ_BUF_SIZE); 11864 mtx_lock(&sc->reg_lock); 11865 if (hw_off_limits(sc)) 11866 rc = ENXIO; 11867 else 11868 read_via_memwin(sc, 2, addr, buf, n); 11869 mtx_unlock(&sc->reg_lock); 11870 if (rc != 0) 11871 break; 11872 11873 rc = copyout(buf, dst, n); 11874 if (rc != 0) 11875 break; 11876 11877 dst += n; 11878 remaining -= n; 11879 addr += n; 11880 } 11881 11882 free(buf, M_CXGBE); 11883 return (rc); 11884 } 11885 #undef MAX_READ_BUF_SIZE 11886 11887 static int 11888 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 11889 { 11890 int rc; 11891 11892 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 11893 return (EINVAL); 11894 11895 if (i2cd->len > sizeof(i2cd->data)) 11896 return (EFBIG); 11897 11898 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 11899 if (rc) 11900 return (rc); 11901 if (hw_off_limits(sc)) 11902 rc = ENXIO; 11903 else 11904 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 11905 i2cd->offset, i2cd->len, &i2cd->data[0]); 11906 end_synchronized_op(sc, 0); 11907 11908 return (rc); 11909 } 11910 11911 static int 11912 clear_stats(struct adapter *sc, u_int port_id) 11913 { 11914 int i, v, chan_map; 11915 struct port_info *pi; 11916 struct vi_info *vi; 11917 struct sge_rxq *rxq; 11918 struct sge_txq *txq; 11919 struct sge_wrq *wrq; 11920 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 11921 struct sge_ofld_txq *ofld_txq; 11922 #endif 11923 #ifdef TCP_OFFLOAD 11924 struct sge_ofld_rxq *ofld_rxq; 11925 #endif 11926 11927 if (port_id >= sc->params.nports) 11928 return (EINVAL); 11929 pi = sc->port[port_id]; 11930 if (pi == NULL) 11931 return (EIO); 11932 11933 mtx_lock(&sc->reg_lock); 11934 if (!hw_off_limits(sc)) { 11935 /* MAC stats */ 11936 t4_clr_port_stats(sc, pi->tx_chan); 11937 if (is_t6(sc)) { 11938 if (pi->fcs_reg != -1) 11939 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 11940 else 11941 pi->stats.rx_fcs_err = 0; 11942 } 11943 for_each_vi(pi, v, vi) { 11944 if (vi->flags & VI_INIT_DONE) 11945 t4_clr_vi_stats(sc, vi->vin); 11946 } 11947 chan_map = pi->rx_e_chan_map; 11948 v = 0; /* reuse */ 11949 while (chan_map) { 11950 i = ffs(chan_map) - 1; 11951 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 11952 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 11953 chan_map &= ~(1 << i); 11954 } 11955 } 11956 mtx_unlock(&sc->reg_lock); 11957 pi->tx_parse_error = 0; 11958 pi->tnl_cong_drops = 0; 11959 11960 /* 11961 * Since this command accepts a port, clear stats for 11962 * all VIs on this port. 11963 */ 11964 for_each_vi(pi, v, vi) { 11965 if (vi->flags & VI_INIT_DONE) { 11966 11967 for_each_rxq(vi, i, rxq) { 11968 #if defined(INET) || defined(INET6) 11969 rxq->lro.lro_queued = 0; 11970 rxq->lro.lro_flushed = 0; 11971 #endif 11972 rxq->rxcsum = 0; 11973 rxq->vlan_extraction = 0; 11974 rxq->vxlan_rxcsum = 0; 11975 11976 rxq->fl.cl_allocated = 0; 11977 rxq->fl.cl_recycled = 0; 11978 rxq->fl.cl_fast_recycled = 0; 11979 } 11980 11981 for_each_txq(vi, i, txq) { 11982 txq->txcsum = 0; 11983 txq->tso_wrs = 0; 11984 txq->vlan_insertion = 0; 11985 txq->imm_wrs = 0; 11986 txq->sgl_wrs = 0; 11987 txq->txpkt_wrs = 0; 11988 txq->txpkts0_wrs = 0; 11989 txq->txpkts1_wrs = 0; 11990 txq->txpkts0_pkts = 0; 11991 txq->txpkts1_pkts = 0; 11992 txq->txpkts_flush = 0; 11993 txq->raw_wrs = 0; 11994 txq->vxlan_tso_wrs = 0; 11995 txq->vxlan_txcsum = 0; 11996 txq->kern_tls_records = 0; 11997 txq->kern_tls_short = 0; 11998 txq->kern_tls_partial = 0; 11999 txq->kern_tls_full = 0; 12000 txq->kern_tls_octets = 0; 12001 txq->kern_tls_waste = 0; 12002 txq->kern_tls_options = 0; 12003 txq->kern_tls_header = 0; 12004 txq->kern_tls_fin = 0; 12005 txq->kern_tls_fin_short = 0; 12006 txq->kern_tls_cbc = 0; 12007 txq->kern_tls_gcm = 0; 12008 mp_ring_reset_stats(txq->r); 12009 } 12010 12011 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12012 for_each_ofld_txq(vi, i, ofld_txq) { 12013 ofld_txq->wrq.tx_wrs_direct = 0; 12014 ofld_txq->wrq.tx_wrs_copied = 0; 12015 counter_u64_zero(ofld_txq->tx_iscsi_pdus); 12016 counter_u64_zero(ofld_txq->tx_iscsi_octets); 12017 counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs); 12018 counter_u64_zero(ofld_txq->tx_aio_jobs); 12019 counter_u64_zero(ofld_txq->tx_aio_octets); 12020 counter_u64_zero(ofld_txq->tx_toe_tls_records); 12021 counter_u64_zero(ofld_txq->tx_toe_tls_octets); 12022 } 12023 #endif 12024 #ifdef TCP_OFFLOAD 12025 for_each_ofld_rxq(vi, i, ofld_rxq) { 12026 ofld_rxq->fl.cl_allocated = 0; 12027 ofld_rxq->fl.cl_recycled = 0; 12028 ofld_rxq->fl.cl_fast_recycled = 0; 12029 counter_u64_zero( 12030 ofld_rxq->rx_iscsi_ddp_setup_ok); 12031 counter_u64_zero( 12032 ofld_rxq->rx_iscsi_ddp_setup_error); 12033 ofld_rxq->rx_iscsi_ddp_pdus = 0; 12034 ofld_rxq->rx_iscsi_ddp_octets = 0; 12035 ofld_rxq->rx_iscsi_fl_pdus = 0; 12036 ofld_rxq->rx_iscsi_fl_octets = 0; 12037 ofld_rxq->rx_aio_ddp_jobs = 0; 12038 ofld_rxq->rx_aio_ddp_octets = 0; 12039 ofld_rxq->rx_toe_tls_records = 0; 12040 ofld_rxq->rx_toe_tls_octets = 0; 12041 ofld_rxq->rx_toe_ddp_octets = 0; 12042 counter_u64_zero(ofld_rxq->ddp_buffer_alloc); 12043 counter_u64_zero(ofld_rxq->ddp_buffer_reuse); 12044 counter_u64_zero(ofld_rxq->ddp_buffer_free); 12045 } 12046 #endif 12047 12048 if (IS_MAIN_VI(vi)) { 12049 wrq = &sc->sge.ctrlq[pi->port_id]; 12050 wrq->tx_wrs_direct = 0; 12051 wrq->tx_wrs_copied = 0; 12052 } 12053 } 12054 } 12055 12056 return (0); 12057 } 12058 12059 static int 12060 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12061 { 12062 #ifdef INET6 12063 struct in6_addr in6; 12064 12065 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12066 if (t4_get_clip_entry(sc, &in6, true) != NULL) 12067 return (0); 12068 else 12069 return (EIO); 12070 #else 12071 return (ENOTSUP); 12072 #endif 12073 } 12074 12075 static int 12076 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12077 { 12078 #ifdef INET6 12079 struct in6_addr in6; 12080 12081 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12082 return (t4_release_clip_addr(sc, &in6)); 12083 #else 12084 return (ENOTSUP); 12085 #endif 12086 } 12087 12088 int 12089 t4_os_find_pci_capability(struct adapter *sc, int cap) 12090 { 12091 int i; 12092 12093 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 12094 } 12095 12096 int 12097 t4_os_pci_save_state(struct adapter *sc) 12098 { 12099 device_t dev; 12100 struct pci_devinfo *dinfo; 12101 12102 dev = sc->dev; 12103 dinfo = device_get_ivars(dev); 12104 12105 pci_cfg_save(dev, dinfo, 0); 12106 return (0); 12107 } 12108 12109 int 12110 t4_os_pci_restore_state(struct adapter *sc) 12111 { 12112 device_t dev; 12113 struct pci_devinfo *dinfo; 12114 12115 dev = sc->dev; 12116 dinfo = device_get_ivars(dev); 12117 12118 pci_cfg_restore(dev, dinfo); 12119 return (0); 12120 } 12121 12122 void 12123 t4_os_portmod_changed(struct port_info *pi) 12124 { 12125 struct adapter *sc = pi->adapter; 12126 struct vi_info *vi; 12127 if_t ifp; 12128 static const char *mod_str[] = { 12129 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 12130 }; 12131 12132 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 12133 ("%s: port_type %u", __func__, pi->port_type)); 12134 12135 vi = &pi->vi[0]; 12136 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 12137 PORT_LOCK(pi); 12138 build_medialist(pi); 12139 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 12140 fixup_link_config(pi); 12141 apply_link_config(pi); 12142 } 12143 PORT_UNLOCK(pi); 12144 end_synchronized_op(sc, LOCK_HELD); 12145 } 12146 12147 ifp = vi->ifp; 12148 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 12149 if_printf(ifp, "transceiver unplugged.\n"); 12150 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 12151 if_printf(ifp, "unknown transceiver inserted.\n"); 12152 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 12153 if_printf(ifp, "unsupported transceiver inserted.\n"); 12154 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 12155 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 12156 port_top_speed(pi), mod_str[pi->mod_type]); 12157 } else { 12158 if_printf(ifp, "transceiver (type %d) inserted.\n", 12159 pi->mod_type); 12160 } 12161 } 12162 12163 void 12164 t4_os_link_changed(struct port_info *pi) 12165 { 12166 struct vi_info *vi; 12167 if_t ifp; 12168 struct link_config *lc = &pi->link_cfg; 12169 struct adapter *sc = pi->adapter; 12170 int v; 12171 12172 PORT_LOCK_ASSERT_OWNED(pi); 12173 12174 if (is_t6(sc)) { 12175 if (lc->link_ok) { 12176 if (lc->speed > 25000 || 12177 (lc->speed == 25000 && lc->fec == FEC_RS)) { 12178 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12179 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS); 12180 } else { 12181 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12182 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS); 12183 } 12184 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 12185 pi->stats.rx_fcs_err = 0; 12186 } else { 12187 pi->fcs_reg = -1; 12188 } 12189 } else { 12190 MPASS(pi->fcs_reg != -1); 12191 MPASS(pi->fcs_base == 0); 12192 } 12193 12194 for_each_vi(pi, v, vi) { 12195 ifp = vi->ifp; 12196 if (ifp == NULL || IS_DETACHING(vi)) 12197 continue; 12198 12199 if (lc->link_ok) { 12200 if_setbaudrate(ifp, IF_Mbps(lc->speed)); 12201 if_link_state_change(ifp, LINK_STATE_UP); 12202 } else { 12203 if_link_state_change(ifp, LINK_STATE_DOWN); 12204 } 12205 } 12206 } 12207 12208 void 12209 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 12210 { 12211 struct adapter *sc; 12212 12213 sx_slock(&t4_list_lock); 12214 SLIST_FOREACH(sc, &t4_list, link) { 12215 /* 12216 * func should not make any assumptions about what state sc is 12217 * in - the only guarantee is that sc->sc_lock is a valid lock. 12218 */ 12219 func(sc, arg); 12220 } 12221 sx_sunlock(&t4_list_lock); 12222 } 12223 12224 static int 12225 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 12226 struct thread *td) 12227 { 12228 int rc; 12229 struct adapter *sc = dev->si_drv1; 12230 12231 rc = priv_check(td, PRIV_DRIVER); 12232 if (rc != 0) 12233 return (rc); 12234 12235 switch (cmd) { 12236 case CHELSIO_T4_GETREG: { 12237 struct t4_reg *edata = (struct t4_reg *)data; 12238 12239 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12240 return (EFAULT); 12241 12242 mtx_lock(&sc->reg_lock); 12243 if (hw_off_limits(sc)) 12244 rc = ENXIO; 12245 else if (edata->size == 4) 12246 edata->val = t4_read_reg(sc, edata->addr); 12247 else if (edata->size == 8) 12248 edata->val = t4_read_reg64(sc, edata->addr); 12249 else 12250 rc = EINVAL; 12251 mtx_unlock(&sc->reg_lock); 12252 12253 break; 12254 } 12255 case CHELSIO_T4_SETREG: { 12256 struct t4_reg *edata = (struct t4_reg *)data; 12257 12258 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12259 return (EFAULT); 12260 12261 mtx_lock(&sc->reg_lock); 12262 if (hw_off_limits(sc)) 12263 rc = ENXIO; 12264 else if (edata->size == 4) { 12265 if (edata->val & 0xffffffff00000000) 12266 rc = EINVAL; 12267 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 12268 } else if (edata->size == 8) 12269 t4_write_reg64(sc, edata->addr, edata->val); 12270 else 12271 rc = EINVAL; 12272 mtx_unlock(&sc->reg_lock); 12273 12274 break; 12275 } 12276 case CHELSIO_T4_REGDUMP: { 12277 struct t4_regdump *regs = (struct t4_regdump *)data; 12278 int reglen = t4_get_regs_len(sc); 12279 uint8_t *buf; 12280 12281 if (regs->len < reglen) { 12282 regs->len = reglen; /* hint to the caller */ 12283 return (ENOBUFS); 12284 } 12285 12286 regs->len = reglen; 12287 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 12288 mtx_lock(&sc->reg_lock); 12289 if (hw_off_limits(sc)) 12290 rc = ENXIO; 12291 else 12292 get_regs(sc, regs, buf); 12293 mtx_unlock(&sc->reg_lock); 12294 if (rc == 0) 12295 rc = copyout(buf, regs->data, reglen); 12296 free(buf, M_CXGBE); 12297 break; 12298 } 12299 case CHELSIO_T4_GET_FILTER_MODE: 12300 rc = get_filter_mode(sc, (uint32_t *)data); 12301 break; 12302 case CHELSIO_T4_SET_FILTER_MODE: 12303 rc = set_filter_mode(sc, *(uint32_t *)data); 12304 break; 12305 case CHELSIO_T4_SET_FILTER_MASK: 12306 rc = set_filter_mask(sc, *(uint32_t *)data); 12307 break; 12308 case CHELSIO_T4_GET_FILTER: 12309 rc = get_filter(sc, (struct t4_filter *)data); 12310 break; 12311 case CHELSIO_T4_SET_FILTER: 12312 rc = set_filter(sc, (struct t4_filter *)data); 12313 break; 12314 case CHELSIO_T4_DEL_FILTER: 12315 rc = del_filter(sc, (struct t4_filter *)data); 12316 break; 12317 case CHELSIO_T4_GET_SGE_CONTEXT: 12318 rc = get_sge_context(sc, (struct t4_sge_context *)data); 12319 break; 12320 case CHELSIO_T4_LOAD_FW: 12321 rc = load_fw(sc, (struct t4_data *)data); 12322 break; 12323 case CHELSIO_T4_GET_MEM: 12324 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 12325 break; 12326 case CHELSIO_T4_GET_I2C: 12327 rc = read_i2c(sc, (struct t4_i2c_data *)data); 12328 break; 12329 case CHELSIO_T4_CLEAR_STATS: 12330 rc = clear_stats(sc, *(uint32_t *)data); 12331 break; 12332 case CHELSIO_T4_SCHED_CLASS: 12333 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 12334 break; 12335 case CHELSIO_T4_SCHED_QUEUE: 12336 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 12337 break; 12338 case CHELSIO_T4_GET_TRACER: 12339 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 12340 break; 12341 case CHELSIO_T4_SET_TRACER: 12342 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 12343 break; 12344 case CHELSIO_T4_LOAD_CFG: 12345 rc = load_cfg(sc, (struct t4_data *)data); 12346 break; 12347 case CHELSIO_T4_LOAD_BOOT: 12348 rc = load_boot(sc, (struct t4_bootrom *)data); 12349 break; 12350 case CHELSIO_T4_LOAD_BOOTCFG: 12351 rc = load_bootcfg(sc, (struct t4_data *)data); 12352 break; 12353 case CHELSIO_T4_CUDBG_DUMP: 12354 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 12355 break; 12356 case CHELSIO_T4_SET_OFLD_POLICY: 12357 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 12358 break; 12359 case CHELSIO_T4_HOLD_CLIP_ADDR: 12360 rc = hold_clip_addr(sc, (struct t4_clip_addr *)data); 12361 break; 12362 case CHELSIO_T4_RELEASE_CLIP_ADDR: 12363 rc = release_clip_addr(sc, (struct t4_clip_addr *)data); 12364 break; 12365 default: 12366 rc = ENOTTY; 12367 } 12368 12369 return (rc); 12370 } 12371 12372 #ifdef TCP_OFFLOAD 12373 static int 12374 toe_capability(struct vi_info *vi, bool enable) 12375 { 12376 int rc; 12377 struct port_info *pi = vi->pi; 12378 struct adapter *sc = pi->adapter; 12379 12380 ASSERT_SYNCHRONIZED_OP(sc); 12381 12382 if (!is_offload(sc)) 12383 return (ENODEV); 12384 if (hw_off_limits(sc)) 12385 return (ENXIO); 12386 12387 if (enable) { 12388 #ifdef KERN_TLS 12389 if (sc->flags & KERN_TLS_ON && is_t6(sc)) { 12390 int i, j, n; 12391 struct port_info *p; 12392 struct vi_info *v; 12393 12394 /* 12395 * Reconfigure hardware for TOE if TXTLS is not enabled 12396 * on any ifnet. 12397 */ 12398 n = 0; 12399 for_each_port(sc, i) { 12400 p = sc->port[i]; 12401 for_each_vi(p, j, v) { 12402 if (if_getcapenable(v->ifp) & IFCAP_TXTLS) { 12403 CH_WARN(sc, 12404 "%s has NIC TLS enabled.\n", 12405 device_get_nameunit(v->dev)); 12406 n++; 12407 } 12408 } 12409 } 12410 if (n > 0) { 12411 CH_WARN(sc, "Disable NIC TLS on all interfaces " 12412 "associated with this adapter before " 12413 "trying to enable TOE.\n"); 12414 return (EAGAIN); 12415 } 12416 rc = t6_config_kern_tls(sc, false); 12417 if (rc) 12418 return (rc); 12419 } 12420 #endif 12421 if ((if_getcapenable(vi->ifp) & IFCAP_TOE) != 0) { 12422 /* TOE is already enabled. */ 12423 return (0); 12424 } 12425 12426 /* 12427 * We need the port's queues around so that we're able to send 12428 * and receive CPLs to/from the TOE even if the ifnet for this 12429 * port has never been UP'd administratively. 12430 */ 12431 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 12432 return (rc); 12433 if (!(pi->vi[0].flags & VI_INIT_DONE) && 12434 ((rc = vi_init(&pi->vi[0])) != 0)) 12435 return (rc); 12436 12437 if (isset(&sc->offload_map, pi->port_id)) { 12438 /* TOE is enabled on another VI of this port. */ 12439 pi->uld_vis++; 12440 return (0); 12441 } 12442 12443 if (!uld_active(sc, ULD_TOM)) { 12444 rc = t4_activate_uld(sc, ULD_TOM); 12445 if (rc == EAGAIN) { 12446 log(LOG_WARNING, 12447 "You must kldload t4_tom.ko before trying " 12448 "to enable TOE on a cxgbe interface.\n"); 12449 } 12450 if (rc != 0) 12451 return (rc); 12452 KASSERT(sc->tom_softc != NULL, 12453 ("%s: TOM activated but softc NULL", __func__)); 12454 KASSERT(uld_active(sc, ULD_TOM), 12455 ("%s: TOM activated but flag not set", __func__)); 12456 } 12457 12458 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 12459 if (!uld_active(sc, ULD_IWARP)) 12460 (void) t4_activate_uld(sc, ULD_IWARP); 12461 if (!uld_active(sc, ULD_ISCSI)) 12462 (void) t4_activate_uld(sc, ULD_ISCSI); 12463 12464 pi->uld_vis++; 12465 setbit(&sc->offload_map, pi->port_id); 12466 } else { 12467 pi->uld_vis--; 12468 12469 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 12470 return (0); 12471 12472 KASSERT(uld_active(sc, ULD_TOM), 12473 ("%s: TOM never initialized?", __func__)); 12474 clrbit(&sc->offload_map, pi->port_id); 12475 } 12476 12477 return (0); 12478 } 12479 12480 /* 12481 * Add an upper layer driver to the global list. 12482 */ 12483 int 12484 t4_register_uld(struct uld_info *ui, int id) 12485 { 12486 int rc; 12487 12488 if (id < 0 || id > ULD_MAX) 12489 return (EINVAL); 12490 sx_xlock(&t4_uld_list_lock); 12491 if (t4_uld_list[id] != NULL) 12492 rc = EEXIST; 12493 else { 12494 t4_uld_list[id] = ui; 12495 rc = 0; 12496 } 12497 sx_xunlock(&t4_uld_list_lock); 12498 return (rc); 12499 } 12500 12501 int 12502 t4_unregister_uld(struct uld_info *ui, int id) 12503 { 12504 12505 if (id < 0 || id > ULD_MAX) 12506 return (EINVAL); 12507 sx_xlock(&t4_uld_list_lock); 12508 MPASS(t4_uld_list[id] == ui); 12509 t4_uld_list[id] = NULL; 12510 sx_xunlock(&t4_uld_list_lock); 12511 return (0); 12512 } 12513 12514 int 12515 t4_activate_uld(struct adapter *sc, int id) 12516 { 12517 int rc; 12518 12519 ASSERT_SYNCHRONIZED_OP(sc); 12520 12521 if (id < 0 || id > ULD_MAX) 12522 return (EINVAL); 12523 12524 /* Adapter needs to be initialized before any ULD can be activated. */ 12525 if (!(sc->flags & FULL_INIT_DONE)) { 12526 rc = adapter_init(sc); 12527 if (rc != 0) 12528 return (rc); 12529 } 12530 12531 sx_slock(&t4_uld_list_lock); 12532 if (t4_uld_list[id] == NULL) 12533 rc = EAGAIN; /* load the KLD with this ULD and try again. */ 12534 else { 12535 rc = t4_uld_list[id]->uld_activate(sc); 12536 if (rc == 0) 12537 setbit(&sc->active_ulds, id); 12538 } 12539 sx_sunlock(&t4_uld_list_lock); 12540 12541 return (rc); 12542 } 12543 12544 int 12545 t4_deactivate_uld(struct adapter *sc, int id) 12546 { 12547 int rc; 12548 12549 ASSERT_SYNCHRONIZED_OP(sc); 12550 12551 if (id < 0 || id > ULD_MAX) 12552 return (EINVAL); 12553 12554 sx_slock(&t4_uld_list_lock); 12555 if (t4_uld_list[id] == NULL) 12556 rc = ENXIO; 12557 else { 12558 rc = t4_uld_list[id]->uld_deactivate(sc); 12559 if (rc == 0) 12560 clrbit(&sc->active_ulds, id); 12561 } 12562 sx_sunlock(&t4_uld_list_lock); 12563 12564 return (rc); 12565 } 12566 12567 static int 12568 deactivate_all_uld(struct adapter *sc) 12569 { 12570 int i, rc; 12571 12572 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld"); 12573 if (rc != 0) 12574 return (ENXIO); 12575 sx_slock(&t4_uld_list_lock); 12576 for (i = 0; i <= ULD_MAX; i++) { 12577 if (t4_uld_list[i] == NULL || !uld_active(sc, i)) 12578 continue; 12579 rc = t4_uld_list[i]->uld_deactivate(sc); 12580 if (rc != 0) 12581 break; 12582 clrbit(&sc->active_ulds, i); 12583 } 12584 sx_sunlock(&t4_uld_list_lock); 12585 end_synchronized_op(sc, 0); 12586 12587 return (rc); 12588 } 12589 12590 static void 12591 stop_all_uld(struct adapter *sc) 12592 { 12593 int i; 12594 12595 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldst") != 0) 12596 return; 12597 sx_slock(&t4_uld_list_lock); 12598 for (i = 0; i <= ULD_MAX; i++) { 12599 if (t4_uld_list[i] == NULL || !uld_active(sc, i) || 12600 t4_uld_list[i]->uld_stop == NULL) 12601 continue; 12602 (void) t4_uld_list[i]->uld_stop(sc); 12603 } 12604 sx_sunlock(&t4_uld_list_lock); 12605 end_synchronized_op(sc, 0); 12606 } 12607 12608 static void 12609 restart_all_uld(struct adapter *sc) 12610 { 12611 int i; 12612 12613 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldre") != 0) 12614 return; 12615 sx_slock(&t4_uld_list_lock); 12616 for (i = 0; i <= ULD_MAX; i++) { 12617 if (t4_uld_list[i] == NULL || !uld_active(sc, i) || 12618 t4_uld_list[i]->uld_restart == NULL) 12619 continue; 12620 (void) t4_uld_list[i]->uld_restart(sc); 12621 } 12622 sx_sunlock(&t4_uld_list_lock); 12623 end_synchronized_op(sc, 0); 12624 } 12625 12626 int 12627 uld_active(struct adapter *sc, int id) 12628 { 12629 12630 MPASS(id >= 0 && id <= ULD_MAX); 12631 12632 return (isset(&sc->active_ulds, id)); 12633 } 12634 #endif 12635 12636 #ifdef KERN_TLS 12637 static int 12638 ktls_capability(struct adapter *sc, bool enable) 12639 { 12640 ASSERT_SYNCHRONIZED_OP(sc); 12641 12642 if (!is_ktls(sc)) 12643 return (ENODEV); 12644 if (!is_t6(sc)) 12645 return (0); 12646 if (hw_off_limits(sc)) 12647 return (ENXIO); 12648 12649 if (enable) { 12650 if (sc->flags & KERN_TLS_ON) 12651 return (0); /* already on */ 12652 if (sc->offload_map != 0) { 12653 CH_WARN(sc, 12654 "Disable TOE on all interfaces associated with " 12655 "this adapter before trying to enable NIC TLS.\n"); 12656 return (EAGAIN); 12657 } 12658 return (t6_config_kern_tls(sc, true)); 12659 } else { 12660 /* 12661 * Nothing to do for disable. If TOE is enabled sometime later 12662 * then toe_capability will reconfigure the hardware. 12663 */ 12664 return (0); 12665 } 12666 } 12667 #endif 12668 12669 /* 12670 * t = ptr to tunable. 12671 * nc = number of CPUs. 12672 * c = compiled in default for that tunable. 12673 */ 12674 static void 12675 calculate_nqueues(int *t, int nc, const int c) 12676 { 12677 int nq; 12678 12679 if (*t > 0) 12680 return; 12681 nq = *t < 0 ? -*t : c; 12682 *t = min(nc, nq); 12683 } 12684 12685 /* 12686 * Come up with reasonable defaults for some of the tunables, provided they're 12687 * not set by the user (in which case we'll use the values as is). 12688 */ 12689 static void 12690 tweak_tunables(void) 12691 { 12692 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 12693 12694 if (t4_ntxq < 1) { 12695 #ifdef RSS 12696 t4_ntxq = rss_getnumbuckets(); 12697 #else 12698 calculate_nqueues(&t4_ntxq, nc, NTXQ); 12699 #endif 12700 } 12701 12702 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 12703 12704 if (t4_nrxq < 1) { 12705 #ifdef RSS 12706 t4_nrxq = rss_getnumbuckets(); 12707 #else 12708 calculate_nqueues(&t4_nrxq, nc, NRXQ); 12709 #endif 12710 } 12711 12712 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 12713 12714 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12715 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 12716 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 12717 #endif 12718 #ifdef TCP_OFFLOAD 12719 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 12720 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 12721 #endif 12722 12723 #if defined(TCP_OFFLOAD) || defined(KERN_TLS) 12724 if (t4_toecaps_allowed == -1) 12725 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 12726 #else 12727 if (t4_toecaps_allowed == -1) 12728 t4_toecaps_allowed = 0; 12729 #endif 12730 12731 #ifdef TCP_OFFLOAD 12732 if (t4_rdmacaps_allowed == -1) { 12733 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 12734 FW_CAPS_CONFIG_RDMA_RDMAC; 12735 } 12736 12737 if (t4_iscsicaps_allowed == -1) { 12738 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 12739 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 12740 FW_CAPS_CONFIG_ISCSI_T10DIF; 12741 } 12742 12743 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 12744 t4_tmr_idx_ofld = TMR_IDX_OFLD; 12745 12746 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 12747 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 12748 #else 12749 if (t4_rdmacaps_allowed == -1) 12750 t4_rdmacaps_allowed = 0; 12751 12752 if (t4_iscsicaps_allowed == -1) 12753 t4_iscsicaps_allowed = 0; 12754 #endif 12755 12756 #ifdef DEV_NETMAP 12757 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ); 12758 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ); 12759 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 12760 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 12761 #endif 12762 12763 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 12764 t4_tmr_idx = TMR_IDX; 12765 12766 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 12767 t4_pktc_idx = PKTC_IDX; 12768 12769 if (t4_qsize_txq < 128) 12770 t4_qsize_txq = 128; 12771 12772 if (t4_qsize_rxq < 128) 12773 t4_qsize_rxq = 128; 12774 while (t4_qsize_rxq & 7) 12775 t4_qsize_rxq++; 12776 12777 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 12778 12779 /* 12780 * Number of VIs to create per-port. The first VI is the "main" regular 12781 * VI for the port. The rest are additional virtual interfaces on the 12782 * same physical port. Note that the main VI does not have native 12783 * netmap support but the extra VIs do. 12784 * 12785 * Limit the number of VIs per port to the number of available 12786 * MAC addresses per port. 12787 */ 12788 if (t4_num_vis < 1) 12789 t4_num_vis = 1; 12790 if (t4_num_vis > nitems(vi_mac_funcs)) { 12791 t4_num_vis = nitems(vi_mac_funcs); 12792 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 12793 } 12794 12795 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 12796 pcie_relaxed_ordering = 1; 12797 #if defined(__i386__) || defined(__amd64__) 12798 if (cpu_vendor_id == CPU_VENDOR_INTEL) 12799 pcie_relaxed_ordering = 0; 12800 #endif 12801 } 12802 } 12803 12804 #ifdef DDB 12805 static void 12806 t4_dump_mem(struct adapter *sc, u_int addr, u_int len) 12807 { 12808 uint32_t base, j, off, pf, reg, save, win_pos; 12809 12810 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 12811 save = t4_read_reg(sc, reg); 12812 base = sc->memwin[2].mw_base; 12813 12814 if (is_t4(sc)) { 12815 pf = 0; 12816 win_pos = addr & ~0xf; /* start must be 16B aligned */ 12817 } else { 12818 pf = V_PFNUM(sc->pf); 12819 win_pos = addr & ~0x7f; /* start must be 128B aligned */ 12820 } 12821 off = addr - win_pos; 12822 t4_write_reg(sc, reg, win_pos | pf); 12823 t4_read_reg(sc, reg); 12824 12825 while (len > 0 && !db_pager_quit) { 12826 uint32_t buf[8]; 12827 for (j = 0; j < 8; j++, off += 4) 12828 buf[j] = htonl(t4_read_reg(sc, base + off)); 12829 12830 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 12831 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 12832 buf[7]); 12833 if (len <= sizeof(buf)) 12834 len = 0; 12835 else 12836 len -= sizeof(buf); 12837 } 12838 12839 t4_write_reg(sc, reg, save); 12840 t4_read_reg(sc, reg); 12841 } 12842 12843 static void 12844 t4_dump_tcb(struct adapter *sc, int tid) 12845 { 12846 uint32_t tcb_addr; 12847 12848 /* Dump TCB for the tid */ 12849 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 12850 tcb_addr += tid * TCB_SIZE; 12851 t4_dump_mem(sc, tcb_addr, TCB_SIZE); 12852 } 12853 12854 static void 12855 t4_dump_devlog(struct adapter *sc) 12856 { 12857 struct devlog_params *dparams = &sc->params.devlog; 12858 struct fw_devlog_e e; 12859 int i, first, j, m, nentries, rc; 12860 uint64_t ftstamp = UINT64_MAX; 12861 12862 if (dparams->start == 0) { 12863 db_printf("devlog params not valid\n"); 12864 return; 12865 } 12866 12867 nentries = dparams->size / sizeof(struct fw_devlog_e); 12868 m = fwmtype_to_hwmtype(dparams->memtype); 12869 12870 /* Find the first entry. */ 12871 first = -1; 12872 for (i = 0; i < nentries && !db_pager_quit; i++) { 12873 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12874 sizeof(e), (void *)&e); 12875 if (rc != 0) 12876 break; 12877 12878 if (e.timestamp == 0) 12879 break; 12880 12881 e.timestamp = be64toh(e.timestamp); 12882 if (e.timestamp < ftstamp) { 12883 ftstamp = e.timestamp; 12884 first = i; 12885 } 12886 } 12887 12888 if (first == -1) 12889 return; 12890 12891 i = first; 12892 do { 12893 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12894 sizeof(e), (void *)&e); 12895 if (rc != 0) 12896 return; 12897 12898 if (e.timestamp == 0) 12899 return; 12900 12901 e.timestamp = be64toh(e.timestamp); 12902 e.seqno = be32toh(e.seqno); 12903 for (j = 0; j < 8; j++) 12904 e.params[j] = be32toh(e.params[j]); 12905 12906 db_printf("%10d %15ju %8s %8s ", 12907 e.seqno, e.timestamp, 12908 (e.level < nitems(devlog_level_strings) ? 12909 devlog_level_strings[e.level] : "UNKNOWN"), 12910 (e.facility < nitems(devlog_facility_strings) ? 12911 devlog_facility_strings[e.facility] : "UNKNOWN")); 12912 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 12913 e.params[3], e.params[4], e.params[5], e.params[6], 12914 e.params[7]); 12915 12916 if (++i == nentries) 12917 i = 0; 12918 } while (i != first && !db_pager_quit); 12919 } 12920 12921 static DB_DEFINE_TABLE(show, t4, show_t4); 12922 12923 DB_TABLE_COMMAND_FLAGS(show_t4, devlog, db_show_devlog, CS_OWN) 12924 { 12925 device_t dev; 12926 int t; 12927 bool valid; 12928 12929 valid = false; 12930 t = db_read_token(); 12931 if (t == tIDENT) { 12932 dev = device_lookup_by_name(db_tok_string); 12933 valid = true; 12934 } 12935 db_skip_to_eol(); 12936 if (!valid) { 12937 db_printf("usage: show t4 devlog <nexus>\n"); 12938 return; 12939 } 12940 12941 if (dev == NULL) { 12942 db_printf("device not found\n"); 12943 return; 12944 } 12945 12946 t4_dump_devlog(device_get_softc(dev)); 12947 } 12948 12949 DB_TABLE_COMMAND_FLAGS(show_t4, tcb, db_show_t4tcb, CS_OWN) 12950 { 12951 device_t dev; 12952 int radix, tid, t; 12953 bool valid; 12954 12955 valid = false; 12956 radix = db_radix; 12957 db_radix = 10; 12958 t = db_read_token(); 12959 if (t == tIDENT) { 12960 dev = device_lookup_by_name(db_tok_string); 12961 t = db_read_token(); 12962 if (t == tNUMBER) { 12963 tid = db_tok_number; 12964 valid = true; 12965 } 12966 } 12967 db_radix = radix; 12968 db_skip_to_eol(); 12969 if (!valid) { 12970 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 12971 return; 12972 } 12973 12974 if (dev == NULL) { 12975 db_printf("device not found\n"); 12976 return; 12977 } 12978 if (tid < 0) { 12979 db_printf("invalid tid\n"); 12980 return; 12981 } 12982 12983 t4_dump_tcb(device_get_softc(dev), tid); 12984 } 12985 12986 DB_TABLE_COMMAND_FLAGS(show_t4, memdump, db_show_memdump, CS_OWN) 12987 { 12988 device_t dev; 12989 int radix, t; 12990 bool valid; 12991 12992 valid = false; 12993 radix = db_radix; 12994 db_radix = 10; 12995 t = db_read_token(); 12996 if (t == tIDENT) { 12997 dev = device_lookup_by_name(db_tok_string); 12998 t = db_read_token(); 12999 if (t == tNUMBER) { 13000 addr = db_tok_number; 13001 t = db_read_token(); 13002 if (t == tNUMBER) { 13003 count = db_tok_number; 13004 valid = true; 13005 } 13006 } 13007 } 13008 db_radix = radix; 13009 db_skip_to_eol(); 13010 if (!valid) { 13011 db_printf("usage: show t4 memdump <nexus> <addr> <len>\n"); 13012 return; 13013 } 13014 13015 if (dev == NULL) { 13016 db_printf("device not found\n"); 13017 return; 13018 } 13019 if (addr < 0) { 13020 db_printf("invalid address\n"); 13021 return; 13022 } 13023 if (count <= 0) { 13024 db_printf("invalid length\n"); 13025 return; 13026 } 13027 13028 t4_dump_mem(device_get_softc(dev), addr, count); 13029 } 13030 #endif 13031 13032 static eventhandler_tag vxlan_start_evtag; 13033 static eventhandler_tag vxlan_stop_evtag; 13034 13035 struct vxlan_evargs { 13036 if_t ifp; 13037 uint16_t port; 13038 }; 13039 13040 static void 13041 enable_vxlan_rx(struct adapter *sc) 13042 { 13043 int i, rc; 13044 struct port_info *pi; 13045 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 13046 13047 ASSERT_SYNCHRONIZED_OP(sc); 13048 13049 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) | 13050 F_VXLAN_EN); 13051 for_each_port(sc, i) { 13052 pi = sc->port[i]; 13053 if (pi->vxlan_tcam_entry == true) 13054 continue; 13055 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac, 13056 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 13057 true); 13058 if (rc < 0) { 13059 rc = -rc; 13060 CH_ERR(&pi->vi[0], 13061 "failed to add VXLAN TCAM entry: %d.\n", rc); 13062 } else { 13063 MPASS(rc == sc->rawf_base + pi->port_id); 13064 pi->vxlan_tcam_entry = true; 13065 } 13066 } 13067 } 13068 13069 static void 13070 t4_vxlan_start(struct adapter *sc, void *arg) 13071 { 13072 struct vxlan_evargs *v = arg; 13073 13074 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13075 return; 13076 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0) 13077 return; 13078 13079 if (sc->vxlan_refcount == 0) { 13080 sc->vxlan_port = v->port; 13081 sc->vxlan_refcount = 1; 13082 if (!hw_off_limits(sc)) 13083 enable_vxlan_rx(sc); 13084 } else if (sc->vxlan_port == v->port) { 13085 sc->vxlan_refcount++; 13086 } else { 13087 CH_ERR(sc, "VXLAN already configured on port %d; " 13088 "ignoring attempt to configure it on port %d\n", 13089 sc->vxlan_port, v->port); 13090 } 13091 end_synchronized_op(sc, 0); 13092 } 13093 13094 static void 13095 t4_vxlan_stop(struct adapter *sc, void *arg) 13096 { 13097 struct vxlan_evargs *v = arg; 13098 13099 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13100 return; 13101 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0) 13102 return; 13103 13104 /* 13105 * VXLANs may have been configured before the driver was loaded so we 13106 * may see more stops than starts. This is not handled cleanly but at 13107 * least we keep the refcount sane. 13108 */ 13109 if (sc->vxlan_port != v->port) 13110 goto done; 13111 if (sc->vxlan_refcount == 0) { 13112 CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; " 13113 "ignoring attempt to stop it again.\n", sc->vxlan_port); 13114 } else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc)) 13115 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0); 13116 done: 13117 end_synchronized_op(sc, 0); 13118 } 13119 13120 static void 13121 t4_vxlan_start_handler(void *arg __unused, if_t ifp, 13122 sa_family_t family, u_int port) 13123 { 13124 struct vxlan_evargs v; 13125 13126 MPASS(family == AF_INET || family == AF_INET6); 13127 v.ifp = ifp; 13128 v.port = port; 13129 13130 t4_iterate(t4_vxlan_start, &v); 13131 } 13132 13133 static void 13134 t4_vxlan_stop_handler(void *arg __unused, if_t ifp, sa_family_t family, 13135 u_int port) 13136 { 13137 struct vxlan_evargs v; 13138 13139 MPASS(family == AF_INET || family == AF_INET6); 13140 v.ifp = ifp; 13141 v.port = port; 13142 13143 t4_iterate(t4_vxlan_stop, &v); 13144 } 13145 13146 13147 static struct sx mlu; /* mod load unload */ 13148 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 13149 13150 static int 13151 mod_event(module_t mod, int cmd, void *arg) 13152 { 13153 int rc = 0; 13154 static int loaded = 0; 13155 13156 switch (cmd) { 13157 case MOD_LOAD: 13158 sx_xlock(&mlu); 13159 if (loaded++ == 0) { 13160 t4_sge_modload(); 13161 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13162 t4_filter_rpl, CPL_COOKIE_FILTER); 13163 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 13164 do_l2t_write_rpl, CPL_COOKIE_FILTER); 13165 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 13166 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 13167 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13168 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 13169 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 13170 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 13171 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 13172 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 13173 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 13174 do_smt_write_rpl); 13175 sx_init(&t4_list_lock, "T4/T5 adapters"); 13176 SLIST_INIT(&t4_list); 13177 callout_init(&fatal_callout, 1); 13178 #ifdef TCP_OFFLOAD 13179 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 13180 #endif 13181 #ifdef INET6 13182 t4_clip_modload(); 13183 #endif 13184 #ifdef KERN_TLS 13185 t6_ktls_modload(); 13186 #endif 13187 t4_tracer_modload(); 13188 tweak_tunables(); 13189 vxlan_start_evtag = 13190 EVENTHANDLER_REGISTER(vxlan_start, 13191 t4_vxlan_start_handler, NULL, 13192 EVENTHANDLER_PRI_ANY); 13193 vxlan_stop_evtag = 13194 EVENTHANDLER_REGISTER(vxlan_stop, 13195 t4_vxlan_stop_handler, NULL, 13196 EVENTHANDLER_PRI_ANY); 13197 reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK, 13198 taskqueue_thread_enqueue, &reset_tq); 13199 taskqueue_start_threads(&reset_tq, 1, PI_SOFT, 13200 "t4_rst_thr"); 13201 } 13202 sx_xunlock(&mlu); 13203 break; 13204 13205 case MOD_UNLOAD: 13206 sx_xlock(&mlu); 13207 if (--loaded == 0) { 13208 #ifdef TCP_OFFLOAD 13209 int i; 13210 #endif 13211 int tries; 13212 13213 taskqueue_free(reset_tq); 13214 13215 tries = 0; 13216 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 13217 uprintf("%ju clusters with custom free routine " 13218 "still is use.\n", t4_sge_extfree_refs()); 13219 pause("t4unload", 2 * hz); 13220 } 13221 13222 sx_slock(&t4_list_lock); 13223 if (!SLIST_EMPTY(&t4_list)) { 13224 rc = EBUSY; 13225 sx_sunlock(&t4_list_lock); 13226 goto done_unload; 13227 } 13228 #ifdef TCP_OFFLOAD 13229 sx_slock(&t4_uld_list_lock); 13230 for (i = 0; i <= ULD_MAX; i++) { 13231 if (t4_uld_list[i] != NULL) { 13232 rc = EBUSY; 13233 sx_sunlock(&t4_uld_list_lock); 13234 sx_sunlock(&t4_list_lock); 13235 goto done_unload; 13236 } 13237 } 13238 sx_sunlock(&t4_uld_list_lock); 13239 #endif 13240 sx_sunlock(&t4_list_lock); 13241 13242 if (t4_sge_extfree_refs() == 0) { 13243 EVENTHANDLER_DEREGISTER(vxlan_start, 13244 vxlan_start_evtag); 13245 EVENTHANDLER_DEREGISTER(vxlan_stop, 13246 vxlan_stop_evtag); 13247 t4_tracer_modunload(); 13248 #ifdef KERN_TLS 13249 t6_ktls_modunload(); 13250 #endif 13251 #ifdef INET6 13252 t4_clip_modunload(); 13253 #endif 13254 #ifdef TCP_OFFLOAD 13255 sx_destroy(&t4_uld_list_lock); 13256 #endif 13257 sx_destroy(&t4_list_lock); 13258 t4_sge_modunload(); 13259 loaded = 0; 13260 } else { 13261 rc = EBUSY; 13262 loaded++; /* undo earlier decrement */ 13263 } 13264 } 13265 done_unload: 13266 sx_xunlock(&mlu); 13267 break; 13268 } 13269 13270 return (rc); 13271 } 13272 13273 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0); 13274 MODULE_VERSION(t4nex, 1); 13275 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 13276 #ifdef DEV_NETMAP 13277 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 13278 #endif /* DEV_NETMAP */ 13279 13280 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0); 13281 MODULE_VERSION(t5nex, 1); 13282 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 13283 #ifdef DEV_NETMAP 13284 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 13285 #endif /* DEV_NETMAP */ 13286 13287 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0); 13288 MODULE_VERSION(t6nex, 1); 13289 MODULE_DEPEND(t6nex, crypto, 1, 1, 1); 13290 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 13291 #ifdef DEV_NETMAP 13292 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 13293 #endif /* DEV_NETMAP */ 13294 13295 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0); 13296 MODULE_VERSION(cxgbe, 1); 13297 13298 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0); 13299 MODULE_VERSION(cxl, 1); 13300 13301 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0); 13302 MODULE_VERSION(cc, 1); 13303 13304 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0); 13305 MODULE_VERSION(vcxgbe, 1); 13306 13307 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0); 13308 MODULE_VERSION(vcxl, 1); 13309 13310 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0); 13311 MODULE_VERSION(vcc, 1); 13312