1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "opt_ddb.h" 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_kern_tls.h" 35 #include "opt_ratelimit.h" 36 #include "opt_rss.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/priv.h> 41 #include <sys/kernel.h> 42 #include <sys/bus.h> 43 #include <sys/eventhandler.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #ifdef KERN_TLS 69 #include <netinet/tcp_seq.h> 70 #endif 71 #if defined(__i386__) || defined(__amd64__) 72 #include <machine/md_var.h> 73 #include <machine/cputypes.h> 74 #include <vm/vm.h> 75 #include <vm/pmap.h> 76 #endif 77 #ifdef DDB 78 #include <ddb/ddb.h> 79 #include <ddb/db_lex.h> 80 #endif 81 82 #include "common/common.h" 83 #include "common/t4_msg.h" 84 #include "common/t4_regs.h" 85 #include "common/t4_regs_values.h" 86 #include "cudbg/cudbg.h" 87 #include "t4_clip.h" 88 #include "t4_ioctl.h" 89 #include "t4_l2t.h" 90 #include "t4_mp_ring.h" 91 #include "t4_if.h" 92 #include "t4_smt.h" 93 94 /* T4 bus driver interface */ 95 static int t4_probe(device_t); 96 static int t4_attach(device_t); 97 static int t4_detach(device_t); 98 static int t4_child_location(device_t, device_t, struct sbuf *); 99 static int t4_ready(device_t); 100 static int t4_read_port_device(device_t, int, device_t *); 101 static int t4_suspend(device_t); 102 static int t4_resume(device_t); 103 static int t4_reset_prepare(device_t, device_t); 104 static int t4_reset_post(device_t, device_t); 105 static device_method_t t4_methods[] = { 106 DEVMETHOD(device_probe, t4_probe), 107 DEVMETHOD(device_attach, t4_attach), 108 DEVMETHOD(device_detach, t4_detach), 109 DEVMETHOD(device_suspend, t4_suspend), 110 DEVMETHOD(device_resume, t4_resume), 111 112 DEVMETHOD(bus_child_location, t4_child_location), 113 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 114 DEVMETHOD(bus_reset_post, t4_reset_post), 115 116 DEVMETHOD(t4_is_main_ready, t4_ready), 117 DEVMETHOD(t4_read_port_device, t4_read_port_device), 118 119 DEVMETHOD_END 120 }; 121 static driver_t t4_driver = { 122 "t4nex", 123 t4_methods, 124 sizeof(struct adapter) 125 }; 126 127 128 /* T4 port (cxgbe) interface */ 129 static int cxgbe_probe(device_t); 130 static int cxgbe_attach(device_t); 131 static int cxgbe_detach(device_t); 132 device_method_t cxgbe_methods[] = { 133 DEVMETHOD(device_probe, cxgbe_probe), 134 DEVMETHOD(device_attach, cxgbe_attach), 135 DEVMETHOD(device_detach, cxgbe_detach), 136 { 0, 0 } 137 }; 138 static driver_t cxgbe_driver = { 139 "cxgbe", 140 cxgbe_methods, 141 sizeof(struct port_info) 142 }; 143 144 /* T4 VI (vcxgbe) interface */ 145 static int vcxgbe_probe(device_t); 146 static int vcxgbe_attach(device_t); 147 static int vcxgbe_detach(device_t); 148 static device_method_t vcxgbe_methods[] = { 149 DEVMETHOD(device_probe, vcxgbe_probe), 150 DEVMETHOD(device_attach, vcxgbe_attach), 151 DEVMETHOD(device_detach, vcxgbe_detach), 152 { 0, 0 } 153 }; 154 static driver_t vcxgbe_driver = { 155 "vcxgbe", 156 vcxgbe_methods, 157 sizeof(struct vi_info) 158 }; 159 160 static d_ioctl_t t4_ioctl; 161 162 static struct cdevsw t4_cdevsw = { 163 .d_version = D_VERSION, 164 .d_ioctl = t4_ioctl, 165 .d_name = "t4nex", 166 }; 167 168 /* T5 bus driver interface */ 169 static int t5_probe(device_t); 170 static device_method_t t5_methods[] = { 171 DEVMETHOD(device_probe, t5_probe), 172 DEVMETHOD(device_attach, t4_attach), 173 DEVMETHOD(device_detach, t4_detach), 174 DEVMETHOD(device_suspend, t4_suspend), 175 DEVMETHOD(device_resume, t4_resume), 176 177 DEVMETHOD(bus_child_location, t4_child_location), 178 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 179 DEVMETHOD(bus_reset_post, t4_reset_post), 180 181 DEVMETHOD(t4_is_main_ready, t4_ready), 182 DEVMETHOD(t4_read_port_device, t4_read_port_device), 183 184 DEVMETHOD_END 185 }; 186 static driver_t t5_driver = { 187 "t5nex", 188 t5_methods, 189 sizeof(struct adapter) 190 }; 191 192 193 /* T5 port (cxl) interface */ 194 static driver_t cxl_driver = { 195 "cxl", 196 cxgbe_methods, 197 sizeof(struct port_info) 198 }; 199 200 /* T5 VI (vcxl) interface */ 201 static driver_t vcxl_driver = { 202 "vcxl", 203 vcxgbe_methods, 204 sizeof(struct vi_info) 205 }; 206 207 /* T6 bus driver interface */ 208 static int t6_probe(device_t); 209 static device_method_t t6_methods[] = { 210 DEVMETHOD(device_probe, t6_probe), 211 DEVMETHOD(device_attach, t4_attach), 212 DEVMETHOD(device_detach, t4_detach), 213 DEVMETHOD(device_suspend, t4_suspend), 214 DEVMETHOD(device_resume, t4_resume), 215 216 DEVMETHOD(bus_child_location, t4_child_location), 217 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 218 DEVMETHOD(bus_reset_post, t4_reset_post), 219 220 DEVMETHOD(t4_is_main_ready, t4_ready), 221 DEVMETHOD(t4_read_port_device, t4_read_port_device), 222 223 DEVMETHOD_END 224 }; 225 static driver_t t6_driver = { 226 "t6nex", 227 t6_methods, 228 sizeof(struct adapter) 229 }; 230 231 232 /* T6 port (cc) interface */ 233 static driver_t cc_driver = { 234 "cc", 235 cxgbe_methods, 236 sizeof(struct port_info) 237 }; 238 239 /* T6 VI (vcc) interface */ 240 static driver_t vcc_driver = { 241 "vcc", 242 vcxgbe_methods, 243 sizeof(struct vi_info) 244 }; 245 246 /* ifnet interface */ 247 static void cxgbe_init(void *); 248 static int cxgbe_ioctl(if_t, unsigned long, caddr_t); 249 static int cxgbe_transmit(if_t, struct mbuf *); 250 static void cxgbe_qflush(if_t); 251 #if defined(KERN_TLS) || defined(RATELIMIT) 252 static int cxgbe_snd_tag_alloc(if_t, union if_snd_tag_alloc_params *, 253 struct m_snd_tag **); 254 #endif 255 256 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 257 258 /* 259 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 260 * then ADAPTER_LOCK, then t4_uld_list_lock. 261 */ 262 static struct sx t4_list_lock; 263 SLIST_HEAD(, adapter) t4_list; 264 #ifdef TCP_OFFLOAD 265 static struct sx t4_uld_list_lock; 266 struct uld_info *t4_uld_list[ULD_MAX + 1]; 267 #endif 268 269 /* 270 * Tunables. See tweak_tunables() too. 271 * 272 * Each tunable is set to a default value here if it's known at compile-time. 273 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 274 * provide a reasonable default (upto n) when the driver is loaded. 275 * 276 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 277 * T5 are under hw.cxl. 278 */ 279 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 280 "cxgbe(4) parameters"); 281 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 282 "cxgbe(4) T5+ parameters"); 283 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 284 "cxgbe(4) TOE parameters"); 285 286 /* 287 * Number of queues for tx and rx, NIC and offload. 288 */ 289 #define NTXQ 16 290 int t4_ntxq = -NTXQ; 291 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 292 "Number of TX queues per port"); 293 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 294 295 #define NRXQ 8 296 int t4_nrxq = -NRXQ; 297 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 298 "Number of RX queues per port"); 299 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 300 301 #define NTXQ_VI 1 302 static int t4_ntxq_vi = -NTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 304 "Number of TX queues per VI"); 305 306 #define NRXQ_VI 1 307 static int t4_nrxq_vi = -NRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 309 "Number of RX queues per VI"); 310 311 static int t4_rsrv_noflowq = 0; 312 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 313 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 314 315 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 316 #define NOFLDTXQ 8 317 static int t4_nofldtxq = -NOFLDTXQ; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 319 "Number of offload TX queues per port"); 320 321 #define NOFLDRXQ 2 322 static int t4_nofldrxq = -NOFLDRXQ; 323 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 324 "Number of offload RX queues per port"); 325 326 #define NOFLDTXQ_VI 1 327 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 328 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 329 "Number of offload TX queues per VI"); 330 331 #define NOFLDRXQ_VI 1 332 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 333 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 334 "Number of offload RX queues per VI"); 335 336 #define TMR_IDX_OFLD 1 337 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 338 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 339 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 340 341 #define PKTC_IDX_OFLD (-1) 342 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 343 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 344 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 345 346 /* 0 means chip/fw default, non-zero number is value in microseconds */ 347 static u_long t4_toe_keepalive_idle = 0; 348 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 349 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 350 351 /* 0 means chip/fw default, non-zero number is value in microseconds */ 352 static u_long t4_toe_keepalive_interval = 0; 353 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 354 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 355 356 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 357 static int t4_toe_keepalive_count = 0; 358 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 359 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 360 361 /* 0 means chip/fw default, non-zero number is value in microseconds */ 362 static u_long t4_toe_rexmt_min = 0; 363 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 365 366 /* 0 means chip/fw default, non-zero number is value in microseconds */ 367 static u_long t4_toe_rexmt_max = 0; 368 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 369 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 370 371 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 372 static int t4_toe_rexmt_count = 0; 373 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 375 376 /* -1 means chip/fw default, other values are raw backoff values to use */ 377 static int t4_toe_rexmt_backoff[16] = { 378 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 379 }; 380 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, 381 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 382 "cxgbe(4) TOE retransmit backoff values"); 383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[0], 0, ""); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[1], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[2], 0, ""); 389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 390 &t4_toe_rexmt_backoff[3], 0, ""); 391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 392 &t4_toe_rexmt_backoff[4], 0, ""); 393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 394 &t4_toe_rexmt_backoff[5], 0, ""); 395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 396 &t4_toe_rexmt_backoff[6], 0, ""); 397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 398 &t4_toe_rexmt_backoff[7], 0, ""); 399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 400 &t4_toe_rexmt_backoff[8], 0, ""); 401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 402 &t4_toe_rexmt_backoff[9], 0, ""); 403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 404 &t4_toe_rexmt_backoff[10], 0, ""); 405 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 406 &t4_toe_rexmt_backoff[11], 0, ""); 407 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 408 &t4_toe_rexmt_backoff[12], 0, ""); 409 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 410 &t4_toe_rexmt_backoff[13], 0, ""); 411 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 412 &t4_toe_rexmt_backoff[14], 0, ""); 413 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 414 &t4_toe_rexmt_backoff[15], 0, ""); 415 416 int t4_ddp_rcvbuf_len = 256 * 1024; 417 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_len, CTLFLAG_RWTUN, 418 &t4_ddp_rcvbuf_len, 0, "length of each DDP RX buffer"); 419 420 unsigned int t4_ddp_rcvbuf_cache = 4; 421 SYSCTL_UINT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_cache, CTLFLAG_RWTUN, 422 &t4_ddp_rcvbuf_cache, 0, 423 "maximum number of free DDP RX buffers to cache per connection"); 424 #endif 425 426 #ifdef DEV_NETMAP 427 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */ 428 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */ 429 static int t4_native_netmap = NN_EXTRA_VI; 430 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap, 431 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs"); 432 433 #define NNMTXQ 8 434 static int t4_nnmtxq = -NNMTXQ; 435 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0, 436 "Number of netmap TX queues"); 437 438 #define NNMRXQ 8 439 static int t4_nnmrxq = -NNMRXQ; 440 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0, 441 "Number of netmap RX queues"); 442 443 #define NNMTXQ_VI 2 444 static int t4_nnmtxq_vi = -NNMTXQ_VI; 445 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 446 "Number of netmap TX queues per VI"); 447 448 #define NNMRXQ_VI 2 449 static int t4_nnmrxq_vi = -NNMRXQ_VI; 450 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 451 "Number of netmap RX queues per VI"); 452 #endif 453 454 /* 455 * Holdoff parameters for ports. 456 */ 457 #define TMR_IDX 1 458 int t4_tmr_idx = TMR_IDX; 459 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 460 0, "Holdoff timer index"); 461 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 462 463 #define PKTC_IDX (-1) 464 int t4_pktc_idx = PKTC_IDX; 465 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 466 0, "Holdoff packet counter index"); 467 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 468 469 /* 470 * Size (# of entries) of each tx and rx queue. 471 */ 472 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 473 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 474 "Number of descriptors in each TX queue"); 475 476 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 477 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 478 "Number of descriptors in each RX queue"); 479 480 /* 481 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 482 */ 483 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 484 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 485 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 486 487 /* 488 * Configuration file. All the _CF names here are special. 489 */ 490 #define DEFAULT_CF "default" 491 #define BUILTIN_CF "built-in" 492 #define FLASH_CF "flash" 493 #define UWIRE_CF "uwire" 494 #define FPGA_CF "fpga" 495 static char t4_cfg_file[32] = DEFAULT_CF; 496 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 497 sizeof(t4_cfg_file), "Firmware configuration file"); 498 499 /* 500 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 501 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 502 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 503 * mark or when signalled to do so, 0 to never emit PAUSE. 504 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 505 * negotiated settings will override rx_pause/tx_pause. 506 * Otherwise rx_pause/tx_pause are applied forcibly. 507 */ 508 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 509 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 510 &t4_pause_settings, 0, 511 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 512 513 /* 514 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 515 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 516 * 0 to disable FEC. 517 */ 518 static int t4_fec = -1; 519 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 520 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 521 522 /* 523 * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it 524 * issues to the firmware. If the firmware doesn't support FORCE_FEC then the 525 * driver runs as if this is set to 0. 526 * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay. 527 * 0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the 528 * transceiver. Multiple FEC bits may not be okay but will be passed on to 529 * the firmware anyway (may result in l1cfg errors with old firmwares). 530 * 1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO 531 * means set all FEC bits that are valid for the speed. 532 */ 533 static int t4_force_fec = -1; 534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0, 535 "Controls the use of FORCE_FEC bit in L1 configuration."); 536 537 /* 538 * Link autonegotiation. 539 * -1 to run with the firmware default. 540 * 0 to disable. 541 * 1 to enable. 542 */ 543 static int t4_autoneg = -1; 544 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 545 "Link autonegotiation"); 546 547 /* 548 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 549 * encouraged respectively). '-n' is the same as 'n' except the firmware 550 * version used in the checks is read from the firmware bundled with the driver. 551 */ 552 static int t4_fw_install = 1; 553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 554 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 555 556 /* 557 * ASIC features that will be used. Disable the ones you don't want so that the 558 * chip resources aren't wasted on features that will not be used. 559 */ 560 static int t4_nbmcaps_allowed = 0; 561 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 562 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 563 564 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 565 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 566 &t4_linkcaps_allowed, 0, "Default link capabilities"); 567 568 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 569 FW_CAPS_CONFIG_SWITCH_EGRESS; 570 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 571 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 572 573 #ifdef RATELIMIT 574 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 575 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 576 #else 577 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 578 FW_CAPS_CONFIG_NIC_HASHFILTER; 579 #endif 580 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 581 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 582 583 static int t4_toecaps_allowed = -1; 584 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 585 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 586 587 static int t4_rdmacaps_allowed = -1; 588 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 589 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 590 591 static int t4_cryptocaps_allowed = -1; 592 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 593 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 594 595 static int t4_iscsicaps_allowed = -1; 596 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 597 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 598 599 static int t4_fcoecaps_allowed = 0; 600 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 601 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 602 603 static int t5_write_combine = 0; 604 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 605 0, "Use WC instead of UC for BAR2"); 606 607 /* From t4_sysctls: doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"} */ 608 static int t4_doorbells_allowed = 0xf; 609 SYSCTL_INT(_hw_cxgbe, OID_AUTO, doorbells_allowed, CTLFLAG_RDTUN, 610 &t4_doorbells_allowed, 0, "Limit tx queues to these doorbells"); 611 612 static int t4_num_vis = 1; 613 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 614 "Number of VIs per port"); 615 616 /* 617 * PCIe Relaxed Ordering. 618 * -1: driver should figure out a good value. 619 * 0: disable RO. 620 * 1: enable RO. 621 * 2: leave RO alone. 622 */ 623 static int pcie_relaxed_ordering = -1; 624 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 625 &pcie_relaxed_ordering, 0, 626 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 627 628 static int t4_panic_on_fatal_err = 0; 629 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN, 630 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 631 632 static int t4_reset_on_fatal_err = 0; 633 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN, 634 &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors"); 635 636 static int t4_clock_gate_on_suspend = 0; 637 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN, 638 &t4_clock_gate_on_suspend, 0, "gate the clock on suspend"); 639 640 static int t4_tx_vm_wr = 0; 641 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0, 642 "Use VM work requests to transmit packets."); 643 644 /* 645 * Set to non-zero to enable the attack filter. A packet that matches any of 646 * these conditions will get dropped on ingress: 647 * 1) IP && source address == destination address. 648 * 2) TCP/IP && source address is not a unicast address. 649 * 3) TCP/IP && destination address is not a unicast address. 650 * 4) IP && source address is loopback (127.x.y.z). 651 * 5) IP && destination address is loopback (127.x.y.z). 652 * 6) IPv6 && source address == destination address. 653 * 7) IPv6 && source address is not a unicast address. 654 * 8) IPv6 && source address is loopback (::1/128). 655 * 9) IPv6 && destination address is loopback (::1/128). 656 * 10) IPv6 && source address is unspecified (::/128). 657 * 11) IPv6 && destination address is unspecified (::/128). 658 * 12) TCP/IPv6 && source address is multicast (ff00::/8). 659 * 13) TCP/IPv6 && destination address is multicast (ff00::/8). 660 */ 661 static int t4_attack_filter = 0; 662 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN, 663 &t4_attack_filter, 0, "Drop suspicious traffic"); 664 665 static int t4_drop_ip_fragments = 0; 666 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN, 667 &t4_drop_ip_fragments, 0, "Drop IP fragments"); 668 669 static int t4_drop_pkts_with_l2_errors = 1; 670 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN, 671 &t4_drop_pkts_with_l2_errors, 0, 672 "Drop all frames with Layer 2 length or checksum errors"); 673 674 static int t4_drop_pkts_with_l3_errors = 0; 675 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN, 676 &t4_drop_pkts_with_l3_errors, 0, 677 "Drop all frames with IP version, length, or checksum errors"); 678 679 static int t4_drop_pkts_with_l4_errors = 0; 680 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN, 681 &t4_drop_pkts_with_l4_errors, 0, 682 "Drop all frames with Layer 4 length, checksum, or other errors"); 683 684 #ifdef TCP_OFFLOAD 685 /* 686 * TOE tunables. 687 */ 688 static int t4_cop_managed_offloading = 0; 689 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 690 &t4_cop_managed_offloading, 0, 691 "COP (Connection Offload Policy) controls all TOE offload"); 692 #endif 693 694 #ifdef KERN_TLS 695 /* 696 * This enables KERN_TLS for all adapters if set. 697 */ 698 static int t4_kern_tls = 0; 699 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0, 700 "Enable KERN_TLS mode for T6 adapters"); 701 702 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 703 "cxgbe(4) KERN_TLS parameters"); 704 705 static int t4_tls_inline_keys = 0; 706 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN, 707 &t4_tls_inline_keys, 0, 708 "Always pass TLS keys in work requests (1) or attempt to store TLS keys " 709 "in card memory."); 710 711 static int t4_tls_combo_wrs = 0; 712 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs, 713 0, "Attempt to combine TCB field updates with TLS record work requests."); 714 #endif 715 716 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 717 static int vi_mac_funcs[] = { 718 FW_VI_FUNC_ETH, 719 FW_VI_FUNC_OFLD, 720 FW_VI_FUNC_IWARP, 721 FW_VI_FUNC_OPENISCSI, 722 FW_VI_FUNC_OPENFCOE, 723 FW_VI_FUNC_FOISCSI, 724 FW_VI_FUNC_FOFCOE, 725 }; 726 727 struct intrs_and_queues { 728 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 729 uint16_t num_vis; /* number of VIs for each port */ 730 uint16_t nirq; /* Total # of vectors */ 731 uint16_t ntxq; /* # of NIC txq's for each port */ 732 uint16_t nrxq; /* # of NIC rxq's for each port */ 733 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 734 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 735 uint16_t nnmtxq; /* # of netmap txq's */ 736 uint16_t nnmrxq; /* # of netmap rxq's */ 737 738 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 739 uint16_t ntxq_vi; /* # of NIC txq's */ 740 uint16_t nrxq_vi; /* # of NIC rxq's */ 741 uint16_t nofldtxq_vi; /* # of TOE txq's */ 742 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 743 uint16_t nnmtxq_vi; /* # of netmap txq's */ 744 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 745 }; 746 747 static void setup_memwin(struct adapter *); 748 static void position_memwin(struct adapter *, int, uint32_t); 749 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 750 static int fwmtype_to_hwmtype(int); 751 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 752 uint32_t *); 753 static int fixup_devlog_params(struct adapter *); 754 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 755 static int contact_firmware(struct adapter *); 756 static int partition_resources(struct adapter *); 757 static int get_params__pre_init(struct adapter *); 758 static int set_params__pre_init(struct adapter *); 759 static int get_params__post_init(struct adapter *); 760 static int set_params__post_init(struct adapter *); 761 static void t4_set_desc(struct adapter *); 762 static bool fixed_ifmedia(struct port_info *); 763 static void build_medialist(struct port_info *); 764 static void init_link_config(struct port_info *); 765 static int fixup_link_config(struct port_info *); 766 static int apply_link_config(struct port_info *); 767 static int cxgbe_init_synchronized(struct vi_info *); 768 static int cxgbe_uninit_synchronized(struct vi_info *); 769 static int adapter_full_init(struct adapter *); 770 static void adapter_full_uninit(struct adapter *); 771 static int vi_full_init(struct vi_info *); 772 static void vi_full_uninit(struct vi_info *); 773 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *); 774 static void quiesce_txq(struct sge_txq *); 775 static void quiesce_wrq(struct sge_wrq *); 776 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 777 static void quiesce_vi(struct vi_info *); 778 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 779 driver_intr_t *, void *, char *); 780 static int t4_free_irq(struct adapter *, struct irq *); 781 static void t4_init_atid_table(struct adapter *); 782 static void t4_free_atid_table(struct adapter *); 783 static void stop_atid_allocator(struct adapter *); 784 static void restart_atid_allocator(struct adapter *); 785 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 786 static void vi_refresh_stats(struct vi_info *); 787 static void cxgbe_refresh_stats(struct vi_info *); 788 static void cxgbe_tick(void *); 789 static void vi_tick(void *); 790 static void cxgbe_sysctls(struct port_info *); 791 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 792 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 793 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 794 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 795 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 796 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS); 797 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 798 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 799 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 800 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 801 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 802 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS); 803 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS); 804 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS); 805 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 806 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS); 807 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 808 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 809 static int sysctl_vdd(SYSCTL_HANDLER_ARGS); 810 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS); 811 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 812 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 813 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 814 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 815 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 816 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 817 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 818 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 819 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 820 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS); 821 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 822 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 823 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 824 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 825 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 826 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 827 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 828 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 829 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 830 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 831 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 832 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 833 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 834 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 835 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS); 836 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 837 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 838 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 839 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 840 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 841 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 842 static int sysctl_reset(SYSCTL_HANDLER_ARGS); 843 #ifdef TCP_OFFLOAD 844 static int sysctl_tls(SYSCTL_HANDLER_ARGS); 845 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 846 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 847 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 848 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 849 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 850 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 851 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 852 #endif 853 static int get_sge_context(struct adapter *, struct t4_sge_context *); 854 static int load_fw(struct adapter *, struct t4_data *); 855 static int load_cfg(struct adapter *, struct t4_data *); 856 static int load_boot(struct adapter *, struct t4_bootrom *); 857 static int load_bootcfg(struct adapter *, struct t4_data *); 858 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 859 static void free_offload_policy(struct t4_offload_policy *); 860 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 861 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 862 static int read_i2c(struct adapter *, struct t4_i2c_data *); 863 static int clear_stats(struct adapter *, u_int); 864 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *); 865 static int release_clip_addr(struct adapter *, struct t4_clip_addr *); 866 static inline int stop_adapter(struct adapter *); 867 static inline void set_adapter_hwstatus(struct adapter *, const bool); 868 static int stop_lld(struct adapter *); 869 static inline int restart_adapter(struct adapter *); 870 static int restart_lld(struct adapter *); 871 #ifdef TCP_OFFLOAD 872 static int toe_capability(struct vi_info *, bool); 873 static int deactivate_all_uld(struct adapter *); 874 static void stop_all_uld(struct adapter *); 875 static void restart_all_uld(struct adapter *); 876 #endif 877 #ifdef KERN_TLS 878 static int ktls_capability(struct adapter *, bool); 879 #endif 880 static int mod_event(module_t, int, void *); 881 static int notify_siblings(device_t, int); 882 static uint64_t vi_get_counter(if_t, ift_counter); 883 static uint64_t cxgbe_get_counter(if_t, ift_counter); 884 static void enable_vxlan_rx(struct adapter *); 885 static void reset_adapter_task(void *, int); 886 static void fatal_error_task(void *, int); 887 static void dump_devlog(struct adapter *); 888 static void dump_cim_regs(struct adapter *); 889 static void dump_cimla(struct adapter *); 890 891 struct { 892 uint16_t device; 893 char *desc; 894 } t4_pciids[] = { 895 {0xa000, "Chelsio Terminator 4 FPGA"}, 896 {0x4400, "Chelsio T440-dbg"}, 897 {0x4401, "Chelsio T420-CR"}, 898 {0x4402, "Chelsio T422-CR"}, 899 {0x4403, "Chelsio T440-CR"}, 900 {0x4404, "Chelsio T420-BCH"}, 901 {0x4405, "Chelsio T440-BCH"}, 902 {0x4406, "Chelsio T440-CH"}, 903 {0x4407, "Chelsio T420-SO"}, 904 {0x4408, "Chelsio T420-CX"}, 905 {0x4409, "Chelsio T420-BT"}, 906 {0x440a, "Chelsio T404-BT"}, 907 {0x440e, "Chelsio T440-LP-CR"}, 908 }, t5_pciids[] = { 909 {0xb000, "Chelsio Terminator 5 FPGA"}, 910 {0x5400, "Chelsio T580-dbg"}, 911 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 912 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 913 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 914 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 915 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 916 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 917 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 918 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 919 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 920 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 921 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 922 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 923 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 924 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 925 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 926 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 927 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 928 929 /* Custom */ 930 {0x5483, "Custom T540-CR"}, 931 {0x5484, "Custom T540-BT"}, 932 }, t6_pciids[] = { 933 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 934 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 935 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 936 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 937 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 938 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 939 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 940 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 941 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 942 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 943 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 944 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 945 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 946 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 947 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 948 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 949 950 /* Custom */ 951 {0x6480, "Custom T6225-CR"}, 952 {0x6481, "Custom T62100-CR"}, 953 {0x6482, "Custom T6225-CR"}, 954 {0x6483, "Custom T62100-CR"}, 955 {0x6484, "Custom T64100-CR"}, 956 {0x6485, "Custom T6240-SO"}, 957 {0x6486, "Custom T6225-SO-CR"}, 958 {0x6487, "Custom T6225-CR"}, 959 }; 960 961 #ifdef TCP_OFFLOAD 962 /* 963 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 964 * be exactly the same for both rxq and ofld_rxq. 965 */ 966 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 967 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 968 #endif 969 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 970 971 static int 972 t4_probe(device_t dev) 973 { 974 int i; 975 uint16_t v = pci_get_vendor(dev); 976 uint16_t d = pci_get_device(dev); 977 uint8_t f = pci_get_function(dev); 978 979 if (v != PCI_VENDOR_ID_CHELSIO) 980 return (ENXIO); 981 982 /* Attach only to PF0 of the FPGA */ 983 if (d == 0xa000 && f != 0) 984 return (ENXIO); 985 986 for (i = 0; i < nitems(t4_pciids); i++) { 987 if (d == t4_pciids[i].device) { 988 device_set_desc(dev, t4_pciids[i].desc); 989 return (BUS_PROBE_DEFAULT); 990 } 991 } 992 993 return (ENXIO); 994 } 995 996 static int 997 t5_probe(device_t dev) 998 { 999 int i; 1000 uint16_t v = pci_get_vendor(dev); 1001 uint16_t d = pci_get_device(dev); 1002 uint8_t f = pci_get_function(dev); 1003 1004 if (v != PCI_VENDOR_ID_CHELSIO) 1005 return (ENXIO); 1006 1007 /* Attach only to PF0 of the FPGA */ 1008 if (d == 0xb000 && f != 0) 1009 return (ENXIO); 1010 1011 for (i = 0; i < nitems(t5_pciids); i++) { 1012 if (d == t5_pciids[i].device) { 1013 device_set_desc(dev, t5_pciids[i].desc); 1014 return (BUS_PROBE_DEFAULT); 1015 } 1016 } 1017 1018 return (ENXIO); 1019 } 1020 1021 static int 1022 t6_probe(device_t dev) 1023 { 1024 int i; 1025 uint16_t v = pci_get_vendor(dev); 1026 uint16_t d = pci_get_device(dev); 1027 1028 if (v != PCI_VENDOR_ID_CHELSIO) 1029 return (ENXIO); 1030 1031 for (i = 0; i < nitems(t6_pciids); i++) { 1032 if (d == t6_pciids[i].device) { 1033 device_set_desc(dev, t6_pciids[i].desc); 1034 return (BUS_PROBE_DEFAULT); 1035 } 1036 } 1037 1038 return (ENXIO); 1039 } 1040 1041 static void 1042 t5_attribute_workaround(device_t dev) 1043 { 1044 device_t root_port; 1045 uint32_t v; 1046 1047 /* 1048 * The T5 chips do not properly echo the No Snoop and Relaxed 1049 * Ordering attributes when replying to a TLP from a Root 1050 * Port. As a workaround, find the parent Root Port and 1051 * disable No Snoop and Relaxed Ordering. Note that this 1052 * affects all devices under this root port. 1053 */ 1054 root_port = pci_find_pcie_root_port(dev); 1055 if (root_port == NULL) { 1056 device_printf(dev, "Unable to find parent root port\n"); 1057 return; 1058 } 1059 1060 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 1061 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 1062 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 1063 0) 1064 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 1065 device_get_nameunit(root_port)); 1066 } 1067 1068 static const struct devnames devnames[] = { 1069 { 1070 .nexus_name = "t4nex", 1071 .ifnet_name = "cxgbe", 1072 .vi_ifnet_name = "vcxgbe", 1073 .pf03_drv_name = "t4iov", 1074 .vf_nexus_name = "t4vf", 1075 .vf_ifnet_name = "cxgbev" 1076 }, { 1077 .nexus_name = "t5nex", 1078 .ifnet_name = "cxl", 1079 .vi_ifnet_name = "vcxl", 1080 .pf03_drv_name = "t5iov", 1081 .vf_nexus_name = "t5vf", 1082 .vf_ifnet_name = "cxlv" 1083 }, { 1084 .nexus_name = "t6nex", 1085 .ifnet_name = "cc", 1086 .vi_ifnet_name = "vcc", 1087 .pf03_drv_name = "t6iov", 1088 .vf_nexus_name = "t6vf", 1089 .vf_ifnet_name = "ccv" 1090 } 1091 }; 1092 1093 void 1094 t4_init_devnames(struct adapter *sc) 1095 { 1096 int id; 1097 1098 id = chip_id(sc); 1099 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 1100 sc->names = &devnames[id - CHELSIO_T4]; 1101 else { 1102 device_printf(sc->dev, "chip id %d is not supported.\n", id); 1103 sc->names = NULL; 1104 } 1105 } 1106 1107 static int 1108 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 1109 { 1110 const char *parent, *name; 1111 long value; 1112 int line, unit; 1113 1114 line = 0; 1115 parent = device_get_nameunit(sc->dev); 1116 name = sc->names->ifnet_name; 1117 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 1118 if (resource_long_value(name, unit, "port", &value) == 0 && 1119 value == pi->port_id) 1120 return (unit); 1121 } 1122 return (-1); 1123 } 1124 1125 static void 1126 t4_calibration(void *arg) 1127 { 1128 struct adapter *sc; 1129 struct clock_sync *cur, *nex; 1130 uint64_t hw; 1131 sbintime_t sbt; 1132 int next_up; 1133 1134 sc = (struct adapter *)arg; 1135 1136 KASSERT((hw_off_limits(sc) == 0), ("hw_off_limits at t4_calibration")); 1137 hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO); 1138 sbt = sbinuptime(); 1139 1140 cur = &sc->cal_info[sc->cal_current]; 1141 next_up = (sc->cal_current + 1) % CNT_CAL_INFO; 1142 nex = &sc->cal_info[next_up]; 1143 if (__predict_false(sc->cal_count == 0)) { 1144 /* First time in, just get the values in */ 1145 cur->hw_cur = hw; 1146 cur->sbt_cur = sbt; 1147 sc->cal_count++; 1148 goto done; 1149 } 1150 1151 if (cur->hw_cur == hw) { 1152 /* The clock is not advancing? */ 1153 sc->cal_count = 0; 1154 atomic_store_rel_int(&cur->gen, 0); 1155 goto done; 1156 } 1157 1158 seqc_write_begin(&nex->gen); 1159 nex->hw_prev = cur->hw_cur; 1160 nex->sbt_prev = cur->sbt_cur; 1161 nex->hw_cur = hw; 1162 nex->sbt_cur = sbt; 1163 seqc_write_end(&nex->gen); 1164 sc->cal_current = next_up; 1165 done: 1166 callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration, 1167 sc, C_DIRECT_EXEC); 1168 } 1169 1170 static void 1171 t4_calibration_start(struct adapter *sc) 1172 { 1173 /* 1174 * Here if we have not done a calibration 1175 * then do so otherwise start the appropriate 1176 * timer. 1177 */ 1178 int i; 1179 1180 for (i = 0; i < CNT_CAL_INFO; i++) { 1181 sc->cal_info[i].gen = 0; 1182 } 1183 sc->cal_current = 0; 1184 sc->cal_count = 0; 1185 sc->cal_gen = 0; 1186 t4_calibration(sc); 1187 } 1188 1189 static int 1190 t4_attach(device_t dev) 1191 { 1192 struct adapter *sc; 1193 int rc = 0, i, j, rqidx, tqidx, nports; 1194 struct make_dev_args mda; 1195 struct intrs_and_queues iaq; 1196 struct sge *s; 1197 uint32_t *buf; 1198 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1199 int ofld_tqidx; 1200 #endif 1201 #ifdef TCP_OFFLOAD 1202 int ofld_rqidx; 1203 #endif 1204 #ifdef DEV_NETMAP 1205 int nm_rqidx, nm_tqidx; 1206 #endif 1207 int num_vis; 1208 1209 sc = device_get_softc(dev); 1210 sc->dev = dev; 1211 sysctl_ctx_init(&sc->ctx); 1212 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 1213 1214 if ((pci_get_device(dev) & 0xff00) == 0x5400) 1215 t5_attribute_workaround(dev); 1216 pci_enable_busmaster(dev); 1217 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 1218 uint32_t v; 1219 1220 pci_set_max_read_req(dev, 4096); 1221 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 1222 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 1223 if (pcie_relaxed_ordering == 0 && 1224 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 1225 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 1226 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1227 } else if (pcie_relaxed_ordering == 1 && 1228 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 1229 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 1230 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1231 } 1232 } 1233 1234 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 1235 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 1236 sc->traceq = -1; 1237 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 1238 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 1239 device_get_nameunit(dev)); 1240 1241 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 1242 device_get_nameunit(dev)); 1243 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 1244 t4_add_adapter(sc); 1245 1246 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 1247 TAILQ_INIT(&sc->sfl); 1248 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 1249 1250 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 1251 1252 sc->policy = NULL; 1253 rw_init(&sc->policy_lock, "connection offload policy"); 1254 1255 callout_init(&sc->ktls_tick, 1); 1256 1257 callout_init(&sc->cal_callout, 1); 1258 1259 refcount_init(&sc->vxlan_refcount, 0); 1260 1261 TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc); 1262 TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc); 1263 1264 sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1265 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq", 1266 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 1267 sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1268 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq", 1269 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 1270 1271 rc = t4_map_bars_0_and_4(sc); 1272 if (rc != 0) 1273 goto done; /* error message displayed already */ 1274 1275 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1276 1277 /* Prepare the adapter for operation. */ 1278 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1279 rc = -t4_prep_adapter(sc, buf); 1280 free(buf, M_CXGBE); 1281 if (rc != 0) { 1282 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1283 goto done; 1284 } 1285 1286 /* 1287 * This is the real PF# to which we're attaching. Works from within PCI 1288 * passthrough environments too, where pci_get_function() could return a 1289 * different PF# depending on the passthrough configuration. We need to 1290 * use the real PF# in all our communication with the firmware. 1291 */ 1292 j = t4_read_reg(sc, A_PL_WHOAMI); 1293 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1294 sc->mbox = sc->pf; 1295 1296 t4_init_devnames(sc); 1297 if (sc->names == NULL) { 1298 rc = ENOTSUP; 1299 goto done; /* error message displayed already */ 1300 } 1301 1302 /* 1303 * Do this really early, with the memory windows set up even before the 1304 * character device. The userland tool's register i/o and mem read 1305 * will work even in "recovery mode". 1306 */ 1307 setup_memwin(sc); 1308 if (t4_init_devlog_params(sc, 0) == 0) 1309 fixup_devlog_params(sc); 1310 make_dev_args_init(&mda); 1311 mda.mda_devsw = &t4_cdevsw; 1312 mda.mda_uid = UID_ROOT; 1313 mda.mda_gid = GID_WHEEL; 1314 mda.mda_mode = 0600; 1315 mda.mda_si_drv1 = sc; 1316 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1317 if (rc != 0) 1318 device_printf(dev, "failed to create nexus char device: %d.\n", 1319 rc); 1320 1321 /* Go no further if recovery mode has been requested. */ 1322 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1323 device_printf(dev, "recovery mode.\n"); 1324 goto done; 1325 } 1326 1327 #if defined(__i386__) 1328 if ((cpu_feature & CPUID_CX8) == 0) { 1329 device_printf(dev, "64 bit atomics not available.\n"); 1330 rc = ENOTSUP; 1331 goto done; 1332 } 1333 #endif 1334 1335 /* Contact the firmware and try to become the master driver. */ 1336 rc = contact_firmware(sc); 1337 if (rc != 0) 1338 goto done; /* error message displayed already */ 1339 MPASS(sc->flags & FW_OK); 1340 1341 rc = get_params__pre_init(sc); 1342 if (rc != 0) 1343 goto done; /* error message displayed already */ 1344 1345 if (sc->flags & MASTER_PF) { 1346 rc = partition_resources(sc); 1347 if (rc != 0) 1348 goto done; /* error message displayed already */ 1349 } 1350 1351 rc = get_params__post_init(sc); 1352 if (rc != 0) 1353 goto done; /* error message displayed already */ 1354 1355 rc = set_params__post_init(sc); 1356 if (rc != 0) 1357 goto done; /* error message displayed already */ 1358 1359 rc = t4_map_bar_2(sc); 1360 if (rc != 0) 1361 goto done; /* error message displayed already */ 1362 1363 rc = t4_adj_doorbells(sc); 1364 if (rc != 0) 1365 goto done; /* error message displayed already */ 1366 1367 rc = t4_create_dma_tag(sc); 1368 if (rc != 0) 1369 goto done; /* error message displayed already */ 1370 1371 /* 1372 * First pass over all the ports - allocate VIs and initialize some 1373 * basic parameters like mac address, port type, etc. 1374 */ 1375 for_each_port(sc, i) { 1376 struct port_info *pi; 1377 1378 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1379 sc->port[i] = pi; 1380 1381 /* These must be set before t4_port_init */ 1382 pi->adapter = sc; 1383 pi->port_id = i; 1384 /* 1385 * XXX: vi[0] is special so we can't delay this allocation until 1386 * pi->nvi's final value is known. 1387 */ 1388 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1389 M_ZERO | M_WAITOK); 1390 1391 /* 1392 * Allocate the "main" VI and initialize parameters 1393 * like mac addr. 1394 */ 1395 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1396 if (rc != 0) { 1397 device_printf(dev, "unable to initialize port %d: %d\n", 1398 i, rc); 1399 free(pi->vi, M_CXGBE); 1400 free(pi, M_CXGBE); 1401 sc->port[i] = NULL; 1402 goto done; 1403 } 1404 1405 if (is_bt(pi->port_type)) 1406 setbit(&sc->bt_map, pi->tx_chan); 1407 else 1408 MPASS(!isset(&sc->bt_map, pi->tx_chan)); 1409 1410 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1411 device_get_nameunit(dev), i); 1412 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1413 sc->chan_map[pi->tx_chan] = i; 1414 1415 /* 1416 * The MPS counter for FCS errors doesn't work correctly on the 1417 * T6 so we use the MAC counter here. Which MAC is in use 1418 * depends on the link settings which will be known when the 1419 * link comes up. 1420 */ 1421 if (is_t6(sc)) 1422 pi->fcs_reg = -1; 1423 else { 1424 pi->fcs_reg = t4_port_reg(sc, pi->tx_chan, 1425 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1426 } 1427 pi->fcs_base = 0; 1428 1429 /* All VIs on this port share this media. */ 1430 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1431 cxgbe_media_status); 1432 1433 PORT_LOCK(pi); 1434 init_link_config(pi); 1435 fixup_link_config(pi); 1436 build_medialist(pi); 1437 if (fixed_ifmedia(pi)) 1438 pi->flags |= FIXED_IFMEDIA; 1439 PORT_UNLOCK(pi); 1440 1441 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1442 t4_ifnet_unit(sc, pi)); 1443 if (pi->dev == NULL) { 1444 device_printf(dev, 1445 "failed to add device for port %d.\n", i); 1446 rc = ENXIO; 1447 goto done; 1448 } 1449 pi->vi[0].dev = pi->dev; 1450 device_set_softc(pi->dev, pi); 1451 } 1452 1453 /* 1454 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1455 */ 1456 nports = sc->params.nports; 1457 rc = cfg_itype_and_nqueues(sc, &iaq); 1458 if (rc != 0) 1459 goto done; /* error message displayed already */ 1460 1461 num_vis = iaq.num_vis; 1462 sc->intr_type = iaq.intr_type; 1463 sc->intr_count = iaq.nirq; 1464 1465 s = &sc->sge; 1466 s->nrxq = nports * iaq.nrxq; 1467 s->ntxq = nports * iaq.ntxq; 1468 if (num_vis > 1) { 1469 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1470 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1471 } 1472 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1473 s->neq += nports; /* ctrl queues: 1 per port */ 1474 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1475 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1476 if (is_offload(sc) || is_ethoffload(sc)) { 1477 s->nofldtxq = nports * iaq.nofldtxq; 1478 if (num_vis > 1) 1479 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1480 s->neq += s->nofldtxq; 1481 1482 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq), 1483 M_CXGBE, M_ZERO | M_WAITOK); 1484 } 1485 #endif 1486 #ifdef TCP_OFFLOAD 1487 if (is_offload(sc)) { 1488 s->nofldrxq = nports * iaq.nofldrxq; 1489 if (num_vis > 1) 1490 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1491 s->neq += s->nofldrxq; /* free list */ 1492 s->niq += s->nofldrxq; 1493 1494 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1495 M_CXGBE, M_ZERO | M_WAITOK); 1496 } 1497 #endif 1498 #ifdef DEV_NETMAP 1499 s->nnmrxq = 0; 1500 s->nnmtxq = 0; 1501 if (t4_native_netmap & NN_MAIN_VI) { 1502 s->nnmrxq += nports * iaq.nnmrxq; 1503 s->nnmtxq += nports * iaq.nnmtxq; 1504 } 1505 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) { 1506 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi; 1507 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi; 1508 } 1509 s->neq += s->nnmtxq + s->nnmrxq; 1510 s->niq += s->nnmrxq; 1511 1512 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1513 M_CXGBE, M_ZERO | M_WAITOK); 1514 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1515 M_CXGBE, M_ZERO | M_WAITOK); 1516 #endif 1517 MPASS(s->niq <= s->iqmap_sz); 1518 MPASS(s->neq <= s->eqmap_sz); 1519 1520 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1521 M_ZERO | M_WAITOK); 1522 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1523 M_ZERO | M_WAITOK); 1524 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1525 M_ZERO | M_WAITOK); 1526 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE, 1527 M_ZERO | M_WAITOK); 1528 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE, 1529 M_ZERO | M_WAITOK); 1530 1531 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1532 M_ZERO | M_WAITOK); 1533 1534 t4_init_l2t(sc, M_WAITOK); 1535 t4_init_smt(sc, M_WAITOK); 1536 t4_init_tx_sched(sc); 1537 t4_init_atid_table(sc); 1538 #ifdef RATELIMIT 1539 t4_init_etid_table(sc); 1540 #endif 1541 #ifdef INET6 1542 t4_init_clip_table(sc); 1543 #endif 1544 if (sc->vres.key.size != 0) 1545 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1546 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1547 1548 /* 1549 * Second pass over the ports. This time we know the number of rx and 1550 * tx queues that each port should get. 1551 */ 1552 rqidx = tqidx = 0; 1553 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1554 ofld_tqidx = 0; 1555 #endif 1556 #ifdef TCP_OFFLOAD 1557 ofld_rqidx = 0; 1558 #endif 1559 #ifdef DEV_NETMAP 1560 nm_rqidx = nm_tqidx = 0; 1561 #endif 1562 for_each_port(sc, i) { 1563 struct port_info *pi = sc->port[i]; 1564 struct vi_info *vi; 1565 1566 if (pi == NULL) 1567 continue; 1568 1569 pi->nvi = num_vis; 1570 for_each_vi(pi, j, vi) { 1571 vi->pi = pi; 1572 vi->adapter = sc; 1573 vi->first_intr = -1; 1574 vi->qsize_rxq = t4_qsize_rxq; 1575 vi->qsize_txq = t4_qsize_txq; 1576 1577 vi->first_rxq = rqidx; 1578 vi->first_txq = tqidx; 1579 vi->tmr_idx = t4_tmr_idx; 1580 vi->pktc_idx = t4_pktc_idx; 1581 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1582 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1583 1584 rqidx += vi->nrxq; 1585 tqidx += vi->ntxq; 1586 1587 if (j == 0 && vi->ntxq > 1) 1588 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1589 else 1590 vi->rsrv_noflowq = 0; 1591 1592 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1593 vi->first_ofld_txq = ofld_tqidx; 1594 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1595 ofld_tqidx += vi->nofldtxq; 1596 #endif 1597 #ifdef TCP_OFFLOAD 1598 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1599 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1600 vi->first_ofld_rxq = ofld_rqidx; 1601 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1602 1603 ofld_rqidx += vi->nofldrxq; 1604 #endif 1605 #ifdef DEV_NETMAP 1606 vi->first_nm_rxq = nm_rqidx; 1607 vi->first_nm_txq = nm_tqidx; 1608 if (j == 0) { 1609 vi->nnmrxq = iaq.nnmrxq; 1610 vi->nnmtxq = iaq.nnmtxq; 1611 } else { 1612 vi->nnmrxq = iaq.nnmrxq_vi; 1613 vi->nnmtxq = iaq.nnmtxq_vi; 1614 } 1615 nm_rqidx += vi->nnmrxq; 1616 nm_tqidx += vi->nnmtxq; 1617 #endif 1618 } 1619 } 1620 1621 rc = t4_setup_intr_handlers(sc); 1622 if (rc != 0) { 1623 device_printf(dev, 1624 "failed to setup interrupt handlers: %d\n", rc); 1625 goto done; 1626 } 1627 1628 rc = bus_generic_probe(dev); 1629 if (rc != 0) { 1630 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1631 goto done; 1632 } 1633 1634 /* 1635 * Ensure thread-safe mailbox access (in debug builds). 1636 * 1637 * So far this was the only thread accessing the mailbox but various 1638 * ifnets and sysctls are about to be created and their handlers/ioctls 1639 * will access the mailbox from different threads. 1640 */ 1641 sc->flags |= CHK_MBOX_ACCESS; 1642 1643 rc = bus_generic_attach(dev); 1644 if (rc != 0) { 1645 device_printf(dev, 1646 "failed to attach all child ports: %d\n", rc); 1647 goto done; 1648 } 1649 t4_calibration_start(sc); 1650 1651 device_printf(dev, 1652 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1653 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1654 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1655 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1656 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1657 1658 t4_set_desc(sc); 1659 1660 notify_siblings(dev, 0); 1661 1662 done: 1663 if (rc != 0 && sc->cdev) { 1664 /* cdev was created and so cxgbetool works; recover that way. */ 1665 device_printf(dev, 1666 "error during attach, adapter is now in recovery mode.\n"); 1667 rc = 0; 1668 } 1669 1670 if (rc != 0) 1671 t4_detach_common(dev); 1672 else 1673 t4_sysctls(sc); 1674 1675 return (rc); 1676 } 1677 1678 static int 1679 t4_child_location(device_t bus, device_t dev, struct sbuf *sb) 1680 { 1681 struct adapter *sc; 1682 struct port_info *pi; 1683 int i; 1684 1685 sc = device_get_softc(bus); 1686 for_each_port(sc, i) { 1687 pi = sc->port[i]; 1688 if (pi != NULL && pi->dev == dev) { 1689 sbuf_printf(sb, "port=%d", pi->port_id); 1690 break; 1691 } 1692 } 1693 return (0); 1694 } 1695 1696 static int 1697 t4_ready(device_t dev) 1698 { 1699 struct adapter *sc; 1700 1701 sc = device_get_softc(dev); 1702 if (sc->flags & FW_OK) 1703 return (0); 1704 return (ENXIO); 1705 } 1706 1707 static int 1708 t4_read_port_device(device_t dev, int port, device_t *child) 1709 { 1710 struct adapter *sc; 1711 struct port_info *pi; 1712 1713 sc = device_get_softc(dev); 1714 if (port < 0 || port >= MAX_NPORTS) 1715 return (EINVAL); 1716 pi = sc->port[port]; 1717 if (pi == NULL || pi->dev == NULL) 1718 return (ENXIO); 1719 *child = pi->dev; 1720 return (0); 1721 } 1722 1723 static int 1724 notify_siblings(device_t dev, int detaching) 1725 { 1726 device_t sibling; 1727 int error, i; 1728 1729 error = 0; 1730 for (i = 0; i < PCI_FUNCMAX; i++) { 1731 if (i == pci_get_function(dev)) 1732 continue; 1733 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1734 pci_get_slot(dev), i); 1735 if (sibling == NULL || !device_is_attached(sibling)) 1736 continue; 1737 if (detaching) 1738 error = T4_DETACH_CHILD(sibling); 1739 else 1740 (void)T4_ATTACH_CHILD(sibling); 1741 if (error) 1742 break; 1743 } 1744 return (error); 1745 } 1746 1747 /* 1748 * Idempotent 1749 */ 1750 static int 1751 t4_detach(device_t dev) 1752 { 1753 int rc; 1754 1755 rc = notify_siblings(dev, 1); 1756 if (rc) { 1757 device_printf(dev, 1758 "failed to detach sibling devices: %d\n", rc); 1759 return (rc); 1760 } 1761 1762 return (t4_detach_common(dev)); 1763 } 1764 1765 int 1766 t4_detach_common(device_t dev) 1767 { 1768 struct adapter *sc; 1769 struct port_info *pi; 1770 int i, rc; 1771 1772 sc = device_get_softc(dev); 1773 1774 #ifdef TCP_OFFLOAD 1775 rc = deactivate_all_uld(sc); 1776 if (rc) { 1777 device_printf(dev, 1778 "failed to detach upper layer drivers: %d\n", rc); 1779 return (rc); 1780 } 1781 #endif 1782 1783 if (sc->cdev) { 1784 destroy_dev(sc->cdev); 1785 sc->cdev = NULL; 1786 } 1787 1788 sx_xlock(&t4_list_lock); 1789 SLIST_REMOVE(&t4_list, sc, adapter, link); 1790 sx_xunlock(&t4_list_lock); 1791 1792 sc->flags &= ~CHK_MBOX_ACCESS; 1793 if (sc->flags & FULL_INIT_DONE) { 1794 if (!(sc->flags & IS_VF)) 1795 t4_intr_disable(sc); 1796 } 1797 1798 if (device_is_attached(dev)) { 1799 rc = bus_generic_detach(dev); 1800 if (rc) { 1801 device_printf(dev, 1802 "failed to detach child devices: %d\n", rc); 1803 return (rc); 1804 } 1805 } 1806 1807 for (i = 0; i < sc->intr_count; i++) 1808 t4_free_irq(sc, &sc->irq[i]); 1809 1810 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1811 t4_free_tx_sched(sc); 1812 1813 for (i = 0; i < MAX_NPORTS; i++) { 1814 pi = sc->port[i]; 1815 if (pi) { 1816 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1817 if (pi->dev) 1818 device_delete_child(dev, pi->dev); 1819 1820 mtx_destroy(&pi->pi_lock); 1821 free(pi->vi, M_CXGBE); 1822 free(pi, M_CXGBE); 1823 } 1824 } 1825 callout_stop(&sc->cal_callout); 1826 callout_drain(&sc->cal_callout); 1827 device_delete_children(dev); 1828 sysctl_ctx_free(&sc->ctx); 1829 adapter_full_uninit(sc); 1830 1831 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1832 t4_fw_bye(sc, sc->mbox); 1833 1834 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1835 pci_release_msi(dev); 1836 1837 if (sc->regs_res) 1838 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1839 sc->regs_res); 1840 1841 if (sc->udbs_res) 1842 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1843 sc->udbs_res); 1844 1845 if (sc->msix_res) 1846 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1847 sc->msix_res); 1848 1849 if (sc->l2t) 1850 t4_free_l2t(sc); 1851 if (sc->smt) 1852 t4_free_smt(sc->smt); 1853 t4_free_atid_table(sc); 1854 #ifdef RATELIMIT 1855 t4_free_etid_table(sc); 1856 #endif 1857 if (sc->key_map) 1858 vmem_destroy(sc->key_map); 1859 #ifdef INET6 1860 t4_destroy_clip_table(sc); 1861 #endif 1862 1863 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1864 free(sc->sge.ofld_txq, M_CXGBE); 1865 #endif 1866 #ifdef TCP_OFFLOAD 1867 free(sc->sge.ofld_rxq, M_CXGBE); 1868 #endif 1869 #ifdef DEV_NETMAP 1870 free(sc->sge.nm_rxq, M_CXGBE); 1871 free(sc->sge.nm_txq, M_CXGBE); 1872 #endif 1873 free(sc->irq, M_CXGBE); 1874 free(sc->sge.rxq, M_CXGBE); 1875 free(sc->sge.txq, M_CXGBE); 1876 free(sc->sge.ctrlq, M_CXGBE); 1877 free(sc->sge.iqmap, M_CXGBE); 1878 free(sc->sge.eqmap, M_CXGBE); 1879 free(sc->tids.ftid_tab, M_CXGBE); 1880 free(sc->tids.hpftid_tab, M_CXGBE); 1881 free_hftid_hash(&sc->tids); 1882 free(sc->tids.tid_tab, M_CXGBE); 1883 t4_destroy_dma_tag(sc); 1884 1885 callout_drain(&sc->ktls_tick); 1886 callout_drain(&sc->sfl_callout); 1887 if (mtx_initialized(&sc->tids.ftid_lock)) { 1888 mtx_destroy(&sc->tids.ftid_lock); 1889 cv_destroy(&sc->tids.ftid_cv); 1890 } 1891 if (mtx_initialized(&sc->tids.atid_lock)) 1892 mtx_destroy(&sc->tids.atid_lock); 1893 if (mtx_initialized(&sc->ifp_lock)) 1894 mtx_destroy(&sc->ifp_lock); 1895 1896 if (rw_initialized(&sc->policy_lock)) { 1897 rw_destroy(&sc->policy_lock); 1898 #ifdef TCP_OFFLOAD 1899 if (sc->policy != NULL) 1900 free_offload_policy(sc->policy); 1901 #endif 1902 } 1903 1904 for (i = 0; i < NUM_MEMWIN; i++) { 1905 struct memwin *mw = &sc->memwin[i]; 1906 1907 if (rw_initialized(&mw->mw_lock)) 1908 rw_destroy(&mw->mw_lock); 1909 } 1910 1911 mtx_destroy(&sc->sfl_lock); 1912 mtx_destroy(&sc->reg_lock); 1913 mtx_destroy(&sc->sc_lock); 1914 1915 bzero(sc, sizeof(*sc)); 1916 1917 return (0); 1918 } 1919 1920 static inline int 1921 stop_adapter(struct adapter *sc) 1922 { 1923 struct port_info *pi; 1924 int i; 1925 1926 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) { 1927 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n", 1928 __func__, curthread, sc->flags, sc->error_flags); 1929 return (EALREADY); 1930 } 1931 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread, 1932 sc->flags, sc->error_flags); 1933 t4_shutdown_adapter(sc); 1934 for_each_port(sc, i) { 1935 pi = sc->port[i]; 1936 PORT_LOCK(pi); 1937 if (pi->up_vis > 0 && pi->link_cfg.link_ok) { 1938 /* 1939 * t4_shutdown_adapter has already shut down all the 1940 * PHYs but it also disables interrupts and DMA so there 1941 * won't be a link interrupt. Update the state manually 1942 * if the link was up previously and inform the kernel. 1943 */ 1944 pi->link_cfg.link_ok = false; 1945 t4_os_link_changed(pi); 1946 } 1947 PORT_UNLOCK(pi); 1948 } 1949 1950 return (0); 1951 } 1952 1953 static inline int 1954 restart_adapter(struct adapter *sc) 1955 { 1956 uint32_t val; 1957 1958 if (!atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_STOPPED))) { 1959 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n", 1960 __func__, curthread, sc->flags, sc->error_flags); 1961 return (EALREADY); 1962 } 1963 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread, 1964 sc->flags, sc->error_flags); 1965 1966 MPASS(hw_off_limits(sc)); 1967 MPASS((sc->flags & FW_OK) == 0); 1968 MPASS((sc->flags & MASTER_PF) == 0); 1969 MPASS(sc->reset_thread == NULL); 1970 1971 /* 1972 * The adapter is supposed to be back on PCIE with its config space and 1973 * BARs restored to their state before reset. Register access via 1974 * t4_read_reg BAR0 should just work. 1975 */ 1976 sc->reset_thread = curthread; 1977 val = t4_read_reg(sc, A_PL_WHOAMI); 1978 if (val == 0xffffffff || val == 0xeeeeeeee) { 1979 CH_ERR(sc, "%s: device registers not readable.\n", __func__); 1980 sc->reset_thread = NULL; 1981 atomic_set_int(&sc->error_flags, ADAP_STOPPED); 1982 return (ENXIO); 1983 } 1984 atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR); 1985 atomic_add_int(&sc->incarnation, 1); 1986 atomic_add_int(&sc->num_resets, 1); 1987 1988 return (0); 1989 } 1990 1991 static inline void 1992 set_adapter_hwstatus(struct adapter *sc, const bool usable) 1993 { 1994 mtx_lock(&sc->reg_lock); 1995 if (usable) { 1996 /* Must be marked reusable by the designated thread. */ 1997 MPASS(sc->reset_thread == curthread); 1998 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 1999 } else { 2000 /* Mark the adapter totally off limits. */ 2001 atomic_set_int(&sc->error_flags, HW_OFF_LIMITS); 2002 sc->flags &= ~(FW_OK | MASTER_PF); 2003 sc->reset_thread = NULL; 2004 } 2005 mtx_unlock(&sc->reg_lock); 2006 } 2007 2008 static int 2009 stop_lld(struct adapter *sc) 2010 { 2011 struct port_info *pi; 2012 struct vi_info *vi; 2013 if_t ifp; 2014 struct sge_rxq *rxq; 2015 struct sge_txq *txq; 2016 struct sge_wrq *wrq; 2017 #ifdef TCP_OFFLOAD 2018 struct sge_ofld_rxq *ofld_rxq; 2019 #endif 2020 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2021 struct sge_ofld_txq *ofld_txq; 2022 #endif 2023 int rc, i, j, k; 2024 2025 /* 2026 * XXX: Can there be a synch_op in progress that will hang because 2027 * hardware has been stopped? We'll hang too and the solution will be 2028 * to use a version of begin_synch_op that wakes up existing synch_op 2029 * with errors. Maybe stop_adapter should do this wakeup? 2030 * 2031 * I don't think any synch_op could get stranded waiting for DMA or 2032 * interrupt so I think we're okay here. Remove this comment block 2033 * after testing. 2034 */ 2035 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4slld"); 2036 if (rc != 0) 2037 return (ENXIO); 2038 2039 /* Quiesce all activity. */ 2040 for_each_port(sc, i) { 2041 pi = sc->port[i]; 2042 pi->vxlan_tcam_entry = false; 2043 for_each_vi(pi, j, vi) { 2044 vi->xact_addr_filt = -1; 2045 mtx_lock(&vi->tick_mtx); 2046 vi->flags |= VI_SKIP_STATS; 2047 mtx_unlock(&vi->tick_mtx); 2048 if (!(vi->flags & VI_INIT_DONE)) 2049 continue; 2050 2051 ifp = vi->ifp; 2052 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2053 mtx_lock(&vi->tick_mtx); 2054 callout_stop(&vi->tick); 2055 mtx_unlock(&vi->tick_mtx); 2056 callout_drain(&vi->tick); 2057 } 2058 2059 /* 2060 * Note that the HW is not available. 2061 */ 2062 for_each_txq(vi, k, txq) { 2063 TXQ_LOCK(txq); 2064 txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED); 2065 TXQ_UNLOCK(txq); 2066 } 2067 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2068 for_each_ofld_txq(vi, k, ofld_txq) { 2069 TXQ_LOCK(&ofld_txq->wrq); 2070 ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED; 2071 TXQ_UNLOCK(&ofld_txq->wrq); 2072 } 2073 #endif 2074 for_each_rxq(vi, k, rxq) { 2075 rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2076 } 2077 #if defined(TCP_OFFLOAD) 2078 for_each_ofld_rxq(vi, k, ofld_rxq) { 2079 ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2080 } 2081 #endif 2082 2083 quiesce_vi(vi); 2084 } 2085 2086 if (sc->flags & FULL_INIT_DONE) { 2087 /* Control queue */ 2088 wrq = &sc->sge.ctrlq[i]; 2089 TXQ_LOCK(wrq); 2090 wrq->eq.flags &= ~EQ_HW_ALLOCATED; 2091 TXQ_UNLOCK(wrq); 2092 quiesce_wrq(wrq); 2093 } 2094 2095 if (pi->flags & HAS_TRACEQ) { 2096 pi->flags &= ~HAS_TRACEQ; 2097 sc->traceq = -1; 2098 sc->tracer_valid = 0; 2099 sc->tracer_enabled = 0; 2100 } 2101 } 2102 if (sc->flags & FULL_INIT_DONE) { 2103 /* Firmware event queue */ 2104 sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED; 2105 quiesce_iq_fl(sc, &sc->sge.fwq, NULL); 2106 } 2107 2108 /* Stop calibration */ 2109 callout_stop(&sc->cal_callout); 2110 callout_drain(&sc->cal_callout); 2111 2112 if (t4_clock_gate_on_suspend) { 2113 t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN | 2114 F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN | 2115 F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0); 2116 } 2117 2118 end_synchronized_op(sc, 0); 2119 2120 stop_atid_allocator(sc); 2121 t4_stop_l2t(sc); 2122 2123 return (rc); 2124 } 2125 2126 int 2127 suspend_adapter(struct adapter *sc) 2128 { 2129 stop_adapter(sc); 2130 stop_lld(sc); 2131 #ifdef TCP_OFFLOAD 2132 stop_all_uld(sc); 2133 #endif 2134 set_adapter_hwstatus(sc, false); 2135 2136 return (0); 2137 } 2138 2139 static int 2140 t4_suspend(device_t dev) 2141 { 2142 struct adapter *sc = device_get_softc(dev); 2143 int rc; 2144 2145 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2146 rc = suspend_adapter(sc); 2147 CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread); 2148 2149 return (rc); 2150 } 2151 2152 struct adapter_pre_reset_state { 2153 u_int flags; 2154 uint16_t nbmcaps; 2155 uint16_t linkcaps; 2156 uint16_t switchcaps; 2157 uint16_t niccaps; 2158 uint16_t toecaps; 2159 uint16_t rdmacaps; 2160 uint16_t cryptocaps; 2161 uint16_t iscsicaps; 2162 uint16_t fcoecaps; 2163 2164 u_int cfcsum; 2165 char cfg_file[32]; 2166 2167 struct adapter_params params; 2168 struct t4_virt_res vres; 2169 struct tid_info tids; 2170 struct sge sge; 2171 2172 int rawf_base; 2173 int nrawf; 2174 2175 }; 2176 2177 static void 2178 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2179 { 2180 2181 ASSERT_SYNCHRONIZED_OP(sc); 2182 2183 o->flags = sc->flags; 2184 2185 o->nbmcaps = sc->nbmcaps; 2186 o->linkcaps = sc->linkcaps; 2187 o->switchcaps = sc->switchcaps; 2188 o->niccaps = sc->niccaps; 2189 o->toecaps = sc->toecaps; 2190 o->rdmacaps = sc->rdmacaps; 2191 o->cryptocaps = sc->cryptocaps; 2192 o->iscsicaps = sc->iscsicaps; 2193 o->fcoecaps = sc->fcoecaps; 2194 2195 o->cfcsum = sc->cfcsum; 2196 MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file)); 2197 memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file)); 2198 2199 o->params = sc->params; 2200 o->vres = sc->vres; 2201 o->tids = sc->tids; 2202 o->sge = sc->sge; 2203 2204 o->rawf_base = sc->rawf_base; 2205 o->nrawf = sc->nrawf; 2206 } 2207 2208 static int 2209 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2210 { 2211 int rc = 0; 2212 2213 ASSERT_SYNCHRONIZED_OP(sc); 2214 2215 /* Capabilities */ 2216 #define COMPARE_CAPS(c) do { \ 2217 if (o->c##caps != sc->c##caps) { \ 2218 CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \ 2219 sc->c##caps); \ 2220 rc = EINVAL; \ 2221 } \ 2222 } while (0) 2223 COMPARE_CAPS(nbm); 2224 COMPARE_CAPS(link); 2225 COMPARE_CAPS(switch); 2226 COMPARE_CAPS(nic); 2227 COMPARE_CAPS(toe); 2228 COMPARE_CAPS(rdma); 2229 COMPARE_CAPS(crypto); 2230 COMPARE_CAPS(iscsi); 2231 COMPARE_CAPS(fcoe); 2232 #undef COMPARE_CAPS 2233 2234 /* Firmware config file */ 2235 if (o->cfcsum != sc->cfcsum) { 2236 CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file, 2237 o->cfcsum, sc->cfg_file, sc->cfcsum); 2238 rc = EINVAL; 2239 } 2240 2241 #define COMPARE_PARAM(p, name) do { \ 2242 if (o->p != sc->p) { \ 2243 CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \ 2244 rc = EINVAL; \ 2245 } \ 2246 } while (0) 2247 COMPARE_PARAM(sge.iq_start, iq_start); 2248 COMPARE_PARAM(sge.eq_start, eq_start); 2249 COMPARE_PARAM(tids.ftid_base, ftid_base); 2250 COMPARE_PARAM(tids.ftid_end, ftid_end); 2251 COMPARE_PARAM(tids.nftids, nftids); 2252 COMPARE_PARAM(vres.l2t.start, l2t_start); 2253 COMPARE_PARAM(vres.l2t.size, l2t_size); 2254 COMPARE_PARAM(sge.iqmap_sz, iqmap_sz); 2255 COMPARE_PARAM(sge.eqmap_sz, eqmap_sz); 2256 COMPARE_PARAM(tids.tid_base, tid_base); 2257 COMPARE_PARAM(tids.hpftid_base, hpftid_base); 2258 COMPARE_PARAM(tids.hpftid_end, hpftid_end); 2259 COMPARE_PARAM(tids.nhpftids, nhpftids); 2260 COMPARE_PARAM(rawf_base, rawf_base); 2261 COMPARE_PARAM(nrawf, nrawf); 2262 COMPARE_PARAM(params.mps_bg_map, mps_bg_map); 2263 COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support); 2264 COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl); 2265 COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support); 2266 COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr); 2267 COMPARE_PARAM(tids.ntids, ntids); 2268 COMPARE_PARAM(tids.etid_base, etid_base); 2269 COMPARE_PARAM(tids.etid_end, etid_end); 2270 COMPARE_PARAM(tids.netids, netids); 2271 COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred); 2272 COMPARE_PARAM(params.ethoffload, ethoffload); 2273 COMPARE_PARAM(tids.natids, natids); 2274 COMPARE_PARAM(tids.stid_base, stid_base); 2275 COMPARE_PARAM(vres.ddp.start, ddp_start); 2276 COMPARE_PARAM(vres.ddp.size, ddp_size); 2277 COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred); 2278 COMPARE_PARAM(vres.stag.start, stag_start); 2279 COMPARE_PARAM(vres.stag.size, stag_size); 2280 COMPARE_PARAM(vres.rq.start, rq_start); 2281 COMPARE_PARAM(vres.rq.size, rq_size); 2282 COMPARE_PARAM(vres.pbl.start, pbl_start); 2283 COMPARE_PARAM(vres.pbl.size, pbl_size); 2284 COMPARE_PARAM(vres.qp.start, qp_start); 2285 COMPARE_PARAM(vres.qp.size, qp_size); 2286 COMPARE_PARAM(vres.cq.start, cq_start); 2287 COMPARE_PARAM(vres.cq.size, cq_size); 2288 COMPARE_PARAM(vres.ocq.start, ocq_start); 2289 COMPARE_PARAM(vres.ocq.size, ocq_size); 2290 COMPARE_PARAM(vres.srq.start, srq_start); 2291 COMPARE_PARAM(vres.srq.size, srq_size); 2292 COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp); 2293 COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter); 2294 COMPARE_PARAM(vres.iscsi.start, iscsi_start); 2295 COMPARE_PARAM(vres.iscsi.size, iscsi_size); 2296 COMPARE_PARAM(vres.key.start, key_start); 2297 COMPARE_PARAM(vres.key.size, key_size); 2298 #undef COMPARE_PARAM 2299 2300 return (rc); 2301 } 2302 2303 static int 2304 restart_lld(struct adapter *sc) 2305 { 2306 struct adapter_pre_reset_state *old_state = NULL; 2307 struct port_info *pi; 2308 struct vi_info *vi; 2309 if_t ifp; 2310 struct sge_txq *txq; 2311 int rc, i, j, k; 2312 2313 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rlld"); 2314 if (rc != 0) 2315 return (ENXIO); 2316 2317 /* Restore memory window. */ 2318 setup_memwin(sc); 2319 2320 /* Go no further if recovery mode has been requested. */ 2321 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 2322 CH_ALERT(sc, "%s: recovery mode during restart.\n", __func__); 2323 rc = 0; 2324 set_adapter_hwstatus(sc, true); 2325 goto done; 2326 } 2327 2328 old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK); 2329 save_caps_and_params(sc, old_state); 2330 2331 /* Reestablish contact with firmware and become the primary PF. */ 2332 rc = contact_firmware(sc); 2333 if (rc != 0) 2334 goto done; /* error message displayed already */ 2335 MPASS(sc->flags & FW_OK); 2336 2337 if (sc->flags & MASTER_PF) { 2338 rc = partition_resources(sc); 2339 if (rc != 0) 2340 goto done; /* error message displayed already */ 2341 } 2342 2343 rc = get_params__post_init(sc); 2344 if (rc != 0) 2345 goto done; /* error message displayed already */ 2346 2347 rc = set_params__post_init(sc); 2348 if (rc != 0) 2349 goto done; /* error message displayed already */ 2350 2351 rc = compare_caps_and_params(sc, old_state); 2352 if (rc != 0) 2353 goto done; /* error message displayed already */ 2354 2355 for_each_port(sc, i) { 2356 pi = sc->port[i]; 2357 MPASS(pi != NULL); 2358 MPASS(pi->vi != NULL); 2359 MPASS(pi->vi[0].dev == pi->dev); 2360 2361 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 2362 if (rc != 0) { 2363 CH_ERR(sc, 2364 "failed to re-initialize port %d: %d\n", i, rc); 2365 goto done; 2366 } 2367 MPASS(sc->chan_map[pi->tx_chan] == i); 2368 2369 PORT_LOCK(pi); 2370 fixup_link_config(pi); 2371 build_medialist(pi); 2372 PORT_UNLOCK(pi); 2373 for_each_vi(pi, j, vi) { 2374 if (IS_MAIN_VI(vi)) 2375 continue; 2376 rc = alloc_extra_vi(sc, pi, vi); 2377 if (rc != 0) { 2378 CH_ERR(vi, 2379 "failed to re-allocate extra VI: %d\n", rc); 2380 goto done; 2381 } 2382 } 2383 } 2384 2385 /* 2386 * Interrupts and queues are about to be enabled and other threads will 2387 * want to access the hardware too. It is safe to do so. Note that 2388 * this thread is still in the middle of a synchronized_op. 2389 */ 2390 set_adapter_hwstatus(sc, true); 2391 2392 if (sc->flags & FULL_INIT_DONE) { 2393 rc = adapter_full_init(sc); 2394 if (rc != 0) { 2395 CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc); 2396 goto done; 2397 } 2398 2399 if (sc->vxlan_refcount > 0) 2400 enable_vxlan_rx(sc); 2401 2402 for_each_port(sc, i) { 2403 pi = sc->port[i]; 2404 for_each_vi(pi, j, vi) { 2405 mtx_lock(&vi->tick_mtx); 2406 vi->flags &= ~VI_SKIP_STATS; 2407 mtx_unlock(&vi->tick_mtx); 2408 if (!(vi->flags & VI_INIT_DONE)) 2409 continue; 2410 rc = vi_full_init(vi); 2411 if (rc != 0) { 2412 CH_ERR(vi, "failed to re-initialize " 2413 "interface: %d\n", rc); 2414 goto done; 2415 } 2416 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 2417 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 2418 t4_write_reg(sc, is_t4(sc) ? 2419 A_MPS_TRC_RSS_CONTROL : 2420 A_MPS_T5_TRC_RSS_CONTROL, 2421 V_RSSCONTROL(pi->tx_chan) | 2422 V_QUEUENUMBER(sc->traceq)); 2423 pi->flags |= HAS_TRACEQ; 2424 } 2425 2426 ifp = vi->ifp; 2427 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2428 continue; 2429 /* 2430 * Note that we do not setup multicast addresses 2431 * in the first pass. This ensures that the 2432 * unicast DMACs for all VIs on all ports get an 2433 * MPS TCAM entry. 2434 */ 2435 rc = update_mac_settings(ifp, XGMAC_ALL & 2436 ~XGMAC_MCADDRS); 2437 if (rc != 0) { 2438 CH_ERR(vi, "failed to re-configure MAC: %d\n", rc); 2439 goto done; 2440 } 2441 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, 2442 true); 2443 if (rc != 0) { 2444 CH_ERR(vi, "failed to re-enable VI: %d\n", rc); 2445 goto done; 2446 } 2447 for_each_txq(vi, k, txq) { 2448 TXQ_LOCK(txq); 2449 txq->eq.flags |= EQ_ENABLED; 2450 TXQ_UNLOCK(txq); 2451 } 2452 mtx_lock(&vi->tick_mtx); 2453 callout_schedule(&vi->tick, hz); 2454 mtx_unlock(&vi->tick_mtx); 2455 } 2456 PORT_LOCK(pi); 2457 if (pi->up_vis > 0) { 2458 t4_update_port_info(pi); 2459 fixup_link_config(pi); 2460 build_medialist(pi); 2461 apply_link_config(pi); 2462 if (pi->link_cfg.link_ok) 2463 t4_os_link_changed(pi); 2464 } 2465 PORT_UNLOCK(pi); 2466 } 2467 2468 /* Now reprogram the L2 multicast addresses. */ 2469 for_each_port(sc, i) { 2470 pi = sc->port[i]; 2471 for_each_vi(pi, j, vi) { 2472 if (!(vi->flags & VI_INIT_DONE)) 2473 continue; 2474 ifp = vi->ifp; 2475 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2476 continue; 2477 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2478 if (rc != 0) { 2479 CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc); 2480 rc = 0; /* carry on */ 2481 } 2482 } 2483 } 2484 } 2485 2486 /* Reset all calibration */ 2487 t4_calibration_start(sc); 2488 done: 2489 end_synchronized_op(sc, 0); 2490 free(old_state, M_CXGBE); 2491 2492 restart_atid_allocator(sc); 2493 t4_restart_l2t(sc); 2494 2495 return (rc); 2496 } 2497 2498 int 2499 resume_adapter(struct adapter *sc) 2500 { 2501 restart_adapter(sc); 2502 restart_lld(sc); 2503 #ifdef TCP_OFFLOAD 2504 restart_all_uld(sc); 2505 #endif 2506 return (0); 2507 } 2508 2509 static int 2510 t4_resume(device_t dev) 2511 { 2512 struct adapter *sc = device_get_softc(dev); 2513 int rc; 2514 2515 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2516 rc = resume_adapter(sc); 2517 CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread); 2518 2519 return (rc); 2520 } 2521 2522 static int 2523 t4_reset_prepare(device_t dev, device_t child) 2524 { 2525 struct adapter *sc = device_get_softc(dev); 2526 2527 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2528 return (0); 2529 } 2530 2531 static int 2532 t4_reset_post(device_t dev, device_t child) 2533 { 2534 struct adapter *sc = device_get_softc(dev); 2535 2536 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2537 return (0); 2538 } 2539 2540 static int 2541 reset_adapter_with_pci_bus_reset(struct adapter *sc) 2542 { 2543 int rc; 2544 2545 mtx_lock(&Giant); 2546 rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0); 2547 mtx_unlock(&Giant); 2548 return (rc); 2549 } 2550 2551 static int 2552 reset_adapter_with_pl_rst(struct adapter *sc) 2553 { 2554 suspend_adapter(sc); 2555 2556 /* This is a t4_write_reg without the hw_off_limits check. */ 2557 MPASS(sc->error_flags & HW_OFF_LIMITS); 2558 bus_space_write_4(sc->bt, sc->bh, A_PL_RST, 2559 F_PIORSTMODE | F_PIORST | F_AUTOPCIEPAUSE); 2560 pause("pl_rst", 1 * hz); /* Wait 1s for reset */ 2561 2562 resume_adapter(sc); 2563 2564 return (0); 2565 } 2566 2567 static inline int 2568 reset_adapter(struct adapter *sc) 2569 { 2570 if (vm_guest == 0) 2571 return (reset_adapter_with_pci_bus_reset(sc)); 2572 else 2573 return (reset_adapter_with_pl_rst(sc)); 2574 } 2575 2576 static void 2577 reset_adapter_task(void *arg, int pending) 2578 { 2579 struct adapter *sc = arg; 2580 const int flags = sc->flags; 2581 const int eflags = sc->error_flags; 2582 int rc; 2583 2584 if (pending > 1) 2585 CH_ALERT(sc, "%s: pending %d\n", __func__, pending); 2586 rc = reset_adapter(sc); 2587 if (rc != 0) { 2588 CH_ERR(sc, "adapter did not reset properly, rc = %d, " 2589 "flags 0x%08x -> 0x%08x, err_flags 0x%08x -> 0x%08x.\n", 2590 rc, flags, sc->flags, eflags, sc->error_flags); 2591 } 2592 } 2593 2594 static int 2595 cxgbe_probe(device_t dev) 2596 { 2597 struct port_info *pi = device_get_softc(dev); 2598 2599 device_set_descf(dev, "port %d", pi->port_id); 2600 2601 return (BUS_PROBE_DEFAULT); 2602 } 2603 2604 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 2605 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 2606 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 2607 IFCAP_HWRXTSTMP | IFCAP_MEXTPG) 2608 #define T4_CAP_ENABLE (T4_CAP) 2609 2610 static void 2611 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 2612 { 2613 if_t ifp; 2614 struct sbuf *sb; 2615 struct sysctl_ctx_list *ctx = &vi->ctx; 2616 struct sysctl_oid_list *children; 2617 struct pfil_head_args pa; 2618 struct adapter *sc = vi->adapter; 2619 2620 sysctl_ctx_init(ctx); 2621 children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev)); 2622 vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq", 2623 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues"); 2624 vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq", 2625 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues"); 2626 #ifdef DEV_NETMAP 2627 vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq", 2628 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues"); 2629 vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq", 2630 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues"); 2631 #endif 2632 #ifdef TCP_OFFLOAD 2633 vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq", 2634 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues"); 2635 #endif 2636 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2637 vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq", 2638 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues"); 2639 #endif 2640 2641 vi->xact_addr_filt = -1; 2642 mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF); 2643 callout_init_mtx(&vi->tick, &vi->tick_mtx, 0); 2644 if (sc->flags & IS_VF || t4_tx_vm_wr != 0) 2645 vi->flags |= TX_USES_VM_WR; 2646 2647 /* Allocate an ifnet and set it up */ 2648 ifp = if_alloc_dev(IFT_ETHER, dev); 2649 vi->ifp = ifp; 2650 if_setsoftc(ifp, vi); 2651 2652 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2653 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2654 2655 if_setinitfn(ifp, cxgbe_init); 2656 if_setioctlfn(ifp, cxgbe_ioctl); 2657 if_settransmitfn(ifp, cxgbe_transmit); 2658 if_setqflushfn(ifp, cxgbe_qflush); 2659 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 2660 if_setgetcounterfn(ifp, vi_get_counter); 2661 else 2662 if_setgetcounterfn(ifp, cxgbe_get_counter); 2663 #if defined(KERN_TLS) || defined(RATELIMIT) 2664 if_setsndtagallocfn(ifp, cxgbe_snd_tag_alloc); 2665 #endif 2666 #ifdef RATELIMIT 2667 if_setratelimitqueryfn(ifp, cxgbe_ratelimit_query); 2668 #endif 2669 2670 if_setcapabilities(ifp, T4_CAP); 2671 if_setcapenable(ifp, T4_CAP_ENABLE); 2672 if_sethwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 2673 CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2674 if (chip_id(sc) >= CHELSIO_T6) { 2675 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2676 if_setcapenablebit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2677 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 2678 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2679 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN, 0); 2680 } 2681 2682 #ifdef TCP_OFFLOAD 2683 if (vi->nofldrxq != 0) 2684 if_setcapabilitiesbit(ifp, IFCAP_TOE, 0); 2685 #endif 2686 #ifdef RATELIMIT 2687 if (is_ethoffload(sc) && vi->nofldtxq != 0) { 2688 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0); 2689 if_setcapenablebit(ifp, IFCAP_TXRTLMT, 0); 2690 } 2691 #endif 2692 2693 if_sethwtsomax(ifp, IP_MAXPACKET); 2694 if (vi->flags & TX_USES_VM_WR) 2695 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_VM_TSO); 2696 else 2697 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_TSO); 2698 #ifdef RATELIMIT 2699 if (is_ethoffload(sc) && vi->nofldtxq != 0) 2700 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_EO_TSO); 2701 #endif 2702 if_sethwtsomaxsegsize(ifp, 65536); 2703 #ifdef KERN_TLS 2704 if (is_ktls(sc)) { 2705 if_setcapabilitiesbit(ifp, IFCAP_TXTLS, 0); 2706 if (sc->flags & KERN_TLS_ON || !is_t6(sc)) 2707 if_setcapenablebit(ifp, IFCAP_TXTLS, 0); 2708 } 2709 #endif 2710 2711 ether_ifattach(ifp, vi->hw_addr); 2712 #ifdef DEV_NETMAP 2713 if (vi->nnmrxq != 0) 2714 cxgbe_nm_attach(vi); 2715 #endif 2716 sb = sbuf_new_auto(); 2717 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 2718 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2719 switch (if_getcapabilities(ifp) & (IFCAP_TOE | IFCAP_TXRTLMT)) { 2720 case IFCAP_TOE: 2721 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 2722 break; 2723 case IFCAP_TOE | IFCAP_TXRTLMT: 2724 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 2725 break; 2726 case IFCAP_TXRTLMT: 2727 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 2728 break; 2729 } 2730 #endif 2731 #ifdef TCP_OFFLOAD 2732 if (if_getcapabilities(ifp) & IFCAP_TOE) 2733 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 2734 #endif 2735 #ifdef DEV_NETMAP 2736 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2737 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 2738 vi->nnmtxq, vi->nnmrxq); 2739 #endif 2740 sbuf_finish(sb); 2741 device_printf(dev, "%s\n", sbuf_data(sb)); 2742 sbuf_delete(sb); 2743 2744 vi_sysctls(vi); 2745 2746 pa.pa_version = PFIL_VERSION; 2747 pa.pa_flags = PFIL_IN; 2748 pa.pa_type = PFIL_TYPE_ETHERNET; 2749 pa.pa_headname = if_name(ifp); 2750 vi->pfil = pfil_head_register(&pa); 2751 } 2752 2753 static int 2754 cxgbe_attach(device_t dev) 2755 { 2756 struct port_info *pi = device_get_softc(dev); 2757 struct adapter *sc = pi->adapter; 2758 struct vi_info *vi; 2759 int i; 2760 2761 sysctl_ctx_init(&pi->ctx); 2762 2763 cxgbe_vi_attach(dev, &pi->vi[0]); 2764 2765 for_each_vi(pi, i, vi) { 2766 if (i == 0) 2767 continue; 2768 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, DEVICE_UNIT_ANY); 2769 if (vi->dev == NULL) { 2770 device_printf(dev, "failed to add VI %d\n", i); 2771 continue; 2772 } 2773 device_set_softc(vi->dev, vi); 2774 } 2775 2776 cxgbe_sysctls(pi); 2777 2778 bus_generic_attach(dev); 2779 2780 return (0); 2781 } 2782 2783 static void 2784 cxgbe_vi_detach(struct vi_info *vi) 2785 { 2786 if_t ifp = vi->ifp; 2787 2788 if (vi->pfil != NULL) { 2789 pfil_head_unregister(vi->pfil); 2790 vi->pfil = NULL; 2791 } 2792 2793 ether_ifdetach(ifp); 2794 2795 /* Let detach proceed even if these fail. */ 2796 #ifdef DEV_NETMAP 2797 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2798 cxgbe_nm_detach(vi); 2799 #endif 2800 cxgbe_uninit_synchronized(vi); 2801 callout_drain(&vi->tick); 2802 mtx_destroy(&vi->tick_mtx); 2803 sysctl_ctx_free(&vi->ctx); 2804 vi_full_uninit(vi); 2805 2806 if_free(vi->ifp); 2807 vi->ifp = NULL; 2808 } 2809 2810 static int 2811 cxgbe_detach(device_t dev) 2812 { 2813 struct port_info *pi = device_get_softc(dev); 2814 struct adapter *sc = pi->adapter; 2815 int rc; 2816 2817 /* Detach the extra VIs first. */ 2818 rc = bus_generic_detach(dev); 2819 if (rc) 2820 return (rc); 2821 device_delete_children(dev); 2822 2823 sysctl_ctx_free(&pi->ctx); 2824 begin_vi_detach(sc, &pi->vi[0]); 2825 if (pi->flags & HAS_TRACEQ) { 2826 sc->traceq = -1; /* cloner should not create ifnet */ 2827 t4_tracer_port_detach(sc); 2828 } 2829 cxgbe_vi_detach(&pi->vi[0]); 2830 ifmedia_removeall(&pi->media); 2831 end_vi_detach(sc, &pi->vi[0]); 2832 2833 return (0); 2834 } 2835 2836 static void 2837 cxgbe_init(void *arg) 2838 { 2839 struct vi_info *vi = arg; 2840 struct adapter *sc = vi->adapter; 2841 2842 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 2843 return; 2844 cxgbe_init_synchronized(vi); 2845 end_synchronized_op(sc, 0); 2846 } 2847 2848 static int 2849 cxgbe_ioctl(if_t ifp, unsigned long cmd, caddr_t data) 2850 { 2851 int rc = 0, mtu, flags; 2852 struct vi_info *vi = if_getsoftc(ifp); 2853 struct port_info *pi = vi->pi; 2854 struct adapter *sc = pi->adapter; 2855 struct ifreq *ifr = (struct ifreq *)data; 2856 uint32_t mask; 2857 2858 switch (cmd) { 2859 case SIOCSIFMTU: 2860 mtu = ifr->ifr_mtu; 2861 if (mtu < ETHERMIN || mtu > MAX_MTU) 2862 return (EINVAL); 2863 2864 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 2865 if (rc) 2866 return (rc); 2867 if_setmtu(ifp, mtu); 2868 if (vi->flags & VI_INIT_DONE) { 2869 t4_update_fl_bufsize(ifp); 2870 if (!hw_off_limits(sc) && 2871 if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2872 rc = update_mac_settings(ifp, XGMAC_MTU); 2873 } 2874 end_synchronized_op(sc, 0); 2875 break; 2876 2877 case SIOCSIFFLAGS: 2878 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 2879 if (rc) 2880 return (rc); 2881 2882 if (hw_off_limits(sc)) { 2883 rc = ENXIO; 2884 goto fail; 2885 } 2886 2887 if (if_getflags(ifp) & IFF_UP) { 2888 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2889 flags = vi->if_flags; 2890 if ((if_getflags(ifp) ^ flags) & 2891 (IFF_PROMISC | IFF_ALLMULTI)) { 2892 rc = update_mac_settings(ifp, 2893 XGMAC_PROMISC | XGMAC_ALLMULTI); 2894 } 2895 } else { 2896 rc = cxgbe_init_synchronized(vi); 2897 } 2898 vi->if_flags = if_getflags(ifp); 2899 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2900 rc = cxgbe_uninit_synchronized(vi); 2901 } 2902 end_synchronized_op(sc, 0); 2903 break; 2904 2905 case SIOCADDMULTI: 2906 case SIOCDELMULTI: 2907 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 2908 if (rc) 2909 return (rc); 2910 if (!hw_off_limits(sc) && if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2911 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2912 end_synchronized_op(sc, 0); 2913 break; 2914 2915 case SIOCSIFCAP: 2916 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 2917 if (rc) 2918 return (rc); 2919 2920 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2921 if (mask & IFCAP_TXCSUM) { 2922 if_togglecapenable(ifp, IFCAP_TXCSUM); 2923 if_togglehwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP); 2924 2925 if (IFCAP_TSO4 & if_getcapenable(ifp) && 2926 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2927 mask &= ~IFCAP_TSO4; 2928 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 2929 if_printf(ifp, 2930 "tso4 disabled due to -txcsum.\n"); 2931 } 2932 } 2933 if (mask & IFCAP_TXCSUM_IPV6) { 2934 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 2935 if_togglehwassist(ifp, CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2936 2937 if (IFCAP_TSO6 & if_getcapenable(ifp) && 2938 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2939 mask &= ~IFCAP_TSO6; 2940 if_setcapenablebit(ifp, 0, IFCAP_TSO6); 2941 if_printf(ifp, 2942 "tso6 disabled due to -txcsum6.\n"); 2943 } 2944 } 2945 if (mask & IFCAP_RXCSUM) 2946 if_togglecapenable(ifp, IFCAP_RXCSUM); 2947 if (mask & IFCAP_RXCSUM_IPV6) 2948 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 2949 2950 /* 2951 * Note that we leave CSUM_TSO alone (it is always set). The 2952 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 2953 * sending a TSO request our way, so it's sufficient to toggle 2954 * IFCAP_TSOx only. 2955 */ 2956 if (mask & IFCAP_TSO4) { 2957 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) && 2958 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2959 if_printf(ifp, "enable txcsum first.\n"); 2960 rc = EAGAIN; 2961 goto fail; 2962 } 2963 if_togglecapenable(ifp, IFCAP_TSO4); 2964 } 2965 if (mask & IFCAP_TSO6) { 2966 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) && 2967 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2968 if_printf(ifp, "enable txcsum6 first.\n"); 2969 rc = EAGAIN; 2970 goto fail; 2971 } 2972 if_togglecapenable(ifp, IFCAP_TSO6); 2973 } 2974 if (mask & IFCAP_LRO) { 2975 #if defined(INET) || defined(INET6) 2976 int i; 2977 struct sge_rxq *rxq; 2978 2979 if_togglecapenable(ifp, IFCAP_LRO); 2980 for_each_rxq(vi, i, rxq) { 2981 if (if_getcapenable(ifp) & IFCAP_LRO) 2982 rxq->iq.flags |= IQ_LRO_ENABLED; 2983 else 2984 rxq->iq.flags &= ~IQ_LRO_ENABLED; 2985 } 2986 #endif 2987 } 2988 #ifdef TCP_OFFLOAD 2989 if (mask & IFCAP_TOE) { 2990 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TOE; 2991 2992 rc = toe_capability(vi, enable); 2993 if (rc != 0) 2994 goto fail; 2995 2996 if_togglecapenable(ifp, mask); 2997 } 2998 #endif 2999 if (mask & IFCAP_VLAN_HWTAGGING) { 3000 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3001 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3002 rc = update_mac_settings(ifp, XGMAC_VLANEX); 3003 } 3004 if (mask & IFCAP_VLAN_MTU) { 3005 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 3006 3007 /* Need to find out how to disable auto-mtu-inflation */ 3008 } 3009 if (mask & IFCAP_VLAN_HWTSO) 3010 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3011 if (mask & IFCAP_VLAN_HWCSUM) 3012 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3013 #ifdef RATELIMIT 3014 if (mask & IFCAP_TXRTLMT) 3015 if_togglecapenable(ifp, IFCAP_TXRTLMT); 3016 #endif 3017 if (mask & IFCAP_HWRXTSTMP) { 3018 int i; 3019 struct sge_rxq *rxq; 3020 3021 if_togglecapenable(ifp, IFCAP_HWRXTSTMP); 3022 for_each_rxq(vi, i, rxq) { 3023 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) 3024 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3025 else 3026 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 3027 } 3028 } 3029 if (mask & IFCAP_MEXTPG) 3030 if_togglecapenable(ifp, IFCAP_MEXTPG); 3031 3032 #ifdef KERN_TLS 3033 if (mask & IFCAP_TXTLS) { 3034 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TXTLS; 3035 3036 rc = ktls_capability(sc, enable); 3037 if (rc != 0) 3038 goto fail; 3039 3040 if_togglecapenable(ifp, mask & IFCAP_TXTLS); 3041 } 3042 #endif 3043 if (mask & IFCAP_VXLAN_HWCSUM) { 3044 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM); 3045 if_togglehwassist(ifp, CSUM_INNER_IP6_UDP | 3046 CSUM_INNER_IP6_TCP | CSUM_INNER_IP | 3047 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP); 3048 } 3049 if (mask & IFCAP_VXLAN_HWTSO) { 3050 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO); 3051 if_togglehwassist(ifp, CSUM_INNER_IP6_TSO | 3052 CSUM_INNER_IP_TSO); 3053 } 3054 3055 #ifdef VLAN_CAPABILITIES 3056 VLAN_CAPABILITIES(ifp); 3057 #endif 3058 fail: 3059 end_synchronized_op(sc, 0); 3060 break; 3061 3062 case SIOCSIFMEDIA: 3063 case SIOCGIFMEDIA: 3064 case SIOCGIFXMEDIA: 3065 rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 3066 break; 3067 3068 case SIOCGI2C: { 3069 struct ifi2creq i2c; 3070 3071 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3072 if (rc != 0) 3073 break; 3074 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3075 rc = EPERM; 3076 break; 3077 } 3078 if (i2c.len > sizeof(i2c.data)) { 3079 rc = EINVAL; 3080 break; 3081 } 3082 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 3083 if (rc) 3084 return (rc); 3085 if (hw_off_limits(sc)) 3086 rc = ENXIO; 3087 else 3088 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 3089 i2c.offset, i2c.len, &i2c.data[0]); 3090 end_synchronized_op(sc, 0); 3091 if (rc == 0) 3092 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3093 break; 3094 } 3095 3096 default: 3097 rc = ether_ioctl(ifp, cmd, data); 3098 } 3099 3100 return (rc); 3101 } 3102 3103 static int 3104 cxgbe_transmit(if_t ifp, struct mbuf *m) 3105 { 3106 struct vi_info *vi = if_getsoftc(ifp); 3107 struct port_info *pi = vi->pi; 3108 struct adapter *sc; 3109 struct sge_txq *txq; 3110 void *items[1]; 3111 int rc; 3112 3113 M_ASSERTPKTHDR(m); 3114 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 3115 #if defined(KERN_TLS) || defined(RATELIMIT) 3116 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) 3117 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 3118 #endif 3119 3120 if (__predict_false(pi->link_cfg.link_ok == false)) { 3121 m_freem(m); 3122 return (ENETDOWN); 3123 } 3124 3125 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR); 3126 if (__predict_false(rc != 0)) { 3127 if (__predict_true(rc == EINPROGRESS)) { 3128 /* queued by parse_pkt */ 3129 MPASS(m != NULL); 3130 return (0); 3131 } 3132 3133 MPASS(m == NULL); /* was freed already */ 3134 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 3135 return (rc); 3136 } 3137 3138 /* Select a txq. */ 3139 sc = vi->adapter; 3140 txq = &sc->sge.txq[vi->first_txq]; 3141 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 3142 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 3143 vi->rsrv_noflowq); 3144 3145 items[0] = m; 3146 rc = mp_ring_enqueue(txq->r, items, 1, 256); 3147 if (__predict_false(rc != 0)) 3148 m_freem(m); 3149 3150 return (rc); 3151 } 3152 3153 static void 3154 cxgbe_qflush(if_t ifp) 3155 { 3156 struct vi_info *vi = if_getsoftc(ifp); 3157 struct sge_txq *txq; 3158 int i; 3159 3160 /* queues do not exist if !VI_INIT_DONE. */ 3161 if (vi->flags & VI_INIT_DONE) { 3162 for_each_txq(vi, i, txq) { 3163 TXQ_LOCK(txq); 3164 txq->eq.flags |= EQ_QFLUSH; 3165 TXQ_UNLOCK(txq); 3166 while (!mp_ring_is_idle(txq->r)) { 3167 mp_ring_check_drainage(txq->r, 4096); 3168 pause("qflush", 1); 3169 } 3170 TXQ_LOCK(txq); 3171 txq->eq.flags &= ~EQ_QFLUSH; 3172 TXQ_UNLOCK(txq); 3173 } 3174 } 3175 if_qflush(ifp); 3176 } 3177 3178 static uint64_t 3179 vi_get_counter(if_t ifp, ift_counter c) 3180 { 3181 struct vi_info *vi = if_getsoftc(ifp); 3182 struct fw_vi_stats_vf *s = &vi->stats; 3183 3184 mtx_lock(&vi->tick_mtx); 3185 vi_refresh_stats(vi); 3186 mtx_unlock(&vi->tick_mtx); 3187 3188 switch (c) { 3189 case IFCOUNTER_IPACKETS: 3190 return (s->rx_bcast_frames + s->rx_mcast_frames + 3191 s->rx_ucast_frames); 3192 case IFCOUNTER_IERRORS: 3193 return (s->rx_err_frames); 3194 case IFCOUNTER_OPACKETS: 3195 return (s->tx_bcast_frames + s->tx_mcast_frames + 3196 s->tx_ucast_frames + s->tx_offload_frames); 3197 case IFCOUNTER_OERRORS: 3198 return (s->tx_drop_frames); 3199 case IFCOUNTER_IBYTES: 3200 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 3201 s->rx_ucast_bytes); 3202 case IFCOUNTER_OBYTES: 3203 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 3204 s->tx_ucast_bytes + s->tx_offload_bytes); 3205 case IFCOUNTER_IMCASTS: 3206 return (s->rx_mcast_frames); 3207 case IFCOUNTER_OMCASTS: 3208 return (s->tx_mcast_frames); 3209 case IFCOUNTER_OQDROPS: { 3210 uint64_t drops; 3211 3212 drops = 0; 3213 if (vi->flags & VI_INIT_DONE) { 3214 int i; 3215 struct sge_txq *txq; 3216 3217 for_each_txq(vi, i, txq) 3218 drops += counter_u64_fetch(txq->r->dropped); 3219 } 3220 3221 return (drops); 3222 3223 } 3224 3225 default: 3226 return (if_get_counter_default(ifp, c)); 3227 } 3228 } 3229 3230 static uint64_t 3231 cxgbe_get_counter(if_t ifp, ift_counter c) 3232 { 3233 struct vi_info *vi = if_getsoftc(ifp); 3234 struct port_info *pi = vi->pi; 3235 struct port_stats *s = &pi->stats; 3236 3237 mtx_lock(&vi->tick_mtx); 3238 cxgbe_refresh_stats(vi); 3239 mtx_unlock(&vi->tick_mtx); 3240 3241 switch (c) { 3242 case IFCOUNTER_IPACKETS: 3243 return (s->rx_frames); 3244 3245 case IFCOUNTER_IERRORS: 3246 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 3247 s->rx_fcs_err + s->rx_len_err); 3248 3249 case IFCOUNTER_OPACKETS: 3250 return (s->tx_frames); 3251 3252 case IFCOUNTER_OERRORS: 3253 return (s->tx_error_frames); 3254 3255 case IFCOUNTER_IBYTES: 3256 return (s->rx_octets); 3257 3258 case IFCOUNTER_OBYTES: 3259 return (s->tx_octets); 3260 3261 case IFCOUNTER_IMCASTS: 3262 return (s->rx_mcast_frames); 3263 3264 case IFCOUNTER_OMCASTS: 3265 return (s->tx_mcast_frames); 3266 3267 case IFCOUNTER_IQDROPS: 3268 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 3269 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 3270 s->rx_trunc3 + pi->tnl_cong_drops); 3271 3272 case IFCOUNTER_OQDROPS: { 3273 uint64_t drops; 3274 3275 drops = s->tx_drop; 3276 if (vi->flags & VI_INIT_DONE) { 3277 int i; 3278 struct sge_txq *txq; 3279 3280 for_each_txq(vi, i, txq) 3281 drops += counter_u64_fetch(txq->r->dropped); 3282 } 3283 3284 return (drops); 3285 3286 } 3287 3288 default: 3289 return (if_get_counter_default(ifp, c)); 3290 } 3291 } 3292 3293 #if defined(KERN_TLS) || defined(RATELIMIT) 3294 static int 3295 cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params, 3296 struct m_snd_tag **pt) 3297 { 3298 int error; 3299 3300 switch (params->hdr.type) { 3301 #ifdef RATELIMIT 3302 case IF_SND_TAG_TYPE_RATE_LIMIT: 3303 error = cxgbe_rate_tag_alloc(ifp, params, pt); 3304 break; 3305 #endif 3306 #ifdef KERN_TLS 3307 case IF_SND_TAG_TYPE_TLS: 3308 { 3309 struct vi_info *vi = if_getsoftc(ifp); 3310 3311 if (is_t6(vi->pi->adapter)) 3312 error = t6_tls_tag_alloc(ifp, params, pt); 3313 else 3314 error = EOPNOTSUPP; 3315 break; 3316 } 3317 #endif 3318 default: 3319 error = EOPNOTSUPP; 3320 } 3321 return (error); 3322 } 3323 #endif 3324 3325 /* 3326 * The kernel picks a media from the list we had provided but we still validate 3327 * the requeste. 3328 */ 3329 int 3330 cxgbe_media_change(if_t ifp) 3331 { 3332 struct vi_info *vi = if_getsoftc(ifp); 3333 struct port_info *pi = vi->pi; 3334 struct ifmedia *ifm = &pi->media; 3335 struct link_config *lc = &pi->link_cfg; 3336 struct adapter *sc = pi->adapter; 3337 int rc; 3338 3339 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 3340 if (rc != 0) 3341 return (rc); 3342 PORT_LOCK(pi); 3343 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 3344 /* ifconfig .. media autoselect */ 3345 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { 3346 rc = ENOTSUP; /* AN not supported by transceiver */ 3347 goto done; 3348 } 3349 lc->requested_aneg = AUTONEG_ENABLE; 3350 lc->requested_speed = 0; 3351 lc->requested_fc |= PAUSE_AUTONEG; 3352 } else { 3353 lc->requested_aneg = AUTONEG_DISABLE; 3354 lc->requested_speed = 3355 ifmedia_baudrate(ifm->ifm_media) / 1000000; 3356 lc->requested_fc = 0; 3357 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 3358 lc->requested_fc |= PAUSE_RX; 3359 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 3360 lc->requested_fc |= PAUSE_TX; 3361 } 3362 if (pi->up_vis > 0 && !hw_off_limits(sc)) { 3363 fixup_link_config(pi); 3364 rc = apply_link_config(pi); 3365 } 3366 done: 3367 PORT_UNLOCK(pi); 3368 end_synchronized_op(sc, 0); 3369 return (rc); 3370 } 3371 3372 /* 3373 * Base media word (without ETHER, pause, link active, etc.) for the port at the 3374 * given speed. 3375 */ 3376 static int 3377 port_mword(struct port_info *pi, uint32_t speed) 3378 { 3379 3380 MPASS(speed & M_FW_PORT_CAP32_SPEED); 3381 MPASS(powerof2(speed)); 3382 3383 switch(pi->port_type) { 3384 case FW_PORT_TYPE_BT_SGMII: 3385 case FW_PORT_TYPE_BT_XFI: 3386 case FW_PORT_TYPE_BT_XAUI: 3387 /* BaseT */ 3388 switch (speed) { 3389 case FW_PORT_CAP32_SPEED_100M: 3390 return (IFM_100_T); 3391 case FW_PORT_CAP32_SPEED_1G: 3392 return (IFM_1000_T); 3393 case FW_PORT_CAP32_SPEED_10G: 3394 return (IFM_10G_T); 3395 } 3396 break; 3397 case FW_PORT_TYPE_KX4: 3398 if (speed == FW_PORT_CAP32_SPEED_10G) 3399 return (IFM_10G_KX4); 3400 break; 3401 case FW_PORT_TYPE_CX4: 3402 if (speed == FW_PORT_CAP32_SPEED_10G) 3403 return (IFM_10G_CX4); 3404 break; 3405 case FW_PORT_TYPE_KX: 3406 if (speed == FW_PORT_CAP32_SPEED_1G) 3407 return (IFM_1000_KX); 3408 break; 3409 case FW_PORT_TYPE_KR: 3410 case FW_PORT_TYPE_BP_AP: 3411 case FW_PORT_TYPE_BP4_AP: 3412 case FW_PORT_TYPE_BP40_BA: 3413 case FW_PORT_TYPE_KR4_100G: 3414 case FW_PORT_TYPE_KR_SFP28: 3415 case FW_PORT_TYPE_KR_XLAUI: 3416 switch (speed) { 3417 case FW_PORT_CAP32_SPEED_1G: 3418 return (IFM_1000_KX); 3419 case FW_PORT_CAP32_SPEED_10G: 3420 return (IFM_10G_KR); 3421 case FW_PORT_CAP32_SPEED_25G: 3422 return (IFM_25G_KR); 3423 case FW_PORT_CAP32_SPEED_40G: 3424 return (IFM_40G_KR4); 3425 case FW_PORT_CAP32_SPEED_50G: 3426 return (IFM_50G_KR2); 3427 case FW_PORT_CAP32_SPEED_100G: 3428 return (IFM_100G_KR4); 3429 } 3430 break; 3431 case FW_PORT_TYPE_FIBER_XFI: 3432 case FW_PORT_TYPE_FIBER_XAUI: 3433 case FW_PORT_TYPE_SFP: 3434 case FW_PORT_TYPE_QSFP_10G: 3435 case FW_PORT_TYPE_QSA: 3436 case FW_PORT_TYPE_QSFP: 3437 case FW_PORT_TYPE_CR4_QSFP: 3438 case FW_PORT_TYPE_CR_QSFP: 3439 case FW_PORT_TYPE_CR2_QSFP: 3440 case FW_PORT_TYPE_SFP28: 3441 /* Pluggable transceiver */ 3442 switch (pi->mod_type) { 3443 case FW_PORT_MOD_TYPE_LR: 3444 switch (speed) { 3445 case FW_PORT_CAP32_SPEED_1G: 3446 return (IFM_1000_LX); 3447 case FW_PORT_CAP32_SPEED_10G: 3448 return (IFM_10G_LR); 3449 case FW_PORT_CAP32_SPEED_25G: 3450 return (IFM_25G_LR); 3451 case FW_PORT_CAP32_SPEED_40G: 3452 return (IFM_40G_LR4); 3453 case FW_PORT_CAP32_SPEED_50G: 3454 return (IFM_50G_LR2); 3455 case FW_PORT_CAP32_SPEED_100G: 3456 return (IFM_100G_LR4); 3457 } 3458 break; 3459 case FW_PORT_MOD_TYPE_SR: 3460 switch (speed) { 3461 case FW_PORT_CAP32_SPEED_1G: 3462 return (IFM_1000_SX); 3463 case FW_PORT_CAP32_SPEED_10G: 3464 return (IFM_10G_SR); 3465 case FW_PORT_CAP32_SPEED_25G: 3466 return (IFM_25G_SR); 3467 case FW_PORT_CAP32_SPEED_40G: 3468 return (IFM_40G_SR4); 3469 case FW_PORT_CAP32_SPEED_50G: 3470 return (IFM_50G_SR2); 3471 case FW_PORT_CAP32_SPEED_100G: 3472 return (IFM_100G_SR4); 3473 } 3474 break; 3475 case FW_PORT_MOD_TYPE_ER: 3476 if (speed == FW_PORT_CAP32_SPEED_10G) 3477 return (IFM_10G_ER); 3478 break; 3479 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3480 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3481 switch (speed) { 3482 case FW_PORT_CAP32_SPEED_1G: 3483 return (IFM_1000_CX); 3484 case FW_PORT_CAP32_SPEED_10G: 3485 return (IFM_10G_TWINAX); 3486 case FW_PORT_CAP32_SPEED_25G: 3487 return (IFM_25G_CR); 3488 case FW_PORT_CAP32_SPEED_40G: 3489 return (IFM_40G_CR4); 3490 case FW_PORT_CAP32_SPEED_50G: 3491 return (IFM_50G_CR2); 3492 case FW_PORT_CAP32_SPEED_100G: 3493 return (IFM_100G_CR4); 3494 } 3495 break; 3496 case FW_PORT_MOD_TYPE_LRM: 3497 if (speed == FW_PORT_CAP32_SPEED_10G) 3498 return (IFM_10G_LRM); 3499 break; 3500 case FW_PORT_MOD_TYPE_NA: 3501 MPASS(0); /* Not pluggable? */ 3502 /* fall throough */ 3503 case FW_PORT_MOD_TYPE_ERROR: 3504 case FW_PORT_MOD_TYPE_UNKNOWN: 3505 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 3506 break; 3507 case FW_PORT_MOD_TYPE_NONE: 3508 return (IFM_NONE); 3509 } 3510 break; 3511 case FW_PORT_TYPE_NONE: 3512 return (IFM_NONE); 3513 } 3514 3515 return (IFM_UNKNOWN); 3516 } 3517 3518 void 3519 cxgbe_media_status(if_t ifp, struct ifmediareq *ifmr) 3520 { 3521 struct vi_info *vi = if_getsoftc(ifp); 3522 struct port_info *pi = vi->pi; 3523 struct adapter *sc = pi->adapter; 3524 struct link_config *lc = &pi->link_cfg; 3525 3526 if (begin_synchronized_op(sc, vi , SLEEP_OK | INTR_OK, "t4med") != 0) 3527 return; 3528 PORT_LOCK(pi); 3529 3530 if (pi->up_vis == 0 && !hw_off_limits(sc)) { 3531 /* 3532 * If all the interfaces are administratively down the firmware 3533 * does not report transceiver changes. Refresh port info here 3534 * so that ifconfig displays accurate ifmedia at all times. 3535 * This is the only reason we have a synchronized op in this 3536 * function. Just PORT_LOCK would have been enough otherwise. 3537 */ 3538 t4_update_port_info(pi); 3539 build_medialist(pi); 3540 } 3541 3542 /* ifm_status */ 3543 ifmr->ifm_status = IFM_AVALID; 3544 if (lc->link_ok == false) 3545 goto done; 3546 ifmr->ifm_status |= IFM_ACTIVE; 3547 3548 /* ifm_active */ 3549 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 3550 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 3551 if (lc->fc & PAUSE_RX) 3552 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3553 if (lc->fc & PAUSE_TX) 3554 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3555 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 3556 done: 3557 PORT_UNLOCK(pi); 3558 end_synchronized_op(sc, 0); 3559 } 3560 3561 static int 3562 vcxgbe_probe(device_t dev) 3563 { 3564 struct vi_info *vi = device_get_softc(dev); 3565 3566 device_set_descf(dev, "port %d vi %td", vi->pi->port_id, 3567 vi - vi->pi->vi); 3568 3569 return (BUS_PROBE_DEFAULT); 3570 } 3571 3572 static int 3573 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 3574 { 3575 int func, index, rc; 3576 uint32_t param, val; 3577 3578 ASSERT_SYNCHRONIZED_OP(sc); 3579 3580 index = vi - pi->vi; 3581 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 3582 KASSERT(index < nitems(vi_mac_funcs), 3583 ("%s: VI %s doesn't have a MAC func", __func__, 3584 device_get_nameunit(vi->dev))); 3585 func = vi_mac_funcs[index]; 3586 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 3587 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 3588 if (rc < 0) { 3589 CH_ERR(vi, "failed to allocate virtual interface %d" 3590 "for port %d: %d\n", index, pi->port_id, -rc); 3591 return (-rc); 3592 } 3593 vi->viid = rc; 3594 3595 if (vi->rss_size == 1) { 3596 /* 3597 * This VI didn't get a slice of the RSS table. Reduce the 3598 * number of VIs being created (hw.cxgbe.num_vis) or modify the 3599 * configuration file (nvi, rssnvi for this PF) if this is a 3600 * problem. 3601 */ 3602 device_printf(vi->dev, "RSS table not available.\n"); 3603 vi->rss_base = 0xffff; 3604 3605 return (0); 3606 } 3607 3608 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3609 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 3610 V_FW_PARAMS_PARAM_YZ(vi->viid); 3611 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3612 if (rc) 3613 vi->rss_base = 0xffff; 3614 else { 3615 MPASS((val >> 16) == vi->rss_size); 3616 vi->rss_base = val & 0xffff; 3617 } 3618 3619 return (0); 3620 } 3621 3622 static int 3623 vcxgbe_attach(device_t dev) 3624 { 3625 struct vi_info *vi; 3626 struct port_info *pi; 3627 struct adapter *sc; 3628 int rc; 3629 3630 vi = device_get_softc(dev); 3631 pi = vi->pi; 3632 sc = pi->adapter; 3633 3634 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 3635 if (rc) 3636 return (rc); 3637 rc = alloc_extra_vi(sc, pi, vi); 3638 end_synchronized_op(sc, 0); 3639 if (rc) 3640 return (rc); 3641 3642 cxgbe_vi_attach(dev, vi); 3643 3644 return (0); 3645 } 3646 3647 static int 3648 vcxgbe_detach(device_t dev) 3649 { 3650 struct vi_info *vi; 3651 struct adapter *sc; 3652 3653 vi = device_get_softc(dev); 3654 sc = vi->adapter; 3655 3656 begin_vi_detach(sc, vi); 3657 cxgbe_vi_detach(vi); 3658 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3659 end_vi_detach(sc, vi); 3660 3661 return (0); 3662 } 3663 3664 static struct callout fatal_callout; 3665 static struct taskqueue *reset_tq; 3666 3667 static void 3668 delayed_panic(void *arg) 3669 { 3670 struct adapter *sc = arg; 3671 3672 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 3673 } 3674 3675 static void 3676 fatal_error_task(void *arg, int pending) 3677 { 3678 struct adapter *sc = arg; 3679 int rc; 3680 3681 if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) { 3682 dump_cim_regs(sc); 3683 dump_cimla(sc); 3684 dump_devlog(sc); 3685 } 3686 3687 if (t4_reset_on_fatal_err) { 3688 CH_ALERT(sc, "resetting adapter after fatal error.\n"); 3689 rc = reset_adapter(sc); 3690 if (rc == 0 && t4_panic_on_fatal_err) { 3691 CH_ALERT(sc, "reset was successful, " 3692 "system will NOT panic.\n"); 3693 return; 3694 } 3695 } 3696 3697 if (t4_panic_on_fatal_err) { 3698 CH_ALERT(sc, "panicking on fatal error (after 30s).\n"); 3699 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 3700 } 3701 } 3702 3703 void 3704 t4_fatal_err(struct adapter *sc, bool fw_error) 3705 { 3706 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 3707 3708 stop_adapter(sc); 3709 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR))) 3710 return; 3711 if (fw_error) { 3712 /* 3713 * We are here because of a firmware error/timeout and not 3714 * because of a hardware interrupt. It is possible (although 3715 * not very likely) that an error interrupt was also raised but 3716 * this thread ran first and inhibited t4_intr_err. We walk the 3717 * main INT_CAUSE registers here to make sure we haven't missed 3718 * anything interesting. 3719 */ 3720 t4_slow_intr_handler(sc, verbose); 3721 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 3722 } 3723 t4_report_fw_error(sc); 3724 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n", 3725 device_get_nameunit(sc->dev), fw_error); 3726 taskqueue_enqueue(reset_tq, &sc->fatal_error_task); 3727 } 3728 3729 void 3730 t4_add_adapter(struct adapter *sc) 3731 { 3732 sx_xlock(&t4_list_lock); 3733 SLIST_INSERT_HEAD(&t4_list, sc, link); 3734 sx_xunlock(&t4_list_lock); 3735 } 3736 3737 int 3738 t4_map_bars_0_and_4(struct adapter *sc) 3739 { 3740 sc->regs_rid = PCIR_BAR(0); 3741 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3742 &sc->regs_rid, RF_ACTIVE); 3743 if (sc->regs_res == NULL) { 3744 device_printf(sc->dev, "cannot map registers.\n"); 3745 return (ENXIO); 3746 } 3747 sc->bt = rman_get_bustag(sc->regs_res); 3748 sc->bh = rman_get_bushandle(sc->regs_res); 3749 sc->mmio_len = rman_get_size(sc->regs_res); 3750 setbit(&sc->doorbells, DOORBELL_KDB); 3751 3752 sc->msix_rid = PCIR_BAR(4); 3753 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3754 &sc->msix_rid, RF_ACTIVE); 3755 if (sc->msix_res == NULL) { 3756 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 3757 return (ENXIO); 3758 } 3759 3760 return (0); 3761 } 3762 3763 int 3764 t4_map_bar_2(struct adapter *sc) 3765 { 3766 3767 /* 3768 * T4: only iWARP driver uses the userspace doorbells. There is no need 3769 * to map it if RDMA is disabled. 3770 */ 3771 if (is_t4(sc) && sc->rdmacaps == 0) 3772 return (0); 3773 3774 sc->udbs_rid = PCIR_BAR(2); 3775 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3776 &sc->udbs_rid, RF_ACTIVE); 3777 if (sc->udbs_res == NULL) { 3778 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 3779 return (ENXIO); 3780 } 3781 sc->udbs_base = rman_get_virtual(sc->udbs_res); 3782 3783 if (chip_id(sc) >= CHELSIO_T5) { 3784 setbit(&sc->doorbells, DOORBELL_UDB); 3785 #if defined(__i386__) || defined(__amd64__) 3786 if (t5_write_combine) { 3787 int rc, mode; 3788 3789 /* 3790 * Enable write combining on BAR2. This is the 3791 * userspace doorbell BAR and is split into 128B 3792 * (UDBS_SEG_SIZE) doorbell regions, each associated 3793 * with an egress queue. The first 64B has the doorbell 3794 * and the second 64B can be used to submit a tx work 3795 * request with an implicit doorbell. 3796 */ 3797 3798 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 3799 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 3800 if (rc == 0) { 3801 clrbit(&sc->doorbells, DOORBELL_UDB); 3802 setbit(&sc->doorbells, DOORBELL_WCWR); 3803 setbit(&sc->doorbells, DOORBELL_UDBWC); 3804 } else { 3805 device_printf(sc->dev, 3806 "couldn't enable write combining: %d\n", 3807 rc); 3808 } 3809 3810 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 3811 t4_write_reg(sc, A_SGE_STAT_CFG, 3812 V_STATSOURCE_T5(7) | mode); 3813 } 3814 #endif 3815 } 3816 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 3817 3818 return (0); 3819 } 3820 3821 int 3822 t4_adj_doorbells(struct adapter *sc) 3823 { 3824 if ((sc->doorbells & t4_doorbells_allowed) != 0) { 3825 sc->doorbells &= t4_doorbells_allowed; 3826 return (0); 3827 } 3828 CH_ERR(sc, "No usable doorbell (available = 0x%x, allowed = 0x%x).\n", 3829 sc->doorbells, t4_doorbells_allowed); 3830 return (EINVAL); 3831 } 3832 3833 struct memwin_init { 3834 uint32_t base; 3835 uint32_t aperture; 3836 }; 3837 3838 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 3839 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3840 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3841 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 3842 }; 3843 3844 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 3845 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3846 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3847 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 3848 }; 3849 3850 static void 3851 setup_memwin(struct adapter *sc) 3852 { 3853 const struct memwin_init *mw_init; 3854 struct memwin *mw; 3855 int i; 3856 uint32_t bar0; 3857 3858 if (is_t4(sc)) { 3859 /* 3860 * Read low 32b of bar0 indirectly via the hardware backdoor 3861 * mechanism. Works from within PCI passthrough environments 3862 * too, where rman_get_start() can return a different value. We 3863 * need to program the T4 memory window decoders with the actual 3864 * addresses that will be coming across the PCIe link. 3865 */ 3866 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 3867 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 3868 3869 mw_init = &t4_memwin[0]; 3870 } else { 3871 /* T5+ use the relative offset inside the PCIe BAR */ 3872 bar0 = 0; 3873 3874 mw_init = &t5_memwin[0]; 3875 } 3876 3877 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 3878 if (!rw_initialized(&mw->mw_lock)) { 3879 rw_init(&mw->mw_lock, "memory window access"); 3880 mw->mw_base = mw_init->base; 3881 mw->mw_aperture = mw_init->aperture; 3882 mw->mw_curpos = 0; 3883 } 3884 t4_write_reg(sc, 3885 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 3886 (mw->mw_base + bar0) | V_BIR(0) | 3887 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 3888 rw_wlock(&mw->mw_lock); 3889 position_memwin(sc, i, mw->mw_curpos); 3890 rw_wunlock(&mw->mw_lock); 3891 } 3892 3893 /* flush */ 3894 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 3895 } 3896 3897 /* 3898 * Positions the memory window at the given address in the card's address space. 3899 * There are some alignment requirements and the actual position may be at an 3900 * address prior to the requested address. mw->mw_curpos always has the actual 3901 * position of the window. 3902 */ 3903 static void 3904 position_memwin(struct adapter *sc, int idx, uint32_t addr) 3905 { 3906 struct memwin *mw; 3907 uint32_t pf; 3908 uint32_t reg; 3909 3910 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3911 mw = &sc->memwin[idx]; 3912 rw_assert(&mw->mw_lock, RA_WLOCKED); 3913 3914 if (is_t4(sc)) { 3915 pf = 0; 3916 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 3917 } else { 3918 pf = V_PFNUM(sc->pf); 3919 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 3920 } 3921 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 3922 t4_write_reg(sc, reg, mw->mw_curpos | pf); 3923 t4_read_reg(sc, reg); /* flush */ 3924 } 3925 3926 int 3927 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 3928 int len, int rw) 3929 { 3930 struct memwin *mw; 3931 uint32_t mw_end, v; 3932 3933 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3934 3935 /* Memory can only be accessed in naturally aligned 4 byte units */ 3936 if (addr & 3 || len & 3 || len <= 0) 3937 return (EINVAL); 3938 3939 mw = &sc->memwin[idx]; 3940 while (len > 0) { 3941 rw_rlock(&mw->mw_lock); 3942 mw_end = mw->mw_curpos + mw->mw_aperture; 3943 if (addr >= mw_end || addr < mw->mw_curpos) { 3944 /* Will need to reposition the window */ 3945 if (!rw_try_upgrade(&mw->mw_lock)) { 3946 rw_runlock(&mw->mw_lock); 3947 rw_wlock(&mw->mw_lock); 3948 } 3949 rw_assert(&mw->mw_lock, RA_WLOCKED); 3950 position_memwin(sc, idx, addr); 3951 rw_downgrade(&mw->mw_lock); 3952 mw_end = mw->mw_curpos + mw->mw_aperture; 3953 } 3954 rw_assert(&mw->mw_lock, RA_RLOCKED); 3955 while (addr < mw_end && len > 0) { 3956 if (rw == 0) { 3957 v = t4_read_reg(sc, mw->mw_base + addr - 3958 mw->mw_curpos); 3959 *val++ = le32toh(v); 3960 } else { 3961 v = *val++; 3962 t4_write_reg(sc, mw->mw_base + addr - 3963 mw->mw_curpos, htole32(v)); 3964 } 3965 addr += 4; 3966 len -= 4; 3967 } 3968 rw_runlock(&mw->mw_lock); 3969 } 3970 3971 return (0); 3972 } 3973 3974 CTASSERT(M_TID_COOKIE == M_COOKIE); 3975 CTASSERT(MAX_ATIDS <= (M_TID_TID + 1)); 3976 3977 static void 3978 t4_init_atid_table(struct adapter *sc) 3979 { 3980 struct tid_info *t; 3981 int i; 3982 3983 t = &sc->tids; 3984 if (t->natids == 0) 3985 return; 3986 3987 MPASS(t->atid_tab == NULL); 3988 3989 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 3990 M_ZERO | M_WAITOK); 3991 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 3992 t->afree = t->atid_tab; 3993 t->atids_in_use = 0; 3994 t->atid_alloc_stopped = false; 3995 for (i = 1; i < t->natids; i++) 3996 t->atid_tab[i - 1].next = &t->atid_tab[i]; 3997 t->atid_tab[t->natids - 1].next = NULL; 3998 } 3999 4000 static void 4001 t4_free_atid_table(struct adapter *sc) 4002 { 4003 struct tid_info *t; 4004 4005 t = &sc->tids; 4006 4007 KASSERT(t->atids_in_use == 0, 4008 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 4009 4010 if (mtx_initialized(&t->atid_lock)) 4011 mtx_destroy(&t->atid_lock); 4012 free(t->atid_tab, M_CXGBE); 4013 t->atid_tab = NULL; 4014 } 4015 4016 static void 4017 stop_atid_allocator(struct adapter *sc) 4018 { 4019 struct tid_info *t = &sc->tids; 4020 4021 mtx_lock(&t->atid_lock); 4022 t->atid_alloc_stopped = true; 4023 mtx_unlock(&t->atid_lock); 4024 } 4025 4026 static void 4027 restart_atid_allocator(struct adapter *sc) 4028 { 4029 struct tid_info *t = &sc->tids; 4030 4031 mtx_lock(&t->atid_lock); 4032 KASSERT(t->atids_in_use == 0, 4033 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 4034 t->atid_alloc_stopped = false; 4035 mtx_unlock(&t->atid_lock); 4036 } 4037 4038 int 4039 alloc_atid(struct adapter *sc, void *ctx) 4040 { 4041 struct tid_info *t = &sc->tids; 4042 int atid = -1; 4043 4044 mtx_lock(&t->atid_lock); 4045 if (t->afree && !t->atid_alloc_stopped) { 4046 union aopen_entry *p = t->afree; 4047 4048 atid = p - t->atid_tab; 4049 MPASS(atid <= M_TID_TID); 4050 t->afree = p->next; 4051 p->data = ctx; 4052 t->atids_in_use++; 4053 } 4054 mtx_unlock(&t->atid_lock); 4055 return (atid); 4056 } 4057 4058 void * 4059 lookup_atid(struct adapter *sc, int atid) 4060 { 4061 struct tid_info *t = &sc->tids; 4062 4063 return (t->atid_tab[atid].data); 4064 } 4065 4066 void 4067 free_atid(struct adapter *sc, int atid) 4068 { 4069 struct tid_info *t = &sc->tids; 4070 union aopen_entry *p = &t->atid_tab[atid]; 4071 4072 mtx_lock(&t->atid_lock); 4073 p->next = t->afree; 4074 t->afree = p; 4075 t->atids_in_use--; 4076 mtx_unlock(&t->atid_lock); 4077 } 4078 4079 static void 4080 queue_tid_release(struct adapter *sc, int tid) 4081 { 4082 4083 CXGBE_UNIMPLEMENTED("deferred tid release"); 4084 } 4085 4086 void 4087 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 4088 { 4089 struct wrqe *wr; 4090 struct cpl_tid_release *req; 4091 4092 wr = alloc_wrqe(sizeof(*req), ctrlq); 4093 if (wr == NULL) { 4094 queue_tid_release(sc, tid); /* defer */ 4095 return; 4096 } 4097 req = wrtod(wr); 4098 4099 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 4100 4101 t4_wrq_tx(sc, wr); 4102 } 4103 4104 static int 4105 t4_range_cmp(const void *a, const void *b) 4106 { 4107 return ((const struct t4_range *)a)->start - 4108 ((const struct t4_range *)b)->start; 4109 } 4110 4111 /* 4112 * Verify that the memory range specified by the addr/len pair is valid within 4113 * the card's address space. 4114 */ 4115 static int 4116 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 4117 { 4118 struct t4_range mem_ranges[4], *r, *next; 4119 uint32_t em, addr_len; 4120 int i, n, remaining; 4121 4122 /* Memory can only be accessed in naturally aligned 4 byte units */ 4123 if (addr & 3 || len & 3 || len == 0) 4124 return (EINVAL); 4125 4126 /* Enabled memories */ 4127 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4128 4129 r = &mem_ranges[0]; 4130 n = 0; 4131 bzero(r, sizeof(mem_ranges)); 4132 if (em & F_EDRAM0_ENABLE) { 4133 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4134 r->size = G_EDRAM0_SIZE(addr_len) << 20; 4135 if (r->size > 0) { 4136 r->start = G_EDRAM0_BASE(addr_len) << 20; 4137 if (addr >= r->start && 4138 addr + len <= r->start + r->size) 4139 return (0); 4140 r++; 4141 n++; 4142 } 4143 } 4144 if (em & F_EDRAM1_ENABLE) { 4145 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4146 r->size = G_EDRAM1_SIZE(addr_len) << 20; 4147 if (r->size > 0) { 4148 r->start = G_EDRAM1_BASE(addr_len) << 20; 4149 if (addr >= r->start && 4150 addr + len <= r->start + r->size) 4151 return (0); 4152 r++; 4153 n++; 4154 } 4155 } 4156 if (em & F_EXT_MEM_ENABLE) { 4157 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4158 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 4159 if (r->size > 0) { 4160 r->start = G_EXT_MEM_BASE(addr_len) << 20; 4161 if (addr >= r->start && 4162 addr + len <= r->start + r->size) 4163 return (0); 4164 r++; 4165 n++; 4166 } 4167 } 4168 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 4169 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4170 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 4171 if (r->size > 0) { 4172 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 4173 if (addr >= r->start && 4174 addr + len <= r->start + r->size) 4175 return (0); 4176 r++; 4177 n++; 4178 } 4179 } 4180 MPASS(n <= nitems(mem_ranges)); 4181 4182 if (n > 1) { 4183 /* Sort and merge the ranges. */ 4184 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 4185 4186 /* Start from index 0 and examine the next n - 1 entries. */ 4187 r = &mem_ranges[0]; 4188 for (remaining = n - 1; remaining > 0; remaining--, r++) { 4189 4190 MPASS(r->size > 0); /* r is a valid entry. */ 4191 next = r + 1; 4192 MPASS(next->size > 0); /* and so is the next one. */ 4193 4194 while (r->start + r->size >= next->start) { 4195 /* Merge the next one into the current entry. */ 4196 r->size = max(r->start + r->size, 4197 next->start + next->size) - r->start; 4198 n--; /* One fewer entry in total. */ 4199 if (--remaining == 0) 4200 goto done; /* short circuit */ 4201 next++; 4202 } 4203 if (next != r + 1) { 4204 /* 4205 * Some entries were merged into r and next 4206 * points to the first valid entry that couldn't 4207 * be merged. 4208 */ 4209 MPASS(next->size > 0); /* must be valid */ 4210 memcpy(r + 1, next, remaining * sizeof(*r)); 4211 #ifdef INVARIANTS 4212 /* 4213 * This so that the foo->size assertion in the 4214 * next iteration of the loop do the right 4215 * thing for entries that were pulled up and are 4216 * no longer valid. 4217 */ 4218 MPASS(n < nitems(mem_ranges)); 4219 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 4220 sizeof(struct t4_range)); 4221 #endif 4222 } 4223 } 4224 done: 4225 /* Done merging the ranges. */ 4226 MPASS(n > 0); 4227 r = &mem_ranges[0]; 4228 for (i = 0; i < n; i++, r++) { 4229 if (addr >= r->start && 4230 addr + len <= r->start + r->size) 4231 return (0); 4232 } 4233 } 4234 4235 return (EFAULT); 4236 } 4237 4238 static int 4239 fwmtype_to_hwmtype(int mtype) 4240 { 4241 4242 switch (mtype) { 4243 case FW_MEMTYPE_EDC0: 4244 return (MEM_EDC0); 4245 case FW_MEMTYPE_EDC1: 4246 return (MEM_EDC1); 4247 case FW_MEMTYPE_EXTMEM: 4248 return (MEM_MC0); 4249 case FW_MEMTYPE_EXTMEM1: 4250 return (MEM_MC1); 4251 default: 4252 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 4253 } 4254 } 4255 4256 /* 4257 * Verify that the memory range specified by the memtype/offset/len pair is 4258 * valid and lies entirely within the memtype specified. The global address of 4259 * the start of the range is returned in addr. 4260 */ 4261 static int 4262 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 4263 uint32_t *addr) 4264 { 4265 uint32_t em, addr_len, maddr; 4266 4267 /* Memory can only be accessed in naturally aligned 4 byte units */ 4268 if (off & 3 || len & 3 || len == 0) 4269 return (EINVAL); 4270 4271 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4272 switch (fwmtype_to_hwmtype(mtype)) { 4273 case MEM_EDC0: 4274 if (!(em & F_EDRAM0_ENABLE)) 4275 return (EINVAL); 4276 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4277 maddr = G_EDRAM0_BASE(addr_len) << 20; 4278 break; 4279 case MEM_EDC1: 4280 if (!(em & F_EDRAM1_ENABLE)) 4281 return (EINVAL); 4282 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4283 maddr = G_EDRAM1_BASE(addr_len) << 20; 4284 break; 4285 case MEM_MC: 4286 if (!(em & F_EXT_MEM_ENABLE)) 4287 return (EINVAL); 4288 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4289 maddr = G_EXT_MEM_BASE(addr_len) << 20; 4290 break; 4291 case MEM_MC1: 4292 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 4293 return (EINVAL); 4294 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4295 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 4296 break; 4297 default: 4298 return (EINVAL); 4299 } 4300 4301 *addr = maddr + off; /* global address */ 4302 return (validate_mem_range(sc, *addr, len)); 4303 } 4304 4305 static int 4306 fixup_devlog_params(struct adapter *sc) 4307 { 4308 struct devlog_params *dparams = &sc->params.devlog; 4309 int rc; 4310 4311 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 4312 dparams->size, &dparams->addr); 4313 4314 return (rc); 4315 } 4316 4317 static void 4318 update_nirq(struct intrs_and_queues *iaq, int nports) 4319 { 4320 4321 iaq->nirq = T4_EXTRA_INTR; 4322 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq); 4323 iaq->nirq += nports * iaq->nofldrxq; 4324 iaq->nirq += nports * (iaq->num_vis - 1) * 4325 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 4326 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 4327 } 4328 4329 /* 4330 * Adjust requirements to fit the number of interrupts available. 4331 */ 4332 static void 4333 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 4334 int navail) 4335 { 4336 int old_nirq; 4337 const int nports = sc->params.nports; 4338 4339 MPASS(nports > 0); 4340 MPASS(navail > 0); 4341 4342 bzero(iaq, sizeof(*iaq)); 4343 iaq->intr_type = itype; 4344 iaq->num_vis = t4_num_vis; 4345 iaq->ntxq = t4_ntxq; 4346 iaq->ntxq_vi = t4_ntxq_vi; 4347 iaq->nrxq = t4_nrxq; 4348 iaq->nrxq_vi = t4_nrxq_vi; 4349 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4350 if (is_offload(sc) || is_ethoffload(sc)) { 4351 iaq->nofldtxq = t4_nofldtxq; 4352 iaq->nofldtxq_vi = t4_nofldtxq_vi; 4353 } 4354 #endif 4355 #ifdef TCP_OFFLOAD 4356 if (is_offload(sc)) { 4357 iaq->nofldrxq = t4_nofldrxq; 4358 iaq->nofldrxq_vi = t4_nofldrxq_vi; 4359 } 4360 #endif 4361 #ifdef DEV_NETMAP 4362 if (t4_native_netmap & NN_MAIN_VI) { 4363 iaq->nnmtxq = t4_nnmtxq; 4364 iaq->nnmrxq = t4_nnmrxq; 4365 } 4366 if (t4_native_netmap & NN_EXTRA_VI) { 4367 iaq->nnmtxq_vi = t4_nnmtxq_vi; 4368 iaq->nnmrxq_vi = t4_nnmrxq_vi; 4369 } 4370 #endif 4371 4372 update_nirq(iaq, nports); 4373 if (iaq->nirq <= navail && 4374 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4375 /* 4376 * This is the normal case -- there are enough interrupts for 4377 * everything. 4378 */ 4379 goto done; 4380 } 4381 4382 /* 4383 * If extra VIs have been configured try reducing their count and see if 4384 * that works. 4385 */ 4386 while (iaq->num_vis > 1) { 4387 iaq->num_vis--; 4388 update_nirq(iaq, nports); 4389 if (iaq->nirq <= navail && 4390 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4391 device_printf(sc->dev, "virtual interfaces per port " 4392 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 4393 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 4394 "itype %d, navail %u, nirq %d.\n", 4395 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 4396 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 4397 itype, navail, iaq->nirq); 4398 goto done; 4399 } 4400 } 4401 4402 /* 4403 * Extra VIs will not be created. Log a message if they were requested. 4404 */ 4405 MPASS(iaq->num_vis == 1); 4406 iaq->ntxq_vi = iaq->nrxq_vi = 0; 4407 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 4408 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 4409 if (iaq->num_vis != t4_num_vis) { 4410 device_printf(sc->dev, "extra virtual interfaces disabled. " 4411 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 4412 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 4413 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 4414 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 4415 } 4416 4417 /* 4418 * Keep reducing the number of NIC rx queues to the next lower power of 4419 * 2 (for even RSS distribution) and halving the TOE rx queues and see 4420 * if that works. 4421 */ 4422 do { 4423 if (iaq->nrxq > 1) { 4424 iaq->nrxq = rounddown_pow_of_two(iaq->nrxq - 1); 4425 if (iaq->nnmrxq > iaq->nrxq) 4426 iaq->nnmrxq = iaq->nrxq; 4427 } 4428 if (iaq->nofldrxq > 1) 4429 iaq->nofldrxq >>= 1; 4430 4431 old_nirq = iaq->nirq; 4432 update_nirq(iaq, nports); 4433 if (iaq->nirq <= navail && 4434 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4435 device_printf(sc->dev, "running with reduced number of " 4436 "rx queues because of shortage of interrupts. " 4437 "nrxq=%u, nofldrxq=%u. " 4438 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 4439 iaq->nofldrxq, itype, navail, iaq->nirq); 4440 goto done; 4441 } 4442 } while (old_nirq != iaq->nirq); 4443 4444 /* One interrupt for everything. Ugh. */ 4445 device_printf(sc->dev, "running with minimal number of queues. " 4446 "itype %d, navail %u.\n", itype, navail); 4447 iaq->nirq = 1; 4448 iaq->nrxq = 1; 4449 iaq->ntxq = 1; 4450 if (iaq->nofldrxq > 0) { 4451 iaq->nofldrxq = 1; 4452 iaq->nofldtxq = 1; 4453 } 4454 iaq->nnmtxq = 0; 4455 iaq->nnmrxq = 0; 4456 done: 4457 MPASS(iaq->num_vis > 0); 4458 if (iaq->num_vis > 1) { 4459 MPASS(iaq->nrxq_vi > 0); 4460 MPASS(iaq->ntxq_vi > 0); 4461 } 4462 MPASS(iaq->nirq > 0); 4463 MPASS(iaq->nrxq > 0); 4464 MPASS(iaq->ntxq > 0); 4465 if (itype == INTR_MSI) { 4466 MPASS(powerof2(iaq->nirq)); 4467 } 4468 } 4469 4470 static int 4471 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 4472 { 4473 int rc, itype, navail, nalloc; 4474 4475 for (itype = INTR_MSIX; itype; itype >>= 1) { 4476 4477 if ((itype & t4_intr_types) == 0) 4478 continue; /* not allowed */ 4479 4480 if (itype == INTR_MSIX) 4481 navail = pci_msix_count(sc->dev); 4482 else if (itype == INTR_MSI) 4483 navail = pci_msi_count(sc->dev); 4484 else 4485 navail = 1; 4486 restart: 4487 if (navail == 0) 4488 continue; 4489 4490 calculate_iaq(sc, iaq, itype, navail); 4491 nalloc = iaq->nirq; 4492 rc = 0; 4493 if (itype == INTR_MSIX) 4494 rc = pci_alloc_msix(sc->dev, &nalloc); 4495 else if (itype == INTR_MSI) 4496 rc = pci_alloc_msi(sc->dev, &nalloc); 4497 4498 if (rc == 0 && nalloc > 0) { 4499 if (nalloc == iaq->nirq) 4500 return (0); 4501 4502 /* 4503 * Didn't get the number requested. Use whatever number 4504 * the kernel is willing to allocate. 4505 */ 4506 device_printf(sc->dev, "fewer vectors than requested, " 4507 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 4508 itype, iaq->nirq, nalloc); 4509 pci_release_msi(sc->dev); 4510 navail = nalloc; 4511 goto restart; 4512 } 4513 4514 device_printf(sc->dev, 4515 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 4516 itype, rc, iaq->nirq, nalloc); 4517 } 4518 4519 device_printf(sc->dev, 4520 "failed to find a usable interrupt type. " 4521 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 4522 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 4523 4524 return (ENXIO); 4525 } 4526 4527 #define FW_VERSION(chip) ( \ 4528 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 4529 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 4530 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 4531 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 4532 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 4533 4534 /* Just enough of fw_hdr to cover all version info. */ 4535 struct fw_h { 4536 __u8 ver; 4537 __u8 chip; 4538 __be16 len512; 4539 __be32 fw_ver; 4540 __be32 tp_microcode_ver; 4541 __u8 intfver_nic; 4542 __u8 intfver_vnic; 4543 __u8 intfver_ofld; 4544 __u8 intfver_ri; 4545 __u8 intfver_iscsipdu; 4546 __u8 intfver_iscsi; 4547 __u8 intfver_fcoepdu; 4548 __u8 intfver_fcoe; 4549 }; 4550 /* Spot check a couple of fields. */ 4551 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 4552 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 4553 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 4554 4555 struct fw_info { 4556 uint8_t chip; 4557 char *kld_name; 4558 char *fw_mod_name; 4559 struct fw_h fw_h; 4560 } fw_info[] = { 4561 { 4562 .chip = CHELSIO_T4, 4563 .kld_name = "t4fw_cfg", 4564 .fw_mod_name = "t4fw", 4565 .fw_h = { 4566 .chip = FW_HDR_CHIP_T4, 4567 .fw_ver = htobe32(FW_VERSION(T4)), 4568 .intfver_nic = FW_INTFVER(T4, NIC), 4569 .intfver_vnic = FW_INTFVER(T4, VNIC), 4570 .intfver_ofld = FW_INTFVER(T4, OFLD), 4571 .intfver_ri = FW_INTFVER(T4, RI), 4572 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 4573 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4574 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 4575 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4576 }, 4577 }, { 4578 .chip = CHELSIO_T5, 4579 .kld_name = "t5fw_cfg", 4580 .fw_mod_name = "t5fw", 4581 .fw_h = { 4582 .chip = FW_HDR_CHIP_T5, 4583 .fw_ver = htobe32(FW_VERSION(T5)), 4584 .intfver_nic = FW_INTFVER(T5, NIC), 4585 .intfver_vnic = FW_INTFVER(T5, VNIC), 4586 .intfver_ofld = FW_INTFVER(T5, OFLD), 4587 .intfver_ri = FW_INTFVER(T5, RI), 4588 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 4589 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4590 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 4591 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4592 }, 4593 }, { 4594 .chip = CHELSIO_T6, 4595 .kld_name = "t6fw_cfg", 4596 .fw_mod_name = "t6fw", 4597 .fw_h = { 4598 .chip = FW_HDR_CHIP_T6, 4599 .fw_ver = htobe32(FW_VERSION(T6)), 4600 .intfver_nic = FW_INTFVER(T6, NIC), 4601 .intfver_vnic = FW_INTFVER(T6, VNIC), 4602 .intfver_ofld = FW_INTFVER(T6, OFLD), 4603 .intfver_ri = FW_INTFVER(T6, RI), 4604 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4605 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4606 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4607 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4608 }, 4609 } 4610 }; 4611 4612 static struct fw_info * 4613 find_fw_info(int chip) 4614 { 4615 int i; 4616 4617 for (i = 0; i < nitems(fw_info); i++) { 4618 if (fw_info[i].chip == chip) 4619 return (&fw_info[i]); 4620 } 4621 return (NULL); 4622 } 4623 4624 /* 4625 * Is the given firmware API compatible with the one the driver was compiled 4626 * with? 4627 */ 4628 static int 4629 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 4630 { 4631 4632 /* short circuit if it's the exact same firmware version */ 4633 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 4634 return (1); 4635 4636 /* 4637 * XXX: Is this too conservative? Perhaps I should limit this to the 4638 * features that are supported in the driver. 4639 */ 4640 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 4641 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 4642 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 4643 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 4644 return (1); 4645 #undef SAME_INTF 4646 4647 return (0); 4648 } 4649 4650 static int 4651 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 4652 const struct firmware **fw) 4653 { 4654 struct fw_info *fw_info; 4655 4656 *dcfg = NULL; 4657 if (fw != NULL) 4658 *fw = NULL; 4659 4660 fw_info = find_fw_info(chip_id(sc)); 4661 if (fw_info == NULL) { 4662 device_printf(sc->dev, 4663 "unable to look up firmware information for chip %d.\n", 4664 chip_id(sc)); 4665 return (EINVAL); 4666 } 4667 4668 *dcfg = firmware_get(fw_info->kld_name); 4669 if (*dcfg != NULL) { 4670 if (fw != NULL) 4671 *fw = firmware_get(fw_info->fw_mod_name); 4672 return (0); 4673 } 4674 4675 return (ENOENT); 4676 } 4677 4678 static void 4679 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 4680 const struct firmware *fw) 4681 { 4682 4683 if (fw != NULL) 4684 firmware_put(fw, FIRMWARE_UNLOAD); 4685 if (dcfg != NULL) 4686 firmware_put(dcfg, FIRMWARE_UNLOAD); 4687 } 4688 4689 /* 4690 * Return values: 4691 * 0 means no firmware install attempted. 4692 * ERESTART means a firmware install was attempted and was successful. 4693 * +ve errno means a firmware install was attempted but failed. 4694 */ 4695 static int 4696 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 4697 const struct fw_h *drv_fw, const char *reason, int *already) 4698 { 4699 const struct firmware *cfg, *fw; 4700 const uint32_t c = be32toh(card_fw->fw_ver); 4701 uint32_t d, k; 4702 int rc, fw_install; 4703 struct fw_h bundled_fw; 4704 bool load_attempted; 4705 4706 cfg = fw = NULL; 4707 load_attempted = false; 4708 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 4709 4710 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 4711 if (t4_fw_install < 0) { 4712 rc = load_fw_module(sc, &cfg, &fw); 4713 if (rc != 0 || fw == NULL) { 4714 device_printf(sc->dev, 4715 "failed to load firmware module: %d. cfg %p, fw %p;" 4716 " will use compiled-in firmware version for" 4717 "hw.cxgbe.fw_install checks.\n", 4718 rc, cfg, fw); 4719 } else { 4720 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 4721 } 4722 load_attempted = true; 4723 } 4724 d = be32toh(bundled_fw.fw_ver); 4725 4726 if (reason != NULL) 4727 goto install; 4728 4729 if ((sc->flags & FW_OK) == 0) { 4730 4731 if (c == 0xffffffff) { 4732 reason = "missing"; 4733 goto install; 4734 } 4735 4736 rc = 0; 4737 goto done; 4738 } 4739 4740 if (!fw_compatible(card_fw, &bundled_fw)) { 4741 reason = "incompatible or unusable"; 4742 goto install; 4743 } 4744 4745 if (d > c) { 4746 reason = "older than the version bundled with this driver"; 4747 goto install; 4748 } 4749 4750 if (fw_install == 2 && d != c) { 4751 reason = "different than the version bundled with this driver"; 4752 goto install; 4753 } 4754 4755 /* No reason to do anything to the firmware already on the card. */ 4756 rc = 0; 4757 goto done; 4758 4759 install: 4760 rc = 0; 4761 if ((*already)++) 4762 goto done; 4763 4764 if (fw_install == 0) { 4765 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4766 "but the driver is prohibited from installing a firmware " 4767 "on the card.\n", 4768 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4769 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4770 4771 goto done; 4772 } 4773 4774 /* 4775 * We'll attempt to install a firmware. Load the module first (if it 4776 * hasn't been loaded already). 4777 */ 4778 if (!load_attempted) { 4779 rc = load_fw_module(sc, &cfg, &fw); 4780 if (rc != 0 || fw == NULL) { 4781 device_printf(sc->dev, 4782 "failed to load firmware module: %d. cfg %p, fw %p\n", 4783 rc, cfg, fw); 4784 /* carry on */ 4785 } 4786 } 4787 if (fw == NULL) { 4788 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4789 "but the driver cannot take corrective action because it " 4790 "is unable to load the firmware module.\n", 4791 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4792 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4793 rc = sc->flags & FW_OK ? 0 : ENOENT; 4794 goto done; 4795 } 4796 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 4797 if (k != d) { 4798 MPASS(t4_fw_install > 0); 4799 device_printf(sc->dev, 4800 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 4801 "expecting (%u.%u.%u.%u) and will not be used.\n", 4802 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 4803 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 4804 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4805 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4806 rc = sc->flags & FW_OK ? 0 : EINVAL; 4807 goto done; 4808 } 4809 4810 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4811 "installing firmware %u.%u.%u.%u on card.\n", 4812 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4813 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 4814 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4815 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4816 4817 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 4818 if (rc != 0) { 4819 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 4820 } else { 4821 /* Installed successfully, update the cached header too. */ 4822 rc = ERESTART; 4823 memcpy(card_fw, fw->data, sizeof(*card_fw)); 4824 } 4825 done: 4826 unload_fw_module(sc, cfg, fw); 4827 4828 return (rc); 4829 } 4830 4831 /* 4832 * Establish contact with the firmware and attempt to become the master driver. 4833 * 4834 * A firmware will be installed to the card if needed (if the driver is allowed 4835 * to do so). 4836 */ 4837 static int 4838 contact_firmware(struct adapter *sc) 4839 { 4840 int rc, already = 0; 4841 enum dev_state state; 4842 struct fw_info *fw_info; 4843 struct fw_hdr *card_fw; /* fw on the card */ 4844 const struct fw_h *drv_fw; 4845 4846 fw_info = find_fw_info(chip_id(sc)); 4847 if (fw_info == NULL) { 4848 device_printf(sc->dev, 4849 "unable to look up firmware information for chip %d.\n", 4850 chip_id(sc)); 4851 return (EINVAL); 4852 } 4853 drv_fw = &fw_info->fw_h; 4854 4855 /* Read the header of the firmware on the card */ 4856 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 4857 restart: 4858 rc = -t4_get_fw_hdr(sc, card_fw); 4859 if (rc != 0) { 4860 device_printf(sc->dev, 4861 "unable to read firmware header from card's flash: %d\n", 4862 rc); 4863 goto done; 4864 } 4865 4866 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 4867 &already); 4868 if (rc == ERESTART) 4869 goto restart; 4870 if (rc != 0) 4871 goto done; 4872 4873 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 4874 if (rc < 0 || state == DEV_STATE_ERR) { 4875 rc = -rc; 4876 device_printf(sc->dev, 4877 "failed to connect to the firmware: %d, %d. " 4878 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4879 #if 0 4880 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4881 "not responding properly to HELLO", &already) == ERESTART) 4882 goto restart; 4883 #endif 4884 goto done; 4885 } 4886 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 4887 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 4888 4889 if (rc == sc->pf) { 4890 sc->flags |= MASTER_PF; 4891 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4892 NULL, &already); 4893 if (rc == ERESTART) 4894 rc = 0; 4895 else if (rc != 0) 4896 goto done; 4897 } else if (state == DEV_STATE_UNINIT) { 4898 /* 4899 * We didn't get to be the master so we definitely won't be 4900 * configuring the chip. It's a bug if someone else hasn't 4901 * configured it already. 4902 */ 4903 device_printf(sc->dev, "couldn't be master(%d), " 4904 "device not already initialized either(%d). " 4905 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4906 rc = EPROTO; 4907 goto done; 4908 } else { 4909 /* 4910 * Some other PF is the master and has configured the chip. 4911 * This is allowed but untested. 4912 */ 4913 device_printf(sc->dev, "PF%d is master, device state %d. " 4914 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4915 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 4916 sc->cfcsum = 0; 4917 rc = 0; 4918 } 4919 done: 4920 if (rc != 0 && sc->flags & FW_OK) { 4921 t4_fw_bye(sc, sc->mbox); 4922 sc->flags &= ~FW_OK; 4923 } 4924 free(card_fw, M_CXGBE); 4925 return (rc); 4926 } 4927 4928 static int 4929 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 4930 uint32_t mtype, uint32_t moff) 4931 { 4932 struct fw_info *fw_info; 4933 const struct firmware *dcfg, *rcfg = NULL; 4934 const uint32_t *cfdata; 4935 uint32_t cflen, addr; 4936 int rc; 4937 4938 load_fw_module(sc, &dcfg, NULL); 4939 4940 /* Card specific interpretation of "default". */ 4941 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4942 if (pci_get_device(sc->dev) == 0x440a) 4943 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 4944 if (is_fpga(sc)) 4945 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 4946 } 4947 4948 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4949 if (dcfg == NULL) { 4950 device_printf(sc->dev, 4951 "KLD with default config is not available.\n"); 4952 rc = ENOENT; 4953 goto done; 4954 } 4955 cfdata = dcfg->data; 4956 cflen = dcfg->datasize & ~3; 4957 } else { 4958 char s[32]; 4959 4960 fw_info = find_fw_info(chip_id(sc)); 4961 if (fw_info == NULL) { 4962 device_printf(sc->dev, 4963 "unable to look up firmware information for chip %d.\n", 4964 chip_id(sc)); 4965 rc = EINVAL; 4966 goto done; 4967 } 4968 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 4969 4970 rcfg = firmware_get(s); 4971 if (rcfg == NULL) { 4972 device_printf(sc->dev, 4973 "unable to load module \"%s\" for configuration " 4974 "profile \"%s\".\n", s, cfg_file); 4975 rc = ENOENT; 4976 goto done; 4977 } 4978 cfdata = rcfg->data; 4979 cflen = rcfg->datasize & ~3; 4980 } 4981 4982 if (cflen > FLASH_CFG_MAX_SIZE) { 4983 device_printf(sc->dev, 4984 "config file too long (%d, max allowed is %d).\n", 4985 cflen, FLASH_CFG_MAX_SIZE); 4986 rc = EINVAL; 4987 goto done; 4988 } 4989 4990 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 4991 if (rc != 0) { 4992 device_printf(sc->dev, 4993 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 4994 __func__, mtype, moff, cflen, rc); 4995 rc = EINVAL; 4996 goto done; 4997 } 4998 write_via_memwin(sc, 2, addr, cfdata, cflen); 4999 done: 5000 if (rcfg != NULL) 5001 firmware_put(rcfg, FIRMWARE_UNLOAD); 5002 unload_fw_module(sc, dcfg, NULL); 5003 return (rc); 5004 } 5005 5006 struct caps_allowed { 5007 uint16_t nbmcaps; 5008 uint16_t linkcaps; 5009 uint16_t switchcaps; 5010 uint16_t niccaps; 5011 uint16_t toecaps; 5012 uint16_t rdmacaps; 5013 uint16_t cryptocaps; 5014 uint16_t iscsicaps; 5015 uint16_t fcoecaps; 5016 }; 5017 5018 #define FW_PARAM_DEV(param) \ 5019 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 5020 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 5021 #define FW_PARAM_PFVF(param) \ 5022 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 5023 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 5024 5025 /* 5026 * Provide a configuration profile to the firmware and have it initialize the 5027 * chip accordingly. This may involve uploading a configuration file to the 5028 * card. 5029 */ 5030 static int 5031 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 5032 const struct caps_allowed *caps_allowed) 5033 { 5034 int rc; 5035 struct fw_caps_config_cmd caps; 5036 uint32_t mtype, moff, finicsum, cfcsum, param, val; 5037 5038 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 5039 if (rc != 0) { 5040 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 5041 return (rc); 5042 } 5043 5044 bzero(&caps, sizeof(caps)); 5045 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5046 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5047 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 5048 mtype = 0; 5049 moff = 0; 5050 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5051 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 5052 mtype = FW_MEMTYPE_FLASH; 5053 moff = t4_flash_cfg_addr(sc); 5054 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 5055 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 5056 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 5057 FW_LEN16(caps)); 5058 } else { 5059 /* 5060 * Ask the firmware where it wants us to upload the config file. 5061 */ 5062 param = FW_PARAM_DEV(CF); 5063 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5064 if (rc != 0) { 5065 /* No support for config file? Shouldn't happen. */ 5066 device_printf(sc->dev, 5067 "failed to query config file location: %d.\n", rc); 5068 goto done; 5069 } 5070 mtype = G_FW_PARAMS_PARAM_Y(val); 5071 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 5072 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 5073 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 5074 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 5075 FW_LEN16(caps)); 5076 5077 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 5078 if (rc != 0) { 5079 device_printf(sc->dev, 5080 "failed to upload config file to card: %d.\n", rc); 5081 goto done; 5082 } 5083 } 5084 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5085 if (rc != 0) { 5086 device_printf(sc->dev, "failed to pre-process config file: %d " 5087 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 5088 goto done; 5089 } 5090 5091 finicsum = be32toh(caps.finicsum); 5092 cfcsum = be32toh(caps.cfcsum); /* actual */ 5093 if (finicsum != cfcsum) { 5094 device_printf(sc->dev, 5095 "WARNING: config file checksum mismatch: %08x %08x\n", 5096 finicsum, cfcsum); 5097 } 5098 sc->cfcsum = cfcsum; 5099 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 5100 5101 /* 5102 * Let the firmware know what features will (not) be used so it can tune 5103 * things accordingly. 5104 */ 5105 #define LIMIT_CAPS(x) do { \ 5106 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 5107 } while (0) 5108 LIMIT_CAPS(nbm); 5109 LIMIT_CAPS(link); 5110 LIMIT_CAPS(switch); 5111 LIMIT_CAPS(nic); 5112 LIMIT_CAPS(toe); 5113 LIMIT_CAPS(rdma); 5114 LIMIT_CAPS(crypto); 5115 LIMIT_CAPS(iscsi); 5116 LIMIT_CAPS(fcoe); 5117 #undef LIMIT_CAPS 5118 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 5119 /* 5120 * TOE and hashfilters are mutually exclusive. It is a config 5121 * file or firmware bug if both are reported as available. Try 5122 * to cope with the situation in non-debug builds by disabling 5123 * TOE. 5124 */ 5125 MPASS(caps.toecaps == 0); 5126 5127 caps.toecaps = 0; 5128 caps.rdmacaps = 0; 5129 caps.iscsicaps = 0; 5130 } 5131 5132 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5133 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5134 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5135 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 5136 if (rc != 0) { 5137 device_printf(sc->dev, 5138 "failed to process config file: %d.\n", rc); 5139 goto done; 5140 } 5141 5142 t4_tweak_chip_settings(sc); 5143 set_params__pre_init(sc); 5144 5145 /* get basic stuff going */ 5146 rc = -t4_fw_initialize(sc, sc->mbox); 5147 if (rc != 0) { 5148 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 5149 goto done; 5150 } 5151 done: 5152 return (rc); 5153 } 5154 5155 /* 5156 * Partition chip resources for use between various PFs, VFs, etc. 5157 */ 5158 static int 5159 partition_resources(struct adapter *sc) 5160 { 5161 char cfg_file[sizeof(t4_cfg_file)]; 5162 struct caps_allowed caps_allowed; 5163 int rc; 5164 bool fallback; 5165 5166 /* Only the master driver gets to configure the chip resources. */ 5167 MPASS(sc->flags & MASTER_PF); 5168 5169 #define COPY_CAPS(x) do { \ 5170 caps_allowed.x##caps = t4_##x##caps_allowed; \ 5171 } while (0) 5172 bzero(&caps_allowed, sizeof(caps_allowed)); 5173 COPY_CAPS(nbm); 5174 COPY_CAPS(link); 5175 COPY_CAPS(switch); 5176 COPY_CAPS(nic); 5177 COPY_CAPS(toe); 5178 COPY_CAPS(rdma); 5179 COPY_CAPS(crypto); 5180 COPY_CAPS(iscsi); 5181 COPY_CAPS(fcoe); 5182 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 5183 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 5184 retry: 5185 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 5186 if (rc != 0 && fallback) { 5187 dump_devlog(sc); 5188 device_printf(sc->dev, 5189 "failed (%d) to configure card with \"%s\" profile, " 5190 "will fall back to a basic configuration and retry.\n", 5191 rc, cfg_file); 5192 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 5193 bzero(&caps_allowed, sizeof(caps_allowed)); 5194 COPY_CAPS(switch); 5195 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 5196 fallback = false; 5197 goto retry; 5198 } 5199 #undef COPY_CAPS 5200 return (rc); 5201 } 5202 5203 /* 5204 * Retrieve parameters that are needed (or nice to have) very early. 5205 */ 5206 static int 5207 get_params__pre_init(struct adapter *sc) 5208 { 5209 int rc; 5210 uint32_t param[2], val[2]; 5211 5212 t4_get_version_info(sc); 5213 5214 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 5215 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 5216 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 5217 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 5218 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 5219 5220 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 5221 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 5222 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 5223 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 5224 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 5225 5226 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 5227 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 5228 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 5229 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 5230 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 5231 5232 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 5233 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 5234 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 5235 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 5236 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 5237 5238 param[0] = FW_PARAM_DEV(PORTVEC); 5239 param[1] = FW_PARAM_DEV(CCLK); 5240 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5241 if (rc != 0) { 5242 device_printf(sc->dev, 5243 "failed to query parameters (pre_init): %d.\n", rc); 5244 return (rc); 5245 } 5246 5247 sc->params.portvec = val[0]; 5248 sc->params.nports = bitcount32(val[0]); 5249 sc->params.vpd.cclk = val[1]; 5250 5251 /* Read device log parameters. */ 5252 rc = -t4_init_devlog_params(sc, 1); 5253 if (rc == 0) 5254 fixup_devlog_params(sc); 5255 else { 5256 device_printf(sc->dev, 5257 "failed to get devlog parameters: %d.\n", rc); 5258 rc = 0; /* devlog isn't critical for device operation */ 5259 } 5260 5261 return (rc); 5262 } 5263 5264 /* 5265 * Any params that need to be set before FW_INITIALIZE. 5266 */ 5267 static int 5268 set_params__pre_init(struct adapter *sc) 5269 { 5270 int rc = 0; 5271 uint32_t param, val; 5272 5273 if (chip_id(sc) >= CHELSIO_T6) { 5274 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 5275 val = 1; 5276 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5277 /* firmwares < 1.20.1.0 do not have this param. */ 5278 if (rc == FW_EINVAL && 5279 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) { 5280 rc = 0; 5281 } 5282 if (rc != 0) { 5283 device_printf(sc->dev, 5284 "failed to enable high priority filters :%d.\n", 5285 rc); 5286 } 5287 5288 param = FW_PARAM_DEV(PPOD_EDRAM); 5289 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5290 if (rc == 0 && val == 1) { 5291 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, 5292 &val); 5293 if (rc != 0) { 5294 device_printf(sc->dev, 5295 "failed to set PPOD_EDRAM: %d.\n", rc); 5296 } 5297 } 5298 } 5299 5300 /* Enable opaque VIIDs with firmwares that support it. */ 5301 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 5302 val = 1; 5303 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5304 if (rc == 0 && val == 1) 5305 sc->params.viid_smt_extn_support = true; 5306 else 5307 sc->params.viid_smt_extn_support = false; 5308 5309 return (rc); 5310 } 5311 5312 /* 5313 * Retrieve various parameters that are of interest to the driver. The device 5314 * has been initialized by the firmware at this point. 5315 */ 5316 static int 5317 get_params__post_init(struct adapter *sc) 5318 { 5319 int rc; 5320 uint32_t param[7], val[7]; 5321 struct fw_caps_config_cmd caps; 5322 5323 param[0] = FW_PARAM_PFVF(IQFLINT_START); 5324 param[1] = FW_PARAM_PFVF(EQ_START); 5325 param[2] = FW_PARAM_PFVF(FILTER_START); 5326 param[3] = FW_PARAM_PFVF(FILTER_END); 5327 param[4] = FW_PARAM_PFVF(L2T_START); 5328 param[5] = FW_PARAM_PFVF(L2T_END); 5329 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5330 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5331 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 5332 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 5333 if (rc != 0) { 5334 device_printf(sc->dev, 5335 "failed to query parameters (post_init): %d.\n", rc); 5336 return (rc); 5337 } 5338 5339 sc->sge.iq_start = val[0]; 5340 sc->sge.eq_start = val[1]; 5341 if ((int)val[3] > (int)val[2]) { 5342 sc->tids.ftid_base = val[2]; 5343 sc->tids.ftid_end = val[3]; 5344 sc->tids.nftids = val[3] - val[2] + 1; 5345 } 5346 sc->vres.l2t.start = val[4]; 5347 sc->vres.l2t.size = val[5] - val[4] + 1; 5348 /* val[5] is the last hwidx and it must not collide with F_SYNC_WR */ 5349 if (sc->vres.l2t.size > 0) 5350 MPASS(fls(val[5]) <= S_SYNC_WR); 5351 sc->params.core_vdd = val[6]; 5352 5353 param[0] = FW_PARAM_PFVF(IQFLINT_END); 5354 param[1] = FW_PARAM_PFVF(EQ_END); 5355 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5356 if (rc != 0) { 5357 device_printf(sc->dev, 5358 "failed to query parameters (post_init2): %d.\n", rc); 5359 return (rc); 5360 } 5361 MPASS((int)val[0] >= sc->sge.iq_start); 5362 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1; 5363 MPASS((int)val[1] >= sc->sge.eq_start); 5364 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1; 5365 5366 if (chip_id(sc) >= CHELSIO_T6) { 5367 5368 sc->tids.tid_base = t4_read_reg(sc, 5369 A_LE_DB_ACTIVE_TABLE_START_INDEX); 5370 5371 param[0] = FW_PARAM_PFVF(HPFILTER_START); 5372 param[1] = FW_PARAM_PFVF(HPFILTER_END); 5373 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5374 if (rc != 0) { 5375 device_printf(sc->dev, 5376 "failed to query hpfilter parameters: %d.\n", rc); 5377 return (rc); 5378 } 5379 if ((int)val[1] > (int)val[0]) { 5380 sc->tids.hpftid_base = val[0]; 5381 sc->tids.hpftid_end = val[1]; 5382 sc->tids.nhpftids = val[1] - val[0] + 1; 5383 5384 /* 5385 * These should go off if the layout changes and the 5386 * driver needs to catch up. 5387 */ 5388 MPASS(sc->tids.hpftid_base == 0); 5389 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 5390 } 5391 5392 param[0] = FW_PARAM_PFVF(RAWF_START); 5393 param[1] = FW_PARAM_PFVF(RAWF_END); 5394 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5395 if (rc != 0) { 5396 device_printf(sc->dev, 5397 "failed to query rawf parameters: %d.\n", rc); 5398 return (rc); 5399 } 5400 if ((int)val[1] > (int)val[0]) { 5401 sc->rawf_base = val[0]; 5402 sc->nrawf = val[1] - val[0] + 1; 5403 } 5404 } 5405 5406 /* 5407 * The parameters that follow may not be available on all firmwares. We 5408 * query them individually rather than in a compound query because old 5409 * firmwares fail the entire query if an unknown parameter is queried. 5410 */ 5411 5412 /* 5413 * MPS buffer group configuration. 5414 */ 5415 param[0] = FW_PARAM_DEV(MPSBGMAP); 5416 val[0] = 0; 5417 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5418 if (rc == 0) 5419 sc->params.mps_bg_map = val[0]; 5420 else 5421 sc->params.mps_bg_map = UINT32_MAX; /* Not a legal value. */ 5422 5423 param[0] = FW_PARAM_DEV(TPCHMAP); 5424 val[0] = 0; 5425 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5426 if (rc == 0) 5427 sc->params.tp_ch_map = val[0]; 5428 else 5429 sc->params.tp_ch_map = UINT32_MAX; /* Not a legal value. */ 5430 5431 /* 5432 * Determine whether the firmware supports the filter2 work request. 5433 */ 5434 param[0] = FW_PARAM_DEV(FILTER2_WR); 5435 val[0] = 0; 5436 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5437 if (rc == 0) 5438 sc->params.filter2_wr_support = val[0] != 0; 5439 else 5440 sc->params.filter2_wr_support = 0; 5441 5442 /* 5443 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 5444 */ 5445 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 5446 val[0] = 0; 5447 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5448 if (rc == 0) 5449 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 5450 else 5451 sc->params.ulptx_memwrite_dsgl = false; 5452 5453 /* FW_RI_FR_NSMR_TPTE_WR support */ 5454 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 5455 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5456 if (rc == 0) 5457 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0; 5458 else 5459 sc->params.fr_nsmr_tpte_wr_support = false; 5460 5461 /* Support for 512 SGL entries per FR MR. */ 5462 param[0] = FW_PARAM_DEV(DEV_512SGL_MR); 5463 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5464 if (rc == 0) 5465 sc->params.dev_512sgl_mr = val[0] != 0; 5466 else 5467 sc->params.dev_512sgl_mr = false; 5468 5469 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 5470 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5471 if (rc == 0) 5472 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0]; 5473 else 5474 sc->params.max_pkts_per_eth_tx_pkts_wr = 15; 5475 5476 param[0] = FW_PARAM_DEV(NUM_TM_CLASS); 5477 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5478 if (rc == 0) { 5479 MPASS(val[0] > 0 && val[0] < 256); /* nsched_cls is 8b */ 5480 sc->params.nsched_cls = val[0]; 5481 } else 5482 sc->params.nsched_cls = sc->chip_params->nsched_cls; 5483 5484 /* get capabilites */ 5485 bzero(&caps, sizeof(caps)); 5486 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5487 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5488 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5489 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5490 if (rc != 0) { 5491 device_printf(sc->dev, 5492 "failed to get card capabilities: %d.\n", rc); 5493 return (rc); 5494 } 5495 5496 #define READ_CAPS(x) do { \ 5497 sc->x = htobe16(caps.x); \ 5498 } while (0) 5499 READ_CAPS(nbmcaps); 5500 READ_CAPS(linkcaps); 5501 READ_CAPS(switchcaps); 5502 READ_CAPS(niccaps); 5503 READ_CAPS(toecaps); 5504 READ_CAPS(rdmacaps); 5505 READ_CAPS(cryptocaps); 5506 READ_CAPS(iscsicaps); 5507 READ_CAPS(fcoecaps); 5508 5509 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 5510 MPASS(chip_id(sc) > CHELSIO_T4); 5511 MPASS(sc->toecaps == 0); 5512 sc->toecaps = 0; 5513 5514 param[0] = FW_PARAM_DEV(NTID); 5515 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5516 if (rc != 0) { 5517 device_printf(sc->dev, 5518 "failed to query HASHFILTER parameters: %d.\n", rc); 5519 return (rc); 5520 } 5521 sc->tids.ntids = val[0]; 5522 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5523 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5524 sc->tids.ntids -= sc->tids.nhpftids; 5525 } 5526 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5527 sc->params.hash_filter = 1; 5528 } 5529 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 5530 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 5531 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 5532 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5533 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 5534 if (rc != 0) { 5535 device_printf(sc->dev, 5536 "failed to query NIC parameters: %d.\n", rc); 5537 return (rc); 5538 } 5539 if ((int)val[1] > (int)val[0]) { 5540 sc->tids.etid_base = val[0]; 5541 sc->tids.etid_end = val[1]; 5542 sc->tids.netids = val[1] - val[0] + 1; 5543 sc->params.eo_wr_cred = val[2]; 5544 sc->params.ethoffload = 1; 5545 } 5546 } 5547 if (sc->toecaps) { 5548 /* query offload-related parameters */ 5549 param[0] = FW_PARAM_DEV(NTID); 5550 param[1] = FW_PARAM_PFVF(SERVER_START); 5551 param[2] = FW_PARAM_PFVF(SERVER_END); 5552 param[3] = FW_PARAM_PFVF(TDDP_START); 5553 param[4] = FW_PARAM_PFVF(TDDP_END); 5554 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5555 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5556 if (rc != 0) { 5557 device_printf(sc->dev, 5558 "failed to query TOE parameters: %d.\n", rc); 5559 return (rc); 5560 } 5561 sc->tids.ntids = val[0]; 5562 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5563 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5564 sc->tids.ntids -= sc->tids.nhpftids; 5565 } 5566 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5567 if ((int)val[2] > (int)val[1]) { 5568 sc->tids.stid_base = val[1]; 5569 sc->tids.nstids = val[2] - val[1] + 1; 5570 } 5571 sc->vres.ddp.start = val[3]; 5572 sc->vres.ddp.size = val[4] - val[3] + 1; 5573 sc->params.ofldq_wr_cred = val[5]; 5574 sc->params.offload = 1; 5575 } else { 5576 /* 5577 * The firmware attempts memfree TOE configuration for -SO cards 5578 * and will report toecaps=0 if it runs out of resources (this 5579 * depends on the config file). It may not report 0 for other 5580 * capabilities dependent on the TOE in this case. Set them to 5581 * 0 here so that the driver doesn't bother tracking resources 5582 * that will never be used. 5583 */ 5584 sc->iscsicaps = 0; 5585 sc->rdmacaps = 0; 5586 } 5587 if (sc->rdmacaps) { 5588 param[0] = FW_PARAM_PFVF(STAG_START); 5589 param[1] = FW_PARAM_PFVF(STAG_END); 5590 param[2] = FW_PARAM_PFVF(RQ_START); 5591 param[3] = FW_PARAM_PFVF(RQ_END); 5592 param[4] = FW_PARAM_PFVF(PBL_START); 5593 param[5] = FW_PARAM_PFVF(PBL_END); 5594 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5595 if (rc != 0) { 5596 device_printf(sc->dev, 5597 "failed to query RDMA parameters(1): %d.\n", rc); 5598 return (rc); 5599 } 5600 sc->vres.stag.start = val[0]; 5601 sc->vres.stag.size = val[1] - val[0] + 1; 5602 sc->vres.rq.start = val[2]; 5603 sc->vres.rq.size = val[3] - val[2] + 1; 5604 sc->vres.pbl.start = val[4]; 5605 sc->vres.pbl.size = val[5] - val[4] + 1; 5606 5607 param[0] = FW_PARAM_PFVF(SQRQ_START); 5608 param[1] = FW_PARAM_PFVF(SQRQ_END); 5609 param[2] = FW_PARAM_PFVF(CQ_START); 5610 param[3] = FW_PARAM_PFVF(CQ_END); 5611 param[4] = FW_PARAM_PFVF(OCQ_START); 5612 param[5] = FW_PARAM_PFVF(OCQ_END); 5613 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5614 if (rc != 0) { 5615 device_printf(sc->dev, 5616 "failed to query RDMA parameters(2): %d.\n", rc); 5617 return (rc); 5618 } 5619 sc->vres.qp.start = val[0]; 5620 sc->vres.qp.size = val[1] - val[0] + 1; 5621 sc->vres.cq.start = val[2]; 5622 sc->vres.cq.size = val[3] - val[2] + 1; 5623 sc->vres.ocq.start = val[4]; 5624 sc->vres.ocq.size = val[5] - val[4] + 1; 5625 5626 param[0] = FW_PARAM_PFVF(SRQ_START); 5627 param[1] = FW_PARAM_PFVF(SRQ_END); 5628 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 5629 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 5630 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 5631 if (rc != 0) { 5632 device_printf(sc->dev, 5633 "failed to query RDMA parameters(3): %d.\n", rc); 5634 return (rc); 5635 } 5636 sc->vres.srq.start = val[0]; 5637 sc->vres.srq.size = val[1] - val[0] + 1; 5638 sc->params.max_ordird_qp = val[2]; 5639 sc->params.max_ird_adapter = val[3]; 5640 } 5641 if (sc->iscsicaps) { 5642 param[0] = FW_PARAM_PFVF(ISCSI_START); 5643 param[1] = FW_PARAM_PFVF(ISCSI_END); 5644 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5645 if (rc != 0) { 5646 device_printf(sc->dev, 5647 "failed to query iSCSI parameters: %d.\n", rc); 5648 return (rc); 5649 } 5650 sc->vres.iscsi.start = val[0]; 5651 sc->vres.iscsi.size = val[1] - val[0] + 1; 5652 } 5653 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 5654 param[0] = FW_PARAM_PFVF(TLS_START); 5655 param[1] = FW_PARAM_PFVF(TLS_END); 5656 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5657 if (rc != 0) { 5658 device_printf(sc->dev, 5659 "failed to query TLS parameters: %d.\n", rc); 5660 return (rc); 5661 } 5662 sc->vres.key.start = val[0]; 5663 sc->vres.key.size = val[1] - val[0] + 1; 5664 } 5665 5666 /* 5667 * We've got the params we wanted to query directly from the firmware. 5668 * Grab some others via other means. 5669 */ 5670 t4_init_sge_params(sc); 5671 t4_init_tp_params(sc); 5672 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 5673 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 5674 5675 rc = t4_verify_chip_settings(sc); 5676 if (rc != 0) 5677 return (rc); 5678 t4_init_rx_buf_info(sc); 5679 5680 return (rc); 5681 } 5682 5683 #ifdef KERN_TLS 5684 static void 5685 ktls_tick(void *arg) 5686 { 5687 struct adapter *sc; 5688 uint32_t tstamp; 5689 5690 sc = arg; 5691 tstamp = tcp_ts_getticks(); 5692 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1); 5693 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31); 5694 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK); 5695 } 5696 5697 static int 5698 t6_config_kern_tls(struct adapter *sc, bool enable) 5699 { 5700 int rc; 5701 uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5702 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) | 5703 V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) | 5704 V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE); 5705 5706 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, ¶m); 5707 if (rc != 0) { 5708 CH_ERR(sc, "failed to %s NIC TLS: %d\n", 5709 enable ? "enable" : "disable", rc); 5710 return (rc); 5711 } 5712 5713 if (enable) { 5714 sc->flags |= KERN_TLS_ON; 5715 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc, 5716 C_HARDCLOCK); 5717 } else { 5718 sc->flags &= ~KERN_TLS_ON; 5719 callout_stop(&sc->ktls_tick); 5720 } 5721 5722 return (rc); 5723 } 5724 #endif 5725 5726 static int 5727 set_params__post_init(struct adapter *sc) 5728 { 5729 uint32_t mask, param, val; 5730 #ifdef TCP_OFFLOAD 5731 int i, v, shift; 5732 #endif 5733 5734 /* ask for encapsulated CPLs */ 5735 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 5736 val = 1; 5737 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5738 5739 /* Enable 32b port caps if the firmware supports it. */ 5740 param = FW_PARAM_PFVF(PORT_CAPS32); 5741 val = 1; 5742 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 5743 sc->params.port_caps32 = 1; 5744 5745 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 5746 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 5747 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 5748 V_MASKFILTER(val - 1)); 5749 5750 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER | 5751 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN | 5752 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5753 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM; 5754 val = 0; 5755 if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) { 5756 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE, 5757 F_ATTACKFILTERENABLE); 5758 val |= F_DROPERRORATTACK; 5759 } 5760 if (t4_drop_ip_fragments != 0) { 5761 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP, 5762 F_FRAGMENTDROP); 5763 val |= F_DROPERRORFRAG; 5764 } 5765 if (t4_drop_pkts_with_l2_errors != 0) 5766 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN; 5767 if (t4_drop_pkts_with_l3_errors != 0) { 5768 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN | 5769 F_DROPERRORCSUMIP; 5770 } 5771 if (t4_drop_pkts_with_l4_errors != 0) { 5772 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5773 F_DROPERRORTCPOPT | F_DROPERRORCSUM; 5774 } 5775 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val); 5776 5777 #ifdef TCP_OFFLOAD 5778 /* 5779 * Override the TOE timers with user provided tunables. This is not the 5780 * recommended way to change the timers (the firmware config file is) so 5781 * these tunables are not documented. 5782 * 5783 * All the timer tunables are in microseconds. 5784 */ 5785 if (t4_toe_keepalive_idle != 0) { 5786 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 5787 v &= M_KEEPALIVEIDLE; 5788 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 5789 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 5790 } 5791 if (t4_toe_keepalive_interval != 0) { 5792 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 5793 v &= M_KEEPALIVEINTVL; 5794 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 5795 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 5796 } 5797 if (t4_toe_keepalive_count != 0) { 5798 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 5799 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5800 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 5801 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 5802 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 5803 } 5804 if (t4_toe_rexmt_min != 0) { 5805 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 5806 v &= M_RXTMIN; 5807 t4_set_reg_field(sc, A_TP_RXT_MIN, 5808 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 5809 } 5810 if (t4_toe_rexmt_max != 0) { 5811 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 5812 v &= M_RXTMAX; 5813 t4_set_reg_field(sc, A_TP_RXT_MAX, 5814 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 5815 } 5816 if (t4_toe_rexmt_count != 0) { 5817 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 5818 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5819 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 5820 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 5821 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 5822 } 5823 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 5824 if (t4_toe_rexmt_backoff[i] != -1) { 5825 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 5826 shift = (i & 3) << 3; 5827 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 5828 M_TIMERBACKOFFINDEX0 << shift, v << shift); 5829 } 5830 } 5831 #endif 5832 5833 /* 5834 * Limit TOE connections to 2 reassembly "islands". This is 5835 * required to permit migrating TOE connections to either 5836 * ULP_MODE_TCPDDP or UPL_MODE_TLS. 5837 */ 5838 t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, V_PASSMODE(M_PASSMODE), 5839 V_PASSMODE(2)); 5840 5841 #ifdef KERN_TLS 5842 if (is_ktls(sc)) { 5843 sc->tlst.inline_keys = t4_tls_inline_keys; 5844 sc->tlst.combo_wrs = t4_tls_combo_wrs; 5845 if (t4_kern_tls != 0 && is_t6(sc)) 5846 t6_config_kern_tls(sc, true); 5847 } 5848 #endif 5849 return (0); 5850 } 5851 5852 #undef FW_PARAM_PFVF 5853 #undef FW_PARAM_DEV 5854 5855 static void 5856 t4_set_desc(struct adapter *sc) 5857 { 5858 struct adapter_params *p = &sc->params; 5859 5860 device_set_descf(sc->dev, "Chelsio %s", p->vpd.id); 5861 } 5862 5863 static inline void 5864 ifmedia_add4(struct ifmedia *ifm, int m) 5865 { 5866 5867 ifmedia_add(ifm, m, 0, NULL); 5868 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 5869 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 5870 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 5871 } 5872 5873 /* 5874 * This is the selected media, which is not quite the same as the active media. 5875 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 5876 * and active are not the same, and "media: Ethernet selected" otherwise. 5877 */ 5878 static void 5879 set_current_media(struct port_info *pi) 5880 { 5881 struct link_config *lc; 5882 struct ifmedia *ifm; 5883 int mword; 5884 u_int speed; 5885 5886 PORT_LOCK_ASSERT_OWNED(pi); 5887 5888 /* Leave current media alone if it's already set to IFM_NONE. */ 5889 ifm = &pi->media; 5890 if (ifm->ifm_cur != NULL && 5891 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 5892 return; 5893 5894 lc = &pi->link_cfg; 5895 if (lc->requested_aneg != AUTONEG_DISABLE && 5896 lc->pcaps & FW_PORT_CAP32_ANEG) { 5897 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 5898 return; 5899 } 5900 mword = IFM_ETHER | IFM_FDX; 5901 if (lc->requested_fc & PAUSE_TX) 5902 mword |= IFM_ETH_TXPAUSE; 5903 if (lc->requested_fc & PAUSE_RX) 5904 mword |= IFM_ETH_RXPAUSE; 5905 if (lc->requested_speed == 0) 5906 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 5907 else 5908 speed = lc->requested_speed; 5909 mword |= port_mword(pi, speed_to_fwcap(speed)); 5910 ifmedia_set(ifm, mword); 5911 } 5912 5913 /* 5914 * Returns true if the ifmedia list for the port cannot change. 5915 */ 5916 static bool 5917 fixed_ifmedia(struct port_info *pi) 5918 { 5919 5920 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 5921 pi->port_type == FW_PORT_TYPE_BT_XFI || 5922 pi->port_type == FW_PORT_TYPE_BT_XAUI || 5923 pi->port_type == FW_PORT_TYPE_KX4 || 5924 pi->port_type == FW_PORT_TYPE_KX || 5925 pi->port_type == FW_PORT_TYPE_KR || 5926 pi->port_type == FW_PORT_TYPE_BP_AP || 5927 pi->port_type == FW_PORT_TYPE_BP4_AP || 5928 pi->port_type == FW_PORT_TYPE_BP40_BA || 5929 pi->port_type == FW_PORT_TYPE_KR4_100G || 5930 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 5931 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 5932 } 5933 5934 static void 5935 build_medialist(struct port_info *pi) 5936 { 5937 uint32_t ss, speed; 5938 int unknown, mword, bit; 5939 struct link_config *lc; 5940 struct ifmedia *ifm; 5941 5942 PORT_LOCK_ASSERT_OWNED(pi); 5943 5944 if (pi->flags & FIXED_IFMEDIA) 5945 return; 5946 5947 /* 5948 * Rebuild the ifmedia list. 5949 */ 5950 ifm = &pi->media; 5951 ifmedia_removeall(ifm); 5952 lc = &pi->link_cfg; 5953 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */ 5954 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 5955 MPASS(ss != 0); 5956 no_media: 5957 MPASS(LIST_EMPTY(&ifm->ifm_list)); 5958 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 5959 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 5960 return; 5961 } 5962 5963 unknown = 0; 5964 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 5965 speed = 1 << bit; 5966 MPASS(speed & M_FW_PORT_CAP32_SPEED); 5967 if (ss & speed) { 5968 mword = port_mword(pi, speed); 5969 if (mword == IFM_NONE) { 5970 goto no_media; 5971 } else if (mword == IFM_UNKNOWN) 5972 unknown++; 5973 else 5974 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 5975 } 5976 } 5977 if (unknown > 0) /* Add one unknown for all unknown media types. */ 5978 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 5979 if (lc->pcaps & FW_PORT_CAP32_ANEG) 5980 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 5981 5982 set_current_media(pi); 5983 } 5984 5985 /* 5986 * Initialize the requested fields in the link config based on driver tunables. 5987 */ 5988 static void 5989 init_link_config(struct port_info *pi) 5990 { 5991 struct link_config *lc = &pi->link_cfg; 5992 5993 PORT_LOCK_ASSERT_OWNED(pi); 5994 5995 lc->requested_caps = 0; 5996 lc->requested_speed = 0; 5997 5998 if (t4_autoneg == 0) 5999 lc->requested_aneg = AUTONEG_DISABLE; 6000 else if (t4_autoneg == 1) 6001 lc->requested_aneg = AUTONEG_ENABLE; 6002 else 6003 lc->requested_aneg = AUTONEG_AUTO; 6004 6005 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 6006 PAUSE_AUTONEG); 6007 6008 if (t4_fec & FEC_AUTO) 6009 lc->requested_fec = FEC_AUTO; 6010 else if (t4_fec == 0) 6011 lc->requested_fec = FEC_NONE; 6012 else { 6013 /* -1 is handled by the FEC_AUTO block above and not here. */ 6014 lc->requested_fec = t4_fec & 6015 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE); 6016 if (lc->requested_fec == 0) 6017 lc->requested_fec = FEC_AUTO; 6018 } 6019 if (t4_force_fec < 0) 6020 lc->force_fec = -1; 6021 else if (t4_force_fec > 0) 6022 lc->force_fec = 1; 6023 else 6024 lc->force_fec = 0; 6025 } 6026 6027 /* 6028 * Makes sure that all requested settings comply with what's supported by the 6029 * port. Returns the number of settings that were invalid and had to be fixed. 6030 */ 6031 static int 6032 fixup_link_config(struct port_info *pi) 6033 { 6034 int n = 0; 6035 struct link_config *lc = &pi->link_cfg; 6036 uint32_t fwspeed; 6037 6038 PORT_LOCK_ASSERT_OWNED(pi); 6039 6040 /* Speed (when not autonegotiating) */ 6041 if (lc->requested_speed != 0) { 6042 fwspeed = speed_to_fwcap(lc->requested_speed); 6043 if ((fwspeed & lc->pcaps) == 0) { 6044 n++; 6045 lc->requested_speed = 0; 6046 } 6047 } 6048 6049 /* Link autonegotiation */ 6050 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 6051 lc->requested_aneg == AUTONEG_DISABLE || 6052 lc->requested_aneg == AUTONEG_AUTO); 6053 if (lc->requested_aneg == AUTONEG_ENABLE && 6054 !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 6055 n++; 6056 lc->requested_aneg = AUTONEG_AUTO; 6057 } 6058 6059 /* Flow control */ 6060 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 6061 if (lc->requested_fc & PAUSE_TX && 6062 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) { 6063 n++; 6064 lc->requested_fc &= ~PAUSE_TX; 6065 } 6066 if (lc->requested_fc & PAUSE_RX && 6067 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) { 6068 n++; 6069 lc->requested_fc &= ~PAUSE_RX; 6070 } 6071 if (!(lc->requested_fc & PAUSE_AUTONEG) && 6072 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) { 6073 n++; 6074 lc->requested_fc |= PAUSE_AUTONEG; 6075 } 6076 6077 /* FEC */ 6078 if ((lc->requested_fec & FEC_RS && 6079 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) || 6080 (lc->requested_fec & FEC_BASER_RS && 6081 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) { 6082 n++; 6083 lc->requested_fec = FEC_AUTO; 6084 } 6085 6086 return (n); 6087 } 6088 6089 /* 6090 * Apply the requested L1 settings, which are expected to be valid, to the 6091 * hardware. 6092 */ 6093 static int 6094 apply_link_config(struct port_info *pi) 6095 { 6096 struct adapter *sc = pi->adapter; 6097 struct link_config *lc = &pi->link_cfg; 6098 int rc; 6099 6100 #ifdef INVARIANTS 6101 ASSERT_SYNCHRONIZED_OP(sc); 6102 PORT_LOCK_ASSERT_OWNED(pi); 6103 6104 if (lc->requested_aneg == AUTONEG_ENABLE) 6105 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG); 6106 if (!(lc->requested_fc & PAUSE_AUTONEG)) 6107 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE); 6108 if (lc->requested_fc & PAUSE_TX) 6109 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX); 6110 if (lc->requested_fc & PAUSE_RX) 6111 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX); 6112 if (lc->requested_fec & FEC_RS) 6113 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS); 6114 if (lc->requested_fec & FEC_BASER_RS) 6115 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS); 6116 #endif 6117 if (!(sc->flags & IS_VF)) { 6118 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6119 if (rc != 0) { 6120 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 6121 return (rc); 6122 } 6123 } 6124 6125 /* 6126 * An L1_CFG will almost always result in a link-change event if the 6127 * link is up, and the driver will refresh the actual fec/fc/etc. when 6128 * the notification is processed. If the link is down then the actual 6129 * settings are meaningless. 6130 * 6131 * This takes care of the case where a change in the L1 settings may not 6132 * result in a notification. 6133 */ 6134 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 6135 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 6136 6137 return (0); 6138 } 6139 6140 #define FW_MAC_EXACT_CHUNK 7 6141 struct mcaddr_ctx { 6142 if_t ifp; 6143 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 6144 uint64_t hash; 6145 int i; 6146 int del; 6147 int rc; 6148 }; 6149 6150 static u_int 6151 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 6152 { 6153 struct mcaddr_ctx *ctx = arg; 6154 struct vi_info *vi = if_getsoftc(ctx->ifp); 6155 struct port_info *pi = vi->pi; 6156 struct adapter *sc = pi->adapter; 6157 6158 if (ctx->rc < 0) 6159 return (0); 6160 6161 ctx->mcaddr[ctx->i] = LLADDR(sdl); 6162 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i])); 6163 ctx->i++; 6164 6165 if (ctx->i == FW_MAC_EXACT_CHUNK) { 6166 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del, 6167 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0); 6168 if (ctx->rc < 0) { 6169 int j; 6170 6171 for (j = 0; j < ctx->i; j++) { 6172 if_printf(ctx->ifp, 6173 "failed to add mc address" 6174 " %02x:%02x:%02x:" 6175 "%02x:%02x:%02x rc=%d\n", 6176 ctx->mcaddr[j][0], ctx->mcaddr[j][1], 6177 ctx->mcaddr[j][2], ctx->mcaddr[j][3], 6178 ctx->mcaddr[j][4], ctx->mcaddr[j][5], 6179 -ctx->rc); 6180 } 6181 return (0); 6182 } 6183 ctx->del = 0; 6184 ctx->i = 0; 6185 } 6186 6187 return (1); 6188 } 6189 6190 /* 6191 * Program the port's XGMAC based on parameters in ifnet. The caller also 6192 * indicates which parameters should be programmed (the rest are left alone). 6193 */ 6194 int 6195 update_mac_settings(if_t ifp, int flags) 6196 { 6197 int rc = 0; 6198 struct vi_info *vi = if_getsoftc(ifp); 6199 struct port_info *pi = vi->pi; 6200 struct adapter *sc = pi->adapter; 6201 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 6202 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 6203 6204 ASSERT_SYNCHRONIZED_OP(sc); 6205 KASSERT(flags, ("%s: not told what to update.", __func__)); 6206 6207 if (flags & XGMAC_MTU) 6208 mtu = if_getmtu(ifp); 6209 6210 if (flags & XGMAC_PROMISC) 6211 promisc = if_getflags(ifp) & IFF_PROMISC ? 1 : 0; 6212 6213 if (flags & XGMAC_ALLMULTI) 6214 allmulti = if_getflags(ifp) & IFF_ALLMULTI ? 1 : 0; 6215 6216 if (flags & XGMAC_VLANEX) 6217 vlanex = if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING ? 1 : 0; 6218 6219 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 6220 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 6221 allmulti, 1, vlanex, false); 6222 if (rc) { 6223 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 6224 rc); 6225 return (rc); 6226 } 6227 } 6228 6229 if (flags & XGMAC_UCADDR) { 6230 uint8_t ucaddr[ETHER_ADDR_LEN]; 6231 6232 bcopy(if_getlladdr(ifp), ucaddr, sizeof(ucaddr)); 6233 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 6234 ucaddr, true, &vi->smt_idx); 6235 if (rc < 0) { 6236 rc = -rc; 6237 if_printf(ifp, "change_mac failed: %d\n", rc); 6238 return (rc); 6239 } else { 6240 vi->xact_addr_filt = rc; 6241 rc = 0; 6242 } 6243 } 6244 6245 if (flags & XGMAC_MCADDRS) { 6246 struct epoch_tracker et; 6247 struct mcaddr_ctx ctx; 6248 int j; 6249 6250 ctx.ifp = ifp; 6251 ctx.hash = 0; 6252 ctx.i = 0; 6253 ctx.del = 1; 6254 ctx.rc = 0; 6255 /* 6256 * Unlike other drivers, we accumulate list of pointers into 6257 * interface address lists and we need to keep it safe even 6258 * after if_foreach_llmaddr() returns, thus we must enter the 6259 * network epoch. 6260 */ 6261 NET_EPOCH_ENTER(et); 6262 if_foreach_llmaddr(ifp, add_maddr, &ctx); 6263 if (ctx.rc < 0) { 6264 NET_EPOCH_EXIT(et); 6265 rc = -ctx.rc; 6266 return (rc); 6267 } 6268 if (ctx.i > 0) { 6269 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 6270 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0); 6271 NET_EPOCH_EXIT(et); 6272 if (rc < 0) { 6273 rc = -rc; 6274 for (j = 0; j < ctx.i; j++) { 6275 if_printf(ifp, 6276 "failed to add mcast address" 6277 " %02x:%02x:%02x:" 6278 "%02x:%02x:%02x rc=%d\n", 6279 ctx.mcaddr[j][0], ctx.mcaddr[j][1], 6280 ctx.mcaddr[j][2], ctx.mcaddr[j][3], 6281 ctx.mcaddr[j][4], ctx.mcaddr[j][5], 6282 rc); 6283 } 6284 return (rc); 6285 } 6286 ctx.del = 0; 6287 } else 6288 NET_EPOCH_EXIT(et); 6289 6290 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0); 6291 if (rc != 0) 6292 if_printf(ifp, "failed to set mcast address hash: %d\n", 6293 rc); 6294 if (ctx.del == 0) { 6295 /* We clobbered the VXLAN entry if there was one. */ 6296 pi->vxlan_tcam_entry = false; 6297 } 6298 } 6299 6300 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 && 6301 pi->vxlan_tcam_entry == false) { 6302 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac, 6303 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 6304 true); 6305 if (rc < 0) { 6306 rc = -rc; 6307 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n", 6308 rc); 6309 } else { 6310 MPASS(rc == sc->rawf_base + pi->port_id); 6311 rc = 0; 6312 pi->vxlan_tcam_entry = true; 6313 } 6314 } 6315 6316 return (rc); 6317 } 6318 6319 /* 6320 * {begin|end}_synchronized_op must be called from the same thread. 6321 */ 6322 int 6323 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 6324 char *wmesg) 6325 { 6326 int rc, pri; 6327 6328 #ifdef WITNESS 6329 /* the caller thinks it's ok to sleep, but is it really? */ 6330 if (flags & SLEEP_OK) 6331 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 6332 "begin_synchronized_op"); 6333 #endif 6334 6335 if (INTR_OK) 6336 pri = PCATCH; 6337 else 6338 pri = 0; 6339 6340 ADAPTER_LOCK(sc); 6341 for (;;) { 6342 6343 if (vi && IS_DETACHING(vi)) { 6344 rc = ENXIO; 6345 goto done; 6346 } 6347 6348 if (!IS_BUSY(sc)) { 6349 rc = 0; 6350 break; 6351 } 6352 6353 if (!(flags & SLEEP_OK)) { 6354 rc = EBUSY; 6355 goto done; 6356 } 6357 6358 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 6359 rc = EINTR; 6360 goto done; 6361 } 6362 } 6363 6364 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 6365 SET_BUSY(sc); 6366 #ifdef INVARIANTS 6367 sc->last_op = wmesg; 6368 sc->last_op_thr = curthread; 6369 sc->last_op_flags = flags; 6370 #endif 6371 6372 done: 6373 if (!(flags & HOLD_LOCK) || rc) 6374 ADAPTER_UNLOCK(sc); 6375 6376 return (rc); 6377 } 6378 6379 /* 6380 * Tell if_ioctl and if_init that the VI is going away. This is 6381 * special variant of begin_synchronized_op and must be paired with a 6382 * call to end_vi_detach. 6383 */ 6384 void 6385 begin_vi_detach(struct adapter *sc, struct vi_info *vi) 6386 { 6387 ADAPTER_LOCK(sc); 6388 SET_DETACHING(vi); 6389 wakeup(&sc->flags); 6390 while (IS_BUSY(sc)) 6391 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 6392 SET_BUSY(sc); 6393 #ifdef INVARIANTS 6394 sc->last_op = "t4detach"; 6395 sc->last_op_thr = curthread; 6396 sc->last_op_flags = 0; 6397 #endif 6398 ADAPTER_UNLOCK(sc); 6399 } 6400 6401 void 6402 end_vi_detach(struct adapter *sc, struct vi_info *vi) 6403 { 6404 ADAPTER_LOCK(sc); 6405 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6406 CLR_BUSY(sc); 6407 CLR_DETACHING(vi); 6408 wakeup(&sc->flags); 6409 ADAPTER_UNLOCK(sc); 6410 } 6411 6412 /* 6413 * {begin|end}_synchronized_op must be called from the same thread. 6414 */ 6415 void 6416 end_synchronized_op(struct adapter *sc, int flags) 6417 { 6418 6419 if (flags & LOCK_HELD) 6420 ADAPTER_LOCK_ASSERT_OWNED(sc); 6421 else 6422 ADAPTER_LOCK(sc); 6423 6424 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6425 CLR_BUSY(sc); 6426 wakeup(&sc->flags); 6427 ADAPTER_UNLOCK(sc); 6428 } 6429 6430 static int 6431 cxgbe_init_synchronized(struct vi_info *vi) 6432 { 6433 struct port_info *pi = vi->pi; 6434 struct adapter *sc = pi->adapter; 6435 if_t ifp = vi->ifp; 6436 int rc = 0, i; 6437 struct sge_txq *txq; 6438 6439 ASSERT_SYNCHRONIZED_OP(sc); 6440 6441 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6442 return (0); /* already running */ 6443 6444 if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0)) 6445 return (rc); /* error message displayed already */ 6446 6447 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 6448 return (rc); /* error message displayed already */ 6449 6450 rc = update_mac_settings(ifp, XGMAC_ALL); 6451 if (rc) 6452 goto done; /* error message displayed already */ 6453 6454 PORT_LOCK(pi); 6455 if (pi->up_vis == 0) { 6456 t4_update_port_info(pi); 6457 fixup_link_config(pi); 6458 build_medialist(pi); 6459 apply_link_config(pi); 6460 } 6461 6462 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 6463 if (rc != 0) { 6464 if_printf(ifp, "enable_vi failed: %d\n", rc); 6465 PORT_UNLOCK(pi); 6466 goto done; 6467 } 6468 6469 /* 6470 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 6471 * if this changes. 6472 */ 6473 6474 for_each_txq(vi, i, txq) { 6475 TXQ_LOCK(txq); 6476 txq->eq.flags |= EQ_ENABLED; 6477 TXQ_UNLOCK(txq); 6478 } 6479 6480 /* 6481 * The first iq of the first port to come up is used for tracing. 6482 */ 6483 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 6484 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 6485 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 6486 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 6487 V_QUEUENUMBER(sc->traceq)); 6488 pi->flags |= HAS_TRACEQ; 6489 } 6490 6491 /* all ok */ 6492 pi->up_vis++; 6493 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 6494 if (pi->link_cfg.link_ok) 6495 t4_os_link_changed(pi); 6496 PORT_UNLOCK(pi); 6497 6498 mtx_lock(&vi->tick_mtx); 6499 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 6500 callout_reset(&vi->tick, hz, vi_tick, vi); 6501 else 6502 callout_reset(&vi->tick, hz, cxgbe_tick, vi); 6503 mtx_unlock(&vi->tick_mtx); 6504 done: 6505 if (rc != 0) 6506 cxgbe_uninit_synchronized(vi); 6507 6508 return (rc); 6509 } 6510 6511 /* 6512 * Idempotent. 6513 */ 6514 static int 6515 cxgbe_uninit_synchronized(struct vi_info *vi) 6516 { 6517 struct port_info *pi = vi->pi; 6518 struct adapter *sc = pi->adapter; 6519 if_t ifp = vi->ifp; 6520 int rc, i; 6521 struct sge_txq *txq; 6522 6523 ASSERT_SYNCHRONIZED_OP(sc); 6524 6525 if (!(vi->flags & VI_INIT_DONE)) { 6526 if (__predict_false(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6527 KASSERT(0, ("uninited VI is running")); 6528 if_printf(ifp, "uninited VI with running ifnet. " 6529 "vi->flags 0x%016lx, if_flags 0x%08x, " 6530 "if_drv_flags 0x%08x\n", vi->flags, if_getflags(ifp), 6531 if_getdrvflags(ifp)); 6532 } 6533 return (0); 6534 } 6535 6536 /* 6537 * Disable the VI so that all its data in either direction is discarded 6538 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 6539 * tick) intact as the TP can deliver negative advice or data that it's 6540 * holding in its RAM (for an offloaded connection) even after the VI is 6541 * disabled. 6542 */ 6543 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 6544 if (rc) { 6545 if_printf(ifp, "disable_vi failed: %d\n", rc); 6546 return (rc); 6547 } 6548 6549 for_each_txq(vi, i, txq) { 6550 TXQ_LOCK(txq); 6551 txq->eq.flags &= ~EQ_ENABLED; 6552 TXQ_UNLOCK(txq); 6553 } 6554 6555 mtx_lock(&vi->tick_mtx); 6556 callout_stop(&vi->tick); 6557 mtx_unlock(&vi->tick_mtx); 6558 6559 PORT_LOCK(pi); 6560 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6561 PORT_UNLOCK(pi); 6562 return (0); 6563 } 6564 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 6565 pi->up_vis--; 6566 if (pi->up_vis > 0) { 6567 PORT_UNLOCK(pi); 6568 return (0); 6569 } 6570 6571 pi->link_cfg.link_ok = false; 6572 pi->link_cfg.speed = 0; 6573 pi->link_cfg.link_down_rc = 255; 6574 t4_os_link_changed(pi); 6575 PORT_UNLOCK(pi); 6576 6577 return (0); 6578 } 6579 6580 /* 6581 * It is ok for this function to fail midway and return right away. t4_detach 6582 * will walk the entire sc->irq list and clean up whatever is valid. 6583 */ 6584 int 6585 t4_setup_intr_handlers(struct adapter *sc) 6586 { 6587 int rc, rid, p, q, v; 6588 char s[8]; 6589 struct irq *irq; 6590 struct port_info *pi; 6591 struct vi_info *vi; 6592 struct sge *sge = &sc->sge; 6593 struct sge_rxq *rxq; 6594 #ifdef TCP_OFFLOAD 6595 struct sge_ofld_rxq *ofld_rxq; 6596 #endif 6597 #ifdef DEV_NETMAP 6598 struct sge_nm_rxq *nm_rxq; 6599 #endif 6600 #ifdef RSS 6601 int nbuckets = rss_getnumbuckets(); 6602 #endif 6603 6604 /* 6605 * Setup interrupts. 6606 */ 6607 irq = &sc->irq[0]; 6608 rid = sc->intr_type == INTR_INTX ? 0 : 1; 6609 if (forwarding_intr_to_fwq(sc)) 6610 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 6611 6612 /* Multiple interrupts. */ 6613 if (sc->flags & IS_VF) 6614 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 6615 ("%s: too few intr.", __func__)); 6616 else 6617 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 6618 ("%s: too few intr.", __func__)); 6619 6620 /* The first one is always error intr on PFs */ 6621 if (!(sc->flags & IS_VF)) { 6622 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 6623 if (rc != 0) 6624 return (rc); 6625 irq++; 6626 rid++; 6627 } 6628 6629 /* The second one is always the firmware event queue (first on VFs) */ 6630 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 6631 if (rc != 0) 6632 return (rc); 6633 irq++; 6634 rid++; 6635 6636 for_each_port(sc, p) { 6637 pi = sc->port[p]; 6638 for_each_vi(pi, v, vi) { 6639 vi->first_intr = rid - 1; 6640 6641 if (vi->nnmrxq > 0) { 6642 int n = max(vi->nrxq, vi->nnmrxq); 6643 6644 rxq = &sge->rxq[vi->first_rxq]; 6645 #ifdef DEV_NETMAP 6646 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 6647 #endif 6648 for (q = 0; q < n; q++) { 6649 snprintf(s, sizeof(s), "%x%c%x", p, 6650 'a' + v, q); 6651 if (q < vi->nrxq) 6652 irq->rxq = rxq++; 6653 #ifdef DEV_NETMAP 6654 if (q < vi->nnmrxq) 6655 irq->nm_rxq = nm_rxq++; 6656 6657 if (irq->nm_rxq != NULL && 6658 irq->rxq == NULL) { 6659 /* Netmap rx only */ 6660 rc = t4_alloc_irq(sc, irq, rid, 6661 t4_nm_intr, irq->nm_rxq, s); 6662 } 6663 if (irq->nm_rxq != NULL && 6664 irq->rxq != NULL) { 6665 /* NIC and Netmap rx */ 6666 rc = t4_alloc_irq(sc, irq, rid, 6667 t4_vi_intr, irq, s); 6668 } 6669 #endif 6670 if (irq->rxq != NULL && 6671 irq->nm_rxq == NULL) { 6672 /* NIC rx only */ 6673 rc = t4_alloc_irq(sc, irq, rid, 6674 t4_intr, irq->rxq, s); 6675 } 6676 if (rc != 0) 6677 return (rc); 6678 #ifdef RSS 6679 if (q < vi->nrxq) { 6680 bus_bind_intr(sc->dev, irq->res, 6681 rss_getcpu(q % nbuckets)); 6682 } 6683 #endif 6684 irq++; 6685 rid++; 6686 vi->nintr++; 6687 } 6688 } else { 6689 for_each_rxq(vi, q, rxq) { 6690 snprintf(s, sizeof(s), "%x%c%x", p, 6691 'a' + v, q); 6692 rc = t4_alloc_irq(sc, irq, rid, 6693 t4_intr, rxq, s); 6694 if (rc != 0) 6695 return (rc); 6696 #ifdef RSS 6697 bus_bind_intr(sc->dev, irq->res, 6698 rss_getcpu(q % nbuckets)); 6699 #endif 6700 irq++; 6701 rid++; 6702 vi->nintr++; 6703 } 6704 } 6705 #ifdef TCP_OFFLOAD 6706 for_each_ofld_rxq(vi, q, ofld_rxq) { 6707 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 6708 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 6709 ofld_rxq, s); 6710 if (rc != 0) 6711 return (rc); 6712 irq++; 6713 rid++; 6714 vi->nintr++; 6715 } 6716 #endif 6717 } 6718 } 6719 MPASS(irq == &sc->irq[sc->intr_count]); 6720 6721 return (0); 6722 } 6723 6724 static void 6725 write_global_rss_key(struct adapter *sc) 6726 { 6727 #ifdef RSS 6728 int i; 6729 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6730 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6731 6732 CTASSERT(RSS_KEYSIZE == 40); 6733 6734 rss_getkey((void *)&raw_rss_key[0]); 6735 for (i = 0; i < nitems(rss_key); i++) { 6736 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 6737 } 6738 t4_write_rss_key(sc, &rss_key[0], -1, 1); 6739 #endif 6740 } 6741 6742 /* 6743 * Idempotent. 6744 */ 6745 static int 6746 adapter_full_init(struct adapter *sc) 6747 { 6748 int rc, i; 6749 6750 ASSERT_SYNCHRONIZED_OP(sc); 6751 6752 /* 6753 * queues that belong to the adapter (not any particular port). 6754 */ 6755 rc = t4_setup_adapter_queues(sc); 6756 if (rc != 0) 6757 return (rc); 6758 6759 MPASS(sc->params.nports <= nitems(sc->tq)); 6760 for (i = 0; i < sc->params.nports; i++) { 6761 if (sc->tq[i] != NULL) 6762 continue; 6763 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 6764 taskqueue_thread_enqueue, &sc->tq[i]); 6765 if (sc->tq[i] == NULL) { 6766 CH_ERR(sc, "failed to allocate task queue %d\n", i); 6767 return (ENOMEM); 6768 } 6769 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 6770 device_get_nameunit(sc->dev), i); 6771 } 6772 6773 if (!(sc->flags & IS_VF)) { 6774 write_global_rss_key(sc); 6775 t4_intr_enable(sc); 6776 } 6777 return (0); 6778 } 6779 6780 int 6781 adapter_init(struct adapter *sc) 6782 { 6783 int rc; 6784 6785 ASSERT_SYNCHRONIZED_OP(sc); 6786 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 6787 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 6788 ("%s: FULL_INIT_DONE already", __func__)); 6789 6790 rc = adapter_full_init(sc); 6791 if (rc != 0) 6792 adapter_full_uninit(sc); 6793 else 6794 sc->flags |= FULL_INIT_DONE; 6795 6796 return (rc); 6797 } 6798 6799 /* 6800 * Idempotent. 6801 */ 6802 static void 6803 adapter_full_uninit(struct adapter *sc) 6804 { 6805 int i; 6806 6807 t4_teardown_adapter_queues(sc); 6808 6809 for (i = 0; i < nitems(sc->tq); i++) { 6810 if (sc->tq[i] == NULL) 6811 continue; 6812 taskqueue_free(sc->tq[i]); 6813 sc->tq[i] = NULL; 6814 } 6815 6816 sc->flags &= ~FULL_INIT_DONE; 6817 } 6818 6819 #ifdef RSS 6820 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 6821 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 6822 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 6823 RSS_HASHTYPE_RSS_UDP_IPV6) 6824 6825 /* Translates kernel hash types to hardware. */ 6826 static int 6827 hashconfig_to_hashen(int hashconfig) 6828 { 6829 int hashen = 0; 6830 6831 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 6832 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 6833 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 6834 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 6835 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 6836 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6837 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6838 } 6839 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 6840 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6841 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6842 } 6843 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 6844 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6845 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 6846 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6847 6848 return (hashen); 6849 } 6850 6851 /* Translates hardware hash types to kernel. */ 6852 static int 6853 hashen_to_hashconfig(int hashen) 6854 { 6855 int hashconfig = 0; 6856 6857 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 6858 /* 6859 * If UDP hashing was enabled it must have been enabled for 6860 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 6861 * enabling any 4-tuple hash is nonsense configuration. 6862 */ 6863 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6864 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 6865 6866 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6867 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 6868 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6869 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 6870 } 6871 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6872 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 6873 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6874 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 6875 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6876 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 6877 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6878 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 6879 6880 return (hashconfig); 6881 } 6882 #endif 6883 6884 /* 6885 * Idempotent. 6886 */ 6887 static int 6888 vi_full_init(struct vi_info *vi) 6889 { 6890 struct adapter *sc = vi->adapter; 6891 struct sge_rxq *rxq; 6892 int rc, i, j; 6893 #ifdef RSS 6894 int nbuckets = rss_getnumbuckets(); 6895 int hashconfig = rss_gethashconfig(); 6896 int extra; 6897 #endif 6898 6899 ASSERT_SYNCHRONIZED_OP(sc); 6900 6901 /* 6902 * Allocate tx/rx/fl queues for this VI. 6903 */ 6904 rc = t4_setup_vi_queues(vi); 6905 if (rc != 0) 6906 return (rc); 6907 6908 /* 6909 * Setup RSS for this VI. Save a copy of the RSS table for later use. 6910 */ 6911 if (vi->nrxq > vi->rss_size) { 6912 CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); " 6913 "some queues will never receive traffic.\n", vi->nrxq, 6914 vi->rss_size); 6915 } else if (vi->rss_size % vi->nrxq) { 6916 CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); " 6917 "expect uneven traffic distribution.\n", vi->nrxq, 6918 vi->rss_size); 6919 } 6920 #ifdef RSS 6921 if (vi->nrxq != nbuckets) { 6922 CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);" 6923 "performance will be impacted.\n", vi->nrxq, nbuckets); 6924 } 6925 #endif 6926 if (vi->rss == NULL) 6927 vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE, 6928 M_ZERO | M_WAITOK); 6929 for (i = 0; i < vi->rss_size;) { 6930 #ifdef RSS 6931 j = rss_get_indirection_to_bucket(i); 6932 j %= vi->nrxq; 6933 rxq = &sc->sge.rxq[vi->first_rxq + j]; 6934 vi->rss[i++] = rxq->iq.abs_id; 6935 #else 6936 for_each_rxq(vi, j, rxq) { 6937 vi->rss[i++] = rxq->iq.abs_id; 6938 if (i == vi->rss_size) 6939 break; 6940 } 6941 #endif 6942 } 6943 6944 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 6945 vi->rss, vi->rss_size); 6946 if (rc != 0) { 6947 CH_ERR(vi, "rss_config failed: %d\n", rc); 6948 return (rc); 6949 } 6950 6951 #ifdef RSS 6952 vi->hashen = hashconfig_to_hashen(hashconfig); 6953 6954 /* 6955 * We may have had to enable some hashes even though the global config 6956 * wants them disabled. This is a potential problem that must be 6957 * reported to the user. 6958 */ 6959 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 6960 6961 /* 6962 * If we consider only the supported hash types, then the enabled hashes 6963 * are a superset of the requested hashes. In other words, there cannot 6964 * be any supported hash that was requested but not enabled, but there 6965 * can be hashes that were not requested but had to be enabled. 6966 */ 6967 extra &= SUPPORTED_RSS_HASHTYPES; 6968 MPASS((extra & hashconfig) == 0); 6969 6970 if (extra) { 6971 CH_ALERT(vi, 6972 "global RSS config (0x%x) cannot be accommodated.\n", 6973 hashconfig); 6974 } 6975 if (extra & RSS_HASHTYPE_RSS_IPV4) 6976 CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n"); 6977 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 6978 CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n"); 6979 if (extra & RSS_HASHTYPE_RSS_IPV6) 6980 CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n"); 6981 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 6982 CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n"); 6983 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 6984 CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n"); 6985 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 6986 CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n"); 6987 #else 6988 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 6989 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 6990 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6991 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 6992 #endif 6993 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 6994 0, 0); 6995 if (rc != 0) { 6996 CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc); 6997 return (rc); 6998 } 6999 7000 return (0); 7001 } 7002 7003 int 7004 vi_init(struct vi_info *vi) 7005 { 7006 int rc; 7007 7008 ASSERT_SYNCHRONIZED_OP(vi->adapter); 7009 KASSERT((vi->flags & VI_INIT_DONE) == 0, 7010 ("%s: VI_INIT_DONE already", __func__)); 7011 7012 rc = vi_full_init(vi); 7013 if (rc != 0) 7014 vi_full_uninit(vi); 7015 else 7016 vi->flags |= VI_INIT_DONE; 7017 7018 return (rc); 7019 } 7020 7021 /* 7022 * Idempotent. 7023 */ 7024 static void 7025 vi_full_uninit(struct vi_info *vi) 7026 { 7027 7028 if (vi->flags & VI_INIT_DONE) { 7029 quiesce_vi(vi); 7030 free(vi->rss, M_CXGBE); 7031 free(vi->nm_rss, M_CXGBE); 7032 } 7033 7034 t4_teardown_vi_queues(vi); 7035 vi->flags &= ~VI_INIT_DONE; 7036 } 7037 7038 static void 7039 quiesce_txq(struct sge_txq *txq) 7040 { 7041 struct sge_eq *eq = &txq->eq; 7042 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 7043 7044 MPASS(eq->flags & EQ_SW_ALLOCATED); 7045 MPASS(!(eq->flags & EQ_ENABLED)); 7046 7047 /* Wait for the mp_ring to empty. */ 7048 while (!mp_ring_is_idle(txq->r)) { 7049 mp_ring_check_drainage(txq->r, 4096); 7050 pause("rquiesce", 1); 7051 } 7052 MPASS(txq->txp.npkt == 0); 7053 7054 if (eq->flags & EQ_HW_ALLOCATED) { 7055 /* 7056 * Hardware is alive and working normally. Wait for it to 7057 * finish and then wait for the driver to catch up and reclaim 7058 * all descriptors. 7059 */ 7060 while (spg->cidx != htobe16(eq->pidx)) 7061 pause("equiesce", 1); 7062 while (eq->cidx != eq->pidx) 7063 pause("dquiesce", 1); 7064 } else { 7065 /* 7066 * Hardware is unavailable. Discard all pending tx and reclaim 7067 * descriptors directly. 7068 */ 7069 TXQ_LOCK(txq); 7070 while (eq->cidx != eq->pidx) { 7071 struct mbuf *m, *nextpkt; 7072 struct tx_sdesc *txsd; 7073 7074 txsd = &txq->sdesc[eq->cidx]; 7075 for (m = txsd->m; m != NULL; m = nextpkt) { 7076 nextpkt = m->m_nextpkt; 7077 m->m_nextpkt = NULL; 7078 m_freem(m); 7079 } 7080 IDXINCR(eq->cidx, txsd->desc_used, eq->sidx); 7081 } 7082 spg->pidx = spg->cidx = htobe16(eq->cidx); 7083 TXQ_UNLOCK(txq); 7084 } 7085 } 7086 7087 static void 7088 quiesce_wrq(struct sge_wrq *wrq) 7089 { 7090 struct wrqe *wr; 7091 7092 TXQ_LOCK(wrq); 7093 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 7094 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 7095 #ifdef INVARIANTS 7096 wrq->nwr_pending--; 7097 wrq->ndesc_needed -= howmany(wr->wr_len, EQ_ESIZE); 7098 #endif 7099 free(wr, M_CXGBE); 7100 } 7101 MPASS(wrq->nwr_pending == 0); 7102 MPASS(wrq->ndesc_needed == 0); 7103 wrq->nwr_pending = 0; 7104 wrq->ndesc_needed = 0; 7105 TXQ_UNLOCK(wrq); 7106 } 7107 7108 static void 7109 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 7110 { 7111 /* Synchronize with the interrupt handler */ 7112 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 7113 pause("iqfree", 1); 7114 7115 if (fl != NULL) { 7116 MPASS(iq->flags & IQ_HAS_FL); 7117 7118 mtx_lock(&sc->sfl_lock); 7119 FL_LOCK(fl); 7120 fl->flags |= FL_DOOMED; 7121 FL_UNLOCK(fl); 7122 callout_stop(&sc->sfl_callout); 7123 mtx_unlock(&sc->sfl_lock); 7124 7125 KASSERT((fl->flags & FL_STARVING) == 0, 7126 ("%s: still starving", __func__)); 7127 7128 /* Release all buffers if hardware is no longer available. */ 7129 if (!(iq->flags & IQ_HW_ALLOCATED)) 7130 free_fl_buffers(sc, fl); 7131 } 7132 } 7133 7134 /* 7135 * Wait for all activity on all the queues of the VI to complete. It is assumed 7136 * that no new work is being enqueued by the hardware or the driver. That part 7137 * should be arranged before calling this function. 7138 */ 7139 static void 7140 quiesce_vi(struct vi_info *vi) 7141 { 7142 int i; 7143 struct adapter *sc = vi->adapter; 7144 struct sge_rxq *rxq; 7145 struct sge_txq *txq; 7146 #ifdef TCP_OFFLOAD 7147 struct sge_ofld_rxq *ofld_rxq; 7148 #endif 7149 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7150 struct sge_ofld_txq *ofld_txq; 7151 #endif 7152 7153 if (!(vi->flags & VI_INIT_DONE)) 7154 return; 7155 7156 for_each_txq(vi, i, txq) { 7157 quiesce_txq(txq); 7158 } 7159 7160 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7161 for_each_ofld_txq(vi, i, ofld_txq) { 7162 quiesce_wrq(&ofld_txq->wrq); 7163 } 7164 #endif 7165 7166 for_each_rxq(vi, i, rxq) { 7167 quiesce_iq_fl(sc, &rxq->iq, &rxq->fl); 7168 } 7169 7170 #ifdef TCP_OFFLOAD 7171 for_each_ofld_rxq(vi, i, ofld_rxq) { 7172 quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl); 7173 } 7174 #endif 7175 } 7176 7177 static int 7178 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 7179 driver_intr_t *handler, void *arg, char *name) 7180 { 7181 int rc; 7182 7183 irq->rid = rid; 7184 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 7185 RF_SHAREABLE | RF_ACTIVE); 7186 if (irq->res == NULL) { 7187 device_printf(sc->dev, 7188 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 7189 return (ENOMEM); 7190 } 7191 7192 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 7193 NULL, handler, arg, &irq->tag); 7194 if (rc != 0) { 7195 device_printf(sc->dev, 7196 "failed to setup interrupt for rid %d, name %s: %d\n", 7197 rid, name, rc); 7198 } else if (name) 7199 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 7200 7201 return (rc); 7202 } 7203 7204 static int 7205 t4_free_irq(struct adapter *sc, struct irq *irq) 7206 { 7207 if (irq->tag) 7208 bus_teardown_intr(sc->dev, irq->res, irq->tag); 7209 if (irq->res) 7210 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 7211 7212 bzero(irq, sizeof(*irq)); 7213 7214 return (0); 7215 } 7216 7217 static void 7218 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 7219 { 7220 7221 regs->version = chip_id(sc) | chip_rev(sc) << 10; 7222 t4_get_regs(sc, buf, regs->len); 7223 } 7224 7225 #define A_PL_INDIR_CMD 0x1f8 7226 7227 #define S_PL_AUTOINC 31 7228 #define M_PL_AUTOINC 0x1U 7229 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 7230 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 7231 7232 #define S_PL_VFID 20 7233 #define M_PL_VFID 0xffU 7234 #define V_PL_VFID(x) ((x) << S_PL_VFID) 7235 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 7236 7237 #define S_PL_ADDR 0 7238 #define M_PL_ADDR 0xfffffU 7239 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 7240 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 7241 7242 #define A_PL_INDIR_DATA 0x1fc 7243 7244 static uint64_t 7245 read_vf_stat(struct adapter *sc, u_int vin, int reg) 7246 { 7247 u32 stats[2]; 7248 7249 if (sc->flags & IS_VF) { 7250 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 7251 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 7252 } else { 7253 mtx_assert(&sc->reg_lock, MA_OWNED); 7254 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 7255 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 7256 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 7257 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 7258 } 7259 return (((uint64_t)stats[1]) << 32 | stats[0]); 7260 } 7261 7262 static void 7263 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 7264 { 7265 7266 #define GET_STAT(name) \ 7267 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 7268 7269 if (!(sc->flags & IS_VF)) 7270 mtx_lock(&sc->reg_lock); 7271 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 7272 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 7273 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 7274 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 7275 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 7276 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 7277 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 7278 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 7279 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 7280 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 7281 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 7282 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 7283 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 7284 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 7285 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 7286 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 7287 if (!(sc->flags & IS_VF)) 7288 mtx_unlock(&sc->reg_lock); 7289 7290 #undef GET_STAT 7291 } 7292 7293 static void 7294 t4_clr_vi_stats(struct adapter *sc, u_int vin) 7295 { 7296 int reg; 7297 7298 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 7299 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 7300 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 7301 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 7302 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 7303 } 7304 7305 static void 7306 vi_refresh_stats(struct vi_info *vi) 7307 { 7308 struct timeval tv; 7309 const struct timeval interval = {0, 250000}; /* 250ms */ 7310 7311 mtx_assert(&vi->tick_mtx, MA_OWNED); 7312 7313 if (vi->flags & VI_SKIP_STATS) 7314 return; 7315 7316 getmicrotime(&tv); 7317 timevalsub(&tv, &interval); 7318 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7319 return; 7320 7321 t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats); 7322 getmicrotime(&vi->last_refreshed); 7323 } 7324 7325 static void 7326 cxgbe_refresh_stats(struct vi_info *vi) 7327 { 7328 u_int i, v, tnl_cong_drops, chan_map; 7329 struct timeval tv; 7330 const struct timeval interval = {0, 250000}; /* 250ms */ 7331 struct port_info *pi; 7332 struct adapter *sc; 7333 7334 mtx_assert(&vi->tick_mtx, MA_OWNED); 7335 7336 if (vi->flags & VI_SKIP_STATS) 7337 return; 7338 7339 getmicrotime(&tv); 7340 timevalsub(&tv, &interval); 7341 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7342 return; 7343 7344 pi = vi->pi; 7345 sc = vi->adapter; 7346 tnl_cong_drops = 0; 7347 t4_get_port_stats(sc, pi->port_id, &pi->stats); 7348 chan_map = pi->rx_e_chan_map; 7349 while (chan_map) { 7350 i = ffs(chan_map) - 1; 7351 mtx_lock(&sc->reg_lock); 7352 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 7353 A_TP_MIB_TNL_CNG_DROP_0 + i); 7354 mtx_unlock(&sc->reg_lock); 7355 tnl_cong_drops += v; 7356 chan_map &= ~(1 << i); 7357 } 7358 pi->tnl_cong_drops = tnl_cong_drops; 7359 getmicrotime(&vi->last_refreshed); 7360 } 7361 7362 static void 7363 cxgbe_tick(void *arg) 7364 { 7365 struct vi_info *vi = arg; 7366 7367 MPASS(IS_MAIN_VI(vi)); 7368 mtx_assert(&vi->tick_mtx, MA_OWNED); 7369 7370 cxgbe_refresh_stats(vi); 7371 callout_schedule(&vi->tick, hz); 7372 } 7373 7374 static void 7375 vi_tick(void *arg) 7376 { 7377 struct vi_info *vi = arg; 7378 7379 mtx_assert(&vi->tick_mtx, MA_OWNED); 7380 7381 vi_refresh_stats(vi); 7382 callout_schedule(&vi->tick, hz); 7383 } 7384 7385 /* 7386 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 7387 */ 7388 static char *caps_decoder[] = { 7389 "\20\001IPMI\002NCSI", /* 0: NBM */ 7390 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 7391 "\20\001INGRESS\002EGRESS", /* 2: switch */ 7392 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 7393 "\006HASHFILTER\007ETHOFLD", 7394 "\20\001TOE", /* 4: TOE */ 7395 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 7396 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 7397 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 7398 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 7399 "\007T10DIF" 7400 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 7401 "\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE" /* 7: Crypto */ 7402 "\004TLS_HW", 7403 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 7404 "\004PO_INITIATOR\005PO_TARGET", 7405 }; 7406 7407 void 7408 t4_sysctls(struct adapter *sc) 7409 { 7410 struct sysctl_ctx_list *ctx = &sc->ctx; 7411 struct sysctl_oid *oid; 7412 struct sysctl_oid_list *children, *c0; 7413 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 7414 7415 /* 7416 * dev.t4nex.X. 7417 */ 7418 oid = device_get_sysctl_tree(sc->dev); 7419 c0 = children = SYSCTL_CHILDREN(oid); 7420 7421 sc->sc_do_rxcopy = 1; 7422 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 7423 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 7424 7425 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 7426 sc->params.nports, "# of ports"); 7427 7428 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 7429 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells, 7430 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A", 7431 "available doorbells"); 7432 7433 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 7434 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 7435 7436 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 7437 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7438 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val), 7439 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 7440 7441 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 7442 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7443 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val), 7444 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 7445 7446 t4_sge_sysctls(sc, ctx, children); 7447 7448 sc->lro_timeout = 100; 7449 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 7450 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 7451 7452 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 7453 &sc->debug_flags, 0, "flags to enable runtime debugging"); 7454 7455 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 7456 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 7457 7458 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 7459 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 7460 7461 if (sc->flags & IS_VF) 7462 return; 7463 7464 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 7465 NULL, chip_rev(sc), "chip hardware revision"); 7466 7467 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 7468 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 7469 7470 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 7471 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 7472 7473 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 7474 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 7475 7476 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 7477 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 7478 7479 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 7480 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 7481 7482 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 7483 sc->er_version, 0, "expansion ROM version"); 7484 7485 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 7486 sc->bs_version, 0, "bootstrap firmware version"); 7487 7488 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 7489 NULL, sc->params.scfg_vers, "serial config version"); 7490 7491 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 7492 NULL, sc->params.vpd_vers, "VPD version"); 7493 7494 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 7495 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 7496 7497 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 7498 sc->cfcsum, "config file checksum"); 7499 7500 #define SYSCTL_CAP(name, n, text) \ 7501 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 7502 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \ 7503 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \ 7504 "available " text " capabilities") 7505 7506 SYSCTL_CAP(nbmcaps, 0, "NBM"); 7507 SYSCTL_CAP(linkcaps, 1, "link"); 7508 SYSCTL_CAP(switchcaps, 2, "switch"); 7509 SYSCTL_CAP(niccaps, 3, "NIC"); 7510 SYSCTL_CAP(toecaps, 4, "TCP offload"); 7511 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 7512 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 7513 SYSCTL_CAP(cryptocaps, 7, "crypto"); 7514 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 7515 #undef SYSCTL_CAP 7516 7517 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 7518 NULL, sc->tids.nftids, "number of filters"); 7519 7520 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7521 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7522 sysctl_temperature, "I", "chip temperature (in Celsius)"); 7523 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", 7524 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7525 sysctl_reset_sensor, "I", "reset the chip's temperature sensor."); 7526 7527 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", 7528 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7529 sysctl_loadavg, "A", 7530 "microprocessor load averages (debug firmwares only)"); 7531 7532 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", 7533 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd, 7534 "I", "core Vdd (in mV)"); 7535 7536 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 7537 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS, 7538 sysctl_cpus, "A", "local CPUs"); 7539 7540 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 7541 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS, 7542 sysctl_cpus, "A", "preferred CPUs for interrupts"); 7543 7544 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 7545 &sc->swintr, 0, "software triggered interrupts"); 7546 7547 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset", 7548 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I", 7549 "1 = reset adapter, 0 = zero reset counter"); 7550 7551 /* 7552 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 7553 */ 7554 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 7555 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL, 7556 "logs and miscellaneous information"); 7557 children = SYSCTL_CHILDREN(oid); 7558 7559 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 7560 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7561 sysctl_cctrl, "A", "congestion control"); 7562 7563 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 7564 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7565 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 7566 7567 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 7568 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7569 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 7570 7571 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 7572 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7573 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 7574 7575 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 7576 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3, 7577 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 7578 7579 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 7580 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4, 7581 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 7582 7583 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 7584 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5, 7585 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 7586 7587 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 7588 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7589 sysctl_cim_la, "A", "CIM logic analyzer"); 7590 7591 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 7592 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7593 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 7594 7595 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 7596 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7597 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 7598 7599 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 7600 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7601 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 7602 7603 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 7604 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7605 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 7606 7607 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 7608 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7609 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 7610 7611 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 7612 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7613 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 7614 7615 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 7616 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7617 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 7618 7619 if (chip_id(sc) > CHELSIO_T4) { 7620 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 7621 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7622 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7623 "CIM OBQ 6 (SGE0-RX)"); 7624 7625 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 7626 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7627 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7628 "CIM OBQ 7 (SGE1-RX)"); 7629 } 7630 7631 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 7632 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7633 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 7634 7635 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 7636 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7637 sysctl_cim_qcfg, "A", "CIM queue configuration"); 7638 7639 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 7640 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7641 sysctl_cpl_stats, "A", "CPL statistics"); 7642 7643 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 7644 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7645 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 7646 7647 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats", 7648 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7649 sysctl_tid_stats, "A", "tid stats"); 7650 7651 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 7652 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7653 sysctl_devlog, "A", "firmware's device log"); 7654 7655 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 7656 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7657 sysctl_fcoe_stats, "A", "FCoE statistics"); 7658 7659 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 7660 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7661 sysctl_hw_sched, "A", "hardware scheduler "); 7662 7663 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 7664 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7665 sysctl_l2t, "A", "hardware L2 table"); 7666 7667 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 7668 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7669 sysctl_smt, "A", "hardware source MAC table"); 7670 7671 #ifdef INET6 7672 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 7673 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7674 sysctl_clip, "A", "active CLIP table entries"); 7675 #endif 7676 7677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 7678 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7679 sysctl_lb_stats, "A", "loopback statistics"); 7680 7681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 7682 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7683 sysctl_meminfo, "A", "memory regions"); 7684 7685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 7686 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7687 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 7688 "A", "MPS TCAM entries"); 7689 7690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 7691 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7692 sysctl_path_mtus, "A", "path MTUs"); 7693 7694 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 7695 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7696 sysctl_pm_stats, "A", "PM statistics"); 7697 7698 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 7699 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7700 sysctl_rdma_stats, "A", "RDMA statistics"); 7701 7702 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 7703 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7704 sysctl_tcp_stats, "A", "TCP statistics"); 7705 7706 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 7707 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7708 sysctl_tids, "A", "TID information"); 7709 7710 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 7711 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7712 sysctl_tp_err_stats, "A", "TP error statistics"); 7713 7714 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats", 7715 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7716 sysctl_tnl_stats, "A", "TP tunnel statistics"); 7717 7718 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 7719 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7720 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask"); 7721 7722 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 7723 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7724 sysctl_tp_la, "A", "TP logic analyzer"); 7725 7726 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 7727 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7728 sysctl_tx_rate, "A", "Tx rate"); 7729 7730 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 7731 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7732 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 7733 7734 if (chip_id(sc) >= CHELSIO_T5) { 7735 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 7736 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7737 sysctl_wcwr_stats, "A", "write combined work requests"); 7738 } 7739 7740 #ifdef KERN_TLS 7741 if (is_ktls(sc)) { 7742 /* 7743 * dev.t4nex.0.tls. 7744 */ 7745 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", 7746 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters"); 7747 children = SYSCTL_CHILDREN(oid); 7748 7749 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys", 7750 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS " 7751 "keys in work requests (1) or attempt to store TLS keys " 7752 "in card memory."); 7753 7754 if (is_t6(sc)) 7755 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs", 7756 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to " 7757 "combine TCB field updates with TLS record work " 7758 "requests."); 7759 } 7760 #endif 7761 7762 #ifdef TCP_OFFLOAD 7763 if (is_offload(sc)) { 7764 int i; 7765 char s[4]; 7766 7767 /* 7768 * dev.t4nex.X.toe. 7769 */ 7770 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", 7771 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters"); 7772 children = SYSCTL_CHILDREN(oid); 7773 7774 sc->tt.cong_algorithm = -1; 7775 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 7776 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 7777 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 7778 "3 = highspeed)"); 7779 7780 sc->tt.sndbuf = -1; 7781 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 7782 &sc->tt.sndbuf, 0, "hardware send buffer"); 7783 7784 sc->tt.ddp = 0; 7785 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", 7786 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, ""); 7787 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW, 7788 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)"); 7789 7790 sc->tt.rx_coalesce = -1; 7791 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 7792 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 7793 7794 sc->tt.tls = 0; 7795 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT | 7796 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I", 7797 "Inline TLS allowed"); 7798 7799 sc->tt.tx_align = -1; 7800 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 7801 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 7802 7803 sc->tt.tx_zcopy = 0; 7804 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 7805 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 7806 "Enable zero-copy aio_write(2)"); 7807 7808 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 7809 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7810 "cop_managed_offloading", CTLFLAG_RW, 7811 &sc->tt.cop_managed_offloading, 0, 7812 "COP (Connection Offload Policy) controls all TOE offload"); 7813 7814 sc->tt.autorcvbuf_inc = 16 * 1024; 7815 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 7816 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 7817 "autorcvbuf increment"); 7818 7819 sc->tt.update_hc_on_pmtu_change = 1; 7820 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7821 "update_hc_on_pmtu_change", CTLFLAG_RW, 7822 &sc->tt.update_hc_on_pmtu_change, 0, 7823 "Update hostcache entry if the PMTU changes"); 7824 7825 sc->tt.iso = 1; 7826 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW, 7827 &sc->tt.iso, 0, "Enable iSCSI segmentation offload"); 7828 7829 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 7830 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7831 sysctl_tp_tick, "A", "TP timer tick (us)"); 7832 7833 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 7834 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7835 sysctl_tp_tick, "A", "TCP timestamp tick (us)"); 7836 7837 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 7838 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7839 sysctl_tp_tick, "A", "DACK tick (us)"); 7840 7841 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 7842 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7843 sysctl_tp_dack_timer, "IU", "DACK timer (us)"); 7844 7845 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 7846 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7847 A_TP_RXT_MIN, sysctl_tp_timer, "LU", 7848 "Minimum retransmit interval (us)"); 7849 7850 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 7851 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7852 A_TP_RXT_MAX, sysctl_tp_timer, "LU", 7853 "Maximum retransmit interval (us)"); 7854 7855 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 7856 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7857 A_TP_PERS_MIN, sysctl_tp_timer, "LU", 7858 "Persist timer min (us)"); 7859 7860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 7861 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7862 A_TP_PERS_MAX, sysctl_tp_timer, "LU", 7863 "Persist timer max (us)"); 7864 7865 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 7866 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7867 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU", 7868 "Keepalive idle timer (us)"); 7869 7870 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 7871 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7872 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU", 7873 "Keepalive interval timer (us)"); 7874 7875 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 7876 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7877 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)"); 7878 7879 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 7880 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7881 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU", 7882 "FINWAIT2 timer (us)"); 7883 7884 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 7885 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7886 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU", 7887 "Number of SYN retransmissions before abort"); 7888 7889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 7890 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7891 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU", 7892 "Number of retransmissions before abort"); 7893 7894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 7895 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7896 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU", 7897 "Number of keepalive probes before abort"); 7898 7899 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 7900 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7901 "TOE retransmit backoffs"); 7902 children = SYSCTL_CHILDREN(oid); 7903 for (i = 0; i < 16; i++) { 7904 snprintf(s, sizeof(s), "%u", i); 7905 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 7906 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7907 i, sysctl_tp_backoff, "IU", 7908 "TOE retransmit backoff"); 7909 } 7910 } 7911 #endif 7912 } 7913 7914 void 7915 vi_sysctls(struct vi_info *vi) 7916 { 7917 struct sysctl_ctx_list *ctx = &vi->ctx; 7918 struct sysctl_oid *oid; 7919 struct sysctl_oid_list *children; 7920 7921 /* 7922 * dev.v?(cxgbe|cxl).X. 7923 */ 7924 oid = device_get_sysctl_tree(vi->dev); 7925 children = SYSCTL_CHILDREN(oid); 7926 7927 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 7928 vi->viid, "VI identifer"); 7929 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 7930 &vi->nrxq, 0, "# of rx queues"); 7931 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 7932 &vi->ntxq, 0, "# of tx queues"); 7933 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 7934 &vi->first_rxq, 0, "index of first rx queue"); 7935 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 7936 &vi->first_txq, 0, "index of first tx queue"); 7937 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 7938 vi->rss_base, "start of RSS indirection table"); 7939 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 7940 vi->rss_size, "size of RSS indirection table"); 7941 7942 if (IS_MAIN_VI(vi)) { 7943 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 7944 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7945 sysctl_noflowq, "IU", 7946 "Reserve queue 0 for non-flowid packets"); 7947 } 7948 7949 if (vi->adapter->flags & IS_VF) { 7950 MPASS(vi->flags & TX_USES_VM_WR); 7951 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD, 7952 NULL, 1, "use VM work requests for transmit"); 7953 } else { 7954 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr", 7955 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7956 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit"); 7957 } 7958 7959 #ifdef TCP_OFFLOAD 7960 if (vi->nofldrxq != 0) { 7961 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 7962 &vi->nofldrxq, 0, 7963 "# of rx queues for offloaded TCP connections"); 7964 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 7965 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 7966 "index of first TOE rx queue"); 7967 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 7968 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7969 sysctl_holdoff_tmr_idx_ofld, "I", 7970 "holdoff timer index for TOE queues"); 7971 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 7972 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7973 sysctl_holdoff_pktc_idx_ofld, "I", 7974 "holdoff packet counter index for TOE queues"); 7975 } 7976 #endif 7977 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7978 if (vi->nofldtxq != 0) { 7979 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 7980 &vi->nofldtxq, 0, 7981 "# of tx queues for TOE/ETHOFLD"); 7982 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 7983 CTLFLAG_RD, &vi->first_ofld_txq, 0, 7984 "index of first TOE/ETHOFLD tx queue"); 7985 } 7986 #endif 7987 #ifdef DEV_NETMAP 7988 if (vi->nnmrxq != 0) { 7989 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 7990 &vi->nnmrxq, 0, "# of netmap rx queues"); 7991 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 7992 &vi->nnmtxq, 0, "# of netmap tx queues"); 7993 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 7994 CTLFLAG_RD, &vi->first_nm_rxq, 0, 7995 "index of first netmap rx queue"); 7996 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 7997 CTLFLAG_RD, &vi->first_nm_txq, 0, 7998 "index of first netmap tx queue"); 7999 } 8000 #endif 8001 8002 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 8003 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 8004 sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); 8005 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 8006 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 8007 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); 8008 8009 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 8010 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 8011 sysctl_qsize_rxq, "I", "rx queue size"); 8012 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 8013 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 8014 sysctl_qsize_txq, "I", "tx queue size"); 8015 } 8016 8017 static void 8018 cxgbe_sysctls(struct port_info *pi) 8019 { 8020 struct sysctl_ctx_list *ctx = &pi->ctx; 8021 struct sysctl_oid *oid; 8022 struct sysctl_oid_list *children, *children2; 8023 struct adapter *sc = pi->adapter; 8024 int i; 8025 char name[16]; 8026 static char *tc_flags = {"\20\1USER"}; 8027 8028 /* 8029 * dev.cxgbe.X. 8030 */ 8031 oid = device_get_sysctl_tree(pi->dev); 8032 children = SYSCTL_CHILDREN(oid); 8033 8034 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", 8035 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 8036 sysctl_linkdnrc, "A", "reason why link is down"); 8037 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 8038 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 8039 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 8040 sysctl_btphy, "I", "PHY temperature (in Celsius)"); 8041 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 8042 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1, 8043 sysctl_btphy, "I", "PHY firmware version"); 8044 } 8045 8046 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 8047 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8048 sysctl_pause_settings, "A", 8049 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 8050 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec", 8051 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A", 8052 "FEC in use on the link"); 8053 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec", 8054 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8055 sysctl_requested_fec, "A", 8056 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)"); 8057 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec", 8058 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A", 8059 "FEC recommended by the cable/transceiver"); 8060 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 8061 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8062 sysctl_autoneg, "I", 8063 "autonegotiation (-1 = not supported)"); 8064 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec", 8065 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8066 sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config"); 8067 8068 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD, 8069 &pi->link_cfg.requested_caps, 0, "L1 config requested by driver"); 8070 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD, 8071 &pi->link_cfg.pcaps, 0, "port capabilities"); 8072 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD, 8073 &pi->link_cfg.acaps, 0, "advertised capabilities"); 8074 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD, 8075 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities"); 8076 8077 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 8078 port_top_speed(pi), "max speed (in Gbps)"); 8079 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 8080 pi->mps_bg_map, "MPS buffer group map"); 8081 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 8082 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 8083 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_chan", CTLFLAG_RD, NULL, 8084 pi->tx_chan, "TP tx c-channel"); 8085 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_chan", CTLFLAG_RD, NULL, 8086 pi->rx_chan, "TP rx c-channel"); 8087 8088 if (sc->flags & IS_VF) 8089 return; 8090 8091 /* 8092 * dev.(cxgbe|cxl).X.tc. 8093 */ 8094 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", 8095 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 8096 "Tx scheduler traffic classes (cl_rl)"); 8097 children2 = SYSCTL_CHILDREN(oid); 8098 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 8099 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 8100 "pktsize for per-flow cl-rl (0 means up to the driver )"); 8101 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 8102 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 8103 "burstsize for per-flow cl-rl (0 means up to the driver)"); 8104 for (i = 0; i < sc->params.nsched_cls; i++) { 8105 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 8106 8107 snprintf(name, sizeof(name), "%d", i); 8108 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 8109 SYSCTL_CHILDREN(oid), OID_AUTO, name, 8110 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class")); 8111 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state", 8112 CTLFLAG_RD, &tc->state, 0, "current state"); 8113 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 8114 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags, 8115 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags"); 8116 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 8117 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 8118 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 8119 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 8120 (pi->port_id << 16) | i, sysctl_tc_params, "A", 8121 "traffic class parameters"); 8122 } 8123 8124 /* 8125 * dev.cxgbe.X.stats. 8126 */ 8127 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 8128 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics"); 8129 children = SYSCTL_CHILDREN(oid); 8130 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 8131 &pi->tx_parse_error, 0, 8132 "# of tx packets with invalid length or # of segments"); 8133 8134 #define T4_REGSTAT(name, stat, desc) \ 8135 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \ 8136 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \ 8137 t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \ 8138 sysctl_handle_t4_reg64, "QU", desc) 8139 8140 /* We get these from port_stats and they may be stale by up to 1s */ 8141 #define T4_PORTSTAT(name, desc) \ 8142 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 8143 &pi->stats.name, desc) 8144 8145 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames"); 8146 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames"); 8147 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames"); 8148 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames"); 8149 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames"); 8150 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames"); 8151 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range"); 8152 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range"); 8153 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range"); 8154 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range"); 8155 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range"); 8156 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range"); 8157 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range"); 8158 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames"); 8159 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted"); 8160 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted"); 8161 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted"); 8162 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted"); 8163 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted"); 8164 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted"); 8165 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted"); 8166 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted"); 8167 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted"); 8168 8169 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames"); 8170 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames"); 8171 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames"); 8172 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames"); 8173 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames"); 8174 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU"); 8175 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames"); 8176 if (is_t6(sc)) { 8177 T4_PORTSTAT(rx_fcs_err, 8178 "# of frames received with bad FCS since last link up"); 8179 } else { 8180 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR, 8181 "# of frames received with bad FCS"); 8182 } 8183 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error"); 8184 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors"); 8185 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received"); 8186 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range"); 8187 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range"); 8188 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range"); 8189 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range"); 8190 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range"); 8191 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range"); 8192 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range"); 8193 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received"); 8194 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received"); 8195 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received"); 8196 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received"); 8197 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received"); 8198 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received"); 8199 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received"); 8200 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received"); 8201 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received"); 8202 8203 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows"); 8204 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows"); 8205 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows"); 8206 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows"); 8207 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets"); 8208 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets"); 8209 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets"); 8210 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets"); 8211 8212 #undef T4_REGSTAT 8213 #undef T4_PORTSTAT 8214 } 8215 8216 static int 8217 sysctl_int_array(SYSCTL_HANDLER_ARGS) 8218 { 8219 int rc, *i, space = 0; 8220 struct sbuf sb; 8221 8222 sbuf_new_for_sysctl(&sb, NULL, 64, req); 8223 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 8224 if (space) 8225 sbuf_printf(&sb, " "); 8226 sbuf_printf(&sb, "%d", *i); 8227 space = 1; 8228 } 8229 rc = sbuf_finish(&sb); 8230 sbuf_delete(&sb); 8231 return (rc); 8232 } 8233 8234 static int 8235 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 8236 { 8237 int rc; 8238 struct sbuf *sb; 8239 8240 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8241 if (sb == NULL) 8242 return (ENOMEM); 8243 8244 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 8245 rc = sbuf_finish(sb); 8246 sbuf_delete(sb); 8247 8248 return (rc); 8249 } 8250 8251 static int 8252 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 8253 { 8254 int rc; 8255 struct sbuf *sb; 8256 8257 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8258 if (sb == NULL) 8259 return (ENOMEM); 8260 8261 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 8262 rc = sbuf_finish(sb); 8263 sbuf_delete(sb); 8264 8265 return (rc); 8266 } 8267 8268 static int 8269 sysctl_btphy(SYSCTL_HANDLER_ARGS) 8270 { 8271 struct port_info *pi = arg1; 8272 int op = arg2; 8273 struct adapter *sc = pi->adapter; 8274 u_int v; 8275 int rc; 8276 8277 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 8278 if (rc) 8279 return (rc); 8280 if (hw_off_limits(sc)) 8281 rc = ENXIO; 8282 else { 8283 /* XXX: magic numbers */ 8284 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, 8285 op ? 0x20 : 0xc820, &v); 8286 } 8287 end_synchronized_op(sc, 0); 8288 if (rc) 8289 return (rc); 8290 if (op == 0) 8291 v /= 256; 8292 8293 rc = sysctl_handle_int(oidp, &v, 0, req); 8294 return (rc); 8295 } 8296 8297 static int 8298 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 8299 { 8300 struct vi_info *vi = arg1; 8301 int rc, val; 8302 8303 val = vi->rsrv_noflowq; 8304 rc = sysctl_handle_int(oidp, &val, 0, req); 8305 if (rc != 0 || req->newptr == NULL) 8306 return (rc); 8307 8308 if ((val >= 1) && (vi->ntxq > 1)) 8309 vi->rsrv_noflowq = 1; 8310 else 8311 vi->rsrv_noflowq = 0; 8312 8313 return (rc); 8314 } 8315 8316 static int 8317 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS) 8318 { 8319 struct vi_info *vi = arg1; 8320 struct adapter *sc = vi->adapter; 8321 int rc, val, i; 8322 8323 MPASS(!(sc->flags & IS_VF)); 8324 8325 val = vi->flags & TX_USES_VM_WR ? 1 : 0; 8326 rc = sysctl_handle_int(oidp, &val, 0, req); 8327 if (rc != 0 || req->newptr == NULL) 8328 return (rc); 8329 8330 if (val != 0 && val != 1) 8331 return (EINVAL); 8332 8333 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8334 "t4txvm"); 8335 if (rc) 8336 return (rc); 8337 if (hw_off_limits(sc)) 8338 rc = ENXIO; 8339 else if (if_getdrvflags(vi->ifp) & IFF_DRV_RUNNING) { 8340 /* 8341 * We don't want parse_pkt to run with one setting (VF or PF) 8342 * and then eth_tx to see a different setting but still use 8343 * stale information calculated by parse_pkt. 8344 */ 8345 rc = EBUSY; 8346 } else { 8347 struct port_info *pi = vi->pi; 8348 struct sge_txq *txq; 8349 uint32_t ctrl0; 8350 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr; 8351 8352 if (val) { 8353 vi->flags |= TX_USES_VM_WR; 8354 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO); 8355 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8356 V_TXPKT_INTF(pi->tx_chan)); 8357 if (!(sc->flags & IS_VF)) 8358 npkt--; 8359 } else { 8360 vi->flags &= ~TX_USES_VM_WR; 8361 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO); 8362 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8363 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 8364 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 8365 } 8366 for_each_txq(vi, i, txq) { 8367 txq->cpl_ctrl0 = ctrl0; 8368 txq->txp.max_npkt = npkt; 8369 } 8370 } 8371 end_synchronized_op(sc, LOCK_HELD); 8372 return (rc); 8373 } 8374 8375 static int 8376 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 8377 { 8378 struct vi_info *vi = arg1; 8379 struct adapter *sc = vi->adapter; 8380 int idx, rc, i; 8381 struct sge_rxq *rxq; 8382 uint8_t v; 8383 8384 idx = vi->tmr_idx; 8385 8386 rc = sysctl_handle_int(oidp, &idx, 0, req); 8387 if (rc != 0 || req->newptr == NULL) 8388 return (rc); 8389 8390 if (idx < 0 || idx >= SGE_NTIMERS) 8391 return (EINVAL); 8392 8393 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8394 "t4tmr"); 8395 if (rc) 8396 return (rc); 8397 8398 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 8399 for_each_rxq(vi, i, rxq) { 8400 #ifdef atomic_store_rel_8 8401 atomic_store_rel_8(&rxq->iq.intr_params, v); 8402 #else 8403 rxq->iq.intr_params = v; 8404 #endif 8405 } 8406 vi->tmr_idx = idx; 8407 8408 end_synchronized_op(sc, LOCK_HELD); 8409 return (0); 8410 } 8411 8412 static int 8413 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 8414 { 8415 struct vi_info *vi = arg1; 8416 struct adapter *sc = vi->adapter; 8417 int idx, rc; 8418 8419 idx = vi->pktc_idx; 8420 8421 rc = sysctl_handle_int(oidp, &idx, 0, req); 8422 if (rc != 0 || req->newptr == NULL) 8423 return (rc); 8424 8425 if (idx < -1 || idx >= SGE_NCOUNTERS) 8426 return (EINVAL); 8427 8428 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8429 "t4pktc"); 8430 if (rc) 8431 return (rc); 8432 8433 if (vi->flags & VI_INIT_DONE) 8434 rc = EBUSY; /* cannot be changed once the queues are created */ 8435 else 8436 vi->pktc_idx = idx; 8437 8438 end_synchronized_op(sc, LOCK_HELD); 8439 return (rc); 8440 } 8441 8442 static int 8443 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 8444 { 8445 struct vi_info *vi = arg1; 8446 struct adapter *sc = vi->adapter; 8447 int qsize, rc; 8448 8449 qsize = vi->qsize_rxq; 8450 8451 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8452 if (rc != 0 || req->newptr == NULL) 8453 return (rc); 8454 8455 if (qsize < 128 || (qsize & 7)) 8456 return (EINVAL); 8457 8458 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8459 "t4rxqs"); 8460 if (rc) 8461 return (rc); 8462 8463 if (vi->flags & VI_INIT_DONE) 8464 rc = EBUSY; /* cannot be changed once the queues are created */ 8465 else 8466 vi->qsize_rxq = qsize; 8467 8468 end_synchronized_op(sc, LOCK_HELD); 8469 return (rc); 8470 } 8471 8472 static int 8473 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 8474 { 8475 struct vi_info *vi = arg1; 8476 struct adapter *sc = vi->adapter; 8477 int qsize, rc; 8478 8479 qsize = vi->qsize_txq; 8480 8481 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8482 if (rc != 0 || req->newptr == NULL) 8483 return (rc); 8484 8485 if (qsize < 128 || qsize > 65536) 8486 return (EINVAL); 8487 8488 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8489 "t4txqs"); 8490 if (rc) 8491 return (rc); 8492 8493 if (vi->flags & VI_INIT_DONE) 8494 rc = EBUSY; /* cannot be changed once the queues are created */ 8495 else 8496 vi->qsize_txq = qsize; 8497 8498 end_synchronized_op(sc, LOCK_HELD); 8499 return (rc); 8500 } 8501 8502 static int 8503 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 8504 { 8505 struct port_info *pi = arg1; 8506 struct adapter *sc = pi->adapter; 8507 struct link_config *lc = &pi->link_cfg; 8508 int rc; 8509 8510 if (req->newptr == NULL) { 8511 struct sbuf *sb; 8512 static char *bits = "\20\1RX\2TX\3AUTO"; 8513 8514 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8515 if (sb == NULL) 8516 return (ENOMEM); 8517 8518 if (lc->link_ok) { 8519 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 8520 (lc->requested_fc & PAUSE_AUTONEG), bits); 8521 } else { 8522 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 8523 PAUSE_RX | PAUSE_AUTONEG), bits); 8524 } 8525 rc = sbuf_finish(sb); 8526 sbuf_delete(sb); 8527 } else { 8528 char s[2]; 8529 int n; 8530 8531 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 8532 PAUSE_AUTONEG)); 8533 s[1] = 0; 8534 8535 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8536 if (rc != 0) 8537 return(rc); 8538 8539 if (s[1] != 0) 8540 return (EINVAL); 8541 if (s[0] < '0' || s[0] > '9') 8542 return (EINVAL); /* not a number */ 8543 n = s[0] - '0'; 8544 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 8545 return (EINVAL); /* some other bit is set too */ 8546 8547 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8548 "t4PAUSE"); 8549 if (rc) 8550 return (rc); 8551 if (!hw_off_limits(sc)) { 8552 PORT_LOCK(pi); 8553 lc->requested_fc = n; 8554 fixup_link_config(pi); 8555 if (pi->up_vis > 0) 8556 rc = apply_link_config(pi); 8557 set_current_media(pi); 8558 PORT_UNLOCK(pi); 8559 } 8560 end_synchronized_op(sc, 0); 8561 } 8562 8563 return (rc); 8564 } 8565 8566 static int 8567 sysctl_link_fec(SYSCTL_HANDLER_ARGS) 8568 { 8569 struct port_info *pi = arg1; 8570 struct link_config *lc = &pi->link_cfg; 8571 int rc; 8572 struct sbuf *sb; 8573 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2"; 8574 8575 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8576 if (sb == NULL) 8577 return (ENOMEM); 8578 if (lc->link_ok) 8579 sbuf_printf(sb, "%b", lc->fec, bits); 8580 else 8581 sbuf_printf(sb, "no link"); 8582 rc = sbuf_finish(sb); 8583 sbuf_delete(sb); 8584 8585 return (rc); 8586 } 8587 8588 static int 8589 sysctl_requested_fec(SYSCTL_HANDLER_ARGS) 8590 { 8591 struct port_info *pi = arg1; 8592 struct adapter *sc = pi->adapter; 8593 struct link_config *lc = &pi->link_cfg; 8594 int rc; 8595 int8_t old; 8596 8597 if (req->newptr == NULL) { 8598 struct sbuf *sb; 8599 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2" 8600 "\5RSVD3\6auto\7module"; 8601 8602 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8603 if (sb == NULL) 8604 return (ENOMEM); 8605 8606 sbuf_printf(sb, "%b", lc->requested_fec, bits); 8607 rc = sbuf_finish(sb); 8608 sbuf_delete(sb); 8609 } else { 8610 char s[8]; 8611 int n; 8612 8613 snprintf(s, sizeof(s), "%d", 8614 lc->requested_fec == FEC_AUTO ? -1 : 8615 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE)); 8616 8617 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8618 if (rc != 0) 8619 return(rc); 8620 8621 n = strtol(&s[0], NULL, 0); 8622 if (n < 0 || n & FEC_AUTO) 8623 n = FEC_AUTO; 8624 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE)) 8625 return (EINVAL);/* some other bit is set too */ 8626 8627 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8628 "t4reqf"); 8629 if (rc) 8630 return (rc); 8631 PORT_LOCK(pi); 8632 old = lc->requested_fec; 8633 if (n == FEC_AUTO) 8634 lc->requested_fec = FEC_AUTO; 8635 else if (n == 0 || n == FEC_NONE) 8636 lc->requested_fec = FEC_NONE; 8637 else { 8638 if ((lc->pcaps | 8639 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) != 8640 lc->pcaps) { 8641 rc = ENOTSUP; 8642 goto done; 8643 } 8644 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC | 8645 FEC_MODULE); 8646 } 8647 if (!hw_off_limits(sc)) { 8648 fixup_link_config(pi); 8649 if (pi->up_vis > 0) { 8650 rc = apply_link_config(pi); 8651 if (rc != 0) { 8652 lc->requested_fec = old; 8653 if (rc == FW_EPROTO) 8654 rc = ENOTSUP; 8655 } 8656 } 8657 } 8658 done: 8659 PORT_UNLOCK(pi); 8660 end_synchronized_op(sc, 0); 8661 } 8662 8663 return (rc); 8664 } 8665 8666 static int 8667 sysctl_module_fec(SYSCTL_HANDLER_ARGS) 8668 { 8669 struct port_info *pi = arg1; 8670 struct adapter *sc = pi->adapter; 8671 struct link_config *lc = &pi->link_cfg; 8672 int rc; 8673 int8_t fec; 8674 struct sbuf *sb; 8675 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3"; 8676 8677 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8678 if (sb == NULL) 8679 return (ENOMEM); 8680 8681 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) { 8682 rc = EBUSY; 8683 goto done; 8684 } 8685 if (hw_off_limits(sc)) { 8686 rc = ENXIO; 8687 goto done; 8688 } 8689 PORT_LOCK(pi); 8690 if (pi->up_vis == 0) { 8691 /* 8692 * If all the interfaces are administratively down the firmware 8693 * does not report transceiver changes. Refresh port info here. 8694 * This is the only reason we have a synchronized op in this 8695 * function. Just PORT_LOCK would have been enough otherwise. 8696 */ 8697 t4_update_port_info(pi); 8698 } 8699 8700 fec = lc->fec_hint; 8701 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE || 8702 !fec_supported(lc->pcaps)) { 8703 PORT_UNLOCK(pi); 8704 sbuf_printf(sb, "n/a"); 8705 } else { 8706 if (fec == 0) 8707 fec = FEC_NONE; 8708 PORT_UNLOCK(pi); 8709 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits); 8710 } 8711 rc = sbuf_finish(sb); 8712 done: 8713 sbuf_delete(sb); 8714 end_synchronized_op(sc, 0); 8715 8716 return (rc); 8717 } 8718 8719 static int 8720 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 8721 { 8722 struct port_info *pi = arg1; 8723 struct adapter *sc = pi->adapter; 8724 struct link_config *lc = &pi->link_cfg; 8725 int rc, val; 8726 8727 if (lc->pcaps & FW_PORT_CAP32_ANEG) 8728 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 8729 else 8730 val = -1; 8731 rc = sysctl_handle_int(oidp, &val, 0, req); 8732 if (rc != 0 || req->newptr == NULL) 8733 return (rc); 8734 if (val == 0) 8735 val = AUTONEG_DISABLE; 8736 else if (val == 1) 8737 val = AUTONEG_ENABLE; 8738 else 8739 val = AUTONEG_AUTO; 8740 8741 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8742 "t4aneg"); 8743 if (rc) 8744 return (rc); 8745 PORT_LOCK(pi); 8746 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 8747 rc = ENOTSUP; 8748 goto done; 8749 } 8750 lc->requested_aneg = val; 8751 if (!hw_off_limits(sc)) { 8752 fixup_link_config(pi); 8753 if (pi->up_vis > 0) 8754 rc = apply_link_config(pi); 8755 set_current_media(pi); 8756 } 8757 done: 8758 PORT_UNLOCK(pi); 8759 end_synchronized_op(sc, 0); 8760 return (rc); 8761 } 8762 8763 static int 8764 sysctl_force_fec(SYSCTL_HANDLER_ARGS) 8765 { 8766 struct port_info *pi = arg1; 8767 struct adapter *sc = pi->adapter; 8768 struct link_config *lc = &pi->link_cfg; 8769 int rc, val; 8770 8771 val = lc->force_fec; 8772 MPASS(val >= -1 && val <= 1); 8773 rc = sysctl_handle_int(oidp, &val, 0, req); 8774 if (rc != 0 || req->newptr == NULL) 8775 return (rc); 8776 if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC)) 8777 return (ENOTSUP); 8778 if (val < -1 || val > 1) 8779 return (EINVAL); 8780 8781 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff"); 8782 if (rc) 8783 return (rc); 8784 PORT_LOCK(pi); 8785 lc->force_fec = val; 8786 if (!hw_off_limits(sc)) { 8787 fixup_link_config(pi); 8788 if (pi->up_vis > 0) 8789 rc = apply_link_config(pi); 8790 } 8791 PORT_UNLOCK(pi); 8792 end_synchronized_op(sc, 0); 8793 return (rc); 8794 } 8795 8796 static int 8797 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 8798 { 8799 struct adapter *sc = arg1; 8800 int rc, reg = arg2; 8801 uint64_t val; 8802 8803 mtx_lock(&sc->reg_lock); 8804 if (hw_off_limits(sc)) 8805 rc = ENXIO; 8806 else { 8807 rc = 0; 8808 val = t4_read_reg64(sc, reg); 8809 } 8810 mtx_unlock(&sc->reg_lock); 8811 if (rc == 0) 8812 rc = sysctl_handle_64(oidp, &val, 0, req); 8813 return (rc); 8814 } 8815 8816 static int 8817 sysctl_temperature(SYSCTL_HANDLER_ARGS) 8818 { 8819 struct adapter *sc = arg1; 8820 int rc, t; 8821 uint32_t param, val; 8822 8823 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 8824 if (rc) 8825 return (rc); 8826 if (hw_off_limits(sc)) 8827 rc = ENXIO; 8828 else { 8829 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8830 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8831 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 8832 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8833 } 8834 end_synchronized_op(sc, 0); 8835 if (rc) 8836 return (rc); 8837 8838 /* unknown is returned as 0 but we display -1 in that case */ 8839 t = val == 0 ? -1 : val; 8840 8841 rc = sysctl_handle_int(oidp, &t, 0, req); 8842 return (rc); 8843 } 8844 8845 static int 8846 sysctl_vdd(SYSCTL_HANDLER_ARGS) 8847 { 8848 struct adapter *sc = arg1; 8849 int rc; 8850 uint32_t param, val; 8851 8852 if (sc->params.core_vdd == 0) { 8853 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8854 "t4vdd"); 8855 if (rc) 8856 return (rc); 8857 if (hw_off_limits(sc)) 8858 rc = ENXIO; 8859 else { 8860 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8861 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8862 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 8863 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, 8864 ¶m, &val); 8865 } 8866 end_synchronized_op(sc, 0); 8867 if (rc) 8868 return (rc); 8869 sc->params.core_vdd = val; 8870 } 8871 8872 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req)); 8873 } 8874 8875 static int 8876 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS) 8877 { 8878 struct adapter *sc = arg1; 8879 int rc, v; 8880 uint32_t param, val; 8881 8882 v = sc->sensor_resets; 8883 rc = sysctl_handle_int(oidp, &v, 0, req); 8884 if (rc != 0 || req->newptr == NULL || v <= 0) 8885 return (rc); 8886 8887 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) || 8888 chip_id(sc) < CHELSIO_T5) 8889 return (ENOTSUP); 8890 8891 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst"); 8892 if (rc) 8893 return (rc); 8894 if (hw_off_limits(sc)) 8895 rc = ENXIO; 8896 else { 8897 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8898 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8899 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR)); 8900 val = 1; 8901 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8902 } 8903 end_synchronized_op(sc, 0); 8904 if (rc == 0) 8905 sc->sensor_resets++; 8906 return (rc); 8907 } 8908 8909 static int 8910 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 8911 { 8912 struct adapter *sc = arg1; 8913 struct sbuf *sb; 8914 int rc; 8915 uint32_t param, val; 8916 8917 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 8918 if (rc) 8919 return (rc); 8920 if (hw_off_limits(sc)) 8921 rc = ENXIO; 8922 else { 8923 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8924 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 8925 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8926 } 8927 end_synchronized_op(sc, 0); 8928 if (rc) 8929 return (rc); 8930 8931 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8932 if (sb == NULL) 8933 return (ENOMEM); 8934 8935 if (val == 0xffffffff) { 8936 /* Only debug and custom firmwares report load averages. */ 8937 sbuf_printf(sb, "not available"); 8938 } else { 8939 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 8940 (val >> 16) & 0xff); 8941 } 8942 rc = sbuf_finish(sb); 8943 sbuf_delete(sb); 8944 8945 return (rc); 8946 } 8947 8948 static int 8949 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 8950 { 8951 struct adapter *sc = arg1; 8952 struct sbuf *sb; 8953 int rc, i; 8954 uint16_t incr[NMTUS][NCCTRL_WIN]; 8955 static const char *dec_fac[] = { 8956 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 8957 "0.9375" 8958 }; 8959 8960 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8961 if (sb == NULL) 8962 return (ENOMEM); 8963 8964 rc = 0; 8965 mtx_lock(&sc->reg_lock); 8966 if (hw_off_limits(sc)) 8967 rc = ENXIO; 8968 else 8969 t4_read_cong_tbl(sc, incr); 8970 mtx_unlock(&sc->reg_lock); 8971 if (rc) 8972 goto done; 8973 8974 for (i = 0; i < NCCTRL_WIN; ++i) { 8975 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 8976 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 8977 incr[5][i], incr[6][i], incr[7][i]); 8978 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 8979 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 8980 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 8981 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 8982 } 8983 8984 rc = sbuf_finish(sb); 8985 done: 8986 sbuf_delete(sb); 8987 return (rc); 8988 } 8989 8990 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 8991 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 8992 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 8993 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 8994 }; 8995 8996 static int 8997 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 8998 { 8999 struct adapter *sc = arg1; 9000 struct sbuf *sb; 9001 int rc, i, n, qid = arg2; 9002 uint32_t *buf, *p; 9003 char *qtype; 9004 u_int cim_num_obq = sc->chip_params->cim_num_obq; 9005 9006 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 9007 ("%s: bad qid %d\n", __func__, qid)); 9008 9009 if (qid < CIM_NUM_IBQ) { 9010 /* inbound queue */ 9011 qtype = "IBQ"; 9012 n = 4 * CIM_IBQ_SIZE; 9013 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 9014 mtx_lock(&sc->reg_lock); 9015 if (hw_off_limits(sc)) 9016 rc = -ENXIO; 9017 else 9018 rc = t4_read_cim_ibq(sc, qid, buf, n); 9019 mtx_unlock(&sc->reg_lock); 9020 } else { 9021 /* outbound queue */ 9022 qtype = "OBQ"; 9023 qid -= CIM_NUM_IBQ; 9024 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 9025 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 9026 mtx_lock(&sc->reg_lock); 9027 if (hw_off_limits(sc)) 9028 rc = -ENXIO; 9029 else 9030 rc = t4_read_cim_obq(sc, qid, buf, n); 9031 mtx_unlock(&sc->reg_lock); 9032 } 9033 9034 if (rc < 0) { 9035 rc = -rc; 9036 goto done; 9037 } 9038 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 9039 9040 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9041 if (sb == NULL) { 9042 rc = ENOMEM; 9043 goto done; 9044 } 9045 9046 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 9047 for (i = 0, p = buf; i < n; i += 16, p += 4) 9048 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 9049 p[2], p[3]); 9050 9051 rc = sbuf_finish(sb); 9052 sbuf_delete(sb); 9053 done: 9054 free(buf, M_CXGBE); 9055 return (rc); 9056 } 9057 9058 static void 9059 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9060 { 9061 uint32_t *p; 9062 9063 sbuf_printf(sb, "Status Data PC%s", 9064 cfg & F_UPDBGLACAPTPCONLY ? "" : 9065 " LS0Stat LS0Addr LS0Data"); 9066 9067 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 9068 if (cfg & F_UPDBGLACAPTPCONLY) { 9069 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 9070 p[6], p[7]); 9071 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 9072 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 9073 p[4] & 0xff, p[5] >> 8); 9074 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 9075 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9076 p[1] & 0xf, p[2] >> 4); 9077 } else { 9078 sbuf_printf(sb, 9079 "\n %02x %x%07x %x%07x %08x %08x " 9080 "%08x%08x%08x%08x", 9081 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9082 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 9083 p[6], p[7]); 9084 } 9085 } 9086 } 9087 9088 static void 9089 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9090 { 9091 uint32_t *p; 9092 9093 sbuf_printf(sb, "Status Inst Data PC%s", 9094 cfg & F_UPDBGLACAPTPCONLY ? "" : 9095 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 9096 9097 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 9098 if (cfg & F_UPDBGLACAPTPCONLY) { 9099 sbuf_printf(sb, "\n %02x %08x %08x %08x", 9100 p[3] & 0xff, p[2], p[1], p[0]); 9101 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 9102 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 9103 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 9104 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 9105 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 9106 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 9107 p[6] >> 16); 9108 } else { 9109 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 9110 "%08x %08x %08x %08x %08x %08x", 9111 (p[9] >> 16) & 0xff, 9112 p[9] & 0xffff, p[8] >> 16, 9113 p[8] & 0xffff, p[7] >> 16, 9114 p[7] & 0xffff, p[6] >> 16, 9115 p[2], p[1], p[0], p[5], p[4], p[3]); 9116 } 9117 } 9118 } 9119 9120 static int 9121 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 9122 { 9123 uint32_t cfg, *buf; 9124 int rc; 9125 9126 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9127 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 9128 M_ZERO | flags); 9129 if (buf == NULL) 9130 return (ENOMEM); 9131 9132 mtx_lock(&sc->reg_lock); 9133 if (hw_off_limits(sc)) 9134 rc = ENXIO; 9135 else { 9136 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9137 if (rc == 0) 9138 rc = -t4_cim_read_la(sc, buf, NULL); 9139 } 9140 mtx_unlock(&sc->reg_lock); 9141 if (rc == 0) { 9142 if (chip_id(sc) < CHELSIO_T6) 9143 sbuf_cim_la4(sc, sb, buf, cfg); 9144 else 9145 sbuf_cim_la6(sc, sb, buf, cfg); 9146 } 9147 free(buf, M_CXGBE); 9148 return (rc); 9149 } 9150 9151 static int 9152 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 9153 { 9154 struct adapter *sc = arg1; 9155 struct sbuf *sb; 9156 int rc; 9157 9158 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9159 if (sb == NULL) 9160 return (ENOMEM); 9161 9162 rc = sbuf_cim_la(sc, sb, M_WAITOK); 9163 if (rc == 0) 9164 rc = sbuf_finish(sb); 9165 sbuf_delete(sb); 9166 return (rc); 9167 } 9168 9169 static void 9170 dump_cim_regs(struct adapter *sc) 9171 { 9172 log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n", 9173 device_get_nameunit(sc->dev), 9174 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9175 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9176 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2), 9177 t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN), 9178 t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA)); 9179 log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n", 9180 device_get_nameunit(sc->dev), 9181 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9182 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9183 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800), 9184 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800), 9185 t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN)); 9186 } 9187 9188 static void 9189 dump_cimla(struct adapter *sc) 9190 { 9191 struct sbuf sb; 9192 int rc; 9193 9194 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9195 log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n", 9196 device_get_nameunit(sc->dev)); 9197 return; 9198 } 9199 rc = sbuf_cim_la(sc, &sb, M_WAITOK); 9200 if (rc == 0) { 9201 rc = sbuf_finish(&sb); 9202 if (rc == 0) { 9203 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n", 9204 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9205 } 9206 } 9207 sbuf_delete(&sb); 9208 } 9209 9210 void 9211 t4_os_cim_err(struct adapter *sc) 9212 { 9213 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 9214 } 9215 9216 static int 9217 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 9218 { 9219 struct adapter *sc = arg1; 9220 u_int i; 9221 struct sbuf *sb; 9222 uint32_t *buf, *p; 9223 int rc; 9224 9225 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9226 if (sb == NULL) 9227 return (ENOMEM); 9228 9229 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 9230 M_ZERO | M_WAITOK); 9231 9232 rc = 0; 9233 mtx_lock(&sc->reg_lock); 9234 if (hw_off_limits(sc)) 9235 rc = ENXIO; 9236 else 9237 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 9238 mtx_unlock(&sc->reg_lock); 9239 if (rc) 9240 goto done; 9241 9242 p = buf; 9243 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9244 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 9245 p[1], p[0]); 9246 } 9247 9248 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 9249 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9250 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 9251 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 9252 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 9253 (p[1] >> 2) | ((p[2] & 3) << 30), 9254 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 9255 p[0] & 1); 9256 } 9257 rc = sbuf_finish(sb); 9258 done: 9259 sbuf_delete(sb); 9260 free(buf, M_CXGBE); 9261 return (rc); 9262 } 9263 9264 static int 9265 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 9266 { 9267 struct adapter *sc = arg1; 9268 u_int i; 9269 struct sbuf *sb; 9270 uint32_t *buf, *p; 9271 int rc; 9272 9273 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9274 if (sb == NULL) 9275 return (ENOMEM); 9276 9277 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 9278 M_ZERO | M_WAITOK); 9279 9280 rc = 0; 9281 mtx_lock(&sc->reg_lock); 9282 if (hw_off_limits(sc)) 9283 rc = ENXIO; 9284 else 9285 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 9286 mtx_unlock(&sc->reg_lock); 9287 if (rc) 9288 goto done; 9289 9290 p = buf; 9291 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 9292 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9293 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 9294 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 9295 p[4], p[3], p[2], p[1], p[0]); 9296 } 9297 9298 sbuf_printf(sb, "\n\nCntl ID Data"); 9299 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9300 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 9301 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 9302 } 9303 9304 rc = sbuf_finish(sb); 9305 done: 9306 sbuf_delete(sb); 9307 free(buf, M_CXGBE); 9308 return (rc); 9309 } 9310 9311 static int 9312 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 9313 { 9314 struct adapter *sc = arg1; 9315 struct sbuf *sb; 9316 int rc, i; 9317 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9318 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9319 uint16_t thres[CIM_NUM_IBQ]; 9320 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 9321 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 9322 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 9323 9324 cim_num_obq = sc->chip_params->cim_num_obq; 9325 if (is_t4(sc)) { 9326 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 9327 obq_rdaddr = A_UP_OBQ_0_REALADDR; 9328 } else { 9329 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 9330 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 9331 } 9332 nq = CIM_NUM_IBQ + cim_num_obq; 9333 9334 mtx_lock(&sc->reg_lock); 9335 if (hw_off_limits(sc)) 9336 rc = ENXIO; 9337 else { 9338 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 9339 if (rc == 0) { 9340 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, 9341 obq_wr); 9342 if (rc == 0) 9343 t4_read_cimq_cfg(sc, base, size, thres); 9344 } 9345 } 9346 mtx_unlock(&sc->reg_lock); 9347 if (rc) 9348 return (rc); 9349 9350 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9351 if (sb == NULL) 9352 return (ENOMEM); 9353 9354 sbuf_printf(sb, 9355 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 9356 9357 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 9358 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 9359 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 9360 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9361 G_QUEREMFLITS(p[2]) * 16); 9362 for ( ; i < nq; i++, p += 4, wr += 2) 9363 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 9364 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 9365 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9366 G_QUEREMFLITS(p[2]) * 16); 9367 9368 rc = sbuf_finish(sb); 9369 sbuf_delete(sb); 9370 9371 return (rc); 9372 } 9373 9374 static int 9375 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 9376 { 9377 struct adapter *sc = arg1; 9378 struct sbuf *sb; 9379 int rc; 9380 struct tp_cpl_stats stats; 9381 9382 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9383 if (sb == NULL) 9384 return (ENOMEM); 9385 9386 rc = 0; 9387 mtx_lock(&sc->reg_lock); 9388 if (hw_off_limits(sc)) 9389 rc = ENXIO; 9390 else 9391 t4_tp_get_cpl_stats(sc, &stats, 0); 9392 mtx_unlock(&sc->reg_lock); 9393 if (rc) 9394 goto done; 9395 9396 if (sc->chip_params->nchan > 2) { 9397 sbuf_printf(sb, " channel 0 channel 1" 9398 " channel 2 channel 3"); 9399 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 9400 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 9401 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 9402 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 9403 } else { 9404 sbuf_printf(sb, " channel 0 channel 1"); 9405 sbuf_printf(sb, "\nCPL requests: %10u %10u", 9406 stats.req[0], stats.req[1]); 9407 sbuf_printf(sb, "\nCPL responses: %10u %10u", 9408 stats.rsp[0], stats.rsp[1]); 9409 } 9410 9411 rc = sbuf_finish(sb); 9412 done: 9413 sbuf_delete(sb); 9414 return (rc); 9415 } 9416 9417 static int 9418 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 9419 { 9420 struct adapter *sc = arg1; 9421 struct sbuf *sb; 9422 int rc; 9423 struct tp_usm_stats stats; 9424 9425 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9426 if (sb == NULL) 9427 return (ENOMEM); 9428 9429 rc = 0; 9430 mtx_lock(&sc->reg_lock); 9431 if (hw_off_limits(sc)) 9432 rc = ENXIO; 9433 else 9434 t4_get_usm_stats(sc, &stats, 1); 9435 mtx_unlock(&sc->reg_lock); 9436 if (rc == 0) { 9437 sbuf_printf(sb, "Frames: %u\n", stats.frames); 9438 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 9439 sbuf_printf(sb, "Drops: %u", stats.drops); 9440 rc = sbuf_finish(sb); 9441 } 9442 sbuf_delete(sb); 9443 9444 return (rc); 9445 } 9446 9447 static int 9448 sysctl_tid_stats(SYSCTL_HANDLER_ARGS) 9449 { 9450 struct adapter *sc = arg1; 9451 struct sbuf *sb; 9452 int rc; 9453 struct tp_tid_stats stats; 9454 9455 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9456 if (sb == NULL) 9457 return (ENOMEM); 9458 9459 rc = 0; 9460 mtx_lock(&sc->reg_lock); 9461 if (hw_off_limits(sc)) 9462 rc = ENXIO; 9463 else 9464 t4_tp_get_tid_stats(sc, &stats, 1); 9465 mtx_unlock(&sc->reg_lock); 9466 if (rc == 0) { 9467 sbuf_printf(sb, "Delete: %u\n", stats.del); 9468 sbuf_printf(sb, "Invalidate: %u\n", stats.inv); 9469 sbuf_printf(sb, "Active: %u\n", stats.act); 9470 sbuf_printf(sb, "Passive: %u", stats.pas); 9471 rc = sbuf_finish(sb); 9472 } 9473 sbuf_delete(sb); 9474 9475 return (rc); 9476 } 9477 9478 static const char * const devlog_level_strings[] = { 9479 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 9480 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 9481 [FW_DEVLOG_LEVEL_ERR] = "ERR", 9482 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 9483 [FW_DEVLOG_LEVEL_INFO] = "INFO", 9484 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 9485 }; 9486 9487 static const char * const devlog_facility_strings[] = { 9488 [FW_DEVLOG_FACILITY_CORE] = "CORE", 9489 [FW_DEVLOG_FACILITY_CF] = "CF", 9490 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 9491 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 9492 [FW_DEVLOG_FACILITY_RES] = "RES", 9493 [FW_DEVLOG_FACILITY_HW] = "HW", 9494 [FW_DEVLOG_FACILITY_FLR] = "FLR", 9495 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 9496 [FW_DEVLOG_FACILITY_PHY] = "PHY", 9497 [FW_DEVLOG_FACILITY_MAC] = "MAC", 9498 [FW_DEVLOG_FACILITY_PORT] = "PORT", 9499 [FW_DEVLOG_FACILITY_VI] = "VI", 9500 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 9501 [FW_DEVLOG_FACILITY_ACL] = "ACL", 9502 [FW_DEVLOG_FACILITY_TM] = "TM", 9503 [FW_DEVLOG_FACILITY_QFC] = "QFC", 9504 [FW_DEVLOG_FACILITY_DCB] = "DCB", 9505 [FW_DEVLOG_FACILITY_ETH] = "ETH", 9506 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 9507 [FW_DEVLOG_FACILITY_RI] = "RI", 9508 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 9509 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 9510 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 9511 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 9512 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 9513 }; 9514 9515 static int 9516 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 9517 { 9518 int i, j, rc, nentries, first = 0; 9519 struct devlog_params *dparams = &sc->params.devlog; 9520 struct fw_devlog_e *buf, *e; 9521 uint64_t ftstamp = UINT64_MAX; 9522 9523 if (dparams->addr == 0) 9524 return (ENXIO); 9525 9526 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9527 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 9528 if (buf == NULL) 9529 return (ENOMEM); 9530 9531 mtx_lock(&sc->reg_lock); 9532 if (hw_off_limits(sc)) 9533 rc = ENXIO; 9534 else 9535 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, 9536 dparams->size); 9537 mtx_unlock(&sc->reg_lock); 9538 if (rc != 0) 9539 goto done; 9540 9541 nentries = dparams->size / sizeof(struct fw_devlog_e); 9542 for (i = 0; i < nentries; i++) { 9543 e = &buf[i]; 9544 9545 if (e->timestamp == 0) 9546 break; /* end */ 9547 9548 e->timestamp = be64toh(e->timestamp); 9549 e->seqno = be32toh(e->seqno); 9550 for (j = 0; j < 8; j++) 9551 e->params[j] = be32toh(e->params[j]); 9552 9553 if (e->timestamp < ftstamp) { 9554 ftstamp = e->timestamp; 9555 first = i; 9556 } 9557 } 9558 9559 if (buf[first].timestamp == 0) 9560 goto done; /* nothing in the log */ 9561 9562 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 9563 "Seq#", "Tstamp", "Level", "Facility", "Message"); 9564 9565 i = first; 9566 do { 9567 e = &buf[i]; 9568 if (e->timestamp == 0) 9569 break; /* end */ 9570 9571 sbuf_printf(sb, "%10d %15ju %8s %8s ", 9572 e->seqno, e->timestamp, 9573 (e->level < nitems(devlog_level_strings) ? 9574 devlog_level_strings[e->level] : "UNKNOWN"), 9575 (e->facility < nitems(devlog_facility_strings) ? 9576 devlog_facility_strings[e->facility] : "UNKNOWN")); 9577 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 9578 e->params[2], e->params[3], e->params[4], 9579 e->params[5], e->params[6], e->params[7]); 9580 9581 if (++i == nentries) 9582 i = 0; 9583 } while (i != first); 9584 done: 9585 free(buf, M_CXGBE); 9586 return (rc); 9587 } 9588 9589 static int 9590 sysctl_devlog(SYSCTL_HANDLER_ARGS) 9591 { 9592 struct adapter *sc = arg1; 9593 int rc; 9594 struct sbuf *sb; 9595 9596 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9597 if (sb == NULL) 9598 return (ENOMEM); 9599 9600 rc = sbuf_devlog(sc, sb, M_WAITOK); 9601 if (rc == 0) 9602 rc = sbuf_finish(sb); 9603 sbuf_delete(sb); 9604 return (rc); 9605 } 9606 9607 static void 9608 dump_devlog(struct adapter *sc) 9609 { 9610 int rc; 9611 struct sbuf sb; 9612 9613 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9614 log(LOG_DEBUG, "%s: failed to generate devlog dump.\n", 9615 device_get_nameunit(sc->dev)); 9616 return; 9617 } 9618 rc = sbuf_devlog(sc, &sb, M_WAITOK); 9619 if (rc == 0) { 9620 rc = sbuf_finish(&sb); 9621 if (rc == 0) { 9622 log(LOG_DEBUG, "%s: device log follows.\n%s", 9623 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9624 } 9625 } 9626 sbuf_delete(&sb); 9627 } 9628 9629 static int 9630 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 9631 { 9632 struct adapter *sc = arg1; 9633 struct sbuf *sb; 9634 int rc; 9635 struct tp_fcoe_stats stats[MAX_NCHAN]; 9636 int i, nchan = sc->chip_params->nchan; 9637 9638 rc = 0; 9639 mtx_lock(&sc->reg_lock); 9640 if (hw_off_limits(sc)) 9641 rc = ENXIO; 9642 else { 9643 for (i = 0; i < nchan; i++) 9644 t4_get_fcoe_stats(sc, i, &stats[i], 1); 9645 } 9646 mtx_unlock(&sc->reg_lock); 9647 if (rc != 0) 9648 return (rc); 9649 9650 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9651 if (sb == NULL) 9652 return (ENOMEM); 9653 9654 if (nchan > 2) { 9655 sbuf_printf(sb, " channel 0 channel 1" 9656 " channel 2 channel 3"); 9657 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 9658 stats[0].octets_ddp, stats[1].octets_ddp, 9659 stats[2].octets_ddp, stats[3].octets_ddp); 9660 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 9661 stats[0].frames_ddp, stats[1].frames_ddp, 9662 stats[2].frames_ddp, stats[3].frames_ddp); 9663 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 9664 stats[0].frames_drop, stats[1].frames_drop, 9665 stats[2].frames_drop, stats[3].frames_drop); 9666 } else { 9667 sbuf_printf(sb, " channel 0 channel 1"); 9668 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 9669 stats[0].octets_ddp, stats[1].octets_ddp); 9670 sbuf_printf(sb, "\nframesDDP: %16u %16u", 9671 stats[0].frames_ddp, stats[1].frames_ddp); 9672 sbuf_printf(sb, "\nframesDrop: %16u %16u", 9673 stats[0].frames_drop, stats[1].frames_drop); 9674 } 9675 9676 rc = sbuf_finish(sb); 9677 sbuf_delete(sb); 9678 9679 return (rc); 9680 } 9681 9682 static int 9683 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 9684 { 9685 struct adapter *sc = arg1; 9686 struct sbuf *sb; 9687 int rc, i; 9688 unsigned int map, kbps, ipg, mode; 9689 unsigned int pace_tab[NTX_SCHED]; 9690 9691 sb = sbuf_new_for_sysctl(NULL, NULL, 512, req); 9692 if (sb == NULL) 9693 return (ENOMEM); 9694 9695 mtx_lock(&sc->reg_lock); 9696 if (hw_off_limits(sc)) { 9697 mtx_unlock(&sc->reg_lock); 9698 rc = ENXIO; 9699 goto done; 9700 } 9701 9702 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 9703 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 9704 t4_read_pace_tbl(sc, pace_tab); 9705 mtx_unlock(&sc->reg_lock); 9706 9707 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 9708 "Class IPG (0.1 ns) Flow IPG (us)"); 9709 9710 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 9711 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 9712 sbuf_printf(sb, "\n %u %-5s %u ", i, 9713 (mode & (1 << i)) ? "flow" : "class", map & 3); 9714 if (kbps) 9715 sbuf_printf(sb, "%9u ", kbps); 9716 else 9717 sbuf_printf(sb, " disabled "); 9718 9719 if (ipg) 9720 sbuf_printf(sb, "%13u ", ipg); 9721 else 9722 sbuf_printf(sb, " disabled "); 9723 9724 if (pace_tab[i]) 9725 sbuf_printf(sb, "%10u", pace_tab[i]); 9726 else 9727 sbuf_printf(sb, " disabled"); 9728 } 9729 rc = sbuf_finish(sb); 9730 done: 9731 sbuf_delete(sb); 9732 return (rc); 9733 } 9734 9735 static int 9736 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 9737 { 9738 struct adapter *sc = arg1; 9739 struct sbuf *sb; 9740 int rc, i, j; 9741 uint64_t *p0, *p1; 9742 struct lb_port_stats s[2]; 9743 static const char *stat_name[] = { 9744 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 9745 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 9746 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 9747 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 9748 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 9749 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 9750 "BG2FramesTrunc:", "BG3FramesTrunc:" 9751 }; 9752 9753 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9754 if (sb == NULL) 9755 return (ENOMEM); 9756 9757 memset(s, 0, sizeof(s)); 9758 9759 rc = 0; 9760 for (i = 0; i < sc->chip_params->nchan; i += 2) { 9761 mtx_lock(&sc->reg_lock); 9762 if (hw_off_limits(sc)) 9763 rc = ENXIO; 9764 else { 9765 t4_get_lb_stats(sc, i, &s[0]); 9766 t4_get_lb_stats(sc, i + 1, &s[1]); 9767 } 9768 mtx_unlock(&sc->reg_lock); 9769 if (rc != 0) 9770 break; 9771 9772 p0 = &s[0].octets; 9773 p1 = &s[1].octets; 9774 sbuf_printf(sb, "%s Loopback %u" 9775 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 9776 9777 for (j = 0; j < nitems(stat_name); j++) 9778 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 9779 *p0++, *p1++); 9780 } 9781 9782 if (rc == 0) 9783 rc = sbuf_finish(sb); 9784 sbuf_delete(sb); 9785 9786 return (rc); 9787 } 9788 9789 static int 9790 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 9791 { 9792 int rc = 0; 9793 struct port_info *pi = arg1; 9794 struct link_config *lc = &pi->link_cfg; 9795 struct sbuf *sb; 9796 9797 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 9798 if (sb == NULL) 9799 return (ENOMEM); 9800 9801 if (lc->link_ok || lc->link_down_rc == 255) 9802 sbuf_printf(sb, "n/a"); 9803 else 9804 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 9805 9806 rc = sbuf_finish(sb); 9807 sbuf_delete(sb); 9808 9809 return (rc); 9810 } 9811 9812 struct mem_desc { 9813 u_int base; 9814 u_int limit; 9815 u_int idx; 9816 }; 9817 9818 static int 9819 mem_desc_cmp(const void *a, const void *b) 9820 { 9821 const u_int v1 = ((const struct mem_desc *)a)->base; 9822 const u_int v2 = ((const struct mem_desc *)b)->base; 9823 9824 if (v1 < v2) 9825 return (-1); 9826 else if (v1 > v2) 9827 return (1); 9828 9829 return (0); 9830 } 9831 9832 static void 9833 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 9834 unsigned int to) 9835 { 9836 unsigned int size; 9837 9838 if (from == to) 9839 return; 9840 9841 size = to - from + 1; 9842 if (size == 0) 9843 return; 9844 9845 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 9846 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 9847 } 9848 9849 static int 9850 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 9851 { 9852 struct adapter *sc = arg1; 9853 struct sbuf *sb; 9854 int rc, i, n; 9855 uint32_t lo, hi, used, free, alloc; 9856 static const char *memory[] = { 9857 "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:" 9858 }; 9859 static const char *region[] = { 9860 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 9861 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 9862 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 9863 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 9864 "RQUDP region:", "PBL region:", "TXPBL region:", 9865 "TLSKey region:", "DBVFIFO region:", "ULPRX state:", 9866 "ULPTX state:", "On-chip queues:", 9867 }; 9868 struct mem_desc avail[4]; 9869 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 9870 struct mem_desc *md = mem; 9871 9872 rc = sysctl_wire_old_buffer(req, 0); 9873 if (rc != 0) 9874 return (rc); 9875 9876 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9877 if (sb == NULL) 9878 return (ENOMEM); 9879 9880 for (i = 0; i < nitems(mem); i++) { 9881 mem[i].limit = 0; 9882 mem[i].idx = i; 9883 } 9884 9885 mtx_lock(&sc->reg_lock); 9886 if (hw_off_limits(sc)) { 9887 rc = ENXIO; 9888 goto done; 9889 } 9890 9891 /* Find and sort the populated memory ranges */ 9892 i = 0; 9893 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 9894 if (lo & F_EDRAM0_ENABLE) { 9895 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 9896 avail[i].base = G_EDRAM0_BASE(hi) << 20; 9897 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 9898 avail[i].idx = 0; 9899 i++; 9900 } 9901 if (lo & F_EDRAM1_ENABLE) { 9902 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 9903 avail[i].base = G_EDRAM1_BASE(hi) << 20; 9904 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 9905 avail[i].idx = 1; 9906 i++; 9907 } 9908 if (lo & F_EXT_MEM_ENABLE) { 9909 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 9910 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 9911 avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20); 9912 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 9913 i++; 9914 } 9915 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 9916 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9917 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9918 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9919 avail[i].idx = 4; 9920 i++; 9921 } 9922 if (is_t6(sc) && lo & F_HMA_MUX) { 9923 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9924 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9925 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9926 avail[i].idx = 5; 9927 i++; 9928 } 9929 MPASS(i <= nitems(avail)); 9930 if (!i) /* no memory available */ 9931 goto done; 9932 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 9933 9934 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 9935 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 9936 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 9937 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9938 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 9939 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 9940 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 9941 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 9942 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 9943 9944 /* the next few have explicit upper bounds */ 9945 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 9946 md->limit = md->base - 1 + 9947 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 9948 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 9949 md++; 9950 9951 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 9952 md->limit = md->base - 1 + 9953 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 9954 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 9955 md++; 9956 9957 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 9958 if (chip_id(sc) <= CHELSIO_T5) 9959 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 9960 else 9961 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 9962 md->limit = 0; 9963 } else { 9964 md->base = 0; 9965 md->idx = nitems(region); /* hide it */ 9966 } 9967 md++; 9968 9969 #define ulp_region(reg) \ 9970 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 9971 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 9972 9973 ulp_region(RX_ISCSI); 9974 ulp_region(RX_TDDP); 9975 ulp_region(TX_TPT); 9976 ulp_region(RX_STAG); 9977 ulp_region(RX_RQ); 9978 ulp_region(RX_RQUDP); 9979 ulp_region(RX_PBL); 9980 ulp_region(TX_PBL); 9981 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 9982 ulp_region(RX_TLS_KEY); 9983 } 9984 #undef ulp_region 9985 9986 md->base = 0; 9987 if (is_t4(sc)) 9988 md->idx = nitems(region); 9989 else { 9990 uint32_t size = 0; 9991 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 9992 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 9993 9994 if (is_t5(sc)) { 9995 if (sge_ctrl & F_VFIFO_ENABLE) 9996 size = fifo_size << 2; 9997 } else 9998 size = G_T6_DBVFIFO_SIZE(fifo_size) << 6; 9999 10000 if (size) { 10001 md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR); 10002 md->limit = md->base + size - 1; 10003 } else 10004 md->idx = nitems(region); 10005 } 10006 md++; 10007 10008 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 10009 md->limit = 0; 10010 md++; 10011 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 10012 md->limit = 0; 10013 md++; 10014 10015 md->base = sc->vres.ocq.start; 10016 if (sc->vres.ocq.size) 10017 md->limit = md->base + sc->vres.ocq.size - 1; 10018 else 10019 md->idx = nitems(region); /* hide it */ 10020 md++; 10021 10022 /* add any address-space holes, there can be up to 3 */ 10023 for (n = 0; n < i - 1; n++) 10024 if (avail[n].limit < avail[n + 1].base) 10025 (md++)->base = avail[n].limit; 10026 if (avail[n].limit) 10027 (md++)->base = avail[n].limit; 10028 10029 n = md - mem; 10030 MPASS(n <= nitems(mem)); 10031 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 10032 10033 for (lo = 0; lo < i; lo++) 10034 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 10035 avail[lo].limit - 1); 10036 10037 sbuf_printf(sb, "\n"); 10038 for (i = 0; i < n; i++) { 10039 if (mem[i].idx >= nitems(region)) 10040 continue; /* skip holes */ 10041 if (!mem[i].limit) 10042 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 10043 mem_region_show(sb, region[mem[i].idx], mem[i].base, 10044 mem[i].limit); 10045 } 10046 10047 sbuf_printf(sb, "\n"); 10048 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 10049 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 10050 mem_region_show(sb, "uP RAM:", lo, hi); 10051 10052 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 10053 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 10054 mem_region_show(sb, "uP Extmem2:", lo, hi); 10055 10056 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 10057 for (i = 0, free = 0; i < 2; i++) 10058 free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT)); 10059 sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n", 10060 G_PMRXMAXPAGE(lo), free, 10061 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 10062 (lo & F_PMRXNUMCHN) ? 2 : 1); 10063 10064 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 10065 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 10066 for (i = 0, free = 0; i < 4; i++) 10067 free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT)); 10068 sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n", 10069 G_PMTXMAXPAGE(lo), free, 10070 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 10071 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 10072 sbuf_printf(sb, "%u p-structs (%u free)\n", 10073 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT), 10074 G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT))); 10075 10076 for (i = 0; i < 4; i++) { 10077 if (chip_id(sc) > CHELSIO_T5) 10078 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 10079 else 10080 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 10081 if (is_t5(sc)) { 10082 used = G_T5_USED(lo); 10083 alloc = G_T5_ALLOC(lo); 10084 } else { 10085 used = G_USED(lo); 10086 alloc = G_ALLOC(lo); 10087 } 10088 /* For T6 these are MAC buffer groups */ 10089 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 10090 i, used, alloc); 10091 } 10092 for (i = 0; i < sc->chip_params->nchan; i++) { 10093 if (chip_id(sc) > CHELSIO_T5) 10094 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 10095 else 10096 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 10097 if (is_t5(sc)) { 10098 used = G_T5_USED(lo); 10099 alloc = G_T5_ALLOC(lo); 10100 } else { 10101 used = G_USED(lo); 10102 alloc = G_ALLOC(lo); 10103 } 10104 /* For T6 these are MAC buffer groups */ 10105 sbuf_printf(sb, 10106 "\nLoopback %d using %u pages out of %u allocated", 10107 i, used, alloc); 10108 } 10109 done: 10110 mtx_unlock(&sc->reg_lock); 10111 if (rc == 0) 10112 rc = sbuf_finish(sb); 10113 sbuf_delete(sb); 10114 return (rc); 10115 } 10116 10117 static inline void 10118 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 10119 { 10120 *mask = x | y; 10121 y = htobe64(y); 10122 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 10123 } 10124 10125 static int 10126 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 10127 { 10128 struct adapter *sc = arg1; 10129 struct sbuf *sb; 10130 int rc, i; 10131 10132 MPASS(chip_id(sc) <= CHELSIO_T5); 10133 10134 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10135 if (sb == NULL) 10136 return (ENOMEM); 10137 10138 sbuf_printf(sb, 10139 "Idx Ethernet address Mask Vld Ports PF" 10140 " VF Replication P0 P1 P2 P3 ML"); 10141 rc = 0; 10142 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10143 uint64_t tcamx, tcamy, mask; 10144 uint32_t cls_lo, cls_hi; 10145 uint8_t addr[ETHER_ADDR_LEN]; 10146 10147 mtx_lock(&sc->reg_lock); 10148 if (hw_off_limits(sc)) 10149 rc = ENXIO; 10150 else { 10151 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 10152 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 10153 } 10154 mtx_unlock(&sc->reg_lock); 10155 if (rc != 0) 10156 break; 10157 if (tcamx & tcamy) 10158 continue; 10159 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10160 mtx_lock(&sc->reg_lock); 10161 if (hw_off_limits(sc)) 10162 rc = ENXIO; 10163 else { 10164 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10165 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10166 } 10167 mtx_unlock(&sc->reg_lock); 10168 if (rc != 0) 10169 break; 10170 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 10171 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 10172 addr[3], addr[4], addr[5], (uintmax_t)mask, 10173 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 10174 G_PORTMAP(cls_hi), G_PF(cls_lo), 10175 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 10176 10177 if (cls_lo & F_REPLICATE) { 10178 struct fw_ldst_cmd ldst_cmd; 10179 10180 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10181 ldst_cmd.op_to_addrspace = 10182 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10183 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10184 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10185 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10186 ldst_cmd.u.mps.rplc.fid_idx = 10187 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10188 V_FW_LDST_CMD_IDX(i)); 10189 10190 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10191 "t4mps"); 10192 if (rc) 10193 break; 10194 if (hw_off_limits(sc)) 10195 rc = ENXIO; 10196 else 10197 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10198 sizeof(ldst_cmd), &ldst_cmd); 10199 end_synchronized_op(sc, 0); 10200 if (rc != 0) 10201 break; 10202 else { 10203 sbuf_printf(sb, " %08x %08x %08x %08x", 10204 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10205 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10206 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10207 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10208 } 10209 } else 10210 sbuf_printf(sb, "%36s", ""); 10211 10212 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 10213 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 10214 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 10215 } 10216 10217 if (rc) 10218 (void) sbuf_finish(sb); 10219 else 10220 rc = sbuf_finish(sb); 10221 sbuf_delete(sb); 10222 10223 return (rc); 10224 } 10225 10226 static int 10227 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 10228 { 10229 struct adapter *sc = arg1; 10230 struct sbuf *sb; 10231 int rc, i; 10232 10233 MPASS(chip_id(sc) > CHELSIO_T5); 10234 10235 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10236 if (sb == NULL) 10237 return (ENOMEM); 10238 10239 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 10240 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 10241 " Replication" 10242 " P0 P1 P2 P3 ML\n"); 10243 10244 rc = 0; 10245 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10246 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 10247 uint16_t ivlan; 10248 uint64_t tcamx, tcamy, val, mask; 10249 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 10250 uint8_t addr[ETHER_ADDR_LEN]; 10251 10252 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 10253 if (i < 256) 10254 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 10255 else 10256 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 10257 mtx_lock(&sc->reg_lock); 10258 if (hw_off_limits(sc)) 10259 rc = ENXIO; 10260 else { 10261 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10262 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10263 tcamy = G_DMACH(val) << 32; 10264 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10265 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10266 } 10267 mtx_unlock(&sc->reg_lock); 10268 if (rc != 0) 10269 break; 10270 10271 lookup_type = G_DATALKPTYPE(data2); 10272 port_num = G_DATAPORTNUM(data2); 10273 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10274 /* Inner header VNI */ 10275 vniy = ((data2 & F_DATAVIDH2) << 23) | 10276 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10277 dip_hit = data2 & F_DATADIPHIT; 10278 vlan_vld = 0; 10279 } else { 10280 vniy = 0; 10281 dip_hit = 0; 10282 vlan_vld = data2 & F_DATAVIDH2; 10283 ivlan = G_VIDL(val); 10284 } 10285 10286 ctl |= V_CTLXYBITSEL(1); 10287 mtx_lock(&sc->reg_lock); 10288 if (hw_off_limits(sc)) 10289 rc = ENXIO; 10290 else { 10291 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10292 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10293 tcamx = G_DMACH(val) << 32; 10294 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10295 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10296 } 10297 mtx_unlock(&sc->reg_lock); 10298 if (rc != 0) 10299 break; 10300 10301 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10302 /* Inner header VNI mask */ 10303 vnix = ((data2 & F_DATAVIDH2) << 23) | 10304 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10305 } else 10306 vnix = 0; 10307 10308 if (tcamx & tcamy) 10309 continue; 10310 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10311 10312 mtx_lock(&sc->reg_lock); 10313 if (hw_off_limits(sc)) 10314 rc = ENXIO; 10315 else { 10316 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10317 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10318 } 10319 mtx_unlock(&sc->reg_lock); 10320 if (rc != 0) 10321 break; 10322 10323 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10324 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10325 "%012jx %06x %06x - - %3c" 10326 " I %4x %3c %#x%4u%4d", i, addr[0], 10327 addr[1], addr[2], addr[3], addr[4], addr[5], 10328 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 10329 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10330 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10331 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10332 } else { 10333 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10334 "%012jx - - ", i, addr[0], addr[1], 10335 addr[2], addr[3], addr[4], addr[5], 10336 (uintmax_t)mask); 10337 10338 if (vlan_vld) 10339 sbuf_printf(sb, "%4u Y ", ivlan); 10340 else 10341 sbuf_printf(sb, " - N "); 10342 10343 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 10344 lookup_type ? 'I' : 'O', port_num, 10345 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10346 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10347 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10348 } 10349 10350 10351 if (cls_lo & F_T6_REPLICATE) { 10352 struct fw_ldst_cmd ldst_cmd; 10353 10354 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10355 ldst_cmd.op_to_addrspace = 10356 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10357 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10358 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10359 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10360 ldst_cmd.u.mps.rplc.fid_idx = 10361 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10362 V_FW_LDST_CMD_IDX(i)); 10363 10364 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10365 "t6mps"); 10366 if (rc) 10367 break; 10368 if (hw_off_limits(sc)) 10369 rc = ENXIO; 10370 else 10371 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10372 sizeof(ldst_cmd), &ldst_cmd); 10373 end_synchronized_op(sc, 0); 10374 if (rc != 0) 10375 break; 10376 else { 10377 sbuf_printf(sb, " %08x %08x %08x %08x" 10378 " %08x %08x %08x %08x", 10379 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 10380 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 10381 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 10382 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 10383 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10384 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10385 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10386 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10387 } 10388 } else 10389 sbuf_printf(sb, "%72s", ""); 10390 10391 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 10392 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 10393 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 10394 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 10395 } 10396 10397 if (rc) 10398 (void) sbuf_finish(sb); 10399 else 10400 rc = sbuf_finish(sb); 10401 sbuf_delete(sb); 10402 10403 return (rc); 10404 } 10405 10406 static int 10407 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 10408 { 10409 struct adapter *sc = arg1; 10410 struct sbuf *sb; 10411 int rc; 10412 uint16_t mtus[NMTUS]; 10413 10414 rc = 0; 10415 mtx_lock(&sc->reg_lock); 10416 if (hw_off_limits(sc)) 10417 rc = ENXIO; 10418 else 10419 t4_read_mtu_tbl(sc, mtus, NULL); 10420 mtx_unlock(&sc->reg_lock); 10421 if (rc != 0) 10422 return (rc); 10423 10424 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10425 if (sb == NULL) 10426 return (ENOMEM); 10427 10428 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 10429 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 10430 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 10431 mtus[14], mtus[15]); 10432 10433 rc = sbuf_finish(sb); 10434 sbuf_delete(sb); 10435 10436 return (rc); 10437 } 10438 10439 static int 10440 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 10441 { 10442 struct adapter *sc = arg1; 10443 struct sbuf *sb; 10444 int rc, i; 10445 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 10446 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 10447 static const char *tx_stats[MAX_PM_NSTATS] = { 10448 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 10449 "Tx FIFO wait", NULL, "Tx latency" 10450 }; 10451 static const char *rx_stats[MAX_PM_NSTATS] = { 10452 "Read:", "Write bypass:", "Write mem:", "Flush:", 10453 "Rx FIFO wait", NULL, "Rx latency" 10454 }; 10455 10456 rc = 0; 10457 mtx_lock(&sc->reg_lock); 10458 if (hw_off_limits(sc)) 10459 rc = ENXIO; 10460 else { 10461 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 10462 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 10463 } 10464 mtx_unlock(&sc->reg_lock); 10465 if (rc != 0) 10466 return (rc); 10467 10468 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10469 if (sb == NULL) 10470 return (ENOMEM); 10471 10472 sbuf_printf(sb, " Tx pcmds Tx bytes"); 10473 for (i = 0; i < 4; i++) { 10474 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10475 tx_cyc[i]); 10476 } 10477 10478 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 10479 for (i = 0; i < 4; i++) { 10480 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10481 rx_cyc[i]); 10482 } 10483 10484 if (chip_id(sc) > CHELSIO_T5) { 10485 sbuf_printf(sb, 10486 "\n Total wait Total occupancy"); 10487 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10488 tx_cyc[i]); 10489 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10490 rx_cyc[i]); 10491 10492 i += 2; 10493 MPASS(i < nitems(tx_stats)); 10494 10495 sbuf_printf(sb, 10496 "\n Reads Total wait"); 10497 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10498 tx_cyc[i]); 10499 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10500 rx_cyc[i]); 10501 } 10502 10503 rc = sbuf_finish(sb); 10504 sbuf_delete(sb); 10505 10506 return (rc); 10507 } 10508 10509 static int 10510 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 10511 { 10512 struct adapter *sc = arg1; 10513 struct sbuf *sb; 10514 int rc; 10515 struct tp_rdma_stats stats; 10516 10517 rc = 0; 10518 mtx_lock(&sc->reg_lock); 10519 if (hw_off_limits(sc)) 10520 rc = ENXIO; 10521 else 10522 t4_tp_get_rdma_stats(sc, &stats, 0); 10523 mtx_unlock(&sc->reg_lock); 10524 if (rc != 0) 10525 return (rc); 10526 10527 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10528 if (sb == NULL) 10529 return (ENOMEM); 10530 10531 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 10532 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 10533 10534 rc = sbuf_finish(sb); 10535 sbuf_delete(sb); 10536 10537 return (rc); 10538 } 10539 10540 static int 10541 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 10542 { 10543 struct adapter *sc = arg1; 10544 struct sbuf *sb; 10545 int rc; 10546 struct tp_tcp_stats v4, v6; 10547 10548 rc = 0; 10549 mtx_lock(&sc->reg_lock); 10550 if (hw_off_limits(sc)) 10551 rc = ENXIO; 10552 else 10553 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 10554 mtx_unlock(&sc->reg_lock); 10555 if (rc != 0) 10556 return (rc); 10557 10558 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10559 if (sb == NULL) 10560 return (ENOMEM); 10561 10562 sbuf_printf(sb, 10563 " IP IPv6\n"); 10564 sbuf_printf(sb, "OutRsts: %20u %20u\n", 10565 v4.tcp_out_rsts, v6.tcp_out_rsts); 10566 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 10567 v4.tcp_in_segs, v6.tcp_in_segs); 10568 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 10569 v4.tcp_out_segs, v6.tcp_out_segs); 10570 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 10571 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 10572 10573 rc = sbuf_finish(sb); 10574 sbuf_delete(sb); 10575 10576 return (rc); 10577 } 10578 10579 static int 10580 sysctl_tids(SYSCTL_HANDLER_ARGS) 10581 { 10582 struct adapter *sc = arg1; 10583 struct sbuf *sb; 10584 int rc; 10585 uint32_t x, y; 10586 struct tid_info *t = &sc->tids; 10587 10588 rc = 0; 10589 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10590 if (sb == NULL) 10591 return (ENOMEM); 10592 10593 if (t->natids) { 10594 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 10595 t->atids_in_use); 10596 } 10597 10598 if (t->nhpftids) { 10599 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 10600 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 10601 } 10602 10603 if (t->ntids) { 10604 bool hashen = false; 10605 10606 mtx_lock(&sc->reg_lock); 10607 if (hw_off_limits(sc)) 10608 rc = ENXIO; 10609 else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 10610 hashen = true; 10611 if (chip_id(sc) <= CHELSIO_T5) { 10612 x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 10613 y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 10614 } else { 10615 x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 10616 y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 10617 } 10618 } 10619 mtx_unlock(&sc->reg_lock); 10620 if (rc != 0) 10621 goto done; 10622 10623 sbuf_printf(sb, "TID range: "); 10624 if (hashen) { 10625 if (x) 10626 sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1); 10627 sbuf_printf(sb, "%u-%u", y, t->ntids - 1); 10628 } else { 10629 sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base + 10630 t->ntids - 1); 10631 } 10632 sbuf_printf(sb, ", in use: %u\n", 10633 atomic_load_acq_int(&t->tids_in_use)); 10634 } 10635 10636 if (t->nstids) { 10637 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 10638 t->stid_base + t->nstids - 1, t->stids_in_use); 10639 } 10640 10641 if (t->nftids) { 10642 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 10643 t->ftid_end, t->ftids_in_use); 10644 } 10645 10646 if (t->netids) { 10647 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 10648 t->etid_base + t->netids - 1, t->etids_in_use); 10649 } 10650 10651 mtx_lock(&sc->reg_lock); 10652 if (hw_off_limits(sc)) 10653 rc = ENXIO; 10654 else { 10655 x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4); 10656 y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6); 10657 } 10658 mtx_unlock(&sc->reg_lock); 10659 if (rc != 0) 10660 goto done; 10661 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y); 10662 done: 10663 if (rc == 0) 10664 rc = sbuf_finish(sb); 10665 else 10666 (void)sbuf_finish(sb); 10667 sbuf_delete(sb); 10668 10669 return (rc); 10670 } 10671 10672 static int 10673 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 10674 { 10675 struct adapter *sc = arg1; 10676 struct sbuf *sb; 10677 int rc; 10678 struct tp_err_stats stats; 10679 10680 rc = 0; 10681 mtx_lock(&sc->reg_lock); 10682 if (hw_off_limits(sc)) 10683 rc = ENXIO; 10684 else 10685 t4_tp_get_err_stats(sc, &stats, 0); 10686 mtx_unlock(&sc->reg_lock); 10687 if (rc != 0) 10688 return (rc); 10689 10690 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10691 if (sb == NULL) 10692 return (ENOMEM); 10693 10694 if (sc->chip_params->nchan > 2) { 10695 sbuf_printf(sb, " channel 0 channel 1" 10696 " channel 2 channel 3\n"); 10697 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 10698 stats.mac_in_errs[0], stats.mac_in_errs[1], 10699 stats.mac_in_errs[2], stats.mac_in_errs[3]); 10700 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 10701 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 10702 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 10703 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 10704 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 10705 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 10706 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 10707 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 10708 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 10709 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 10710 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 10711 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 10712 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 10713 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 10714 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 10715 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 10716 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 10717 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 10718 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 10719 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 10720 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 10721 } else { 10722 sbuf_printf(sb, " channel 0 channel 1\n"); 10723 sbuf_printf(sb, "macInErrs: %10u %10u\n", 10724 stats.mac_in_errs[0], stats.mac_in_errs[1]); 10725 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 10726 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 10727 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 10728 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 10729 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 10730 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 10731 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 10732 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 10733 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 10734 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 10735 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 10736 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 10737 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 10738 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 10739 } 10740 10741 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 10742 stats.ofld_no_neigh, stats.ofld_cong_defer); 10743 10744 rc = sbuf_finish(sb); 10745 sbuf_delete(sb); 10746 10747 return (rc); 10748 } 10749 10750 static int 10751 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS) 10752 { 10753 struct adapter *sc = arg1; 10754 struct sbuf *sb; 10755 int rc; 10756 struct tp_tnl_stats stats; 10757 10758 rc = 0; 10759 mtx_lock(&sc->reg_lock); 10760 if (hw_off_limits(sc)) 10761 rc = ENXIO; 10762 else 10763 t4_tp_get_tnl_stats(sc, &stats, 1); 10764 mtx_unlock(&sc->reg_lock); 10765 if (rc != 0) 10766 return (rc); 10767 10768 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10769 if (sb == NULL) 10770 return (ENOMEM); 10771 10772 if (sc->chip_params->nchan > 2) { 10773 sbuf_printf(sb, " channel 0 channel 1" 10774 " channel 2 channel 3\n"); 10775 sbuf_printf(sb, "OutPkts: %10u %10u %10u %10u\n", 10776 stats.out_pkt[0], stats.out_pkt[1], 10777 stats.out_pkt[2], stats.out_pkt[3]); 10778 sbuf_printf(sb, "InPkts: %10u %10u %10u %10u", 10779 stats.in_pkt[0], stats.in_pkt[1], 10780 stats.in_pkt[2], stats.in_pkt[3]); 10781 } else { 10782 sbuf_printf(sb, " channel 0 channel 1\n"); 10783 sbuf_printf(sb, "OutPkts: %10u %10u\n", 10784 stats.out_pkt[0], stats.out_pkt[1]); 10785 sbuf_printf(sb, "InPkts: %10u %10u", 10786 stats.in_pkt[0], stats.in_pkt[1]); 10787 } 10788 10789 rc = sbuf_finish(sb); 10790 sbuf_delete(sb); 10791 10792 return (rc); 10793 } 10794 10795 static int 10796 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 10797 { 10798 struct adapter *sc = arg1; 10799 struct tp_params *tpp = &sc->params.tp; 10800 u_int mask; 10801 int rc; 10802 10803 mask = tpp->la_mask >> 16; 10804 rc = sysctl_handle_int(oidp, &mask, 0, req); 10805 if (rc != 0 || req->newptr == NULL) 10806 return (rc); 10807 if (mask > 0xffff) 10808 return (EINVAL); 10809 mtx_lock(&sc->reg_lock); 10810 if (hw_off_limits(sc)) 10811 rc = ENXIO; 10812 else { 10813 tpp->la_mask = mask << 16; 10814 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, 10815 tpp->la_mask); 10816 } 10817 mtx_unlock(&sc->reg_lock); 10818 10819 return (rc); 10820 } 10821 10822 struct field_desc { 10823 const char *name; 10824 u_int start; 10825 u_int width; 10826 }; 10827 10828 static void 10829 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 10830 { 10831 char buf[32]; 10832 int line_size = 0; 10833 10834 while (f->name) { 10835 uint64_t mask = (1ULL << f->width) - 1; 10836 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 10837 ((uintmax_t)v >> f->start) & mask); 10838 10839 if (line_size + len >= 79) { 10840 line_size = 8; 10841 sbuf_printf(sb, "\n "); 10842 } 10843 sbuf_printf(sb, "%s ", buf); 10844 line_size += len + 1; 10845 f++; 10846 } 10847 sbuf_printf(sb, "\n"); 10848 } 10849 10850 static const struct field_desc tp_la0[] = { 10851 { "RcfOpCodeOut", 60, 4 }, 10852 { "State", 56, 4 }, 10853 { "WcfState", 52, 4 }, 10854 { "RcfOpcSrcOut", 50, 2 }, 10855 { "CRxError", 49, 1 }, 10856 { "ERxError", 48, 1 }, 10857 { "SanityFailed", 47, 1 }, 10858 { "SpuriousMsg", 46, 1 }, 10859 { "FlushInputMsg", 45, 1 }, 10860 { "FlushInputCpl", 44, 1 }, 10861 { "RssUpBit", 43, 1 }, 10862 { "RssFilterHit", 42, 1 }, 10863 { "Tid", 32, 10 }, 10864 { "InitTcb", 31, 1 }, 10865 { "LineNumber", 24, 7 }, 10866 { "Emsg", 23, 1 }, 10867 { "EdataOut", 22, 1 }, 10868 { "Cmsg", 21, 1 }, 10869 { "CdataOut", 20, 1 }, 10870 { "EreadPdu", 19, 1 }, 10871 { "CreadPdu", 18, 1 }, 10872 { "TunnelPkt", 17, 1 }, 10873 { "RcfPeerFin", 16, 1 }, 10874 { "RcfReasonOut", 12, 4 }, 10875 { "TxCchannel", 10, 2 }, 10876 { "RcfTxChannel", 8, 2 }, 10877 { "RxEchannel", 6, 2 }, 10878 { "RcfRxChannel", 5, 1 }, 10879 { "RcfDataOutSrdy", 4, 1 }, 10880 { "RxDvld", 3, 1 }, 10881 { "RxOoDvld", 2, 1 }, 10882 { "RxCongestion", 1, 1 }, 10883 { "TxCongestion", 0, 1 }, 10884 { NULL } 10885 }; 10886 10887 static const struct field_desc tp_la1[] = { 10888 { "CplCmdIn", 56, 8 }, 10889 { "CplCmdOut", 48, 8 }, 10890 { "ESynOut", 47, 1 }, 10891 { "EAckOut", 46, 1 }, 10892 { "EFinOut", 45, 1 }, 10893 { "ERstOut", 44, 1 }, 10894 { "SynIn", 43, 1 }, 10895 { "AckIn", 42, 1 }, 10896 { "FinIn", 41, 1 }, 10897 { "RstIn", 40, 1 }, 10898 { "DataIn", 39, 1 }, 10899 { "DataInVld", 38, 1 }, 10900 { "PadIn", 37, 1 }, 10901 { "RxBufEmpty", 36, 1 }, 10902 { "RxDdp", 35, 1 }, 10903 { "RxFbCongestion", 34, 1 }, 10904 { "TxFbCongestion", 33, 1 }, 10905 { "TxPktSumSrdy", 32, 1 }, 10906 { "RcfUlpType", 28, 4 }, 10907 { "Eread", 27, 1 }, 10908 { "Ebypass", 26, 1 }, 10909 { "Esave", 25, 1 }, 10910 { "Static0", 24, 1 }, 10911 { "Cread", 23, 1 }, 10912 { "Cbypass", 22, 1 }, 10913 { "Csave", 21, 1 }, 10914 { "CPktOut", 20, 1 }, 10915 { "RxPagePoolFull", 18, 2 }, 10916 { "RxLpbkPkt", 17, 1 }, 10917 { "TxLpbkPkt", 16, 1 }, 10918 { "RxVfValid", 15, 1 }, 10919 { "SynLearned", 14, 1 }, 10920 { "SetDelEntry", 13, 1 }, 10921 { "SetInvEntry", 12, 1 }, 10922 { "CpcmdDvld", 11, 1 }, 10923 { "CpcmdSave", 10, 1 }, 10924 { "RxPstructsFull", 8, 2 }, 10925 { "EpcmdDvld", 7, 1 }, 10926 { "EpcmdFlush", 6, 1 }, 10927 { "EpcmdTrimPrefix", 5, 1 }, 10928 { "EpcmdTrimPostfix", 4, 1 }, 10929 { "ERssIp4Pkt", 3, 1 }, 10930 { "ERssIp6Pkt", 2, 1 }, 10931 { "ERssTcpUdpPkt", 1, 1 }, 10932 { "ERssFceFipPkt", 0, 1 }, 10933 { NULL } 10934 }; 10935 10936 static const struct field_desc tp_la2[] = { 10937 { "CplCmdIn", 56, 8 }, 10938 { "MpsVfVld", 55, 1 }, 10939 { "MpsPf", 52, 3 }, 10940 { "MpsVf", 44, 8 }, 10941 { "SynIn", 43, 1 }, 10942 { "AckIn", 42, 1 }, 10943 { "FinIn", 41, 1 }, 10944 { "RstIn", 40, 1 }, 10945 { "DataIn", 39, 1 }, 10946 { "DataInVld", 38, 1 }, 10947 { "PadIn", 37, 1 }, 10948 { "RxBufEmpty", 36, 1 }, 10949 { "RxDdp", 35, 1 }, 10950 { "RxFbCongestion", 34, 1 }, 10951 { "TxFbCongestion", 33, 1 }, 10952 { "TxPktSumSrdy", 32, 1 }, 10953 { "RcfUlpType", 28, 4 }, 10954 { "Eread", 27, 1 }, 10955 { "Ebypass", 26, 1 }, 10956 { "Esave", 25, 1 }, 10957 { "Static0", 24, 1 }, 10958 { "Cread", 23, 1 }, 10959 { "Cbypass", 22, 1 }, 10960 { "Csave", 21, 1 }, 10961 { "CPktOut", 20, 1 }, 10962 { "RxPagePoolFull", 18, 2 }, 10963 { "RxLpbkPkt", 17, 1 }, 10964 { "TxLpbkPkt", 16, 1 }, 10965 { "RxVfValid", 15, 1 }, 10966 { "SynLearned", 14, 1 }, 10967 { "SetDelEntry", 13, 1 }, 10968 { "SetInvEntry", 12, 1 }, 10969 { "CpcmdDvld", 11, 1 }, 10970 { "CpcmdSave", 10, 1 }, 10971 { "RxPstructsFull", 8, 2 }, 10972 { "EpcmdDvld", 7, 1 }, 10973 { "EpcmdFlush", 6, 1 }, 10974 { "EpcmdTrimPrefix", 5, 1 }, 10975 { "EpcmdTrimPostfix", 4, 1 }, 10976 { "ERssIp4Pkt", 3, 1 }, 10977 { "ERssIp6Pkt", 2, 1 }, 10978 { "ERssTcpUdpPkt", 1, 1 }, 10979 { "ERssFceFipPkt", 0, 1 }, 10980 { NULL } 10981 }; 10982 10983 static void 10984 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 10985 { 10986 10987 field_desc_show(sb, *p, tp_la0); 10988 } 10989 10990 static void 10991 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 10992 { 10993 10994 if (idx) 10995 sbuf_printf(sb, "\n"); 10996 field_desc_show(sb, p[0], tp_la0); 10997 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10998 field_desc_show(sb, p[1], tp_la0); 10999 } 11000 11001 static void 11002 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 11003 { 11004 11005 if (idx) 11006 sbuf_printf(sb, "\n"); 11007 field_desc_show(sb, p[0], tp_la0); 11008 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 11009 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 11010 } 11011 11012 static int 11013 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 11014 { 11015 struct adapter *sc = arg1; 11016 struct sbuf *sb; 11017 uint64_t *buf, *p; 11018 int rc; 11019 u_int i, inc; 11020 void (*show_func)(struct sbuf *, uint64_t *, int); 11021 11022 rc = 0; 11023 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11024 if (sb == NULL) 11025 return (ENOMEM); 11026 11027 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 11028 11029 mtx_lock(&sc->reg_lock); 11030 if (hw_off_limits(sc)) 11031 rc = ENXIO; 11032 else { 11033 t4_tp_read_la(sc, buf, NULL); 11034 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 11035 case 2: 11036 inc = 2; 11037 show_func = tp_la_show2; 11038 break; 11039 case 3: 11040 inc = 2; 11041 show_func = tp_la_show3; 11042 break; 11043 default: 11044 inc = 1; 11045 show_func = tp_la_show; 11046 } 11047 } 11048 mtx_unlock(&sc->reg_lock); 11049 if (rc != 0) 11050 goto done; 11051 11052 p = buf; 11053 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 11054 (*show_func)(sb, p, i); 11055 rc = sbuf_finish(sb); 11056 done: 11057 sbuf_delete(sb); 11058 free(buf, M_CXGBE); 11059 return (rc); 11060 } 11061 11062 static int 11063 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 11064 { 11065 struct adapter *sc = arg1; 11066 struct sbuf *sb; 11067 int rc; 11068 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 11069 11070 rc = 0; 11071 mtx_lock(&sc->reg_lock); 11072 if (hw_off_limits(sc)) 11073 rc = ENXIO; 11074 else 11075 t4_get_chan_txrate(sc, nrate, orate); 11076 mtx_unlock(&sc->reg_lock); 11077 if (rc != 0) 11078 return (rc); 11079 11080 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 11081 if (sb == NULL) 11082 return (ENOMEM); 11083 11084 if (sc->chip_params->nchan > 2) { 11085 sbuf_printf(sb, " channel 0 channel 1" 11086 " channel 2 channel 3\n"); 11087 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 11088 nrate[0], nrate[1], nrate[2], nrate[3]); 11089 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 11090 orate[0], orate[1], orate[2], orate[3]); 11091 } else { 11092 sbuf_printf(sb, " channel 0 channel 1\n"); 11093 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 11094 nrate[0], nrate[1]); 11095 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 11096 orate[0], orate[1]); 11097 } 11098 11099 rc = sbuf_finish(sb); 11100 sbuf_delete(sb); 11101 11102 return (rc); 11103 } 11104 11105 static int 11106 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 11107 { 11108 struct adapter *sc = arg1; 11109 struct sbuf *sb; 11110 uint32_t *buf, *p; 11111 int rc, i; 11112 11113 rc = 0; 11114 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11115 if (sb == NULL) 11116 return (ENOMEM); 11117 11118 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 11119 M_ZERO | M_WAITOK); 11120 11121 mtx_lock(&sc->reg_lock); 11122 if (hw_off_limits(sc)) 11123 rc = ENXIO; 11124 else 11125 t4_ulprx_read_la(sc, buf); 11126 mtx_unlock(&sc->reg_lock); 11127 if (rc != 0) 11128 goto done; 11129 11130 p = buf; 11131 sbuf_printf(sb, " Pcmd Type Message" 11132 " Data"); 11133 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 11134 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 11135 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 11136 } 11137 rc = sbuf_finish(sb); 11138 done: 11139 sbuf_delete(sb); 11140 free(buf, M_CXGBE); 11141 return (rc); 11142 } 11143 11144 static int 11145 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 11146 { 11147 struct adapter *sc = arg1; 11148 struct sbuf *sb; 11149 int rc; 11150 uint32_t cfg, s1, s2; 11151 11152 MPASS(chip_id(sc) >= CHELSIO_T5); 11153 11154 rc = 0; 11155 mtx_lock(&sc->reg_lock); 11156 if (hw_off_limits(sc)) 11157 rc = ENXIO; 11158 else { 11159 cfg = t4_read_reg(sc, A_SGE_STAT_CFG); 11160 s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL); 11161 s2 = t4_read_reg(sc, A_SGE_STAT_MATCH); 11162 } 11163 mtx_unlock(&sc->reg_lock); 11164 if (rc != 0) 11165 return (rc); 11166 11167 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11168 if (sb == NULL) 11169 return (ENOMEM); 11170 11171 if (G_STATSOURCE_T5(cfg) == 7) { 11172 int mode; 11173 11174 mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg); 11175 if (mode == 0) 11176 sbuf_printf(sb, "total %d, incomplete %d", s1, s2); 11177 else if (mode == 1) 11178 sbuf_printf(sb, "total %d, data overflow %d", s1, s2); 11179 else 11180 sbuf_printf(sb, "unknown mode %d", mode); 11181 } 11182 rc = sbuf_finish(sb); 11183 sbuf_delete(sb); 11184 11185 return (rc); 11186 } 11187 11188 static int 11189 sysctl_cpus(SYSCTL_HANDLER_ARGS) 11190 { 11191 struct adapter *sc = arg1; 11192 enum cpu_sets op = arg2; 11193 cpuset_t cpuset; 11194 struct sbuf *sb; 11195 int i, rc; 11196 11197 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 11198 11199 CPU_ZERO(&cpuset); 11200 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 11201 if (rc != 0) 11202 return (rc); 11203 11204 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11205 if (sb == NULL) 11206 return (ENOMEM); 11207 11208 CPU_FOREACH(i) 11209 sbuf_printf(sb, "%d ", i); 11210 rc = sbuf_finish(sb); 11211 sbuf_delete(sb); 11212 11213 return (rc); 11214 } 11215 11216 static int 11217 sysctl_reset(SYSCTL_HANDLER_ARGS) 11218 { 11219 struct adapter *sc = arg1; 11220 u_int val; 11221 int rc; 11222 11223 val = atomic_load_int(&sc->num_resets); 11224 rc = sysctl_handle_int(oidp, &val, 0, req); 11225 if (rc != 0 || req->newptr == NULL) 11226 return (rc); 11227 11228 if (val == 0) { 11229 /* Zero out the counter that tracks reset. */ 11230 atomic_store_int(&sc->num_resets, 0); 11231 return (0); 11232 } 11233 11234 if (val != 1) 11235 return (EINVAL); /* 0 or 1 are the only legal values */ 11236 11237 if (hw_off_limits(sc)) /* harmless race */ 11238 return (EALREADY); 11239 11240 taskqueue_enqueue(reset_tq, &sc->reset_task); 11241 return (0); 11242 } 11243 11244 #ifdef TCP_OFFLOAD 11245 static int 11246 sysctl_tls(SYSCTL_HANDLER_ARGS) 11247 { 11248 struct adapter *sc = arg1; 11249 int i, j, v, rc; 11250 struct vi_info *vi; 11251 11252 v = sc->tt.tls; 11253 rc = sysctl_handle_int(oidp, &v, 0, req); 11254 if (rc != 0 || req->newptr == NULL) 11255 return (rc); 11256 11257 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 11258 return (ENOTSUP); 11259 11260 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls"); 11261 if (rc) 11262 return (rc); 11263 if (hw_off_limits(sc)) 11264 rc = ENXIO; 11265 else { 11266 sc->tt.tls = !!v; 11267 for_each_port(sc, i) { 11268 for_each_vi(sc->port[i], j, vi) { 11269 if (vi->flags & VI_INIT_DONE) 11270 t4_update_fl_bufsize(vi->ifp); 11271 } 11272 } 11273 } 11274 end_synchronized_op(sc, 0); 11275 11276 return (rc); 11277 11278 } 11279 11280 static void 11281 unit_conv(char *buf, size_t len, u_int val, u_int factor) 11282 { 11283 u_int rem = val % factor; 11284 11285 if (rem == 0) 11286 snprintf(buf, len, "%u", val / factor); 11287 else { 11288 while (rem % 10 == 0) 11289 rem /= 10; 11290 snprintf(buf, len, "%u.%u", val / factor, rem); 11291 } 11292 } 11293 11294 static int 11295 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 11296 { 11297 struct adapter *sc = arg1; 11298 char buf[16]; 11299 u_int res, re; 11300 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11301 11302 mtx_lock(&sc->reg_lock); 11303 if (hw_off_limits(sc)) 11304 res = (u_int)-1; 11305 else 11306 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 11307 mtx_unlock(&sc->reg_lock); 11308 if (res == (u_int)-1) 11309 return (ENXIO); 11310 11311 switch (arg2) { 11312 case 0: 11313 /* timer_tick */ 11314 re = G_TIMERRESOLUTION(res); 11315 break; 11316 case 1: 11317 /* TCP timestamp tick */ 11318 re = G_TIMESTAMPRESOLUTION(res); 11319 break; 11320 case 2: 11321 /* DACK tick */ 11322 re = G_DELAYEDACKRESOLUTION(res); 11323 break; 11324 default: 11325 return (EDOOFUS); 11326 } 11327 11328 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 11329 11330 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 11331 } 11332 11333 static int 11334 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 11335 { 11336 struct adapter *sc = arg1; 11337 int rc; 11338 u_int dack_tmr, dack_re, v; 11339 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11340 11341 mtx_lock(&sc->reg_lock); 11342 if (hw_off_limits(sc)) 11343 rc = ENXIO; 11344 else { 11345 rc = 0; 11346 dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc, 11347 A_TP_TIMER_RESOLUTION)); 11348 dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER); 11349 } 11350 mtx_unlock(&sc->reg_lock); 11351 if (rc != 0) 11352 return (rc); 11353 11354 v = ((cclk_ps << dack_re) / 1000000) * dack_tmr; 11355 11356 return (sysctl_handle_int(oidp, &v, 0, req)); 11357 } 11358 11359 static int 11360 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 11361 { 11362 struct adapter *sc = arg1; 11363 int rc, reg = arg2; 11364 u_int tre; 11365 u_long tp_tick_us, v; 11366 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11367 11368 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 11369 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 11370 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 11371 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 11372 11373 mtx_lock(&sc->reg_lock); 11374 if (hw_off_limits(sc)) 11375 rc = ENXIO; 11376 else { 11377 rc = 0; 11378 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 11379 tp_tick_us = (cclk_ps << tre) / 1000000; 11380 if (reg == A_TP_INIT_SRTT) 11381 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 11382 else 11383 v = tp_tick_us * t4_read_reg(sc, reg); 11384 } 11385 mtx_unlock(&sc->reg_lock); 11386 if (rc != 0) 11387 return (rc); 11388 else 11389 return (sysctl_handle_long(oidp, &v, 0, req)); 11390 } 11391 11392 /* 11393 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 11394 * passed to this function. 11395 */ 11396 static int 11397 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 11398 { 11399 struct adapter *sc = arg1; 11400 int rc, idx = arg2; 11401 u_int v; 11402 11403 MPASS(idx >= 0 && idx <= 24); 11404 11405 mtx_lock(&sc->reg_lock); 11406 if (hw_off_limits(sc)) 11407 rc = ENXIO; 11408 else { 11409 rc = 0; 11410 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 11411 } 11412 mtx_unlock(&sc->reg_lock); 11413 if (rc != 0) 11414 return (rc); 11415 else 11416 return (sysctl_handle_int(oidp, &v, 0, req)); 11417 } 11418 11419 static int 11420 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 11421 { 11422 struct adapter *sc = arg1; 11423 int rc, idx = arg2; 11424 u_int shift, v, r; 11425 11426 MPASS(idx >= 0 && idx < 16); 11427 11428 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 11429 shift = (idx & 3) << 3; 11430 mtx_lock(&sc->reg_lock); 11431 if (hw_off_limits(sc)) 11432 rc = ENXIO; 11433 else { 11434 rc = 0; 11435 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 11436 } 11437 mtx_unlock(&sc->reg_lock); 11438 if (rc != 0) 11439 return (rc); 11440 else 11441 return (sysctl_handle_int(oidp, &v, 0, req)); 11442 } 11443 11444 static int 11445 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 11446 { 11447 struct vi_info *vi = arg1; 11448 struct adapter *sc = vi->adapter; 11449 int idx, rc, i; 11450 struct sge_ofld_rxq *ofld_rxq; 11451 uint8_t v; 11452 11453 idx = vi->ofld_tmr_idx; 11454 11455 rc = sysctl_handle_int(oidp, &idx, 0, req); 11456 if (rc != 0 || req->newptr == NULL) 11457 return (rc); 11458 11459 if (idx < 0 || idx >= SGE_NTIMERS) 11460 return (EINVAL); 11461 11462 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11463 "t4otmr"); 11464 if (rc) 11465 return (rc); 11466 11467 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 11468 for_each_ofld_rxq(vi, i, ofld_rxq) { 11469 #ifdef atomic_store_rel_8 11470 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 11471 #else 11472 ofld_rxq->iq.intr_params = v; 11473 #endif 11474 } 11475 vi->ofld_tmr_idx = idx; 11476 11477 end_synchronized_op(sc, LOCK_HELD); 11478 return (0); 11479 } 11480 11481 static int 11482 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 11483 { 11484 struct vi_info *vi = arg1; 11485 struct adapter *sc = vi->adapter; 11486 int idx, rc; 11487 11488 idx = vi->ofld_pktc_idx; 11489 11490 rc = sysctl_handle_int(oidp, &idx, 0, req); 11491 if (rc != 0 || req->newptr == NULL) 11492 return (rc); 11493 11494 if (idx < -1 || idx >= SGE_NCOUNTERS) 11495 return (EINVAL); 11496 11497 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11498 "t4opktc"); 11499 if (rc) 11500 return (rc); 11501 11502 if (vi->flags & VI_INIT_DONE) 11503 rc = EBUSY; /* cannot be changed once the queues are created */ 11504 else 11505 vi->ofld_pktc_idx = idx; 11506 11507 end_synchronized_op(sc, LOCK_HELD); 11508 return (rc); 11509 } 11510 #endif 11511 11512 static int 11513 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 11514 { 11515 int rc; 11516 11517 if (cntxt->cid > M_CTXTQID) 11518 return (EINVAL); 11519 11520 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 11521 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 11522 return (EINVAL); 11523 11524 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 11525 if (rc) 11526 return (rc); 11527 11528 if (hw_off_limits(sc)) { 11529 rc = ENXIO; 11530 goto done; 11531 } 11532 11533 if (sc->flags & FW_OK) { 11534 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 11535 &cntxt->data[0]); 11536 if (rc == 0) 11537 goto done; 11538 } 11539 11540 /* 11541 * Read via firmware failed or wasn't even attempted. Read directly via 11542 * the backdoor. 11543 */ 11544 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 11545 done: 11546 end_synchronized_op(sc, 0); 11547 return (rc); 11548 } 11549 11550 static int 11551 load_fw(struct adapter *sc, struct t4_data *fw) 11552 { 11553 int rc; 11554 uint8_t *fw_data; 11555 11556 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 11557 if (rc) 11558 return (rc); 11559 11560 if (hw_off_limits(sc)) { 11561 rc = ENXIO; 11562 goto done; 11563 } 11564 11565 /* 11566 * The firmware, with the sole exception of the memory parity error 11567 * handler, runs from memory and not flash. It is almost always safe to 11568 * install a new firmware on a running system. Just set bit 1 in 11569 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 11570 */ 11571 if (sc->flags & FULL_INIT_DONE && 11572 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 11573 rc = EBUSY; 11574 goto done; 11575 } 11576 11577 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 11578 11579 rc = copyin(fw->data, fw_data, fw->len); 11580 if (rc == 0) 11581 rc = -t4_load_fw(sc, fw_data, fw->len); 11582 11583 free(fw_data, M_CXGBE); 11584 done: 11585 end_synchronized_op(sc, 0); 11586 return (rc); 11587 } 11588 11589 static int 11590 load_cfg(struct adapter *sc, struct t4_data *cfg) 11591 { 11592 int rc; 11593 uint8_t *cfg_data = NULL; 11594 11595 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11596 if (rc) 11597 return (rc); 11598 11599 if (hw_off_limits(sc)) { 11600 rc = ENXIO; 11601 goto done; 11602 } 11603 11604 if (cfg->len == 0) { 11605 /* clear */ 11606 rc = -t4_load_cfg(sc, NULL, 0); 11607 goto done; 11608 } 11609 11610 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 11611 11612 rc = copyin(cfg->data, cfg_data, cfg->len); 11613 if (rc == 0) 11614 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 11615 11616 free(cfg_data, M_CXGBE); 11617 done: 11618 end_synchronized_op(sc, 0); 11619 return (rc); 11620 } 11621 11622 static int 11623 load_boot(struct adapter *sc, struct t4_bootrom *br) 11624 { 11625 int rc; 11626 uint8_t *br_data = NULL; 11627 u_int offset; 11628 11629 if (br->len > 1024 * 1024) 11630 return (EFBIG); 11631 11632 if (br->pf_offset == 0) { 11633 /* pfidx */ 11634 if (br->pfidx_addr > 7) 11635 return (EINVAL); 11636 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 11637 A_PCIE_PF_EXPROM_OFST))); 11638 } else if (br->pf_offset == 1) { 11639 /* offset */ 11640 offset = G_OFFSET(br->pfidx_addr); 11641 } else { 11642 return (EINVAL); 11643 } 11644 11645 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 11646 if (rc) 11647 return (rc); 11648 11649 if (hw_off_limits(sc)) { 11650 rc = ENXIO; 11651 goto done; 11652 } 11653 11654 if (br->len == 0) { 11655 /* clear */ 11656 rc = -t4_load_boot(sc, NULL, offset, 0); 11657 goto done; 11658 } 11659 11660 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 11661 11662 rc = copyin(br->data, br_data, br->len); 11663 if (rc == 0) 11664 rc = -t4_load_boot(sc, br_data, offset, br->len); 11665 11666 free(br_data, M_CXGBE); 11667 done: 11668 end_synchronized_op(sc, 0); 11669 return (rc); 11670 } 11671 11672 static int 11673 load_bootcfg(struct adapter *sc, struct t4_data *bc) 11674 { 11675 int rc; 11676 uint8_t *bc_data = NULL; 11677 11678 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11679 if (rc) 11680 return (rc); 11681 11682 if (hw_off_limits(sc)) { 11683 rc = ENXIO; 11684 goto done; 11685 } 11686 11687 if (bc->len == 0) { 11688 /* clear */ 11689 rc = -t4_load_bootcfg(sc, NULL, 0); 11690 goto done; 11691 } 11692 11693 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 11694 11695 rc = copyin(bc->data, bc_data, bc->len); 11696 if (rc == 0) 11697 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 11698 11699 free(bc_data, M_CXGBE); 11700 done: 11701 end_synchronized_op(sc, 0); 11702 return (rc); 11703 } 11704 11705 static int 11706 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 11707 { 11708 int rc; 11709 struct cudbg_init *cudbg; 11710 void *handle, *buf; 11711 11712 /* buf is large, don't block if no memory is available */ 11713 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 11714 if (buf == NULL) 11715 return (ENOMEM); 11716 11717 handle = cudbg_alloc_handle(); 11718 if (handle == NULL) { 11719 rc = ENOMEM; 11720 goto done; 11721 } 11722 11723 cudbg = cudbg_get_init(handle); 11724 cudbg->adap = sc; 11725 cudbg->print = (cudbg_print_cb)printf; 11726 11727 #ifndef notyet 11728 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 11729 __func__, dump->wr_flash, dump->len, dump->data); 11730 #endif 11731 11732 if (dump->wr_flash) 11733 cudbg->use_flash = 1; 11734 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 11735 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 11736 11737 rc = cudbg_collect(handle, buf, &dump->len); 11738 if (rc != 0) 11739 goto done; 11740 11741 rc = copyout(buf, dump->data, dump->len); 11742 done: 11743 cudbg_free_handle(handle); 11744 free(buf, M_CXGBE); 11745 return (rc); 11746 } 11747 11748 static void 11749 free_offload_policy(struct t4_offload_policy *op) 11750 { 11751 struct offload_rule *r; 11752 int i; 11753 11754 if (op == NULL) 11755 return; 11756 11757 r = &op->rule[0]; 11758 for (i = 0; i < op->nrules; i++, r++) { 11759 free(r->bpf_prog.bf_insns, M_CXGBE); 11760 } 11761 free(op->rule, M_CXGBE); 11762 free(op, M_CXGBE); 11763 } 11764 11765 static int 11766 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 11767 { 11768 int i, rc, len; 11769 struct t4_offload_policy *op, *old; 11770 struct bpf_program *bf; 11771 const struct offload_settings *s; 11772 struct offload_rule *r; 11773 void *u; 11774 11775 if (!is_offload(sc)) 11776 return (ENODEV); 11777 11778 if (uop->nrules == 0) { 11779 /* Delete installed policies. */ 11780 op = NULL; 11781 goto set_policy; 11782 } else if (uop->nrules > 256) { /* arbitrary */ 11783 return (E2BIG); 11784 } 11785 11786 /* Copy userspace offload policy to kernel */ 11787 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 11788 op->nrules = uop->nrules; 11789 len = op->nrules * sizeof(struct offload_rule); 11790 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11791 rc = copyin(uop->rule, op->rule, len); 11792 if (rc) { 11793 free(op->rule, M_CXGBE); 11794 free(op, M_CXGBE); 11795 return (rc); 11796 } 11797 11798 r = &op->rule[0]; 11799 for (i = 0; i < op->nrules; i++, r++) { 11800 11801 /* Validate open_type */ 11802 if (r->open_type != OPEN_TYPE_LISTEN && 11803 r->open_type != OPEN_TYPE_ACTIVE && 11804 r->open_type != OPEN_TYPE_PASSIVE && 11805 r->open_type != OPEN_TYPE_DONTCARE) { 11806 error: 11807 /* 11808 * Rules 0 to i have malloc'd filters that need to be 11809 * freed. Rules i+1 to nrules have userspace pointers 11810 * and should be left alone. 11811 */ 11812 op->nrules = i; 11813 free_offload_policy(op); 11814 return (rc); 11815 } 11816 11817 /* Validate settings */ 11818 s = &r->settings; 11819 if ((s->offload != 0 && s->offload != 1) || 11820 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 11821 s->sched_class < -1 || 11822 s->sched_class >= sc->params.nsched_cls) { 11823 rc = EINVAL; 11824 goto error; 11825 } 11826 11827 bf = &r->bpf_prog; 11828 u = bf->bf_insns; /* userspace ptr */ 11829 bf->bf_insns = NULL; 11830 if (bf->bf_len == 0) { 11831 /* legal, matches everything */ 11832 continue; 11833 } 11834 len = bf->bf_len * sizeof(*bf->bf_insns); 11835 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11836 rc = copyin(u, bf->bf_insns, len); 11837 if (rc != 0) 11838 goto error; 11839 11840 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 11841 rc = EINVAL; 11842 goto error; 11843 } 11844 } 11845 set_policy: 11846 rw_wlock(&sc->policy_lock); 11847 old = sc->policy; 11848 sc->policy = op; 11849 rw_wunlock(&sc->policy_lock); 11850 free_offload_policy(old); 11851 11852 return (0); 11853 } 11854 11855 #define MAX_READ_BUF_SIZE (128 * 1024) 11856 static int 11857 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 11858 { 11859 uint32_t addr, remaining, n; 11860 uint32_t *buf; 11861 int rc; 11862 uint8_t *dst; 11863 11864 mtx_lock(&sc->reg_lock); 11865 if (hw_off_limits(sc)) 11866 rc = ENXIO; 11867 else 11868 rc = validate_mem_range(sc, mr->addr, mr->len); 11869 mtx_unlock(&sc->reg_lock); 11870 if (rc != 0) 11871 return (rc); 11872 11873 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 11874 addr = mr->addr; 11875 remaining = mr->len; 11876 dst = (void *)mr->data; 11877 11878 while (remaining) { 11879 n = min(remaining, MAX_READ_BUF_SIZE); 11880 mtx_lock(&sc->reg_lock); 11881 if (hw_off_limits(sc)) 11882 rc = ENXIO; 11883 else 11884 read_via_memwin(sc, 2, addr, buf, n); 11885 mtx_unlock(&sc->reg_lock); 11886 if (rc != 0) 11887 break; 11888 11889 rc = copyout(buf, dst, n); 11890 if (rc != 0) 11891 break; 11892 11893 dst += n; 11894 remaining -= n; 11895 addr += n; 11896 } 11897 11898 free(buf, M_CXGBE); 11899 return (rc); 11900 } 11901 #undef MAX_READ_BUF_SIZE 11902 11903 static int 11904 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 11905 { 11906 int rc; 11907 11908 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 11909 return (EINVAL); 11910 11911 if (i2cd->len > sizeof(i2cd->data)) 11912 return (EFBIG); 11913 11914 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 11915 if (rc) 11916 return (rc); 11917 if (hw_off_limits(sc)) 11918 rc = ENXIO; 11919 else 11920 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 11921 i2cd->offset, i2cd->len, &i2cd->data[0]); 11922 end_synchronized_op(sc, 0); 11923 11924 return (rc); 11925 } 11926 11927 static int 11928 clear_stats(struct adapter *sc, u_int port_id) 11929 { 11930 int i, v, chan_map; 11931 struct port_info *pi; 11932 struct vi_info *vi; 11933 struct sge_rxq *rxq; 11934 struct sge_txq *txq; 11935 struct sge_wrq *wrq; 11936 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 11937 struct sge_ofld_txq *ofld_txq; 11938 #endif 11939 #ifdef TCP_OFFLOAD 11940 struct sge_ofld_rxq *ofld_rxq; 11941 #endif 11942 11943 if (port_id >= sc->params.nports) 11944 return (EINVAL); 11945 pi = sc->port[port_id]; 11946 if (pi == NULL) 11947 return (EIO); 11948 11949 mtx_lock(&sc->reg_lock); 11950 if (!hw_off_limits(sc)) { 11951 /* MAC stats */ 11952 t4_clr_port_stats(sc, pi->tx_chan); 11953 if (is_t6(sc)) { 11954 if (pi->fcs_reg != -1) 11955 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 11956 else 11957 pi->stats.rx_fcs_err = 0; 11958 } 11959 for_each_vi(pi, v, vi) { 11960 if (vi->flags & VI_INIT_DONE) 11961 t4_clr_vi_stats(sc, vi->vin); 11962 } 11963 chan_map = pi->rx_e_chan_map; 11964 v = 0; /* reuse */ 11965 while (chan_map) { 11966 i = ffs(chan_map) - 1; 11967 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 11968 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 11969 chan_map &= ~(1 << i); 11970 } 11971 } 11972 mtx_unlock(&sc->reg_lock); 11973 pi->tx_parse_error = 0; 11974 pi->tnl_cong_drops = 0; 11975 11976 /* 11977 * Since this command accepts a port, clear stats for 11978 * all VIs on this port. 11979 */ 11980 for_each_vi(pi, v, vi) { 11981 if (vi->flags & VI_INIT_DONE) { 11982 11983 for_each_rxq(vi, i, rxq) { 11984 #if defined(INET) || defined(INET6) 11985 rxq->lro.lro_queued = 0; 11986 rxq->lro.lro_flushed = 0; 11987 #endif 11988 rxq->rxcsum = 0; 11989 rxq->vlan_extraction = 0; 11990 rxq->vxlan_rxcsum = 0; 11991 11992 rxq->fl.cl_allocated = 0; 11993 rxq->fl.cl_recycled = 0; 11994 rxq->fl.cl_fast_recycled = 0; 11995 } 11996 11997 for_each_txq(vi, i, txq) { 11998 txq->txcsum = 0; 11999 txq->tso_wrs = 0; 12000 txq->vlan_insertion = 0; 12001 txq->imm_wrs = 0; 12002 txq->sgl_wrs = 0; 12003 txq->txpkt_wrs = 0; 12004 txq->txpkts0_wrs = 0; 12005 txq->txpkts1_wrs = 0; 12006 txq->txpkts0_pkts = 0; 12007 txq->txpkts1_pkts = 0; 12008 txq->txpkts_flush = 0; 12009 txq->raw_wrs = 0; 12010 txq->vxlan_tso_wrs = 0; 12011 txq->vxlan_txcsum = 0; 12012 txq->kern_tls_records = 0; 12013 txq->kern_tls_short = 0; 12014 txq->kern_tls_partial = 0; 12015 txq->kern_tls_full = 0; 12016 txq->kern_tls_octets = 0; 12017 txq->kern_tls_waste = 0; 12018 txq->kern_tls_options = 0; 12019 txq->kern_tls_header = 0; 12020 txq->kern_tls_fin = 0; 12021 txq->kern_tls_fin_short = 0; 12022 txq->kern_tls_cbc = 0; 12023 txq->kern_tls_gcm = 0; 12024 mp_ring_reset_stats(txq->r); 12025 } 12026 12027 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12028 for_each_ofld_txq(vi, i, ofld_txq) { 12029 ofld_txq->wrq.tx_wrs_direct = 0; 12030 ofld_txq->wrq.tx_wrs_copied = 0; 12031 counter_u64_zero(ofld_txq->tx_iscsi_pdus); 12032 counter_u64_zero(ofld_txq->tx_iscsi_octets); 12033 counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs); 12034 counter_u64_zero(ofld_txq->tx_aio_jobs); 12035 counter_u64_zero(ofld_txq->tx_aio_octets); 12036 counter_u64_zero(ofld_txq->tx_toe_tls_records); 12037 counter_u64_zero(ofld_txq->tx_toe_tls_octets); 12038 } 12039 #endif 12040 #ifdef TCP_OFFLOAD 12041 for_each_ofld_rxq(vi, i, ofld_rxq) { 12042 ofld_rxq->fl.cl_allocated = 0; 12043 ofld_rxq->fl.cl_recycled = 0; 12044 ofld_rxq->fl.cl_fast_recycled = 0; 12045 counter_u64_zero( 12046 ofld_rxq->rx_iscsi_ddp_setup_ok); 12047 counter_u64_zero( 12048 ofld_rxq->rx_iscsi_ddp_setup_error); 12049 ofld_rxq->rx_iscsi_ddp_pdus = 0; 12050 ofld_rxq->rx_iscsi_ddp_octets = 0; 12051 ofld_rxq->rx_iscsi_fl_pdus = 0; 12052 ofld_rxq->rx_iscsi_fl_octets = 0; 12053 ofld_rxq->rx_aio_ddp_jobs = 0; 12054 ofld_rxq->rx_aio_ddp_octets = 0; 12055 ofld_rxq->rx_toe_tls_records = 0; 12056 ofld_rxq->rx_toe_tls_octets = 0; 12057 ofld_rxq->rx_toe_ddp_octets = 0; 12058 counter_u64_zero(ofld_rxq->ddp_buffer_alloc); 12059 counter_u64_zero(ofld_rxq->ddp_buffer_reuse); 12060 counter_u64_zero(ofld_rxq->ddp_buffer_free); 12061 } 12062 #endif 12063 12064 if (IS_MAIN_VI(vi)) { 12065 wrq = &sc->sge.ctrlq[pi->port_id]; 12066 wrq->tx_wrs_direct = 0; 12067 wrq->tx_wrs_copied = 0; 12068 } 12069 } 12070 } 12071 12072 return (0); 12073 } 12074 12075 static int 12076 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12077 { 12078 #ifdef INET6 12079 struct in6_addr in6; 12080 12081 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12082 if (t4_get_clip_entry(sc, &in6, true) != NULL) 12083 return (0); 12084 else 12085 return (EIO); 12086 #else 12087 return (ENOTSUP); 12088 #endif 12089 } 12090 12091 static int 12092 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12093 { 12094 #ifdef INET6 12095 struct in6_addr in6; 12096 12097 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12098 return (t4_release_clip_addr(sc, &in6)); 12099 #else 12100 return (ENOTSUP); 12101 #endif 12102 } 12103 12104 int 12105 t4_os_find_pci_capability(struct adapter *sc, int cap) 12106 { 12107 int i; 12108 12109 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 12110 } 12111 12112 int 12113 t4_os_pci_save_state(struct adapter *sc) 12114 { 12115 device_t dev; 12116 struct pci_devinfo *dinfo; 12117 12118 dev = sc->dev; 12119 dinfo = device_get_ivars(dev); 12120 12121 pci_cfg_save(dev, dinfo, 0); 12122 return (0); 12123 } 12124 12125 int 12126 t4_os_pci_restore_state(struct adapter *sc) 12127 { 12128 device_t dev; 12129 struct pci_devinfo *dinfo; 12130 12131 dev = sc->dev; 12132 dinfo = device_get_ivars(dev); 12133 12134 pci_cfg_restore(dev, dinfo); 12135 return (0); 12136 } 12137 12138 void 12139 t4_os_portmod_changed(struct port_info *pi) 12140 { 12141 struct adapter *sc = pi->adapter; 12142 struct vi_info *vi; 12143 if_t ifp; 12144 static const char *mod_str[] = { 12145 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 12146 }; 12147 12148 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 12149 ("%s: port_type %u", __func__, pi->port_type)); 12150 12151 vi = &pi->vi[0]; 12152 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 12153 PORT_LOCK(pi); 12154 build_medialist(pi); 12155 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 12156 fixup_link_config(pi); 12157 apply_link_config(pi); 12158 } 12159 PORT_UNLOCK(pi); 12160 end_synchronized_op(sc, LOCK_HELD); 12161 } 12162 12163 ifp = vi->ifp; 12164 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 12165 if_printf(ifp, "transceiver unplugged.\n"); 12166 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 12167 if_printf(ifp, "unknown transceiver inserted.\n"); 12168 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 12169 if_printf(ifp, "unsupported transceiver inserted.\n"); 12170 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 12171 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 12172 port_top_speed(pi), mod_str[pi->mod_type]); 12173 } else { 12174 if_printf(ifp, "transceiver (type %d) inserted.\n", 12175 pi->mod_type); 12176 } 12177 } 12178 12179 void 12180 t4_os_link_changed(struct port_info *pi) 12181 { 12182 struct vi_info *vi; 12183 if_t ifp; 12184 struct link_config *lc = &pi->link_cfg; 12185 struct adapter *sc = pi->adapter; 12186 int v; 12187 12188 PORT_LOCK_ASSERT_OWNED(pi); 12189 12190 if (is_t6(sc)) { 12191 if (lc->link_ok) { 12192 if (lc->speed > 25000 || 12193 (lc->speed == 25000 && lc->fec == FEC_RS)) { 12194 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12195 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS); 12196 } else { 12197 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12198 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS); 12199 } 12200 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 12201 pi->stats.rx_fcs_err = 0; 12202 } else { 12203 pi->fcs_reg = -1; 12204 } 12205 } else { 12206 MPASS(pi->fcs_reg != -1); 12207 MPASS(pi->fcs_base == 0); 12208 } 12209 12210 for_each_vi(pi, v, vi) { 12211 ifp = vi->ifp; 12212 if (ifp == NULL || IS_DETACHING(vi)) 12213 continue; 12214 12215 if (lc->link_ok) { 12216 if_setbaudrate(ifp, IF_Mbps(lc->speed)); 12217 if_link_state_change(ifp, LINK_STATE_UP); 12218 } else { 12219 if_link_state_change(ifp, LINK_STATE_DOWN); 12220 } 12221 } 12222 } 12223 12224 void 12225 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 12226 { 12227 struct adapter *sc; 12228 12229 sx_slock(&t4_list_lock); 12230 SLIST_FOREACH(sc, &t4_list, link) { 12231 /* 12232 * func should not make any assumptions about what state sc is 12233 * in - the only guarantee is that sc->sc_lock is a valid lock. 12234 */ 12235 func(sc, arg); 12236 } 12237 sx_sunlock(&t4_list_lock); 12238 } 12239 12240 static int 12241 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 12242 struct thread *td) 12243 { 12244 int rc; 12245 struct adapter *sc = dev->si_drv1; 12246 12247 rc = priv_check(td, PRIV_DRIVER); 12248 if (rc != 0) 12249 return (rc); 12250 12251 switch (cmd) { 12252 case CHELSIO_T4_GETREG: { 12253 struct t4_reg *edata = (struct t4_reg *)data; 12254 12255 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12256 return (EFAULT); 12257 12258 mtx_lock(&sc->reg_lock); 12259 if (hw_off_limits(sc)) 12260 rc = ENXIO; 12261 else if (edata->size == 4) 12262 edata->val = t4_read_reg(sc, edata->addr); 12263 else if (edata->size == 8) 12264 edata->val = t4_read_reg64(sc, edata->addr); 12265 else 12266 rc = EINVAL; 12267 mtx_unlock(&sc->reg_lock); 12268 12269 break; 12270 } 12271 case CHELSIO_T4_SETREG: { 12272 struct t4_reg *edata = (struct t4_reg *)data; 12273 12274 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12275 return (EFAULT); 12276 12277 mtx_lock(&sc->reg_lock); 12278 if (hw_off_limits(sc)) 12279 rc = ENXIO; 12280 else if (edata->size == 4) { 12281 if (edata->val & 0xffffffff00000000) 12282 rc = EINVAL; 12283 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 12284 } else if (edata->size == 8) 12285 t4_write_reg64(sc, edata->addr, edata->val); 12286 else 12287 rc = EINVAL; 12288 mtx_unlock(&sc->reg_lock); 12289 12290 break; 12291 } 12292 case CHELSIO_T4_REGDUMP: { 12293 struct t4_regdump *regs = (struct t4_regdump *)data; 12294 int reglen = t4_get_regs_len(sc); 12295 uint8_t *buf; 12296 12297 if (regs->len < reglen) { 12298 regs->len = reglen; /* hint to the caller */ 12299 return (ENOBUFS); 12300 } 12301 12302 regs->len = reglen; 12303 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 12304 mtx_lock(&sc->reg_lock); 12305 if (hw_off_limits(sc)) 12306 rc = ENXIO; 12307 else 12308 get_regs(sc, regs, buf); 12309 mtx_unlock(&sc->reg_lock); 12310 if (rc == 0) 12311 rc = copyout(buf, regs->data, reglen); 12312 free(buf, M_CXGBE); 12313 break; 12314 } 12315 case CHELSIO_T4_GET_FILTER_MODE: 12316 rc = get_filter_mode(sc, (uint32_t *)data); 12317 break; 12318 case CHELSIO_T4_SET_FILTER_MODE: 12319 rc = set_filter_mode(sc, *(uint32_t *)data); 12320 break; 12321 case CHELSIO_T4_SET_FILTER_MASK: 12322 rc = set_filter_mask(sc, *(uint32_t *)data); 12323 break; 12324 case CHELSIO_T4_GET_FILTER: 12325 rc = get_filter(sc, (struct t4_filter *)data); 12326 break; 12327 case CHELSIO_T4_SET_FILTER: 12328 rc = set_filter(sc, (struct t4_filter *)data); 12329 break; 12330 case CHELSIO_T4_DEL_FILTER: 12331 rc = del_filter(sc, (struct t4_filter *)data); 12332 break; 12333 case CHELSIO_T4_GET_SGE_CONTEXT: 12334 rc = get_sge_context(sc, (struct t4_sge_context *)data); 12335 break; 12336 case CHELSIO_T4_LOAD_FW: 12337 rc = load_fw(sc, (struct t4_data *)data); 12338 break; 12339 case CHELSIO_T4_GET_MEM: 12340 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 12341 break; 12342 case CHELSIO_T4_GET_I2C: 12343 rc = read_i2c(sc, (struct t4_i2c_data *)data); 12344 break; 12345 case CHELSIO_T4_CLEAR_STATS: 12346 rc = clear_stats(sc, *(uint32_t *)data); 12347 break; 12348 case CHELSIO_T4_SCHED_CLASS: 12349 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 12350 break; 12351 case CHELSIO_T4_SCHED_QUEUE: 12352 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 12353 break; 12354 case CHELSIO_T4_GET_TRACER: 12355 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 12356 break; 12357 case CHELSIO_T4_SET_TRACER: 12358 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 12359 break; 12360 case CHELSIO_T4_LOAD_CFG: 12361 rc = load_cfg(sc, (struct t4_data *)data); 12362 break; 12363 case CHELSIO_T4_LOAD_BOOT: 12364 rc = load_boot(sc, (struct t4_bootrom *)data); 12365 break; 12366 case CHELSIO_T4_LOAD_BOOTCFG: 12367 rc = load_bootcfg(sc, (struct t4_data *)data); 12368 break; 12369 case CHELSIO_T4_CUDBG_DUMP: 12370 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 12371 break; 12372 case CHELSIO_T4_SET_OFLD_POLICY: 12373 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 12374 break; 12375 case CHELSIO_T4_HOLD_CLIP_ADDR: 12376 rc = hold_clip_addr(sc, (struct t4_clip_addr *)data); 12377 break; 12378 case CHELSIO_T4_RELEASE_CLIP_ADDR: 12379 rc = release_clip_addr(sc, (struct t4_clip_addr *)data); 12380 break; 12381 default: 12382 rc = ENOTTY; 12383 } 12384 12385 return (rc); 12386 } 12387 12388 #ifdef TCP_OFFLOAD 12389 static int 12390 toe_capability(struct vi_info *vi, bool enable) 12391 { 12392 int rc; 12393 struct port_info *pi = vi->pi; 12394 struct adapter *sc = pi->adapter; 12395 12396 ASSERT_SYNCHRONIZED_OP(sc); 12397 12398 if (!is_offload(sc)) 12399 return (ENODEV); 12400 if (hw_off_limits(sc)) 12401 return (ENXIO); 12402 12403 if (enable) { 12404 #ifdef KERN_TLS 12405 if (sc->flags & KERN_TLS_ON && is_t6(sc)) { 12406 int i, j, n; 12407 struct port_info *p; 12408 struct vi_info *v; 12409 12410 /* 12411 * Reconfigure hardware for TOE if TXTLS is not enabled 12412 * on any ifnet. 12413 */ 12414 n = 0; 12415 for_each_port(sc, i) { 12416 p = sc->port[i]; 12417 for_each_vi(p, j, v) { 12418 if (if_getcapenable(v->ifp) & IFCAP_TXTLS) { 12419 CH_WARN(sc, 12420 "%s has NIC TLS enabled.\n", 12421 device_get_nameunit(v->dev)); 12422 n++; 12423 } 12424 } 12425 } 12426 if (n > 0) { 12427 CH_WARN(sc, "Disable NIC TLS on all interfaces " 12428 "associated with this adapter before " 12429 "trying to enable TOE.\n"); 12430 return (EAGAIN); 12431 } 12432 rc = t6_config_kern_tls(sc, false); 12433 if (rc) 12434 return (rc); 12435 } 12436 #endif 12437 if ((if_getcapenable(vi->ifp) & IFCAP_TOE) != 0) { 12438 /* TOE is already enabled. */ 12439 return (0); 12440 } 12441 12442 /* 12443 * We need the port's queues around so that we're able to send 12444 * and receive CPLs to/from the TOE even if the ifnet for this 12445 * port has never been UP'd administratively. 12446 */ 12447 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 12448 return (rc); 12449 if (!(pi->vi[0].flags & VI_INIT_DONE) && 12450 ((rc = vi_init(&pi->vi[0])) != 0)) 12451 return (rc); 12452 12453 if (isset(&sc->offload_map, pi->port_id)) { 12454 /* TOE is enabled on another VI of this port. */ 12455 pi->uld_vis++; 12456 return (0); 12457 } 12458 12459 if (!uld_active(sc, ULD_TOM)) { 12460 rc = t4_activate_uld(sc, ULD_TOM); 12461 if (rc == EAGAIN) { 12462 log(LOG_WARNING, 12463 "You must kldload t4_tom.ko before trying " 12464 "to enable TOE on a cxgbe interface.\n"); 12465 } 12466 if (rc != 0) 12467 return (rc); 12468 KASSERT(sc->tom_softc != NULL, 12469 ("%s: TOM activated but softc NULL", __func__)); 12470 KASSERT(uld_active(sc, ULD_TOM), 12471 ("%s: TOM activated but flag not set", __func__)); 12472 } 12473 12474 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 12475 if (!uld_active(sc, ULD_IWARP)) 12476 (void) t4_activate_uld(sc, ULD_IWARP); 12477 if (!uld_active(sc, ULD_ISCSI)) 12478 (void) t4_activate_uld(sc, ULD_ISCSI); 12479 12480 pi->uld_vis++; 12481 setbit(&sc->offload_map, pi->port_id); 12482 } else { 12483 pi->uld_vis--; 12484 12485 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 12486 return (0); 12487 12488 KASSERT(uld_active(sc, ULD_TOM), 12489 ("%s: TOM never initialized?", __func__)); 12490 clrbit(&sc->offload_map, pi->port_id); 12491 } 12492 12493 return (0); 12494 } 12495 12496 /* 12497 * Add an upper layer driver to the global list. 12498 */ 12499 int 12500 t4_register_uld(struct uld_info *ui, int id) 12501 { 12502 int rc; 12503 12504 if (id < 0 || id > ULD_MAX) 12505 return (EINVAL); 12506 sx_xlock(&t4_uld_list_lock); 12507 if (t4_uld_list[id] != NULL) 12508 rc = EEXIST; 12509 else { 12510 t4_uld_list[id] = ui; 12511 rc = 0; 12512 } 12513 sx_xunlock(&t4_uld_list_lock); 12514 return (rc); 12515 } 12516 12517 int 12518 t4_unregister_uld(struct uld_info *ui, int id) 12519 { 12520 12521 if (id < 0 || id > ULD_MAX) 12522 return (EINVAL); 12523 sx_xlock(&t4_uld_list_lock); 12524 MPASS(t4_uld_list[id] == ui); 12525 t4_uld_list[id] = NULL; 12526 sx_xunlock(&t4_uld_list_lock); 12527 return (0); 12528 } 12529 12530 int 12531 t4_activate_uld(struct adapter *sc, int id) 12532 { 12533 int rc; 12534 12535 ASSERT_SYNCHRONIZED_OP(sc); 12536 12537 if (id < 0 || id > ULD_MAX) 12538 return (EINVAL); 12539 12540 /* Adapter needs to be initialized before any ULD can be activated. */ 12541 if (!(sc->flags & FULL_INIT_DONE)) { 12542 rc = adapter_init(sc); 12543 if (rc != 0) 12544 return (rc); 12545 } 12546 12547 sx_slock(&t4_uld_list_lock); 12548 if (t4_uld_list[id] == NULL) 12549 rc = EAGAIN; /* load the KLD with this ULD and try again. */ 12550 else { 12551 rc = t4_uld_list[id]->uld_activate(sc); 12552 if (rc == 0) 12553 setbit(&sc->active_ulds, id); 12554 } 12555 sx_sunlock(&t4_uld_list_lock); 12556 12557 return (rc); 12558 } 12559 12560 int 12561 t4_deactivate_uld(struct adapter *sc, int id) 12562 { 12563 int rc; 12564 12565 ASSERT_SYNCHRONIZED_OP(sc); 12566 12567 if (id < 0 || id > ULD_MAX) 12568 return (EINVAL); 12569 12570 sx_slock(&t4_uld_list_lock); 12571 if (t4_uld_list[id] == NULL) 12572 rc = ENXIO; 12573 else { 12574 rc = t4_uld_list[id]->uld_deactivate(sc); 12575 if (rc == 0) 12576 clrbit(&sc->active_ulds, id); 12577 } 12578 sx_sunlock(&t4_uld_list_lock); 12579 12580 return (rc); 12581 } 12582 12583 static int 12584 deactivate_all_uld(struct adapter *sc) 12585 { 12586 int i, rc; 12587 12588 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld"); 12589 if (rc != 0) 12590 return (ENXIO); 12591 sx_slock(&t4_uld_list_lock); 12592 for (i = 0; i <= ULD_MAX; i++) { 12593 if (t4_uld_list[i] == NULL || !uld_active(sc, i)) 12594 continue; 12595 rc = t4_uld_list[i]->uld_deactivate(sc); 12596 if (rc != 0) 12597 break; 12598 clrbit(&sc->active_ulds, i); 12599 } 12600 sx_sunlock(&t4_uld_list_lock); 12601 end_synchronized_op(sc, 0); 12602 12603 return (rc); 12604 } 12605 12606 static void 12607 stop_all_uld(struct adapter *sc) 12608 { 12609 int i; 12610 12611 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldst") != 0) 12612 return; 12613 sx_slock(&t4_uld_list_lock); 12614 for (i = 0; i <= ULD_MAX; i++) { 12615 if (t4_uld_list[i] == NULL || !uld_active(sc, i) || 12616 t4_uld_list[i]->uld_stop == NULL) 12617 continue; 12618 (void) t4_uld_list[i]->uld_stop(sc); 12619 } 12620 sx_sunlock(&t4_uld_list_lock); 12621 end_synchronized_op(sc, 0); 12622 } 12623 12624 static void 12625 restart_all_uld(struct adapter *sc) 12626 { 12627 int i; 12628 12629 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldre") != 0) 12630 return; 12631 sx_slock(&t4_uld_list_lock); 12632 for (i = 0; i <= ULD_MAX; i++) { 12633 if (t4_uld_list[i] == NULL || !uld_active(sc, i) || 12634 t4_uld_list[i]->uld_restart == NULL) 12635 continue; 12636 (void) t4_uld_list[i]->uld_restart(sc); 12637 } 12638 sx_sunlock(&t4_uld_list_lock); 12639 end_synchronized_op(sc, 0); 12640 } 12641 12642 int 12643 uld_active(struct adapter *sc, int id) 12644 { 12645 12646 MPASS(id >= 0 && id <= ULD_MAX); 12647 12648 return (isset(&sc->active_ulds, id)); 12649 } 12650 #endif 12651 12652 #ifdef KERN_TLS 12653 static int 12654 ktls_capability(struct adapter *sc, bool enable) 12655 { 12656 ASSERT_SYNCHRONIZED_OP(sc); 12657 12658 if (!is_ktls(sc)) 12659 return (ENODEV); 12660 if (!is_t6(sc)) 12661 return (0); 12662 if (hw_off_limits(sc)) 12663 return (ENXIO); 12664 12665 if (enable) { 12666 if (sc->flags & KERN_TLS_ON) 12667 return (0); /* already on */ 12668 if (sc->offload_map != 0) { 12669 CH_WARN(sc, 12670 "Disable TOE on all interfaces associated with " 12671 "this adapter before trying to enable NIC TLS.\n"); 12672 return (EAGAIN); 12673 } 12674 return (t6_config_kern_tls(sc, true)); 12675 } else { 12676 /* 12677 * Nothing to do for disable. If TOE is enabled sometime later 12678 * then toe_capability will reconfigure the hardware. 12679 */ 12680 return (0); 12681 } 12682 } 12683 #endif 12684 12685 /* 12686 * t = ptr to tunable. 12687 * nc = number of CPUs. 12688 * c = compiled in default for that tunable. 12689 */ 12690 static void 12691 calculate_nqueues(int *t, int nc, const int c) 12692 { 12693 int nq; 12694 12695 if (*t > 0) 12696 return; 12697 nq = *t < 0 ? -*t : c; 12698 *t = min(nc, nq); 12699 } 12700 12701 /* 12702 * Come up with reasonable defaults for some of the tunables, provided they're 12703 * not set by the user (in which case we'll use the values as is). 12704 */ 12705 static void 12706 tweak_tunables(void) 12707 { 12708 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 12709 12710 if (t4_ntxq < 1) { 12711 #ifdef RSS 12712 t4_ntxq = rss_getnumbuckets(); 12713 #else 12714 calculate_nqueues(&t4_ntxq, nc, NTXQ); 12715 #endif 12716 } 12717 12718 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 12719 12720 if (t4_nrxq < 1) { 12721 #ifdef RSS 12722 t4_nrxq = rss_getnumbuckets(); 12723 #else 12724 calculate_nqueues(&t4_nrxq, nc, NRXQ); 12725 #endif 12726 } 12727 12728 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 12729 12730 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12731 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 12732 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 12733 #endif 12734 #ifdef TCP_OFFLOAD 12735 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 12736 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 12737 #endif 12738 12739 #if defined(TCP_OFFLOAD) || defined(KERN_TLS) 12740 if (t4_toecaps_allowed == -1) 12741 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 12742 #else 12743 if (t4_toecaps_allowed == -1) 12744 t4_toecaps_allowed = 0; 12745 #endif 12746 12747 #ifdef TCP_OFFLOAD 12748 if (t4_rdmacaps_allowed == -1) { 12749 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 12750 FW_CAPS_CONFIG_RDMA_RDMAC; 12751 } 12752 12753 if (t4_iscsicaps_allowed == -1) { 12754 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 12755 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 12756 FW_CAPS_CONFIG_ISCSI_T10DIF; 12757 } 12758 12759 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 12760 t4_tmr_idx_ofld = TMR_IDX_OFLD; 12761 12762 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 12763 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 12764 #else 12765 if (t4_rdmacaps_allowed == -1) 12766 t4_rdmacaps_allowed = 0; 12767 12768 if (t4_iscsicaps_allowed == -1) 12769 t4_iscsicaps_allowed = 0; 12770 #endif 12771 12772 #ifdef DEV_NETMAP 12773 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ); 12774 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ); 12775 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 12776 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 12777 #endif 12778 12779 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 12780 t4_tmr_idx = TMR_IDX; 12781 12782 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 12783 t4_pktc_idx = PKTC_IDX; 12784 12785 if (t4_qsize_txq < 128) 12786 t4_qsize_txq = 128; 12787 12788 if (t4_qsize_rxq < 128) 12789 t4_qsize_rxq = 128; 12790 while (t4_qsize_rxq & 7) 12791 t4_qsize_rxq++; 12792 12793 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 12794 12795 /* 12796 * Number of VIs to create per-port. The first VI is the "main" regular 12797 * VI for the port. The rest are additional virtual interfaces on the 12798 * same physical port. Note that the main VI does not have native 12799 * netmap support but the extra VIs do. 12800 * 12801 * Limit the number of VIs per port to the number of available 12802 * MAC addresses per port. 12803 */ 12804 if (t4_num_vis < 1) 12805 t4_num_vis = 1; 12806 if (t4_num_vis > nitems(vi_mac_funcs)) { 12807 t4_num_vis = nitems(vi_mac_funcs); 12808 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 12809 } 12810 12811 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 12812 pcie_relaxed_ordering = 1; 12813 #if defined(__i386__) || defined(__amd64__) 12814 if (cpu_vendor_id == CPU_VENDOR_INTEL) 12815 pcie_relaxed_ordering = 0; 12816 #endif 12817 } 12818 } 12819 12820 #ifdef DDB 12821 static void 12822 t4_dump_mem(struct adapter *sc, u_int addr, u_int len) 12823 { 12824 uint32_t base, j, off, pf, reg, save, win_pos; 12825 12826 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 12827 save = t4_read_reg(sc, reg); 12828 base = sc->memwin[2].mw_base; 12829 12830 if (is_t4(sc)) { 12831 pf = 0; 12832 win_pos = addr & ~0xf; /* start must be 16B aligned */ 12833 } else { 12834 pf = V_PFNUM(sc->pf); 12835 win_pos = addr & ~0x7f; /* start must be 128B aligned */ 12836 } 12837 off = addr - win_pos; 12838 t4_write_reg(sc, reg, win_pos | pf); 12839 t4_read_reg(sc, reg); 12840 12841 while (len > 0 && !db_pager_quit) { 12842 uint32_t buf[8]; 12843 for (j = 0; j < 8; j++, off += 4) 12844 buf[j] = htonl(t4_read_reg(sc, base + off)); 12845 12846 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 12847 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 12848 buf[7]); 12849 if (len <= sizeof(buf)) 12850 len = 0; 12851 else 12852 len -= sizeof(buf); 12853 } 12854 12855 t4_write_reg(sc, reg, save); 12856 t4_read_reg(sc, reg); 12857 } 12858 12859 static void 12860 t4_dump_tcb(struct adapter *sc, int tid) 12861 { 12862 uint32_t tcb_addr; 12863 12864 /* Dump TCB for the tid */ 12865 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 12866 tcb_addr += tid * TCB_SIZE; 12867 t4_dump_mem(sc, tcb_addr, TCB_SIZE); 12868 } 12869 12870 static void 12871 t4_dump_devlog(struct adapter *sc) 12872 { 12873 struct devlog_params *dparams = &sc->params.devlog; 12874 struct fw_devlog_e e; 12875 int i, first, j, m, nentries, rc; 12876 uint64_t ftstamp = UINT64_MAX; 12877 12878 if (dparams->start == 0) { 12879 db_printf("devlog params not valid\n"); 12880 return; 12881 } 12882 12883 nentries = dparams->size / sizeof(struct fw_devlog_e); 12884 m = fwmtype_to_hwmtype(dparams->memtype); 12885 12886 /* Find the first entry. */ 12887 first = -1; 12888 for (i = 0; i < nentries && !db_pager_quit; i++) { 12889 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12890 sizeof(e), (void *)&e); 12891 if (rc != 0) 12892 break; 12893 12894 if (e.timestamp == 0) 12895 break; 12896 12897 e.timestamp = be64toh(e.timestamp); 12898 if (e.timestamp < ftstamp) { 12899 ftstamp = e.timestamp; 12900 first = i; 12901 } 12902 } 12903 12904 if (first == -1) 12905 return; 12906 12907 i = first; 12908 do { 12909 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12910 sizeof(e), (void *)&e); 12911 if (rc != 0) 12912 return; 12913 12914 if (e.timestamp == 0) 12915 return; 12916 12917 e.timestamp = be64toh(e.timestamp); 12918 e.seqno = be32toh(e.seqno); 12919 for (j = 0; j < 8; j++) 12920 e.params[j] = be32toh(e.params[j]); 12921 12922 db_printf("%10d %15ju %8s %8s ", 12923 e.seqno, e.timestamp, 12924 (e.level < nitems(devlog_level_strings) ? 12925 devlog_level_strings[e.level] : "UNKNOWN"), 12926 (e.facility < nitems(devlog_facility_strings) ? 12927 devlog_facility_strings[e.facility] : "UNKNOWN")); 12928 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 12929 e.params[3], e.params[4], e.params[5], e.params[6], 12930 e.params[7]); 12931 12932 if (++i == nentries) 12933 i = 0; 12934 } while (i != first && !db_pager_quit); 12935 } 12936 12937 static DB_DEFINE_TABLE(show, t4, show_t4); 12938 12939 DB_TABLE_COMMAND_FLAGS(show_t4, devlog, db_show_devlog, CS_OWN) 12940 { 12941 device_t dev; 12942 int t; 12943 bool valid; 12944 12945 valid = false; 12946 t = db_read_token(); 12947 if (t == tIDENT) { 12948 dev = device_lookup_by_name(db_tok_string); 12949 valid = true; 12950 } 12951 db_skip_to_eol(); 12952 if (!valid) { 12953 db_printf("usage: show t4 devlog <nexus>\n"); 12954 return; 12955 } 12956 12957 if (dev == NULL) { 12958 db_printf("device not found\n"); 12959 return; 12960 } 12961 12962 t4_dump_devlog(device_get_softc(dev)); 12963 } 12964 12965 DB_TABLE_COMMAND_FLAGS(show_t4, tcb, db_show_t4tcb, CS_OWN) 12966 { 12967 device_t dev; 12968 int radix, tid, t; 12969 bool valid; 12970 12971 valid = false; 12972 radix = db_radix; 12973 db_radix = 10; 12974 t = db_read_token(); 12975 if (t == tIDENT) { 12976 dev = device_lookup_by_name(db_tok_string); 12977 t = db_read_token(); 12978 if (t == tNUMBER) { 12979 tid = db_tok_number; 12980 valid = true; 12981 } 12982 } 12983 db_radix = radix; 12984 db_skip_to_eol(); 12985 if (!valid) { 12986 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 12987 return; 12988 } 12989 12990 if (dev == NULL) { 12991 db_printf("device not found\n"); 12992 return; 12993 } 12994 if (tid < 0) { 12995 db_printf("invalid tid\n"); 12996 return; 12997 } 12998 12999 t4_dump_tcb(device_get_softc(dev), tid); 13000 } 13001 13002 DB_TABLE_COMMAND_FLAGS(show_t4, memdump, db_show_memdump, CS_OWN) 13003 { 13004 device_t dev; 13005 int radix, t; 13006 bool valid; 13007 13008 valid = false; 13009 radix = db_radix; 13010 db_radix = 10; 13011 t = db_read_token(); 13012 if (t == tIDENT) { 13013 dev = device_lookup_by_name(db_tok_string); 13014 t = db_read_token(); 13015 if (t == tNUMBER) { 13016 addr = db_tok_number; 13017 t = db_read_token(); 13018 if (t == tNUMBER) { 13019 count = db_tok_number; 13020 valid = true; 13021 } 13022 } 13023 } 13024 db_radix = radix; 13025 db_skip_to_eol(); 13026 if (!valid) { 13027 db_printf("usage: show t4 memdump <nexus> <addr> <len>\n"); 13028 return; 13029 } 13030 13031 if (dev == NULL) { 13032 db_printf("device not found\n"); 13033 return; 13034 } 13035 if (addr < 0) { 13036 db_printf("invalid address\n"); 13037 return; 13038 } 13039 if (count <= 0) { 13040 db_printf("invalid length\n"); 13041 return; 13042 } 13043 13044 t4_dump_mem(device_get_softc(dev), addr, count); 13045 } 13046 #endif 13047 13048 static eventhandler_tag vxlan_start_evtag; 13049 static eventhandler_tag vxlan_stop_evtag; 13050 13051 struct vxlan_evargs { 13052 if_t ifp; 13053 uint16_t port; 13054 }; 13055 13056 static void 13057 enable_vxlan_rx(struct adapter *sc) 13058 { 13059 int i, rc; 13060 struct port_info *pi; 13061 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 13062 13063 ASSERT_SYNCHRONIZED_OP(sc); 13064 13065 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) | 13066 F_VXLAN_EN); 13067 for_each_port(sc, i) { 13068 pi = sc->port[i]; 13069 if (pi->vxlan_tcam_entry == true) 13070 continue; 13071 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac, 13072 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 13073 true); 13074 if (rc < 0) { 13075 rc = -rc; 13076 CH_ERR(&pi->vi[0], 13077 "failed to add VXLAN TCAM entry: %d.\n", rc); 13078 } else { 13079 MPASS(rc == sc->rawf_base + pi->port_id); 13080 pi->vxlan_tcam_entry = true; 13081 } 13082 } 13083 } 13084 13085 static void 13086 t4_vxlan_start(struct adapter *sc, void *arg) 13087 { 13088 struct vxlan_evargs *v = arg; 13089 13090 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13091 return; 13092 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0) 13093 return; 13094 13095 if (sc->vxlan_refcount == 0) { 13096 sc->vxlan_port = v->port; 13097 sc->vxlan_refcount = 1; 13098 if (!hw_off_limits(sc)) 13099 enable_vxlan_rx(sc); 13100 } else if (sc->vxlan_port == v->port) { 13101 sc->vxlan_refcount++; 13102 } else { 13103 CH_ERR(sc, "VXLAN already configured on port %d; " 13104 "ignoring attempt to configure it on port %d\n", 13105 sc->vxlan_port, v->port); 13106 } 13107 end_synchronized_op(sc, 0); 13108 } 13109 13110 static void 13111 t4_vxlan_stop(struct adapter *sc, void *arg) 13112 { 13113 struct vxlan_evargs *v = arg; 13114 13115 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13116 return; 13117 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0) 13118 return; 13119 13120 /* 13121 * VXLANs may have been configured before the driver was loaded so we 13122 * may see more stops than starts. This is not handled cleanly but at 13123 * least we keep the refcount sane. 13124 */ 13125 if (sc->vxlan_port != v->port) 13126 goto done; 13127 if (sc->vxlan_refcount == 0) { 13128 CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; " 13129 "ignoring attempt to stop it again.\n", sc->vxlan_port); 13130 } else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc)) 13131 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0); 13132 done: 13133 end_synchronized_op(sc, 0); 13134 } 13135 13136 static void 13137 t4_vxlan_start_handler(void *arg __unused, if_t ifp, 13138 sa_family_t family, u_int port) 13139 { 13140 struct vxlan_evargs v; 13141 13142 MPASS(family == AF_INET || family == AF_INET6); 13143 v.ifp = ifp; 13144 v.port = port; 13145 13146 t4_iterate(t4_vxlan_start, &v); 13147 } 13148 13149 static void 13150 t4_vxlan_stop_handler(void *arg __unused, if_t ifp, sa_family_t family, 13151 u_int port) 13152 { 13153 struct vxlan_evargs v; 13154 13155 MPASS(family == AF_INET || family == AF_INET6); 13156 v.ifp = ifp; 13157 v.port = port; 13158 13159 t4_iterate(t4_vxlan_stop, &v); 13160 } 13161 13162 13163 static struct sx mlu; /* mod load unload */ 13164 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 13165 13166 static int 13167 mod_event(module_t mod, int cmd, void *arg) 13168 { 13169 int rc = 0; 13170 static int loaded = 0; 13171 13172 switch (cmd) { 13173 case MOD_LOAD: 13174 sx_xlock(&mlu); 13175 if (loaded++ == 0) { 13176 t4_sge_modload(); 13177 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13178 t4_filter_rpl, CPL_COOKIE_FILTER); 13179 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 13180 do_l2t_write_rpl, CPL_COOKIE_FILTER); 13181 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 13182 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 13183 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13184 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 13185 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 13186 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 13187 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 13188 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 13189 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 13190 do_smt_write_rpl); 13191 sx_init(&t4_list_lock, "T4/T5 adapters"); 13192 SLIST_INIT(&t4_list); 13193 callout_init(&fatal_callout, 1); 13194 #ifdef TCP_OFFLOAD 13195 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 13196 #endif 13197 #ifdef INET6 13198 t4_clip_modload(); 13199 #endif 13200 #ifdef KERN_TLS 13201 t6_ktls_modload(); 13202 #endif 13203 t4_tracer_modload(); 13204 tweak_tunables(); 13205 vxlan_start_evtag = 13206 EVENTHANDLER_REGISTER(vxlan_start, 13207 t4_vxlan_start_handler, NULL, 13208 EVENTHANDLER_PRI_ANY); 13209 vxlan_stop_evtag = 13210 EVENTHANDLER_REGISTER(vxlan_stop, 13211 t4_vxlan_stop_handler, NULL, 13212 EVENTHANDLER_PRI_ANY); 13213 reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK, 13214 taskqueue_thread_enqueue, &reset_tq); 13215 taskqueue_start_threads(&reset_tq, 1, PI_SOFT, 13216 "t4_rst_thr"); 13217 } 13218 sx_xunlock(&mlu); 13219 break; 13220 13221 case MOD_UNLOAD: 13222 sx_xlock(&mlu); 13223 if (--loaded == 0) { 13224 #ifdef TCP_OFFLOAD 13225 int i; 13226 #endif 13227 int tries; 13228 13229 taskqueue_free(reset_tq); 13230 13231 tries = 0; 13232 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 13233 uprintf("%ju clusters with custom free routine " 13234 "still is use.\n", t4_sge_extfree_refs()); 13235 pause("t4unload", 2 * hz); 13236 } 13237 13238 sx_slock(&t4_list_lock); 13239 if (!SLIST_EMPTY(&t4_list)) { 13240 rc = EBUSY; 13241 sx_sunlock(&t4_list_lock); 13242 goto done_unload; 13243 } 13244 #ifdef TCP_OFFLOAD 13245 sx_slock(&t4_uld_list_lock); 13246 for (i = 0; i <= ULD_MAX; i++) { 13247 if (t4_uld_list[i] != NULL) { 13248 rc = EBUSY; 13249 sx_sunlock(&t4_uld_list_lock); 13250 sx_sunlock(&t4_list_lock); 13251 goto done_unload; 13252 } 13253 } 13254 sx_sunlock(&t4_uld_list_lock); 13255 #endif 13256 sx_sunlock(&t4_list_lock); 13257 13258 if (t4_sge_extfree_refs() == 0) { 13259 EVENTHANDLER_DEREGISTER(vxlan_start, 13260 vxlan_start_evtag); 13261 EVENTHANDLER_DEREGISTER(vxlan_stop, 13262 vxlan_stop_evtag); 13263 t4_tracer_modunload(); 13264 #ifdef KERN_TLS 13265 t6_ktls_modunload(); 13266 #endif 13267 #ifdef INET6 13268 t4_clip_modunload(); 13269 #endif 13270 #ifdef TCP_OFFLOAD 13271 sx_destroy(&t4_uld_list_lock); 13272 #endif 13273 sx_destroy(&t4_list_lock); 13274 t4_sge_modunload(); 13275 loaded = 0; 13276 } else { 13277 rc = EBUSY; 13278 loaded++; /* undo earlier decrement */ 13279 } 13280 } 13281 done_unload: 13282 sx_xunlock(&mlu); 13283 break; 13284 } 13285 13286 return (rc); 13287 } 13288 13289 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0); 13290 MODULE_VERSION(t4nex, 1); 13291 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 13292 #ifdef DEV_NETMAP 13293 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 13294 #endif /* DEV_NETMAP */ 13295 13296 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0); 13297 MODULE_VERSION(t5nex, 1); 13298 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 13299 #ifdef DEV_NETMAP 13300 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 13301 #endif /* DEV_NETMAP */ 13302 13303 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0); 13304 MODULE_VERSION(t6nex, 1); 13305 MODULE_DEPEND(t6nex, crypto, 1, 1, 1); 13306 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 13307 #ifdef DEV_NETMAP 13308 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 13309 #endif /* DEV_NETMAP */ 13310 13311 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0); 13312 MODULE_VERSION(cxgbe, 1); 13313 13314 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0); 13315 MODULE_VERSION(cxl, 1); 13316 13317 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0); 13318 MODULE_VERSION(cc, 1); 13319 13320 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0); 13321 MODULE_VERSION(vcxgbe, 1); 13322 13323 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0); 13324 MODULE_VERSION(vcxl, 1); 13325 13326 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0); 13327 MODULE_VERSION(vcc, 1); 13328