1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_kern_tls.h" 37 #include "opt_ratelimit.h" 38 #include "opt_rss.h" 39 40 #include <sys/param.h> 41 #include <sys/conf.h> 42 #include <sys/priv.h> 43 #include <sys/kernel.h> 44 #include <sys/bus.h> 45 #include <sys/eventhandler.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/queue.h> 49 #include <sys/taskqueue.h> 50 #include <sys/pciio.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pci_private.h> 54 #include <sys/firmware.h> 55 #include <sys/sbuf.h> 56 #include <sys/smp.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/sysctl.h> 60 #include <net/ethernet.h> 61 #include <net/if.h> 62 #include <net/if_types.h> 63 #include <net/if_dl.h> 64 #include <net/if_vlan_var.h> 65 #ifdef RSS 66 #include <net/rss_config.h> 67 #endif 68 #include <netinet/in.h> 69 #include <netinet/ip.h> 70 #ifdef KERN_TLS 71 #include <netinet/tcp_seq.h> 72 #endif 73 #if defined(__i386__) || defined(__amd64__) 74 #include <machine/md_var.h> 75 #include <machine/cputypes.h> 76 #include <vm/vm.h> 77 #include <vm/pmap.h> 78 #endif 79 #ifdef DDB 80 #include <ddb/ddb.h> 81 #include <ddb/db_lex.h> 82 #endif 83 84 #include "common/common.h" 85 #include "common/t4_msg.h" 86 #include "common/t4_regs.h" 87 #include "common/t4_regs_values.h" 88 #include "cudbg/cudbg.h" 89 #include "t4_clip.h" 90 #include "t4_ioctl.h" 91 #include "t4_l2t.h" 92 #include "t4_mp_ring.h" 93 #include "t4_if.h" 94 #include "t4_smt.h" 95 96 /* T4 bus driver interface */ 97 static int t4_probe(device_t); 98 static int t4_attach(device_t); 99 static int t4_detach(device_t); 100 static int t4_child_location_str(device_t, device_t, char *, size_t); 101 static int t4_ready(device_t); 102 static int t4_read_port_device(device_t, int, device_t *); 103 static device_method_t t4_methods[] = { 104 DEVMETHOD(device_probe, t4_probe), 105 DEVMETHOD(device_attach, t4_attach), 106 DEVMETHOD(device_detach, t4_detach), 107 108 DEVMETHOD(bus_child_location_str, t4_child_location_str), 109 110 DEVMETHOD(t4_is_main_ready, t4_ready), 111 DEVMETHOD(t4_read_port_device, t4_read_port_device), 112 113 DEVMETHOD_END 114 }; 115 static driver_t t4_driver = { 116 "t4nex", 117 t4_methods, 118 sizeof(struct adapter) 119 }; 120 121 122 /* T4 port (cxgbe) interface */ 123 static int cxgbe_probe(device_t); 124 static int cxgbe_attach(device_t); 125 static int cxgbe_detach(device_t); 126 device_method_t cxgbe_methods[] = { 127 DEVMETHOD(device_probe, cxgbe_probe), 128 DEVMETHOD(device_attach, cxgbe_attach), 129 DEVMETHOD(device_detach, cxgbe_detach), 130 { 0, 0 } 131 }; 132 static driver_t cxgbe_driver = { 133 "cxgbe", 134 cxgbe_methods, 135 sizeof(struct port_info) 136 }; 137 138 /* T4 VI (vcxgbe) interface */ 139 static int vcxgbe_probe(device_t); 140 static int vcxgbe_attach(device_t); 141 static int vcxgbe_detach(device_t); 142 static device_method_t vcxgbe_methods[] = { 143 DEVMETHOD(device_probe, vcxgbe_probe), 144 DEVMETHOD(device_attach, vcxgbe_attach), 145 DEVMETHOD(device_detach, vcxgbe_detach), 146 { 0, 0 } 147 }; 148 static driver_t vcxgbe_driver = { 149 "vcxgbe", 150 vcxgbe_methods, 151 sizeof(struct vi_info) 152 }; 153 154 static d_ioctl_t t4_ioctl; 155 156 static struct cdevsw t4_cdevsw = { 157 .d_version = D_VERSION, 158 .d_ioctl = t4_ioctl, 159 .d_name = "t4nex", 160 }; 161 162 /* T5 bus driver interface */ 163 static int t5_probe(device_t); 164 static device_method_t t5_methods[] = { 165 DEVMETHOD(device_probe, t5_probe), 166 DEVMETHOD(device_attach, t4_attach), 167 DEVMETHOD(device_detach, t4_detach), 168 169 DEVMETHOD(bus_child_location_str, t4_child_location_str), 170 171 DEVMETHOD(t4_is_main_ready, t4_ready), 172 DEVMETHOD(t4_read_port_device, t4_read_port_device), 173 174 DEVMETHOD_END 175 }; 176 static driver_t t5_driver = { 177 "t5nex", 178 t5_methods, 179 sizeof(struct adapter) 180 }; 181 182 183 /* T5 port (cxl) interface */ 184 static driver_t cxl_driver = { 185 "cxl", 186 cxgbe_methods, 187 sizeof(struct port_info) 188 }; 189 190 /* T5 VI (vcxl) interface */ 191 static driver_t vcxl_driver = { 192 "vcxl", 193 vcxgbe_methods, 194 sizeof(struct vi_info) 195 }; 196 197 /* T6 bus driver interface */ 198 static int t6_probe(device_t); 199 static device_method_t t6_methods[] = { 200 DEVMETHOD(device_probe, t6_probe), 201 DEVMETHOD(device_attach, t4_attach), 202 DEVMETHOD(device_detach, t4_detach), 203 204 DEVMETHOD(bus_child_location_str, t4_child_location_str), 205 206 DEVMETHOD(t4_is_main_ready, t4_ready), 207 DEVMETHOD(t4_read_port_device, t4_read_port_device), 208 209 DEVMETHOD_END 210 }; 211 static driver_t t6_driver = { 212 "t6nex", 213 t6_methods, 214 sizeof(struct adapter) 215 }; 216 217 218 /* T6 port (cc) interface */ 219 static driver_t cc_driver = { 220 "cc", 221 cxgbe_methods, 222 sizeof(struct port_info) 223 }; 224 225 /* T6 VI (vcc) interface */ 226 static driver_t vcc_driver = { 227 "vcc", 228 vcxgbe_methods, 229 sizeof(struct vi_info) 230 }; 231 232 /* ifnet interface */ 233 static void cxgbe_init(void *); 234 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 235 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 236 static void cxgbe_qflush(struct ifnet *); 237 #if defined(KERN_TLS) || defined(RATELIMIT) 238 static int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 239 struct m_snd_tag **); 240 static int cxgbe_snd_tag_modify(struct m_snd_tag *, 241 union if_snd_tag_modify_params *); 242 static int cxgbe_snd_tag_query(struct m_snd_tag *, 243 union if_snd_tag_query_params *); 244 static void cxgbe_snd_tag_free(struct m_snd_tag *); 245 #endif 246 247 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 248 249 /* 250 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 251 * then ADAPTER_LOCK, then t4_uld_list_lock. 252 */ 253 static struct sx t4_list_lock; 254 SLIST_HEAD(, adapter) t4_list; 255 #ifdef TCP_OFFLOAD 256 static struct sx t4_uld_list_lock; 257 SLIST_HEAD(, uld_info) t4_uld_list; 258 #endif 259 260 /* 261 * Tunables. See tweak_tunables() too. 262 * 263 * Each tunable is set to a default value here if it's known at compile-time. 264 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 265 * provide a reasonable default (upto n) when the driver is loaded. 266 * 267 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 268 * T5 are under hw.cxl. 269 */ 270 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 271 "cxgbe(4) parameters"); 272 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 273 "cxgbe(4) T5+ parameters"); 274 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 275 "cxgbe(4) TOE parameters"); 276 277 /* 278 * Number of queues for tx and rx, NIC and offload. 279 */ 280 #define NTXQ 16 281 int t4_ntxq = -NTXQ; 282 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 283 "Number of TX queues per port"); 284 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 285 286 #define NRXQ 8 287 int t4_nrxq = -NRXQ; 288 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 289 "Number of RX queues per port"); 290 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 291 292 #define NTXQ_VI 1 293 static int t4_ntxq_vi = -NTXQ_VI; 294 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 295 "Number of TX queues per VI"); 296 297 #define NRXQ_VI 1 298 static int t4_nrxq_vi = -NRXQ_VI; 299 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 300 "Number of RX queues per VI"); 301 302 static int t4_rsrv_noflowq = 0; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 304 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 305 306 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 307 #define NOFLDTXQ 8 308 static int t4_nofldtxq = -NOFLDTXQ; 309 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 310 "Number of offload TX queues per port"); 311 312 #define NOFLDRXQ 2 313 static int t4_nofldrxq = -NOFLDRXQ; 314 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 315 "Number of offload RX queues per port"); 316 317 #define NOFLDTXQ_VI 1 318 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 319 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 320 "Number of offload TX queues per VI"); 321 322 #define NOFLDRXQ_VI 1 323 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 324 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 325 "Number of offload RX queues per VI"); 326 327 #define TMR_IDX_OFLD 1 328 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 329 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 330 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 331 332 #define PKTC_IDX_OFLD (-1) 333 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 334 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 335 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 336 337 /* 0 means chip/fw default, non-zero number is value in microseconds */ 338 static u_long t4_toe_keepalive_idle = 0; 339 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 340 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 341 342 /* 0 means chip/fw default, non-zero number is value in microseconds */ 343 static u_long t4_toe_keepalive_interval = 0; 344 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 345 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 346 347 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 348 static int t4_toe_keepalive_count = 0; 349 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 350 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 351 352 /* 0 means chip/fw default, non-zero number is value in microseconds */ 353 static u_long t4_toe_rexmt_min = 0; 354 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 355 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 356 357 /* 0 means chip/fw default, non-zero number is value in microseconds */ 358 static u_long t4_toe_rexmt_max = 0; 359 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 360 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 361 362 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 363 static int t4_toe_rexmt_count = 0; 364 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 365 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 366 367 /* -1 means chip/fw default, other values are raw backoff values to use */ 368 static int t4_toe_rexmt_backoff[16] = { 369 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 370 }; 371 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, 372 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 373 "cxgbe(4) TOE retransmit backoff values"); 374 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 375 &t4_toe_rexmt_backoff[0], 0, ""); 376 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 377 &t4_toe_rexmt_backoff[1], 0, ""); 378 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 379 &t4_toe_rexmt_backoff[2], 0, ""); 380 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 381 &t4_toe_rexmt_backoff[3], 0, ""); 382 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 383 &t4_toe_rexmt_backoff[4], 0, ""); 384 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 385 &t4_toe_rexmt_backoff[5], 0, ""); 386 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 387 &t4_toe_rexmt_backoff[6], 0, ""); 388 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 389 &t4_toe_rexmt_backoff[7], 0, ""); 390 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 391 &t4_toe_rexmt_backoff[8], 0, ""); 392 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 393 &t4_toe_rexmt_backoff[9], 0, ""); 394 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 395 &t4_toe_rexmt_backoff[10], 0, ""); 396 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 397 &t4_toe_rexmt_backoff[11], 0, ""); 398 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 399 &t4_toe_rexmt_backoff[12], 0, ""); 400 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 401 &t4_toe_rexmt_backoff[13], 0, ""); 402 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 403 &t4_toe_rexmt_backoff[14], 0, ""); 404 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 405 &t4_toe_rexmt_backoff[15], 0, ""); 406 #endif 407 408 #ifdef DEV_NETMAP 409 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */ 410 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */ 411 static int t4_native_netmap = NN_EXTRA_VI; 412 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap, 413 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs"); 414 415 #define NNMTXQ 8 416 static int t4_nnmtxq = -NNMTXQ; 417 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0, 418 "Number of netmap TX queues"); 419 420 #define NNMRXQ 8 421 static int t4_nnmrxq = -NNMRXQ; 422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0, 423 "Number of netmap RX queues"); 424 425 #define NNMTXQ_VI 2 426 static int t4_nnmtxq_vi = -NNMTXQ_VI; 427 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 428 "Number of netmap TX queues per VI"); 429 430 #define NNMRXQ_VI 2 431 static int t4_nnmrxq_vi = -NNMRXQ_VI; 432 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 433 "Number of netmap RX queues per VI"); 434 #endif 435 436 /* 437 * Holdoff parameters for ports. 438 */ 439 #define TMR_IDX 1 440 int t4_tmr_idx = TMR_IDX; 441 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 442 0, "Holdoff timer index"); 443 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 444 445 #define PKTC_IDX (-1) 446 int t4_pktc_idx = PKTC_IDX; 447 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 448 0, "Holdoff packet counter index"); 449 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 450 451 /* 452 * Size (# of entries) of each tx and rx queue. 453 */ 454 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 455 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 456 "Number of descriptors in each TX queue"); 457 458 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 459 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 460 "Number of descriptors in each RX queue"); 461 462 /* 463 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 464 */ 465 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 466 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 467 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 468 469 /* 470 * Configuration file. All the _CF names here are special. 471 */ 472 #define DEFAULT_CF "default" 473 #define BUILTIN_CF "built-in" 474 #define FLASH_CF "flash" 475 #define UWIRE_CF "uwire" 476 #define FPGA_CF "fpga" 477 static char t4_cfg_file[32] = DEFAULT_CF; 478 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 479 sizeof(t4_cfg_file), "Firmware configuration file"); 480 481 /* 482 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 483 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 484 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 485 * mark or when signalled to do so, 0 to never emit PAUSE. 486 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 487 * negotiated settings will override rx_pause/tx_pause. 488 * Otherwise rx_pause/tx_pause are applied forcibly. 489 */ 490 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 491 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 492 &t4_pause_settings, 0, 493 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 494 495 /* 496 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 497 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 498 * 0 to disable FEC. 499 */ 500 static int t4_fec = -1; 501 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 502 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 503 504 /* 505 * Link autonegotiation. 506 * -1 to run with the firmware default. 507 * 0 to disable. 508 * 1 to enable. 509 */ 510 static int t4_autoneg = -1; 511 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 512 "Link autonegotiation"); 513 514 /* 515 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 516 * encouraged respectively). '-n' is the same as 'n' except the firmware 517 * version used in the checks is read from the firmware bundled with the driver. 518 */ 519 static int t4_fw_install = 1; 520 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 521 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 522 523 /* 524 * ASIC features that will be used. Disable the ones you don't want so that the 525 * chip resources aren't wasted on features that will not be used. 526 */ 527 static int t4_nbmcaps_allowed = 0; 528 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 529 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 530 531 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 532 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 533 &t4_linkcaps_allowed, 0, "Default link capabilities"); 534 535 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 536 FW_CAPS_CONFIG_SWITCH_EGRESS; 537 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 538 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 539 540 #ifdef RATELIMIT 541 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 542 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 543 #else 544 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 545 FW_CAPS_CONFIG_NIC_HASHFILTER; 546 #endif 547 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 548 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 549 550 static int t4_toecaps_allowed = -1; 551 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 552 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 553 554 static int t4_rdmacaps_allowed = -1; 555 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 556 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 557 558 static int t4_cryptocaps_allowed = -1; 559 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 560 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 561 562 static int t4_iscsicaps_allowed = -1; 563 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 564 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 565 566 static int t4_fcoecaps_allowed = 0; 567 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 568 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 569 570 static int t5_write_combine = 0; 571 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 572 0, "Use WC instead of UC for BAR2"); 573 574 static int t4_num_vis = 1; 575 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 576 "Number of VIs per port"); 577 578 /* 579 * PCIe Relaxed Ordering. 580 * -1: driver should figure out a good value. 581 * 0: disable RO. 582 * 1: enable RO. 583 * 2: leave RO alone. 584 */ 585 static int pcie_relaxed_ordering = -1; 586 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 587 &pcie_relaxed_ordering, 0, 588 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 589 590 static int t4_panic_on_fatal_err = 0; 591 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN, 592 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 593 594 #ifdef TCP_OFFLOAD 595 /* 596 * TOE tunables. 597 */ 598 static int t4_cop_managed_offloading = 0; 599 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 600 &t4_cop_managed_offloading, 0, 601 "COP (Connection Offload Policy) controls all TOE offload"); 602 #endif 603 604 #ifdef KERN_TLS 605 /* 606 * This enables KERN_TLS for all adapters if set. 607 */ 608 static int t4_kern_tls = 0; 609 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0, 610 "Enable KERN_TLS mode for all supported adapters"); 611 612 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 613 "cxgbe(4) KERN_TLS parameters"); 614 615 static int t4_tls_inline_keys = 0; 616 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN, 617 &t4_tls_inline_keys, 0, 618 "Always pass TLS keys in work requests (1) or attempt to store TLS keys " 619 "in card memory."); 620 621 static int t4_tls_combo_wrs = 0; 622 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs, 623 0, "Attempt to combine TCB field updates with TLS record work requests."); 624 #endif 625 626 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 627 static int vi_mac_funcs[] = { 628 FW_VI_FUNC_ETH, 629 FW_VI_FUNC_OFLD, 630 FW_VI_FUNC_IWARP, 631 FW_VI_FUNC_OPENISCSI, 632 FW_VI_FUNC_OPENFCOE, 633 FW_VI_FUNC_FOISCSI, 634 FW_VI_FUNC_FOFCOE, 635 }; 636 637 struct intrs_and_queues { 638 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 639 uint16_t num_vis; /* number of VIs for each port */ 640 uint16_t nirq; /* Total # of vectors */ 641 uint16_t ntxq; /* # of NIC txq's for each port */ 642 uint16_t nrxq; /* # of NIC rxq's for each port */ 643 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 644 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 645 uint16_t nnmtxq; /* # of netmap txq's */ 646 uint16_t nnmrxq; /* # of netmap rxq's */ 647 648 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 649 uint16_t ntxq_vi; /* # of NIC txq's */ 650 uint16_t nrxq_vi; /* # of NIC rxq's */ 651 uint16_t nofldtxq_vi; /* # of TOE txq's */ 652 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 653 uint16_t nnmtxq_vi; /* # of netmap txq's */ 654 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 655 }; 656 657 static void setup_memwin(struct adapter *); 658 static void position_memwin(struct adapter *, int, uint32_t); 659 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 660 static int fwmtype_to_hwmtype(int); 661 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 662 uint32_t *); 663 static int fixup_devlog_params(struct adapter *); 664 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 665 static int contact_firmware(struct adapter *); 666 static int partition_resources(struct adapter *); 667 static int get_params__pre_init(struct adapter *); 668 static int set_params__pre_init(struct adapter *); 669 static int get_params__post_init(struct adapter *); 670 static int set_params__post_init(struct adapter *); 671 static void t4_set_desc(struct adapter *); 672 static bool fixed_ifmedia(struct port_info *); 673 static void build_medialist(struct port_info *); 674 static void init_link_config(struct port_info *); 675 static int fixup_link_config(struct port_info *); 676 static int apply_link_config(struct port_info *); 677 static int cxgbe_init_synchronized(struct vi_info *); 678 static int cxgbe_uninit_synchronized(struct vi_info *); 679 static void quiesce_txq(struct adapter *, struct sge_txq *); 680 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 681 static void quiesce_iq(struct adapter *, struct sge_iq *); 682 static void quiesce_fl(struct adapter *, struct sge_fl *); 683 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 684 driver_intr_t *, void *, char *); 685 static int t4_free_irq(struct adapter *, struct irq *); 686 static void t4_init_atid_table(struct adapter *); 687 static void t4_free_atid_table(struct adapter *); 688 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 689 static void vi_refresh_stats(struct adapter *, struct vi_info *); 690 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 691 static void cxgbe_tick(void *); 692 static void cxgbe_sysctls(struct port_info *); 693 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 694 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 695 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 696 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 697 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 698 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 699 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 700 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 701 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 702 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 703 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 704 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS); 705 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 706 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 707 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 708 static int sysctl_vdd(SYSCTL_HANDLER_ARGS); 709 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS); 710 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 711 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 712 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 713 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 714 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 715 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 716 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 717 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 718 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 719 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 720 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 721 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 722 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 723 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 724 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 725 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 726 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 727 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 728 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 729 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 730 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 731 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 732 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 733 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 734 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 735 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 736 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 737 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 738 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 739 #ifdef TCP_OFFLOAD 740 static int sysctl_tls(SYSCTL_HANDLER_ARGS); 741 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 742 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 743 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 744 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 745 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 746 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 747 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 748 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 749 #endif 750 static int get_sge_context(struct adapter *, struct t4_sge_context *); 751 static int load_fw(struct adapter *, struct t4_data *); 752 static int load_cfg(struct adapter *, struct t4_data *); 753 static int load_boot(struct adapter *, struct t4_bootrom *); 754 static int load_bootcfg(struct adapter *, struct t4_data *); 755 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 756 static void free_offload_policy(struct t4_offload_policy *); 757 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 758 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 759 static int read_i2c(struct adapter *, struct t4_i2c_data *); 760 static int clear_stats(struct adapter *, u_int); 761 #ifdef TCP_OFFLOAD 762 static int toe_capability(struct vi_info *, int); 763 static void t4_async_event(void *, int); 764 #endif 765 static int mod_event(module_t, int, void *); 766 static int notify_siblings(device_t, int); 767 768 struct { 769 uint16_t device; 770 char *desc; 771 } t4_pciids[] = { 772 {0xa000, "Chelsio Terminator 4 FPGA"}, 773 {0x4400, "Chelsio T440-dbg"}, 774 {0x4401, "Chelsio T420-CR"}, 775 {0x4402, "Chelsio T422-CR"}, 776 {0x4403, "Chelsio T440-CR"}, 777 {0x4404, "Chelsio T420-BCH"}, 778 {0x4405, "Chelsio T440-BCH"}, 779 {0x4406, "Chelsio T440-CH"}, 780 {0x4407, "Chelsio T420-SO"}, 781 {0x4408, "Chelsio T420-CX"}, 782 {0x4409, "Chelsio T420-BT"}, 783 {0x440a, "Chelsio T404-BT"}, 784 {0x440e, "Chelsio T440-LP-CR"}, 785 }, t5_pciids[] = { 786 {0xb000, "Chelsio Terminator 5 FPGA"}, 787 {0x5400, "Chelsio T580-dbg"}, 788 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 789 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 790 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 791 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 792 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 793 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 794 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 795 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 796 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 797 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 798 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 799 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 800 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 801 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 802 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 803 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 804 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 805 806 /* Custom */ 807 {0x5483, "Custom T540-CR"}, 808 {0x5484, "Custom T540-BT"}, 809 }, t6_pciids[] = { 810 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 811 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 812 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 813 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 814 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 815 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 816 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 817 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 818 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 819 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 820 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 821 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 822 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 823 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 824 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 825 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 826 827 /* Custom */ 828 {0x6480, "Custom T6225-CR"}, 829 {0x6481, "Custom T62100-CR"}, 830 {0x6482, "Custom T6225-CR"}, 831 {0x6483, "Custom T62100-CR"}, 832 {0x6484, "Custom T64100-CR"}, 833 {0x6485, "Custom T6240-SO"}, 834 {0x6486, "Custom T6225-SO-CR"}, 835 {0x6487, "Custom T6225-CR"}, 836 }; 837 838 #ifdef TCP_OFFLOAD 839 /* 840 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 841 * be exactly the same for both rxq and ofld_rxq. 842 */ 843 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 844 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 845 #endif 846 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 847 848 static int 849 t4_probe(device_t dev) 850 { 851 int i; 852 uint16_t v = pci_get_vendor(dev); 853 uint16_t d = pci_get_device(dev); 854 uint8_t f = pci_get_function(dev); 855 856 if (v != PCI_VENDOR_ID_CHELSIO) 857 return (ENXIO); 858 859 /* Attach only to PF0 of the FPGA */ 860 if (d == 0xa000 && f != 0) 861 return (ENXIO); 862 863 for (i = 0; i < nitems(t4_pciids); i++) { 864 if (d == t4_pciids[i].device) { 865 device_set_desc(dev, t4_pciids[i].desc); 866 return (BUS_PROBE_DEFAULT); 867 } 868 } 869 870 return (ENXIO); 871 } 872 873 static int 874 t5_probe(device_t dev) 875 { 876 int i; 877 uint16_t v = pci_get_vendor(dev); 878 uint16_t d = pci_get_device(dev); 879 uint8_t f = pci_get_function(dev); 880 881 if (v != PCI_VENDOR_ID_CHELSIO) 882 return (ENXIO); 883 884 /* Attach only to PF0 of the FPGA */ 885 if (d == 0xb000 && f != 0) 886 return (ENXIO); 887 888 for (i = 0; i < nitems(t5_pciids); i++) { 889 if (d == t5_pciids[i].device) { 890 device_set_desc(dev, t5_pciids[i].desc); 891 return (BUS_PROBE_DEFAULT); 892 } 893 } 894 895 return (ENXIO); 896 } 897 898 static int 899 t6_probe(device_t dev) 900 { 901 int i; 902 uint16_t v = pci_get_vendor(dev); 903 uint16_t d = pci_get_device(dev); 904 905 if (v != PCI_VENDOR_ID_CHELSIO) 906 return (ENXIO); 907 908 for (i = 0; i < nitems(t6_pciids); i++) { 909 if (d == t6_pciids[i].device) { 910 device_set_desc(dev, t6_pciids[i].desc); 911 return (BUS_PROBE_DEFAULT); 912 } 913 } 914 915 return (ENXIO); 916 } 917 918 static void 919 t5_attribute_workaround(device_t dev) 920 { 921 device_t root_port; 922 uint32_t v; 923 924 /* 925 * The T5 chips do not properly echo the No Snoop and Relaxed 926 * Ordering attributes when replying to a TLP from a Root 927 * Port. As a workaround, find the parent Root Port and 928 * disable No Snoop and Relaxed Ordering. Note that this 929 * affects all devices under this root port. 930 */ 931 root_port = pci_find_pcie_root_port(dev); 932 if (root_port == NULL) { 933 device_printf(dev, "Unable to find parent root port\n"); 934 return; 935 } 936 937 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 938 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 939 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 940 0) 941 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 942 device_get_nameunit(root_port)); 943 } 944 945 static const struct devnames devnames[] = { 946 { 947 .nexus_name = "t4nex", 948 .ifnet_name = "cxgbe", 949 .vi_ifnet_name = "vcxgbe", 950 .pf03_drv_name = "t4iov", 951 .vf_nexus_name = "t4vf", 952 .vf_ifnet_name = "cxgbev" 953 }, { 954 .nexus_name = "t5nex", 955 .ifnet_name = "cxl", 956 .vi_ifnet_name = "vcxl", 957 .pf03_drv_name = "t5iov", 958 .vf_nexus_name = "t5vf", 959 .vf_ifnet_name = "cxlv" 960 }, { 961 .nexus_name = "t6nex", 962 .ifnet_name = "cc", 963 .vi_ifnet_name = "vcc", 964 .pf03_drv_name = "t6iov", 965 .vf_nexus_name = "t6vf", 966 .vf_ifnet_name = "ccv" 967 } 968 }; 969 970 void 971 t4_init_devnames(struct adapter *sc) 972 { 973 int id; 974 975 id = chip_id(sc); 976 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 977 sc->names = &devnames[id - CHELSIO_T4]; 978 else { 979 device_printf(sc->dev, "chip id %d is not supported.\n", id); 980 sc->names = NULL; 981 } 982 } 983 984 static int 985 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 986 { 987 const char *parent, *name; 988 long value; 989 int line, unit; 990 991 line = 0; 992 parent = device_get_nameunit(sc->dev); 993 name = sc->names->ifnet_name; 994 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 995 if (resource_long_value(name, unit, "port", &value) == 0 && 996 value == pi->port_id) 997 return (unit); 998 } 999 return (-1); 1000 } 1001 1002 static int 1003 t4_attach(device_t dev) 1004 { 1005 struct adapter *sc; 1006 int rc = 0, i, j, rqidx, tqidx, nports; 1007 struct make_dev_args mda; 1008 struct intrs_and_queues iaq; 1009 struct sge *s; 1010 uint32_t *buf; 1011 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1012 int ofld_tqidx; 1013 #endif 1014 #ifdef TCP_OFFLOAD 1015 int ofld_rqidx; 1016 #endif 1017 #ifdef DEV_NETMAP 1018 int nm_rqidx, nm_tqidx; 1019 #endif 1020 int num_vis; 1021 1022 sc = device_get_softc(dev); 1023 sc->dev = dev; 1024 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 1025 1026 if ((pci_get_device(dev) & 0xff00) == 0x5400) 1027 t5_attribute_workaround(dev); 1028 pci_enable_busmaster(dev); 1029 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 1030 uint32_t v; 1031 1032 pci_set_max_read_req(dev, 4096); 1033 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 1034 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 1035 if (pcie_relaxed_ordering == 0 && 1036 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 1037 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 1038 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1039 } else if (pcie_relaxed_ordering == 1 && 1040 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 1041 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 1042 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1043 } 1044 } 1045 1046 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 1047 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 1048 sc->traceq = -1; 1049 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 1050 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 1051 device_get_nameunit(dev)); 1052 1053 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 1054 device_get_nameunit(dev)); 1055 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 1056 t4_add_adapter(sc); 1057 1058 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 1059 TAILQ_INIT(&sc->sfl); 1060 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 1061 1062 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 1063 1064 sc->policy = NULL; 1065 rw_init(&sc->policy_lock, "connection offload policy"); 1066 1067 callout_init(&sc->ktls_tick, 1); 1068 1069 #ifdef TCP_OFFLOAD 1070 TASK_INIT(&sc->async_event_task, 0, t4_async_event, sc); 1071 #endif 1072 1073 refcount_init(&sc->vxlan_refcount, 0); 1074 1075 rc = t4_map_bars_0_and_4(sc); 1076 if (rc != 0) 1077 goto done; /* error message displayed already */ 1078 1079 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1080 1081 /* Prepare the adapter for operation. */ 1082 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1083 rc = -t4_prep_adapter(sc, buf); 1084 free(buf, M_CXGBE); 1085 if (rc != 0) { 1086 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1087 goto done; 1088 } 1089 1090 /* 1091 * This is the real PF# to which we're attaching. Works from within PCI 1092 * passthrough environments too, where pci_get_function() could return a 1093 * different PF# depending on the passthrough configuration. We need to 1094 * use the real PF# in all our communication with the firmware. 1095 */ 1096 j = t4_read_reg(sc, A_PL_WHOAMI); 1097 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1098 sc->mbox = sc->pf; 1099 1100 t4_init_devnames(sc); 1101 if (sc->names == NULL) { 1102 rc = ENOTSUP; 1103 goto done; /* error message displayed already */ 1104 } 1105 1106 /* 1107 * Do this really early, with the memory windows set up even before the 1108 * character device. The userland tool's register i/o and mem read 1109 * will work even in "recovery mode". 1110 */ 1111 setup_memwin(sc); 1112 if (t4_init_devlog_params(sc, 0) == 0) 1113 fixup_devlog_params(sc); 1114 make_dev_args_init(&mda); 1115 mda.mda_devsw = &t4_cdevsw; 1116 mda.mda_uid = UID_ROOT; 1117 mda.mda_gid = GID_WHEEL; 1118 mda.mda_mode = 0600; 1119 mda.mda_si_drv1 = sc; 1120 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1121 if (rc != 0) 1122 device_printf(dev, "failed to create nexus char device: %d.\n", 1123 rc); 1124 1125 /* Go no further if recovery mode has been requested. */ 1126 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1127 device_printf(dev, "recovery mode.\n"); 1128 goto done; 1129 } 1130 1131 #if defined(__i386__) 1132 if ((cpu_feature & CPUID_CX8) == 0) { 1133 device_printf(dev, "64 bit atomics not available.\n"); 1134 rc = ENOTSUP; 1135 goto done; 1136 } 1137 #endif 1138 1139 /* Contact the firmware and try to become the master driver. */ 1140 rc = contact_firmware(sc); 1141 if (rc != 0) 1142 goto done; /* error message displayed already */ 1143 MPASS(sc->flags & FW_OK); 1144 1145 rc = get_params__pre_init(sc); 1146 if (rc != 0) 1147 goto done; /* error message displayed already */ 1148 1149 if (sc->flags & MASTER_PF) { 1150 rc = partition_resources(sc); 1151 if (rc != 0) 1152 goto done; /* error message displayed already */ 1153 t4_intr_clear(sc); 1154 } 1155 1156 rc = get_params__post_init(sc); 1157 if (rc != 0) 1158 goto done; /* error message displayed already */ 1159 1160 rc = set_params__post_init(sc); 1161 if (rc != 0) 1162 goto done; /* error message displayed already */ 1163 1164 rc = t4_map_bar_2(sc); 1165 if (rc != 0) 1166 goto done; /* error message displayed already */ 1167 1168 rc = t4_create_dma_tag(sc); 1169 if (rc != 0) 1170 goto done; /* error message displayed already */ 1171 1172 /* 1173 * First pass over all the ports - allocate VIs and initialize some 1174 * basic parameters like mac address, port type, etc. 1175 */ 1176 for_each_port(sc, i) { 1177 struct port_info *pi; 1178 1179 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1180 sc->port[i] = pi; 1181 1182 /* These must be set before t4_port_init */ 1183 pi->adapter = sc; 1184 pi->port_id = i; 1185 /* 1186 * XXX: vi[0] is special so we can't delay this allocation until 1187 * pi->nvi's final value is known. 1188 */ 1189 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1190 M_ZERO | M_WAITOK); 1191 1192 /* 1193 * Allocate the "main" VI and initialize parameters 1194 * like mac addr. 1195 */ 1196 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1197 if (rc != 0) { 1198 device_printf(dev, "unable to initialize port %d: %d\n", 1199 i, rc); 1200 free(pi->vi, M_CXGBE); 1201 free(pi, M_CXGBE); 1202 sc->port[i] = NULL; 1203 goto done; 1204 } 1205 1206 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1207 device_get_nameunit(dev), i); 1208 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1209 sc->chan_map[pi->tx_chan] = i; 1210 1211 /* All VIs on this port share this media. */ 1212 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1213 cxgbe_media_status); 1214 1215 PORT_LOCK(pi); 1216 init_link_config(pi); 1217 fixup_link_config(pi); 1218 build_medialist(pi); 1219 if (fixed_ifmedia(pi)) 1220 pi->flags |= FIXED_IFMEDIA; 1221 PORT_UNLOCK(pi); 1222 1223 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1224 t4_ifnet_unit(sc, pi)); 1225 if (pi->dev == NULL) { 1226 device_printf(dev, 1227 "failed to add device for port %d.\n", i); 1228 rc = ENXIO; 1229 goto done; 1230 } 1231 pi->vi[0].dev = pi->dev; 1232 device_set_softc(pi->dev, pi); 1233 } 1234 1235 /* 1236 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1237 */ 1238 nports = sc->params.nports; 1239 rc = cfg_itype_and_nqueues(sc, &iaq); 1240 if (rc != 0) 1241 goto done; /* error message displayed already */ 1242 1243 num_vis = iaq.num_vis; 1244 sc->intr_type = iaq.intr_type; 1245 sc->intr_count = iaq.nirq; 1246 1247 s = &sc->sge; 1248 s->nrxq = nports * iaq.nrxq; 1249 s->ntxq = nports * iaq.ntxq; 1250 if (num_vis > 1) { 1251 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1252 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1253 } 1254 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1255 s->neq += nports; /* ctrl queues: 1 per port */ 1256 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1257 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1258 if (is_offload(sc) || is_ethoffload(sc)) { 1259 s->nofldtxq = nports * iaq.nofldtxq; 1260 if (num_vis > 1) 1261 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1262 s->neq += s->nofldtxq; 1263 1264 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1265 M_CXGBE, M_ZERO | M_WAITOK); 1266 } 1267 #endif 1268 #ifdef TCP_OFFLOAD 1269 if (is_offload(sc)) { 1270 s->nofldrxq = nports * iaq.nofldrxq; 1271 if (num_vis > 1) 1272 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1273 s->neq += s->nofldrxq; /* free list */ 1274 s->niq += s->nofldrxq; 1275 1276 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1277 M_CXGBE, M_ZERO | M_WAITOK); 1278 } 1279 #endif 1280 #ifdef DEV_NETMAP 1281 s->nnmrxq = 0; 1282 s->nnmtxq = 0; 1283 if (t4_native_netmap & NN_MAIN_VI) { 1284 s->nnmrxq += nports * iaq.nnmrxq; 1285 s->nnmtxq += nports * iaq.nnmtxq; 1286 } 1287 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) { 1288 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi; 1289 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi; 1290 } 1291 s->neq += s->nnmtxq + s->nnmrxq; 1292 s->niq += s->nnmrxq; 1293 1294 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1295 M_CXGBE, M_ZERO | M_WAITOK); 1296 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1297 M_CXGBE, M_ZERO | M_WAITOK); 1298 #endif 1299 1300 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1301 M_ZERO | M_WAITOK); 1302 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1303 M_ZERO | M_WAITOK); 1304 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1305 M_ZERO | M_WAITOK); 1306 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1307 M_ZERO | M_WAITOK); 1308 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1309 M_ZERO | M_WAITOK); 1310 1311 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1312 M_ZERO | M_WAITOK); 1313 1314 t4_init_l2t(sc, M_WAITOK); 1315 t4_init_smt(sc, M_WAITOK); 1316 t4_init_tx_sched(sc); 1317 t4_init_atid_table(sc); 1318 #ifdef RATELIMIT 1319 t4_init_etid_table(sc); 1320 #endif 1321 #ifdef INET6 1322 t4_init_clip_table(sc); 1323 #endif 1324 if (sc->vres.key.size != 0) 1325 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1326 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1327 1328 /* 1329 * Second pass over the ports. This time we know the number of rx and 1330 * tx queues that each port should get. 1331 */ 1332 rqidx = tqidx = 0; 1333 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1334 ofld_tqidx = 0; 1335 #endif 1336 #ifdef TCP_OFFLOAD 1337 ofld_rqidx = 0; 1338 #endif 1339 #ifdef DEV_NETMAP 1340 nm_rqidx = nm_tqidx = 0; 1341 #endif 1342 for_each_port(sc, i) { 1343 struct port_info *pi = sc->port[i]; 1344 struct vi_info *vi; 1345 1346 if (pi == NULL) 1347 continue; 1348 1349 pi->nvi = num_vis; 1350 for_each_vi(pi, j, vi) { 1351 vi->pi = pi; 1352 vi->adapter = sc; 1353 vi->qsize_rxq = t4_qsize_rxq; 1354 vi->qsize_txq = t4_qsize_txq; 1355 1356 vi->first_rxq = rqidx; 1357 vi->first_txq = tqidx; 1358 vi->tmr_idx = t4_tmr_idx; 1359 vi->pktc_idx = t4_pktc_idx; 1360 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1361 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1362 1363 rqidx += vi->nrxq; 1364 tqidx += vi->ntxq; 1365 1366 if (j == 0 && vi->ntxq > 1) 1367 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1368 else 1369 vi->rsrv_noflowq = 0; 1370 1371 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1372 vi->first_ofld_txq = ofld_tqidx; 1373 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1374 ofld_tqidx += vi->nofldtxq; 1375 #endif 1376 #ifdef TCP_OFFLOAD 1377 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1378 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1379 vi->first_ofld_rxq = ofld_rqidx; 1380 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1381 1382 ofld_rqidx += vi->nofldrxq; 1383 #endif 1384 #ifdef DEV_NETMAP 1385 vi->first_nm_rxq = nm_rqidx; 1386 vi->first_nm_txq = nm_tqidx; 1387 if (j == 0) { 1388 vi->nnmrxq = iaq.nnmrxq; 1389 vi->nnmtxq = iaq.nnmtxq; 1390 } else { 1391 vi->nnmrxq = iaq.nnmrxq_vi; 1392 vi->nnmtxq = iaq.nnmtxq_vi; 1393 } 1394 nm_rqidx += vi->nnmrxq; 1395 nm_tqidx += vi->nnmtxq; 1396 #endif 1397 } 1398 } 1399 1400 rc = t4_setup_intr_handlers(sc); 1401 if (rc != 0) { 1402 device_printf(dev, 1403 "failed to setup interrupt handlers: %d\n", rc); 1404 goto done; 1405 } 1406 1407 rc = bus_generic_probe(dev); 1408 if (rc != 0) { 1409 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1410 goto done; 1411 } 1412 1413 /* 1414 * Ensure thread-safe mailbox access (in debug builds). 1415 * 1416 * So far this was the only thread accessing the mailbox but various 1417 * ifnets and sysctls are about to be created and their handlers/ioctls 1418 * will access the mailbox from different threads. 1419 */ 1420 sc->flags |= CHK_MBOX_ACCESS; 1421 1422 rc = bus_generic_attach(dev); 1423 if (rc != 0) { 1424 device_printf(dev, 1425 "failed to attach all child ports: %d\n", rc); 1426 goto done; 1427 } 1428 1429 device_printf(dev, 1430 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1431 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1432 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1433 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1434 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1435 1436 t4_set_desc(sc); 1437 1438 notify_siblings(dev, 0); 1439 1440 done: 1441 if (rc != 0 && sc->cdev) { 1442 /* cdev was created and so cxgbetool works; recover that way. */ 1443 device_printf(dev, 1444 "error during attach, adapter is now in recovery mode.\n"); 1445 rc = 0; 1446 } 1447 1448 if (rc != 0) 1449 t4_detach_common(dev); 1450 else 1451 t4_sysctls(sc); 1452 1453 return (rc); 1454 } 1455 1456 static int 1457 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen) 1458 { 1459 struct adapter *sc; 1460 struct port_info *pi; 1461 int i; 1462 1463 sc = device_get_softc(bus); 1464 buf[0] = '\0'; 1465 for_each_port(sc, i) { 1466 pi = sc->port[i]; 1467 if (pi != NULL && pi->dev == dev) { 1468 snprintf(buf, buflen, "port=%d", pi->port_id); 1469 break; 1470 } 1471 } 1472 return (0); 1473 } 1474 1475 static int 1476 t4_ready(device_t dev) 1477 { 1478 struct adapter *sc; 1479 1480 sc = device_get_softc(dev); 1481 if (sc->flags & FW_OK) 1482 return (0); 1483 return (ENXIO); 1484 } 1485 1486 static int 1487 t4_read_port_device(device_t dev, int port, device_t *child) 1488 { 1489 struct adapter *sc; 1490 struct port_info *pi; 1491 1492 sc = device_get_softc(dev); 1493 if (port < 0 || port >= MAX_NPORTS) 1494 return (EINVAL); 1495 pi = sc->port[port]; 1496 if (pi == NULL || pi->dev == NULL) 1497 return (ENXIO); 1498 *child = pi->dev; 1499 return (0); 1500 } 1501 1502 static int 1503 notify_siblings(device_t dev, int detaching) 1504 { 1505 device_t sibling; 1506 int error, i; 1507 1508 error = 0; 1509 for (i = 0; i < PCI_FUNCMAX; i++) { 1510 if (i == pci_get_function(dev)) 1511 continue; 1512 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1513 pci_get_slot(dev), i); 1514 if (sibling == NULL || !device_is_attached(sibling)) 1515 continue; 1516 if (detaching) 1517 error = T4_DETACH_CHILD(sibling); 1518 else 1519 (void)T4_ATTACH_CHILD(sibling); 1520 if (error) 1521 break; 1522 } 1523 return (error); 1524 } 1525 1526 /* 1527 * Idempotent 1528 */ 1529 static int 1530 t4_detach(device_t dev) 1531 { 1532 struct adapter *sc; 1533 int rc; 1534 1535 sc = device_get_softc(dev); 1536 1537 rc = notify_siblings(dev, 1); 1538 if (rc) { 1539 device_printf(dev, 1540 "failed to detach sibling devices: %d\n", rc); 1541 return (rc); 1542 } 1543 1544 return (t4_detach_common(dev)); 1545 } 1546 1547 int 1548 t4_detach_common(device_t dev) 1549 { 1550 struct adapter *sc; 1551 struct port_info *pi; 1552 int i, rc; 1553 1554 sc = device_get_softc(dev); 1555 1556 if (sc->cdev) { 1557 destroy_dev(sc->cdev); 1558 sc->cdev = NULL; 1559 } 1560 1561 sx_xlock(&t4_list_lock); 1562 SLIST_REMOVE(&t4_list, sc, adapter, link); 1563 sx_xunlock(&t4_list_lock); 1564 1565 sc->flags &= ~CHK_MBOX_ACCESS; 1566 if (sc->flags & FULL_INIT_DONE) { 1567 if (!(sc->flags & IS_VF)) 1568 t4_intr_disable(sc); 1569 } 1570 1571 if (device_is_attached(dev)) { 1572 rc = bus_generic_detach(dev); 1573 if (rc) { 1574 device_printf(dev, 1575 "failed to detach child devices: %d\n", rc); 1576 return (rc); 1577 } 1578 } 1579 1580 #ifdef TCP_OFFLOAD 1581 taskqueue_drain(taskqueue_thread, &sc->async_event_task); 1582 #endif 1583 1584 for (i = 0; i < sc->intr_count; i++) 1585 t4_free_irq(sc, &sc->irq[i]); 1586 1587 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1588 t4_free_tx_sched(sc); 1589 1590 for (i = 0; i < MAX_NPORTS; i++) { 1591 pi = sc->port[i]; 1592 if (pi) { 1593 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1594 if (pi->dev) 1595 device_delete_child(dev, pi->dev); 1596 1597 mtx_destroy(&pi->pi_lock); 1598 free(pi->vi, M_CXGBE); 1599 free(pi, M_CXGBE); 1600 } 1601 } 1602 1603 device_delete_children(dev); 1604 1605 if (sc->flags & FULL_INIT_DONE) 1606 adapter_full_uninit(sc); 1607 1608 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1609 t4_fw_bye(sc, sc->mbox); 1610 1611 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1612 pci_release_msi(dev); 1613 1614 if (sc->regs_res) 1615 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1616 sc->regs_res); 1617 1618 if (sc->udbs_res) 1619 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1620 sc->udbs_res); 1621 1622 if (sc->msix_res) 1623 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1624 sc->msix_res); 1625 1626 if (sc->l2t) 1627 t4_free_l2t(sc->l2t); 1628 if (sc->smt) 1629 t4_free_smt(sc->smt); 1630 t4_free_atid_table(sc); 1631 #ifdef RATELIMIT 1632 t4_free_etid_table(sc); 1633 #endif 1634 if (sc->key_map) 1635 vmem_destroy(sc->key_map); 1636 #ifdef INET6 1637 t4_destroy_clip_table(sc); 1638 #endif 1639 1640 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1641 free(sc->sge.ofld_txq, M_CXGBE); 1642 #endif 1643 #ifdef TCP_OFFLOAD 1644 free(sc->sge.ofld_rxq, M_CXGBE); 1645 #endif 1646 #ifdef DEV_NETMAP 1647 free(sc->sge.nm_rxq, M_CXGBE); 1648 free(sc->sge.nm_txq, M_CXGBE); 1649 #endif 1650 free(sc->irq, M_CXGBE); 1651 free(sc->sge.rxq, M_CXGBE); 1652 free(sc->sge.txq, M_CXGBE); 1653 free(sc->sge.ctrlq, M_CXGBE); 1654 free(sc->sge.iqmap, M_CXGBE); 1655 free(sc->sge.eqmap, M_CXGBE); 1656 free(sc->tids.ftid_tab, M_CXGBE); 1657 free(sc->tids.hpftid_tab, M_CXGBE); 1658 free_hftid_hash(&sc->tids); 1659 free(sc->tids.tid_tab, M_CXGBE); 1660 free(sc->tt.tls_rx_ports, M_CXGBE); 1661 t4_destroy_dma_tag(sc); 1662 1663 callout_drain(&sc->ktls_tick); 1664 callout_drain(&sc->sfl_callout); 1665 if (mtx_initialized(&sc->tids.ftid_lock)) { 1666 mtx_destroy(&sc->tids.ftid_lock); 1667 cv_destroy(&sc->tids.ftid_cv); 1668 } 1669 if (mtx_initialized(&sc->tids.atid_lock)) 1670 mtx_destroy(&sc->tids.atid_lock); 1671 if (mtx_initialized(&sc->ifp_lock)) 1672 mtx_destroy(&sc->ifp_lock); 1673 1674 if (rw_initialized(&sc->policy_lock)) { 1675 rw_destroy(&sc->policy_lock); 1676 #ifdef TCP_OFFLOAD 1677 if (sc->policy != NULL) 1678 free_offload_policy(sc->policy); 1679 #endif 1680 } 1681 1682 for (i = 0; i < NUM_MEMWIN; i++) { 1683 struct memwin *mw = &sc->memwin[i]; 1684 1685 if (rw_initialized(&mw->mw_lock)) 1686 rw_destroy(&mw->mw_lock); 1687 } 1688 1689 mtx_destroy(&sc->sfl_lock); 1690 mtx_destroy(&sc->reg_lock); 1691 mtx_destroy(&sc->sc_lock); 1692 1693 bzero(sc, sizeof(*sc)); 1694 1695 return (0); 1696 } 1697 1698 static int 1699 cxgbe_probe(device_t dev) 1700 { 1701 char buf[128]; 1702 struct port_info *pi = device_get_softc(dev); 1703 1704 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1705 device_set_desc_copy(dev, buf); 1706 1707 return (BUS_PROBE_DEFAULT); 1708 } 1709 1710 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1711 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1712 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 1713 IFCAP_HWRXTSTMP | IFCAP_NOMAP) 1714 #define T4_CAP_ENABLE (T4_CAP) 1715 1716 static int 1717 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1718 { 1719 struct ifnet *ifp; 1720 struct sbuf *sb; 1721 struct pfil_head_args pa; 1722 struct adapter *sc = vi->adapter; 1723 1724 vi->xact_addr_filt = -1; 1725 callout_init(&vi->tick, 1); 1726 1727 /* Allocate an ifnet and set it up */ 1728 ifp = if_alloc_dev(IFT_ETHER, dev); 1729 if (ifp == NULL) { 1730 device_printf(dev, "Cannot allocate ifnet\n"); 1731 return (ENOMEM); 1732 } 1733 vi->ifp = ifp; 1734 ifp->if_softc = vi; 1735 1736 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1737 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1738 1739 ifp->if_init = cxgbe_init; 1740 ifp->if_ioctl = cxgbe_ioctl; 1741 ifp->if_transmit = cxgbe_transmit; 1742 ifp->if_qflush = cxgbe_qflush; 1743 ifp->if_get_counter = cxgbe_get_counter; 1744 #if defined(KERN_TLS) || defined(RATELIMIT) 1745 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 1746 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify; 1747 ifp->if_snd_tag_query = cxgbe_snd_tag_query; 1748 ifp->if_snd_tag_free = cxgbe_snd_tag_free; 1749 #endif 1750 #ifdef RATELIMIT 1751 ifp->if_ratelimit_query = cxgbe_ratelimit_query; 1752 #endif 1753 1754 ifp->if_capabilities = T4_CAP; 1755 ifp->if_capenable = T4_CAP_ENABLE; 1756 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1757 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1758 if (chip_id(sc) >= CHELSIO_T6) { 1759 ifp->if_capabilities |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 1760 ifp->if_capenable |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 1761 ifp->if_hwassist |= CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 1762 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 1763 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN; 1764 } 1765 1766 #ifdef TCP_OFFLOAD 1767 if (vi->nofldrxq != 0 && (sc->flags & KERN_TLS_OK) == 0) 1768 ifp->if_capabilities |= IFCAP_TOE; 1769 #endif 1770 #ifdef RATELIMIT 1771 if (is_ethoffload(sc) && vi->nofldtxq != 0) { 1772 ifp->if_capabilities |= IFCAP_TXRTLMT; 1773 ifp->if_capenable |= IFCAP_TXRTLMT; 1774 } 1775 #endif 1776 1777 ifp->if_hw_tsomax = IP_MAXPACKET; 1778 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 1779 #ifdef RATELIMIT 1780 if (is_ethoffload(sc) && vi->nofldtxq != 0) 1781 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO; 1782 #endif 1783 ifp->if_hw_tsomaxsegsize = 65536; 1784 #ifdef KERN_TLS 1785 if (sc->flags & KERN_TLS_OK) { 1786 ifp->if_capabilities |= IFCAP_TXTLS; 1787 ifp->if_capenable |= IFCAP_TXTLS; 1788 } 1789 #endif 1790 1791 ether_ifattach(ifp, vi->hw_addr); 1792 #ifdef DEV_NETMAP 1793 if (vi->nnmrxq != 0) 1794 cxgbe_nm_attach(vi); 1795 #endif 1796 sb = sbuf_new_auto(); 1797 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1798 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1799 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 1800 case IFCAP_TOE: 1801 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 1802 break; 1803 case IFCAP_TOE | IFCAP_TXRTLMT: 1804 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 1805 break; 1806 case IFCAP_TXRTLMT: 1807 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 1808 break; 1809 } 1810 #endif 1811 #ifdef TCP_OFFLOAD 1812 if (ifp->if_capabilities & IFCAP_TOE) 1813 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 1814 #endif 1815 #ifdef DEV_NETMAP 1816 if (ifp->if_capabilities & IFCAP_NETMAP) 1817 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1818 vi->nnmtxq, vi->nnmrxq); 1819 #endif 1820 sbuf_finish(sb); 1821 device_printf(dev, "%s\n", sbuf_data(sb)); 1822 sbuf_delete(sb); 1823 1824 vi_sysctls(vi); 1825 1826 pa.pa_version = PFIL_VERSION; 1827 pa.pa_flags = PFIL_IN; 1828 pa.pa_type = PFIL_TYPE_ETHERNET; 1829 pa.pa_headname = ifp->if_xname; 1830 vi->pfil = pfil_head_register(&pa); 1831 1832 return (0); 1833 } 1834 1835 static int 1836 cxgbe_attach(device_t dev) 1837 { 1838 struct port_info *pi = device_get_softc(dev); 1839 struct adapter *sc = pi->adapter; 1840 struct vi_info *vi; 1841 int i, rc; 1842 1843 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1844 1845 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1846 if (rc) 1847 return (rc); 1848 1849 for_each_vi(pi, i, vi) { 1850 if (i == 0) 1851 continue; 1852 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1853 if (vi->dev == NULL) { 1854 device_printf(dev, "failed to add VI %d\n", i); 1855 continue; 1856 } 1857 device_set_softc(vi->dev, vi); 1858 } 1859 1860 cxgbe_sysctls(pi); 1861 1862 bus_generic_attach(dev); 1863 1864 return (0); 1865 } 1866 1867 static void 1868 cxgbe_vi_detach(struct vi_info *vi) 1869 { 1870 struct ifnet *ifp = vi->ifp; 1871 1872 if (vi->pfil != NULL) { 1873 pfil_head_unregister(vi->pfil); 1874 vi->pfil = NULL; 1875 } 1876 1877 ether_ifdetach(ifp); 1878 1879 /* Let detach proceed even if these fail. */ 1880 #ifdef DEV_NETMAP 1881 if (ifp->if_capabilities & IFCAP_NETMAP) 1882 cxgbe_nm_detach(vi); 1883 #endif 1884 cxgbe_uninit_synchronized(vi); 1885 callout_drain(&vi->tick); 1886 vi_full_uninit(vi); 1887 1888 if_free(vi->ifp); 1889 vi->ifp = NULL; 1890 } 1891 1892 static int 1893 cxgbe_detach(device_t dev) 1894 { 1895 struct port_info *pi = device_get_softc(dev); 1896 struct adapter *sc = pi->adapter; 1897 int rc; 1898 1899 /* Detach the extra VIs first. */ 1900 rc = bus_generic_detach(dev); 1901 if (rc) 1902 return (rc); 1903 device_delete_children(dev); 1904 1905 doom_vi(sc, &pi->vi[0]); 1906 1907 if (pi->flags & HAS_TRACEQ) { 1908 sc->traceq = -1; /* cloner should not create ifnet */ 1909 t4_tracer_port_detach(sc); 1910 } 1911 1912 cxgbe_vi_detach(&pi->vi[0]); 1913 callout_drain(&pi->tick); 1914 ifmedia_removeall(&pi->media); 1915 1916 end_synchronized_op(sc, 0); 1917 1918 return (0); 1919 } 1920 1921 static void 1922 cxgbe_init(void *arg) 1923 { 1924 struct vi_info *vi = arg; 1925 struct adapter *sc = vi->adapter; 1926 1927 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1928 return; 1929 cxgbe_init_synchronized(vi); 1930 end_synchronized_op(sc, 0); 1931 } 1932 1933 static int 1934 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1935 { 1936 int rc = 0, mtu, flags; 1937 struct vi_info *vi = ifp->if_softc; 1938 struct port_info *pi = vi->pi; 1939 struct adapter *sc = pi->adapter; 1940 struct ifreq *ifr = (struct ifreq *)data; 1941 uint32_t mask; 1942 1943 switch (cmd) { 1944 case SIOCSIFMTU: 1945 mtu = ifr->ifr_mtu; 1946 if (mtu < ETHERMIN || mtu > MAX_MTU) 1947 return (EINVAL); 1948 1949 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1950 if (rc) 1951 return (rc); 1952 ifp->if_mtu = mtu; 1953 if (vi->flags & VI_INIT_DONE) { 1954 t4_update_fl_bufsize(ifp); 1955 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1956 rc = update_mac_settings(ifp, XGMAC_MTU); 1957 } 1958 end_synchronized_op(sc, 0); 1959 break; 1960 1961 case SIOCSIFFLAGS: 1962 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 1963 if (rc) 1964 return (rc); 1965 1966 if (ifp->if_flags & IFF_UP) { 1967 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1968 flags = vi->if_flags; 1969 if ((ifp->if_flags ^ flags) & 1970 (IFF_PROMISC | IFF_ALLMULTI)) { 1971 rc = update_mac_settings(ifp, 1972 XGMAC_PROMISC | XGMAC_ALLMULTI); 1973 } 1974 } else { 1975 rc = cxgbe_init_synchronized(vi); 1976 } 1977 vi->if_flags = ifp->if_flags; 1978 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1979 rc = cxgbe_uninit_synchronized(vi); 1980 } 1981 end_synchronized_op(sc, 0); 1982 break; 1983 1984 case SIOCADDMULTI: 1985 case SIOCDELMULTI: 1986 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 1987 if (rc) 1988 return (rc); 1989 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1990 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1991 end_synchronized_op(sc, 0); 1992 break; 1993 1994 case SIOCSIFCAP: 1995 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1996 if (rc) 1997 return (rc); 1998 1999 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2000 if (mask & IFCAP_TXCSUM) { 2001 ifp->if_capenable ^= IFCAP_TXCSUM; 2002 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2003 2004 if (IFCAP_TSO4 & ifp->if_capenable && 2005 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2006 mask &= ~IFCAP_TSO4; 2007 ifp->if_capenable &= ~IFCAP_TSO4; 2008 if_printf(ifp, 2009 "tso4 disabled due to -txcsum.\n"); 2010 } 2011 } 2012 if (mask & IFCAP_TXCSUM_IPV6) { 2013 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 2014 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2015 2016 if (IFCAP_TSO6 & ifp->if_capenable && 2017 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2018 mask &= ~IFCAP_TSO6; 2019 ifp->if_capenable &= ~IFCAP_TSO6; 2020 if_printf(ifp, 2021 "tso6 disabled due to -txcsum6.\n"); 2022 } 2023 } 2024 if (mask & IFCAP_RXCSUM) 2025 ifp->if_capenable ^= IFCAP_RXCSUM; 2026 if (mask & IFCAP_RXCSUM_IPV6) 2027 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 2028 2029 /* 2030 * Note that we leave CSUM_TSO alone (it is always set). The 2031 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 2032 * sending a TSO request our way, so it's sufficient to toggle 2033 * IFCAP_TSOx only. 2034 */ 2035 if (mask & IFCAP_TSO4) { 2036 if (!(IFCAP_TSO4 & ifp->if_capenable) && 2037 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2038 if_printf(ifp, "enable txcsum first.\n"); 2039 rc = EAGAIN; 2040 goto fail; 2041 } 2042 ifp->if_capenable ^= IFCAP_TSO4; 2043 } 2044 if (mask & IFCAP_TSO6) { 2045 if (!(IFCAP_TSO6 & ifp->if_capenable) && 2046 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2047 if_printf(ifp, "enable txcsum6 first.\n"); 2048 rc = EAGAIN; 2049 goto fail; 2050 } 2051 ifp->if_capenable ^= IFCAP_TSO6; 2052 } 2053 if (mask & IFCAP_LRO) { 2054 #if defined(INET) || defined(INET6) 2055 int i; 2056 struct sge_rxq *rxq; 2057 2058 ifp->if_capenable ^= IFCAP_LRO; 2059 for_each_rxq(vi, i, rxq) { 2060 if (ifp->if_capenable & IFCAP_LRO) 2061 rxq->iq.flags |= IQ_LRO_ENABLED; 2062 else 2063 rxq->iq.flags &= ~IQ_LRO_ENABLED; 2064 } 2065 #endif 2066 } 2067 #ifdef TCP_OFFLOAD 2068 if (mask & IFCAP_TOE) { 2069 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 2070 2071 rc = toe_capability(vi, enable); 2072 if (rc != 0) 2073 goto fail; 2074 2075 ifp->if_capenable ^= mask; 2076 } 2077 #endif 2078 if (mask & IFCAP_VLAN_HWTAGGING) { 2079 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2080 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2081 rc = update_mac_settings(ifp, XGMAC_VLANEX); 2082 } 2083 if (mask & IFCAP_VLAN_MTU) { 2084 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2085 2086 /* Need to find out how to disable auto-mtu-inflation */ 2087 } 2088 if (mask & IFCAP_VLAN_HWTSO) 2089 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2090 if (mask & IFCAP_VLAN_HWCSUM) 2091 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2092 #ifdef RATELIMIT 2093 if (mask & IFCAP_TXRTLMT) 2094 ifp->if_capenable ^= IFCAP_TXRTLMT; 2095 #endif 2096 if (mask & IFCAP_HWRXTSTMP) { 2097 int i; 2098 struct sge_rxq *rxq; 2099 2100 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 2101 for_each_rxq(vi, i, rxq) { 2102 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 2103 rxq->iq.flags |= IQ_RX_TIMESTAMP; 2104 else 2105 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 2106 } 2107 } 2108 if (mask & IFCAP_NOMAP) 2109 ifp->if_capenable ^= IFCAP_NOMAP; 2110 2111 #ifdef KERN_TLS 2112 if (mask & IFCAP_TXTLS) 2113 ifp->if_capenable ^= (mask & IFCAP_TXTLS); 2114 #endif 2115 if (mask & IFCAP_VXLAN_HWCSUM) { 2116 ifp->if_capenable ^= IFCAP_VXLAN_HWCSUM; 2117 ifp->if_hwassist ^= CSUM_INNER_IP6_UDP | 2118 CSUM_INNER_IP6_TCP | CSUM_INNER_IP | 2119 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP; 2120 } 2121 if (mask & IFCAP_VXLAN_HWTSO) { 2122 ifp->if_capenable ^= IFCAP_VXLAN_HWTSO; 2123 ifp->if_hwassist ^= CSUM_INNER_IP6_TSO | 2124 CSUM_INNER_IP_TSO; 2125 } 2126 2127 #ifdef VLAN_CAPABILITIES 2128 VLAN_CAPABILITIES(ifp); 2129 #endif 2130 fail: 2131 end_synchronized_op(sc, 0); 2132 break; 2133 2134 case SIOCSIFMEDIA: 2135 case SIOCGIFMEDIA: 2136 case SIOCGIFXMEDIA: 2137 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 2138 break; 2139 2140 case SIOCGI2C: { 2141 struct ifi2creq i2c; 2142 2143 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 2144 if (rc != 0) 2145 break; 2146 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 2147 rc = EPERM; 2148 break; 2149 } 2150 if (i2c.len > sizeof(i2c.data)) { 2151 rc = EINVAL; 2152 break; 2153 } 2154 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 2155 if (rc) 2156 return (rc); 2157 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 2158 i2c.offset, i2c.len, &i2c.data[0]); 2159 end_synchronized_op(sc, 0); 2160 if (rc == 0) 2161 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 2162 break; 2163 } 2164 2165 default: 2166 rc = ether_ioctl(ifp, cmd, data); 2167 } 2168 2169 return (rc); 2170 } 2171 2172 static int 2173 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 2174 { 2175 struct vi_info *vi = ifp->if_softc; 2176 struct port_info *pi = vi->pi; 2177 struct adapter *sc = pi->adapter; 2178 struct sge_txq *txq; 2179 #ifdef RATELIMIT 2180 struct cxgbe_snd_tag *cst; 2181 #endif 2182 void *items[1]; 2183 int rc; 2184 2185 M_ASSERTPKTHDR(m); 2186 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 2187 #if defined(KERN_TLS) || defined(RATELIMIT) 2188 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) 2189 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 2190 #endif 2191 2192 if (__predict_false(pi->link_cfg.link_ok == false)) { 2193 m_freem(m); 2194 return (ENETDOWN); 2195 } 2196 2197 rc = parse_pkt(sc, &m); 2198 if (__predict_false(rc != 0)) { 2199 MPASS(m == NULL); /* was freed already */ 2200 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 2201 return (rc); 2202 } 2203 #ifdef RATELIMIT 2204 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) { 2205 cst = mst_to_cst(m->m_pkthdr.snd_tag); 2206 if (cst->type == IF_SND_TAG_TYPE_RATE_LIMIT) 2207 return (ethofld_transmit(ifp, m)); 2208 } 2209 #endif 2210 2211 /* Select a txq. */ 2212 txq = &sc->sge.txq[vi->first_txq]; 2213 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2214 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 2215 vi->rsrv_noflowq); 2216 2217 items[0] = m; 2218 rc = mp_ring_enqueue(txq->r, items, 1, 256); 2219 if (__predict_false(rc != 0)) 2220 m_freem(m); 2221 2222 return (rc); 2223 } 2224 2225 static void 2226 cxgbe_qflush(struct ifnet *ifp) 2227 { 2228 struct vi_info *vi = ifp->if_softc; 2229 struct sge_txq *txq; 2230 int i; 2231 2232 /* queues do not exist if !VI_INIT_DONE. */ 2233 if (vi->flags & VI_INIT_DONE) { 2234 for_each_txq(vi, i, txq) { 2235 TXQ_LOCK(txq); 2236 txq->eq.flags |= EQ_QFLUSH; 2237 TXQ_UNLOCK(txq); 2238 while (!mp_ring_is_idle(txq->r)) { 2239 mp_ring_check_drainage(txq->r, 4096); 2240 pause("qflush", 1); 2241 } 2242 TXQ_LOCK(txq); 2243 txq->eq.flags &= ~EQ_QFLUSH; 2244 TXQ_UNLOCK(txq); 2245 } 2246 } 2247 if_qflush(ifp); 2248 } 2249 2250 static uint64_t 2251 vi_get_counter(struct ifnet *ifp, ift_counter c) 2252 { 2253 struct vi_info *vi = ifp->if_softc; 2254 struct fw_vi_stats_vf *s = &vi->stats; 2255 2256 vi_refresh_stats(vi->adapter, vi); 2257 2258 switch (c) { 2259 case IFCOUNTER_IPACKETS: 2260 return (s->rx_bcast_frames + s->rx_mcast_frames + 2261 s->rx_ucast_frames); 2262 case IFCOUNTER_IERRORS: 2263 return (s->rx_err_frames); 2264 case IFCOUNTER_OPACKETS: 2265 return (s->tx_bcast_frames + s->tx_mcast_frames + 2266 s->tx_ucast_frames + s->tx_offload_frames); 2267 case IFCOUNTER_OERRORS: 2268 return (s->tx_drop_frames); 2269 case IFCOUNTER_IBYTES: 2270 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 2271 s->rx_ucast_bytes); 2272 case IFCOUNTER_OBYTES: 2273 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 2274 s->tx_ucast_bytes + s->tx_offload_bytes); 2275 case IFCOUNTER_IMCASTS: 2276 return (s->rx_mcast_frames); 2277 case IFCOUNTER_OMCASTS: 2278 return (s->tx_mcast_frames); 2279 case IFCOUNTER_OQDROPS: { 2280 uint64_t drops; 2281 2282 drops = 0; 2283 if (vi->flags & VI_INIT_DONE) { 2284 int i; 2285 struct sge_txq *txq; 2286 2287 for_each_txq(vi, i, txq) 2288 drops += counter_u64_fetch(txq->r->dropped); 2289 } 2290 2291 return (drops); 2292 2293 } 2294 2295 default: 2296 return (if_get_counter_default(ifp, c)); 2297 } 2298 } 2299 2300 uint64_t 2301 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2302 { 2303 struct vi_info *vi = ifp->if_softc; 2304 struct port_info *pi = vi->pi; 2305 struct adapter *sc = pi->adapter; 2306 struct port_stats *s = &pi->stats; 2307 2308 if (pi->nvi > 1 || sc->flags & IS_VF) 2309 return (vi_get_counter(ifp, c)); 2310 2311 cxgbe_refresh_stats(sc, pi); 2312 2313 switch (c) { 2314 case IFCOUNTER_IPACKETS: 2315 return (s->rx_frames); 2316 2317 case IFCOUNTER_IERRORS: 2318 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2319 s->rx_fcs_err + s->rx_len_err); 2320 2321 case IFCOUNTER_OPACKETS: 2322 return (s->tx_frames); 2323 2324 case IFCOUNTER_OERRORS: 2325 return (s->tx_error_frames); 2326 2327 case IFCOUNTER_IBYTES: 2328 return (s->rx_octets); 2329 2330 case IFCOUNTER_OBYTES: 2331 return (s->tx_octets); 2332 2333 case IFCOUNTER_IMCASTS: 2334 return (s->rx_mcast_frames); 2335 2336 case IFCOUNTER_OMCASTS: 2337 return (s->tx_mcast_frames); 2338 2339 case IFCOUNTER_IQDROPS: 2340 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2341 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2342 s->rx_trunc3 + pi->tnl_cong_drops); 2343 2344 case IFCOUNTER_OQDROPS: { 2345 uint64_t drops; 2346 2347 drops = s->tx_drop; 2348 if (vi->flags & VI_INIT_DONE) { 2349 int i; 2350 struct sge_txq *txq; 2351 2352 for_each_txq(vi, i, txq) 2353 drops += counter_u64_fetch(txq->r->dropped); 2354 } 2355 2356 return (drops); 2357 2358 } 2359 2360 default: 2361 return (if_get_counter_default(ifp, c)); 2362 } 2363 } 2364 2365 #if defined(KERN_TLS) || defined(RATELIMIT) 2366 void 2367 cxgbe_snd_tag_init(struct cxgbe_snd_tag *cst, struct ifnet *ifp, int type) 2368 { 2369 2370 m_snd_tag_init(&cst->com, ifp); 2371 cst->type = type; 2372 } 2373 2374 static int 2375 cxgbe_snd_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params, 2376 struct m_snd_tag **pt) 2377 { 2378 int error; 2379 2380 switch (params->hdr.type) { 2381 #ifdef RATELIMIT 2382 case IF_SND_TAG_TYPE_RATE_LIMIT: 2383 error = cxgbe_rate_tag_alloc(ifp, params, pt); 2384 break; 2385 #endif 2386 #ifdef KERN_TLS 2387 case IF_SND_TAG_TYPE_TLS: 2388 error = cxgbe_tls_tag_alloc(ifp, params, pt); 2389 break; 2390 #endif 2391 default: 2392 error = EOPNOTSUPP; 2393 } 2394 if (error == 0) 2395 MPASS(mst_to_cst(*pt)->type == params->hdr.type); 2396 return (error); 2397 } 2398 2399 static int 2400 cxgbe_snd_tag_modify(struct m_snd_tag *mst, 2401 union if_snd_tag_modify_params *params) 2402 { 2403 struct cxgbe_snd_tag *cst; 2404 2405 cst = mst_to_cst(mst); 2406 switch (cst->type) { 2407 #ifdef RATELIMIT 2408 case IF_SND_TAG_TYPE_RATE_LIMIT: 2409 return (cxgbe_rate_tag_modify(mst, params)); 2410 #endif 2411 default: 2412 return (EOPNOTSUPP); 2413 } 2414 } 2415 2416 static int 2417 cxgbe_snd_tag_query(struct m_snd_tag *mst, 2418 union if_snd_tag_query_params *params) 2419 { 2420 struct cxgbe_snd_tag *cst; 2421 2422 cst = mst_to_cst(mst); 2423 switch (cst->type) { 2424 #ifdef RATELIMIT 2425 case IF_SND_TAG_TYPE_RATE_LIMIT: 2426 return (cxgbe_rate_tag_query(mst, params)); 2427 #endif 2428 default: 2429 return (EOPNOTSUPP); 2430 } 2431 } 2432 2433 static void 2434 cxgbe_snd_tag_free(struct m_snd_tag *mst) 2435 { 2436 struct cxgbe_snd_tag *cst; 2437 2438 cst = mst_to_cst(mst); 2439 switch (cst->type) { 2440 #ifdef RATELIMIT 2441 case IF_SND_TAG_TYPE_RATE_LIMIT: 2442 cxgbe_rate_tag_free(mst); 2443 return; 2444 #endif 2445 #ifdef KERN_TLS 2446 case IF_SND_TAG_TYPE_TLS: 2447 cxgbe_tls_tag_free(mst); 2448 return; 2449 #endif 2450 default: 2451 panic("shouldn't get here"); 2452 } 2453 } 2454 #endif 2455 2456 /* 2457 * The kernel picks a media from the list we had provided but we still validate 2458 * the requeste. 2459 */ 2460 int 2461 cxgbe_media_change(struct ifnet *ifp) 2462 { 2463 struct vi_info *vi = ifp->if_softc; 2464 struct port_info *pi = vi->pi; 2465 struct ifmedia *ifm = &pi->media; 2466 struct link_config *lc = &pi->link_cfg; 2467 struct adapter *sc = pi->adapter; 2468 int rc; 2469 2470 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2471 if (rc != 0) 2472 return (rc); 2473 PORT_LOCK(pi); 2474 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2475 /* ifconfig .. media autoselect */ 2476 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { 2477 rc = ENOTSUP; /* AN not supported by transceiver */ 2478 goto done; 2479 } 2480 lc->requested_aneg = AUTONEG_ENABLE; 2481 lc->requested_speed = 0; 2482 lc->requested_fc |= PAUSE_AUTONEG; 2483 } else { 2484 lc->requested_aneg = AUTONEG_DISABLE; 2485 lc->requested_speed = 2486 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2487 lc->requested_fc = 0; 2488 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2489 lc->requested_fc |= PAUSE_RX; 2490 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2491 lc->requested_fc |= PAUSE_TX; 2492 } 2493 if (pi->up_vis > 0) { 2494 fixup_link_config(pi); 2495 rc = apply_link_config(pi); 2496 } 2497 done: 2498 PORT_UNLOCK(pi); 2499 end_synchronized_op(sc, 0); 2500 return (rc); 2501 } 2502 2503 /* 2504 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2505 * given speed. 2506 */ 2507 static int 2508 port_mword(struct port_info *pi, uint32_t speed) 2509 { 2510 2511 MPASS(speed & M_FW_PORT_CAP32_SPEED); 2512 MPASS(powerof2(speed)); 2513 2514 switch(pi->port_type) { 2515 case FW_PORT_TYPE_BT_SGMII: 2516 case FW_PORT_TYPE_BT_XFI: 2517 case FW_PORT_TYPE_BT_XAUI: 2518 /* BaseT */ 2519 switch (speed) { 2520 case FW_PORT_CAP32_SPEED_100M: 2521 return (IFM_100_T); 2522 case FW_PORT_CAP32_SPEED_1G: 2523 return (IFM_1000_T); 2524 case FW_PORT_CAP32_SPEED_10G: 2525 return (IFM_10G_T); 2526 } 2527 break; 2528 case FW_PORT_TYPE_KX4: 2529 if (speed == FW_PORT_CAP32_SPEED_10G) 2530 return (IFM_10G_KX4); 2531 break; 2532 case FW_PORT_TYPE_CX4: 2533 if (speed == FW_PORT_CAP32_SPEED_10G) 2534 return (IFM_10G_CX4); 2535 break; 2536 case FW_PORT_TYPE_KX: 2537 if (speed == FW_PORT_CAP32_SPEED_1G) 2538 return (IFM_1000_KX); 2539 break; 2540 case FW_PORT_TYPE_KR: 2541 case FW_PORT_TYPE_BP_AP: 2542 case FW_PORT_TYPE_BP4_AP: 2543 case FW_PORT_TYPE_BP40_BA: 2544 case FW_PORT_TYPE_KR4_100G: 2545 case FW_PORT_TYPE_KR_SFP28: 2546 case FW_PORT_TYPE_KR_XLAUI: 2547 switch (speed) { 2548 case FW_PORT_CAP32_SPEED_1G: 2549 return (IFM_1000_KX); 2550 case FW_PORT_CAP32_SPEED_10G: 2551 return (IFM_10G_KR); 2552 case FW_PORT_CAP32_SPEED_25G: 2553 return (IFM_25G_KR); 2554 case FW_PORT_CAP32_SPEED_40G: 2555 return (IFM_40G_KR4); 2556 case FW_PORT_CAP32_SPEED_50G: 2557 return (IFM_50G_KR2); 2558 case FW_PORT_CAP32_SPEED_100G: 2559 return (IFM_100G_KR4); 2560 } 2561 break; 2562 case FW_PORT_TYPE_FIBER_XFI: 2563 case FW_PORT_TYPE_FIBER_XAUI: 2564 case FW_PORT_TYPE_SFP: 2565 case FW_PORT_TYPE_QSFP_10G: 2566 case FW_PORT_TYPE_QSA: 2567 case FW_PORT_TYPE_QSFP: 2568 case FW_PORT_TYPE_CR4_QSFP: 2569 case FW_PORT_TYPE_CR_QSFP: 2570 case FW_PORT_TYPE_CR2_QSFP: 2571 case FW_PORT_TYPE_SFP28: 2572 /* Pluggable transceiver */ 2573 switch (pi->mod_type) { 2574 case FW_PORT_MOD_TYPE_LR: 2575 switch (speed) { 2576 case FW_PORT_CAP32_SPEED_1G: 2577 return (IFM_1000_LX); 2578 case FW_PORT_CAP32_SPEED_10G: 2579 return (IFM_10G_LR); 2580 case FW_PORT_CAP32_SPEED_25G: 2581 return (IFM_25G_LR); 2582 case FW_PORT_CAP32_SPEED_40G: 2583 return (IFM_40G_LR4); 2584 case FW_PORT_CAP32_SPEED_50G: 2585 return (IFM_50G_LR2); 2586 case FW_PORT_CAP32_SPEED_100G: 2587 return (IFM_100G_LR4); 2588 } 2589 break; 2590 case FW_PORT_MOD_TYPE_SR: 2591 switch (speed) { 2592 case FW_PORT_CAP32_SPEED_1G: 2593 return (IFM_1000_SX); 2594 case FW_PORT_CAP32_SPEED_10G: 2595 return (IFM_10G_SR); 2596 case FW_PORT_CAP32_SPEED_25G: 2597 return (IFM_25G_SR); 2598 case FW_PORT_CAP32_SPEED_40G: 2599 return (IFM_40G_SR4); 2600 case FW_PORT_CAP32_SPEED_50G: 2601 return (IFM_50G_SR2); 2602 case FW_PORT_CAP32_SPEED_100G: 2603 return (IFM_100G_SR4); 2604 } 2605 break; 2606 case FW_PORT_MOD_TYPE_ER: 2607 if (speed == FW_PORT_CAP32_SPEED_10G) 2608 return (IFM_10G_ER); 2609 break; 2610 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2611 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2612 switch (speed) { 2613 case FW_PORT_CAP32_SPEED_1G: 2614 return (IFM_1000_CX); 2615 case FW_PORT_CAP32_SPEED_10G: 2616 return (IFM_10G_TWINAX); 2617 case FW_PORT_CAP32_SPEED_25G: 2618 return (IFM_25G_CR); 2619 case FW_PORT_CAP32_SPEED_40G: 2620 return (IFM_40G_CR4); 2621 case FW_PORT_CAP32_SPEED_50G: 2622 return (IFM_50G_CR2); 2623 case FW_PORT_CAP32_SPEED_100G: 2624 return (IFM_100G_CR4); 2625 } 2626 break; 2627 case FW_PORT_MOD_TYPE_LRM: 2628 if (speed == FW_PORT_CAP32_SPEED_10G) 2629 return (IFM_10G_LRM); 2630 break; 2631 case FW_PORT_MOD_TYPE_NA: 2632 MPASS(0); /* Not pluggable? */ 2633 /* fall throough */ 2634 case FW_PORT_MOD_TYPE_ERROR: 2635 case FW_PORT_MOD_TYPE_UNKNOWN: 2636 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2637 break; 2638 case FW_PORT_MOD_TYPE_NONE: 2639 return (IFM_NONE); 2640 } 2641 break; 2642 case FW_PORT_TYPE_NONE: 2643 return (IFM_NONE); 2644 } 2645 2646 return (IFM_UNKNOWN); 2647 } 2648 2649 void 2650 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2651 { 2652 struct vi_info *vi = ifp->if_softc; 2653 struct port_info *pi = vi->pi; 2654 struct adapter *sc = pi->adapter; 2655 struct link_config *lc = &pi->link_cfg; 2656 2657 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2658 return; 2659 PORT_LOCK(pi); 2660 2661 if (pi->up_vis == 0) { 2662 /* 2663 * If all the interfaces are administratively down the firmware 2664 * does not report transceiver changes. Refresh port info here 2665 * so that ifconfig displays accurate ifmedia at all times. 2666 * This is the only reason we have a synchronized op in this 2667 * function. Just PORT_LOCK would have been enough otherwise. 2668 */ 2669 t4_update_port_info(pi); 2670 build_medialist(pi); 2671 } 2672 2673 /* ifm_status */ 2674 ifmr->ifm_status = IFM_AVALID; 2675 if (lc->link_ok == false) 2676 goto done; 2677 ifmr->ifm_status |= IFM_ACTIVE; 2678 2679 /* ifm_active */ 2680 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2681 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2682 if (lc->fc & PAUSE_RX) 2683 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2684 if (lc->fc & PAUSE_TX) 2685 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2686 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 2687 done: 2688 PORT_UNLOCK(pi); 2689 end_synchronized_op(sc, 0); 2690 } 2691 2692 static int 2693 vcxgbe_probe(device_t dev) 2694 { 2695 char buf[128]; 2696 struct vi_info *vi = device_get_softc(dev); 2697 2698 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2699 vi - vi->pi->vi); 2700 device_set_desc_copy(dev, buf); 2701 2702 return (BUS_PROBE_DEFAULT); 2703 } 2704 2705 static int 2706 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2707 { 2708 int func, index, rc; 2709 uint32_t param, val; 2710 2711 ASSERT_SYNCHRONIZED_OP(sc); 2712 2713 index = vi - pi->vi; 2714 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2715 KASSERT(index < nitems(vi_mac_funcs), 2716 ("%s: VI %s doesn't have a MAC func", __func__, 2717 device_get_nameunit(vi->dev))); 2718 func = vi_mac_funcs[index]; 2719 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2720 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 2721 if (rc < 0) { 2722 device_printf(vi->dev, "failed to allocate virtual interface %d" 2723 "for port %d: %d\n", index, pi->port_id, -rc); 2724 return (-rc); 2725 } 2726 vi->viid = rc; 2727 2728 if (vi->rss_size == 1) { 2729 /* 2730 * This VI didn't get a slice of the RSS table. Reduce the 2731 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2732 * configuration file (nvi, rssnvi for this PF) if this is a 2733 * problem. 2734 */ 2735 device_printf(vi->dev, "RSS table not available.\n"); 2736 vi->rss_base = 0xffff; 2737 2738 return (0); 2739 } 2740 2741 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2742 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2743 V_FW_PARAMS_PARAM_YZ(vi->viid); 2744 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2745 if (rc) 2746 vi->rss_base = 0xffff; 2747 else { 2748 MPASS((val >> 16) == vi->rss_size); 2749 vi->rss_base = val & 0xffff; 2750 } 2751 2752 return (0); 2753 } 2754 2755 static int 2756 vcxgbe_attach(device_t dev) 2757 { 2758 struct vi_info *vi; 2759 struct port_info *pi; 2760 struct adapter *sc; 2761 int rc; 2762 2763 vi = device_get_softc(dev); 2764 pi = vi->pi; 2765 sc = pi->adapter; 2766 2767 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2768 if (rc) 2769 return (rc); 2770 rc = alloc_extra_vi(sc, pi, vi); 2771 end_synchronized_op(sc, 0); 2772 if (rc) 2773 return (rc); 2774 2775 rc = cxgbe_vi_attach(dev, vi); 2776 if (rc) { 2777 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2778 return (rc); 2779 } 2780 return (0); 2781 } 2782 2783 static int 2784 vcxgbe_detach(device_t dev) 2785 { 2786 struct vi_info *vi; 2787 struct adapter *sc; 2788 2789 vi = device_get_softc(dev); 2790 sc = vi->adapter; 2791 2792 doom_vi(sc, vi); 2793 2794 cxgbe_vi_detach(vi); 2795 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2796 2797 end_synchronized_op(sc, 0); 2798 2799 return (0); 2800 } 2801 2802 static struct callout fatal_callout; 2803 2804 static void 2805 delayed_panic(void *arg) 2806 { 2807 struct adapter *sc = arg; 2808 2809 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 2810 } 2811 2812 void 2813 t4_fatal_err(struct adapter *sc, bool fw_error) 2814 { 2815 2816 t4_shutdown_adapter(sc); 2817 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n", 2818 device_get_nameunit(sc->dev)); 2819 if (fw_error) { 2820 ASSERT_SYNCHRONIZED_OP(sc); 2821 sc->flags |= ADAP_ERR; 2822 } else { 2823 ADAPTER_LOCK(sc); 2824 sc->flags |= ADAP_ERR; 2825 ADAPTER_UNLOCK(sc); 2826 } 2827 #ifdef TCP_OFFLOAD 2828 taskqueue_enqueue(taskqueue_thread, &sc->async_event_task); 2829 #endif 2830 2831 if (t4_panic_on_fatal_err) { 2832 log(LOG_ALERT, "%s: panic on fatal error after 30s", 2833 device_get_nameunit(sc->dev)); 2834 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 2835 } 2836 } 2837 2838 void 2839 t4_add_adapter(struct adapter *sc) 2840 { 2841 sx_xlock(&t4_list_lock); 2842 SLIST_INSERT_HEAD(&t4_list, sc, link); 2843 sx_xunlock(&t4_list_lock); 2844 } 2845 2846 int 2847 t4_map_bars_0_and_4(struct adapter *sc) 2848 { 2849 sc->regs_rid = PCIR_BAR(0); 2850 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2851 &sc->regs_rid, RF_ACTIVE); 2852 if (sc->regs_res == NULL) { 2853 device_printf(sc->dev, "cannot map registers.\n"); 2854 return (ENXIO); 2855 } 2856 sc->bt = rman_get_bustag(sc->regs_res); 2857 sc->bh = rman_get_bushandle(sc->regs_res); 2858 sc->mmio_len = rman_get_size(sc->regs_res); 2859 setbit(&sc->doorbells, DOORBELL_KDB); 2860 2861 sc->msix_rid = PCIR_BAR(4); 2862 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2863 &sc->msix_rid, RF_ACTIVE); 2864 if (sc->msix_res == NULL) { 2865 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2866 return (ENXIO); 2867 } 2868 2869 return (0); 2870 } 2871 2872 int 2873 t4_map_bar_2(struct adapter *sc) 2874 { 2875 2876 /* 2877 * T4: only iWARP driver uses the userspace doorbells. There is no need 2878 * to map it if RDMA is disabled. 2879 */ 2880 if (is_t4(sc) && sc->rdmacaps == 0) 2881 return (0); 2882 2883 sc->udbs_rid = PCIR_BAR(2); 2884 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2885 &sc->udbs_rid, RF_ACTIVE); 2886 if (sc->udbs_res == NULL) { 2887 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2888 return (ENXIO); 2889 } 2890 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2891 2892 if (chip_id(sc) >= CHELSIO_T5) { 2893 setbit(&sc->doorbells, DOORBELL_UDB); 2894 #if defined(__i386__) || defined(__amd64__) 2895 if (t5_write_combine) { 2896 int rc, mode; 2897 2898 /* 2899 * Enable write combining on BAR2. This is the 2900 * userspace doorbell BAR and is split into 128B 2901 * (UDBS_SEG_SIZE) doorbell regions, each associated 2902 * with an egress queue. The first 64B has the doorbell 2903 * and the second 64B can be used to submit a tx work 2904 * request with an implicit doorbell. 2905 */ 2906 2907 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2908 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2909 if (rc == 0) { 2910 clrbit(&sc->doorbells, DOORBELL_UDB); 2911 setbit(&sc->doorbells, DOORBELL_WCWR); 2912 setbit(&sc->doorbells, DOORBELL_UDBWC); 2913 } else { 2914 device_printf(sc->dev, 2915 "couldn't enable write combining: %d\n", 2916 rc); 2917 } 2918 2919 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2920 t4_write_reg(sc, A_SGE_STAT_CFG, 2921 V_STATSOURCE_T5(7) | mode); 2922 } 2923 #endif 2924 } 2925 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2926 2927 return (0); 2928 } 2929 2930 struct memwin_init { 2931 uint32_t base; 2932 uint32_t aperture; 2933 }; 2934 2935 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2936 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2937 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2938 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2939 }; 2940 2941 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2942 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2943 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2944 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2945 }; 2946 2947 static void 2948 setup_memwin(struct adapter *sc) 2949 { 2950 const struct memwin_init *mw_init; 2951 struct memwin *mw; 2952 int i; 2953 uint32_t bar0; 2954 2955 if (is_t4(sc)) { 2956 /* 2957 * Read low 32b of bar0 indirectly via the hardware backdoor 2958 * mechanism. Works from within PCI passthrough environments 2959 * too, where rman_get_start() can return a different value. We 2960 * need to program the T4 memory window decoders with the actual 2961 * addresses that will be coming across the PCIe link. 2962 */ 2963 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2964 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2965 2966 mw_init = &t4_memwin[0]; 2967 } else { 2968 /* T5+ use the relative offset inside the PCIe BAR */ 2969 bar0 = 0; 2970 2971 mw_init = &t5_memwin[0]; 2972 } 2973 2974 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2975 rw_init(&mw->mw_lock, "memory window access"); 2976 mw->mw_base = mw_init->base; 2977 mw->mw_aperture = mw_init->aperture; 2978 mw->mw_curpos = 0; 2979 t4_write_reg(sc, 2980 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2981 (mw->mw_base + bar0) | V_BIR(0) | 2982 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2983 rw_wlock(&mw->mw_lock); 2984 position_memwin(sc, i, 0); 2985 rw_wunlock(&mw->mw_lock); 2986 } 2987 2988 /* flush */ 2989 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2990 } 2991 2992 /* 2993 * Positions the memory window at the given address in the card's address space. 2994 * There are some alignment requirements and the actual position may be at an 2995 * address prior to the requested address. mw->mw_curpos always has the actual 2996 * position of the window. 2997 */ 2998 static void 2999 position_memwin(struct adapter *sc, int idx, uint32_t addr) 3000 { 3001 struct memwin *mw; 3002 uint32_t pf; 3003 uint32_t reg; 3004 3005 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3006 mw = &sc->memwin[idx]; 3007 rw_assert(&mw->mw_lock, RA_WLOCKED); 3008 3009 if (is_t4(sc)) { 3010 pf = 0; 3011 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 3012 } else { 3013 pf = V_PFNUM(sc->pf); 3014 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 3015 } 3016 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 3017 t4_write_reg(sc, reg, mw->mw_curpos | pf); 3018 t4_read_reg(sc, reg); /* flush */ 3019 } 3020 3021 int 3022 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 3023 int len, int rw) 3024 { 3025 struct memwin *mw; 3026 uint32_t mw_end, v; 3027 3028 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3029 3030 /* Memory can only be accessed in naturally aligned 4 byte units */ 3031 if (addr & 3 || len & 3 || len <= 0) 3032 return (EINVAL); 3033 3034 mw = &sc->memwin[idx]; 3035 while (len > 0) { 3036 rw_rlock(&mw->mw_lock); 3037 mw_end = mw->mw_curpos + mw->mw_aperture; 3038 if (addr >= mw_end || addr < mw->mw_curpos) { 3039 /* Will need to reposition the window */ 3040 if (!rw_try_upgrade(&mw->mw_lock)) { 3041 rw_runlock(&mw->mw_lock); 3042 rw_wlock(&mw->mw_lock); 3043 } 3044 rw_assert(&mw->mw_lock, RA_WLOCKED); 3045 position_memwin(sc, idx, addr); 3046 rw_downgrade(&mw->mw_lock); 3047 mw_end = mw->mw_curpos + mw->mw_aperture; 3048 } 3049 rw_assert(&mw->mw_lock, RA_RLOCKED); 3050 while (addr < mw_end && len > 0) { 3051 if (rw == 0) { 3052 v = t4_read_reg(sc, mw->mw_base + addr - 3053 mw->mw_curpos); 3054 *val++ = le32toh(v); 3055 } else { 3056 v = *val++; 3057 t4_write_reg(sc, mw->mw_base + addr - 3058 mw->mw_curpos, htole32(v)); 3059 } 3060 addr += 4; 3061 len -= 4; 3062 } 3063 rw_runlock(&mw->mw_lock); 3064 } 3065 3066 return (0); 3067 } 3068 3069 static void 3070 t4_init_atid_table(struct adapter *sc) 3071 { 3072 struct tid_info *t; 3073 int i; 3074 3075 t = &sc->tids; 3076 if (t->natids == 0) 3077 return; 3078 3079 MPASS(t->atid_tab == NULL); 3080 3081 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 3082 M_ZERO | M_WAITOK); 3083 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 3084 t->afree = t->atid_tab; 3085 t->atids_in_use = 0; 3086 for (i = 1; i < t->natids; i++) 3087 t->atid_tab[i - 1].next = &t->atid_tab[i]; 3088 t->atid_tab[t->natids - 1].next = NULL; 3089 } 3090 3091 static void 3092 t4_free_atid_table(struct adapter *sc) 3093 { 3094 struct tid_info *t; 3095 3096 t = &sc->tids; 3097 3098 KASSERT(t->atids_in_use == 0, 3099 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 3100 3101 if (mtx_initialized(&t->atid_lock)) 3102 mtx_destroy(&t->atid_lock); 3103 free(t->atid_tab, M_CXGBE); 3104 t->atid_tab = NULL; 3105 } 3106 3107 int 3108 alloc_atid(struct adapter *sc, void *ctx) 3109 { 3110 struct tid_info *t = &sc->tids; 3111 int atid = -1; 3112 3113 mtx_lock(&t->atid_lock); 3114 if (t->afree) { 3115 union aopen_entry *p = t->afree; 3116 3117 atid = p - t->atid_tab; 3118 MPASS(atid <= M_TID_TID); 3119 t->afree = p->next; 3120 p->data = ctx; 3121 t->atids_in_use++; 3122 } 3123 mtx_unlock(&t->atid_lock); 3124 return (atid); 3125 } 3126 3127 void * 3128 lookup_atid(struct adapter *sc, int atid) 3129 { 3130 struct tid_info *t = &sc->tids; 3131 3132 return (t->atid_tab[atid].data); 3133 } 3134 3135 void 3136 free_atid(struct adapter *sc, int atid) 3137 { 3138 struct tid_info *t = &sc->tids; 3139 union aopen_entry *p = &t->atid_tab[atid]; 3140 3141 mtx_lock(&t->atid_lock); 3142 p->next = t->afree; 3143 t->afree = p; 3144 t->atids_in_use--; 3145 mtx_unlock(&t->atid_lock); 3146 } 3147 3148 static void 3149 queue_tid_release(struct adapter *sc, int tid) 3150 { 3151 3152 CXGBE_UNIMPLEMENTED("deferred tid release"); 3153 } 3154 3155 void 3156 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 3157 { 3158 struct wrqe *wr; 3159 struct cpl_tid_release *req; 3160 3161 wr = alloc_wrqe(sizeof(*req), ctrlq); 3162 if (wr == NULL) { 3163 queue_tid_release(sc, tid); /* defer */ 3164 return; 3165 } 3166 req = wrtod(wr); 3167 3168 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 3169 3170 t4_wrq_tx(sc, wr); 3171 } 3172 3173 static int 3174 t4_range_cmp(const void *a, const void *b) 3175 { 3176 return ((const struct t4_range *)a)->start - 3177 ((const struct t4_range *)b)->start; 3178 } 3179 3180 /* 3181 * Verify that the memory range specified by the addr/len pair is valid within 3182 * the card's address space. 3183 */ 3184 static int 3185 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 3186 { 3187 struct t4_range mem_ranges[4], *r, *next; 3188 uint32_t em, addr_len; 3189 int i, n, remaining; 3190 3191 /* Memory can only be accessed in naturally aligned 4 byte units */ 3192 if (addr & 3 || len & 3 || len == 0) 3193 return (EINVAL); 3194 3195 /* Enabled memories */ 3196 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3197 3198 r = &mem_ranges[0]; 3199 n = 0; 3200 bzero(r, sizeof(mem_ranges)); 3201 if (em & F_EDRAM0_ENABLE) { 3202 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3203 r->size = G_EDRAM0_SIZE(addr_len) << 20; 3204 if (r->size > 0) { 3205 r->start = G_EDRAM0_BASE(addr_len) << 20; 3206 if (addr >= r->start && 3207 addr + len <= r->start + r->size) 3208 return (0); 3209 r++; 3210 n++; 3211 } 3212 } 3213 if (em & F_EDRAM1_ENABLE) { 3214 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3215 r->size = G_EDRAM1_SIZE(addr_len) << 20; 3216 if (r->size > 0) { 3217 r->start = G_EDRAM1_BASE(addr_len) << 20; 3218 if (addr >= r->start && 3219 addr + len <= r->start + r->size) 3220 return (0); 3221 r++; 3222 n++; 3223 } 3224 } 3225 if (em & F_EXT_MEM_ENABLE) { 3226 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3227 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 3228 if (r->size > 0) { 3229 r->start = G_EXT_MEM_BASE(addr_len) << 20; 3230 if (addr >= r->start && 3231 addr + len <= r->start + r->size) 3232 return (0); 3233 r++; 3234 n++; 3235 } 3236 } 3237 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 3238 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3239 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 3240 if (r->size > 0) { 3241 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 3242 if (addr >= r->start && 3243 addr + len <= r->start + r->size) 3244 return (0); 3245 r++; 3246 n++; 3247 } 3248 } 3249 MPASS(n <= nitems(mem_ranges)); 3250 3251 if (n > 1) { 3252 /* Sort and merge the ranges. */ 3253 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 3254 3255 /* Start from index 0 and examine the next n - 1 entries. */ 3256 r = &mem_ranges[0]; 3257 for (remaining = n - 1; remaining > 0; remaining--, r++) { 3258 3259 MPASS(r->size > 0); /* r is a valid entry. */ 3260 next = r + 1; 3261 MPASS(next->size > 0); /* and so is the next one. */ 3262 3263 while (r->start + r->size >= next->start) { 3264 /* Merge the next one into the current entry. */ 3265 r->size = max(r->start + r->size, 3266 next->start + next->size) - r->start; 3267 n--; /* One fewer entry in total. */ 3268 if (--remaining == 0) 3269 goto done; /* short circuit */ 3270 next++; 3271 } 3272 if (next != r + 1) { 3273 /* 3274 * Some entries were merged into r and next 3275 * points to the first valid entry that couldn't 3276 * be merged. 3277 */ 3278 MPASS(next->size > 0); /* must be valid */ 3279 memcpy(r + 1, next, remaining * sizeof(*r)); 3280 #ifdef INVARIANTS 3281 /* 3282 * This so that the foo->size assertion in the 3283 * next iteration of the loop do the right 3284 * thing for entries that were pulled up and are 3285 * no longer valid. 3286 */ 3287 MPASS(n < nitems(mem_ranges)); 3288 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 3289 sizeof(struct t4_range)); 3290 #endif 3291 } 3292 } 3293 done: 3294 /* Done merging the ranges. */ 3295 MPASS(n > 0); 3296 r = &mem_ranges[0]; 3297 for (i = 0; i < n; i++, r++) { 3298 if (addr >= r->start && 3299 addr + len <= r->start + r->size) 3300 return (0); 3301 } 3302 } 3303 3304 return (EFAULT); 3305 } 3306 3307 static int 3308 fwmtype_to_hwmtype(int mtype) 3309 { 3310 3311 switch (mtype) { 3312 case FW_MEMTYPE_EDC0: 3313 return (MEM_EDC0); 3314 case FW_MEMTYPE_EDC1: 3315 return (MEM_EDC1); 3316 case FW_MEMTYPE_EXTMEM: 3317 return (MEM_MC0); 3318 case FW_MEMTYPE_EXTMEM1: 3319 return (MEM_MC1); 3320 default: 3321 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 3322 } 3323 } 3324 3325 /* 3326 * Verify that the memory range specified by the memtype/offset/len pair is 3327 * valid and lies entirely within the memtype specified. The global address of 3328 * the start of the range is returned in addr. 3329 */ 3330 static int 3331 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 3332 uint32_t *addr) 3333 { 3334 uint32_t em, addr_len, maddr; 3335 3336 /* Memory can only be accessed in naturally aligned 4 byte units */ 3337 if (off & 3 || len & 3 || len == 0) 3338 return (EINVAL); 3339 3340 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3341 switch (fwmtype_to_hwmtype(mtype)) { 3342 case MEM_EDC0: 3343 if (!(em & F_EDRAM0_ENABLE)) 3344 return (EINVAL); 3345 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3346 maddr = G_EDRAM0_BASE(addr_len) << 20; 3347 break; 3348 case MEM_EDC1: 3349 if (!(em & F_EDRAM1_ENABLE)) 3350 return (EINVAL); 3351 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3352 maddr = G_EDRAM1_BASE(addr_len) << 20; 3353 break; 3354 case MEM_MC: 3355 if (!(em & F_EXT_MEM_ENABLE)) 3356 return (EINVAL); 3357 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3358 maddr = G_EXT_MEM_BASE(addr_len) << 20; 3359 break; 3360 case MEM_MC1: 3361 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 3362 return (EINVAL); 3363 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3364 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 3365 break; 3366 default: 3367 return (EINVAL); 3368 } 3369 3370 *addr = maddr + off; /* global address */ 3371 return (validate_mem_range(sc, *addr, len)); 3372 } 3373 3374 static int 3375 fixup_devlog_params(struct adapter *sc) 3376 { 3377 struct devlog_params *dparams = &sc->params.devlog; 3378 int rc; 3379 3380 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 3381 dparams->size, &dparams->addr); 3382 3383 return (rc); 3384 } 3385 3386 static void 3387 update_nirq(struct intrs_and_queues *iaq, int nports) 3388 { 3389 3390 iaq->nirq = T4_EXTRA_INTR; 3391 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq); 3392 iaq->nirq += nports * iaq->nofldrxq; 3393 iaq->nirq += nports * (iaq->num_vis - 1) * 3394 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 3395 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 3396 } 3397 3398 /* 3399 * Adjust requirements to fit the number of interrupts available. 3400 */ 3401 static void 3402 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 3403 int navail) 3404 { 3405 int old_nirq; 3406 const int nports = sc->params.nports; 3407 3408 MPASS(nports > 0); 3409 MPASS(navail > 0); 3410 3411 bzero(iaq, sizeof(*iaq)); 3412 iaq->intr_type = itype; 3413 iaq->num_vis = t4_num_vis; 3414 iaq->ntxq = t4_ntxq; 3415 iaq->ntxq_vi = t4_ntxq_vi; 3416 iaq->nrxq = t4_nrxq; 3417 iaq->nrxq_vi = t4_nrxq_vi; 3418 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3419 if (is_offload(sc) || is_ethoffload(sc)) { 3420 iaq->nofldtxq = t4_nofldtxq; 3421 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3422 } 3423 #endif 3424 #ifdef TCP_OFFLOAD 3425 if (is_offload(sc)) { 3426 iaq->nofldrxq = t4_nofldrxq; 3427 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3428 } 3429 #endif 3430 #ifdef DEV_NETMAP 3431 if (t4_native_netmap & NN_MAIN_VI) { 3432 iaq->nnmtxq = t4_nnmtxq; 3433 iaq->nnmrxq = t4_nnmrxq; 3434 } 3435 if (t4_native_netmap & NN_EXTRA_VI) { 3436 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3437 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3438 } 3439 #endif 3440 3441 update_nirq(iaq, nports); 3442 if (iaq->nirq <= navail && 3443 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3444 /* 3445 * This is the normal case -- there are enough interrupts for 3446 * everything. 3447 */ 3448 goto done; 3449 } 3450 3451 /* 3452 * If extra VIs have been configured try reducing their count and see if 3453 * that works. 3454 */ 3455 while (iaq->num_vis > 1) { 3456 iaq->num_vis--; 3457 update_nirq(iaq, nports); 3458 if (iaq->nirq <= navail && 3459 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3460 device_printf(sc->dev, "virtual interfaces per port " 3461 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3462 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3463 "itype %d, navail %u, nirq %d.\n", 3464 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3465 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3466 itype, navail, iaq->nirq); 3467 goto done; 3468 } 3469 } 3470 3471 /* 3472 * Extra VIs will not be created. Log a message if they were requested. 3473 */ 3474 MPASS(iaq->num_vis == 1); 3475 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3476 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3477 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3478 if (iaq->num_vis != t4_num_vis) { 3479 device_printf(sc->dev, "extra virtual interfaces disabled. " 3480 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3481 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3482 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3483 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3484 } 3485 3486 /* 3487 * Keep reducing the number of NIC rx queues to the next lower power of 3488 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3489 * if that works. 3490 */ 3491 do { 3492 if (iaq->nrxq > 1) { 3493 do { 3494 iaq->nrxq--; 3495 } while (!powerof2(iaq->nrxq)); 3496 if (iaq->nnmrxq > iaq->nrxq) 3497 iaq->nnmrxq = iaq->nrxq; 3498 } 3499 if (iaq->nofldrxq > 1) 3500 iaq->nofldrxq >>= 1; 3501 3502 old_nirq = iaq->nirq; 3503 update_nirq(iaq, nports); 3504 if (iaq->nirq <= navail && 3505 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3506 device_printf(sc->dev, "running with reduced number of " 3507 "rx queues because of shortage of interrupts. " 3508 "nrxq=%u, nofldrxq=%u. " 3509 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3510 iaq->nofldrxq, itype, navail, iaq->nirq); 3511 goto done; 3512 } 3513 } while (old_nirq != iaq->nirq); 3514 3515 /* One interrupt for everything. Ugh. */ 3516 device_printf(sc->dev, "running with minimal number of queues. " 3517 "itype %d, navail %u.\n", itype, navail); 3518 iaq->nirq = 1; 3519 iaq->nrxq = 1; 3520 iaq->ntxq = 1; 3521 if (iaq->nofldrxq > 0) { 3522 iaq->nofldrxq = 1; 3523 iaq->nofldtxq = 1; 3524 } 3525 iaq->nnmtxq = 0; 3526 iaq->nnmrxq = 0; 3527 done: 3528 MPASS(iaq->num_vis > 0); 3529 if (iaq->num_vis > 1) { 3530 MPASS(iaq->nrxq_vi > 0); 3531 MPASS(iaq->ntxq_vi > 0); 3532 } 3533 MPASS(iaq->nirq > 0); 3534 MPASS(iaq->nrxq > 0); 3535 MPASS(iaq->ntxq > 0); 3536 if (itype == INTR_MSI) { 3537 MPASS(powerof2(iaq->nirq)); 3538 } 3539 } 3540 3541 static int 3542 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3543 { 3544 int rc, itype, navail, nalloc; 3545 3546 for (itype = INTR_MSIX; itype; itype >>= 1) { 3547 3548 if ((itype & t4_intr_types) == 0) 3549 continue; /* not allowed */ 3550 3551 if (itype == INTR_MSIX) 3552 navail = pci_msix_count(sc->dev); 3553 else if (itype == INTR_MSI) 3554 navail = pci_msi_count(sc->dev); 3555 else 3556 navail = 1; 3557 restart: 3558 if (navail == 0) 3559 continue; 3560 3561 calculate_iaq(sc, iaq, itype, navail); 3562 nalloc = iaq->nirq; 3563 rc = 0; 3564 if (itype == INTR_MSIX) 3565 rc = pci_alloc_msix(sc->dev, &nalloc); 3566 else if (itype == INTR_MSI) 3567 rc = pci_alloc_msi(sc->dev, &nalloc); 3568 3569 if (rc == 0 && nalloc > 0) { 3570 if (nalloc == iaq->nirq) 3571 return (0); 3572 3573 /* 3574 * Didn't get the number requested. Use whatever number 3575 * the kernel is willing to allocate. 3576 */ 3577 device_printf(sc->dev, "fewer vectors than requested, " 3578 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3579 itype, iaq->nirq, nalloc); 3580 pci_release_msi(sc->dev); 3581 navail = nalloc; 3582 goto restart; 3583 } 3584 3585 device_printf(sc->dev, 3586 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3587 itype, rc, iaq->nirq, nalloc); 3588 } 3589 3590 device_printf(sc->dev, 3591 "failed to find a usable interrupt type. " 3592 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3593 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3594 3595 return (ENXIO); 3596 } 3597 3598 #define FW_VERSION(chip) ( \ 3599 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3600 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3601 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3602 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3603 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3604 3605 /* Just enough of fw_hdr to cover all version info. */ 3606 struct fw_h { 3607 __u8 ver; 3608 __u8 chip; 3609 __be16 len512; 3610 __be32 fw_ver; 3611 __be32 tp_microcode_ver; 3612 __u8 intfver_nic; 3613 __u8 intfver_vnic; 3614 __u8 intfver_ofld; 3615 __u8 intfver_ri; 3616 __u8 intfver_iscsipdu; 3617 __u8 intfver_iscsi; 3618 __u8 intfver_fcoepdu; 3619 __u8 intfver_fcoe; 3620 }; 3621 /* Spot check a couple of fields. */ 3622 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 3623 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 3624 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 3625 3626 struct fw_info { 3627 uint8_t chip; 3628 char *kld_name; 3629 char *fw_mod_name; 3630 struct fw_h fw_h; 3631 } fw_info[] = { 3632 { 3633 .chip = CHELSIO_T4, 3634 .kld_name = "t4fw_cfg", 3635 .fw_mod_name = "t4fw", 3636 .fw_h = { 3637 .chip = FW_HDR_CHIP_T4, 3638 .fw_ver = htobe32(FW_VERSION(T4)), 3639 .intfver_nic = FW_INTFVER(T4, NIC), 3640 .intfver_vnic = FW_INTFVER(T4, VNIC), 3641 .intfver_ofld = FW_INTFVER(T4, OFLD), 3642 .intfver_ri = FW_INTFVER(T4, RI), 3643 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3644 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3645 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3646 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3647 }, 3648 }, { 3649 .chip = CHELSIO_T5, 3650 .kld_name = "t5fw_cfg", 3651 .fw_mod_name = "t5fw", 3652 .fw_h = { 3653 .chip = FW_HDR_CHIP_T5, 3654 .fw_ver = htobe32(FW_VERSION(T5)), 3655 .intfver_nic = FW_INTFVER(T5, NIC), 3656 .intfver_vnic = FW_INTFVER(T5, VNIC), 3657 .intfver_ofld = FW_INTFVER(T5, OFLD), 3658 .intfver_ri = FW_INTFVER(T5, RI), 3659 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3660 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3661 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3662 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3663 }, 3664 }, { 3665 .chip = CHELSIO_T6, 3666 .kld_name = "t6fw_cfg", 3667 .fw_mod_name = "t6fw", 3668 .fw_h = { 3669 .chip = FW_HDR_CHIP_T6, 3670 .fw_ver = htobe32(FW_VERSION(T6)), 3671 .intfver_nic = FW_INTFVER(T6, NIC), 3672 .intfver_vnic = FW_INTFVER(T6, VNIC), 3673 .intfver_ofld = FW_INTFVER(T6, OFLD), 3674 .intfver_ri = FW_INTFVER(T6, RI), 3675 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3676 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3677 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3678 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3679 }, 3680 } 3681 }; 3682 3683 static struct fw_info * 3684 find_fw_info(int chip) 3685 { 3686 int i; 3687 3688 for (i = 0; i < nitems(fw_info); i++) { 3689 if (fw_info[i].chip == chip) 3690 return (&fw_info[i]); 3691 } 3692 return (NULL); 3693 } 3694 3695 /* 3696 * Is the given firmware API compatible with the one the driver was compiled 3697 * with? 3698 */ 3699 static int 3700 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 3701 { 3702 3703 /* short circuit if it's the exact same firmware version */ 3704 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3705 return (1); 3706 3707 /* 3708 * XXX: Is this too conservative? Perhaps I should limit this to the 3709 * features that are supported in the driver. 3710 */ 3711 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3712 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3713 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3714 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3715 return (1); 3716 #undef SAME_INTF 3717 3718 return (0); 3719 } 3720 3721 static int 3722 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 3723 const struct firmware **fw) 3724 { 3725 struct fw_info *fw_info; 3726 3727 *dcfg = NULL; 3728 if (fw != NULL) 3729 *fw = NULL; 3730 3731 fw_info = find_fw_info(chip_id(sc)); 3732 if (fw_info == NULL) { 3733 device_printf(sc->dev, 3734 "unable to look up firmware information for chip %d.\n", 3735 chip_id(sc)); 3736 return (EINVAL); 3737 } 3738 3739 *dcfg = firmware_get(fw_info->kld_name); 3740 if (*dcfg != NULL) { 3741 if (fw != NULL) 3742 *fw = firmware_get(fw_info->fw_mod_name); 3743 return (0); 3744 } 3745 3746 return (ENOENT); 3747 } 3748 3749 static void 3750 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 3751 const struct firmware *fw) 3752 { 3753 3754 if (fw != NULL) 3755 firmware_put(fw, FIRMWARE_UNLOAD); 3756 if (dcfg != NULL) 3757 firmware_put(dcfg, FIRMWARE_UNLOAD); 3758 } 3759 3760 /* 3761 * Return values: 3762 * 0 means no firmware install attempted. 3763 * ERESTART means a firmware install was attempted and was successful. 3764 * +ve errno means a firmware install was attempted but failed. 3765 */ 3766 static int 3767 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 3768 const struct fw_h *drv_fw, const char *reason, int *already) 3769 { 3770 const struct firmware *cfg, *fw; 3771 const uint32_t c = be32toh(card_fw->fw_ver); 3772 uint32_t d, k; 3773 int rc, fw_install; 3774 struct fw_h bundled_fw; 3775 bool load_attempted; 3776 3777 cfg = fw = NULL; 3778 load_attempted = false; 3779 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 3780 3781 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 3782 if (t4_fw_install < 0) { 3783 rc = load_fw_module(sc, &cfg, &fw); 3784 if (rc != 0 || fw == NULL) { 3785 device_printf(sc->dev, 3786 "failed to load firmware module: %d. cfg %p, fw %p;" 3787 " will use compiled-in firmware version for" 3788 "hw.cxgbe.fw_install checks.\n", 3789 rc, cfg, fw); 3790 } else { 3791 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 3792 } 3793 load_attempted = true; 3794 } 3795 d = be32toh(bundled_fw.fw_ver); 3796 3797 if (reason != NULL) 3798 goto install; 3799 3800 if ((sc->flags & FW_OK) == 0) { 3801 3802 if (c == 0xffffffff) { 3803 reason = "missing"; 3804 goto install; 3805 } 3806 3807 rc = 0; 3808 goto done; 3809 } 3810 3811 if (!fw_compatible(card_fw, &bundled_fw)) { 3812 reason = "incompatible or unusable"; 3813 goto install; 3814 } 3815 3816 if (d > c) { 3817 reason = "older than the version bundled with this driver"; 3818 goto install; 3819 } 3820 3821 if (fw_install == 2 && d != c) { 3822 reason = "different than the version bundled with this driver"; 3823 goto install; 3824 } 3825 3826 /* No reason to do anything to the firmware already on the card. */ 3827 rc = 0; 3828 goto done; 3829 3830 install: 3831 rc = 0; 3832 if ((*already)++) 3833 goto done; 3834 3835 if (fw_install == 0) { 3836 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3837 "but the driver is prohibited from installing a firmware " 3838 "on the card.\n", 3839 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3840 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3841 3842 goto done; 3843 } 3844 3845 /* 3846 * We'll attempt to install a firmware. Load the module first (if it 3847 * hasn't been loaded already). 3848 */ 3849 if (!load_attempted) { 3850 rc = load_fw_module(sc, &cfg, &fw); 3851 if (rc != 0 || fw == NULL) { 3852 device_printf(sc->dev, 3853 "failed to load firmware module: %d. cfg %p, fw %p\n", 3854 rc, cfg, fw); 3855 /* carry on */ 3856 } 3857 } 3858 if (fw == NULL) { 3859 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3860 "but the driver cannot take corrective action because it " 3861 "is unable to load the firmware module.\n", 3862 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3863 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3864 rc = sc->flags & FW_OK ? 0 : ENOENT; 3865 goto done; 3866 } 3867 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 3868 if (k != d) { 3869 MPASS(t4_fw_install > 0); 3870 device_printf(sc->dev, 3871 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 3872 "expecting (%u.%u.%u.%u) and will not be used.\n", 3873 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3874 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 3875 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3876 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3877 rc = sc->flags & FW_OK ? 0 : EINVAL; 3878 goto done; 3879 } 3880 3881 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3882 "installing firmware %u.%u.%u.%u on card.\n", 3883 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3884 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3885 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3886 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3887 3888 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3889 if (rc != 0) { 3890 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 3891 } else { 3892 /* Installed successfully, update the cached header too. */ 3893 rc = ERESTART; 3894 memcpy(card_fw, fw->data, sizeof(*card_fw)); 3895 } 3896 done: 3897 unload_fw_module(sc, cfg, fw); 3898 3899 return (rc); 3900 } 3901 3902 /* 3903 * Establish contact with the firmware and attempt to become the master driver. 3904 * 3905 * A firmware will be installed to the card if needed (if the driver is allowed 3906 * to do so). 3907 */ 3908 static int 3909 contact_firmware(struct adapter *sc) 3910 { 3911 int rc, already = 0; 3912 enum dev_state state; 3913 struct fw_info *fw_info; 3914 struct fw_hdr *card_fw; /* fw on the card */ 3915 const struct fw_h *drv_fw; 3916 3917 fw_info = find_fw_info(chip_id(sc)); 3918 if (fw_info == NULL) { 3919 device_printf(sc->dev, 3920 "unable to look up firmware information for chip %d.\n", 3921 chip_id(sc)); 3922 return (EINVAL); 3923 } 3924 drv_fw = &fw_info->fw_h; 3925 3926 /* Read the header of the firmware on the card */ 3927 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3928 restart: 3929 rc = -t4_get_fw_hdr(sc, card_fw); 3930 if (rc != 0) { 3931 device_printf(sc->dev, 3932 "unable to read firmware header from card's flash: %d\n", 3933 rc); 3934 goto done; 3935 } 3936 3937 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 3938 &already); 3939 if (rc == ERESTART) 3940 goto restart; 3941 if (rc != 0) 3942 goto done; 3943 3944 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3945 if (rc < 0 || state == DEV_STATE_ERR) { 3946 rc = -rc; 3947 device_printf(sc->dev, 3948 "failed to connect to the firmware: %d, %d. " 3949 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3950 #if 0 3951 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3952 "not responding properly to HELLO", &already) == ERESTART) 3953 goto restart; 3954 #endif 3955 goto done; 3956 } 3957 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 3958 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 3959 3960 if (rc == sc->pf) { 3961 sc->flags |= MASTER_PF; 3962 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3963 NULL, &already); 3964 if (rc == ERESTART) 3965 rc = 0; 3966 else if (rc != 0) 3967 goto done; 3968 } else if (state == DEV_STATE_UNINIT) { 3969 /* 3970 * We didn't get to be the master so we definitely won't be 3971 * configuring the chip. It's a bug if someone else hasn't 3972 * configured it already. 3973 */ 3974 device_printf(sc->dev, "couldn't be master(%d), " 3975 "device not already initialized either(%d). " 3976 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3977 rc = EPROTO; 3978 goto done; 3979 } else { 3980 /* 3981 * Some other PF is the master and has configured the chip. 3982 * This is allowed but untested. 3983 */ 3984 device_printf(sc->dev, "PF%d is master, device state %d. " 3985 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3986 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 3987 sc->cfcsum = 0; 3988 rc = 0; 3989 } 3990 done: 3991 if (rc != 0 && sc->flags & FW_OK) { 3992 t4_fw_bye(sc, sc->mbox); 3993 sc->flags &= ~FW_OK; 3994 } 3995 free(card_fw, M_CXGBE); 3996 return (rc); 3997 } 3998 3999 static int 4000 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 4001 uint32_t mtype, uint32_t moff) 4002 { 4003 struct fw_info *fw_info; 4004 const struct firmware *dcfg, *rcfg = NULL; 4005 const uint32_t *cfdata; 4006 uint32_t cflen, addr; 4007 int rc; 4008 4009 load_fw_module(sc, &dcfg, NULL); 4010 4011 /* Card specific interpretation of "default". */ 4012 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4013 if (pci_get_device(sc->dev) == 0x440a) 4014 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 4015 if (is_fpga(sc)) 4016 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 4017 } 4018 4019 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4020 if (dcfg == NULL) { 4021 device_printf(sc->dev, 4022 "KLD with default config is not available.\n"); 4023 rc = ENOENT; 4024 goto done; 4025 } 4026 cfdata = dcfg->data; 4027 cflen = dcfg->datasize & ~3; 4028 } else { 4029 char s[32]; 4030 4031 fw_info = find_fw_info(chip_id(sc)); 4032 if (fw_info == NULL) { 4033 device_printf(sc->dev, 4034 "unable to look up firmware information for chip %d.\n", 4035 chip_id(sc)); 4036 rc = EINVAL; 4037 goto done; 4038 } 4039 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 4040 4041 rcfg = firmware_get(s); 4042 if (rcfg == NULL) { 4043 device_printf(sc->dev, 4044 "unable to load module \"%s\" for configuration " 4045 "profile \"%s\".\n", s, cfg_file); 4046 rc = ENOENT; 4047 goto done; 4048 } 4049 cfdata = rcfg->data; 4050 cflen = rcfg->datasize & ~3; 4051 } 4052 4053 if (cflen > FLASH_CFG_MAX_SIZE) { 4054 device_printf(sc->dev, 4055 "config file too long (%d, max allowed is %d).\n", 4056 cflen, FLASH_CFG_MAX_SIZE); 4057 rc = EINVAL; 4058 goto done; 4059 } 4060 4061 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 4062 if (rc != 0) { 4063 device_printf(sc->dev, 4064 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 4065 __func__, mtype, moff, cflen, rc); 4066 rc = EINVAL; 4067 goto done; 4068 } 4069 write_via_memwin(sc, 2, addr, cfdata, cflen); 4070 done: 4071 if (rcfg != NULL) 4072 firmware_put(rcfg, FIRMWARE_UNLOAD); 4073 unload_fw_module(sc, dcfg, NULL); 4074 return (rc); 4075 } 4076 4077 struct caps_allowed { 4078 uint16_t nbmcaps; 4079 uint16_t linkcaps; 4080 uint16_t switchcaps; 4081 uint16_t niccaps; 4082 uint16_t toecaps; 4083 uint16_t rdmacaps; 4084 uint16_t cryptocaps; 4085 uint16_t iscsicaps; 4086 uint16_t fcoecaps; 4087 }; 4088 4089 #define FW_PARAM_DEV(param) \ 4090 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 4091 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 4092 #define FW_PARAM_PFVF(param) \ 4093 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 4094 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 4095 4096 /* 4097 * Provide a configuration profile to the firmware and have it initialize the 4098 * chip accordingly. This may involve uploading a configuration file to the 4099 * card. 4100 */ 4101 static int 4102 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 4103 const struct caps_allowed *caps_allowed) 4104 { 4105 int rc; 4106 struct fw_caps_config_cmd caps; 4107 uint32_t mtype, moff, finicsum, cfcsum, param, val; 4108 4109 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 4110 if (rc != 0) { 4111 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 4112 return (rc); 4113 } 4114 4115 bzero(&caps, sizeof(caps)); 4116 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4117 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4118 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 4119 mtype = 0; 4120 moff = 0; 4121 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4122 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 4123 mtype = FW_MEMTYPE_FLASH; 4124 moff = t4_flash_cfg_addr(sc); 4125 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4126 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4127 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4128 FW_LEN16(caps)); 4129 } else { 4130 /* 4131 * Ask the firmware where it wants us to upload the config file. 4132 */ 4133 param = FW_PARAM_DEV(CF); 4134 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4135 if (rc != 0) { 4136 /* No support for config file? Shouldn't happen. */ 4137 device_printf(sc->dev, 4138 "failed to query config file location: %d.\n", rc); 4139 goto done; 4140 } 4141 mtype = G_FW_PARAMS_PARAM_Y(val); 4142 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 4143 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4144 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4145 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4146 FW_LEN16(caps)); 4147 4148 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 4149 if (rc != 0) { 4150 device_printf(sc->dev, 4151 "failed to upload config file to card: %d.\n", rc); 4152 goto done; 4153 } 4154 } 4155 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4156 if (rc != 0) { 4157 device_printf(sc->dev, "failed to pre-process config file: %d " 4158 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 4159 goto done; 4160 } 4161 4162 finicsum = be32toh(caps.finicsum); 4163 cfcsum = be32toh(caps.cfcsum); /* actual */ 4164 if (finicsum != cfcsum) { 4165 device_printf(sc->dev, 4166 "WARNING: config file checksum mismatch: %08x %08x\n", 4167 finicsum, cfcsum); 4168 } 4169 sc->cfcsum = cfcsum; 4170 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 4171 4172 /* 4173 * Let the firmware know what features will (not) be used so it can tune 4174 * things accordingly. 4175 */ 4176 #define LIMIT_CAPS(x) do { \ 4177 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 4178 } while (0) 4179 LIMIT_CAPS(nbm); 4180 LIMIT_CAPS(link); 4181 LIMIT_CAPS(switch); 4182 LIMIT_CAPS(nic); 4183 LIMIT_CAPS(toe); 4184 LIMIT_CAPS(rdma); 4185 LIMIT_CAPS(crypto); 4186 LIMIT_CAPS(iscsi); 4187 LIMIT_CAPS(fcoe); 4188 #undef LIMIT_CAPS 4189 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 4190 /* 4191 * TOE and hashfilters are mutually exclusive. It is a config 4192 * file or firmware bug if both are reported as available. Try 4193 * to cope with the situation in non-debug builds by disabling 4194 * TOE. 4195 */ 4196 MPASS(caps.toecaps == 0); 4197 4198 caps.toecaps = 0; 4199 caps.rdmacaps = 0; 4200 caps.iscsicaps = 0; 4201 } 4202 4203 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4204 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 4205 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4206 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 4207 if (rc != 0) { 4208 device_printf(sc->dev, 4209 "failed to process config file: %d.\n", rc); 4210 goto done; 4211 } 4212 4213 t4_tweak_chip_settings(sc); 4214 set_params__pre_init(sc); 4215 4216 /* get basic stuff going */ 4217 rc = -t4_fw_initialize(sc, sc->mbox); 4218 if (rc != 0) { 4219 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 4220 goto done; 4221 } 4222 done: 4223 return (rc); 4224 } 4225 4226 /* 4227 * Partition chip resources for use between various PFs, VFs, etc. 4228 */ 4229 static int 4230 partition_resources(struct adapter *sc) 4231 { 4232 char cfg_file[sizeof(t4_cfg_file)]; 4233 struct caps_allowed caps_allowed; 4234 int rc; 4235 bool fallback; 4236 4237 /* Only the master driver gets to configure the chip resources. */ 4238 MPASS(sc->flags & MASTER_PF); 4239 4240 #define COPY_CAPS(x) do { \ 4241 caps_allowed.x##caps = t4_##x##caps_allowed; \ 4242 } while (0) 4243 bzero(&caps_allowed, sizeof(caps_allowed)); 4244 COPY_CAPS(nbm); 4245 COPY_CAPS(link); 4246 COPY_CAPS(switch); 4247 COPY_CAPS(nic); 4248 COPY_CAPS(toe); 4249 COPY_CAPS(rdma); 4250 COPY_CAPS(crypto); 4251 COPY_CAPS(iscsi); 4252 COPY_CAPS(fcoe); 4253 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 4254 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 4255 retry: 4256 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 4257 if (rc != 0 && fallback) { 4258 device_printf(sc->dev, 4259 "failed (%d) to configure card with \"%s\" profile, " 4260 "will fall back to a basic configuration and retry.\n", 4261 rc, cfg_file); 4262 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 4263 bzero(&caps_allowed, sizeof(caps_allowed)); 4264 COPY_CAPS(switch); 4265 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 4266 fallback = false; 4267 goto retry; 4268 } 4269 #undef COPY_CAPS 4270 return (rc); 4271 } 4272 4273 /* 4274 * Retrieve parameters that are needed (or nice to have) very early. 4275 */ 4276 static int 4277 get_params__pre_init(struct adapter *sc) 4278 { 4279 int rc; 4280 uint32_t param[2], val[2]; 4281 4282 t4_get_version_info(sc); 4283 4284 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 4285 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 4286 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 4287 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 4288 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 4289 4290 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 4291 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 4292 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 4293 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 4294 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 4295 4296 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 4297 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 4298 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 4299 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 4300 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 4301 4302 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 4303 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 4304 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 4305 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 4306 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 4307 4308 param[0] = FW_PARAM_DEV(PORTVEC); 4309 param[1] = FW_PARAM_DEV(CCLK); 4310 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4311 if (rc != 0) { 4312 device_printf(sc->dev, 4313 "failed to query parameters (pre_init): %d.\n", rc); 4314 return (rc); 4315 } 4316 4317 sc->params.portvec = val[0]; 4318 sc->params.nports = bitcount32(val[0]); 4319 sc->params.vpd.cclk = val[1]; 4320 4321 /* Read device log parameters. */ 4322 rc = -t4_init_devlog_params(sc, 1); 4323 if (rc == 0) 4324 fixup_devlog_params(sc); 4325 else { 4326 device_printf(sc->dev, 4327 "failed to get devlog parameters: %d.\n", rc); 4328 rc = 0; /* devlog isn't critical for device operation */ 4329 } 4330 4331 return (rc); 4332 } 4333 4334 /* 4335 * Any params that need to be set before FW_INITIALIZE. 4336 */ 4337 static int 4338 set_params__pre_init(struct adapter *sc) 4339 { 4340 int rc = 0; 4341 uint32_t param, val; 4342 4343 if (chip_id(sc) >= CHELSIO_T6) { 4344 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 4345 val = 1; 4346 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4347 /* firmwares < 1.20.1.0 do not have this param. */ 4348 if (rc == FW_EINVAL && 4349 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) { 4350 rc = 0; 4351 } 4352 if (rc != 0) { 4353 device_printf(sc->dev, 4354 "failed to enable high priority filters :%d.\n", 4355 rc); 4356 } 4357 } 4358 4359 /* Enable opaque VIIDs with firmwares that support it. */ 4360 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 4361 val = 1; 4362 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4363 if (rc == 0 && val == 1) 4364 sc->params.viid_smt_extn_support = true; 4365 else 4366 sc->params.viid_smt_extn_support = false; 4367 4368 return (rc); 4369 } 4370 4371 /* 4372 * Retrieve various parameters that are of interest to the driver. The device 4373 * has been initialized by the firmware at this point. 4374 */ 4375 static int 4376 get_params__post_init(struct adapter *sc) 4377 { 4378 int rc; 4379 uint32_t param[7], val[7]; 4380 struct fw_caps_config_cmd caps; 4381 4382 param[0] = FW_PARAM_PFVF(IQFLINT_START); 4383 param[1] = FW_PARAM_PFVF(EQ_START); 4384 param[2] = FW_PARAM_PFVF(FILTER_START); 4385 param[3] = FW_PARAM_PFVF(FILTER_END); 4386 param[4] = FW_PARAM_PFVF(L2T_START); 4387 param[5] = FW_PARAM_PFVF(L2T_END); 4388 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 4389 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 4390 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 4391 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 4392 if (rc != 0) { 4393 device_printf(sc->dev, 4394 "failed to query parameters (post_init): %d.\n", rc); 4395 return (rc); 4396 } 4397 4398 sc->sge.iq_start = val[0]; 4399 sc->sge.eq_start = val[1]; 4400 if ((int)val[3] > (int)val[2]) { 4401 sc->tids.ftid_base = val[2]; 4402 sc->tids.ftid_end = val[3]; 4403 sc->tids.nftids = val[3] - val[2] + 1; 4404 } 4405 sc->vres.l2t.start = val[4]; 4406 sc->vres.l2t.size = val[5] - val[4] + 1; 4407 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 4408 ("%s: L2 table size (%u) larger than expected (%u)", 4409 __func__, sc->vres.l2t.size, L2T_SIZE)); 4410 sc->params.core_vdd = val[6]; 4411 4412 if (chip_id(sc) >= CHELSIO_T6) { 4413 4414 sc->tids.tid_base = t4_read_reg(sc, 4415 A_LE_DB_ACTIVE_TABLE_START_INDEX); 4416 4417 param[0] = FW_PARAM_PFVF(HPFILTER_START); 4418 param[1] = FW_PARAM_PFVF(HPFILTER_END); 4419 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4420 if (rc != 0) { 4421 device_printf(sc->dev, 4422 "failed to query hpfilter parameters: %d.\n", rc); 4423 return (rc); 4424 } 4425 if ((int)val[1] > (int)val[0]) { 4426 sc->tids.hpftid_base = val[0]; 4427 sc->tids.hpftid_end = val[1]; 4428 sc->tids.nhpftids = val[1] - val[0] + 1; 4429 4430 /* 4431 * These should go off if the layout changes and the 4432 * driver needs to catch up. 4433 */ 4434 MPASS(sc->tids.hpftid_base == 0); 4435 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 4436 } 4437 4438 param[0] = FW_PARAM_PFVF(RAWF_START); 4439 param[1] = FW_PARAM_PFVF(RAWF_END); 4440 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4441 if (rc != 0) { 4442 device_printf(sc->dev, 4443 "failed to query rawf parameters: %d.\n", rc); 4444 return (rc); 4445 } 4446 if ((int)val[1] > (int)val[0]) { 4447 sc->rawf_base = val[0]; 4448 sc->nrawf = val[1] - val[0] + 1; 4449 } 4450 } 4451 4452 /* 4453 * MPSBGMAP is queried separately because only recent firmwares support 4454 * it as a parameter and we don't want the compound query above to fail 4455 * on older firmwares. 4456 */ 4457 param[0] = FW_PARAM_DEV(MPSBGMAP); 4458 val[0] = 0; 4459 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4460 if (rc == 0) 4461 sc->params.mps_bg_map = val[0]; 4462 else 4463 sc->params.mps_bg_map = 0; 4464 4465 /* 4466 * Determine whether the firmware supports the filter2 work request. 4467 * This is queried separately for the same reason as MPSBGMAP above. 4468 */ 4469 param[0] = FW_PARAM_DEV(FILTER2_WR); 4470 val[0] = 0; 4471 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4472 if (rc == 0) 4473 sc->params.filter2_wr_support = val[0] != 0; 4474 else 4475 sc->params.filter2_wr_support = 0; 4476 4477 /* 4478 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 4479 * This is queried separately for the same reason as other params above. 4480 */ 4481 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4482 val[0] = 0; 4483 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4484 if (rc == 0) 4485 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 4486 else 4487 sc->params.ulptx_memwrite_dsgl = false; 4488 4489 /* FW_RI_FR_NSMR_TPTE_WR support */ 4490 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 4491 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4492 if (rc == 0) 4493 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0; 4494 else 4495 sc->params.fr_nsmr_tpte_wr_support = false; 4496 4497 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 4498 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4499 if (rc == 0) 4500 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0]; 4501 else 4502 sc->params.max_pkts_per_eth_tx_pkts_wr = 15; 4503 4504 /* get capabilites */ 4505 bzero(&caps, sizeof(caps)); 4506 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4507 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4508 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4509 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4510 if (rc != 0) { 4511 device_printf(sc->dev, 4512 "failed to get card capabilities: %d.\n", rc); 4513 return (rc); 4514 } 4515 4516 #define READ_CAPS(x) do { \ 4517 sc->x = htobe16(caps.x); \ 4518 } while (0) 4519 READ_CAPS(nbmcaps); 4520 READ_CAPS(linkcaps); 4521 READ_CAPS(switchcaps); 4522 READ_CAPS(niccaps); 4523 READ_CAPS(toecaps); 4524 READ_CAPS(rdmacaps); 4525 READ_CAPS(cryptocaps); 4526 READ_CAPS(iscsicaps); 4527 READ_CAPS(fcoecaps); 4528 4529 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 4530 MPASS(chip_id(sc) > CHELSIO_T4); 4531 MPASS(sc->toecaps == 0); 4532 sc->toecaps = 0; 4533 4534 param[0] = FW_PARAM_DEV(NTID); 4535 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4536 if (rc != 0) { 4537 device_printf(sc->dev, 4538 "failed to query HASHFILTER parameters: %d.\n", rc); 4539 return (rc); 4540 } 4541 sc->tids.ntids = val[0]; 4542 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 4543 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4544 sc->tids.ntids -= sc->tids.nhpftids; 4545 } 4546 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4547 sc->params.hash_filter = 1; 4548 } 4549 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 4550 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 4551 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 4552 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4553 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 4554 if (rc != 0) { 4555 device_printf(sc->dev, 4556 "failed to query NIC parameters: %d.\n", rc); 4557 return (rc); 4558 } 4559 if ((int)val[1] > (int)val[0]) { 4560 sc->tids.etid_base = val[0]; 4561 sc->tids.etid_end = val[1]; 4562 sc->tids.netids = val[1] - val[0] + 1; 4563 sc->params.eo_wr_cred = val[2]; 4564 sc->params.ethoffload = 1; 4565 } 4566 } 4567 if (sc->toecaps) { 4568 /* query offload-related parameters */ 4569 param[0] = FW_PARAM_DEV(NTID); 4570 param[1] = FW_PARAM_PFVF(SERVER_START); 4571 param[2] = FW_PARAM_PFVF(SERVER_END); 4572 param[3] = FW_PARAM_PFVF(TDDP_START); 4573 param[4] = FW_PARAM_PFVF(TDDP_END); 4574 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4575 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4576 if (rc != 0) { 4577 device_printf(sc->dev, 4578 "failed to query TOE parameters: %d.\n", rc); 4579 return (rc); 4580 } 4581 sc->tids.ntids = val[0]; 4582 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 4583 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4584 sc->tids.ntids -= sc->tids.nhpftids; 4585 } 4586 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4587 if ((int)val[2] > (int)val[1]) { 4588 sc->tids.stid_base = val[1]; 4589 sc->tids.nstids = val[2] - val[1] + 1; 4590 } 4591 sc->vres.ddp.start = val[3]; 4592 sc->vres.ddp.size = val[4] - val[3] + 1; 4593 sc->params.ofldq_wr_cred = val[5]; 4594 sc->params.offload = 1; 4595 } else { 4596 /* 4597 * The firmware attempts memfree TOE configuration for -SO cards 4598 * and will report toecaps=0 if it runs out of resources (this 4599 * depends on the config file). It may not report 0 for other 4600 * capabilities dependent on the TOE in this case. Set them to 4601 * 0 here so that the driver doesn't bother tracking resources 4602 * that will never be used. 4603 */ 4604 sc->iscsicaps = 0; 4605 sc->rdmacaps = 0; 4606 } 4607 if (sc->rdmacaps) { 4608 param[0] = FW_PARAM_PFVF(STAG_START); 4609 param[1] = FW_PARAM_PFVF(STAG_END); 4610 param[2] = FW_PARAM_PFVF(RQ_START); 4611 param[3] = FW_PARAM_PFVF(RQ_END); 4612 param[4] = FW_PARAM_PFVF(PBL_START); 4613 param[5] = FW_PARAM_PFVF(PBL_END); 4614 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4615 if (rc != 0) { 4616 device_printf(sc->dev, 4617 "failed to query RDMA parameters(1): %d.\n", rc); 4618 return (rc); 4619 } 4620 sc->vres.stag.start = val[0]; 4621 sc->vres.stag.size = val[1] - val[0] + 1; 4622 sc->vres.rq.start = val[2]; 4623 sc->vres.rq.size = val[3] - val[2] + 1; 4624 sc->vres.pbl.start = val[4]; 4625 sc->vres.pbl.size = val[5] - val[4] + 1; 4626 4627 param[0] = FW_PARAM_PFVF(SQRQ_START); 4628 param[1] = FW_PARAM_PFVF(SQRQ_END); 4629 param[2] = FW_PARAM_PFVF(CQ_START); 4630 param[3] = FW_PARAM_PFVF(CQ_END); 4631 param[4] = FW_PARAM_PFVF(OCQ_START); 4632 param[5] = FW_PARAM_PFVF(OCQ_END); 4633 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4634 if (rc != 0) { 4635 device_printf(sc->dev, 4636 "failed to query RDMA parameters(2): %d.\n", rc); 4637 return (rc); 4638 } 4639 sc->vres.qp.start = val[0]; 4640 sc->vres.qp.size = val[1] - val[0] + 1; 4641 sc->vres.cq.start = val[2]; 4642 sc->vres.cq.size = val[3] - val[2] + 1; 4643 sc->vres.ocq.start = val[4]; 4644 sc->vres.ocq.size = val[5] - val[4] + 1; 4645 4646 param[0] = FW_PARAM_PFVF(SRQ_START); 4647 param[1] = FW_PARAM_PFVF(SRQ_END); 4648 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4649 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4650 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4651 if (rc != 0) { 4652 device_printf(sc->dev, 4653 "failed to query RDMA parameters(3): %d.\n", rc); 4654 return (rc); 4655 } 4656 sc->vres.srq.start = val[0]; 4657 sc->vres.srq.size = val[1] - val[0] + 1; 4658 sc->params.max_ordird_qp = val[2]; 4659 sc->params.max_ird_adapter = val[3]; 4660 } 4661 if (sc->iscsicaps) { 4662 param[0] = FW_PARAM_PFVF(ISCSI_START); 4663 param[1] = FW_PARAM_PFVF(ISCSI_END); 4664 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4665 if (rc != 0) { 4666 device_printf(sc->dev, 4667 "failed to query iSCSI parameters: %d.\n", rc); 4668 return (rc); 4669 } 4670 sc->vres.iscsi.start = val[0]; 4671 sc->vres.iscsi.size = val[1] - val[0] + 1; 4672 } 4673 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4674 param[0] = FW_PARAM_PFVF(TLS_START); 4675 param[1] = FW_PARAM_PFVF(TLS_END); 4676 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4677 if (rc != 0) { 4678 device_printf(sc->dev, 4679 "failed to query TLS parameters: %d.\n", rc); 4680 return (rc); 4681 } 4682 sc->vres.key.start = val[0]; 4683 sc->vres.key.size = val[1] - val[0] + 1; 4684 } 4685 4686 t4_init_sge_params(sc); 4687 4688 /* 4689 * We've got the params we wanted to query via the firmware. Now grab 4690 * some others directly from the chip. 4691 */ 4692 rc = t4_read_chip_settings(sc); 4693 4694 return (rc); 4695 } 4696 4697 #ifdef KERN_TLS 4698 static void 4699 ktls_tick(void *arg) 4700 { 4701 struct adapter *sc; 4702 uint32_t tstamp; 4703 4704 sc = arg; 4705 4706 tstamp = tcp_ts_getticks(); 4707 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1); 4708 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31); 4709 4710 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK); 4711 } 4712 4713 static void 4714 t4_enable_kern_tls(struct adapter *sc) 4715 { 4716 uint32_t m, v; 4717 4718 m = F_ENABLECBYP; 4719 v = F_ENABLECBYP; 4720 t4_set_reg_field(sc, A_TP_PARA_REG6, m, v); 4721 4722 m = F_CPL_FLAGS_UPDATE_EN | F_SEQ_UPDATE_EN; 4723 v = F_CPL_FLAGS_UPDATE_EN | F_SEQ_UPDATE_EN; 4724 t4_set_reg_field(sc, A_ULP_TX_CONFIG, m, v); 4725 4726 m = F_NICMODE; 4727 v = F_NICMODE; 4728 t4_set_reg_field(sc, A_TP_IN_CONFIG, m, v); 4729 4730 m = F_LOOKUPEVERYPKT; 4731 v = 0; 4732 t4_set_reg_field(sc, A_TP_INGRESS_CONFIG, m, v); 4733 4734 m = F_TXDEFERENABLE | F_DISABLEWINDOWPSH | F_DISABLESEPPSHFLAG; 4735 v = F_DISABLEWINDOWPSH; 4736 t4_set_reg_field(sc, A_TP_PC_CONFIG, m, v); 4737 4738 m = V_TIMESTAMPRESOLUTION(M_TIMESTAMPRESOLUTION); 4739 v = V_TIMESTAMPRESOLUTION(0x1f); 4740 t4_set_reg_field(sc, A_TP_TIMER_RESOLUTION, m, v); 4741 4742 sc->flags |= KERN_TLS_OK; 4743 4744 sc->tlst.inline_keys = t4_tls_inline_keys; 4745 sc->tlst.combo_wrs = t4_tls_combo_wrs; 4746 } 4747 #endif 4748 4749 static int 4750 set_params__post_init(struct adapter *sc) 4751 { 4752 uint32_t param, val; 4753 #ifdef TCP_OFFLOAD 4754 int i, v, shift; 4755 #endif 4756 4757 /* ask for encapsulated CPLs */ 4758 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4759 val = 1; 4760 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4761 4762 /* Enable 32b port caps if the firmware supports it. */ 4763 param = FW_PARAM_PFVF(PORT_CAPS32); 4764 val = 1; 4765 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 4766 sc->params.port_caps32 = 1; 4767 4768 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 4769 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 4770 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 4771 V_MASKFILTER(val - 1)); 4772 4773 #ifdef TCP_OFFLOAD 4774 /* 4775 * Override the TOE timers with user provided tunables. This is not the 4776 * recommended way to change the timers (the firmware config file is) so 4777 * these tunables are not documented. 4778 * 4779 * All the timer tunables are in microseconds. 4780 */ 4781 if (t4_toe_keepalive_idle != 0) { 4782 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4783 v &= M_KEEPALIVEIDLE; 4784 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4785 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4786 } 4787 if (t4_toe_keepalive_interval != 0) { 4788 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4789 v &= M_KEEPALIVEINTVL; 4790 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4791 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4792 } 4793 if (t4_toe_keepalive_count != 0) { 4794 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4795 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4796 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4797 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4798 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4799 } 4800 if (t4_toe_rexmt_min != 0) { 4801 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4802 v &= M_RXTMIN; 4803 t4_set_reg_field(sc, A_TP_RXT_MIN, 4804 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4805 } 4806 if (t4_toe_rexmt_max != 0) { 4807 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4808 v &= M_RXTMAX; 4809 t4_set_reg_field(sc, A_TP_RXT_MAX, 4810 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4811 } 4812 if (t4_toe_rexmt_count != 0) { 4813 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4814 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4815 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4816 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4817 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4818 } 4819 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4820 if (t4_toe_rexmt_backoff[i] != -1) { 4821 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4822 shift = (i & 3) << 3; 4823 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4824 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4825 } 4826 } 4827 #endif 4828 4829 #ifdef KERN_TLS 4830 if (t4_kern_tls != 0 && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 4831 sc->toecaps & FW_CAPS_CONFIG_TOE) 4832 t4_enable_kern_tls(sc); 4833 #endif 4834 return (0); 4835 } 4836 4837 #undef FW_PARAM_PFVF 4838 #undef FW_PARAM_DEV 4839 4840 static void 4841 t4_set_desc(struct adapter *sc) 4842 { 4843 char buf[128]; 4844 struct adapter_params *p = &sc->params; 4845 4846 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4847 4848 device_set_desc_copy(sc->dev, buf); 4849 } 4850 4851 static inline void 4852 ifmedia_add4(struct ifmedia *ifm, int m) 4853 { 4854 4855 ifmedia_add(ifm, m, 0, NULL); 4856 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4857 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4858 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4859 } 4860 4861 /* 4862 * This is the selected media, which is not quite the same as the active media. 4863 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 4864 * and active are not the same, and "media: Ethernet selected" otherwise. 4865 */ 4866 static void 4867 set_current_media(struct port_info *pi) 4868 { 4869 struct link_config *lc; 4870 struct ifmedia *ifm; 4871 int mword; 4872 u_int speed; 4873 4874 PORT_LOCK_ASSERT_OWNED(pi); 4875 4876 /* Leave current media alone if it's already set to IFM_NONE. */ 4877 ifm = &pi->media; 4878 if (ifm->ifm_cur != NULL && 4879 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4880 return; 4881 4882 lc = &pi->link_cfg; 4883 if (lc->requested_aneg != AUTONEG_DISABLE && 4884 lc->pcaps & FW_PORT_CAP32_ANEG) { 4885 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4886 return; 4887 } 4888 mword = IFM_ETHER | IFM_FDX; 4889 if (lc->requested_fc & PAUSE_TX) 4890 mword |= IFM_ETH_TXPAUSE; 4891 if (lc->requested_fc & PAUSE_RX) 4892 mword |= IFM_ETH_RXPAUSE; 4893 if (lc->requested_speed == 0) 4894 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 4895 else 4896 speed = lc->requested_speed; 4897 mword |= port_mword(pi, speed_to_fwcap(speed)); 4898 ifmedia_set(ifm, mword); 4899 } 4900 4901 /* 4902 * Returns true if the ifmedia list for the port cannot change. 4903 */ 4904 static bool 4905 fixed_ifmedia(struct port_info *pi) 4906 { 4907 4908 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 4909 pi->port_type == FW_PORT_TYPE_BT_XFI || 4910 pi->port_type == FW_PORT_TYPE_BT_XAUI || 4911 pi->port_type == FW_PORT_TYPE_KX4 || 4912 pi->port_type == FW_PORT_TYPE_KX || 4913 pi->port_type == FW_PORT_TYPE_KR || 4914 pi->port_type == FW_PORT_TYPE_BP_AP || 4915 pi->port_type == FW_PORT_TYPE_BP4_AP || 4916 pi->port_type == FW_PORT_TYPE_BP40_BA || 4917 pi->port_type == FW_PORT_TYPE_KR4_100G || 4918 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 4919 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 4920 } 4921 4922 static void 4923 build_medialist(struct port_info *pi) 4924 { 4925 uint32_t ss, speed; 4926 int unknown, mword, bit; 4927 struct link_config *lc; 4928 struct ifmedia *ifm; 4929 4930 PORT_LOCK_ASSERT_OWNED(pi); 4931 4932 if (pi->flags & FIXED_IFMEDIA) 4933 return; 4934 4935 /* 4936 * Rebuild the ifmedia list. 4937 */ 4938 ifm = &pi->media; 4939 ifmedia_removeall(ifm); 4940 lc = &pi->link_cfg; 4941 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */ 4942 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 4943 MPASS(ss != 0); 4944 no_media: 4945 MPASS(LIST_EMPTY(&ifm->ifm_list)); 4946 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 4947 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 4948 return; 4949 } 4950 4951 unknown = 0; 4952 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 4953 speed = 1 << bit; 4954 MPASS(speed & M_FW_PORT_CAP32_SPEED); 4955 if (ss & speed) { 4956 mword = port_mword(pi, speed); 4957 if (mword == IFM_NONE) { 4958 goto no_media; 4959 } else if (mword == IFM_UNKNOWN) 4960 unknown++; 4961 else 4962 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 4963 } 4964 } 4965 if (unknown > 0) /* Add one unknown for all unknown media types. */ 4966 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 4967 if (lc->pcaps & FW_PORT_CAP32_ANEG) 4968 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 4969 4970 set_current_media(pi); 4971 } 4972 4973 /* 4974 * Initialize the requested fields in the link config based on driver tunables. 4975 */ 4976 static void 4977 init_link_config(struct port_info *pi) 4978 { 4979 struct link_config *lc = &pi->link_cfg; 4980 4981 PORT_LOCK_ASSERT_OWNED(pi); 4982 4983 lc->requested_speed = 0; 4984 4985 if (t4_autoneg == 0) 4986 lc->requested_aneg = AUTONEG_DISABLE; 4987 else if (t4_autoneg == 1) 4988 lc->requested_aneg = AUTONEG_ENABLE; 4989 else 4990 lc->requested_aneg = AUTONEG_AUTO; 4991 4992 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 4993 PAUSE_AUTONEG); 4994 4995 if (t4_fec & FEC_AUTO) 4996 lc->requested_fec = FEC_AUTO; 4997 else if (t4_fec == 0) 4998 lc->requested_fec = FEC_NONE; 4999 else { 5000 /* -1 is handled by the FEC_AUTO block above and not here. */ 5001 lc->requested_fec = t4_fec & 5002 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE); 5003 if (lc->requested_fec == 0) 5004 lc->requested_fec = FEC_AUTO; 5005 } 5006 } 5007 5008 /* 5009 * Makes sure that all requested settings comply with what's supported by the 5010 * port. Returns the number of settings that were invalid and had to be fixed. 5011 */ 5012 static int 5013 fixup_link_config(struct port_info *pi) 5014 { 5015 int n = 0; 5016 struct link_config *lc = &pi->link_cfg; 5017 uint32_t fwspeed; 5018 5019 PORT_LOCK_ASSERT_OWNED(pi); 5020 5021 /* Speed (when not autonegotiating) */ 5022 if (lc->requested_speed != 0) { 5023 fwspeed = speed_to_fwcap(lc->requested_speed); 5024 if ((fwspeed & lc->pcaps) == 0) { 5025 n++; 5026 lc->requested_speed = 0; 5027 } 5028 } 5029 5030 /* Link autonegotiation */ 5031 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 5032 lc->requested_aneg == AUTONEG_DISABLE || 5033 lc->requested_aneg == AUTONEG_AUTO); 5034 if (lc->requested_aneg == AUTONEG_ENABLE && 5035 !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 5036 n++; 5037 lc->requested_aneg = AUTONEG_AUTO; 5038 } 5039 5040 /* Flow control */ 5041 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 5042 if (lc->requested_fc & PAUSE_TX && 5043 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) { 5044 n++; 5045 lc->requested_fc &= ~PAUSE_TX; 5046 } 5047 if (lc->requested_fc & PAUSE_RX && 5048 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) { 5049 n++; 5050 lc->requested_fc &= ~PAUSE_RX; 5051 } 5052 if (!(lc->requested_fc & PAUSE_AUTONEG) && 5053 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) { 5054 n++; 5055 lc->requested_fc |= PAUSE_AUTONEG; 5056 } 5057 5058 /* FEC */ 5059 if ((lc->requested_fec & FEC_RS && 5060 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) || 5061 (lc->requested_fec & FEC_BASER_RS && 5062 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) { 5063 n++; 5064 lc->requested_fec = FEC_AUTO; 5065 } 5066 5067 return (n); 5068 } 5069 5070 /* 5071 * Apply the requested L1 settings, which are expected to be valid, to the 5072 * hardware. 5073 */ 5074 static int 5075 apply_link_config(struct port_info *pi) 5076 { 5077 struct adapter *sc = pi->adapter; 5078 struct link_config *lc = &pi->link_cfg; 5079 int rc; 5080 5081 #ifdef INVARIANTS 5082 ASSERT_SYNCHRONIZED_OP(sc); 5083 PORT_LOCK_ASSERT_OWNED(pi); 5084 5085 if (lc->requested_aneg == AUTONEG_ENABLE) 5086 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG); 5087 if (!(lc->requested_fc & PAUSE_AUTONEG)) 5088 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE); 5089 if (lc->requested_fc & PAUSE_TX) 5090 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX); 5091 if (lc->requested_fc & PAUSE_RX) 5092 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX); 5093 if (lc->requested_fec & FEC_RS) 5094 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS); 5095 if (lc->requested_fec & FEC_BASER_RS) 5096 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS); 5097 #endif 5098 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5099 if (rc != 0) { 5100 /* Don't complain if the VF driver gets back an EPERM. */ 5101 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 5102 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 5103 } else { 5104 /* 5105 * An L1_CFG will almost always result in a link-change event if 5106 * the link is up, and the driver will refresh the actual 5107 * fec/fc/etc. when the notification is processed. If the link 5108 * is down then the actual settings are meaningless. 5109 * 5110 * This takes care of the case where a change in the L1 settings 5111 * may not result in a notification. 5112 */ 5113 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 5114 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 5115 } 5116 return (rc); 5117 } 5118 5119 #define FW_MAC_EXACT_CHUNK 7 5120 struct mcaddr_ctx { 5121 struct ifnet *ifp; 5122 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 5123 uint64_t hash; 5124 int i; 5125 int del; 5126 int rc; 5127 }; 5128 5129 static u_int 5130 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 5131 { 5132 struct mcaddr_ctx *ctx = arg; 5133 struct vi_info *vi = ctx->ifp->if_softc; 5134 struct port_info *pi = vi->pi; 5135 struct adapter *sc = pi->adapter; 5136 5137 if (ctx->rc < 0) 5138 return (0); 5139 5140 ctx->mcaddr[ctx->i] = LLADDR(sdl); 5141 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i])); 5142 ctx->i++; 5143 5144 if (ctx->i == FW_MAC_EXACT_CHUNK) { 5145 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del, 5146 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0); 5147 if (ctx->rc < 0) { 5148 int j; 5149 5150 for (j = 0; j < ctx->i; j++) { 5151 if_printf(ctx->ifp, 5152 "failed to add mc address" 5153 " %02x:%02x:%02x:" 5154 "%02x:%02x:%02x rc=%d\n", 5155 ctx->mcaddr[j][0], ctx->mcaddr[j][1], 5156 ctx->mcaddr[j][2], ctx->mcaddr[j][3], 5157 ctx->mcaddr[j][4], ctx->mcaddr[j][5], 5158 -ctx->rc); 5159 } 5160 return (0); 5161 } 5162 ctx->del = 0; 5163 ctx->i = 0; 5164 } 5165 5166 return (1); 5167 } 5168 5169 /* 5170 * Program the port's XGMAC based on parameters in ifnet. The caller also 5171 * indicates which parameters should be programmed (the rest are left alone). 5172 */ 5173 int 5174 update_mac_settings(struct ifnet *ifp, int flags) 5175 { 5176 int rc = 0; 5177 struct vi_info *vi = ifp->if_softc; 5178 struct port_info *pi = vi->pi; 5179 struct adapter *sc = pi->adapter; 5180 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 5181 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 5182 5183 ASSERT_SYNCHRONIZED_OP(sc); 5184 KASSERT(flags, ("%s: not told what to update.", __func__)); 5185 5186 if (flags & XGMAC_MTU) 5187 mtu = ifp->if_mtu; 5188 5189 if (flags & XGMAC_PROMISC) 5190 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 5191 5192 if (flags & XGMAC_ALLMULTI) 5193 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 5194 5195 if (flags & XGMAC_VLANEX) 5196 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 5197 5198 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 5199 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 5200 allmulti, 1, vlanex, false); 5201 if (rc) { 5202 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 5203 rc); 5204 return (rc); 5205 } 5206 } 5207 5208 if (flags & XGMAC_UCADDR) { 5209 uint8_t ucaddr[ETHER_ADDR_LEN]; 5210 5211 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 5212 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 5213 ucaddr, true, &vi->smt_idx); 5214 if (rc < 0) { 5215 rc = -rc; 5216 if_printf(ifp, "change_mac failed: %d\n", rc); 5217 return (rc); 5218 } else { 5219 vi->xact_addr_filt = rc; 5220 rc = 0; 5221 } 5222 } 5223 5224 if (flags & XGMAC_MCADDRS) { 5225 struct epoch_tracker et; 5226 struct mcaddr_ctx ctx; 5227 int j; 5228 5229 ctx.ifp = ifp; 5230 ctx.hash = 0; 5231 ctx.i = 0; 5232 ctx.del = 1; 5233 ctx.rc = 0; 5234 /* 5235 * Unlike other drivers, we accumulate list of pointers into 5236 * interface address lists and we need to keep it safe even 5237 * after if_foreach_llmaddr() returns, thus we must enter the 5238 * network epoch. 5239 */ 5240 NET_EPOCH_ENTER(et); 5241 if_foreach_llmaddr(ifp, add_maddr, &ctx); 5242 if (ctx.rc < 0) { 5243 NET_EPOCH_EXIT(et); 5244 rc = -ctx.rc; 5245 return (rc); 5246 } 5247 if (ctx.i > 0) { 5248 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 5249 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0); 5250 NET_EPOCH_EXIT(et); 5251 if (rc < 0) { 5252 rc = -rc; 5253 for (j = 0; j < ctx.i; j++) { 5254 if_printf(ifp, 5255 "failed to add mcast address" 5256 " %02x:%02x:%02x:" 5257 "%02x:%02x:%02x rc=%d\n", 5258 ctx.mcaddr[j][0], ctx.mcaddr[j][1], 5259 ctx.mcaddr[j][2], ctx.mcaddr[j][3], 5260 ctx.mcaddr[j][4], ctx.mcaddr[j][5], 5261 rc); 5262 } 5263 return (rc); 5264 } 5265 ctx.del = 0; 5266 } else 5267 NET_EPOCH_EXIT(et); 5268 5269 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0); 5270 if (rc != 0) 5271 if_printf(ifp, "failed to set mcast address hash: %d\n", 5272 rc); 5273 if (ctx.del == 0) { 5274 /* We clobbered the VXLAN entry if there was one. */ 5275 pi->vxlan_tcam_entry = false; 5276 } 5277 } 5278 5279 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 && 5280 pi->vxlan_tcam_entry == false) { 5281 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac, 5282 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 5283 true); 5284 if (rc < 0) { 5285 rc = -rc; 5286 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n", 5287 rc); 5288 } else { 5289 MPASS(rc == sc->rawf_base + pi->port_id); 5290 rc = 0; 5291 pi->vxlan_tcam_entry = true; 5292 } 5293 } 5294 5295 return (rc); 5296 } 5297 5298 /* 5299 * {begin|end}_synchronized_op must be called from the same thread. 5300 */ 5301 int 5302 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 5303 char *wmesg) 5304 { 5305 int rc, pri; 5306 5307 #ifdef WITNESS 5308 /* the caller thinks it's ok to sleep, but is it really? */ 5309 if (flags & SLEEP_OK) 5310 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 5311 "begin_synchronized_op"); 5312 #endif 5313 5314 if (INTR_OK) 5315 pri = PCATCH; 5316 else 5317 pri = 0; 5318 5319 ADAPTER_LOCK(sc); 5320 for (;;) { 5321 5322 if (vi && IS_DOOMED(vi)) { 5323 rc = ENXIO; 5324 goto done; 5325 } 5326 5327 if (!IS_BUSY(sc)) { 5328 rc = 0; 5329 break; 5330 } 5331 5332 if (!(flags & SLEEP_OK)) { 5333 rc = EBUSY; 5334 goto done; 5335 } 5336 5337 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 5338 rc = EINTR; 5339 goto done; 5340 } 5341 } 5342 5343 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 5344 SET_BUSY(sc); 5345 #ifdef INVARIANTS 5346 sc->last_op = wmesg; 5347 sc->last_op_thr = curthread; 5348 sc->last_op_flags = flags; 5349 #endif 5350 5351 done: 5352 if (!(flags & HOLD_LOCK) || rc) 5353 ADAPTER_UNLOCK(sc); 5354 5355 return (rc); 5356 } 5357 5358 /* 5359 * Tell if_ioctl and if_init that the VI is going away. This is 5360 * special variant of begin_synchronized_op and must be paired with a 5361 * call to end_synchronized_op. 5362 */ 5363 void 5364 doom_vi(struct adapter *sc, struct vi_info *vi) 5365 { 5366 5367 ADAPTER_LOCK(sc); 5368 SET_DOOMED(vi); 5369 wakeup(&sc->flags); 5370 while (IS_BUSY(sc)) 5371 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 5372 SET_BUSY(sc); 5373 #ifdef INVARIANTS 5374 sc->last_op = "t4detach"; 5375 sc->last_op_thr = curthread; 5376 sc->last_op_flags = 0; 5377 #endif 5378 ADAPTER_UNLOCK(sc); 5379 } 5380 5381 /* 5382 * {begin|end}_synchronized_op must be called from the same thread. 5383 */ 5384 void 5385 end_synchronized_op(struct adapter *sc, int flags) 5386 { 5387 5388 if (flags & LOCK_HELD) 5389 ADAPTER_LOCK_ASSERT_OWNED(sc); 5390 else 5391 ADAPTER_LOCK(sc); 5392 5393 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 5394 CLR_BUSY(sc); 5395 wakeup(&sc->flags); 5396 ADAPTER_UNLOCK(sc); 5397 } 5398 5399 static int 5400 cxgbe_init_synchronized(struct vi_info *vi) 5401 { 5402 struct port_info *pi = vi->pi; 5403 struct adapter *sc = pi->adapter; 5404 struct ifnet *ifp = vi->ifp; 5405 int rc = 0, i; 5406 struct sge_txq *txq; 5407 5408 ASSERT_SYNCHRONIZED_OP(sc); 5409 5410 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5411 return (0); /* already running */ 5412 5413 if (!(sc->flags & FULL_INIT_DONE) && 5414 ((rc = adapter_full_init(sc)) != 0)) 5415 return (rc); /* error message displayed already */ 5416 5417 if (!(vi->flags & VI_INIT_DONE) && 5418 ((rc = vi_full_init(vi)) != 0)) 5419 return (rc); /* error message displayed already */ 5420 5421 rc = update_mac_settings(ifp, XGMAC_ALL); 5422 if (rc) 5423 goto done; /* error message displayed already */ 5424 5425 PORT_LOCK(pi); 5426 if (pi->up_vis == 0) { 5427 t4_update_port_info(pi); 5428 fixup_link_config(pi); 5429 build_medialist(pi); 5430 apply_link_config(pi); 5431 } 5432 5433 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 5434 if (rc != 0) { 5435 if_printf(ifp, "enable_vi failed: %d\n", rc); 5436 PORT_UNLOCK(pi); 5437 goto done; 5438 } 5439 5440 /* 5441 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 5442 * if this changes. 5443 */ 5444 5445 for_each_txq(vi, i, txq) { 5446 TXQ_LOCK(txq); 5447 txq->eq.flags |= EQ_ENABLED; 5448 TXQ_UNLOCK(txq); 5449 } 5450 5451 /* 5452 * The first iq of the first port to come up is used for tracing. 5453 */ 5454 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 5455 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 5456 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 5457 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 5458 V_QUEUENUMBER(sc->traceq)); 5459 pi->flags |= HAS_TRACEQ; 5460 } 5461 5462 /* all ok */ 5463 pi->up_vis++; 5464 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5465 5466 if (pi->nvi > 1 || sc->flags & IS_VF) 5467 callout_reset(&vi->tick, hz, vi_tick, vi); 5468 else 5469 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 5470 if (pi->link_cfg.link_ok) 5471 t4_os_link_changed(pi); 5472 PORT_UNLOCK(pi); 5473 done: 5474 if (rc != 0) 5475 cxgbe_uninit_synchronized(vi); 5476 5477 return (rc); 5478 } 5479 5480 /* 5481 * Idempotent. 5482 */ 5483 static int 5484 cxgbe_uninit_synchronized(struct vi_info *vi) 5485 { 5486 struct port_info *pi = vi->pi; 5487 struct adapter *sc = pi->adapter; 5488 struct ifnet *ifp = vi->ifp; 5489 int rc, i; 5490 struct sge_txq *txq; 5491 5492 ASSERT_SYNCHRONIZED_OP(sc); 5493 5494 if (!(vi->flags & VI_INIT_DONE)) { 5495 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5496 KASSERT(0, ("uninited VI is running")); 5497 if_printf(ifp, "uninited VI with running ifnet. " 5498 "vi->flags 0x%016lx, if_flags 0x%08x, " 5499 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 5500 ifp->if_drv_flags); 5501 } 5502 return (0); 5503 } 5504 5505 /* 5506 * Disable the VI so that all its data in either direction is discarded 5507 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 5508 * tick) intact as the TP can deliver negative advice or data that it's 5509 * holding in its RAM (for an offloaded connection) even after the VI is 5510 * disabled. 5511 */ 5512 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 5513 if (rc) { 5514 if_printf(ifp, "disable_vi failed: %d\n", rc); 5515 return (rc); 5516 } 5517 5518 for_each_txq(vi, i, txq) { 5519 TXQ_LOCK(txq); 5520 txq->eq.flags &= ~EQ_ENABLED; 5521 TXQ_UNLOCK(txq); 5522 } 5523 5524 PORT_LOCK(pi); 5525 if (pi->nvi > 1 || sc->flags & IS_VF) 5526 callout_stop(&vi->tick); 5527 else 5528 callout_stop(&pi->tick); 5529 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5530 PORT_UNLOCK(pi); 5531 return (0); 5532 } 5533 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5534 pi->up_vis--; 5535 if (pi->up_vis > 0) { 5536 PORT_UNLOCK(pi); 5537 return (0); 5538 } 5539 5540 pi->link_cfg.link_ok = false; 5541 pi->link_cfg.speed = 0; 5542 pi->link_cfg.link_down_rc = 255; 5543 t4_os_link_changed(pi); 5544 PORT_UNLOCK(pi); 5545 5546 return (0); 5547 } 5548 5549 /* 5550 * It is ok for this function to fail midway and return right away. t4_detach 5551 * will walk the entire sc->irq list and clean up whatever is valid. 5552 */ 5553 int 5554 t4_setup_intr_handlers(struct adapter *sc) 5555 { 5556 int rc, rid, p, q, v; 5557 char s[8]; 5558 struct irq *irq; 5559 struct port_info *pi; 5560 struct vi_info *vi; 5561 struct sge *sge = &sc->sge; 5562 struct sge_rxq *rxq; 5563 #ifdef TCP_OFFLOAD 5564 struct sge_ofld_rxq *ofld_rxq; 5565 #endif 5566 #ifdef DEV_NETMAP 5567 struct sge_nm_rxq *nm_rxq; 5568 #endif 5569 #ifdef RSS 5570 int nbuckets = rss_getnumbuckets(); 5571 #endif 5572 5573 /* 5574 * Setup interrupts. 5575 */ 5576 irq = &sc->irq[0]; 5577 rid = sc->intr_type == INTR_INTX ? 0 : 1; 5578 if (forwarding_intr_to_fwq(sc)) 5579 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 5580 5581 /* Multiple interrupts. */ 5582 if (sc->flags & IS_VF) 5583 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 5584 ("%s: too few intr.", __func__)); 5585 else 5586 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 5587 ("%s: too few intr.", __func__)); 5588 5589 /* The first one is always error intr on PFs */ 5590 if (!(sc->flags & IS_VF)) { 5591 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 5592 if (rc != 0) 5593 return (rc); 5594 irq++; 5595 rid++; 5596 } 5597 5598 /* The second one is always the firmware event queue (first on VFs) */ 5599 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 5600 if (rc != 0) 5601 return (rc); 5602 irq++; 5603 rid++; 5604 5605 for_each_port(sc, p) { 5606 pi = sc->port[p]; 5607 for_each_vi(pi, v, vi) { 5608 vi->first_intr = rid - 1; 5609 5610 if (vi->nnmrxq > 0) { 5611 int n = max(vi->nrxq, vi->nnmrxq); 5612 5613 rxq = &sge->rxq[vi->first_rxq]; 5614 #ifdef DEV_NETMAP 5615 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 5616 #endif 5617 for (q = 0; q < n; q++) { 5618 snprintf(s, sizeof(s), "%x%c%x", p, 5619 'a' + v, q); 5620 if (q < vi->nrxq) 5621 irq->rxq = rxq++; 5622 #ifdef DEV_NETMAP 5623 if (q < vi->nnmrxq) 5624 irq->nm_rxq = nm_rxq++; 5625 5626 if (irq->nm_rxq != NULL && 5627 irq->rxq == NULL) { 5628 /* Netmap rx only */ 5629 rc = t4_alloc_irq(sc, irq, rid, 5630 t4_nm_intr, irq->nm_rxq, s); 5631 } 5632 if (irq->nm_rxq != NULL && 5633 irq->rxq != NULL) { 5634 /* NIC and Netmap rx */ 5635 rc = t4_alloc_irq(sc, irq, rid, 5636 t4_vi_intr, irq, s); 5637 } 5638 #endif 5639 if (irq->rxq != NULL && 5640 irq->nm_rxq == NULL) { 5641 /* NIC rx only */ 5642 rc = t4_alloc_irq(sc, irq, rid, 5643 t4_intr, irq->rxq, s); 5644 } 5645 if (rc != 0) 5646 return (rc); 5647 #ifdef RSS 5648 if (q < vi->nrxq) { 5649 bus_bind_intr(sc->dev, irq->res, 5650 rss_getcpu(q % nbuckets)); 5651 } 5652 #endif 5653 irq++; 5654 rid++; 5655 vi->nintr++; 5656 } 5657 } else { 5658 for_each_rxq(vi, q, rxq) { 5659 snprintf(s, sizeof(s), "%x%c%x", p, 5660 'a' + v, q); 5661 rc = t4_alloc_irq(sc, irq, rid, 5662 t4_intr, rxq, s); 5663 if (rc != 0) 5664 return (rc); 5665 #ifdef RSS 5666 bus_bind_intr(sc->dev, irq->res, 5667 rss_getcpu(q % nbuckets)); 5668 #endif 5669 irq++; 5670 rid++; 5671 vi->nintr++; 5672 } 5673 } 5674 #ifdef TCP_OFFLOAD 5675 for_each_ofld_rxq(vi, q, ofld_rxq) { 5676 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 5677 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 5678 ofld_rxq, s); 5679 if (rc != 0) 5680 return (rc); 5681 irq++; 5682 rid++; 5683 vi->nintr++; 5684 } 5685 #endif 5686 } 5687 } 5688 MPASS(irq == &sc->irq[sc->intr_count]); 5689 5690 return (0); 5691 } 5692 5693 int 5694 adapter_full_init(struct adapter *sc) 5695 { 5696 int rc, i; 5697 #ifdef RSS 5698 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5699 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5700 #endif 5701 5702 ASSERT_SYNCHRONIZED_OP(sc); 5703 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5704 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 5705 ("%s: FULL_INIT_DONE already", __func__)); 5706 5707 /* 5708 * queues that belong to the adapter (not any particular port). 5709 */ 5710 rc = t4_setup_adapter_queues(sc); 5711 if (rc != 0) 5712 goto done; 5713 5714 for (i = 0; i < nitems(sc->tq); i++) { 5715 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 5716 taskqueue_thread_enqueue, &sc->tq[i]); 5717 if (sc->tq[i] == NULL) { 5718 device_printf(sc->dev, 5719 "failed to allocate task queue %d\n", i); 5720 rc = ENOMEM; 5721 goto done; 5722 } 5723 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 5724 device_get_nameunit(sc->dev), i); 5725 } 5726 #ifdef RSS 5727 MPASS(RSS_KEYSIZE == 40); 5728 rss_getkey((void *)&raw_rss_key[0]); 5729 for (i = 0; i < nitems(rss_key); i++) { 5730 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 5731 } 5732 t4_write_rss_key(sc, &rss_key[0], -1, 1); 5733 #endif 5734 5735 if (!(sc->flags & IS_VF)) 5736 t4_intr_enable(sc); 5737 #ifdef KERN_TLS 5738 if (sc->flags & KERN_TLS_OK) 5739 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc, 5740 C_HARDCLOCK); 5741 #endif 5742 sc->flags |= FULL_INIT_DONE; 5743 done: 5744 if (rc != 0) 5745 adapter_full_uninit(sc); 5746 5747 return (rc); 5748 } 5749 5750 int 5751 adapter_full_uninit(struct adapter *sc) 5752 { 5753 int i; 5754 5755 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5756 5757 t4_teardown_adapter_queues(sc); 5758 5759 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 5760 taskqueue_free(sc->tq[i]); 5761 sc->tq[i] = NULL; 5762 } 5763 5764 sc->flags &= ~FULL_INIT_DONE; 5765 5766 return (0); 5767 } 5768 5769 #ifdef RSS 5770 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 5771 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 5772 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 5773 RSS_HASHTYPE_RSS_UDP_IPV6) 5774 5775 /* Translates kernel hash types to hardware. */ 5776 static int 5777 hashconfig_to_hashen(int hashconfig) 5778 { 5779 int hashen = 0; 5780 5781 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 5782 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 5783 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 5784 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 5785 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 5786 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5787 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5788 } 5789 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 5790 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5791 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5792 } 5793 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 5794 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5795 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 5796 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5797 5798 return (hashen); 5799 } 5800 5801 /* Translates hardware hash types to kernel. */ 5802 static int 5803 hashen_to_hashconfig(int hashen) 5804 { 5805 int hashconfig = 0; 5806 5807 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 5808 /* 5809 * If UDP hashing was enabled it must have been enabled for 5810 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 5811 * enabling any 4-tuple hash is nonsense configuration. 5812 */ 5813 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5814 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 5815 5816 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5817 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 5818 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5819 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 5820 } 5821 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5822 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 5823 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5824 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 5825 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 5826 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 5827 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 5828 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 5829 5830 return (hashconfig); 5831 } 5832 #endif 5833 5834 int 5835 vi_full_init(struct vi_info *vi) 5836 { 5837 struct adapter *sc = vi->adapter; 5838 struct ifnet *ifp = vi->ifp; 5839 uint16_t *rss; 5840 struct sge_rxq *rxq; 5841 int rc, i, j; 5842 #ifdef RSS 5843 int nbuckets = rss_getnumbuckets(); 5844 int hashconfig = rss_gethashconfig(); 5845 int extra; 5846 #endif 5847 5848 ASSERT_SYNCHRONIZED_OP(sc); 5849 KASSERT((vi->flags & VI_INIT_DONE) == 0, 5850 ("%s: VI_INIT_DONE already", __func__)); 5851 5852 sysctl_ctx_init(&vi->ctx); 5853 vi->flags |= VI_SYSCTL_CTX; 5854 5855 /* 5856 * Allocate tx/rx/fl queues for this VI. 5857 */ 5858 rc = t4_setup_vi_queues(vi); 5859 if (rc != 0) 5860 goto done; /* error message displayed already */ 5861 5862 /* 5863 * Setup RSS for this VI. Save a copy of the RSS table for later use. 5864 */ 5865 if (vi->nrxq > vi->rss_size) { 5866 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 5867 "some queues will never receive traffic.\n", vi->nrxq, 5868 vi->rss_size); 5869 } else if (vi->rss_size % vi->nrxq) { 5870 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 5871 "expect uneven traffic distribution.\n", vi->nrxq, 5872 vi->rss_size); 5873 } 5874 #ifdef RSS 5875 if (vi->nrxq != nbuckets) { 5876 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5877 "performance will be impacted.\n", vi->nrxq, nbuckets); 5878 } 5879 #endif 5880 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5881 for (i = 0; i < vi->rss_size;) { 5882 #ifdef RSS 5883 j = rss_get_indirection_to_bucket(i); 5884 j %= vi->nrxq; 5885 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5886 rss[i++] = rxq->iq.abs_id; 5887 #else 5888 for_each_rxq(vi, j, rxq) { 5889 rss[i++] = rxq->iq.abs_id; 5890 if (i == vi->rss_size) 5891 break; 5892 } 5893 #endif 5894 } 5895 5896 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5897 vi->rss_size); 5898 if (rc != 0) { 5899 free(rss, M_CXGBE); 5900 if_printf(ifp, "rss_config failed: %d\n", rc); 5901 goto done; 5902 } 5903 5904 #ifdef RSS 5905 vi->hashen = hashconfig_to_hashen(hashconfig); 5906 5907 /* 5908 * We may have had to enable some hashes even though the global config 5909 * wants them disabled. This is a potential problem that must be 5910 * reported to the user. 5911 */ 5912 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 5913 5914 /* 5915 * If we consider only the supported hash types, then the enabled hashes 5916 * are a superset of the requested hashes. In other words, there cannot 5917 * be any supported hash that was requested but not enabled, but there 5918 * can be hashes that were not requested but had to be enabled. 5919 */ 5920 extra &= SUPPORTED_RSS_HASHTYPES; 5921 MPASS((extra & hashconfig) == 0); 5922 5923 if (extra) { 5924 if_printf(ifp, 5925 "global RSS config (0x%x) cannot be accommodated.\n", 5926 hashconfig); 5927 } 5928 if (extra & RSS_HASHTYPE_RSS_IPV4) 5929 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 5930 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 5931 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 5932 if (extra & RSS_HASHTYPE_RSS_IPV6) 5933 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 5934 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 5935 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 5936 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 5937 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 5938 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 5939 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 5940 #else 5941 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 5942 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 5943 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5944 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 5945 #endif 5946 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0); 5947 if (rc != 0) { 5948 free(rss, M_CXGBE); 5949 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 5950 goto done; 5951 } 5952 5953 vi->rss = rss; 5954 vi->flags |= VI_INIT_DONE; 5955 done: 5956 if (rc != 0) 5957 vi_full_uninit(vi); 5958 5959 return (rc); 5960 } 5961 5962 /* 5963 * Idempotent. 5964 */ 5965 int 5966 vi_full_uninit(struct vi_info *vi) 5967 { 5968 struct port_info *pi = vi->pi; 5969 struct adapter *sc = pi->adapter; 5970 int i; 5971 struct sge_rxq *rxq; 5972 struct sge_txq *txq; 5973 #ifdef TCP_OFFLOAD 5974 struct sge_ofld_rxq *ofld_rxq; 5975 #endif 5976 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5977 struct sge_wrq *ofld_txq; 5978 #endif 5979 5980 if (vi->flags & VI_INIT_DONE) { 5981 5982 /* Need to quiesce queues. */ 5983 5984 /* XXX: Only for the first VI? */ 5985 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5986 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5987 5988 for_each_txq(vi, i, txq) { 5989 quiesce_txq(sc, txq); 5990 } 5991 5992 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5993 for_each_ofld_txq(vi, i, ofld_txq) { 5994 quiesce_wrq(sc, ofld_txq); 5995 } 5996 #endif 5997 5998 for_each_rxq(vi, i, rxq) { 5999 quiesce_iq(sc, &rxq->iq); 6000 quiesce_fl(sc, &rxq->fl); 6001 } 6002 6003 #ifdef TCP_OFFLOAD 6004 for_each_ofld_rxq(vi, i, ofld_rxq) { 6005 quiesce_iq(sc, &ofld_rxq->iq); 6006 quiesce_fl(sc, &ofld_rxq->fl); 6007 } 6008 #endif 6009 free(vi->rss, M_CXGBE); 6010 free(vi->nm_rss, M_CXGBE); 6011 } 6012 6013 t4_teardown_vi_queues(vi); 6014 vi->flags &= ~VI_INIT_DONE; 6015 6016 return (0); 6017 } 6018 6019 static void 6020 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 6021 { 6022 struct sge_eq *eq = &txq->eq; 6023 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6024 6025 (void) sc; /* unused */ 6026 6027 #ifdef INVARIANTS 6028 TXQ_LOCK(txq); 6029 MPASS((eq->flags & EQ_ENABLED) == 0); 6030 TXQ_UNLOCK(txq); 6031 #endif 6032 6033 /* Wait for the mp_ring to empty. */ 6034 while (!mp_ring_is_idle(txq->r)) { 6035 mp_ring_check_drainage(txq->r, 4096); 6036 pause("rquiesce", 1); 6037 } 6038 6039 /* Then wait for the hardware to finish. */ 6040 while (spg->cidx != htobe16(eq->pidx)) 6041 pause("equiesce", 1); 6042 6043 /* Finally, wait for the driver to reclaim all descriptors. */ 6044 while (eq->cidx != eq->pidx) 6045 pause("dquiesce", 1); 6046 } 6047 6048 static void 6049 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 6050 { 6051 6052 /* XXXTX */ 6053 } 6054 6055 static void 6056 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 6057 { 6058 (void) sc; /* unused */ 6059 6060 /* Synchronize with the interrupt handler */ 6061 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 6062 pause("iqfree", 1); 6063 } 6064 6065 static void 6066 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 6067 { 6068 mtx_lock(&sc->sfl_lock); 6069 FL_LOCK(fl); 6070 fl->flags |= FL_DOOMED; 6071 FL_UNLOCK(fl); 6072 callout_stop(&sc->sfl_callout); 6073 mtx_unlock(&sc->sfl_lock); 6074 6075 KASSERT((fl->flags & FL_STARVING) == 0, 6076 ("%s: still starving", __func__)); 6077 } 6078 6079 static int 6080 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 6081 driver_intr_t *handler, void *arg, char *name) 6082 { 6083 int rc; 6084 6085 irq->rid = rid; 6086 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 6087 RF_SHAREABLE | RF_ACTIVE); 6088 if (irq->res == NULL) { 6089 device_printf(sc->dev, 6090 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 6091 return (ENOMEM); 6092 } 6093 6094 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 6095 NULL, handler, arg, &irq->tag); 6096 if (rc != 0) { 6097 device_printf(sc->dev, 6098 "failed to setup interrupt for rid %d, name %s: %d\n", 6099 rid, name, rc); 6100 } else if (name) 6101 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 6102 6103 return (rc); 6104 } 6105 6106 static int 6107 t4_free_irq(struct adapter *sc, struct irq *irq) 6108 { 6109 if (irq->tag) 6110 bus_teardown_intr(sc->dev, irq->res, irq->tag); 6111 if (irq->res) 6112 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 6113 6114 bzero(irq, sizeof(*irq)); 6115 6116 return (0); 6117 } 6118 6119 static void 6120 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 6121 { 6122 6123 regs->version = chip_id(sc) | chip_rev(sc) << 10; 6124 t4_get_regs(sc, buf, regs->len); 6125 } 6126 6127 #define A_PL_INDIR_CMD 0x1f8 6128 6129 #define S_PL_AUTOINC 31 6130 #define M_PL_AUTOINC 0x1U 6131 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 6132 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 6133 6134 #define S_PL_VFID 20 6135 #define M_PL_VFID 0xffU 6136 #define V_PL_VFID(x) ((x) << S_PL_VFID) 6137 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 6138 6139 #define S_PL_ADDR 0 6140 #define M_PL_ADDR 0xfffffU 6141 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 6142 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 6143 6144 #define A_PL_INDIR_DATA 0x1fc 6145 6146 static uint64_t 6147 read_vf_stat(struct adapter *sc, u_int vin, int reg) 6148 { 6149 u32 stats[2]; 6150 6151 mtx_assert(&sc->reg_lock, MA_OWNED); 6152 if (sc->flags & IS_VF) { 6153 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 6154 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 6155 } else { 6156 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 6157 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 6158 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 6159 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 6160 } 6161 return (((uint64_t)stats[1]) << 32 | stats[0]); 6162 } 6163 6164 static void 6165 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 6166 { 6167 6168 #define GET_STAT(name) \ 6169 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 6170 6171 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 6172 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 6173 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 6174 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 6175 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 6176 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 6177 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 6178 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 6179 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 6180 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 6181 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 6182 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 6183 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 6184 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 6185 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 6186 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 6187 6188 #undef GET_STAT 6189 } 6190 6191 static void 6192 t4_clr_vi_stats(struct adapter *sc, u_int vin) 6193 { 6194 int reg; 6195 6196 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 6197 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 6198 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 6199 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 6200 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 6201 } 6202 6203 static void 6204 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 6205 { 6206 struct timeval tv; 6207 const struct timeval interval = {0, 250000}; /* 250ms */ 6208 6209 if (!(vi->flags & VI_INIT_DONE)) 6210 return; 6211 6212 getmicrotime(&tv); 6213 timevalsub(&tv, &interval); 6214 if (timevalcmp(&tv, &vi->last_refreshed, <)) 6215 return; 6216 6217 mtx_lock(&sc->reg_lock); 6218 t4_get_vi_stats(sc, vi->vin, &vi->stats); 6219 getmicrotime(&vi->last_refreshed); 6220 mtx_unlock(&sc->reg_lock); 6221 } 6222 6223 static void 6224 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 6225 { 6226 u_int i, v, tnl_cong_drops, chan_map; 6227 struct timeval tv; 6228 const struct timeval interval = {0, 250000}; /* 250ms */ 6229 6230 getmicrotime(&tv); 6231 timevalsub(&tv, &interval); 6232 if (timevalcmp(&tv, &pi->last_refreshed, <)) 6233 return; 6234 6235 tnl_cong_drops = 0; 6236 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 6237 chan_map = pi->rx_e_chan_map; 6238 while (chan_map) { 6239 i = ffs(chan_map) - 1; 6240 mtx_lock(&sc->reg_lock); 6241 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 6242 A_TP_MIB_TNL_CNG_DROP_0 + i); 6243 mtx_unlock(&sc->reg_lock); 6244 tnl_cong_drops += v; 6245 chan_map &= ~(1 << i); 6246 } 6247 pi->tnl_cong_drops = tnl_cong_drops; 6248 getmicrotime(&pi->last_refreshed); 6249 } 6250 6251 static void 6252 cxgbe_tick(void *arg) 6253 { 6254 struct port_info *pi = arg; 6255 struct adapter *sc = pi->adapter; 6256 6257 PORT_LOCK_ASSERT_OWNED(pi); 6258 cxgbe_refresh_stats(sc, pi); 6259 6260 callout_schedule(&pi->tick, hz); 6261 } 6262 6263 void 6264 vi_tick(void *arg) 6265 { 6266 struct vi_info *vi = arg; 6267 struct adapter *sc = vi->adapter; 6268 6269 vi_refresh_stats(sc, vi); 6270 6271 callout_schedule(&vi->tick, hz); 6272 } 6273 6274 /* 6275 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 6276 */ 6277 static char *caps_decoder[] = { 6278 "\20\001IPMI\002NCSI", /* 0: NBM */ 6279 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 6280 "\20\001INGRESS\002EGRESS", /* 2: switch */ 6281 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 6282 "\006HASHFILTER\007ETHOFLD", 6283 "\20\001TOE", /* 4: TOE */ 6284 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 6285 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 6286 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 6287 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 6288 "\007T10DIF" 6289 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 6290 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 6291 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 6292 "\004PO_INITIATOR\005PO_TARGET", 6293 }; 6294 6295 void 6296 t4_sysctls(struct adapter *sc) 6297 { 6298 struct sysctl_ctx_list *ctx; 6299 struct sysctl_oid *oid; 6300 struct sysctl_oid_list *children, *c0; 6301 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 6302 6303 ctx = device_get_sysctl_ctx(sc->dev); 6304 6305 /* 6306 * dev.t4nex.X. 6307 */ 6308 oid = device_get_sysctl_tree(sc->dev); 6309 c0 = children = SYSCTL_CHILDREN(oid); 6310 6311 sc->sc_do_rxcopy = 1; 6312 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 6313 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 6314 6315 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 6316 sc->params.nports, "# of ports"); 6317 6318 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 6319 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, doorbells, 6320 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A", 6321 "available doorbells"); 6322 6323 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 6324 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 6325 6326 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 6327 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6328 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val), 6329 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 6330 6331 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 6332 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6333 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val), 6334 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 6335 6336 t4_sge_sysctls(sc, ctx, children); 6337 6338 sc->lro_timeout = 100; 6339 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 6340 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 6341 6342 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 6343 &sc->debug_flags, 0, "flags to enable runtime debugging"); 6344 6345 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 6346 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 6347 6348 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 6349 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 6350 6351 if (sc->flags & IS_VF) 6352 return; 6353 6354 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 6355 NULL, chip_rev(sc), "chip hardware revision"); 6356 6357 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 6358 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 6359 6360 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 6361 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 6362 6363 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 6364 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 6365 6366 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 6367 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 6368 6369 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 6370 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 6371 6372 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 6373 sc->er_version, 0, "expansion ROM version"); 6374 6375 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 6376 sc->bs_version, 0, "bootstrap firmware version"); 6377 6378 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 6379 NULL, sc->params.scfg_vers, "serial config version"); 6380 6381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 6382 NULL, sc->params.vpd_vers, "VPD version"); 6383 6384 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 6385 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 6386 6387 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 6388 sc->cfcsum, "config file checksum"); 6389 6390 #define SYSCTL_CAP(name, n, text) \ 6391 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 6392 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, caps_decoder[n], \ 6393 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \ 6394 "available " text " capabilities") 6395 6396 SYSCTL_CAP(nbmcaps, 0, "NBM"); 6397 SYSCTL_CAP(linkcaps, 1, "link"); 6398 SYSCTL_CAP(switchcaps, 2, "switch"); 6399 SYSCTL_CAP(niccaps, 3, "NIC"); 6400 SYSCTL_CAP(toecaps, 4, "TCP offload"); 6401 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 6402 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 6403 SYSCTL_CAP(cryptocaps, 7, "crypto"); 6404 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 6405 #undef SYSCTL_CAP 6406 6407 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 6408 NULL, sc->tids.nftids, "number of filters"); 6409 6410 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6411 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6412 sysctl_temperature, "I", "chip temperature (in Celsius)"); 6413 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", 6414 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6415 sysctl_reset_sensor, "I", "reset the chip's temperature sensor."); 6416 6417 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", 6418 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6419 sysctl_loadavg, "A", 6420 "microprocessor load averages (debug firmwares only)"); 6421 6422 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", 6423 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, sysctl_vdd, 6424 "I", "core Vdd (in mV)"); 6425 6426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 6427 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, LOCAL_CPUS, 6428 sysctl_cpus, "A", "local CPUs"); 6429 6430 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 6431 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, INTR_CPUS, 6432 sysctl_cpus, "A", "preferred CPUs for interrupts"); 6433 6434 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 6435 &sc->swintr, 0, "software triggered interrupts"); 6436 6437 /* 6438 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 6439 */ 6440 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 6441 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL, 6442 "logs and miscellaneous information"); 6443 children = SYSCTL_CHILDREN(oid); 6444 6445 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 6446 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6447 sysctl_cctrl, "A", "congestion control"); 6448 6449 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 6450 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6451 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 6452 6453 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 6454 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 1, 6455 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 6456 6457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 6458 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 2, 6459 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 6460 6461 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 6462 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3, 6463 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 6464 6465 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 6466 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4, 6467 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 6468 6469 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 6470 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 5, 6471 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 6472 6473 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 6474 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6475 sysctl_cim_la, "A", "CIM logic analyzer"); 6476 6477 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 6478 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6479 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 6480 6481 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 6482 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6483 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 6484 6485 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 6486 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6487 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 6488 6489 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 6490 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6491 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 6492 6493 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 6494 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6495 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 6496 6497 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 6498 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6499 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 6500 6501 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 6502 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6503 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 6504 6505 if (chip_id(sc) > CHELSIO_T4) { 6506 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 6507 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6508 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 6509 "CIM OBQ 6 (SGE0-RX)"); 6510 6511 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 6512 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6513 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 6514 "CIM OBQ 7 (SGE1-RX)"); 6515 } 6516 6517 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 6518 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6519 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 6520 6521 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 6522 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6523 sysctl_cim_qcfg, "A", "CIM queue configuration"); 6524 6525 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 6526 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6527 sysctl_cpl_stats, "A", "CPL statistics"); 6528 6529 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 6530 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6531 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 6532 6533 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 6534 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6535 sysctl_devlog, "A", "firmware's device log"); 6536 6537 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 6538 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6539 sysctl_fcoe_stats, "A", "FCoE statistics"); 6540 6541 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 6542 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6543 sysctl_hw_sched, "A", "hardware scheduler "); 6544 6545 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 6546 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6547 sysctl_l2t, "A", "hardware L2 table"); 6548 6549 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 6550 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6551 sysctl_smt, "A", "hardware source MAC table"); 6552 6553 #ifdef INET6 6554 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 6555 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6556 sysctl_clip, "A", "active CLIP table entries"); 6557 #endif 6558 6559 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 6560 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6561 sysctl_lb_stats, "A", "loopback statistics"); 6562 6563 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 6564 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6565 sysctl_meminfo, "A", "memory regions"); 6566 6567 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 6568 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6569 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 6570 "A", "MPS TCAM entries"); 6571 6572 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 6573 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6574 sysctl_path_mtus, "A", "path MTUs"); 6575 6576 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 6577 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6578 sysctl_pm_stats, "A", "PM statistics"); 6579 6580 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 6581 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6582 sysctl_rdma_stats, "A", "RDMA statistics"); 6583 6584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 6585 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6586 sysctl_tcp_stats, "A", "TCP statistics"); 6587 6588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 6589 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6590 sysctl_tids, "A", "TID information"); 6591 6592 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 6593 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6594 sysctl_tp_err_stats, "A", "TP error statistics"); 6595 6596 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 6597 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6598 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask"); 6599 6600 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 6601 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6602 sysctl_tp_la, "A", "TP logic analyzer"); 6603 6604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 6605 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6606 sysctl_tx_rate, "A", "Tx rate"); 6607 6608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 6609 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6610 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 6611 6612 if (chip_id(sc) >= CHELSIO_T5) { 6613 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 6614 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6615 sysctl_wcwr_stats, "A", "write combined work requests"); 6616 } 6617 6618 #ifdef KERN_TLS 6619 if (sc->flags & KERN_TLS_OK) { 6620 /* 6621 * dev.t4nex.0.tls. 6622 */ 6623 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", 6624 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters"); 6625 children = SYSCTL_CHILDREN(oid); 6626 6627 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys", 6628 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS " 6629 "keys in work requests (1) or attempt to store TLS keys " 6630 "in card memory."); 6631 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs", 6632 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to combine " 6633 "TCB field updates with TLS record work requests."); 6634 } 6635 #endif 6636 6637 #ifdef TCP_OFFLOAD 6638 if (is_offload(sc)) { 6639 int i; 6640 char s[4]; 6641 6642 /* 6643 * dev.t4nex.X.toe. 6644 */ 6645 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", 6646 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters"); 6647 children = SYSCTL_CHILDREN(oid); 6648 6649 sc->tt.cong_algorithm = -1; 6650 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 6651 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 6652 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 6653 "3 = highspeed)"); 6654 6655 sc->tt.sndbuf = -1; 6656 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 6657 &sc->tt.sndbuf, 0, "hardware send buffer"); 6658 6659 sc->tt.ddp = 0; 6660 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", 6661 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, ""); 6662 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW, 6663 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)"); 6664 6665 sc->tt.rx_coalesce = -1; 6666 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 6667 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 6668 6669 sc->tt.tls = 0; 6670 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT | 6671 CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, sysctl_tls, "I", 6672 "Inline TLS allowed"); 6673 6674 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 6675 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6676 sysctl_tls_rx_ports, "I", 6677 "TCP ports that use inline TLS+TOE RX"); 6678 6679 sc->tt.tx_align = -1; 6680 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 6681 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 6682 6683 sc->tt.tx_zcopy = 0; 6684 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 6685 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 6686 "Enable zero-copy aio_write(2)"); 6687 6688 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 6689 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6690 "cop_managed_offloading", CTLFLAG_RW, 6691 &sc->tt.cop_managed_offloading, 0, 6692 "COP (Connection Offload Policy) controls all TOE offload"); 6693 6694 sc->tt.autorcvbuf_inc = 16 * 1024; 6695 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 6696 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 6697 "autorcvbuf increment"); 6698 6699 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 6700 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6701 sysctl_tp_tick, "A", "TP timer tick (us)"); 6702 6703 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 6704 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 1, 6705 sysctl_tp_tick, "A", "TCP timestamp tick (us)"); 6706 6707 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 6708 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 2, 6709 sysctl_tp_tick, "A", "DACK tick (us)"); 6710 6711 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 6712 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 6713 sysctl_tp_dack_timer, "IU", "DACK timer (us)"); 6714 6715 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 6716 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6717 A_TP_RXT_MIN, sysctl_tp_timer, "LU", 6718 "Minimum retransmit interval (us)"); 6719 6720 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 6721 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6722 A_TP_RXT_MAX, sysctl_tp_timer, "LU", 6723 "Maximum retransmit interval (us)"); 6724 6725 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 6726 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6727 A_TP_PERS_MIN, sysctl_tp_timer, "LU", 6728 "Persist timer min (us)"); 6729 6730 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 6731 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6732 A_TP_PERS_MAX, sysctl_tp_timer, "LU", 6733 "Persist timer max (us)"); 6734 6735 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 6736 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6737 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU", 6738 "Keepalive idle timer (us)"); 6739 6740 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 6741 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6742 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU", 6743 "Keepalive interval timer (us)"); 6744 6745 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 6746 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6747 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)"); 6748 6749 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 6750 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6751 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU", 6752 "FINWAIT2 timer (us)"); 6753 6754 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 6755 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6756 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU", 6757 "Number of SYN retransmissions before abort"); 6758 6759 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 6760 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6761 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU", 6762 "Number of retransmissions before abort"); 6763 6764 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 6765 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6766 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU", 6767 "Number of keepalive probes before abort"); 6768 6769 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 6770 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 6771 "TOE retransmit backoffs"); 6772 children = SYSCTL_CHILDREN(oid); 6773 for (i = 0; i < 16; i++) { 6774 snprintf(s, sizeof(s), "%u", i); 6775 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 6776 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6777 i, sysctl_tp_backoff, "IU", 6778 "TOE retransmit backoff"); 6779 } 6780 } 6781 #endif 6782 } 6783 6784 void 6785 vi_sysctls(struct vi_info *vi) 6786 { 6787 struct sysctl_ctx_list *ctx; 6788 struct sysctl_oid *oid; 6789 struct sysctl_oid_list *children; 6790 6791 ctx = device_get_sysctl_ctx(vi->dev); 6792 6793 /* 6794 * dev.v?(cxgbe|cxl).X. 6795 */ 6796 oid = device_get_sysctl_tree(vi->dev); 6797 children = SYSCTL_CHILDREN(oid); 6798 6799 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 6800 vi->viid, "VI identifer"); 6801 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 6802 &vi->nrxq, 0, "# of rx queues"); 6803 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 6804 &vi->ntxq, 0, "# of tx queues"); 6805 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 6806 &vi->first_rxq, 0, "index of first rx queue"); 6807 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 6808 &vi->first_txq, 0, "index of first tx queue"); 6809 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 6810 vi->rss_base, "start of RSS indirection table"); 6811 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 6812 vi->rss_size, "size of RSS indirection table"); 6813 6814 if (IS_MAIN_VI(vi)) { 6815 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 6816 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0, 6817 sysctl_noflowq, "IU", 6818 "Reserve queue 0 for non-flowid packets"); 6819 } 6820 6821 #ifdef TCP_OFFLOAD 6822 if (vi->nofldrxq != 0) { 6823 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 6824 &vi->nofldrxq, 0, 6825 "# of rx queues for offloaded TCP connections"); 6826 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 6827 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 6828 "index of first TOE rx queue"); 6829 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 6830 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0, 6831 sysctl_holdoff_tmr_idx_ofld, "I", 6832 "holdoff timer index for TOE queues"); 6833 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 6834 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0, 6835 sysctl_holdoff_pktc_idx_ofld, "I", 6836 "holdoff packet counter index for TOE queues"); 6837 } 6838 #endif 6839 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 6840 if (vi->nofldtxq != 0) { 6841 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 6842 &vi->nofldtxq, 0, 6843 "# of tx queues for TOE/ETHOFLD"); 6844 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 6845 CTLFLAG_RD, &vi->first_ofld_txq, 0, 6846 "index of first TOE/ETHOFLD tx queue"); 6847 } 6848 #endif 6849 #ifdef DEV_NETMAP 6850 if (vi->nnmrxq != 0) { 6851 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 6852 &vi->nnmrxq, 0, "# of netmap rx queues"); 6853 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 6854 &vi->nnmtxq, 0, "# of netmap tx queues"); 6855 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 6856 CTLFLAG_RD, &vi->first_nm_rxq, 0, 6857 "index of first netmap rx queue"); 6858 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 6859 CTLFLAG_RD, &vi->first_nm_txq, 0, 6860 "index of first netmap tx queue"); 6861 } 6862 #endif 6863 6864 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 6865 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0, 6866 sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); 6867 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 6868 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0, 6869 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); 6870 6871 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 6872 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0, 6873 sysctl_qsize_rxq, "I", "rx queue size"); 6874 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 6875 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0, 6876 sysctl_qsize_txq, "I", "tx queue size"); 6877 } 6878 6879 static void 6880 cxgbe_sysctls(struct port_info *pi) 6881 { 6882 struct sysctl_ctx_list *ctx; 6883 struct sysctl_oid *oid; 6884 struct sysctl_oid_list *children, *children2; 6885 struct adapter *sc = pi->adapter; 6886 int i; 6887 char name[16]; 6888 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"}; 6889 6890 ctx = device_get_sysctl_ctx(pi->dev); 6891 6892 /* 6893 * dev.cxgbe.X. 6894 */ 6895 oid = device_get_sysctl_tree(pi->dev); 6896 children = SYSCTL_CHILDREN(oid); 6897 6898 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", 6899 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, pi, 0, 6900 sysctl_linkdnrc, "A", "reason why link is down"); 6901 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 6902 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6903 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, pi, 0, 6904 sysctl_btphy, "I", "PHY temperature (in Celsius)"); 6905 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 6906 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, pi, 1, 6907 sysctl_btphy, "I", "PHY firmware version"); 6908 } 6909 6910 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 6911 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_NEEDGIANT, pi, 0, 6912 sysctl_pause_settings, "A", 6913 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 6914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 6915 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_NEEDGIANT, pi, 0, 6916 sysctl_fec, "A", 6917 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)"); 6918 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec", 6919 CTLTYPE_STRING | CTLFLAG_NEEDGIANT, pi, 0, sysctl_module_fec, "A", 6920 "FEC recommended by the cable/transceiver"); 6921 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 6922 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, pi, 0, 6923 sysctl_autoneg, "I", 6924 "autonegotiation (-1 = not supported)"); 6925 6926 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD, 6927 &pi->link_cfg.pcaps, 0, "port capabilities"); 6928 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD, 6929 &pi->link_cfg.acaps, 0, "advertised capabilities"); 6930 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD, 6931 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities"); 6932 6933 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 6934 port_top_speed(pi), "max speed (in Gbps)"); 6935 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 6936 pi->mps_bg_map, "MPS buffer group map"); 6937 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 6938 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 6939 6940 if (sc->flags & IS_VF) 6941 return; 6942 6943 /* 6944 * dev.(cxgbe|cxl).X.tc. 6945 */ 6946 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", 6947 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 6948 "Tx scheduler traffic classes (cl_rl)"); 6949 children2 = SYSCTL_CHILDREN(oid); 6950 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 6951 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 6952 "pktsize for per-flow cl-rl (0 means up to the driver )"); 6953 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 6954 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 6955 "burstsize for per-flow cl-rl (0 means up to the driver)"); 6956 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 6957 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 6958 6959 snprintf(name, sizeof(name), "%d", i); 6960 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 6961 SYSCTL_CHILDREN(oid), OID_AUTO, name, 6962 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class")); 6963 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 6964 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, tc_flags, 6965 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags"); 6966 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 6967 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 6968 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 6969 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 6970 (pi->port_id << 16) | i, sysctl_tc_params, "A", 6971 "traffic class parameters"); 6972 } 6973 6974 /* 6975 * dev.cxgbe.X.stats. 6976 */ 6977 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 6978 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics"); 6979 children = SYSCTL_CHILDREN(oid); 6980 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 6981 &pi->tx_parse_error, 0, 6982 "# of tx packets with invalid length or # of segments"); 6983 6984 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 6985 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 6986 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, reg, \ 6987 sysctl_handle_t4_reg64, "QU", desc) 6988 6989 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 6990 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 6991 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 6992 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 6993 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 6994 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 6995 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 6996 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 6997 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 6998 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 6999 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 7000 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 7001 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 7002 "# of tx frames in this range", 7003 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 7004 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 7005 "# of tx frames in this range", 7006 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 7007 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 7008 "# of tx frames in this range", 7009 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 7010 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 7011 "# of tx frames in this range", 7012 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 7013 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 7014 "# of tx frames in this range", 7015 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 7016 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 7017 "# of tx frames in this range", 7018 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 7019 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 7020 "# of tx frames in this range", 7021 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 7022 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 7023 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 7024 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 7025 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 7026 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 7027 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 7028 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 7029 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 7030 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 7031 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 7032 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 7033 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 7034 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 7035 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 7036 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 7037 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 7038 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 7039 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 7040 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 7041 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 7042 7043 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 7044 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 7045 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 7046 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 7047 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 7048 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 7049 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 7050 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 7051 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 7052 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 7053 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 7054 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 7055 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 7056 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 7057 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 7058 "# of frames received with bad FCS", 7059 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 7060 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 7061 "# of frames received with length error", 7062 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 7063 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 7064 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 7065 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 7066 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 7067 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 7068 "# of rx frames in this range", 7069 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 7070 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 7071 "# of rx frames in this range", 7072 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 7073 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 7074 "# of rx frames in this range", 7075 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 7076 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 7077 "# of rx frames in this range", 7078 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 7079 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 7080 "# of rx frames in this range", 7081 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 7082 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 7083 "# of rx frames in this range", 7084 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 7085 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 7086 "# of rx frames in this range", 7087 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 7088 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 7089 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 7090 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 7091 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 7092 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 7093 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 7094 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 7095 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 7096 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 7097 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 7098 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 7099 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 7100 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 7101 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 7102 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 7103 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 7104 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 7105 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 7106 7107 #undef SYSCTL_ADD_T4_REG64 7108 7109 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 7110 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 7111 &pi->stats.name, desc) 7112 7113 /* We get these from port_stats and they may be stale by up to 1s */ 7114 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 7115 "# drops due to buffer-group 0 overflows"); 7116 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 7117 "# drops due to buffer-group 1 overflows"); 7118 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 7119 "# drops due to buffer-group 2 overflows"); 7120 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 7121 "# drops due to buffer-group 3 overflows"); 7122 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 7123 "# of buffer-group 0 truncated packets"); 7124 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 7125 "# of buffer-group 1 truncated packets"); 7126 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 7127 "# of buffer-group 2 truncated packets"); 7128 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 7129 "# of buffer-group 3 truncated packets"); 7130 7131 #undef SYSCTL_ADD_T4_PORTSTAT 7132 7133 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_toe_tls_records", 7134 CTLFLAG_RD, &pi->tx_toe_tls_records, 7135 "# of TOE TLS records transmitted"); 7136 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_toe_tls_octets", 7137 CTLFLAG_RD, &pi->tx_toe_tls_octets, 7138 "# of payload octets in transmitted TOE TLS records"); 7139 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_toe_tls_records", 7140 CTLFLAG_RD, &pi->rx_toe_tls_records, 7141 "# of TOE TLS records received"); 7142 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_toe_tls_octets", 7143 CTLFLAG_RD, &pi->rx_toe_tls_octets, 7144 "# of payload octets in received TOE TLS records"); 7145 } 7146 7147 static int 7148 sysctl_int_array(SYSCTL_HANDLER_ARGS) 7149 { 7150 int rc, *i, space = 0; 7151 struct sbuf sb; 7152 7153 sbuf_new_for_sysctl(&sb, NULL, 64, req); 7154 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 7155 if (space) 7156 sbuf_printf(&sb, " "); 7157 sbuf_printf(&sb, "%d", *i); 7158 space = 1; 7159 } 7160 rc = sbuf_finish(&sb); 7161 sbuf_delete(&sb); 7162 return (rc); 7163 } 7164 7165 static int 7166 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 7167 { 7168 int rc; 7169 struct sbuf *sb; 7170 7171 rc = sysctl_wire_old_buffer(req, 0); 7172 if (rc != 0) 7173 return(rc); 7174 7175 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7176 if (sb == NULL) 7177 return (ENOMEM); 7178 7179 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 7180 rc = sbuf_finish(sb); 7181 sbuf_delete(sb); 7182 7183 return (rc); 7184 } 7185 7186 static int 7187 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 7188 { 7189 int rc; 7190 struct sbuf *sb; 7191 7192 rc = sysctl_wire_old_buffer(req, 0); 7193 if (rc != 0) 7194 return(rc); 7195 7196 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7197 if (sb == NULL) 7198 return (ENOMEM); 7199 7200 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 7201 rc = sbuf_finish(sb); 7202 sbuf_delete(sb); 7203 7204 return (rc); 7205 } 7206 7207 static int 7208 sysctl_btphy(SYSCTL_HANDLER_ARGS) 7209 { 7210 struct port_info *pi = arg1; 7211 int op = arg2; 7212 struct adapter *sc = pi->adapter; 7213 u_int v; 7214 int rc; 7215 7216 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 7217 if (rc) 7218 return (rc); 7219 /* XXX: magic numbers */ 7220 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 7221 &v); 7222 end_synchronized_op(sc, 0); 7223 if (rc) 7224 return (rc); 7225 if (op == 0) 7226 v /= 256; 7227 7228 rc = sysctl_handle_int(oidp, &v, 0, req); 7229 return (rc); 7230 } 7231 7232 static int 7233 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 7234 { 7235 struct vi_info *vi = arg1; 7236 int rc, val; 7237 7238 val = vi->rsrv_noflowq; 7239 rc = sysctl_handle_int(oidp, &val, 0, req); 7240 if (rc != 0 || req->newptr == NULL) 7241 return (rc); 7242 7243 if ((val >= 1) && (vi->ntxq > 1)) 7244 vi->rsrv_noflowq = 1; 7245 else 7246 vi->rsrv_noflowq = 0; 7247 7248 return (rc); 7249 } 7250 7251 static int 7252 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 7253 { 7254 struct vi_info *vi = arg1; 7255 struct adapter *sc = vi->adapter; 7256 int idx, rc, i; 7257 struct sge_rxq *rxq; 7258 uint8_t v; 7259 7260 idx = vi->tmr_idx; 7261 7262 rc = sysctl_handle_int(oidp, &idx, 0, req); 7263 if (rc != 0 || req->newptr == NULL) 7264 return (rc); 7265 7266 if (idx < 0 || idx >= SGE_NTIMERS) 7267 return (EINVAL); 7268 7269 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 7270 "t4tmr"); 7271 if (rc) 7272 return (rc); 7273 7274 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 7275 for_each_rxq(vi, i, rxq) { 7276 #ifdef atomic_store_rel_8 7277 atomic_store_rel_8(&rxq->iq.intr_params, v); 7278 #else 7279 rxq->iq.intr_params = v; 7280 #endif 7281 } 7282 vi->tmr_idx = idx; 7283 7284 end_synchronized_op(sc, LOCK_HELD); 7285 return (0); 7286 } 7287 7288 static int 7289 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 7290 { 7291 struct vi_info *vi = arg1; 7292 struct adapter *sc = vi->adapter; 7293 int idx, rc; 7294 7295 idx = vi->pktc_idx; 7296 7297 rc = sysctl_handle_int(oidp, &idx, 0, req); 7298 if (rc != 0 || req->newptr == NULL) 7299 return (rc); 7300 7301 if (idx < -1 || idx >= SGE_NCOUNTERS) 7302 return (EINVAL); 7303 7304 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 7305 "t4pktc"); 7306 if (rc) 7307 return (rc); 7308 7309 if (vi->flags & VI_INIT_DONE) 7310 rc = EBUSY; /* cannot be changed once the queues are created */ 7311 else 7312 vi->pktc_idx = idx; 7313 7314 end_synchronized_op(sc, LOCK_HELD); 7315 return (rc); 7316 } 7317 7318 static int 7319 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 7320 { 7321 struct vi_info *vi = arg1; 7322 struct adapter *sc = vi->adapter; 7323 int qsize, rc; 7324 7325 qsize = vi->qsize_rxq; 7326 7327 rc = sysctl_handle_int(oidp, &qsize, 0, req); 7328 if (rc != 0 || req->newptr == NULL) 7329 return (rc); 7330 7331 if (qsize < 128 || (qsize & 7)) 7332 return (EINVAL); 7333 7334 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 7335 "t4rxqs"); 7336 if (rc) 7337 return (rc); 7338 7339 if (vi->flags & VI_INIT_DONE) 7340 rc = EBUSY; /* cannot be changed once the queues are created */ 7341 else 7342 vi->qsize_rxq = qsize; 7343 7344 end_synchronized_op(sc, LOCK_HELD); 7345 return (rc); 7346 } 7347 7348 static int 7349 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 7350 { 7351 struct vi_info *vi = arg1; 7352 struct adapter *sc = vi->adapter; 7353 int qsize, rc; 7354 7355 qsize = vi->qsize_txq; 7356 7357 rc = sysctl_handle_int(oidp, &qsize, 0, req); 7358 if (rc != 0 || req->newptr == NULL) 7359 return (rc); 7360 7361 if (qsize < 128 || qsize > 65536) 7362 return (EINVAL); 7363 7364 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 7365 "t4txqs"); 7366 if (rc) 7367 return (rc); 7368 7369 if (vi->flags & VI_INIT_DONE) 7370 rc = EBUSY; /* cannot be changed once the queues are created */ 7371 else 7372 vi->qsize_txq = qsize; 7373 7374 end_synchronized_op(sc, LOCK_HELD); 7375 return (rc); 7376 } 7377 7378 static int 7379 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 7380 { 7381 struct port_info *pi = arg1; 7382 struct adapter *sc = pi->adapter; 7383 struct link_config *lc = &pi->link_cfg; 7384 int rc; 7385 7386 if (req->newptr == NULL) { 7387 struct sbuf *sb; 7388 static char *bits = "\20\1RX\2TX\3AUTO"; 7389 7390 rc = sysctl_wire_old_buffer(req, 0); 7391 if (rc != 0) 7392 return(rc); 7393 7394 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7395 if (sb == NULL) 7396 return (ENOMEM); 7397 7398 if (lc->link_ok) { 7399 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 7400 (lc->requested_fc & PAUSE_AUTONEG), bits); 7401 } else { 7402 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 7403 PAUSE_RX | PAUSE_AUTONEG), bits); 7404 } 7405 rc = sbuf_finish(sb); 7406 sbuf_delete(sb); 7407 } else { 7408 char s[2]; 7409 int n; 7410 7411 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 7412 PAUSE_AUTONEG)); 7413 s[1] = 0; 7414 7415 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 7416 if (rc != 0) 7417 return(rc); 7418 7419 if (s[1] != 0) 7420 return (EINVAL); 7421 if (s[0] < '0' || s[0] > '9') 7422 return (EINVAL); /* not a number */ 7423 n = s[0] - '0'; 7424 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 7425 return (EINVAL); /* some other bit is set too */ 7426 7427 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7428 "t4PAUSE"); 7429 if (rc) 7430 return (rc); 7431 PORT_LOCK(pi); 7432 lc->requested_fc = n; 7433 fixup_link_config(pi); 7434 if (pi->up_vis > 0) 7435 rc = apply_link_config(pi); 7436 set_current_media(pi); 7437 PORT_UNLOCK(pi); 7438 end_synchronized_op(sc, 0); 7439 } 7440 7441 return (rc); 7442 } 7443 7444 static int 7445 sysctl_fec(SYSCTL_HANDLER_ARGS) 7446 { 7447 struct port_info *pi = arg1; 7448 struct adapter *sc = pi->adapter; 7449 struct link_config *lc = &pi->link_cfg; 7450 int rc; 7451 int8_t old; 7452 7453 if (req->newptr == NULL) { 7454 struct sbuf *sb; 7455 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2" 7456 "\5RSVD3\6auto\7module"; 7457 7458 rc = sysctl_wire_old_buffer(req, 0); 7459 if (rc != 0) 7460 return(rc); 7461 7462 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7463 if (sb == NULL) 7464 return (ENOMEM); 7465 7466 /* 7467 * Display the requested_fec when the link is down -- the actual 7468 * FEC makes sense only when the link is up. 7469 */ 7470 if (lc->link_ok) { 7471 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) | 7472 (lc->requested_fec & (FEC_AUTO | FEC_MODULE)), 7473 bits); 7474 } else { 7475 sbuf_printf(sb, "%b", lc->requested_fec, bits); 7476 } 7477 rc = sbuf_finish(sb); 7478 sbuf_delete(sb); 7479 } else { 7480 char s[8]; 7481 int n; 7482 7483 snprintf(s, sizeof(s), "%d", 7484 lc->requested_fec == FEC_AUTO ? -1 : 7485 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE)); 7486 7487 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 7488 if (rc != 0) 7489 return(rc); 7490 7491 n = strtol(&s[0], NULL, 0); 7492 if (n < 0 || n & FEC_AUTO) 7493 n = FEC_AUTO; 7494 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE)) 7495 return (EINVAL);/* some other bit is set too */ 7496 7497 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7498 "t4fec"); 7499 if (rc) 7500 return (rc); 7501 PORT_LOCK(pi); 7502 old = lc->requested_fec; 7503 if (n == FEC_AUTO) 7504 lc->requested_fec = FEC_AUTO; 7505 else if (n == 0 || n == FEC_NONE) 7506 lc->requested_fec = FEC_NONE; 7507 else { 7508 if ((lc->pcaps | 7509 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) != 7510 lc->pcaps) { 7511 rc = ENOTSUP; 7512 goto done; 7513 } 7514 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC | 7515 FEC_MODULE); 7516 } 7517 fixup_link_config(pi); 7518 if (pi->up_vis > 0) { 7519 rc = apply_link_config(pi); 7520 if (rc != 0) { 7521 lc->requested_fec = old; 7522 if (rc == FW_EPROTO) 7523 rc = ENOTSUP; 7524 } 7525 } 7526 done: 7527 PORT_UNLOCK(pi); 7528 end_synchronized_op(sc, 0); 7529 } 7530 7531 return (rc); 7532 } 7533 7534 static int 7535 sysctl_module_fec(SYSCTL_HANDLER_ARGS) 7536 { 7537 struct port_info *pi = arg1; 7538 struct adapter *sc = pi->adapter; 7539 struct link_config *lc = &pi->link_cfg; 7540 int rc; 7541 int8_t fec; 7542 struct sbuf *sb; 7543 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3"; 7544 7545 rc = sysctl_wire_old_buffer(req, 0); 7546 if (rc != 0) 7547 return (rc); 7548 7549 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7550 if (sb == NULL) 7551 return (ENOMEM); 7552 7553 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) 7554 return (EBUSY); 7555 PORT_LOCK(pi); 7556 if (pi->up_vis == 0) { 7557 /* 7558 * If all the interfaces are administratively down the firmware 7559 * does not report transceiver changes. Refresh port info here. 7560 * This is the only reason we have a synchronized op in this 7561 * function. Just PORT_LOCK would have been enough otherwise. 7562 */ 7563 t4_update_port_info(pi); 7564 } 7565 7566 fec = lc->fec_hint; 7567 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE || 7568 !fec_supported(lc->pcaps)) { 7569 sbuf_printf(sb, "n/a"); 7570 } else { 7571 if (fec == 0) 7572 fec = FEC_NONE; 7573 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits); 7574 } 7575 rc = sbuf_finish(sb); 7576 sbuf_delete(sb); 7577 7578 PORT_UNLOCK(pi); 7579 end_synchronized_op(sc, 0); 7580 7581 return (rc); 7582 } 7583 7584 static int 7585 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 7586 { 7587 struct port_info *pi = arg1; 7588 struct adapter *sc = pi->adapter; 7589 struct link_config *lc = &pi->link_cfg; 7590 int rc, val; 7591 7592 if (lc->pcaps & FW_PORT_CAP32_ANEG) 7593 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 7594 else 7595 val = -1; 7596 rc = sysctl_handle_int(oidp, &val, 0, req); 7597 if (rc != 0 || req->newptr == NULL) 7598 return (rc); 7599 if (val == 0) 7600 val = AUTONEG_DISABLE; 7601 else if (val == 1) 7602 val = AUTONEG_ENABLE; 7603 else 7604 val = AUTONEG_AUTO; 7605 7606 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7607 "t4aneg"); 7608 if (rc) 7609 return (rc); 7610 PORT_LOCK(pi); 7611 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 7612 rc = ENOTSUP; 7613 goto done; 7614 } 7615 lc->requested_aneg = val; 7616 fixup_link_config(pi); 7617 if (pi->up_vis > 0) 7618 rc = apply_link_config(pi); 7619 set_current_media(pi); 7620 done: 7621 PORT_UNLOCK(pi); 7622 end_synchronized_op(sc, 0); 7623 return (rc); 7624 } 7625 7626 static int 7627 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 7628 { 7629 struct adapter *sc = arg1; 7630 int reg = arg2; 7631 uint64_t val; 7632 7633 val = t4_read_reg64(sc, reg); 7634 7635 return (sysctl_handle_64(oidp, &val, 0, req)); 7636 } 7637 7638 static int 7639 sysctl_temperature(SYSCTL_HANDLER_ARGS) 7640 { 7641 struct adapter *sc = arg1; 7642 int rc, t; 7643 uint32_t param, val; 7644 7645 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 7646 if (rc) 7647 return (rc); 7648 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7649 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7650 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 7651 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7652 end_synchronized_op(sc, 0); 7653 if (rc) 7654 return (rc); 7655 7656 /* unknown is returned as 0 but we display -1 in that case */ 7657 t = val == 0 ? -1 : val; 7658 7659 rc = sysctl_handle_int(oidp, &t, 0, req); 7660 return (rc); 7661 } 7662 7663 static int 7664 sysctl_vdd(SYSCTL_HANDLER_ARGS) 7665 { 7666 struct adapter *sc = arg1; 7667 int rc; 7668 uint32_t param, val; 7669 7670 if (sc->params.core_vdd == 0) { 7671 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7672 "t4vdd"); 7673 if (rc) 7674 return (rc); 7675 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7676 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7677 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 7678 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7679 end_synchronized_op(sc, 0); 7680 if (rc) 7681 return (rc); 7682 sc->params.core_vdd = val; 7683 } 7684 7685 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req)); 7686 } 7687 7688 static int 7689 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS) 7690 { 7691 struct adapter *sc = arg1; 7692 int rc, v; 7693 uint32_t param, val; 7694 7695 v = sc->sensor_resets; 7696 rc = sysctl_handle_int(oidp, &v, 0, req); 7697 if (rc != 0 || req->newptr == NULL || v <= 0) 7698 return (rc); 7699 7700 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) || 7701 chip_id(sc) < CHELSIO_T5) 7702 return (ENOTSUP); 7703 7704 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst"); 7705 if (rc) 7706 return (rc); 7707 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7708 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7709 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR)); 7710 val = 1; 7711 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7712 end_synchronized_op(sc, 0); 7713 if (rc == 0) 7714 sc->sensor_resets++; 7715 return (rc); 7716 } 7717 7718 static int 7719 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 7720 { 7721 struct adapter *sc = arg1; 7722 struct sbuf *sb; 7723 int rc; 7724 uint32_t param, val; 7725 7726 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 7727 if (rc) 7728 return (rc); 7729 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7730 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 7731 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7732 end_synchronized_op(sc, 0); 7733 if (rc) 7734 return (rc); 7735 7736 rc = sysctl_wire_old_buffer(req, 0); 7737 if (rc != 0) 7738 return (rc); 7739 7740 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7741 if (sb == NULL) 7742 return (ENOMEM); 7743 7744 if (val == 0xffffffff) { 7745 /* Only debug and custom firmwares report load averages. */ 7746 sbuf_printf(sb, "not available"); 7747 } else { 7748 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 7749 (val >> 16) & 0xff); 7750 } 7751 rc = sbuf_finish(sb); 7752 sbuf_delete(sb); 7753 7754 return (rc); 7755 } 7756 7757 static int 7758 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 7759 { 7760 struct adapter *sc = arg1; 7761 struct sbuf *sb; 7762 int rc, i; 7763 uint16_t incr[NMTUS][NCCTRL_WIN]; 7764 static const char *dec_fac[] = { 7765 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 7766 "0.9375" 7767 }; 7768 7769 rc = sysctl_wire_old_buffer(req, 0); 7770 if (rc != 0) 7771 return (rc); 7772 7773 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7774 if (sb == NULL) 7775 return (ENOMEM); 7776 7777 t4_read_cong_tbl(sc, incr); 7778 7779 for (i = 0; i < NCCTRL_WIN; ++i) { 7780 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 7781 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 7782 incr[5][i], incr[6][i], incr[7][i]); 7783 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 7784 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 7785 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 7786 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 7787 } 7788 7789 rc = sbuf_finish(sb); 7790 sbuf_delete(sb); 7791 7792 return (rc); 7793 } 7794 7795 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 7796 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 7797 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 7798 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 7799 }; 7800 7801 static int 7802 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 7803 { 7804 struct adapter *sc = arg1; 7805 struct sbuf *sb; 7806 int rc, i, n, qid = arg2; 7807 uint32_t *buf, *p; 7808 char *qtype; 7809 u_int cim_num_obq = sc->chip_params->cim_num_obq; 7810 7811 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 7812 ("%s: bad qid %d\n", __func__, qid)); 7813 7814 if (qid < CIM_NUM_IBQ) { 7815 /* inbound queue */ 7816 qtype = "IBQ"; 7817 n = 4 * CIM_IBQ_SIZE; 7818 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7819 rc = t4_read_cim_ibq(sc, qid, buf, n); 7820 } else { 7821 /* outbound queue */ 7822 qtype = "OBQ"; 7823 qid -= CIM_NUM_IBQ; 7824 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 7825 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7826 rc = t4_read_cim_obq(sc, qid, buf, n); 7827 } 7828 7829 if (rc < 0) { 7830 rc = -rc; 7831 goto done; 7832 } 7833 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 7834 7835 rc = sysctl_wire_old_buffer(req, 0); 7836 if (rc != 0) 7837 goto done; 7838 7839 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7840 if (sb == NULL) { 7841 rc = ENOMEM; 7842 goto done; 7843 } 7844 7845 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 7846 for (i = 0, p = buf; i < n; i += 16, p += 4) 7847 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 7848 p[2], p[3]); 7849 7850 rc = sbuf_finish(sb); 7851 sbuf_delete(sb); 7852 done: 7853 free(buf, M_CXGBE); 7854 return (rc); 7855 } 7856 7857 static void 7858 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7859 { 7860 uint32_t *p; 7861 7862 sbuf_printf(sb, "Status Data PC%s", 7863 cfg & F_UPDBGLACAPTPCONLY ? "" : 7864 " LS0Stat LS0Addr LS0Data"); 7865 7866 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 7867 if (cfg & F_UPDBGLACAPTPCONLY) { 7868 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 7869 p[6], p[7]); 7870 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 7871 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 7872 p[4] & 0xff, p[5] >> 8); 7873 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 7874 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7875 p[1] & 0xf, p[2] >> 4); 7876 } else { 7877 sbuf_printf(sb, 7878 "\n %02x %x%07x %x%07x %08x %08x " 7879 "%08x%08x%08x%08x", 7880 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7881 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 7882 p[6], p[7]); 7883 } 7884 } 7885 } 7886 7887 static void 7888 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7889 { 7890 uint32_t *p; 7891 7892 sbuf_printf(sb, "Status Inst Data PC%s", 7893 cfg & F_UPDBGLACAPTPCONLY ? "" : 7894 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 7895 7896 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 7897 if (cfg & F_UPDBGLACAPTPCONLY) { 7898 sbuf_printf(sb, "\n %02x %08x %08x %08x", 7899 p[3] & 0xff, p[2], p[1], p[0]); 7900 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 7901 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 7902 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 7903 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 7904 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 7905 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 7906 p[6] >> 16); 7907 } else { 7908 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 7909 "%08x %08x %08x %08x %08x %08x", 7910 (p[9] >> 16) & 0xff, 7911 p[9] & 0xffff, p[8] >> 16, 7912 p[8] & 0xffff, p[7] >> 16, 7913 p[7] & 0xffff, p[6] >> 16, 7914 p[2], p[1], p[0], p[5], p[4], p[3]); 7915 } 7916 } 7917 } 7918 7919 static int 7920 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 7921 { 7922 uint32_t cfg, *buf; 7923 int rc; 7924 7925 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7926 if (rc != 0) 7927 return (rc); 7928 7929 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7930 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7931 M_ZERO | flags); 7932 if (buf == NULL) 7933 return (ENOMEM); 7934 7935 rc = -t4_cim_read_la(sc, buf, NULL); 7936 if (rc != 0) 7937 goto done; 7938 if (chip_id(sc) < CHELSIO_T6) 7939 sbuf_cim_la4(sc, sb, buf, cfg); 7940 else 7941 sbuf_cim_la6(sc, sb, buf, cfg); 7942 7943 done: 7944 free(buf, M_CXGBE); 7945 return (rc); 7946 } 7947 7948 static int 7949 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 7950 { 7951 struct adapter *sc = arg1; 7952 struct sbuf *sb; 7953 int rc; 7954 7955 rc = sysctl_wire_old_buffer(req, 0); 7956 if (rc != 0) 7957 return (rc); 7958 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7959 if (sb == NULL) 7960 return (ENOMEM); 7961 7962 rc = sbuf_cim_la(sc, sb, M_WAITOK); 7963 if (rc == 0) 7964 rc = sbuf_finish(sb); 7965 sbuf_delete(sb); 7966 return (rc); 7967 } 7968 7969 bool 7970 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose) 7971 { 7972 struct sbuf sb; 7973 int rc; 7974 7975 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7976 return (false); 7977 rc = sbuf_cim_la(sc, &sb, M_NOWAIT); 7978 if (rc == 0) { 7979 rc = sbuf_finish(&sb); 7980 if (rc == 0) { 7981 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s", 7982 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7983 } 7984 } 7985 sbuf_delete(&sb); 7986 return (false); 7987 } 7988 7989 static int 7990 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 7991 { 7992 struct adapter *sc = arg1; 7993 u_int i; 7994 struct sbuf *sb; 7995 uint32_t *buf, *p; 7996 int rc; 7997 7998 rc = sysctl_wire_old_buffer(req, 0); 7999 if (rc != 0) 8000 return (rc); 8001 8002 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8003 if (sb == NULL) 8004 return (ENOMEM); 8005 8006 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 8007 M_ZERO | M_WAITOK); 8008 8009 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 8010 p = buf; 8011 8012 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 8013 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 8014 p[1], p[0]); 8015 } 8016 8017 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 8018 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 8019 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 8020 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 8021 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 8022 (p[1] >> 2) | ((p[2] & 3) << 30), 8023 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 8024 p[0] & 1); 8025 } 8026 8027 rc = sbuf_finish(sb); 8028 sbuf_delete(sb); 8029 free(buf, M_CXGBE); 8030 return (rc); 8031 } 8032 8033 static int 8034 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 8035 { 8036 struct adapter *sc = arg1; 8037 u_int i; 8038 struct sbuf *sb; 8039 uint32_t *buf, *p; 8040 int rc; 8041 8042 rc = sysctl_wire_old_buffer(req, 0); 8043 if (rc != 0) 8044 return (rc); 8045 8046 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8047 if (sb == NULL) 8048 return (ENOMEM); 8049 8050 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 8051 M_ZERO | M_WAITOK); 8052 8053 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 8054 p = buf; 8055 8056 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 8057 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 8058 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 8059 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 8060 p[4], p[3], p[2], p[1], p[0]); 8061 } 8062 8063 sbuf_printf(sb, "\n\nCntl ID Data"); 8064 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 8065 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 8066 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 8067 } 8068 8069 rc = sbuf_finish(sb); 8070 sbuf_delete(sb); 8071 free(buf, M_CXGBE); 8072 return (rc); 8073 } 8074 8075 static int 8076 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 8077 { 8078 struct adapter *sc = arg1; 8079 struct sbuf *sb; 8080 int rc, i; 8081 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 8082 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 8083 uint16_t thres[CIM_NUM_IBQ]; 8084 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 8085 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 8086 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 8087 8088 cim_num_obq = sc->chip_params->cim_num_obq; 8089 if (is_t4(sc)) { 8090 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 8091 obq_rdaddr = A_UP_OBQ_0_REALADDR; 8092 } else { 8093 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 8094 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 8095 } 8096 nq = CIM_NUM_IBQ + cim_num_obq; 8097 8098 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 8099 if (rc == 0) 8100 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 8101 if (rc != 0) 8102 return (rc); 8103 8104 t4_read_cimq_cfg(sc, base, size, thres); 8105 8106 rc = sysctl_wire_old_buffer(req, 0); 8107 if (rc != 0) 8108 return (rc); 8109 8110 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 8111 if (sb == NULL) 8112 return (ENOMEM); 8113 8114 sbuf_printf(sb, 8115 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 8116 8117 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 8118 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 8119 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 8120 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 8121 G_QUEREMFLITS(p[2]) * 16); 8122 for ( ; i < nq; i++, p += 4, wr += 2) 8123 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 8124 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 8125 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 8126 G_QUEREMFLITS(p[2]) * 16); 8127 8128 rc = sbuf_finish(sb); 8129 sbuf_delete(sb); 8130 8131 return (rc); 8132 } 8133 8134 static int 8135 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 8136 { 8137 struct adapter *sc = arg1; 8138 struct sbuf *sb; 8139 int rc; 8140 struct tp_cpl_stats stats; 8141 8142 rc = sysctl_wire_old_buffer(req, 0); 8143 if (rc != 0) 8144 return (rc); 8145 8146 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8147 if (sb == NULL) 8148 return (ENOMEM); 8149 8150 mtx_lock(&sc->reg_lock); 8151 t4_tp_get_cpl_stats(sc, &stats, 0); 8152 mtx_unlock(&sc->reg_lock); 8153 8154 if (sc->chip_params->nchan > 2) { 8155 sbuf_printf(sb, " channel 0 channel 1" 8156 " channel 2 channel 3"); 8157 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 8158 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 8159 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 8160 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 8161 } else { 8162 sbuf_printf(sb, " channel 0 channel 1"); 8163 sbuf_printf(sb, "\nCPL requests: %10u %10u", 8164 stats.req[0], stats.req[1]); 8165 sbuf_printf(sb, "\nCPL responses: %10u %10u", 8166 stats.rsp[0], stats.rsp[1]); 8167 } 8168 8169 rc = sbuf_finish(sb); 8170 sbuf_delete(sb); 8171 8172 return (rc); 8173 } 8174 8175 static int 8176 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 8177 { 8178 struct adapter *sc = arg1; 8179 struct sbuf *sb; 8180 int rc; 8181 struct tp_usm_stats stats; 8182 8183 rc = sysctl_wire_old_buffer(req, 0); 8184 if (rc != 0) 8185 return(rc); 8186 8187 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8188 if (sb == NULL) 8189 return (ENOMEM); 8190 8191 t4_get_usm_stats(sc, &stats, 1); 8192 8193 sbuf_printf(sb, "Frames: %u\n", stats.frames); 8194 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 8195 sbuf_printf(sb, "Drops: %u", stats.drops); 8196 8197 rc = sbuf_finish(sb); 8198 sbuf_delete(sb); 8199 8200 return (rc); 8201 } 8202 8203 static const char * const devlog_level_strings[] = { 8204 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 8205 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 8206 [FW_DEVLOG_LEVEL_ERR] = "ERR", 8207 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 8208 [FW_DEVLOG_LEVEL_INFO] = "INFO", 8209 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 8210 }; 8211 8212 static const char * const devlog_facility_strings[] = { 8213 [FW_DEVLOG_FACILITY_CORE] = "CORE", 8214 [FW_DEVLOG_FACILITY_CF] = "CF", 8215 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 8216 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 8217 [FW_DEVLOG_FACILITY_RES] = "RES", 8218 [FW_DEVLOG_FACILITY_HW] = "HW", 8219 [FW_DEVLOG_FACILITY_FLR] = "FLR", 8220 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 8221 [FW_DEVLOG_FACILITY_PHY] = "PHY", 8222 [FW_DEVLOG_FACILITY_MAC] = "MAC", 8223 [FW_DEVLOG_FACILITY_PORT] = "PORT", 8224 [FW_DEVLOG_FACILITY_VI] = "VI", 8225 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 8226 [FW_DEVLOG_FACILITY_ACL] = "ACL", 8227 [FW_DEVLOG_FACILITY_TM] = "TM", 8228 [FW_DEVLOG_FACILITY_QFC] = "QFC", 8229 [FW_DEVLOG_FACILITY_DCB] = "DCB", 8230 [FW_DEVLOG_FACILITY_ETH] = "ETH", 8231 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 8232 [FW_DEVLOG_FACILITY_RI] = "RI", 8233 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 8234 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 8235 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 8236 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 8237 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 8238 }; 8239 8240 static int 8241 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 8242 { 8243 int i, j, rc, nentries, first = 0; 8244 struct devlog_params *dparams = &sc->params.devlog; 8245 struct fw_devlog_e *buf, *e; 8246 uint64_t ftstamp = UINT64_MAX; 8247 8248 if (dparams->addr == 0) 8249 return (ENXIO); 8250 8251 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 8252 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 8253 if (buf == NULL) 8254 return (ENOMEM); 8255 8256 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 8257 if (rc != 0) 8258 goto done; 8259 8260 nentries = dparams->size / sizeof(struct fw_devlog_e); 8261 for (i = 0; i < nentries; i++) { 8262 e = &buf[i]; 8263 8264 if (e->timestamp == 0) 8265 break; /* end */ 8266 8267 e->timestamp = be64toh(e->timestamp); 8268 e->seqno = be32toh(e->seqno); 8269 for (j = 0; j < 8; j++) 8270 e->params[j] = be32toh(e->params[j]); 8271 8272 if (e->timestamp < ftstamp) { 8273 ftstamp = e->timestamp; 8274 first = i; 8275 } 8276 } 8277 8278 if (buf[first].timestamp == 0) 8279 goto done; /* nothing in the log */ 8280 8281 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 8282 "Seq#", "Tstamp", "Level", "Facility", "Message"); 8283 8284 i = first; 8285 do { 8286 e = &buf[i]; 8287 if (e->timestamp == 0) 8288 break; /* end */ 8289 8290 sbuf_printf(sb, "%10d %15ju %8s %8s ", 8291 e->seqno, e->timestamp, 8292 (e->level < nitems(devlog_level_strings) ? 8293 devlog_level_strings[e->level] : "UNKNOWN"), 8294 (e->facility < nitems(devlog_facility_strings) ? 8295 devlog_facility_strings[e->facility] : "UNKNOWN")); 8296 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 8297 e->params[2], e->params[3], e->params[4], 8298 e->params[5], e->params[6], e->params[7]); 8299 8300 if (++i == nentries) 8301 i = 0; 8302 } while (i != first); 8303 done: 8304 free(buf, M_CXGBE); 8305 return (rc); 8306 } 8307 8308 static int 8309 sysctl_devlog(SYSCTL_HANDLER_ARGS) 8310 { 8311 struct adapter *sc = arg1; 8312 int rc; 8313 struct sbuf *sb; 8314 8315 rc = sysctl_wire_old_buffer(req, 0); 8316 if (rc != 0) 8317 return (rc); 8318 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8319 if (sb == NULL) 8320 return (ENOMEM); 8321 8322 rc = sbuf_devlog(sc, sb, M_WAITOK); 8323 if (rc == 0) 8324 rc = sbuf_finish(sb); 8325 sbuf_delete(sb); 8326 return (rc); 8327 } 8328 8329 void 8330 t4_os_dump_devlog(struct adapter *sc) 8331 { 8332 int rc; 8333 struct sbuf sb; 8334 8335 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 8336 return; 8337 rc = sbuf_devlog(sc, &sb, M_NOWAIT); 8338 if (rc == 0) { 8339 rc = sbuf_finish(&sb); 8340 if (rc == 0) { 8341 log(LOG_DEBUG, "%s: device log follows.\n%s", 8342 device_get_nameunit(sc->dev), sbuf_data(&sb)); 8343 } 8344 } 8345 sbuf_delete(&sb); 8346 } 8347 8348 static int 8349 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 8350 { 8351 struct adapter *sc = arg1; 8352 struct sbuf *sb; 8353 int rc; 8354 struct tp_fcoe_stats stats[MAX_NCHAN]; 8355 int i, nchan = sc->chip_params->nchan; 8356 8357 rc = sysctl_wire_old_buffer(req, 0); 8358 if (rc != 0) 8359 return (rc); 8360 8361 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8362 if (sb == NULL) 8363 return (ENOMEM); 8364 8365 for (i = 0; i < nchan; i++) 8366 t4_get_fcoe_stats(sc, i, &stats[i], 1); 8367 8368 if (nchan > 2) { 8369 sbuf_printf(sb, " channel 0 channel 1" 8370 " channel 2 channel 3"); 8371 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 8372 stats[0].octets_ddp, stats[1].octets_ddp, 8373 stats[2].octets_ddp, stats[3].octets_ddp); 8374 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 8375 stats[0].frames_ddp, stats[1].frames_ddp, 8376 stats[2].frames_ddp, stats[3].frames_ddp); 8377 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 8378 stats[0].frames_drop, stats[1].frames_drop, 8379 stats[2].frames_drop, stats[3].frames_drop); 8380 } else { 8381 sbuf_printf(sb, " channel 0 channel 1"); 8382 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 8383 stats[0].octets_ddp, stats[1].octets_ddp); 8384 sbuf_printf(sb, "\nframesDDP: %16u %16u", 8385 stats[0].frames_ddp, stats[1].frames_ddp); 8386 sbuf_printf(sb, "\nframesDrop: %16u %16u", 8387 stats[0].frames_drop, stats[1].frames_drop); 8388 } 8389 8390 rc = sbuf_finish(sb); 8391 sbuf_delete(sb); 8392 8393 return (rc); 8394 } 8395 8396 static int 8397 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 8398 { 8399 struct adapter *sc = arg1; 8400 struct sbuf *sb; 8401 int rc, i; 8402 unsigned int map, kbps, ipg, mode; 8403 unsigned int pace_tab[NTX_SCHED]; 8404 8405 rc = sysctl_wire_old_buffer(req, 0); 8406 if (rc != 0) 8407 return (rc); 8408 8409 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8410 if (sb == NULL) 8411 return (ENOMEM); 8412 8413 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 8414 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 8415 t4_read_pace_tbl(sc, pace_tab); 8416 8417 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 8418 "Class IPG (0.1 ns) Flow IPG (us)"); 8419 8420 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 8421 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 8422 sbuf_printf(sb, "\n %u %-5s %u ", i, 8423 (mode & (1 << i)) ? "flow" : "class", map & 3); 8424 if (kbps) 8425 sbuf_printf(sb, "%9u ", kbps); 8426 else 8427 sbuf_printf(sb, " disabled "); 8428 8429 if (ipg) 8430 sbuf_printf(sb, "%13u ", ipg); 8431 else 8432 sbuf_printf(sb, " disabled "); 8433 8434 if (pace_tab[i]) 8435 sbuf_printf(sb, "%10u", pace_tab[i]); 8436 else 8437 sbuf_printf(sb, " disabled"); 8438 } 8439 8440 rc = sbuf_finish(sb); 8441 sbuf_delete(sb); 8442 8443 return (rc); 8444 } 8445 8446 static int 8447 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 8448 { 8449 struct adapter *sc = arg1; 8450 struct sbuf *sb; 8451 int rc, i, j; 8452 uint64_t *p0, *p1; 8453 struct lb_port_stats s[2]; 8454 static const char *stat_name[] = { 8455 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 8456 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 8457 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 8458 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 8459 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 8460 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 8461 "BG2FramesTrunc:", "BG3FramesTrunc:" 8462 }; 8463 8464 rc = sysctl_wire_old_buffer(req, 0); 8465 if (rc != 0) 8466 return (rc); 8467 8468 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8469 if (sb == NULL) 8470 return (ENOMEM); 8471 8472 memset(s, 0, sizeof(s)); 8473 8474 for (i = 0; i < sc->chip_params->nchan; i += 2) { 8475 t4_get_lb_stats(sc, i, &s[0]); 8476 t4_get_lb_stats(sc, i + 1, &s[1]); 8477 8478 p0 = &s[0].octets; 8479 p1 = &s[1].octets; 8480 sbuf_printf(sb, "%s Loopback %u" 8481 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 8482 8483 for (j = 0; j < nitems(stat_name); j++) 8484 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 8485 *p0++, *p1++); 8486 } 8487 8488 rc = sbuf_finish(sb); 8489 sbuf_delete(sb); 8490 8491 return (rc); 8492 } 8493 8494 static int 8495 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 8496 { 8497 int rc = 0; 8498 struct port_info *pi = arg1; 8499 struct link_config *lc = &pi->link_cfg; 8500 struct sbuf *sb; 8501 8502 rc = sysctl_wire_old_buffer(req, 0); 8503 if (rc != 0) 8504 return(rc); 8505 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 8506 if (sb == NULL) 8507 return (ENOMEM); 8508 8509 if (lc->link_ok || lc->link_down_rc == 255) 8510 sbuf_printf(sb, "n/a"); 8511 else 8512 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 8513 8514 rc = sbuf_finish(sb); 8515 sbuf_delete(sb); 8516 8517 return (rc); 8518 } 8519 8520 struct mem_desc { 8521 unsigned int base; 8522 unsigned int limit; 8523 unsigned int idx; 8524 }; 8525 8526 static int 8527 mem_desc_cmp(const void *a, const void *b) 8528 { 8529 return ((const struct mem_desc *)a)->base - 8530 ((const struct mem_desc *)b)->base; 8531 } 8532 8533 static void 8534 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 8535 unsigned int to) 8536 { 8537 unsigned int size; 8538 8539 if (from == to) 8540 return; 8541 8542 size = to - from + 1; 8543 if (size == 0) 8544 return; 8545 8546 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 8547 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 8548 } 8549 8550 static int 8551 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 8552 { 8553 struct adapter *sc = arg1; 8554 struct sbuf *sb; 8555 int rc, i, n; 8556 uint32_t lo, hi, used, alloc; 8557 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 8558 static const char *region[] = { 8559 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 8560 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 8561 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 8562 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 8563 "RQUDP region:", "PBL region:", "TXPBL region:", 8564 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 8565 "On-chip queues:", "TLS keys:", 8566 }; 8567 struct mem_desc avail[4]; 8568 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 8569 struct mem_desc *md = mem; 8570 8571 rc = sysctl_wire_old_buffer(req, 0); 8572 if (rc != 0) 8573 return (rc); 8574 8575 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8576 if (sb == NULL) 8577 return (ENOMEM); 8578 8579 for (i = 0; i < nitems(mem); i++) { 8580 mem[i].limit = 0; 8581 mem[i].idx = i; 8582 } 8583 8584 /* Find and sort the populated memory ranges */ 8585 i = 0; 8586 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 8587 if (lo & F_EDRAM0_ENABLE) { 8588 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 8589 avail[i].base = G_EDRAM0_BASE(hi) << 20; 8590 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 8591 avail[i].idx = 0; 8592 i++; 8593 } 8594 if (lo & F_EDRAM1_ENABLE) { 8595 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 8596 avail[i].base = G_EDRAM1_BASE(hi) << 20; 8597 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 8598 avail[i].idx = 1; 8599 i++; 8600 } 8601 if (lo & F_EXT_MEM_ENABLE) { 8602 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 8603 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 8604 avail[i].limit = avail[i].base + 8605 (G_EXT_MEM_SIZE(hi) << 20); 8606 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 8607 i++; 8608 } 8609 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 8610 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 8611 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 8612 avail[i].limit = avail[i].base + 8613 (G_EXT_MEM1_SIZE(hi) << 20); 8614 avail[i].idx = 4; 8615 i++; 8616 } 8617 if (!i) /* no memory available */ 8618 return 0; 8619 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 8620 8621 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 8622 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 8623 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 8624 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 8625 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 8626 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 8627 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 8628 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 8629 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 8630 8631 /* the next few have explicit upper bounds */ 8632 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 8633 md->limit = md->base - 1 + 8634 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 8635 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 8636 md++; 8637 8638 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 8639 md->limit = md->base - 1 + 8640 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 8641 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 8642 md++; 8643 8644 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8645 if (chip_id(sc) <= CHELSIO_T5) 8646 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 8647 else 8648 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 8649 md->limit = 0; 8650 } else { 8651 md->base = 0; 8652 md->idx = nitems(region); /* hide it */ 8653 } 8654 md++; 8655 8656 #define ulp_region(reg) \ 8657 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 8658 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 8659 8660 ulp_region(RX_ISCSI); 8661 ulp_region(RX_TDDP); 8662 ulp_region(TX_TPT); 8663 ulp_region(RX_STAG); 8664 ulp_region(RX_RQ); 8665 ulp_region(RX_RQUDP); 8666 ulp_region(RX_PBL); 8667 ulp_region(TX_PBL); 8668 #undef ulp_region 8669 8670 md->base = 0; 8671 md->idx = nitems(region); 8672 if (!is_t4(sc)) { 8673 uint32_t size = 0; 8674 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 8675 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 8676 8677 if (is_t5(sc)) { 8678 if (sge_ctrl & F_VFIFO_ENABLE) 8679 size = G_DBVFIFO_SIZE(fifo_size); 8680 } else 8681 size = G_T6_DBVFIFO_SIZE(fifo_size); 8682 8683 if (size) { 8684 md->base = G_BASEADDR(t4_read_reg(sc, 8685 A_SGE_DBVFIFO_BADDR)); 8686 md->limit = md->base + (size << 2) - 1; 8687 } 8688 } 8689 md++; 8690 8691 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 8692 md->limit = 0; 8693 md++; 8694 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 8695 md->limit = 0; 8696 md++; 8697 8698 md->base = sc->vres.ocq.start; 8699 if (sc->vres.ocq.size) 8700 md->limit = md->base + sc->vres.ocq.size - 1; 8701 else 8702 md->idx = nitems(region); /* hide it */ 8703 md++; 8704 8705 md->base = sc->vres.key.start; 8706 if (sc->vres.key.size) 8707 md->limit = md->base + sc->vres.key.size - 1; 8708 else 8709 md->idx = nitems(region); /* hide it */ 8710 md++; 8711 8712 /* add any address-space holes, there can be up to 3 */ 8713 for (n = 0; n < i - 1; n++) 8714 if (avail[n].limit < avail[n + 1].base) 8715 (md++)->base = avail[n].limit; 8716 if (avail[n].limit) 8717 (md++)->base = avail[n].limit; 8718 8719 n = md - mem; 8720 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 8721 8722 for (lo = 0; lo < i; lo++) 8723 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 8724 avail[lo].limit - 1); 8725 8726 sbuf_printf(sb, "\n"); 8727 for (i = 0; i < n; i++) { 8728 if (mem[i].idx >= nitems(region)) 8729 continue; /* skip holes */ 8730 if (!mem[i].limit) 8731 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 8732 mem_region_show(sb, region[mem[i].idx], mem[i].base, 8733 mem[i].limit); 8734 } 8735 8736 sbuf_printf(sb, "\n"); 8737 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 8738 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 8739 mem_region_show(sb, "uP RAM:", lo, hi); 8740 8741 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 8742 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 8743 mem_region_show(sb, "uP Extmem2:", lo, hi); 8744 8745 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 8746 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 8747 G_PMRXMAXPAGE(lo), 8748 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 8749 (lo & F_PMRXNUMCHN) ? 2 : 1); 8750 8751 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 8752 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 8753 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 8754 G_PMTXMAXPAGE(lo), 8755 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 8756 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 8757 sbuf_printf(sb, "%u p-structs\n", 8758 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 8759 8760 for (i = 0; i < 4; i++) { 8761 if (chip_id(sc) > CHELSIO_T5) 8762 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 8763 else 8764 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 8765 if (is_t5(sc)) { 8766 used = G_T5_USED(lo); 8767 alloc = G_T5_ALLOC(lo); 8768 } else { 8769 used = G_USED(lo); 8770 alloc = G_ALLOC(lo); 8771 } 8772 /* For T6 these are MAC buffer groups */ 8773 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 8774 i, used, alloc); 8775 } 8776 for (i = 0; i < sc->chip_params->nchan; i++) { 8777 if (chip_id(sc) > CHELSIO_T5) 8778 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 8779 else 8780 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 8781 if (is_t5(sc)) { 8782 used = G_T5_USED(lo); 8783 alloc = G_T5_ALLOC(lo); 8784 } else { 8785 used = G_USED(lo); 8786 alloc = G_ALLOC(lo); 8787 } 8788 /* For T6 these are MAC buffer groups */ 8789 sbuf_printf(sb, 8790 "\nLoopback %d using %u pages out of %u allocated", 8791 i, used, alloc); 8792 } 8793 8794 rc = sbuf_finish(sb); 8795 sbuf_delete(sb); 8796 8797 return (rc); 8798 } 8799 8800 static inline void 8801 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 8802 { 8803 *mask = x | y; 8804 y = htobe64(y); 8805 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 8806 } 8807 8808 static int 8809 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 8810 { 8811 struct adapter *sc = arg1; 8812 struct sbuf *sb; 8813 int rc, i; 8814 8815 MPASS(chip_id(sc) <= CHELSIO_T5); 8816 8817 rc = sysctl_wire_old_buffer(req, 0); 8818 if (rc != 0) 8819 return (rc); 8820 8821 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8822 if (sb == NULL) 8823 return (ENOMEM); 8824 8825 sbuf_printf(sb, 8826 "Idx Ethernet address Mask Vld Ports PF" 8827 " VF Replication P0 P1 P2 P3 ML"); 8828 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8829 uint64_t tcamx, tcamy, mask; 8830 uint32_t cls_lo, cls_hi; 8831 uint8_t addr[ETHER_ADDR_LEN]; 8832 8833 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 8834 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 8835 if (tcamx & tcamy) 8836 continue; 8837 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8838 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8839 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8840 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 8841 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 8842 addr[3], addr[4], addr[5], (uintmax_t)mask, 8843 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 8844 G_PORTMAP(cls_hi), G_PF(cls_lo), 8845 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 8846 8847 if (cls_lo & F_REPLICATE) { 8848 struct fw_ldst_cmd ldst_cmd; 8849 8850 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8851 ldst_cmd.op_to_addrspace = 8852 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8853 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8854 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8855 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8856 ldst_cmd.u.mps.rplc.fid_idx = 8857 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8858 V_FW_LDST_CMD_IDX(i)); 8859 8860 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8861 "t4mps"); 8862 if (rc) 8863 break; 8864 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8865 sizeof(ldst_cmd), &ldst_cmd); 8866 end_synchronized_op(sc, 0); 8867 8868 if (rc != 0) { 8869 sbuf_printf(sb, "%36d", rc); 8870 rc = 0; 8871 } else { 8872 sbuf_printf(sb, " %08x %08x %08x %08x", 8873 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8874 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8875 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8876 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8877 } 8878 } else 8879 sbuf_printf(sb, "%36s", ""); 8880 8881 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 8882 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 8883 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 8884 } 8885 8886 if (rc) 8887 (void) sbuf_finish(sb); 8888 else 8889 rc = sbuf_finish(sb); 8890 sbuf_delete(sb); 8891 8892 return (rc); 8893 } 8894 8895 static int 8896 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 8897 { 8898 struct adapter *sc = arg1; 8899 struct sbuf *sb; 8900 int rc, i; 8901 8902 MPASS(chip_id(sc) > CHELSIO_T5); 8903 8904 rc = sysctl_wire_old_buffer(req, 0); 8905 if (rc != 0) 8906 return (rc); 8907 8908 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8909 if (sb == NULL) 8910 return (ENOMEM); 8911 8912 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 8913 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 8914 " Replication" 8915 " P0 P1 P2 P3 ML\n"); 8916 8917 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8918 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 8919 uint16_t ivlan; 8920 uint64_t tcamx, tcamy, val, mask; 8921 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 8922 uint8_t addr[ETHER_ADDR_LEN]; 8923 8924 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 8925 if (i < 256) 8926 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 8927 else 8928 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 8929 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8930 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8931 tcamy = G_DMACH(val) << 32; 8932 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8933 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8934 lookup_type = G_DATALKPTYPE(data2); 8935 port_num = G_DATAPORTNUM(data2); 8936 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8937 /* Inner header VNI */ 8938 vniy = ((data2 & F_DATAVIDH2) << 23) | 8939 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8940 dip_hit = data2 & F_DATADIPHIT; 8941 vlan_vld = 0; 8942 } else { 8943 vniy = 0; 8944 dip_hit = 0; 8945 vlan_vld = data2 & F_DATAVIDH2; 8946 ivlan = G_VIDL(val); 8947 } 8948 8949 ctl |= V_CTLXYBITSEL(1); 8950 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8951 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8952 tcamx = G_DMACH(val) << 32; 8953 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8954 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8955 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8956 /* Inner header VNI mask */ 8957 vnix = ((data2 & F_DATAVIDH2) << 23) | 8958 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8959 } else 8960 vnix = 0; 8961 8962 if (tcamx & tcamy) 8963 continue; 8964 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8965 8966 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8967 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8968 8969 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8970 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8971 "%012jx %06x %06x - - %3c" 8972 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 8973 addr[1], addr[2], addr[3], addr[4], addr[5], 8974 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 8975 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8976 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8977 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8978 } else { 8979 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8980 "%012jx - - ", i, addr[0], addr[1], 8981 addr[2], addr[3], addr[4], addr[5], 8982 (uintmax_t)mask); 8983 8984 if (vlan_vld) 8985 sbuf_printf(sb, "%4u Y ", ivlan); 8986 else 8987 sbuf_printf(sb, " - N "); 8988 8989 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 8990 lookup_type ? 'I' : 'O', port_num, 8991 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8992 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8993 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8994 } 8995 8996 8997 if (cls_lo & F_T6_REPLICATE) { 8998 struct fw_ldst_cmd ldst_cmd; 8999 9000 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 9001 ldst_cmd.op_to_addrspace = 9002 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 9003 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9004 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 9005 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 9006 ldst_cmd.u.mps.rplc.fid_idx = 9007 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 9008 V_FW_LDST_CMD_IDX(i)); 9009 9010 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 9011 "t6mps"); 9012 if (rc) 9013 break; 9014 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 9015 sizeof(ldst_cmd), &ldst_cmd); 9016 end_synchronized_op(sc, 0); 9017 9018 if (rc != 0) { 9019 sbuf_printf(sb, "%72d", rc); 9020 rc = 0; 9021 } else { 9022 sbuf_printf(sb, " %08x %08x %08x %08x" 9023 " %08x %08x %08x %08x", 9024 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 9025 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 9026 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 9027 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 9028 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 9029 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 9030 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 9031 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 9032 } 9033 } else 9034 sbuf_printf(sb, "%72s", ""); 9035 9036 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 9037 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 9038 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 9039 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 9040 } 9041 9042 if (rc) 9043 (void) sbuf_finish(sb); 9044 else 9045 rc = sbuf_finish(sb); 9046 sbuf_delete(sb); 9047 9048 return (rc); 9049 } 9050 9051 static int 9052 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 9053 { 9054 struct adapter *sc = arg1; 9055 struct sbuf *sb; 9056 int rc; 9057 uint16_t mtus[NMTUS]; 9058 9059 rc = sysctl_wire_old_buffer(req, 0); 9060 if (rc != 0) 9061 return (rc); 9062 9063 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9064 if (sb == NULL) 9065 return (ENOMEM); 9066 9067 t4_read_mtu_tbl(sc, mtus, NULL); 9068 9069 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 9070 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 9071 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 9072 mtus[14], mtus[15]); 9073 9074 rc = sbuf_finish(sb); 9075 sbuf_delete(sb); 9076 9077 return (rc); 9078 } 9079 9080 static int 9081 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 9082 { 9083 struct adapter *sc = arg1; 9084 struct sbuf *sb; 9085 int rc, i; 9086 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 9087 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 9088 static const char *tx_stats[MAX_PM_NSTATS] = { 9089 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 9090 "Tx FIFO wait", NULL, "Tx latency" 9091 }; 9092 static const char *rx_stats[MAX_PM_NSTATS] = { 9093 "Read:", "Write bypass:", "Write mem:", "Flush:", 9094 "Rx FIFO wait", NULL, "Rx latency" 9095 }; 9096 9097 rc = sysctl_wire_old_buffer(req, 0); 9098 if (rc != 0) 9099 return (rc); 9100 9101 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9102 if (sb == NULL) 9103 return (ENOMEM); 9104 9105 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 9106 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 9107 9108 sbuf_printf(sb, " Tx pcmds Tx bytes"); 9109 for (i = 0; i < 4; i++) { 9110 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 9111 tx_cyc[i]); 9112 } 9113 9114 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 9115 for (i = 0; i < 4; i++) { 9116 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 9117 rx_cyc[i]); 9118 } 9119 9120 if (chip_id(sc) > CHELSIO_T5) { 9121 sbuf_printf(sb, 9122 "\n Total wait Total occupancy"); 9123 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 9124 tx_cyc[i]); 9125 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 9126 rx_cyc[i]); 9127 9128 i += 2; 9129 MPASS(i < nitems(tx_stats)); 9130 9131 sbuf_printf(sb, 9132 "\n Reads Total wait"); 9133 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 9134 tx_cyc[i]); 9135 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 9136 rx_cyc[i]); 9137 } 9138 9139 rc = sbuf_finish(sb); 9140 sbuf_delete(sb); 9141 9142 return (rc); 9143 } 9144 9145 static int 9146 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 9147 { 9148 struct adapter *sc = arg1; 9149 struct sbuf *sb; 9150 int rc; 9151 struct tp_rdma_stats stats; 9152 9153 rc = sysctl_wire_old_buffer(req, 0); 9154 if (rc != 0) 9155 return (rc); 9156 9157 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9158 if (sb == NULL) 9159 return (ENOMEM); 9160 9161 mtx_lock(&sc->reg_lock); 9162 t4_tp_get_rdma_stats(sc, &stats, 0); 9163 mtx_unlock(&sc->reg_lock); 9164 9165 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 9166 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 9167 9168 rc = sbuf_finish(sb); 9169 sbuf_delete(sb); 9170 9171 return (rc); 9172 } 9173 9174 static int 9175 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 9176 { 9177 struct adapter *sc = arg1; 9178 struct sbuf *sb; 9179 int rc; 9180 struct tp_tcp_stats v4, v6; 9181 9182 rc = sysctl_wire_old_buffer(req, 0); 9183 if (rc != 0) 9184 return (rc); 9185 9186 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9187 if (sb == NULL) 9188 return (ENOMEM); 9189 9190 mtx_lock(&sc->reg_lock); 9191 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 9192 mtx_unlock(&sc->reg_lock); 9193 9194 sbuf_printf(sb, 9195 " IP IPv6\n"); 9196 sbuf_printf(sb, "OutRsts: %20u %20u\n", 9197 v4.tcp_out_rsts, v6.tcp_out_rsts); 9198 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 9199 v4.tcp_in_segs, v6.tcp_in_segs); 9200 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 9201 v4.tcp_out_segs, v6.tcp_out_segs); 9202 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 9203 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 9204 9205 rc = sbuf_finish(sb); 9206 sbuf_delete(sb); 9207 9208 return (rc); 9209 } 9210 9211 static int 9212 sysctl_tids(SYSCTL_HANDLER_ARGS) 9213 { 9214 struct adapter *sc = arg1; 9215 struct sbuf *sb; 9216 int rc; 9217 struct tid_info *t = &sc->tids; 9218 9219 rc = sysctl_wire_old_buffer(req, 0); 9220 if (rc != 0) 9221 return (rc); 9222 9223 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9224 if (sb == NULL) 9225 return (ENOMEM); 9226 9227 if (t->natids) { 9228 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 9229 t->atids_in_use); 9230 } 9231 9232 if (t->nhpftids) { 9233 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 9234 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 9235 } 9236 9237 if (t->ntids) { 9238 sbuf_printf(sb, "TID range: "); 9239 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 9240 uint32_t b, hb; 9241 9242 if (chip_id(sc) <= CHELSIO_T5) { 9243 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 9244 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 9245 } else { 9246 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 9247 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 9248 } 9249 9250 if (b) 9251 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1); 9252 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 9253 } else 9254 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1); 9255 sbuf_printf(sb, ", in use: %u\n", 9256 atomic_load_acq_int(&t->tids_in_use)); 9257 } 9258 9259 if (t->nstids) { 9260 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 9261 t->stid_base + t->nstids - 1, t->stids_in_use); 9262 } 9263 9264 if (t->nftids) { 9265 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 9266 t->ftid_end, t->ftids_in_use); 9267 } 9268 9269 if (t->netids) { 9270 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 9271 t->etid_base + t->netids - 1, t->etids_in_use); 9272 } 9273 9274 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 9275 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 9276 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 9277 9278 rc = sbuf_finish(sb); 9279 sbuf_delete(sb); 9280 9281 return (rc); 9282 } 9283 9284 static int 9285 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 9286 { 9287 struct adapter *sc = arg1; 9288 struct sbuf *sb; 9289 int rc; 9290 struct tp_err_stats stats; 9291 9292 rc = sysctl_wire_old_buffer(req, 0); 9293 if (rc != 0) 9294 return (rc); 9295 9296 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9297 if (sb == NULL) 9298 return (ENOMEM); 9299 9300 mtx_lock(&sc->reg_lock); 9301 t4_tp_get_err_stats(sc, &stats, 0); 9302 mtx_unlock(&sc->reg_lock); 9303 9304 if (sc->chip_params->nchan > 2) { 9305 sbuf_printf(sb, " channel 0 channel 1" 9306 " channel 2 channel 3\n"); 9307 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 9308 stats.mac_in_errs[0], stats.mac_in_errs[1], 9309 stats.mac_in_errs[2], stats.mac_in_errs[3]); 9310 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 9311 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 9312 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 9313 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 9314 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 9315 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 9316 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 9317 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 9318 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 9319 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 9320 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 9321 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 9322 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 9323 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 9324 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 9325 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 9326 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 9327 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 9328 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 9329 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 9330 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 9331 } else { 9332 sbuf_printf(sb, " channel 0 channel 1\n"); 9333 sbuf_printf(sb, "macInErrs: %10u %10u\n", 9334 stats.mac_in_errs[0], stats.mac_in_errs[1]); 9335 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 9336 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 9337 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 9338 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 9339 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 9340 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 9341 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 9342 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 9343 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 9344 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 9345 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 9346 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 9347 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 9348 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 9349 } 9350 9351 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 9352 stats.ofld_no_neigh, stats.ofld_cong_defer); 9353 9354 rc = sbuf_finish(sb); 9355 sbuf_delete(sb); 9356 9357 return (rc); 9358 } 9359 9360 static int 9361 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 9362 { 9363 struct adapter *sc = arg1; 9364 struct tp_params *tpp = &sc->params.tp; 9365 u_int mask; 9366 int rc; 9367 9368 mask = tpp->la_mask >> 16; 9369 rc = sysctl_handle_int(oidp, &mask, 0, req); 9370 if (rc != 0 || req->newptr == NULL) 9371 return (rc); 9372 if (mask > 0xffff) 9373 return (EINVAL); 9374 tpp->la_mask = mask << 16; 9375 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 9376 9377 return (0); 9378 } 9379 9380 struct field_desc { 9381 const char *name; 9382 u_int start; 9383 u_int width; 9384 }; 9385 9386 static void 9387 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 9388 { 9389 char buf[32]; 9390 int line_size = 0; 9391 9392 while (f->name) { 9393 uint64_t mask = (1ULL << f->width) - 1; 9394 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 9395 ((uintmax_t)v >> f->start) & mask); 9396 9397 if (line_size + len >= 79) { 9398 line_size = 8; 9399 sbuf_printf(sb, "\n "); 9400 } 9401 sbuf_printf(sb, "%s ", buf); 9402 line_size += len + 1; 9403 f++; 9404 } 9405 sbuf_printf(sb, "\n"); 9406 } 9407 9408 static const struct field_desc tp_la0[] = { 9409 { "RcfOpCodeOut", 60, 4 }, 9410 { "State", 56, 4 }, 9411 { "WcfState", 52, 4 }, 9412 { "RcfOpcSrcOut", 50, 2 }, 9413 { "CRxError", 49, 1 }, 9414 { "ERxError", 48, 1 }, 9415 { "SanityFailed", 47, 1 }, 9416 { "SpuriousMsg", 46, 1 }, 9417 { "FlushInputMsg", 45, 1 }, 9418 { "FlushInputCpl", 44, 1 }, 9419 { "RssUpBit", 43, 1 }, 9420 { "RssFilterHit", 42, 1 }, 9421 { "Tid", 32, 10 }, 9422 { "InitTcb", 31, 1 }, 9423 { "LineNumber", 24, 7 }, 9424 { "Emsg", 23, 1 }, 9425 { "EdataOut", 22, 1 }, 9426 { "Cmsg", 21, 1 }, 9427 { "CdataOut", 20, 1 }, 9428 { "EreadPdu", 19, 1 }, 9429 { "CreadPdu", 18, 1 }, 9430 { "TunnelPkt", 17, 1 }, 9431 { "RcfPeerFin", 16, 1 }, 9432 { "RcfReasonOut", 12, 4 }, 9433 { "TxCchannel", 10, 2 }, 9434 { "RcfTxChannel", 8, 2 }, 9435 { "RxEchannel", 6, 2 }, 9436 { "RcfRxChannel", 5, 1 }, 9437 { "RcfDataOutSrdy", 4, 1 }, 9438 { "RxDvld", 3, 1 }, 9439 { "RxOoDvld", 2, 1 }, 9440 { "RxCongestion", 1, 1 }, 9441 { "TxCongestion", 0, 1 }, 9442 { NULL } 9443 }; 9444 9445 static const struct field_desc tp_la1[] = { 9446 { "CplCmdIn", 56, 8 }, 9447 { "CplCmdOut", 48, 8 }, 9448 { "ESynOut", 47, 1 }, 9449 { "EAckOut", 46, 1 }, 9450 { "EFinOut", 45, 1 }, 9451 { "ERstOut", 44, 1 }, 9452 { "SynIn", 43, 1 }, 9453 { "AckIn", 42, 1 }, 9454 { "FinIn", 41, 1 }, 9455 { "RstIn", 40, 1 }, 9456 { "DataIn", 39, 1 }, 9457 { "DataInVld", 38, 1 }, 9458 { "PadIn", 37, 1 }, 9459 { "RxBufEmpty", 36, 1 }, 9460 { "RxDdp", 35, 1 }, 9461 { "RxFbCongestion", 34, 1 }, 9462 { "TxFbCongestion", 33, 1 }, 9463 { "TxPktSumSrdy", 32, 1 }, 9464 { "RcfUlpType", 28, 4 }, 9465 { "Eread", 27, 1 }, 9466 { "Ebypass", 26, 1 }, 9467 { "Esave", 25, 1 }, 9468 { "Static0", 24, 1 }, 9469 { "Cread", 23, 1 }, 9470 { "Cbypass", 22, 1 }, 9471 { "Csave", 21, 1 }, 9472 { "CPktOut", 20, 1 }, 9473 { "RxPagePoolFull", 18, 2 }, 9474 { "RxLpbkPkt", 17, 1 }, 9475 { "TxLpbkPkt", 16, 1 }, 9476 { "RxVfValid", 15, 1 }, 9477 { "SynLearned", 14, 1 }, 9478 { "SetDelEntry", 13, 1 }, 9479 { "SetInvEntry", 12, 1 }, 9480 { "CpcmdDvld", 11, 1 }, 9481 { "CpcmdSave", 10, 1 }, 9482 { "RxPstructsFull", 8, 2 }, 9483 { "EpcmdDvld", 7, 1 }, 9484 { "EpcmdFlush", 6, 1 }, 9485 { "EpcmdTrimPrefix", 5, 1 }, 9486 { "EpcmdTrimPostfix", 4, 1 }, 9487 { "ERssIp4Pkt", 3, 1 }, 9488 { "ERssIp6Pkt", 2, 1 }, 9489 { "ERssTcpUdpPkt", 1, 1 }, 9490 { "ERssFceFipPkt", 0, 1 }, 9491 { NULL } 9492 }; 9493 9494 static const struct field_desc tp_la2[] = { 9495 { "CplCmdIn", 56, 8 }, 9496 { "MpsVfVld", 55, 1 }, 9497 { "MpsPf", 52, 3 }, 9498 { "MpsVf", 44, 8 }, 9499 { "SynIn", 43, 1 }, 9500 { "AckIn", 42, 1 }, 9501 { "FinIn", 41, 1 }, 9502 { "RstIn", 40, 1 }, 9503 { "DataIn", 39, 1 }, 9504 { "DataInVld", 38, 1 }, 9505 { "PadIn", 37, 1 }, 9506 { "RxBufEmpty", 36, 1 }, 9507 { "RxDdp", 35, 1 }, 9508 { "RxFbCongestion", 34, 1 }, 9509 { "TxFbCongestion", 33, 1 }, 9510 { "TxPktSumSrdy", 32, 1 }, 9511 { "RcfUlpType", 28, 4 }, 9512 { "Eread", 27, 1 }, 9513 { "Ebypass", 26, 1 }, 9514 { "Esave", 25, 1 }, 9515 { "Static0", 24, 1 }, 9516 { "Cread", 23, 1 }, 9517 { "Cbypass", 22, 1 }, 9518 { "Csave", 21, 1 }, 9519 { "CPktOut", 20, 1 }, 9520 { "RxPagePoolFull", 18, 2 }, 9521 { "RxLpbkPkt", 17, 1 }, 9522 { "TxLpbkPkt", 16, 1 }, 9523 { "RxVfValid", 15, 1 }, 9524 { "SynLearned", 14, 1 }, 9525 { "SetDelEntry", 13, 1 }, 9526 { "SetInvEntry", 12, 1 }, 9527 { "CpcmdDvld", 11, 1 }, 9528 { "CpcmdSave", 10, 1 }, 9529 { "RxPstructsFull", 8, 2 }, 9530 { "EpcmdDvld", 7, 1 }, 9531 { "EpcmdFlush", 6, 1 }, 9532 { "EpcmdTrimPrefix", 5, 1 }, 9533 { "EpcmdTrimPostfix", 4, 1 }, 9534 { "ERssIp4Pkt", 3, 1 }, 9535 { "ERssIp6Pkt", 2, 1 }, 9536 { "ERssTcpUdpPkt", 1, 1 }, 9537 { "ERssFceFipPkt", 0, 1 }, 9538 { NULL } 9539 }; 9540 9541 static void 9542 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 9543 { 9544 9545 field_desc_show(sb, *p, tp_la0); 9546 } 9547 9548 static void 9549 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 9550 { 9551 9552 if (idx) 9553 sbuf_printf(sb, "\n"); 9554 field_desc_show(sb, p[0], tp_la0); 9555 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9556 field_desc_show(sb, p[1], tp_la0); 9557 } 9558 9559 static void 9560 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 9561 { 9562 9563 if (idx) 9564 sbuf_printf(sb, "\n"); 9565 field_desc_show(sb, p[0], tp_la0); 9566 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9567 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 9568 } 9569 9570 static int 9571 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 9572 { 9573 struct adapter *sc = arg1; 9574 struct sbuf *sb; 9575 uint64_t *buf, *p; 9576 int rc; 9577 u_int i, inc; 9578 void (*show_func)(struct sbuf *, uint64_t *, int); 9579 9580 rc = sysctl_wire_old_buffer(req, 0); 9581 if (rc != 0) 9582 return (rc); 9583 9584 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9585 if (sb == NULL) 9586 return (ENOMEM); 9587 9588 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 9589 9590 t4_tp_read_la(sc, buf, NULL); 9591 p = buf; 9592 9593 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 9594 case 2: 9595 inc = 2; 9596 show_func = tp_la_show2; 9597 break; 9598 case 3: 9599 inc = 2; 9600 show_func = tp_la_show3; 9601 break; 9602 default: 9603 inc = 1; 9604 show_func = tp_la_show; 9605 } 9606 9607 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 9608 (*show_func)(sb, p, i); 9609 9610 rc = sbuf_finish(sb); 9611 sbuf_delete(sb); 9612 free(buf, M_CXGBE); 9613 return (rc); 9614 } 9615 9616 static int 9617 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 9618 { 9619 struct adapter *sc = arg1; 9620 struct sbuf *sb; 9621 int rc; 9622 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 9623 9624 rc = sysctl_wire_old_buffer(req, 0); 9625 if (rc != 0) 9626 return (rc); 9627 9628 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9629 if (sb == NULL) 9630 return (ENOMEM); 9631 9632 t4_get_chan_txrate(sc, nrate, orate); 9633 9634 if (sc->chip_params->nchan > 2) { 9635 sbuf_printf(sb, " channel 0 channel 1" 9636 " channel 2 channel 3\n"); 9637 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 9638 nrate[0], nrate[1], nrate[2], nrate[3]); 9639 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 9640 orate[0], orate[1], orate[2], orate[3]); 9641 } else { 9642 sbuf_printf(sb, " channel 0 channel 1\n"); 9643 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 9644 nrate[0], nrate[1]); 9645 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 9646 orate[0], orate[1]); 9647 } 9648 9649 rc = sbuf_finish(sb); 9650 sbuf_delete(sb); 9651 9652 return (rc); 9653 } 9654 9655 static int 9656 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 9657 { 9658 struct adapter *sc = arg1; 9659 struct sbuf *sb; 9660 uint32_t *buf, *p; 9661 int rc, i; 9662 9663 rc = sysctl_wire_old_buffer(req, 0); 9664 if (rc != 0) 9665 return (rc); 9666 9667 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9668 if (sb == NULL) 9669 return (ENOMEM); 9670 9671 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 9672 M_ZERO | M_WAITOK); 9673 9674 t4_ulprx_read_la(sc, buf); 9675 p = buf; 9676 9677 sbuf_printf(sb, " Pcmd Type Message" 9678 " Data"); 9679 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 9680 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 9681 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 9682 } 9683 9684 rc = sbuf_finish(sb); 9685 sbuf_delete(sb); 9686 free(buf, M_CXGBE); 9687 return (rc); 9688 } 9689 9690 static int 9691 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 9692 { 9693 struct adapter *sc = arg1; 9694 struct sbuf *sb; 9695 int rc, v; 9696 9697 MPASS(chip_id(sc) >= CHELSIO_T5); 9698 9699 rc = sysctl_wire_old_buffer(req, 0); 9700 if (rc != 0) 9701 return (rc); 9702 9703 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9704 if (sb == NULL) 9705 return (ENOMEM); 9706 9707 v = t4_read_reg(sc, A_SGE_STAT_CFG); 9708 if (G_STATSOURCE_T5(v) == 7) { 9709 int mode; 9710 9711 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 9712 if (mode == 0) { 9713 sbuf_printf(sb, "total %d, incomplete %d", 9714 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9715 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9716 } else if (mode == 1) { 9717 sbuf_printf(sb, "total %d, data overflow %d", 9718 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9719 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9720 } else { 9721 sbuf_printf(sb, "unknown mode %d", mode); 9722 } 9723 } 9724 rc = sbuf_finish(sb); 9725 sbuf_delete(sb); 9726 9727 return (rc); 9728 } 9729 9730 static int 9731 sysctl_cpus(SYSCTL_HANDLER_ARGS) 9732 { 9733 struct adapter *sc = arg1; 9734 enum cpu_sets op = arg2; 9735 cpuset_t cpuset; 9736 struct sbuf *sb; 9737 int i, rc; 9738 9739 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 9740 9741 CPU_ZERO(&cpuset); 9742 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 9743 if (rc != 0) 9744 return (rc); 9745 9746 rc = sysctl_wire_old_buffer(req, 0); 9747 if (rc != 0) 9748 return (rc); 9749 9750 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9751 if (sb == NULL) 9752 return (ENOMEM); 9753 9754 CPU_FOREACH(i) 9755 sbuf_printf(sb, "%d ", i); 9756 rc = sbuf_finish(sb); 9757 sbuf_delete(sb); 9758 9759 return (rc); 9760 } 9761 9762 #ifdef TCP_OFFLOAD 9763 static int 9764 sysctl_tls(SYSCTL_HANDLER_ARGS) 9765 { 9766 struct adapter *sc = arg1; 9767 int i, j, v, rc; 9768 struct vi_info *vi; 9769 9770 v = sc->tt.tls; 9771 rc = sysctl_handle_int(oidp, &v, 0, req); 9772 if (rc != 0 || req->newptr == NULL) 9773 return (rc); 9774 9775 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 9776 return (ENOTSUP); 9777 9778 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls"); 9779 if (rc) 9780 return (rc); 9781 sc->tt.tls = !!v; 9782 for_each_port(sc, i) { 9783 for_each_vi(sc->port[i], j, vi) { 9784 if (vi->flags & VI_INIT_DONE) 9785 t4_update_fl_bufsize(vi->ifp); 9786 } 9787 } 9788 end_synchronized_op(sc, 0); 9789 9790 return (0); 9791 9792 } 9793 9794 static int 9795 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 9796 { 9797 struct adapter *sc = arg1; 9798 int *old_ports, *new_ports; 9799 int i, new_count, rc; 9800 9801 if (req->newptr == NULL && req->oldptr == NULL) 9802 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 9803 sizeof(sc->tt.tls_rx_ports[0]))); 9804 9805 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 9806 if (rc) 9807 return (rc); 9808 9809 if (sc->tt.num_tls_rx_ports == 0) { 9810 i = -1; 9811 rc = SYSCTL_OUT(req, &i, sizeof(i)); 9812 } else 9813 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 9814 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 9815 if (rc == 0 && req->newptr != NULL) { 9816 new_count = req->newlen / sizeof(new_ports[0]); 9817 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 9818 M_WAITOK); 9819 rc = SYSCTL_IN(req, new_ports, new_count * 9820 sizeof(new_ports[0])); 9821 if (rc) 9822 goto err; 9823 9824 /* Allow setting to a single '-1' to clear the list. */ 9825 if (new_count == 1 && new_ports[0] == -1) { 9826 ADAPTER_LOCK(sc); 9827 old_ports = sc->tt.tls_rx_ports; 9828 sc->tt.tls_rx_ports = NULL; 9829 sc->tt.num_tls_rx_ports = 0; 9830 ADAPTER_UNLOCK(sc); 9831 free(old_ports, M_CXGBE); 9832 } else { 9833 for (i = 0; i < new_count; i++) { 9834 if (new_ports[i] < 1 || 9835 new_ports[i] > IPPORT_MAX) { 9836 rc = EINVAL; 9837 goto err; 9838 } 9839 } 9840 9841 ADAPTER_LOCK(sc); 9842 old_ports = sc->tt.tls_rx_ports; 9843 sc->tt.tls_rx_ports = new_ports; 9844 sc->tt.num_tls_rx_ports = new_count; 9845 ADAPTER_UNLOCK(sc); 9846 free(old_ports, M_CXGBE); 9847 new_ports = NULL; 9848 } 9849 err: 9850 free(new_ports, M_CXGBE); 9851 } 9852 end_synchronized_op(sc, 0); 9853 return (rc); 9854 } 9855 9856 static void 9857 unit_conv(char *buf, size_t len, u_int val, u_int factor) 9858 { 9859 u_int rem = val % factor; 9860 9861 if (rem == 0) 9862 snprintf(buf, len, "%u", val / factor); 9863 else { 9864 while (rem % 10 == 0) 9865 rem /= 10; 9866 snprintf(buf, len, "%u.%u", val / factor, rem); 9867 } 9868 } 9869 9870 static int 9871 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 9872 { 9873 struct adapter *sc = arg1; 9874 char buf[16]; 9875 u_int res, re; 9876 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9877 9878 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9879 switch (arg2) { 9880 case 0: 9881 /* timer_tick */ 9882 re = G_TIMERRESOLUTION(res); 9883 break; 9884 case 1: 9885 /* TCP timestamp tick */ 9886 re = G_TIMESTAMPRESOLUTION(res); 9887 break; 9888 case 2: 9889 /* DACK tick */ 9890 re = G_DELAYEDACKRESOLUTION(res); 9891 break; 9892 default: 9893 return (EDOOFUS); 9894 } 9895 9896 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 9897 9898 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 9899 } 9900 9901 static int 9902 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 9903 { 9904 struct adapter *sc = arg1; 9905 u_int res, dack_re, v; 9906 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9907 9908 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9909 dack_re = G_DELAYEDACKRESOLUTION(res); 9910 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 9911 9912 return (sysctl_handle_int(oidp, &v, 0, req)); 9913 } 9914 9915 static int 9916 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 9917 { 9918 struct adapter *sc = arg1; 9919 int reg = arg2; 9920 u_int tre; 9921 u_long tp_tick_us, v; 9922 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9923 9924 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 9925 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 9926 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 9927 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 9928 9929 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 9930 tp_tick_us = (cclk_ps << tre) / 1000000; 9931 9932 if (reg == A_TP_INIT_SRTT) 9933 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 9934 else 9935 v = tp_tick_us * t4_read_reg(sc, reg); 9936 9937 return (sysctl_handle_long(oidp, &v, 0, req)); 9938 } 9939 9940 /* 9941 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 9942 * passed to this function. 9943 */ 9944 static int 9945 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 9946 { 9947 struct adapter *sc = arg1; 9948 int idx = arg2; 9949 u_int v; 9950 9951 MPASS(idx >= 0 && idx <= 24); 9952 9953 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 9954 9955 return (sysctl_handle_int(oidp, &v, 0, req)); 9956 } 9957 9958 static int 9959 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 9960 { 9961 struct adapter *sc = arg1; 9962 int idx = arg2; 9963 u_int shift, v, r; 9964 9965 MPASS(idx >= 0 && idx < 16); 9966 9967 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 9968 shift = (idx & 3) << 3; 9969 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 9970 9971 return (sysctl_handle_int(oidp, &v, 0, req)); 9972 } 9973 9974 static int 9975 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 9976 { 9977 struct vi_info *vi = arg1; 9978 struct adapter *sc = vi->adapter; 9979 int idx, rc, i; 9980 struct sge_ofld_rxq *ofld_rxq; 9981 uint8_t v; 9982 9983 idx = vi->ofld_tmr_idx; 9984 9985 rc = sysctl_handle_int(oidp, &idx, 0, req); 9986 if (rc != 0 || req->newptr == NULL) 9987 return (rc); 9988 9989 if (idx < 0 || idx >= SGE_NTIMERS) 9990 return (EINVAL); 9991 9992 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9993 "t4otmr"); 9994 if (rc) 9995 return (rc); 9996 9997 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 9998 for_each_ofld_rxq(vi, i, ofld_rxq) { 9999 #ifdef atomic_store_rel_8 10000 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 10001 #else 10002 ofld_rxq->iq.intr_params = v; 10003 #endif 10004 } 10005 vi->ofld_tmr_idx = idx; 10006 10007 end_synchronized_op(sc, LOCK_HELD); 10008 return (0); 10009 } 10010 10011 static int 10012 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 10013 { 10014 struct vi_info *vi = arg1; 10015 struct adapter *sc = vi->adapter; 10016 int idx, rc; 10017 10018 idx = vi->ofld_pktc_idx; 10019 10020 rc = sysctl_handle_int(oidp, &idx, 0, req); 10021 if (rc != 0 || req->newptr == NULL) 10022 return (rc); 10023 10024 if (idx < -1 || idx >= SGE_NCOUNTERS) 10025 return (EINVAL); 10026 10027 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 10028 "t4opktc"); 10029 if (rc) 10030 return (rc); 10031 10032 if (vi->flags & VI_INIT_DONE) 10033 rc = EBUSY; /* cannot be changed once the queues are created */ 10034 else 10035 vi->ofld_pktc_idx = idx; 10036 10037 end_synchronized_op(sc, LOCK_HELD); 10038 return (rc); 10039 } 10040 #endif 10041 10042 static int 10043 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 10044 { 10045 int rc; 10046 10047 if (cntxt->cid > M_CTXTQID) 10048 return (EINVAL); 10049 10050 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 10051 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 10052 return (EINVAL); 10053 10054 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 10055 if (rc) 10056 return (rc); 10057 10058 if (sc->flags & FW_OK) { 10059 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 10060 &cntxt->data[0]); 10061 if (rc == 0) 10062 goto done; 10063 } 10064 10065 /* 10066 * Read via firmware failed or wasn't even attempted. Read directly via 10067 * the backdoor. 10068 */ 10069 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 10070 done: 10071 end_synchronized_op(sc, 0); 10072 return (rc); 10073 } 10074 10075 static int 10076 load_fw(struct adapter *sc, struct t4_data *fw) 10077 { 10078 int rc; 10079 uint8_t *fw_data; 10080 10081 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 10082 if (rc) 10083 return (rc); 10084 10085 /* 10086 * The firmware, with the sole exception of the memory parity error 10087 * handler, runs from memory and not flash. It is almost always safe to 10088 * install a new firmware on a running system. Just set bit 1 in 10089 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 10090 */ 10091 if (sc->flags & FULL_INIT_DONE && 10092 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 10093 rc = EBUSY; 10094 goto done; 10095 } 10096 10097 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 10098 10099 rc = copyin(fw->data, fw_data, fw->len); 10100 if (rc == 0) 10101 rc = -t4_load_fw(sc, fw_data, fw->len); 10102 10103 free(fw_data, M_CXGBE); 10104 done: 10105 end_synchronized_op(sc, 0); 10106 return (rc); 10107 } 10108 10109 static int 10110 load_cfg(struct adapter *sc, struct t4_data *cfg) 10111 { 10112 int rc; 10113 uint8_t *cfg_data = NULL; 10114 10115 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 10116 if (rc) 10117 return (rc); 10118 10119 if (cfg->len == 0) { 10120 /* clear */ 10121 rc = -t4_load_cfg(sc, NULL, 0); 10122 goto done; 10123 } 10124 10125 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 10126 10127 rc = copyin(cfg->data, cfg_data, cfg->len); 10128 if (rc == 0) 10129 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 10130 10131 free(cfg_data, M_CXGBE); 10132 done: 10133 end_synchronized_op(sc, 0); 10134 return (rc); 10135 } 10136 10137 static int 10138 load_boot(struct adapter *sc, struct t4_bootrom *br) 10139 { 10140 int rc; 10141 uint8_t *br_data = NULL; 10142 u_int offset; 10143 10144 if (br->len > 1024 * 1024) 10145 return (EFBIG); 10146 10147 if (br->pf_offset == 0) { 10148 /* pfidx */ 10149 if (br->pfidx_addr > 7) 10150 return (EINVAL); 10151 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 10152 A_PCIE_PF_EXPROM_OFST))); 10153 } else if (br->pf_offset == 1) { 10154 /* offset */ 10155 offset = G_OFFSET(br->pfidx_addr); 10156 } else { 10157 return (EINVAL); 10158 } 10159 10160 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 10161 if (rc) 10162 return (rc); 10163 10164 if (br->len == 0) { 10165 /* clear */ 10166 rc = -t4_load_boot(sc, NULL, offset, 0); 10167 goto done; 10168 } 10169 10170 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 10171 10172 rc = copyin(br->data, br_data, br->len); 10173 if (rc == 0) 10174 rc = -t4_load_boot(sc, br_data, offset, br->len); 10175 10176 free(br_data, M_CXGBE); 10177 done: 10178 end_synchronized_op(sc, 0); 10179 return (rc); 10180 } 10181 10182 static int 10183 load_bootcfg(struct adapter *sc, struct t4_data *bc) 10184 { 10185 int rc; 10186 uint8_t *bc_data = NULL; 10187 10188 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 10189 if (rc) 10190 return (rc); 10191 10192 if (bc->len == 0) { 10193 /* clear */ 10194 rc = -t4_load_bootcfg(sc, NULL, 0); 10195 goto done; 10196 } 10197 10198 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 10199 10200 rc = copyin(bc->data, bc_data, bc->len); 10201 if (rc == 0) 10202 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 10203 10204 free(bc_data, M_CXGBE); 10205 done: 10206 end_synchronized_op(sc, 0); 10207 return (rc); 10208 } 10209 10210 static int 10211 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 10212 { 10213 int rc; 10214 struct cudbg_init *cudbg; 10215 void *handle, *buf; 10216 10217 /* buf is large, don't block if no memory is available */ 10218 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 10219 if (buf == NULL) 10220 return (ENOMEM); 10221 10222 handle = cudbg_alloc_handle(); 10223 if (handle == NULL) { 10224 rc = ENOMEM; 10225 goto done; 10226 } 10227 10228 cudbg = cudbg_get_init(handle); 10229 cudbg->adap = sc; 10230 cudbg->print = (cudbg_print_cb)printf; 10231 10232 #ifndef notyet 10233 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 10234 __func__, dump->wr_flash, dump->len, dump->data); 10235 #endif 10236 10237 if (dump->wr_flash) 10238 cudbg->use_flash = 1; 10239 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 10240 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 10241 10242 rc = cudbg_collect(handle, buf, &dump->len); 10243 if (rc != 0) 10244 goto done; 10245 10246 rc = copyout(buf, dump->data, dump->len); 10247 done: 10248 cudbg_free_handle(handle); 10249 free(buf, M_CXGBE); 10250 return (rc); 10251 } 10252 10253 static void 10254 free_offload_policy(struct t4_offload_policy *op) 10255 { 10256 struct offload_rule *r; 10257 int i; 10258 10259 if (op == NULL) 10260 return; 10261 10262 r = &op->rule[0]; 10263 for (i = 0; i < op->nrules; i++, r++) { 10264 free(r->bpf_prog.bf_insns, M_CXGBE); 10265 } 10266 free(op->rule, M_CXGBE); 10267 free(op, M_CXGBE); 10268 } 10269 10270 static int 10271 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 10272 { 10273 int i, rc, len; 10274 struct t4_offload_policy *op, *old; 10275 struct bpf_program *bf; 10276 const struct offload_settings *s; 10277 struct offload_rule *r; 10278 void *u; 10279 10280 if (!is_offload(sc)) 10281 return (ENODEV); 10282 10283 if (uop->nrules == 0) { 10284 /* Delete installed policies. */ 10285 op = NULL; 10286 goto set_policy; 10287 } else if (uop->nrules > 256) { /* arbitrary */ 10288 return (E2BIG); 10289 } 10290 10291 /* Copy userspace offload policy to kernel */ 10292 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 10293 op->nrules = uop->nrules; 10294 len = op->nrules * sizeof(struct offload_rule); 10295 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 10296 rc = copyin(uop->rule, op->rule, len); 10297 if (rc) { 10298 free(op->rule, M_CXGBE); 10299 free(op, M_CXGBE); 10300 return (rc); 10301 } 10302 10303 r = &op->rule[0]; 10304 for (i = 0; i < op->nrules; i++, r++) { 10305 10306 /* Validate open_type */ 10307 if (r->open_type != OPEN_TYPE_LISTEN && 10308 r->open_type != OPEN_TYPE_ACTIVE && 10309 r->open_type != OPEN_TYPE_PASSIVE && 10310 r->open_type != OPEN_TYPE_DONTCARE) { 10311 error: 10312 /* 10313 * Rules 0 to i have malloc'd filters that need to be 10314 * freed. Rules i+1 to nrules have userspace pointers 10315 * and should be left alone. 10316 */ 10317 op->nrules = i; 10318 free_offload_policy(op); 10319 return (rc); 10320 } 10321 10322 /* Validate settings */ 10323 s = &r->settings; 10324 if ((s->offload != 0 && s->offload != 1) || 10325 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 10326 s->sched_class < -1 || 10327 s->sched_class >= sc->chip_params->nsched_cls) { 10328 rc = EINVAL; 10329 goto error; 10330 } 10331 10332 bf = &r->bpf_prog; 10333 u = bf->bf_insns; /* userspace ptr */ 10334 bf->bf_insns = NULL; 10335 if (bf->bf_len == 0) { 10336 /* legal, matches everything */ 10337 continue; 10338 } 10339 len = bf->bf_len * sizeof(*bf->bf_insns); 10340 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 10341 rc = copyin(u, bf->bf_insns, len); 10342 if (rc != 0) 10343 goto error; 10344 10345 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 10346 rc = EINVAL; 10347 goto error; 10348 } 10349 } 10350 set_policy: 10351 rw_wlock(&sc->policy_lock); 10352 old = sc->policy; 10353 sc->policy = op; 10354 rw_wunlock(&sc->policy_lock); 10355 free_offload_policy(old); 10356 10357 return (0); 10358 } 10359 10360 #define MAX_READ_BUF_SIZE (128 * 1024) 10361 static int 10362 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 10363 { 10364 uint32_t addr, remaining, n; 10365 uint32_t *buf; 10366 int rc; 10367 uint8_t *dst; 10368 10369 rc = validate_mem_range(sc, mr->addr, mr->len); 10370 if (rc != 0) 10371 return (rc); 10372 10373 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 10374 addr = mr->addr; 10375 remaining = mr->len; 10376 dst = (void *)mr->data; 10377 10378 while (remaining) { 10379 n = min(remaining, MAX_READ_BUF_SIZE); 10380 read_via_memwin(sc, 2, addr, buf, n); 10381 10382 rc = copyout(buf, dst, n); 10383 if (rc != 0) 10384 break; 10385 10386 dst += n; 10387 remaining -= n; 10388 addr += n; 10389 } 10390 10391 free(buf, M_CXGBE); 10392 return (rc); 10393 } 10394 #undef MAX_READ_BUF_SIZE 10395 10396 static int 10397 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 10398 { 10399 int rc; 10400 10401 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 10402 return (EINVAL); 10403 10404 if (i2cd->len > sizeof(i2cd->data)) 10405 return (EFBIG); 10406 10407 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 10408 if (rc) 10409 return (rc); 10410 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 10411 i2cd->offset, i2cd->len, &i2cd->data[0]); 10412 end_synchronized_op(sc, 0); 10413 10414 return (rc); 10415 } 10416 10417 static int 10418 clear_stats(struct adapter *sc, u_int port_id) 10419 { 10420 int i, v, chan_map; 10421 struct port_info *pi; 10422 struct vi_info *vi; 10423 struct sge_rxq *rxq; 10424 struct sge_txq *txq; 10425 struct sge_wrq *wrq; 10426 #ifdef TCP_OFFLOAD 10427 struct sge_ofld_rxq *ofld_rxq; 10428 #endif 10429 10430 if (port_id >= sc->params.nports) 10431 return (EINVAL); 10432 pi = sc->port[port_id]; 10433 if (pi == NULL) 10434 return (EIO); 10435 10436 /* MAC stats */ 10437 t4_clr_port_stats(sc, pi->tx_chan); 10438 pi->tx_parse_error = 0; 10439 pi->tnl_cong_drops = 0; 10440 mtx_lock(&sc->reg_lock); 10441 for_each_vi(pi, v, vi) { 10442 if (vi->flags & VI_INIT_DONE) 10443 t4_clr_vi_stats(sc, vi->vin); 10444 } 10445 chan_map = pi->rx_e_chan_map; 10446 v = 0; /* reuse */ 10447 while (chan_map) { 10448 i = ffs(chan_map) - 1; 10449 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 10450 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 10451 chan_map &= ~(1 << i); 10452 } 10453 mtx_unlock(&sc->reg_lock); 10454 10455 /* 10456 * Since this command accepts a port, clear stats for 10457 * all VIs on this port. 10458 */ 10459 for_each_vi(pi, v, vi) { 10460 if (vi->flags & VI_INIT_DONE) { 10461 10462 for_each_rxq(vi, i, rxq) { 10463 #if defined(INET) || defined(INET6) 10464 rxq->lro.lro_queued = 0; 10465 rxq->lro.lro_flushed = 0; 10466 #endif 10467 rxq->rxcsum = 0; 10468 rxq->vlan_extraction = 0; 10469 rxq->vxlan_rxcsum = 0; 10470 10471 rxq->fl.cl_allocated = 0; 10472 rxq->fl.cl_recycled = 0; 10473 rxq->fl.cl_fast_recycled = 0; 10474 } 10475 10476 for_each_txq(vi, i, txq) { 10477 txq->txcsum = 0; 10478 txq->tso_wrs = 0; 10479 txq->vlan_insertion = 0; 10480 txq->imm_wrs = 0; 10481 txq->sgl_wrs = 0; 10482 txq->txpkt_wrs = 0; 10483 txq->txpkts0_wrs = 0; 10484 txq->txpkts1_wrs = 0; 10485 txq->txpkts0_pkts = 0; 10486 txq->txpkts1_pkts = 0; 10487 txq->raw_wrs = 0; 10488 txq->vxlan_tso_wrs = 0; 10489 txq->vxlan_txcsum = 0; 10490 txq->kern_tls_records = 0; 10491 txq->kern_tls_short = 0; 10492 txq->kern_tls_partial = 0; 10493 txq->kern_tls_full = 0; 10494 txq->kern_tls_octets = 0; 10495 txq->kern_tls_waste = 0; 10496 txq->kern_tls_options = 0; 10497 txq->kern_tls_header = 0; 10498 txq->kern_tls_fin = 0; 10499 txq->kern_tls_fin_short = 0; 10500 txq->kern_tls_cbc = 0; 10501 txq->kern_tls_gcm = 0; 10502 mp_ring_reset_stats(txq->r); 10503 } 10504 10505 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10506 for_each_ofld_txq(vi, i, wrq) { 10507 wrq->tx_wrs_direct = 0; 10508 wrq->tx_wrs_copied = 0; 10509 } 10510 #endif 10511 #ifdef TCP_OFFLOAD 10512 for_each_ofld_rxq(vi, i, ofld_rxq) { 10513 ofld_rxq->fl.cl_allocated = 0; 10514 ofld_rxq->fl.cl_recycled = 0; 10515 ofld_rxq->fl.cl_fast_recycled = 0; 10516 } 10517 #endif 10518 10519 if (IS_MAIN_VI(vi)) { 10520 wrq = &sc->sge.ctrlq[pi->port_id]; 10521 wrq->tx_wrs_direct = 0; 10522 wrq->tx_wrs_copied = 0; 10523 } 10524 } 10525 } 10526 10527 return (0); 10528 } 10529 10530 int 10531 t4_os_find_pci_capability(struct adapter *sc, int cap) 10532 { 10533 int i; 10534 10535 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 10536 } 10537 10538 int 10539 t4_os_pci_save_state(struct adapter *sc) 10540 { 10541 device_t dev; 10542 struct pci_devinfo *dinfo; 10543 10544 dev = sc->dev; 10545 dinfo = device_get_ivars(dev); 10546 10547 pci_cfg_save(dev, dinfo, 0); 10548 return (0); 10549 } 10550 10551 int 10552 t4_os_pci_restore_state(struct adapter *sc) 10553 { 10554 device_t dev; 10555 struct pci_devinfo *dinfo; 10556 10557 dev = sc->dev; 10558 dinfo = device_get_ivars(dev); 10559 10560 pci_cfg_restore(dev, dinfo); 10561 return (0); 10562 } 10563 10564 void 10565 t4_os_portmod_changed(struct port_info *pi) 10566 { 10567 struct adapter *sc = pi->adapter; 10568 struct vi_info *vi; 10569 struct ifnet *ifp; 10570 static const char *mod_str[] = { 10571 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 10572 }; 10573 10574 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 10575 ("%s: port_type %u", __func__, pi->port_type)); 10576 10577 vi = &pi->vi[0]; 10578 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 10579 PORT_LOCK(pi); 10580 build_medialist(pi); 10581 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 10582 fixup_link_config(pi); 10583 apply_link_config(pi); 10584 } 10585 PORT_UNLOCK(pi); 10586 end_synchronized_op(sc, LOCK_HELD); 10587 } 10588 10589 ifp = vi->ifp; 10590 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 10591 if_printf(ifp, "transceiver unplugged.\n"); 10592 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 10593 if_printf(ifp, "unknown transceiver inserted.\n"); 10594 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 10595 if_printf(ifp, "unsupported transceiver inserted.\n"); 10596 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 10597 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 10598 port_top_speed(pi), mod_str[pi->mod_type]); 10599 } else { 10600 if_printf(ifp, "transceiver (type %d) inserted.\n", 10601 pi->mod_type); 10602 } 10603 } 10604 10605 void 10606 t4_os_link_changed(struct port_info *pi) 10607 { 10608 struct vi_info *vi; 10609 struct ifnet *ifp; 10610 struct link_config *lc; 10611 int v; 10612 10613 PORT_LOCK_ASSERT_OWNED(pi); 10614 10615 for_each_vi(pi, v, vi) { 10616 ifp = vi->ifp; 10617 if (ifp == NULL) 10618 continue; 10619 10620 lc = &pi->link_cfg; 10621 if (lc->link_ok) { 10622 ifp->if_baudrate = IF_Mbps(lc->speed); 10623 if_link_state_change(ifp, LINK_STATE_UP); 10624 } else { 10625 if_link_state_change(ifp, LINK_STATE_DOWN); 10626 } 10627 } 10628 } 10629 10630 void 10631 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 10632 { 10633 struct adapter *sc; 10634 10635 sx_slock(&t4_list_lock); 10636 SLIST_FOREACH(sc, &t4_list, link) { 10637 /* 10638 * func should not make any assumptions about what state sc is 10639 * in - the only guarantee is that sc->sc_lock is a valid lock. 10640 */ 10641 func(sc, arg); 10642 } 10643 sx_sunlock(&t4_list_lock); 10644 } 10645 10646 static int 10647 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 10648 struct thread *td) 10649 { 10650 int rc; 10651 struct adapter *sc = dev->si_drv1; 10652 10653 rc = priv_check(td, PRIV_DRIVER); 10654 if (rc != 0) 10655 return (rc); 10656 10657 switch (cmd) { 10658 case CHELSIO_T4_GETREG: { 10659 struct t4_reg *edata = (struct t4_reg *)data; 10660 10661 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 10662 return (EFAULT); 10663 10664 if (edata->size == 4) 10665 edata->val = t4_read_reg(sc, edata->addr); 10666 else if (edata->size == 8) 10667 edata->val = t4_read_reg64(sc, edata->addr); 10668 else 10669 return (EINVAL); 10670 10671 break; 10672 } 10673 case CHELSIO_T4_SETREG: { 10674 struct t4_reg *edata = (struct t4_reg *)data; 10675 10676 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 10677 return (EFAULT); 10678 10679 if (edata->size == 4) { 10680 if (edata->val & 0xffffffff00000000) 10681 return (EINVAL); 10682 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 10683 } else if (edata->size == 8) 10684 t4_write_reg64(sc, edata->addr, edata->val); 10685 else 10686 return (EINVAL); 10687 break; 10688 } 10689 case CHELSIO_T4_REGDUMP: { 10690 struct t4_regdump *regs = (struct t4_regdump *)data; 10691 int reglen = t4_get_regs_len(sc); 10692 uint8_t *buf; 10693 10694 if (regs->len < reglen) { 10695 regs->len = reglen; /* hint to the caller */ 10696 return (ENOBUFS); 10697 } 10698 10699 regs->len = reglen; 10700 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 10701 get_regs(sc, regs, buf); 10702 rc = copyout(buf, regs->data, reglen); 10703 free(buf, M_CXGBE); 10704 break; 10705 } 10706 case CHELSIO_T4_GET_FILTER_MODE: 10707 rc = get_filter_mode(sc, (uint32_t *)data); 10708 break; 10709 case CHELSIO_T4_SET_FILTER_MODE: 10710 rc = set_filter_mode(sc, *(uint32_t *)data); 10711 break; 10712 case CHELSIO_T4_GET_FILTER: 10713 rc = get_filter(sc, (struct t4_filter *)data); 10714 break; 10715 case CHELSIO_T4_SET_FILTER: 10716 rc = set_filter(sc, (struct t4_filter *)data); 10717 break; 10718 case CHELSIO_T4_DEL_FILTER: 10719 rc = del_filter(sc, (struct t4_filter *)data); 10720 break; 10721 case CHELSIO_T4_GET_SGE_CONTEXT: 10722 rc = get_sge_context(sc, (struct t4_sge_context *)data); 10723 break; 10724 case CHELSIO_T4_LOAD_FW: 10725 rc = load_fw(sc, (struct t4_data *)data); 10726 break; 10727 case CHELSIO_T4_GET_MEM: 10728 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 10729 break; 10730 case CHELSIO_T4_GET_I2C: 10731 rc = read_i2c(sc, (struct t4_i2c_data *)data); 10732 break; 10733 case CHELSIO_T4_CLEAR_STATS: 10734 rc = clear_stats(sc, *(uint32_t *)data); 10735 break; 10736 case CHELSIO_T4_SCHED_CLASS: 10737 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 10738 break; 10739 case CHELSIO_T4_SCHED_QUEUE: 10740 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 10741 break; 10742 case CHELSIO_T4_GET_TRACER: 10743 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 10744 break; 10745 case CHELSIO_T4_SET_TRACER: 10746 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 10747 break; 10748 case CHELSIO_T4_LOAD_CFG: 10749 rc = load_cfg(sc, (struct t4_data *)data); 10750 break; 10751 case CHELSIO_T4_LOAD_BOOT: 10752 rc = load_boot(sc, (struct t4_bootrom *)data); 10753 break; 10754 case CHELSIO_T4_LOAD_BOOTCFG: 10755 rc = load_bootcfg(sc, (struct t4_data *)data); 10756 break; 10757 case CHELSIO_T4_CUDBG_DUMP: 10758 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 10759 break; 10760 case CHELSIO_T4_SET_OFLD_POLICY: 10761 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 10762 break; 10763 default: 10764 rc = ENOTTY; 10765 } 10766 10767 return (rc); 10768 } 10769 10770 #ifdef TCP_OFFLOAD 10771 static int 10772 toe_capability(struct vi_info *vi, int enable) 10773 { 10774 int rc; 10775 struct port_info *pi = vi->pi; 10776 struct adapter *sc = pi->adapter; 10777 10778 ASSERT_SYNCHRONIZED_OP(sc); 10779 10780 if (!is_offload(sc)) 10781 return (ENODEV); 10782 10783 if (enable) { 10784 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 10785 /* TOE is already enabled. */ 10786 return (0); 10787 } 10788 10789 /* 10790 * We need the port's queues around so that we're able to send 10791 * and receive CPLs to/from the TOE even if the ifnet for this 10792 * port has never been UP'd administratively. 10793 */ 10794 if (!(vi->flags & VI_INIT_DONE)) { 10795 rc = vi_full_init(vi); 10796 if (rc) 10797 return (rc); 10798 } 10799 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 10800 rc = vi_full_init(&pi->vi[0]); 10801 if (rc) 10802 return (rc); 10803 } 10804 10805 if (isset(&sc->offload_map, pi->port_id)) { 10806 /* TOE is enabled on another VI of this port. */ 10807 pi->uld_vis++; 10808 return (0); 10809 } 10810 10811 if (!uld_active(sc, ULD_TOM)) { 10812 rc = t4_activate_uld(sc, ULD_TOM); 10813 if (rc == EAGAIN) { 10814 log(LOG_WARNING, 10815 "You must kldload t4_tom.ko before trying " 10816 "to enable TOE on a cxgbe interface.\n"); 10817 } 10818 if (rc != 0) 10819 return (rc); 10820 KASSERT(sc->tom_softc != NULL, 10821 ("%s: TOM activated but softc NULL", __func__)); 10822 KASSERT(uld_active(sc, ULD_TOM), 10823 ("%s: TOM activated but flag not set", __func__)); 10824 } 10825 10826 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 10827 if (!uld_active(sc, ULD_IWARP)) 10828 (void) t4_activate_uld(sc, ULD_IWARP); 10829 if (!uld_active(sc, ULD_ISCSI)) 10830 (void) t4_activate_uld(sc, ULD_ISCSI); 10831 10832 pi->uld_vis++; 10833 setbit(&sc->offload_map, pi->port_id); 10834 } else { 10835 pi->uld_vis--; 10836 10837 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 10838 return (0); 10839 10840 KASSERT(uld_active(sc, ULD_TOM), 10841 ("%s: TOM never initialized?", __func__)); 10842 clrbit(&sc->offload_map, pi->port_id); 10843 } 10844 10845 return (0); 10846 } 10847 10848 /* 10849 * Add an upper layer driver to the global list. 10850 */ 10851 int 10852 t4_register_uld(struct uld_info *ui) 10853 { 10854 int rc = 0; 10855 struct uld_info *u; 10856 10857 sx_xlock(&t4_uld_list_lock); 10858 SLIST_FOREACH(u, &t4_uld_list, link) { 10859 if (u->uld_id == ui->uld_id) { 10860 rc = EEXIST; 10861 goto done; 10862 } 10863 } 10864 10865 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 10866 ui->refcount = 0; 10867 done: 10868 sx_xunlock(&t4_uld_list_lock); 10869 return (rc); 10870 } 10871 10872 int 10873 t4_unregister_uld(struct uld_info *ui) 10874 { 10875 int rc = EINVAL; 10876 struct uld_info *u; 10877 10878 sx_xlock(&t4_uld_list_lock); 10879 10880 SLIST_FOREACH(u, &t4_uld_list, link) { 10881 if (u == ui) { 10882 if (ui->refcount > 0) { 10883 rc = EBUSY; 10884 goto done; 10885 } 10886 10887 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 10888 rc = 0; 10889 goto done; 10890 } 10891 } 10892 done: 10893 sx_xunlock(&t4_uld_list_lock); 10894 return (rc); 10895 } 10896 10897 int 10898 t4_activate_uld(struct adapter *sc, int id) 10899 { 10900 int rc; 10901 struct uld_info *ui; 10902 10903 ASSERT_SYNCHRONIZED_OP(sc); 10904 10905 if (id < 0 || id > ULD_MAX) 10906 return (EINVAL); 10907 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 10908 10909 sx_slock(&t4_uld_list_lock); 10910 10911 SLIST_FOREACH(ui, &t4_uld_list, link) { 10912 if (ui->uld_id == id) { 10913 if (!(sc->flags & FULL_INIT_DONE)) { 10914 rc = adapter_full_init(sc); 10915 if (rc != 0) 10916 break; 10917 } 10918 10919 rc = ui->activate(sc); 10920 if (rc == 0) { 10921 setbit(&sc->active_ulds, id); 10922 ui->refcount++; 10923 } 10924 break; 10925 } 10926 } 10927 10928 sx_sunlock(&t4_uld_list_lock); 10929 10930 return (rc); 10931 } 10932 10933 int 10934 t4_deactivate_uld(struct adapter *sc, int id) 10935 { 10936 int rc; 10937 struct uld_info *ui; 10938 10939 ASSERT_SYNCHRONIZED_OP(sc); 10940 10941 if (id < 0 || id > ULD_MAX) 10942 return (EINVAL); 10943 rc = ENXIO; 10944 10945 sx_slock(&t4_uld_list_lock); 10946 10947 SLIST_FOREACH(ui, &t4_uld_list, link) { 10948 if (ui->uld_id == id) { 10949 rc = ui->deactivate(sc); 10950 if (rc == 0) { 10951 clrbit(&sc->active_ulds, id); 10952 ui->refcount--; 10953 } 10954 break; 10955 } 10956 } 10957 10958 sx_sunlock(&t4_uld_list_lock); 10959 10960 return (rc); 10961 } 10962 10963 static void 10964 t4_async_event(void *arg, int n) 10965 { 10966 struct uld_info *ui; 10967 struct adapter *sc = (struct adapter *)arg; 10968 10969 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4async") != 0) 10970 return; 10971 sx_slock(&t4_uld_list_lock); 10972 SLIST_FOREACH(ui, &t4_uld_list, link) { 10973 if (ui->uld_id == ULD_IWARP) { 10974 ui->async_event(sc); 10975 break; 10976 } 10977 } 10978 sx_sunlock(&t4_uld_list_lock); 10979 end_synchronized_op(sc, 0); 10980 } 10981 10982 int 10983 uld_active(struct adapter *sc, int uld_id) 10984 { 10985 10986 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 10987 10988 return (isset(&sc->active_ulds, uld_id)); 10989 } 10990 #endif 10991 10992 /* 10993 * t = ptr to tunable. 10994 * nc = number of CPUs. 10995 * c = compiled in default for that tunable. 10996 */ 10997 static void 10998 calculate_nqueues(int *t, int nc, const int c) 10999 { 11000 int nq; 11001 11002 if (*t > 0) 11003 return; 11004 nq = *t < 0 ? -*t : c; 11005 *t = min(nc, nq); 11006 } 11007 11008 /* 11009 * Come up with reasonable defaults for some of the tunables, provided they're 11010 * not set by the user (in which case we'll use the values as is). 11011 */ 11012 static void 11013 tweak_tunables(void) 11014 { 11015 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 11016 11017 if (t4_ntxq < 1) { 11018 #ifdef RSS 11019 t4_ntxq = rss_getnumbuckets(); 11020 #else 11021 calculate_nqueues(&t4_ntxq, nc, NTXQ); 11022 #endif 11023 } 11024 11025 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 11026 11027 if (t4_nrxq < 1) { 11028 #ifdef RSS 11029 t4_nrxq = rss_getnumbuckets(); 11030 #else 11031 calculate_nqueues(&t4_nrxq, nc, NRXQ); 11032 #endif 11033 } 11034 11035 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 11036 11037 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 11038 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 11039 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 11040 #endif 11041 #ifdef TCP_OFFLOAD 11042 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 11043 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 11044 #endif 11045 11046 #if defined(TCP_OFFLOAD) || defined(KERN_TLS) 11047 if (t4_toecaps_allowed == -1) 11048 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 11049 #else 11050 if (t4_toecaps_allowed == -1) 11051 t4_toecaps_allowed = 0; 11052 #endif 11053 11054 #ifdef TCP_OFFLOAD 11055 if (t4_rdmacaps_allowed == -1) { 11056 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 11057 FW_CAPS_CONFIG_RDMA_RDMAC; 11058 } 11059 11060 if (t4_iscsicaps_allowed == -1) { 11061 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 11062 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 11063 FW_CAPS_CONFIG_ISCSI_T10DIF; 11064 } 11065 11066 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 11067 t4_tmr_idx_ofld = TMR_IDX_OFLD; 11068 11069 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 11070 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 11071 #else 11072 if (t4_rdmacaps_allowed == -1) 11073 t4_rdmacaps_allowed = 0; 11074 11075 if (t4_iscsicaps_allowed == -1) 11076 t4_iscsicaps_allowed = 0; 11077 #endif 11078 11079 #ifdef DEV_NETMAP 11080 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ); 11081 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ); 11082 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 11083 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 11084 #endif 11085 11086 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 11087 t4_tmr_idx = TMR_IDX; 11088 11089 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 11090 t4_pktc_idx = PKTC_IDX; 11091 11092 if (t4_qsize_txq < 128) 11093 t4_qsize_txq = 128; 11094 11095 if (t4_qsize_rxq < 128) 11096 t4_qsize_rxq = 128; 11097 while (t4_qsize_rxq & 7) 11098 t4_qsize_rxq++; 11099 11100 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 11101 11102 /* 11103 * Number of VIs to create per-port. The first VI is the "main" regular 11104 * VI for the port. The rest are additional virtual interfaces on the 11105 * same physical port. Note that the main VI does not have native 11106 * netmap support but the extra VIs do. 11107 * 11108 * Limit the number of VIs per port to the number of available 11109 * MAC addresses per port. 11110 */ 11111 if (t4_num_vis < 1) 11112 t4_num_vis = 1; 11113 if (t4_num_vis > nitems(vi_mac_funcs)) { 11114 t4_num_vis = nitems(vi_mac_funcs); 11115 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 11116 } 11117 11118 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 11119 pcie_relaxed_ordering = 1; 11120 #if defined(__i386__) || defined(__amd64__) 11121 if (cpu_vendor_id == CPU_VENDOR_INTEL) 11122 pcie_relaxed_ordering = 0; 11123 #endif 11124 } 11125 } 11126 11127 #ifdef DDB 11128 static void 11129 t4_dump_tcb(struct adapter *sc, int tid) 11130 { 11131 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 11132 11133 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 11134 save = t4_read_reg(sc, reg); 11135 base = sc->memwin[2].mw_base; 11136 11137 /* Dump TCB for the tid */ 11138 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 11139 tcb_addr += tid * TCB_SIZE; 11140 11141 if (is_t4(sc)) { 11142 pf = 0; 11143 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 11144 } else { 11145 pf = V_PFNUM(sc->pf); 11146 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 11147 } 11148 t4_write_reg(sc, reg, win_pos | pf); 11149 t4_read_reg(sc, reg); 11150 11151 off = tcb_addr - win_pos; 11152 for (i = 0; i < 4; i++) { 11153 uint32_t buf[8]; 11154 for (j = 0; j < 8; j++, off += 4) 11155 buf[j] = htonl(t4_read_reg(sc, base + off)); 11156 11157 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 11158 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 11159 buf[7]); 11160 } 11161 11162 t4_write_reg(sc, reg, save); 11163 t4_read_reg(sc, reg); 11164 } 11165 11166 static void 11167 t4_dump_devlog(struct adapter *sc) 11168 { 11169 struct devlog_params *dparams = &sc->params.devlog; 11170 struct fw_devlog_e e; 11171 int i, first, j, m, nentries, rc; 11172 uint64_t ftstamp = UINT64_MAX; 11173 11174 if (dparams->start == 0) { 11175 db_printf("devlog params not valid\n"); 11176 return; 11177 } 11178 11179 nentries = dparams->size / sizeof(struct fw_devlog_e); 11180 m = fwmtype_to_hwmtype(dparams->memtype); 11181 11182 /* Find the first entry. */ 11183 first = -1; 11184 for (i = 0; i < nentries && !db_pager_quit; i++) { 11185 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 11186 sizeof(e), (void *)&e); 11187 if (rc != 0) 11188 break; 11189 11190 if (e.timestamp == 0) 11191 break; 11192 11193 e.timestamp = be64toh(e.timestamp); 11194 if (e.timestamp < ftstamp) { 11195 ftstamp = e.timestamp; 11196 first = i; 11197 } 11198 } 11199 11200 if (first == -1) 11201 return; 11202 11203 i = first; 11204 do { 11205 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 11206 sizeof(e), (void *)&e); 11207 if (rc != 0) 11208 return; 11209 11210 if (e.timestamp == 0) 11211 return; 11212 11213 e.timestamp = be64toh(e.timestamp); 11214 e.seqno = be32toh(e.seqno); 11215 for (j = 0; j < 8; j++) 11216 e.params[j] = be32toh(e.params[j]); 11217 11218 db_printf("%10d %15ju %8s %8s ", 11219 e.seqno, e.timestamp, 11220 (e.level < nitems(devlog_level_strings) ? 11221 devlog_level_strings[e.level] : "UNKNOWN"), 11222 (e.facility < nitems(devlog_facility_strings) ? 11223 devlog_facility_strings[e.facility] : "UNKNOWN")); 11224 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 11225 e.params[3], e.params[4], e.params[5], e.params[6], 11226 e.params[7]); 11227 11228 if (++i == nentries) 11229 i = 0; 11230 } while (i != first && !db_pager_quit); 11231 } 11232 11233 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 11234 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 11235 11236 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 11237 { 11238 device_t dev; 11239 int t; 11240 bool valid; 11241 11242 valid = false; 11243 t = db_read_token(); 11244 if (t == tIDENT) { 11245 dev = device_lookup_by_name(db_tok_string); 11246 valid = true; 11247 } 11248 db_skip_to_eol(); 11249 if (!valid) { 11250 db_printf("usage: show t4 devlog <nexus>\n"); 11251 return; 11252 } 11253 11254 if (dev == NULL) { 11255 db_printf("device not found\n"); 11256 return; 11257 } 11258 11259 t4_dump_devlog(device_get_softc(dev)); 11260 } 11261 11262 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 11263 { 11264 device_t dev; 11265 int radix, tid, t; 11266 bool valid; 11267 11268 valid = false; 11269 radix = db_radix; 11270 db_radix = 10; 11271 t = db_read_token(); 11272 if (t == tIDENT) { 11273 dev = device_lookup_by_name(db_tok_string); 11274 t = db_read_token(); 11275 if (t == tNUMBER) { 11276 tid = db_tok_number; 11277 valid = true; 11278 } 11279 } 11280 db_radix = radix; 11281 db_skip_to_eol(); 11282 if (!valid) { 11283 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 11284 return; 11285 } 11286 11287 if (dev == NULL) { 11288 db_printf("device not found\n"); 11289 return; 11290 } 11291 if (tid < 0) { 11292 db_printf("invalid tid\n"); 11293 return; 11294 } 11295 11296 t4_dump_tcb(device_get_softc(dev), tid); 11297 } 11298 #endif 11299 11300 static eventhandler_tag vxlan_start_evtag; 11301 static eventhandler_tag vxlan_stop_evtag; 11302 11303 struct vxlan_evargs { 11304 struct ifnet *ifp; 11305 uint16_t port; 11306 }; 11307 11308 static void 11309 t4_vxlan_start(struct adapter *sc, void *arg) 11310 { 11311 struct vxlan_evargs *v = arg; 11312 struct port_info *pi; 11313 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 11314 int i, rc; 11315 11316 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 11317 return; 11318 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0) 11319 return; 11320 11321 if (sc->vxlan_refcount == 0) { 11322 sc->vxlan_port = v->port; 11323 sc->vxlan_refcount = 1; 11324 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, 11325 V_VXLAN(v->port) | F_VXLAN_EN); 11326 for_each_port(sc, i) { 11327 pi = sc->port[i]; 11328 if (pi->vxlan_tcam_entry == true) 11329 continue; 11330 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, 11331 match_all_mac, match_all_mac, 11332 sc->rawf_base + pi->port_id, 1, pi->port_id, true); 11333 if (rc < 0) { 11334 rc = -rc; 11335 log(LOG_ERR, 11336 "%s: failed to add VXLAN TCAM entry: %d.\n", 11337 device_get_name(pi->vi[0].dev), rc); 11338 } else { 11339 MPASS(rc == sc->rawf_base + pi->port_id); 11340 rc = 0; 11341 pi->vxlan_tcam_entry = true; 11342 } 11343 } 11344 } else if (sc->vxlan_port == v->port) { 11345 sc->vxlan_refcount++; 11346 } else { 11347 log(LOG_ERR, "%s: VXLAN already configured on port %d; " 11348 "ignoring attempt to configure it on port %d\n", 11349 device_get_nameunit(sc->dev), sc->vxlan_port, v->port); 11350 } 11351 end_synchronized_op(sc, 0); 11352 } 11353 11354 static void 11355 t4_vxlan_stop(struct adapter *sc, void *arg) 11356 { 11357 struct vxlan_evargs *v = arg; 11358 11359 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 11360 return; 11361 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0) 11362 return; 11363 11364 /* 11365 * VXLANs may have been configured before the driver was loaded so we 11366 * may see more stops than starts. This is not handled cleanly but at 11367 * least we keep the refcount sane. 11368 */ 11369 if (sc->vxlan_port != v->port) 11370 goto done; 11371 if (sc->vxlan_refcount == 0) { 11372 log(LOG_ERR, 11373 "%s: VXLAN operation on port %d was stopped earlier; " 11374 "ignoring attempt to stop it again.\n", 11375 device_get_nameunit(sc->dev), sc->vxlan_port); 11376 } else if (--sc->vxlan_refcount == 0) { 11377 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0); 11378 } 11379 done: 11380 end_synchronized_op(sc, 0); 11381 } 11382 11383 static void 11384 t4_vxlan_start_handler(void *arg __unused, struct ifnet *ifp, 11385 sa_family_t family, u_int port) 11386 { 11387 struct vxlan_evargs v; 11388 11389 MPASS(family == AF_INET || family == AF_INET6); 11390 v.ifp = ifp; 11391 v.port = port; 11392 11393 t4_iterate(t4_vxlan_start, &v); 11394 } 11395 11396 static void 11397 t4_vxlan_stop_handler(void *arg __unused, struct ifnet *ifp, sa_family_t family, 11398 u_int port) 11399 { 11400 struct vxlan_evargs v; 11401 11402 MPASS(family == AF_INET || family == AF_INET6); 11403 v.ifp = ifp; 11404 v.port = port; 11405 11406 t4_iterate(t4_vxlan_stop, &v); 11407 } 11408 11409 11410 static struct sx mlu; /* mod load unload */ 11411 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 11412 11413 static int 11414 mod_event(module_t mod, int cmd, void *arg) 11415 { 11416 int rc = 0; 11417 static int loaded = 0; 11418 11419 switch (cmd) { 11420 case MOD_LOAD: 11421 sx_xlock(&mlu); 11422 if (loaded++ == 0) { 11423 t4_sge_modload(); 11424 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 11425 t4_filter_rpl, CPL_COOKIE_FILTER); 11426 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 11427 do_l2t_write_rpl, CPL_COOKIE_FILTER); 11428 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 11429 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 11430 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 11431 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 11432 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 11433 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 11434 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 11435 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 11436 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 11437 do_smt_write_rpl); 11438 sx_init(&t4_list_lock, "T4/T5 adapters"); 11439 SLIST_INIT(&t4_list); 11440 callout_init(&fatal_callout, 1); 11441 #ifdef TCP_OFFLOAD 11442 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 11443 SLIST_INIT(&t4_uld_list); 11444 #endif 11445 #ifdef INET6 11446 t4_clip_modload(); 11447 #endif 11448 #ifdef KERN_TLS 11449 t6_ktls_modload(); 11450 #endif 11451 t4_tracer_modload(); 11452 tweak_tunables(); 11453 vxlan_start_evtag = 11454 EVENTHANDLER_REGISTER(vxlan_start, 11455 t4_vxlan_start_handler, NULL, 11456 EVENTHANDLER_PRI_ANY); 11457 vxlan_stop_evtag = 11458 EVENTHANDLER_REGISTER(vxlan_stop, 11459 t4_vxlan_stop_handler, NULL, 11460 EVENTHANDLER_PRI_ANY); 11461 } 11462 sx_xunlock(&mlu); 11463 break; 11464 11465 case MOD_UNLOAD: 11466 sx_xlock(&mlu); 11467 if (--loaded == 0) { 11468 int tries; 11469 11470 sx_slock(&t4_list_lock); 11471 if (!SLIST_EMPTY(&t4_list)) { 11472 rc = EBUSY; 11473 sx_sunlock(&t4_list_lock); 11474 goto done_unload; 11475 } 11476 #ifdef TCP_OFFLOAD 11477 sx_slock(&t4_uld_list_lock); 11478 if (!SLIST_EMPTY(&t4_uld_list)) { 11479 rc = EBUSY; 11480 sx_sunlock(&t4_uld_list_lock); 11481 sx_sunlock(&t4_list_lock); 11482 goto done_unload; 11483 } 11484 #endif 11485 tries = 0; 11486 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 11487 uprintf("%ju clusters with custom free routine " 11488 "still is use.\n", t4_sge_extfree_refs()); 11489 pause("t4unload", 2 * hz); 11490 } 11491 #ifdef TCP_OFFLOAD 11492 sx_sunlock(&t4_uld_list_lock); 11493 #endif 11494 sx_sunlock(&t4_list_lock); 11495 11496 if (t4_sge_extfree_refs() == 0) { 11497 EVENTHANDLER_DEREGISTER(vxlan_start, 11498 vxlan_start_evtag); 11499 EVENTHANDLER_DEREGISTER(vxlan_stop, 11500 vxlan_stop_evtag); 11501 t4_tracer_modunload(); 11502 #ifdef KERN_TLS 11503 t6_ktls_modunload(); 11504 #endif 11505 #ifdef INET6 11506 t4_clip_modunload(); 11507 #endif 11508 #ifdef TCP_OFFLOAD 11509 sx_destroy(&t4_uld_list_lock); 11510 #endif 11511 sx_destroy(&t4_list_lock); 11512 t4_sge_modunload(); 11513 loaded = 0; 11514 } else { 11515 rc = EBUSY; 11516 loaded++; /* undo earlier decrement */ 11517 } 11518 } 11519 done_unload: 11520 sx_xunlock(&mlu); 11521 break; 11522 } 11523 11524 return (rc); 11525 } 11526 11527 static devclass_t t4_devclass, t5_devclass, t6_devclass; 11528 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 11529 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 11530 11531 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 11532 MODULE_VERSION(t4nex, 1); 11533 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 11534 #ifdef DEV_NETMAP 11535 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 11536 #endif /* DEV_NETMAP */ 11537 11538 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 11539 MODULE_VERSION(t5nex, 1); 11540 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 11541 #ifdef DEV_NETMAP 11542 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 11543 #endif /* DEV_NETMAP */ 11544 11545 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 11546 MODULE_VERSION(t6nex, 1); 11547 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 11548 #ifdef DEV_NETMAP 11549 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 11550 #endif /* DEV_NETMAP */ 11551 11552 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 11553 MODULE_VERSION(cxgbe, 1); 11554 11555 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 11556 MODULE_VERSION(cxl, 1); 11557 11558 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 11559 MODULE_VERSION(cc, 1); 11560 11561 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 11562 MODULE_VERSION(vcxgbe, 1); 11563 11564 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 11565 MODULE_VERSION(vcxl, 1); 11566 11567 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 11568 MODULE_VERSION(vcc, 1); 11569