xref: /freebsd/sys/dev/cxgbe/t4_main.c (revision c2dee7786bf32cb66cedec226e42e79e06457c51) 
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2011, 2025 Chelsio Communications.
5  * Written by: Navdeep Parhar <np@FreeBSD.org>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 #include "opt_ddb.h"
31 #include "opt_inet.h"
32 #include "opt_inet6.h"
33 #include "opt_kern_tls.h"
34 #include "opt_ratelimit.h"
35 #include "opt_rss.h"
36 
37 #include <sys/param.h>
38 #include <sys/conf.h>
39 #include <sys/priv.h>
40 #include <sys/kernel.h>
41 #include <sys/bus.h>
42 #include <sys/eventhandler.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/queue.h>
46 #include <sys/taskqueue.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <sys/firmware.h>
50 #include <sys/sbuf.h>
51 #include <sys/smp.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/sysctl.h>
55 #include <net/ethernet.h>
56 #include <net/if.h>
57 #include <net/if_types.h>
58 #include <net/if_dl.h>
59 #include <net/if_vlan_var.h>
60 #include <net/rss_config.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
63 #ifdef KERN_TLS
64 #include <netinet/tcp_seq.h>
65 #endif
66 #if defined(__i386__) || defined(__amd64__)
67 #include <machine/md_var.h>
68 #include <machine/cputypes.h>
69 #include <vm/vm.h>
70 #include <vm/pmap.h>
71 #endif
72 #ifdef DDB
73 #include <ddb/ddb.h>
74 #include <ddb/db_lex.h>
75 #endif
76 
77 #include "common/common.h"
78 #include "common/t4_msg.h"
79 #include "common/t4_regs.h"
80 #include "common/t4_regs_values.h"
81 #include "cudbg/cudbg.h"
82 #include "t4_clip.h"
83 #include "t4_ioctl.h"
84 #include "t4_l2t.h"
85 #include "t4_mp_ring.h"
86 #include "t4_if.h"
87 #include "t4_smt.h"
88 
89 /* T4 bus driver interface */
90 static int t4_probe(device_t);
91 static int t4_attach(device_t);
92 static int t4_detach(device_t);
93 static int t4_child_location(device_t, device_t, struct sbuf *);
94 static int t4_ready(device_t);
95 static int t4_read_port_device(device_t, int, device_t *);
96 static int t4_suspend(device_t);
97 static int t4_resume(device_t);
98 static int t4_reset_prepare(device_t, device_t);
99 static int t4_reset_post(device_t, device_t);
100 static device_method_t t4_methods[] = {
101 	DEVMETHOD(device_probe,		t4_probe),
102 	DEVMETHOD(device_attach,	t4_attach),
103 	DEVMETHOD(device_detach,	t4_detach),
104 	DEVMETHOD(device_suspend,	t4_suspend),
105 	DEVMETHOD(device_resume,	t4_resume),
106 
107 	DEVMETHOD(bus_child_location,	t4_child_location),
108 	DEVMETHOD(bus_reset_prepare,	t4_reset_prepare),
109 	DEVMETHOD(bus_reset_post,	t4_reset_post),
110 
111 	DEVMETHOD(t4_is_main_ready,	t4_ready),
112 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
113 
114 	DEVMETHOD_END
115 };
116 static driver_t t4_driver = {
117 	"t4nex",
118 	t4_methods,
119 	sizeof(struct adapter)
120 };
121 
122 
123 /* T4 port (cxgbe) interface */
124 static int cxgbe_probe(device_t);
125 static int cxgbe_attach(device_t);
126 static int cxgbe_detach(device_t);
127 device_method_t cxgbe_methods[] = {
128 	DEVMETHOD(device_probe,		cxgbe_probe),
129 	DEVMETHOD(device_attach,	cxgbe_attach),
130 	DEVMETHOD(device_detach,	cxgbe_detach),
131 	DEVMETHOD_END
132 };
133 static driver_t cxgbe_driver = {
134 	"cxgbe",
135 	cxgbe_methods,
136 	sizeof(struct port_info)
137 };
138 
139 /* T4 VI (vcxgbe) interface */
140 static int vcxgbe_probe(device_t);
141 static int vcxgbe_attach(device_t);
142 static int vcxgbe_detach(device_t);
143 static device_method_t vcxgbe_methods[] = {
144 	DEVMETHOD(device_probe,		vcxgbe_probe),
145 	DEVMETHOD(device_attach,	vcxgbe_attach),
146 	DEVMETHOD(device_detach,	vcxgbe_detach),
147 	DEVMETHOD_END
148 };
149 static driver_t vcxgbe_driver = {
150 	"vcxgbe",
151 	vcxgbe_methods,
152 	sizeof(struct vi_info)
153 };
154 
155 static d_ioctl_t t4_ioctl;
156 
157 static struct cdevsw t4_cdevsw = {
158        .d_version = D_VERSION,
159        .d_ioctl = t4_ioctl,
160        .d_name = "t4nex",
161 };
162 
163 /* T5 bus driver interface */
164 static int t5_probe(device_t);
165 static device_method_t t5_methods[] = {
166 	DEVMETHOD(device_probe,		t5_probe),
167 	DEVMETHOD(device_attach,	t4_attach),
168 	DEVMETHOD(device_detach,	t4_detach),
169 	DEVMETHOD(device_suspend,	t4_suspend),
170 	DEVMETHOD(device_resume,	t4_resume),
171 
172 	DEVMETHOD(bus_child_location,	t4_child_location),
173 	DEVMETHOD(bus_reset_prepare,	t4_reset_prepare),
174 	DEVMETHOD(bus_reset_post,	t4_reset_post),
175 
176 	DEVMETHOD(t4_is_main_ready,	t4_ready),
177 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
178 
179 	DEVMETHOD_END
180 };
181 static driver_t t5_driver = {
182 	"t5nex",
183 	t5_methods,
184 	sizeof(struct adapter)
185 };
186 
187 
188 /* T5 port (cxl) interface */
189 static driver_t cxl_driver = {
190 	"cxl",
191 	cxgbe_methods,
192 	sizeof(struct port_info)
193 };
194 
195 /* T5 VI (vcxl) interface */
196 static driver_t vcxl_driver = {
197 	"vcxl",
198 	vcxgbe_methods,
199 	sizeof(struct vi_info)
200 };
201 
202 /* T6 bus driver interface */
203 static int t6_probe(device_t);
204 static device_method_t t6_methods[] = {
205 	DEVMETHOD(device_probe,		t6_probe),
206 	DEVMETHOD(device_attach,	t4_attach),
207 	DEVMETHOD(device_detach,	t4_detach),
208 	DEVMETHOD(device_suspend,	t4_suspend),
209 	DEVMETHOD(device_resume,	t4_resume),
210 
211 	DEVMETHOD(bus_child_location,	t4_child_location),
212 	DEVMETHOD(bus_reset_prepare,	t4_reset_prepare),
213 	DEVMETHOD(bus_reset_post,	t4_reset_post),
214 
215 	DEVMETHOD(t4_is_main_ready,	t4_ready),
216 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
217 
218 	DEVMETHOD_END
219 };
220 static driver_t t6_driver = {
221 	"t6nex",
222 	t6_methods,
223 	sizeof(struct adapter)
224 };
225 
226 
227 /* T6 port (cc) interface */
228 static driver_t cc_driver = {
229 	"cc",
230 	cxgbe_methods,
231 	sizeof(struct port_info)
232 };
233 
234 /* T6 VI (vcc) interface */
235 static driver_t vcc_driver = {
236 	"vcc",
237 	vcxgbe_methods,
238 	sizeof(struct vi_info)
239 };
240 
241 /* T7+ bus driver interface */
242 static int ch_probe(device_t);
243 static device_method_t ch_methods[] = {
244 	DEVMETHOD(device_probe,		ch_probe),
245 	DEVMETHOD(device_attach,	t4_attach),
246 	DEVMETHOD(device_detach,	t4_detach),
247 	DEVMETHOD(device_suspend,	t4_suspend),
248 	DEVMETHOD(device_resume,	t4_resume),
249 
250 	DEVMETHOD(bus_child_location,	t4_child_location),
251 	DEVMETHOD(bus_reset_prepare, 	t4_reset_prepare),
252 	DEVMETHOD(bus_reset_post, 	t4_reset_post),
253 
254 	DEVMETHOD(t4_is_main_ready,	t4_ready),
255 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
256 
257 	DEVMETHOD_END
258 };
259 static driver_t ch_driver = {
260 	"chnex",
261 	ch_methods,
262 	sizeof(struct adapter)
263 };
264 
265 
266 /* T7+ port (che) interface */
267 static driver_t che_driver = {
268 	"che",
269 	cxgbe_methods,
270 	sizeof(struct port_info)
271 };
272 
273 /* T7+ VI (vche) interface */
274 static driver_t vche_driver = {
275 	"vche",
276 	vcxgbe_methods,
277 	sizeof(struct vi_info)
278 };
279 
280 /* ifnet interface */
281 static void cxgbe_init(void *);
282 static int cxgbe_ioctl(if_t, unsigned long, caddr_t);
283 static int cxgbe_transmit(if_t, struct mbuf *);
284 static void cxgbe_qflush(if_t);
285 #if defined(KERN_TLS) || defined(RATELIMIT)
286 static int cxgbe_snd_tag_alloc(if_t, union if_snd_tag_alloc_params *,
287     struct m_snd_tag **);
288 #endif
289 
290 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
291 
292 /*
293  * Correct lock order when you need to acquire multiple locks is t4_list_lock,
294  * then ADAPTER_LOCK, then t4_uld_list_lock.
295  */
296 static struct sx t4_list_lock;
297 SLIST_HEAD(, adapter) t4_list;
298 #ifdef TCP_OFFLOAD
299 static struct sx t4_uld_list_lock;
300 struct uld_info *t4_uld_list[ULD_MAX + 1];
301 #endif
302 
303 /*
304  * Tunables.  See tweak_tunables() too.
305  *
306  * Each tunable is set to a default value here if it's known at compile-time.
307  * Otherwise it is set to -n as an indication to tweak_tunables() that it should
308  * provide a reasonable default (upto n) when the driver is loaded.
309  *
310  * Tunables applicable to both T4 and T5 are under hw.cxgbe.  Those specific to
311  * T5 are under hw.cxl.
312  */
313 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
314     "cxgbe(4) parameters");
315 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
316     "cxgbe(4) T5+ parameters");
317 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
318     "cxgbe(4) TOE parameters");
319 
320 /*
321  * Number of queues for tx and rx, NIC and offload.
322  */
323 #define NTXQ 16
324 int t4_ntxq = -NTXQ;
325 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
326     "Number of TX queues per port");
327 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq);	/* Old name, undocumented */
328 
329 #define NRXQ 8
330 int t4_nrxq = -NRXQ;
331 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
332     "Number of RX queues per port");
333 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq);	/* Old name, undocumented */
334 
335 #define NTXQ_VI 1
336 static int t4_ntxq_vi = -NTXQ_VI;
337 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
338     "Number of TX queues per VI");
339 
340 #define NRXQ_VI 1
341 static int t4_nrxq_vi = -NRXQ_VI;
342 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
343     "Number of RX queues per VI");
344 
345 static int t4_rsrv_noflowq = 0;
346 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
347     0, "Reserve TX queue 0 of each VI for non-flowid packets");
348 
349 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
350 #define NOFLDTXQ 8
351 static int t4_nofldtxq = -NOFLDTXQ;
352 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
353     "Number of offload TX queues per port");
354 
355 #define NOFLDTXQ_VI 1
356 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
357 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
358     "Number of offload TX queues per VI");
359 #endif
360 
361 #if defined(TCP_OFFLOAD)
362 #define NOFLDRXQ 2
363 static int t4_nofldrxq = -NOFLDRXQ;
364 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
365     "Number of offload RX queues per port");
366 
367 #define NOFLDRXQ_VI 1
368 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
369 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
370     "Number of offload RX queues per VI");
371 
372 #define TMR_IDX_OFLD 1
373 static int t4_tmr_idx_ofld = TMR_IDX_OFLD;
374 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
375     &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
376 
377 #define PKTC_IDX_OFLD (-1)
378 static int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
379 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
380     &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
381 
382 /* 0 means chip/fw default, non-zero number is value in microseconds */
383 static u_long t4_toe_keepalive_idle = 0;
384 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
385     &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
386 
387 /* 0 means chip/fw default, non-zero number is value in microseconds */
388 static u_long t4_toe_keepalive_interval = 0;
389 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
390     &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
391 
392 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
393 static int t4_toe_keepalive_count = 0;
394 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
395     &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
396 
397 /* 0 means chip/fw default, non-zero number is value in microseconds */
398 static u_long t4_toe_rexmt_min = 0;
399 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
400     &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
401 
402 /* 0 means chip/fw default, non-zero number is value in microseconds */
403 static u_long t4_toe_rexmt_max = 0;
404 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
405     &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
406 
407 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
408 static int t4_toe_rexmt_count = 0;
409 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
410     &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
411 
412 /* -1 means chip/fw default, other values are raw backoff values to use */
413 static int t4_toe_rexmt_backoff[16] = {
414 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
415 };
416 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff,
417     CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
418     "cxgbe(4) TOE retransmit backoff values");
419 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
420     &t4_toe_rexmt_backoff[0], 0, "");
421 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
422     &t4_toe_rexmt_backoff[1], 0, "");
423 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
424     &t4_toe_rexmt_backoff[2], 0, "");
425 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
426     &t4_toe_rexmt_backoff[3], 0, "");
427 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
428     &t4_toe_rexmt_backoff[4], 0, "");
429 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
430     &t4_toe_rexmt_backoff[5], 0, "");
431 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
432     &t4_toe_rexmt_backoff[6], 0, "");
433 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
434     &t4_toe_rexmt_backoff[7], 0, "");
435 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
436     &t4_toe_rexmt_backoff[8], 0, "");
437 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
438     &t4_toe_rexmt_backoff[9], 0, "");
439 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
440     &t4_toe_rexmt_backoff[10], 0, "");
441 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
442     &t4_toe_rexmt_backoff[11], 0, "");
443 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
444     &t4_toe_rexmt_backoff[12], 0, "");
445 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
446     &t4_toe_rexmt_backoff[13], 0, "");
447 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
448     &t4_toe_rexmt_backoff[14], 0, "");
449 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
450     &t4_toe_rexmt_backoff[15], 0, "");
451 
452 int t4_ddp_rcvbuf_len = 256 * 1024;
453 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_len, CTLFLAG_RWTUN,
454     &t4_ddp_rcvbuf_len, 0, "length of each DDP RX buffer");
455 
456 unsigned int t4_ddp_rcvbuf_cache = 4;
457 SYSCTL_UINT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_cache, CTLFLAG_RWTUN,
458     &t4_ddp_rcvbuf_cache, 0,
459     "maximum number of free DDP RX buffers to cache per connection");
460 #endif
461 
462 #ifdef DEV_NETMAP
463 #define NN_MAIN_VI	(1 << 0)	/* Native netmap on the main VI */
464 #define NN_EXTRA_VI	(1 << 1)	/* Native netmap on the extra VI(s) */
465 static int t4_native_netmap = NN_EXTRA_VI;
466 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap,
467     0, "Native netmap support.  bit 0 = main VI, bit 1 = extra VIs");
468 
469 #define NNMTXQ 8
470 static int t4_nnmtxq = -NNMTXQ;
471 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0,
472     "Number of netmap TX queues");
473 
474 #define NNMRXQ 8
475 static int t4_nnmrxq = -NNMRXQ;
476 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0,
477     "Number of netmap RX queues");
478 
479 #define NNMTXQ_VI 2
480 static int t4_nnmtxq_vi = -NNMTXQ_VI;
481 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
482     "Number of netmap TX queues per VI");
483 
484 #define NNMRXQ_VI 2
485 static int t4_nnmrxq_vi = -NNMRXQ_VI;
486 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
487     "Number of netmap RX queues per VI");
488 #endif
489 
490 /*
491  * Holdoff parameters for ports.
492  */
493 #define TMR_IDX 1
494 int t4_tmr_idx = TMR_IDX;
495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
496     0, "Holdoff timer index");
497 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx);	/* Old name */
498 
499 #define PKTC_IDX (-1)
500 int t4_pktc_idx = PKTC_IDX;
501 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
502     0, "Holdoff packet counter index");
503 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx);	/* Old name */
504 
505 /*
506  * Size (# of entries) of each tx and rx queue.
507  */
508 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
509 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
510     "Number of descriptors in each TX queue");
511 
512 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
513 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
514     "Number of descriptors in each RX queue");
515 
516 /*
517  * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
518  */
519 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
520 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
521     0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
522 
523 /*
524  * Configuration file.  All the _CF names here are special.
525  */
526 #define DEFAULT_CF	"default"
527 #define BUILTIN_CF	"built-in"
528 #define FLASH_CF	"flash"
529 #define UWIRE_CF	"uwire"
530 #define FPGA_CF		"fpga"
531 static char t4_cfg_file[32] = DEFAULT_CF;
532 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
533     sizeof(t4_cfg_file), "Firmware configuration file");
534 
535 /*
536  * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
537  * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
538  * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
539  *            mark or when signalled to do so, 0 to never emit PAUSE.
540  * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
541  *                 negotiated settings will override rx_pause/tx_pause.
542  *                 Otherwise rx_pause/tx_pause are applied forcibly.
543  */
544 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
545 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
546     &t4_pause_settings, 0,
547     "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
548 
549 /*
550  * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
551  * -1 to run with the firmware default.  Same as FEC_AUTO (bit 5)
552  *  0 to disable FEC.
553  */
554 static int t4_fec = -1;
555 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
556     "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
557 
558 static const char *
559 t4_fec_bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2\6auto\7module";
560 
561 /*
562  * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it
563  * issues to the firmware.  If the firmware doesn't support FORCE_FEC then the
564  * driver runs as if this is set to 0.
565  * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay.
566  *  0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the
567  *    transceiver. Multiple FEC bits may not be okay but will be passed on to
568  *    the firmware anyway (may result in l1cfg errors with old firmwares).
569  *  1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO
570  *    means set all FEC bits that are valid for the speed.
571  */
572 static int t4_force_fec = -1;
573 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0,
574     "Controls the use of FORCE_FEC bit in L1 configuration.");
575 
576 /*
577  * Link autonegotiation.
578  * -1 to run with the firmware default.
579  *  0 to disable.
580  *  1 to enable.
581  */
582 static int t4_autoneg = -1;
583 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
584     "Link autonegotiation");
585 
586 /*
587  * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
588  * encouraged respectively).  '-n' is the same as 'n' except the firmware
589  * version used in the checks is read from the firmware bundled with the driver.
590  */
591 static int t4_fw_install = 1;
592 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
593     "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
594 
595 /*
596  * ASIC features that will be used.  Disable the ones you don't want so that the
597  * chip resources aren't wasted on features that will not be used.
598  */
599 static int t4_nbmcaps_allowed = 0;
600 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
601     &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
602 
603 static int t4_linkcaps_allowed = 0;	/* No DCBX, PPP, etc. by default */
604 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
605     &t4_linkcaps_allowed, 0, "Default link capabilities");
606 
607 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
608     FW_CAPS_CONFIG_SWITCH_EGRESS;
609 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
610     &t4_switchcaps_allowed, 0, "Default switch capabilities");
611 
612 static int t4_nvmecaps_allowed = -1;
613 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nvmecaps_allowed, CTLFLAG_RDTUN,
614     &t4_nvmecaps_allowed, 0, "Default NVMe capabilities");
615 
616 #ifdef RATELIMIT
617 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
618 	FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
619 #else
620 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
621 	FW_CAPS_CONFIG_NIC_HASHFILTER;
622 #endif
623 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
624     &t4_niccaps_allowed, 0, "Default NIC capabilities");
625 
626 static int t4_toecaps_allowed = -1;
627 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
628     &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
629 
630 static int t4_rdmacaps_allowed = -1;
631 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
632     &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
633 
634 static int t4_cryptocaps_allowed = -1;
635 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
636     &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
637 
638 static int t4_iscsicaps_allowed = -1;
639 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
640     &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
641 
642 static int t4_fcoecaps_allowed = 0;
643 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
644     &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
645 
646 static int t5_write_combine = 0;
647 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
648     0, "Use WC instead of UC for BAR2");
649 
650 /* From t4_sysctls: doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"} */
651 static int t4_doorbells_allowed = 0xf;
652 SYSCTL_INT(_hw_cxgbe, OID_AUTO, doorbells_allowed, CTLFLAG_RDTUN,
653 	   &t4_doorbells_allowed, 0, "Limit tx queues to these doorbells");
654 
655 static int t4_num_vis = 1;
656 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
657     "Number of VIs per port");
658 
659 /*
660  * PCIe Relaxed Ordering.
661  * -1: driver should figure out a good value.
662  * 0: disable RO.
663  * 1: enable RO.
664  * 2: leave RO alone.
665  */
666 static int pcie_relaxed_ordering = -1;
667 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
668     &pcie_relaxed_ordering, 0,
669     "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
670 
671 static int t4_panic_on_fatal_err = 0;
672 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN,
673     &t4_panic_on_fatal_err, 0, "panic on fatal errors");
674 
675 static int t4_reset_on_fatal_err = 0;
676 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN,
677     &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors");
678 
679 static int t4_reset_method = 1;
680 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_method, CTLFLAG_RWTUN, &t4_reset_method,
681     0, "reset method: 0 = PL_RST, 1 = PCIe secondary bus reset, 2 = PCIe link bounce");
682 
683 static int t4_clock_gate_on_suspend = 0;
684 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN,
685     &t4_clock_gate_on_suspend, 0, "gate the clock on suspend");
686 
687 static int t4_tx_vm_wr = 0;
688 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0,
689     "Use VM work requests to transmit packets.");
690 
691 /*
692  * Set to non-zero to enable the attack filter.  A packet that matches any of
693  * these conditions will get dropped on ingress:
694  * 1) IP && source address == destination address.
695  * 2) TCP/IP && source address is not a unicast address.
696  * 3) TCP/IP && destination address is not a unicast address.
697  * 4) IP && source address is loopback (127.x.y.z).
698  * 5) IP && destination address is loopback (127.x.y.z).
699  * 6) IPv6 && source address == destination address.
700  * 7) IPv6 && source address is not a unicast address.
701  * 8) IPv6 && source address is loopback (::1/128).
702  * 9) IPv6 && destination address is loopback (::1/128).
703  * 10) IPv6 && source address is unspecified (::/128).
704  * 11) IPv6 && destination address is unspecified (::/128).
705  * 12) TCP/IPv6 && source address is multicast (ff00::/8).
706  * 13) TCP/IPv6 && destination address is multicast (ff00::/8).
707  */
708 static int t4_attack_filter = 0;
709 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN,
710     &t4_attack_filter, 0, "Drop suspicious traffic");
711 
712 static int t4_drop_ip_fragments = 0;
713 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN,
714     &t4_drop_ip_fragments, 0, "Drop IP fragments");
715 
716 static int t4_drop_pkts_with_l2_errors = 1;
717 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN,
718     &t4_drop_pkts_with_l2_errors, 0,
719     "Drop all frames with Layer 2 length or checksum errors");
720 
721 static int t4_drop_pkts_with_l3_errors = 0;
722 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN,
723     &t4_drop_pkts_with_l3_errors, 0,
724     "Drop all frames with IP version, length, or checksum errors");
725 
726 static int t4_drop_pkts_with_l4_errors = 0;
727 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN,
728     &t4_drop_pkts_with_l4_errors, 0,
729     "Drop all frames with Layer 4 length, checksum, or other errors");
730 
731 #ifdef TCP_OFFLOAD
732 /*
733  * TOE tunables.
734  */
735 static int t4_cop_managed_offloading = 0;
736 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
737     &t4_cop_managed_offloading, 0,
738     "COP (Connection Offload Policy) controls all TOE offload");
739 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading);
740 #endif
741 
742 #ifdef KERN_TLS
743 /*
744  * This enables KERN_TLS for all adapters if set.
745  */
746 static int t4_kern_tls = 0;
747 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0,
748     "Enable KERN_TLS mode for T6 adapters");
749 
750 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
751     "cxgbe(4) KERN_TLS parameters");
752 
753 static int t4_tls_inline_keys = 0;
754 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN,
755     &t4_tls_inline_keys, 0,
756     "Always pass TLS keys in work requests (1) or attempt to store TLS keys "
757     "in card memory.");
758 
759 static int t4_tls_combo_wrs = 0;
760 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs,
761     0, "Attempt to combine TCB field updates with TLS record work requests.");
762 
763 static int t4_tls_short_records = 1;
764 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, short_records, CTLFLAG_RDTUN,
765     &t4_tls_short_records, 0, "Use cipher-only mode for short records.");
766 
767 static int t4_tls_partial_ghash = 1;
768 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, partial_ghash, CTLFLAG_RDTUN,
769     &t4_tls_partial_ghash, 0, "Use partial GHASH for AES-GCM records.");
770 #endif
771 
772 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
773 static int vi_mac_funcs[] = {
774 	FW_VI_FUNC_ETH,
775 	FW_VI_FUNC_OFLD,
776 	FW_VI_FUNC_IWARP,
777 	FW_VI_FUNC_OPENISCSI,
778 	FW_VI_FUNC_OPENFCOE,
779 	FW_VI_FUNC_FOISCSI,
780 	FW_VI_FUNC_FOFCOE,
781 };
782 
783 struct intrs_and_queues {
784 	uint16_t intr_type;	/* INTx, MSI, or MSI-X */
785 	uint16_t num_vis;	/* number of VIs for each port */
786 	uint16_t nirq;		/* Total # of vectors */
787 	uint16_t ntxq;		/* # of NIC txq's for each port */
788 	uint16_t nrxq;		/* # of NIC rxq's for each port */
789 	uint16_t nofldtxq;	/* # of TOE/ETHOFLD txq's for each port */
790 	uint16_t nofldrxq;	/* # of TOE rxq's for each port */
791 	uint16_t nnmtxq;	/* # of netmap txq's */
792 	uint16_t nnmrxq;	/* # of netmap rxq's */
793 
794 	/* The vcxgbe/vcxl interfaces use these and not the ones above. */
795 	uint16_t ntxq_vi;	/* # of NIC txq's */
796 	uint16_t nrxq_vi;	/* # of NIC rxq's */
797 	uint16_t nofldtxq_vi;	/* # of TOE txq's */
798 	uint16_t nofldrxq_vi;	/* # of TOE rxq's */
799 	uint16_t nnmtxq_vi;	/* # of netmap txq's */
800 	uint16_t nnmrxq_vi;	/* # of netmap rxq's */
801 };
802 
803 static void setup_memwin(struct adapter *);
804 static void position_memwin(struct adapter *, int, uint32_t);
805 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
806 static int fwmtype_to_hwmtype(int);
807 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
808     uint32_t *);
809 static int fixup_devlog_params(struct adapter *);
810 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
811 static int contact_firmware(struct adapter *);
812 static int partition_resources(struct adapter *);
813 static int get_params__pre_init(struct adapter *);
814 static int set_params__pre_init(struct adapter *);
815 static int get_params__post_init(struct adapter *);
816 static int set_params__post_init(struct adapter *);
817 static void t4_set_desc(struct adapter *);
818 static bool fixed_ifmedia(struct port_info *);
819 static void build_medialist(struct port_info *);
820 static void init_link_config(struct port_info *);
821 static int fixup_link_config(struct port_info *);
822 static int apply_link_config(struct port_info *);
823 static int cxgbe_init_synchronized(struct vi_info *);
824 static int cxgbe_uninit_synchronized(struct vi_info *);
825 static int adapter_full_init(struct adapter *);
826 static void adapter_full_uninit(struct adapter *);
827 static int vi_full_init(struct vi_info *);
828 static void vi_full_uninit(struct vi_info *);
829 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *);
830 static void quiesce_txq(struct sge_txq *);
831 static void quiesce_wrq(struct sge_wrq *);
832 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
833 static void quiesce_vi(struct vi_info *);
834 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
835     driver_intr_t *, void *, char *);
836 static int t4_free_irq(struct adapter *, struct irq *);
837 static void t4_init_atid_table(struct adapter *);
838 static void t4_free_atid_table(struct adapter *);
839 static void stop_atid_allocator(struct adapter *);
840 static void restart_atid_allocator(struct adapter *);
841 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
842 static void vi_refresh_stats(struct vi_info *);
843 static void cxgbe_refresh_stats(struct vi_info *);
844 static void cxgbe_tick(void *);
845 static void vi_tick(void *);
846 static void cxgbe_sysctls(struct port_info *);
847 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
848 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
849 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
850 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
851 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
852 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS);
853 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
854 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
855 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
856 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
857 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
858 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS);
859 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS);
860 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS);
861 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
862 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS);
863 static int sysctl_handle_t4_portstat64(SYSCTL_HANDLER_ARGS);
864 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
865 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
866 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
867 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS);
868 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
869 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
870 static int sysctl_cim_ibq(SYSCTL_HANDLER_ARGS);
871 static int sysctl_cim_obq(SYSCTL_HANDLER_ARGS);
872 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
873 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
874 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
875 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
876 static int sysctl_cim_qcfg_t7(SYSCTL_HANDLER_ARGS);
877 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
878 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
879 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS);
880 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
881 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
882 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
883 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
884 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
885 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
886 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
887 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
888 static int sysctl_mps_tcam_t7(SYSCTL_HANDLER_ARGS);
889 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
890 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
891 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
892 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
893 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
894 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
895 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS);
896 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
897 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
898 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
899 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
900 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
901 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
902 static int sysctl_reset(SYSCTL_HANDLER_ARGS);
903 static int sysctl_tcb_cache(SYSCTL_HANDLER_ARGS);
904 #ifdef TCP_OFFLOAD
905 static int sysctl_tls(SYSCTL_HANDLER_ARGS);
906 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
907 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
908 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
909 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
910 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
911 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
912 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
913 #endif
914 static int get_sge_context(struct adapter *, int, uint32_t, int, uint32_t *);
915 static int load_fw(struct adapter *, struct t4_data *);
916 static int load_cfg(struct adapter *, struct t4_data *);
917 static int load_boot(struct adapter *, struct t4_bootrom *);
918 static int load_bootcfg(struct adapter *, struct t4_data *);
919 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
920 static void free_offload_policy(struct t4_offload_policy *);
921 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
922 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
923 static int read_i2c(struct adapter *, struct t4_i2c_data *);
924 static int clear_stats(struct adapter *, u_int);
925 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *);
926 static int release_clip_addr(struct adapter *, struct t4_clip_addr *);
927 static inline int stop_adapter(struct adapter *);
928 static inline void set_adapter_hwstatus(struct adapter *, const bool);
929 static int stop_lld(struct adapter *);
930 static inline int restart_adapter(struct adapter *);
931 static int restart_lld(struct adapter *);
932 #ifdef TCP_OFFLOAD
933 static int deactivate_all_uld(struct adapter *);
934 static void stop_all_uld(struct adapter *);
935 static void restart_all_uld(struct adapter *);
936 #endif
937 #ifdef KERN_TLS
938 static int ktls_capability(struct adapter *, bool);
939 #endif
940 static int mod_event(module_t, int, void *);
941 static int notify_siblings(device_t, int);
942 static uint64_t vi_get_counter(if_t, ift_counter);
943 static uint64_t cxgbe_get_counter(if_t, ift_counter);
944 static void enable_vxlan_rx(struct adapter *);
945 static void reset_adapter_task(void *, int);
946 static void fatal_error_task(void *, int);
947 static void dump_devlog(struct adapter *);
948 static void dump_cim_regs(struct adapter *);
949 static void dump_cimla(struct adapter *);
950 
951 struct {
952 	uint16_t device;
953 	char *desc;
954 } t4_pciids[] = {
955 	{0xa000, "Chelsio Terminator 4 FPGA"},
956 	{0x4400, "Chelsio T440-dbg"},
957 	{0x4401, "Chelsio T420-CR"},
958 	{0x4402, "Chelsio T422-CR"},
959 	{0x4403, "Chelsio T440-CR"},
960 	{0x4404, "Chelsio T420-BCH"},
961 	{0x4405, "Chelsio T440-BCH"},
962 	{0x4406, "Chelsio T440-CH"},
963 	{0x4407, "Chelsio T420-SO"},
964 	{0x4408, "Chelsio T420-CX"},
965 	{0x4409, "Chelsio T420-BT"},
966 	{0x440a, "Chelsio T404-BT"},
967 	{0x440e, "Chelsio T440-LP-CR"},
968 }, t5_pciids[] = {
969 	{0xb000, "Chelsio Terminator 5 FPGA"},
970 	{0x5400, "Chelsio T580-dbg"},
971 	{0x5401,  "Chelsio T520-CR"},		/* 2 x 10G */
972 	{0x5402,  "Chelsio T522-CR"},		/* 2 x 10G, 2 X 1G */
973 	{0x5403,  "Chelsio T540-CR"},		/* 4 x 10G */
974 	{0x5407,  "Chelsio T520-SO"},		/* 2 x 10G, nomem */
975 	{0x5409,  "Chelsio T520-BT"},		/* 2 x 10GBaseT */
976 	{0x540a,  "Chelsio T504-BT"},		/* 4 x 1G */
977 	{0x540d,  "Chelsio T580-CR"},		/* 2 x 40G */
978 	{0x540e,  "Chelsio T540-LP-CR"},	/* 4 x 10G */
979 	{0x5410,  "Chelsio T580-LP-CR"},	/* 2 x 40G */
980 	{0x5411,  "Chelsio T520-LL-CR"},	/* 2 x 10G */
981 	{0x5412,  "Chelsio T560-CR"},		/* 1 x 40G, 2 x 10G */
982 	{0x5414,  "Chelsio T580-LP-SO-CR"},	/* 2 x 40G, nomem */
983 	{0x5415,  "Chelsio T502-BT"},		/* 2 x 1G */
984 	{0x5418,  "Chelsio T540-BT"},		/* 4 x 10GBaseT */
985 	{0x5419,  "Chelsio T540-LP-BT"},	/* 4 x 10GBaseT */
986 	{0x541a,  "Chelsio T540-SO-BT"},	/* 4 x 10GBaseT, nomem */
987 	{0x541b,  "Chelsio T540-SO-CR"},	/* 4 x 10G, nomem */
988 
989 	/* Custom */
990 	{0x5483, "Custom T540-CR"},
991 	{0x5484, "Custom T540-BT"},
992 }, t6_pciids[] = {
993 	{0xc006, "Chelsio Terminator 6 FPGA"},	/* T6 PE10K6 FPGA (PF0) */
994 	{0x6400, "Chelsio T6-DBG-25"},		/* 2 x 10/25G, debug */
995 	{0x6401, "Chelsio T6225-CR"},		/* 2 x 10/25G */
996 	{0x6402, "Chelsio T6225-SO-CR"},	/* 2 x 10/25G, nomem */
997 	{0x6403, "Chelsio T6425-CR"},		/* 4 x 10/25G */
998 	{0x6404, "Chelsio T6425-SO-CR"},	/* 4 x 10/25G, nomem */
999 	{0x6405, "Chelsio T6225-SO-OCP3"},	/* 2 x 10/25G, nomem */
1000 	{0x6406, "Chelsio T6225-OCP3"},		/* 2 x 10/25G */
1001 	{0x6407, "Chelsio T62100-LP-CR"},	/* 2 x 40/50/100G */
1002 	{0x6408, "Chelsio T62100-SO-CR"},	/* 2 x 40/50/100G, nomem */
1003 	{0x6409, "Chelsio T6210-BT"},		/* 2 x 10GBASE-T */
1004 	{0x640d, "Chelsio T62100-CR"},		/* 2 x 40/50/100G */
1005 	{0x6410, "Chelsio T6-DBG-100"},		/* 2 x 40/50/100G, debug */
1006 	{0x6411, "Chelsio T6225-LL-CR"},	/* 2 x 10/25G */
1007 	{0x6414, "Chelsio T62100-SO-OCP3"},	/* 2 x 40/50/100G, nomem */
1008 	{0x6415, "Chelsio T6201-BT"},		/* 2 x 1000BASE-T */
1009 
1010 	/* Custom */
1011 	{0x6480, "Custom T6225-CR"},
1012 	{0x6481, "Custom T62100-CR"},
1013 	{0x6482, "Custom T6225-CR"},
1014 	{0x6483, "Custom T62100-CR"},
1015 	{0x6484, "Custom T64100-CR"},
1016 	{0x6485, "Custom T6240-SO"},
1017 	{0x6486, "Custom T6225-SO-CR"},
1018 	{0x6487, "Custom T6225-CR"},
1019 }, t7_pciids[] = {
1020 	{0xd000, "Chelsio Terminator 7 FPGA"},	/* T7 PE12K FPGA */
1021 	{0x7400, "Chelsio T72200-DBG"},		/* 2 x 200G, debug */
1022 	{0x7401, "Chelsio T7250"},		/* 2 x 10/25/50G, 1 mem */
1023 	{0x7402, "Chelsio S7250"},		/* 2 x 10/25/50G, nomem */
1024 	{0x7403, "Chelsio T7450"},		/* 4 x 10/25/50G, 1 mem */
1025 	{0x7404, "Chelsio S7450"},		/* 4 x 10/25/50G, nomem */
1026 	{0x7405, "Chelsio T72200"},		/* 2 x 40/100/200G, 1 mem */
1027 	{0x7406, "Chelsio S72200"},		/* 2 x 40/100/200G, nomem */
1028 	{0x7407, "Chelsio T72200-FH"},		/* 2 x 40/100/200G, 2 mem */
1029 	{0x7408, "Chelsio S71400"},		/* 1 x 400G, nomem */
1030 	{0x7409, "Chelsio S7210-BT"},		/* 2 x 10GBASE-T, nomem */
1031 	{0x740a, "Chelsio T7450-RC"},		/* 4 x 10/25/50G, 1 mem, RC */
1032 	{0x740b, "Chelsio T72200-RC"},		/* 2 x 40/100/200G, 1 mem, RC */
1033 	{0x740c, "Chelsio T72200-FH-RC"},	/* 2 x 40/100/200G, 2 mem, RC */
1034 	{0x740d, "Chelsio S72200-OCP3"},	/* 2 x 40/100/200G OCP3 */
1035 	{0x740e, "Chelsio S7450-OCP3"},		/* 4 x 1/20/25/50G OCP3 */
1036 	{0x740f, "Chelsio S7410-BT-OCP3"},	/* 4 x 10GBASE-T OCP3 */
1037 	{0x7410, "Chelsio S7210-BT-A"},		/* 2 x 10GBASE-T */
1038 	{0x7411, "Chelsio T7_MAYRA_7"},		/* Motherboard */
1039 
1040 	/* Custom */
1041 	{0x7480, "Custom T7"},
1042 };
1043 
1044 #ifdef TCP_OFFLOAD
1045 /*
1046  * service_iq_fl() has an iq and needs the fl.  Offset of fl from the iq should
1047  * be exactly the same for both rxq and ofld_rxq.
1048  */
1049 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
1050 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
1051 #endif
1052 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
1053 
1054 static int
1055 t4_probe(device_t dev)
1056 {
1057 	int i;
1058 	uint16_t v = pci_get_vendor(dev);
1059 	uint16_t d = pci_get_device(dev);
1060 	uint8_t f = pci_get_function(dev);
1061 
1062 	if (v != PCI_VENDOR_ID_CHELSIO)
1063 		return (ENXIO);
1064 
1065 	/* Attach only to PF0 of the FPGA */
1066 	if (d == 0xa000 && f != 0)
1067 		return (ENXIO);
1068 
1069 	for (i = 0; i < nitems(t4_pciids); i++) {
1070 		if (d == t4_pciids[i].device) {
1071 			device_set_desc(dev, t4_pciids[i].desc);
1072 			return (BUS_PROBE_DEFAULT);
1073 		}
1074 	}
1075 
1076 	return (ENXIO);
1077 }
1078 
1079 static int
1080 t5_probe(device_t dev)
1081 {
1082 	int i;
1083 	uint16_t v = pci_get_vendor(dev);
1084 	uint16_t d = pci_get_device(dev);
1085 	uint8_t f = pci_get_function(dev);
1086 
1087 	if (v != PCI_VENDOR_ID_CHELSIO)
1088 		return (ENXIO);
1089 
1090 	/* Attach only to PF0 of the FPGA */
1091 	if (d == 0xb000 && f != 0)
1092 		return (ENXIO);
1093 
1094 	for (i = 0; i < nitems(t5_pciids); i++) {
1095 		if (d == t5_pciids[i].device) {
1096 			device_set_desc(dev, t5_pciids[i].desc);
1097 			return (BUS_PROBE_DEFAULT);
1098 		}
1099 	}
1100 
1101 	return (ENXIO);
1102 }
1103 
1104 static int
1105 t6_probe(device_t dev)
1106 {
1107 	int i;
1108 	uint16_t v = pci_get_vendor(dev);
1109 	uint16_t d = pci_get_device(dev);
1110 
1111 	if (v != PCI_VENDOR_ID_CHELSIO)
1112 		return (ENXIO);
1113 
1114 	for (i = 0; i < nitems(t6_pciids); i++) {
1115 		if (d == t6_pciids[i].device) {
1116 			device_set_desc(dev, t6_pciids[i].desc);
1117 			return (BUS_PROBE_DEFAULT);
1118 		}
1119 	}
1120 
1121 	return (ENXIO);
1122 }
1123 
1124 static int
1125 ch_probe(device_t dev)
1126 {
1127 	int i;
1128 	uint16_t v = pci_get_vendor(dev);
1129 	uint16_t d = pci_get_device(dev);
1130 	uint8_t f = pci_get_function(dev);
1131 
1132 	if (v != PCI_VENDOR_ID_CHELSIO)
1133 		return (ENXIO);
1134 
1135 	/* Attach only to PF0 of the FPGA */
1136 	if (d == 0xd000 && f != 0)
1137 		return (ENXIO);
1138 
1139 	for (i = 0; i < nitems(t7_pciids); i++) {
1140 		if (d == t7_pciids[i].device) {
1141 			device_set_desc(dev, t7_pciids[i].desc);
1142 			return (BUS_PROBE_DEFAULT);
1143 		}
1144 	}
1145 
1146 	return (ENXIO);
1147 }
1148 
1149 static void
1150 t5_attribute_workaround(device_t dev)
1151 {
1152 	device_t root_port;
1153 	uint32_t v;
1154 
1155 	/*
1156 	 * The T5 chips do not properly echo the No Snoop and Relaxed
1157 	 * Ordering attributes when replying to a TLP from a Root
1158 	 * Port.  As a workaround, find the parent Root Port and
1159 	 * disable No Snoop and Relaxed Ordering.  Note that this
1160 	 * affects all devices under this root port.
1161 	 */
1162 	root_port = pci_find_pcie_root_port(dev);
1163 	if (root_port == NULL) {
1164 		device_printf(dev, "Unable to find parent root port\n");
1165 		return;
1166 	}
1167 
1168 	v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
1169 	    PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
1170 	if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
1171 	    0)
1172 		device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
1173 		    device_get_nameunit(root_port));
1174 }
1175 
1176 static const struct devnames devnames[] = {
1177 	{
1178 		.nexus_name = "t4nex",
1179 		.ifnet_name = "cxgbe",
1180 		.vi_ifnet_name = "vcxgbe",
1181 		.pf03_drv_name = "t4iov",
1182 		.vf_nexus_name = "t4vf",
1183 		.vf_ifnet_name = "cxgbev"
1184 	}, {
1185 		.nexus_name = "t5nex",
1186 		.ifnet_name = "cxl",
1187 		.vi_ifnet_name = "vcxl",
1188 		.pf03_drv_name = "t5iov",
1189 		.vf_nexus_name = "t5vf",
1190 		.vf_ifnet_name = "cxlv"
1191 	}, {
1192 		.nexus_name = "t6nex",
1193 		.ifnet_name = "cc",
1194 		.vi_ifnet_name = "vcc",
1195 		.pf03_drv_name = "t6iov",
1196 		.vf_nexus_name = "t6vf",
1197 		.vf_ifnet_name = "ccv"
1198 	}, {
1199 		.nexus_name = "chnex",
1200 		.ifnet_name = "che",
1201 		.vi_ifnet_name = "vche",
1202 		.pf03_drv_name = "chiov",
1203 		.vf_nexus_name = "chvf",
1204 		.vf_ifnet_name = "chev"
1205 	}
1206 };
1207 
1208 void
1209 t4_init_devnames(struct adapter *sc)
1210 {
1211 	int id;
1212 
1213 	id = chip_id(sc);
1214 	if (id < CHELSIO_T4) {
1215 		device_printf(sc->dev, "chip id %d is not supported.\n", id);
1216 		sc->names = NULL;
1217 	} else if (id - CHELSIO_T4 < nitems(devnames))
1218 		sc->names = &devnames[id - CHELSIO_T4];
1219 	else
1220 		sc->names = &devnames[nitems(devnames) - 1];
1221 }
1222 
1223 static int
1224 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
1225 {
1226 	const char *parent, *name;
1227 	long value;
1228 	int line, unit;
1229 
1230 	line = 0;
1231 	parent = device_get_nameunit(sc->dev);
1232 	name = sc->names->ifnet_name;
1233 	while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
1234 		if (resource_long_value(name, unit, "port", &value) == 0 &&
1235 		    value == pi->port_id)
1236 			return (unit);
1237 	}
1238 	return (-1);
1239 }
1240 
1241 static void
1242 t4_calibration(void *arg)
1243 {
1244 	struct adapter *sc;
1245 	struct clock_sync *cur, *nex;
1246 	uint64_t hw;
1247 	sbintime_t sbt;
1248 	int next_up;
1249 
1250 	sc = (struct adapter *)arg;
1251 
1252 	KASSERT(!hw_off_limits(sc), ("hw_off_limits at t4_calibration"));
1253 	hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO);
1254 	sbt = sbinuptime();
1255 
1256 	cur = &sc->cal_info[sc->cal_current];
1257 	next_up = (sc->cal_current + 1) % CNT_CAL_INFO;
1258 	nex = &sc->cal_info[next_up];
1259 	if (__predict_false(sc->cal_count == 0)) {
1260 		/* First time in, just get the values in */
1261 		cur->hw_cur = hw;
1262 		cur->sbt_cur = sbt;
1263 		sc->cal_count++;
1264 		goto done;
1265 	}
1266 
1267 	if (cur->hw_cur == hw) {
1268 		/* The clock is not advancing? */
1269 		sc->cal_count = 0;
1270 		atomic_store_rel_int(&cur->gen, 0);
1271 		goto done;
1272 	}
1273 
1274 	seqc_write_begin(&nex->gen);
1275 	nex->hw_prev = cur->hw_cur;
1276 	nex->sbt_prev = cur->sbt_cur;
1277 	nex->hw_cur = hw;
1278 	nex->sbt_cur = sbt;
1279 	seqc_write_end(&nex->gen);
1280 	sc->cal_current = next_up;
1281 done:
1282 	callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration,
1283 	    sc, C_DIRECT_EXEC);
1284 }
1285 
1286 static void
1287 t4_calibration_start(struct adapter *sc)
1288 {
1289 	/*
1290 	 * Here if we have not done a calibration
1291 	 * then do so otherwise start the appropriate
1292 	 * timer.
1293 	 */
1294 	int i;
1295 
1296 	for (i = 0; i < CNT_CAL_INFO; i++) {
1297 		sc->cal_info[i].gen = 0;
1298 	}
1299 	sc->cal_current = 0;
1300 	sc->cal_count = 0;
1301 	sc->cal_gen = 0;
1302 	t4_calibration(sc);
1303 }
1304 
1305 static int
1306 t4_attach(device_t dev)
1307 {
1308 	struct adapter *sc;
1309 	int rc = 0, i, j, rqidx, tqidx, nports;
1310 	struct make_dev_args mda;
1311 	struct intrs_and_queues iaq;
1312 	struct sge *s;
1313 	uint32_t *buf;
1314 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1315 	int ofld_tqidx;
1316 #endif
1317 #ifdef TCP_OFFLOAD
1318 	int ofld_rqidx;
1319 #endif
1320 #ifdef DEV_NETMAP
1321 	int nm_rqidx, nm_tqidx;
1322 #endif
1323 	int num_vis;
1324 
1325 	sc = device_get_softc(dev);
1326 	sc->dev = dev;
1327 	sysctl_ctx_init(&sc->ctx);
1328 	TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
1329 	if (TUNABLE_INT_FETCH("hw.cxgbe.iflags", &sc->intr_flags) == 0)
1330 		sc->intr_flags = IHF_INTR_CLEAR_ON_INIT | IHF_CLR_ALL_UNIGNORED;
1331 
1332 	if ((pci_get_device(dev) & 0xff00) == 0x5400)
1333 		t5_attribute_workaround(dev);
1334 	pci_enable_busmaster(dev);
1335 	if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
1336 		uint32_t v;
1337 
1338 		pci_set_max_read_req(dev, 4096);
1339 		v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
1340 		sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
1341 		if (pcie_relaxed_ordering == 0 &&
1342 		    (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
1343 			v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
1344 			pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1345 		} else if (pcie_relaxed_ordering == 1 &&
1346 		    (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
1347 			v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
1348 			pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1349 		}
1350 	}
1351 
1352 	sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
1353 	sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
1354 	sc->traceq = -1;
1355 	mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
1356 	snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
1357 	    device_get_nameunit(dev));
1358 
1359 	snprintf(sc->lockname, sizeof(sc->lockname), "%s",
1360 	    device_get_nameunit(dev));
1361 	mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
1362 	t4_add_adapter(sc);
1363 
1364 	mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
1365 	TAILQ_INIT(&sc->sfl);
1366 	callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
1367 
1368 	mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1369 
1370 	sc->policy = NULL;
1371 	rw_init(&sc->policy_lock, "connection offload policy");
1372 
1373 	callout_init(&sc->ktls_tick, 1);
1374 
1375 	callout_init(&sc->cal_callout, 1);
1376 
1377 	refcount_init(&sc->vxlan_refcount, 0);
1378 
1379 	TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc);
1380 	TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc);
1381 
1382 	sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1383 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq",
1384 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues");
1385 	sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1386 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq",
1387 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue");
1388 
1389 	rc = t4_map_bars_0_and_4(sc);
1390 	if (rc != 0)
1391 		goto done; /* error message displayed already */
1392 
1393 	memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1394 	memset(sc->port_map, 0xff, sizeof(sc->port_map));
1395 
1396 	/* Prepare the adapter for operation. */
1397 	buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1398 	rc = -t4_prep_adapter(sc, buf);
1399 	free(buf, M_CXGBE);
1400 	if (rc != 0) {
1401 		device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1402 		goto done;
1403 	}
1404 
1405 	/*
1406 	 * This is the real PF# to which we're attaching.  Works from within PCI
1407 	 * passthrough environments too, where pci_get_function() could return a
1408 	 * different PF# depending on the passthrough configuration.  We need to
1409 	 * use the real PF# in all our communication with the firmware.
1410 	 */
1411 	j = t4_read_reg(sc, A_PL_WHOAMI);
1412 	sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1413 	sc->mbox = sc->pf;
1414 
1415 	t4_init_devnames(sc);
1416 	if (sc->names == NULL) {
1417 		rc = ENOTSUP;
1418 		goto done; /* error message displayed already */
1419 	}
1420 
1421 	/*
1422 	 * Do this really early, with the memory windows set up even before the
1423 	 * character device.  The userland tool's register i/o and mem read
1424 	 * will work even in "recovery mode".
1425 	 */
1426 	setup_memwin(sc);
1427 	if (t4_init_devlog_ncores_params(sc, 0) == 0)
1428 		fixup_devlog_params(sc);
1429 	make_dev_args_init(&mda);
1430 	mda.mda_devsw = &t4_cdevsw;
1431 	mda.mda_uid = UID_ROOT;
1432 	mda.mda_gid = GID_WHEEL;
1433 	mda.mda_mode = 0600;
1434 	mda.mda_si_drv1 = sc;
1435 	rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1436 	if (rc != 0)
1437 		device_printf(dev, "failed to create nexus char device: %d.\n",
1438 		    rc);
1439 
1440 	/* Go no further if recovery mode has been requested. */
1441 	if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1442 		device_printf(dev, "recovery mode.\n");
1443 		goto done;
1444 	}
1445 
1446 #if defined(__i386__)
1447 	if ((cpu_feature & CPUID_CX8) == 0) {
1448 		device_printf(dev, "64 bit atomics not available.\n");
1449 		rc = ENOTSUP;
1450 		goto done;
1451 	}
1452 #endif
1453 
1454 	/* Contact the firmware and try to become the master driver. */
1455 	rc = contact_firmware(sc);
1456 	if (rc != 0)
1457 		goto done; /* error message displayed already */
1458 	MPASS(sc->flags & FW_OK);
1459 
1460 	rc = get_params__pre_init(sc);
1461 	if (rc != 0)
1462 		goto done; /* error message displayed already */
1463 
1464 	if (sc->flags & MASTER_PF) {
1465 		rc = partition_resources(sc);
1466 		if (rc != 0)
1467 			goto done; /* error message displayed already */
1468 	}
1469 
1470 	rc = get_params__post_init(sc);
1471 	if (rc != 0)
1472 		goto done; /* error message displayed already */
1473 
1474 	rc = set_params__post_init(sc);
1475 	if (rc != 0)
1476 		goto done; /* error message displayed already */
1477 
1478 	rc = t4_map_bar_2(sc);
1479 	if (rc != 0)
1480 		goto done; /* error message displayed already */
1481 
1482 	rc = t4_adj_doorbells(sc);
1483 	if (rc != 0)
1484 		goto done; /* error message displayed already */
1485 
1486 	rc = t4_create_dma_tag(sc);
1487 	if (rc != 0)
1488 		goto done; /* error message displayed already */
1489 
1490 	/*
1491 	 * First pass over all the ports - allocate VIs and initialize some
1492 	 * basic parameters like mac address, port type, etc.
1493 	 */
1494 	for_each_port(sc, i) {
1495 		struct port_info *pi;
1496 
1497 		pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1498 		sc->port[i] = pi;
1499 
1500 		/* These must be set before t4_port_init */
1501 		pi->adapter = sc;
1502 		pi->port_id = i;
1503 		/*
1504 		 * XXX: vi[0] is special so we can't delay this allocation until
1505 		 * pi->nvi's final value is known.
1506 		 */
1507 		pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1508 		    M_ZERO | M_WAITOK);
1509 
1510 		/*
1511 		 * Allocate the "main" VI and initialize parameters
1512 		 * like mac addr.
1513 		 */
1514 		rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1515 		if (rc != 0) {
1516 			device_printf(dev, "unable to initialize port %d: %d\n",
1517 			    i, rc);
1518 			free(pi->vi, M_CXGBE);
1519 			free(pi, M_CXGBE);
1520 			sc->port[i] = NULL;
1521 			goto done;
1522 		}
1523 
1524 		if (is_bt(pi->port_type))
1525 			setbit(&sc->bt_map, pi->hw_port);
1526 		else
1527 			MPASS(!isset(&sc->bt_map, pi->hw_port));
1528 
1529 		snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1530 		    device_get_nameunit(dev), i);
1531 		mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1532 		for (j = 0; j < sc->params.tp.lb_nchan; j++)
1533 			sc->chan_map[pi->tx_chan + j] = i;
1534 		sc->port_map[pi->hw_port] = i;
1535 
1536 		/*
1537 		 * The MPS counter for FCS errors doesn't work correctly on the
1538 		 * T6 so we use the MAC counter here.  Which MAC is in use
1539 		 * depends on the link settings which will be known when the
1540 		 * link comes up.
1541 		 */
1542 		if (is_t6(sc))
1543 			pi->fcs_reg = -1;
1544 		else
1545 			pi->fcs_reg = A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L;
1546 		pi->fcs_base = 0;
1547 
1548 		/* All VIs on this port share this media. */
1549 		ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1550 		    cxgbe_media_status);
1551 
1552 		PORT_LOCK(pi);
1553 		init_link_config(pi);
1554 		fixup_link_config(pi);
1555 		build_medialist(pi);
1556 		if (fixed_ifmedia(pi))
1557 			pi->flags |= FIXED_IFMEDIA;
1558 		PORT_UNLOCK(pi);
1559 
1560 		pi->dev = device_add_child(dev, sc->names->ifnet_name,
1561 		    t4_ifnet_unit(sc, pi));
1562 		if (pi->dev == NULL) {
1563 			device_printf(dev,
1564 			    "failed to add device for port %d.\n", i);
1565 			rc = ENXIO;
1566 			goto done;
1567 		}
1568 		pi->vi[0].dev = pi->dev;
1569 		device_set_softc(pi->dev, pi);
1570 	}
1571 
1572 	/*
1573 	 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1574 	 */
1575 	nports = sc->params.nports;
1576 	rc = cfg_itype_and_nqueues(sc, &iaq);
1577 	if (rc != 0)
1578 		goto done; /* error message displayed already */
1579 
1580 	num_vis = iaq.num_vis;
1581 	sc->intr_type = iaq.intr_type;
1582 	sc->intr_count = iaq.nirq;
1583 
1584 	s = &sc->sge;
1585 	s->nctrlq = max(sc->params.nports, sc->params.ncores);
1586 	s->nrxq = nports * iaq.nrxq;
1587 	s->ntxq = nports * iaq.ntxq;
1588 	if (num_vis > 1) {
1589 		s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1590 		s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1591 	}
1592 	s->neq = s->ntxq + s->nrxq;	/* the free list in an rxq is an eq */
1593 	s->neq += nports;		/* ctrl queues: 1 per port */
1594 	s->niq = s->nrxq + 1;		/* 1 extra for firmware event queue */
1595 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1596 	if (is_offload(sc) || is_ethoffload(sc)) {
1597 		s->nofldtxq = nports * iaq.nofldtxq;
1598 		if (num_vis > 1)
1599 			s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1600 		s->neq += s->nofldtxq;
1601 
1602 		s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq),
1603 		    M_CXGBE, M_ZERO | M_WAITOK);
1604 	}
1605 #endif
1606 #ifdef TCP_OFFLOAD
1607 	if (is_offload(sc)) {
1608 		s->nofldrxq = nports * iaq.nofldrxq;
1609 		if (num_vis > 1)
1610 			s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1611 		s->neq += s->nofldrxq;	/* free list */
1612 		s->niq += s->nofldrxq;
1613 
1614 		s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1615 		    M_CXGBE, M_ZERO | M_WAITOK);
1616 	}
1617 #endif
1618 #ifdef DEV_NETMAP
1619 	s->nnmrxq = 0;
1620 	s->nnmtxq = 0;
1621 	if (t4_native_netmap & NN_MAIN_VI) {
1622 		s->nnmrxq += nports * iaq.nnmrxq;
1623 		s->nnmtxq += nports * iaq.nnmtxq;
1624 	}
1625 	if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) {
1626 		s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi;
1627 		s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi;
1628 	}
1629 	s->neq += s->nnmtxq + s->nnmrxq;
1630 	s->niq += s->nnmrxq;
1631 
1632 	s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1633 	    M_CXGBE, M_ZERO | M_WAITOK);
1634 	s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1635 	    M_CXGBE, M_ZERO | M_WAITOK);
1636 #endif
1637 	MPASS(s->niq <= s->iqmap_sz);
1638 	MPASS(s->neq <= s->eqmap_sz);
1639 
1640 	s->ctrlq = malloc(s->nctrlq * sizeof(struct sge_wrq), M_CXGBE,
1641 	    M_ZERO | M_WAITOK);
1642 	s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1643 	    M_ZERO | M_WAITOK);
1644 	s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1645 	    M_ZERO | M_WAITOK);
1646 	s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE,
1647 	    M_ZERO | M_WAITOK);
1648 	s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE,
1649 	    M_ZERO | M_WAITOK);
1650 
1651 	sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1652 	    M_ZERO | M_WAITOK);
1653 
1654 	t4_init_l2t(sc, M_WAITOK);
1655 	t4_init_smt(sc, M_WAITOK);
1656 	t4_init_tx_sched(sc);
1657 	t4_init_atid_table(sc);
1658 #ifdef RATELIMIT
1659 	t4_init_etid_table(sc);
1660 #endif
1661 #ifdef INET6
1662 	t4_init_clip_table(sc);
1663 #endif
1664 	if (sc->vres.key.size != 0)
1665 		sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1666 		    sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1667 	t4_init_tpt(sc);
1668 
1669 	/*
1670 	 * Second pass over the ports.  This time we know the number of rx and
1671 	 * tx queues that each port should get.
1672 	 */
1673 	rqidx = tqidx = 0;
1674 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1675 	ofld_tqidx = 0;
1676 #endif
1677 #ifdef TCP_OFFLOAD
1678 	ofld_rqidx = 0;
1679 #endif
1680 #ifdef DEV_NETMAP
1681 	nm_rqidx = nm_tqidx = 0;
1682 #endif
1683 	for_each_port(sc, i) {
1684 		struct port_info *pi = sc->port[i];
1685 		struct vi_info *vi;
1686 
1687 		if (pi == NULL)
1688 			continue;
1689 
1690 		pi->nvi = num_vis;
1691 		for_each_vi(pi, j, vi) {
1692 			vi->pi = pi;
1693 			vi->adapter = sc;
1694 			vi->first_intr = -1;
1695 			vi->qsize_rxq = t4_qsize_rxq;
1696 			vi->qsize_txq = t4_qsize_txq;
1697 
1698 			vi->first_rxq = rqidx;
1699 			vi->first_txq = tqidx;
1700 			vi->tmr_idx = t4_tmr_idx;
1701 			vi->pktc_idx = t4_pktc_idx;
1702 			vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1703 			vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1704 
1705 			rqidx += vi->nrxq;
1706 			tqidx += vi->ntxq;
1707 
1708 			if (j == 0 && vi->ntxq > 1)
1709 				vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1710 			else
1711 				vi->rsrv_noflowq = 0;
1712 
1713 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1714 			vi->first_ofld_txq = ofld_tqidx;
1715 			vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1716 			ofld_tqidx += vi->nofldtxq;
1717 #endif
1718 #ifdef TCP_OFFLOAD
1719 			vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1720 			vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1721 			vi->first_ofld_rxq = ofld_rqidx;
1722 			vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1723 
1724 			ofld_rqidx += vi->nofldrxq;
1725 #endif
1726 #ifdef DEV_NETMAP
1727 			vi->first_nm_rxq = nm_rqidx;
1728 			vi->first_nm_txq = nm_tqidx;
1729 			if (j == 0) {
1730 				vi->nnmrxq = iaq.nnmrxq;
1731 				vi->nnmtxq = iaq.nnmtxq;
1732 			} else {
1733 				vi->nnmrxq = iaq.nnmrxq_vi;
1734 				vi->nnmtxq = iaq.nnmtxq_vi;
1735 			}
1736 			nm_rqidx += vi->nnmrxq;
1737 			nm_tqidx += vi->nnmtxq;
1738 #endif
1739 		}
1740 	}
1741 
1742 	rc = t4_setup_intr_handlers(sc);
1743 	if (rc != 0) {
1744 		device_printf(dev,
1745 		    "failed to setup interrupt handlers: %d\n", rc);
1746 		goto done;
1747 	}
1748 
1749 	bus_identify_children(dev);
1750 
1751 	/*
1752 	 * Ensure thread-safe mailbox access (in debug builds).
1753 	 *
1754 	 * So far this was the only thread accessing the mailbox but various
1755 	 * ifnets and sysctls are about to be created and their handlers/ioctls
1756 	 * will access the mailbox from different threads.
1757 	 */
1758 	sc->flags |= CHK_MBOX_ACCESS;
1759 
1760 	bus_attach_children(dev);
1761 	t4_calibration_start(sc);
1762 
1763 	device_printf(dev,
1764 	    "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1765 	    sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1766 	    sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1767 	    (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1768 	    sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1769 
1770 	t4_set_desc(sc);
1771 
1772 	notify_siblings(dev, 0);
1773 
1774 done:
1775 	if (rc != 0 && sc->cdev) {
1776 		/* cdev was created and so cxgbetool works; recover that way. */
1777 		device_printf(dev,
1778 		    "error during attach, adapter is now in recovery mode.\n");
1779 		rc = 0;
1780 	}
1781 
1782 	if (rc != 0)
1783 		t4_detach_common(dev);
1784 	else
1785 		t4_sysctls(sc);
1786 
1787 	return (rc);
1788 }
1789 
1790 static int
1791 t4_child_location(device_t bus, device_t dev, struct sbuf *sb)
1792 {
1793 	struct adapter *sc;
1794 	struct port_info *pi;
1795 	int i;
1796 
1797 	sc = device_get_softc(bus);
1798 	for_each_port(sc, i) {
1799 		pi = sc->port[i];
1800 		if (pi != NULL && pi->dev == dev) {
1801 			sbuf_printf(sb, "port=%d", pi->port_id);
1802 			break;
1803 		}
1804 	}
1805 	return (0);
1806 }
1807 
1808 static int
1809 t4_ready(device_t dev)
1810 {
1811 	struct adapter *sc;
1812 
1813 	sc = device_get_softc(dev);
1814 	if (sc->flags & FW_OK)
1815 		return (0);
1816 	return (ENXIO);
1817 }
1818 
1819 static int
1820 t4_read_port_device(device_t dev, int port, device_t *child)
1821 {
1822 	struct adapter *sc;
1823 	struct port_info *pi;
1824 
1825 	sc = device_get_softc(dev);
1826 	if (port < 0 || port >= MAX_NPORTS)
1827 		return (EINVAL);
1828 	pi = sc->port[port];
1829 	if (pi == NULL || pi->dev == NULL)
1830 		return (ENXIO);
1831 	*child = pi->dev;
1832 	return (0);
1833 }
1834 
1835 static int
1836 notify_siblings(device_t dev, int detaching)
1837 {
1838 	device_t sibling;
1839 	int error, i;
1840 
1841 	error = 0;
1842 	for (i = 0; i < PCI_FUNCMAX; i++) {
1843 		if (i == pci_get_function(dev))
1844 			continue;
1845 		sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1846 		    pci_get_slot(dev), i);
1847 		if (sibling == NULL || !device_is_attached(sibling))
1848 			continue;
1849 		if (detaching)
1850 			error = T4_DETACH_CHILD(sibling);
1851 		else
1852 			(void)T4_ATTACH_CHILD(sibling);
1853 		if (error)
1854 			break;
1855 	}
1856 	return (error);
1857 }
1858 
1859 /*
1860  * Idempotent
1861  */
1862 static int
1863 t4_detach(device_t dev)
1864 {
1865 	int rc;
1866 
1867 	rc = notify_siblings(dev, 1);
1868 	if (rc) {
1869 		device_printf(dev,
1870 		    "failed to detach sibling devices: %d\n", rc);
1871 		return (rc);
1872 	}
1873 
1874 	return (t4_detach_common(dev));
1875 }
1876 
1877 int
1878 t4_detach_common(device_t dev)
1879 {
1880 	struct adapter *sc;
1881 	struct port_info *pi;
1882 	int i, rc;
1883 
1884 	sc = device_get_softc(dev);
1885 
1886 #ifdef TCP_OFFLOAD
1887 	rc = deactivate_all_uld(sc);
1888 	if (rc) {
1889 		device_printf(dev,
1890 		    "failed to detach upper layer drivers: %d\n", rc);
1891 		return (rc);
1892 	}
1893 #endif
1894 
1895 	if (sc->cdev) {
1896 		destroy_dev(sc->cdev);
1897 		sc->cdev = NULL;
1898 	}
1899 
1900 	sx_xlock(&t4_list_lock);
1901 	SLIST_REMOVE(&t4_list, sc, adapter, link);
1902 	sx_xunlock(&t4_list_lock);
1903 
1904 	sc->flags &= ~CHK_MBOX_ACCESS;
1905 	if (sc->flags & FULL_INIT_DONE) {
1906 		if (!(sc->flags & IS_VF))
1907 			t4_intr_disable(sc);
1908 	}
1909 
1910 	if (device_is_attached(dev)) {
1911 		rc = bus_detach_children(dev);
1912 		if (rc) {
1913 			device_printf(dev,
1914 			    "failed to detach child devices: %d\n", rc);
1915 			return (rc);
1916 		}
1917 	}
1918 
1919 	for (i = 0; i < sc->intr_count; i++)
1920 		t4_free_irq(sc, &sc->irq[i]);
1921 
1922 	if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1923 		t4_free_tx_sched(sc);
1924 
1925 	for (i = 0; i < MAX_NPORTS; i++) {
1926 		pi = sc->port[i];
1927 		if (pi) {
1928 			t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1929 
1930 			mtx_destroy(&pi->pi_lock);
1931 			free(pi->vi, M_CXGBE);
1932 			free(pi, M_CXGBE);
1933 		}
1934 	}
1935 	callout_stop(&sc->cal_callout);
1936 	callout_drain(&sc->cal_callout);
1937 	device_delete_children(dev);
1938 	sysctl_ctx_free(&sc->ctx);
1939 	adapter_full_uninit(sc);
1940 
1941 	if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1942 		t4_fw_bye(sc, sc->mbox);
1943 
1944 	if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1945 		pci_release_msi(dev);
1946 
1947 	if (sc->regs_res)
1948 		bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1949 		    sc->regs_res);
1950 
1951 	if (sc->udbs_res)
1952 		bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1953 		    sc->udbs_res);
1954 
1955 	if (sc->msix_res)
1956 		bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1957 		    sc->msix_res);
1958 
1959 	if (sc->l2t)
1960 		t4_free_l2t(sc);
1961 	if (sc->smt)
1962 		t4_free_smt(sc->smt);
1963 	t4_free_atid_table(sc);
1964 #ifdef RATELIMIT
1965 	t4_free_etid_table(sc);
1966 #endif
1967 	if (sc->key_map)
1968 		vmem_destroy(sc->key_map);
1969 	t4_free_tpt(sc);
1970 #ifdef INET6
1971 	t4_destroy_clip_table(sc);
1972 #endif
1973 
1974 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1975 	free(sc->sge.ofld_txq, M_CXGBE);
1976 #endif
1977 #ifdef TCP_OFFLOAD
1978 	free(sc->sge.ofld_rxq, M_CXGBE);
1979 #endif
1980 #ifdef DEV_NETMAP
1981 	free(sc->sge.nm_rxq, M_CXGBE);
1982 	free(sc->sge.nm_txq, M_CXGBE);
1983 #endif
1984 	free(sc->irq, M_CXGBE);
1985 	free(sc->sge.rxq, M_CXGBE);
1986 	free(sc->sge.txq, M_CXGBE);
1987 	free(sc->sge.ctrlq, M_CXGBE);
1988 	free(sc->sge.iqmap, M_CXGBE);
1989 	free(sc->sge.eqmap, M_CXGBE);
1990 	free(sc->tids.ftid_tab, M_CXGBE);
1991 	free(sc->tids.hpftid_tab, M_CXGBE);
1992 	free_hftid_hash(&sc->tids);
1993 	free(sc->tids.tid_tab, M_CXGBE);
1994 	t4_destroy_dma_tag(sc);
1995 
1996 	callout_drain(&sc->ktls_tick);
1997 	callout_drain(&sc->sfl_callout);
1998 	if (mtx_initialized(&sc->tids.ftid_lock)) {
1999 		mtx_destroy(&sc->tids.ftid_lock);
2000 		cv_destroy(&sc->tids.ftid_cv);
2001 	}
2002 	if (mtx_initialized(&sc->tids.atid_lock))
2003 		mtx_destroy(&sc->tids.atid_lock);
2004 	if (mtx_initialized(&sc->ifp_lock))
2005 		mtx_destroy(&sc->ifp_lock);
2006 
2007 	if (rw_initialized(&sc->policy_lock)) {
2008 		rw_destroy(&sc->policy_lock);
2009 #ifdef TCP_OFFLOAD
2010 		if (sc->policy != NULL)
2011 			free_offload_policy(sc->policy);
2012 #endif
2013 	}
2014 
2015 	for (i = 0; i < NUM_MEMWIN; i++) {
2016 		struct memwin *mw = &sc->memwin[i];
2017 
2018 		if (rw_initialized(&mw->mw_lock))
2019 			rw_destroy(&mw->mw_lock);
2020 	}
2021 
2022 	mtx_destroy(&sc->sfl_lock);
2023 	mtx_destroy(&sc->reg_lock);
2024 	mtx_destroy(&sc->sc_lock);
2025 
2026 	bzero(sc, sizeof(*sc));
2027 
2028 	return (0);
2029 }
2030 
2031 static inline int
2032 stop_adapter(struct adapter *sc)
2033 {
2034 	struct port_info *pi;
2035 	int i;
2036 
2037 	if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) {
2038 		CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n",
2039 			 __func__, curthread, sc->flags, sc->error_flags);
2040 		return (EALREADY);
2041 	}
2042 	CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread,
2043 		 sc->flags, sc->error_flags);
2044 	t4_shutdown_adapter(sc);
2045 	for_each_port(sc, i) {
2046 		pi = sc->port[i];
2047 		if (pi == NULL)
2048 			continue;
2049 		PORT_LOCK(pi);
2050 		if (pi->up_vis > 0 && pi->link_cfg.link_ok) {
2051 			/*
2052 			 * t4_shutdown_adapter has already shut down all the
2053 			 * PHYs but it also disables interrupts and DMA so there
2054 			 * won't be a link interrupt.  Update the state manually
2055 			 * if the link was up previously and inform the kernel.
2056 			 */
2057 			pi->link_cfg.link_ok = false;
2058 			t4_os_link_changed(pi);
2059 		}
2060 		PORT_UNLOCK(pi);
2061 	}
2062 
2063 	return (0);
2064 }
2065 
2066 static inline int
2067 restart_adapter(struct adapter *sc)
2068 {
2069 	uint32_t val;
2070 
2071 	if (!atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_STOPPED))) {
2072 		CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n",
2073 			 __func__, curthread, sc->flags, sc->error_flags);
2074 		return (EALREADY);
2075 	}
2076 	CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread,
2077 		 sc->flags, sc->error_flags);
2078 
2079 	MPASS(hw_off_limits(sc));
2080 	MPASS((sc->flags & FW_OK) == 0);
2081 	MPASS((sc->flags & MASTER_PF) == 0);
2082 	MPASS(sc->reset_thread == NULL);
2083 
2084 	/*
2085 	 * The adapter is supposed to be back on PCIE with its config space and
2086 	 * BARs restored to their state before reset.  Register access via
2087 	 * t4_read_reg BAR0 should just work.
2088 	 */
2089 	sc->reset_thread = curthread;
2090 	val = t4_read_reg(sc, A_PL_WHOAMI);
2091 	if (val == 0xffffffff || val == 0xeeeeeeee) {
2092 		CH_ERR(sc, "%s: device registers not readable.\n", __func__);
2093 		sc->reset_thread = NULL;
2094 		atomic_set_int(&sc->error_flags, ADAP_STOPPED);
2095 		return (ENXIO);
2096 	}
2097 	atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR);
2098 	atomic_add_int(&sc->incarnation, 1);
2099 	atomic_add_int(&sc->num_resets, 1);
2100 
2101 	return (0);
2102 }
2103 
2104 static inline void
2105 set_adapter_hwstatus(struct adapter *sc, const bool usable)
2106 {
2107 	if (usable) {
2108 		/* Must be marked reusable by the designated thread. */
2109 		ASSERT_SYNCHRONIZED_OP(sc);
2110 		MPASS(sc->reset_thread == curthread);
2111 		mtx_lock(&sc->reg_lock);
2112 		atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS);
2113 		mtx_unlock(&sc->reg_lock);
2114 	} else {
2115 		/* Mark the adapter totally off limits. */
2116 		begin_synchronized_op(sc, NULL, SLEEP_OK, "t4hwsts");
2117 		mtx_lock(&sc->reg_lock);
2118 		atomic_set_int(&sc->error_flags, HW_OFF_LIMITS);
2119 		mtx_unlock(&sc->reg_lock);
2120 		sc->flags &= ~(FW_OK | MASTER_PF);
2121 		sc->reset_thread = NULL;
2122 		end_synchronized_op(sc, 0);
2123 	}
2124 }
2125 
2126 static int
2127 stop_lld(struct adapter *sc)
2128 {
2129 	struct port_info *pi;
2130 	struct vi_info *vi;
2131 	if_t ifp;
2132 	struct sge_rxq *rxq;
2133 	struct sge_txq *txq;
2134 	struct sge_wrq *wrq;
2135 #ifdef TCP_OFFLOAD
2136 	struct sge_ofld_rxq *ofld_rxq;
2137 #endif
2138 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2139 	struct sge_ofld_txq *ofld_txq;
2140 #endif
2141 	int rc, i, j, k;
2142 
2143 	/*
2144 	 * XXX: Can there be a synch_op in progress that will hang because
2145 	 * hardware has been stopped?  We'll hang too and the solution will be
2146 	 * to use a version of begin_synch_op that wakes up existing synch_op
2147 	 * with errors.  Maybe stop_adapter should do this wakeup?
2148 	 *
2149 	 * I don't think any synch_op could get stranded waiting for DMA or
2150 	 * interrupt so I think we're okay here.  Remove this comment block
2151 	 * after testing.
2152 	 */
2153 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4slld");
2154 	if (rc != 0)
2155 		return (ENXIO);
2156 
2157 	/* Quiesce all activity. */
2158 	for_each_port(sc, i) {
2159 		pi = sc->port[i];
2160 		if (pi == NULL)
2161 			continue;
2162 		pi->vxlan_tcam_entry = false;
2163 		for_each_vi(pi, j, vi) {
2164 			vi->xact_addr_filt = -1;
2165 			mtx_lock(&vi->tick_mtx);
2166 			vi->flags |= VI_SKIP_STATS;
2167 			mtx_unlock(&vi->tick_mtx);
2168 			if (!(vi->flags & VI_INIT_DONE))
2169 				continue;
2170 
2171 			ifp = vi->ifp;
2172 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2173 				mtx_lock(&vi->tick_mtx);
2174 				callout_stop(&vi->tick);
2175 				mtx_unlock(&vi->tick_mtx);
2176 				callout_drain(&vi->tick);
2177 			}
2178 
2179 			/*
2180 			 * Note that the HW is not available.
2181 			 */
2182 			for_each_txq(vi, k, txq) {
2183 				TXQ_LOCK(txq);
2184 				txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED);
2185 				TXQ_UNLOCK(txq);
2186 			}
2187 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2188 			for_each_ofld_txq(vi, k, ofld_txq) {
2189 				TXQ_LOCK(&ofld_txq->wrq);
2190 				ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED;
2191 				TXQ_UNLOCK(&ofld_txq->wrq);
2192 			}
2193 #endif
2194 			for_each_rxq(vi, k, rxq) {
2195 				rxq->iq.flags &= ~IQ_HW_ALLOCATED;
2196 			}
2197 #if defined(TCP_OFFLOAD)
2198 			for_each_ofld_rxq(vi, k, ofld_rxq) {
2199 				ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED;
2200 			}
2201 #endif
2202 
2203 			quiesce_vi(vi);
2204 		}
2205 
2206 		if (sc->flags & FULL_INIT_DONE) {
2207 			/* Control queue */
2208 			wrq = &sc->sge.ctrlq[i];
2209 			TXQ_LOCK(wrq);
2210 			wrq->eq.flags &= ~EQ_HW_ALLOCATED;
2211 			TXQ_UNLOCK(wrq);
2212 			quiesce_wrq(wrq);
2213 		}
2214 
2215 		if (pi->flags & HAS_TRACEQ) {
2216 			pi->flags &= ~HAS_TRACEQ;
2217 			sc->traceq = -1;
2218 			sc->tracer_valid = 0;
2219 			sc->tracer_enabled = 0;
2220 		}
2221 	}
2222 	if (sc->flags & FULL_INIT_DONE) {
2223 		/* Firmware event queue */
2224 		sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED;
2225 		quiesce_iq_fl(sc, &sc->sge.fwq, NULL);
2226 	}
2227 
2228 	/* Stop calibration */
2229 	callout_stop(&sc->cal_callout);
2230 	callout_drain(&sc->cal_callout);
2231 
2232 	if (t4_clock_gate_on_suspend) {
2233 		t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN |
2234 		    F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN |
2235 		    F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0);
2236 	}
2237 
2238 	end_synchronized_op(sc, 0);
2239 
2240 	stop_atid_allocator(sc);
2241 	t4_stop_l2t(sc);
2242 
2243 	return (rc);
2244 }
2245 
2246 int
2247 suspend_adapter(struct adapter *sc)
2248 {
2249 	stop_adapter(sc);
2250 	stop_lld(sc);
2251 #ifdef TCP_OFFLOAD
2252 	stop_all_uld(sc);
2253 #endif
2254 	set_adapter_hwstatus(sc, false);
2255 
2256 	return (0);
2257 }
2258 
2259 static int
2260 t4_suspend(device_t dev)
2261 {
2262 	struct adapter *sc = device_get_softc(dev);
2263 	int rc;
2264 
2265 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2266 	rc = suspend_adapter(sc);
2267 	CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread);
2268 
2269 	return (rc);
2270 }
2271 
2272 struct adapter_pre_reset_state {
2273 	u_int flags;
2274 	uint16_t nbmcaps;
2275 	uint16_t linkcaps;
2276 	uint16_t switchcaps;
2277 	uint16_t nvmecaps;
2278 	uint16_t niccaps;
2279 	uint16_t toecaps;
2280 	uint16_t rdmacaps;
2281 	uint16_t cryptocaps;
2282 	uint16_t iscsicaps;
2283 	uint16_t fcoecaps;
2284 
2285 	u_int cfcsum;
2286 	char cfg_file[32];
2287 
2288 	struct adapter_params params;
2289 	struct t4_virt_res vres;
2290 	struct tid_info tids;
2291 	struct sge sge;
2292 
2293 	int rawf_base;
2294 	int nrawf;
2295 
2296 };
2297 
2298 static void
2299 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2300 {
2301 
2302 	ASSERT_SYNCHRONIZED_OP(sc);
2303 
2304 	o->flags = sc->flags;
2305 
2306 	o->nbmcaps =  sc->nbmcaps;
2307 	o->linkcaps = sc->linkcaps;
2308 	o->switchcaps = sc->switchcaps;
2309 	o->nvmecaps = sc->nvmecaps;
2310 	o->niccaps = sc->niccaps;
2311 	o->toecaps = sc->toecaps;
2312 	o->rdmacaps = sc->rdmacaps;
2313 	o->cryptocaps = sc->cryptocaps;
2314 	o->iscsicaps = sc->iscsicaps;
2315 	o->fcoecaps = sc->fcoecaps;
2316 
2317 	o->cfcsum = sc->cfcsum;
2318 	MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file));
2319 	memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file));
2320 
2321 	o->params = sc->params;
2322 	o->vres = sc->vres;
2323 	o->tids = sc->tids;
2324 	o->sge = sc->sge;
2325 
2326 	o->rawf_base = sc->rawf_base;
2327 	o->nrawf = sc->nrawf;
2328 }
2329 
2330 static int
2331 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2332 {
2333 	int rc = 0;
2334 
2335 	ASSERT_SYNCHRONIZED_OP(sc);
2336 
2337 	/* Capabilities */
2338 #define COMPARE_CAPS(c) do { \
2339 	if (o->c##caps != sc->c##caps) { \
2340 		CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \
2341 		    sc->c##caps); \
2342 		rc = EINVAL; \
2343 	} \
2344 } while (0)
2345 	COMPARE_CAPS(nbm);
2346 	COMPARE_CAPS(link);
2347 	COMPARE_CAPS(switch);
2348 	COMPARE_CAPS(nvme);
2349 	COMPARE_CAPS(nic);
2350 	COMPARE_CAPS(toe);
2351 	COMPARE_CAPS(rdma);
2352 	COMPARE_CAPS(crypto);
2353 	COMPARE_CAPS(iscsi);
2354 	COMPARE_CAPS(fcoe);
2355 #undef COMPARE_CAPS
2356 
2357 	/* Firmware config file */
2358 	if (o->cfcsum != sc->cfcsum) {
2359 		CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file,
2360 		    o->cfcsum, sc->cfg_file, sc->cfcsum);
2361 		rc = EINVAL;
2362 	}
2363 
2364 #define COMPARE_PARAM(p, name) do { \
2365 	if (o->p != sc->p) { \
2366 		CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \
2367 		rc = EINVAL; \
2368 	} \
2369 } while (0)
2370 	COMPARE_PARAM(sge.iq_start, iq_start);
2371 	COMPARE_PARAM(sge.eq_start, eq_start);
2372 	COMPARE_PARAM(tids.ftid_base, ftid_base);
2373 	COMPARE_PARAM(tids.ftid_end, ftid_end);
2374 	COMPARE_PARAM(tids.nftids, nftids);
2375 	COMPARE_PARAM(vres.l2t.start, l2t_start);
2376 	COMPARE_PARAM(vres.l2t.size, l2t_size);
2377 	COMPARE_PARAM(sge.iqmap_sz, iqmap_sz);
2378 	COMPARE_PARAM(sge.eqmap_sz, eqmap_sz);
2379 	COMPARE_PARAM(tids.tid_base, tid_base);
2380 	COMPARE_PARAM(tids.hpftid_base, hpftid_base);
2381 	COMPARE_PARAM(tids.hpftid_end, hpftid_end);
2382 	COMPARE_PARAM(tids.nhpftids, nhpftids);
2383 	COMPARE_PARAM(rawf_base, rawf_base);
2384 	COMPARE_PARAM(nrawf, nrawf);
2385 	COMPARE_PARAM(params.mps_bg_map, mps_bg_map);
2386 	COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support);
2387 	COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl);
2388 	COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support);
2389 	COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr);
2390 	COMPARE_PARAM(tids.ntids, ntids);
2391 	COMPARE_PARAM(tids.etid_base, etid_base);
2392 	COMPARE_PARAM(tids.etid_end, etid_end);
2393 	COMPARE_PARAM(tids.netids, netids);
2394 	COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred);
2395 	COMPARE_PARAM(params.ethoffload, ethoffload);
2396 	COMPARE_PARAM(tids.natids, natids);
2397 	COMPARE_PARAM(tids.stid_base, stid_base);
2398 	COMPARE_PARAM(vres.ddp.start, ddp_start);
2399 	COMPARE_PARAM(vres.ddp.size, ddp_size);
2400 	COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred);
2401 	COMPARE_PARAM(vres.stag.start, stag_start);
2402 	COMPARE_PARAM(vres.stag.size, stag_size);
2403 	COMPARE_PARAM(vres.rq.start, rq_start);
2404 	COMPARE_PARAM(vres.rq.size, rq_size);
2405 	COMPARE_PARAM(vres.pbl.start, pbl_start);
2406 	COMPARE_PARAM(vres.pbl.size, pbl_size);
2407 	COMPARE_PARAM(vres.qp.start, qp_start);
2408 	COMPARE_PARAM(vres.qp.size, qp_size);
2409 	COMPARE_PARAM(vres.cq.start, cq_start);
2410 	COMPARE_PARAM(vres.cq.size, cq_size);
2411 	COMPARE_PARAM(vres.ocq.start, ocq_start);
2412 	COMPARE_PARAM(vres.ocq.size, ocq_size);
2413 	COMPARE_PARAM(vres.srq.start, srq_start);
2414 	COMPARE_PARAM(vres.srq.size, srq_size);
2415 	COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp);
2416 	COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter);
2417 	COMPARE_PARAM(vres.iscsi.start, iscsi_start);
2418 	COMPARE_PARAM(vres.iscsi.size, iscsi_size);
2419 	COMPARE_PARAM(vres.key.start, key_start);
2420 	COMPARE_PARAM(vres.key.size, key_size);
2421 #undef COMPARE_PARAM
2422 
2423 	return (rc);
2424 }
2425 
2426 static int
2427 restart_lld(struct adapter *sc)
2428 {
2429 	struct adapter_pre_reset_state *old_state = NULL;
2430 	struct port_info *pi;
2431 	struct vi_info *vi;
2432 	if_t ifp;
2433 	struct sge_txq *txq;
2434 	int rc, i, j, k;
2435 
2436 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rlld");
2437 	if (rc != 0)
2438 		return (ENXIO);
2439 
2440 	/* Restore memory window. */
2441 	setup_memwin(sc);
2442 
2443 	/* Go no further if recovery mode has been requested. */
2444 	if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
2445 		CH_ALERT(sc, "%s: recovery mode during restart.\n", __func__);
2446 		rc = 0;
2447 		set_adapter_hwstatus(sc, true);
2448 		goto done;
2449 	}
2450 
2451 	old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK);
2452 	save_caps_and_params(sc, old_state);
2453 
2454 	/* Reestablish contact with firmware and become the primary PF. */
2455 	rc = contact_firmware(sc);
2456 	if (rc != 0)
2457 		goto done; /* error message displayed already */
2458 	MPASS(sc->flags & FW_OK);
2459 
2460 	if (sc->flags & MASTER_PF) {
2461 		rc = partition_resources(sc);
2462 		if (rc != 0)
2463 			goto done; /* error message displayed already */
2464 	}
2465 
2466 	rc = get_params__post_init(sc);
2467 	if (rc != 0)
2468 		goto done; /* error message displayed already */
2469 
2470 	rc = set_params__post_init(sc);
2471 	if (rc != 0)
2472 		goto done; /* error message displayed already */
2473 
2474 	rc = compare_caps_and_params(sc, old_state);
2475 	if (rc != 0)
2476 		goto done; /* error message displayed already */
2477 
2478 	for_each_port(sc, i) {
2479 		pi = sc->port[i];
2480 		MPASS(pi != NULL);
2481 		MPASS(pi->vi != NULL);
2482 		MPASS(pi->vi[0].dev == pi->dev);
2483 
2484 		rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
2485 		if (rc != 0) {
2486 			CH_ERR(sc,
2487 			    "failed to re-initialize port %d: %d\n", i, rc);
2488 			goto done;
2489 		}
2490 		MPASS(sc->chan_map[pi->tx_chan] == i);
2491 
2492 		PORT_LOCK(pi);
2493 		fixup_link_config(pi);
2494 		build_medialist(pi);
2495 		PORT_UNLOCK(pi);
2496 		for_each_vi(pi, j, vi) {
2497 			if (IS_MAIN_VI(vi))
2498 				continue;
2499 			rc = alloc_extra_vi(sc, pi, vi);
2500 			if (rc != 0) {
2501 				CH_ERR(vi,
2502 				    "failed to re-allocate extra VI: %d\n", rc);
2503 				goto done;
2504 			}
2505 		}
2506 	}
2507 
2508 	/*
2509 	 * Interrupts and queues are about to be enabled and other threads will
2510 	 * want to access the hardware too.  It is safe to do so.  Note that
2511 	 * this thread is still in the middle of a synchronized_op.
2512 	 */
2513 	set_adapter_hwstatus(sc, true);
2514 
2515 	if (sc->flags & FULL_INIT_DONE) {
2516 		rc = adapter_full_init(sc);
2517 		if (rc != 0) {
2518 			CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc);
2519 			goto done;
2520 		}
2521 
2522 		if (sc->vxlan_refcount > 0)
2523 			enable_vxlan_rx(sc);
2524 
2525 		for_each_port(sc, i) {
2526 			pi = sc->port[i];
2527 			for_each_vi(pi, j, vi) {
2528 				mtx_lock(&vi->tick_mtx);
2529 				vi->flags &= ~VI_SKIP_STATS;
2530 				mtx_unlock(&vi->tick_mtx);
2531 				if (!(vi->flags & VI_INIT_DONE))
2532 					continue;
2533 				rc = vi_full_init(vi);
2534 				if (rc != 0) {
2535 					CH_ERR(vi, "failed to re-initialize "
2536 					    "interface: %d\n", rc);
2537 					goto done;
2538 				}
2539 				if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
2540 					sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
2541 					t4_set_trace_rss_control(sc, pi->tx_chan, sc->traceq);
2542 					pi->flags |= HAS_TRACEQ;
2543 				}
2544 
2545 				ifp = vi->ifp;
2546 				if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
2547 					continue;
2548 				/*
2549 				 * Note that we do not setup multicast addresses
2550 				 * in the first pass.  This ensures that the
2551 				 * unicast DMACs for all VIs on all ports get an
2552 				 * MPS TCAM entry.
2553 				 */
2554 				rc = update_mac_settings(ifp, XGMAC_ALL &
2555 				    ~XGMAC_MCADDRS);
2556 				if (rc != 0) {
2557 					CH_ERR(vi, "failed to re-configure MAC: %d\n", rc);
2558 					goto done;
2559 				}
2560 				rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true,
2561 				    true);
2562 				if (rc != 0) {
2563 					CH_ERR(vi, "failed to re-enable VI: %d\n", rc);
2564 					goto done;
2565 				}
2566 				for_each_txq(vi, k, txq) {
2567 					TXQ_LOCK(txq);
2568 					txq->eq.flags |= EQ_ENABLED;
2569 					TXQ_UNLOCK(txq);
2570 				}
2571 				mtx_lock(&vi->tick_mtx);
2572 				callout_schedule(&vi->tick, hz);
2573 				mtx_unlock(&vi->tick_mtx);
2574 			}
2575 			PORT_LOCK(pi);
2576 			if (pi->up_vis > 0) {
2577 				t4_update_port_info(pi);
2578 				fixup_link_config(pi);
2579 				build_medialist(pi);
2580 				apply_link_config(pi);
2581 				if (pi->link_cfg.link_ok)
2582 					t4_os_link_changed(pi);
2583 			}
2584 			PORT_UNLOCK(pi);
2585 		}
2586 
2587 		/* Now reprogram the L2 multicast addresses. */
2588 		for_each_port(sc, i) {
2589 			pi = sc->port[i];
2590 			for_each_vi(pi, j, vi) {
2591 				if (!(vi->flags & VI_INIT_DONE))
2592 					continue;
2593 				ifp = vi->ifp;
2594 				if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
2595 					continue;
2596 				rc = update_mac_settings(ifp, XGMAC_MCADDRS);
2597 				if (rc != 0) {
2598 					CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc);
2599 					rc = 0;	/* carry on */
2600 				}
2601 			}
2602 		}
2603 	}
2604 
2605 	/* Reset all calibration */
2606 	t4_calibration_start(sc);
2607 done:
2608 	end_synchronized_op(sc, 0);
2609 	free(old_state, M_CXGBE);
2610 
2611 	restart_atid_allocator(sc);
2612 	t4_restart_l2t(sc);
2613 
2614 	return (rc);
2615 }
2616 
2617 int
2618 resume_adapter(struct adapter *sc)
2619 {
2620 	restart_adapter(sc);
2621 	restart_lld(sc);
2622 #ifdef TCP_OFFLOAD
2623 	restart_all_uld(sc);
2624 #endif
2625 	return (0);
2626 }
2627 
2628 static int
2629 t4_resume(device_t dev)
2630 {
2631 	struct adapter *sc = device_get_softc(dev);
2632 	int rc;
2633 
2634 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2635 	rc = resume_adapter(sc);
2636 	CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread);
2637 
2638 	return (rc);
2639 }
2640 
2641 static int
2642 t4_reset_prepare(device_t dev, device_t child)
2643 {
2644 	struct adapter *sc = device_get_softc(dev);
2645 
2646 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2647 	return (0);
2648 }
2649 
2650 static int
2651 t4_reset_post(device_t dev, device_t child)
2652 {
2653 	struct adapter *sc = device_get_softc(dev);
2654 
2655 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2656 	return (0);
2657 }
2658 
2659 static int
2660 reset_adapter_with_pl_rst(struct adapter *sc)
2661 {
2662 	/* This is a t4_write_reg without the hw_off_limits check. */
2663 	MPASS(sc->error_flags & HW_OFF_LIMITS);
2664 	bus_write_4(sc->regs_res, A_PL_RST,
2665 	    F_PIORSTMODE | F_PIORST | F_AUTOPCIEPAUSE);
2666 	pause("pl_rst", 1 * hz);		/* Wait 1s for reset */
2667 	return (0);
2668 }
2669 
2670 static int
2671 reset_adapter_with_pcie_sbr(struct adapter *sc)
2672 {
2673 	device_t pdev = device_get_parent(sc->dev);
2674 	device_t gpdev = device_get_parent(pdev);
2675 	device_t *children;
2676 	int rc, i, lcap, lsta, nchildren;
2677 	uint32_t v;
2678 
2679 	rc = pci_find_cap(gpdev, PCIY_EXPRESS, &v);
2680 	if (rc != 0) {
2681 		CH_ERR(sc, "%s: pci_find_cap(%s, pcie) failed: %d\n", __func__,
2682 		    device_get_nameunit(gpdev), rc);
2683 		return (ENOTSUP);
2684 	}
2685 	lcap = v + PCIER_LINK_CAP;
2686 	lsta = v + PCIER_LINK_STA;
2687 
2688 	nchildren = 0;
2689 	device_get_children(pdev, &children, &nchildren);
2690 	for (i = 0; i < nchildren; i++)
2691 		pci_save_state(children[i]);
2692 	v = pci_read_config(gpdev, PCIR_BRIDGECTL_1, 2);
2693 	pci_write_config(gpdev, PCIR_BRIDGECTL_1, v | PCIB_BCR_SECBUS_RESET, 2);
2694 	pause("pcie_sbr1", hz / 10);	/* 100ms */
2695 	pci_write_config(gpdev, PCIR_BRIDGECTL_1, v, 2);
2696 	pause("pcie_sbr2", hz);		/* Wait 1s before restore_state. */
2697 	v = pci_read_config(gpdev, lsta, 2);
2698 	if (pci_read_config(gpdev, lcap, 2) & PCIEM_LINK_CAP_DL_ACTIVE)
2699 		rc = v & PCIEM_LINK_STA_DL_ACTIVE ? 0 : ETIMEDOUT;
2700 	else if (v & (PCIEM_LINK_STA_TRAINING_ERROR | PCIEM_LINK_STA_TRAINING))
2701 		rc = ETIMEDOUT;
2702 	else
2703 		rc = 0;
2704 	if (rc != 0)
2705 		CH_ERR(sc, "%s: PCIe link is down after reset, LINK_STA 0x%x\n",
2706 		    __func__, v);
2707 	else {
2708 		for (i = 0; i < nchildren; i++)
2709 			pci_restore_state(children[i]);
2710 	}
2711 	free(children, M_TEMP);
2712 
2713 	return (rc);
2714 }
2715 
2716 static int
2717 reset_adapter_with_pcie_link_bounce(struct adapter *sc)
2718 {
2719 	device_t pdev = device_get_parent(sc->dev);
2720 	device_t gpdev = device_get_parent(pdev);
2721 	device_t *children;
2722 	int rc, i, lcap, lctl, lsta, nchildren;
2723 	uint32_t v;
2724 
2725 	rc = pci_find_cap(gpdev, PCIY_EXPRESS, &v);
2726 	if (rc != 0) {
2727 		CH_ERR(sc, "%s: pci_find_cap(%s, pcie) failed: %d\n", __func__,
2728 		    device_get_nameunit(gpdev), rc);
2729 		return (ENOTSUP);
2730 	}
2731 	lcap = v + PCIER_LINK_CAP;
2732 	lctl = v + PCIER_LINK_CTL;
2733 	lsta = v + PCIER_LINK_STA;
2734 
2735 	nchildren = 0;
2736 	device_get_children(pdev, &children, &nchildren);
2737 	for (i = 0; i < nchildren; i++)
2738 		pci_save_state(children[i]);
2739 	v = pci_read_config(gpdev, lctl, 2);
2740 	pci_write_config(gpdev, lctl, v | PCIEM_LINK_CTL_LINK_DIS, 2);
2741 	pause("pcie_lnk1", 100 * hz / 1000);	/* 100ms */
2742 	pci_write_config(gpdev, lctl, v | PCIEM_LINK_CTL_RETRAIN_LINK, 2);
2743 	pause("pcie_lnk2", hz);		/* Wait 1s before restore_state. */
2744 	v = pci_read_config(gpdev, lsta, 2);
2745 	if (pci_read_config(gpdev, lcap, 2) & PCIEM_LINK_CAP_DL_ACTIVE)
2746 		rc = v & PCIEM_LINK_STA_DL_ACTIVE ? 0 : ETIMEDOUT;
2747 	else if (v & (PCIEM_LINK_STA_TRAINING_ERROR | PCIEM_LINK_STA_TRAINING))
2748 		rc = ETIMEDOUT;
2749 	else
2750 		rc = 0;
2751 	if (rc != 0)
2752 		CH_ERR(sc, "%s: PCIe link is down after reset, LINK_STA 0x%x\n",
2753 		    __func__, v);
2754 	else {
2755 		for (i = 0; i < nchildren; i++)
2756 			pci_restore_state(children[i]);
2757 	}
2758 	free(children, M_TEMP);
2759 
2760 	return (rc);
2761 }
2762 
2763 static inline int
2764 reset_adapter(struct adapter *sc)
2765 {
2766 	int rc;
2767 	const int reset_method = vm_guest == VM_GUEST_NO ? t4_reset_method : 0;
2768 
2769 	rc = suspend_adapter(sc);
2770 	if (rc != 0)
2771 		return (rc);
2772 
2773 	switch (reset_method) {
2774 	case 1:
2775 		rc = reset_adapter_with_pcie_sbr(sc);
2776 		break;
2777 	case 2:
2778 		rc = reset_adapter_with_pcie_link_bounce(sc);
2779 		break;
2780 	case 0:
2781 	default:
2782 		rc = reset_adapter_with_pl_rst(sc);
2783 		break;
2784 	}
2785 	if (rc == 0)
2786 		rc = resume_adapter(sc);
2787 	return (rc);
2788 }
2789 
2790 static void
2791 reset_adapter_task(void *arg, int pending)
2792 {
2793 	struct adapter *sc = arg;
2794 	const int flags = sc->flags;
2795 	const int eflags = sc->error_flags;
2796 	int rc;
2797 
2798 	if (pending > 1)
2799 		CH_ALERT(sc, "%s: pending %d\n", __func__, pending);
2800 	rc = reset_adapter(sc);
2801 	if (rc != 0) {
2802 		CH_ERR(sc, "adapter did not reset properly, rc = %d, "
2803 		       "flags 0x%08x -> 0x%08x, err_flags 0x%08x -> 0x%08x.\n",
2804 		       rc, flags, sc->flags, eflags, sc->error_flags);
2805 	}
2806 }
2807 
2808 static int
2809 cxgbe_probe(device_t dev)
2810 {
2811 	struct port_info *pi = device_get_softc(dev);
2812 
2813 	device_set_descf(dev, "port %d", pi->port_id);
2814 
2815 	return (BUS_PROBE_DEFAULT);
2816 }
2817 
2818 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
2819     IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
2820     IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
2821     IFCAP_HWRXTSTMP | IFCAP_MEXTPG | IFCAP_NV)
2822 #define T4_CAP_ENABLE (T4_CAP)
2823 
2824 static void
2825 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
2826 {
2827 	if_t ifp;
2828 	struct sbuf *sb;
2829 	struct sysctl_ctx_list *ctx = &vi->ctx;
2830 	struct sysctl_oid_list *children;
2831 	struct pfil_head_args pa;
2832 	struct adapter *sc = vi->adapter;
2833 
2834 	sysctl_ctx_init(ctx);
2835 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev));
2836 	vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq",
2837 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues");
2838 	vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq",
2839 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues");
2840 #ifdef DEV_NETMAP
2841 	vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq",
2842 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues");
2843 	vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq",
2844 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues");
2845 #endif
2846 #ifdef TCP_OFFLOAD
2847 	vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq",
2848 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues");
2849 #endif
2850 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2851 	vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq",
2852 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues");
2853 #endif
2854 
2855 	vi->xact_addr_filt = -1;
2856 	mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF);
2857 	callout_init_mtx(&vi->tick, &vi->tick_mtx, 0);
2858 	if (sc->flags & IS_VF || t4_tx_vm_wr != 0)
2859 		vi->flags |= TX_USES_VM_WR;
2860 
2861 	/* Allocate an ifnet and set it up */
2862 	ifp = if_alloc_dev(IFT_ETHER, dev);
2863 	vi->ifp = ifp;
2864 	if_setsoftc(ifp, vi);
2865 
2866 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2867 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
2868 
2869 	if_setinitfn(ifp, cxgbe_init);
2870 	if_setioctlfn(ifp, cxgbe_ioctl);
2871 	if_settransmitfn(ifp, cxgbe_transmit);
2872 	if_setqflushfn(ifp, cxgbe_qflush);
2873 	if (vi->pi->nvi > 1 || sc->flags & IS_VF)
2874 		if_setgetcounterfn(ifp, vi_get_counter);
2875 	else
2876 		if_setgetcounterfn(ifp, cxgbe_get_counter);
2877 #if defined(KERN_TLS) || defined(RATELIMIT)
2878 	if_setsndtagallocfn(ifp, cxgbe_snd_tag_alloc);
2879 #endif
2880 #ifdef RATELIMIT
2881 	if_setratelimitqueryfn(ifp, cxgbe_ratelimit_query);
2882 #endif
2883 
2884 	if_setcapabilities(ifp, T4_CAP);
2885 	if_setcapenable(ifp, T4_CAP_ENABLE);
2886 	if_sethwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
2887 	    CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2888 	if (chip_id(sc) >= CHELSIO_T6) {
2889 		if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
2890 		if_setcapenablebit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
2891 		if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP |
2892 		    CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2893 		    CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN, 0);
2894 	}
2895 
2896 #ifdef TCP_OFFLOAD
2897 	if (vi->nofldrxq != 0)
2898 		if_setcapabilitiesbit(ifp, IFCAP_TOE, 0);
2899 #endif
2900 #ifdef RATELIMIT
2901 	if (is_ethoffload(sc) && vi->nofldtxq != 0) {
2902 		if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0);
2903 		if_setcapenablebit(ifp, IFCAP_TXRTLMT, 0);
2904 	}
2905 #endif
2906 
2907 	if_sethwtsomax(ifp, IP_MAXPACKET);
2908 	if (vi->flags & TX_USES_VM_WR)
2909 		if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_VM_TSO);
2910 	else
2911 		if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_TSO);
2912 #ifdef RATELIMIT
2913 	if (is_ethoffload(sc) && vi->nofldtxq != 0)
2914 		if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_EO_TSO);
2915 #endif
2916 	if_sethwtsomaxsegsize(ifp, 65536);
2917 #ifdef KERN_TLS
2918 	if (is_ktls(sc)) {
2919 		if_setcapabilitiesbit(ifp, IFCAP_TXTLS, 0);
2920 		if (sc->flags & KERN_TLS_ON || !is_t6(sc))
2921 			if_setcapenablebit(ifp, IFCAP_TXTLS, 0);
2922 	}
2923 #endif
2924 
2925 	ether_ifattach(ifp, vi->hw_addr);
2926 #ifdef DEV_NETMAP
2927 	if (vi->nnmrxq != 0)
2928 		cxgbe_nm_attach(vi);
2929 #endif
2930 	sb = sbuf_new_auto();
2931 	sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
2932 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2933 	switch (if_getcapabilities(ifp) & (IFCAP_TOE | IFCAP_TXRTLMT)) {
2934 	case IFCAP_TOE:
2935 		sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
2936 		break;
2937 	case IFCAP_TOE | IFCAP_TXRTLMT:
2938 		sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
2939 		break;
2940 	case IFCAP_TXRTLMT:
2941 		sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
2942 		break;
2943 	}
2944 #endif
2945 #ifdef TCP_OFFLOAD
2946 	if (if_getcapabilities(ifp) & IFCAP_TOE)
2947 		sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
2948 #endif
2949 #ifdef DEV_NETMAP
2950 	if (if_getcapabilities(ifp) & IFCAP_NETMAP)
2951 		sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
2952 		    vi->nnmtxq, vi->nnmrxq);
2953 #endif
2954 	sbuf_finish(sb);
2955 	device_printf(dev, "%s\n", sbuf_data(sb));
2956 	sbuf_delete(sb);
2957 
2958 	vi_sysctls(vi);
2959 
2960 	pa.pa_version = PFIL_VERSION;
2961 	pa.pa_flags = PFIL_IN;
2962 	pa.pa_type = PFIL_TYPE_ETHERNET;
2963 	pa.pa_headname = if_name(ifp);
2964 	vi->pfil = pfil_head_register(&pa);
2965 }
2966 
2967 static int
2968 cxgbe_attach(device_t dev)
2969 {
2970 	struct port_info *pi = device_get_softc(dev);
2971 	struct adapter *sc = pi->adapter;
2972 	struct vi_info *vi;
2973 	int i;
2974 
2975 	sysctl_ctx_init(&pi->ctx);
2976 
2977 	cxgbe_vi_attach(dev, &pi->vi[0]);
2978 
2979 	for_each_vi(pi, i, vi) {
2980 		if (i == 0)
2981 			continue;
2982 		vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, DEVICE_UNIT_ANY);
2983 		if (vi->dev == NULL) {
2984 			device_printf(dev, "failed to add VI %d\n", i);
2985 			continue;
2986 		}
2987 		device_set_softc(vi->dev, vi);
2988 	}
2989 
2990 	cxgbe_sysctls(pi);
2991 
2992 	bus_attach_children(dev);
2993 
2994 	return (0);
2995 }
2996 
2997 static void
2998 cxgbe_vi_detach(struct vi_info *vi)
2999 {
3000 	if_t ifp = vi->ifp;
3001 
3002 	if (vi->pfil != NULL) {
3003 		pfil_head_unregister(vi->pfil);
3004 		vi->pfil = NULL;
3005 	}
3006 
3007 	ether_ifdetach(ifp);
3008 
3009 	/* Let detach proceed even if these fail. */
3010 #ifdef DEV_NETMAP
3011 	if (if_getcapabilities(ifp) & IFCAP_NETMAP)
3012 		cxgbe_nm_detach(vi);
3013 #endif
3014 	cxgbe_uninit_synchronized(vi);
3015 	callout_drain(&vi->tick);
3016 	mtx_destroy(&vi->tick_mtx);
3017 	sysctl_ctx_free(&vi->ctx);
3018 	vi_full_uninit(vi);
3019 
3020 	if_free(vi->ifp);
3021 	vi->ifp = NULL;
3022 }
3023 
3024 static int
3025 cxgbe_detach(device_t dev)
3026 {
3027 	struct port_info *pi = device_get_softc(dev);
3028 	struct adapter *sc = pi->adapter;
3029 	int rc;
3030 
3031 	/* Detach the extra VIs first. */
3032 	rc = bus_generic_detach(dev);
3033 	if (rc)
3034 		return (rc);
3035 
3036 	sysctl_ctx_free(&pi->ctx);
3037 	begin_vi_detach(sc, &pi->vi[0]);
3038 	if (pi->flags & HAS_TRACEQ) {
3039 		sc->traceq = -1;	/* cloner should not create ifnet */
3040 		t4_tracer_port_detach(sc);
3041 	}
3042 	cxgbe_vi_detach(&pi->vi[0]);
3043 	ifmedia_removeall(&pi->media);
3044 	end_vi_detach(sc, &pi->vi[0]);
3045 
3046 	return (0);
3047 }
3048 
3049 static void
3050 cxgbe_init(void *arg)
3051 {
3052 	struct vi_info *vi = arg;
3053 	struct adapter *sc = vi->adapter;
3054 
3055 	if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
3056 		return;
3057 	cxgbe_init_synchronized(vi);
3058 	end_synchronized_op(sc, 0);
3059 }
3060 
3061 static int
3062 cxgbe_ioctl(if_t ifp, unsigned long cmd, caddr_t data)
3063 {
3064 	int rc = 0, mtu, flags;
3065 	struct vi_info *vi = if_getsoftc(ifp);
3066 	struct port_info *pi = vi->pi;
3067 	struct adapter *sc = pi->adapter;
3068 	struct ifreq *ifr = (struct ifreq *)data;
3069 	uint32_t mask, mask2;
3070 
3071 	switch (cmd) {
3072 	case SIOCSIFMTU:
3073 		mtu = ifr->ifr_mtu;
3074 		if (mtu < ETHERMIN || mtu > MAX_MTU)
3075 			return (EINVAL);
3076 
3077 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
3078 		if (rc)
3079 			return (rc);
3080 		if_setmtu(ifp, mtu);
3081 		if (vi->flags & VI_INIT_DONE) {
3082 			t4_update_fl_bufsize(ifp);
3083 			if (hw_all_ok(sc) &&
3084 			    if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3085 				rc = update_mac_settings(ifp, XGMAC_MTU);
3086 		}
3087 		end_synchronized_op(sc, 0);
3088 		break;
3089 
3090 	case SIOCSIFFLAGS:
3091 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
3092 		if (rc)
3093 			return (rc);
3094 
3095 		if (!hw_all_ok(sc)) {
3096 			rc = ENXIO;
3097 			goto fail;
3098 		}
3099 
3100 		if (if_getflags(ifp) & IFF_UP) {
3101 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3102 				flags = vi->if_flags;
3103 				if ((if_getflags(ifp) ^ flags) &
3104 				    (IFF_PROMISC | IFF_ALLMULTI)) {
3105 					rc = update_mac_settings(ifp,
3106 					    XGMAC_PROMISC | XGMAC_ALLMULTI);
3107 				}
3108 			} else {
3109 				rc = cxgbe_init_synchronized(vi);
3110 			}
3111 			vi->if_flags = if_getflags(ifp);
3112 		} else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3113 			rc = cxgbe_uninit_synchronized(vi);
3114 		}
3115 		end_synchronized_op(sc, 0);
3116 		break;
3117 
3118 	case SIOCADDMULTI:
3119 	case SIOCDELMULTI:
3120 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
3121 		if (rc)
3122 			return (rc);
3123 		if (hw_all_ok(sc) && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3124 			rc = update_mac_settings(ifp, XGMAC_MCADDRS);
3125 		end_synchronized_op(sc, 0);
3126 		break;
3127 
3128 	case SIOCGIFCAPNV:
3129 		break;
3130 	case SIOCSIFCAPNV:
3131 	case SIOCSIFCAP:
3132 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
3133 		if (rc)
3134 			return (rc);
3135 
3136 		if (cmd == SIOCSIFCAPNV) {
3137 			const struct siocsifcapnv_driver_data *ifr_nv =
3138 			    (struct siocsifcapnv_driver_data *)data;
3139 
3140 			mask = ifr_nv->reqcap ^ if_getcapenable(ifp);
3141 			mask2 = ifr_nv->reqcap2 ^ if_getcapenable2(ifp);
3142 		} else {
3143 			mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3144 			mask2 = 0;
3145 		}
3146 		if (mask & IFCAP_TXCSUM) {
3147 			if_togglecapenable(ifp, IFCAP_TXCSUM);
3148 			if_togglehwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP);
3149 
3150 			if (IFCAP_TSO4 & if_getcapenable(ifp) &&
3151 			    !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3152 				mask &= ~IFCAP_TSO4;
3153 				if_setcapenablebit(ifp, 0, IFCAP_TSO4);
3154 				if_printf(ifp,
3155 				    "tso4 disabled due to -txcsum.\n");
3156 			}
3157 		}
3158 		if (mask & IFCAP_TXCSUM_IPV6) {
3159 			if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
3160 			if_togglehwassist(ifp, CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3161 
3162 			if (IFCAP_TSO6 & if_getcapenable(ifp) &&
3163 			    !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3164 				mask &= ~IFCAP_TSO6;
3165 				if_setcapenablebit(ifp, 0, IFCAP_TSO6);
3166 				if_printf(ifp,
3167 				    "tso6 disabled due to -txcsum6.\n");
3168 			}
3169 		}
3170 		if (mask & IFCAP_RXCSUM)
3171 			if_togglecapenable(ifp, IFCAP_RXCSUM);
3172 		if (mask & IFCAP_RXCSUM_IPV6)
3173 			if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
3174 
3175 		/*
3176 		 * Note that we leave CSUM_TSO alone (it is always set).  The
3177 		 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
3178 		 * sending a TSO request our way, so it's sufficient to toggle
3179 		 * IFCAP_TSOx only.
3180 		 */
3181 		if (mask & IFCAP_TSO4) {
3182 			if (!(IFCAP_TSO4 & if_getcapenable(ifp)) &&
3183 			    !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3184 				if_printf(ifp, "enable txcsum first.\n");
3185 				rc = EAGAIN;
3186 				goto fail;
3187 			}
3188 			if_togglecapenable(ifp, IFCAP_TSO4);
3189 		}
3190 		if (mask & IFCAP_TSO6) {
3191 			if (!(IFCAP_TSO6 & if_getcapenable(ifp)) &&
3192 			    !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3193 				if_printf(ifp, "enable txcsum6 first.\n");
3194 				rc = EAGAIN;
3195 				goto fail;
3196 			}
3197 			if_togglecapenable(ifp, IFCAP_TSO6);
3198 		}
3199 		if (mask & IFCAP_LRO) {
3200 #if defined(INET) || defined(INET6)
3201 			int i;
3202 			struct sge_rxq *rxq;
3203 
3204 			if_togglecapenable(ifp, IFCAP_LRO);
3205 			for_each_rxq(vi, i, rxq) {
3206 				if (if_getcapenable(ifp) & IFCAP_LRO)
3207 					rxq->iq.flags |= IQ_LRO_ENABLED;
3208 				else
3209 					rxq->iq.flags &= ~IQ_LRO_ENABLED;
3210 			}
3211 #endif
3212 		}
3213 #ifdef TCP_OFFLOAD
3214 		if (mask & IFCAP_TOE) {
3215 			int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TOE;
3216 
3217 			rc = toe_capability(vi, enable);
3218 			if (rc != 0)
3219 				goto fail;
3220 
3221 			if_togglecapenable(ifp, mask);
3222 		}
3223 #endif
3224 		if (mask & IFCAP_VLAN_HWTAGGING) {
3225 			if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
3226 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3227 				rc = update_mac_settings(ifp, XGMAC_VLANEX);
3228 		}
3229 		if (mask & IFCAP_VLAN_MTU) {
3230 			if_togglecapenable(ifp, IFCAP_VLAN_MTU);
3231 
3232 			/* Need to find out how to disable auto-mtu-inflation */
3233 		}
3234 		if (mask & IFCAP_VLAN_HWTSO)
3235 			if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
3236 		if (mask & IFCAP_VLAN_HWCSUM)
3237 			if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
3238 #ifdef RATELIMIT
3239 		if (mask & IFCAP_TXRTLMT)
3240 			if_togglecapenable(ifp, IFCAP_TXRTLMT);
3241 #endif
3242 		if (mask & IFCAP_HWRXTSTMP) {
3243 			int i;
3244 			struct sge_rxq *rxq;
3245 
3246 			if_togglecapenable(ifp, IFCAP_HWRXTSTMP);
3247 			for_each_rxq(vi, i, rxq) {
3248 				if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP)
3249 					rxq->iq.flags |= IQ_RX_TIMESTAMP;
3250 				else
3251 					rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
3252 			}
3253 		}
3254 		if (mask & IFCAP_MEXTPG)
3255 			if_togglecapenable(ifp, IFCAP_MEXTPG);
3256 
3257 #ifdef KERN_TLS
3258 		if (mask & IFCAP_TXTLS) {
3259 			int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TXTLS;
3260 
3261 			rc = ktls_capability(sc, enable);
3262 			if (rc != 0)
3263 				goto fail;
3264 
3265 			if_togglecapenable(ifp, mask & IFCAP_TXTLS);
3266 		}
3267 #endif
3268 		if (mask & IFCAP_VXLAN_HWCSUM) {
3269 			if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM);
3270 			if_togglehwassist(ifp, CSUM_INNER_IP6_UDP |
3271 			    CSUM_INNER_IP6_TCP | CSUM_INNER_IP |
3272 			    CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP);
3273 		}
3274 		if (mask & IFCAP_VXLAN_HWTSO) {
3275 			if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO);
3276 			if_togglehwassist(ifp, CSUM_INNER_IP6_TSO |
3277 			    CSUM_INNER_IP_TSO);
3278 		}
3279 
3280 		MPASS(mask2 == 0);
3281 		(void)mask2;
3282 
3283 #ifdef VLAN_CAPABILITIES
3284 		VLAN_CAPABILITIES(ifp);
3285 #endif
3286 fail:
3287 		end_synchronized_op(sc, 0);
3288 		break;
3289 
3290 	case SIOCSIFMEDIA:
3291 	case SIOCGIFMEDIA:
3292 	case SIOCGIFXMEDIA:
3293 		rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
3294 		break;
3295 
3296 	case SIOCGI2C: {
3297 		struct ifi2creq i2c;
3298 
3299 		rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3300 		if (rc != 0)
3301 			break;
3302 		if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3303 			rc = EPERM;
3304 			break;
3305 		}
3306 		if (i2c.len > sizeof(i2c.data)) {
3307 			rc = EINVAL;
3308 			break;
3309 		}
3310 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
3311 		if (rc)
3312 			return (rc);
3313 		if (!hw_all_ok(sc))
3314 			rc = ENXIO;
3315 		else
3316 			rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
3317 			    i2c.offset, i2c.len, &i2c.data[0]);
3318 		end_synchronized_op(sc, 0);
3319 		if (rc == 0)
3320 			rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3321 		break;
3322 	}
3323 
3324 	default:
3325 		rc = ether_ioctl(ifp, cmd, data);
3326 	}
3327 
3328 	return (rc);
3329 }
3330 
3331 static int
3332 cxgbe_transmit(if_t ifp, struct mbuf *m)
3333 {
3334 	struct vi_info *vi = if_getsoftc(ifp);
3335 	struct port_info *pi = vi->pi;
3336 	struct adapter *sc;
3337 	struct sge_txq *txq;
3338 	void *items[1];
3339 	int rc;
3340 
3341 	M_ASSERTPKTHDR(m);
3342 	MPASS(m->m_nextpkt == NULL);	/* not quite ready for this yet */
3343 #if defined(KERN_TLS) || defined(RATELIMIT)
3344 	if (m->m_pkthdr.csum_flags & CSUM_SND_TAG)
3345 		MPASS(m->m_pkthdr.snd_tag->ifp == ifp);
3346 #endif
3347 
3348 	if (__predict_false(pi->link_cfg.link_ok == false)) {
3349 		m_freem(m);
3350 		return (ENETDOWN);
3351 	}
3352 
3353 	rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR);
3354 	if (__predict_false(rc != 0)) {
3355 		if (__predict_true(rc == EINPROGRESS)) {
3356 			/* queued by parse_pkt */
3357 			MPASS(m != NULL);
3358 			return (0);
3359 		}
3360 
3361 		MPASS(m == NULL);			/* was freed already */
3362 		atomic_add_int(&pi->tx_parse_error, 1);	/* rare, atomic is ok */
3363 		return (rc);
3364 	}
3365 
3366 	/* Select a txq. */
3367 	sc = vi->adapter;
3368 	txq = &sc->sge.txq[vi->first_txq];
3369 	if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
3370 		txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
3371 		    vi->rsrv_noflowq);
3372 
3373 	items[0] = m;
3374 	rc = mp_ring_enqueue(txq->r, items, 1, 256);
3375 	if (__predict_false(rc != 0))
3376 		m_freem(m);
3377 
3378 	return (rc);
3379 }
3380 
3381 static void
3382 cxgbe_qflush(if_t ifp)
3383 {
3384 	struct vi_info *vi = if_getsoftc(ifp);
3385 	struct sge_txq *txq;
3386 	int i;
3387 
3388 	/* queues do not exist if !VI_INIT_DONE. */
3389 	if (vi->flags & VI_INIT_DONE) {
3390 		for_each_txq(vi, i, txq) {
3391 			TXQ_LOCK(txq);
3392 			txq->eq.flags |= EQ_QFLUSH;
3393 			TXQ_UNLOCK(txq);
3394 			while (!mp_ring_is_idle(txq->r)) {
3395 				mp_ring_check_drainage(txq->r, 4096);
3396 				pause("qflush", 1);
3397 			}
3398 			TXQ_LOCK(txq);
3399 			txq->eq.flags &= ~EQ_QFLUSH;
3400 			TXQ_UNLOCK(txq);
3401 		}
3402 	}
3403 	if_qflush(ifp);
3404 }
3405 
3406 static uint64_t
3407 vi_get_counter(if_t ifp, ift_counter c)
3408 {
3409 	struct vi_info *vi = if_getsoftc(ifp);
3410 	struct fw_vi_stats_vf *s = &vi->stats;
3411 
3412 	mtx_lock(&vi->tick_mtx);
3413 	vi_refresh_stats(vi);
3414 	mtx_unlock(&vi->tick_mtx);
3415 
3416 	switch (c) {
3417 	case IFCOUNTER_IPACKETS:
3418 		return (s->rx_bcast_frames + s->rx_mcast_frames +
3419 		    s->rx_ucast_frames);
3420 	case IFCOUNTER_IERRORS:
3421 		return (s->rx_err_frames);
3422 	case IFCOUNTER_OPACKETS:
3423 		return (s->tx_bcast_frames + s->tx_mcast_frames +
3424 		    s->tx_ucast_frames + s->tx_offload_frames);
3425 	case IFCOUNTER_OERRORS:
3426 		return (s->tx_drop_frames);
3427 	case IFCOUNTER_IBYTES:
3428 		return (s->rx_bcast_bytes + s->rx_mcast_bytes +
3429 		    s->rx_ucast_bytes);
3430 	case IFCOUNTER_OBYTES:
3431 		return (s->tx_bcast_bytes + s->tx_mcast_bytes +
3432 		    s->tx_ucast_bytes + s->tx_offload_bytes);
3433 	case IFCOUNTER_IMCASTS:
3434 		return (s->rx_mcast_frames);
3435 	case IFCOUNTER_OMCASTS:
3436 		return (s->tx_mcast_frames);
3437 	case IFCOUNTER_OQDROPS: {
3438 		uint64_t drops;
3439 
3440 		drops = 0;
3441 		if (vi->flags & VI_INIT_DONE) {
3442 			int i;
3443 			struct sge_txq *txq;
3444 
3445 			for_each_txq(vi, i, txq)
3446 				drops += counter_u64_fetch(txq->r->dropped);
3447 		}
3448 
3449 		return (drops);
3450 
3451 	}
3452 
3453 	default:
3454 		return (if_get_counter_default(ifp, c));
3455 	}
3456 }
3457 
3458 static uint64_t
3459 cxgbe_get_counter(if_t ifp, ift_counter c)
3460 {
3461 	struct vi_info *vi = if_getsoftc(ifp);
3462 	struct port_info *pi = vi->pi;
3463 	struct port_stats *s = &pi->stats;
3464 
3465 	mtx_lock(&vi->tick_mtx);
3466 	cxgbe_refresh_stats(vi);
3467 	mtx_unlock(&vi->tick_mtx);
3468 
3469 	switch (c) {
3470 	case IFCOUNTER_IPACKETS:
3471 		return (s->rx_frames);
3472 
3473 	case IFCOUNTER_IERRORS:
3474 		return (s->rx_jabber + s->rx_runt + s->rx_too_long +
3475 		    s->rx_fcs_err + s->rx_len_err);
3476 
3477 	case IFCOUNTER_OPACKETS:
3478 		return (s->tx_frames);
3479 
3480 	case IFCOUNTER_OERRORS:
3481 		return (s->tx_error_frames);
3482 
3483 	case IFCOUNTER_IBYTES:
3484 		return (s->rx_octets);
3485 
3486 	case IFCOUNTER_OBYTES:
3487 		return (s->tx_octets);
3488 
3489 	case IFCOUNTER_IMCASTS:
3490 		return (s->rx_mcast_frames);
3491 
3492 	case IFCOUNTER_OMCASTS:
3493 		return (s->tx_mcast_frames);
3494 
3495 	case IFCOUNTER_IQDROPS:
3496 		return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
3497 		    s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
3498 		    s->rx_trunc3 + pi->tnl_cong_drops);
3499 
3500 	case IFCOUNTER_OQDROPS: {
3501 		uint64_t drops;
3502 
3503 		drops = s->tx_drop;
3504 		if (vi->flags & VI_INIT_DONE) {
3505 			int i;
3506 			struct sge_txq *txq;
3507 
3508 			for_each_txq(vi, i, txq)
3509 				drops += counter_u64_fetch(txq->r->dropped);
3510 		}
3511 
3512 		return (drops);
3513 
3514 	}
3515 
3516 	default:
3517 		return (if_get_counter_default(ifp, c));
3518 	}
3519 }
3520 
3521 #if defined(KERN_TLS) || defined(RATELIMIT)
3522 static int
3523 cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params,
3524     struct m_snd_tag **pt)
3525 {
3526 	int error;
3527 
3528 	switch (params->hdr.type) {
3529 #ifdef RATELIMIT
3530 	case IF_SND_TAG_TYPE_RATE_LIMIT:
3531 		error = cxgbe_rate_tag_alloc(ifp, params, pt);
3532 		break;
3533 #endif
3534 #ifdef KERN_TLS
3535 	case IF_SND_TAG_TYPE_TLS:
3536 	{
3537 		struct vi_info *vi = if_getsoftc(ifp);
3538 
3539 		if (is_t6(vi->pi->adapter))
3540 			error = t6_tls_tag_alloc(ifp, params, pt);
3541 		else
3542 			error = t7_tls_tag_alloc(ifp, params, pt);
3543 		break;
3544 	}
3545 #endif
3546 	default:
3547 		error = EOPNOTSUPP;
3548 	}
3549 	return (error);
3550 }
3551 #endif
3552 
3553 /*
3554  * The kernel picks a media from the list we had provided but we still validate
3555  * the requeste.
3556  */
3557 int
3558 cxgbe_media_change(if_t ifp)
3559 {
3560 	struct vi_info *vi = if_getsoftc(ifp);
3561 	struct port_info *pi = vi->pi;
3562 	struct ifmedia *ifm = &pi->media;
3563 	struct link_config *lc = &pi->link_cfg;
3564 	struct adapter *sc = pi->adapter;
3565 	int rc;
3566 
3567 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
3568 	if (rc != 0)
3569 		return (rc);
3570 	PORT_LOCK(pi);
3571 	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
3572 		/* ifconfig .. media autoselect */
3573 		if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
3574 			rc = ENOTSUP; /* AN not supported by transceiver */
3575 			goto done;
3576 		}
3577 		lc->requested_aneg = AUTONEG_ENABLE;
3578 		lc->requested_speed = 0;
3579 		lc->requested_fc |= PAUSE_AUTONEG;
3580 	} else {
3581 		lc->requested_aneg = AUTONEG_DISABLE;
3582 		lc->requested_speed =
3583 		    ifmedia_baudrate(ifm->ifm_media) / 1000000;
3584 		lc->requested_fc = 0;
3585 		if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
3586 			lc->requested_fc |= PAUSE_RX;
3587 		if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
3588 			lc->requested_fc |= PAUSE_TX;
3589 	}
3590 	if (pi->up_vis > 0 && hw_all_ok(sc)) {
3591 		fixup_link_config(pi);
3592 		rc = apply_link_config(pi);
3593 	}
3594 done:
3595 	PORT_UNLOCK(pi);
3596 	end_synchronized_op(sc, 0);
3597 	return (rc);
3598 }
3599 
3600 /*
3601  * Base media word (without ETHER, pause, link active, etc.) for the port at the
3602  * given speed.
3603  */
3604 static int
3605 port_mword(struct port_info *pi, uint32_t speed)
3606 {
3607 
3608 	MPASS(speed & M_FW_PORT_CAP32_SPEED);
3609 	MPASS(powerof2(speed));
3610 
3611 	switch(pi->port_type) {
3612 	case FW_PORT_TYPE_BT_SGMII:
3613 	case FW_PORT_TYPE_BT_XFI:
3614 	case FW_PORT_TYPE_BT_XAUI:
3615 		/* BaseT */
3616 		switch (speed) {
3617 		case FW_PORT_CAP32_SPEED_100M:
3618 			return (IFM_100_T);
3619 		case FW_PORT_CAP32_SPEED_1G:
3620 			return (IFM_1000_T);
3621 		case FW_PORT_CAP32_SPEED_10G:
3622 			return (IFM_10G_T);
3623 		}
3624 		break;
3625 	case FW_PORT_TYPE_KX4:
3626 		if (speed == FW_PORT_CAP32_SPEED_10G)
3627 			return (IFM_10G_KX4);
3628 		break;
3629 	case FW_PORT_TYPE_CX4:
3630 		if (speed == FW_PORT_CAP32_SPEED_10G)
3631 			return (IFM_10G_CX4);
3632 		break;
3633 	case FW_PORT_TYPE_KX:
3634 		if (speed == FW_PORT_CAP32_SPEED_1G)
3635 			return (IFM_1000_KX);
3636 		break;
3637 	case FW_PORT_TYPE_KR:
3638 	case FW_PORT_TYPE_BP_AP:
3639 	case FW_PORT_TYPE_BP4_AP:
3640 	case FW_PORT_TYPE_BP40_BA:
3641 	case FW_PORT_TYPE_KR4_100G:
3642 	case FW_PORT_TYPE_KR_SFP28:
3643 	case FW_PORT_TYPE_KR_XLAUI:
3644 		switch (speed) {
3645 		case FW_PORT_CAP32_SPEED_1G:
3646 			return (IFM_1000_KX);
3647 		case FW_PORT_CAP32_SPEED_10G:
3648 			return (IFM_10G_KR);
3649 		case FW_PORT_CAP32_SPEED_25G:
3650 			return (IFM_25G_KR);
3651 		case FW_PORT_CAP32_SPEED_40G:
3652 			return (IFM_40G_KR4);
3653 		case FW_PORT_CAP32_SPEED_50G:
3654 			return (IFM_50G_KR2);
3655 		case FW_PORT_CAP32_SPEED_100G:
3656 			return (IFM_100G_KR4);
3657 		}
3658 		break;
3659 	case FW_PORT_TYPE_FIBER_XFI:
3660 	case FW_PORT_TYPE_FIBER_XAUI:
3661 	case FW_PORT_TYPE_SFP:
3662 	case FW_PORT_TYPE_QSFP_10G:
3663 	case FW_PORT_TYPE_QSA:
3664 	case FW_PORT_TYPE_QSFP:
3665 	case FW_PORT_TYPE_CR4_QSFP:
3666 	case FW_PORT_TYPE_CR_QSFP:
3667 	case FW_PORT_TYPE_CR2_QSFP:
3668 	case FW_PORT_TYPE_SFP28:
3669 	case FW_PORT_TYPE_SFP56:
3670 	case FW_PORT_TYPE_QSFP56:
3671 	case FW_PORT_TYPE_QSFPDD:
3672 		/* Pluggable transceiver */
3673 		switch (pi->mod_type) {
3674 		case FW_PORT_MOD_TYPE_LR:
3675 		case FW_PORT_MOD_TYPE_LR_SIMPLEX:
3676 			switch (speed) {
3677 			case FW_PORT_CAP32_SPEED_1G:
3678 				return (IFM_1000_LX);
3679 			case FW_PORT_CAP32_SPEED_10G:
3680 				return (IFM_10G_LR);
3681 			case FW_PORT_CAP32_SPEED_25G:
3682 				return (IFM_25G_LR);
3683 			case FW_PORT_CAP32_SPEED_40G:
3684 				return (IFM_40G_LR4);
3685 			case FW_PORT_CAP32_SPEED_50G:
3686 				return (IFM_50G_LR2);
3687 			case FW_PORT_CAP32_SPEED_100G:
3688 				return (IFM_100G_LR4);
3689 			case FW_PORT_CAP32_SPEED_200G:
3690 				return (IFM_200G_LR4);
3691 			case FW_PORT_CAP32_SPEED_400G:
3692 				return (IFM_400G_LR8);
3693 			}
3694 			break;
3695 		case FW_PORT_MOD_TYPE_SR:
3696 			switch (speed) {
3697 			case FW_PORT_CAP32_SPEED_1G:
3698 				return (IFM_1000_SX);
3699 			case FW_PORT_CAP32_SPEED_10G:
3700 				return (IFM_10G_SR);
3701 			case FW_PORT_CAP32_SPEED_25G:
3702 				return (IFM_25G_SR);
3703 			case FW_PORT_CAP32_SPEED_40G:
3704 				return (IFM_40G_SR4);
3705 			case FW_PORT_CAP32_SPEED_50G:
3706 				return (IFM_50G_SR2);
3707 			case FW_PORT_CAP32_SPEED_100G:
3708 				return (IFM_100G_SR4);
3709 			case FW_PORT_CAP32_SPEED_200G:
3710 				return (IFM_200G_SR4);
3711 			case FW_PORT_CAP32_SPEED_400G:
3712 				return (IFM_400G_SR8);
3713 			}
3714 			break;
3715 		case FW_PORT_MOD_TYPE_ER:
3716 			if (speed == FW_PORT_CAP32_SPEED_10G)
3717 				return (IFM_10G_ER);
3718 			break;
3719 		case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3720 		case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3721 			switch (speed) {
3722 			case FW_PORT_CAP32_SPEED_1G:
3723 				return (IFM_1000_CX);
3724 			case FW_PORT_CAP32_SPEED_10G:
3725 				return (IFM_10G_TWINAX);
3726 			case FW_PORT_CAP32_SPEED_25G:
3727 				return (IFM_25G_CR);
3728 			case FW_PORT_CAP32_SPEED_40G:
3729 				return (IFM_40G_CR4);
3730 			case FW_PORT_CAP32_SPEED_50G:
3731 				return (IFM_50G_CR2);
3732 			case FW_PORT_CAP32_SPEED_100G:
3733 				return (IFM_100G_CR4);
3734 			case FW_PORT_CAP32_SPEED_200G:
3735 				return (IFM_200G_CR4_PAM4);
3736 			case FW_PORT_CAP32_SPEED_400G:
3737 				return (IFM_400G_CR8);
3738 			}
3739 			break;
3740 		case FW_PORT_MOD_TYPE_LRM:
3741 			if (speed == FW_PORT_CAP32_SPEED_10G)
3742 				return (IFM_10G_LRM);
3743 			break;
3744 		case FW_PORT_MOD_TYPE_DR:
3745 			if (speed == FW_PORT_CAP32_SPEED_100G)
3746 				return (IFM_100G_DR);
3747 			if (speed == FW_PORT_CAP32_SPEED_200G)
3748 				return (IFM_200G_DR4);
3749 			if (speed == FW_PORT_CAP32_SPEED_400G)
3750 				return (IFM_400G_DR4);
3751 			break;
3752 		case FW_PORT_MOD_TYPE_NA:
3753 			MPASS(0);	/* Not pluggable? */
3754 			/* fall through */
3755 		case FW_PORT_MOD_TYPE_ERROR:
3756 		case FW_PORT_MOD_TYPE_UNKNOWN:
3757 		case FW_PORT_MOD_TYPE_NOTSUPPORTED:
3758 			break;
3759 		case FW_PORT_MOD_TYPE_NONE:
3760 			return (IFM_NONE);
3761 		}
3762 		break;
3763 	case M_FW_PORT_CMD_PTYPE:	/* FW_PORT_TYPE_NONE for old firmware */
3764 		if (chip_id(pi->adapter) >= CHELSIO_T7)
3765 			return (IFM_UNKNOWN);
3766 		/* fall through */
3767 	case FW_PORT_TYPE_NONE:
3768 		return (IFM_NONE);
3769 	}
3770 
3771 	return (IFM_UNKNOWN);
3772 }
3773 
3774 void
3775 cxgbe_media_status(if_t ifp, struct ifmediareq *ifmr)
3776 {
3777 	struct vi_info *vi = if_getsoftc(ifp);
3778 	struct port_info *pi = vi->pi;
3779 	struct adapter *sc = pi->adapter;
3780 	struct link_config *lc = &pi->link_cfg;
3781 
3782 	if (begin_synchronized_op(sc, vi , SLEEP_OK | INTR_OK, "t4med") != 0)
3783 		return;
3784 	PORT_LOCK(pi);
3785 
3786 	if (pi->up_vis == 0 && hw_all_ok(sc)) {
3787 		/*
3788 		 * If all the interfaces are administratively down the firmware
3789 		 * does not report transceiver changes.  Refresh port info here
3790 		 * so that ifconfig displays accurate ifmedia at all times.
3791 		 * This is the only reason we have a synchronized op in this
3792 		 * function.  Just PORT_LOCK would have been enough otherwise.
3793 		 */
3794 		t4_update_port_info(pi);
3795 		build_medialist(pi);
3796 	}
3797 
3798 	/* ifm_status */
3799 	ifmr->ifm_status = IFM_AVALID;
3800 	if (lc->link_ok == false)
3801 		goto done;
3802 	ifmr->ifm_status |= IFM_ACTIVE;
3803 
3804 	/* ifm_active */
3805 	ifmr->ifm_active = IFM_ETHER | IFM_FDX;
3806 	ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
3807 	if (lc->fc & PAUSE_RX)
3808 		ifmr->ifm_active |= IFM_ETH_RXPAUSE;
3809 	if (lc->fc & PAUSE_TX)
3810 		ifmr->ifm_active |= IFM_ETH_TXPAUSE;
3811 	ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
3812 done:
3813 	PORT_UNLOCK(pi);
3814 	end_synchronized_op(sc, 0);
3815 }
3816 
3817 static int
3818 vcxgbe_probe(device_t dev)
3819 {
3820 	struct vi_info *vi = device_get_softc(dev);
3821 
3822 	device_set_descf(dev, "port %d vi %td", vi->pi->port_id,
3823 	    vi - vi->pi->vi);
3824 
3825 	return (BUS_PROBE_DEFAULT);
3826 }
3827 
3828 static int
3829 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
3830 {
3831 	int func, index, rc;
3832 	uint32_t param, val;
3833 
3834 	ASSERT_SYNCHRONIZED_OP(sc);
3835 
3836 	index = vi - pi->vi;
3837 	MPASS(index > 0);	/* This function deals with _extra_ VIs only */
3838 	KASSERT(index < nitems(vi_mac_funcs),
3839 	    ("%s: VI %s doesn't have a MAC func", __func__,
3840 	    device_get_nameunit(vi->dev)));
3841 	func = vi_mac_funcs[index];
3842 	rc = t4_alloc_vi_func(sc, sc->mbox, pi->hw_port, sc->pf, 0, 1,
3843 	    vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
3844 	if (rc < 0) {
3845 		CH_ERR(vi, "failed to allocate virtual interface %d"
3846 		    "for port %d: %d\n", index, pi->port_id, -rc);
3847 		return (-rc);
3848 	}
3849 	vi->viid = rc;
3850 
3851 	if (vi->rss_size == 1) {
3852 		/*
3853 		 * This VI didn't get a slice of the RSS table.  Reduce the
3854 		 * number of VIs being created (hw.cxgbe.num_vis) or modify the
3855 		 * configuration file (nvi, rssnvi for this PF) if this is a
3856 		 * problem.
3857 		 */
3858 		device_printf(vi->dev, "RSS table not available.\n");
3859 		vi->rss_base = 0xffff;
3860 
3861 		return (0);
3862 	}
3863 
3864 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3865 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
3866 	    V_FW_PARAMS_PARAM_YZ(vi->viid);
3867 	rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
3868 	if (rc)
3869 		vi->rss_base = 0xffff;
3870 	else {
3871 		MPASS((val >> 16) == vi->rss_size);
3872 		vi->rss_base = val & 0xffff;
3873 	}
3874 
3875 	return (0);
3876 }
3877 
3878 static int
3879 vcxgbe_attach(device_t dev)
3880 {
3881 	struct vi_info *vi;
3882 	struct port_info *pi;
3883 	struct adapter *sc;
3884 	int rc;
3885 
3886 	vi = device_get_softc(dev);
3887 	pi = vi->pi;
3888 	sc = pi->adapter;
3889 
3890 	rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
3891 	if (rc)
3892 		return (rc);
3893 	rc = alloc_extra_vi(sc, pi, vi);
3894 	end_synchronized_op(sc, 0);
3895 	if (rc)
3896 		return (rc);
3897 
3898 	cxgbe_vi_attach(dev, vi);
3899 
3900 	return (0);
3901 }
3902 
3903 static int
3904 vcxgbe_detach(device_t dev)
3905 {
3906 	struct vi_info *vi;
3907 	struct adapter *sc;
3908 
3909 	vi = device_get_softc(dev);
3910 	sc = vi->adapter;
3911 
3912 	begin_vi_detach(sc, vi);
3913 	cxgbe_vi_detach(vi);
3914 	t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
3915 	end_vi_detach(sc, vi);
3916 
3917 	return (0);
3918 }
3919 
3920 static struct callout fatal_callout;
3921 static struct taskqueue *reset_tq;
3922 
3923 static void
3924 delayed_panic(void *arg)
3925 {
3926 	struct adapter *sc = arg;
3927 
3928 	panic("%s: panic on fatal error", device_get_nameunit(sc->dev));
3929 }
3930 
3931 static void
3932 fatal_error_task(void *arg, int pending)
3933 {
3934 	struct adapter *sc = arg;
3935 	int rc;
3936 
3937 	if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) {
3938 		dump_cim_regs(sc);
3939 		dump_cimla(sc);
3940 		dump_devlog(sc);
3941 	}
3942 
3943 	if (t4_reset_on_fatal_err) {
3944 		CH_ALERT(sc, "resetting adapter after fatal error.\n");
3945 		rc = reset_adapter(sc);
3946 		if (rc == 0 && t4_panic_on_fatal_err) {
3947 			CH_ALERT(sc, "reset was successful, "
3948 			    "system will NOT panic.\n");
3949 			return;
3950 		}
3951 	}
3952 
3953 	if (t4_panic_on_fatal_err) {
3954 		CH_ALERT(sc, "panicking on fatal error (after 30s).\n");
3955 		callout_reset(&fatal_callout, hz * 30, delayed_panic, sc);
3956 	}
3957 }
3958 
3959 void
3960 t4_fatal_err(struct adapter *sc, bool fw_error)
3961 {
3962 	stop_adapter(sc);
3963 	if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR)))
3964 		return;
3965 	if (fw_error) {
3966 		/*
3967 		 * We are here because of a firmware error/timeout and not
3968 		 * because of a hardware interrupt.  It is possible (although
3969 		 * not very likely) that an error interrupt was also raised but
3970 		 * this thread ran first and inhibited t4_intr_err.  We walk the
3971 		 * main INT_CAUSE registers here to make sure we haven't missed
3972 		 * anything interesting.
3973 		 */
3974 		t4_slow_intr_handler(sc, sc->intr_flags);
3975 		atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
3976 	}
3977 	t4_report_fw_error(sc);
3978 	log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n",
3979 	    device_get_nameunit(sc->dev), fw_error);
3980 	taskqueue_enqueue(reset_tq, &sc->fatal_error_task);
3981 }
3982 
3983 void
3984 t4_add_adapter(struct adapter *sc)
3985 {
3986 	sx_xlock(&t4_list_lock);
3987 	SLIST_INSERT_HEAD(&t4_list, sc, link);
3988 	sx_xunlock(&t4_list_lock);
3989 }
3990 
3991 int
3992 t4_map_bars_0_and_4(struct adapter *sc)
3993 {
3994 	sc->regs_rid = PCIR_BAR(0);
3995 	sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3996 	    &sc->regs_rid, RF_ACTIVE);
3997 	if (sc->regs_res == NULL) {
3998 		device_printf(sc->dev, "cannot map registers.\n");
3999 		return (ENXIO);
4000 	}
4001 	sc->mmio_len = rman_get_size(sc->regs_res);
4002 	setbit(&sc->doorbells, DOORBELL_KDB);
4003 
4004 	sc->msix_rid = PCIR_BAR(4);
4005 	sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4006 	    &sc->msix_rid, RF_ACTIVE);
4007 	if (sc->msix_res == NULL) {
4008 		device_printf(sc->dev, "cannot map MSI-X BAR.\n");
4009 		return (ENXIO);
4010 	}
4011 
4012 	return (0);
4013 }
4014 
4015 int
4016 t4_map_bar_2(struct adapter *sc)
4017 {
4018 
4019 	/*
4020 	 * T4: only iWARP driver uses the userspace doorbells.  There is no need
4021 	 * to map it if RDMA is disabled.
4022 	 */
4023 	if (is_t4(sc) && sc->rdmacaps == 0)
4024 		return (0);
4025 
4026 	sc->udbs_rid = PCIR_BAR(2);
4027 	sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4028 	    &sc->udbs_rid, RF_ACTIVE);
4029 	if (sc->udbs_res == NULL) {
4030 		device_printf(sc->dev, "cannot map doorbell BAR.\n");
4031 		return (ENXIO);
4032 	}
4033 	sc->udbs_base = rman_get_virtual(sc->udbs_res);
4034 
4035 	if (chip_id(sc) >= CHELSIO_T5) {
4036 		setbit(&sc->doorbells, DOORBELL_UDB);
4037 #if defined(__i386__) || defined(__amd64__)
4038 		if (t5_write_combine) {
4039 			int rc, mode;
4040 
4041 			/*
4042 			 * Enable write combining on BAR2.  This is the
4043 			 * userspace doorbell BAR and is split into 128B
4044 			 * (UDBS_SEG_SIZE) doorbell regions, each associated
4045 			 * with an egress queue.  The first 64B has the doorbell
4046 			 * and the second 64B can be used to submit a tx work
4047 			 * request with an implicit doorbell.
4048 			 */
4049 
4050 			rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
4051 			    rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
4052 			if (rc == 0) {
4053 				clrbit(&sc->doorbells, DOORBELL_UDB);
4054 				setbit(&sc->doorbells, DOORBELL_WCWR);
4055 				setbit(&sc->doorbells, DOORBELL_UDBWC);
4056 			} else {
4057 				device_printf(sc->dev,
4058 				    "couldn't enable write combining: %d\n",
4059 				    rc);
4060 			}
4061 
4062 			mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
4063 			t4_write_reg(sc, A_SGE_STAT_CFG,
4064 			    V_STATSOURCE_T5(7) | mode);
4065 		}
4066 #endif
4067 	}
4068 	sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
4069 
4070 	return (0);
4071 }
4072 
4073 int
4074 t4_adj_doorbells(struct adapter *sc)
4075 {
4076 	if ((sc->doorbells & t4_doorbells_allowed) != 0) {
4077 		sc->doorbells &= t4_doorbells_allowed;
4078 		return (0);
4079 	}
4080 	CH_ERR(sc, "No usable doorbell (available = 0x%x, allowed = 0x%x).\n",
4081 	       sc->doorbells, t4_doorbells_allowed);
4082 	return (EINVAL);
4083 }
4084 
4085 struct memwin_init {
4086 	uint32_t base;
4087 	uint32_t aperture;
4088 };
4089 
4090 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
4091 	{ MEMWIN0_BASE, MEMWIN0_APERTURE },
4092 	{ MEMWIN1_BASE, MEMWIN1_APERTURE },
4093 	{ MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
4094 };
4095 
4096 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
4097 	{ MEMWIN0_BASE, MEMWIN0_APERTURE },
4098 	{ MEMWIN1_BASE, MEMWIN1_APERTURE },
4099 	{ MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
4100 };
4101 
4102 static void
4103 setup_memwin(struct adapter *sc)
4104 {
4105 	const struct memwin_init *mw_init;
4106 	struct memwin *mw;
4107 	int i;
4108 	uint32_t bar0, reg;
4109 
4110 	if (is_t4(sc)) {
4111 		/*
4112 		 * Read low 32b of bar0 indirectly via the hardware backdoor
4113 		 * mechanism.  Works from within PCI passthrough environments
4114 		 * too, where rman_get_start() can return a different value.  We
4115 		 * need to program the T4 memory window decoders with the actual
4116 		 * addresses that will be coming across the PCIe link.
4117 		 */
4118 		bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
4119 		bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
4120 
4121 		mw_init = &t4_memwin[0];
4122 	} else {
4123 		/* T5+ use the relative offset inside the PCIe BAR */
4124 		bar0 = 0;
4125 
4126 		mw_init = &t5_memwin[0];
4127 	}
4128 
4129 	for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
4130 		if (!rw_initialized(&mw->mw_lock)) {
4131 			rw_init(&mw->mw_lock, "memory window access");
4132 			mw->mw_base = mw_init->base;
4133 			mw->mw_aperture = mw_init->aperture;
4134 			mw->mw_curpos = 0;
4135 		}
4136 		reg = chip_id(sc) > CHELSIO_T6 ?
4137 		    PCIE_MEM_ACCESS_T7_REG(A_T7_PCIE_MEM_ACCESS_BASE_WIN, i) :
4138 		    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i);
4139 		t4_write_reg(sc, reg, (mw->mw_base + bar0) | V_BIR(0) |
4140 		    V_WINDOW(ilog2(mw->mw_aperture) - 10));
4141 		rw_wlock(&mw->mw_lock);
4142 		position_memwin(sc, i, mw->mw_curpos);
4143 		rw_wunlock(&mw->mw_lock);
4144 	}
4145 
4146 	/* flush */
4147 	t4_read_reg(sc, reg);
4148 }
4149 
4150 /*
4151  * Positions the memory window at the given address in the card's address space.
4152  * There are some alignment requirements and the actual position may be at an
4153  * address prior to the requested address.  mw->mw_curpos always has the actual
4154  * position of the window.
4155  */
4156 static void
4157 position_memwin(struct adapter *sc, int idx, uint32_t addr)
4158 {
4159 	struct memwin *mw;
4160 	uint32_t pf, reg, val;
4161 
4162 	MPASS(idx >= 0 && idx < NUM_MEMWIN);
4163 	mw = &sc->memwin[idx];
4164 	rw_assert(&mw->mw_lock, RA_WLOCKED);
4165 
4166 	if (is_t4(sc)) {
4167 		pf = 0;
4168 		mw->mw_curpos = addr & ~0xf;	/* start must be 16B aligned */
4169 	} else {
4170 		pf = V_PFNUM(sc->pf);
4171 		mw->mw_curpos = addr & ~0x7f;	/* start must be 128B aligned */
4172 	}
4173 	if (chip_id(sc) > CHELSIO_T6) {
4174 		reg = PCIE_MEM_ACCESS_T7_REG(A_PCIE_MEM_ACCESS_OFFSET0, idx);
4175 		val = (mw->mw_curpos >> X_T7_MEMOFST_SHIFT) | pf;
4176 	} else {
4177 		reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
4178 		val = mw->mw_curpos | pf;
4179 	}
4180 	t4_write_reg(sc, reg, val);
4181 	t4_read_reg(sc, reg);	/* flush */
4182 }
4183 
4184 int
4185 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
4186     int len, int rw)
4187 {
4188 	struct memwin *mw;
4189 	uint32_t mw_end, v;
4190 
4191 	MPASS(idx >= 0 && idx < NUM_MEMWIN);
4192 
4193 	/* Memory can only be accessed in naturally aligned 4 byte units */
4194 	if (addr & 3 || len & 3 || len <= 0)
4195 		return (EINVAL);
4196 
4197 	mw = &sc->memwin[idx];
4198 	while (len > 0) {
4199 		rw_rlock(&mw->mw_lock);
4200 		mw_end = mw->mw_curpos + mw->mw_aperture;
4201 		if (addr >= mw_end || addr < mw->mw_curpos) {
4202 			/* Will need to reposition the window */
4203 			if (!rw_try_upgrade(&mw->mw_lock)) {
4204 				rw_runlock(&mw->mw_lock);
4205 				rw_wlock(&mw->mw_lock);
4206 			}
4207 			rw_assert(&mw->mw_lock, RA_WLOCKED);
4208 			position_memwin(sc, idx, addr);
4209 			rw_downgrade(&mw->mw_lock);
4210 			mw_end = mw->mw_curpos + mw->mw_aperture;
4211 		}
4212 		rw_assert(&mw->mw_lock, RA_RLOCKED);
4213 		while (addr < mw_end && len > 0) {
4214 			if (rw == 0) {
4215 				v = t4_read_reg(sc, mw->mw_base + addr -
4216 				    mw->mw_curpos);
4217 				*val++ = le32toh(v);
4218 			} else {
4219 				v = *val++;
4220 				t4_write_reg(sc, mw->mw_base + addr -
4221 				    mw->mw_curpos, htole32(v));
4222 			}
4223 			addr += 4;
4224 			len -= 4;
4225 		}
4226 		rw_runlock(&mw->mw_lock);
4227 	}
4228 
4229 	return (0);
4230 }
4231 
4232 CTASSERT(M_TID_COOKIE == M_COOKIE);
4233 CTASSERT(MAX_ATIDS <= (M_TID_TID + 1));
4234 
4235 static void
4236 t4_init_atid_table(struct adapter *sc)
4237 {
4238 	struct tid_info *t;
4239 	int i;
4240 
4241 	t = &sc->tids;
4242 	if (t->natids == 0)
4243 		return;
4244 
4245 	MPASS(t->atid_tab == NULL);
4246 
4247 	t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
4248 	    M_ZERO | M_WAITOK);
4249 	mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
4250 	t->afree = t->atid_tab;
4251 	t->atids_in_use = 0;
4252 	t->atid_alloc_stopped = false;
4253 	for (i = 1; i < t->natids; i++)
4254 		t->atid_tab[i - 1].next = &t->atid_tab[i];
4255 	t->atid_tab[t->natids - 1].next = NULL;
4256 }
4257 
4258 static void
4259 t4_free_atid_table(struct adapter *sc)
4260 {
4261 	struct tid_info *t;
4262 
4263 	t = &sc->tids;
4264 
4265 	KASSERT(t->atids_in_use == 0,
4266 	    ("%s: %d atids still in use.", __func__, t->atids_in_use));
4267 
4268 	if (mtx_initialized(&t->atid_lock))
4269 		mtx_destroy(&t->atid_lock);
4270 	free(t->atid_tab, M_CXGBE);
4271 	t->atid_tab = NULL;
4272 }
4273 
4274 static void
4275 stop_atid_allocator(struct adapter *sc)
4276 {
4277 	struct tid_info *t = &sc->tids;
4278 
4279 	if (t->natids == 0)
4280 		return;
4281 	mtx_lock(&t->atid_lock);
4282 	t->atid_alloc_stopped = true;
4283 	mtx_unlock(&t->atid_lock);
4284 }
4285 
4286 static void
4287 restart_atid_allocator(struct adapter *sc)
4288 {
4289 	struct tid_info *t = &sc->tids;
4290 
4291 	if (t->natids == 0)
4292 		return;
4293 	mtx_lock(&t->atid_lock);
4294 	KASSERT(t->atids_in_use == 0,
4295 	    ("%s: %d atids still in use.", __func__, t->atids_in_use));
4296 	t->atid_alloc_stopped = false;
4297 	mtx_unlock(&t->atid_lock);
4298 }
4299 
4300 int
4301 alloc_atid(struct adapter *sc, void *ctx)
4302 {
4303 	struct tid_info *t = &sc->tids;
4304 	int atid = -1;
4305 
4306 	mtx_lock(&t->atid_lock);
4307 	if (t->afree && !t->atid_alloc_stopped) {
4308 		union aopen_entry *p = t->afree;
4309 
4310 		atid = p - t->atid_tab;
4311 		MPASS(atid <= M_TID_TID);
4312 		t->afree = p->next;
4313 		p->data = ctx;
4314 		t->atids_in_use++;
4315 	}
4316 	mtx_unlock(&t->atid_lock);
4317 	return (atid);
4318 }
4319 
4320 void *
4321 lookup_atid(struct adapter *sc, int atid)
4322 {
4323 	struct tid_info *t = &sc->tids;
4324 
4325 	return (t->atid_tab[atid].data);
4326 }
4327 
4328 void
4329 free_atid(struct adapter *sc, int atid)
4330 {
4331 	struct tid_info *t = &sc->tids;
4332 	union aopen_entry *p = &t->atid_tab[atid];
4333 
4334 	mtx_lock(&t->atid_lock);
4335 	p->next = t->afree;
4336 	t->afree = p;
4337 	t->atids_in_use--;
4338 	mtx_unlock(&t->atid_lock);
4339 }
4340 
4341 static void
4342 queue_tid_release(struct adapter *sc, int tid)
4343 {
4344 
4345 	CXGBE_UNIMPLEMENTED("deferred tid release");
4346 }
4347 
4348 void
4349 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
4350 {
4351 	struct wrqe *wr;
4352 	struct cpl_tid_release *req;
4353 
4354 	wr = alloc_wrqe(sizeof(*req), ctrlq);
4355 	if (wr == NULL) {
4356 		queue_tid_release(sc, tid);	/* defer */
4357 		return;
4358 	}
4359 	req = wrtod(wr);
4360 
4361 	INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
4362 
4363 	t4_wrq_tx(sc, wr);
4364 }
4365 
4366 static int
4367 t4_range_cmp(const void *a, const void *b)
4368 {
4369 	return ((const struct t4_range *)a)->start -
4370 	       ((const struct t4_range *)b)->start;
4371 }
4372 
4373 /*
4374  * Verify that the memory range specified by the addr/len pair is valid within
4375  * the card's address space.
4376  */
4377 static int
4378 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
4379 {
4380 	struct t4_range mem_ranges[4], *r, *next;
4381 	uint32_t em, addr_len;
4382 	int i, n, remaining;
4383 
4384 	/* Memory can only be accessed in naturally aligned 4 byte units */
4385 	if (addr & 3 || len & 3 || len == 0)
4386 		return (EINVAL);
4387 
4388 	/* Enabled memories */
4389 	em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
4390 
4391 	r = &mem_ranges[0];
4392 	n = 0;
4393 	bzero(r, sizeof(mem_ranges));
4394 	if (em & F_EDRAM0_ENABLE) {
4395 		addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
4396 		r->size = G_EDRAM0_SIZE(addr_len) << 20;
4397 		if (r->size > 0) {
4398 			r->start = G_EDRAM0_BASE(addr_len) << 20;
4399 			if (addr >= r->start &&
4400 			    addr + len <= r->start + r->size)
4401 				return (0);
4402 			r++;
4403 			n++;
4404 		}
4405 	}
4406 	if (em & F_EDRAM1_ENABLE) {
4407 		addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
4408 		r->size = G_EDRAM1_SIZE(addr_len) << 20;
4409 		if (r->size > 0) {
4410 			r->start = G_EDRAM1_BASE(addr_len) << 20;
4411 			if (addr >= r->start &&
4412 			    addr + len <= r->start + r->size)
4413 				return (0);
4414 			r++;
4415 			n++;
4416 		}
4417 	}
4418 	if (em & F_EXT_MEM_ENABLE) {
4419 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
4420 		r->size = G_EXT_MEM_SIZE(addr_len) << 20;
4421 		if (r->size > 0) {
4422 			r->start = G_EXT_MEM_BASE(addr_len) << 20;
4423 			if (addr >= r->start &&
4424 			    addr + len <= r->start + r->size)
4425 				return (0);
4426 			r++;
4427 			n++;
4428 		}
4429 	}
4430 	if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
4431 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
4432 		r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
4433 		if (r->size > 0) {
4434 			r->start = G_EXT_MEM1_BASE(addr_len) << 20;
4435 			if (addr >= r->start &&
4436 			    addr + len <= r->start + r->size)
4437 				return (0);
4438 			r++;
4439 			n++;
4440 		}
4441 	}
4442 	MPASS(n <= nitems(mem_ranges));
4443 
4444 	if (n > 1) {
4445 		/* Sort and merge the ranges. */
4446 		qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
4447 
4448 		/* Start from index 0 and examine the next n - 1 entries. */
4449 		r = &mem_ranges[0];
4450 		for (remaining = n - 1; remaining > 0; remaining--, r++) {
4451 
4452 			MPASS(r->size > 0);	/* r is a valid entry. */
4453 			next = r + 1;
4454 			MPASS(next->size > 0);	/* and so is the next one. */
4455 
4456 			while (r->start + r->size >= next->start) {
4457 				/* Merge the next one into the current entry. */
4458 				r->size = max(r->start + r->size,
4459 				    next->start + next->size) - r->start;
4460 				n--;	/* One fewer entry in total. */
4461 				if (--remaining == 0)
4462 					goto done;	/* short circuit */
4463 				next++;
4464 			}
4465 			if (next != r + 1) {
4466 				/*
4467 				 * Some entries were merged into r and next
4468 				 * points to the first valid entry that couldn't
4469 				 * be merged.
4470 				 */
4471 				MPASS(next->size > 0);	/* must be valid */
4472 				memcpy(r + 1, next, remaining * sizeof(*r));
4473 #ifdef INVARIANTS
4474 				/*
4475 				 * This so that the foo->size assertion in the
4476 				 * next iteration of the loop do the right
4477 				 * thing for entries that were pulled up and are
4478 				 * no longer valid.
4479 				 */
4480 				MPASS(n < nitems(mem_ranges));
4481 				bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
4482 				    sizeof(struct t4_range));
4483 #endif
4484 			}
4485 		}
4486 done:
4487 		/* Done merging the ranges. */
4488 		MPASS(n > 0);
4489 		r = &mem_ranges[0];
4490 		for (i = 0; i < n; i++, r++) {
4491 			if (addr >= r->start &&
4492 			    addr + len <= r->start + r->size)
4493 				return (0);
4494 		}
4495 	}
4496 
4497 	return (EFAULT);
4498 }
4499 
4500 static int
4501 fwmtype_to_hwmtype(int mtype)
4502 {
4503 
4504 	switch (mtype) {
4505 	case FW_MEMTYPE_EDC0:
4506 		return (MEM_EDC0);
4507 	case FW_MEMTYPE_EDC1:
4508 		return (MEM_EDC1);
4509 	case FW_MEMTYPE_EXTMEM:
4510 		return (MEM_MC0);
4511 	case FW_MEMTYPE_EXTMEM1:
4512 		return (MEM_MC1);
4513 	default:
4514 		panic("%s: cannot translate fw mtype %d.", __func__, mtype);
4515 	}
4516 }
4517 
4518 /*
4519  * Verify that the memory range specified by the memtype/offset/len pair is
4520  * valid and lies entirely within the memtype specified.  The global address of
4521  * the start of the range is returned in addr.
4522  */
4523 static int
4524 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
4525     uint32_t *addr)
4526 {
4527 	uint32_t em, addr_len, maddr;
4528 
4529 	/* Memory can only be accessed in naturally aligned 4 byte units */
4530 	if (off & 3 || len & 3 || len == 0)
4531 		return (EINVAL);
4532 
4533 	em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
4534 	switch (fwmtype_to_hwmtype(mtype)) {
4535 	case MEM_EDC0:
4536 		if (!(em & F_EDRAM0_ENABLE))
4537 			return (EINVAL);
4538 		addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
4539 		maddr = G_EDRAM0_BASE(addr_len) << 20;
4540 		break;
4541 	case MEM_EDC1:
4542 		if (!(em & F_EDRAM1_ENABLE))
4543 			return (EINVAL);
4544 		addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
4545 		maddr = G_EDRAM1_BASE(addr_len) << 20;
4546 		break;
4547 	case MEM_MC:
4548 		if (!(em & F_EXT_MEM_ENABLE))
4549 			return (EINVAL);
4550 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
4551 		maddr = G_EXT_MEM_BASE(addr_len) << 20;
4552 		break;
4553 	case MEM_MC1:
4554 		if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
4555 			return (EINVAL);
4556 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
4557 		maddr = G_EXT_MEM1_BASE(addr_len) << 20;
4558 		break;
4559 	default:
4560 		return (EINVAL);
4561 	}
4562 
4563 	*addr = maddr + off;	/* global address */
4564 	return (validate_mem_range(sc, *addr, len));
4565 }
4566 
4567 static int
4568 fixup_devlog_params(struct adapter *sc)
4569 {
4570 	struct devlog_params *dparams = &sc->params.devlog;
4571 	int rc;
4572 
4573 	rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
4574 	    dparams->size, &dparams->addr);
4575 
4576 	return (rc);
4577 }
4578 
4579 static void
4580 update_nirq(struct intrs_and_queues *iaq, int nports)
4581 {
4582 
4583 	iaq->nirq = T4_EXTRA_INTR;
4584 	iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq);
4585 	iaq->nirq += nports * iaq->nofldrxq;
4586 	iaq->nirq += nports * (iaq->num_vis - 1) *
4587 	    max(iaq->nrxq_vi, iaq->nnmrxq_vi);
4588 	iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
4589 }
4590 
4591 /*
4592  * Adjust requirements to fit the number of interrupts available.
4593  */
4594 static void
4595 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
4596     int navail)
4597 {
4598 	int old_nirq;
4599 	const int nports = sc->params.nports;
4600 
4601 	MPASS(nports > 0);
4602 	MPASS(navail > 0);
4603 
4604 	bzero(iaq, sizeof(*iaq));
4605 	iaq->intr_type = itype;
4606 	iaq->num_vis = t4_num_vis;
4607 	iaq->ntxq = t4_ntxq;
4608 	iaq->ntxq_vi = t4_ntxq_vi;
4609 	iaq->nrxq = t4_nrxq;
4610 	iaq->nrxq_vi = t4_nrxq_vi;
4611 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4612 	if (is_offload(sc) || is_ethoffload(sc)) {
4613 		if (sc->params.tid_qid_sel_mask == 0) {
4614 			iaq->nofldtxq = t4_nofldtxq;
4615 			iaq->nofldtxq_vi = t4_nofldtxq_vi;
4616 		} else {
4617 			iaq->nofldtxq = roundup(t4_nofldtxq, sc->params.ncores);
4618 			iaq->nofldtxq_vi = roundup(t4_nofldtxq_vi,
4619 			    sc->params.ncores);
4620 			if (iaq->nofldtxq != t4_nofldtxq)
4621 				device_printf(sc->dev,
4622 				    "nofldtxq updated (%d -> %d) for correct"
4623 				    " operation with %d firmware cores.\n",
4624 				    t4_nofldtxq, iaq->nofldtxq,
4625 				    sc->params.ncores);
4626 			if (iaq->num_vis > 1 &&
4627 			    iaq->nofldtxq_vi != t4_nofldtxq_vi)
4628 				device_printf(sc->dev,
4629 				    "nofldtxq_vi updated (%d -> %d) for correct"
4630 				    " operation with %d firmware cores.\n",
4631 				    t4_nofldtxq_vi, iaq->nofldtxq_vi,
4632 				    sc->params.ncores);
4633 		}
4634 	}
4635 #endif
4636 #ifdef TCP_OFFLOAD
4637 	if (is_offload(sc)) {
4638 		iaq->nofldrxq = t4_nofldrxq;
4639 		iaq->nofldrxq_vi = t4_nofldrxq_vi;
4640 	}
4641 #endif
4642 #ifdef DEV_NETMAP
4643 	if (t4_native_netmap & NN_MAIN_VI) {
4644 		iaq->nnmtxq = t4_nnmtxq;
4645 		iaq->nnmrxq = t4_nnmrxq;
4646 	}
4647 	if (t4_native_netmap & NN_EXTRA_VI) {
4648 		iaq->nnmtxq_vi = t4_nnmtxq_vi;
4649 		iaq->nnmrxq_vi = t4_nnmrxq_vi;
4650 	}
4651 #endif
4652 
4653 	update_nirq(iaq, nports);
4654 	if (iaq->nirq <= navail &&
4655 	    (itype != INTR_MSI || powerof2(iaq->nirq))) {
4656 		/*
4657 		 * This is the normal case -- there are enough interrupts for
4658 		 * everything.
4659 		 */
4660 		goto done;
4661 	}
4662 
4663 	/*
4664 	 * If extra VIs have been configured try reducing their count and see if
4665 	 * that works.
4666 	 */
4667 	while (iaq->num_vis > 1) {
4668 		iaq->num_vis--;
4669 		update_nirq(iaq, nports);
4670 		if (iaq->nirq <= navail &&
4671 		    (itype != INTR_MSI || powerof2(iaq->nirq))) {
4672 			device_printf(sc->dev, "virtual interfaces per port "
4673 			    "reduced to %d from %d.  nrxq=%u, nofldrxq=%u, "
4674 			    "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u.  "
4675 			    "itype %d, navail %u, nirq %d.\n",
4676 			    iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
4677 			    iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
4678 			    itype, navail, iaq->nirq);
4679 			goto done;
4680 		}
4681 	}
4682 
4683 	/*
4684 	 * Extra VIs will not be created.  Log a message if they were requested.
4685 	 */
4686 	MPASS(iaq->num_vis == 1);
4687 	iaq->ntxq_vi = iaq->nrxq_vi = 0;
4688 	iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
4689 	iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
4690 	if (iaq->num_vis != t4_num_vis) {
4691 		device_printf(sc->dev, "extra virtual interfaces disabled.  "
4692 		    "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
4693 		    "nnmrxq_vi=%u.  itype %d, navail %u, nirq %d.\n",
4694 		    iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
4695 		    iaq->nnmrxq_vi, itype, navail, iaq->nirq);
4696 	}
4697 
4698 	/*
4699 	 * Keep reducing the number of NIC rx queues to the next lower power of
4700 	 * 2 (for even RSS distribution) and halving the TOE rx queues and see
4701 	 * if that works.
4702 	 */
4703 	do {
4704 		if (iaq->nrxq > 1) {
4705 			iaq->nrxq = rounddown_pow_of_two(iaq->nrxq - 1);
4706 			if (iaq->nnmrxq > iaq->nrxq)
4707 				iaq->nnmrxq = iaq->nrxq;
4708 		}
4709 		if (iaq->nofldrxq > 1)
4710 			iaq->nofldrxq >>= 1;
4711 
4712 		old_nirq = iaq->nirq;
4713 		update_nirq(iaq, nports);
4714 		if (iaq->nirq <= navail &&
4715 		    (itype != INTR_MSI || powerof2(iaq->nirq))) {
4716 			device_printf(sc->dev, "running with reduced number of "
4717 			    "rx queues because of shortage of interrupts.  "
4718 			    "nrxq=%u, nofldrxq=%u.  "
4719 			    "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
4720 			    iaq->nofldrxq, itype, navail, iaq->nirq);
4721 			goto done;
4722 		}
4723 	} while (old_nirq != iaq->nirq);
4724 
4725 	/* One interrupt for everything.  Ugh. */
4726 	device_printf(sc->dev, "running with minimal number of queues.  "
4727 	    "itype %d, navail %u.\n", itype, navail);
4728 	iaq->nirq = 1;
4729 	iaq->nrxq = 1;
4730 	iaq->ntxq = 1;
4731 	if (iaq->nofldrxq > 0) {
4732 		iaq->nofldrxq = 1;
4733 		iaq->nofldtxq = 1;
4734 		if (sc->params.tid_qid_sel_mask == 0)
4735 			iaq->nofldtxq = 1;
4736 		else
4737 			iaq->nofldtxq = sc->params.ncores;
4738 	}
4739 	iaq->nnmtxq = 0;
4740 	iaq->nnmrxq = 0;
4741 done:
4742 	MPASS(iaq->num_vis > 0);
4743 	if (iaq->num_vis > 1) {
4744 		MPASS(iaq->nrxq_vi > 0);
4745 		MPASS(iaq->ntxq_vi > 0);
4746 	}
4747 	MPASS(iaq->nirq > 0);
4748 	MPASS(iaq->nrxq > 0);
4749 	MPASS(iaq->ntxq > 0);
4750 	if (itype == INTR_MSI)
4751 		MPASS(powerof2(iaq->nirq));
4752 	if (sc->params.tid_qid_sel_mask != 0)
4753 		MPASS(iaq->nofldtxq % sc->params.ncores == 0);
4754 }
4755 
4756 static int
4757 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
4758 {
4759 	int rc, itype, navail, nalloc;
4760 
4761 	for (itype = INTR_MSIX; itype; itype >>= 1) {
4762 
4763 		if ((itype & t4_intr_types) == 0)
4764 			continue;	/* not allowed */
4765 
4766 		if (itype == INTR_MSIX)
4767 			navail = pci_msix_count(sc->dev);
4768 		else if (itype == INTR_MSI)
4769 			navail = pci_msi_count(sc->dev);
4770 		else
4771 			navail = 1;
4772 restart:
4773 		if (navail == 0)
4774 			continue;
4775 
4776 		calculate_iaq(sc, iaq, itype, navail);
4777 		nalloc = iaq->nirq;
4778 		rc = 0;
4779 		if (itype == INTR_MSIX)
4780 			rc = pci_alloc_msix(sc->dev, &nalloc);
4781 		else if (itype == INTR_MSI)
4782 			rc = pci_alloc_msi(sc->dev, &nalloc);
4783 
4784 		if (rc == 0 && nalloc > 0) {
4785 			if (nalloc == iaq->nirq)
4786 				return (0);
4787 
4788 			/*
4789 			 * Didn't get the number requested.  Use whatever number
4790 			 * the kernel is willing to allocate.
4791 			 */
4792 			device_printf(sc->dev, "fewer vectors than requested, "
4793 			    "type=%d, req=%d, rcvd=%d; will downshift req.\n",
4794 			    itype, iaq->nirq, nalloc);
4795 			pci_release_msi(sc->dev);
4796 			navail = nalloc;
4797 			goto restart;
4798 		}
4799 
4800 		device_printf(sc->dev,
4801 		    "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
4802 		    itype, rc, iaq->nirq, nalloc);
4803 	}
4804 
4805 	device_printf(sc->dev,
4806 	    "failed to find a usable interrupt type.  "
4807 	    "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
4808 	    pci_msix_count(sc->dev), pci_msi_count(sc->dev));
4809 
4810 	return (ENXIO);
4811 }
4812 
4813 #define FW_VERSION(chip) ( \
4814     V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
4815     V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
4816     V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
4817     V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
4818 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
4819 
4820 /* Just enough of fw_hdr to cover all version info. */
4821 struct fw_h {
4822 	__u8	ver;
4823 	__u8	chip;
4824 	__be16	len512;
4825 	__be32	fw_ver;
4826 	__be32	tp_microcode_ver;
4827 	__u8	intfver_nic;
4828 	__u8	intfver_vnic;
4829 	__u8	intfver_ofld;
4830 	__u8	intfver_ri;
4831 	__u8	intfver_iscsipdu;
4832 	__u8	intfver_iscsi;
4833 	__u8	intfver_fcoepdu;
4834 	__u8	intfver_fcoe;
4835 };
4836 /* Spot check a couple of fields. */
4837 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
4838 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
4839 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
4840 
4841 struct fw_info {
4842 	uint8_t chip;
4843 	char *kld_name;
4844 	char *fw_mod_name;
4845 	struct fw_h fw_h;
4846 } fw_info[] = {
4847 	{
4848 		.chip = CHELSIO_T4,
4849 		.kld_name = "t4fw_cfg",
4850 		.fw_mod_name = "t4fw",
4851 		.fw_h = {
4852 			.chip = FW_HDR_CHIP_T4,
4853 			.fw_ver = htobe32(FW_VERSION(T4)),
4854 			.intfver_nic = FW_INTFVER(T4, NIC),
4855 			.intfver_vnic = FW_INTFVER(T4, VNIC),
4856 			.intfver_ofld = FW_INTFVER(T4, OFLD),
4857 			.intfver_ri = FW_INTFVER(T4, RI),
4858 			.intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
4859 			.intfver_iscsi = FW_INTFVER(T4, ISCSI),
4860 			.intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
4861 			.intfver_fcoe = FW_INTFVER(T4, FCOE),
4862 		},
4863 	}, {
4864 		.chip = CHELSIO_T5,
4865 		.kld_name = "t5fw_cfg",
4866 		.fw_mod_name = "t5fw",
4867 		.fw_h = {
4868 			.chip = FW_HDR_CHIP_T5,
4869 			.fw_ver = htobe32(FW_VERSION(T5)),
4870 			.intfver_nic = FW_INTFVER(T5, NIC),
4871 			.intfver_vnic = FW_INTFVER(T5, VNIC),
4872 			.intfver_ofld = FW_INTFVER(T5, OFLD),
4873 			.intfver_ri = FW_INTFVER(T5, RI),
4874 			.intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
4875 			.intfver_iscsi = FW_INTFVER(T5, ISCSI),
4876 			.intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
4877 			.intfver_fcoe = FW_INTFVER(T5, FCOE),
4878 		},
4879 	}, {
4880 		.chip = CHELSIO_T6,
4881 		.kld_name = "t6fw_cfg",
4882 		.fw_mod_name = "t6fw",
4883 		.fw_h = {
4884 			.chip = FW_HDR_CHIP_T6,
4885 			.fw_ver = htobe32(FW_VERSION(T6)),
4886 			.intfver_nic = FW_INTFVER(T6, NIC),
4887 			.intfver_vnic = FW_INTFVER(T6, VNIC),
4888 			.intfver_ofld = FW_INTFVER(T6, OFLD),
4889 			.intfver_ri = FW_INTFVER(T6, RI),
4890 			.intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4891 			.intfver_iscsi = FW_INTFVER(T6, ISCSI),
4892 			.intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4893 			.intfver_fcoe = FW_INTFVER(T6, FCOE),
4894 		},
4895 	}, {
4896 		.chip = CHELSIO_T7,
4897 		.kld_name = "t7fw_cfg",
4898 		.fw_mod_name = "t7fw",
4899 		.fw_h = {
4900 			.chip = FW_HDR_CHIP_T7,
4901 			.fw_ver = htobe32(FW_VERSION(T7)),
4902 			.intfver_nic = FW_INTFVER(T7, NIC),
4903 			.intfver_vnic = FW_INTFVER(T7, VNIC),
4904 			.intfver_ofld = FW_INTFVER(T7, OFLD),
4905 			.intfver_ri = FW_INTFVER(T7, RI),
4906 			.intfver_iscsipdu = FW_INTFVER(T7, ISCSIPDU),
4907 			.intfver_iscsi = FW_INTFVER(T7, ISCSI),
4908 			.intfver_fcoepdu = FW_INTFVER(T7, FCOEPDU),
4909 			.intfver_fcoe = FW_INTFVER(T7, FCOE),
4910 		},
4911 	}
4912 };
4913 
4914 static struct fw_info *
4915 find_fw_info(int chip)
4916 {
4917 	int i;
4918 
4919 	for (i = 0; i < nitems(fw_info); i++) {
4920 		if (fw_info[i].chip == chip)
4921 			return (&fw_info[i]);
4922 	}
4923 	return (NULL);
4924 }
4925 
4926 /*
4927  * Is the given firmware API compatible with the one the driver was compiled
4928  * with?
4929  */
4930 static int
4931 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
4932 {
4933 
4934 	/* short circuit if it's the exact same firmware version */
4935 	if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
4936 		return (1);
4937 
4938 	/*
4939 	 * XXX: Is this too conservative?  Perhaps I should limit this to the
4940 	 * features that are supported in the driver.
4941 	 */
4942 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
4943 	if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
4944 	    SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
4945 	    SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
4946 		return (1);
4947 #undef SAME_INTF
4948 
4949 	return (0);
4950 }
4951 
4952 static int
4953 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
4954     const struct firmware **fw)
4955 {
4956 	struct fw_info *fw_info;
4957 
4958 	*dcfg = NULL;
4959 	if (fw != NULL)
4960 		*fw = NULL;
4961 
4962 	fw_info = find_fw_info(chip_id(sc));
4963 	if (fw_info == NULL) {
4964 		device_printf(sc->dev,
4965 		    "unable to look up firmware information for chip %d.\n",
4966 		    chip_id(sc));
4967 		return (EINVAL);
4968 	}
4969 
4970 	*dcfg = firmware_get(fw_info->kld_name);
4971 	if (*dcfg != NULL) {
4972 		if (fw != NULL)
4973 			*fw = firmware_get(fw_info->fw_mod_name);
4974 		return (0);
4975 	}
4976 
4977 	return (ENOENT);
4978 }
4979 
4980 static void
4981 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
4982     const struct firmware *fw)
4983 {
4984 
4985 	if (fw != NULL)
4986 		firmware_put(fw, FIRMWARE_UNLOAD);
4987 	if (dcfg != NULL)
4988 		firmware_put(dcfg, FIRMWARE_UNLOAD);
4989 }
4990 
4991 /*
4992  * Return values:
4993  * 0 means no firmware install attempted.
4994  * ERESTART means a firmware install was attempted and was successful.
4995  * +ve errno means a firmware install was attempted but failed.
4996  */
4997 static int
4998 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
4999     const struct fw_h *drv_fw, const char *reason, int *already)
5000 {
5001 	const struct firmware *cfg, *fw;
5002 	const uint32_t c = be32toh(card_fw->fw_ver);
5003 	uint32_t d, k;
5004 	int rc, fw_install;
5005 	struct fw_h bundled_fw;
5006 	bool load_attempted;
5007 
5008 	cfg = fw = NULL;
5009 	load_attempted = false;
5010 	fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
5011 
5012 	memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
5013 	if (t4_fw_install < 0) {
5014 		rc = load_fw_module(sc, &cfg, &fw);
5015 		if (rc != 0 || fw == NULL) {
5016 			device_printf(sc->dev,
5017 			    "failed to load firmware module: %d. cfg %p, fw %p;"
5018 			    " will use compiled-in firmware version for"
5019 			    "hw.cxgbe.fw_install checks.\n",
5020 			    rc, cfg, fw);
5021 		} else {
5022 			memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
5023 		}
5024 		load_attempted = true;
5025 	}
5026 	d = be32toh(bundled_fw.fw_ver);
5027 
5028 	if (reason != NULL)
5029 		goto install;
5030 
5031 	if ((sc->flags & FW_OK) == 0) {
5032 
5033 		if (c == 0xffffffff) {
5034 			reason = "missing";
5035 			goto install;
5036 		}
5037 
5038 		rc = 0;
5039 		goto done;
5040 	}
5041 
5042 	if (!fw_compatible(card_fw, &bundled_fw)) {
5043 		reason = "incompatible or unusable";
5044 		goto install;
5045 	}
5046 
5047 	if (d > c) {
5048 		reason = "older than the version bundled with this driver";
5049 		goto install;
5050 	}
5051 
5052 	if (fw_install == 2 && d != c) {
5053 		reason = "different than the version bundled with this driver";
5054 		goto install;
5055 	}
5056 
5057 	/* No reason to do anything to the firmware already on the card. */
5058 	rc = 0;
5059 	goto done;
5060 
5061 install:
5062 	rc = 0;
5063 	if ((*already)++)
5064 		goto done;
5065 
5066 	if (fw_install == 0) {
5067 		device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
5068 		    "but the driver is prohibited from installing a firmware "
5069 		    "on the card.\n",
5070 		    G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
5071 		    G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
5072 
5073 		goto done;
5074 	}
5075 
5076 	/*
5077 	 * We'll attempt to install a firmware.  Load the module first (if it
5078 	 * hasn't been loaded already).
5079 	 */
5080 	if (!load_attempted) {
5081 		rc = load_fw_module(sc, &cfg, &fw);
5082 		if (rc != 0 || fw == NULL) {
5083 			device_printf(sc->dev,
5084 			    "failed to load firmware module: %d. cfg %p, fw %p\n",
5085 			    rc, cfg, fw);
5086 			/* carry on */
5087 		}
5088 	}
5089 	if (fw == NULL) {
5090 		device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
5091 		    "but the driver cannot take corrective action because it "
5092 		    "is unable to load the firmware module.\n",
5093 		    G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
5094 		    G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
5095 		rc = sc->flags & FW_OK ? 0 : ENOENT;
5096 		goto done;
5097 	}
5098 	k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
5099 	if (k != d) {
5100 		MPASS(t4_fw_install > 0);
5101 		device_printf(sc->dev,
5102 		    "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
5103 		    "expecting (%u.%u.%u.%u) and will not be used.\n",
5104 		    G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
5105 		    G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
5106 		    G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
5107 		    G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
5108 		rc = sc->flags & FW_OK ? 0 : EINVAL;
5109 		goto done;
5110 	}
5111 
5112 	device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
5113 	    "installing firmware %u.%u.%u.%u on card.\n",
5114 	    G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
5115 	    G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
5116 	    G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
5117 	    G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
5118 
5119 	rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
5120 	if (rc != 0) {
5121 		device_printf(sc->dev, "failed to install firmware: %d\n", rc);
5122 	} else {
5123 		/* Installed successfully, update the cached header too. */
5124 		rc = ERESTART;
5125 		memcpy(card_fw, fw->data, sizeof(*card_fw));
5126 	}
5127 done:
5128 	unload_fw_module(sc, cfg, fw);
5129 
5130 	return (rc);
5131 }
5132 
5133 /*
5134  * Establish contact with the firmware and attempt to become the master driver.
5135  *
5136  * A firmware will be installed to the card if needed (if the driver is allowed
5137  * to do so).
5138  */
5139 static int
5140 contact_firmware(struct adapter *sc)
5141 {
5142 	int rc, already = 0;
5143 	enum dev_state state;
5144 	struct fw_info *fw_info;
5145 	struct fw_hdr *card_fw;		/* fw on the card */
5146 	const struct fw_h *drv_fw;
5147 
5148 	fw_info = find_fw_info(chip_id(sc));
5149 	if (fw_info == NULL) {
5150 		device_printf(sc->dev,
5151 		    "unable to look up firmware information for chip %d.\n",
5152 		    chip_id(sc));
5153 		return (EINVAL);
5154 	}
5155 	drv_fw = &fw_info->fw_h;
5156 
5157 	/* Read the header of the firmware on the card */
5158 	card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
5159 restart:
5160 	rc = -t4_get_fw_hdr(sc, card_fw);
5161 	if (rc != 0) {
5162 		device_printf(sc->dev,
5163 		    "unable to read firmware header from card's flash: %d\n",
5164 		    rc);
5165 		goto done;
5166 	}
5167 
5168 	rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
5169 	    &already);
5170 	if (rc == ERESTART)
5171 		goto restart;
5172 	if (rc != 0)
5173 		goto done;
5174 
5175 	rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
5176 	if (rc < 0 || state == DEV_STATE_ERR) {
5177 		rc = -rc;
5178 		device_printf(sc->dev,
5179 		    "failed to connect to the firmware: %d, %d.  "
5180 		    "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
5181 #if 0
5182 		if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
5183 		    "not responding properly to HELLO", &already) == ERESTART)
5184 			goto restart;
5185 #endif
5186 		goto done;
5187 	}
5188 	MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
5189 	sc->flags |= FW_OK;	/* The firmware responded to the FW_HELLO. */
5190 
5191 	if (rc == sc->pf) {
5192 		sc->flags |= MASTER_PF;
5193 		rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
5194 		    NULL, &already);
5195 		if (rc == ERESTART)
5196 			rc = 0;
5197 		else if (rc != 0)
5198 			goto done;
5199 	} else if (state == DEV_STATE_UNINIT) {
5200 		/*
5201 		 * We didn't get to be the master so we definitely won't be
5202 		 * configuring the chip.  It's a bug if someone else hasn't
5203 		 * configured it already.
5204 		 */
5205 		device_printf(sc->dev, "couldn't be master(%d), "
5206 		    "device not already initialized either(%d).  "
5207 		    "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
5208 		rc = EPROTO;
5209 		goto done;
5210 	} else {
5211 		/*
5212 		 * Some other PF is the master and has configured the chip.
5213 		 * This is allowed but untested.
5214 		 */
5215 		device_printf(sc->dev, "PF%d is master, device state %d.  "
5216 		    "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
5217 		snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
5218 		sc->cfcsum = 0;
5219 		rc = 0;
5220 	}
5221 done:
5222 	if (rc != 0 && sc->flags & FW_OK) {
5223 		t4_fw_bye(sc, sc->mbox);
5224 		sc->flags &= ~FW_OK;
5225 	}
5226 	free(card_fw, M_CXGBE);
5227 	return (rc);
5228 }
5229 
5230 static int
5231 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
5232     uint32_t mtype, uint32_t moff, u_int maxlen)
5233 {
5234 	struct fw_info *fw_info;
5235 	const struct firmware *dcfg, *rcfg = NULL;
5236 	const uint32_t *cfdata;
5237 	uint32_t cflen, addr;
5238 	int rc;
5239 
5240 	load_fw_module(sc, &dcfg, NULL);
5241 
5242 	/* Card specific interpretation of "default". */
5243 	if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
5244 		if (pci_get_device(sc->dev) == 0x440a)
5245 			snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
5246 		if (is_fpga(sc))
5247 			snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
5248 	}
5249 
5250 	if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
5251 		if (dcfg == NULL) {
5252 			device_printf(sc->dev,
5253 			    "KLD with default config is not available.\n");
5254 			rc = ENOENT;
5255 			goto done;
5256 		}
5257 		cfdata = dcfg->data;
5258 		cflen = dcfg->datasize & ~3;
5259 	} else {
5260 		char s[32];
5261 
5262 		fw_info = find_fw_info(chip_id(sc));
5263 		if (fw_info == NULL) {
5264 			device_printf(sc->dev,
5265 			    "unable to look up firmware information for chip %d.\n",
5266 			    chip_id(sc));
5267 			rc = EINVAL;
5268 			goto done;
5269 		}
5270 		snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
5271 
5272 		rcfg = firmware_get(s);
5273 		if (rcfg == NULL) {
5274 			device_printf(sc->dev,
5275 			    "unable to load module \"%s\" for configuration "
5276 			    "profile \"%s\".\n", s, cfg_file);
5277 			rc = ENOENT;
5278 			goto done;
5279 		}
5280 		cfdata = rcfg->data;
5281 		cflen = rcfg->datasize & ~3;
5282 	}
5283 
5284 	if (cflen > maxlen) {
5285 		device_printf(sc->dev,
5286 		    "config file too long (%d, max allowed is %d).\n",
5287 		    cflen, maxlen);
5288 		rc = EINVAL;
5289 		goto done;
5290 	}
5291 
5292 	rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
5293 	if (rc != 0) {
5294 		device_printf(sc->dev,
5295 		    "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
5296 		    __func__, mtype, moff, cflen, rc);
5297 		rc = EINVAL;
5298 		goto done;
5299 	}
5300 	write_via_memwin(sc, 2, addr, cfdata, cflen);
5301 done:
5302 	if (rcfg != NULL)
5303 		firmware_put(rcfg, FIRMWARE_UNLOAD);
5304 	unload_fw_module(sc, dcfg, NULL);
5305 	return (rc);
5306 }
5307 
5308 struct caps_allowed {
5309 	uint16_t nbmcaps;
5310 	uint16_t linkcaps;
5311 	uint16_t switchcaps;
5312 	uint16_t nvmecaps;
5313 	uint16_t niccaps;
5314 	uint16_t toecaps;
5315 	uint16_t rdmacaps;
5316 	uint16_t cryptocaps;
5317 	uint16_t iscsicaps;
5318 	uint16_t fcoecaps;
5319 };
5320 
5321 #define FW_PARAM_DEV(param) \
5322 	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5323 	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5324 #define FW_PARAM_PFVF(param) \
5325 	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5326 	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
5327 
5328 /*
5329  * Provide a configuration profile to the firmware and have it initialize the
5330  * chip accordingly.  This may involve uploading a configuration file to the
5331  * card.
5332  */
5333 static int
5334 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
5335     const struct caps_allowed *caps_allowed)
5336 {
5337 	int rc;
5338 	struct fw_caps_config_cmd caps;
5339 	uint32_t mtype, moff, finicsum, cfcsum, param, val;
5340 	unsigned int maxlen = 0;
5341 	const int cfg_addr = t4_flash_cfg_addr(sc, &maxlen);
5342 
5343 	rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
5344 	if (rc != 0) {
5345 		device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
5346 		return (rc);
5347 	}
5348 
5349 	bzero(&caps, sizeof(caps));
5350 	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5351 	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
5352 	if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
5353 		mtype = 0;
5354 		moff = 0;
5355 		caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5356 	} else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
5357 		mtype = FW_MEMTYPE_FLASH;
5358 		moff = cfg_addr;
5359 		caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
5360 		    V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5361 		    V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
5362 		    FW_LEN16(caps));
5363 	} else {
5364 		/*
5365 		 * Ask the firmware where it wants us to upload the config file.
5366 		 */
5367 		param = FW_PARAM_DEV(CF);
5368 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5369 		if (rc != 0) {
5370 			/* No support for config file?  Shouldn't happen. */
5371 			device_printf(sc->dev,
5372 			    "failed to query config file location: %d.\n", rc);
5373 			goto done;
5374 		}
5375 		mtype = G_FW_PARAMS_PARAM_Y(val);
5376 		moff = G_FW_PARAMS_PARAM_Z(val) << 16;
5377 		caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
5378 		    V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5379 		    V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
5380 		    FW_LEN16(caps));
5381 
5382 		rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff, maxlen);
5383 		if (rc != 0) {
5384 			device_printf(sc->dev,
5385 			    "failed to upload config file to card: %d.\n", rc);
5386 			goto done;
5387 		}
5388 	}
5389 	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
5390 	if (rc != 0) {
5391 		device_printf(sc->dev, "failed to pre-process config file: %d "
5392 		    "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
5393 		goto done;
5394 	}
5395 
5396 	finicsum = be32toh(caps.finicsum);
5397 	cfcsum = be32toh(caps.cfcsum);	/* actual */
5398 	if (finicsum != cfcsum) {
5399 		device_printf(sc->dev,
5400 		    "WARNING: config file checksum mismatch: %08x %08x\n",
5401 		    finicsum, cfcsum);
5402 	}
5403 	sc->cfcsum = cfcsum;
5404 	snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
5405 
5406 	/*
5407 	 * Let the firmware know what features will (not) be used so it can tune
5408 	 * things accordingly.
5409 	 */
5410 #define LIMIT_CAPS(x) do { \
5411 	caps.x##caps &= htobe16(caps_allowed->x##caps); \
5412 } while (0)
5413 	LIMIT_CAPS(nbm);
5414 	LIMIT_CAPS(link);
5415 	LIMIT_CAPS(switch);
5416 	LIMIT_CAPS(nvme);
5417 	LIMIT_CAPS(nic);
5418 	LIMIT_CAPS(toe);
5419 	LIMIT_CAPS(rdma);
5420 	LIMIT_CAPS(crypto);
5421 	LIMIT_CAPS(iscsi);
5422 	LIMIT_CAPS(fcoe);
5423 #undef LIMIT_CAPS
5424 	if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
5425 		/*
5426 		 * TOE and hashfilters are mutually exclusive.  It is a config
5427 		 * file or firmware bug if both are reported as available.  Try
5428 		 * to cope with the situation in non-debug builds by disabling
5429 		 * TOE.
5430 		 */
5431 		MPASS(caps.toecaps == 0);
5432 
5433 		caps.toecaps = 0;
5434 		caps.rdmacaps = 0;
5435 		caps.iscsicaps = 0;
5436 		caps.nvmecaps = 0;
5437 	}
5438 
5439 	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5440 	    F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5441 	caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5442 	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
5443 	if (rc != 0) {
5444 		device_printf(sc->dev,
5445 		    "failed to process config file: %d.\n", rc);
5446 		goto done;
5447 	}
5448 
5449 	t4_tweak_chip_settings(sc);
5450 	set_params__pre_init(sc);
5451 
5452 	/* get basic stuff going */
5453 	rc = -t4_fw_initialize(sc, sc->mbox);
5454 	if (rc != 0) {
5455 		device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
5456 		goto done;
5457 	}
5458 done:
5459 	return (rc);
5460 }
5461 
5462 /*
5463  * Partition chip resources for use between various PFs, VFs, etc.
5464  */
5465 static int
5466 partition_resources(struct adapter *sc)
5467 {
5468 	char cfg_file[sizeof(t4_cfg_file)];
5469 	struct caps_allowed caps_allowed;
5470 	int rc;
5471 	bool fallback;
5472 
5473 	/* Only the master driver gets to configure the chip resources. */
5474 	MPASS(sc->flags & MASTER_PF);
5475 
5476 #define COPY_CAPS(x) do { \
5477 	caps_allowed.x##caps = t4_##x##caps_allowed; \
5478 } while (0)
5479 	bzero(&caps_allowed, sizeof(caps_allowed));
5480 	COPY_CAPS(nbm);
5481 	COPY_CAPS(link);
5482 	COPY_CAPS(switch);
5483 	COPY_CAPS(nvme);
5484 	COPY_CAPS(nic);
5485 	COPY_CAPS(toe);
5486 	COPY_CAPS(rdma);
5487 	COPY_CAPS(crypto);
5488 	COPY_CAPS(iscsi);
5489 	COPY_CAPS(fcoe);
5490 	fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
5491 	snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
5492 retry:
5493 	rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
5494 	if (rc != 0 && fallback) {
5495 		dump_devlog(sc);
5496 		device_printf(sc->dev,
5497 		    "failed (%d) to configure card with \"%s\" profile, "
5498 		    "will fall back to a basic configuration and retry.\n",
5499 		    rc, cfg_file);
5500 		snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
5501 		bzero(&caps_allowed, sizeof(caps_allowed));
5502 		COPY_CAPS(switch);
5503 		caps_allowed.niccaps = FW_CAPS_CONFIG_NIC;
5504 		fallback = false;
5505 		goto retry;
5506 	}
5507 #undef COPY_CAPS
5508 	return (rc);
5509 }
5510 
5511 /*
5512  * Retrieve parameters that are needed (or nice to have) very early.
5513  */
5514 static int
5515 get_params__pre_init(struct adapter *sc)
5516 {
5517 	int rc;
5518 	uint32_t param[2], val[2];
5519 
5520 	t4_get_version_info(sc);
5521 
5522 	snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
5523 	    G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
5524 	    G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
5525 	    G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
5526 	    G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
5527 
5528 	snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
5529 	    G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
5530 	    G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
5531 	    G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
5532 	    G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
5533 
5534 	snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
5535 	    G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
5536 	    G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
5537 	    G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
5538 	    G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
5539 
5540 	snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
5541 	    G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
5542 	    G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
5543 	    G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
5544 	    G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
5545 
5546 	param[0] = FW_PARAM_DEV(PORTVEC);
5547 	param[1] = FW_PARAM_DEV(CCLK);
5548 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5549 	if (rc != 0) {
5550 		device_printf(sc->dev,
5551 		    "failed to query parameters (pre_init): %d.\n", rc);
5552 		return (rc);
5553 	}
5554 
5555 	sc->params.portvec = val[0];
5556 	sc->params.nports = bitcount32(val[0]);
5557 	sc->params.vpd.cclk = val[1];
5558 
5559 	/* Read device log parameters. */
5560 	rc = -t4_init_devlog_ncores_params(sc, 1);
5561 	if (rc == 0)
5562 		fixup_devlog_params(sc);
5563 	else {
5564 		device_printf(sc->dev,
5565 		    "failed to get devlog parameters: %d.\n", rc);
5566 		rc = 0;	/* devlog isn't critical for device operation */
5567 	}
5568 
5569 	return (rc);
5570 }
5571 
5572 /*
5573  * Any params that need to be set before FW_INITIALIZE.
5574  */
5575 static int
5576 set_params__pre_init(struct adapter *sc)
5577 {
5578 	int rc = 0;
5579 	uint32_t param, val;
5580 
5581 	if (chip_id(sc) >= CHELSIO_T6) {
5582 		param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
5583 		val = 1;
5584 		rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5585 		/* firmwares < 1.20.1.0 do not have this param. */
5586 		if (rc == FW_EINVAL &&
5587 		    sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) {
5588 			rc = 0;
5589 		}
5590 		if (rc != 0) {
5591 			device_printf(sc->dev,
5592 			    "failed to enable high priority filters :%d.\n",
5593 			    rc);
5594 		}
5595 
5596 		param = FW_PARAM_DEV(PPOD_EDRAM);
5597 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5598 		if (rc == 0 && val == 1) {
5599 			rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param,
5600 			    &val);
5601 			if (rc != 0) {
5602 				device_printf(sc->dev,
5603 				    "failed to set PPOD_EDRAM: %d.\n", rc);
5604 			}
5605 		}
5606 	}
5607 
5608 	/* Enable opaque VIIDs with firmwares that support it. */
5609 	param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
5610 	val = 1;
5611 	rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5612 	if (rc == 0 && val == 1)
5613 		sc->params.viid_smt_extn_support = true;
5614 	else
5615 		sc->params.viid_smt_extn_support = false;
5616 
5617 	return (rc);
5618 }
5619 
5620 /*
5621  * Retrieve various parameters that are of interest to the driver.  The device
5622  * has been initialized by the firmware at this point.
5623  */
5624 static int
5625 get_params__post_init(struct adapter *sc)
5626 {
5627 	int rc;
5628 	uint32_t param[7], val[7];
5629 	struct fw_caps_config_cmd caps;
5630 
5631 	param[0] = FW_PARAM_PFVF(IQFLINT_START);
5632 	param[1] = FW_PARAM_PFVF(EQ_START);
5633 	param[2] = FW_PARAM_PFVF(FILTER_START);
5634 	param[3] = FW_PARAM_PFVF(FILTER_END);
5635 	param[4] = FW_PARAM_PFVF(L2T_START);
5636 	param[5] = FW_PARAM_PFVF(L2T_END);
5637 	param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5638 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5639 	    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
5640 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
5641 	if (rc != 0) {
5642 		device_printf(sc->dev,
5643 		    "failed to query parameters (post_init): %d.\n", rc);
5644 		return (rc);
5645 	}
5646 
5647 	sc->sge.iq_start = val[0];
5648 	sc->sge.eq_start = val[1];
5649 	if ((int)val[3] > (int)val[2]) {
5650 		sc->tids.ftid_base = val[2];
5651 		sc->tids.ftid_end = val[3];
5652 		sc->tids.nftids = val[3] - val[2] + 1;
5653 	}
5654 	sc->vres.l2t.start = val[4];
5655 	sc->vres.l2t.size = val[5] - val[4] + 1;
5656 	/* val[5] is the last hwidx and it must not collide with F_SYNC_WR */
5657 	if (sc->vres.l2t.size > 0)
5658 		MPASS(fls(val[5]) <= S_SYNC_WR);
5659 	sc->params.core_vdd = val[6];
5660 
5661 	param[0] = FW_PARAM_PFVF(IQFLINT_END);
5662 	param[1] = FW_PARAM_PFVF(EQ_END);
5663 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5664 	if (rc != 0) {
5665 		device_printf(sc->dev,
5666 		    "failed to query parameters (post_init2): %d.\n", rc);
5667 		return (rc);
5668 	}
5669 	MPASS((int)val[0] >= sc->sge.iq_start);
5670 	sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1;
5671 	MPASS((int)val[1] >= sc->sge.eq_start);
5672 	sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1;
5673 
5674 	if (chip_id(sc) >= CHELSIO_T6) {
5675 
5676 		sc->tids.tid_base = t4_read_reg(sc,
5677 		    A_LE_DB_ACTIVE_TABLE_START_INDEX);
5678 
5679 		param[0] = FW_PARAM_PFVF(HPFILTER_START);
5680 		param[1] = FW_PARAM_PFVF(HPFILTER_END);
5681 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5682 		if (rc != 0) {
5683 			device_printf(sc->dev,
5684 			   "failed to query hpfilter parameters: %d.\n", rc);
5685 			return (rc);
5686 		}
5687 		if ((int)val[1] > (int)val[0]) {
5688 			sc->tids.hpftid_base = val[0];
5689 			sc->tids.hpftid_end = val[1];
5690 			sc->tids.nhpftids = val[1] - val[0] + 1;
5691 
5692 			/*
5693 			 * These should go off if the layout changes and the
5694 			 * driver needs to catch up.
5695 			 */
5696 			MPASS(sc->tids.hpftid_base == 0);
5697 			MPASS(sc->tids.tid_base == sc->tids.nhpftids);
5698 		}
5699 
5700 		param[0] = FW_PARAM_PFVF(RAWF_START);
5701 		param[1] = FW_PARAM_PFVF(RAWF_END);
5702 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5703 		if (rc != 0) {
5704 			device_printf(sc->dev,
5705 			   "failed to query rawf parameters: %d.\n", rc);
5706 			return (rc);
5707 		}
5708 		if ((int)val[1] > (int)val[0]) {
5709 			sc->rawf_base = val[0];
5710 			sc->nrawf = val[1] - val[0] + 1;
5711 		}
5712 	}
5713 
5714 	if (sc->params.ncores > 1) {
5715 		MPASS(chip_id(sc) >= CHELSIO_T7);
5716 
5717 		param[0] = FW_PARAM_DEV(TID_QID_SEL_MASK);
5718 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5719 		sc->params.tid_qid_sel_mask = rc == 0 ? val[0] : 0;
5720 	}
5721 
5722 	/*
5723 	 * The parameters that follow may not be available on all firmwares.  We
5724 	 * query them individually rather than in a compound query because old
5725 	 * firmwares fail the entire query if an unknown parameter is queried.
5726 	 */
5727 
5728 	/*
5729 	 * MPS buffer group configuration.
5730 	 */
5731 	param[0] = FW_PARAM_DEV(MPSBGMAP);
5732 	val[0] = 0;
5733 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5734 	if (rc == 0)
5735 		sc->params.mps_bg_map = val[0];
5736 	else
5737 		sc->params.mps_bg_map = UINT32_MAX;	/* Not a legal value. */
5738 
5739 	param[0] = FW_PARAM_DEV(TPCHMAP);
5740 	val[0] = 0;
5741 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5742 	if (rc == 0)
5743 		sc->params.tp_ch_map = val[0];
5744 	else
5745 		sc->params.tp_ch_map = UINT32_MAX;	/* Not a legal value. */
5746 
5747 	param[0] = FW_PARAM_DEV(TX_TPCHMAP);
5748 	val[0] = 0;
5749 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5750 	if (rc == 0)
5751 		sc->params.tx_tp_ch_map = val[0];
5752 	else
5753 		sc->params.tx_tp_ch_map = UINT32_MAX;	/* Not a legal value. */
5754 
5755 	/*
5756 	 * Determine whether the firmware supports the filter2 work request.
5757 	 */
5758 	param[0] = FW_PARAM_DEV(FILTER2_WR);
5759 	val[0] = 0;
5760 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5761 	if (rc == 0)
5762 		sc->params.filter2_wr_support = val[0] != 0;
5763 	else
5764 		sc->params.filter2_wr_support = 0;
5765 
5766 	/*
5767 	 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
5768 	 */
5769 	param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5770 	val[0] = 0;
5771 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5772 	if (rc == 0)
5773 		sc->params.ulptx_memwrite_dsgl = val[0] != 0;
5774 	else
5775 		sc->params.ulptx_memwrite_dsgl = false;
5776 
5777 	/* FW_RI_FR_NSMR_TPTE_WR support */
5778 	param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
5779 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5780 	if (rc == 0)
5781 		sc->params.fr_nsmr_tpte_wr_support = val[0] != 0;
5782 	else
5783 		sc->params.fr_nsmr_tpte_wr_support = false;
5784 
5785 	/* Support for 512 SGL entries per FR MR. */
5786 	param[0] = FW_PARAM_DEV(DEV_512SGL_MR);
5787 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5788 	if (rc == 0)
5789 		sc->params.dev_512sgl_mr = val[0] != 0;
5790 	else
5791 		sc->params.dev_512sgl_mr = false;
5792 
5793 	param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
5794 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5795 	if (rc == 0)
5796 		sc->params.max_pkts_per_eth_tx_pkts_wr = val[0];
5797 	else
5798 		sc->params.max_pkts_per_eth_tx_pkts_wr = 15;
5799 
5800 	param[0] = FW_PARAM_DEV(NUM_TM_CLASS);
5801 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5802 	if (rc == 0) {
5803 		MPASS(val[0] > 0 && val[0] < 256);	/* nsched_cls is 8b */
5804 		sc->params.nsched_cls = val[0];
5805 	} else
5806 		sc->params.nsched_cls = sc->chip_params->nsched_cls;
5807 
5808 	/* get capabilites */
5809 	bzero(&caps, sizeof(caps));
5810 	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5811 	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
5812 	caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5813 	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
5814 	if (rc != 0) {
5815 		device_printf(sc->dev,
5816 		    "failed to get card capabilities: %d.\n", rc);
5817 		return (rc);
5818 	}
5819 
5820 #define READ_CAPS(x) do { \
5821 	sc->x = htobe16(caps.x); \
5822 } while (0)
5823 	READ_CAPS(nbmcaps);
5824 	READ_CAPS(linkcaps);
5825 	READ_CAPS(switchcaps);
5826 	READ_CAPS(nvmecaps);
5827 	READ_CAPS(niccaps);
5828 	READ_CAPS(toecaps);
5829 	READ_CAPS(rdmacaps);
5830 	READ_CAPS(cryptocaps);
5831 	READ_CAPS(iscsicaps);
5832 	READ_CAPS(fcoecaps);
5833 
5834 	if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
5835 		MPASS(chip_id(sc) > CHELSIO_T4);
5836 		MPASS(sc->toecaps == 0);
5837 		sc->toecaps = 0;
5838 
5839 		param[0] = FW_PARAM_DEV(NTID);
5840 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5841 		if (rc != 0) {
5842 			device_printf(sc->dev,
5843 			    "failed to query HASHFILTER parameters: %d.\n", rc);
5844 			return (rc);
5845 		}
5846 		sc->tids.ntids = val[0];
5847 		if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5848 			MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5849 			sc->tids.ntids -= sc->tids.nhpftids;
5850 		}
5851 		sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5852 		sc->params.hash_filter = 1;
5853 	}
5854 	if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
5855 		param[0] = FW_PARAM_PFVF(ETHOFLD_START);
5856 		param[1] = FW_PARAM_PFVF(ETHOFLD_END);
5857 		param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5858 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
5859 		if (rc != 0) {
5860 			device_printf(sc->dev,
5861 			    "failed to query NIC parameters: %d.\n", rc);
5862 			return (rc);
5863 		}
5864 		if ((int)val[1] > (int)val[0]) {
5865 			sc->tids.etid_base = val[0];
5866 			sc->tids.etid_end = val[1];
5867 			sc->tids.netids = val[1] - val[0] + 1;
5868 			sc->params.eo_wr_cred = val[2];
5869 			sc->params.ethoffload = 1;
5870 		}
5871 	}
5872 	if (sc->toecaps) {
5873 		/* query offload-related parameters */
5874 		param[0] = FW_PARAM_DEV(NTID);
5875 		param[1] = FW_PARAM_PFVF(SERVER_START);
5876 		param[2] = FW_PARAM_PFVF(SERVER_END);
5877 		param[3] = FW_PARAM_PFVF(TDDP_START);
5878 		param[4] = FW_PARAM_PFVF(TDDP_END);
5879 		param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5880 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5881 		if (rc != 0) {
5882 			device_printf(sc->dev,
5883 			    "failed to query TOE parameters: %d.\n", rc);
5884 			return (rc);
5885 		}
5886 		sc->tids.ntids = val[0];
5887 		if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5888 			MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5889 			sc->tids.ntids -= sc->tids.nhpftids;
5890 		}
5891 		sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5892 		if ((int)val[2] > (int)val[1]) {
5893 			sc->tids.stid_base = val[1];
5894 			sc->tids.nstids = val[2] - val[1] + 1;
5895 		}
5896 		sc->vres.ddp.start = val[3];
5897 		sc->vres.ddp.size = val[4] - val[3] + 1;
5898 		sc->params.ofldq_wr_cred = val[5];
5899 		sc->params.offload = 1;
5900 	} else {
5901 		/*
5902 		 * The firmware attempts memfree TOE configuration for -SO cards
5903 		 * and will report toecaps=0 if it runs out of resources (this
5904 		 * depends on the config file).  It may not report 0 for other
5905 		 * capabilities dependent on the TOE in this case.  Set them to
5906 		 * 0 here so that the driver doesn't bother tracking resources
5907 		 * that will never be used.
5908 		 */
5909 		sc->iscsicaps = 0;
5910 		sc->nvmecaps = 0;
5911 		sc->rdmacaps = 0;
5912 	}
5913 	if (sc->nvmecaps || sc->rdmacaps) {
5914 		param[0] = FW_PARAM_PFVF(STAG_START);
5915 		param[1] = FW_PARAM_PFVF(STAG_END);
5916 		param[2] = FW_PARAM_PFVF(PBL_START);
5917 		param[3] = FW_PARAM_PFVF(PBL_END);
5918 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
5919 		if (rc != 0) {
5920 			device_printf(sc->dev,
5921 			    "failed to query NVMe/RDMA parameters: %d.\n", rc);
5922 			return (rc);
5923 		}
5924 		sc->vres.stag.start = val[0];
5925 		sc->vres.stag.size = val[1] - val[0] + 1;
5926 		sc->vres.pbl.start = val[2];
5927 		sc->vres.pbl.size = val[3] - val[2] + 1;
5928 	}
5929 	if (sc->rdmacaps) {
5930 		param[0] = FW_PARAM_PFVF(RQ_START);
5931 		param[1] = FW_PARAM_PFVF(RQ_END);
5932 		param[2] = FW_PARAM_PFVF(SQRQ_START);
5933 		param[3] = FW_PARAM_PFVF(SQRQ_END);
5934 		param[4] = FW_PARAM_PFVF(CQ_START);
5935 		param[5] = FW_PARAM_PFVF(CQ_END);
5936 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5937 		if (rc != 0) {
5938 			device_printf(sc->dev,
5939 			    "failed to query RDMA parameters(1): %d.\n", rc);
5940 			return (rc);
5941 		}
5942 		sc->vres.rq.start = val[0];
5943 		sc->vres.rq.size = val[1] - val[0] + 1;
5944 		sc->vres.qp.start = val[2];
5945 		sc->vres.qp.size = val[3] - val[2] + 1;
5946 		sc->vres.cq.start = val[4];
5947 		sc->vres.cq.size = val[5] - val[4] + 1;
5948 
5949 		param[0] = FW_PARAM_PFVF(OCQ_START);
5950 		param[1] = FW_PARAM_PFVF(OCQ_END);
5951 		param[2] = FW_PARAM_PFVF(SRQ_START);
5952 		param[3] = FW_PARAM_PFVF(SRQ_END);
5953 		param[4] = FW_PARAM_DEV(MAXORDIRD_QP);
5954 		param[5] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5955 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5956 		if (rc != 0) {
5957 			device_printf(sc->dev,
5958 			    "failed to query RDMA parameters(2): %d.\n", rc);
5959 			return (rc);
5960 		}
5961 		sc->vres.ocq.start = val[0];
5962 		sc->vres.ocq.size = val[1] - val[0] + 1;
5963 		sc->vres.srq.start = val[2];
5964 		sc->vres.srq.size = val[3] - val[2] + 1;
5965 		sc->params.max_ordird_qp = val[4];
5966 		sc->params.max_ird_adapter = val[5];
5967 	}
5968 	if (sc->iscsicaps) {
5969 		param[0] = FW_PARAM_PFVF(ISCSI_START);
5970 		param[1] = FW_PARAM_PFVF(ISCSI_END);
5971 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5972 		if (rc != 0) {
5973 			device_printf(sc->dev,
5974 			    "failed to query iSCSI parameters: %d.\n", rc);
5975 			return (rc);
5976 		}
5977 		sc->vres.iscsi.start = val[0];
5978 		sc->vres.iscsi.size = val[1] - val[0] + 1;
5979 	}
5980 	if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
5981 		param[0] = FW_PARAM_PFVF(TLS_START);
5982 		param[1] = FW_PARAM_PFVF(TLS_END);
5983 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5984 		if (rc != 0) {
5985 			device_printf(sc->dev,
5986 			    "failed to query TLS parameters: %d.\n", rc);
5987 			return (rc);
5988 		}
5989 		sc->vres.key.start = val[0];
5990 		sc->vres.key.size = val[1] - val[0] + 1;
5991 	}
5992 
5993 	/*
5994 	 * We've got the params we wanted to query directly from the firmware.
5995 	 * Grab some others via other means.
5996 	 */
5997 	t4_init_sge_params(sc);
5998 	t4_init_tp_params(sc);
5999 	t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
6000 	t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
6001 
6002 	rc = t4_verify_chip_settings(sc);
6003 	if (rc != 0)
6004 		return (rc);
6005 	t4_init_rx_buf_info(sc);
6006 
6007 	return (rc);
6008 }
6009 
6010 #ifdef KERN_TLS
6011 static void
6012 ktls_tick(void *arg)
6013 {
6014 	struct adapter *sc;
6015 	uint32_t tstamp;
6016 
6017 	sc = arg;
6018 	tstamp = tcp_ts_getticks();
6019 	t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1);
6020 	t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31);
6021 	callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK);
6022 }
6023 
6024 static int
6025 t6_config_kern_tls(struct adapter *sc, bool enable)
6026 {
6027 	int rc;
6028 	uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6029 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) |
6030 	    V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) |
6031 	    V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE);
6032 
6033 	rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &param);
6034 	if (rc != 0) {
6035 		CH_ERR(sc, "failed to %s NIC TLS: %d\n",
6036 		    enable ?  "enable" : "disable", rc);
6037 		return (rc);
6038 	}
6039 
6040 	if (enable) {
6041 		sc->flags |= KERN_TLS_ON;
6042 		callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc,
6043 		    C_HARDCLOCK);
6044 	} else {
6045 		sc->flags &= ~KERN_TLS_ON;
6046 		callout_stop(&sc->ktls_tick);
6047 	}
6048 
6049 	return (rc);
6050 }
6051 #endif
6052 
6053 static int
6054 set_params__post_init(struct adapter *sc)
6055 {
6056 	uint32_t mask, param, val;
6057 #ifdef TCP_OFFLOAD
6058 	int i, v, shift;
6059 #endif
6060 
6061 	/* ask for encapsulated CPLs */
6062 	param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
6063 	val = 1;
6064 	(void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
6065 
6066 	/* Enable 32b port caps if the firmware supports it. */
6067 	param = FW_PARAM_PFVF(PORT_CAPS32);
6068 	val = 1;
6069 	if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val) == 0)
6070 		sc->params.port_caps32 = 1;
6071 
6072 	/* Let filter + maskhash steer to a part of the VI's RSS region. */
6073 	val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
6074 	t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
6075 	    V_MASKFILTER(val - 1));
6076 
6077 	mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER |
6078 	    F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN |
6079 	    F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
6080 	    F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM;
6081 	val = 0;
6082 	if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) {
6083 		t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE,
6084 		    F_ATTACKFILTERENABLE);
6085 		val |= F_DROPERRORATTACK;
6086 	}
6087 	if (t4_drop_ip_fragments != 0) {
6088 		t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP,
6089 		    F_FRAGMENTDROP);
6090 		val |= F_DROPERRORFRAG;
6091 	}
6092 	if (t4_drop_pkts_with_l2_errors != 0)
6093 		val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN;
6094 	if (t4_drop_pkts_with_l3_errors != 0) {
6095 		val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN |
6096 		    F_DROPERRORCSUMIP;
6097 	}
6098 	if (t4_drop_pkts_with_l4_errors != 0) {
6099 		val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
6100 		    F_DROPERRORTCPOPT | F_DROPERRORCSUM;
6101 	}
6102 	t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val);
6103 
6104 #ifdef TCP_OFFLOAD
6105 	/*
6106 	 * Override the TOE timers with user provided tunables.  This is not the
6107 	 * recommended way to change the timers (the firmware config file is) so
6108 	 * these tunables are not documented.
6109 	 *
6110 	 * All the timer tunables are in microseconds.
6111 	 */
6112 	if (t4_toe_keepalive_idle != 0) {
6113 		v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
6114 		v &= M_KEEPALIVEIDLE;
6115 		t4_set_reg_field(sc, A_TP_KEEP_IDLE,
6116 		    V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
6117 	}
6118 	if (t4_toe_keepalive_interval != 0) {
6119 		v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
6120 		v &= M_KEEPALIVEINTVL;
6121 		t4_set_reg_field(sc, A_TP_KEEP_INTVL,
6122 		    V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
6123 	}
6124 	if (t4_toe_keepalive_count != 0) {
6125 		v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
6126 		t4_set_reg_field(sc, A_TP_SHIFT_CNT,
6127 		    V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
6128 		    V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
6129 		    V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
6130 	}
6131 	if (t4_toe_rexmt_min != 0) {
6132 		v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
6133 		v &= M_RXTMIN;
6134 		t4_set_reg_field(sc, A_TP_RXT_MIN,
6135 		    V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
6136 	}
6137 	if (t4_toe_rexmt_max != 0) {
6138 		v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
6139 		v &= M_RXTMAX;
6140 		t4_set_reg_field(sc, A_TP_RXT_MAX,
6141 		    V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
6142 	}
6143 	if (t4_toe_rexmt_count != 0) {
6144 		v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
6145 		t4_set_reg_field(sc, A_TP_SHIFT_CNT,
6146 		    V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
6147 		    V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
6148 		    V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
6149 	}
6150 	for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
6151 		if (t4_toe_rexmt_backoff[i] != -1) {
6152 			v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
6153 			shift = (i & 3) << 3;
6154 			t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
6155 			    M_TIMERBACKOFFINDEX0 << shift, v << shift);
6156 		}
6157 	}
6158 #endif
6159 
6160 	/*
6161 	 * Limit TOE connections to 2 reassembly "islands".  This is
6162 	 * required to permit migrating TOE connections to either
6163 	 * ULP_MODE_TCPDDP or UPL_MODE_TLS.
6164 	 */
6165 	t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, V_PASSMODE(M_PASSMODE),
6166 	    V_PASSMODE(2));
6167 
6168 #ifdef KERN_TLS
6169 	if (is_ktls(sc)) {
6170 		sc->tlst.inline_keys = t4_tls_inline_keys;
6171 		if (t4_kern_tls != 0 && is_t6(sc)) {
6172 			sc->tlst.combo_wrs = t4_tls_combo_wrs;
6173 			t6_config_kern_tls(sc, true);
6174 		} else {
6175 			sc->tlst.short_records = t4_tls_short_records;
6176 			sc->tlst.partial_ghash = t4_tls_partial_ghash;
6177 		}
6178 	}
6179 #endif
6180 	return (0);
6181 }
6182 
6183 #undef FW_PARAM_PFVF
6184 #undef FW_PARAM_DEV
6185 
6186 static void
6187 t4_set_desc(struct adapter *sc)
6188 {
6189 	struct adapter_params *p = &sc->params;
6190 
6191 	device_set_descf(sc->dev, "Chelsio %s", p->vpd.id);
6192 }
6193 
6194 static inline void
6195 ifmedia_add4(struct ifmedia *ifm, int m)
6196 {
6197 
6198 	ifmedia_add(ifm, m, 0, NULL);
6199 	ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
6200 	ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
6201 	ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
6202 }
6203 
6204 /*
6205  * This is the selected media, which is not quite the same as the active media.
6206  * The media line in ifconfig is "media: Ethernet selected (active)" if selected
6207  * and active are not the same, and "media: Ethernet selected" otherwise.
6208  */
6209 static void
6210 set_current_media(struct port_info *pi)
6211 {
6212 	struct link_config *lc;
6213 	struct ifmedia *ifm;
6214 	int mword;
6215 	u_int speed;
6216 
6217 	PORT_LOCK_ASSERT_OWNED(pi);
6218 
6219 	/* Leave current media alone if it's already set to IFM_NONE. */
6220 	ifm = &pi->media;
6221 	if (ifm->ifm_cur != NULL &&
6222 	    IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
6223 		return;
6224 
6225 	lc = &pi->link_cfg;
6226 	if (lc->requested_aneg != AUTONEG_DISABLE &&
6227 	    lc->pcaps & FW_PORT_CAP32_ANEG) {
6228 		ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
6229 		return;
6230 	}
6231 	mword = IFM_ETHER | IFM_FDX;
6232 	if (lc->requested_fc & PAUSE_TX)
6233 		mword |= IFM_ETH_TXPAUSE;
6234 	if (lc->requested_fc & PAUSE_RX)
6235 		mword |= IFM_ETH_RXPAUSE;
6236 	if (lc->requested_speed == 0)
6237 		speed = port_top_speed(pi) * 1000;	/* Gbps -> Mbps */
6238 	else
6239 		speed = lc->requested_speed;
6240 	mword |= port_mword(pi, speed_to_fwcap(speed));
6241 	ifmedia_set(ifm, mword);
6242 }
6243 
6244 /*
6245  * Returns true if the ifmedia list for the port cannot change.
6246  */
6247 static bool
6248 fixed_ifmedia(struct port_info *pi)
6249 {
6250 
6251 	return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
6252 	    pi->port_type == FW_PORT_TYPE_BT_XFI ||
6253 	    pi->port_type == FW_PORT_TYPE_BT_XAUI ||
6254 	    pi->port_type == FW_PORT_TYPE_KX4 ||
6255 	    pi->port_type == FW_PORT_TYPE_KX ||
6256 	    pi->port_type == FW_PORT_TYPE_KR ||
6257 	    pi->port_type == FW_PORT_TYPE_BP_AP ||
6258 	    pi->port_type == FW_PORT_TYPE_BP4_AP ||
6259 	    pi->port_type == FW_PORT_TYPE_BP40_BA ||
6260 	    pi->port_type == FW_PORT_TYPE_KR4_100G ||
6261 	    pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
6262 	    pi->port_type == FW_PORT_TYPE_KR_XLAUI);
6263 }
6264 
6265 static void
6266 build_medialist(struct port_info *pi)
6267 {
6268 	uint32_t ss, speed;
6269 	int unknown, mword, bit;
6270 	struct link_config *lc;
6271 	struct ifmedia *ifm;
6272 
6273 	PORT_LOCK_ASSERT_OWNED(pi);
6274 
6275 	if (pi->flags & FIXED_IFMEDIA)
6276 		return;
6277 
6278 	/*
6279 	 * Rebuild the ifmedia list.
6280 	 */
6281 	ifm = &pi->media;
6282 	ifmedia_removeall(ifm);
6283 	lc = &pi->link_cfg;
6284 	ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */
6285 	if (__predict_false(ss == 0)) {	/* not supposed to happen. */
6286 		MPASS(ss != 0);
6287 no_media:
6288 		MPASS(LIST_EMPTY(&ifm->ifm_list));
6289 		ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
6290 		ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
6291 		return;
6292 	}
6293 
6294 	unknown = 0;
6295 	for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
6296 		speed = 1 << bit;
6297 		MPASS(speed & M_FW_PORT_CAP32_SPEED);
6298 		if (ss & speed) {
6299 			mword = port_mword(pi, speed);
6300 			if (mword == IFM_NONE) {
6301 				goto no_media;
6302 			} else if (mword == IFM_UNKNOWN)
6303 				unknown++;
6304 			else
6305 				ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
6306 		}
6307 	}
6308 	if (unknown > 0) /* Add one unknown for all unknown media types. */
6309 		ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
6310 	if (lc->pcaps & FW_PORT_CAP32_ANEG)
6311 		ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
6312 
6313 	set_current_media(pi);
6314 }
6315 
6316 /*
6317  * Initialize the requested fields in the link config based on driver tunables.
6318  */
6319 static void
6320 init_link_config(struct port_info *pi)
6321 {
6322 	struct link_config *lc = &pi->link_cfg;
6323 
6324 	PORT_LOCK_ASSERT_OWNED(pi);
6325 
6326 	lc->requested_caps = 0;
6327 	lc->requested_speed = 0;
6328 
6329 	if (t4_autoneg == 0)
6330 		lc->requested_aneg = AUTONEG_DISABLE;
6331 	else if (t4_autoneg == 1)
6332 		lc->requested_aneg = AUTONEG_ENABLE;
6333 	else
6334 		lc->requested_aneg = AUTONEG_AUTO;
6335 
6336 	lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
6337 	    PAUSE_AUTONEG);
6338 
6339 	if (t4_fec & FEC_AUTO)
6340 		lc->requested_fec = FEC_AUTO;
6341 	else if (t4_fec == 0)
6342 		lc->requested_fec = FEC_NONE;
6343 	else {
6344 		/* -1 is handled by the FEC_AUTO block above and not here. */
6345 		lc->requested_fec = t4_fec &
6346 		    (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE);
6347 		if (lc->requested_fec == 0)
6348 			lc->requested_fec = FEC_AUTO;
6349 	}
6350 	if (t4_force_fec < 0)
6351 		lc->force_fec = -1;
6352 	else if (t4_force_fec > 0)
6353 		lc->force_fec = 1;
6354 	else
6355 		lc->force_fec = 0;
6356 }
6357 
6358 /*
6359  * Makes sure that all requested settings comply with what's supported by the
6360  * port.  Returns the number of settings that were invalid and had to be fixed.
6361  */
6362 static int
6363 fixup_link_config(struct port_info *pi)
6364 {
6365 	int n = 0;
6366 	struct link_config *lc = &pi->link_cfg;
6367 	uint32_t fwspeed;
6368 
6369 	PORT_LOCK_ASSERT_OWNED(pi);
6370 
6371 	/* Speed (when not autonegotiating) */
6372 	if (lc->requested_speed != 0) {
6373 		fwspeed = speed_to_fwcap(lc->requested_speed);
6374 		if ((fwspeed & lc->pcaps) == 0) {
6375 			n++;
6376 			lc->requested_speed = 0;
6377 		}
6378 	}
6379 
6380 	/* Link autonegotiation */
6381 	MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
6382 	    lc->requested_aneg == AUTONEG_DISABLE ||
6383 	    lc->requested_aneg == AUTONEG_AUTO);
6384 	if (lc->requested_aneg == AUTONEG_ENABLE &&
6385 	    !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
6386 		n++;
6387 		lc->requested_aneg = AUTONEG_AUTO;
6388 	}
6389 
6390 	/* Flow control */
6391 	MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
6392 	if (lc->requested_fc & PAUSE_TX &&
6393 	    !(lc->pcaps & FW_PORT_CAP32_FC_TX)) {
6394 		n++;
6395 		lc->requested_fc &= ~PAUSE_TX;
6396 	}
6397 	if (lc->requested_fc & PAUSE_RX &&
6398 	    !(lc->pcaps & FW_PORT_CAP32_FC_RX)) {
6399 		n++;
6400 		lc->requested_fc &= ~PAUSE_RX;
6401 	}
6402 	if (!(lc->requested_fc & PAUSE_AUTONEG) &&
6403 	    !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) {
6404 		n++;
6405 		lc->requested_fc |= PAUSE_AUTONEG;
6406 	}
6407 
6408 	/* FEC */
6409 	if ((lc->requested_fec & FEC_RS &&
6410 	    !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) ||
6411 	    (lc->requested_fec & FEC_BASER_RS &&
6412 	    !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) {
6413 		n++;
6414 		lc->requested_fec = FEC_AUTO;
6415 	}
6416 
6417 	return (n);
6418 }
6419 
6420 /*
6421  * Apply the requested L1 settings, which are expected to be valid, to the
6422  * hardware.
6423  */
6424 static int
6425 apply_link_config(struct port_info *pi)
6426 {
6427 	struct adapter *sc = pi->adapter;
6428 	struct link_config *lc = &pi->link_cfg;
6429 	int rc;
6430 
6431 #ifdef INVARIANTS
6432 	ASSERT_SYNCHRONIZED_OP(sc);
6433 	PORT_LOCK_ASSERT_OWNED(pi);
6434 
6435 	if (lc->requested_aneg == AUTONEG_ENABLE)
6436 		MPASS(lc->pcaps & FW_PORT_CAP32_ANEG);
6437 	if (!(lc->requested_fc & PAUSE_AUTONEG))
6438 		MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE);
6439 	if (lc->requested_fc & PAUSE_TX)
6440 		MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX);
6441 	if (lc->requested_fc & PAUSE_RX)
6442 		MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX);
6443 	if (lc->requested_fec & FEC_RS)
6444 		MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS);
6445 	if (lc->requested_fec & FEC_BASER_RS)
6446 		MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS);
6447 #endif
6448 	if (!(sc->flags & IS_VF)) {
6449 		rc = -t4_link_l1cfg(sc, sc->mbox, pi->hw_port, lc);
6450 		if (rc != 0) {
6451 			device_printf(pi->dev, "l1cfg failed: %d\n", rc);
6452 			return (rc);
6453 		}
6454 	}
6455 
6456 	/*
6457 	 * An L1_CFG will almost always result in a link-change event if the
6458 	 * link is up, and the driver will refresh the actual fec/fc/etc. when
6459 	 * the notification is processed.  If the link is down then the actual
6460 	 * settings are meaningless.
6461 	 *
6462 	 * This takes care of the case where a change in the L1 settings may not
6463 	 * result in a notification.
6464 	 */
6465 	if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
6466 		lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
6467 
6468 	return (0);
6469 }
6470 
6471 #define FW_MAC_EXACT_CHUNK	7
6472 struct mcaddr_ctx {
6473 	if_t ifp;
6474 	const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
6475 	uint64_t hash;
6476 	int i;
6477 	int del;
6478 	int rc;
6479 };
6480 
6481 static u_int
6482 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
6483 {
6484 	struct mcaddr_ctx *ctx = arg;
6485 	struct vi_info *vi = if_getsoftc(ctx->ifp);
6486 	struct port_info *pi = vi->pi;
6487 	struct adapter *sc = pi->adapter;
6488 
6489 	if (ctx->rc < 0)
6490 		return (0);
6491 
6492 	ctx->mcaddr[ctx->i] = LLADDR(sdl);
6493 	MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i]));
6494 	ctx->i++;
6495 
6496 	if (ctx->i == FW_MAC_EXACT_CHUNK) {
6497 		ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del,
6498 		    ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0);
6499 		if (ctx->rc < 0) {
6500 			int j;
6501 
6502 			for (j = 0; j < ctx->i; j++) {
6503 				if_printf(ctx->ifp,
6504 				    "failed to add mc address"
6505 				    " %02x:%02x:%02x:"
6506 				    "%02x:%02x:%02x rc=%d\n",
6507 				    ctx->mcaddr[j][0], ctx->mcaddr[j][1],
6508 				    ctx->mcaddr[j][2], ctx->mcaddr[j][3],
6509 				    ctx->mcaddr[j][4], ctx->mcaddr[j][5],
6510 				    -ctx->rc);
6511 			}
6512 			return (0);
6513 		}
6514 		ctx->del = 0;
6515 		ctx->i = 0;
6516 	}
6517 
6518 	return (1);
6519 }
6520 
6521 /*
6522  * Program the port's XGMAC based on parameters in ifnet.  The caller also
6523  * indicates which parameters should be programmed (the rest are left alone).
6524  */
6525 int
6526 update_mac_settings(if_t ifp, int flags)
6527 {
6528 	int rc = 0;
6529 	struct vi_info *vi = if_getsoftc(ifp);
6530 	struct port_info *pi = vi->pi;
6531 	struct adapter *sc = pi->adapter;
6532 	int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
6533 	uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
6534 
6535 	ASSERT_SYNCHRONIZED_OP(sc);
6536 	KASSERT(flags, ("%s: not told what to update.", __func__));
6537 
6538 	if (flags & XGMAC_MTU)
6539 		mtu = if_getmtu(ifp);
6540 
6541 	if (flags & XGMAC_PROMISC)
6542 		promisc = if_getflags(ifp) & IFF_PROMISC ? 1 : 0;
6543 
6544 	if (flags & XGMAC_ALLMULTI)
6545 		allmulti = if_getflags(ifp) & IFF_ALLMULTI ? 1 : 0;
6546 
6547 	if (flags & XGMAC_VLANEX)
6548 		vlanex = if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING ? 1 : 0;
6549 
6550 	if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
6551 		rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
6552 		    allmulti, 1, vlanex, false);
6553 		if (rc) {
6554 			if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
6555 			    rc);
6556 			return (rc);
6557 		}
6558 	}
6559 
6560 	if (flags & XGMAC_UCADDR) {
6561 		uint8_t ucaddr[ETHER_ADDR_LEN];
6562 
6563 		bcopy(if_getlladdr(ifp), ucaddr, sizeof(ucaddr));
6564 		rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
6565 		    ucaddr, true, &vi->smt_idx);
6566 		if (rc < 0) {
6567 			rc = -rc;
6568 			if_printf(ifp, "change_mac failed: %d\n", rc);
6569 			return (rc);
6570 		} else {
6571 			vi->xact_addr_filt = rc;
6572 			rc = 0;
6573 		}
6574 	}
6575 
6576 	if (flags & XGMAC_MCADDRS) {
6577 		struct epoch_tracker et;
6578 		struct mcaddr_ctx ctx;
6579 		int j;
6580 
6581 		ctx.ifp = ifp;
6582 		ctx.hash = 0;
6583 		ctx.i = 0;
6584 		ctx.del = 1;
6585 		ctx.rc = 0;
6586 		/*
6587 		 * Unlike other drivers, we accumulate list of pointers into
6588 		 * interface address lists and we need to keep it safe even
6589 		 * after if_foreach_llmaddr() returns, thus we must enter the
6590 		 * network epoch.
6591 		 */
6592 		NET_EPOCH_ENTER(et);
6593 		if_foreach_llmaddr(ifp, add_maddr, &ctx);
6594 		if (ctx.rc < 0) {
6595 			NET_EPOCH_EXIT(et);
6596 			rc = -ctx.rc;
6597 			return (rc);
6598 		}
6599 		if (ctx.i > 0) {
6600 			rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
6601 			    ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0);
6602 			NET_EPOCH_EXIT(et);
6603 			if (rc < 0) {
6604 				rc = -rc;
6605 				for (j = 0; j < ctx.i; j++) {
6606 					if_printf(ifp,
6607 					    "failed to add mcast address"
6608 					    " %02x:%02x:%02x:"
6609 					    "%02x:%02x:%02x rc=%d\n",
6610 					    ctx.mcaddr[j][0], ctx.mcaddr[j][1],
6611 					    ctx.mcaddr[j][2], ctx.mcaddr[j][3],
6612 					    ctx.mcaddr[j][4], ctx.mcaddr[j][5],
6613 					    rc);
6614 				}
6615 				return (rc);
6616 			}
6617 			ctx.del = 0;
6618 		} else
6619 			NET_EPOCH_EXIT(et);
6620 
6621 		rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0);
6622 		if (rc != 0)
6623 			if_printf(ifp, "failed to set mcast address hash: %d\n",
6624 			    rc);
6625 		if (ctx.del == 0) {
6626 			/* We clobbered the VXLAN entry if there was one. */
6627 			pi->vxlan_tcam_entry = false;
6628 		}
6629 	}
6630 
6631 	if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 &&
6632 	    pi->vxlan_tcam_entry == false) {
6633 		rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac,
6634 		    match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
6635 		    true);
6636 		if (rc < 0) {
6637 			rc = -rc;
6638 			if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n",
6639 			    rc);
6640 		} else {
6641 			MPASS(rc == sc->rawf_base + pi->port_id);
6642 			rc = 0;
6643 			pi->vxlan_tcam_entry = true;
6644 		}
6645 	}
6646 
6647 	return (rc);
6648 }
6649 
6650 /*
6651  * {begin|end}_synchronized_op must be called from the same thread.
6652  */
6653 int
6654 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
6655     char *wmesg)
6656 {
6657 	int rc;
6658 
6659 #ifdef WITNESS
6660 	/* the caller thinks it's ok to sleep, but is it really? */
6661 	if (flags & SLEEP_OK)
6662 		WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, __func__);
6663 #endif
6664 	ADAPTER_LOCK(sc);
6665 	for (;;) {
6666 
6667 		if (vi && IS_DETACHING(vi)) {
6668 			rc = ENXIO;
6669 			goto done;
6670 		}
6671 
6672 		if (!IS_BUSY(sc)) {
6673 			rc = 0;
6674 			break;
6675 		}
6676 
6677 		if (!(flags & SLEEP_OK)) {
6678 			rc = EBUSY;
6679 			goto done;
6680 		}
6681 
6682 		if (mtx_sleep(&sc->flags, &sc->sc_lock,
6683 		    flags & INTR_OK ? PCATCH : 0, wmesg, 0)) {
6684 			rc = EINTR;
6685 			goto done;
6686 		}
6687 	}
6688 
6689 	KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
6690 	SET_BUSY(sc);
6691 #ifdef INVARIANTS
6692 	sc->last_op = wmesg;
6693 	sc->last_op_thr = curthread;
6694 	sc->last_op_flags = flags;
6695 #endif
6696 
6697 done:
6698 	if (!(flags & HOLD_LOCK) || rc)
6699 		ADAPTER_UNLOCK(sc);
6700 
6701 	return (rc);
6702 }
6703 
6704 /*
6705  * Tell if_ioctl and if_init that the VI is going away.  This is
6706  * special variant of begin_synchronized_op and must be paired with a
6707  * call to end_vi_detach.
6708  */
6709 void
6710 begin_vi_detach(struct adapter *sc, struct vi_info *vi)
6711 {
6712 	ADAPTER_LOCK(sc);
6713 	SET_DETACHING(vi);
6714 	wakeup(&sc->flags);
6715 	while (IS_BUSY(sc))
6716 		mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
6717 	SET_BUSY(sc);
6718 #ifdef INVARIANTS
6719 	sc->last_op = "t4detach";
6720 	sc->last_op_thr = curthread;
6721 	sc->last_op_flags = 0;
6722 #endif
6723 	ADAPTER_UNLOCK(sc);
6724 }
6725 
6726 void
6727 end_vi_detach(struct adapter *sc, struct vi_info *vi)
6728 {
6729 	ADAPTER_LOCK(sc);
6730 	KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
6731 	CLR_BUSY(sc);
6732 	CLR_DETACHING(vi);
6733 	wakeup(&sc->flags);
6734 	ADAPTER_UNLOCK(sc);
6735 }
6736 
6737 /*
6738  * {begin|end}_synchronized_op must be called from the same thread.
6739  */
6740 void
6741 end_synchronized_op(struct adapter *sc, int flags)
6742 {
6743 
6744 	if (flags & LOCK_HELD)
6745 		ADAPTER_LOCK_ASSERT_OWNED(sc);
6746 	else
6747 		ADAPTER_LOCK(sc);
6748 
6749 	KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
6750 	CLR_BUSY(sc);
6751 	wakeup(&sc->flags);
6752 	ADAPTER_UNLOCK(sc);
6753 }
6754 
6755 static int
6756 cxgbe_init_synchronized(struct vi_info *vi)
6757 {
6758 	struct port_info *pi = vi->pi;
6759 	struct adapter *sc = pi->adapter;
6760 	if_t ifp = vi->ifp;
6761 	int rc = 0, i;
6762 	struct sge_txq *txq;
6763 
6764 	ASSERT_SYNCHRONIZED_OP(sc);
6765 
6766 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6767 		return (0);	/* already running */
6768 
6769 	if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0))
6770 		return (rc);	/* error message displayed already */
6771 
6772 	if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
6773 		return (rc); /* error message displayed already */
6774 
6775 	rc = update_mac_settings(ifp, XGMAC_ALL);
6776 	if (rc)
6777 		goto done;	/* error message displayed already */
6778 
6779 	PORT_LOCK(pi);
6780 	if (pi->up_vis == 0) {
6781 		t4_update_port_info(pi);
6782 		fixup_link_config(pi);
6783 		build_medialist(pi);
6784 		apply_link_config(pi);
6785 	}
6786 
6787 	rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
6788 	if (rc != 0) {
6789 		if_printf(ifp, "enable_vi failed: %d\n", rc);
6790 		PORT_UNLOCK(pi);
6791 		goto done;
6792 	}
6793 
6794 	/*
6795 	 * Can't fail from this point onwards.  Review cxgbe_uninit_synchronized
6796 	 * if this changes.
6797 	 */
6798 
6799 	for_each_txq(vi, i, txq) {
6800 		TXQ_LOCK(txq);
6801 		txq->eq.flags |= EQ_ENABLED;
6802 		TXQ_UNLOCK(txq);
6803 	}
6804 
6805 	/*
6806 	 * The first iq of the first port to come up is used for tracing.
6807 	 */
6808 	if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
6809 		sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
6810 		t4_set_trace_rss_control(sc, pi->tx_chan, sc->traceq);
6811 		pi->flags |= HAS_TRACEQ;
6812 	}
6813 
6814 	/* all ok */
6815 	pi->up_vis++;
6816 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
6817 	if (pi->link_cfg.link_ok)
6818 		t4_os_link_changed(pi);
6819 	PORT_UNLOCK(pi);
6820 
6821 	mtx_lock(&vi->tick_mtx);
6822 	if (vi->pi->nvi > 1 || sc->flags & IS_VF)
6823 		callout_reset(&vi->tick, hz, vi_tick, vi);
6824 	else
6825 		callout_reset(&vi->tick, hz, cxgbe_tick, vi);
6826 	mtx_unlock(&vi->tick_mtx);
6827 done:
6828 	if (rc != 0)
6829 		cxgbe_uninit_synchronized(vi);
6830 
6831 	return (rc);
6832 }
6833 
6834 /*
6835  * Idempotent.
6836  */
6837 static int
6838 cxgbe_uninit_synchronized(struct vi_info *vi)
6839 {
6840 	struct port_info *pi = vi->pi;
6841 	struct adapter *sc = pi->adapter;
6842 	if_t ifp = vi->ifp;
6843 	int rc, i;
6844 	struct sge_txq *txq;
6845 
6846 	ASSERT_SYNCHRONIZED_OP(sc);
6847 
6848 	if (!(vi->flags & VI_INIT_DONE)) {
6849 		if (__predict_false(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
6850 			KASSERT(0, ("uninited VI is running"));
6851 			if_printf(ifp, "uninited VI with running ifnet.  "
6852 			    "vi->flags 0x%016lx, if_flags 0x%08x, "
6853 			    "if_drv_flags 0x%08x\n", vi->flags, if_getflags(ifp),
6854 			    if_getdrvflags(ifp));
6855 		}
6856 		return (0);
6857 	}
6858 
6859 	/*
6860 	 * Disable the VI so that all its data in either direction is discarded
6861 	 * by the MPS.  Leave everything else (the queues, interrupts, and 1Hz
6862 	 * tick) intact as the TP can deliver negative advice or data that it's
6863 	 * holding in its RAM (for an offloaded connection) even after the VI is
6864 	 * disabled.
6865 	 */
6866 	rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
6867 	if (rc) {
6868 		if_printf(ifp, "disable_vi failed: %d\n", rc);
6869 		return (rc);
6870 	}
6871 
6872 	for_each_txq(vi, i, txq) {
6873 		TXQ_LOCK(txq);
6874 		txq->eq.flags &= ~EQ_ENABLED;
6875 		TXQ_UNLOCK(txq);
6876 	}
6877 
6878 	mtx_lock(&vi->tick_mtx);
6879 	callout_stop(&vi->tick);
6880 	mtx_unlock(&vi->tick_mtx);
6881 
6882 	PORT_LOCK(pi);
6883 	if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
6884 		PORT_UNLOCK(pi);
6885 		return (0);
6886 	}
6887 	if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
6888 	pi->up_vis--;
6889 	if (pi->up_vis > 0) {
6890 		PORT_UNLOCK(pi);
6891 		return (0);
6892 	}
6893 
6894 	pi->link_cfg.link_ok = false;
6895 	pi->link_cfg.speed = 0;
6896 	pi->link_cfg.link_down_rc = 255;
6897 	t4_os_link_changed(pi);
6898 	PORT_UNLOCK(pi);
6899 
6900 	return (0);
6901 }
6902 
6903 /*
6904  * It is ok for this function to fail midway and return right away.  t4_detach
6905  * will walk the entire sc->irq list and clean up whatever is valid.
6906  */
6907 int
6908 t4_setup_intr_handlers(struct adapter *sc)
6909 {
6910 	int rc, rid, p, q, v;
6911 	char s[8];
6912 	struct irq *irq;
6913 	struct port_info *pi;
6914 	struct vi_info *vi;
6915 	struct sge *sge = &sc->sge;
6916 	struct sge_rxq *rxq;
6917 #ifdef TCP_OFFLOAD
6918 	struct sge_ofld_rxq *ofld_rxq;
6919 #endif
6920 #ifdef DEV_NETMAP
6921 	struct sge_nm_rxq *nm_rxq;
6922 #endif
6923 #ifdef RSS
6924 	int nbuckets = rss_getnumbuckets();
6925 #endif
6926 
6927 	/*
6928 	 * Setup interrupts.
6929 	 */
6930 	irq = &sc->irq[0];
6931 	rid = sc->intr_type == INTR_INTX ? 0 : 1;
6932 	if (forwarding_intr_to_fwq(sc))
6933 		return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
6934 
6935 	/* Multiple interrupts. */
6936 	if (sc->flags & IS_VF)
6937 		KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
6938 		    ("%s: too few intr.", __func__));
6939 	else
6940 		KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
6941 		    ("%s: too few intr.", __func__));
6942 
6943 	/* The first one is always error intr on PFs */
6944 	if (!(sc->flags & IS_VF)) {
6945 		rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
6946 		if (rc != 0)
6947 			return (rc);
6948 		irq++;
6949 		rid++;
6950 	}
6951 
6952 	/* The second one is always the firmware event queue (first on VFs) */
6953 	rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
6954 	if (rc != 0)
6955 		return (rc);
6956 	irq++;
6957 	rid++;
6958 
6959 	for_each_port(sc, p) {
6960 		pi = sc->port[p];
6961 		for_each_vi(pi, v, vi) {
6962 			vi->first_intr = rid - 1;
6963 
6964 			if (vi->nnmrxq > 0) {
6965 				int n = max(vi->nrxq, vi->nnmrxq);
6966 
6967 				rxq = &sge->rxq[vi->first_rxq];
6968 #ifdef DEV_NETMAP
6969 				nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
6970 #endif
6971 				for (q = 0; q < n; q++) {
6972 					snprintf(s, sizeof(s), "%x%c%x", p,
6973 					    'a' + v, q);
6974 					if (q < vi->nrxq)
6975 						irq->rxq = rxq++;
6976 #ifdef DEV_NETMAP
6977 					if (q < vi->nnmrxq)
6978 						irq->nm_rxq = nm_rxq++;
6979 
6980 					if (irq->nm_rxq != NULL &&
6981 					    irq->rxq == NULL) {
6982 						/* Netmap rx only */
6983 						rc = t4_alloc_irq(sc, irq, rid,
6984 						    t4_nm_intr, irq->nm_rxq, s);
6985 					}
6986 					if (irq->nm_rxq != NULL &&
6987 					    irq->rxq != NULL) {
6988 						/* NIC and Netmap rx */
6989 						rc = t4_alloc_irq(sc, irq, rid,
6990 						    t4_vi_intr, irq, s);
6991 					}
6992 #endif
6993 					if (irq->rxq != NULL &&
6994 					    irq->nm_rxq == NULL) {
6995 						/* NIC rx only */
6996 						rc = t4_alloc_irq(sc, irq, rid,
6997 						    t4_intr, irq->rxq, s);
6998 					}
6999 					if (rc != 0)
7000 						return (rc);
7001 #ifdef RSS
7002 					if (q < vi->nrxq) {
7003 						bus_bind_intr(sc->dev, irq->res,
7004 						    rss_getcpu(q % nbuckets));
7005 					}
7006 #endif
7007 					irq++;
7008 					rid++;
7009 					vi->nintr++;
7010 				}
7011 			} else {
7012 				for_each_rxq(vi, q, rxq) {
7013 					snprintf(s, sizeof(s), "%x%c%x", p,
7014 					    'a' + v, q);
7015 					rc = t4_alloc_irq(sc, irq, rid,
7016 					    t4_intr, rxq, s);
7017 					if (rc != 0)
7018 						return (rc);
7019 #ifdef RSS
7020 					bus_bind_intr(sc->dev, irq->res,
7021 					    rss_getcpu(q % nbuckets));
7022 #endif
7023 					irq++;
7024 					rid++;
7025 					vi->nintr++;
7026 				}
7027 			}
7028 #ifdef TCP_OFFLOAD
7029 			for_each_ofld_rxq(vi, q, ofld_rxq) {
7030 				snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
7031 				rc = t4_alloc_irq(sc, irq, rid, t4_intr,
7032 				    ofld_rxq, s);
7033 				if (rc != 0)
7034 					return (rc);
7035 				irq++;
7036 				rid++;
7037 				vi->nintr++;
7038 			}
7039 #endif
7040 		}
7041 	}
7042 	MPASS(irq == &sc->irq[sc->intr_count]);
7043 
7044 	return (0);
7045 }
7046 
7047 static void
7048 write_global_rss_key(struct adapter *sc)
7049 {
7050 	int i;
7051 	uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
7052 	uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
7053 
7054 	CTASSERT(RSS_KEYSIZE == 40);
7055 
7056 	rss_getkey((void *)&raw_rss_key[0]);
7057 	for (i = 0; i < nitems(rss_key); i++) {
7058 		rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
7059 	}
7060 	t4_write_rss_key(sc, &rss_key[0], -1, 1);
7061 }
7062 
7063 /*
7064  * Idempotent.
7065  */
7066 static int
7067 adapter_full_init(struct adapter *sc)
7068 {
7069 	int rc, i;
7070 
7071 	ASSERT_SYNCHRONIZED_OP(sc);
7072 
7073 	/*
7074 	 * queues that belong to the adapter (not any particular port).
7075 	 */
7076 	rc = t4_setup_adapter_queues(sc);
7077 	if (rc != 0)
7078 		return (rc);
7079 
7080 	MPASS(sc->params.nports <= nitems(sc->tq));
7081 	for (i = 0; i < sc->params.nports; i++) {
7082 		if (sc->tq[i] != NULL)
7083 			continue;
7084 		sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
7085 		    taskqueue_thread_enqueue, &sc->tq[i]);
7086 		if (sc->tq[i] == NULL) {
7087 			CH_ERR(sc, "failed to allocate task queue %d\n", i);
7088 			return (ENOMEM);
7089 		}
7090 		taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
7091 		    device_get_nameunit(sc->dev), i);
7092 	}
7093 
7094 	if (!(sc->flags & IS_VF)) {
7095 		write_global_rss_key(sc);
7096 		t4_intr_enable(sc);
7097 	}
7098 	return (0);
7099 }
7100 
7101 int
7102 adapter_init(struct adapter *sc)
7103 {
7104 	int rc;
7105 
7106 	ASSERT_SYNCHRONIZED_OP(sc);
7107 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
7108 	KASSERT((sc->flags & FULL_INIT_DONE) == 0,
7109 	    ("%s: FULL_INIT_DONE already", __func__));
7110 
7111 	rc = adapter_full_init(sc);
7112 	if (rc != 0)
7113 		adapter_full_uninit(sc);
7114 	else
7115 		sc->flags |= FULL_INIT_DONE;
7116 
7117 	return (rc);
7118 }
7119 
7120 /*
7121  * Idempotent.
7122  */
7123 static void
7124 adapter_full_uninit(struct adapter *sc)
7125 {
7126 	int i;
7127 
7128 	t4_teardown_adapter_queues(sc);
7129 
7130 	for (i = 0; i < nitems(sc->tq); i++) {
7131 		if (sc->tq[i] == NULL)
7132 			continue;
7133 		taskqueue_free(sc->tq[i]);
7134 		sc->tq[i] = NULL;
7135 	}
7136 
7137 	sc->flags &= ~FULL_INIT_DONE;
7138 }
7139 
7140 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
7141     RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
7142     RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
7143     RSS_HASHTYPE_RSS_UDP_IPV6)
7144 
7145 /* Translates kernel hash types to hardware. */
7146 static int
7147 hashconfig_to_hashen(int hashconfig)
7148 {
7149 	int hashen = 0;
7150 
7151 	if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
7152 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
7153 	if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
7154 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
7155 	if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
7156 		hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
7157 		    F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
7158 	}
7159 	if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
7160 		hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
7161 		    F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
7162 	}
7163 	if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
7164 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
7165 	if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
7166 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
7167 
7168 	return (hashen);
7169 }
7170 
7171 /* Translates hardware hash types to kernel. */
7172 static int
7173 hashen_to_hashconfig(int hashen)
7174 {
7175 	int hashconfig = 0;
7176 
7177 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
7178 		/*
7179 		 * If UDP hashing was enabled it must have been enabled for
7180 		 * either IPv4 or IPv6 (inclusive or).  Enabling UDP without
7181 		 * enabling any 4-tuple hash is nonsense configuration.
7182 		 */
7183 		MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
7184 		    F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
7185 
7186 		if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
7187 			hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
7188 		if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
7189 			hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
7190 	}
7191 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
7192 		hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
7193 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
7194 		hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
7195 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
7196 		hashconfig |= RSS_HASHTYPE_RSS_IPV4;
7197 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
7198 		hashconfig |= RSS_HASHTYPE_RSS_IPV6;
7199 
7200 	return (hashconfig);
7201 }
7202 
7203 /*
7204  * Idempotent.
7205  */
7206 static int
7207 vi_full_init(struct vi_info *vi)
7208 {
7209 	struct adapter *sc = vi->adapter;
7210 	struct sge_rxq *rxq;
7211 	int rc, i, j, extra;
7212 	int hashconfig = rss_gethashconfig();
7213 #ifdef RSS
7214 	int nbuckets = rss_getnumbuckets();
7215 #endif
7216 
7217 	ASSERT_SYNCHRONIZED_OP(sc);
7218 
7219 	/*
7220 	 * Allocate tx/rx/fl queues for this VI.
7221 	 */
7222 	rc = t4_setup_vi_queues(vi);
7223 	if (rc != 0)
7224 		return (rc);
7225 
7226 	/*
7227 	 * Setup RSS for this VI.  Save a copy of the RSS table for later use.
7228 	 */
7229 	if (vi->nrxq > vi->rss_size) {
7230 		CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); "
7231 		    "some queues will never receive traffic.\n", vi->nrxq,
7232 		    vi->rss_size);
7233 	} else if (vi->rss_size % vi->nrxq) {
7234 		CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); "
7235 		    "expect uneven traffic distribution.\n", vi->nrxq,
7236 		    vi->rss_size);
7237 	}
7238 #ifdef RSS
7239 	if (vi->nrxq != nbuckets) {
7240 		CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);"
7241 		    "performance will be impacted.\n", vi->nrxq, nbuckets);
7242 	}
7243 #endif
7244 	if (vi->rss == NULL)
7245 		vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE,
7246 		    M_ZERO | M_WAITOK);
7247 	for (i = 0; i < vi->rss_size;) {
7248 #ifdef RSS
7249 		j = rss_get_indirection_to_bucket(i);
7250 		j %= vi->nrxq;
7251 		rxq = &sc->sge.rxq[vi->first_rxq + j];
7252 		vi->rss[i++] = rxq->iq.abs_id;
7253 #else
7254 		for_each_rxq(vi, j, rxq) {
7255 			vi->rss[i++] = rxq->iq.abs_id;
7256 			if (i == vi->rss_size)
7257 				break;
7258 		}
7259 #endif
7260 	}
7261 
7262 	rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
7263 	    vi->rss, vi->rss_size);
7264 	if (rc != 0) {
7265 		CH_ERR(vi, "rss_config failed: %d\n", rc);
7266 		return (rc);
7267 	}
7268 
7269 	vi->hashen = hashconfig_to_hashen(hashconfig);
7270 
7271 	/*
7272 	 * We may have had to enable some hashes even though the global config
7273 	 * wants them disabled.  This is a potential problem that must be
7274 	 * reported to the user.
7275 	 */
7276 	extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
7277 
7278 	/*
7279 	 * If we consider only the supported hash types, then the enabled hashes
7280 	 * are a superset of the requested hashes.  In other words, there cannot
7281 	 * be any supported hash that was requested but not enabled, but there
7282 	 * can be hashes that were not requested but had to be enabled.
7283 	 */
7284 	extra &= SUPPORTED_RSS_HASHTYPES;
7285 	MPASS((extra & hashconfig) == 0);
7286 
7287 	if (extra) {
7288 		CH_ALERT(vi,
7289 		    "global RSS config (0x%x) cannot be accommodated.\n",
7290 		    hashconfig);
7291 	}
7292 	if (extra & RSS_HASHTYPE_RSS_IPV4)
7293 		CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n");
7294 	if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
7295 		CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n");
7296 	if (extra & RSS_HASHTYPE_RSS_IPV6)
7297 		CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n");
7298 	if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
7299 		CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n");
7300 	if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
7301 		CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n");
7302 	if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
7303 		CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n");
7304 
7305 	rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0],
7306 	    0, 0);
7307 	if (rc != 0) {
7308 		CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc);
7309 		return (rc);
7310 	}
7311 
7312 	return (0);
7313 }
7314 
7315 int
7316 vi_init(struct vi_info *vi)
7317 {
7318 	int rc;
7319 
7320 	ASSERT_SYNCHRONIZED_OP(vi->adapter);
7321 	KASSERT((vi->flags & VI_INIT_DONE) == 0,
7322 	    ("%s: VI_INIT_DONE already", __func__));
7323 
7324 	rc = vi_full_init(vi);
7325 	if (rc != 0)
7326 		vi_full_uninit(vi);
7327 	else
7328 		vi->flags |= VI_INIT_DONE;
7329 
7330 	return (rc);
7331 }
7332 
7333 /*
7334  * Idempotent.
7335  */
7336 static void
7337 vi_full_uninit(struct vi_info *vi)
7338 {
7339 
7340 	if (vi->flags & VI_INIT_DONE) {
7341 		quiesce_vi(vi);
7342 		free(vi->rss, M_CXGBE);
7343 		free(vi->nm_rss, M_CXGBE);
7344 	}
7345 
7346 	t4_teardown_vi_queues(vi);
7347 	vi->flags &= ~VI_INIT_DONE;
7348 }
7349 
7350 static void
7351 quiesce_txq(struct sge_txq *txq)
7352 {
7353 	struct sge_eq *eq = &txq->eq;
7354 	struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
7355 
7356 	MPASS(eq->flags & EQ_SW_ALLOCATED);
7357 	MPASS(!(eq->flags & EQ_ENABLED));
7358 
7359 	/* Wait for the mp_ring to empty. */
7360 	while (!mp_ring_is_idle(txq->r)) {
7361 		mp_ring_check_drainage(txq->r, 4096);
7362 		pause("rquiesce", 1);
7363 	}
7364 	MPASS(txq->txp.npkt == 0);
7365 
7366 	if (eq->flags & EQ_HW_ALLOCATED) {
7367 		/*
7368 		 * Hardware is alive and working normally.  Wait for it to
7369 		 * finish and then wait for the driver to catch up and reclaim
7370 		 * all descriptors.
7371 		 */
7372 		while (spg->cidx != htobe16(eq->pidx))
7373 			pause("equiesce", 1);
7374 		while (eq->cidx != eq->pidx)
7375 			pause("dquiesce", 1);
7376 	} else {
7377 		/*
7378 		 * Hardware is unavailable.  Discard all pending tx and reclaim
7379 		 * descriptors directly.
7380 		 */
7381 		TXQ_LOCK(txq);
7382 		while (eq->cidx != eq->pidx) {
7383 			struct mbuf *m, *nextpkt;
7384 			struct tx_sdesc *txsd;
7385 
7386 			txsd = &txq->sdesc[eq->cidx];
7387 			for (m = txsd->m; m != NULL; m = nextpkt) {
7388 				nextpkt = m->m_nextpkt;
7389 				m->m_nextpkt = NULL;
7390 				m_freem(m);
7391 			}
7392 			IDXINCR(eq->cidx, txsd->desc_used, eq->sidx);
7393 		}
7394 		spg->pidx = spg->cidx = htobe16(eq->cidx);
7395 		TXQ_UNLOCK(txq);
7396 	}
7397 }
7398 
7399 static void
7400 quiesce_wrq(struct sge_wrq *wrq)
7401 {
7402 	struct wrqe *wr;
7403 
7404 	TXQ_LOCK(wrq);
7405 	while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) {
7406 		STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
7407 #ifdef INVARIANTS
7408 		wrq->nwr_pending--;
7409 		wrq->ndesc_needed -= howmany(wr->wr_len, EQ_ESIZE);
7410 #endif
7411 		free(wr, M_CXGBE);
7412 	}
7413 	MPASS(wrq->nwr_pending == 0);
7414 	MPASS(wrq->ndesc_needed == 0);
7415 	wrq->nwr_pending = 0;
7416 	wrq->ndesc_needed = 0;
7417 	TXQ_UNLOCK(wrq);
7418 }
7419 
7420 static void
7421 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
7422 {
7423 	/* Synchronize with the interrupt handler */
7424 	while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
7425 		pause("iqfree", 1);
7426 
7427 	if (fl != NULL) {
7428 		MPASS(iq->flags & IQ_HAS_FL);
7429 
7430 		mtx_lock(&sc->sfl_lock);
7431 		FL_LOCK(fl);
7432 		fl->flags |= FL_DOOMED;
7433 		FL_UNLOCK(fl);
7434 		callout_stop(&sc->sfl_callout);
7435 		mtx_unlock(&sc->sfl_lock);
7436 
7437 		KASSERT((fl->flags & FL_STARVING) == 0,
7438 		    ("%s: still starving", __func__));
7439 
7440 		/* Release all buffers if hardware is no longer available. */
7441 		if (!(iq->flags & IQ_HW_ALLOCATED))
7442 			free_fl_buffers(sc, fl);
7443 	}
7444 }
7445 
7446 /*
7447  * Wait for all activity on all the queues of the VI to complete.  It is assumed
7448  * that no new work is being enqueued by the hardware or the driver.  That part
7449  * should be arranged before calling this function.
7450  */
7451 static void
7452 quiesce_vi(struct vi_info *vi)
7453 {
7454 	int i;
7455 	struct adapter *sc = vi->adapter;
7456 	struct sge_rxq *rxq;
7457 	struct sge_txq *txq;
7458 #ifdef TCP_OFFLOAD
7459 	struct sge_ofld_rxq *ofld_rxq;
7460 #endif
7461 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7462 	struct sge_ofld_txq *ofld_txq;
7463 #endif
7464 
7465 	if (!(vi->flags & VI_INIT_DONE))
7466 		return;
7467 
7468 	for_each_txq(vi, i, txq) {
7469 		quiesce_txq(txq);
7470 	}
7471 
7472 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7473 	for_each_ofld_txq(vi, i, ofld_txq) {
7474 		quiesce_wrq(&ofld_txq->wrq);
7475 	}
7476 #endif
7477 
7478 	for_each_rxq(vi, i, rxq) {
7479 		quiesce_iq_fl(sc, &rxq->iq, &rxq->fl);
7480 	}
7481 
7482 #ifdef TCP_OFFLOAD
7483 	for_each_ofld_rxq(vi, i, ofld_rxq) {
7484 		quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl);
7485 	}
7486 #endif
7487 }
7488 
7489 static int
7490 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
7491     driver_intr_t *handler, void *arg, char *name)
7492 {
7493 	int rc;
7494 
7495 	irq->rid = rid;
7496 	irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
7497 	    RF_SHAREABLE | RF_ACTIVE);
7498 	if (irq->res == NULL) {
7499 		device_printf(sc->dev,
7500 		    "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
7501 		return (ENOMEM);
7502 	}
7503 
7504 	rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
7505 	    NULL, handler, arg, &irq->tag);
7506 	if (rc != 0) {
7507 		device_printf(sc->dev,
7508 		    "failed to setup interrupt for rid %d, name %s: %d\n",
7509 		    rid, name, rc);
7510 	} else if (name)
7511 		bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
7512 
7513 	return (rc);
7514 }
7515 
7516 static int
7517 t4_free_irq(struct adapter *sc, struct irq *irq)
7518 {
7519 	if (irq->tag)
7520 		bus_teardown_intr(sc->dev, irq->res, irq->tag);
7521 	if (irq->res)
7522 		bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
7523 
7524 	bzero(irq, sizeof(*irq));
7525 
7526 	return (0);
7527 }
7528 
7529 static void
7530 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
7531 {
7532 
7533 	regs->version = chip_id(sc) | chip_rev(sc) << 10;
7534 	t4_get_regs(sc, buf, regs->len);
7535 }
7536 
7537 #define	A_PL_INDIR_CMD	0x1f8
7538 
7539 #define	S_PL_AUTOINC	31
7540 #define	M_PL_AUTOINC	0x1U
7541 #define	V_PL_AUTOINC(x)	((x) << S_PL_AUTOINC)
7542 #define	G_PL_AUTOINC(x)	(((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
7543 
7544 #define	S_PL_VFID	20
7545 #define	M_PL_VFID	0xffU
7546 #define	V_PL_VFID(x)	((x) << S_PL_VFID)
7547 #define	G_PL_VFID(x)	(((x) >> S_PL_VFID) & M_PL_VFID)
7548 
7549 #define	S_PL_ADDR	0
7550 #define	M_PL_ADDR	0xfffffU
7551 #define	V_PL_ADDR(x)	((x) << S_PL_ADDR)
7552 #define	G_PL_ADDR(x)	(((x) >> S_PL_ADDR) & M_PL_ADDR)
7553 
7554 #define	A_PL_INDIR_DATA	0x1fc
7555 
7556 static uint64_t
7557 read_vf_stat(struct adapter *sc, u_int vin, int reg)
7558 {
7559 	u32 stats[2];
7560 
7561 	if (sc->flags & IS_VF) {
7562 		stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
7563 		stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
7564 	} else {
7565 		mtx_assert(&sc->reg_lock, MA_OWNED);
7566 		t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
7567 		    V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));
7568 		stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
7569 		stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
7570 	}
7571 	return (((uint64_t)stats[1]) << 32 | stats[0]);
7572 }
7573 
7574 static void
7575 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats)
7576 {
7577 
7578 #define GET_STAT(name) \
7579 	read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L)
7580 
7581 	if (!(sc->flags & IS_VF))
7582 		mtx_lock(&sc->reg_lock);
7583 	stats->tx_bcast_bytes    = GET_STAT(TX_VF_BCAST_BYTES);
7584 	stats->tx_bcast_frames   = GET_STAT(TX_VF_BCAST_FRAMES);
7585 	stats->tx_mcast_bytes    = GET_STAT(TX_VF_MCAST_BYTES);
7586 	stats->tx_mcast_frames   = GET_STAT(TX_VF_MCAST_FRAMES);
7587 	stats->tx_ucast_bytes    = GET_STAT(TX_VF_UCAST_BYTES);
7588 	stats->tx_ucast_frames   = GET_STAT(TX_VF_UCAST_FRAMES);
7589 	stats->tx_drop_frames    = GET_STAT(TX_VF_DROP_FRAMES);
7590 	stats->tx_offload_bytes  = GET_STAT(TX_VF_OFFLOAD_BYTES);
7591 	stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
7592 	stats->rx_bcast_bytes    = GET_STAT(RX_VF_BCAST_BYTES);
7593 	stats->rx_bcast_frames   = GET_STAT(RX_VF_BCAST_FRAMES);
7594 	stats->rx_mcast_bytes    = GET_STAT(RX_VF_MCAST_BYTES);
7595 	stats->rx_mcast_frames   = GET_STAT(RX_VF_MCAST_FRAMES);
7596 	stats->rx_ucast_bytes    = GET_STAT(RX_VF_UCAST_BYTES);
7597 	stats->rx_ucast_frames   = GET_STAT(RX_VF_UCAST_FRAMES);
7598 	stats->rx_err_frames     = GET_STAT(RX_VF_ERR_FRAMES);
7599 	if (!(sc->flags & IS_VF))
7600 		mtx_unlock(&sc->reg_lock);
7601 
7602 #undef GET_STAT
7603 }
7604 
7605 static void
7606 t4_clr_vi_stats(struct adapter *sc, u_int vin)
7607 {
7608 	int reg;
7609 
7610 	t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) |
7611 	    V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
7612 	for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
7613 	     reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
7614 		t4_write_reg(sc, A_PL_INDIR_DATA, 0);
7615 }
7616 
7617 static void
7618 vi_refresh_stats(struct vi_info *vi)
7619 {
7620 	struct timeval tv;
7621 	const struct timeval interval = {0, 250000};	/* 250ms */
7622 
7623 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7624 
7625 	if (vi->flags & VI_SKIP_STATS)
7626 		return;
7627 
7628 	getmicrotime(&tv);
7629 	timevalsub(&tv, &interval);
7630 	if (timevalcmp(&tv, &vi->last_refreshed, <))
7631 		return;
7632 
7633 	t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats);
7634 	getmicrotime(&vi->last_refreshed);
7635 }
7636 
7637 static void
7638 cxgbe_refresh_stats(struct vi_info *vi)
7639 {
7640 	u_int i, v, tnl_cong_drops, chan_map;
7641 	struct timeval tv;
7642 	const struct timeval interval = {0, 250000};	/* 250ms */
7643 	struct port_info *pi;
7644 	struct adapter *sc;
7645 
7646 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7647 
7648 	if (vi->flags & VI_SKIP_STATS)
7649 		return;
7650 
7651 	getmicrotime(&tv);
7652 	timevalsub(&tv, &interval);
7653 	if (timevalcmp(&tv, &vi->last_refreshed, <))
7654 		return;
7655 
7656 	pi = vi->pi;
7657 	sc = vi->adapter;
7658 	tnl_cong_drops = 0;
7659 	t4_get_port_stats(sc, pi->hw_port, &pi->stats);
7660 	chan_map = pi->rx_e_chan_map;
7661 	while (chan_map) {
7662 		i = ffs(chan_map) - 1;
7663 		mtx_lock(&sc->reg_lock);
7664 		t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
7665 		    A_TP_MIB_TNL_CNG_DROP_0 + i);
7666 		mtx_unlock(&sc->reg_lock);
7667 		tnl_cong_drops += v;
7668 		chan_map &= ~(1 << i);
7669 	}
7670 	pi->tnl_cong_drops = tnl_cong_drops;
7671 	getmicrotime(&vi->last_refreshed);
7672 }
7673 
7674 static void
7675 cxgbe_tick(void *arg)
7676 {
7677 	struct vi_info *vi = arg;
7678 
7679 	MPASS(IS_MAIN_VI(vi));
7680 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7681 
7682 	cxgbe_refresh_stats(vi);
7683 	callout_schedule(&vi->tick, hz);
7684 }
7685 
7686 static void
7687 vi_tick(void *arg)
7688 {
7689 	struct vi_info *vi = arg;
7690 
7691 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7692 
7693 	vi_refresh_stats(vi);
7694 	callout_schedule(&vi->tick, hz);
7695 }
7696 
7697 /* CIM inbound queues */
7698 static const char *t4_ibq[CIM_NUM_IBQ] = {
7699 	"ibq_tp0", "ibq_tp1", "ibq_ulp", "ibq_sge0", "ibq_sge1", "ibq_ncsi"
7700 };
7701 static const char *t7_ibq[CIM_NUM_IBQ_T7] = {
7702 	"ibq_tp0", "ibq_tp1", "ibq_tp2", "ibq_tp3", "ibq_ulp", "ibq_sge0",
7703 	"ibq_sge1", "ibq_ncsi", NULL, "ibq_ipc1", "ibq_ipc2", "ibq_ipc3",
7704 	"ibq_ipc4", "ibq_ipc5", "ibq_ipc6", "ibq_ipc7"
7705 };
7706 static const char *t7_ibq_sec[] = {
7707 	"ibq_tp0", "ibq_tp1", "ibq_tp2", "ibq_tp3", "ibq_ulp", "ibq_sge0",
7708 	NULL, NULL, NULL, "ibq_ipc0"
7709 };
7710 
7711 /* CIM outbound queues */
7712 static const char *t4_obq[CIM_NUM_OBQ_T5] = {
7713 	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", "obq_ncsi",
7714 	"obq_sge_rx_q0", "obq_sge_rx_q1" /* These two are T5/T6 only */
7715 };
7716 static const char *t7_obq[CIM_NUM_OBQ_T7] = {
7717 	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", "obq_ncsi",
7718 	"obq_sge_rx_q0", NULL, NULL, "obq_ipc1", "obq_ipc2", "obq_ipc3",
7719 	"obq_ipc4", "obq_ipc5", "obq_ipc6", "obq_ipc7"
7720 };
7721 static const char *t7_obq_sec[] = {
7722 	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", NULL,
7723 	"obq_sge_rx_q0", NULL, NULL, "obq_ipc0"
7724 };
7725 
7726 static void
7727 cim_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
7728     struct sysctl_oid_list *c0)
7729 {
7730 	struct sysctl_oid *oid;
7731 	struct sysctl_oid_list *children1;
7732 	int i, j, qcount;
7733 	char s[16];
7734 	const char **qname;
7735 
7736 	oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "cim",
7737 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CIM block");
7738 	c0 = SYSCTL_CHILDREN(oid);
7739 
7740 	SYSCTL_ADD_U8(ctx, c0, OID_AUTO, "ncores", CTLFLAG_RD, NULL,
7741 	    sc->params.ncores, "# of active CIM cores");
7742 
7743 	for (i = 0; i < sc->params.ncores; i++) {
7744 		snprintf(s, sizeof(s), "%u", i);
7745 		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, s,
7746 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CIM core");
7747 		children1 = SYSCTL_CHILDREN(oid);
7748 
7749 		/*
7750 		 * CTLFLAG_SKIP because the misc.devlog sysctl already displays
7751 		 * the log for all cores.  Use this sysctl to get the log for a
7752 		 * particular core only.
7753 		 */
7754 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "devlog",
7755 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
7756 		    sc, i, sysctl_devlog, "A", "firmware's device log");
7757 
7758 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "loadavg",
7759 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7760 		    sysctl_loadavg, "A",
7761 		    "microprocessor load averages (select firmwares only)");
7762 
7763 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "qcfg",
7764 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7765 		    chip_id(sc) > CHELSIO_T6 ? sysctl_cim_qcfg_t7 : sysctl_cim_qcfg,
7766 		    "A", "Queue configuration");
7767 
7768 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "la",
7769 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7770 		    sysctl_cim_la, "A", "Logic analyzer");
7771 
7772 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "ma_la",
7773 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7774 		    sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
7775 
7776 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "pif_la",
7777 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7778 		    sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
7779 
7780 		/* IBQs */
7781 		switch (chip_id(sc)) {
7782 		case CHELSIO_T4:
7783 		case CHELSIO_T5:
7784 		case CHELSIO_T6:
7785 			qname = &t4_ibq[0];
7786 			qcount = nitems(t4_ibq);
7787 			break;
7788 		case CHELSIO_T7:
7789 		default:
7790 			if (i == 0) {
7791 				qname = &t7_ibq[0];
7792 				qcount = nitems(t7_ibq);
7793 			} else {
7794 				qname = &t7_ibq_sec[0];
7795 				qcount = nitems(t7_ibq_sec);
7796 			}
7797 			break;
7798 		}
7799 		MPASS(qcount <= sc->chip_params->cim_num_ibq);
7800 		for (j = 0; j < qcount; j++) {
7801 			if (qname[j] == NULL)
7802 				continue;
7803 			SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, qname[j],
7804 			    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7805 			    (i << 16) | j, sysctl_cim_ibq, "A", NULL);
7806 		}
7807 
7808 		/* OBQs */
7809 		switch (chip_id(sc)) {
7810 		case CHELSIO_T4:
7811 			qname = t4_obq;
7812 			qcount = CIM_NUM_OBQ;
7813 			break;
7814 		case CHELSIO_T5:
7815 		case CHELSIO_T6:
7816 			qname = t4_obq;
7817 			qcount = nitems(t4_obq);
7818 			break;
7819 		case CHELSIO_T7:
7820 		default:
7821 			if (i == 0) {
7822 				qname = t7_obq;
7823 				qcount = nitems(t7_obq);
7824 			} else {
7825 				qname = t7_obq_sec;
7826 				qcount = nitems(t7_obq_sec);
7827 			}
7828 			break;
7829 		}
7830 		MPASS(qcount <= sc->chip_params->cim_num_obq);
7831 		for (j = 0; j < qcount; j++) {
7832 			if (qname[j] == NULL)
7833 				continue;
7834 			SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, qname[j],
7835 			    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7836 			    (i << 16) | j, sysctl_cim_obq, "A", NULL);
7837 		}
7838 	}
7839 }
7840 
7841 /*
7842  * Should match fw_caps_config_<foo> enums in t4fw_interface.h
7843  */
7844 static char *caps_decoder[] = {
7845 	"\20\001IPMI\002NCSI",				/* 0: NBM */
7846 	"\20\001PPP\002QFC\003DCBX",			/* 1: link */
7847 	"\20\001INGRESS\002EGRESS",			/* 2: switch */
7848 	"\20\001NIC\002VM\003IDS\004UM\005UM_ISGL"	/* 3: NIC */
7849 	    "\006HASHFILTER\007ETHOFLD",
7850 	"\20\001TOE\002SENDPATH",			/* 4: TOE */
7851 	"\20\001RDDP\002RDMAC\003ROCEv2",		/* 5: RDMA */
7852 	"\20\001INITIATOR_PDU\002TARGET_PDU"		/* 6: iSCSI */
7853 	    "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
7854 	    "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
7855 	    "\007T10DIF"
7856 	    "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
7857 	"\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE"	/* 7: Crypto */
7858 	    "\004TLS_HW,\005TOE_IPSEC",
7859 	"\20\001INITIATOR\002TARGET\003CTRL_OFLD"	/* 8: FCoE */
7860 		    "\004PO_INITIATOR\005PO_TARGET",
7861 	"\20\001NVMe_TCP",				/* 9: NVMe */
7862 };
7863 
7864 void
7865 t4_sysctls(struct adapter *sc)
7866 {
7867 	struct sysctl_ctx_list *ctx = &sc->ctx;
7868 	struct sysctl_oid *oid;
7869 	struct sysctl_oid_list *children, *c0;
7870 	static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
7871 
7872 	/*
7873 	 * dev.t4nex.X.
7874 	 */
7875 	oid = device_get_sysctl_tree(sc->dev);
7876 	c0 = children = SYSCTL_CHILDREN(oid);
7877 
7878 	sc->sc_do_rxcopy = 1;
7879 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
7880 	    &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
7881 
7882 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
7883 	    sc->params.nports, "# of ports");
7884 
7885 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
7886 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells,
7887 	    (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A",
7888 	    "available doorbells");
7889 
7890 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
7891 	    sc->params.vpd.cclk, "core clock frequency (in KHz)");
7892 
7893 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
7894 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7895 	    sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val),
7896 	    sysctl_int_array, "A", "interrupt holdoff timer values (us)");
7897 
7898 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
7899 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7900 	    sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val),
7901 	    sysctl_int_array, "A", "interrupt holdoff packet counter values");
7902 
7903 	t4_sge_sysctls(sc, ctx, children);
7904 
7905 	sc->lro_timeout = 100;
7906 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
7907 	    &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
7908 
7909 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
7910 	    &sc->debug_flags, 0, "flags to enable runtime debugging");
7911 
7912 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iflags", CTLFLAG_RW,
7913 	    &sc->intr_flags, 0, "flags for the slow interrupt handler");
7914 
7915 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
7916 	    CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
7917 
7918 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
7919 	    CTLFLAG_RD, sc->fw_version, 0, "firmware version");
7920 
7921 	if (sc->flags & IS_VF)
7922 		return;
7923 
7924 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
7925 	    NULL, chip_rev(sc), "chip hardware revision");
7926 
7927 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
7928 	    CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
7929 
7930 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
7931 	    CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
7932 
7933 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
7934 	    CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
7935 
7936 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
7937 	    CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
7938 
7939 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
7940 	    CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
7941 
7942 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
7943 	    sc->er_version, 0, "expansion ROM version");
7944 
7945 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
7946 	    sc->bs_version, 0, "bootstrap firmware version");
7947 
7948 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
7949 	    NULL, sc->params.scfg_vers, "serial config version");
7950 
7951 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
7952 	    NULL, sc->params.vpd_vers, "VPD version");
7953 
7954 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
7955 	    CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
7956 
7957 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
7958 	    sc->cfcsum, "config file checksum");
7959 
7960 #define SYSCTL_CAP(name, n, text) \
7961 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
7962 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \
7963 	    (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \
7964 	    "available " text " capabilities")
7965 
7966 	SYSCTL_CAP(nbmcaps, 0, "NBM");
7967 	SYSCTL_CAP(linkcaps, 1, "link");
7968 	SYSCTL_CAP(switchcaps, 2, "switch");
7969 	SYSCTL_CAP(nvmecaps, 9, "NVMe");
7970 	SYSCTL_CAP(niccaps, 3, "NIC");
7971 	SYSCTL_CAP(toecaps, 4, "TCP offload");
7972 	SYSCTL_CAP(rdmacaps, 5, "RDMA");
7973 	SYSCTL_CAP(iscsicaps, 6, "iSCSI");
7974 	SYSCTL_CAP(cryptocaps, 7, "crypto");
7975 	SYSCTL_CAP(fcoecaps, 8, "FCoE");
7976 #undef SYSCTL_CAP
7977 
7978 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
7979 	    NULL, sc->tids.nftids, "number of filters");
7980 
7981 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
7982 	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7983 	    sysctl_temperature, "I", "chip temperature (in Celsius)");
7984 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor",
7985 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
7986 	    sysctl_reset_sensor, "I", "reset the chip's temperature sensor.");
7987 
7988 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd",
7989 	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd,
7990 	    "I", "core Vdd (in mV)");
7991 
7992 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
7993 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS,
7994 	    sysctl_cpus, "A", "local CPUs");
7995 
7996 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
7997 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS,
7998 	    sysctl_cpus, "A", "preferred CPUs for interrupts");
7999 
8000 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW,
8001 	    &sc->swintr, 0, "software triggered interrupts");
8002 
8003 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset",
8004 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I",
8005 	    "1 = reset adapter, 0 = zero reset counter");
8006 
8007 	/*
8008 	 * dev.t4nex.X.misc.  Marked CTLFLAG_SKIP to avoid information overload.
8009 	 */
8010 	oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
8011 	    CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL,
8012 	    "logs and miscellaneous information");
8013 	children = SYSCTL_CHILDREN(oid);
8014 
8015 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
8016 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8017 	    sysctl_cctrl, "A", "congestion control");
8018 
8019 	cim_sysctls(sc, ctx, children);
8020 
8021 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
8022 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8023 	    sysctl_cpl_stats, "A", "CPL statistics");
8024 
8025 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
8026 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8027 	    sysctl_ddp_stats, "A", "non-TCP DDP statistics");
8028 
8029 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats",
8030 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8031 	    sysctl_tid_stats, "A", "tid stats");
8032 
8033 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
8034 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, -1,
8035 	    sysctl_devlog, "A", "firmware's device log (all cores)");
8036 
8037 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
8038 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8039 	    sysctl_fcoe_stats, "A", "FCoE statistics");
8040 
8041 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
8042 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8043 	    sysctl_hw_sched, "A", "hardware scheduler ");
8044 
8045 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
8046 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8047 	    sysctl_l2t, "A", "hardware L2 table");
8048 
8049 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
8050 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8051 	    sysctl_smt, "A", "hardware source MAC table");
8052 
8053 #ifdef INET6
8054 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
8055 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8056 	    sysctl_clip, "A", "active CLIP table entries");
8057 #endif
8058 
8059 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
8060 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8061 	    sysctl_lb_stats, "A", "loopback statistics");
8062 
8063 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
8064 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8065 	    sysctl_meminfo, "A", "memory regions");
8066 
8067 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
8068 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8069 	    chip_id(sc) >= CHELSIO_T7 ? sysctl_mps_tcam_t7 :
8070 	    (chip_id(sc) >= CHELSIO_T6 ? sysctl_mps_tcam_t6 : sysctl_mps_tcam),
8071 	    "A", "MPS TCAM entries");
8072 
8073 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
8074 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8075 	    sysctl_path_mtus, "A", "path MTUs");
8076 
8077 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
8078 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8079 	    sysctl_pm_stats, "A", "PM statistics");
8080 
8081 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
8082 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8083 	    sysctl_rdma_stats, "A", "RDMA statistics");
8084 
8085 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
8086 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8087 	    sysctl_tcp_stats, "A", "TCP statistics");
8088 
8089 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
8090 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8091 	    sysctl_tids, "A", "TID information");
8092 
8093 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
8094 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8095 	    sysctl_tp_err_stats, "A", "TP error statistics");
8096 
8097 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats",
8098 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8099 	    sysctl_tnl_stats, "A", "TP tunnel statistics");
8100 
8101 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
8102 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
8103 	    sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask");
8104 
8105 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
8106 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8107 	    sysctl_tp_la, "A", "TP logic analyzer");
8108 
8109 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
8110 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8111 	    sysctl_tx_rate, "A", "Tx rate");
8112 
8113 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
8114 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8115 	    sysctl_ulprx_la, "A", "ULPRX logic analyzer");
8116 
8117 	if (chip_id(sc) >= CHELSIO_T5) {
8118 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
8119 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8120 		    sysctl_wcwr_stats, "A", "write combined work requests");
8121 	}
8122 
8123 	if (chip_id(sc) >= CHELSIO_T7) {
8124 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcb_cache",
8125 		    CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tcb_cache, "I",
8126 		    "1 = enabled (default), 0 = disabled (for debug only)");
8127 	}
8128 
8129 #ifdef KERN_TLS
8130 	if (is_ktls(sc)) {
8131 		/*
8132 		 * dev.t4nex.0.tls.
8133 		 */
8134 		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls",
8135 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters");
8136 		children = SYSCTL_CHILDREN(oid);
8137 
8138 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys",
8139 		    CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS "
8140 		    "keys in work requests (1) or attempt to store TLS keys "
8141 		    "in card memory.");
8142 
8143 		if (is_t6(sc))
8144 			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs",
8145 			    CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to "
8146 			    "combine TCB field updates with TLS record work "
8147 			    "requests.");
8148 		else {
8149 			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "short_records",
8150 			    CTLFLAG_RW, &sc->tlst.short_records, 0,
8151 			    "Use cipher-only mode for short records.");
8152 			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "partial_ghash",
8153 			    CTLFLAG_RW, &sc->tlst.partial_ghash, 0,
8154 			    "Use partial GHASH for AES-GCM records.");
8155 		}
8156 	}
8157 #endif
8158 
8159 #ifdef TCP_OFFLOAD
8160 	if (is_offload(sc)) {
8161 		int i;
8162 		char s[4];
8163 
8164 		/*
8165 		 * dev.t4nex.X.toe.
8166 		 */
8167 		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe",
8168 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters");
8169 		children = SYSCTL_CHILDREN(oid);
8170 
8171 		sc->tt.cong_algorithm = -1;
8172 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
8173 		    CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
8174 		    "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
8175 		    "3 = highspeed)");
8176 
8177 		sc->tt.sndbuf = -1;
8178 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
8179 		    &sc->tt.sndbuf, 0, "hardware send buffer");
8180 
8181 		sc->tt.ddp = 0;
8182 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp",
8183 		    CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, "");
8184 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW,
8185 		    &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)");
8186 
8187 		sc->tt.rx_coalesce = -1;
8188 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
8189 		    CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
8190 
8191 		sc->tt.tls = 1;
8192 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT |
8193 		    CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I",
8194 		    "Inline TLS allowed");
8195 
8196 		sc->tt.tx_align = -1;
8197 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
8198 		    CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
8199 
8200 		sc->tt.tx_zcopy = 0;
8201 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
8202 		    CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
8203 		    "Enable zero-copy aio_write(2)");
8204 
8205 		sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
8206 		SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8207 		    "cop_managed_offloading", CTLFLAG_RW,
8208 		    &sc->tt.cop_managed_offloading, 0,
8209 		    "COP (Connection Offload Policy) controls all TOE offload");
8210 
8211 		sc->tt.autorcvbuf_inc = 16 * 1024;
8212 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc",
8213 		    CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0,
8214 		    "autorcvbuf increment");
8215 
8216 		sc->tt.update_hc_on_pmtu_change = 1;
8217 		SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8218 		    "update_hc_on_pmtu_change", CTLFLAG_RW,
8219 		    &sc->tt.update_hc_on_pmtu_change, 0,
8220 		    "Update hostcache entry if the PMTU changes");
8221 
8222 		sc->tt.iso = 1;
8223 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW,
8224 		    &sc->tt.iso, 0, "Enable iSCSI segmentation offload");
8225 
8226 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
8227 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8228 		    sysctl_tp_tick, "A", "TP timer tick (us)");
8229 
8230 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
8231 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1,
8232 		    sysctl_tp_tick, "A", "TCP timestamp tick (us)");
8233 
8234 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
8235 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2,
8236 		    sysctl_tp_tick, "A", "DACK tick (us)");
8237 
8238 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
8239 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8240 		    sysctl_tp_dack_timer, "IU", "DACK timer (us)");
8241 
8242 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
8243 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8244 		    A_TP_RXT_MIN, sysctl_tp_timer, "LU",
8245 		    "Minimum retransmit interval (us)");
8246 
8247 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
8248 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8249 		    A_TP_RXT_MAX, sysctl_tp_timer, "LU",
8250 		    "Maximum retransmit interval (us)");
8251 
8252 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
8253 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8254 		    A_TP_PERS_MIN, sysctl_tp_timer, "LU",
8255 		    "Persist timer min (us)");
8256 
8257 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
8258 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8259 		    A_TP_PERS_MAX, sysctl_tp_timer, "LU",
8260 		    "Persist timer max (us)");
8261 
8262 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
8263 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8264 		    A_TP_KEEP_IDLE, sysctl_tp_timer, "LU",
8265 		    "Keepalive idle timer (us)");
8266 
8267 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
8268 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8269 		    A_TP_KEEP_INTVL, sysctl_tp_timer, "LU",
8270 		    "Keepalive interval timer (us)");
8271 
8272 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
8273 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8274 		    A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)");
8275 
8276 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
8277 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8278 		    A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU",
8279 		    "FINWAIT2 timer (us)");
8280 
8281 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
8282 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8283 		    S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU",
8284 		    "Number of SYN retransmissions before abort");
8285 
8286 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
8287 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8288 		    S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU",
8289 		    "Number of retransmissions before abort");
8290 
8291 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
8292 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8293 		    S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU",
8294 		    "Number of keepalive probes before abort");
8295 
8296 		oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
8297 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
8298 		    "TOE retransmit backoffs");
8299 		children = SYSCTL_CHILDREN(oid);
8300 		for (i = 0; i < 16; i++) {
8301 			snprintf(s, sizeof(s), "%u", i);
8302 			SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
8303 			    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8304 			    i, sysctl_tp_backoff, "IU",
8305 			    "TOE retransmit backoff");
8306 		}
8307 	}
8308 #endif
8309 }
8310 
8311 void
8312 vi_sysctls(struct vi_info *vi)
8313 {
8314 	struct sysctl_ctx_list *ctx = &vi->ctx;
8315 	struct sysctl_oid *oid;
8316 	struct sysctl_oid_list *children;
8317 
8318 	/*
8319 	 * dev.v?(cxgbe|cxl).X.
8320 	 */
8321 	oid = device_get_sysctl_tree(vi->dev);
8322 	children = SYSCTL_CHILDREN(oid);
8323 
8324 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
8325 	    vi->viid, "VI identifer");
8326 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
8327 	    &vi->nrxq, 0, "# of rx queues");
8328 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
8329 	    &vi->ntxq, 0, "# of tx queues");
8330 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
8331 	    &vi->first_rxq, 0, "index of first rx queue");
8332 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
8333 	    &vi->first_txq, 0, "index of first tx queue");
8334 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
8335 	    vi->rss_base, "start of RSS indirection table");
8336 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
8337 	    vi->rss_size, "size of RSS indirection table");
8338 
8339 	if (IS_MAIN_VI(vi)) {
8340 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
8341 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8342 		    sysctl_noflowq, "IU",
8343 		    "Reserve queue 0 for non-flowid packets");
8344 	}
8345 
8346 	if (vi->adapter->flags & IS_VF) {
8347 		MPASS(vi->flags & TX_USES_VM_WR);
8348 		SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD,
8349 		    NULL, 1, "use VM work requests for transmit");
8350 	} else {
8351 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr",
8352 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8353 		    sysctl_tx_vm_wr, "I", "use VM work requestes for transmit");
8354 	}
8355 
8356 #ifdef TCP_OFFLOAD
8357 	if (vi->nofldrxq != 0) {
8358 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
8359 		    &vi->nofldrxq, 0,
8360 		    "# of rx queues for offloaded TCP connections");
8361 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
8362 		    CTLFLAG_RD, &vi->first_ofld_rxq, 0,
8363 		    "index of first TOE rx queue");
8364 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
8365 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8366 		    sysctl_holdoff_tmr_idx_ofld, "I",
8367 		    "holdoff timer index for TOE queues");
8368 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
8369 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8370 		    sysctl_holdoff_pktc_idx_ofld, "I",
8371 		    "holdoff packet counter index for TOE queues");
8372 	}
8373 #endif
8374 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
8375 	if (vi->nofldtxq != 0) {
8376 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
8377 		    &vi->nofldtxq, 0,
8378 		    "# of tx queues for TOE/ETHOFLD");
8379 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
8380 		    CTLFLAG_RD, &vi->first_ofld_txq, 0,
8381 		    "index of first TOE/ETHOFLD tx queue");
8382 	}
8383 #endif
8384 #ifdef DEV_NETMAP
8385 	if (vi->nnmrxq != 0) {
8386 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
8387 		    &vi->nnmrxq, 0, "# of netmap rx queues");
8388 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
8389 		    &vi->nnmtxq, 0, "# of netmap tx queues");
8390 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
8391 		    CTLFLAG_RD, &vi->first_nm_rxq, 0,
8392 		    "index of first netmap rx queue");
8393 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
8394 		    CTLFLAG_RD, &vi->first_nm_txq, 0,
8395 		    "index of first netmap tx queue");
8396 	}
8397 #endif
8398 
8399 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
8400 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8401 	    sysctl_holdoff_tmr_idx, "I", "holdoff timer index");
8402 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
8403 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8404 	    sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index");
8405 
8406 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
8407 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8408 	    sysctl_qsize_rxq, "I", "rx queue size");
8409 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
8410 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8411 	    sysctl_qsize_txq, "I", "tx queue size");
8412 }
8413 
8414 static void
8415 cxgbe_sysctls(struct port_info *pi)
8416 {
8417 	struct sysctl_ctx_list *ctx = &pi->ctx;
8418 	struct sysctl_oid *oid;
8419 	struct sysctl_oid_list *children, *children2;
8420 	struct adapter *sc = pi->adapter;
8421 	int i;
8422 	char name[16];
8423 	static char *tc_flags = {"\20\1USER"};
8424 
8425 	/*
8426 	 * dev.cxgbe.X.
8427 	 */
8428 	oid = device_get_sysctl_tree(pi->dev);
8429 	children = SYSCTL_CHILDREN(oid);
8430 
8431 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc",
8432 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
8433 	    sysctl_linkdnrc, "A", "reason why link is down");
8434 	if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
8435 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
8436 		    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
8437 		    sysctl_btphy, "I", "PHY temperature (in Celsius)");
8438 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
8439 		    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1,
8440 		    sysctl_btphy, "I", "PHY firmware version");
8441 	}
8442 
8443 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
8444 	    CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8445 	    sysctl_pause_settings, "A",
8446 	    "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
8447 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec",
8448 	    CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A",
8449 	    "FEC in use on the link");
8450 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec",
8451 	    CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8452 	    sysctl_requested_fec, "A",
8453 	    "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)");
8454 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec",
8455 	    CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A",
8456 	    "FEC recommended by the cable/transceiver");
8457 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
8458 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8459 	    sysctl_autoneg, "I",
8460 	    "autonegotiation (-1 = not supported)");
8461 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec",
8462 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8463 	    sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config");
8464 
8465 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD,
8466 	    &pi->link_cfg.requested_caps, 0, "L1 config requested by driver");
8467 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD,
8468 	    &pi->link_cfg.pcaps, 0, "port capabilities");
8469 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD,
8470 	    &pi->link_cfg.acaps, 0, "advertised capabilities");
8471 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD,
8472 	    &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities");
8473 
8474 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
8475 	    port_top_speed(pi), "max speed (in Gbps)");
8476 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
8477 	    pi->mps_bg_map, "MPS buffer group map");
8478 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
8479 	    NULL, pi->rx_e_chan_map, "TP rx e-channel map");
8480 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_chan", CTLFLAG_RD, NULL,
8481 	    pi->tx_chan, "TP tx c-channel");
8482 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_chan", CTLFLAG_RD, NULL,
8483 	    pi->rx_chan, "TP rx c-channel");
8484 
8485 	if (sc->flags & IS_VF)
8486 		return;
8487 
8488 	/*
8489 	 * dev.(cxgbe|cxl).X.tc.
8490 	 */
8491 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc",
8492 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
8493 	    "Tx scheduler traffic classes (cl_rl)");
8494 	children2 = SYSCTL_CHILDREN(oid);
8495 	SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
8496 	    CTLFLAG_RW, &pi->sched_params->pktsize, 0,
8497 	    "pktsize for per-flow cl-rl (0 means up to the driver )");
8498 	SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
8499 	    CTLFLAG_RW, &pi->sched_params->burstsize, 0,
8500 	    "burstsize for per-flow cl-rl (0 means up to the driver)");
8501 	for (i = 0; i < sc->params.nsched_cls; i++) {
8502 		struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
8503 
8504 		snprintf(name, sizeof(name), "%d", i);
8505 		children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
8506 		    SYSCTL_CHILDREN(oid), OID_AUTO, name,
8507 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class"));
8508 		SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state",
8509 		    CTLFLAG_RD, &tc->state, 0, "current state");
8510 		SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
8511 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags,
8512 		    (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags");
8513 		SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
8514 		    CTLFLAG_RD, &tc->refcount, 0, "references to this class");
8515 		SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
8516 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8517 		    (pi->port_id << 16) | i, sysctl_tc_params, "A",
8518 		    "traffic class parameters");
8519 	}
8520 
8521 	/*
8522 	 * dev.cxgbe.X.stats.
8523 	 */
8524 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats",
8525 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics");
8526 	children = SYSCTL_CHILDREN(oid);
8527 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
8528 	    &pi->tx_parse_error, 0,
8529 	    "# of tx packets with invalid length or # of segments");
8530 
8531 #define T4_LBSTAT(name, stat, desc) do { \
8532 	if (sc->params.tp.lb_mode) { \
8533 		SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8534 		    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, \
8535 		    A_MPS_PORT_STAT_##stat##_L, \
8536 		    sysctl_handle_t4_portstat64, "QU", desc); \
8537 	} else { \
8538 		SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8539 		    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
8540 		    t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \
8541 		    sysctl_handle_t4_reg64, "QU", desc); \
8542 	} \
8543 } while (0)
8544 
8545 	T4_LBSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames");
8546 	T4_LBSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames");
8547 	T4_LBSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames");
8548 	T4_LBSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames");
8549 	T4_LBSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames");
8550 	T4_LBSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames");
8551 	T4_LBSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range");
8552 	T4_LBSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range");
8553 	T4_LBSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range");
8554 	T4_LBSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range");
8555 	T4_LBSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range");
8556 	T4_LBSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range");
8557 	T4_LBSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range");
8558 	T4_LBSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames");
8559 	T4_LBSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted");
8560 	T4_LBSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted");
8561 	T4_LBSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted");
8562 	T4_LBSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted");
8563 	T4_LBSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted");
8564 	T4_LBSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted");
8565 	T4_LBSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted");
8566 	T4_LBSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted");
8567 	T4_LBSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted");
8568 
8569 	T4_LBSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames");
8570 	T4_LBSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames");
8571 	T4_LBSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames");
8572 	T4_LBSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames");
8573 	T4_LBSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames");
8574 	T4_LBSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU");
8575 	T4_LBSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames");
8576 	if (is_t6(sc)) {
8577 		/* Read from port_stats and may be stale by up to 1s */
8578 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rx_fcs_err",
8579 		    CTLFLAG_RD, &pi->stats.rx_fcs_err,
8580 		    "# of frames received with bad FCS since last link up");
8581 	} else {
8582 		T4_LBSTAT(rx_fcs_err, RX_PORT_CRC_ERROR,
8583 		    "# of frames received with bad FCS");
8584 	}
8585 	T4_LBSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error");
8586 	T4_LBSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors");
8587 	T4_LBSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received");
8588 	T4_LBSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range");
8589 	T4_LBSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range");
8590 	T4_LBSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range");
8591 	T4_LBSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range");
8592 	T4_LBSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range");
8593 	T4_LBSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range");
8594 	T4_LBSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range");
8595 	T4_LBSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received");
8596 	T4_LBSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received");
8597 	T4_LBSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received");
8598 	T4_LBSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received");
8599 	T4_LBSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received");
8600 	T4_LBSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received");
8601 	T4_LBSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received");
8602 	T4_LBSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received");
8603 	T4_LBSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received");
8604 #undef T4_LBSTAT
8605 
8606 #define T4_REGSTAT(name, stat, desc) do { \
8607 	SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8608 	    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
8609 	    A_MPS_STAT_##stat##_L, sysctl_handle_t4_reg64, "QU", desc); \
8610 } while (0)
8611 
8612 	if (pi->mps_bg_map & 1) {
8613 		T4_REGSTAT(rx_ovflow0, RX_BG_0_MAC_DROP_FRAME,
8614 		    "# drops due to buffer-group 0 overflows");
8615 		T4_REGSTAT(rx_trunc0, RX_BG_0_MAC_TRUNC_FRAME,
8616 		    "# of buffer-group 0 truncated packets");
8617 	}
8618 	if (pi->mps_bg_map & 2) {
8619 		T4_REGSTAT(rx_ovflow1, RX_BG_1_MAC_DROP_FRAME,
8620 		    "# drops due to buffer-group 1 overflows");
8621 		T4_REGSTAT(rx_trunc1, RX_BG_1_MAC_TRUNC_FRAME,
8622 		    "# of buffer-group 1 truncated packets");
8623 	}
8624 	if (pi->mps_bg_map & 4) {
8625 		T4_REGSTAT(rx_ovflow2, RX_BG_2_MAC_DROP_FRAME,
8626 		    "# drops due to buffer-group 2 overflows");
8627 		T4_REGSTAT(rx_trunc2, RX_BG_2_MAC_TRUNC_FRAME,
8628 		    "# of buffer-group 2 truncated packets");
8629 	}
8630 	if (pi->mps_bg_map & 8) {
8631 		T4_REGSTAT(rx_ovflow3, RX_BG_3_MAC_DROP_FRAME,
8632 		    "# drops due to buffer-group 3 overflows");
8633 		T4_REGSTAT(rx_trunc3, RX_BG_3_MAC_TRUNC_FRAME,
8634 		    "# of buffer-group 3 truncated packets");
8635 	}
8636 #undef T4_REGSTAT
8637 }
8638 
8639 static int
8640 sysctl_int_array(SYSCTL_HANDLER_ARGS)
8641 {
8642 	int rc, *i, space = 0;
8643 	struct sbuf sb;
8644 
8645 	sbuf_new_for_sysctl(&sb, NULL, 64, req);
8646 	for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
8647 		if (space)
8648 			sbuf_printf(&sb, " ");
8649 		sbuf_printf(&sb, "%d", *i);
8650 		space = 1;
8651 	}
8652 	rc = sbuf_finish(&sb);
8653 	sbuf_delete(&sb);
8654 	return (rc);
8655 }
8656 
8657 static int
8658 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
8659 {
8660 	int rc;
8661 	struct sbuf *sb;
8662 
8663 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8664 	if (sb == NULL)
8665 		return (ENOMEM);
8666 
8667 	sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
8668 	rc = sbuf_finish(sb);
8669 	sbuf_delete(sb);
8670 
8671 	return (rc);
8672 }
8673 
8674 static int
8675 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
8676 {
8677 	int rc;
8678 	struct sbuf *sb;
8679 
8680 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8681 	if (sb == NULL)
8682 		return (ENOMEM);
8683 
8684 	sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
8685 	rc = sbuf_finish(sb);
8686 	sbuf_delete(sb);
8687 
8688 	return (rc);
8689 }
8690 
8691 static int
8692 sysctl_btphy(SYSCTL_HANDLER_ARGS)
8693 {
8694 	struct port_info *pi = arg1;
8695 	int op = arg2;
8696 	struct adapter *sc = pi->adapter;
8697 	u_int v;
8698 	int rc;
8699 
8700 	rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
8701 	if (rc)
8702 		return (rc);
8703 	if (!hw_all_ok(sc))
8704 		rc = ENXIO;
8705 	else {
8706 		/* XXX: magic numbers */
8707 		rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e,
8708 		    op ? 0x20 : 0xc820, &v);
8709 	}
8710 	end_synchronized_op(sc, 0);
8711 	if (rc)
8712 		return (rc);
8713 	if (op == 0)
8714 		v /= 256;
8715 
8716 	rc = sysctl_handle_int(oidp, &v, 0, req);
8717 	return (rc);
8718 }
8719 
8720 static int
8721 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
8722 {
8723 	struct vi_info *vi = arg1;
8724 	int rc, val;
8725 
8726 	val = vi->rsrv_noflowq;
8727 	rc = sysctl_handle_int(oidp, &val, 0, req);
8728 	if (rc != 0 || req->newptr == NULL)
8729 		return (rc);
8730 
8731 	if ((val >= 1) && (vi->ntxq > 1))
8732 		vi->rsrv_noflowq = 1;
8733 	else
8734 		vi->rsrv_noflowq = 0;
8735 
8736 	return (rc);
8737 }
8738 
8739 static int
8740 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS)
8741 {
8742 	struct vi_info *vi = arg1;
8743 	struct adapter *sc = vi->adapter;
8744 	int rc, val, i;
8745 
8746 	MPASS(!(sc->flags & IS_VF));
8747 
8748 	val = vi->flags & TX_USES_VM_WR ? 1 : 0;
8749 	rc = sysctl_handle_int(oidp, &val, 0, req);
8750 	if (rc != 0 || req->newptr == NULL)
8751 		return (rc);
8752 
8753 	if (val != 0 && val != 1)
8754 		return (EINVAL);
8755 
8756 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8757 	    "t4txvm");
8758 	if (rc)
8759 		return (rc);
8760 	if (!hw_all_ok(sc))
8761 		rc = ENXIO;
8762 	else if (if_getdrvflags(vi->ifp) & IFF_DRV_RUNNING) {
8763 		/*
8764 		 * We don't want parse_pkt to run with one setting (VF or PF)
8765 		 * and then eth_tx to see a different setting but still use
8766 		 * stale information calculated by parse_pkt.
8767 		 */
8768 		rc = EBUSY;
8769 	} else {
8770 		struct port_info *pi = vi->pi;
8771 		struct sge_txq *txq;
8772 		uint32_t ctrl0;
8773 		uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr;
8774 
8775 		if (val) {
8776 			vi->flags |= TX_USES_VM_WR;
8777 			if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO);
8778 			ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8779 			    V_TXPKT_INTF(pi->hw_port));
8780 			if (!(sc->flags & IS_VF))
8781 				npkt--;
8782 		} else {
8783 			vi->flags &= ~TX_USES_VM_WR;
8784 			if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO);
8785 			ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8786 			    V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) |
8787 			    V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
8788 		}
8789 		for_each_txq(vi, i, txq) {
8790 			txq->cpl_ctrl0 = ctrl0;
8791 			txq->txp.max_npkt = npkt;
8792 		}
8793 	}
8794 	end_synchronized_op(sc, LOCK_HELD);
8795 	return (rc);
8796 }
8797 
8798 static int
8799 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
8800 {
8801 	struct vi_info *vi = arg1;
8802 	struct adapter *sc = vi->adapter;
8803 	int idx, rc, i;
8804 	struct sge_rxq *rxq;
8805 	uint8_t v;
8806 
8807 	idx = vi->tmr_idx;
8808 
8809 	rc = sysctl_handle_int(oidp, &idx, 0, req);
8810 	if (rc != 0 || req->newptr == NULL)
8811 		return (rc);
8812 
8813 	if (idx < 0 || idx >= SGE_NTIMERS)
8814 		return (EINVAL);
8815 
8816 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8817 	    "t4tmr");
8818 	if (rc)
8819 		return (rc);
8820 
8821 	v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
8822 	for_each_rxq(vi, i, rxq) {
8823 #ifdef atomic_store_rel_8
8824 		atomic_store_rel_8(&rxq->iq.intr_params, v);
8825 #else
8826 		rxq->iq.intr_params = v;
8827 #endif
8828 	}
8829 	vi->tmr_idx = idx;
8830 
8831 	end_synchronized_op(sc, LOCK_HELD);
8832 	return (0);
8833 }
8834 
8835 static int
8836 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
8837 {
8838 	struct vi_info *vi = arg1;
8839 	struct adapter *sc = vi->adapter;
8840 	int idx, rc;
8841 
8842 	idx = vi->pktc_idx;
8843 
8844 	rc = sysctl_handle_int(oidp, &idx, 0, req);
8845 	if (rc != 0 || req->newptr == NULL)
8846 		return (rc);
8847 
8848 	if (idx < -1 || idx >= SGE_NCOUNTERS)
8849 		return (EINVAL);
8850 
8851 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8852 	    "t4pktc");
8853 	if (rc)
8854 		return (rc);
8855 
8856 	if (vi->flags & VI_INIT_DONE)
8857 		rc = EBUSY; /* cannot be changed once the queues are created */
8858 	else
8859 		vi->pktc_idx = idx;
8860 
8861 	end_synchronized_op(sc, LOCK_HELD);
8862 	return (rc);
8863 }
8864 
8865 static int
8866 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
8867 {
8868 	struct vi_info *vi = arg1;
8869 	struct adapter *sc = vi->adapter;
8870 	int qsize, rc;
8871 
8872 	qsize = vi->qsize_rxq;
8873 
8874 	rc = sysctl_handle_int(oidp, &qsize, 0, req);
8875 	if (rc != 0 || req->newptr == NULL)
8876 		return (rc);
8877 
8878 	if (qsize < 128 || (qsize & 7))
8879 		return (EINVAL);
8880 
8881 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8882 	    "t4rxqs");
8883 	if (rc)
8884 		return (rc);
8885 
8886 	if (vi->flags & VI_INIT_DONE)
8887 		rc = EBUSY; /* cannot be changed once the queues are created */
8888 	else
8889 		vi->qsize_rxq = qsize;
8890 
8891 	end_synchronized_op(sc, LOCK_HELD);
8892 	return (rc);
8893 }
8894 
8895 static int
8896 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
8897 {
8898 	struct vi_info *vi = arg1;
8899 	struct adapter *sc = vi->adapter;
8900 	int qsize, rc;
8901 
8902 	qsize = vi->qsize_txq;
8903 
8904 	rc = sysctl_handle_int(oidp, &qsize, 0, req);
8905 	if (rc != 0 || req->newptr == NULL)
8906 		return (rc);
8907 
8908 	if (qsize < 128 || qsize > 65536)
8909 		return (EINVAL);
8910 
8911 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8912 	    "t4txqs");
8913 	if (rc)
8914 		return (rc);
8915 
8916 	if (vi->flags & VI_INIT_DONE)
8917 		rc = EBUSY; /* cannot be changed once the queues are created */
8918 	else
8919 		vi->qsize_txq = qsize;
8920 
8921 	end_synchronized_op(sc, LOCK_HELD);
8922 	return (rc);
8923 }
8924 
8925 static int
8926 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
8927 {
8928 	struct port_info *pi = arg1;
8929 	struct adapter *sc = pi->adapter;
8930 	struct link_config *lc = &pi->link_cfg;
8931 	int rc;
8932 
8933 	if (req->newptr == NULL) {
8934 		struct sbuf *sb;
8935 		static char *bits = "\20\1RX\2TX\3AUTO";
8936 
8937 		sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8938 		if (sb == NULL)
8939 			return (ENOMEM);
8940 
8941 		if (lc->link_ok) {
8942 			sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
8943 			    (lc->requested_fc & PAUSE_AUTONEG), bits);
8944 		} else {
8945 			sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
8946 			    PAUSE_RX | PAUSE_AUTONEG), bits);
8947 		}
8948 		rc = sbuf_finish(sb);
8949 		sbuf_delete(sb);
8950 	} else {
8951 		char s[2];
8952 		int n;
8953 
8954 		s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
8955 		    PAUSE_AUTONEG));
8956 		s[1] = 0;
8957 
8958 		rc = sysctl_handle_string(oidp, s, sizeof(s), req);
8959 		if (rc != 0)
8960 			return(rc);
8961 
8962 		if (s[1] != 0)
8963 			return (EINVAL);
8964 		if (s[0] < '0' || s[0] > '9')
8965 			return (EINVAL);	/* not a number */
8966 		n = s[0] - '0';
8967 		if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
8968 			return (EINVAL);	/* some other bit is set too */
8969 
8970 		rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
8971 		    "t4PAUSE");
8972 		if (rc)
8973 			return (rc);
8974 		if (hw_all_ok(sc)) {
8975 			PORT_LOCK(pi);
8976 			lc->requested_fc = n;
8977 			fixup_link_config(pi);
8978 			if (pi->up_vis > 0)
8979 				rc = apply_link_config(pi);
8980 			set_current_media(pi);
8981 			PORT_UNLOCK(pi);
8982 		}
8983 		end_synchronized_op(sc, 0);
8984 	}
8985 
8986 	return (rc);
8987 }
8988 
8989 static int
8990 sysctl_link_fec(SYSCTL_HANDLER_ARGS)
8991 {
8992 	struct port_info *pi = arg1;
8993 	struct link_config *lc = &pi->link_cfg;
8994 	int rc;
8995 	struct sbuf *sb;
8996 
8997 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8998 	if (sb == NULL)
8999 		return (ENOMEM);
9000 	if (lc->link_ok)
9001 		sbuf_printf(sb, "%b", lc->fec, t4_fec_bits);
9002 	else
9003 		sbuf_printf(sb, "no link");
9004 	rc = sbuf_finish(sb);
9005 	sbuf_delete(sb);
9006 
9007 	return (rc);
9008 }
9009 
9010 static int
9011 sysctl_requested_fec(SYSCTL_HANDLER_ARGS)
9012 {
9013 	struct port_info *pi = arg1;
9014 	struct adapter *sc = pi->adapter;
9015 	struct link_config *lc = &pi->link_cfg;
9016 	int rc;
9017 	int8_t old = lc->requested_fec;
9018 
9019 	if (req->newptr == NULL) {
9020 		struct sbuf *sb;
9021 
9022 		sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
9023 		if (sb == NULL)
9024 			return (ENOMEM);
9025 
9026 		sbuf_printf(sb, "%b", old, t4_fec_bits);
9027 		rc = sbuf_finish(sb);
9028 		sbuf_delete(sb);
9029 	} else {
9030 		char s[8];
9031 		int n;
9032 
9033 		snprintf(s, sizeof(s), "%d", old == FEC_AUTO ? -1 :
9034 		    old & (M_FW_PORT_CAP32_FEC | FEC_MODULE));
9035 
9036 		rc = sysctl_handle_string(oidp, s, sizeof(s), req);
9037 		if (rc != 0)
9038 			return(rc);
9039 
9040 		n = strtol(&s[0], NULL, 0);
9041 		if (n < 0 || n & FEC_AUTO)
9042 			n = FEC_AUTO;
9043 		else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE))
9044 			return (EINVAL);/* some other bit is set too */
9045 
9046 		rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
9047 		    "t4reqf");
9048 		if (rc)
9049 			return (rc);
9050 		PORT_LOCK(pi);
9051 		if (lc->requested_fec != old) {
9052 			rc = EBUSY;
9053 			goto done;
9054 		}
9055 		if (n == FEC_AUTO)
9056 			lc->requested_fec = FEC_AUTO;
9057 		else if (n == 0 || n == FEC_NONE)
9058 			lc->requested_fec = FEC_NONE;
9059 		else {
9060 			if ((lc->pcaps |
9061 			    V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) !=
9062 			    lc->pcaps) {
9063 				rc = ENOTSUP;
9064 				goto done;
9065 			}
9066 			lc->requested_fec = n & (M_FW_PORT_CAP32_FEC |
9067 			    FEC_MODULE);
9068 		}
9069 		if (hw_all_ok(sc)) {
9070 			fixup_link_config(pi);
9071 			if (pi->up_vis > 0) {
9072 				rc = apply_link_config(pi);
9073 				if (rc != 0) {
9074 					lc->requested_fec = old;
9075 					if (rc == FW_EPROTO)
9076 						rc = ENOTSUP;
9077 				}
9078 			}
9079 		}
9080 done:
9081 		PORT_UNLOCK(pi);
9082 		end_synchronized_op(sc, 0);
9083 	}
9084 
9085 	return (rc);
9086 }
9087 
9088 static int
9089 sysctl_module_fec(SYSCTL_HANDLER_ARGS)
9090 {
9091 	struct port_info *pi = arg1;
9092 	struct adapter *sc = pi->adapter;
9093 	struct link_config *lc = &pi->link_cfg;
9094 	int rc;
9095 	int8_t fec;
9096 	struct sbuf *sb;
9097 
9098 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
9099 	if (sb == NULL)
9100 		return (ENOMEM);
9101 
9102 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) {
9103 		rc = EBUSY;
9104 		goto done;
9105 	}
9106 	if (!hw_all_ok(sc)) {
9107 		rc = ENXIO;
9108 		goto done;
9109 	}
9110 	PORT_LOCK(pi);
9111 	if (pi->up_vis == 0) {
9112 		/*
9113 		 * If all the interfaces are administratively down the firmware
9114 		 * does not report transceiver changes.  Refresh port info here.
9115 		 * This is the only reason we have a synchronized op in this
9116 		 * function.  Just PORT_LOCK would have been enough otherwise.
9117 		 */
9118 		t4_update_port_info(pi);
9119 	}
9120 
9121 	fec = lc->fec_hint;
9122 	if (pi->mod_type == FW_PORT_MOD_TYPE_NONE ||
9123 	    !fec_supported(lc->pcaps)) {
9124 		PORT_UNLOCK(pi);
9125 		sbuf_printf(sb, "n/a");
9126 	} else {
9127 		if (fec == 0)
9128 			fec = FEC_NONE;
9129 		PORT_UNLOCK(pi);
9130 		sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, t4_fec_bits);
9131 	}
9132 	rc = sbuf_finish(sb);
9133 done:
9134 	sbuf_delete(sb);
9135 	end_synchronized_op(sc, 0);
9136 
9137 	return (rc);
9138 }
9139 
9140 static int
9141 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
9142 {
9143 	struct port_info *pi = arg1;
9144 	struct adapter *sc = pi->adapter;
9145 	struct link_config *lc = &pi->link_cfg;
9146 	int rc, val;
9147 
9148 	if (lc->pcaps & FW_PORT_CAP32_ANEG)
9149 		val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
9150 	else
9151 		val = -1;
9152 	rc = sysctl_handle_int(oidp, &val, 0, req);
9153 	if (rc != 0 || req->newptr == NULL)
9154 		return (rc);
9155 	if (val == 0)
9156 		val = AUTONEG_DISABLE;
9157 	else if (val == 1)
9158 		val = AUTONEG_ENABLE;
9159 	else
9160 		val = AUTONEG_AUTO;
9161 
9162 	rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
9163 	    "t4aneg");
9164 	if (rc)
9165 		return (rc);
9166 	PORT_LOCK(pi);
9167 	if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
9168 		rc = ENOTSUP;
9169 		goto done;
9170 	}
9171 	lc->requested_aneg = val;
9172 	if (hw_all_ok(sc)) {
9173 		fixup_link_config(pi);
9174 		if (pi->up_vis > 0)
9175 			rc = apply_link_config(pi);
9176 		set_current_media(pi);
9177 	}
9178 done:
9179 	PORT_UNLOCK(pi);
9180 	end_synchronized_op(sc, 0);
9181 	return (rc);
9182 }
9183 
9184 static int
9185 sysctl_force_fec(SYSCTL_HANDLER_ARGS)
9186 {
9187 	struct port_info *pi = arg1;
9188 	struct adapter *sc = pi->adapter;
9189 	struct link_config *lc = &pi->link_cfg;
9190 	int rc, val;
9191 
9192 	val = lc->force_fec;
9193 	MPASS(val >= -1 && val <= 1);
9194 	rc = sysctl_handle_int(oidp, &val, 0, req);
9195 	if (rc != 0 || req->newptr == NULL)
9196 		return (rc);
9197 	if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC))
9198 		return (ENOTSUP);
9199 	if (val < -1 || val > 1)
9200 		return (EINVAL);
9201 
9202 	rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff");
9203 	if (rc)
9204 		return (rc);
9205 	PORT_LOCK(pi);
9206 	lc->force_fec = val;
9207 	if (hw_all_ok(sc)) {
9208 		fixup_link_config(pi);
9209 		if (pi->up_vis > 0)
9210 			rc = apply_link_config(pi);
9211 	}
9212 	PORT_UNLOCK(pi);
9213 	end_synchronized_op(sc, 0);
9214 	return (rc);
9215 }
9216 
9217 static int
9218 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
9219 {
9220 	struct adapter *sc = arg1;
9221 	int rc, reg = arg2;
9222 	uint64_t val;
9223 
9224 	mtx_lock(&sc->reg_lock);
9225 	if (hw_off_limits(sc))
9226 		rc = ENXIO;
9227 	else {
9228 		rc = 0;
9229 		val = t4_read_reg64(sc, reg);
9230 	}
9231 	mtx_unlock(&sc->reg_lock);
9232 	if (rc == 0)
9233 		rc = sysctl_handle_64(oidp, &val, 0, req);
9234 	return (rc);
9235 }
9236 
9237 static int
9238 sysctl_handle_t4_portstat64(SYSCTL_HANDLER_ARGS)
9239 {
9240 	struct port_info *pi = arg1;
9241 	struct adapter *sc = pi->adapter;
9242 	int rc, i, reg = arg2;
9243 	uint64_t val;
9244 
9245 	mtx_lock(&sc->reg_lock);
9246 	if (hw_off_limits(sc))
9247 		rc = ENXIO;
9248 	else {
9249 		val = 0;
9250 		for (i = 0; i < sc->params.tp.lb_nchan; i++) {
9251 			val += t4_read_reg64(sc,
9252 			    t4_port_reg(sc, pi->tx_chan + i, reg));
9253 		}
9254 		rc = 0;
9255 	}
9256 	mtx_unlock(&sc->reg_lock);
9257 	if (rc == 0)
9258 		rc = sysctl_handle_64(oidp, &val, 0, req);
9259 	return (rc);
9260 }
9261 
9262 static int
9263 sysctl_temperature(SYSCTL_HANDLER_ARGS)
9264 {
9265 	struct adapter *sc = arg1;
9266 	int rc, t;
9267 	uint32_t param, val;
9268 
9269 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
9270 	if (rc)
9271 		return (rc);
9272 	if (!hw_all_ok(sc))
9273 		rc = ENXIO;
9274 	else {
9275 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9276 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
9277 		    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
9278 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
9279 	}
9280 	end_synchronized_op(sc, 0);
9281 	if (rc)
9282 		return (rc);
9283 
9284 	/* unknown is returned as 0 but we display -1 in that case */
9285 	t = val == 0 ? -1 : val;
9286 
9287 	rc = sysctl_handle_int(oidp, &t, 0, req);
9288 	return (rc);
9289 }
9290 
9291 static int
9292 sysctl_vdd(SYSCTL_HANDLER_ARGS)
9293 {
9294 	struct adapter *sc = arg1;
9295 	int rc;
9296 	uint32_t param, val;
9297 
9298 	if (sc->params.core_vdd == 0) {
9299 		rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
9300 		    "t4vdd");
9301 		if (rc)
9302 			return (rc);
9303 		if (!hw_all_ok(sc))
9304 			rc = ENXIO;
9305 		else {
9306 			param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9307 			    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
9308 			    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
9309 			rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1,
9310 			    &param, &val);
9311 		}
9312 		end_synchronized_op(sc, 0);
9313 		if (rc)
9314 			return (rc);
9315 		sc->params.core_vdd = val;
9316 	}
9317 
9318 	return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req));
9319 }
9320 
9321 static int
9322 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS)
9323 {
9324 	struct adapter *sc = arg1;
9325 	int rc, v;
9326 	uint32_t param, val;
9327 
9328 	v = sc->sensor_resets;
9329 	rc = sysctl_handle_int(oidp, &v, 0, req);
9330 	if (rc != 0 || req->newptr == NULL || v <= 0)
9331 		return (rc);
9332 
9333 	if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) ||
9334 	    chip_id(sc) < CHELSIO_T5)
9335 		return (ENOTSUP);
9336 
9337 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst");
9338 	if (rc)
9339 		return (rc);
9340 	if (!hw_all_ok(sc))
9341 		rc = ENXIO;
9342 	else {
9343 		param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9344 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
9345 		    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR));
9346 		val = 1;
9347 		rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
9348 	}
9349 	end_synchronized_op(sc, 0);
9350 	if (rc == 0)
9351 		sc->sensor_resets++;
9352 	return (rc);
9353 }
9354 
9355 static int
9356 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
9357 {
9358 	struct adapter *sc = arg1;
9359 	struct sbuf *sb;
9360 	int rc;
9361 	uint32_t param, val;
9362 	uint8_t coreid = (uint8_t)arg2;
9363 
9364 	KASSERT(coreid < sc->params.ncores,
9365 	    ("%s: bad coreid %u\n", __func__, coreid));
9366 
9367 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
9368 	if (rc)
9369 		return (rc);
9370 	if (!hw_all_ok(sc))
9371 		rc = ENXIO;
9372 	else {
9373 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9374 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD) |
9375 		    V_FW_PARAMS_PARAM_Y(coreid);
9376 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
9377 	}
9378 	end_synchronized_op(sc, 0);
9379 	if (rc)
9380 		return (rc);
9381 
9382 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9383 	if (sb == NULL)
9384 		return (ENOMEM);
9385 
9386 	if (val == 0xffffffff) {
9387 		/* Only debug and custom firmwares report load averages. */
9388 		sbuf_printf(sb, "not available");
9389 	} else {
9390 		sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
9391 		    (val >> 16) & 0xff);
9392 	}
9393 	rc = sbuf_finish(sb);
9394 	sbuf_delete(sb);
9395 
9396 	return (rc);
9397 }
9398 
9399 static int
9400 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
9401 {
9402 	struct adapter *sc = arg1;
9403 	struct sbuf *sb;
9404 	int rc, i;
9405 	uint16_t incr[NMTUS][NCCTRL_WIN];
9406 	static const char *dec_fac[] = {
9407 		"0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
9408 		"0.9375"
9409 	};
9410 
9411 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9412 	if (sb == NULL)
9413 		return (ENOMEM);
9414 
9415 	rc = 0;
9416 	mtx_lock(&sc->reg_lock);
9417 	if (hw_off_limits(sc))
9418 		rc = ENXIO;
9419 	else
9420 		t4_read_cong_tbl(sc, incr);
9421 	mtx_unlock(&sc->reg_lock);
9422 	if (rc)
9423 		goto done;
9424 
9425 	for (i = 0; i < NCCTRL_WIN; ++i) {
9426 		sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
9427 		    incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
9428 		    incr[5][i], incr[6][i], incr[7][i]);
9429 		sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
9430 		    incr[8][i], incr[9][i], incr[10][i], incr[11][i],
9431 		    incr[12][i], incr[13][i], incr[14][i], incr[15][i],
9432 		    sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
9433 	}
9434 
9435 	rc = sbuf_finish(sb);
9436 done:
9437 	sbuf_delete(sb);
9438 	return (rc);
9439 }
9440 
9441 static int
9442 sysctl_cim_ibq(SYSCTL_HANDLER_ARGS)
9443 {
9444 	struct adapter *sc = arg1;
9445 	struct sbuf *sb;
9446 	int rc, i, n, qid, coreid;
9447 	uint32_t *buf, *p;
9448 
9449 	qid = arg2 & 0xffff;
9450 	coreid = arg2 >> 16;
9451 
9452 	KASSERT(qid >= 0 && qid < sc->chip_params->cim_num_ibq,
9453 	    ("%s: bad ibq qid %d\n", __func__, qid));
9454 	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
9455 	    ("%s: bad coreid %d\n", __func__, coreid));
9456 
9457 	n = 4 * CIM_IBQ_SIZE;
9458 	buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
9459 	mtx_lock(&sc->reg_lock);
9460 	if (hw_off_limits(sc))
9461 		rc = -ENXIO;
9462 	else
9463 		rc = t4_read_cim_ibq_core(sc, coreid, qid, buf, n);
9464 	mtx_unlock(&sc->reg_lock);
9465 	if (rc < 0) {
9466 		rc = -rc;
9467 		goto done;
9468 	}
9469 	n = rc * sizeof(uint32_t);	/* rc has # of words actually read */
9470 
9471 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9472 	if (sb == NULL) {
9473 		rc = ENOMEM;
9474 		goto done;
9475 	}
9476 	for (i = 0, p = buf; i < n; i += 16, p += 4)
9477 		sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
9478 		    p[2], p[3]);
9479 	rc = sbuf_finish(sb);
9480 	sbuf_delete(sb);
9481 done:
9482 	free(buf, M_CXGBE);
9483 	return (rc);
9484 }
9485 
9486 static int
9487 sysctl_cim_obq(SYSCTL_HANDLER_ARGS)
9488 {
9489 	struct adapter *sc = arg1;
9490 	struct sbuf *sb;
9491 	int rc, i, n, qid, coreid;
9492 	uint32_t *buf, *p;
9493 
9494 	qid = arg2 & 0xffff;
9495 	coreid = arg2 >> 16;
9496 
9497 	KASSERT(qid >= 0 && qid < sc->chip_params->cim_num_obq,
9498 	    ("%s: bad obq qid %d\n", __func__, qid));
9499 	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
9500 	    ("%s: bad coreid %d\n", __func__, coreid));
9501 
9502 	n = 6 * CIM_OBQ_SIZE * 4;
9503 	buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
9504 	mtx_lock(&sc->reg_lock);
9505 	if (hw_off_limits(sc))
9506 		rc = -ENXIO;
9507 	else
9508 		rc = t4_read_cim_obq_core(sc, coreid, qid, buf, n);
9509 	mtx_unlock(&sc->reg_lock);
9510 	if (rc < 0) {
9511 		rc = -rc;
9512 		goto done;
9513 	}
9514 	n = rc * sizeof(uint32_t);	/* rc has # of words actually read */
9515 
9516 	rc = sysctl_wire_old_buffer(req, 0);
9517 	if (rc != 0)
9518 		goto done;
9519 
9520 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9521 	if (sb == NULL) {
9522 		rc = ENOMEM;
9523 		goto done;
9524 	}
9525 	for (i = 0, p = buf; i < n; i += 16, p += 4)
9526 		sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
9527 		    p[2], p[3]);
9528 	rc = sbuf_finish(sb);
9529 	sbuf_delete(sb);
9530 done:
9531 	free(buf, M_CXGBE);
9532 	return (rc);
9533 }
9534 
9535 static void
9536 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
9537 {
9538 	uint32_t *p;
9539 
9540 	sbuf_printf(sb, "Status   Data      PC%s",
9541 	    cfg & F_UPDBGLACAPTPCONLY ? "" :
9542 	    "     LS0Stat  LS0Addr             LS0Data");
9543 
9544 	for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
9545 		if (cfg & F_UPDBGLACAPTPCONLY) {
9546 			sbuf_printf(sb, "\n  %02x   %08x %08x", p[5] & 0xff,
9547 			    p[6], p[7]);
9548 			sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x",
9549 			    (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
9550 			    p[4] & 0xff, p[5] >> 8);
9551 			sbuf_printf(sb, "\n  %02x   %x%07x %x%07x",
9552 			    (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
9553 			    p[1] & 0xf, p[2] >> 4);
9554 		} else {
9555 			sbuf_printf(sb,
9556 			    "\n  %02x   %x%07x %x%07x %08x %08x "
9557 			    "%08x%08x%08x%08x",
9558 			    (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
9559 			    p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
9560 			    p[6], p[7]);
9561 		}
9562 	}
9563 }
9564 
9565 static void
9566 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
9567 {
9568 	uint32_t *p;
9569 
9570 	sbuf_printf(sb, "Status   Inst    Data      PC%s",
9571 	    cfg & F_UPDBGLACAPTPCONLY ? "" :
9572 	    "     LS0Stat  LS0Addr  LS0Data  LS1Stat  LS1Addr  LS1Data");
9573 
9574 	for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
9575 		if (cfg & F_UPDBGLACAPTPCONLY) {
9576 			sbuf_printf(sb, "\n  %02x   %08x %08x %08x",
9577 			    p[3] & 0xff, p[2], p[1], p[0]);
9578 			sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x %02x%06x",
9579 			    (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
9580 			    p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
9581 			sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x",
9582 			    (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
9583 			    p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
9584 			    p[6] >> 16);
9585 		} else {
9586 			sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x "
9587 			    "%08x %08x %08x %08x %08x %08x",
9588 			    (p[9] >> 16) & 0xff,
9589 			    p[9] & 0xffff, p[8] >> 16,
9590 			    p[8] & 0xffff, p[7] >> 16,
9591 			    p[7] & 0xffff, p[6] >> 16,
9592 			    p[2], p[1], p[0], p[5], p[4], p[3]);
9593 		}
9594 	}
9595 }
9596 
9597 static int
9598 sbuf_cim_la(struct adapter *sc, int coreid, struct sbuf *sb, int flags)
9599 {
9600 	uint32_t cfg, *buf;
9601 	int rc;
9602 
9603 	MPASS(flags == M_WAITOK || flags == M_NOWAIT);
9604 	buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
9605 	    M_ZERO | flags);
9606 	if (buf == NULL)
9607 		return (ENOMEM);
9608 
9609 	mtx_lock(&sc->reg_lock);
9610 	if (hw_off_limits(sc))
9611 		rc = ENXIO;
9612 	else {
9613 		rc = -t4_cim_read_core(sc, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
9614 		    &cfg);
9615 		if (rc == 0)
9616 			rc = -t4_cim_read_la_core(sc, coreid, buf, NULL);
9617 	}
9618 	mtx_unlock(&sc->reg_lock);
9619 	if (rc == 0) {
9620 		if (chip_id(sc) < CHELSIO_T6)
9621 			sbuf_cim_la4(sc, sb, buf, cfg);
9622 		else
9623 			sbuf_cim_la6(sc, sb, buf, cfg);
9624 	}
9625 	free(buf, M_CXGBE);
9626 	return (rc);
9627 }
9628 
9629 static int
9630 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
9631 {
9632 	struct adapter *sc = arg1;
9633 	int coreid = arg2;
9634 	struct sbuf *sb;
9635 	int rc;
9636 
9637 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9638 	if (sb == NULL)
9639 		return (ENOMEM);
9640 
9641 	rc = sbuf_cim_la(sc, coreid, sb, M_WAITOK);
9642 	if (rc == 0)
9643 		rc = sbuf_finish(sb);
9644 	sbuf_delete(sb);
9645 	return (rc);
9646 }
9647 
9648 static void
9649 dump_cim_regs(struct adapter *sc)
9650 {
9651 	log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n",
9652 	    device_get_nameunit(sc->dev),
9653 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
9654 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
9655 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2),
9656 	    t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN),
9657 	    t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA));
9658 	log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n",
9659 	    device_get_nameunit(sc->dev),
9660 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
9661 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
9662 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800),
9663 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800),
9664 	    t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN));
9665 }
9666 
9667 static void
9668 dump_cimla(struct adapter *sc)
9669 {
9670 	struct sbuf sb;
9671 	int rc;
9672 
9673 	if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
9674 		log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n",
9675 		    device_get_nameunit(sc->dev));
9676 		return;
9677 	}
9678 	rc = sbuf_cim_la(sc, 0, &sb, M_WAITOK);
9679 	if (rc == 0) {
9680 		rc = sbuf_finish(&sb);
9681 		if (rc == 0) {
9682 			log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n",
9683 			    device_get_nameunit(sc->dev), sbuf_data(&sb));
9684 		}
9685 	}
9686 	sbuf_delete(&sb);
9687 }
9688 
9689 void
9690 t4_os_cim_err(struct adapter *sc)
9691 {
9692 	atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
9693 }
9694 
9695 static int
9696 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
9697 {
9698 	struct adapter *sc = arg1;
9699 	u_int i;
9700 	struct sbuf *sb;
9701 	uint32_t *buf, *p;
9702 	int rc;
9703 
9704 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9705 	if (sb == NULL)
9706 		return (ENOMEM);
9707 
9708 	buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
9709 	    M_ZERO | M_WAITOK);
9710 
9711 	rc = 0;
9712 	mtx_lock(&sc->reg_lock);
9713 	if (hw_off_limits(sc))
9714 		rc = ENXIO;
9715 	else
9716 		t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
9717 	mtx_unlock(&sc->reg_lock);
9718 	if (rc)
9719 		goto done;
9720 
9721 	p = buf;
9722 	for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9723 		sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
9724 		    p[1], p[0]);
9725 	}
9726 
9727 	sbuf_printf(sb, "\n\nCnt ID Tag UE       Data       RDY VLD");
9728 	for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9729 		sbuf_printf(sb, "\n%3u %2u  %x   %u %08x%08x  %u   %u",
9730 		    (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
9731 		    (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
9732 		    (p[1] >> 2) | ((p[2] & 3) << 30),
9733 		    (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
9734 		    p[0] & 1);
9735 	}
9736 	rc = sbuf_finish(sb);
9737 done:
9738 	sbuf_delete(sb);
9739 	free(buf, M_CXGBE);
9740 	return (rc);
9741 }
9742 
9743 static int
9744 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
9745 {
9746 	struct adapter *sc = arg1;
9747 	u_int i;
9748 	struct sbuf *sb;
9749 	uint32_t *buf, *p;
9750 	int rc;
9751 
9752 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9753 	if (sb == NULL)
9754 		return (ENOMEM);
9755 
9756 	buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
9757 	    M_ZERO | M_WAITOK);
9758 
9759 	rc = 0;
9760 	mtx_lock(&sc->reg_lock);
9761 	if (hw_off_limits(sc))
9762 		rc = ENXIO;
9763 	else
9764 		t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
9765 	mtx_unlock(&sc->reg_lock);
9766 	if (rc)
9767 		goto done;
9768 
9769 	p = buf;
9770 	sbuf_printf(sb, "Cntl ID DataBE   Addr                 Data");
9771 	for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9772 		sbuf_printf(sb, "\n %02x  %02x  %04x  %08x %08x%08x%08x%08x",
9773 		    (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
9774 		    p[4], p[3], p[2], p[1], p[0]);
9775 	}
9776 
9777 	sbuf_printf(sb, "\n\nCntl ID               Data");
9778 	for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9779 		sbuf_printf(sb, "\n %02x  %02x %08x%08x%08x%08x",
9780 		    (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
9781 	}
9782 
9783 	rc = sbuf_finish(sb);
9784 done:
9785 	sbuf_delete(sb);
9786 	free(buf, M_CXGBE);
9787 	return (rc);
9788 }
9789 
9790 static int
9791 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
9792 {
9793 	struct adapter *sc = arg1;
9794 	struct sbuf *sb;
9795 	int rc, i;
9796 	uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9797 	uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9798 	uint16_t thres[CIM_NUM_IBQ];
9799 	uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
9800 	uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
9801 	u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
9802 	static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
9803 		"TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",	/* ibq's */
9804 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",	/* obq's */
9805 		"SGE0-RX", "SGE1-RX"	/* additional obq's (T5 onwards) */
9806 	};
9807 
9808 	MPASS(chip_id(sc) < CHELSIO_T7);
9809 
9810 	cim_num_obq = sc->chip_params->cim_num_obq;
9811 	if (is_t4(sc)) {
9812 		ibq_rdaddr = A_UP_IBQ_0_RDADDR;
9813 		obq_rdaddr = A_UP_OBQ_0_REALADDR;
9814 	} else {
9815 		ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
9816 		obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
9817 	}
9818 	nq = CIM_NUM_IBQ + cim_num_obq;
9819 
9820 	mtx_lock(&sc->reg_lock);
9821 	if (hw_off_limits(sc))
9822 		rc = ENXIO;
9823 	else {
9824 		rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
9825 		if (rc == 0) {
9826 			rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq,
9827 			    obq_wr);
9828 			if (rc == 0)
9829 				t4_read_cimq_cfg(sc, base, size, thres);
9830 		}
9831 	}
9832 	mtx_unlock(&sc->reg_lock);
9833 	if (rc)
9834 		return (rc);
9835 
9836 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9837 	if (sb == NULL)
9838 		return (ENOMEM);
9839 
9840 	sbuf_printf(sb,
9841 	    "  Queue  Base  Size Thres  RdPtr WrPtr  SOP  EOP Avail");
9842 
9843 	for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
9844 		sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
9845 		    qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
9846 		    G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9847 		    G_QUEREMFLITS(p[2]) * 16);
9848 	for ( ; i < nq; i++, p += 4, wr += 2)
9849 		sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u", qname[i],
9850 		    base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
9851 		    wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9852 		    G_QUEREMFLITS(p[2]) * 16);
9853 
9854 	rc = sbuf_finish(sb);
9855 	sbuf_delete(sb);
9856 
9857 	return (rc);
9858 }
9859 
9860 static int
9861 sysctl_cim_qcfg_t7(SYSCTL_HANDLER_ARGS)
9862 {
9863 	struct adapter *sc = arg1;
9864 	u_int coreid = arg2;
9865 	struct sbuf *sb;
9866 	int rc, i;
9867 	u_int addr;
9868 	uint16_t base[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
9869 	uint16_t size[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
9870 	uint16_t thres[CIM_NUM_IBQ_T7];
9871 	uint32_t obq_wr[2 * CIM_NUM_OBQ_T7], *wr = obq_wr;
9872 	uint32_t stat[4 * (CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7)], *p = stat;
9873 	static const char * const qname_ibq_t7[] = {
9874 		"TP0", "TP1", "TP2", "TP3", "ULP", "SGE0", "SGE1", "NC-SI",
9875 		"RSVD", "IPC1", "IPC2", "IPC3", "IPC4", "IPC5", "IPC6", "IPC7",
9876 	};
9877 	static const char * const qname_obq_t7[] = {
9878 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", "SGE0-RX",
9879 		"RSVD", "RSVD", "IPC1", "IPC2", "IPC3", "IPC4", "IPC5",
9880 		"IPC6", "IPC7"
9881 	};
9882 	static const char * const qname_ibq_sec_t7[] = {
9883 		"TP0", "TP1", "TP2", "TP3", "ULP", "SGE0", "RSVD", "RSVD",
9884 		"RSVD", "IPC0", "RSVD", "RSVD", "RSVD", "RSVD",	"RSVD", "RSVD",
9885 	};
9886 	static const char * const qname_obq_sec_t7[] = {
9887 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "RSVD", "SGE0-RX",
9888 		"RSVD", "RSVD", "IPC0", "RSVD", "RSVD", "RSVD", "RSVD",
9889 		"RSVD", "RSVD",
9890 	};
9891 
9892 	MPASS(chip_id(sc) >= CHELSIO_T7);
9893 
9894 	mtx_lock(&sc->reg_lock);
9895 	if (hw_off_limits(sc))
9896 		rc = ENXIO;
9897 	else {
9898 		rc = -t4_cim_read_core(sc, 1, coreid,
9899 		    A_T7_UP_IBQ_0_SHADOW_RDADDR, 4 * CIM_NUM_IBQ_T7, stat);
9900 		if (rc != 0)
9901 			goto unlock;
9902 
9903 		rc = -t4_cim_read_core(sc, 1, coreid,
9904 		    A_T7_UP_OBQ_0_SHADOW_RDADDR, 4 * CIM_NUM_OBQ_T7,
9905 		    &stat[4 * CIM_NUM_IBQ_T7]);
9906 		if (rc != 0)
9907 			goto unlock;
9908 
9909 		addr = A_T7_UP_OBQ_0_SHADOW_REALADDR;
9910 		for (i = 0; i < CIM_NUM_OBQ_T7 * 2; i++, addr += 8) {
9911 			rc = -t4_cim_read_core(sc, 1, coreid, addr, 1,
9912 			    &obq_wr[i]);
9913 			if (rc != 0)
9914 				goto unlock;
9915 		}
9916 		t4_read_cimq_cfg_core(sc, coreid, base, size, thres);
9917 	}
9918 unlock:
9919 	mtx_unlock(&sc->reg_lock);
9920 	if (rc)
9921 		return (rc);
9922 
9923 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9924 	if (sb == NULL)
9925 		return (ENOMEM);
9926 
9927 	sbuf_printf(sb,
9928 	    "  Queue  Base  Size Thres  RdPtr WrPtr  SOP  EOP Avail");
9929 
9930 	for (i = 0; i < CIM_NUM_IBQ_T7; i++, p += 4) {
9931 		if (!size[i])
9932 			continue;
9933 
9934 		sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
9935 		    coreid == 0 ? qname_ibq_t7[i] : qname_ibq_sec_t7[i],
9936 		    base[i], size[i], thres[i], G_IBQRDADDR(p[0]) & 0xfff,
9937 		    G_IBQWRADDR(p[1]) & 0xfff, G_QUESOPCNT(p[3]),
9938 		    G_QUEEOPCNT(p[3]), G_T7_QUEREMFLITS(p[2]) * 16);
9939 	}
9940 
9941 	for ( ; i < CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7; i++, p += 4, wr += 2) {
9942 		if (!size[i])
9943 			continue;
9944 
9945 		sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u",
9946 		    coreid == 0 ? qname_obq_t7[i - CIM_NUM_IBQ_T7] :
9947 		    qname_obq_sec_t7[i - CIM_NUM_IBQ_T7],
9948 		    base[i], size[i], G_QUERDADDR(p[0]) & 0xfff,
9949 		    wr[0] << 1, G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9950 		    G_T7_QUEREMFLITS(p[2]) * 16);
9951 	}
9952 
9953 	rc = sbuf_finish(sb);
9954 	sbuf_delete(sb);
9955 	return (rc);
9956 }
9957 
9958 static int
9959 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
9960 {
9961 	struct adapter *sc = arg1;
9962 	struct sbuf *sb;
9963 	int rc;
9964 	struct tp_cpl_stats stats;
9965 
9966 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9967 	if (sb == NULL)
9968 		return (ENOMEM);
9969 
9970 	rc = 0;
9971 	mtx_lock(&sc->reg_lock);
9972 	if (hw_off_limits(sc))
9973 		rc = ENXIO;
9974 	else
9975 		t4_tp_get_cpl_stats(sc, &stats, 0);
9976 	mtx_unlock(&sc->reg_lock);
9977 	if (rc)
9978 		goto done;
9979 
9980 	if (sc->chip_params->nchan > 2) {
9981 		sbuf_printf(sb, "                 channel 0  channel 1"
9982 		    "  channel 2  channel 3");
9983 		sbuf_printf(sb, "\nCPL requests:   %10u %10u %10u %10u",
9984 		    stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
9985 		sbuf_printf(sb, "\nCPL responses:  %10u %10u %10u %10u",
9986 		    stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
9987 	} else {
9988 		sbuf_printf(sb, "                 channel 0  channel 1");
9989 		sbuf_printf(sb, "\nCPL requests:   %10u %10u",
9990 		    stats.req[0], stats.req[1]);
9991 		sbuf_printf(sb, "\nCPL responses:  %10u %10u",
9992 		    stats.rsp[0], stats.rsp[1]);
9993 	}
9994 
9995 	rc = sbuf_finish(sb);
9996 done:
9997 	sbuf_delete(sb);
9998 	return (rc);
9999 }
10000 
10001 static int
10002 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
10003 {
10004 	struct adapter *sc = arg1;
10005 	struct sbuf *sb;
10006 	int rc;
10007 	struct tp_usm_stats stats;
10008 
10009 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10010 	if (sb == NULL)
10011 		return (ENOMEM);
10012 
10013 	rc = 0;
10014 	mtx_lock(&sc->reg_lock);
10015 	if (hw_off_limits(sc))
10016 		rc = ENXIO;
10017 	else
10018 		t4_get_usm_stats(sc, &stats, 1);
10019 	mtx_unlock(&sc->reg_lock);
10020 	if (rc == 0) {
10021 		sbuf_printf(sb, "Frames: %u\n", stats.frames);
10022 		sbuf_printf(sb, "Octets: %ju\n", stats.octets);
10023 		sbuf_printf(sb, "Drops:  %u", stats.drops);
10024 		rc = sbuf_finish(sb);
10025 	}
10026 	sbuf_delete(sb);
10027 
10028 	return (rc);
10029 }
10030 
10031 static int
10032 sysctl_tid_stats(SYSCTL_HANDLER_ARGS)
10033 {
10034 	struct adapter *sc = arg1;
10035 	struct sbuf *sb;
10036 	int rc;
10037 	struct tp_tid_stats stats;
10038 
10039 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10040 	if (sb == NULL)
10041 		return (ENOMEM);
10042 
10043 	rc = 0;
10044 	mtx_lock(&sc->reg_lock);
10045 	if (hw_off_limits(sc))
10046 		rc = ENXIO;
10047 	else
10048 		t4_tp_get_tid_stats(sc, &stats, 1);
10049 	mtx_unlock(&sc->reg_lock);
10050 	if (rc == 0) {
10051 		sbuf_printf(sb, "Delete:     %u\n", stats.del);
10052 		sbuf_printf(sb, "Invalidate: %u\n", stats.inv);
10053 		sbuf_printf(sb, "Active:     %u\n", stats.act);
10054 		sbuf_printf(sb, "Passive:    %u", stats.pas);
10055 		rc = sbuf_finish(sb);
10056 	}
10057 	sbuf_delete(sb);
10058 
10059 	return (rc);
10060 }
10061 
10062 static const char * const devlog_level_strings[] = {
10063 	[FW_DEVLOG_LEVEL_EMERG]		= "EMERG",
10064 	[FW_DEVLOG_LEVEL_CRIT]		= "CRIT",
10065 	[FW_DEVLOG_LEVEL_ERR]		= "ERR",
10066 	[FW_DEVLOG_LEVEL_NOTICE]	= "NOTICE",
10067 	[FW_DEVLOG_LEVEL_INFO]		= "INFO",
10068 	[FW_DEVLOG_LEVEL_DEBUG]		= "DEBUG"
10069 };
10070 
10071 static const char * const devlog_facility_strings[] = {
10072 	[FW_DEVLOG_FACILITY_CORE]	= "CORE",
10073 	[FW_DEVLOG_FACILITY_CF]		= "CF",
10074 	[FW_DEVLOG_FACILITY_SCHED]	= "SCHED",
10075 	[FW_DEVLOG_FACILITY_TIMER]	= "TIMER",
10076 	[FW_DEVLOG_FACILITY_RES]	= "RES",
10077 	[FW_DEVLOG_FACILITY_HW]		= "HW",
10078 	[FW_DEVLOG_FACILITY_FLR]	= "FLR",
10079 	[FW_DEVLOG_FACILITY_DMAQ]	= "DMAQ",
10080 	[FW_DEVLOG_FACILITY_PHY]	= "PHY",
10081 	[FW_DEVLOG_FACILITY_MAC]	= "MAC",
10082 	[FW_DEVLOG_FACILITY_PORT]	= "PORT",
10083 	[FW_DEVLOG_FACILITY_VI]		= "VI",
10084 	[FW_DEVLOG_FACILITY_FILTER]	= "FILTER",
10085 	[FW_DEVLOG_FACILITY_ACL]	= "ACL",
10086 	[FW_DEVLOG_FACILITY_TM]		= "TM",
10087 	[FW_DEVLOG_FACILITY_QFC]	= "QFC",
10088 	[FW_DEVLOG_FACILITY_DCB]	= "DCB",
10089 	[FW_DEVLOG_FACILITY_ETH]	= "ETH",
10090 	[FW_DEVLOG_FACILITY_OFLD]	= "OFLD",
10091 	[FW_DEVLOG_FACILITY_RI]		= "RI",
10092 	[FW_DEVLOG_FACILITY_ISCSI]	= "ISCSI",
10093 	[FW_DEVLOG_FACILITY_FCOE]	= "FCOE",
10094 	[FW_DEVLOG_FACILITY_FOISCSI]	= "FOISCSI",
10095 	[FW_DEVLOG_FACILITY_FOFCOE]	= "FOFCOE",
10096 	[FW_DEVLOG_FACILITY_CHNET]	= "CHNET",
10097 };
10098 
10099 static int
10100 sbuf_devlog(struct adapter *sc, int coreid, struct sbuf *sb, int flags)
10101 {
10102 	int i, j, rc, nentries, first = 0;
10103 	struct devlog_params *dparams = &sc->params.devlog;
10104 	struct fw_devlog_e *buf, *e;
10105 	uint32_t addr, size;
10106 	uint64_t ftstamp = UINT64_MAX;
10107 
10108 	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
10109 	    ("%s: bad coreid %d\n", __func__, coreid));
10110 
10111 	if (dparams->addr == 0)
10112 		return (ENXIO);
10113 
10114 	size = dparams->size / sc->params.ncores;
10115 	addr = dparams->addr + coreid * size;
10116 
10117 	MPASS(flags == M_WAITOK || flags == M_NOWAIT);
10118 	buf = malloc(size, M_CXGBE, M_ZERO | flags);
10119 	if (buf == NULL)
10120 		return (ENOMEM);
10121 
10122 	mtx_lock(&sc->reg_lock);
10123 	if (hw_off_limits(sc))
10124 		rc = ENXIO;
10125 	else
10126 		rc = read_via_memwin(sc, 1, addr, (void *)buf, size);
10127 	mtx_unlock(&sc->reg_lock);
10128 	if (rc != 0)
10129 		goto done;
10130 
10131 	nentries = size / sizeof(struct fw_devlog_e);
10132 	for (i = 0; i < nentries; i++) {
10133 		e = &buf[i];
10134 
10135 		if (e->timestamp == 0)
10136 			break;	/* end */
10137 
10138 		e->timestamp = be64toh(e->timestamp);
10139 		e->seqno = be32toh(e->seqno);
10140 		for (j = 0; j < 8; j++)
10141 			e->params[j] = be32toh(e->params[j]);
10142 
10143 		if (e->timestamp < ftstamp) {
10144 			ftstamp = e->timestamp;
10145 			first = i;
10146 		}
10147 	}
10148 
10149 	if (buf[first].timestamp == 0)
10150 		goto done;	/* nothing in the log */
10151 
10152 	sbuf_printf(sb, "%10s  %15s  %8s  %8s  %s\n",
10153 	    "Seq#", "Tstamp", "Level", "Facility", "Message");
10154 
10155 	i = first;
10156 	do {
10157 		e = &buf[i];
10158 		if (e->timestamp == 0)
10159 			break;	/* end */
10160 
10161 		sbuf_printf(sb, "%10d  %15ju  %8s  %8s  ",
10162 		    e->seqno, e->timestamp,
10163 		    (e->level < nitems(devlog_level_strings) ?
10164 			devlog_level_strings[e->level] : "UNKNOWN"),
10165 		    (e->facility < nitems(devlog_facility_strings) ?
10166 			devlog_facility_strings[e->facility] : "UNKNOWN"));
10167 		sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
10168 		    e->params[2], e->params[3], e->params[4],
10169 		    e->params[5], e->params[6], e->params[7]);
10170 
10171 		if (++i == nentries)
10172 			i = 0;
10173 	} while (i != first);
10174 done:
10175 	free(buf, M_CXGBE);
10176 	return (rc);
10177 }
10178 
10179 static int
10180 sysctl_devlog(SYSCTL_HANDLER_ARGS)
10181 {
10182 	struct adapter *sc = arg1;
10183 	int rc, i, coreid = arg2;
10184 	struct sbuf *sb;
10185 
10186 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10187 	if (sb == NULL)
10188 		return (ENOMEM);
10189 	if (coreid == -1) {
10190 		/* -1 means all cores */
10191 		for (i = rc = 0; i < sc->params.ncores && rc == 0; i++) {
10192 			if (sc->params.ncores > 0)
10193 				sbuf_printf(sb, "=== CIM core %u ===\n", i);
10194 			rc = sbuf_devlog(sc, i, sb, M_WAITOK);
10195 		}
10196 	} else {
10197 		KASSERT(coreid >= 0 && coreid < sc->params.ncores,
10198 		    ("%s: bad coreid %d\n", __func__, coreid));
10199 		rc = sbuf_devlog(sc, coreid, sb, M_WAITOK);
10200 	}
10201 	if (rc == 0)
10202 		rc = sbuf_finish(sb);
10203 	sbuf_delete(sb);
10204 	return (rc);
10205 }
10206 
10207 static void
10208 dump_devlog(struct adapter *sc)
10209 {
10210 	int rc, i;
10211 	struct sbuf sb;
10212 
10213 	if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
10214 		log(LOG_DEBUG, "%s: failed to generate devlog dump.\n",
10215 		    device_get_nameunit(sc->dev));
10216 		return;
10217 	}
10218 	for (i = rc = 0; i < sc->params.ncores && rc == 0; i++) {
10219 		if (sc->params.ncores > 0)
10220 			sbuf_printf(&sb, "=== CIM core %u ===\n", i);
10221 		rc = sbuf_devlog(sc, i, &sb, M_WAITOK);
10222 	}
10223 	if (rc == 0) {
10224 		sbuf_finish(&sb);
10225 		log(LOG_DEBUG, "%s: device log follows.\n%s",
10226 		    device_get_nameunit(sc->dev), sbuf_data(&sb));
10227 	}
10228 	sbuf_delete(&sb);
10229 }
10230 
10231 static int
10232 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
10233 {
10234 	struct adapter *sc = arg1;
10235 	struct sbuf *sb;
10236 	int rc;
10237 	struct tp_fcoe_stats stats[MAX_NCHAN];
10238 	int i, nchan = sc->chip_params->nchan;
10239 
10240 	rc = 0;
10241 	mtx_lock(&sc->reg_lock);
10242 	if (hw_off_limits(sc))
10243 		rc = ENXIO;
10244 	else {
10245 		for (i = 0; i < nchan; i++)
10246 			t4_get_fcoe_stats(sc, i, &stats[i], 1);
10247 	}
10248 	mtx_unlock(&sc->reg_lock);
10249 	if (rc != 0)
10250 		return (rc);
10251 
10252 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10253 	if (sb == NULL)
10254 		return (ENOMEM);
10255 
10256 	if (nchan > 2) {
10257 		sbuf_printf(sb, "                   channel 0        channel 1"
10258 		    "        channel 2        channel 3");
10259 		sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju %16ju %16ju",
10260 		    stats[0].octets_ddp, stats[1].octets_ddp,
10261 		    stats[2].octets_ddp, stats[3].octets_ddp);
10262 		sbuf_printf(sb, "\nframesDDP:  %16u %16u %16u %16u",
10263 		    stats[0].frames_ddp, stats[1].frames_ddp,
10264 		    stats[2].frames_ddp, stats[3].frames_ddp);
10265 		sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
10266 		    stats[0].frames_drop, stats[1].frames_drop,
10267 		    stats[2].frames_drop, stats[3].frames_drop);
10268 	} else {
10269 		sbuf_printf(sb, "                   channel 0        channel 1");
10270 		sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju",
10271 		    stats[0].octets_ddp, stats[1].octets_ddp);
10272 		sbuf_printf(sb, "\nframesDDP:  %16u %16u",
10273 		    stats[0].frames_ddp, stats[1].frames_ddp);
10274 		sbuf_printf(sb, "\nframesDrop: %16u %16u",
10275 		    stats[0].frames_drop, stats[1].frames_drop);
10276 	}
10277 
10278 	rc = sbuf_finish(sb);
10279 	sbuf_delete(sb);
10280 
10281 	return (rc);
10282 }
10283 
10284 static int
10285 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
10286 {
10287 	struct adapter *sc = arg1;
10288 	struct sbuf *sb;
10289 	int rc, i;
10290 	unsigned int map, kbps, ipg, mode;
10291 	unsigned int pace_tab[NTX_SCHED];
10292 
10293 	sb = sbuf_new_for_sysctl(NULL, NULL, 512, req);
10294 	if (sb == NULL)
10295 		return (ENOMEM);
10296 
10297 	mtx_lock(&sc->reg_lock);
10298 	if (hw_off_limits(sc)) {
10299 		mtx_unlock(&sc->reg_lock);
10300 		rc = ENXIO;
10301 		goto done;
10302 	}
10303 
10304 	map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
10305 	mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
10306 	t4_read_pace_tbl(sc, pace_tab);
10307 	mtx_unlock(&sc->reg_lock);
10308 
10309 	sbuf_printf(sb, "Scheduler  Mode   Channel  Rate (Kbps)   "
10310 	    "Class IPG (0.1 ns)   Flow IPG (us)");
10311 
10312 	for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
10313 		t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
10314 		sbuf_printf(sb, "\n    %u      %-5s     %u     ", i,
10315 		    (mode & (1 << i)) ? "flow" : "class", map & 3);
10316 		if (kbps)
10317 			sbuf_printf(sb, "%9u     ", kbps);
10318 		else
10319 			sbuf_printf(sb, " disabled     ");
10320 
10321 		if (ipg)
10322 			sbuf_printf(sb, "%13u        ", ipg);
10323 		else
10324 			sbuf_printf(sb, "     disabled        ");
10325 
10326 		if (pace_tab[i])
10327 			sbuf_printf(sb, "%10u", pace_tab[i]);
10328 		else
10329 			sbuf_printf(sb, "  disabled");
10330 	}
10331 	rc = sbuf_finish(sb);
10332 done:
10333 	sbuf_delete(sb);
10334 	return (rc);
10335 }
10336 
10337 static int
10338 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
10339 {
10340 	struct adapter *sc = arg1;
10341 	struct sbuf *sb;
10342 	int rc, i, j;
10343 	uint64_t *p0, *p1;
10344 	struct lb_port_stats s[2];
10345 	static const char *stat_name[] = {
10346 		"OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
10347 		"UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
10348 		"Frames128To255:", "Frames256To511:", "Frames512To1023:",
10349 		"Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
10350 		"BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
10351 		"BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
10352 		"BG2FramesTrunc:", "BG3FramesTrunc:"
10353 	};
10354 
10355 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10356 	if (sb == NULL)
10357 		return (ENOMEM);
10358 
10359 	memset(s, 0, sizeof(s));
10360 
10361 	rc = 0;
10362 	for (i = 0; i < sc->chip_params->nchan; i += 2) {
10363 		mtx_lock(&sc->reg_lock);
10364 		if (hw_off_limits(sc))
10365 			rc = ENXIO;
10366 		else {
10367 			t4_get_lb_stats(sc, i, &s[0]);
10368 			t4_get_lb_stats(sc, i + 1, &s[1]);
10369 		}
10370 		mtx_unlock(&sc->reg_lock);
10371 		if (rc != 0)
10372 			break;
10373 
10374 		p0 = &s[0].octets;
10375 		p1 = &s[1].octets;
10376 		sbuf_printf(sb, "%s                       Loopback %u"
10377 		    "           Loopback %u", i == 0 ? "" : "\n", i, i + 1);
10378 
10379 		for (j = 0; j < nitems(stat_name); j++)
10380 			sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
10381 				   *p0++, *p1++);
10382 	}
10383 
10384 	if (rc == 0)
10385 		rc = sbuf_finish(sb);
10386 	sbuf_delete(sb);
10387 
10388 	return (rc);
10389 }
10390 
10391 static int
10392 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
10393 {
10394 	int rc = 0;
10395 	struct port_info *pi = arg1;
10396 	struct link_config *lc = &pi->link_cfg;
10397 	struct sbuf *sb;
10398 
10399 	sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
10400 	if (sb == NULL)
10401 		return (ENOMEM);
10402 
10403 	if (lc->link_ok || lc->link_down_rc == 255)
10404 		sbuf_printf(sb, "n/a");
10405 	else
10406 		sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
10407 
10408 	rc = sbuf_finish(sb);
10409 	sbuf_delete(sb);
10410 
10411 	return (rc);
10412 }
10413 
10414 struct mem_desc {
10415 	uint64_t base;
10416 	uint64_t limit;
10417 	u_int idx;
10418 };
10419 
10420 static int
10421 mem_desc_cmp(const void *a, const void *b)
10422 {
10423 	const uint64_t v1 = ((const struct mem_desc *)a)->base;
10424 	const uint64_t v2 = ((const struct mem_desc *)b)->base;
10425 
10426 	if (v1 < v2)
10427 		return (-1);
10428 	else if (v1 > v2)
10429 		return (1);
10430 
10431 	return (0);
10432 }
10433 
10434 static void
10435 mem_region_show(struct sbuf *sb, const char *name, uint64_t from, uint64_t to)
10436 {
10437 	uintmax_t size;
10438 
10439 	if (from == to)
10440 		return;
10441 
10442 	size = to - from + 1;
10443 	if (size == 0)
10444 		return;
10445 
10446 	if (from > UINT32_MAX || to > UINT32_MAX)
10447 		sbuf_printf(sb, "%-18s 0x%012jx-0x%012jx [%ju]\n", name,
10448 		    (uintmax_t)from, (uintmax_t)to, size);
10449 	else
10450 		sbuf_printf(sb, "%-18s 0x%08jx-0x%08jx [%ju]\n", name,
10451 		    (uintmax_t)from, (uintmax_t)to, size);
10452 }
10453 
10454 static int
10455 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
10456 {
10457 	struct adapter *sc = arg1;
10458 	struct sbuf *sb;
10459 	int rc, i, n, nchan;
10460 	uint32_t lo, hi, used, free, alloc;
10461 	static const char *memory[] = {
10462 		"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:"
10463 	};
10464 	static const char *region[] = {
10465 		"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
10466 		"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
10467 		"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
10468 		"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
10469 		"RQUDP region:", "PBL region:", "TXPBL region:",
10470 		"TLSKey region:", "RRQ region:", "NVMe STAG region:",
10471 		"NVMe RQ region:", "NVMe RXPBL region:", "NVMe TPT region:",
10472 		"NVMe TXPBL region:", "DBVFIFO region:", "ULPRX state:",
10473 		"ULPTX state:", "RoCE RRQ region:", "On-chip queues:",
10474 	};
10475 	struct mem_desc avail[4];
10476 	struct mem_desc mem[nitems(region) + 3];	/* up to 3 holes */
10477 	struct mem_desc *md;
10478 
10479 	rc = sysctl_wire_old_buffer(req, 0);
10480 	if (rc != 0)
10481 		return (rc);
10482 
10483 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10484 	if (sb == NULL)
10485 		return (ENOMEM);
10486 
10487 	for (i = 0; i < nitems(mem); i++) {
10488 		mem[i].limit = 0;
10489 		mem[i].idx = i;
10490 	}
10491 
10492 	mtx_lock(&sc->reg_lock);
10493 	if (hw_off_limits(sc)) {
10494 		rc = ENXIO;
10495 		goto done;
10496 	}
10497 
10498 	/* Find and sort the populated memory ranges */
10499 	i = 0;
10500 	lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
10501 	if (lo & F_EDRAM0_ENABLE) {
10502 		hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
10503 		if (chip_id(sc) >= CHELSIO_T7) {
10504 			avail[i].base = (uint64_t)G_T7_EDRAM0_BASE(hi) << 20;
10505 			avail[i].limit = avail[i].base +
10506 			    (G_T7_EDRAM0_SIZE(hi) << 20);
10507 		} else {
10508 			avail[i].base = (uint64_t)G_EDRAM0_BASE(hi) << 20;
10509 			avail[i].limit = avail[i].base +
10510 			    (G_EDRAM0_SIZE(hi) << 20);
10511 		}
10512 		avail[i].idx = 0;
10513 		i++;
10514 	}
10515 	if (lo & F_EDRAM1_ENABLE) {
10516 		hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
10517 		if (chip_id(sc) >= CHELSIO_T7) {
10518 			avail[i].base = (uint64_t)G_T7_EDRAM1_BASE(hi) << 20;
10519 			avail[i].limit = avail[i].base +
10520 			    (G_T7_EDRAM1_SIZE(hi) << 20);
10521 		} else {
10522 			avail[i].base = (uint64_t)G_EDRAM1_BASE(hi) << 20;
10523 			avail[i].limit = avail[i].base +
10524 			    (G_EDRAM1_SIZE(hi) << 20);
10525 		}
10526 		avail[i].idx = 1;
10527 		i++;
10528 	}
10529 	if (lo & F_EXT_MEM_ENABLE) {
10530 		switch (chip_id(sc)) {
10531 		case CHELSIO_T4:
10532 		case CHELSIO_T6:
10533 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
10534 			avail[i].base = (uint64_t)G_EXT_MEM_BASE(hi) << 20;
10535 			avail[i].limit = avail[i].base +
10536 			    (G_EXT_MEM_SIZE(hi) << 20);
10537 			avail[i].idx = 2;
10538 			break;
10539 		case CHELSIO_T5:
10540 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY0_BAR);
10541 			avail[i].base = (uint64_t)G_EXT_MEM0_BASE(hi) << 20;
10542 			avail[i].limit = avail[i].base +
10543 			    (G_EXT_MEM0_SIZE(hi) << 20);
10544 			avail[i].idx = 3;	/* Call it MC0 for T5 */
10545 			break;
10546 		default:
10547 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY0_BAR);
10548 			avail[i].base = (uint64_t)G_T7_EXT_MEM0_BASE(hi) << 20;
10549 			avail[i].limit = avail[i].base +
10550 			    (G_T7_EXT_MEM0_SIZE(hi) << 20);
10551 			avail[i].idx = 3;	/* Call it MC0 for T7+ */
10552 			break;
10553 		}
10554 		i++;
10555 	}
10556 	if (lo & F_EXT_MEM1_ENABLE && !(lo & F_MC_SPLIT)) {
10557 		/* Only T5 and T7+ have 2 MCs. */
10558 		MPASS(is_t5(sc) || chip_id(sc) >= CHELSIO_T7);
10559 
10560 		hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
10561 		if (chip_id(sc) >= CHELSIO_T7) {
10562 			avail[i].base = (uint64_t)G_T7_EXT_MEM1_BASE(hi) << 20;
10563 			avail[i].limit = avail[i].base +
10564 			    (G_T7_EXT_MEM1_SIZE(hi) << 20);
10565 		} else {
10566 			avail[i].base = (uint64_t)G_EXT_MEM1_BASE(hi) << 20;
10567 			avail[i].limit = avail[i].base +
10568 			    (G_EXT_MEM1_SIZE(hi) << 20);
10569 		}
10570 		avail[i].idx = 4;
10571 		i++;
10572 	}
10573 	if (lo & F_HMA_MUX) {
10574 		/* Only T6+ have HMA. */
10575 		MPASS(chip_id(sc) >= CHELSIO_T6);
10576 
10577 		if (chip_id(sc) >= CHELSIO_T7) {
10578 			hi = t4_read_reg(sc, A_MA_HOST_MEMORY_BAR);
10579 			avail[i].base = (uint64_t)G_HMATARGETBASE(hi) << 20;
10580 			avail[i].limit = avail[i].base +
10581 			    (G_T7_HMA_SIZE(hi) << 20);
10582 		} else {
10583 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
10584 			avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
10585 			avail[i].limit = avail[i].base +
10586 			    (G_EXT_MEM1_SIZE(hi) << 20);
10587 		}
10588 		avail[i].idx = 5;
10589 		i++;
10590 	}
10591 	MPASS(i <= nitems(avail));
10592 	if (!i)                                    /* no memory available */
10593 		goto done;
10594 	qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
10595 
10596 	md = &mem[0];
10597 	(md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
10598 	(md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
10599 	(md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
10600 	(md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10601 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
10602 	(md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
10603 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
10604 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
10605 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
10606 
10607 	/* the next few have explicit upper bounds */
10608 	md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
10609 	md->limit = md->base - 1 +
10610 		    t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
10611 		    G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
10612 	md++;
10613 
10614 	md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
10615 	md->limit = md->base - 1 +
10616 		    t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
10617 		    G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
10618 	md++;
10619 
10620 	if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
10621 		if (chip_id(sc) <= CHELSIO_T5)
10622 			md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
10623 		else
10624 			md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
10625 		md->limit = 0;
10626 	} else {
10627 		md->base = 0;
10628 		md->idx = nitems(region);  /* hide it */
10629 	}
10630 	md++;
10631 
10632 #define ulp_region(reg) do {\
10633 		const u_int shift = chip_id(sc) >= CHELSIO_T7 ? 4 : 0; \
10634 		md->base = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT) << shift; \
10635 		md->limit = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) << shift; \
10636 		md->limit += (1 << shift) - 1; \
10637 		md++; \
10638 	} while (0)
10639 
10640 #define	hide_ulp_region() do { \
10641 		md->base = 0; \
10642 		md->idx = nitems(region); \
10643 		md++; \
10644 	} while (0)
10645 
10646 	ulp_region(RX_ISCSI);
10647 	ulp_region(RX_TDDP);
10648 	ulp_region(TX_TPT);
10649 	ulp_region(RX_STAG);
10650 	ulp_region(RX_RQ);
10651 	if (chip_id(sc) < CHELSIO_T7)
10652 		ulp_region(RX_RQUDP);
10653 	else
10654 		hide_ulp_region();
10655 	ulp_region(RX_PBL);
10656 	ulp_region(TX_PBL);
10657 	if (chip_id(sc) >= CHELSIO_T6)
10658 		ulp_region(RX_TLS_KEY);
10659 	else
10660 		hide_ulp_region();
10661 	if (chip_id(sc) >= CHELSIO_T7) {
10662 		ulp_region(RX_RRQ);
10663 		ulp_region(RX_NVME_TCP_STAG);
10664 		ulp_region(RX_NVME_TCP_RQ);
10665 		ulp_region(RX_NVME_TCP_PBL);
10666 		ulp_region(TX_NVME_TCP_TPT);
10667 		ulp_region(TX_NVME_TCP_PBL);
10668 	} else {
10669 		hide_ulp_region();
10670 		hide_ulp_region();
10671 		hide_ulp_region();
10672 		hide_ulp_region();
10673 		hide_ulp_region();
10674 		hide_ulp_region();
10675 	}
10676 #undef ulp_region
10677 #undef hide_ulp_region
10678 
10679 	md->base = 0;
10680 	if (is_t4(sc))
10681 		md->idx = nitems(region);
10682 	else {
10683 		uint32_t size = 0;
10684 		uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
10685 		uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
10686 
10687 		if (is_t5(sc)) {
10688 			if (sge_ctrl & F_VFIFO_ENABLE)
10689 				size = fifo_size << 2;
10690 		} else
10691 			size = G_T6_DBVFIFO_SIZE(fifo_size) << 6;
10692 
10693 		if (size) {
10694 			md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR);
10695 			md->limit = md->base + size - 1;
10696 		} else
10697 			md->idx = nitems(region);
10698 	}
10699 	md++;
10700 
10701 	md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
10702 	md->limit = 0;
10703 	md++;
10704 	md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
10705 	md->limit = 0;
10706 	md++;
10707 
10708 	if (chip_id(sc) >= CHELSIO_T7) {
10709 		t4_tp_pio_read(sc, &lo, 1, A_TP_ROCE_RRQ_BASE, false);
10710 		md->base = lo;
10711 	} else {
10712 		md->base = 0;
10713 		md->idx = nitems(region);
10714 	}
10715 	md++;
10716 
10717 	md->base = sc->vres.ocq.start;
10718 	if (sc->vres.ocq.size)
10719 		md->limit = md->base + sc->vres.ocq.size - 1;
10720 	else
10721 		md->idx = nitems(region);  /* hide it */
10722 	md++;
10723 
10724 	/* add any address-space holes, there can be up to 3 */
10725 	for (n = 0; n < i - 1; n++)
10726 		if (avail[n].limit < avail[n + 1].base)
10727 			(md++)->base = avail[n].limit;
10728 	if (avail[n].limit)
10729 		(md++)->base = avail[n].limit;
10730 
10731 	n = md - mem;
10732 	MPASS(n <= nitems(mem));
10733 	qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
10734 
10735 	for (lo = 0; lo < i; lo++)
10736 		mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
10737 				avail[lo].limit - 1);
10738 
10739 	sbuf_printf(sb, "\n");
10740 	for (i = 0; i < n; i++) {
10741 		if (mem[i].idx >= nitems(region))
10742 			continue;                        /* skip holes */
10743 		if (!mem[i].limit)
10744 			mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
10745 		mem_region_show(sb, region[mem[i].idx], mem[i].base,
10746 				mem[i].limit);
10747 	}
10748 
10749 	lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
10750 	hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
10751 	if (hi != lo  - 1) {
10752 		sbuf_printf(sb, "\n");
10753 		mem_region_show(sb, "uP RAM:", lo, hi);
10754 	}
10755 
10756 	lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
10757 	hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
10758 	if (hi != lo  - 1)
10759 		mem_region_show(sb, "uP Extmem2:", lo, hi);
10760 
10761 	lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
10762 	if (chip_id(sc) >= CHELSIO_T7)
10763 		nchan = 1 << G_T7_PMRXNUMCHN(lo);
10764 	else
10765 		nchan = lo & F_PMRXNUMCHN ? 2 : 1;
10766 	for (i = 0, free = 0; i < nchan; i++)
10767 		free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT));
10768 	sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n",
10769 		   G_PMRXMAXPAGE(lo), free,
10770 		   t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, nchan);
10771 
10772 	lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
10773 	hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
10774 	if (chip_id(sc) >= CHELSIO_T7)
10775 		nchan = 1 << G_T7_PMTXNUMCHN(lo);
10776 	else
10777 		nchan = 1 << G_PMTXNUMCHN(lo);
10778 	for (i = 0, free = 0; i < nchan; i++)
10779 		free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT));
10780 	sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n",
10781 		   G_PMTXMAXPAGE(lo), free,
10782 		   hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
10783 		   hi >= (1 << 20) ? 'M' : 'K', nchan);
10784 	sbuf_printf(sb, "%u p-structs (%u free)\n",
10785 		   t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT),
10786 		   G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT)));
10787 
10788 	for (i = 0; i < 4; i++) {
10789 		if (chip_id(sc) > CHELSIO_T5)
10790 			lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
10791 		else
10792 			lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
10793 		if (is_t5(sc)) {
10794 			used = G_T5_USED(lo);
10795 			alloc = G_T5_ALLOC(lo);
10796 		} else {
10797 			used = G_USED(lo);
10798 			alloc = G_ALLOC(lo);
10799 		}
10800 		/* For T6+ these are MAC buffer groups */
10801 		sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
10802 		    i, used, alloc);
10803 	}
10804 	for (i = 0; i < sc->chip_params->nchan; i++) {
10805 		if (chip_id(sc) > CHELSIO_T5)
10806 			lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
10807 		else
10808 			lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
10809 		if (is_t5(sc)) {
10810 			used = G_T5_USED(lo);
10811 			alloc = G_T5_ALLOC(lo);
10812 		} else {
10813 			used = G_USED(lo);
10814 			alloc = G_ALLOC(lo);
10815 		}
10816 		/* For T6+ these are MAC buffer groups */
10817 		sbuf_printf(sb,
10818 		    "\nLoopback %d using %u pages out of %u allocated",
10819 		    i, used, alloc);
10820 	}
10821 done:
10822 	mtx_unlock(&sc->reg_lock);
10823 	if (rc == 0)
10824 		rc = sbuf_finish(sb);
10825 	sbuf_delete(sb);
10826 	return (rc);
10827 }
10828 
10829 static inline void
10830 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
10831 {
10832 	*mask = x | y;
10833 	y = htobe64(y);
10834 	memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
10835 }
10836 
10837 static int
10838 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
10839 {
10840 	struct adapter *sc = arg1;
10841 	struct sbuf *sb;
10842 	int rc, i;
10843 
10844 	MPASS(chip_id(sc) <= CHELSIO_T5);
10845 
10846 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10847 	if (sb == NULL)
10848 		return (ENOMEM);
10849 
10850 	sbuf_printf(sb,
10851 	    "Idx  Ethernet address     Mask     Vld Ports PF"
10852 	    "  VF              Replication             P0 P1 P2 P3  ML");
10853 	rc = 0;
10854 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
10855 		uint64_t tcamx, tcamy, mask;
10856 		uint32_t cls_lo, cls_hi;
10857 		uint8_t addr[ETHER_ADDR_LEN];
10858 
10859 		mtx_lock(&sc->reg_lock);
10860 		if (hw_off_limits(sc))
10861 			rc = ENXIO;
10862 		else {
10863 			tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
10864 			tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
10865 		}
10866 		mtx_unlock(&sc->reg_lock);
10867 		if (rc != 0)
10868 			break;
10869 		if (tcamx & tcamy)
10870 			continue;
10871 		tcamxy2valmask(tcamx, tcamy, addr, &mask);
10872 		mtx_lock(&sc->reg_lock);
10873 		if (hw_off_limits(sc))
10874 			rc = ENXIO;
10875 		else {
10876 			cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
10877 			cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
10878 		}
10879 		mtx_unlock(&sc->reg_lock);
10880 		if (rc != 0)
10881 			break;
10882 		sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
10883 			   "  %c   %#x%4u%4d", i, addr[0], addr[1], addr[2],
10884 			   addr[3], addr[4], addr[5], (uintmax_t)mask,
10885 			   (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
10886 			   G_PORTMAP(cls_hi), G_PF(cls_lo),
10887 			   (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
10888 
10889 		if (cls_lo & F_REPLICATE) {
10890 			struct fw_ldst_cmd ldst_cmd;
10891 
10892 			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10893 			ldst_cmd.op_to_addrspace =
10894 			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
10895 				F_FW_CMD_REQUEST | F_FW_CMD_READ |
10896 				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
10897 			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
10898 			ldst_cmd.u.mps.rplc.fid_idx =
10899 			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
10900 				V_FW_LDST_CMD_IDX(i));
10901 
10902 			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
10903 			    "t4mps");
10904 			if (rc)
10905 				break;
10906 			if (hw_off_limits(sc))
10907 				rc = ENXIO;
10908 			else
10909 				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
10910 				    sizeof(ldst_cmd), &ldst_cmd);
10911 			end_synchronized_op(sc, 0);
10912 			if (rc != 0)
10913 				break;
10914 			else {
10915 				sbuf_printf(sb, " %08x %08x %08x %08x",
10916 				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
10917 				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
10918 				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
10919 				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
10920 			}
10921 		} else
10922 			sbuf_printf(sb, "%36s", "");
10923 
10924 		sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
10925 		    G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
10926 		    G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
10927 	}
10928 
10929 	if (rc)
10930 		(void) sbuf_finish(sb);
10931 	else
10932 		rc = sbuf_finish(sb);
10933 	sbuf_delete(sb);
10934 
10935 	return (rc);
10936 }
10937 
10938 static int
10939 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
10940 {
10941 	struct adapter *sc = arg1;
10942 	struct sbuf *sb;
10943 	int rc, i;
10944 
10945 	MPASS(chip_id(sc) == CHELSIO_T6);
10946 
10947 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10948 	if (sb == NULL)
10949 		return (ENOMEM);
10950 
10951 	sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
10952 	    "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
10953 	    "                           Replication"
10954 	    "                                    P0 P1 P2 P3  ML");
10955 
10956 	rc = 0;
10957 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
10958 		uint8_t dip_hit, vlan_vld, lookup_type, port_num;
10959 		uint16_t ivlan;
10960 		uint64_t tcamx, tcamy, val, mask;
10961 		uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
10962 		uint8_t addr[ETHER_ADDR_LEN];
10963 
10964 		ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
10965 		if (i < 256)
10966 			ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
10967 		else
10968 			ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
10969 		mtx_lock(&sc->reg_lock);
10970 		if (hw_off_limits(sc))
10971 			rc = ENXIO;
10972 		else {
10973 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
10974 			val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
10975 			tcamy = G_DMACH(val) << 32;
10976 			tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
10977 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
10978 		}
10979 		mtx_unlock(&sc->reg_lock);
10980 		if (rc != 0)
10981 			break;
10982 
10983 		lookup_type = G_DATALKPTYPE(data2);
10984 		port_num = G_DATAPORTNUM(data2);
10985 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
10986 			/* Inner header VNI */
10987 			vniy = ((data2 & F_DATAVIDH2) << 23) |
10988 				       (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
10989 			dip_hit = data2 & F_DATADIPHIT;
10990 			vlan_vld = 0;
10991 		} else {
10992 			vniy = 0;
10993 			dip_hit = 0;
10994 			vlan_vld = data2 & F_DATAVIDH2;
10995 			ivlan = G_VIDL(val);
10996 		}
10997 
10998 		ctl |= V_CTLXYBITSEL(1);
10999 		mtx_lock(&sc->reg_lock);
11000 		if (hw_off_limits(sc))
11001 			rc = ENXIO;
11002 		else {
11003 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
11004 			val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
11005 			tcamx = G_DMACH(val) << 32;
11006 			tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
11007 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
11008 		}
11009 		mtx_unlock(&sc->reg_lock);
11010 		if (rc != 0)
11011 			break;
11012 
11013 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11014 			/* Inner header VNI mask */
11015 			vnix = ((data2 & F_DATAVIDH2) << 23) |
11016 			       (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
11017 		} else
11018 			vnix = 0;
11019 
11020 		if (tcamx & tcamy)
11021 			continue;
11022 		tcamxy2valmask(tcamx, tcamy, addr, &mask);
11023 
11024 		mtx_lock(&sc->reg_lock);
11025 		if (hw_off_limits(sc))
11026 			rc = ENXIO;
11027 		else {
11028 			cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
11029 			cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
11030 		}
11031 		mtx_unlock(&sc->reg_lock);
11032 		if (rc != 0)
11033 			break;
11034 
11035 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11036 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11037 			    "%012jx %06x %06x    -    -   %3c"
11038 			    "        I  %4x   %3c   %#x%4u%4d", i, addr[0],
11039 			    addr[1], addr[2], addr[3], addr[4], addr[5],
11040 			    (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
11041 			    port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11042 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11043 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11044 		} else {
11045 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11046 			    "%012jx    -       -   ", i, addr[0], addr[1],
11047 			    addr[2], addr[3], addr[4], addr[5],
11048 			    (uintmax_t)mask);
11049 
11050 			if (vlan_vld)
11051 				sbuf_printf(sb, "%4u   Y     ", ivlan);
11052 			else
11053 				sbuf_printf(sb, "  -    N     ");
11054 
11055 			sbuf_printf(sb, "-      %3c  %4x   %3c   %#x%4u%4d",
11056 			    lookup_type ? 'I' : 'O', port_num,
11057 			    cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11058 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11059 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11060 		}
11061 
11062 
11063 		if (cls_lo & F_T6_REPLICATE) {
11064 			struct fw_ldst_cmd ldst_cmd;
11065 
11066 			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
11067 			ldst_cmd.op_to_addrspace =
11068 			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
11069 				F_FW_CMD_REQUEST | F_FW_CMD_READ |
11070 				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
11071 			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
11072 			ldst_cmd.u.mps.rplc.fid_idx =
11073 			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
11074 				V_FW_LDST_CMD_IDX(i));
11075 
11076 			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
11077 			    "t6mps");
11078 			if (rc)
11079 				break;
11080 			if (hw_off_limits(sc))
11081 				rc = ENXIO;
11082 			else
11083 				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
11084 				    sizeof(ldst_cmd), &ldst_cmd);
11085 			end_synchronized_op(sc, 0);
11086 			if (rc != 0)
11087 				break;
11088 			else {
11089 				sbuf_printf(sb, " %08x %08x %08x %08x"
11090 				    " %08x %08x %08x %08x",
11091 				    be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
11092 				    be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
11093 				    be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
11094 				    be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
11095 				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
11096 				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
11097 				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
11098 				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
11099 			}
11100 		} else
11101 			sbuf_printf(sb, "%72s", "");
11102 
11103 		sbuf_printf(sb, "%4u%3u%3u%3u %#x",
11104 		    G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
11105 		    G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
11106 		    (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
11107 	}
11108 
11109 	if (rc)
11110 		(void) sbuf_finish(sb);
11111 	else
11112 		rc = sbuf_finish(sb);
11113 	sbuf_delete(sb);
11114 
11115 	return (rc);
11116 }
11117 
11118 static int
11119 sysctl_mps_tcam_t7(SYSCTL_HANDLER_ARGS)
11120 {
11121 	struct adapter *sc = arg1;
11122 	struct sbuf *sb;
11123 	int rc, i;
11124 
11125 	MPASS(chip_id(sc) >= CHELSIO_T7);
11126 
11127 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11128 	if (sb == NULL)
11129 		return (ENOMEM);
11130 
11131 	sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
11132 	    "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
11133 	    "                           Replication"
11134 	    "                                    P0 P1 P2 P3  ML");
11135 
11136 	rc = 0;
11137 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
11138 		uint8_t dip_hit, vlan_vld, lookup_type, port_num;
11139 		uint16_t ivlan;
11140 		uint64_t tcamx, tcamy, val, mask;
11141 		uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
11142 		uint8_t addr[ETHER_ADDR_LEN];
11143 
11144 		/* Read tcamy */
11145 		ctl = (V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0));
11146 		if (chip_rev(sc) == 0) {
11147 			if (i < 256)
11148 				ctl |= V_CTLTCAMINDEX(i) | V_T7_CTLTCAMSEL(0);
11149 			else
11150 				ctl |= V_CTLTCAMINDEX(i - 256) | V_T7_CTLTCAMSEL(1);
11151 		} else {
11152 #if 0
11153 			ctl = (V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0));
11154 #endif
11155 			if (i < 512)
11156 				ctl |= V_CTLTCAMINDEX(i) | V_T7_CTLTCAMSEL(0);
11157 			else if (i < 1024)
11158 				ctl |= V_CTLTCAMINDEX(i - 512) | V_T7_CTLTCAMSEL(1);
11159 			else
11160 				ctl |= V_CTLTCAMINDEX(i - 1024) | V_T7_CTLTCAMSEL(2);
11161 		}
11162 
11163 		mtx_lock(&sc->reg_lock);
11164 		if (hw_off_limits(sc))
11165 			rc = ENXIO;
11166 		else {
11167 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
11168 			val = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA1_REQ_ID1);
11169 			tcamy = G_DMACH(val) << 32;
11170 			tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA0_REQ_ID1);
11171 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA2_REQ_ID1);
11172 		}
11173 		mtx_unlock(&sc->reg_lock);
11174 		if (rc != 0)
11175 			break;
11176 
11177 		lookup_type = G_DATALKPTYPE(data2);
11178 		port_num = G_DATAPORTNUM(data2);
11179 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11180 			/* Inner header VNI */
11181 			vniy = (((data2 & F_DATAVIDH2) |
11182 			    G_DATAVIDH1(data2)) << 16) | G_VIDL(val);
11183 			dip_hit = data2 & F_DATADIPHIT;
11184 			vlan_vld = 0;
11185 		} else {
11186 			vniy = 0;
11187 			dip_hit = 0;
11188 			vlan_vld = data2 & F_DATAVIDH2;
11189 			ivlan = G_VIDL(val);
11190 		}
11191 
11192 		ctl |= V_CTLXYBITSEL(1);
11193 		mtx_lock(&sc->reg_lock);
11194 		if (hw_off_limits(sc))
11195 			rc = ENXIO;
11196 		else {
11197 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
11198 			val = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA1_REQ_ID1);
11199 			tcamx = G_DMACH(val) << 32;
11200 			tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA0_REQ_ID1);
11201 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA2_REQ_ID1);
11202 		}
11203 		mtx_unlock(&sc->reg_lock);
11204 		if (rc != 0)
11205 			break;
11206 
11207 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11208 			/* Inner header VNI mask */
11209 			vnix = (((data2 & F_DATAVIDH2) |
11210 			    G_DATAVIDH1(data2)) << 16) | G_VIDL(val);
11211 		} else
11212 			vnix = 0;
11213 
11214 		if (tcamx & tcamy)
11215 			continue;
11216 		tcamxy2valmask(tcamx, tcamy, addr, &mask);
11217 
11218 		mtx_lock(&sc->reg_lock);
11219 		if (hw_off_limits(sc))
11220 			rc = ENXIO;
11221 		else {
11222 			if (chip_rev(sc) == 0) {
11223 				cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
11224 				cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
11225 			} else {
11226 				t4_write_reg(sc, A_MPS_CLS_SRAM_H,
11227 				    V_SRAMWRN(0) | V_SRAMINDEX(i));
11228 				cls_lo = t4_read_reg(sc, A_MPS_CLS_SRAM_L);
11229 				cls_hi = t4_read_reg(sc, A_MPS_CLS_SRAM_H);
11230 			}
11231 		}
11232 		mtx_unlock(&sc->reg_lock);
11233 		if (rc != 0)
11234 			break;
11235 
11236 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11237 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11238 			    "%012jx %06x %06x    -    -   %3c"
11239 			    "        I  %4x   %3c   %#x%4u%4d", i, addr[0],
11240 			    addr[1], addr[2], addr[3], addr[4], addr[5],
11241 			    (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
11242 			    port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11243 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11244 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11245 		} else {
11246 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11247 			    "%012jx    -       -   ", i, addr[0], addr[1],
11248 			    addr[2], addr[3], addr[4], addr[5],
11249 			    (uintmax_t)mask);
11250 
11251 			if (vlan_vld)
11252 				sbuf_printf(sb, "%4u   Y     ", ivlan);
11253 			else
11254 				sbuf_printf(sb, "  -    N     ");
11255 
11256 			sbuf_printf(sb, "-      %3c  %4x   %3c   %#x%4u%4d",
11257 			    lookup_type ? 'I' : 'O', port_num,
11258 			    cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11259 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11260 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11261 		}
11262 
11263 		if (cls_lo & F_T6_REPLICATE) {
11264 			struct fw_ldst_cmd ldst_cmd;
11265 
11266 			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
11267 			ldst_cmd.op_to_addrspace =
11268 			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
11269 				F_FW_CMD_REQUEST | F_FW_CMD_READ |
11270 				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
11271 			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
11272 			ldst_cmd.u.mps.rplc.fid_idx =
11273 			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
11274 				V_FW_LDST_CMD_IDX(i));
11275 
11276 			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
11277 			    "t6mps");
11278 			if (rc)
11279 				break;
11280 			if (hw_off_limits(sc))
11281 				rc = ENXIO;
11282 			else
11283 				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
11284 				    sizeof(ldst_cmd), &ldst_cmd);
11285 			end_synchronized_op(sc, 0);
11286 			if (rc != 0)
11287 				break;
11288 			else {
11289 				sbuf_printf(sb, " %08x %08x %08x %08x"
11290 				    " %08x %08x %08x %08x",
11291 				    be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
11292 				    be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
11293 				    be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
11294 				    be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
11295 				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
11296 				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
11297 				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
11298 				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
11299 			}
11300 		} else
11301 			sbuf_printf(sb, "%72s", "");
11302 
11303 		sbuf_printf(sb, "%4u%3u%3u%3u %#x",
11304 		    G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
11305 		    G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
11306 		    (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
11307 	}
11308 
11309 	if (rc)
11310 		(void) sbuf_finish(sb);
11311 	else
11312 		rc = sbuf_finish(sb);
11313 	sbuf_delete(sb);
11314 
11315 	return (rc);
11316 }
11317 
11318 static int
11319 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
11320 {
11321 	struct adapter *sc = arg1;
11322 	struct sbuf *sb;
11323 	int rc;
11324 	uint16_t mtus[NMTUS];
11325 
11326 	rc = 0;
11327 	mtx_lock(&sc->reg_lock);
11328 	if (hw_off_limits(sc))
11329 		rc = ENXIO;
11330 	else
11331 		t4_read_mtu_tbl(sc, mtus, NULL);
11332 	mtx_unlock(&sc->reg_lock);
11333 	if (rc != 0)
11334 		return (rc);
11335 
11336 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11337 	if (sb == NULL)
11338 		return (ENOMEM);
11339 
11340 	sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
11341 	    mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
11342 	    mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
11343 	    mtus[14], mtus[15]);
11344 
11345 	rc = sbuf_finish(sb);
11346 	sbuf_delete(sb);
11347 
11348 	return (rc);
11349 }
11350 
11351 static int
11352 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
11353 {
11354 	struct adapter *sc = arg1;
11355 	struct sbuf *sb;
11356 	int rc, i;
11357 	uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
11358 	uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
11359 	uint32_t stats[T7_PM_RX_CACHE_NSTATS];
11360 	static const char *tx_stats[MAX_PM_NSTATS] = {
11361 		"Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
11362 		"Tx FIFO wait", NULL, "Tx latency"
11363 	};
11364 	static const char *rx_stats[MAX_PM_NSTATS] = {
11365 		"Read:", "Write bypass:", "Write mem:", "Flush:",
11366 		"Rx FIFO wait", NULL, "Rx latency"
11367 	};
11368 
11369 	rc = 0;
11370 	mtx_lock(&sc->reg_lock);
11371 	if (hw_off_limits(sc))
11372 		rc = ENXIO;
11373 	else {
11374 		t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
11375 		t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
11376 		if (chip_id(sc) >= CHELSIO_T7)
11377 			t4_pmrx_cache_get_stats(sc, stats);
11378 	}
11379 	mtx_unlock(&sc->reg_lock);
11380 	if (rc != 0)
11381 		return (rc);
11382 
11383 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11384 	if (sb == NULL)
11385 		return (ENOMEM);
11386 
11387 	sbuf_printf(sb, "                Tx pcmds             Tx bytes");
11388 	for (i = 0; i < 4; i++) {
11389 		sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
11390 		    tx_cyc[i]);
11391 	}
11392 
11393 	sbuf_printf(sb, "\n                Rx pcmds             Rx bytes");
11394 	for (i = 0; i < 4; i++) {
11395 		sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
11396 		    rx_cyc[i]);
11397 	}
11398 
11399 	if (chip_id(sc) > CHELSIO_T5) {
11400 		sbuf_printf(sb,
11401 		    "\n              Total wait      Total occupancy");
11402 		sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
11403 		    tx_cyc[i]);
11404 		sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
11405 		    rx_cyc[i]);
11406 
11407 		i += 2;
11408 		MPASS(i < nitems(tx_stats));
11409 
11410 		sbuf_printf(sb,
11411 		    "\n                   Reads           Total wait");
11412 		sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
11413 		    tx_cyc[i]);
11414 		sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
11415 		    rx_cyc[i]);
11416 	}
11417 
11418 	if (chip_id(sc) >= CHELSIO_T7) {
11419 		i = 0;
11420 		sbuf_printf(sb, "\n\nPM RX Cache Stats\n");
11421 		sbuf_printf(sb, "%-40s    %u\n", "ReqWrite", stats[i++]);
11422 		sbuf_printf(sb, "%-40s    %u\n", "ReqReadInv", stats[i++]);
11423 		sbuf_printf(sb, "%-40s    %u\n", "ReqReadNoInv", stats[i++]);
11424 		sbuf_printf(sb, "%-40s    %u\n", "Write Split Request",
11425 			   stats[i++]);
11426 		sbuf_printf(sb, "%-40s    %u\n",
11427 			   "Normal Read Split (Read Invalidate)", stats[i++]);
11428 		sbuf_printf(sb, "%-40s    %u\n",
11429 			   "Feedback Read Split (Read NoInvalidate)",
11430 			   stats[i++]);
11431 		sbuf_printf(sb, "%-40s    %u\n", "Write Hit", stats[i++]);
11432 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit",
11433 			   stats[i++]);
11434 		sbuf_printf(sb, "%-40s    %u\n", "Feedback Read Hit",
11435 			   stats[i++]);
11436 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit Full Avail",
11437 			   stats[i++]);
11438 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit Full UnAvail",
11439 			   stats[i++]);
11440 		sbuf_printf(sb, "%-40s    %u\n",
11441 			   "Normal Read Hit Partial Avail",
11442 			   stats[i++]);
11443 		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Full Avail",
11444 			   stats[i++]);
11445 		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Full UnAvail",
11446 			   stats[i++]);
11447 		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Partial Avail",
11448 			   stats[i++]);
11449 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Full Free",
11450 			   stats[i++]);
11451 		sbuf_printf(sb, "%-40s    %u\n",
11452 			   "Normal Read Part-avail Mul-Regions",
11453 			   stats[i++]);
11454 		sbuf_printf(sb, "%-40s    %u\n",
11455 			   "FB Read Part-avail Mul-Regions",
11456 			   stats[i++]);
11457 		sbuf_printf(sb, "%-40s    %u\n", "Write Miss FL Used",
11458 			   stats[i++]);
11459 		sbuf_printf(sb, "%-40s    %u\n", "Write Miss LRU Used",
11460 			   stats[i++]);
11461 		sbuf_printf(sb, "%-40s    %u\n",
11462 			   "Write Miss LRU-Multiple Evict", stats[i++]);
11463 		sbuf_printf(sb, "%-40s    %u\n",
11464 			   "Write Hit Increasing Islands", stats[i++]);
11465 		sbuf_printf(sb, "%-40s    %u\n",
11466 			   "Normal Read Island Read split", stats[i++]);
11467 		sbuf_printf(sb, "%-40s    %u\n", "Write Overflow Eviction",
11468 			   stats[i++]);
11469 		sbuf_printf(sb, "%-40s    %u", "Read Overflow Eviction",
11470 			   stats[i++]);
11471 	}
11472 
11473 	rc = sbuf_finish(sb);
11474 	sbuf_delete(sb);
11475 
11476 	return (rc);
11477 }
11478 
11479 static int
11480 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
11481 {
11482 	struct adapter *sc = arg1;
11483 	struct sbuf *sb;
11484 	int rc;
11485 	struct tp_rdma_stats stats;
11486 
11487 	rc = 0;
11488 	mtx_lock(&sc->reg_lock);
11489 	if (hw_off_limits(sc))
11490 		rc = ENXIO;
11491 	else
11492 		t4_tp_get_rdma_stats(sc, &stats, 0);
11493 	mtx_unlock(&sc->reg_lock);
11494 	if (rc != 0)
11495 		return (rc);
11496 
11497 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11498 	if (sb == NULL)
11499 		return (ENOMEM);
11500 
11501 	sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
11502 	sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
11503 
11504 	rc = sbuf_finish(sb);
11505 	sbuf_delete(sb);
11506 
11507 	return (rc);
11508 }
11509 
11510 static int
11511 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
11512 {
11513 	struct adapter *sc = arg1;
11514 	struct sbuf *sb;
11515 	int rc;
11516 	struct tp_tcp_stats v4, v6;
11517 
11518 	rc = 0;
11519 	mtx_lock(&sc->reg_lock);
11520 	if (hw_off_limits(sc))
11521 		rc = ENXIO;
11522 	else
11523 		t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
11524 	mtx_unlock(&sc->reg_lock);
11525 	if (rc != 0)
11526 		return (rc);
11527 
11528 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11529 	if (sb == NULL)
11530 		return (ENOMEM);
11531 
11532 	sbuf_printf(sb,
11533 	    "                                IP                 IPv6\n");
11534 	sbuf_printf(sb, "OutRsts:      %20u %20u\n",
11535 	    v4.tcp_out_rsts, v6.tcp_out_rsts);
11536 	sbuf_printf(sb, "InSegs:       %20ju %20ju\n",
11537 	    v4.tcp_in_segs, v6.tcp_in_segs);
11538 	sbuf_printf(sb, "OutSegs:      %20ju %20ju\n",
11539 	    v4.tcp_out_segs, v6.tcp_out_segs);
11540 	sbuf_printf(sb, "RetransSegs:  %20ju %20ju",
11541 	    v4.tcp_retrans_segs, v6.tcp_retrans_segs);
11542 
11543 	rc = sbuf_finish(sb);
11544 	sbuf_delete(sb);
11545 
11546 	return (rc);
11547 }
11548 
11549 static int
11550 sysctl_tids(SYSCTL_HANDLER_ARGS)
11551 {
11552 	struct adapter *sc = arg1;
11553 	struct sbuf *sb;
11554 	int rc;
11555 	uint32_t x, y;
11556 	struct tid_info *t = &sc->tids;
11557 
11558 	rc = 0;
11559 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11560 	if (sb == NULL)
11561 		return (ENOMEM);
11562 
11563 	if (t->natids) {
11564 		sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
11565 		    t->atids_in_use);
11566 	}
11567 
11568 	if (t->nhpftids) {
11569 		sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
11570 		    t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
11571 	}
11572 
11573 	if (t->ntids) {
11574 		bool hashen = false;
11575 
11576 		mtx_lock(&sc->reg_lock);
11577 		if (hw_off_limits(sc))
11578 			rc = ENXIO;
11579 		else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
11580 			hashen = true;
11581 			if (chip_id(sc) <= CHELSIO_T5) {
11582 				x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
11583 				y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
11584 			} else {
11585 				x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
11586 				y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
11587 			}
11588 		}
11589 		mtx_unlock(&sc->reg_lock);
11590 		if (rc != 0)
11591 			goto done;
11592 
11593 		sbuf_printf(sb, "TID range: ");
11594 		if (hashen) {
11595 			if (x)
11596 				sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1);
11597 			sbuf_printf(sb, "%u-%u", y, t->tid_base + t->ntids - 1);
11598 		} else {
11599 			sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base +
11600 			    t->ntids - 1);
11601 		}
11602 		sbuf_printf(sb, ", in use: %u\n",
11603 		    atomic_load_acq_int(&t->tids_in_use));
11604 	}
11605 
11606 	if (t->nstids) {
11607 		sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
11608 		    t->stid_base + t->nstids - 1, t->stids_in_use);
11609 	}
11610 
11611 	if (t->nftids) {
11612 		sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
11613 		    t->ftid_end, t->ftids_in_use);
11614 	}
11615 
11616 	if (t->netids) {
11617 		sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
11618 		    t->etid_base + t->netids - 1, t->etids_in_use);
11619 	}
11620 
11621 	mtx_lock(&sc->reg_lock);
11622 	if (hw_off_limits(sc))
11623 		rc = ENXIO;
11624 	else {
11625 		x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4);
11626 		y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6);
11627 	}
11628 	mtx_unlock(&sc->reg_lock);
11629 	if (rc != 0)
11630 		goto done;
11631 	sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y);
11632 done:
11633 	if (rc == 0)
11634 		rc = sbuf_finish(sb);
11635 	else
11636 		(void)sbuf_finish(sb);
11637 	sbuf_delete(sb);
11638 
11639 	return (rc);
11640 }
11641 
11642 static int
11643 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
11644 {
11645 	struct adapter *sc = arg1;
11646 	struct sbuf *sb;
11647 	int rc;
11648 	struct tp_err_stats stats;
11649 
11650 	rc = 0;
11651 	mtx_lock(&sc->reg_lock);
11652 	if (hw_off_limits(sc))
11653 		rc = ENXIO;
11654 	else
11655 		t4_tp_get_err_stats(sc, &stats, 0);
11656 	mtx_unlock(&sc->reg_lock);
11657 	if (rc != 0)
11658 		return (rc);
11659 
11660 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11661 	if (sb == NULL)
11662 		return (ENOMEM);
11663 
11664 	if (sc->chip_params->nchan > 2) {
11665 		sbuf_printf(sb, "                 channel 0  channel 1"
11666 		    "  channel 2  channel 3\n");
11667 		sbuf_printf(sb, "macInErrs:      %10u %10u %10u %10u\n",
11668 		    stats.mac_in_errs[0], stats.mac_in_errs[1],
11669 		    stats.mac_in_errs[2], stats.mac_in_errs[3]);
11670 		sbuf_printf(sb, "hdrInErrs:      %10u %10u %10u %10u\n",
11671 		    stats.hdr_in_errs[0], stats.hdr_in_errs[1],
11672 		    stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
11673 		sbuf_printf(sb, "tcpInErrs:      %10u %10u %10u %10u\n",
11674 		    stats.tcp_in_errs[0], stats.tcp_in_errs[1],
11675 		    stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
11676 		sbuf_printf(sb, "tcp6InErrs:     %10u %10u %10u %10u\n",
11677 		    stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
11678 		    stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
11679 		sbuf_printf(sb, "tnlCongDrops:   %10u %10u %10u %10u\n",
11680 		    stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
11681 		    stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
11682 		sbuf_printf(sb, "tnlTxDrops:     %10u %10u %10u %10u\n",
11683 		    stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
11684 		    stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
11685 		sbuf_printf(sb, "ofldVlanDrops:  %10u %10u %10u %10u\n",
11686 		    stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
11687 		    stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
11688 		sbuf_printf(sb, "ofldChanDrops:  %10u %10u %10u %10u\n\n",
11689 		    stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
11690 		    stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
11691 	} else {
11692 		sbuf_printf(sb, "                 channel 0  channel 1\n");
11693 		sbuf_printf(sb, "macInErrs:      %10u %10u\n",
11694 		    stats.mac_in_errs[0], stats.mac_in_errs[1]);
11695 		sbuf_printf(sb, "hdrInErrs:      %10u %10u\n",
11696 		    stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
11697 		sbuf_printf(sb, "tcpInErrs:      %10u %10u\n",
11698 		    stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
11699 		sbuf_printf(sb, "tcp6InErrs:     %10u %10u\n",
11700 		    stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
11701 		sbuf_printf(sb, "tnlCongDrops:   %10u %10u\n",
11702 		    stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
11703 		sbuf_printf(sb, "tnlTxDrops:     %10u %10u\n",
11704 		    stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
11705 		sbuf_printf(sb, "ofldVlanDrops:  %10u %10u\n",
11706 		    stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
11707 		sbuf_printf(sb, "ofldChanDrops:  %10u %10u\n\n",
11708 		    stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
11709 	}
11710 
11711 	sbuf_printf(sb, "ofldNoNeigh:    %u\nofldCongDefer:  %u",
11712 	    stats.ofld_no_neigh, stats.ofld_cong_defer);
11713 
11714 	rc = sbuf_finish(sb);
11715 	sbuf_delete(sb);
11716 
11717 	return (rc);
11718 }
11719 
11720 static int
11721 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS)
11722 {
11723 	struct adapter *sc = arg1;
11724 	struct sbuf *sb;
11725 	int rc;
11726 	struct tp_tnl_stats stats;
11727 
11728 	rc = 0;
11729 	mtx_lock(&sc->reg_lock);
11730 	if (hw_off_limits(sc))
11731 		rc = ENXIO;
11732 	else
11733 		t4_tp_get_tnl_stats(sc, &stats, 1);
11734 	mtx_unlock(&sc->reg_lock);
11735 	if (rc != 0)
11736 		return (rc);
11737 
11738 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11739 	if (sb == NULL)
11740 		return (ENOMEM);
11741 
11742 	if (sc->chip_params->nchan > 2) {
11743 		sbuf_printf(sb, "           channel 0  channel 1"
11744 		    "  channel 2  channel 3\n");
11745 		sbuf_printf(sb, "OutPkts:  %10u %10u %10u %10u\n",
11746 		    stats.out_pkt[0], stats.out_pkt[1],
11747 		    stats.out_pkt[2], stats.out_pkt[3]);
11748 		sbuf_printf(sb, "InPkts:   %10u %10u %10u %10u",
11749 		    stats.in_pkt[0], stats.in_pkt[1],
11750 		    stats.in_pkt[2], stats.in_pkt[3]);
11751 	} else {
11752 		sbuf_printf(sb, "           channel 0  channel 1\n");
11753 		sbuf_printf(sb, "OutPkts:  %10u %10u\n",
11754 		    stats.out_pkt[0], stats.out_pkt[1]);
11755 		sbuf_printf(sb, "InPkts:   %10u %10u",
11756 		    stats.in_pkt[0], stats.in_pkt[1]);
11757 	}
11758 
11759 	rc = sbuf_finish(sb);
11760 	sbuf_delete(sb);
11761 
11762 	return (rc);
11763 }
11764 
11765 static int
11766 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
11767 {
11768 	struct adapter *sc = arg1;
11769 	struct tp_params *tpp = &sc->params.tp;
11770 	u_int mask;
11771 	int rc;
11772 
11773 	mask = tpp->la_mask >> 16;
11774 	rc = sysctl_handle_int(oidp, &mask, 0, req);
11775 	if (rc != 0 || req->newptr == NULL)
11776 		return (rc);
11777 	if (mask > 0xffff)
11778 		return (EINVAL);
11779 	mtx_lock(&sc->reg_lock);
11780 	if (hw_off_limits(sc))
11781 		rc = ENXIO;
11782 	else {
11783 		tpp->la_mask = mask << 16;
11784 		t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U,
11785 		    tpp->la_mask);
11786 	}
11787 	mtx_unlock(&sc->reg_lock);
11788 
11789 	return (rc);
11790 }
11791 
11792 struct field_desc {
11793 	const char *name;
11794 	u_int start;
11795 	u_int width;
11796 };
11797 
11798 static void
11799 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
11800 {
11801 	char buf[32];
11802 	int line_size = 0;
11803 
11804 	while (f->name) {
11805 		uint64_t mask = (1ULL << f->width) - 1;
11806 		int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
11807 		    ((uintmax_t)v >> f->start) & mask);
11808 
11809 		if (line_size + len >= 79) {
11810 			line_size = 8;
11811 			sbuf_printf(sb, "\n        ");
11812 		}
11813 		sbuf_printf(sb, "%s ", buf);
11814 		line_size += len + 1;
11815 		f++;
11816 	}
11817 	sbuf_printf(sb, "\n");
11818 }
11819 
11820 static const struct field_desc tp_la0[] = {
11821 	{ "RcfOpCodeOut", 60, 4 },
11822 	{ "State", 56, 4 },
11823 	{ "WcfState", 52, 4 },
11824 	{ "RcfOpcSrcOut", 50, 2 },
11825 	{ "CRxError", 49, 1 },
11826 	{ "ERxError", 48, 1 },
11827 	{ "SanityFailed", 47, 1 },
11828 	{ "SpuriousMsg", 46, 1 },
11829 	{ "FlushInputMsg", 45, 1 },
11830 	{ "FlushInputCpl", 44, 1 },
11831 	{ "RssUpBit", 43, 1 },
11832 	{ "RssFilterHit", 42, 1 },
11833 	{ "Tid", 32, 10 },
11834 	{ "InitTcb", 31, 1 },
11835 	{ "LineNumber", 24, 7 },
11836 	{ "Emsg", 23, 1 },
11837 	{ "EdataOut", 22, 1 },
11838 	{ "Cmsg", 21, 1 },
11839 	{ "CdataOut", 20, 1 },
11840 	{ "EreadPdu", 19, 1 },
11841 	{ "CreadPdu", 18, 1 },
11842 	{ "TunnelPkt", 17, 1 },
11843 	{ "RcfPeerFin", 16, 1 },
11844 	{ "RcfReasonOut", 12, 4 },
11845 	{ "TxCchannel", 10, 2 },
11846 	{ "RcfTxChannel", 8, 2 },
11847 	{ "RxEchannel", 6, 2 },
11848 	{ "RcfRxChannel", 5, 1 },
11849 	{ "RcfDataOutSrdy", 4, 1 },
11850 	{ "RxDvld", 3, 1 },
11851 	{ "RxOoDvld", 2, 1 },
11852 	{ "RxCongestion", 1, 1 },
11853 	{ "TxCongestion", 0, 1 },
11854 	{ NULL }
11855 };
11856 
11857 static const struct field_desc tp_la1[] = {
11858 	{ "CplCmdIn", 56, 8 },
11859 	{ "CplCmdOut", 48, 8 },
11860 	{ "ESynOut", 47, 1 },
11861 	{ "EAckOut", 46, 1 },
11862 	{ "EFinOut", 45, 1 },
11863 	{ "ERstOut", 44, 1 },
11864 	{ "SynIn", 43, 1 },
11865 	{ "AckIn", 42, 1 },
11866 	{ "FinIn", 41, 1 },
11867 	{ "RstIn", 40, 1 },
11868 	{ "DataIn", 39, 1 },
11869 	{ "DataInVld", 38, 1 },
11870 	{ "PadIn", 37, 1 },
11871 	{ "RxBufEmpty", 36, 1 },
11872 	{ "RxDdp", 35, 1 },
11873 	{ "RxFbCongestion", 34, 1 },
11874 	{ "TxFbCongestion", 33, 1 },
11875 	{ "TxPktSumSrdy", 32, 1 },
11876 	{ "RcfUlpType", 28, 4 },
11877 	{ "Eread", 27, 1 },
11878 	{ "Ebypass", 26, 1 },
11879 	{ "Esave", 25, 1 },
11880 	{ "Static0", 24, 1 },
11881 	{ "Cread", 23, 1 },
11882 	{ "Cbypass", 22, 1 },
11883 	{ "Csave", 21, 1 },
11884 	{ "CPktOut", 20, 1 },
11885 	{ "RxPagePoolFull", 18, 2 },
11886 	{ "RxLpbkPkt", 17, 1 },
11887 	{ "TxLpbkPkt", 16, 1 },
11888 	{ "RxVfValid", 15, 1 },
11889 	{ "SynLearned", 14, 1 },
11890 	{ "SetDelEntry", 13, 1 },
11891 	{ "SetInvEntry", 12, 1 },
11892 	{ "CpcmdDvld", 11, 1 },
11893 	{ "CpcmdSave", 10, 1 },
11894 	{ "RxPstructsFull", 8, 2 },
11895 	{ "EpcmdDvld", 7, 1 },
11896 	{ "EpcmdFlush", 6, 1 },
11897 	{ "EpcmdTrimPrefix", 5, 1 },
11898 	{ "EpcmdTrimPostfix", 4, 1 },
11899 	{ "ERssIp4Pkt", 3, 1 },
11900 	{ "ERssIp6Pkt", 2, 1 },
11901 	{ "ERssTcpUdpPkt", 1, 1 },
11902 	{ "ERssFceFipPkt", 0, 1 },
11903 	{ NULL }
11904 };
11905 
11906 static const struct field_desc tp_la2[] = {
11907 	{ "CplCmdIn", 56, 8 },
11908 	{ "MpsVfVld", 55, 1 },
11909 	{ "MpsPf", 52, 3 },
11910 	{ "MpsVf", 44, 8 },
11911 	{ "SynIn", 43, 1 },
11912 	{ "AckIn", 42, 1 },
11913 	{ "FinIn", 41, 1 },
11914 	{ "RstIn", 40, 1 },
11915 	{ "DataIn", 39, 1 },
11916 	{ "DataInVld", 38, 1 },
11917 	{ "PadIn", 37, 1 },
11918 	{ "RxBufEmpty", 36, 1 },
11919 	{ "RxDdp", 35, 1 },
11920 	{ "RxFbCongestion", 34, 1 },
11921 	{ "TxFbCongestion", 33, 1 },
11922 	{ "TxPktSumSrdy", 32, 1 },
11923 	{ "RcfUlpType", 28, 4 },
11924 	{ "Eread", 27, 1 },
11925 	{ "Ebypass", 26, 1 },
11926 	{ "Esave", 25, 1 },
11927 	{ "Static0", 24, 1 },
11928 	{ "Cread", 23, 1 },
11929 	{ "Cbypass", 22, 1 },
11930 	{ "Csave", 21, 1 },
11931 	{ "CPktOut", 20, 1 },
11932 	{ "RxPagePoolFull", 18, 2 },
11933 	{ "RxLpbkPkt", 17, 1 },
11934 	{ "TxLpbkPkt", 16, 1 },
11935 	{ "RxVfValid", 15, 1 },
11936 	{ "SynLearned", 14, 1 },
11937 	{ "SetDelEntry", 13, 1 },
11938 	{ "SetInvEntry", 12, 1 },
11939 	{ "CpcmdDvld", 11, 1 },
11940 	{ "CpcmdSave", 10, 1 },
11941 	{ "RxPstructsFull", 8, 2 },
11942 	{ "EpcmdDvld", 7, 1 },
11943 	{ "EpcmdFlush", 6, 1 },
11944 	{ "EpcmdTrimPrefix", 5, 1 },
11945 	{ "EpcmdTrimPostfix", 4, 1 },
11946 	{ "ERssIp4Pkt", 3, 1 },
11947 	{ "ERssIp6Pkt", 2, 1 },
11948 	{ "ERssTcpUdpPkt", 1, 1 },
11949 	{ "ERssFceFipPkt", 0, 1 },
11950 	{ NULL }
11951 };
11952 
11953 static void
11954 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
11955 {
11956 
11957 	field_desc_show(sb, *p, tp_la0);
11958 }
11959 
11960 static void
11961 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
11962 {
11963 
11964 	if (idx)
11965 		sbuf_printf(sb, "\n");
11966 	field_desc_show(sb, p[0], tp_la0);
11967 	if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
11968 		field_desc_show(sb, p[1], tp_la0);
11969 }
11970 
11971 static void
11972 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
11973 {
11974 
11975 	if (idx)
11976 		sbuf_printf(sb, "\n");
11977 	field_desc_show(sb, p[0], tp_la0);
11978 	if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
11979 		field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
11980 }
11981 
11982 static int
11983 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
11984 {
11985 	struct adapter *sc = arg1;
11986 	struct sbuf *sb;
11987 	uint64_t *buf, *p;
11988 	int rc;
11989 	u_int i, inc;
11990 	void (*show_func)(struct sbuf *, uint64_t *, int);
11991 
11992 	rc = 0;
11993 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11994 	if (sb == NULL)
11995 		return (ENOMEM);
11996 
11997 	buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
11998 
11999 	mtx_lock(&sc->reg_lock);
12000 	if (hw_off_limits(sc))
12001 		rc = ENXIO;
12002 	else {
12003 		t4_tp_read_la(sc, buf, NULL);
12004 		switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
12005 		case 2:
12006 			inc = 2;
12007 			show_func = tp_la_show2;
12008 			break;
12009 		case 3:
12010 			inc = 2;
12011 			show_func = tp_la_show3;
12012 			break;
12013 		default:
12014 			inc = 1;
12015 			show_func = tp_la_show;
12016 		}
12017 	}
12018 	mtx_unlock(&sc->reg_lock);
12019 	if (rc != 0)
12020 		goto done;
12021 
12022 	p = buf;
12023 	for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
12024 		(*show_func)(sb, p, i);
12025 	rc = sbuf_finish(sb);
12026 done:
12027 	sbuf_delete(sb);
12028 	free(buf, M_CXGBE);
12029 	return (rc);
12030 }
12031 
12032 static int
12033 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
12034 {
12035 	struct adapter *sc = arg1;
12036 	struct sbuf *sb;
12037 	int rc;
12038 	u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
12039 
12040 	rc = 0;
12041 	mtx_lock(&sc->reg_lock);
12042 	if (hw_off_limits(sc))
12043 		rc = ENXIO;
12044 	else
12045 		t4_get_chan_txrate(sc, nrate, orate);
12046 	mtx_unlock(&sc->reg_lock);
12047 	if (rc != 0)
12048 		return (rc);
12049 
12050 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
12051 	if (sb == NULL)
12052 		return (ENOMEM);
12053 
12054 	if (sc->chip_params->nchan > 2) {
12055 		sbuf_printf(sb, "              channel 0   channel 1"
12056 		    "   channel 2   channel 3\n");
12057 		sbuf_printf(sb, "NIC B/s:     %10ju  %10ju  %10ju  %10ju\n",
12058 		    nrate[0], nrate[1], nrate[2], nrate[3]);
12059 		sbuf_printf(sb, "Offload B/s: %10ju  %10ju  %10ju  %10ju",
12060 		    orate[0], orate[1], orate[2], orate[3]);
12061 	} else {
12062 		sbuf_printf(sb, "              channel 0   channel 1\n");
12063 		sbuf_printf(sb, "NIC B/s:     %10ju  %10ju\n",
12064 		    nrate[0], nrate[1]);
12065 		sbuf_printf(sb, "Offload B/s: %10ju  %10ju",
12066 		    orate[0], orate[1]);
12067 	}
12068 
12069 	rc = sbuf_finish(sb);
12070 	sbuf_delete(sb);
12071 
12072 	return (rc);
12073 }
12074 
12075 static int
12076 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
12077 {
12078 	struct adapter *sc = arg1;
12079 	struct sbuf *sb;
12080 	uint32_t *buf, *p;
12081 	int rc, i;
12082 
12083 	rc = 0;
12084 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12085 	if (sb == NULL)
12086 		return (ENOMEM);
12087 
12088 	buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
12089 	    M_ZERO | M_WAITOK);
12090 
12091 	mtx_lock(&sc->reg_lock);
12092 	if (hw_off_limits(sc))
12093 		rc = ENXIO;
12094 	else
12095 		t4_ulprx_read_la(sc, buf);
12096 	mtx_unlock(&sc->reg_lock);
12097 	if (rc != 0)
12098 		goto done;
12099 
12100 	p = buf;
12101 	sbuf_printf(sb, "      Pcmd        Type   Message"
12102 	    "                Data");
12103 	for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
12104 		sbuf_printf(sb, "\n%08x%08x  %4x  %08x  %08x%08x%08x%08x",
12105 		    p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
12106 	}
12107 	rc = sbuf_finish(sb);
12108 done:
12109 	sbuf_delete(sb);
12110 	free(buf, M_CXGBE);
12111 	return (rc);
12112 }
12113 
12114 static int
12115 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
12116 {
12117 	struct adapter *sc = arg1;
12118 	struct sbuf *sb;
12119 	int rc;
12120 	uint32_t cfg, s1, s2;
12121 
12122 	MPASS(chip_id(sc) >= CHELSIO_T5);
12123 
12124 	rc = 0;
12125 	mtx_lock(&sc->reg_lock);
12126 	if (hw_off_limits(sc))
12127 		rc = ENXIO;
12128 	else {
12129 		cfg = t4_read_reg(sc, A_SGE_STAT_CFG);
12130 		s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL);
12131 		s2 = t4_read_reg(sc, A_SGE_STAT_MATCH);
12132 	}
12133 	mtx_unlock(&sc->reg_lock);
12134 	if (rc != 0)
12135 		return (rc);
12136 
12137 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12138 	if (sb == NULL)
12139 		return (ENOMEM);
12140 
12141 	if (G_STATSOURCE_T5(cfg) == 7) {
12142 		int mode;
12143 
12144 		mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg);
12145 		if (mode == 0)
12146 			sbuf_printf(sb, "total %d, incomplete %d", s1, s2);
12147 		else if (mode == 1)
12148 			sbuf_printf(sb, "total %d, data overflow %d", s1, s2);
12149 		else
12150 			sbuf_printf(sb, "unknown mode %d", mode);
12151 	}
12152 	rc = sbuf_finish(sb);
12153 	sbuf_delete(sb);
12154 
12155 	return (rc);
12156 }
12157 
12158 static int
12159 sysctl_cpus(SYSCTL_HANDLER_ARGS)
12160 {
12161 	struct adapter *sc = arg1;
12162 	enum cpu_sets op = arg2;
12163 	cpuset_t cpuset;
12164 	struct sbuf *sb;
12165 	int i, rc;
12166 
12167 	MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
12168 
12169 	CPU_ZERO(&cpuset);
12170 	rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
12171 	if (rc != 0)
12172 		return (rc);
12173 
12174 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12175 	if (sb == NULL)
12176 		return (ENOMEM);
12177 
12178 	CPU_FOREACH(i)
12179 		sbuf_printf(sb, "%d ", i);
12180 	rc = sbuf_finish(sb);
12181 	sbuf_delete(sb);
12182 
12183 	return (rc);
12184 }
12185 
12186 static int
12187 sysctl_reset(SYSCTL_HANDLER_ARGS)
12188 {
12189 	struct adapter *sc = arg1;
12190 	u_int val;
12191 	int rc;
12192 
12193 	val = atomic_load_int(&sc->num_resets);
12194 	rc = sysctl_handle_int(oidp, &val, 0, req);
12195 	if (rc != 0 || req->newptr == NULL)
12196 		return (rc);
12197 
12198 	if (val == 0) {
12199 		/* Zero out the counter that tracks reset. */
12200 		atomic_store_int(&sc->num_resets, 0);
12201 		return (0);
12202 	}
12203 
12204 	if (val != 1)
12205 		return (EINVAL);	/* 0 or 1 are the only legal values */
12206 
12207 	if (hw_off_limits(sc))		/* harmless race */
12208 		return (EALREADY);
12209 
12210 	taskqueue_enqueue(reset_tq, &sc->reset_task);
12211 	return (0);
12212 }
12213 
12214 static int
12215 sysctl_tcb_cache(SYSCTL_HANDLER_ARGS)
12216 {
12217 	struct adapter *sc = arg1;
12218 	u_int val, v;
12219 	int rc;
12220 
12221 	mtx_lock(&sc->reg_lock);
12222 	if (hw_off_limits(sc)) {
12223 		rc = ENXIO;
12224 		goto done;
12225 	}
12226 	t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
12227 	mtx_unlock(&sc->reg_lock);
12228 
12229 	val = v & F_GLFL ? 0 : 1;
12230 	rc = sysctl_handle_int(oidp, &val, 0, req);
12231 	if (rc != 0 || req->newptr == NULL)
12232 		return (rc);
12233 	if (val == 0)
12234 		v |= F_GLFL;
12235 	else
12236 		v &= ~F_GLFL;
12237 
12238 	mtx_lock(&sc->reg_lock);
12239 	if (hw_off_limits(sc))
12240 		rc = ENXIO;
12241 	else
12242 		t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
12243 done:
12244 	mtx_unlock(&sc->reg_lock);
12245 	return (rc);
12246 }
12247 
12248 #ifdef TCP_OFFLOAD
12249 static int
12250 sysctl_tls(SYSCTL_HANDLER_ARGS)
12251 {
12252 	struct adapter *sc = arg1;
12253 	int i, j, v, rc;
12254 	struct vi_info *vi;
12255 
12256 	v = sc->tt.tls;
12257 	rc = sysctl_handle_int(oidp, &v, 0, req);
12258 	if (rc != 0 || req->newptr == NULL)
12259 		return (rc);
12260 
12261 	if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS))
12262 		return (ENOTSUP);
12263 
12264 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls");
12265 	if (rc)
12266 		return (rc);
12267 	if (hw_off_limits(sc))
12268 		rc = ENXIO;
12269 	else {
12270 		sc->tt.tls = !!v;
12271 		for_each_port(sc, i) {
12272 			for_each_vi(sc->port[i], j, vi) {
12273 				if (vi->flags & VI_INIT_DONE)
12274 					t4_update_fl_bufsize(vi->ifp);
12275 			}
12276 		}
12277 	}
12278 	end_synchronized_op(sc, 0);
12279 
12280 	return (rc);
12281 
12282 }
12283 
12284 static void
12285 unit_conv(char *buf, size_t len, u_int val, u_int factor)
12286 {
12287 	u_int rem = val % factor;
12288 
12289 	if (rem == 0)
12290 		snprintf(buf, len, "%u", val / factor);
12291 	else {
12292 		while (rem % 10 == 0)
12293 			rem /= 10;
12294 		snprintf(buf, len, "%u.%u", val / factor, rem);
12295 	}
12296 }
12297 
12298 static int
12299 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
12300 {
12301 	struct adapter *sc = arg1;
12302 	char buf[16];
12303 	u_int res, re;
12304 	u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
12305 
12306 	mtx_lock(&sc->reg_lock);
12307 	if (hw_off_limits(sc))
12308 		res = (u_int)-1;
12309 	else
12310 		res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
12311 	mtx_unlock(&sc->reg_lock);
12312 	if (res == (u_int)-1)
12313 		return (ENXIO);
12314 
12315 	switch (arg2) {
12316 	case 0:
12317 		/* timer_tick */
12318 		re = G_TIMERRESOLUTION(res);
12319 		break;
12320 	case 1:
12321 		/* TCP timestamp tick */
12322 		re = G_TIMESTAMPRESOLUTION(res);
12323 		break;
12324 	case 2:
12325 		/* DACK tick */
12326 		re = G_DELAYEDACKRESOLUTION(res);
12327 		break;
12328 	default:
12329 		return (EDOOFUS);
12330 	}
12331 
12332 	unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
12333 
12334 	return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
12335 }
12336 
12337 static int
12338 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
12339 {
12340 	struct adapter *sc = arg1;
12341 	int rc;
12342 	u_int dack_tmr, dack_re, v;
12343 	u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
12344 
12345 	mtx_lock(&sc->reg_lock);
12346 	if (hw_off_limits(sc))
12347 		rc = ENXIO;
12348 	else {
12349 		rc = 0;
12350 		dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc,
12351 		    A_TP_TIMER_RESOLUTION));
12352 		dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER);
12353 	}
12354 	mtx_unlock(&sc->reg_lock);
12355 	if (rc != 0)
12356 		return (rc);
12357 
12358 	v = ((cclk_ps << dack_re) / 1000000) * dack_tmr;
12359 
12360 	return (sysctl_handle_int(oidp, &v, 0, req));
12361 }
12362 
12363 static int
12364 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
12365 {
12366 	struct adapter *sc = arg1;
12367 	int rc, reg = arg2;
12368 	u_int tre;
12369 	u_long tp_tick_us, v;
12370 	u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
12371 
12372 	MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
12373 	    reg == A_TP_PERS_MIN  || reg == A_TP_PERS_MAX ||
12374 	    reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
12375 	    reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
12376 
12377 	mtx_lock(&sc->reg_lock);
12378 	if (hw_off_limits(sc))
12379 		rc = ENXIO;
12380 	else {
12381 		rc = 0;
12382 		tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
12383 		tp_tick_us = (cclk_ps << tre) / 1000000;
12384 		if (reg == A_TP_INIT_SRTT)
12385 			v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
12386 		else
12387 			v = tp_tick_us * t4_read_reg(sc, reg);
12388 	}
12389 	mtx_unlock(&sc->reg_lock);
12390 	if (rc != 0)
12391 		return (rc);
12392 	else
12393 		return (sysctl_handle_long(oidp, &v, 0, req));
12394 }
12395 
12396 /*
12397  * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
12398  * passed to this function.
12399  */
12400 static int
12401 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
12402 {
12403 	struct adapter *sc = arg1;
12404 	int rc, idx = arg2;
12405 	u_int v;
12406 
12407 	MPASS(idx >= 0 && idx <= 24);
12408 
12409 	mtx_lock(&sc->reg_lock);
12410 	if (hw_off_limits(sc))
12411 		rc = ENXIO;
12412 	else {
12413 		rc = 0;
12414 		v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
12415 	}
12416 	mtx_unlock(&sc->reg_lock);
12417 	if (rc != 0)
12418 		return (rc);
12419 	else
12420 		return (sysctl_handle_int(oidp, &v, 0, req));
12421 }
12422 
12423 static int
12424 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
12425 {
12426 	struct adapter *sc = arg1;
12427 	int rc, idx = arg2;
12428 	u_int shift, v, r;
12429 
12430 	MPASS(idx >= 0 && idx < 16);
12431 
12432 	r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
12433 	shift = (idx & 3) << 3;
12434 	mtx_lock(&sc->reg_lock);
12435 	if (hw_off_limits(sc))
12436 		rc = ENXIO;
12437 	else {
12438 		rc = 0;
12439 		v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
12440 	}
12441 	mtx_unlock(&sc->reg_lock);
12442 	if (rc != 0)
12443 		return (rc);
12444 	else
12445 		return (sysctl_handle_int(oidp, &v, 0, req));
12446 }
12447 
12448 static int
12449 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
12450 {
12451 	struct vi_info *vi = arg1;
12452 	struct adapter *sc = vi->adapter;
12453 	int idx, rc, i;
12454 	struct sge_ofld_rxq *ofld_rxq;
12455 	uint8_t v;
12456 
12457 	idx = vi->ofld_tmr_idx;
12458 
12459 	rc = sysctl_handle_int(oidp, &idx, 0, req);
12460 	if (rc != 0 || req->newptr == NULL)
12461 		return (rc);
12462 
12463 	if (idx < 0 || idx >= SGE_NTIMERS)
12464 		return (EINVAL);
12465 
12466 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
12467 	    "t4otmr");
12468 	if (rc)
12469 		return (rc);
12470 
12471 	v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
12472 	for_each_ofld_rxq(vi, i, ofld_rxq) {
12473 #ifdef atomic_store_rel_8
12474 		atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
12475 #else
12476 		ofld_rxq->iq.intr_params = v;
12477 #endif
12478 	}
12479 	vi->ofld_tmr_idx = idx;
12480 
12481 	end_synchronized_op(sc, LOCK_HELD);
12482 	return (0);
12483 }
12484 
12485 static int
12486 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
12487 {
12488 	struct vi_info *vi = arg1;
12489 	struct adapter *sc = vi->adapter;
12490 	int idx, rc;
12491 
12492 	idx = vi->ofld_pktc_idx;
12493 
12494 	rc = sysctl_handle_int(oidp, &idx, 0, req);
12495 	if (rc != 0 || req->newptr == NULL)
12496 		return (rc);
12497 
12498 	if (idx < -1 || idx >= SGE_NCOUNTERS)
12499 		return (EINVAL);
12500 
12501 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
12502 	    "t4opktc");
12503 	if (rc)
12504 		return (rc);
12505 
12506 	if (vi->flags & VI_INIT_DONE)
12507 		rc = EBUSY; /* cannot be changed once the queues are created */
12508 	else
12509 		vi->ofld_pktc_idx = idx;
12510 
12511 	end_synchronized_op(sc, LOCK_HELD);
12512 	return (rc);
12513 }
12514 #endif
12515 
12516 static int
12517 get_sge_context(struct adapter *sc, int mem_id, uint32_t cid, int len,
12518     uint32_t *data)
12519 {
12520 	int rc;
12521 
12522 	if (len < sc->chip_params->sge_ctxt_size)
12523 		return (ENOBUFS);
12524 	if (cid > M_CTXTQID)
12525 		return (EINVAL);
12526 	if (mem_id != CTXT_EGRESS && mem_id != CTXT_INGRESS &&
12527 	    mem_id != CTXT_FLM && mem_id != CTXT_CNM)
12528 		return (EINVAL);
12529 
12530 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
12531 	if (rc)
12532 		return (rc);
12533 
12534 	if (hw_off_limits(sc)) {
12535 		rc = ENXIO;
12536 		goto done;
12537 	}
12538 
12539 	if (sc->flags & FW_OK) {
12540 		rc = -t4_sge_ctxt_rd(sc, sc->mbox, cid, mem_id, data);
12541 		if (rc == 0)
12542 			goto done;
12543 	}
12544 
12545 	/*
12546 	 * Read via firmware failed or wasn't even attempted.  Read directly via
12547 	 * the backdoor.
12548 	 */
12549 	rc = -t4_sge_ctxt_rd_bd(sc, cid, mem_id, data);
12550 done:
12551 	end_synchronized_op(sc, 0);
12552 	return (rc);
12553 }
12554 
12555 static int
12556 load_fw(struct adapter *sc, struct t4_data *fw)
12557 {
12558 	int rc;
12559 	uint8_t *fw_data;
12560 
12561 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
12562 	if (rc)
12563 		return (rc);
12564 
12565 	if (hw_off_limits(sc)) {
12566 		rc = ENXIO;
12567 		goto done;
12568 	}
12569 
12570 	/*
12571 	 * The firmware, with the sole exception of the memory parity error
12572 	 * handler, runs from memory and not flash.  It is almost always safe to
12573 	 * install a new firmware on a running system.  Just set bit 1 in
12574 	 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
12575 	 */
12576 	if (sc->flags & FULL_INIT_DONE &&
12577 	    (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
12578 		rc = EBUSY;
12579 		goto done;
12580 	}
12581 
12582 	fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
12583 
12584 	rc = copyin(fw->data, fw_data, fw->len);
12585 	if (rc == 0)
12586 		rc = -t4_load_fw(sc, fw_data, fw->len);
12587 
12588 	free(fw_data, M_CXGBE);
12589 done:
12590 	end_synchronized_op(sc, 0);
12591 	return (rc);
12592 }
12593 
12594 static int
12595 load_cfg(struct adapter *sc, struct t4_data *cfg)
12596 {
12597 	int rc;
12598 	uint8_t *cfg_data = NULL;
12599 
12600 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
12601 	if (rc)
12602 		return (rc);
12603 
12604 	if (hw_off_limits(sc)) {
12605 		rc = ENXIO;
12606 		goto done;
12607 	}
12608 
12609 	if (cfg->len == 0) {
12610 		/* clear */
12611 		rc = -t4_load_cfg(sc, NULL, 0);
12612 		goto done;
12613 	}
12614 
12615 	cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
12616 
12617 	rc = copyin(cfg->data, cfg_data, cfg->len);
12618 	if (rc == 0)
12619 		rc = -t4_load_cfg(sc, cfg_data, cfg->len);
12620 
12621 	free(cfg_data, M_CXGBE);
12622 done:
12623 	end_synchronized_op(sc, 0);
12624 	return (rc);
12625 }
12626 
12627 static int
12628 load_boot(struct adapter *sc, struct t4_bootrom *br)
12629 {
12630 	int rc;
12631 	uint8_t *br_data = NULL;
12632 	u_int offset;
12633 
12634 	if (br->len > 1024 * 1024)
12635 		return (EFBIG);
12636 
12637 	if (br->pf_offset == 0) {
12638 		/* pfidx */
12639 		if (br->pfidx_addr > 7)
12640 			return (EINVAL);
12641 		offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
12642 		    A_PCIE_PF_EXPROM_OFST)));
12643 	} else if (br->pf_offset == 1) {
12644 		/* offset */
12645 		offset = G_OFFSET(br->pfidx_addr);
12646 	} else {
12647 		return (EINVAL);
12648 	}
12649 
12650 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
12651 	if (rc)
12652 		return (rc);
12653 
12654 	if (hw_off_limits(sc)) {
12655 		rc = ENXIO;
12656 		goto done;
12657 	}
12658 
12659 	if (br->len == 0) {
12660 		/* clear */
12661 		rc = -t4_load_boot(sc, NULL, offset, 0);
12662 		goto done;
12663 	}
12664 
12665 	br_data = malloc(br->len, M_CXGBE, M_WAITOK);
12666 
12667 	rc = copyin(br->data, br_data, br->len);
12668 	if (rc == 0)
12669 		rc = -t4_load_boot(sc, br_data, offset, br->len);
12670 
12671 	free(br_data, M_CXGBE);
12672 done:
12673 	end_synchronized_op(sc, 0);
12674 	return (rc);
12675 }
12676 
12677 static int
12678 load_bootcfg(struct adapter *sc, struct t4_data *bc)
12679 {
12680 	int rc;
12681 	uint8_t *bc_data = NULL;
12682 
12683 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
12684 	if (rc)
12685 		return (rc);
12686 
12687 	if (hw_off_limits(sc)) {
12688 		rc = ENXIO;
12689 		goto done;
12690 	}
12691 
12692 	if (bc->len == 0) {
12693 		/* clear */
12694 		rc = -t4_load_bootcfg(sc, NULL, 0);
12695 		goto done;
12696 	}
12697 
12698 	bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
12699 
12700 	rc = copyin(bc->data, bc_data, bc->len);
12701 	if (rc == 0)
12702 		rc = -t4_load_bootcfg(sc, bc_data, bc->len);
12703 
12704 	free(bc_data, M_CXGBE);
12705 done:
12706 	end_synchronized_op(sc, 0);
12707 	return (rc);
12708 }
12709 
12710 static int
12711 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
12712 {
12713 	int rc;
12714 	struct cudbg_init *cudbg;
12715 	void *handle, *buf;
12716 
12717 	/* buf is large, don't block if no memory is available */
12718 	buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
12719 	if (buf == NULL)
12720 		return (ENOMEM);
12721 
12722 	handle = cudbg_alloc_handle();
12723 	if (handle == NULL) {
12724 		rc = ENOMEM;
12725 		goto done;
12726 	}
12727 
12728 	cudbg = cudbg_get_init(handle);
12729 	cudbg->adap = sc;
12730 	cudbg->print = (cudbg_print_cb)printf;
12731 
12732 #ifndef notyet
12733 	device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
12734 	    __func__, dump->wr_flash, dump->len, dump->data);
12735 #endif
12736 
12737 	if (dump->wr_flash)
12738 		cudbg->use_flash = 1;
12739 	MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
12740 	memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
12741 
12742 	rc = cudbg_collect(handle, buf, &dump->len);
12743 	if (rc != 0)
12744 		goto done;
12745 
12746 	rc = copyout(buf, dump->data, dump->len);
12747 done:
12748 	cudbg_free_handle(handle);
12749 	free(buf, M_CXGBE);
12750 	return (rc);
12751 }
12752 
12753 static void
12754 free_offload_policy(struct t4_offload_policy *op)
12755 {
12756 	struct offload_rule *r;
12757 	int i;
12758 
12759 	if (op == NULL)
12760 		return;
12761 
12762 	r = &op->rule[0];
12763 	for (i = 0; i < op->nrules; i++, r++) {
12764 		free(r->bpf_prog.bf_insns, M_CXGBE);
12765 	}
12766 	free(op->rule, M_CXGBE);
12767 	free(op, M_CXGBE);
12768 }
12769 
12770 static int
12771 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
12772 {
12773 	int i, rc, len;
12774 	struct t4_offload_policy *op, *old;
12775 	struct bpf_program *bf;
12776 	const struct offload_settings *s;
12777 	struct offload_rule *r;
12778 	void *u;
12779 
12780 	if (!is_offload(sc))
12781 		return (ENODEV);
12782 
12783 	if (uop->nrules == 0) {
12784 		/* Delete installed policies. */
12785 		op = NULL;
12786 		goto set_policy;
12787 	} else if (uop->nrules > 256) { /* arbitrary */
12788 		return (E2BIG);
12789 	}
12790 
12791 	/* Copy userspace offload policy to kernel */
12792 	op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
12793 	op->nrules = uop->nrules;
12794 	len = op->nrules * sizeof(struct offload_rule);
12795 	op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
12796 	rc = copyin(uop->rule, op->rule, len);
12797 	if (rc) {
12798 		free(op->rule, M_CXGBE);
12799 		free(op, M_CXGBE);
12800 		return (rc);
12801 	}
12802 
12803 	r = &op->rule[0];
12804 	for (i = 0; i < op->nrules; i++, r++) {
12805 
12806 		/* Validate open_type */
12807 		if (r->open_type != OPEN_TYPE_LISTEN &&
12808 		    r->open_type != OPEN_TYPE_ACTIVE &&
12809 		    r->open_type != OPEN_TYPE_PASSIVE &&
12810 		    r->open_type != OPEN_TYPE_DONTCARE) {
12811 error:
12812 			/*
12813 			 * Rules 0 to i have malloc'd filters that need to be
12814 			 * freed.  Rules i+1 to nrules have userspace pointers
12815 			 * and should be left alone.
12816 			 */
12817 			op->nrules = i;
12818 			free_offload_policy(op);
12819 			return (rc);
12820 		}
12821 
12822 		/* Validate settings */
12823 		s = &r->settings;
12824 		if ((s->offload != 0 && s->offload != 1) ||
12825 		    s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
12826 		    s->sched_class < -1 ||
12827 		    s->sched_class >= sc->params.nsched_cls) {
12828 			rc = EINVAL;
12829 			goto error;
12830 		}
12831 
12832 		bf = &r->bpf_prog;
12833 		u = bf->bf_insns;	/* userspace ptr */
12834 		bf->bf_insns = NULL;
12835 		if (bf->bf_len == 0) {
12836 			/* legal, matches everything */
12837 			continue;
12838 		}
12839 		len = bf->bf_len * sizeof(*bf->bf_insns);
12840 		bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
12841 		rc = copyin(u, bf->bf_insns, len);
12842 		if (rc != 0)
12843 			goto error;
12844 
12845 		if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
12846 			rc = EINVAL;
12847 			goto error;
12848 		}
12849 	}
12850 set_policy:
12851 	rw_wlock(&sc->policy_lock);
12852 	old = sc->policy;
12853 	sc->policy = op;
12854 	rw_wunlock(&sc->policy_lock);
12855 	free_offload_policy(old);
12856 
12857 	return (0);
12858 }
12859 
12860 #define MAX_READ_BUF_SIZE (128 * 1024)
12861 static int
12862 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
12863 {
12864 	uint32_t addr, remaining, n;
12865 	uint32_t *buf;
12866 	int rc;
12867 	uint8_t *dst;
12868 
12869 	mtx_lock(&sc->reg_lock);
12870 	if (hw_off_limits(sc))
12871 		rc = ENXIO;
12872 	else
12873 		rc = validate_mem_range(sc, mr->addr, mr->len);
12874 	mtx_unlock(&sc->reg_lock);
12875 	if (rc != 0)
12876 		return (rc);
12877 
12878 	buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
12879 	addr = mr->addr;
12880 	remaining = mr->len;
12881 	dst = (void *)mr->data;
12882 
12883 	while (remaining) {
12884 		n = min(remaining, MAX_READ_BUF_SIZE);
12885 		mtx_lock(&sc->reg_lock);
12886 		if (hw_off_limits(sc))
12887 			rc = ENXIO;
12888 		else
12889 			read_via_memwin(sc, 2, addr, buf, n);
12890 		mtx_unlock(&sc->reg_lock);
12891 		if (rc != 0)
12892 			break;
12893 
12894 		rc = copyout(buf, dst, n);
12895 		if (rc != 0)
12896 			break;
12897 
12898 		dst += n;
12899 		remaining -= n;
12900 		addr += n;
12901 	}
12902 
12903 	free(buf, M_CXGBE);
12904 	return (rc);
12905 }
12906 #undef MAX_READ_BUF_SIZE
12907 
12908 static int
12909 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
12910 {
12911 	int rc;
12912 
12913 	if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
12914 		return (EINVAL);
12915 
12916 	if (i2cd->len > sizeof(i2cd->data))
12917 		return (EFBIG);
12918 
12919 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
12920 	if (rc)
12921 		return (rc);
12922 	if (hw_off_limits(sc))
12923 		rc = ENXIO;
12924 	else
12925 		rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
12926 		    i2cd->offset, i2cd->len, &i2cd->data[0]);
12927 	end_synchronized_op(sc, 0);
12928 
12929 	return (rc);
12930 }
12931 
12932 static int
12933 clear_stats(struct adapter *sc, u_int port_id)
12934 {
12935 	int i, v, chan_map;
12936 	struct port_info *pi;
12937 	struct vi_info *vi;
12938 	struct sge_rxq *rxq;
12939 	struct sge_txq *txq;
12940 	struct sge_wrq *wrq;
12941 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
12942 	struct sge_ofld_txq *ofld_txq;
12943 #endif
12944 #ifdef TCP_OFFLOAD
12945 	struct sge_ofld_rxq *ofld_rxq;
12946 #endif
12947 
12948 	if (port_id >= sc->params.nports)
12949 		return (EINVAL);
12950 	pi = sc->port[port_id];
12951 	if (pi == NULL)
12952 		return (EIO);
12953 
12954 	mtx_lock(&sc->reg_lock);
12955 	if (!hw_off_limits(sc)) {
12956 		/* MAC stats */
12957 		t4_clr_port_stats(sc, pi->hw_port);
12958 		if (is_t6(sc)) {
12959 			if (pi->fcs_reg != -1)
12960 				pi->fcs_base = t4_read_reg64(sc,
12961 				    t4_port_reg(sc, pi->tx_chan, pi->fcs_reg));
12962 			else
12963 				pi->stats.rx_fcs_err = 0;
12964 		}
12965 		for_each_vi(pi, v, vi) {
12966 			if (vi->flags & VI_INIT_DONE)
12967 				t4_clr_vi_stats(sc, vi->vin);
12968 		}
12969 		chan_map = pi->rx_e_chan_map;
12970 		v = 0;	/* reuse */
12971 		while (chan_map) {
12972 			i = ffs(chan_map) - 1;
12973 			t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
12974 			    1, A_TP_MIB_TNL_CNG_DROP_0 + i);
12975 			chan_map &= ~(1 << i);
12976 		}
12977 	}
12978 	mtx_unlock(&sc->reg_lock);
12979 	pi->tx_parse_error = 0;
12980 	pi->tnl_cong_drops = 0;
12981 
12982 	/*
12983 	 * Since this command accepts a port, clear stats for
12984 	 * all VIs on this port.
12985 	 */
12986 	for_each_vi(pi, v, vi) {
12987 		if (vi->flags & VI_INIT_DONE) {
12988 
12989 			for_each_rxq(vi, i, rxq) {
12990 #if defined(INET) || defined(INET6)
12991 				rxq->lro.lro_queued = 0;
12992 				rxq->lro.lro_flushed = 0;
12993 #endif
12994 				rxq->rxcsum = 0;
12995 				rxq->vlan_extraction = 0;
12996 				rxq->vxlan_rxcsum = 0;
12997 
12998 				rxq->fl.cl_allocated = 0;
12999 				rxq->fl.cl_recycled = 0;
13000 				rxq->fl.cl_fast_recycled = 0;
13001 			}
13002 
13003 			for_each_txq(vi, i, txq) {
13004 				txq->txcsum = 0;
13005 				txq->tso_wrs = 0;
13006 				txq->vlan_insertion = 0;
13007 				txq->imm_wrs = 0;
13008 				txq->sgl_wrs = 0;
13009 				txq->txpkt_wrs = 0;
13010 				txq->txpkts0_wrs = 0;
13011 				txq->txpkts1_wrs = 0;
13012 				txq->txpkts0_pkts = 0;
13013 				txq->txpkts1_pkts = 0;
13014 				txq->txpkts_flush = 0;
13015 				txq->raw_wrs = 0;
13016 				txq->vxlan_tso_wrs = 0;
13017 				txq->vxlan_txcsum = 0;
13018 				txq->kern_tls_records = 0;
13019 				txq->kern_tls_short = 0;
13020 				txq->kern_tls_partial = 0;
13021 				txq->kern_tls_full = 0;
13022 				txq->kern_tls_octets = 0;
13023 				txq->kern_tls_waste = 0;
13024 				txq->kern_tls_header = 0;
13025 				txq->kern_tls_fin_short = 0;
13026 				txq->kern_tls_cbc = 0;
13027 				txq->kern_tls_gcm = 0;
13028 				if (is_t6(sc)) {
13029 					txq->kern_tls_options = 0;
13030 					txq->kern_tls_fin = 0;
13031 				} else {
13032 					txq->kern_tls_ghash_received = 0;
13033 					txq->kern_tls_ghash_requested = 0;
13034 					txq->kern_tls_lso = 0;
13035 					txq->kern_tls_partial_ghash = 0;
13036 					txq->kern_tls_splitmode = 0;
13037 					txq->kern_tls_trailer = 0;
13038 				}
13039 				mp_ring_reset_stats(txq->r);
13040 			}
13041 
13042 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
13043 			for_each_ofld_txq(vi, i, ofld_txq) {
13044 				ofld_txq->wrq.tx_wrs_direct = 0;
13045 				ofld_txq->wrq.tx_wrs_copied = 0;
13046 				counter_u64_zero(ofld_txq->tx_iscsi_pdus);
13047 				counter_u64_zero(ofld_txq->tx_iscsi_octets);
13048 				counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs);
13049 				counter_u64_zero(ofld_txq->tx_nvme_pdus);
13050 				counter_u64_zero(ofld_txq->tx_nvme_octets);
13051 				counter_u64_zero(ofld_txq->tx_nvme_iso_wrs);
13052 				counter_u64_zero(ofld_txq->tx_aio_jobs);
13053 				counter_u64_zero(ofld_txq->tx_aio_octets);
13054 				counter_u64_zero(ofld_txq->tx_toe_tls_records);
13055 				counter_u64_zero(ofld_txq->tx_toe_tls_octets);
13056 			}
13057 #endif
13058 #ifdef TCP_OFFLOAD
13059 			for_each_ofld_rxq(vi, i, ofld_rxq) {
13060 				ofld_rxq->fl.cl_allocated = 0;
13061 				ofld_rxq->fl.cl_recycled = 0;
13062 				ofld_rxq->fl.cl_fast_recycled = 0;
13063 				counter_u64_zero(
13064 				    ofld_rxq->rx_iscsi_ddp_setup_ok);
13065 				counter_u64_zero(
13066 				    ofld_rxq->rx_iscsi_ddp_setup_error);
13067 				ofld_rxq->rx_iscsi_ddp_pdus = 0;
13068 				ofld_rxq->rx_iscsi_ddp_octets = 0;
13069 				ofld_rxq->rx_iscsi_fl_pdus = 0;
13070 				ofld_rxq->rx_iscsi_fl_octets = 0;
13071 				counter_u64_zero(
13072 				    ofld_rxq->rx_nvme_ddp_setup_ok);
13073 				counter_u64_zero(
13074 				    ofld_rxq->rx_nvme_ddp_setup_no_stag);
13075 				counter_u64_zero(
13076 				    ofld_rxq->rx_nvme_ddp_setup_error);
13077 				counter_u64_zero(ofld_rxq->rx_nvme_ddp_pdus);
13078 				counter_u64_zero(ofld_rxq->rx_nvme_ddp_octets);
13079 				counter_u64_zero(ofld_rxq->rx_nvme_fl_pdus);
13080 				counter_u64_zero(ofld_rxq->rx_nvme_fl_octets);
13081 				counter_u64_zero(
13082 				    ofld_rxq->rx_nvme_invalid_headers);
13083 				counter_u64_zero(
13084 				    ofld_rxq->rx_nvme_header_digest_errors);
13085 				counter_u64_zero(
13086 				    ofld_rxq->rx_nvme_data_digest_errors);
13087 				ofld_rxq->rx_aio_ddp_jobs = 0;
13088 				ofld_rxq->rx_aio_ddp_octets = 0;
13089 				ofld_rxq->rx_toe_tls_records = 0;
13090 				ofld_rxq->rx_toe_tls_octets = 0;
13091 				ofld_rxq->rx_toe_ddp_octets = 0;
13092 				counter_u64_zero(ofld_rxq->ddp_buffer_alloc);
13093 				counter_u64_zero(ofld_rxq->ddp_buffer_reuse);
13094 				counter_u64_zero(ofld_rxq->ddp_buffer_free);
13095 			}
13096 #endif
13097 
13098 			if (IS_MAIN_VI(vi)) {
13099 				wrq = &sc->sge.ctrlq[pi->port_id];
13100 				wrq->tx_wrs_direct = 0;
13101 				wrq->tx_wrs_copied = 0;
13102 			}
13103 		}
13104 	}
13105 
13106 	return (0);
13107 }
13108 
13109 static int
13110 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
13111 {
13112 #ifdef INET6
13113 	struct in6_addr in6;
13114 
13115 	bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
13116 	if (t4_get_clip_entry(sc, &in6, true) != NULL)
13117 		return (0);
13118 	else
13119 		return (EIO);
13120 #else
13121 	return (ENOTSUP);
13122 #endif
13123 }
13124 
13125 static int
13126 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
13127 {
13128 #ifdef INET6
13129 	struct in6_addr in6;
13130 
13131 	bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
13132 	return (t4_release_clip_addr(sc, &in6));
13133 #else
13134 	return (ENOTSUP);
13135 #endif
13136 }
13137 
13138 int
13139 t4_os_find_pci_capability(struct adapter *sc, int cap)
13140 {
13141 	int i;
13142 
13143 	return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
13144 }
13145 
13146 void
13147 t4_os_portmod_changed(struct port_info *pi)
13148 {
13149 	struct adapter *sc = pi->adapter;
13150 	struct vi_info *vi;
13151 	if_t ifp;
13152 	static const char *mod_str[] = {
13153 		NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM",
13154 		"LR_SIMPLEX", "DR"
13155 	};
13156 
13157 	KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
13158 	    ("%s: port_type %u", __func__, pi->port_type));
13159 
13160 	vi = &pi->vi[0];
13161 	if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
13162 		PORT_LOCK(pi);
13163 		build_medialist(pi);
13164 		if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
13165 			fixup_link_config(pi);
13166 			apply_link_config(pi);
13167 		}
13168 		PORT_UNLOCK(pi);
13169 		end_synchronized_op(sc, LOCK_HELD);
13170 	}
13171 
13172 	ifp = vi->ifp;
13173 	if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
13174 		if_printf(ifp, "transceiver unplugged.\n");
13175 	else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
13176 		if_printf(ifp, "unknown transceiver inserted.\n");
13177 	else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
13178 		if_printf(ifp, "unsupported transceiver inserted.\n");
13179 	else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
13180 		if_printf(ifp, "%dGbps %s transceiver inserted.\n",
13181 		    port_top_speed(pi), mod_str[pi->mod_type]);
13182 	} else {
13183 		if_printf(ifp, "transceiver (type %d) inserted.\n",
13184 		    pi->mod_type);
13185 	}
13186 }
13187 
13188 void
13189 t4_os_link_changed(struct port_info *pi)
13190 {
13191 	struct vi_info *vi;
13192 	if_t ifp;
13193 	struct link_config *lc = &pi->link_cfg;
13194 	struct adapter *sc = pi->adapter;
13195 	int v;
13196 
13197 	PORT_LOCK_ASSERT_OWNED(pi);
13198 
13199 	if (is_t6(sc)) {
13200 		if (lc->link_ok) {
13201 			if (lc->speed > 25000 ||
13202 			    (lc->speed == 25000 && lc->fec == FEC_RS))
13203 				pi->fcs_reg = A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS;
13204 			else
13205 				pi->fcs_reg = A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS;
13206 			pi->fcs_base = t4_read_reg64(sc,
13207 			    t4_port_reg(sc, pi->tx_chan, pi->fcs_reg));
13208 			pi->stats.rx_fcs_err = 0;
13209 		} else {
13210 			pi->fcs_reg = -1;
13211 		}
13212 	} else {
13213 		MPASS(pi->fcs_reg != -1);
13214 		MPASS(pi->fcs_base == 0);
13215 	}
13216 
13217 	for_each_vi(pi, v, vi) {
13218 		ifp = vi->ifp;
13219 		if (ifp == NULL || IS_DETACHING(vi))
13220 			continue;
13221 
13222 		if (lc->link_ok) {
13223 			if_setbaudrate(ifp, IF_Mbps(lc->speed));
13224 			if_link_state_change(ifp, LINK_STATE_UP);
13225 		} else {
13226 			if_link_state_change(ifp, LINK_STATE_DOWN);
13227 		}
13228 	}
13229 }
13230 
13231 void
13232 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
13233 {
13234 	struct adapter *sc;
13235 
13236 	sx_slock(&t4_list_lock);
13237 	SLIST_FOREACH(sc, &t4_list, link) {
13238 		/*
13239 		 * func should not make any assumptions about what state sc is
13240 		 * in - the only guarantee is that sc->sc_lock is a valid lock.
13241 		 */
13242 		func(sc, arg);
13243 	}
13244 	sx_sunlock(&t4_list_lock);
13245 }
13246 
13247 static int
13248 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
13249     struct thread *td)
13250 {
13251 	int rc;
13252 	struct adapter *sc = dev->si_drv1;
13253 
13254 	rc = priv_check(td, PRIV_DRIVER);
13255 	if (rc != 0)
13256 		return (rc);
13257 
13258 	switch (cmd) {
13259 	case CHELSIO_T4_GETREG: {
13260 		struct t4_reg *edata = (struct t4_reg *)data;
13261 
13262 		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
13263 			return (EFAULT);
13264 
13265 		mtx_lock(&sc->reg_lock);
13266 		if (hw_off_limits(sc))
13267 			rc = ENXIO;
13268 		else if (edata->size == 4)
13269 			edata->val = t4_read_reg(sc, edata->addr);
13270 		else if (edata->size == 8)
13271 			edata->val = t4_read_reg64(sc, edata->addr);
13272 		else
13273 			rc = EINVAL;
13274 		mtx_unlock(&sc->reg_lock);
13275 
13276 		break;
13277 	}
13278 	case CHELSIO_T4_SETREG: {
13279 		struct t4_reg *edata = (struct t4_reg *)data;
13280 
13281 		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
13282 			return (EFAULT);
13283 
13284 		mtx_lock(&sc->reg_lock);
13285 		if (hw_off_limits(sc))
13286 			rc = ENXIO;
13287 		else if (edata->size == 4) {
13288 			if (edata->val & 0xffffffff00000000)
13289 				rc = EINVAL;
13290 			t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
13291 		} else if (edata->size == 8)
13292 			t4_write_reg64(sc, edata->addr, edata->val);
13293 		else
13294 			rc = EINVAL;
13295 		mtx_unlock(&sc->reg_lock);
13296 
13297 		break;
13298 	}
13299 	case CHELSIO_T4_REGDUMP: {
13300 		struct t4_regdump *regs = (struct t4_regdump *)data;
13301 		int reglen = t4_get_regs_len(sc);
13302 		uint8_t *buf;
13303 
13304 		if (regs->len < reglen) {
13305 			regs->len = reglen; /* hint to the caller */
13306 			return (ENOBUFS);
13307 		}
13308 
13309 		regs->len = reglen;
13310 		buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
13311 		mtx_lock(&sc->reg_lock);
13312 		if (hw_off_limits(sc))
13313 			rc = ENXIO;
13314 		else
13315 			get_regs(sc, regs, buf);
13316 		mtx_unlock(&sc->reg_lock);
13317 		if (rc == 0)
13318 			rc = copyout(buf, regs->data, reglen);
13319 		free(buf, M_CXGBE);
13320 		break;
13321 	}
13322 	case CHELSIO_T4_GET_FILTER_MODE:
13323 		rc = get_filter_mode(sc, (uint32_t *)data);
13324 		break;
13325 	case CHELSIO_T4_SET_FILTER_MODE:
13326 		rc = set_filter_mode(sc, *(uint32_t *)data);
13327 		break;
13328 	case CHELSIO_T4_SET_FILTER_MASK:
13329 		rc = set_filter_mask(sc, *(uint32_t *)data);
13330 		break;
13331 	case CHELSIO_T4_GET_FILTER:
13332 		rc = get_filter(sc, (struct t4_filter *)data);
13333 		break;
13334 	case CHELSIO_T4_SET_FILTER:
13335 		rc = set_filter(sc, (struct t4_filter *)data);
13336 		break;
13337 	case CHELSIO_T4_DEL_FILTER:
13338 		rc = del_filter(sc, (struct t4_filter *)data);
13339 		break;
13340 	case CHELSIO_T4_GET_SGE_CONTEXT: {
13341 		struct t4_sge_context *ctxt = (struct t4_sge_context *)data;
13342 
13343 		rc = get_sge_context(sc, ctxt->mem_id, ctxt->cid,
13344 		    sizeof(ctxt->data), &ctxt->data[0]);
13345 		break;
13346 	}
13347 	case CHELSIO_T4_LOAD_FW:
13348 		rc = load_fw(sc, (struct t4_data *)data);
13349 		break;
13350 	case CHELSIO_T4_GET_MEM:
13351 		rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
13352 		break;
13353 	case CHELSIO_T4_GET_I2C:
13354 		rc = read_i2c(sc, (struct t4_i2c_data *)data);
13355 		break;
13356 	case CHELSIO_T4_CLEAR_STATS:
13357 		rc = clear_stats(sc, *(uint32_t *)data);
13358 		break;
13359 	case CHELSIO_T4_SCHED_CLASS:
13360 		rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
13361 		break;
13362 	case CHELSIO_T4_SCHED_QUEUE:
13363 		rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
13364 		break;
13365 	case CHELSIO_T4_GET_TRACER:
13366 		rc = t4_get_tracer(sc, (struct t4_tracer *)data);
13367 		break;
13368 	case CHELSIO_T4_SET_TRACER:
13369 		rc = t4_set_tracer(sc, (struct t4_tracer *)data);
13370 		break;
13371 	case CHELSIO_T4_LOAD_CFG:
13372 		rc = load_cfg(sc, (struct t4_data *)data);
13373 		break;
13374 	case CHELSIO_T4_LOAD_BOOT:
13375 		rc = load_boot(sc, (struct t4_bootrom *)data);
13376 		break;
13377 	case CHELSIO_T4_LOAD_BOOTCFG:
13378 		rc = load_bootcfg(sc, (struct t4_data *)data);
13379 		break;
13380 	case CHELSIO_T4_CUDBG_DUMP:
13381 		rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
13382 		break;
13383 	case CHELSIO_T4_SET_OFLD_POLICY:
13384 		rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
13385 		break;
13386 	case CHELSIO_T4_HOLD_CLIP_ADDR:
13387 		rc = hold_clip_addr(sc, (struct t4_clip_addr *)data);
13388 		break;
13389 	case CHELSIO_T4_RELEASE_CLIP_ADDR:
13390 		rc = release_clip_addr(sc, (struct t4_clip_addr *)data);
13391 		break;
13392 	case CHELSIO_T4_GET_SGE_CTXT: {
13393 		struct t4_sge_ctxt *ctxt = (struct t4_sge_ctxt *)data;
13394 
13395 		rc = get_sge_context(sc, ctxt->mem_id, ctxt->cid,
13396 		    sizeof(ctxt->data), &ctxt->data[0]);
13397 		break;
13398 	}
13399 	default:
13400 		rc = ENOTTY;
13401 	}
13402 
13403 	return (rc);
13404 }
13405 
13406 #ifdef TCP_OFFLOAD
13407 int
13408 toe_capability(struct vi_info *vi, bool enable)
13409 {
13410 	int rc;
13411 	struct port_info *pi = vi->pi;
13412 	struct adapter *sc = pi->adapter;
13413 
13414 	ASSERT_SYNCHRONIZED_OP(sc);
13415 
13416 	if (!is_offload(sc))
13417 		return (ENODEV);
13418 	if (!hw_all_ok(sc))
13419 		return (ENXIO);
13420 
13421 	if (enable) {
13422 #ifdef KERN_TLS
13423 		if (sc->flags & KERN_TLS_ON && is_t6(sc)) {
13424 			int i, j, n;
13425 			struct port_info *p;
13426 			struct vi_info *v;
13427 
13428 			/*
13429 			 * Reconfigure hardware for TOE if TXTLS is not enabled
13430 			 * on any ifnet.
13431 			 */
13432 			n = 0;
13433 			for_each_port(sc, i) {
13434 				p = sc->port[i];
13435 				for_each_vi(p, j, v) {
13436 					if (if_getcapenable(v->ifp) & IFCAP_TXTLS) {
13437 						CH_WARN(sc,
13438 						    "%s has NIC TLS enabled.\n",
13439 						    device_get_nameunit(v->dev));
13440 						n++;
13441 					}
13442 				}
13443 			}
13444 			if (n > 0) {
13445 				CH_WARN(sc, "Disable NIC TLS on all interfaces "
13446 				    "associated with this adapter before "
13447 				    "trying to enable TOE.\n");
13448 				return (EAGAIN);
13449 			}
13450 			rc = t6_config_kern_tls(sc, false);
13451 			if (rc)
13452 				return (rc);
13453 		}
13454 #endif
13455 		if ((if_getcapenable(vi->ifp) & IFCAP_TOE) != 0) {
13456 			/* TOE is already enabled. */
13457 			return (0);
13458 		}
13459 
13460 		/*
13461 		 * We need the port's queues around so that we're able to send
13462 		 * and receive CPLs to/from the TOE even if the ifnet for this
13463 		 * port has never been UP'd administratively.
13464 		 */
13465 		if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
13466 			return (rc);
13467 		if (!(pi->vi[0].flags & VI_INIT_DONE) &&
13468 		    ((rc = vi_init(&pi->vi[0])) != 0))
13469 			return (rc);
13470 
13471 		if (isset(&sc->offload_map, pi->port_id)) {
13472 			/* TOE is enabled on another VI of this port. */
13473 			MPASS(pi->uld_vis > 0);
13474 			pi->uld_vis++;
13475 			return (0);
13476 		}
13477 
13478 		if (!uld_active(sc, ULD_TOM)) {
13479 			rc = t4_activate_uld(sc, ULD_TOM);
13480 			if (rc == EAGAIN) {
13481 				log(LOG_WARNING,
13482 				    "You must kldload t4_tom.ko before trying "
13483 				    "to enable TOE on a cxgbe interface.\n");
13484 			}
13485 			if (rc != 0)
13486 				return (rc);
13487 			KASSERT(sc->tom_softc != NULL,
13488 			    ("%s: TOM activated but softc NULL", __func__));
13489 			KASSERT(uld_active(sc, ULD_TOM),
13490 			    ("%s: TOM activated but flag not set", __func__));
13491 		}
13492 
13493 		/*
13494 		 * Activate iWARP, iSCSI, and NVMe too, if the modules
13495 		 * are loaded.
13496 		 */
13497 		if (!uld_active(sc, ULD_IWARP))
13498 			(void) t4_activate_uld(sc, ULD_IWARP);
13499 		if (!uld_active(sc, ULD_ISCSI))
13500 			(void) t4_activate_uld(sc, ULD_ISCSI);
13501 		if (!uld_active(sc, ULD_NVME))
13502 			(void) t4_activate_uld(sc, ULD_NVME);
13503 
13504 		if (pi->uld_vis++ == 0)
13505 			setbit(&sc->offload_map, pi->port_id);
13506 	} else {
13507 		if ((if_getcapenable(vi->ifp) & IFCAP_TOE) == 0) {
13508 			/* TOE is already disabled. */
13509 			return (0);
13510 		}
13511 		MPASS(isset(&sc->offload_map, pi->port_id));
13512 		MPASS(pi->uld_vis > 0);
13513 		if (--pi->uld_vis == 0)
13514 			clrbit(&sc->offload_map, pi->port_id);
13515 	}
13516 
13517 	return (0);
13518 }
13519 
13520 /*
13521  * Add an upper layer driver to the global list.
13522  */
13523 int
13524 t4_register_uld(struct uld_info *ui, int id)
13525 {
13526 	int rc;
13527 
13528 	if (id < 0 || id > ULD_MAX)
13529 		return (EINVAL);
13530 	sx_xlock(&t4_uld_list_lock);
13531 	if (t4_uld_list[id] != NULL)
13532 		rc = EEXIST;
13533 	else {
13534 		t4_uld_list[id] = ui;
13535 		rc = 0;
13536 	}
13537 	sx_xunlock(&t4_uld_list_lock);
13538 	return (rc);
13539 }
13540 
13541 int
13542 t4_unregister_uld(struct uld_info *ui, int id)
13543 {
13544 
13545 	if (id < 0 || id > ULD_MAX)
13546 		return (EINVAL);
13547 	sx_xlock(&t4_uld_list_lock);
13548 	MPASS(t4_uld_list[id] == ui);
13549 	t4_uld_list[id] = NULL;
13550 	sx_xunlock(&t4_uld_list_lock);
13551 	return (0);
13552 }
13553 
13554 int
13555 t4_activate_uld(struct adapter *sc, int id)
13556 {
13557 	int rc;
13558 
13559 	ASSERT_SYNCHRONIZED_OP(sc);
13560 
13561 	if (id < 0 || id > ULD_MAX)
13562 		return (EINVAL);
13563 
13564 	/* Adapter needs to be initialized before any ULD can be activated. */
13565 	if (!(sc->flags & FULL_INIT_DONE)) {
13566 		rc = adapter_init(sc);
13567 		if (rc != 0)
13568 			return (rc);
13569 	}
13570 
13571 	sx_slock(&t4_uld_list_lock);
13572 	if (t4_uld_list[id] == NULL)
13573 		rc = EAGAIN;	/* load the KLD with this ULD and try again. */
13574 	else {
13575 		rc = t4_uld_list[id]->uld_activate(sc);
13576 		if (rc == 0)
13577 			setbit(&sc->active_ulds, id);
13578 	}
13579 	sx_sunlock(&t4_uld_list_lock);
13580 
13581 	return (rc);
13582 }
13583 
13584 int
13585 t4_deactivate_uld(struct adapter *sc, int id)
13586 {
13587 	int rc;
13588 
13589 	ASSERT_SYNCHRONIZED_OP(sc);
13590 
13591 	if (id < 0 || id > ULD_MAX)
13592 		return (EINVAL);
13593 
13594 	sx_slock(&t4_uld_list_lock);
13595 	if (t4_uld_list[id] == NULL)
13596 		rc = ENXIO;
13597 	else {
13598 		rc = t4_uld_list[id]->uld_deactivate(sc);
13599 		if (rc == 0)
13600 			clrbit(&sc->active_ulds, id);
13601 	}
13602 	sx_sunlock(&t4_uld_list_lock);
13603 
13604 	return (rc);
13605 }
13606 
13607 static int
13608 deactivate_all_uld(struct adapter *sc)
13609 {
13610 	int i, rc;
13611 
13612 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld");
13613 	if (rc != 0)
13614 		return (ENXIO);
13615 	sx_slock(&t4_uld_list_lock);
13616 	for (i = 0; i <= ULD_MAX; i++) {
13617 		if (t4_uld_list[i] == NULL || !uld_active(sc, i))
13618 			continue;
13619 		rc = t4_uld_list[i]->uld_deactivate(sc);
13620 		if (rc != 0)
13621 			break;
13622 		clrbit(&sc->active_ulds, i);
13623 	}
13624 	sx_sunlock(&t4_uld_list_lock);
13625 	end_synchronized_op(sc, 0);
13626 
13627 	return (rc);
13628 }
13629 
13630 static void
13631 stop_all_uld(struct adapter *sc)
13632 {
13633 	int i;
13634 
13635 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldst") != 0)
13636 		return;
13637 	sx_slock(&t4_uld_list_lock);
13638 	for (i = 0; i <= ULD_MAX; i++) {
13639 		if (t4_uld_list[i] == NULL || !uld_active(sc, i) ||
13640 		    t4_uld_list[i]->uld_stop == NULL)
13641 			continue;
13642 		(void) t4_uld_list[i]->uld_stop(sc);
13643 	}
13644 	sx_sunlock(&t4_uld_list_lock);
13645 	end_synchronized_op(sc, 0);
13646 }
13647 
13648 static void
13649 restart_all_uld(struct adapter *sc)
13650 {
13651 	int i;
13652 
13653 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldre") != 0)
13654 		return;
13655 	sx_slock(&t4_uld_list_lock);
13656 	for (i = 0; i <= ULD_MAX; i++) {
13657 		if (t4_uld_list[i] == NULL || !uld_active(sc, i) ||
13658 		    t4_uld_list[i]->uld_restart == NULL)
13659 			continue;
13660 		(void) t4_uld_list[i]->uld_restart(sc);
13661 	}
13662 	sx_sunlock(&t4_uld_list_lock);
13663 	end_synchronized_op(sc, 0);
13664 }
13665 
13666 int
13667 uld_active(struct adapter *sc, int id)
13668 {
13669 
13670 	MPASS(id >= 0 && id <= ULD_MAX);
13671 
13672 	return (isset(&sc->active_ulds, id));
13673 }
13674 #endif
13675 
13676 #ifdef KERN_TLS
13677 static int
13678 ktls_capability(struct adapter *sc, bool enable)
13679 {
13680 	ASSERT_SYNCHRONIZED_OP(sc);
13681 
13682 	if (!is_ktls(sc))
13683 		return (ENODEV);
13684 	if (!is_t6(sc))
13685 		return (0);
13686 	if (!hw_all_ok(sc))
13687 		return (ENXIO);
13688 
13689 	if (enable) {
13690 		if (sc->flags & KERN_TLS_ON)
13691 			return (0);	/* already on */
13692 		if (sc->offload_map != 0) {
13693 			CH_WARN(sc,
13694 			    "Disable TOE on all interfaces associated with "
13695 			    "this adapter before trying to enable NIC TLS.\n");
13696 			return (EAGAIN);
13697 		}
13698 		return (t6_config_kern_tls(sc, true));
13699 	} else {
13700 		/*
13701 		 * Nothing to do for disable.  If TOE is enabled sometime later
13702 		 * then toe_capability will reconfigure the hardware.
13703 		 */
13704 		return (0);
13705 	}
13706 }
13707 #endif
13708 
13709 /*
13710  * t  = ptr to tunable.
13711  * nc = number of CPUs.
13712  * c  = compiled in default for that tunable.
13713  */
13714 static void
13715 calculate_nqueues(int *t, int nc, const int c)
13716 {
13717 	int nq;
13718 
13719 	if (*t > 0)
13720 		return;
13721 	nq = *t < 0 ? -*t : c;
13722 	*t = min(nc, nq);
13723 }
13724 
13725 /*
13726  * Come up with reasonable defaults for some of the tunables, provided they're
13727  * not set by the user (in which case we'll use the values as is).
13728  */
13729 static void
13730 tweak_tunables(void)
13731 {
13732 	int nc = mp_ncpus;	/* our snapshot of the number of CPUs */
13733 
13734 	if (t4_ntxq < 1) {
13735 #ifdef RSS
13736 		t4_ntxq = rss_getnumbuckets();
13737 #else
13738 		calculate_nqueues(&t4_ntxq, nc, NTXQ);
13739 #endif
13740 	}
13741 
13742 	calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
13743 
13744 	if (t4_nrxq < 1) {
13745 #ifdef RSS
13746 		t4_nrxq = rss_getnumbuckets();
13747 #else
13748 		calculate_nqueues(&t4_nrxq, nc, NRXQ);
13749 #endif
13750 	}
13751 
13752 	calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
13753 
13754 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
13755 	calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
13756 	calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
13757 #endif
13758 #ifdef TCP_OFFLOAD
13759 	calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
13760 	calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
13761 #endif
13762 
13763 #if defined(TCP_OFFLOAD) || defined(KERN_TLS)
13764 	if (t4_toecaps_allowed == -1)
13765 		t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
13766 #else
13767 	if (t4_toecaps_allowed == -1)
13768 		t4_toecaps_allowed = 0;
13769 #endif
13770 
13771 #ifdef TCP_OFFLOAD
13772 	if (t4_rdmacaps_allowed == -1) {
13773 		t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
13774 		    FW_CAPS_CONFIG_RDMA_RDMAC;
13775 	}
13776 
13777 	if (t4_iscsicaps_allowed == -1) {
13778 		t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
13779 		    FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
13780 		    FW_CAPS_CONFIG_ISCSI_T10DIF;
13781 	}
13782 
13783 	if (t4_nvmecaps_allowed == -1)
13784 		t4_nvmecaps_allowed = FW_CAPS_CONFIG_NVME_TCP;
13785 
13786 	if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
13787 		t4_tmr_idx_ofld = TMR_IDX_OFLD;
13788 
13789 	if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
13790 		t4_pktc_idx_ofld = PKTC_IDX_OFLD;
13791 #else
13792 	if (t4_rdmacaps_allowed == -1)
13793 		t4_rdmacaps_allowed = 0;
13794 
13795 	if (t4_iscsicaps_allowed == -1)
13796 		t4_iscsicaps_allowed = 0;
13797 
13798 	if (t4_nvmecaps_allowed == -1)
13799 		t4_nvmecaps_allowed = 0;
13800 #endif
13801 
13802 #ifdef DEV_NETMAP
13803 	calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ);
13804 	calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ);
13805 	calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
13806 	calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
13807 #endif
13808 
13809 	if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
13810 		t4_tmr_idx = TMR_IDX;
13811 
13812 	if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
13813 		t4_pktc_idx = PKTC_IDX;
13814 
13815 	if (t4_qsize_txq < 128)
13816 		t4_qsize_txq = 128;
13817 
13818 	if (t4_qsize_rxq < 128)
13819 		t4_qsize_rxq = 128;
13820 	while (t4_qsize_rxq & 7)
13821 		t4_qsize_rxq++;
13822 
13823 	t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
13824 
13825 	/*
13826 	 * Number of VIs to create per-port.  The first VI is the "main" regular
13827 	 * VI for the port.  The rest are additional virtual interfaces on the
13828 	 * same physical port.  Note that the main VI does not have native
13829 	 * netmap support but the extra VIs do.
13830 	 *
13831 	 * Limit the number of VIs per port to the number of available
13832 	 * MAC addresses per port.
13833 	 */
13834 	if (t4_num_vis < 1)
13835 		t4_num_vis = 1;
13836 	if (t4_num_vis > nitems(vi_mac_funcs)) {
13837 		t4_num_vis = nitems(vi_mac_funcs);
13838 		printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
13839 	}
13840 
13841 	if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
13842 		pcie_relaxed_ordering = 1;
13843 #if defined(__i386__) || defined(__amd64__)
13844 		if (cpu_vendor_id == CPU_VENDOR_INTEL)
13845 			pcie_relaxed_ordering = 0;
13846 #endif
13847 	}
13848 }
13849 
13850 #ifdef DDB
13851 static void
13852 t4_dump_mem(struct adapter *sc, u_int addr, u_int len)
13853 {
13854 	uint32_t base, j, off, pf, reg, save, win_pos;
13855 
13856 	reg = chip_id(sc) > CHELSIO_T6 ?
13857 	    PCIE_MEM_ACCESS_T7_REG(A_PCIE_MEM_ACCESS_OFFSET0, 2) :
13858 	    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
13859 	save = t4_read_reg(sc, reg);
13860 	base = sc->memwin[2].mw_base;
13861 
13862 	if (is_t4(sc)) {
13863 		pf = 0;
13864 		win_pos = addr & ~0xf;	/* start must be 16B aligned */
13865 	} else {
13866 		pf = V_PFNUM(sc->pf);
13867 		win_pos = addr & ~0x7f;	/* start must be 128B aligned */
13868 	}
13869 	off = addr - win_pos;
13870 	if (chip_id(sc) > CHELSIO_T6)
13871 		win_pos >>= X_T7_MEMOFST_SHIFT;
13872 	t4_write_reg(sc, reg, win_pos | pf);
13873 	t4_read_reg(sc, reg);
13874 
13875 	while (len > 0 && !db_pager_quit) {
13876 		uint32_t buf[8];
13877 		for (j = 0; j < 8; j++, off += 4)
13878 			buf[j] = htonl(t4_read_reg(sc, base + off));
13879 
13880 		db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
13881 		    buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
13882 		    buf[7]);
13883 		if (len <= sizeof(buf))
13884 			len = 0;
13885 		else
13886 			len -= sizeof(buf);
13887 	}
13888 
13889 	t4_write_reg(sc, reg, save);
13890 	t4_read_reg(sc, reg);
13891 }
13892 
13893 static void
13894 t4_dump_tcb(struct adapter *sc, int tid)
13895 {
13896 	uint32_t tcb_addr;
13897 
13898 	/* Dump TCB for the tid */
13899 	tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
13900 	tcb_addr += tid * TCB_SIZE;
13901 	t4_dump_mem(sc, tcb_addr, TCB_SIZE);
13902 }
13903 
13904 static void
13905 t4_dump_devlog(struct adapter *sc)
13906 {
13907 	struct devlog_params *dparams = &sc->params.devlog;
13908 	struct fw_devlog_e e;
13909 	int i, first, j, m, nentries, rc;
13910 	uint64_t ftstamp = UINT64_MAX;
13911 
13912 	if (dparams->start == 0) {
13913 		db_printf("devlog params not valid\n");
13914 		return;
13915 	}
13916 
13917 	nentries = dparams->size / sizeof(struct fw_devlog_e);
13918 	m = fwmtype_to_hwmtype(dparams->memtype);
13919 
13920 	/* Find the first entry. */
13921 	first = -1;
13922 	for (i = 0; i < nentries && !db_pager_quit; i++) {
13923 		rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
13924 		    sizeof(e), (void *)&e);
13925 		if (rc != 0)
13926 			break;
13927 
13928 		if (e.timestamp == 0)
13929 			break;
13930 
13931 		e.timestamp = be64toh(e.timestamp);
13932 		if (e.timestamp < ftstamp) {
13933 			ftstamp = e.timestamp;
13934 			first = i;
13935 		}
13936 	}
13937 
13938 	if (first == -1)
13939 		return;
13940 
13941 	i = first;
13942 	do {
13943 		rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
13944 		    sizeof(e), (void *)&e);
13945 		if (rc != 0)
13946 			return;
13947 
13948 		if (e.timestamp == 0)
13949 			return;
13950 
13951 		e.timestamp = be64toh(e.timestamp);
13952 		e.seqno = be32toh(e.seqno);
13953 		for (j = 0; j < 8; j++)
13954 			e.params[j] = be32toh(e.params[j]);
13955 
13956 		db_printf("%10d  %15ju  %8s  %8s  ",
13957 		    e.seqno, e.timestamp,
13958 		    (e.level < nitems(devlog_level_strings) ?
13959 			devlog_level_strings[e.level] : "UNKNOWN"),
13960 		    (e.facility < nitems(devlog_facility_strings) ?
13961 			devlog_facility_strings[e.facility] : "UNKNOWN"));
13962 		db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
13963 		    e.params[3], e.params[4], e.params[5], e.params[6],
13964 		    e.params[7]);
13965 
13966 		if (++i == nentries)
13967 			i = 0;
13968 	} while (i != first && !db_pager_quit);
13969 }
13970 
13971 static DB_DEFINE_TABLE(show, t4, show_t4);
13972 
13973 DB_TABLE_COMMAND_FLAGS(show_t4, devlog, db_show_devlog, CS_OWN)
13974 {
13975 	device_t dev;
13976 	int t;
13977 	bool valid;
13978 
13979 	valid = false;
13980 	t = db_read_token();
13981 	if (t == tIDENT) {
13982 		dev = device_lookup_by_name(db_tok_string);
13983 		valid = true;
13984 	}
13985 	db_skip_to_eol();
13986 	if (!valid) {
13987 		db_printf("usage: show t4 devlog <nexus>\n");
13988 		return;
13989 	}
13990 
13991 	if (dev == NULL) {
13992 		db_printf("device not found\n");
13993 		return;
13994 	}
13995 
13996 	t4_dump_devlog(device_get_softc(dev));
13997 }
13998 
13999 DB_TABLE_COMMAND_FLAGS(show_t4, tcb, db_show_t4tcb, CS_OWN)
14000 {
14001 	device_t dev;
14002 	int radix, tid, t;
14003 	bool valid;
14004 
14005 	valid = false;
14006 	radix = db_radix;
14007 	db_radix = 10;
14008 	t = db_read_token();
14009 	if (t == tIDENT) {
14010 		dev = device_lookup_by_name(db_tok_string);
14011 		t = db_read_token();
14012 		if (t == tNUMBER) {
14013 			tid = db_tok_number;
14014 			valid = true;
14015 		}
14016 	}
14017 	db_radix = radix;
14018 	db_skip_to_eol();
14019 	if (!valid) {
14020 		db_printf("usage: show t4 tcb <nexus> <tid>\n");
14021 		return;
14022 	}
14023 
14024 	if (dev == NULL) {
14025 		db_printf("device not found\n");
14026 		return;
14027 	}
14028 	if (tid < 0) {
14029 		db_printf("invalid tid\n");
14030 		return;
14031 	}
14032 
14033 	t4_dump_tcb(device_get_softc(dev), tid);
14034 }
14035 
14036 DB_TABLE_COMMAND_FLAGS(show_t4, memdump, db_show_memdump, CS_OWN)
14037 {
14038 	device_t dev;
14039 	int radix, t;
14040 	bool valid;
14041 
14042 	valid = false;
14043 	radix = db_radix;
14044 	db_radix = 10;
14045 	t = db_read_token();
14046 	if (t == tIDENT) {
14047 		dev = device_lookup_by_name(db_tok_string);
14048 		t = db_read_token();
14049 		if (t == tNUMBER) {
14050 			addr = db_tok_number;
14051 			t = db_read_token();
14052 			if (t == tNUMBER) {
14053 				count = db_tok_number;
14054 				valid = true;
14055 			}
14056 		}
14057 	}
14058 	db_radix = radix;
14059 	db_skip_to_eol();
14060 	if (!valid) {
14061 		db_printf("usage: show t4 memdump <nexus> <addr> <len>\n");
14062 		return;
14063 	}
14064 
14065 	if (dev == NULL) {
14066 		db_printf("device not found\n");
14067 		return;
14068 	}
14069 	if (addr < 0) {
14070 		db_printf("invalid address\n");
14071 		return;
14072 	}
14073 	if (count <= 0) {
14074 		db_printf("invalid length\n");
14075 		return;
14076 	}
14077 
14078 	t4_dump_mem(device_get_softc(dev), addr, count);
14079 }
14080 #endif
14081 
14082 static eventhandler_tag vxlan_start_evtag;
14083 static eventhandler_tag vxlan_stop_evtag;
14084 
14085 struct vxlan_evargs {
14086 	if_t ifp;
14087 	uint16_t port;
14088 };
14089 
14090 static void
14091 enable_vxlan_rx(struct adapter *sc)
14092 {
14093 	int i, rc;
14094 	struct port_info *pi;
14095 	uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
14096 
14097 	ASSERT_SYNCHRONIZED_OP(sc);
14098 
14099 	t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) |
14100 	    F_VXLAN_EN);
14101 	for_each_port(sc, i) {
14102 		pi = sc->port[i];
14103 		if (pi->vxlan_tcam_entry == true)
14104 			continue;
14105 		rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac,
14106 		    match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
14107 		    true);
14108 		if (rc < 0) {
14109 			rc = -rc;
14110 			CH_ERR(&pi->vi[0],
14111 			    "failed to add VXLAN TCAM entry: %d.\n", rc);
14112 		} else {
14113 			MPASS(rc == sc->rawf_base + pi->port_id);
14114 			pi->vxlan_tcam_entry = true;
14115 		}
14116 	}
14117 }
14118 
14119 static void
14120 t4_vxlan_start(struct adapter *sc, void *arg)
14121 {
14122 	struct vxlan_evargs *v = arg;
14123 
14124 	if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
14125 		return;
14126 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0)
14127 		return;
14128 
14129 	if (sc->vxlan_refcount == 0) {
14130 		sc->vxlan_port = v->port;
14131 		sc->vxlan_refcount = 1;
14132 		if (!hw_off_limits(sc))
14133 			enable_vxlan_rx(sc);
14134 	} else if (sc->vxlan_port == v->port) {
14135 		sc->vxlan_refcount++;
14136 	} else {
14137 		CH_ERR(sc, "VXLAN already configured on port  %d; "
14138 		    "ignoring attempt to configure it on port %d\n",
14139 		    sc->vxlan_port, v->port);
14140 	}
14141 	end_synchronized_op(sc, 0);
14142 }
14143 
14144 static void
14145 t4_vxlan_stop(struct adapter *sc, void *arg)
14146 {
14147 	struct vxlan_evargs *v = arg;
14148 
14149 	if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
14150 		return;
14151 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0)
14152 		return;
14153 
14154 	/*
14155 	 * VXLANs may have been configured before the driver was loaded so we
14156 	 * may see more stops than starts.  This is not handled cleanly but at
14157 	 * least we keep the refcount sane.
14158 	 */
14159 	if (sc->vxlan_port != v->port)
14160 		goto done;
14161 	if (sc->vxlan_refcount == 0) {
14162 		CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; "
14163 		    "ignoring attempt to stop it again.\n", sc->vxlan_port);
14164 	} else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc))
14165 		t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0);
14166 done:
14167 	end_synchronized_op(sc, 0);
14168 }
14169 
14170 static void
14171 t4_vxlan_start_handler(void *arg __unused, if_t ifp,
14172     sa_family_t family, u_int port)
14173 {
14174 	struct vxlan_evargs v;
14175 
14176 	MPASS(family == AF_INET || family == AF_INET6);
14177 	v.ifp = ifp;
14178 	v.port = port;
14179 
14180 	t4_iterate(t4_vxlan_start, &v);
14181 }
14182 
14183 static void
14184 t4_vxlan_stop_handler(void *arg __unused, if_t ifp, sa_family_t family,
14185     u_int port)
14186 {
14187 	struct vxlan_evargs v;
14188 
14189 	MPASS(family == AF_INET || family == AF_INET6);
14190 	v.ifp = ifp;
14191 	v.port = port;
14192 
14193 	t4_iterate(t4_vxlan_stop, &v);
14194 }
14195 
14196 
14197 static struct sx mlu;	/* mod load unload */
14198 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
14199 
14200 static int
14201 mod_event(module_t mod, int cmd, void *arg)
14202 {
14203 	int rc = 0;
14204 	static int loaded = 0;
14205 
14206 	switch (cmd) {
14207 	case MOD_LOAD:
14208 		sx_xlock(&mlu);
14209 		if (loaded++ == 0) {
14210 			t4_sge_modload();
14211 			t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
14212 			    t4_filter_rpl, CPL_COOKIE_FILTER);
14213 			t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
14214 			    do_l2t_write_rpl, CPL_COOKIE_FILTER);
14215 			t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
14216 			    t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
14217 			t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
14218 			    t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
14219 			t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
14220 			    t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
14221 			t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
14222 			t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
14223 			t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
14224 			    do_smt_write_rpl);
14225 			sx_init(&t4_list_lock, "T4/T5 adapters");
14226 			SLIST_INIT(&t4_list);
14227 			callout_init(&fatal_callout, 1);
14228 #ifdef TCP_OFFLOAD
14229 			sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
14230 #endif
14231 #ifdef INET6
14232 			t4_clip_modload();
14233 #endif
14234 #ifdef KERN_TLS
14235 			t6_ktls_modload();
14236 			t7_ktls_modload();
14237 #endif
14238 			t4_tracer_modload();
14239 			tweak_tunables();
14240 			vxlan_start_evtag =
14241 			    EVENTHANDLER_REGISTER(vxlan_start,
14242 				t4_vxlan_start_handler, NULL,
14243 				EVENTHANDLER_PRI_ANY);
14244 			vxlan_stop_evtag =
14245 			    EVENTHANDLER_REGISTER(vxlan_stop,
14246 				t4_vxlan_stop_handler, NULL,
14247 				EVENTHANDLER_PRI_ANY);
14248 			reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK,
14249 			    taskqueue_thread_enqueue, &reset_tq);
14250 			taskqueue_start_threads(&reset_tq, 1, PI_SOFT,
14251 			    "t4_rst_thr");
14252 		}
14253 		sx_xunlock(&mlu);
14254 		break;
14255 
14256 	case MOD_UNLOAD:
14257 		sx_xlock(&mlu);
14258 		if (--loaded == 0) {
14259 #ifdef TCP_OFFLOAD
14260 			int i;
14261 #endif
14262 			int tries;
14263 
14264 			taskqueue_free(reset_tq);
14265 
14266 			tries = 0;
14267 			while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
14268 				uprintf("%ju clusters with custom free routine "
14269 				    "still is use.\n", t4_sge_extfree_refs());
14270 				pause("t4unload", 2 * hz);
14271 			}
14272 
14273 			sx_slock(&t4_list_lock);
14274 			if (!SLIST_EMPTY(&t4_list)) {
14275 				rc = EBUSY;
14276 				sx_sunlock(&t4_list_lock);
14277 				goto done_unload;
14278 			}
14279 #ifdef TCP_OFFLOAD
14280 			sx_slock(&t4_uld_list_lock);
14281 			for (i = 0; i <= ULD_MAX; i++) {
14282 				if (t4_uld_list[i] != NULL) {
14283 					rc = EBUSY;
14284 					sx_sunlock(&t4_uld_list_lock);
14285 					sx_sunlock(&t4_list_lock);
14286 					goto done_unload;
14287 				}
14288 			}
14289 			sx_sunlock(&t4_uld_list_lock);
14290 #endif
14291 			sx_sunlock(&t4_list_lock);
14292 
14293 			if (t4_sge_extfree_refs() == 0) {
14294 				EVENTHANDLER_DEREGISTER(vxlan_start,
14295 				    vxlan_start_evtag);
14296 				EVENTHANDLER_DEREGISTER(vxlan_stop,
14297 				    vxlan_stop_evtag);
14298 				t4_tracer_modunload();
14299 #ifdef KERN_TLS
14300 				t7_ktls_modunload();
14301 				t6_ktls_modunload();
14302 #endif
14303 #ifdef INET6
14304 				t4_clip_modunload();
14305 #endif
14306 #ifdef TCP_OFFLOAD
14307 				sx_destroy(&t4_uld_list_lock);
14308 #endif
14309 				sx_destroy(&t4_list_lock);
14310 				t4_sge_modunload();
14311 				loaded = 0;
14312 			} else {
14313 				rc = EBUSY;
14314 				loaded++;	/* undo earlier decrement */
14315 			}
14316 		}
14317 done_unload:
14318 		sx_xunlock(&mlu);
14319 		break;
14320 	}
14321 
14322 	return (rc);
14323 }
14324 
14325 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0);
14326 MODULE_VERSION(t4nex, 1);
14327 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
14328 #ifdef DEV_NETMAP
14329 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
14330 #endif /* DEV_NETMAP */
14331 
14332 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0);
14333 MODULE_VERSION(t5nex, 1);
14334 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
14335 #ifdef DEV_NETMAP
14336 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
14337 #endif /* DEV_NETMAP */
14338 
14339 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0);
14340 MODULE_VERSION(t6nex, 1);
14341 MODULE_DEPEND(t6nex, crypto, 1, 1, 1);
14342 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
14343 #ifdef DEV_NETMAP
14344 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
14345 #endif /* DEV_NETMAP */
14346 
14347 DRIVER_MODULE(chnex, pci, ch_driver, mod_event, 0);
14348 MODULE_VERSION(chnex, 1);
14349 MODULE_DEPEND(chnex, crypto, 1, 1, 1);
14350 MODULE_DEPEND(chnex, firmware, 1, 1, 1);
14351 #ifdef DEV_NETMAP
14352 MODULE_DEPEND(chnex, netmap, 1, 1, 1);
14353 #endif /* DEV_NETMAP */
14354 
14355 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0);
14356 MODULE_VERSION(cxgbe, 1);
14357 
14358 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0);
14359 MODULE_VERSION(cxl, 1);
14360 
14361 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0);
14362 MODULE_VERSION(cc, 1);
14363 
14364 DRIVER_MODULE(che, chnex, che_driver, 0, 0);
14365 MODULE_VERSION(che, 1);
14366 
14367 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0);
14368 MODULE_VERSION(vcxgbe, 1);
14369 
14370 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0);
14371 MODULE_VERSION(vcxl, 1);
14372 
14373 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0);
14374 MODULE_VERSION(vcc, 1);
14375 
14376 DRIVER_MODULE(vche, che, vche_driver, 0, 0);
14377 MODULE_VERSION(vche, 1);
14378