1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 33 #include <sys/param.h> 34 #include <sys/conf.h> 35 #include <sys/priv.h> 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/taskqueue.h> 42 #include <sys/pciio.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pci_private.h> 46 #include <sys/firmware.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/sysctl.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_types.h> 55 #include <net/if_dl.h> 56 57 #include "common/t4_hw.h" 58 #include "common/common.h" 59 #include "common/t4_regs.h" 60 #include "common/t4_regs_values.h" 61 #include "common/t4fw_interface.h" 62 #include "t4_ioctl.h" 63 64 /* T4 bus driver interface */ 65 static int t4_probe(device_t); 66 static int t4_attach(device_t); 67 static int t4_detach(device_t); 68 static device_method_t t4_methods[] = { 69 DEVMETHOD(device_probe, t4_probe), 70 DEVMETHOD(device_attach, t4_attach), 71 DEVMETHOD(device_detach, t4_detach), 72 73 /* bus interface */ 74 DEVMETHOD(bus_print_child, bus_generic_print_child), 75 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 76 77 { 0, 0 } 78 }; 79 static driver_t t4_driver = { 80 "t4nex", 81 t4_methods, 82 sizeof(struct adapter) 83 }; 84 85 86 /* T4 port (cxgbe) interface */ 87 static int cxgbe_probe(device_t); 88 static int cxgbe_attach(device_t); 89 static int cxgbe_detach(device_t); 90 static device_method_t cxgbe_methods[] = { 91 DEVMETHOD(device_probe, cxgbe_probe), 92 DEVMETHOD(device_attach, cxgbe_attach), 93 DEVMETHOD(device_detach, cxgbe_detach), 94 { 0, 0 } 95 }; 96 static driver_t cxgbe_driver = { 97 "cxgbe", 98 cxgbe_methods, 99 sizeof(struct port_info) 100 }; 101 102 static d_ioctl_t t4_ioctl; 103 static d_open_t t4_open; 104 static d_close_t t4_close; 105 106 static struct cdevsw t4_cdevsw = { 107 .d_version = D_VERSION, 108 .d_flags = 0, 109 .d_open = t4_open, 110 .d_close = t4_close, 111 .d_ioctl = t4_ioctl, 112 .d_name = "t4nex", 113 }; 114 115 /* ifnet + media interface */ 116 static void cxgbe_init(void *); 117 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 118 static void cxgbe_start(struct ifnet *); 119 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 120 static void cxgbe_qflush(struct ifnet *); 121 static int cxgbe_media_change(struct ifnet *); 122 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 123 124 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4 Ethernet driver and services"); 125 126 /* 127 * Tunables. 128 */ 129 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe driver parameters"); 130 131 static int force_firmware_install = 0; 132 TUNABLE_INT("hw.cxgbe.force_firmware_install", &force_firmware_install); 133 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, force_firmware_install, CTLFLAG_RDTUN, 134 &force_firmware_install, 0, "install firmware on every attach."); 135 136 /* 137 * Holdoff timer and packet counter values. 138 */ 139 static unsigned int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 140 static unsigned int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 141 142 /* 143 * Max # of tx and rx queues to use for each 10G and 1G port. 144 */ 145 static unsigned int max_ntxq_10g = 8; 146 TUNABLE_INT("hw.cxgbe.max_ntxq_10G_port", &max_ntxq_10g); 147 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_ntxq_10G_port, CTLFLAG_RDTUN, 148 &max_ntxq_10g, 0, "maximum number of tx queues per 10G port."); 149 150 static unsigned int max_nrxq_10g = 8; 151 TUNABLE_INT("hw.cxgbe.max_nrxq_10G_port", &max_nrxq_10g); 152 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_nrxq_10G_port, CTLFLAG_RDTUN, 153 &max_nrxq_10g, 0, "maximum number of rxq's (per 10G port)."); 154 155 static unsigned int max_ntxq_1g = 2; 156 TUNABLE_INT("hw.cxgbe.max_ntxq_1G_port", &max_ntxq_1g); 157 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_ntxq_1G_port, CTLFLAG_RDTUN, 158 &max_ntxq_1g, 0, "maximum number of tx queues per 1G port."); 159 160 static unsigned int max_nrxq_1g = 2; 161 TUNABLE_INT("hw.cxgbe.max_nrxq_1G_port", &max_nrxq_1g); 162 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_nrxq_1G_port, CTLFLAG_RDTUN, 163 &max_nrxq_1g, 0, "maximum number of rxq's (per 1G port)."); 164 165 /* 166 * Holdoff parameters for 10G and 1G ports. 167 */ 168 static unsigned int tmr_idx_10g = 1; 169 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &tmr_idx_10g); 170 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_10G, CTLFLAG_RDTUN, 171 &tmr_idx_10g, 0, 172 "default timer index for interrupt holdoff (10G ports)."); 173 174 static int pktc_idx_10g = 2; 175 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &pktc_idx_10g); 176 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_10G, CTLFLAG_RDTUN, 177 &pktc_idx_10g, 0, 178 "default pkt counter index for interrupt holdoff (10G ports)."); 179 180 static unsigned int tmr_idx_1g = 1; 181 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &tmr_idx_1g); 182 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_1G, CTLFLAG_RDTUN, 183 &tmr_idx_1g, 0, 184 "default timer index for interrupt holdoff (1G ports)."); 185 186 static int pktc_idx_1g = 2; 187 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &pktc_idx_1g); 188 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_1G, CTLFLAG_RDTUN, 189 &pktc_idx_1g, 0, 190 "default pkt counter index for interrupt holdoff (1G ports)."); 191 192 /* 193 * Size (# of entries) of each tx and rx queue. 194 */ 195 static unsigned int qsize_txq = TX_EQ_QSIZE; 196 TUNABLE_INT("hw.cxgbe.qsize_txq", &qsize_txq); 197 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, 198 &qsize_txq, 0, "default queue size of NIC tx queues."); 199 200 static unsigned int qsize_rxq = RX_IQ_QSIZE; 201 TUNABLE_INT("hw.cxgbe.qsize_rxq", &qsize_rxq); 202 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, 203 &qsize_rxq, 0, "default queue size of NIC rx queues."); 204 205 /* 206 * Interrupt types allowed. 207 */ 208 static int intr_types = 7; 209 TUNABLE_INT("hw.cxgbe.interrupt_types", &intr_types); 210 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &intr_types, 0, 211 "interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively)"); 212 213 /* 214 * Force the driver to use interrupt forwarding. 215 */ 216 static int intr_fwd = 0; 217 TUNABLE_INT("hw.cxgbe.interrupt_forwarding", &intr_fwd); 218 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, interrupt_forwarding, CTLFLAG_RDTUN, 219 &intr_fwd, 0, "always use forwarded interrupts"); 220 221 struct intrs_and_queues { 222 int intr_type; /* 1, 2, or 4 for INTx, MSI, or MSI-X */ 223 int nirq; /* Number of vectors */ 224 int intr_fwd; /* Interrupts forwarded */ 225 int ntxq10g; /* # of NIC txq's for each 10G port */ 226 int nrxq10g; /* # of NIC rxq's for each 10G port */ 227 int ntxq1g; /* # of NIC txq's for each 1G port */ 228 int nrxq1g; /* # of NIC rxq's for each 1G port */ 229 }; 230 231 enum { 232 MEMWIN0_APERTURE = 2048, 233 MEMWIN0_BASE = 0x1b800, 234 MEMWIN1_APERTURE = 32768, 235 MEMWIN1_BASE = 0x28000, 236 MEMWIN2_APERTURE = 65536, 237 MEMWIN2_BASE = 0x30000, 238 }; 239 240 enum { 241 XGMAC_MTU = (1 << 0), 242 XGMAC_PROMISC = (1 << 1), 243 XGMAC_ALLMULTI = (1 << 2), 244 XGMAC_VLANEX = (1 << 3), 245 XGMAC_UCADDR = (1 << 4), 246 XGMAC_MCADDRS = (1 << 5), 247 248 XGMAC_ALL = 0xffff 249 }; 250 251 static int map_bars(struct adapter *); 252 static void setup_memwin(struct adapter *); 253 static int cfg_itype_and_nqueues(struct adapter *, int, int, 254 struct intrs_and_queues *); 255 static int prep_firmware(struct adapter *); 256 static int get_capabilities(struct adapter *, struct fw_caps_config_cmd *); 257 static int get_params(struct adapter *, struct fw_caps_config_cmd *); 258 static void t4_set_desc(struct adapter *); 259 static void build_medialist(struct port_info *); 260 static int update_mac_settings(struct port_info *, int); 261 static int cxgbe_init_locked(struct port_info *); 262 static int cxgbe_init_synchronized(struct port_info *); 263 static int cxgbe_uninit_locked(struct port_info *); 264 static int cxgbe_uninit_synchronized(struct port_info *); 265 static int first_port_up(struct adapter *); 266 static int last_port_down(struct adapter *); 267 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 268 iq_intr_handler_t *, void *, char *); 269 static int t4_free_irq(struct adapter *, struct irq *); 270 static void reg_block_dump(struct adapter *, uint8_t *, unsigned int, 271 unsigned int); 272 static void t4_get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 273 static void cxgbe_tick(void *); 274 static int t4_sysctls(struct adapter *); 275 static int cxgbe_sysctls(struct port_info *); 276 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 277 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 278 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 279 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 280 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 281 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 282 static inline void txq_start(struct ifnet *, struct sge_txq *); 283 static int t4_mod_event(module_t, int, void *); 284 285 struct t4_pciids { 286 uint16_t device; 287 uint8_t mpf; 288 char *desc; 289 } t4_pciids[] = { 290 {0xa000, 0, "Chelsio Terminator 4 FPGA"}, 291 {0x4400, 4, "Chelsio T440-dbg"}, 292 {0x4401, 4, "Chelsio T420-CR"}, 293 {0x4402, 4, "Chelsio T422-CR"}, 294 {0x4403, 4, "Chelsio T440-CR"}, 295 {0x4404, 4, "Chelsio T420-BCH"}, 296 {0x4405, 4, "Chelsio T440-BCH"}, 297 {0x4406, 4, "Chelsio T440-CH"}, 298 {0x4407, 4, "Chelsio T420-SO"}, 299 {0x4408, 4, "Chelsio T420-CX"}, 300 {0x4409, 4, "Chelsio T420-BT"}, 301 {0x440a, 4, "Chelsio T404-BT"}, 302 }; 303 304 static int 305 t4_probe(device_t dev) 306 { 307 int i; 308 uint16_t v = pci_get_vendor(dev); 309 uint16_t d = pci_get_device(dev); 310 311 if (v != PCI_VENDOR_ID_CHELSIO) 312 return (ENXIO); 313 314 for (i = 0; i < ARRAY_SIZE(t4_pciids); i++) { 315 if (d == t4_pciids[i].device && 316 pci_get_function(dev) == t4_pciids[i].mpf) { 317 device_set_desc(dev, t4_pciids[i].desc); 318 return (BUS_PROBE_DEFAULT); 319 } 320 } 321 322 return (ENXIO); 323 } 324 325 static int 326 t4_attach(device_t dev) 327 { 328 struct adapter *sc; 329 int rc = 0, i, n10g, n1g, rqidx, tqidx; 330 struct fw_caps_config_cmd caps; 331 uint32_t p, v; 332 struct intrs_and_queues iaq; 333 struct sge *s; 334 335 sc = device_get_softc(dev); 336 sc->dev = dev; 337 sc->pf = pci_get_function(dev); 338 sc->mbox = sc->pf; 339 340 pci_enable_busmaster(dev); 341 pci_set_max_read_req(dev, 4096); 342 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 343 device_get_nameunit(dev)); 344 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 345 346 rc = map_bars(sc); 347 if (rc != 0) 348 goto done; /* error message displayed already */ 349 350 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 351 352 /* Prepare the adapter for operation */ 353 rc = -t4_prep_adapter(sc); 354 if (rc != 0) { 355 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 356 goto done; 357 } 358 359 /* Do this really early */ 360 sc->cdev = make_dev(&t4_cdevsw, device_get_unit(dev), UID_ROOT, 361 GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); 362 sc->cdev->si_drv1 = sc; 363 364 /* Prepare the firmware for operation */ 365 rc = prep_firmware(sc); 366 if (rc != 0) 367 goto done; /* error message displayed already */ 368 369 /* Get device capabilities and select which ones we'll use */ 370 rc = get_capabilities(sc, &caps); 371 if (rc != 0) { 372 device_printf(dev, 373 "failed to initialize adapter capabilities: %d.\n", rc); 374 goto done; 375 } 376 377 /* Choose the global RSS mode. */ 378 rc = -t4_config_glbl_rss(sc, sc->mbox, 379 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 380 F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN | 381 F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP); 382 if (rc != 0) { 383 device_printf(dev, 384 "failed to select global RSS mode: %d.\n", rc); 385 goto done; 386 } 387 388 /* These are total (sum of all ports) limits for a bus driver */ 389 rc = -t4_cfg_pfvf(sc, sc->mbox, sc->pf, 0, 390 64, /* max # of egress queues */ 391 64, /* max # of egress Ethernet or control queues */ 392 64, /* max # of ingress queues with fl/interrupt */ 393 0, /* max # of ingress queues without interrupt */ 394 0, /* PCIe traffic class */ 395 4, /* max # of virtual interfaces */ 396 M_FW_PFVF_CMD_CMASK, M_FW_PFVF_CMD_PMASK, 16, 397 FW_CMD_CAP_PF, FW_CMD_CAP_PF); 398 if (rc != 0) { 399 device_printf(dev, 400 "failed to configure pf/vf resources: %d.\n", rc); 401 goto done; 402 } 403 404 /* Need this before sge_init */ 405 for (i = 0; i < SGE_NTIMERS; i++) 406 sc->sge.timer_val[i] = min(intr_timer[i], 200U); 407 for (i = 0; i < SGE_NCOUNTERS; i++) 408 sc->sge.counter_val[i] = min(intr_pktcount[i], M_THRESHOLD_0); 409 410 /* Also need the cooked value of cclk before sge_init */ 411 p = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 412 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK)); 413 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &p, &v); 414 if (rc != 0) { 415 device_printf(sc->dev, 416 "failed to obtain core clock value: %d.\n", rc); 417 goto done; 418 } 419 sc->params.vpd.cclk = v; 420 421 t4_sge_init(sc); 422 423 /* 424 * XXX: This is the place to call t4_set_filter_mode() 425 */ 426 427 /* get basic stuff going */ 428 rc = -t4_early_init(sc, sc->mbox); 429 if (rc != 0) { 430 device_printf(dev, "early init failed: %d.\n", rc); 431 goto done; 432 } 433 434 rc = get_params(sc, &caps); 435 if (rc != 0) 436 goto done; /* error message displayed already */ 437 438 /* These are finalized by FW initialization, load their values now */ 439 v = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 440 sc->params.tp.tre = G_TIMERRESOLUTION(v); 441 sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v); 442 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 443 444 /* tweak some settings */ 445 t4_write_reg(sc, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | V_RXTSHIFTMAXR1(4) | 446 V_RXTSHIFTMAXR2(15) | V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) | 447 V_KEEPALIVEMAXR1(4) | V_KEEPALIVEMAXR2(9)); 448 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 449 450 setup_memwin(sc); 451 452 rc = t4_create_dma_tag(sc); 453 if (rc != 0) 454 goto done; /* error message displayed already */ 455 456 /* 457 * First pass over all the ports - allocate VIs and initialize some 458 * basic parameters like mac address, port type, etc. We also figure 459 * out whether a port is 10G or 1G and use that information when 460 * calculating how many interrupts to attempt to allocate. 461 */ 462 n10g = n1g = 0; 463 for_each_port(sc, i) { 464 struct port_info *pi; 465 466 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 467 sc->port[i] = pi; 468 469 /* These must be set before t4_port_init */ 470 pi->adapter = sc; 471 pi->port_id = i; 472 473 /* Allocate the vi and initialize parameters like mac addr */ 474 rc = -t4_port_init(pi, sc->mbox, sc->pf, 0); 475 if (rc != 0) { 476 device_printf(dev, "unable to initialize port %d: %d\n", 477 i, rc); 478 free(pi, M_CXGBE); 479 sc->port[i] = NULL; /* indicates init failed */ 480 continue; 481 } 482 483 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 484 device_get_nameunit(dev), i); 485 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 486 487 if (is_10G_port(pi)) { 488 n10g++; 489 pi->tmr_idx = tmr_idx_10g; 490 pi->pktc_idx = pktc_idx_10g; 491 } else { 492 n1g++; 493 pi->tmr_idx = tmr_idx_1g; 494 pi->pktc_idx = pktc_idx_1g; 495 } 496 497 pi->xact_addr_filt = -1; 498 499 pi->qsize_rxq = max(qsize_rxq, 128); 500 while (pi->qsize_rxq & 7) 501 pi->qsize_rxq++; 502 pi->qsize_txq = max(qsize_txq, 128); 503 504 if (pi->qsize_rxq != qsize_rxq) { 505 device_printf(dev, 506 "using %d instead of %d as the rx queue size.\n", 507 pi->qsize_rxq, qsize_rxq); 508 } 509 if (pi->qsize_txq != qsize_txq) { 510 device_printf(dev, 511 "using %d instead of %d as the tx queue size.\n", 512 pi->qsize_txq, qsize_txq); 513 } 514 515 pi->dev = device_add_child(dev, "cxgbe", -1); 516 if (pi->dev == NULL) { 517 device_printf(dev, 518 "failed to add device for port %d.\n", i); 519 rc = ENXIO; 520 goto done; 521 } 522 device_set_softc(pi->dev, pi); 523 524 setbit(&sc->registered_device_map, i); 525 } 526 527 if (sc->registered_device_map == 0) { 528 device_printf(dev, "no usable ports\n"); 529 rc = ENXIO; 530 goto done; 531 } 532 533 /* 534 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 535 */ 536 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq); 537 if (rc != 0) 538 goto done; /* error message displayed already */ 539 540 sc->intr_type = iaq.intr_type; 541 sc->intr_count = iaq.nirq; 542 543 s = &sc->sge; 544 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; 545 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; 546 s->neq = s->ntxq + s->nrxq; /* the fl in an rxq is an eq */ 547 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 548 if (iaq.intr_fwd) { 549 sc->flags |= INTR_FWD; 550 s->niq += NFIQ(sc); /* forwarded interrupt queues */ 551 s->fiq = malloc(NFIQ(sc) * sizeof(struct sge_iq), M_CXGBE, 552 M_ZERO | M_WAITOK); 553 } 554 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 555 M_ZERO | M_WAITOK); 556 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 557 M_ZERO | M_WAITOK); 558 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 559 M_ZERO | M_WAITOK); 560 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 561 M_ZERO | M_WAITOK); 562 563 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 564 M_ZERO | M_WAITOK); 565 566 t4_sysctls(sc); 567 568 /* 569 * Second pass over the ports. This time we know the number of rx and 570 * tx queues that each port should get. 571 */ 572 rqidx = tqidx = 0; 573 for_each_port(sc, i) { 574 struct port_info *pi = sc->port[i]; 575 576 if (pi == NULL) 577 continue; 578 579 pi->first_rxq = rqidx; 580 pi->nrxq = is_10G_port(pi) ? iaq.nrxq10g : iaq.nrxq1g; 581 582 pi->first_txq = tqidx; 583 pi->ntxq = is_10G_port(pi) ? iaq.ntxq10g : iaq.ntxq1g; 584 585 rqidx += pi->nrxq; 586 tqidx += pi->ntxq; 587 } 588 589 rc = bus_generic_attach(dev); 590 if (rc != 0) { 591 device_printf(dev, 592 "failed to attach all child ports: %d\n", rc); 593 goto done; 594 } 595 596 #ifdef INVARIANTS 597 device_printf(dev, 598 "%p, %d ports (0x%x), %d intr_type, %d intr_count\n", 599 sc, sc->params.nports, sc->params.portvec, 600 sc->intr_type, sc->intr_count); 601 #endif 602 t4_set_desc(sc); 603 604 done: 605 if (rc != 0) 606 t4_detach(dev); 607 608 return (rc); 609 } 610 611 /* 612 * Idempotent 613 */ 614 static int 615 t4_detach(device_t dev) 616 { 617 struct adapter *sc; 618 struct port_info *pi; 619 int i; 620 621 sc = device_get_softc(dev); 622 623 if (sc->cdev) 624 destroy_dev(sc->cdev); 625 626 bus_generic_detach(dev); 627 for (i = 0; i < MAX_NPORTS; i++) { 628 pi = sc->port[i]; 629 if (pi) { 630 t4_free_vi(pi->adapter, sc->mbox, sc->pf, 0, pi->viid); 631 if (pi->dev) 632 device_delete_child(dev, pi->dev); 633 634 mtx_destroy(&pi->pi_lock); 635 free(pi, M_CXGBE); 636 } 637 } 638 639 if (sc->flags & FW_OK) 640 t4_fw_bye(sc, sc->mbox); 641 642 if (sc->intr_type == 2 || sc->intr_type == 4) 643 pci_release_msi(dev); 644 645 if (sc->regs_res) 646 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 647 sc->regs_res); 648 649 if (sc->msix_res) 650 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 651 sc->msix_res); 652 653 free(sc->irq, M_CXGBE); 654 free(sc->sge.rxq, M_CXGBE); 655 free(sc->sge.txq, M_CXGBE); 656 free(sc->sge.fiq, M_CXGBE); 657 free(sc->sge.iqmap, M_CXGBE); 658 free(sc->sge.eqmap, M_CXGBE); 659 t4_destroy_dma_tag(sc); 660 mtx_destroy(&sc->sc_lock); 661 662 bzero(sc, sizeof(*sc)); 663 664 return (0); 665 } 666 667 668 static int 669 cxgbe_probe(device_t dev) 670 { 671 char buf[128]; 672 struct port_info *pi = device_get_softc(dev); 673 674 snprintf(buf, sizeof(buf), "Port %d", pi->port_id); 675 device_set_desc_copy(dev, buf); 676 677 return (BUS_PROBE_DEFAULT); 678 } 679 680 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 681 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 682 IFCAP_VLAN_HWTSO) 683 #define T4_CAP_ENABLE (T4_CAP & ~IFCAP_TSO6) 684 685 static int 686 cxgbe_attach(device_t dev) 687 { 688 struct port_info *pi = device_get_softc(dev); 689 struct ifnet *ifp; 690 691 /* Allocate an ifnet and set it up */ 692 ifp = if_alloc(IFT_ETHER); 693 if (ifp == NULL) { 694 device_printf(dev, "Cannot allocate ifnet\n"); 695 return (ENOMEM); 696 } 697 pi->ifp = ifp; 698 ifp->if_softc = pi; 699 700 callout_init(&pi->tick, CALLOUT_MPSAFE); 701 pi->tq = taskqueue_create("cxgbe_taskq", M_NOWAIT, 702 taskqueue_thread_enqueue, &pi->tq); 703 if (pi->tq == NULL) { 704 device_printf(dev, "failed to allocate port task queue\n"); 705 if_free(pi->ifp); 706 return (ENOMEM); 707 } 708 taskqueue_start_threads(&pi->tq, 1, PI_NET, "%s taskq", 709 device_get_nameunit(dev)); 710 711 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 712 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 713 714 ifp->if_init = cxgbe_init; 715 ifp->if_ioctl = cxgbe_ioctl; 716 ifp->if_start = cxgbe_start; 717 ifp->if_transmit = cxgbe_transmit; 718 ifp->if_qflush = cxgbe_qflush; 719 720 ifp->if_snd.ifq_drv_maxlen = 1024; 721 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 722 IFQ_SET_READY(&ifp->if_snd); 723 724 ifp->if_capabilities = T4_CAP; 725 ifp->if_capenable = T4_CAP_ENABLE; 726 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO; 727 728 /* Initialize ifmedia for this port */ 729 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 730 cxgbe_media_status); 731 build_medialist(pi); 732 733 ether_ifattach(ifp, pi->hw_addr); 734 735 #ifdef INVARIANTS 736 device_printf(dev, "%p, %d txq, %d rxq\n", pi, pi->ntxq, pi->nrxq); 737 #endif 738 739 cxgbe_sysctls(pi); 740 741 return (0); 742 } 743 744 static int 745 cxgbe_detach(device_t dev) 746 { 747 struct port_info *pi = device_get_softc(dev); 748 struct adapter *sc = pi->adapter; 749 int rc; 750 751 /* Tell if_ioctl and if_init that the port is going away */ 752 ADAPTER_LOCK(sc); 753 SET_DOOMED(pi); 754 wakeup(&sc->flags); 755 while (IS_BUSY(sc)) 756 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 757 SET_BUSY(sc); 758 ADAPTER_UNLOCK(sc); 759 760 rc = cxgbe_uninit_synchronized(pi); 761 if (rc != 0) 762 device_printf(dev, "port uninit failed: %d.\n", rc); 763 764 taskqueue_free(pi->tq); 765 766 ifmedia_removeall(&pi->media); 767 ether_ifdetach(pi->ifp); 768 if_free(pi->ifp); 769 770 ADAPTER_LOCK(sc); 771 CLR_BUSY(sc); 772 wakeup_one(&sc->flags); 773 ADAPTER_UNLOCK(sc); 774 775 return (0); 776 } 777 778 static void 779 cxgbe_init(void *arg) 780 { 781 struct port_info *pi = arg; 782 struct adapter *sc = pi->adapter; 783 784 ADAPTER_LOCK(sc); 785 cxgbe_init_locked(pi); /* releases adapter lock */ 786 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 787 } 788 789 static int 790 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 791 { 792 int rc = 0, mtu, flags; 793 struct port_info *pi = ifp->if_softc; 794 struct adapter *sc = pi->adapter; 795 struct ifreq *ifr = (struct ifreq *)data; 796 uint32_t mask; 797 798 switch (cmd) { 799 case SIOCSIFMTU: 800 ADAPTER_LOCK(sc); 801 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 802 if (rc) { 803 fail: 804 ADAPTER_UNLOCK(sc); 805 return (rc); 806 } 807 808 mtu = ifr->ifr_mtu; 809 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) { 810 rc = EINVAL; 811 } else { 812 ifp->if_mtu = mtu; 813 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 814 t4_update_fl_bufsize(ifp); 815 PORT_LOCK(pi); 816 rc = update_mac_settings(pi, XGMAC_MTU); 817 PORT_UNLOCK(pi); 818 } 819 } 820 ADAPTER_UNLOCK(sc); 821 break; 822 823 case SIOCSIFFLAGS: 824 ADAPTER_LOCK(sc); 825 if (IS_DOOMED(pi)) { 826 rc = ENXIO; 827 goto fail; 828 } 829 if (ifp->if_flags & IFF_UP) { 830 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 831 flags = pi->if_flags; 832 if ((ifp->if_flags ^ flags) & 833 (IFF_PROMISC | IFF_ALLMULTI)) { 834 if (IS_BUSY(sc)) { 835 rc = EBUSY; 836 goto fail; 837 } 838 PORT_LOCK(pi); 839 rc = update_mac_settings(pi, 840 XGMAC_PROMISC | XGMAC_ALLMULTI); 841 PORT_UNLOCK(pi); 842 } 843 ADAPTER_UNLOCK(sc); 844 } else 845 rc = cxgbe_init_locked(pi); 846 pi->if_flags = ifp->if_flags; 847 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 848 rc = cxgbe_uninit_locked(pi); 849 else 850 ADAPTER_UNLOCK(sc); 851 852 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 853 break; 854 855 case SIOCADDMULTI: 856 case SIOCDELMULTI: /* these two can be called with a mutex held :-( */ 857 ADAPTER_LOCK(sc); 858 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 859 if (rc) 860 goto fail; 861 862 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 863 PORT_LOCK(pi); 864 rc = update_mac_settings(pi, XGMAC_MCADDRS); 865 PORT_UNLOCK(pi); 866 } 867 ADAPTER_UNLOCK(sc); 868 break; 869 870 case SIOCSIFCAP: 871 ADAPTER_LOCK(sc); 872 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 873 if (rc) 874 goto fail; 875 876 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 877 if (mask & IFCAP_TXCSUM) { 878 ifp->if_capenable ^= IFCAP_TXCSUM; 879 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 880 881 if (IFCAP_TSO & ifp->if_capenable && 882 !(IFCAP_TXCSUM & ifp->if_capenable)) { 883 ifp->if_capenable &= ~IFCAP_TSO; 884 ifp->if_hwassist &= ~CSUM_TSO; 885 if_printf(ifp, 886 "tso disabled due to -txcsum.\n"); 887 } 888 } 889 if (mask & IFCAP_RXCSUM) 890 ifp->if_capenable ^= IFCAP_RXCSUM; 891 if (mask & IFCAP_TSO4) { 892 ifp->if_capenable ^= IFCAP_TSO4; 893 894 if (IFCAP_TSO & ifp->if_capenable) { 895 if (IFCAP_TXCSUM & ifp->if_capenable) 896 ifp->if_hwassist |= CSUM_TSO; 897 else { 898 ifp->if_capenable &= ~IFCAP_TSO; 899 ifp->if_hwassist &= ~CSUM_TSO; 900 if_printf(ifp, 901 "enable txcsum first.\n"); 902 rc = EAGAIN; 903 } 904 } else 905 ifp->if_hwassist &= ~CSUM_TSO; 906 } 907 if (mask & IFCAP_LRO) { 908 #ifdef INET 909 int i; 910 struct sge_rxq *rxq; 911 912 ifp->if_capenable ^= IFCAP_LRO; 913 for_each_rxq(pi, i, rxq) { 914 if (ifp->if_capenable & IFCAP_LRO) 915 rxq->flags |= RXQ_LRO_ENABLED; 916 else 917 rxq->flags &= ~RXQ_LRO_ENABLED; 918 } 919 #endif 920 } 921 #ifndef TCP_OFFLOAD_DISABLE 922 if (mask & IFCAP_TOE4) { 923 rc = EOPNOTSUPP; 924 } 925 #endif 926 if (mask & IFCAP_VLAN_HWTAGGING) { 927 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 928 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 929 PORT_LOCK(pi); 930 rc = update_mac_settings(pi, XGMAC_VLANEX); 931 PORT_UNLOCK(pi); 932 } 933 } 934 if (mask & IFCAP_VLAN_MTU) { 935 ifp->if_capenable ^= IFCAP_VLAN_MTU; 936 937 /* Need to find out how to disable auto-mtu-inflation */ 938 } 939 if (mask & IFCAP_VLAN_HWTSO) 940 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 941 if (mask & IFCAP_VLAN_HWCSUM) 942 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 943 944 #ifdef VLAN_CAPABILITIES 945 VLAN_CAPABILITIES(ifp); 946 #endif 947 ADAPTER_UNLOCK(sc); 948 break; 949 950 case SIOCSIFMEDIA: 951 case SIOCGIFMEDIA: 952 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 953 break; 954 955 default: 956 rc = ether_ioctl(ifp, cmd, data); 957 } 958 959 return (rc); 960 } 961 962 static void 963 cxgbe_start(struct ifnet *ifp) 964 { 965 struct port_info *pi = ifp->if_softc; 966 struct sge_txq *txq; 967 int i; 968 969 for_each_txq(pi, i, txq) { 970 if (TXQ_TRYLOCK(txq)) { 971 txq_start(ifp, txq); 972 TXQ_UNLOCK(txq); 973 } 974 } 975 } 976 977 static int 978 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 979 { 980 struct port_info *pi = ifp->if_softc; 981 struct adapter *sc = pi->adapter; 982 struct sge_txq *txq = &sc->sge.txq[pi->first_txq]; 983 struct buf_ring *br; 984 int rc; 985 986 M_ASSERTPKTHDR(m); 987 988 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 989 m_freem(m); 990 return (0); 991 } 992 993 if (m->m_flags & M_FLOWID) 994 txq += (m->m_pkthdr.flowid % pi->ntxq); 995 br = txq->eq.br; 996 997 if (TXQ_TRYLOCK(txq) == 0) { 998 /* 999 * XXX: make sure that this packet really is sent out. There is 1000 * a small race where t4_eth_tx may stop draining the drbr and 1001 * goes away, just before we enqueued this mbuf. 1002 */ 1003 1004 return (drbr_enqueue(ifp, br, m)); 1005 } 1006 1007 /* 1008 * txq->m is the mbuf that is held up due to a temporary shortage of 1009 * resources and it should be put on the wire first. Then what's in 1010 * drbr and finally the mbuf that was just passed in to us. 1011 * 1012 * Return code should indicate the fate of the mbuf that was passed in 1013 * this time. 1014 */ 1015 1016 TXQ_LOCK_ASSERT_OWNED(txq); 1017 if (drbr_needs_enqueue(ifp, br) || txq->m) { 1018 1019 /* Queued for transmission. */ 1020 1021 rc = drbr_enqueue(ifp, br, m); 1022 m = txq->m ? txq->m : drbr_dequeue(ifp, br); 1023 (void) t4_eth_tx(ifp, txq, m); 1024 TXQ_UNLOCK(txq); 1025 return (rc); 1026 } 1027 1028 /* Direct transmission. */ 1029 rc = t4_eth_tx(ifp, txq, m); 1030 if (rc != 0 && txq->m) 1031 rc = 0; /* held, will be transmitted soon (hopefully) */ 1032 1033 TXQ_UNLOCK(txq); 1034 return (rc); 1035 } 1036 1037 static void 1038 cxgbe_qflush(struct ifnet *ifp) 1039 { 1040 struct port_info *pi = ifp->if_softc; 1041 1042 device_printf(pi->dev, "%s unimplemented.\n", __func__); 1043 } 1044 1045 static int 1046 cxgbe_media_change(struct ifnet *ifp) 1047 { 1048 struct port_info *pi = ifp->if_softc; 1049 1050 device_printf(pi->dev, "%s unimplemented.\n", __func__); 1051 1052 return (EOPNOTSUPP); 1053 } 1054 1055 static void 1056 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1057 { 1058 struct port_info *pi = ifp->if_softc; 1059 struct ifmedia_entry *cur = pi->media.ifm_cur; 1060 int speed = pi->link_cfg.speed; 1061 int data = (pi->port_type << 8) | pi->mod_type; 1062 1063 if (cur->ifm_data != data) { 1064 build_medialist(pi); 1065 cur = pi->media.ifm_cur; 1066 } 1067 1068 ifmr->ifm_status = IFM_AVALID; 1069 if (!pi->link_cfg.link_ok) 1070 return; 1071 1072 ifmr->ifm_status |= IFM_ACTIVE; 1073 1074 /* active and current will differ iff current media is autoselect. */ 1075 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 1076 return; 1077 1078 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 1079 if (speed == SPEED_10000) 1080 ifmr->ifm_active |= IFM_10G_T; 1081 else if (speed == SPEED_1000) 1082 ifmr->ifm_active |= IFM_1000_T; 1083 else if (speed == SPEED_100) 1084 ifmr->ifm_active |= IFM_100_TX; 1085 else if (speed == SPEED_10) 1086 ifmr->ifm_active |= IFM_10_T; 1087 else 1088 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 1089 speed)); 1090 } 1091 1092 void 1093 t4_fatal_err(struct adapter *sc) 1094 { 1095 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 1096 t4_intr_disable(sc); 1097 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 1098 device_get_nameunit(sc->dev)); 1099 } 1100 1101 static int 1102 map_bars(struct adapter *sc) 1103 { 1104 sc->regs_rid = PCIR_BAR(0); 1105 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1106 &sc->regs_rid, RF_ACTIVE); 1107 if (sc->regs_res == NULL) { 1108 device_printf(sc->dev, "cannot map registers.\n"); 1109 return (ENXIO); 1110 } 1111 sc->bt = rman_get_bustag(sc->regs_res); 1112 sc->bh = rman_get_bushandle(sc->regs_res); 1113 sc->mmio_len = rman_get_size(sc->regs_res); 1114 1115 sc->msix_rid = PCIR_BAR(4); 1116 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1117 &sc->msix_rid, RF_ACTIVE); 1118 if (sc->msix_res == NULL) { 1119 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 1120 return (ENXIO); 1121 } 1122 1123 return (0); 1124 } 1125 1126 static void 1127 setup_memwin(struct adapter *sc) 1128 { 1129 u_long bar0; 1130 1131 bar0 = rman_get_start(sc->regs_res); 1132 1133 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0), 1134 (bar0 + MEMWIN0_BASE) | V_BIR(0) | 1135 V_WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); 1136 1137 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1), 1138 (bar0 + MEMWIN1_BASE) | V_BIR(0) | 1139 V_WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); 1140 1141 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2), 1142 (bar0 + MEMWIN2_BASE) | V_BIR(0) | 1143 V_WINDOW(ilog2(MEMWIN2_APERTURE) - 10)); 1144 } 1145 1146 static int 1147 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 1148 struct intrs_and_queues *iaq) 1149 { 1150 int rc, itype, navail, nc, nrxq10g, nrxq1g; 1151 1152 bzero(iaq, sizeof(*iaq)); 1153 nc = mp_ncpus; /* our snapshot of the number of CPUs */ 1154 1155 for (itype = 4; itype; itype >>= 1) { 1156 1157 if ((itype & intr_types) == 0) 1158 continue; /* not allowed */ 1159 1160 if (itype == 4) 1161 navail = pci_msix_count(sc->dev); 1162 else if (itype == 2) 1163 navail = pci_msi_count(sc->dev); 1164 else 1165 navail = 1; 1166 1167 if (navail == 0) 1168 continue; 1169 1170 iaq->intr_type = itype; 1171 1172 iaq->ntxq10g = min(nc, max_ntxq_10g); 1173 iaq->ntxq1g = min(nc, max_ntxq_1g); 1174 1175 nrxq10g = min(nc, max_nrxq_10g); 1176 nrxq1g = min(nc, max_nrxq_1g); 1177 1178 /* Extra 2 is for a) error interrupt b) firmware event */ 1179 iaq->nirq = n10g * nrxq10g + n1g * nrxq1g + 2; 1180 if (iaq->nirq <= navail && intr_fwd == 0) { 1181 1182 /* One for err, one for fwq, and one for each rxq */ 1183 1184 iaq->intr_fwd = 0; 1185 iaq->nrxq10g = nrxq10g; 1186 iaq->nrxq1g = nrxq1g; 1187 if (itype == 2) { 1188 /* # of vectors requested must be power of 2 */ 1189 while (!powerof2(iaq->nirq)) 1190 iaq->nirq++; 1191 KASSERT(iaq->nirq <= navail, 1192 ("%s: bad MSI calculation", __func__)); 1193 } 1194 } else { 1195 fwd: 1196 iaq->intr_fwd = 1; 1197 iaq->nirq = navail; 1198 1199 /* 1200 * If we have multiple vectors available reserve one 1201 * exclusively for errors. The rest will be shared by 1202 * the fwq and data. 1203 */ 1204 if (navail > 1) { 1205 navail--; 1206 1207 if (navail > nc && itype == 4) 1208 iaq->nirq = nc + 1; 1209 } 1210 1211 iaq->nrxq10g = min(nrxq10g, navail); 1212 iaq->nrxq1g = min(nrxq1g, navail); 1213 } 1214 1215 navail = iaq->nirq; 1216 rc = 0; 1217 if (itype == 4) 1218 rc = pci_alloc_msix(sc->dev, &navail); 1219 else if (itype == 2) 1220 rc = pci_alloc_msi(sc->dev, &navail); 1221 1222 if (rc == 0) { 1223 if (navail == iaq->nirq) 1224 return (0); 1225 1226 /* 1227 * Didn't get the number requested. Use whatever number 1228 * the kernel is willing to allocate (it's in navail). 1229 */ 1230 pci_release_msi(sc->dev); 1231 goto fwd; 1232 } 1233 1234 device_printf(sc->dev, 1235 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 1236 itype, rc, iaq->nirq, navail); 1237 } 1238 1239 device_printf(sc->dev, 1240 "failed to find a usable interrupt type. " 1241 "allowed=%d, msi-x=%d, msi=%d, intx=1", intr_types, 1242 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 1243 1244 return (ENXIO); 1245 } 1246 1247 /* 1248 * Install a compatible firmware (if required), establish contact with it, 1249 * become the master, and reset the device. 1250 */ 1251 static int 1252 prep_firmware(struct adapter *sc) 1253 { 1254 const struct firmware *fw; 1255 int rc; 1256 enum dev_state state; 1257 1258 /* Check firmware version and install a different one if necessary */ 1259 rc = t4_check_fw_version(sc); 1260 if (rc != 0 || force_firmware_install) { 1261 uint32_t v = 0; 1262 1263 fw = firmware_get(T4_FWNAME); 1264 if (fw != NULL) { 1265 const struct fw_hdr *hdr = (const void *)fw->data; 1266 1267 v = ntohl(hdr->fw_ver); 1268 1269 /* 1270 * The firmware module will not be used if it isn't the 1271 * same major version as what the driver was compiled 1272 * with. This check trumps force_firmware_install. 1273 */ 1274 if (G_FW_HDR_FW_VER_MAJOR(v) != FW_VERSION_MAJOR) { 1275 device_printf(sc->dev, 1276 "Found firmware image but version %d " 1277 "can not be used with this driver (%d)\n", 1278 G_FW_HDR_FW_VER_MAJOR(v), FW_VERSION_MAJOR); 1279 1280 firmware_put(fw, FIRMWARE_UNLOAD); 1281 fw = NULL; 1282 } 1283 } 1284 1285 if (fw == NULL && (rc < 0 || force_firmware_install)) { 1286 device_printf(sc->dev, "No usable firmware. " 1287 "card has %d.%d.%d, driver compiled with %d.%d.%d, " 1288 "force_firmware_install%s set", 1289 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 1290 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 1291 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 1292 FW_VERSION_MAJOR, FW_VERSION_MINOR, 1293 FW_VERSION_MICRO, 1294 force_firmware_install ? "" : " not"); 1295 return (EAGAIN); 1296 } 1297 1298 /* 1299 * Always upgrade, even for minor/micro/build mismatches. 1300 * Downgrade only for a major version mismatch or if 1301 * force_firmware_install was specified. 1302 */ 1303 if (fw != NULL && (rc < 0 || force_firmware_install || 1304 v > sc->params.fw_vers)) { 1305 device_printf(sc->dev, 1306 "installing firmware %d.%d.%d.%d on card.\n", 1307 G_FW_HDR_FW_VER_MAJOR(v), G_FW_HDR_FW_VER_MINOR(v), 1308 G_FW_HDR_FW_VER_MICRO(v), G_FW_HDR_FW_VER_BUILD(v)); 1309 1310 rc = -t4_load_fw(sc, fw->data, fw->datasize); 1311 if (rc != 0) { 1312 device_printf(sc->dev, 1313 "failed to install firmware: %d\n", rc); 1314 firmware_put(fw, FIRMWARE_UNLOAD); 1315 return (rc); 1316 } else { 1317 /* refresh */ 1318 (void) t4_check_fw_version(sc); 1319 } 1320 } 1321 1322 if (fw != NULL) 1323 firmware_put(fw, FIRMWARE_UNLOAD); 1324 } 1325 1326 /* Contact firmware, request master */ 1327 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MUST, &state); 1328 if (rc < 0) { 1329 rc = -rc; 1330 device_printf(sc->dev, 1331 "failed to connect to the firmware: %d.\n", rc); 1332 return (rc); 1333 } 1334 1335 /* Reset device */ 1336 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 1337 if (rc != 0) { 1338 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 1339 if (rc != ETIMEDOUT && rc != EIO) 1340 t4_fw_bye(sc, sc->mbox); 1341 return (rc); 1342 } 1343 1344 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 1345 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 1346 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 1347 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 1348 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 1349 sc->flags |= FW_OK; 1350 1351 return (0); 1352 } 1353 1354 static int 1355 get_capabilities(struct adapter *sc, struct fw_caps_config_cmd *caps) 1356 { 1357 int rc; 1358 1359 bzero(caps, sizeof(*caps)); 1360 caps->op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1361 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1362 caps->retval_len16 = htobe32(FW_LEN16(*caps)); 1363 1364 rc = -t4_wr_mbox(sc, sc->mbox, caps, sizeof(*caps), caps); 1365 if (rc != 0) 1366 return (rc); 1367 1368 if (caps->niccaps & htobe16(FW_CAPS_CONFIG_NIC_VM)) 1369 caps->niccaps ^= htobe16(FW_CAPS_CONFIG_NIC_VM); 1370 1371 caps->op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1372 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 1373 rc = -t4_wr_mbox(sc, sc->mbox, caps, sizeof(*caps), NULL); 1374 1375 return (rc); 1376 } 1377 1378 static int 1379 get_params(struct adapter *sc, struct fw_caps_config_cmd *caps) 1380 { 1381 int rc; 1382 uint32_t params[7], val[7]; 1383 1384 #define FW_PARAM_DEV(param) \ 1385 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 1386 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 1387 #define FW_PARAM_PFVF(param) \ 1388 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 1389 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 1390 1391 params[0] = FW_PARAM_DEV(PORTVEC); 1392 params[1] = FW_PARAM_PFVF(IQFLINT_START); 1393 params[2] = FW_PARAM_PFVF(EQ_START); 1394 params[3] = FW_PARAM_PFVF(FILTER_START); 1395 params[4] = FW_PARAM_PFVF(FILTER_END); 1396 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 5, params, val); 1397 if (rc != 0) { 1398 device_printf(sc->dev, 1399 "failed to query parameters: %d.\n", rc); 1400 goto done; 1401 } 1402 1403 sc->params.portvec = val[0]; 1404 sc->params.nports = 0; 1405 while (val[0]) { 1406 sc->params.nports++; 1407 val[0] &= val[0] - 1; 1408 } 1409 1410 sc->sge.iq_start = val[1]; 1411 sc->sge.eq_start = val[2]; 1412 sc->tids.ftid_base = val[3]; 1413 sc->tids.nftids = val[4] - val[3] + 1; 1414 1415 if (caps->toecaps) { 1416 /* query offload-related parameters */ 1417 params[0] = FW_PARAM_DEV(NTID); 1418 params[1] = FW_PARAM_PFVF(SERVER_START); 1419 params[2] = FW_PARAM_PFVF(SERVER_END); 1420 params[3] = FW_PARAM_PFVF(TDDP_START); 1421 params[4] = FW_PARAM_PFVF(TDDP_END); 1422 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 1423 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, params, val); 1424 if (rc != 0) { 1425 device_printf(sc->dev, 1426 "failed to query TOE parameters: %d.\n", rc); 1427 goto done; 1428 } 1429 sc->tids.ntids = val[0]; 1430 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 1431 sc->tids.stid_base = val[1]; 1432 sc->tids.nstids = val[2] - val[1] + 1; 1433 sc->vres.ddp.start = val[3]; 1434 sc->vres.ddp.size = val[4] - val[3] + 1; 1435 sc->params.ofldq_wr_cred = val[5]; 1436 sc->params.offload = 1; 1437 } 1438 if (caps->rdmacaps) { 1439 params[0] = FW_PARAM_PFVF(STAG_START); 1440 params[1] = FW_PARAM_PFVF(STAG_END); 1441 params[2] = FW_PARAM_PFVF(RQ_START); 1442 params[3] = FW_PARAM_PFVF(RQ_END); 1443 params[4] = FW_PARAM_PFVF(PBL_START); 1444 params[5] = FW_PARAM_PFVF(PBL_END); 1445 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, params, val); 1446 if (rc != 0) { 1447 device_printf(sc->dev, 1448 "failed to query RDMA parameters: %d.\n", rc); 1449 goto done; 1450 } 1451 sc->vres.stag.start = val[0]; 1452 sc->vres.stag.size = val[1] - val[0] + 1; 1453 sc->vres.rq.start = val[2]; 1454 sc->vres.rq.size = val[3] - val[2] + 1; 1455 sc->vres.pbl.start = val[4]; 1456 sc->vres.pbl.size = val[5] - val[4] + 1; 1457 } 1458 if (caps->iscsicaps) { 1459 params[0] = FW_PARAM_PFVF(ISCSI_START); 1460 params[1] = FW_PARAM_PFVF(ISCSI_END); 1461 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, params, val); 1462 if (rc != 0) { 1463 device_printf(sc->dev, 1464 "failed to query iSCSI parameters: %d.\n", rc); 1465 goto done; 1466 } 1467 sc->vres.iscsi.start = val[0]; 1468 sc->vres.iscsi.size = val[1] - val[0] + 1; 1469 } 1470 #undef FW_PARAM_PFVF 1471 #undef FW_PARAM_DEV 1472 1473 done: 1474 return (rc); 1475 } 1476 1477 static void 1478 t4_set_desc(struct adapter *sc) 1479 { 1480 char buf[128]; 1481 struct adapter_params *p = &sc->params; 1482 1483 snprintf(buf, sizeof(buf), 1484 "Chelsio %s (rev %d) %d port %sNIC PCIe-x%d %s, S/N:%s, E/C:%s", 1485 p->vpd.id, p->rev, p->nports, is_offload(sc) ? "R" : "", 1486 p->pci.width, (sc->intr_type == 4 ) ? "MSI-X" : 1487 (sc->intr_type == 2) ? "MSI" : "INTx", p->vpd.sn, p->vpd.ec); 1488 1489 device_set_desc_copy(sc->dev, buf); 1490 } 1491 1492 static void 1493 build_medialist(struct port_info *pi) 1494 { 1495 struct ifmedia *media = &pi->media; 1496 int data, m; 1497 1498 PORT_LOCK(pi); 1499 1500 ifmedia_removeall(media); 1501 1502 m = IFM_ETHER | IFM_FDX; 1503 data = (pi->port_type << 8) | pi->mod_type; 1504 1505 switch(pi->port_type) { 1506 case FW_PORT_TYPE_BT_XFI: 1507 ifmedia_add(media, m | IFM_10G_T, data, NULL); 1508 break; 1509 1510 case FW_PORT_TYPE_BT_XAUI: 1511 ifmedia_add(media, m | IFM_10G_T, data, NULL); 1512 /* fall through */ 1513 1514 case FW_PORT_TYPE_BT_SGMII: 1515 ifmedia_add(media, m | IFM_1000_T, data, NULL); 1516 ifmedia_add(media, m | IFM_100_TX, data, NULL); 1517 ifmedia_add(media, IFM_ETHER | IFM_AUTO, data, NULL); 1518 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 1519 break; 1520 1521 case FW_PORT_TYPE_CX4: 1522 ifmedia_add(media, m | IFM_10G_CX4, data, NULL); 1523 ifmedia_set(media, m | IFM_10G_CX4); 1524 break; 1525 1526 case FW_PORT_TYPE_SFP: 1527 case FW_PORT_TYPE_FIBER_XFI: 1528 case FW_PORT_TYPE_FIBER_XAUI: 1529 switch (pi->mod_type) { 1530 1531 case FW_PORT_MOD_TYPE_LR: 1532 ifmedia_add(media, m | IFM_10G_LR, data, NULL); 1533 ifmedia_set(media, m | IFM_10G_LR); 1534 break; 1535 1536 case FW_PORT_MOD_TYPE_SR: 1537 ifmedia_add(media, m | IFM_10G_SR, data, NULL); 1538 ifmedia_set(media, m | IFM_10G_SR); 1539 break; 1540 1541 case FW_PORT_MOD_TYPE_LRM: 1542 ifmedia_add(media, m | IFM_10G_LRM, data, NULL); 1543 ifmedia_set(media, m | IFM_10G_LRM); 1544 break; 1545 1546 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 1547 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 1548 ifmedia_add(media, m | IFM_10G_TWINAX, data, NULL); 1549 ifmedia_set(media, m | IFM_10G_TWINAX); 1550 break; 1551 1552 case FW_PORT_MOD_TYPE_NONE: 1553 m &= ~IFM_FDX; 1554 ifmedia_add(media, m | IFM_NONE, data, NULL); 1555 ifmedia_set(media, m | IFM_NONE); 1556 break; 1557 1558 case FW_PORT_MOD_TYPE_NA: 1559 case FW_PORT_MOD_TYPE_ER: 1560 default: 1561 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL); 1562 ifmedia_set(media, m | IFM_UNKNOWN); 1563 break; 1564 } 1565 break; 1566 1567 case FW_PORT_TYPE_KX4: 1568 case FW_PORT_TYPE_KX: 1569 case FW_PORT_TYPE_KR: 1570 default: 1571 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL); 1572 ifmedia_set(media, m | IFM_UNKNOWN); 1573 break; 1574 } 1575 1576 PORT_UNLOCK(pi); 1577 } 1578 1579 /* 1580 * Program the port's XGMAC based on parameters in ifnet. The caller also 1581 * indicates which parameters should be programmed (the rest are left alone). 1582 */ 1583 static int 1584 update_mac_settings(struct port_info *pi, int flags) 1585 { 1586 int rc; 1587 struct ifnet *ifp = pi->ifp; 1588 struct adapter *sc = pi->adapter; 1589 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 1590 1591 PORT_LOCK_ASSERT_OWNED(pi); 1592 KASSERT(flags, ("%s: not told what to update.", __func__)); 1593 1594 if (flags & XGMAC_MTU) 1595 mtu = ifp->if_mtu; 1596 1597 if (flags & XGMAC_PROMISC) 1598 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 1599 1600 if (flags & XGMAC_ALLMULTI) 1601 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 1602 1603 if (flags & XGMAC_VLANEX) 1604 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 1605 1606 rc = -t4_set_rxmode(sc, sc->mbox, pi->viid, mtu, promisc, allmulti, 1, 1607 vlanex, false); 1608 if (rc) { 1609 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, rc); 1610 return (rc); 1611 } 1612 1613 if (flags & XGMAC_UCADDR) { 1614 uint8_t ucaddr[ETHER_ADDR_LEN]; 1615 1616 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 1617 rc = t4_change_mac(sc, sc->mbox, pi->viid, pi->xact_addr_filt, 1618 ucaddr, true, true); 1619 if (rc < 0) { 1620 rc = -rc; 1621 if_printf(ifp, "change_mac failed: %d\n", rc); 1622 return (rc); 1623 } else { 1624 pi->xact_addr_filt = rc; 1625 rc = 0; 1626 } 1627 } 1628 1629 if (flags & XGMAC_MCADDRS) { 1630 const uint8_t *mcaddr; 1631 int del = 1; 1632 uint64_t hash = 0; 1633 struct ifmultiaddr *ifma; 1634 1635 if_maddr_rlock(ifp); 1636 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1637 if (ifma->ifma_addr->sa_family != AF_LINK) 1638 continue; 1639 mcaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1640 1641 rc = t4_alloc_mac_filt(sc, sc->mbox, pi->viid, del, 1, 1642 &mcaddr, NULL, &hash, 0); 1643 if (rc < 0) { 1644 rc = -rc; 1645 if_printf(ifp, "failed to add mc address" 1646 " %02x:%02x:%02x:%02x:%02x:%02x rc=%d\n", 1647 mcaddr[0], mcaddr[1], mcaddr[2], mcaddr[3], 1648 mcaddr[4], mcaddr[5], rc); 1649 goto mcfail; 1650 } 1651 del = 0; 1652 } 1653 1654 rc = -t4_set_addr_hash(sc, sc->mbox, pi->viid, 0, hash, 0); 1655 if (rc != 0) 1656 if_printf(ifp, "failed to set mc address hash: %d", rc); 1657 mcfail: 1658 if_maddr_runlock(ifp); 1659 } 1660 1661 return (rc); 1662 } 1663 1664 static int 1665 cxgbe_init_locked(struct port_info *pi) 1666 { 1667 struct adapter *sc = pi->adapter; 1668 int rc = 0; 1669 1670 ADAPTER_LOCK_ASSERT_OWNED(sc); 1671 1672 while (!IS_DOOMED(pi) && IS_BUSY(sc)) { 1673 if (mtx_sleep(&sc->flags, &sc->sc_lock, PCATCH, "t4init", 0)) { 1674 rc = EINTR; 1675 goto done; 1676 } 1677 } 1678 if (IS_DOOMED(pi)) { 1679 rc = ENXIO; 1680 goto done; 1681 } 1682 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 1683 1684 /* Give up the adapter lock, port init code can sleep. */ 1685 SET_BUSY(sc); 1686 ADAPTER_UNLOCK(sc); 1687 1688 rc = cxgbe_init_synchronized(pi); 1689 1690 done: 1691 ADAPTER_LOCK(sc); 1692 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 1693 CLR_BUSY(sc); 1694 wakeup_one(&sc->flags); 1695 ADAPTER_UNLOCK(sc); 1696 return (rc); 1697 } 1698 1699 static int 1700 cxgbe_init_synchronized(struct port_info *pi) 1701 { 1702 struct adapter *sc = pi->adapter; 1703 struct ifnet *ifp = pi->ifp; 1704 int rc = 0, i; 1705 uint16_t *rss; 1706 struct sge_rxq *rxq; 1707 1708 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1709 1710 if (isset(&sc->open_device_map, pi->port_id)) { 1711 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, 1712 ("mismatch between open_device_map and if_drv_flags")); 1713 return (0); /* already running */ 1714 } 1715 1716 if (sc->open_device_map == 0 && ((rc = first_port_up(sc)) != 0)) 1717 return (rc); /* error message displayed already */ 1718 1719 /* 1720 * Allocate tx/rx/fl queues for this port. 1721 */ 1722 rc = t4_setup_eth_queues(pi); 1723 if (rc != 0) 1724 goto done; /* error message displayed already */ 1725 1726 /* 1727 * Setup RSS for this port. 1728 */ 1729 rss = malloc(pi->nrxq * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 1730 for_each_rxq(pi, i, rxq) { 1731 rss[i] = rxq->iq.abs_id; 1732 } 1733 rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0, pi->rss_size, rss, 1734 pi->nrxq); 1735 free(rss, M_CXGBE); 1736 if (rc != 0) { 1737 if_printf(ifp, "rss_config failed: %d\n", rc); 1738 goto done; 1739 } 1740 1741 PORT_LOCK(pi); 1742 rc = update_mac_settings(pi, XGMAC_ALL); 1743 PORT_UNLOCK(pi); 1744 if (rc) 1745 goto done; /* error message displayed already */ 1746 1747 rc = -t4_link_start(sc, sc->mbox, pi->tx_chan, &pi->link_cfg); 1748 if (rc != 0) { 1749 if_printf(ifp, "start_link failed: %d\n", rc); 1750 goto done; 1751 } 1752 1753 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, true, true); 1754 if (rc != 0) { 1755 if_printf(ifp, "enable_vi failed: %d\n", rc); 1756 goto done; 1757 } 1758 pi->flags |= VI_ENABLED; 1759 1760 /* all ok */ 1761 setbit(&sc->open_device_map, pi->port_id); 1762 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1763 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1764 1765 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 1766 done: 1767 if (rc != 0) 1768 cxgbe_uninit_synchronized(pi); 1769 1770 return (rc); 1771 } 1772 1773 static int 1774 cxgbe_uninit_locked(struct port_info *pi) 1775 { 1776 struct adapter *sc = pi->adapter; 1777 int rc; 1778 1779 ADAPTER_LOCK_ASSERT_OWNED(sc); 1780 1781 while (!IS_DOOMED(pi) && IS_BUSY(sc)) { 1782 if (mtx_sleep(&sc->flags, &sc->sc_lock, PCATCH, "t4uninit", 0)) { 1783 rc = EINTR; 1784 goto done; 1785 } 1786 } 1787 if (IS_DOOMED(pi)) { 1788 rc = ENXIO; 1789 goto done; 1790 } 1791 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 1792 SET_BUSY(sc); 1793 ADAPTER_UNLOCK(sc); 1794 1795 rc = cxgbe_uninit_synchronized(pi); 1796 1797 ADAPTER_LOCK(sc); 1798 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 1799 CLR_BUSY(sc); 1800 wakeup_one(&sc->flags); 1801 done: 1802 ADAPTER_UNLOCK(sc); 1803 return (rc); 1804 } 1805 1806 /* 1807 * Idempotent. 1808 */ 1809 static int 1810 cxgbe_uninit_synchronized(struct port_info *pi) 1811 { 1812 struct adapter *sc = pi->adapter; 1813 struct ifnet *ifp = pi->ifp; 1814 int rc; 1815 1816 /* 1817 * taskqueue_drain may cause a deadlock if the adapter lock is held. 1818 */ 1819 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1820 1821 /* 1822 * Clear this port's bit from the open device map, and then drain 1823 * tasks and callouts. 1824 */ 1825 clrbit(&sc->open_device_map, pi->port_id); 1826 1827 PORT_LOCK(pi); 1828 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1829 callout_stop(&pi->tick); 1830 PORT_UNLOCK(pi); 1831 callout_drain(&pi->tick); 1832 1833 /* 1834 * Stop and then free the queues' resources, including the queues 1835 * themselves. 1836 * 1837 * XXX: we could just stop the queues here (on ifconfig down) and free 1838 * them later (on port detach), but having up/down go through the entire 1839 * allocate/activate/deactivate/free sequence is a good way to find 1840 * leaks and bugs. 1841 */ 1842 rc = t4_teardown_eth_queues(pi); 1843 if (rc != 0) 1844 if_printf(ifp, "teardown failed: %d\n", rc); 1845 1846 if (pi->flags & VI_ENABLED) { 1847 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, false, false); 1848 if (rc) 1849 if_printf(ifp, "disable_vi failed: %d\n", rc); 1850 else 1851 pi->flags &= ~VI_ENABLED; 1852 } 1853 1854 pi->link_cfg.link_ok = 0; 1855 pi->link_cfg.speed = 0; 1856 t4_os_link_changed(sc, pi->port_id, 0); 1857 1858 if (sc->open_device_map == 0) 1859 last_port_down(sc); 1860 1861 return (0); 1862 } 1863 1864 #define T4_ALLOC_IRQ(sc, irqid, rid, handler, arg, name) do { \ 1865 rc = t4_alloc_irq(sc, &sc->irq[irqid], rid, handler, arg, name); \ 1866 if (rc != 0) \ 1867 goto done; \ 1868 } while (0) 1869 static int 1870 first_port_up(struct adapter *sc) 1871 { 1872 int rc, i; 1873 char name[8]; 1874 1875 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1876 1877 /* 1878 * The firmware event queue and the optional forwarded interrupt queues. 1879 */ 1880 rc = t4_setup_adapter_iqs(sc); 1881 if (rc != 0) 1882 goto done; 1883 1884 /* 1885 * Setup interrupts. 1886 */ 1887 if (sc->intr_count == 1) { 1888 KASSERT(sc->flags & INTR_FWD, 1889 ("%s: single interrupt but not forwarded?", __func__)); 1890 T4_ALLOC_IRQ(sc, 0, 0, t4_intr_all, sc, "all"); 1891 } else { 1892 /* Multiple interrupts. The first one is always error intr */ 1893 T4_ALLOC_IRQ(sc, 0, 1, t4_intr_err, sc, "err"); 1894 1895 if (sc->flags & INTR_FWD) { 1896 /* The rest are shared by the fwq and all data intr */ 1897 for (i = 1; i < sc->intr_count; i++) { 1898 snprintf(name, sizeof(name), "mux%d", i - 1); 1899 T4_ALLOC_IRQ(sc, i, i + 1, t4_intr_fwd, 1900 &sc->sge.fiq[i - 1], name); 1901 } 1902 } else { 1903 struct port_info *pi; 1904 int p, q; 1905 1906 T4_ALLOC_IRQ(sc, 1, 2, t4_intr_evt, &sc->sge.fwq, 1907 "evt"); 1908 1909 p = q = 0; 1910 pi = sc->port[p]; 1911 for (i = 2; i < sc->intr_count; i++) { 1912 snprintf(name, sizeof(name), "p%dq%d", p, q); 1913 if (++q >= pi->nrxq) { 1914 p++; 1915 q = 0; 1916 pi = sc->port[p]; 1917 } 1918 T4_ALLOC_IRQ(sc, i, i + 1, t4_intr_data, 1919 &sc->sge.rxq[i - 2], name); 1920 } 1921 } 1922 } 1923 1924 t4_intr_enable(sc); 1925 sc->flags |= FULL_INIT_DONE; 1926 1927 done: 1928 if (rc != 0) 1929 last_port_down(sc); 1930 1931 return (rc); 1932 } 1933 #undef T4_ALLOC_IRQ 1934 1935 /* 1936 * Idempotent. 1937 */ 1938 static int 1939 last_port_down(struct adapter *sc) 1940 { 1941 int i; 1942 1943 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1944 1945 t4_intr_disable(sc); 1946 1947 t4_teardown_adapter_iqs(sc); 1948 1949 for (i = 0; i < sc->intr_count; i++) 1950 t4_free_irq(sc, &sc->irq[i]); 1951 1952 sc->flags &= ~FULL_INIT_DONE; 1953 1954 return (0); 1955 } 1956 1957 static int 1958 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 1959 iq_intr_handler_t *handler, void *arg, char *name) 1960 { 1961 int rc; 1962 1963 irq->rid = rid; 1964 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 1965 RF_SHAREABLE | RF_ACTIVE); 1966 if (irq->res == NULL) { 1967 device_printf(sc->dev, 1968 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1969 return (ENOMEM); 1970 } 1971 1972 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 1973 NULL, handler, arg, &irq->tag); 1974 if (rc != 0) { 1975 device_printf(sc->dev, 1976 "failed to setup interrupt for rid %d, name %s: %d\n", 1977 rid, name, rc); 1978 } else if (name) 1979 bus_describe_intr(sc->dev, irq->res, irq->tag, name); 1980 1981 return (rc); 1982 } 1983 1984 static int 1985 t4_free_irq(struct adapter *sc, struct irq *irq) 1986 { 1987 if (irq->tag) 1988 bus_teardown_intr(sc->dev, irq->res, irq->tag); 1989 if (irq->res) 1990 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 1991 1992 bzero(irq, sizeof(*irq)); 1993 1994 return (0); 1995 } 1996 1997 static void 1998 reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start, 1999 unsigned int end) 2000 { 2001 uint32_t *p = (uint32_t *)(buf + start); 2002 2003 for ( ; start <= end; start += sizeof(uint32_t)) 2004 *p++ = t4_read_reg(sc, start); 2005 } 2006 2007 static void 2008 t4_get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 2009 { 2010 int i; 2011 static const unsigned int reg_ranges[] = { 2012 0x1008, 0x1108, 2013 0x1180, 0x11b4, 2014 0x11fc, 0x123c, 2015 0x1300, 0x173c, 2016 0x1800, 0x18fc, 2017 0x3000, 0x30d8, 2018 0x30e0, 0x5924, 2019 0x5960, 0x59d4, 2020 0x5a00, 0x5af8, 2021 0x6000, 0x6098, 2022 0x6100, 0x6150, 2023 0x6200, 0x6208, 2024 0x6240, 0x6248, 2025 0x6280, 0x6338, 2026 0x6370, 0x638c, 2027 0x6400, 0x643c, 2028 0x6500, 0x6524, 2029 0x6a00, 0x6a38, 2030 0x6a60, 0x6a78, 2031 0x6b00, 0x6b84, 2032 0x6bf0, 0x6c84, 2033 0x6cf0, 0x6d84, 2034 0x6df0, 0x6e84, 2035 0x6ef0, 0x6f84, 2036 0x6ff0, 0x7084, 2037 0x70f0, 0x7184, 2038 0x71f0, 0x7284, 2039 0x72f0, 0x7384, 2040 0x73f0, 0x7450, 2041 0x7500, 0x7530, 2042 0x7600, 0x761c, 2043 0x7680, 0x76cc, 2044 0x7700, 0x7798, 2045 0x77c0, 0x77fc, 2046 0x7900, 0x79fc, 2047 0x7b00, 0x7c38, 2048 0x7d00, 0x7efc, 2049 0x8dc0, 0x8e1c, 2050 0x8e30, 0x8e78, 2051 0x8ea0, 0x8f6c, 2052 0x8fc0, 0x9074, 2053 0x90fc, 0x90fc, 2054 0x9400, 0x9458, 2055 0x9600, 0x96bc, 2056 0x9800, 0x9808, 2057 0x9820, 0x983c, 2058 0x9850, 0x9864, 2059 0x9c00, 0x9c6c, 2060 0x9c80, 0x9cec, 2061 0x9d00, 0x9d6c, 2062 0x9d80, 0x9dec, 2063 0x9e00, 0x9e6c, 2064 0x9e80, 0x9eec, 2065 0x9f00, 0x9f6c, 2066 0x9f80, 0x9fec, 2067 0xd004, 0xd03c, 2068 0xdfc0, 0xdfe0, 2069 0xe000, 0xea7c, 2070 0xf000, 0x11190, 2071 0x19040, 0x19124, 2072 0x19150, 0x191b0, 2073 0x191d0, 0x191e8, 2074 0x19238, 0x1924c, 2075 0x193f8, 0x19474, 2076 0x19490, 0x194f8, 2077 0x19800, 0x19f30, 2078 0x1a000, 0x1a06c, 2079 0x1a0b0, 0x1a120, 2080 0x1a128, 0x1a138, 2081 0x1a190, 0x1a1c4, 2082 0x1a1fc, 0x1a1fc, 2083 0x1e040, 0x1e04c, 2084 0x1e240, 0x1e28c, 2085 0x1e2c0, 0x1e2c0, 2086 0x1e2e0, 0x1e2e0, 2087 0x1e300, 0x1e384, 2088 0x1e3c0, 0x1e3c8, 2089 0x1e440, 0x1e44c, 2090 0x1e640, 0x1e68c, 2091 0x1e6c0, 0x1e6c0, 2092 0x1e6e0, 0x1e6e0, 2093 0x1e700, 0x1e784, 2094 0x1e7c0, 0x1e7c8, 2095 0x1e840, 0x1e84c, 2096 0x1ea40, 0x1ea8c, 2097 0x1eac0, 0x1eac0, 2098 0x1eae0, 0x1eae0, 2099 0x1eb00, 0x1eb84, 2100 0x1ebc0, 0x1ebc8, 2101 0x1ec40, 0x1ec4c, 2102 0x1ee40, 0x1ee8c, 2103 0x1eec0, 0x1eec0, 2104 0x1eee0, 0x1eee0, 2105 0x1ef00, 0x1ef84, 2106 0x1efc0, 0x1efc8, 2107 0x1f040, 0x1f04c, 2108 0x1f240, 0x1f28c, 2109 0x1f2c0, 0x1f2c0, 2110 0x1f2e0, 0x1f2e0, 2111 0x1f300, 0x1f384, 2112 0x1f3c0, 0x1f3c8, 2113 0x1f440, 0x1f44c, 2114 0x1f640, 0x1f68c, 2115 0x1f6c0, 0x1f6c0, 2116 0x1f6e0, 0x1f6e0, 2117 0x1f700, 0x1f784, 2118 0x1f7c0, 0x1f7c8, 2119 0x1f840, 0x1f84c, 2120 0x1fa40, 0x1fa8c, 2121 0x1fac0, 0x1fac0, 2122 0x1fae0, 0x1fae0, 2123 0x1fb00, 0x1fb84, 2124 0x1fbc0, 0x1fbc8, 2125 0x1fc40, 0x1fc4c, 2126 0x1fe40, 0x1fe8c, 2127 0x1fec0, 0x1fec0, 2128 0x1fee0, 0x1fee0, 2129 0x1ff00, 0x1ff84, 2130 0x1ffc0, 0x1ffc8, 2131 0x20000, 0x2002c, 2132 0x20100, 0x2013c, 2133 0x20190, 0x201c8, 2134 0x20200, 0x20318, 2135 0x20400, 0x20528, 2136 0x20540, 0x20614, 2137 0x21000, 0x21040, 2138 0x2104c, 0x21060, 2139 0x210c0, 0x210ec, 2140 0x21200, 0x21268, 2141 0x21270, 0x21284, 2142 0x212fc, 0x21388, 2143 0x21400, 0x21404, 2144 0x21500, 0x21518, 2145 0x2152c, 0x2153c, 2146 0x21550, 0x21554, 2147 0x21600, 0x21600, 2148 0x21608, 0x21628, 2149 0x21630, 0x2163c, 2150 0x21700, 0x2171c, 2151 0x21780, 0x2178c, 2152 0x21800, 0x21c38, 2153 0x21c80, 0x21d7c, 2154 0x21e00, 0x21e04, 2155 0x22000, 0x2202c, 2156 0x22100, 0x2213c, 2157 0x22190, 0x221c8, 2158 0x22200, 0x22318, 2159 0x22400, 0x22528, 2160 0x22540, 0x22614, 2161 0x23000, 0x23040, 2162 0x2304c, 0x23060, 2163 0x230c0, 0x230ec, 2164 0x23200, 0x23268, 2165 0x23270, 0x23284, 2166 0x232fc, 0x23388, 2167 0x23400, 0x23404, 2168 0x23500, 0x23518, 2169 0x2352c, 0x2353c, 2170 0x23550, 0x23554, 2171 0x23600, 0x23600, 2172 0x23608, 0x23628, 2173 0x23630, 0x2363c, 2174 0x23700, 0x2371c, 2175 0x23780, 0x2378c, 2176 0x23800, 0x23c38, 2177 0x23c80, 0x23d7c, 2178 0x23e00, 0x23e04, 2179 0x24000, 0x2402c, 2180 0x24100, 0x2413c, 2181 0x24190, 0x241c8, 2182 0x24200, 0x24318, 2183 0x24400, 0x24528, 2184 0x24540, 0x24614, 2185 0x25000, 0x25040, 2186 0x2504c, 0x25060, 2187 0x250c0, 0x250ec, 2188 0x25200, 0x25268, 2189 0x25270, 0x25284, 2190 0x252fc, 0x25388, 2191 0x25400, 0x25404, 2192 0x25500, 0x25518, 2193 0x2552c, 0x2553c, 2194 0x25550, 0x25554, 2195 0x25600, 0x25600, 2196 0x25608, 0x25628, 2197 0x25630, 0x2563c, 2198 0x25700, 0x2571c, 2199 0x25780, 0x2578c, 2200 0x25800, 0x25c38, 2201 0x25c80, 0x25d7c, 2202 0x25e00, 0x25e04, 2203 0x26000, 0x2602c, 2204 0x26100, 0x2613c, 2205 0x26190, 0x261c8, 2206 0x26200, 0x26318, 2207 0x26400, 0x26528, 2208 0x26540, 0x26614, 2209 0x27000, 0x27040, 2210 0x2704c, 0x27060, 2211 0x270c0, 0x270ec, 2212 0x27200, 0x27268, 2213 0x27270, 0x27284, 2214 0x272fc, 0x27388, 2215 0x27400, 0x27404, 2216 0x27500, 0x27518, 2217 0x2752c, 0x2753c, 2218 0x27550, 0x27554, 2219 0x27600, 0x27600, 2220 0x27608, 0x27628, 2221 0x27630, 0x2763c, 2222 0x27700, 0x2771c, 2223 0x27780, 0x2778c, 2224 0x27800, 0x27c38, 2225 0x27c80, 0x27d7c, 2226 0x27e00, 0x27e04 2227 }; 2228 2229 regs->version = 4 | (sc->params.rev << 10); 2230 for (i = 0; i < ARRAY_SIZE(reg_ranges); i += 2) 2231 reg_block_dump(sc, buf, reg_ranges[i], reg_ranges[i + 1]); 2232 } 2233 2234 static void 2235 cxgbe_tick(void *arg) 2236 { 2237 struct port_info *pi = arg; 2238 struct ifnet *ifp = pi->ifp; 2239 struct sge_txq *txq; 2240 int i, drops; 2241 struct port_stats *s = &pi->stats; 2242 2243 PORT_LOCK(pi); 2244 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2245 PORT_UNLOCK(pi); 2246 return; /* without scheduling another callout */ 2247 } 2248 2249 t4_get_port_stats(pi->adapter, pi->tx_chan, s); 2250 2251 ifp->if_opackets = s->tx_frames; 2252 ifp->if_ipackets = s->rx_frames; 2253 ifp->if_obytes = s->tx_octets; 2254 ifp->if_ibytes = s->rx_octets; 2255 ifp->if_omcasts = s->tx_mcast_frames; 2256 ifp->if_imcasts = s->rx_mcast_frames; 2257 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2258 s->rx_ovflow3; 2259 2260 drops = s->tx_drop; 2261 for_each_txq(pi, i, txq) 2262 drops += txq->eq.br->br_drops; 2263 ifp->if_snd.ifq_drops = drops; 2264 2265 ifp->if_oerrors = s->tx_error_frames; 2266 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long + 2267 s->rx_fcs_err + s->rx_len_err; 2268 2269 callout_schedule(&pi->tick, hz); 2270 PORT_UNLOCK(pi); 2271 } 2272 2273 static int 2274 t4_sysctls(struct adapter *sc) 2275 { 2276 struct sysctl_ctx_list *ctx; 2277 struct sysctl_oid *oid; 2278 struct sysctl_oid_list *children; 2279 2280 ctx = device_get_sysctl_ctx(sc->dev); 2281 oid = device_get_sysctl_tree(sc->dev); 2282 children = SYSCTL_CHILDREN(oid); 2283 2284 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, 2285 &sc->params.nports, 0, "# of ports"); 2286 2287 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 2288 &sc->params.rev, 0, "chip hardware revision"); 2289 2290 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 2291 CTLFLAG_RD, &sc->fw_version, 0, "firmware version"); 2292 2293 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "TOE", CTLFLAG_RD, 2294 &sc->params.offload, 0, "hardware is capable of TCP offload"); 2295 2296 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, 2297 &sc->params.vpd.cclk, 0, "core clock frequency (in KHz)"); 2298 2299 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 2300 CTLTYPE_STRING | CTLFLAG_RD, &intr_timer, sizeof(intr_timer), 2301 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 2302 2303 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 2304 CTLTYPE_STRING | CTLFLAG_RD, &intr_pktcount, sizeof(intr_pktcount), 2305 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 2306 2307 return (0); 2308 } 2309 2310 static int 2311 cxgbe_sysctls(struct port_info *pi) 2312 { 2313 struct sysctl_ctx_list *ctx; 2314 struct sysctl_oid *oid; 2315 struct sysctl_oid_list *children; 2316 2317 ctx = device_get_sysctl_ctx(pi->dev); 2318 2319 /* 2320 * dev.cxgbe.X. 2321 */ 2322 oid = device_get_sysctl_tree(pi->dev); 2323 children = SYSCTL_CHILDREN(oid); 2324 2325 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 2326 &pi->nrxq, 0, "# of rx queues"); 2327 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 2328 &pi->ntxq, 0, "# of tx queues"); 2329 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 2330 &pi->first_rxq, 0, "index of first rx queue"); 2331 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 2332 &pi->first_txq, 0, "index of first tx queue"); 2333 2334 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 2335 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_tmr_idx, "I", 2336 "holdoff timer index"); 2337 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 2338 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_pktc_idx, "I", 2339 "holdoff packet counter index"); 2340 2341 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 2342 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_rxq, "I", 2343 "rx queue size"); 2344 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 2345 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_txq, "I", 2346 "tx queue size"); 2347 2348 /* 2349 * dev.cxgbe.X.stats. 2350 */ 2351 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 2352 NULL, "port statistics"); 2353 children = SYSCTL_CHILDREN(oid); 2354 2355 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 2356 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 2357 CTLTYPE_U64 | CTLFLAG_RD, pi->adapter, reg, \ 2358 sysctl_handle_t4_reg64, "QU", desc) 2359 2360 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 2361 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 2362 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 2363 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 2364 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 2365 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 2366 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 2367 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 2368 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 2369 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 2370 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 2371 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 2372 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 2373 "# of tx frames in this range", 2374 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 2375 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 2376 "# of tx frames in this range", 2377 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 2378 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 2379 "# of tx frames in this range", 2380 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 2381 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 2382 "# of tx frames in this range", 2383 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 2384 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 2385 "# of tx frames in this range", 2386 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 2387 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 2388 "# of tx frames in this range", 2389 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 2390 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 2391 "# of tx frames in this range", 2392 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 2393 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 2394 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 2395 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 2396 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 2397 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 2398 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 2399 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 2400 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 2401 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 2402 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 2403 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 2404 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 2405 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 2406 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 2407 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 2408 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 2409 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 2410 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 2411 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 2412 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 2413 2414 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 2415 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 2416 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 2417 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 2418 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 2419 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 2420 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 2421 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 2422 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 2423 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 2424 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 2425 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 2426 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 2427 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 2428 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 2429 "# of frames received with bad FCS", 2430 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 2431 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 2432 "# of frames received with length error", 2433 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 2434 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 2435 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 2436 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 2437 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 2438 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 2439 "# of rx frames in this range", 2440 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 2441 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 2442 "# of rx frames in this range", 2443 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 2444 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 2445 "# of rx frames in this range", 2446 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 2447 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 2448 "# of rx frames in this range", 2449 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 2450 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 2451 "# of rx frames in this range", 2452 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 2453 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 2454 "# of rx frames in this range", 2455 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 2456 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 2457 "# of rx frames in this range", 2458 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 2459 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 2460 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 2461 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 2462 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 2463 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 2464 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 2465 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 2466 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 2467 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 2468 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 2469 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 2470 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 2471 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 2472 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 2473 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 2474 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 2475 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 2476 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 2477 2478 #undef SYSCTL_ADD_T4_REG64 2479 2480 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 2481 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 2482 &pi->stats.name, desc) 2483 2484 /* We get these from port_stats and they may be stale by upto 1s */ 2485 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 2486 "# drops due to buffer-group 0 overflows"); 2487 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 2488 "# drops due to buffer-group 1 overflows"); 2489 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 2490 "# drops due to buffer-group 2 overflows"); 2491 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 2492 "# drops due to buffer-group 3 overflows"); 2493 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 2494 "# of buffer-group 0 truncated packets"); 2495 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 2496 "# of buffer-group 1 truncated packets"); 2497 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 2498 "# of buffer-group 2 truncated packets"); 2499 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 2500 "# of buffer-group 3 truncated packets"); 2501 2502 #undef SYSCTL_ADD_T4_PORTSTAT 2503 2504 return (0); 2505 } 2506 2507 static int 2508 sysctl_int_array(SYSCTL_HANDLER_ARGS) 2509 { 2510 int rc, *i; 2511 struct sbuf sb; 2512 2513 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 2514 for (i = arg1; arg2; arg2 -= sizeof(int), i++) 2515 sbuf_printf(&sb, "%d ", *i); 2516 sbuf_trim(&sb); 2517 sbuf_finish(&sb); 2518 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 2519 sbuf_delete(&sb); 2520 return (rc); 2521 } 2522 2523 static int 2524 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 2525 { 2526 struct port_info *pi = arg1; 2527 struct adapter *sc = pi->adapter; 2528 struct sge_rxq *rxq; 2529 int idx, rc, i; 2530 2531 idx = pi->tmr_idx; 2532 2533 rc = sysctl_handle_int(oidp, &idx, 0, req); 2534 if (rc != 0 || req->newptr == NULL) 2535 return (rc); 2536 2537 if (idx < 0 || idx >= SGE_NTIMERS) 2538 return (EINVAL); 2539 2540 ADAPTER_LOCK(sc); 2541 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2542 if (rc == 0) { 2543 for_each_rxq(pi, i, rxq) { 2544 rxq->iq.intr_params = V_QINTR_TIMER_IDX(idx) | 2545 V_QINTR_CNT_EN(pi->pktc_idx != -1); 2546 } 2547 pi->tmr_idx = idx; 2548 } 2549 2550 ADAPTER_UNLOCK(sc); 2551 return (rc); 2552 } 2553 2554 static int 2555 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 2556 { 2557 struct port_info *pi = arg1; 2558 struct adapter *sc = pi->adapter; 2559 int idx, rc; 2560 2561 idx = pi->pktc_idx; 2562 2563 rc = sysctl_handle_int(oidp, &idx, 0, req); 2564 if (rc != 0 || req->newptr == NULL) 2565 return (rc); 2566 2567 if (idx < -1 || idx >= SGE_NCOUNTERS) 2568 return (EINVAL); 2569 2570 ADAPTER_LOCK(sc); 2571 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2572 if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING) 2573 rc = EBUSY; /* can be changed only when port is down */ 2574 2575 if (rc == 0) 2576 pi->pktc_idx = idx; 2577 2578 ADAPTER_UNLOCK(sc); 2579 return (rc); 2580 } 2581 2582 static int 2583 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 2584 { 2585 struct port_info *pi = arg1; 2586 struct adapter *sc = pi->adapter; 2587 int qsize, rc; 2588 2589 qsize = pi->qsize_rxq; 2590 2591 rc = sysctl_handle_int(oidp, &qsize, 0, req); 2592 if (rc != 0 || req->newptr == NULL) 2593 return (rc); 2594 2595 if (qsize < 128 || (qsize & 7)) 2596 return (EINVAL); 2597 2598 ADAPTER_LOCK(sc); 2599 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2600 if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING) 2601 rc = EBUSY; /* can be changed only when port is down */ 2602 2603 if (rc == 0) 2604 pi->qsize_rxq = qsize; 2605 2606 ADAPTER_UNLOCK(sc); 2607 return (rc); 2608 } 2609 2610 static int 2611 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 2612 { 2613 struct port_info *pi = arg1; 2614 struct adapter *sc = pi->adapter; 2615 int qsize, rc; 2616 2617 qsize = pi->qsize_txq; 2618 2619 rc = sysctl_handle_int(oidp, &qsize, 0, req); 2620 if (rc != 0 || req->newptr == NULL) 2621 return (rc); 2622 2623 if (qsize < 128) 2624 return (EINVAL); 2625 2626 ADAPTER_LOCK(sc); 2627 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2628 if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING) 2629 rc = EBUSY; /* can be changed only when port is down */ 2630 2631 if (rc == 0) 2632 pi->qsize_txq = qsize; 2633 2634 ADAPTER_UNLOCK(sc); 2635 return (rc); 2636 } 2637 2638 static int 2639 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 2640 { 2641 struct adapter *sc = arg1; 2642 int reg = arg2; 2643 uint64_t val; 2644 2645 val = t4_read_reg64(sc, reg); 2646 2647 return (sysctl_handle_64(oidp, &val, 0, req)); 2648 } 2649 2650 static inline void 2651 txq_start(struct ifnet *ifp, struct sge_txq *txq) 2652 { 2653 struct buf_ring *br; 2654 struct mbuf *m; 2655 2656 TXQ_LOCK_ASSERT_OWNED(txq); 2657 2658 br = txq->eq.br; 2659 m = txq->m ? txq->m : drbr_dequeue(ifp, br); 2660 if (m) 2661 t4_eth_tx(ifp, txq, m); 2662 } 2663 2664 void 2665 cxgbe_txq_start(void *arg, int count) 2666 { 2667 struct sge_txq *txq = arg; 2668 2669 TXQ_LOCK(txq); 2670 txq_start(txq->ifp, txq); 2671 TXQ_UNLOCK(txq); 2672 } 2673 2674 int 2675 t4_os_find_pci_capability(struct adapter *sc, int cap) 2676 { 2677 device_t dev; 2678 struct pci_devinfo *dinfo; 2679 pcicfgregs *cfg; 2680 uint32_t status; 2681 uint8_t ptr; 2682 2683 dev = sc->dev; 2684 dinfo = device_get_ivars(dev); 2685 cfg = &dinfo->cfg; 2686 2687 status = pci_read_config(dev, PCIR_STATUS, 2); 2688 if (!(status & PCIM_STATUS_CAPPRESENT)) 2689 return (0); 2690 2691 switch (cfg->hdrtype & PCIM_HDRTYPE) { 2692 case 0: 2693 case 1: 2694 ptr = PCIR_CAP_PTR; 2695 break; 2696 case 2: 2697 ptr = PCIR_CAP_PTR_2; 2698 break; 2699 default: 2700 return (0); 2701 break; 2702 } 2703 ptr = pci_read_config(dev, ptr, 1); 2704 2705 while (ptr != 0) { 2706 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 2707 return (ptr); 2708 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 2709 } 2710 2711 return (0); 2712 } 2713 2714 int 2715 t4_os_pci_save_state(struct adapter *sc) 2716 { 2717 device_t dev; 2718 struct pci_devinfo *dinfo; 2719 2720 dev = sc->dev; 2721 dinfo = device_get_ivars(dev); 2722 2723 pci_cfg_save(dev, dinfo, 0); 2724 return (0); 2725 } 2726 2727 int 2728 t4_os_pci_restore_state(struct adapter *sc) 2729 { 2730 device_t dev; 2731 struct pci_devinfo *dinfo; 2732 2733 dev = sc->dev; 2734 dinfo = device_get_ivars(dev); 2735 2736 pci_cfg_restore(dev, dinfo); 2737 return (0); 2738 } 2739 2740 void 2741 t4_os_portmod_changed(const struct adapter *sc, int idx) 2742 { 2743 struct port_info *pi = sc->port[idx]; 2744 static const char *mod_str[] = { 2745 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX" 2746 }; 2747 2748 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 2749 if_printf(pi->ifp, "transceiver unplugged.\n"); 2750 else if (pi->mod_type > 0 && pi->mod_type < ARRAY_SIZE(mod_str)) { 2751 if_printf(pi->ifp, "%s transceiver inserted.\n", 2752 mod_str[pi->mod_type]); 2753 } else { 2754 if_printf(pi->ifp, "transceiver (type %d) inserted.\n", 2755 pi->mod_type); 2756 } 2757 } 2758 2759 void 2760 t4_os_link_changed(struct adapter *sc, int idx, int link_stat) 2761 { 2762 struct port_info *pi = sc->port[idx]; 2763 struct ifnet *ifp = pi->ifp; 2764 2765 if (link_stat) { 2766 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed); 2767 if_link_state_change(ifp, LINK_STATE_UP); 2768 } else 2769 if_link_state_change(ifp, LINK_STATE_DOWN); 2770 } 2771 2772 static int 2773 t4_open(struct cdev *dev, int flags, int type, struct thread *td) 2774 { 2775 return (0); 2776 } 2777 2778 static int 2779 t4_close(struct cdev *dev, int flags, int type, struct thread *td) 2780 { 2781 return (0); 2782 } 2783 2784 static int 2785 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 2786 struct thread *td) 2787 { 2788 int rc; 2789 struct adapter *sc = dev->si_drv1; 2790 2791 rc = priv_check(td, PRIV_DRIVER); 2792 if (rc != 0) 2793 return (rc); 2794 2795 switch (cmd) { 2796 case CHELSIO_T4_GETREG32: { 2797 struct t4_reg32 *edata = (struct t4_reg32 *)data; 2798 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2799 return (EFAULT); 2800 edata->val = t4_read_reg(sc, edata->addr); 2801 break; 2802 } 2803 case CHELSIO_T4_SETREG32: { 2804 struct t4_reg32 *edata = (struct t4_reg32 *)data; 2805 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2806 return (EFAULT); 2807 t4_write_reg(sc, edata->addr, edata->val); 2808 break; 2809 } 2810 case CHELSIO_T4_REGDUMP: { 2811 struct t4_regdump *regs = (struct t4_regdump *)data; 2812 int reglen = T4_REGDUMP_SIZE; 2813 uint8_t *buf; 2814 2815 if (regs->len < reglen) { 2816 regs->len = reglen; /* hint to the caller */ 2817 return (ENOBUFS); 2818 } 2819 2820 regs->len = reglen; 2821 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 2822 t4_get_regs(sc, regs, buf); 2823 rc = copyout(buf, regs->data, reglen); 2824 free(buf, M_CXGBE); 2825 break; 2826 } 2827 default: 2828 rc = EINVAL; 2829 } 2830 2831 return (rc); 2832 } 2833 2834 static int 2835 t4_mod_event(module_t mod, int cmd, void *arg) 2836 { 2837 2838 if (cmd == MOD_LOAD) 2839 t4_sge_modload(); 2840 2841 return (0); 2842 } 2843 2844 static devclass_t t4_devclass; 2845 static devclass_t cxgbe_devclass; 2846 2847 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, t4_mod_event, 0); 2848 MODULE_VERSION(t4nex, 1); 2849 2850 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 2851 MODULE_VERSION(cxgbe, 1); 2852