1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_kern_tls.h" 37 #include "opt_ratelimit.h" 38 #include "opt_rss.h" 39 40 #include <sys/param.h> 41 #include <sys/conf.h> 42 #include <sys/priv.h> 43 #include <sys/kernel.h> 44 #include <sys/bus.h> 45 #include <sys/eventhandler.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/queue.h> 49 #include <sys/taskqueue.h> 50 #include <sys/pciio.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pci_private.h> 54 #include <sys/firmware.h> 55 #include <sys/sbuf.h> 56 #include <sys/smp.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/sysctl.h> 60 #include <net/ethernet.h> 61 #include <net/if.h> 62 #include <net/if_types.h> 63 #include <net/if_dl.h> 64 #include <net/if_vlan_var.h> 65 #ifdef RSS 66 #include <net/rss_config.h> 67 #endif 68 #include <netinet/in.h> 69 #include <netinet/ip.h> 70 #ifdef KERN_TLS 71 #include <netinet/tcp_seq.h> 72 #endif 73 #if defined(__i386__) || defined(__amd64__) 74 #include <machine/md_var.h> 75 #include <machine/cputypes.h> 76 #include <vm/vm.h> 77 #include <vm/pmap.h> 78 #endif 79 #ifdef DDB 80 #include <ddb/ddb.h> 81 #include <ddb/db_lex.h> 82 #endif 83 84 #include "common/common.h" 85 #include "common/t4_msg.h" 86 #include "common/t4_regs.h" 87 #include "common/t4_regs_values.h" 88 #include "cudbg/cudbg.h" 89 #include "t4_clip.h" 90 #include "t4_ioctl.h" 91 #include "t4_l2t.h" 92 #include "t4_mp_ring.h" 93 #include "t4_if.h" 94 #include "t4_smt.h" 95 96 /* T4 bus driver interface */ 97 static int t4_probe(device_t); 98 static int t4_attach(device_t); 99 static int t4_detach(device_t); 100 static int t4_child_location_str(device_t, device_t, char *, size_t); 101 static int t4_ready(device_t); 102 static int t4_read_port_device(device_t, int, device_t *); 103 static device_method_t t4_methods[] = { 104 DEVMETHOD(device_probe, t4_probe), 105 DEVMETHOD(device_attach, t4_attach), 106 DEVMETHOD(device_detach, t4_detach), 107 108 DEVMETHOD(bus_child_location_str, t4_child_location_str), 109 110 DEVMETHOD(t4_is_main_ready, t4_ready), 111 DEVMETHOD(t4_read_port_device, t4_read_port_device), 112 113 DEVMETHOD_END 114 }; 115 static driver_t t4_driver = { 116 "t4nex", 117 t4_methods, 118 sizeof(struct adapter) 119 }; 120 121 122 /* T4 port (cxgbe) interface */ 123 static int cxgbe_probe(device_t); 124 static int cxgbe_attach(device_t); 125 static int cxgbe_detach(device_t); 126 device_method_t cxgbe_methods[] = { 127 DEVMETHOD(device_probe, cxgbe_probe), 128 DEVMETHOD(device_attach, cxgbe_attach), 129 DEVMETHOD(device_detach, cxgbe_detach), 130 { 0, 0 } 131 }; 132 static driver_t cxgbe_driver = { 133 "cxgbe", 134 cxgbe_methods, 135 sizeof(struct port_info) 136 }; 137 138 /* T4 VI (vcxgbe) interface */ 139 static int vcxgbe_probe(device_t); 140 static int vcxgbe_attach(device_t); 141 static int vcxgbe_detach(device_t); 142 static device_method_t vcxgbe_methods[] = { 143 DEVMETHOD(device_probe, vcxgbe_probe), 144 DEVMETHOD(device_attach, vcxgbe_attach), 145 DEVMETHOD(device_detach, vcxgbe_detach), 146 { 0, 0 } 147 }; 148 static driver_t vcxgbe_driver = { 149 "vcxgbe", 150 vcxgbe_methods, 151 sizeof(struct vi_info) 152 }; 153 154 static d_ioctl_t t4_ioctl; 155 156 static struct cdevsw t4_cdevsw = { 157 .d_version = D_VERSION, 158 .d_ioctl = t4_ioctl, 159 .d_name = "t4nex", 160 }; 161 162 /* T5 bus driver interface */ 163 static int t5_probe(device_t); 164 static device_method_t t5_methods[] = { 165 DEVMETHOD(device_probe, t5_probe), 166 DEVMETHOD(device_attach, t4_attach), 167 DEVMETHOD(device_detach, t4_detach), 168 169 DEVMETHOD(bus_child_location_str, t4_child_location_str), 170 171 DEVMETHOD(t4_is_main_ready, t4_ready), 172 DEVMETHOD(t4_read_port_device, t4_read_port_device), 173 174 DEVMETHOD_END 175 }; 176 static driver_t t5_driver = { 177 "t5nex", 178 t5_methods, 179 sizeof(struct adapter) 180 }; 181 182 183 /* T5 port (cxl) interface */ 184 static driver_t cxl_driver = { 185 "cxl", 186 cxgbe_methods, 187 sizeof(struct port_info) 188 }; 189 190 /* T5 VI (vcxl) interface */ 191 static driver_t vcxl_driver = { 192 "vcxl", 193 vcxgbe_methods, 194 sizeof(struct vi_info) 195 }; 196 197 /* T6 bus driver interface */ 198 static int t6_probe(device_t); 199 static device_method_t t6_methods[] = { 200 DEVMETHOD(device_probe, t6_probe), 201 DEVMETHOD(device_attach, t4_attach), 202 DEVMETHOD(device_detach, t4_detach), 203 204 DEVMETHOD(bus_child_location_str, t4_child_location_str), 205 206 DEVMETHOD(t4_is_main_ready, t4_ready), 207 DEVMETHOD(t4_read_port_device, t4_read_port_device), 208 209 DEVMETHOD_END 210 }; 211 static driver_t t6_driver = { 212 "t6nex", 213 t6_methods, 214 sizeof(struct adapter) 215 }; 216 217 218 /* T6 port (cc) interface */ 219 static driver_t cc_driver = { 220 "cc", 221 cxgbe_methods, 222 sizeof(struct port_info) 223 }; 224 225 /* T6 VI (vcc) interface */ 226 static driver_t vcc_driver = { 227 "vcc", 228 vcxgbe_methods, 229 sizeof(struct vi_info) 230 }; 231 232 /* ifnet interface */ 233 static void cxgbe_init(void *); 234 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 235 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 236 static void cxgbe_qflush(struct ifnet *); 237 #if defined(KERN_TLS) || defined(RATELIMIT) 238 static int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 239 struct m_snd_tag **); 240 static int cxgbe_snd_tag_modify(struct m_snd_tag *, 241 union if_snd_tag_modify_params *); 242 static int cxgbe_snd_tag_query(struct m_snd_tag *, 243 union if_snd_tag_query_params *); 244 static void cxgbe_snd_tag_free(struct m_snd_tag *); 245 #endif 246 247 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 248 249 /* 250 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 251 * then ADAPTER_LOCK, then t4_uld_list_lock. 252 */ 253 static struct sx t4_list_lock; 254 SLIST_HEAD(, adapter) t4_list; 255 #ifdef TCP_OFFLOAD 256 static struct sx t4_uld_list_lock; 257 SLIST_HEAD(, uld_info) t4_uld_list; 258 #endif 259 260 /* 261 * Tunables. See tweak_tunables() too. 262 * 263 * Each tunable is set to a default value here if it's known at compile-time. 264 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 265 * provide a reasonable default (upto n) when the driver is loaded. 266 * 267 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 268 * T5 are under hw.cxl. 269 */ 270 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 271 "cxgbe(4) parameters"); 272 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 273 "cxgbe(4) T5+ parameters"); 274 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 275 "cxgbe(4) TOE parameters"); 276 277 /* 278 * Number of queues for tx and rx, NIC and offload. 279 */ 280 #define NTXQ 16 281 int t4_ntxq = -NTXQ; 282 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 283 "Number of TX queues per port"); 284 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 285 286 #define NRXQ 8 287 int t4_nrxq = -NRXQ; 288 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 289 "Number of RX queues per port"); 290 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 291 292 #define NTXQ_VI 1 293 static int t4_ntxq_vi = -NTXQ_VI; 294 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 295 "Number of TX queues per VI"); 296 297 #define NRXQ_VI 1 298 static int t4_nrxq_vi = -NRXQ_VI; 299 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 300 "Number of RX queues per VI"); 301 302 static int t4_rsrv_noflowq = 0; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 304 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 305 306 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 307 #define NOFLDTXQ 8 308 static int t4_nofldtxq = -NOFLDTXQ; 309 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 310 "Number of offload TX queues per port"); 311 312 #define NOFLDRXQ 2 313 static int t4_nofldrxq = -NOFLDRXQ; 314 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 315 "Number of offload RX queues per port"); 316 317 #define NOFLDTXQ_VI 1 318 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 319 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 320 "Number of offload TX queues per VI"); 321 322 #define NOFLDRXQ_VI 1 323 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 324 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 325 "Number of offload RX queues per VI"); 326 327 #define TMR_IDX_OFLD 1 328 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 329 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 330 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 331 332 #define PKTC_IDX_OFLD (-1) 333 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 334 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 335 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 336 337 /* 0 means chip/fw default, non-zero number is value in microseconds */ 338 static u_long t4_toe_keepalive_idle = 0; 339 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 340 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 341 342 /* 0 means chip/fw default, non-zero number is value in microseconds */ 343 static u_long t4_toe_keepalive_interval = 0; 344 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 345 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 346 347 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 348 static int t4_toe_keepalive_count = 0; 349 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 350 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 351 352 /* 0 means chip/fw default, non-zero number is value in microseconds */ 353 static u_long t4_toe_rexmt_min = 0; 354 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 355 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 356 357 /* 0 means chip/fw default, non-zero number is value in microseconds */ 358 static u_long t4_toe_rexmt_max = 0; 359 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 360 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 361 362 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 363 static int t4_toe_rexmt_count = 0; 364 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 365 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 366 367 /* -1 means chip/fw default, other values are raw backoff values to use */ 368 static int t4_toe_rexmt_backoff[16] = { 369 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 370 }; 371 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, 372 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 373 "cxgbe(4) TOE retransmit backoff values"); 374 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 375 &t4_toe_rexmt_backoff[0], 0, ""); 376 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 377 &t4_toe_rexmt_backoff[1], 0, ""); 378 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 379 &t4_toe_rexmt_backoff[2], 0, ""); 380 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 381 &t4_toe_rexmt_backoff[3], 0, ""); 382 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 383 &t4_toe_rexmt_backoff[4], 0, ""); 384 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 385 &t4_toe_rexmt_backoff[5], 0, ""); 386 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 387 &t4_toe_rexmt_backoff[6], 0, ""); 388 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 389 &t4_toe_rexmt_backoff[7], 0, ""); 390 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 391 &t4_toe_rexmt_backoff[8], 0, ""); 392 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 393 &t4_toe_rexmt_backoff[9], 0, ""); 394 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 395 &t4_toe_rexmt_backoff[10], 0, ""); 396 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 397 &t4_toe_rexmt_backoff[11], 0, ""); 398 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 399 &t4_toe_rexmt_backoff[12], 0, ""); 400 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 401 &t4_toe_rexmt_backoff[13], 0, ""); 402 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 403 &t4_toe_rexmt_backoff[14], 0, ""); 404 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 405 &t4_toe_rexmt_backoff[15], 0, ""); 406 #endif 407 408 #ifdef DEV_NETMAP 409 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */ 410 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */ 411 static int t4_native_netmap = NN_EXTRA_VI; 412 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap, 413 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs"); 414 415 #define NNMTXQ 8 416 static int t4_nnmtxq = -NNMTXQ; 417 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0, 418 "Number of netmap TX queues"); 419 420 #define NNMRXQ 8 421 static int t4_nnmrxq = -NNMRXQ; 422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0, 423 "Number of netmap RX queues"); 424 425 #define NNMTXQ_VI 2 426 static int t4_nnmtxq_vi = -NNMTXQ_VI; 427 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 428 "Number of netmap TX queues per VI"); 429 430 #define NNMRXQ_VI 2 431 static int t4_nnmrxq_vi = -NNMRXQ_VI; 432 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 433 "Number of netmap RX queues per VI"); 434 #endif 435 436 /* 437 * Holdoff parameters for ports. 438 */ 439 #define TMR_IDX 1 440 int t4_tmr_idx = TMR_IDX; 441 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 442 0, "Holdoff timer index"); 443 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 444 445 #define PKTC_IDX (-1) 446 int t4_pktc_idx = PKTC_IDX; 447 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 448 0, "Holdoff packet counter index"); 449 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 450 451 /* 452 * Size (# of entries) of each tx and rx queue. 453 */ 454 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 455 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 456 "Number of descriptors in each TX queue"); 457 458 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 459 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 460 "Number of descriptors in each RX queue"); 461 462 /* 463 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 464 */ 465 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 466 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 467 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 468 469 /* 470 * Configuration file. All the _CF names here are special. 471 */ 472 #define DEFAULT_CF "default" 473 #define BUILTIN_CF "built-in" 474 #define FLASH_CF "flash" 475 #define UWIRE_CF "uwire" 476 #define FPGA_CF "fpga" 477 static char t4_cfg_file[32] = DEFAULT_CF; 478 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 479 sizeof(t4_cfg_file), "Firmware configuration file"); 480 481 /* 482 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 483 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 484 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 485 * mark or when signalled to do so, 0 to never emit PAUSE. 486 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 487 * negotiated settings will override rx_pause/tx_pause. 488 * Otherwise rx_pause/tx_pause are applied forcibly. 489 */ 490 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 491 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 492 &t4_pause_settings, 0, 493 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 494 495 /* 496 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 497 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 498 * 0 to disable FEC. 499 */ 500 static int t4_fec = -1; 501 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 502 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 503 504 /* 505 * Link autonegotiation. 506 * -1 to run with the firmware default. 507 * 0 to disable. 508 * 1 to enable. 509 */ 510 static int t4_autoneg = -1; 511 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 512 "Link autonegotiation"); 513 514 /* 515 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 516 * encouraged respectively). '-n' is the same as 'n' except the firmware 517 * version used in the checks is read from the firmware bundled with the driver. 518 */ 519 static int t4_fw_install = 1; 520 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 521 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 522 523 /* 524 * ASIC features that will be used. Disable the ones you don't want so that the 525 * chip resources aren't wasted on features that will not be used. 526 */ 527 static int t4_nbmcaps_allowed = 0; 528 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 529 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 530 531 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 532 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 533 &t4_linkcaps_allowed, 0, "Default link capabilities"); 534 535 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 536 FW_CAPS_CONFIG_SWITCH_EGRESS; 537 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 538 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 539 540 #ifdef RATELIMIT 541 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 542 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 543 #else 544 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 545 FW_CAPS_CONFIG_NIC_HASHFILTER; 546 #endif 547 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 548 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 549 550 static int t4_toecaps_allowed = -1; 551 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 552 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 553 554 static int t4_rdmacaps_allowed = -1; 555 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 556 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 557 558 static int t4_cryptocaps_allowed = -1; 559 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 560 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 561 562 static int t4_iscsicaps_allowed = -1; 563 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 564 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 565 566 static int t4_fcoecaps_allowed = 0; 567 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 568 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 569 570 static int t5_write_combine = 0; 571 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 572 0, "Use WC instead of UC for BAR2"); 573 574 static int t4_num_vis = 1; 575 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 576 "Number of VIs per port"); 577 578 /* 579 * PCIe Relaxed Ordering. 580 * -1: driver should figure out a good value. 581 * 0: disable RO. 582 * 1: enable RO. 583 * 2: leave RO alone. 584 */ 585 static int pcie_relaxed_ordering = -1; 586 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 587 &pcie_relaxed_ordering, 0, 588 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 589 590 static int t4_panic_on_fatal_err = 0; 591 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN, 592 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 593 594 static int t4_tx_vm_wr = 0; 595 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0, 596 "Use VM work requests to transmit packets."); 597 598 /* 599 * Set to non-zero to enable the attack filter. A packet that matches any of 600 * these conditions will get dropped on ingress: 601 * 1) IP && source address == destination address. 602 * 2) TCP/IP && source address is not a unicast address. 603 * 3) TCP/IP && destination address is not a unicast address. 604 * 4) IP && source address is loopback (127.x.y.z). 605 * 5) IP && destination address is loopback (127.x.y.z). 606 * 6) IPv6 && source address == destination address. 607 * 7) IPv6 && source address is not a unicast address. 608 * 8) IPv6 && source address is loopback (::1/128). 609 * 9) IPv6 && destination address is loopback (::1/128). 610 * 10) IPv6 && source address is unspecified (::/128). 611 * 11) IPv6 && destination address is unspecified (::/128). 612 * 12) TCP/IPv6 && source address is multicast (ff00::/8). 613 * 13) TCP/IPv6 && destination address is multicast (ff00::/8). 614 */ 615 static int t4_attack_filter = 0; 616 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN, 617 &t4_attack_filter, 0, "Drop suspicious traffic"); 618 619 static int t4_drop_ip_fragments = 0; 620 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN, 621 &t4_drop_ip_fragments, 0, "Drop IP fragments"); 622 623 static int t4_drop_pkts_with_l2_errors = 1; 624 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN, 625 &t4_drop_pkts_with_l2_errors, 0, 626 "Drop all frames with Layer 2 length or checksum errors"); 627 628 static int t4_drop_pkts_with_l3_errors = 0; 629 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN, 630 &t4_drop_pkts_with_l3_errors, 0, 631 "Drop all frames with IP version, length, or checksum errors"); 632 633 static int t4_drop_pkts_with_l4_errors = 0; 634 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN, 635 &t4_drop_pkts_with_l4_errors, 0, 636 "Drop all frames with Layer 4 length, checksum, or other errors"); 637 638 #ifdef TCP_OFFLOAD 639 /* 640 * TOE tunables. 641 */ 642 static int t4_cop_managed_offloading = 0; 643 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 644 &t4_cop_managed_offloading, 0, 645 "COP (Connection Offload Policy) controls all TOE offload"); 646 #endif 647 648 #ifdef KERN_TLS 649 /* 650 * This enables KERN_TLS for all adapters if set. 651 */ 652 static int t4_kern_tls = 0; 653 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0, 654 "Enable KERN_TLS mode for all supported adapters"); 655 656 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 657 "cxgbe(4) KERN_TLS parameters"); 658 659 static int t4_tls_inline_keys = 0; 660 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN, 661 &t4_tls_inline_keys, 0, 662 "Always pass TLS keys in work requests (1) or attempt to store TLS keys " 663 "in card memory."); 664 665 static int t4_tls_combo_wrs = 0; 666 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs, 667 0, "Attempt to combine TCB field updates with TLS record work requests."); 668 #endif 669 670 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 671 static int vi_mac_funcs[] = { 672 FW_VI_FUNC_ETH, 673 FW_VI_FUNC_OFLD, 674 FW_VI_FUNC_IWARP, 675 FW_VI_FUNC_OPENISCSI, 676 FW_VI_FUNC_OPENFCOE, 677 FW_VI_FUNC_FOISCSI, 678 FW_VI_FUNC_FOFCOE, 679 }; 680 681 struct intrs_and_queues { 682 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 683 uint16_t num_vis; /* number of VIs for each port */ 684 uint16_t nirq; /* Total # of vectors */ 685 uint16_t ntxq; /* # of NIC txq's for each port */ 686 uint16_t nrxq; /* # of NIC rxq's for each port */ 687 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 688 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 689 uint16_t nnmtxq; /* # of netmap txq's */ 690 uint16_t nnmrxq; /* # of netmap rxq's */ 691 692 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 693 uint16_t ntxq_vi; /* # of NIC txq's */ 694 uint16_t nrxq_vi; /* # of NIC rxq's */ 695 uint16_t nofldtxq_vi; /* # of TOE txq's */ 696 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 697 uint16_t nnmtxq_vi; /* # of netmap txq's */ 698 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 699 }; 700 701 static void setup_memwin(struct adapter *); 702 static void position_memwin(struct adapter *, int, uint32_t); 703 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 704 static int fwmtype_to_hwmtype(int); 705 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 706 uint32_t *); 707 static int fixup_devlog_params(struct adapter *); 708 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 709 static int contact_firmware(struct adapter *); 710 static int partition_resources(struct adapter *); 711 static int get_params__pre_init(struct adapter *); 712 static int set_params__pre_init(struct adapter *); 713 static int get_params__post_init(struct adapter *); 714 static int set_params__post_init(struct adapter *); 715 static void t4_set_desc(struct adapter *); 716 static bool fixed_ifmedia(struct port_info *); 717 static void build_medialist(struct port_info *); 718 static void init_link_config(struct port_info *); 719 static int fixup_link_config(struct port_info *); 720 static int apply_link_config(struct port_info *); 721 static int cxgbe_init_synchronized(struct vi_info *); 722 static int cxgbe_uninit_synchronized(struct vi_info *); 723 static void quiesce_txq(struct adapter *, struct sge_txq *); 724 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 725 static void quiesce_iq(struct adapter *, struct sge_iq *); 726 static void quiesce_fl(struct adapter *, struct sge_fl *); 727 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 728 driver_intr_t *, void *, char *); 729 static int t4_free_irq(struct adapter *, struct irq *); 730 static void t4_init_atid_table(struct adapter *); 731 static void t4_free_atid_table(struct adapter *); 732 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 733 static void vi_refresh_stats(struct adapter *, struct vi_info *); 734 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 735 static void cxgbe_tick(void *); 736 static void cxgbe_sysctls(struct port_info *); 737 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 738 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 739 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 740 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 741 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 742 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS); 743 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 744 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 745 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 746 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 747 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 748 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 749 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS); 750 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 751 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 752 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 753 static int sysctl_vdd(SYSCTL_HANDLER_ARGS); 754 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS); 755 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 756 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 757 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 758 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 759 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 760 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 761 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 762 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 763 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 764 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 765 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 766 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 767 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 768 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 769 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 770 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 771 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 772 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 773 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 774 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 775 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 776 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 777 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 778 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 779 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 780 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 781 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 782 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 783 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 784 #ifdef TCP_OFFLOAD 785 static int sysctl_tls(SYSCTL_HANDLER_ARGS); 786 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 787 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 788 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 789 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 790 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 791 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 792 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 793 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 794 #endif 795 static int get_sge_context(struct adapter *, struct t4_sge_context *); 796 static int load_fw(struct adapter *, struct t4_data *); 797 static int load_cfg(struct adapter *, struct t4_data *); 798 static int load_boot(struct adapter *, struct t4_bootrom *); 799 static int load_bootcfg(struct adapter *, struct t4_data *); 800 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 801 static void free_offload_policy(struct t4_offload_policy *); 802 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 803 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 804 static int read_i2c(struct adapter *, struct t4_i2c_data *); 805 static int clear_stats(struct adapter *, u_int); 806 #ifdef TCP_OFFLOAD 807 static int toe_capability(struct vi_info *, int); 808 static void t4_async_event(void *, int); 809 #endif 810 static int mod_event(module_t, int, void *); 811 static int notify_siblings(device_t, int); 812 813 struct { 814 uint16_t device; 815 char *desc; 816 } t4_pciids[] = { 817 {0xa000, "Chelsio Terminator 4 FPGA"}, 818 {0x4400, "Chelsio T440-dbg"}, 819 {0x4401, "Chelsio T420-CR"}, 820 {0x4402, "Chelsio T422-CR"}, 821 {0x4403, "Chelsio T440-CR"}, 822 {0x4404, "Chelsio T420-BCH"}, 823 {0x4405, "Chelsio T440-BCH"}, 824 {0x4406, "Chelsio T440-CH"}, 825 {0x4407, "Chelsio T420-SO"}, 826 {0x4408, "Chelsio T420-CX"}, 827 {0x4409, "Chelsio T420-BT"}, 828 {0x440a, "Chelsio T404-BT"}, 829 {0x440e, "Chelsio T440-LP-CR"}, 830 }, t5_pciids[] = { 831 {0xb000, "Chelsio Terminator 5 FPGA"}, 832 {0x5400, "Chelsio T580-dbg"}, 833 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 834 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 835 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 836 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 837 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 838 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 839 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 840 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 841 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 842 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 843 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 844 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 845 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 846 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 847 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 848 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 849 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 850 851 /* Custom */ 852 {0x5483, "Custom T540-CR"}, 853 {0x5484, "Custom T540-BT"}, 854 }, t6_pciids[] = { 855 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 856 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 857 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 858 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 859 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 860 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 861 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 862 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 863 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 864 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 865 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 866 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 867 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 868 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 869 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 870 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 871 872 /* Custom */ 873 {0x6480, "Custom T6225-CR"}, 874 {0x6481, "Custom T62100-CR"}, 875 {0x6482, "Custom T6225-CR"}, 876 {0x6483, "Custom T62100-CR"}, 877 {0x6484, "Custom T64100-CR"}, 878 {0x6485, "Custom T6240-SO"}, 879 {0x6486, "Custom T6225-SO-CR"}, 880 {0x6487, "Custom T6225-CR"}, 881 }; 882 883 #ifdef TCP_OFFLOAD 884 /* 885 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 886 * be exactly the same for both rxq and ofld_rxq. 887 */ 888 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 889 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 890 #endif 891 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 892 893 static int 894 t4_probe(device_t dev) 895 { 896 int i; 897 uint16_t v = pci_get_vendor(dev); 898 uint16_t d = pci_get_device(dev); 899 uint8_t f = pci_get_function(dev); 900 901 if (v != PCI_VENDOR_ID_CHELSIO) 902 return (ENXIO); 903 904 /* Attach only to PF0 of the FPGA */ 905 if (d == 0xa000 && f != 0) 906 return (ENXIO); 907 908 for (i = 0; i < nitems(t4_pciids); i++) { 909 if (d == t4_pciids[i].device) { 910 device_set_desc(dev, t4_pciids[i].desc); 911 return (BUS_PROBE_DEFAULT); 912 } 913 } 914 915 return (ENXIO); 916 } 917 918 static int 919 t5_probe(device_t dev) 920 { 921 int i; 922 uint16_t v = pci_get_vendor(dev); 923 uint16_t d = pci_get_device(dev); 924 uint8_t f = pci_get_function(dev); 925 926 if (v != PCI_VENDOR_ID_CHELSIO) 927 return (ENXIO); 928 929 /* Attach only to PF0 of the FPGA */ 930 if (d == 0xb000 && f != 0) 931 return (ENXIO); 932 933 for (i = 0; i < nitems(t5_pciids); i++) { 934 if (d == t5_pciids[i].device) { 935 device_set_desc(dev, t5_pciids[i].desc); 936 return (BUS_PROBE_DEFAULT); 937 } 938 } 939 940 return (ENXIO); 941 } 942 943 static int 944 t6_probe(device_t dev) 945 { 946 int i; 947 uint16_t v = pci_get_vendor(dev); 948 uint16_t d = pci_get_device(dev); 949 950 if (v != PCI_VENDOR_ID_CHELSIO) 951 return (ENXIO); 952 953 for (i = 0; i < nitems(t6_pciids); i++) { 954 if (d == t6_pciids[i].device) { 955 device_set_desc(dev, t6_pciids[i].desc); 956 return (BUS_PROBE_DEFAULT); 957 } 958 } 959 960 return (ENXIO); 961 } 962 963 static void 964 t5_attribute_workaround(device_t dev) 965 { 966 device_t root_port; 967 uint32_t v; 968 969 /* 970 * The T5 chips do not properly echo the No Snoop and Relaxed 971 * Ordering attributes when replying to a TLP from a Root 972 * Port. As a workaround, find the parent Root Port and 973 * disable No Snoop and Relaxed Ordering. Note that this 974 * affects all devices under this root port. 975 */ 976 root_port = pci_find_pcie_root_port(dev); 977 if (root_port == NULL) { 978 device_printf(dev, "Unable to find parent root port\n"); 979 return; 980 } 981 982 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 983 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 984 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 985 0) 986 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 987 device_get_nameunit(root_port)); 988 } 989 990 static const struct devnames devnames[] = { 991 { 992 .nexus_name = "t4nex", 993 .ifnet_name = "cxgbe", 994 .vi_ifnet_name = "vcxgbe", 995 .pf03_drv_name = "t4iov", 996 .vf_nexus_name = "t4vf", 997 .vf_ifnet_name = "cxgbev" 998 }, { 999 .nexus_name = "t5nex", 1000 .ifnet_name = "cxl", 1001 .vi_ifnet_name = "vcxl", 1002 .pf03_drv_name = "t5iov", 1003 .vf_nexus_name = "t5vf", 1004 .vf_ifnet_name = "cxlv" 1005 }, { 1006 .nexus_name = "t6nex", 1007 .ifnet_name = "cc", 1008 .vi_ifnet_name = "vcc", 1009 .pf03_drv_name = "t6iov", 1010 .vf_nexus_name = "t6vf", 1011 .vf_ifnet_name = "ccv" 1012 } 1013 }; 1014 1015 void 1016 t4_init_devnames(struct adapter *sc) 1017 { 1018 int id; 1019 1020 id = chip_id(sc); 1021 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 1022 sc->names = &devnames[id - CHELSIO_T4]; 1023 else { 1024 device_printf(sc->dev, "chip id %d is not supported.\n", id); 1025 sc->names = NULL; 1026 } 1027 } 1028 1029 static int 1030 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 1031 { 1032 const char *parent, *name; 1033 long value; 1034 int line, unit; 1035 1036 line = 0; 1037 parent = device_get_nameunit(sc->dev); 1038 name = sc->names->ifnet_name; 1039 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 1040 if (resource_long_value(name, unit, "port", &value) == 0 && 1041 value == pi->port_id) 1042 return (unit); 1043 } 1044 return (-1); 1045 } 1046 1047 static int 1048 t4_attach(device_t dev) 1049 { 1050 struct adapter *sc; 1051 int rc = 0, i, j, rqidx, tqidx, nports; 1052 struct make_dev_args mda; 1053 struct intrs_and_queues iaq; 1054 struct sge *s; 1055 uint32_t *buf; 1056 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1057 int ofld_tqidx; 1058 #endif 1059 #ifdef TCP_OFFLOAD 1060 int ofld_rqidx; 1061 #endif 1062 #ifdef DEV_NETMAP 1063 int nm_rqidx, nm_tqidx; 1064 #endif 1065 int num_vis; 1066 1067 sc = device_get_softc(dev); 1068 sc->dev = dev; 1069 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 1070 1071 if ((pci_get_device(dev) & 0xff00) == 0x5400) 1072 t5_attribute_workaround(dev); 1073 pci_enable_busmaster(dev); 1074 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 1075 uint32_t v; 1076 1077 pci_set_max_read_req(dev, 4096); 1078 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 1079 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 1080 if (pcie_relaxed_ordering == 0 && 1081 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 1082 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 1083 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1084 } else if (pcie_relaxed_ordering == 1 && 1085 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 1086 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 1087 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1088 } 1089 } 1090 1091 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 1092 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 1093 sc->traceq = -1; 1094 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 1095 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 1096 device_get_nameunit(dev)); 1097 1098 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 1099 device_get_nameunit(dev)); 1100 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 1101 t4_add_adapter(sc); 1102 1103 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 1104 TAILQ_INIT(&sc->sfl); 1105 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 1106 1107 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 1108 1109 sc->policy = NULL; 1110 rw_init(&sc->policy_lock, "connection offload policy"); 1111 1112 callout_init(&sc->ktls_tick, 1); 1113 1114 #ifdef TCP_OFFLOAD 1115 TASK_INIT(&sc->async_event_task, 0, t4_async_event, sc); 1116 #endif 1117 1118 refcount_init(&sc->vxlan_refcount, 0); 1119 1120 rc = t4_map_bars_0_and_4(sc); 1121 if (rc != 0) 1122 goto done; /* error message displayed already */ 1123 1124 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1125 1126 /* Prepare the adapter for operation. */ 1127 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1128 rc = -t4_prep_adapter(sc, buf); 1129 free(buf, M_CXGBE); 1130 if (rc != 0) { 1131 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1132 goto done; 1133 } 1134 1135 /* 1136 * This is the real PF# to which we're attaching. Works from within PCI 1137 * passthrough environments too, where pci_get_function() could return a 1138 * different PF# depending on the passthrough configuration. We need to 1139 * use the real PF# in all our communication with the firmware. 1140 */ 1141 j = t4_read_reg(sc, A_PL_WHOAMI); 1142 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1143 sc->mbox = sc->pf; 1144 1145 t4_init_devnames(sc); 1146 if (sc->names == NULL) { 1147 rc = ENOTSUP; 1148 goto done; /* error message displayed already */ 1149 } 1150 1151 /* 1152 * Do this really early, with the memory windows set up even before the 1153 * character device. The userland tool's register i/o and mem read 1154 * will work even in "recovery mode". 1155 */ 1156 setup_memwin(sc); 1157 if (t4_init_devlog_params(sc, 0) == 0) 1158 fixup_devlog_params(sc); 1159 make_dev_args_init(&mda); 1160 mda.mda_devsw = &t4_cdevsw; 1161 mda.mda_uid = UID_ROOT; 1162 mda.mda_gid = GID_WHEEL; 1163 mda.mda_mode = 0600; 1164 mda.mda_si_drv1 = sc; 1165 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1166 if (rc != 0) 1167 device_printf(dev, "failed to create nexus char device: %d.\n", 1168 rc); 1169 1170 /* Go no further if recovery mode has been requested. */ 1171 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1172 device_printf(dev, "recovery mode.\n"); 1173 goto done; 1174 } 1175 1176 #if defined(__i386__) 1177 if ((cpu_feature & CPUID_CX8) == 0) { 1178 device_printf(dev, "64 bit atomics not available.\n"); 1179 rc = ENOTSUP; 1180 goto done; 1181 } 1182 #endif 1183 1184 /* Contact the firmware and try to become the master driver. */ 1185 rc = contact_firmware(sc); 1186 if (rc != 0) 1187 goto done; /* error message displayed already */ 1188 MPASS(sc->flags & FW_OK); 1189 1190 rc = get_params__pre_init(sc); 1191 if (rc != 0) 1192 goto done; /* error message displayed already */ 1193 1194 if (sc->flags & MASTER_PF) { 1195 rc = partition_resources(sc); 1196 if (rc != 0) 1197 goto done; /* error message displayed already */ 1198 t4_intr_clear(sc); 1199 } 1200 1201 rc = get_params__post_init(sc); 1202 if (rc != 0) 1203 goto done; /* error message displayed already */ 1204 1205 rc = set_params__post_init(sc); 1206 if (rc != 0) 1207 goto done; /* error message displayed already */ 1208 1209 rc = t4_map_bar_2(sc); 1210 if (rc != 0) 1211 goto done; /* error message displayed already */ 1212 1213 rc = t4_create_dma_tag(sc); 1214 if (rc != 0) 1215 goto done; /* error message displayed already */ 1216 1217 /* 1218 * First pass over all the ports - allocate VIs and initialize some 1219 * basic parameters like mac address, port type, etc. 1220 */ 1221 for_each_port(sc, i) { 1222 struct port_info *pi; 1223 1224 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1225 sc->port[i] = pi; 1226 1227 /* These must be set before t4_port_init */ 1228 pi->adapter = sc; 1229 pi->port_id = i; 1230 /* 1231 * XXX: vi[0] is special so we can't delay this allocation until 1232 * pi->nvi's final value is known. 1233 */ 1234 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1235 M_ZERO | M_WAITOK); 1236 1237 /* 1238 * Allocate the "main" VI and initialize parameters 1239 * like mac addr. 1240 */ 1241 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1242 if (rc != 0) { 1243 device_printf(dev, "unable to initialize port %d: %d\n", 1244 i, rc); 1245 free(pi->vi, M_CXGBE); 1246 free(pi, M_CXGBE); 1247 sc->port[i] = NULL; 1248 goto done; 1249 } 1250 1251 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1252 device_get_nameunit(dev), i); 1253 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1254 sc->chan_map[pi->tx_chan] = i; 1255 1256 /* 1257 * The MPS counter for FCS errors doesn't work correctly on the 1258 * T6 so we use the MAC counter here. Which MAC is in use 1259 * depends on the link settings which will be known when the 1260 * link comes up. 1261 */ 1262 if (is_t6(sc)) { 1263 pi->fcs_reg = -1; 1264 } else if (is_t4(sc)) { 1265 pi->fcs_reg = PORT_REG(pi->tx_chan, 1266 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1267 } else { 1268 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 1269 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1270 } 1271 pi->fcs_base = 0; 1272 1273 /* All VIs on this port share this media. */ 1274 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1275 cxgbe_media_status); 1276 1277 PORT_LOCK(pi); 1278 init_link_config(pi); 1279 fixup_link_config(pi); 1280 build_medialist(pi); 1281 if (fixed_ifmedia(pi)) 1282 pi->flags |= FIXED_IFMEDIA; 1283 PORT_UNLOCK(pi); 1284 1285 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1286 t4_ifnet_unit(sc, pi)); 1287 if (pi->dev == NULL) { 1288 device_printf(dev, 1289 "failed to add device for port %d.\n", i); 1290 rc = ENXIO; 1291 goto done; 1292 } 1293 pi->vi[0].dev = pi->dev; 1294 device_set_softc(pi->dev, pi); 1295 } 1296 1297 /* 1298 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1299 */ 1300 nports = sc->params.nports; 1301 rc = cfg_itype_and_nqueues(sc, &iaq); 1302 if (rc != 0) 1303 goto done; /* error message displayed already */ 1304 1305 num_vis = iaq.num_vis; 1306 sc->intr_type = iaq.intr_type; 1307 sc->intr_count = iaq.nirq; 1308 1309 s = &sc->sge; 1310 s->nrxq = nports * iaq.nrxq; 1311 s->ntxq = nports * iaq.ntxq; 1312 if (num_vis > 1) { 1313 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1314 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1315 } 1316 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1317 s->neq += nports; /* ctrl queues: 1 per port */ 1318 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1319 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1320 if (is_offload(sc) || is_ethoffload(sc)) { 1321 s->nofldtxq = nports * iaq.nofldtxq; 1322 if (num_vis > 1) 1323 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1324 s->neq += s->nofldtxq; 1325 1326 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1327 M_CXGBE, M_ZERO | M_WAITOK); 1328 } 1329 #endif 1330 #ifdef TCP_OFFLOAD 1331 if (is_offload(sc)) { 1332 s->nofldrxq = nports * iaq.nofldrxq; 1333 if (num_vis > 1) 1334 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1335 s->neq += s->nofldrxq; /* free list */ 1336 s->niq += s->nofldrxq; 1337 1338 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1339 M_CXGBE, M_ZERO | M_WAITOK); 1340 } 1341 #endif 1342 #ifdef DEV_NETMAP 1343 s->nnmrxq = 0; 1344 s->nnmtxq = 0; 1345 if (t4_native_netmap & NN_MAIN_VI) { 1346 s->nnmrxq += nports * iaq.nnmrxq; 1347 s->nnmtxq += nports * iaq.nnmtxq; 1348 } 1349 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) { 1350 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi; 1351 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi; 1352 } 1353 s->neq += s->nnmtxq + s->nnmrxq; 1354 s->niq += s->nnmrxq; 1355 1356 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1357 M_CXGBE, M_ZERO | M_WAITOK); 1358 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1359 M_CXGBE, M_ZERO | M_WAITOK); 1360 #endif 1361 1362 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1363 M_ZERO | M_WAITOK); 1364 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1365 M_ZERO | M_WAITOK); 1366 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1367 M_ZERO | M_WAITOK); 1368 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1369 M_ZERO | M_WAITOK); 1370 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1371 M_ZERO | M_WAITOK); 1372 1373 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1374 M_ZERO | M_WAITOK); 1375 1376 t4_init_l2t(sc, M_WAITOK); 1377 t4_init_smt(sc, M_WAITOK); 1378 t4_init_tx_sched(sc); 1379 t4_init_atid_table(sc); 1380 #ifdef RATELIMIT 1381 t4_init_etid_table(sc); 1382 #endif 1383 #ifdef INET6 1384 t4_init_clip_table(sc); 1385 #endif 1386 if (sc->vres.key.size != 0) 1387 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1388 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1389 1390 /* 1391 * Second pass over the ports. This time we know the number of rx and 1392 * tx queues that each port should get. 1393 */ 1394 rqidx = tqidx = 0; 1395 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1396 ofld_tqidx = 0; 1397 #endif 1398 #ifdef TCP_OFFLOAD 1399 ofld_rqidx = 0; 1400 #endif 1401 #ifdef DEV_NETMAP 1402 nm_rqidx = nm_tqidx = 0; 1403 #endif 1404 for_each_port(sc, i) { 1405 struct port_info *pi = sc->port[i]; 1406 struct vi_info *vi; 1407 1408 if (pi == NULL) 1409 continue; 1410 1411 pi->nvi = num_vis; 1412 for_each_vi(pi, j, vi) { 1413 vi->pi = pi; 1414 vi->adapter = sc; 1415 vi->qsize_rxq = t4_qsize_rxq; 1416 vi->qsize_txq = t4_qsize_txq; 1417 1418 vi->first_rxq = rqidx; 1419 vi->first_txq = tqidx; 1420 vi->tmr_idx = t4_tmr_idx; 1421 vi->pktc_idx = t4_pktc_idx; 1422 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1423 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1424 1425 rqidx += vi->nrxq; 1426 tqidx += vi->ntxq; 1427 1428 if (j == 0 && vi->ntxq > 1) 1429 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1430 else 1431 vi->rsrv_noflowq = 0; 1432 1433 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1434 vi->first_ofld_txq = ofld_tqidx; 1435 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1436 ofld_tqidx += vi->nofldtxq; 1437 #endif 1438 #ifdef TCP_OFFLOAD 1439 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1440 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1441 vi->first_ofld_rxq = ofld_rqidx; 1442 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1443 1444 ofld_rqidx += vi->nofldrxq; 1445 #endif 1446 #ifdef DEV_NETMAP 1447 vi->first_nm_rxq = nm_rqidx; 1448 vi->first_nm_txq = nm_tqidx; 1449 if (j == 0) { 1450 vi->nnmrxq = iaq.nnmrxq; 1451 vi->nnmtxq = iaq.nnmtxq; 1452 } else { 1453 vi->nnmrxq = iaq.nnmrxq_vi; 1454 vi->nnmtxq = iaq.nnmtxq_vi; 1455 } 1456 nm_rqidx += vi->nnmrxq; 1457 nm_tqidx += vi->nnmtxq; 1458 #endif 1459 } 1460 } 1461 1462 rc = t4_setup_intr_handlers(sc); 1463 if (rc != 0) { 1464 device_printf(dev, 1465 "failed to setup interrupt handlers: %d\n", rc); 1466 goto done; 1467 } 1468 1469 rc = bus_generic_probe(dev); 1470 if (rc != 0) { 1471 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1472 goto done; 1473 } 1474 1475 /* 1476 * Ensure thread-safe mailbox access (in debug builds). 1477 * 1478 * So far this was the only thread accessing the mailbox but various 1479 * ifnets and sysctls are about to be created and their handlers/ioctls 1480 * will access the mailbox from different threads. 1481 */ 1482 sc->flags |= CHK_MBOX_ACCESS; 1483 1484 rc = bus_generic_attach(dev); 1485 if (rc != 0) { 1486 device_printf(dev, 1487 "failed to attach all child ports: %d\n", rc); 1488 goto done; 1489 } 1490 1491 device_printf(dev, 1492 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1493 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1494 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1495 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1496 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1497 1498 t4_set_desc(sc); 1499 1500 notify_siblings(dev, 0); 1501 1502 done: 1503 if (rc != 0 && sc->cdev) { 1504 /* cdev was created and so cxgbetool works; recover that way. */ 1505 device_printf(dev, 1506 "error during attach, adapter is now in recovery mode.\n"); 1507 rc = 0; 1508 } 1509 1510 if (rc != 0) 1511 t4_detach_common(dev); 1512 else 1513 t4_sysctls(sc); 1514 1515 return (rc); 1516 } 1517 1518 static int 1519 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen) 1520 { 1521 struct adapter *sc; 1522 struct port_info *pi; 1523 int i; 1524 1525 sc = device_get_softc(bus); 1526 buf[0] = '\0'; 1527 for_each_port(sc, i) { 1528 pi = sc->port[i]; 1529 if (pi != NULL && pi->dev == dev) { 1530 snprintf(buf, buflen, "port=%d", pi->port_id); 1531 break; 1532 } 1533 } 1534 return (0); 1535 } 1536 1537 static int 1538 t4_ready(device_t dev) 1539 { 1540 struct adapter *sc; 1541 1542 sc = device_get_softc(dev); 1543 if (sc->flags & FW_OK) 1544 return (0); 1545 return (ENXIO); 1546 } 1547 1548 static int 1549 t4_read_port_device(device_t dev, int port, device_t *child) 1550 { 1551 struct adapter *sc; 1552 struct port_info *pi; 1553 1554 sc = device_get_softc(dev); 1555 if (port < 0 || port >= MAX_NPORTS) 1556 return (EINVAL); 1557 pi = sc->port[port]; 1558 if (pi == NULL || pi->dev == NULL) 1559 return (ENXIO); 1560 *child = pi->dev; 1561 return (0); 1562 } 1563 1564 static int 1565 notify_siblings(device_t dev, int detaching) 1566 { 1567 device_t sibling; 1568 int error, i; 1569 1570 error = 0; 1571 for (i = 0; i < PCI_FUNCMAX; i++) { 1572 if (i == pci_get_function(dev)) 1573 continue; 1574 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1575 pci_get_slot(dev), i); 1576 if (sibling == NULL || !device_is_attached(sibling)) 1577 continue; 1578 if (detaching) 1579 error = T4_DETACH_CHILD(sibling); 1580 else 1581 (void)T4_ATTACH_CHILD(sibling); 1582 if (error) 1583 break; 1584 } 1585 return (error); 1586 } 1587 1588 /* 1589 * Idempotent 1590 */ 1591 static int 1592 t4_detach(device_t dev) 1593 { 1594 struct adapter *sc; 1595 int rc; 1596 1597 sc = device_get_softc(dev); 1598 1599 rc = notify_siblings(dev, 1); 1600 if (rc) { 1601 device_printf(dev, 1602 "failed to detach sibling devices: %d\n", rc); 1603 return (rc); 1604 } 1605 1606 return (t4_detach_common(dev)); 1607 } 1608 1609 int 1610 t4_detach_common(device_t dev) 1611 { 1612 struct adapter *sc; 1613 struct port_info *pi; 1614 int i, rc; 1615 1616 sc = device_get_softc(dev); 1617 1618 if (sc->cdev) { 1619 destroy_dev(sc->cdev); 1620 sc->cdev = NULL; 1621 } 1622 1623 sx_xlock(&t4_list_lock); 1624 SLIST_REMOVE(&t4_list, sc, adapter, link); 1625 sx_xunlock(&t4_list_lock); 1626 1627 sc->flags &= ~CHK_MBOX_ACCESS; 1628 if (sc->flags & FULL_INIT_DONE) { 1629 if (!(sc->flags & IS_VF)) 1630 t4_intr_disable(sc); 1631 } 1632 1633 if (device_is_attached(dev)) { 1634 rc = bus_generic_detach(dev); 1635 if (rc) { 1636 device_printf(dev, 1637 "failed to detach child devices: %d\n", rc); 1638 return (rc); 1639 } 1640 } 1641 1642 #ifdef TCP_OFFLOAD 1643 taskqueue_drain(taskqueue_thread, &sc->async_event_task); 1644 #endif 1645 1646 for (i = 0; i < sc->intr_count; i++) 1647 t4_free_irq(sc, &sc->irq[i]); 1648 1649 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1650 t4_free_tx_sched(sc); 1651 1652 for (i = 0; i < MAX_NPORTS; i++) { 1653 pi = sc->port[i]; 1654 if (pi) { 1655 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1656 if (pi->dev) 1657 device_delete_child(dev, pi->dev); 1658 1659 mtx_destroy(&pi->pi_lock); 1660 free(pi->vi, M_CXGBE); 1661 free(pi, M_CXGBE); 1662 } 1663 } 1664 1665 device_delete_children(dev); 1666 1667 if (sc->flags & FULL_INIT_DONE) 1668 adapter_full_uninit(sc); 1669 1670 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1671 t4_fw_bye(sc, sc->mbox); 1672 1673 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1674 pci_release_msi(dev); 1675 1676 if (sc->regs_res) 1677 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1678 sc->regs_res); 1679 1680 if (sc->udbs_res) 1681 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1682 sc->udbs_res); 1683 1684 if (sc->msix_res) 1685 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1686 sc->msix_res); 1687 1688 if (sc->l2t) 1689 t4_free_l2t(sc->l2t); 1690 if (sc->smt) 1691 t4_free_smt(sc->smt); 1692 t4_free_atid_table(sc); 1693 #ifdef RATELIMIT 1694 t4_free_etid_table(sc); 1695 #endif 1696 if (sc->key_map) 1697 vmem_destroy(sc->key_map); 1698 #ifdef INET6 1699 t4_destroy_clip_table(sc); 1700 #endif 1701 1702 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1703 free(sc->sge.ofld_txq, M_CXGBE); 1704 #endif 1705 #ifdef TCP_OFFLOAD 1706 free(sc->sge.ofld_rxq, M_CXGBE); 1707 #endif 1708 #ifdef DEV_NETMAP 1709 free(sc->sge.nm_rxq, M_CXGBE); 1710 free(sc->sge.nm_txq, M_CXGBE); 1711 #endif 1712 free(sc->irq, M_CXGBE); 1713 free(sc->sge.rxq, M_CXGBE); 1714 free(sc->sge.txq, M_CXGBE); 1715 free(sc->sge.ctrlq, M_CXGBE); 1716 free(sc->sge.iqmap, M_CXGBE); 1717 free(sc->sge.eqmap, M_CXGBE); 1718 free(sc->tids.ftid_tab, M_CXGBE); 1719 free(sc->tids.hpftid_tab, M_CXGBE); 1720 free_hftid_hash(&sc->tids); 1721 free(sc->tids.tid_tab, M_CXGBE); 1722 free(sc->tt.tls_rx_ports, M_CXGBE); 1723 t4_destroy_dma_tag(sc); 1724 1725 callout_drain(&sc->ktls_tick); 1726 callout_drain(&sc->sfl_callout); 1727 if (mtx_initialized(&sc->tids.ftid_lock)) { 1728 mtx_destroy(&sc->tids.ftid_lock); 1729 cv_destroy(&sc->tids.ftid_cv); 1730 } 1731 if (mtx_initialized(&sc->tids.atid_lock)) 1732 mtx_destroy(&sc->tids.atid_lock); 1733 if (mtx_initialized(&sc->ifp_lock)) 1734 mtx_destroy(&sc->ifp_lock); 1735 1736 if (rw_initialized(&sc->policy_lock)) { 1737 rw_destroy(&sc->policy_lock); 1738 #ifdef TCP_OFFLOAD 1739 if (sc->policy != NULL) 1740 free_offload_policy(sc->policy); 1741 #endif 1742 } 1743 1744 for (i = 0; i < NUM_MEMWIN; i++) { 1745 struct memwin *mw = &sc->memwin[i]; 1746 1747 if (rw_initialized(&mw->mw_lock)) 1748 rw_destroy(&mw->mw_lock); 1749 } 1750 1751 mtx_destroy(&sc->sfl_lock); 1752 mtx_destroy(&sc->reg_lock); 1753 mtx_destroy(&sc->sc_lock); 1754 1755 bzero(sc, sizeof(*sc)); 1756 1757 return (0); 1758 } 1759 1760 static int 1761 cxgbe_probe(device_t dev) 1762 { 1763 char buf[128]; 1764 struct port_info *pi = device_get_softc(dev); 1765 1766 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1767 device_set_desc_copy(dev, buf); 1768 1769 return (BUS_PROBE_DEFAULT); 1770 } 1771 1772 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1773 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1774 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 1775 IFCAP_HWRXTSTMP | IFCAP_NOMAP) 1776 #define T4_CAP_ENABLE (T4_CAP) 1777 1778 static int 1779 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1780 { 1781 struct ifnet *ifp; 1782 struct sbuf *sb; 1783 struct pfil_head_args pa; 1784 struct adapter *sc = vi->adapter; 1785 1786 vi->xact_addr_filt = -1; 1787 callout_init(&vi->tick, 1); 1788 if (sc->flags & IS_VF || t4_tx_vm_wr != 0) 1789 vi->flags |= TX_USES_VM_WR; 1790 1791 /* Allocate an ifnet and set it up */ 1792 ifp = if_alloc_dev(IFT_ETHER, dev); 1793 if (ifp == NULL) { 1794 device_printf(dev, "Cannot allocate ifnet\n"); 1795 return (ENOMEM); 1796 } 1797 vi->ifp = ifp; 1798 ifp->if_softc = vi; 1799 1800 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1801 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1802 1803 ifp->if_init = cxgbe_init; 1804 ifp->if_ioctl = cxgbe_ioctl; 1805 ifp->if_transmit = cxgbe_transmit; 1806 ifp->if_qflush = cxgbe_qflush; 1807 ifp->if_get_counter = cxgbe_get_counter; 1808 #if defined(KERN_TLS) || defined(RATELIMIT) 1809 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 1810 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify; 1811 ifp->if_snd_tag_query = cxgbe_snd_tag_query; 1812 ifp->if_snd_tag_free = cxgbe_snd_tag_free; 1813 #endif 1814 #ifdef RATELIMIT 1815 ifp->if_ratelimit_query = cxgbe_ratelimit_query; 1816 #endif 1817 1818 ifp->if_capabilities = T4_CAP; 1819 ifp->if_capenable = T4_CAP_ENABLE; 1820 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1821 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1822 if (chip_id(sc) >= CHELSIO_T6) { 1823 ifp->if_capabilities |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 1824 ifp->if_capenable |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 1825 ifp->if_hwassist |= CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 1826 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 1827 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN; 1828 } 1829 1830 #ifdef TCP_OFFLOAD 1831 if (vi->nofldrxq != 0 && (sc->flags & KERN_TLS_OK) == 0) 1832 ifp->if_capabilities |= IFCAP_TOE; 1833 #endif 1834 #ifdef RATELIMIT 1835 if (is_ethoffload(sc) && vi->nofldtxq != 0) { 1836 ifp->if_capabilities |= IFCAP_TXRTLMT; 1837 ifp->if_capenable |= IFCAP_TXRTLMT; 1838 } 1839 #endif 1840 1841 ifp->if_hw_tsomax = IP_MAXPACKET; 1842 if (vi->flags & TX_USES_VM_WR) 1843 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_VM_TSO; 1844 else 1845 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 1846 #ifdef RATELIMIT 1847 if (is_ethoffload(sc) && vi->nofldtxq != 0) 1848 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO; 1849 #endif 1850 ifp->if_hw_tsomaxsegsize = 65536; 1851 #ifdef KERN_TLS 1852 if (sc->flags & KERN_TLS_OK) { 1853 ifp->if_capabilities |= IFCAP_TXTLS; 1854 ifp->if_capenable |= IFCAP_TXTLS; 1855 } 1856 #endif 1857 1858 ether_ifattach(ifp, vi->hw_addr); 1859 #ifdef DEV_NETMAP 1860 if (vi->nnmrxq != 0) 1861 cxgbe_nm_attach(vi); 1862 #endif 1863 sb = sbuf_new_auto(); 1864 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1865 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1866 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 1867 case IFCAP_TOE: 1868 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 1869 break; 1870 case IFCAP_TOE | IFCAP_TXRTLMT: 1871 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 1872 break; 1873 case IFCAP_TXRTLMT: 1874 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 1875 break; 1876 } 1877 #endif 1878 #ifdef TCP_OFFLOAD 1879 if (ifp->if_capabilities & IFCAP_TOE) 1880 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 1881 #endif 1882 #ifdef DEV_NETMAP 1883 if (ifp->if_capabilities & IFCAP_NETMAP) 1884 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1885 vi->nnmtxq, vi->nnmrxq); 1886 #endif 1887 sbuf_finish(sb); 1888 device_printf(dev, "%s\n", sbuf_data(sb)); 1889 sbuf_delete(sb); 1890 1891 vi_sysctls(vi); 1892 1893 pa.pa_version = PFIL_VERSION; 1894 pa.pa_flags = PFIL_IN; 1895 pa.pa_type = PFIL_TYPE_ETHERNET; 1896 pa.pa_headname = ifp->if_xname; 1897 vi->pfil = pfil_head_register(&pa); 1898 1899 return (0); 1900 } 1901 1902 static int 1903 cxgbe_attach(device_t dev) 1904 { 1905 struct port_info *pi = device_get_softc(dev); 1906 struct adapter *sc = pi->adapter; 1907 struct vi_info *vi; 1908 int i, rc; 1909 1910 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1911 1912 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1913 if (rc) 1914 return (rc); 1915 1916 for_each_vi(pi, i, vi) { 1917 if (i == 0) 1918 continue; 1919 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1920 if (vi->dev == NULL) { 1921 device_printf(dev, "failed to add VI %d\n", i); 1922 continue; 1923 } 1924 device_set_softc(vi->dev, vi); 1925 } 1926 1927 cxgbe_sysctls(pi); 1928 1929 bus_generic_attach(dev); 1930 1931 return (0); 1932 } 1933 1934 static void 1935 cxgbe_vi_detach(struct vi_info *vi) 1936 { 1937 struct ifnet *ifp = vi->ifp; 1938 1939 if (vi->pfil != NULL) { 1940 pfil_head_unregister(vi->pfil); 1941 vi->pfil = NULL; 1942 } 1943 1944 ether_ifdetach(ifp); 1945 1946 /* Let detach proceed even if these fail. */ 1947 #ifdef DEV_NETMAP 1948 if (ifp->if_capabilities & IFCAP_NETMAP) 1949 cxgbe_nm_detach(vi); 1950 #endif 1951 cxgbe_uninit_synchronized(vi); 1952 callout_drain(&vi->tick); 1953 vi_full_uninit(vi); 1954 1955 if_free(vi->ifp); 1956 vi->ifp = NULL; 1957 } 1958 1959 static int 1960 cxgbe_detach(device_t dev) 1961 { 1962 struct port_info *pi = device_get_softc(dev); 1963 struct adapter *sc = pi->adapter; 1964 int rc; 1965 1966 /* Detach the extra VIs first. */ 1967 rc = bus_generic_detach(dev); 1968 if (rc) 1969 return (rc); 1970 device_delete_children(dev); 1971 1972 doom_vi(sc, &pi->vi[0]); 1973 1974 if (pi->flags & HAS_TRACEQ) { 1975 sc->traceq = -1; /* cloner should not create ifnet */ 1976 t4_tracer_port_detach(sc); 1977 } 1978 1979 cxgbe_vi_detach(&pi->vi[0]); 1980 callout_drain(&pi->tick); 1981 ifmedia_removeall(&pi->media); 1982 1983 end_synchronized_op(sc, 0); 1984 1985 return (0); 1986 } 1987 1988 static void 1989 cxgbe_init(void *arg) 1990 { 1991 struct vi_info *vi = arg; 1992 struct adapter *sc = vi->adapter; 1993 1994 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1995 return; 1996 cxgbe_init_synchronized(vi); 1997 end_synchronized_op(sc, 0); 1998 } 1999 2000 static int 2001 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 2002 { 2003 int rc = 0, mtu, flags; 2004 struct vi_info *vi = ifp->if_softc; 2005 struct port_info *pi = vi->pi; 2006 struct adapter *sc = pi->adapter; 2007 struct ifreq *ifr = (struct ifreq *)data; 2008 uint32_t mask; 2009 2010 switch (cmd) { 2011 case SIOCSIFMTU: 2012 mtu = ifr->ifr_mtu; 2013 if (mtu < ETHERMIN || mtu > MAX_MTU) 2014 return (EINVAL); 2015 2016 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 2017 if (rc) 2018 return (rc); 2019 ifp->if_mtu = mtu; 2020 if (vi->flags & VI_INIT_DONE) { 2021 t4_update_fl_bufsize(ifp); 2022 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2023 rc = update_mac_settings(ifp, XGMAC_MTU); 2024 } 2025 end_synchronized_op(sc, 0); 2026 break; 2027 2028 case SIOCSIFFLAGS: 2029 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 2030 if (rc) 2031 return (rc); 2032 2033 if (ifp->if_flags & IFF_UP) { 2034 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2035 flags = vi->if_flags; 2036 if ((ifp->if_flags ^ flags) & 2037 (IFF_PROMISC | IFF_ALLMULTI)) { 2038 rc = update_mac_settings(ifp, 2039 XGMAC_PROMISC | XGMAC_ALLMULTI); 2040 } 2041 } else { 2042 rc = cxgbe_init_synchronized(vi); 2043 } 2044 vi->if_flags = ifp->if_flags; 2045 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2046 rc = cxgbe_uninit_synchronized(vi); 2047 } 2048 end_synchronized_op(sc, 0); 2049 break; 2050 2051 case SIOCADDMULTI: 2052 case SIOCDELMULTI: 2053 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 2054 if (rc) 2055 return (rc); 2056 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2057 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2058 end_synchronized_op(sc, 0); 2059 break; 2060 2061 case SIOCSIFCAP: 2062 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 2063 if (rc) 2064 return (rc); 2065 2066 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2067 if (mask & IFCAP_TXCSUM) { 2068 ifp->if_capenable ^= IFCAP_TXCSUM; 2069 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2070 2071 if (IFCAP_TSO4 & ifp->if_capenable && 2072 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2073 mask &= ~IFCAP_TSO4; 2074 ifp->if_capenable &= ~IFCAP_TSO4; 2075 if_printf(ifp, 2076 "tso4 disabled due to -txcsum.\n"); 2077 } 2078 } 2079 if (mask & IFCAP_TXCSUM_IPV6) { 2080 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 2081 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2082 2083 if (IFCAP_TSO6 & ifp->if_capenable && 2084 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2085 mask &= ~IFCAP_TSO6; 2086 ifp->if_capenable &= ~IFCAP_TSO6; 2087 if_printf(ifp, 2088 "tso6 disabled due to -txcsum6.\n"); 2089 } 2090 } 2091 if (mask & IFCAP_RXCSUM) 2092 ifp->if_capenable ^= IFCAP_RXCSUM; 2093 if (mask & IFCAP_RXCSUM_IPV6) 2094 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 2095 2096 /* 2097 * Note that we leave CSUM_TSO alone (it is always set). The 2098 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 2099 * sending a TSO request our way, so it's sufficient to toggle 2100 * IFCAP_TSOx only. 2101 */ 2102 if (mask & IFCAP_TSO4) { 2103 if (!(IFCAP_TSO4 & ifp->if_capenable) && 2104 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2105 if_printf(ifp, "enable txcsum first.\n"); 2106 rc = EAGAIN; 2107 goto fail; 2108 } 2109 ifp->if_capenable ^= IFCAP_TSO4; 2110 } 2111 if (mask & IFCAP_TSO6) { 2112 if (!(IFCAP_TSO6 & ifp->if_capenable) && 2113 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2114 if_printf(ifp, "enable txcsum6 first.\n"); 2115 rc = EAGAIN; 2116 goto fail; 2117 } 2118 ifp->if_capenable ^= IFCAP_TSO6; 2119 } 2120 if (mask & IFCAP_LRO) { 2121 #if defined(INET) || defined(INET6) 2122 int i; 2123 struct sge_rxq *rxq; 2124 2125 ifp->if_capenable ^= IFCAP_LRO; 2126 for_each_rxq(vi, i, rxq) { 2127 if (ifp->if_capenable & IFCAP_LRO) 2128 rxq->iq.flags |= IQ_LRO_ENABLED; 2129 else 2130 rxq->iq.flags &= ~IQ_LRO_ENABLED; 2131 } 2132 #endif 2133 } 2134 #ifdef TCP_OFFLOAD 2135 if (mask & IFCAP_TOE) { 2136 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 2137 2138 rc = toe_capability(vi, enable); 2139 if (rc != 0) 2140 goto fail; 2141 2142 ifp->if_capenable ^= mask; 2143 } 2144 #endif 2145 if (mask & IFCAP_VLAN_HWTAGGING) { 2146 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2147 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2148 rc = update_mac_settings(ifp, XGMAC_VLANEX); 2149 } 2150 if (mask & IFCAP_VLAN_MTU) { 2151 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2152 2153 /* Need to find out how to disable auto-mtu-inflation */ 2154 } 2155 if (mask & IFCAP_VLAN_HWTSO) 2156 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2157 if (mask & IFCAP_VLAN_HWCSUM) 2158 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2159 #ifdef RATELIMIT 2160 if (mask & IFCAP_TXRTLMT) 2161 ifp->if_capenable ^= IFCAP_TXRTLMT; 2162 #endif 2163 if (mask & IFCAP_HWRXTSTMP) { 2164 int i; 2165 struct sge_rxq *rxq; 2166 2167 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 2168 for_each_rxq(vi, i, rxq) { 2169 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 2170 rxq->iq.flags |= IQ_RX_TIMESTAMP; 2171 else 2172 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 2173 } 2174 } 2175 if (mask & IFCAP_NOMAP) 2176 ifp->if_capenable ^= IFCAP_NOMAP; 2177 2178 #ifdef KERN_TLS 2179 if (mask & IFCAP_TXTLS) 2180 ifp->if_capenable ^= (mask & IFCAP_TXTLS); 2181 #endif 2182 if (mask & IFCAP_VXLAN_HWCSUM) { 2183 ifp->if_capenable ^= IFCAP_VXLAN_HWCSUM; 2184 ifp->if_hwassist ^= CSUM_INNER_IP6_UDP | 2185 CSUM_INNER_IP6_TCP | CSUM_INNER_IP | 2186 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP; 2187 } 2188 if (mask & IFCAP_VXLAN_HWTSO) { 2189 ifp->if_capenable ^= IFCAP_VXLAN_HWTSO; 2190 ifp->if_hwassist ^= CSUM_INNER_IP6_TSO | 2191 CSUM_INNER_IP_TSO; 2192 } 2193 2194 #ifdef VLAN_CAPABILITIES 2195 VLAN_CAPABILITIES(ifp); 2196 #endif 2197 fail: 2198 end_synchronized_op(sc, 0); 2199 break; 2200 2201 case SIOCSIFMEDIA: 2202 case SIOCGIFMEDIA: 2203 case SIOCGIFXMEDIA: 2204 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 2205 break; 2206 2207 case SIOCGI2C: { 2208 struct ifi2creq i2c; 2209 2210 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 2211 if (rc != 0) 2212 break; 2213 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 2214 rc = EPERM; 2215 break; 2216 } 2217 if (i2c.len > sizeof(i2c.data)) { 2218 rc = EINVAL; 2219 break; 2220 } 2221 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 2222 if (rc) 2223 return (rc); 2224 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 2225 i2c.offset, i2c.len, &i2c.data[0]); 2226 end_synchronized_op(sc, 0); 2227 if (rc == 0) 2228 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 2229 break; 2230 } 2231 2232 default: 2233 rc = ether_ioctl(ifp, cmd, data); 2234 } 2235 2236 return (rc); 2237 } 2238 2239 static int 2240 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 2241 { 2242 struct vi_info *vi = ifp->if_softc; 2243 struct port_info *pi = vi->pi; 2244 struct adapter *sc; 2245 struct sge_txq *txq; 2246 void *items[1]; 2247 int rc; 2248 2249 M_ASSERTPKTHDR(m); 2250 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 2251 #if defined(KERN_TLS) || defined(RATELIMIT) 2252 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) 2253 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 2254 #endif 2255 2256 if (__predict_false(pi->link_cfg.link_ok == false)) { 2257 m_freem(m); 2258 return (ENETDOWN); 2259 } 2260 2261 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR); 2262 if (__predict_false(rc != 0)) { 2263 MPASS(m == NULL); /* was freed already */ 2264 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 2265 return (rc); 2266 } 2267 #ifdef RATELIMIT 2268 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) { 2269 if (m->m_pkthdr.snd_tag->type == IF_SND_TAG_TYPE_RATE_LIMIT) 2270 return (ethofld_transmit(ifp, m)); 2271 } 2272 #endif 2273 2274 /* Select a txq. */ 2275 sc = vi->adapter; 2276 txq = &sc->sge.txq[vi->first_txq]; 2277 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2278 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 2279 vi->rsrv_noflowq); 2280 2281 items[0] = m; 2282 rc = mp_ring_enqueue(txq->r, items, 1, 256); 2283 if (__predict_false(rc != 0)) 2284 m_freem(m); 2285 2286 return (rc); 2287 } 2288 2289 static void 2290 cxgbe_qflush(struct ifnet *ifp) 2291 { 2292 struct vi_info *vi = ifp->if_softc; 2293 struct sge_txq *txq; 2294 int i; 2295 2296 /* queues do not exist if !VI_INIT_DONE. */ 2297 if (vi->flags & VI_INIT_DONE) { 2298 for_each_txq(vi, i, txq) { 2299 TXQ_LOCK(txq); 2300 txq->eq.flags |= EQ_QFLUSH; 2301 TXQ_UNLOCK(txq); 2302 while (!mp_ring_is_idle(txq->r)) { 2303 mp_ring_check_drainage(txq->r, 4096); 2304 pause("qflush", 1); 2305 } 2306 TXQ_LOCK(txq); 2307 txq->eq.flags &= ~EQ_QFLUSH; 2308 TXQ_UNLOCK(txq); 2309 } 2310 } 2311 if_qflush(ifp); 2312 } 2313 2314 static uint64_t 2315 vi_get_counter(struct ifnet *ifp, ift_counter c) 2316 { 2317 struct vi_info *vi = ifp->if_softc; 2318 struct fw_vi_stats_vf *s = &vi->stats; 2319 2320 vi_refresh_stats(vi->adapter, vi); 2321 2322 switch (c) { 2323 case IFCOUNTER_IPACKETS: 2324 return (s->rx_bcast_frames + s->rx_mcast_frames + 2325 s->rx_ucast_frames); 2326 case IFCOUNTER_IERRORS: 2327 return (s->rx_err_frames); 2328 case IFCOUNTER_OPACKETS: 2329 return (s->tx_bcast_frames + s->tx_mcast_frames + 2330 s->tx_ucast_frames + s->tx_offload_frames); 2331 case IFCOUNTER_OERRORS: 2332 return (s->tx_drop_frames); 2333 case IFCOUNTER_IBYTES: 2334 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 2335 s->rx_ucast_bytes); 2336 case IFCOUNTER_OBYTES: 2337 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 2338 s->tx_ucast_bytes + s->tx_offload_bytes); 2339 case IFCOUNTER_IMCASTS: 2340 return (s->rx_mcast_frames); 2341 case IFCOUNTER_OMCASTS: 2342 return (s->tx_mcast_frames); 2343 case IFCOUNTER_OQDROPS: { 2344 uint64_t drops; 2345 2346 drops = 0; 2347 if (vi->flags & VI_INIT_DONE) { 2348 int i; 2349 struct sge_txq *txq; 2350 2351 for_each_txq(vi, i, txq) 2352 drops += counter_u64_fetch(txq->r->dropped); 2353 } 2354 2355 return (drops); 2356 2357 } 2358 2359 default: 2360 return (if_get_counter_default(ifp, c)); 2361 } 2362 } 2363 2364 uint64_t 2365 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2366 { 2367 struct vi_info *vi = ifp->if_softc; 2368 struct port_info *pi = vi->pi; 2369 struct adapter *sc = pi->adapter; 2370 struct port_stats *s = &pi->stats; 2371 2372 if (pi->nvi > 1 || sc->flags & IS_VF) 2373 return (vi_get_counter(ifp, c)); 2374 2375 cxgbe_refresh_stats(sc, pi); 2376 2377 switch (c) { 2378 case IFCOUNTER_IPACKETS: 2379 return (s->rx_frames); 2380 2381 case IFCOUNTER_IERRORS: 2382 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2383 s->rx_fcs_err + s->rx_len_err); 2384 2385 case IFCOUNTER_OPACKETS: 2386 return (s->tx_frames); 2387 2388 case IFCOUNTER_OERRORS: 2389 return (s->tx_error_frames); 2390 2391 case IFCOUNTER_IBYTES: 2392 return (s->rx_octets); 2393 2394 case IFCOUNTER_OBYTES: 2395 return (s->tx_octets); 2396 2397 case IFCOUNTER_IMCASTS: 2398 return (s->rx_mcast_frames); 2399 2400 case IFCOUNTER_OMCASTS: 2401 return (s->tx_mcast_frames); 2402 2403 case IFCOUNTER_IQDROPS: 2404 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2405 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2406 s->rx_trunc3 + pi->tnl_cong_drops); 2407 2408 case IFCOUNTER_OQDROPS: { 2409 uint64_t drops; 2410 2411 drops = s->tx_drop; 2412 if (vi->flags & VI_INIT_DONE) { 2413 int i; 2414 struct sge_txq *txq; 2415 2416 for_each_txq(vi, i, txq) 2417 drops += counter_u64_fetch(txq->r->dropped); 2418 } 2419 2420 return (drops); 2421 2422 } 2423 2424 default: 2425 return (if_get_counter_default(ifp, c)); 2426 } 2427 } 2428 2429 #if defined(KERN_TLS) || defined(RATELIMIT) 2430 static int 2431 cxgbe_snd_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params, 2432 struct m_snd_tag **pt) 2433 { 2434 int error; 2435 2436 switch (params->hdr.type) { 2437 #ifdef RATELIMIT 2438 case IF_SND_TAG_TYPE_RATE_LIMIT: 2439 error = cxgbe_rate_tag_alloc(ifp, params, pt); 2440 break; 2441 #endif 2442 #ifdef KERN_TLS 2443 case IF_SND_TAG_TYPE_TLS: 2444 error = cxgbe_tls_tag_alloc(ifp, params, pt); 2445 break; 2446 #endif 2447 default: 2448 error = EOPNOTSUPP; 2449 } 2450 return (error); 2451 } 2452 2453 static int 2454 cxgbe_snd_tag_modify(struct m_snd_tag *mst, 2455 union if_snd_tag_modify_params *params) 2456 { 2457 2458 switch (mst->type) { 2459 #ifdef RATELIMIT 2460 case IF_SND_TAG_TYPE_RATE_LIMIT: 2461 return (cxgbe_rate_tag_modify(mst, params)); 2462 #endif 2463 default: 2464 return (EOPNOTSUPP); 2465 } 2466 } 2467 2468 static int 2469 cxgbe_snd_tag_query(struct m_snd_tag *mst, 2470 union if_snd_tag_query_params *params) 2471 { 2472 2473 switch (mst->type) { 2474 #ifdef RATELIMIT 2475 case IF_SND_TAG_TYPE_RATE_LIMIT: 2476 return (cxgbe_rate_tag_query(mst, params)); 2477 #endif 2478 default: 2479 return (EOPNOTSUPP); 2480 } 2481 } 2482 2483 static void 2484 cxgbe_snd_tag_free(struct m_snd_tag *mst) 2485 { 2486 2487 switch (mst->type) { 2488 #ifdef RATELIMIT 2489 case IF_SND_TAG_TYPE_RATE_LIMIT: 2490 cxgbe_rate_tag_free(mst); 2491 return; 2492 #endif 2493 #ifdef KERN_TLS 2494 case IF_SND_TAG_TYPE_TLS: 2495 cxgbe_tls_tag_free(mst); 2496 return; 2497 #endif 2498 default: 2499 panic("shouldn't get here"); 2500 } 2501 } 2502 #endif 2503 2504 /* 2505 * The kernel picks a media from the list we had provided but we still validate 2506 * the requeste. 2507 */ 2508 int 2509 cxgbe_media_change(struct ifnet *ifp) 2510 { 2511 struct vi_info *vi = ifp->if_softc; 2512 struct port_info *pi = vi->pi; 2513 struct ifmedia *ifm = &pi->media; 2514 struct link_config *lc = &pi->link_cfg; 2515 struct adapter *sc = pi->adapter; 2516 int rc; 2517 2518 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2519 if (rc != 0) 2520 return (rc); 2521 PORT_LOCK(pi); 2522 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2523 /* ifconfig .. media autoselect */ 2524 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { 2525 rc = ENOTSUP; /* AN not supported by transceiver */ 2526 goto done; 2527 } 2528 lc->requested_aneg = AUTONEG_ENABLE; 2529 lc->requested_speed = 0; 2530 lc->requested_fc |= PAUSE_AUTONEG; 2531 } else { 2532 lc->requested_aneg = AUTONEG_DISABLE; 2533 lc->requested_speed = 2534 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2535 lc->requested_fc = 0; 2536 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2537 lc->requested_fc |= PAUSE_RX; 2538 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2539 lc->requested_fc |= PAUSE_TX; 2540 } 2541 if (pi->up_vis > 0) { 2542 fixup_link_config(pi); 2543 rc = apply_link_config(pi); 2544 } 2545 done: 2546 PORT_UNLOCK(pi); 2547 end_synchronized_op(sc, 0); 2548 return (rc); 2549 } 2550 2551 /* 2552 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2553 * given speed. 2554 */ 2555 static int 2556 port_mword(struct port_info *pi, uint32_t speed) 2557 { 2558 2559 MPASS(speed & M_FW_PORT_CAP32_SPEED); 2560 MPASS(powerof2(speed)); 2561 2562 switch(pi->port_type) { 2563 case FW_PORT_TYPE_BT_SGMII: 2564 case FW_PORT_TYPE_BT_XFI: 2565 case FW_PORT_TYPE_BT_XAUI: 2566 /* BaseT */ 2567 switch (speed) { 2568 case FW_PORT_CAP32_SPEED_100M: 2569 return (IFM_100_T); 2570 case FW_PORT_CAP32_SPEED_1G: 2571 return (IFM_1000_T); 2572 case FW_PORT_CAP32_SPEED_10G: 2573 return (IFM_10G_T); 2574 } 2575 break; 2576 case FW_PORT_TYPE_KX4: 2577 if (speed == FW_PORT_CAP32_SPEED_10G) 2578 return (IFM_10G_KX4); 2579 break; 2580 case FW_PORT_TYPE_CX4: 2581 if (speed == FW_PORT_CAP32_SPEED_10G) 2582 return (IFM_10G_CX4); 2583 break; 2584 case FW_PORT_TYPE_KX: 2585 if (speed == FW_PORT_CAP32_SPEED_1G) 2586 return (IFM_1000_KX); 2587 break; 2588 case FW_PORT_TYPE_KR: 2589 case FW_PORT_TYPE_BP_AP: 2590 case FW_PORT_TYPE_BP4_AP: 2591 case FW_PORT_TYPE_BP40_BA: 2592 case FW_PORT_TYPE_KR4_100G: 2593 case FW_PORT_TYPE_KR_SFP28: 2594 case FW_PORT_TYPE_KR_XLAUI: 2595 switch (speed) { 2596 case FW_PORT_CAP32_SPEED_1G: 2597 return (IFM_1000_KX); 2598 case FW_PORT_CAP32_SPEED_10G: 2599 return (IFM_10G_KR); 2600 case FW_PORT_CAP32_SPEED_25G: 2601 return (IFM_25G_KR); 2602 case FW_PORT_CAP32_SPEED_40G: 2603 return (IFM_40G_KR4); 2604 case FW_PORT_CAP32_SPEED_50G: 2605 return (IFM_50G_KR2); 2606 case FW_PORT_CAP32_SPEED_100G: 2607 return (IFM_100G_KR4); 2608 } 2609 break; 2610 case FW_PORT_TYPE_FIBER_XFI: 2611 case FW_PORT_TYPE_FIBER_XAUI: 2612 case FW_PORT_TYPE_SFP: 2613 case FW_PORT_TYPE_QSFP_10G: 2614 case FW_PORT_TYPE_QSA: 2615 case FW_PORT_TYPE_QSFP: 2616 case FW_PORT_TYPE_CR4_QSFP: 2617 case FW_PORT_TYPE_CR_QSFP: 2618 case FW_PORT_TYPE_CR2_QSFP: 2619 case FW_PORT_TYPE_SFP28: 2620 /* Pluggable transceiver */ 2621 switch (pi->mod_type) { 2622 case FW_PORT_MOD_TYPE_LR: 2623 switch (speed) { 2624 case FW_PORT_CAP32_SPEED_1G: 2625 return (IFM_1000_LX); 2626 case FW_PORT_CAP32_SPEED_10G: 2627 return (IFM_10G_LR); 2628 case FW_PORT_CAP32_SPEED_25G: 2629 return (IFM_25G_LR); 2630 case FW_PORT_CAP32_SPEED_40G: 2631 return (IFM_40G_LR4); 2632 case FW_PORT_CAP32_SPEED_50G: 2633 return (IFM_50G_LR2); 2634 case FW_PORT_CAP32_SPEED_100G: 2635 return (IFM_100G_LR4); 2636 } 2637 break; 2638 case FW_PORT_MOD_TYPE_SR: 2639 switch (speed) { 2640 case FW_PORT_CAP32_SPEED_1G: 2641 return (IFM_1000_SX); 2642 case FW_PORT_CAP32_SPEED_10G: 2643 return (IFM_10G_SR); 2644 case FW_PORT_CAP32_SPEED_25G: 2645 return (IFM_25G_SR); 2646 case FW_PORT_CAP32_SPEED_40G: 2647 return (IFM_40G_SR4); 2648 case FW_PORT_CAP32_SPEED_50G: 2649 return (IFM_50G_SR2); 2650 case FW_PORT_CAP32_SPEED_100G: 2651 return (IFM_100G_SR4); 2652 } 2653 break; 2654 case FW_PORT_MOD_TYPE_ER: 2655 if (speed == FW_PORT_CAP32_SPEED_10G) 2656 return (IFM_10G_ER); 2657 break; 2658 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2659 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2660 switch (speed) { 2661 case FW_PORT_CAP32_SPEED_1G: 2662 return (IFM_1000_CX); 2663 case FW_PORT_CAP32_SPEED_10G: 2664 return (IFM_10G_TWINAX); 2665 case FW_PORT_CAP32_SPEED_25G: 2666 return (IFM_25G_CR); 2667 case FW_PORT_CAP32_SPEED_40G: 2668 return (IFM_40G_CR4); 2669 case FW_PORT_CAP32_SPEED_50G: 2670 return (IFM_50G_CR2); 2671 case FW_PORT_CAP32_SPEED_100G: 2672 return (IFM_100G_CR4); 2673 } 2674 break; 2675 case FW_PORT_MOD_TYPE_LRM: 2676 if (speed == FW_PORT_CAP32_SPEED_10G) 2677 return (IFM_10G_LRM); 2678 break; 2679 case FW_PORT_MOD_TYPE_NA: 2680 MPASS(0); /* Not pluggable? */ 2681 /* fall throough */ 2682 case FW_PORT_MOD_TYPE_ERROR: 2683 case FW_PORT_MOD_TYPE_UNKNOWN: 2684 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2685 break; 2686 case FW_PORT_MOD_TYPE_NONE: 2687 return (IFM_NONE); 2688 } 2689 break; 2690 case FW_PORT_TYPE_NONE: 2691 return (IFM_NONE); 2692 } 2693 2694 return (IFM_UNKNOWN); 2695 } 2696 2697 void 2698 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2699 { 2700 struct vi_info *vi = ifp->if_softc; 2701 struct port_info *pi = vi->pi; 2702 struct adapter *sc = pi->adapter; 2703 struct link_config *lc = &pi->link_cfg; 2704 2705 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2706 return; 2707 PORT_LOCK(pi); 2708 2709 if (pi->up_vis == 0) { 2710 /* 2711 * If all the interfaces are administratively down the firmware 2712 * does not report transceiver changes. Refresh port info here 2713 * so that ifconfig displays accurate ifmedia at all times. 2714 * This is the only reason we have a synchronized op in this 2715 * function. Just PORT_LOCK would have been enough otherwise. 2716 */ 2717 t4_update_port_info(pi); 2718 build_medialist(pi); 2719 } 2720 2721 /* ifm_status */ 2722 ifmr->ifm_status = IFM_AVALID; 2723 if (lc->link_ok == false) 2724 goto done; 2725 ifmr->ifm_status |= IFM_ACTIVE; 2726 2727 /* ifm_active */ 2728 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2729 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2730 if (lc->fc & PAUSE_RX) 2731 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2732 if (lc->fc & PAUSE_TX) 2733 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2734 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 2735 done: 2736 PORT_UNLOCK(pi); 2737 end_synchronized_op(sc, 0); 2738 } 2739 2740 static int 2741 vcxgbe_probe(device_t dev) 2742 { 2743 char buf[128]; 2744 struct vi_info *vi = device_get_softc(dev); 2745 2746 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2747 vi - vi->pi->vi); 2748 device_set_desc_copy(dev, buf); 2749 2750 return (BUS_PROBE_DEFAULT); 2751 } 2752 2753 static int 2754 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2755 { 2756 int func, index, rc; 2757 uint32_t param, val; 2758 2759 ASSERT_SYNCHRONIZED_OP(sc); 2760 2761 index = vi - pi->vi; 2762 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2763 KASSERT(index < nitems(vi_mac_funcs), 2764 ("%s: VI %s doesn't have a MAC func", __func__, 2765 device_get_nameunit(vi->dev))); 2766 func = vi_mac_funcs[index]; 2767 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2768 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 2769 if (rc < 0) { 2770 device_printf(vi->dev, "failed to allocate virtual interface %d" 2771 "for port %d: %d\n", index, pi->port_id, -rc); 2772 return (-rc); 2773 } 2774 vi->viid = rc; 2775 2776 if (vi->rss_size == 1) { 2777 /* 2778 * This VI didn't get a slice of the RSS table. Reduce the 2779 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2780 * configuration file (nvi, rssnvi for this PF) if this is a 2781 * problem. 2782 */ 2783 device_printf(vi->dev, "RSS table not available.\n"); 2784 vi->rss_base = 0xffff; 2785 2786 return (0); 2787 } 2788 2789 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2790 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2791 V_FW_PARAMS_PARAM_YZ(vi->viid); 2792 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2793 if (rc) 2794 vi->rss_base = 0xffff; 2795 else { 2796 MPASS((val >> 16) == vi->rss_size); 2797 vi->rss_base = val & 0xffff; 2798 } 2799 2800 return (0); 2801 } 2802 2803 static int 2804 vcxgbe_attach(device_t dev) 2805 { 2806 struct vi_info *vi; 2807 struct port_info *pi; 2808 struct adapter *sc; 2809 int rc; 2810 2811 vi = device_get_softc(dev); 2812 pi = vi->pi; 2813 sc = pi->adapter; 2814 2815 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2816 if (rc) 2817 return (rc); 2818 rc = alloc_extra_vi(sc, pi, vi); 2819 end_synchronized_op(sc, 0); 2820 if (rc) 2821 return (rc); 2822 2823 rc = cxgbe_vi_attach(dev, vi); 2824 if (rc) { 2825 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2826 return (rc); 2827 } 2828 return (0); 2829 } 2830 2831 static int 2832 vcxgbe_detach(device_t dev) 2833 { 2834 struct vi_info *vi; 2835 struct adapter *sc; 2836 2837 vi = device_get_softc(dev); 2838 sc = vi->adapter; 2839 2840 doom_vi(sc, vi); 2841 2842 cxgbe_vi_detach(vi); 2843 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2844 2845 end_synchronized_op(sc, 0); 2846 2847 return (0); 2848 } 2849 2850 static struct callout fatal_callout; 2851 2852 static void 2853 delayed_panic(void *arg) 2854 { 2855 struct adapter *sc = arg; 2856 2857 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 2858 } 2859 2860 void 2861 t4_fatal_err(struct adapter *sc, bool fw_error) 2862 { 2863 2864 t4_shutdown_adapter(sc); 2865 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n", 2866 device_get_nameunit(sc->dev)); 2867 if (fw_error) { 2868 ASSERT_SYNCHRONIZED_OP(sc); 2869 sc->flags |= ADAP_ERR; 2870 } else { 2871 ADAPTER_LOCK(sc); 2872 sc->flags |= ADAP_ERR; 2873 ADAPTER_UNLOCK(sc); 2874 } 2875 #ifdef TCP_OFFLOAD 2876 taskqueue_enqueue(taskqueue_thread, &sc->async_event_task); 2877 #endif 2878 2879 if (t4_panic_on_fatal_err) { 2880 log(LOG_ALERT, "%s: panic on fatal error after 30s", 2881 device_get_nameunit(sc->dev)); 2882 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 2883 } 2884 } 2885 2886 void 2887 t4_add_adapter(struct adapter *sc) 2888 { 2889 sx_xlock(&t4_list_lock); 2890 SLIST_INSERT_HEAD(&t4_list, sc, link); 2891 sx_xunlock(&t4_list_lock); 2892 } 2893 2894 int 2895 t4_map_bars_0_and_4(struct adapter *sc) 2896 { 2897 sc->regs_rid = PCIR_BAR(0); 2898 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2899 &sc->regs_rid, RF_ACTIVE); 2900 if (sc->regs_res == NULL) { 2901 device_printf(sc->dev, "cannot map registers.\n"); 2902 return (ENXIO); 2903 } 2904 sc->bt = rman_get_bustag(sc->regs_res); 2905 sc->bh = rman_get_bushandle(sc->regs_res); 2906 sc->mmio_len = rman_get_size(sc->regs_res); 2907 setbit(&sc->doorbells, DOORBELL_KDB); 2908 2909 sc->msix_rid = PCIR_BAR(4); 2910 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2911 &sc->msix_rid, RF_ACTIVE); 2912 if (sc->msix_res == NULL) { 2913 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2914 return (ENXIO); 2915 } 2916 2917 return (0); 2918 } 2919 2920 int 2921 t4_map_bar_2(struct adapter *sc) 2922 { 2923 2924 /* 2925 * T4: only iWARP driver uses the userspace doorbells. There is no need 2926 * to map it if RDMA is disabled. 2927 */ 2928 if (is_t4(sc) && sc->rdmacaps == 0) 2929 return (0); 2930 2931 sc->udbs_rid = PCIR_BAR(2); 2932 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2933 &sc->udbs_rid, RF_ACTIVE); 2934 if (sc->udbs_res == NULL) { 2935 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2936 return (ENXIO); 2937 } 2938 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2939 2940 if (chip_id(sc) >= CHELSIO_T5) { 2941 setbit(&sc->doorbells, DOORBELL_UDB); 2942 #if defined(__i386__) || defined(__amd64__) 2943 if (t5_write_combine) { 2944 int rc, mode; 2945 2946 /* 2947 * Enable write combining on BAR2. This is the 2948 * userspace doorbell BAR and is split into 128B 2949 * (UDBS_SEG_SIZE) doorbell regions, each associated 2950 * with an egress queue. The first 64B has the doorbell 2951 * and the second 64B can be used to submit a tx work 2952 * request with an implicit doorbell. 2953 */ 2954 2955 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2956 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2957 if (rc == 0) { 2958 clrbit(&sc->doorbells, DOORBELL_UDB); 2959 setbit(&sc->doorbells, DOORBELL_WCWR); 2960 setbit(&sc->doorbells, DOORBELL_UDBWC); 2961 } else { 2962 device_printf(sc->dev, 2963 "couldn't enable write combining: %d\n", 2964 rc); 2965 } 2966 2967 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2968 t4_write_reg(sc, A_SGE_STAT_CFG, 2969 V_STATSOURCE_T5(7) | mode); 2970 } 2971 #endif 2972 } 2973 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2974 2975 return (0); 2976 } 2977 2978 struct memwin_init { 2979 uint32_t base; 2980 uint32_t aperture; 2981 }; 2982 2983 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2984 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2985 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2986 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2987 }; 2988 2989 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2990 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2991 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2992 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2993 }; 2994 2995 static void 2996 setup_memwin(struct adapter *sc) 2997 { 2998 const struct memwin_init *mw_init; 2999 struct memwin *mw; 3000 int i; 3001 uint32_t bar0; 3002 3003 if (is_t4(sc)) { 3004 /* 3005 * Read low 32b of bar0 indirectly via the hardware backdoor 3006 * mechanism. Works from within PCI passthrough environments 3007 * too, where rman_get_start() can return a different value. We 3008 * need to program the T4 memory window decoders with the actual 3009 * addresses that will be coming across the PCIe link. 3010 */ 3011 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 3012 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 3013 3014 mw_init = &t4_memwin[0]; 3015 } else { 3016 /* T5+ use the relative offset inside the PCIe BAR */ 3017 bar0 = 0; 3018 3019 mw_init = &t5_memwin[0]; 3020 } 3021 3022 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 3023 rw_init(&mw->mw_lock, "memory window access"); 3024 mw->mw_base = mw_init->base; 3025 mw->mw_aperture = mw_init->aperture; 3026 mw->mw_curpos = 0; 3027 t4_write_reg(sc, 3028 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 3029 (mw->mw_base + bar0) | V_BIR(0) | 3030 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 3031 rw_wlock(&mw->mw_lock); 3032 position_memwin(sc, i, 0); 3033 rw_wunlock(&mw->mw_lock); 3034 } 3035 3036 /* flush */ 3037 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 3038 } 3039 3040 /* 3041 * Positions the memory window at the given address in the card's address space. 3042 * There are some alignment requirements and the actual position may be at an 3043 * address prior to the requested address. mw->mw_curpos always has the actual 3044 * position of the window. 3045 */ 3046 static void 3047 position_memwin(struct adapter *sc, int idx, uint32_t addr) 3048 { 3049 struct memwin *mw; 3050 uint32_t pf; 3051 uint32_t reg; 3052 3053 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3054 mw = &sc->memwin[idx]; 3055 rw_assert(&mw->mw_lock, RA_WLOCKED); 3056 3057 if (is_t4(sc)) { 3058 pf = 0; 3059 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 3060 } else { 3061 pf = V_PFNUM(sc->pf); 3062 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 3063 } 3064 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 3065 t4_write_reg(sc, reg, mw->mw_curpos | pf); 3066 t4_read_reg(sc, reg); /* flush */ 3067 } 3068 3069 int 3070 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 3071 int len, int rw) 3072 { 3073 struct memwin *mw; 3074 uint32_t mw_end, v; 3075 3076 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3077 3078 /* Memory can only be accessed in naturally aligned 4 byte units */ 3079 if (addr & 3 || len & 3 || len <= 0) 3080 return (EINVAL); 3081 3082 mw = &sc->memwin[idx]; 3083 while (len > 0) { 3084 rw_rlock(&mw->mw_lock); 3085 mw_end = mw->mw_curpos + mw->mw_aperture; 3086 if (addr >= mw_end || addr < mw->mw_curpos) { 3087 /* Will need to reposition the window */ 3088 if (!rw_try_upgrade(&mw->mw_lock)) { 3089 rw_runlock(&mw->mw_lock); 3090 rw_wlock(&mw->mw_lock); 3091 } 3092 rw_assert(&mw->mw_lock, RA_WLOCKED); 3093 position_memwin(sc, idx, addr); 3094 rw_downgrade(&mw->mw_lock); 3095 mw_end = mw->mw_curpos + mw->mw_aperture; 3096 } 3097 rw_assert(&mw->mw_lock, RA_RLOCKED); 3098 while (addr < mw_end && len > 0) { 3099 if (rw == 0) { 3100 v = t4_read_reg(sc, mw->mw_base + addr - 3101 mw->mw_curpos); 3102 *val++ = le32toh(v); 3103 } else { 3104 v = *val++; 3105 t4_write_reg(sc, mw->mw_base + addr - 3106 mw->mw_curpos, htole32(v)); 3107 } 3108 addr += 4; 3109 len -= 4; 3110 } 3111 rw_runlock(&mw->mw_lock); 3112 } 3113 3114 return (0); 3115 } 3116 3117 static void 3118 t4_init_atid_table(struct adapter *sc) 3119 { 3120 struct tid_info *t; 3121 int i; 3122 3123 t = &sc->tids; 3124 if (t->natids == 0) 3125 return; 3126 3127 MPASS(t->atid_tab == NULL); 3128 3129 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 3130 M_ZERO | M_WAITOK); 3131 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 3132 t->afree = t->atid_tab; 3133 t->atids_in_use = 0; 3134 for (i = 1; i < t->natids; i++) 3135 t->atid_tab[i - 1].next = &t->atid_tab[i]; 3136 t->atid_tab[t->natids - 1].next = NULL; 3137 } 3138 3139 static void 3140 t4_free_atid_table(struct adapter *sc) 3141 { 3142 struct tid_info *t; 3143 3144 t = &sc->tids; 3145 3146 KASSERT(t->atids_in_use == 0, 3147 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 3148 3149 if (mtx_initialized(&t->atid_lock)) 3150 mtx_destroy(&t->atid_lock); 3151 free(t->atid_tab, M_CXGBE); 3152 t->atid_tab = NULL; 3153 } 3154 3155 int 3156 alloc_atid(struct adapter *sc, void *ctx) 3157 { 3158 struct tid_info *t = &sc->tids; 3159 int atid = -1; 3160 3161 mtx_lock(&t->atid_lock); 3162 if (t->afree) { 3163 union aopen_entry *p = t->afree; 3164 3165 atid = p - t->atid_tab; 3166 MPASS(atid <= M_TID_TID); 3167 t->afree = p->next; 3168 p->data = ctx; 3169 t->atids_in_use++; 3170 } 3171 mtx_unlock(&t->atid_lock); 3172 return (atid); 3173 } 3174 3175 void * 3176 lookup_atid(struct adapter *sc, int atid) 3177 { 3178 struct tid_info *t = &sc->tids; 3179 3180 return (t->atid_tab[atid].data); 3181 } 3182 3183 void 3184 free_atid(struct adapter *sc, int atid) 3185 { 3186 struct tid_info *t = &sc->tids; 3187 union aopen_entry *p = &t->atid_tab[atid]; 3188 3189 mtx_lock(&t->atid_lock); 3190 p->next = t->afree; 3191 t->afree = p; 3192 t->atids_in_use--; 3193 mtx_unlock(&t->atid_lock); 3194 } 3195 3196 static void 3197 queue_tid_release(struct adapter *sc, int tid) 3198 { 3199 3200 CXGBE_UNIMPLEMENTED("deferred tid release"); 3201 } 3202 3203 void 3204 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 3205 { 3206 struct wrqe *wr; 3207 struct cpl_tid_release *req; 3208 3209 wr = alloc_wrqe(sizeof(*req), ctrlq); 3210 if (wr == NULL) { 3211 queue_tid_release(sc, tid); /* defer */ 3212 return; 3213 } 3214 req = wrtod(wr); 3215 3216 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 3217 3218 t4_wrq_tx(sc, wr); 3219 } 3220 3221 static int 3222 t4_range_cmp(const void *a, const void *b) 3223 { 3224 return ((const struct t4_range *)a)->start - 3225 ((const struct t4_range *)b)->start; 3226 } 3227 3228 /* 3229 * Verify that the memory range specified by the addr/len pair is valid within 3230 * the card's address space. 3231 */ 3232 static int 3233 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 3234 { 3235 struct t4_range mem_ranges[4], *r, *next; 3236 uint32_t em, addr_len; 3237 int i, n, remaining; 3238 3239 /* Memory can only be accessed in naturally aligned 4 byte units */ 3240 if (addr & 3 || len & 3 || len == 0) 3241 return (EINVAL); 3242 3243 /* Enabled memories */ 3244 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3245 3246 r = &mem_ranges[0]; 3247 n = 0; 3248 bzero(r, sizeof(mem_ranges)); 3249 if (em & F_EDRAM0_ENABLE) { 3250 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3251 r->size = G_EDRAM0_SIZE(addr_len) << 20; 3252 if (r->size > 0) { 3253 r->start = G_EDRAM0_BASE(addr_len) << 20; 3254 if (addr >= r->start && 3255 addr + len <= r->start + r->size) 3256 return (0); 3257 r++; 3258 n++; 3259 } 3260 } 3261 if (em & F_EDRAM1_ENABLE) { 3262 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3263 r->size = G_EDRAM1_SIZE(addr_len) << 20; 3264 if (r->size > 0) { 3265 r->start = G_EDRAM1_BASE(addr_len) << 20; 3266 if (addr >= r->start && 3267 addr + len <= r->start + r->size) 3268 return (0); 3269 r++; 3270 n++; 3271 } 3272 } 3273 if (em & F_EXT_MEM_ENABLE) { 3274 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3275 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 3276 if (r->size > 0) { 3277 r->start = G_EXT_MEM_BASE(addr_len) << 20; 3278 if (addr >= r->start && 3279 addr + len <= r->start + r->size) 3280 return (0); 3281 r++; 3282 n++; 3283 } 3284 } 3285 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 3286 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3287 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 3288 if (r->size > 0) { 3289 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 3290 if (addr >= r->start && 3291 addr + len <= r->start + r->size) 3292 return (0); 3293 r++; 3294 n++; 3295 } 3296 } 3297 MPASS(n <= nitems(mem_ranges)); 3298 3299 if (n > 1) { 3300 /* Sort and merge the ranges. */ 3301 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 3302 3303 /* Start from index 0 and examine the next n - 1 entries. */ 3304 r = &mem_ranges[0]; 3305 for (remaining = n - 1; remaining > 0; remaining--, r++) { 3306 3307 MPASS(r->size > 0); /* r is a valid entry. */ 3308 next = r + 1; 3309 MPASS(next->size > 0); /* and so is the next one. */ 3310 3311 while (r->start + r->size >= next->start) { 3312 /* Merge the next one into the current entry. */ 3313 r->size = max(r->start + r->size, 3314 next->start + next->size) - r->start; 3315 n--; /* One fewer entry in total. */ 3316 if (--remaining == 0) 3317 goto done; /* short circuit */ 3318 next++; 3319 } 3320 if (next != r + 1) { 3321 /* 3322 * Some entries were merged into r and next 3323 * points to the first valid entry that couldn't 3324 * be merged. 3325 */ 3326 MPASS(next->size > 0); /* must be valid */ 3327 memcpy(r + 1, next, remaining * sizeof(*r)); 3328 #ifdef INVARIANTS 3329 /* 3330 * This so that the foo->size assertion in the 3331 * next iteration of the loop do the right 3332 * thing for entries that were pulled up and are 3333 * no longer valid. 3334 */ 3335 MPASS(n < nitems(mem_ranges)); 3336 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 3337 sizeof(struct t4_range)); 3338 #endif 3339 } 3340 } 3341 done: 3342 /* Done merging the ranges. */ 3343 MPASS(n > 0); 3344 r = &mem_ranges[0]; 3345 for (i = 0; i < n; i++, r++) { 3346 if (addr >= r->start && 3347 addr + len <= r->start + r->size) 3348 return (0); 3349 } 3350 } 3351 3352 return (EFAULT); 3353 } 3354 3355 static int 3356 fwmtype_to_hwmtype(int mtype) 3357 { 3358 3359 switch (mtype) { 3360 case FW_MEMTYPE_EDC0: 3361 return (MEM_EDC0); 3362 case FW_MEMTYPE_EDC1: 3363 return (MEM_EDC1); 3364 case FW_MEMTYPE_EXTMEM: 3365 return (MEM_MC0); 3366 case FW_MEMTYPE_EXTMEM1: 3367 return (MEM_MC1); 3368 default: 3369 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 3370 } 3371 } 3372 3373 /* 3374 * Verify that the memory range specified by the memtype/offset/len pair is 3375 * valid and lies entirely within the memtype specified. The global address of 3376 * the start of the range is returned in addr. 3377 */ 3378 static int 3379 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 3380 uint32_t *addr) 3381 { 3382 uint32_t em, addr_len, maddr; 3383 3384 /* Memory can only be accessed in naturally aligned 4 byte units */ 3385 if (off & 3 || len & 3 || len == 0) 3386 return (EINVAL); 3387 3388 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3389 switch (fwmtype_to_hwmtype(mtype)) { 3390 case MEM_EDC0: 3391 if (!(em & F_EDRAM0_ENABLE)) 3392 return (EINVAL); 3393 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3394 maddr = G_EDRAM0_BASE(addr_len) << 20; 3395 break; 3396 case MEM_EDC1: 3397 if (!(em & F_EDRAM1_ENABLE)) 3398 return (EINVAL); 3399 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3400 maddr = G_EDRAM1_BASE(addr_len) << 20; 3401 break; 3402 case MEM_MC: 3403 if (!(em & F_EXT_MEM_ENABLE)) 3404 return (EINVAL); 3405 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3406 maddr = G_EXT_MEM_BASE(addr_len) << 20; 3407 break; 3408 case MEM_MC1: 3409 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 3410 return (EINVAL); 3411 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3412 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 3413 break; 3414 default: 3415 return (EINVAL); 3416 } 3417 3418 *addr = maddr + off; /* global address */ 3419 return (validate_mem_range(sc, *addr, len)); 3420 } 3421 3422 static int 3423 fixup_devlog_params(struct adapter *sc) 3424 { 3425 struct devlog_params *dparams = &sc->params.devlog; 3426 int rc; 3427 3428 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 3429 dparams->size, &dparams->addr); 3430 3431 return (rc); 3432 } 3433 3434 static void 3435 update_nirq(struct intrs_and_queues *iaq, int nports) 3436 { 3437 3438 iaq->nirq = T4_EXTRA_INTR; 3439 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq); 3440 iaq->nirq += nports * iaq->nofldrxq; 3441 iaq->nirq += nports * (iaq->num_vis - 1) * 3442 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 3443 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 3444 } 3445 3446 /* 3447 * Adjust requirements to fit the number of interrupts available. 3448 */ 3449 static void 3450 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 3451 int navail) 3452 { 3453 int old_nirq; 3454 const int nports = sc->params.nports; 3455 3456 MPASS(nports > 0); 3457 MPASS(navail > 0); 3458 3459 bzero(iaq, sizeof(*iaq)); 3460 iaq->intr_type = itype; 3461 iaq->num_vis = t4_num_vis; 3462 iaq->ntxq = t4_ntxq; 3463 iaq->ntxq_vi = t4_ntxq_vi; 3464 iaq->nrxq = t4_nrxq; 3465 iaq->nrxq_vi = t4_nrxq_vi; 3466 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3467 if (is_offload(sc) || is_ethoffload(sc)) { 3468 iaq->nofldtxq = t4_nofldtxq; 3469 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3470 } 3471 #endif 3472 #ifdef TCP_OFFLOAD 3473 if (is_offload(sc)) { 3474 iaq->nofldrxq = t4_nofldrxq; 3475 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3476 } 3477 #endif 3478 #ifdef DEV_NETMAP 3479 if (t4_native_netmap & NN_MAIN_VI) { 3480 iaq->nnmtxq = t4_nnmtxq; 3481 iaq->nnmrxq = t4_nnmrxq; 3482 } 3483 if (t4_native_netmap & NN_EXTRA_VI) { 3484 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3485 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3486 } 3487 #endif 3488 3489 update_nirq(iaq, nports); 3490 if (iaq->nirq <= navail && 3491 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3492 /* 3493 * This is the normal case -- there are enough interrupts for 3494 * everything. 3495 */ 3496 goto done; 3497 } 3498 3499 /* 3500 * If extra VIs have been configured try reducing their count and see if 3501 * that works. 3502 */ 3503 while (iaq->num_vis > 1) { 3504 iaq->num_vis--; 3505 update_nirq(iaq, nports); 3506 if (iaq->nirq <= navail && 3507 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3508 device_printf(sc->dev, "virtual interfaces per port " 3509 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3510 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3511 "itype %d, navail %u, nirq %d.\n", 3512 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3513 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3514 itype, navail, iaq->nirq); 3515 goto done; 3516 } 3517 } 3518 3519 /* 3520 * Extra VIs will not be created. Log a message if they were requested. 3521 */ 3522 MPASS(iaq->num_vis == 1); 3523 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3524 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3525 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3526 if (iaq->num_vis != t4_num_vis) { 3527 device_printf(sc->dev, "extra virtual interfaces disabled. " 3528 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3529 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3530 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3531 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3532 } 3533 3534 /* 3535 * Keep reducing the number of NIC rx queues to the next lower power of 3536 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3537 * if that works. 3538 */ 3539 do { 3540 if (iaq->nrxq > 1) { 3541 do { 3542 iaq->nrxq--; 3543 } while (!powerof2(iaq->nrxq)); 3544 if (iaq->nnmrxq > iaq->nrxq) 3545 iaq->nnmrxq = iaq->nrxq; 3546 } 3547 if (iaq->nofldrxq > 1) 3548 iaq->nofldrxq >>= 1; 3549 3550 old_nirq = iaq->nirq; 3551 update_nirq(iaq, nports); 3552 if (iaq->nirq <= navail && 3553 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3554 device_printf(sc->dev, "running with reduced number of " 3555 "rx queues because of shortage of interrupts. " 3556 "nrxq=%u, nofldrxq=%u. " 3557 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3558 iaq->nofldrxq, itype, navail, iaq->nirq); 3559 goto done; 3560 } 3561 } while (old_nirq != iaq->nirq); 3562 3563 /* One interrupt for everything. Ugh. */ 3564 device_printf(sc->dev, "running with minimal number of queues. " 3565 "itype %d, navail %u.\n", itype, navail); 3566 iaq->nirq = 1; 3567 iaq->nrxq = 1; 3568 iaq->ntxq = 1; 3569 if (iaq->nofldrxq > 0) { 3570 iaq->nofldrxq = 1; 3571 iaq->nofldtxq = 1; 3572 } 3573 iaq->nnmtxq = 0; 3574 iaq->nnmrxq = 0; 3575 done: 3576 MPASS(iaq->num_vis > 0); 3577 if (iaq->num_vis > 1) { 3578 MPASS(iaq->nrxq_vi > 0); 3579 MPASS(iaq->ntxq_vi > 0); 3580 } 3581 MPASS(iaq->nirq > 0); 3582 MPASS(iaq->nrxq > 0); 3583 MPASS(iaq->ntxq > 0); 3584 if (itype == INTR_MSI) { 3585 MPASS(powerof2(iaq->nirq)); 3586 } 3587 } 3588 3589 static int 3590 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3591 { 3592 int rc, itype, navail, nalloc; 3593 3594 for (itype = INTR_MSIX; itype; itype >>= 1) { 3595 3596 if ((itype & t4_intr_types) == 0) 3597 continue; /* not allowed */ 3598 3599 if (itype == INTR_MSIX) 3600 navail = pci_msix_count(sc->dev); 3601 else if (itype == INTR_MSI) 3602 navail = pci_msi_count(sc->dev); 3603 else 3604 navail = 1; 3605 restart: 3606 if (navail == 0) 3607 continue; 3608 3609 calculate_iaq(sc, iaq, itype, navail); 3610 nalloc = iaq->nirq; 3611 rc = 0; 3612 if (itype == INTR_MSIX) 3613 rc = pci_alloc_msix(sc->dev, &nalloc); 3614 else if (itype == INTR_MSI) 3615 rc = pci_alloc_msi(sc->dev, &nalloc); 3616 3617 if (rc == 0 && nalloc > 0) { 3618 if (nalloc == iaq->nirq) 3619 return (0); 3620 3621 /* 3622 * Didn't get the number requested. Use whatever number 3623 * the kernel is willing to allocate. 3624 */ 3625 device_printf(sc->dev, "fewer vectors than requested, " 3626 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3627 itype, iaq->nirq, nalloc); 3628 pci_release_msi(sc->dev); 3629 navail = nalloc; 3630 goto restart; 3631 } 3632 3633 device_printf(sc->dev, 3634 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3635 itype, rc, iaq->nirq, nalloc); 3636 } 3637 3638 device_printf(sc->dev, 3639 "failed to find a usable interrupt type. " 3640 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3641 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3642 3643 return (ENXIO); 3644 } 3645 3646 #define FW_VERSION(chip) ( \ 3647 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3648 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3649 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3650 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3651 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3652 3653 /* Just enough of fw_hdr to cover all version info. */ 3654 struct fw_h { 3655 __u8 ver; 3656 __u8 chip; 3657 __be16 len512; 3658 __be32 fw_ver; 3659 __be32 tp_microcode_ver; 3660 __u8 intfver_nic; 3661 __u8 intfver_vnic; 3662 __u8 intfver_ofld; 3663 __u8 intfver_ri; 3664 __u8 intfver_iscsipdu; 3665 __u8 intfver_iscsi; 3666 __u8 intfver_fcoepdu; 3667 __u8 intfver_fcoe; 3668 }; 3669 /* Spot check a couple of fields. */ 3670 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 3671 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 3672 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 3673 3674 struct fw_info { 3675 uint8_t chip; 3676 char *kld_name; 3677 char *fw_mod_name; 3678 struct fw_h fw_h; 3679 } fw_info[] = { 3680 { 3681 .chip = CHELSIO_T4, 3682 .kld_name = "t4fw_cfg", 3683 .fw_mod_name = "t4fw", 3684 .fw_h = { 3685 .chip = FW_HDR_CHIP_T4, 3686 .fw_ver = htobe32(FW_VERSION(T4)), 3687 .intfver_nic = FW_INTFVER(T4, NIC), 3688 .intfver_vnic = FW_INTFVER(T4, VNIC), 3689 .intfver_ofld = FW_INTFVER(T4, OFLD), 3690 .intfver_ri = FW_INTFVER(T4, RI), 3691 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3692 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3693 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3694 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3695 }, 3696 }, { 3697 .chip = CHELSIO_T5, 3698 .kld_name = "t5fw_cfg", 3699 .fw_mod_name = "t5fw", 3700 .fw_h = { 3701 .chip = FW_HDR_CHIP_T5, 3702 .fw_ver = htobe32(FW_VERSION(T5)), 3703 .intfver_nic = FW_INTFVER(T5, NIC), 3704 .intfver_vnic = FW_INTFVER(T5, VNIC), 3705 .intfver_ofld = FW_INTFVER(T5, OFLD), 3706 .intfver_ri = FW_INTFVER(T5, RI), 3707 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3708 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3709 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3710 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3711 }, 3712 }, { 3713 .chip = CHELSIO_T6, 3714 .kld_name = "t6fw_cfg", 3715 .fw_mod_name = "t6fw", 3716 .fw_h = { 3717 .chip = FW_HDR_CHIP_T6, 3718 .fw_ver = htobe32(FW_VERSION(T6)), 3719 .intfver_nic = FW_INTFVER(T6, NIC), 3720 .intfver_vnic = FW_INTFVER(T6, VNIC), 3721 .intfver_ofld = FW_INTFVER(T6, OFLD), 3722 .intfver_ri = FW_INTFVER(T6, RI), 3723 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3724 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3725 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3726 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3727 }, 3728 } 3729 }; 3730 3731 static struct fw_info * 3732 find_fw_info(int chip) 3733 { 3734 int i; 3735 3736 for (i = 0; i < nitems(fw_info); i++) { 3737 if (fw_info[i].chip == chip) 3738 return (&fw_info[i]); 3739 } 3740 return (NULL); 3741 } 3742 3743 /* 3744 * Is the given firmware API compatible with the one the driver was compiled 3745 * with? 3746 */ 3747 static int 3748 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 3749 { 3750 3751 /* short circuit if it's the exact same firmware version */ 3752 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3753 return (1); 3754 3755 /* 3756 * XXX: Is this too conservative? Perhaps I should limit this to the 3757 * features that are supported in the driver. 3758 */ 3759 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3760 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3761 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3762 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3763 return (1); 3764 #undef SAME_INTF 3765 3766 return (0); 3767 } 3768 3769 static int 3770 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 3771 const struct firmware **fw) 3772 { 3773 struct fw_info *fw_info; 3774 3775 *dcfg = NULL; 3776 if (fw != NULL) 3777 *fw = NULL; 3778 3779 fw_info = find_fw_info(chip_id(sc)); 3780 if (fw_info == NULL) { 3781 device_printf(sc->dev, 3782 "unable to look up firmware information for chip %d.\n", 3783 chip_id(sc)); 3784 return (EINVAL); 3785 } 3786 3787 *dcfg = firmware_get(fw_info->kld_name); 3788 if (*dcfg != NULL) { 3789 if (fw != NULL) 3790 *fw = firmware_get(fw_info->fw_mod_name); 3791 return (0); 3792 } 3793 3794 return (ENOENT); 3795 } 3796 3797 static void 3798 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 3799 const struct firmware *fw) 3800 { 3801 3802 if (fw != NULL) 3803 firmware_put(fw, FIRMWARE_UNLOAD); 3804 if (dcfg != NULL) 3805 firmware_put(dcfg, FIRMWARE_UNLOAD); 3806 } 3807 3808 /* 3809 * Return values: 3810 * 0 means no firmware install attempted. 3811 * ERESTART means a firmware install was attempted and was successful. 3812 * +ve errno means a firmware install was attempted but failed. 3813 */ 3814 static int 3815 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 3816 const struct fw_h *drv_fw, const char *reason, int *already) 3817 { 3818 const struct firmware *cfg, *fw; 3819 const uint32_t c = be32toh(card_fw->fw_ver); 3820 uint32_t d, k; 3821 int rc, fw_install; 3822 struct fw_h bundled_fw; 3823 bool load_attempted; 3824 3825 cfg = fw = NULL; 3826 load_attempted = false; 3827 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 3828 3829 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 3830 if (t4_fw_install < 0) { 3831 rc = load_fw_module(sc, &cfg, &fw); 3832 if (rc != 0 || fw == NULL) { 3833 device_printf(sc->dev, 3834 "failed to load firmware module: %d. cfg %p, fw %p;" 3835 " will use compiled-in firmware version for" 3836 "hw.cxgbe.fw_install checks.\n", 3837 rc, cfg, fw); 3838 } else { 3839 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 3840 } 3841 load_attempted = true; 3842 } 3843 d = be32toh(bundled_fw.fw_ver); 3844 3845 if (reason != NULL) 3846 goto install; 3847 3848 if ((sc->flags & FW_OK) == 0) { 3849 3850 if (c == 0xffffffff) { 3851 reason = "missing"; 3852 goto install; 3853 } 3854 3855 rc = 0; 3856 goto done; 3857 } 3858 3859 if (!fw_compatible(card_fw, &bundled_fw)) { 3860 reason = "incompatible or unusable"; 3861 goto install; 3862 } 3863 3864 if (d > c) { 3865 reason = "older than the version bundled with this driver"; 3866 goto install; 3867 } 3868 3869 if (fw_install == 2 && d != c) { 3870 reason = "different than the version bundled with this driver"; 3871 goto install; 3872 } 3873 3874 /* No reason to do anything to the firmware already on the card. */ 3875 rc = 0; 3876 goto done; 3877 3878 install: 3879 rc = 0; 3880 if ((*already)++) 3881 goto done; 3882 3883 if (fw_install == 0) { 3884 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3885 "but the driver is prohibited from installing a firmware " 3886 "on the card.\n", 3887 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3888 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3889 3890 goto done; 3891 } 3892 3893 /* 3894 * We'll attempt to install a firmware. Load the module first (if it 3895 * hasn't been loaded already). 3896 */ 3897 if (!load_attempted) { 3898 rc = load_fw_module(sc, &cfg, &fw); 3899 if (rc != 0 || fw == NULL) { 3900 device_printf(sc->dev, 3901 "failed to load firmware module: %d. cfg %p, fw %p\n", 3902 rc, cfg, fw); 3903 /* carry on */ 3904 } 3905 } 3906 if (fw == NULL) { 3907 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3908 "but the driver cannot take corrective action because it " 3909 "is unable to load the firmware module.\n", 3910 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3911 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3912 rc = sc->flags & FW_OK ? 0 : ENOENT; 3913 goto done; 3914 } 3915 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 3916 if (k != d) { 3917 MPASS(t4_fw_install > 0); 3918 device_printf(sc->dev, 3919 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 3920 "expecting (%u.%u.%u.%u) and will not be used.\n", 3921 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3922 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 3923 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3924 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3925 rc = sc->flags & FW_OK ? 0 : EINVAL; 3926 goto done; 3927 } 3928 3929 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3930 "installing firmware %u.%u.%u.%u on card.\n", 3931 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3932 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3933 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3934 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3935 3936 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3937 if (rc != 0) { 3938 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 3939 } else { 3940 /* Installed successfully, update the cached header too. */ 3941 rc = ERESTART; 3942 memcpy(card_fw, fw->data, sizeof(*card_fw)); 3943 } 3944 done: 3945 unload_fw_module(sc, cfg, fw); 3946 3947 return (rc); 3948 } 3949 3950 /* 3951 * Establish contact with the firmware and attempt to become the master driver. 3952 * 3953 * A firmware will be installed to the card if needed (if the driver is allowed 3954 * to do so). 3955 */ 3956 static int 3957 contact_firmware(struct adapter *sc) 3958 { 3959 int rc, already = 0; 3960 enum dev_state state; 3961 struct fw_info *fw_info; 3962 struct fw_hdr *card_fw; /* fw on the card */ 3963 const struct fw_h *drv_fw; 3964 3965 fw_info = find_fw_info(chip_id(sc)); 3966 if (fw_info == NULL) { 3967 device_printf(sc->dev, 3968 "unable to look up firmware information for chip %d.\n", 3969 chip_id(sc)); 3970 return (EINVAL); 3971 } 3972 drv_fw = &fw_info->fw_h; 3973 3974 /* Read the header of the firmware on the card */ 3975 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3976 restart: 3977 rc = -t4_get_fw_hdr(sc, card_fw); 3978 if (rc != 0) { 3979 device_printf(sc->dev, 3980 "unable to read firmware header from card's flash: %d\n", 3981 rc); 3982 goto done; 3983 } 3984 3985 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 3986 &already); 3987 if (rc == ERESTART) 3988 goto restart; 3989 if (rc != 0) 3990 goto done; 3991 3992 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3993 if (rc < 0 || state == DEV_STATE_ERR) { 3994 rc = -rc; 3995 device_printf(sc->dev, 3996 "failed to connect to the firmware: %d, %d. " 3997 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3998 #if 0 3999 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4000 "not responding properly to HELLO", &already) == ERESTART) 4001 goto restart; 4002 #endif 4003 goto done; 4004 } 4005 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 4006 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 4007 4008 if (rc == sc->pf) { 4009 sc->flags |= MASTER_PF; 4010 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4011 NULL, &already); 4012 if (rc == ERESTART) 4013 rc = 0; 4014 else if (rc != 0) 4015 goto done; 4016 } else if (state == DEV_STATE_UNINIT) { 4017 /* 4018 * We didn't get to be the master so we definitely won't be 4019 * configuring the chip. It's a bug if someone else hasn't 4020 * configured it already. 4021 */ 4022 device_printf(sc->dev, "couldn't be master(%d), " 4023 "device not already initialized either(%d). " 4024 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4025 rc = EPROTO; 4026 goto done; 4027 } else { 4028 /* 4029 * Some other PF is the master and has configured the chip. 4030 * This is allowed but untested. 4031 */ 4032 device_printf(sc->dev, "PF%d is master, device state %d. " 4033 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4034 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 4035 sc->cfcsum = 0; 4036 rc = 0; 4037 } 4038 done: 4039 if (rc != 0 && sc->flags & FW_OK) { 4040 t4_fw_bye(sc, sc->mbox); 4041 sc->flags &= ~FW_OK; 4042 } 4043 free(card_fw, M_CXGBE); 4044 return (rc); 4045 } 4046 4047 static int 4048 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 4049 uint32_t mtype, uint32_t moff) 4050 { 4051 struct fw_info *fw_info; 4052 const struct firmware *dcfg, *rcfg = NULL; 4053 const uint32_t *cfdata; 4054 uint32_t cflen, addr; 4055 int rc; 4056 4057 load_fw_module(sc, &dcfg, NULL); 4058 4059 /* Card specific interpretation of "default". */ 4060 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4061 if (pci_get_device(sc->dev) == 0x440a) 4062 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 4063 if (is_fpga(sc)) 4064 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 4065 } 4066 4067 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4068 if (dcfg == NULL) { 4069 device_printf(sc->dev, 4070 "KLD with default config is not available.\n"); 4071 rc = ENOENT; 4072 goto done; 4073 } 4074 cfdata = dcfg->data; 4075 cflen = dcfg->datasize & ~3; 4076 } else { 4077 char s[32]; 4078 4079 fw_info = find_fw_info(chip_id(sc)); 4080 if (fw_info == NULL) { 4081 device_printf(sc->dev, 4082 "unable to look up firmware information for chip %d.\n", 4083 chip_id(sc)); 4084 rc = EINVAL; 4085 goto done; 4086 } 4087 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 4088 4089 rcfg = firmware_get(s); 4090 if (rcfg == NULL) { 4091 device_printf(sc->dev, 4092 "unable to load module \"%s\" for configuration " 4093 "profile \"%s\".\n", s, cfg_file); 4094 rc = ENOENT; 4095 goto done; 4096 } 4097 cfdata = rcfg->data; 4098 cflen = rcfg->datasize & ~3; 4099 } 4100 4101 if (cflen > FLASH_CFG_MAX_SIZE) { 4102 device_printf(sc->dev, 4103 "config file too long (%d, max allowed is %d).\n", 4104 cflen, FLASH_CFG_MAX_SIZE); 4105 rc = EINVAL; 4106 goto done; 4107 } 4108 4109 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 4110 if (rc != 0) { 4111 device_printf(sc->dev, 4112 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 4113 __func__, mtype, moff, cflen, rc); 4114 rc = EINVAL; 4115 goto done; 4116 } 4117 write_via_memwin(sc, 2, addr, cfdata, cflen); 4118 done: 4119 if (rcfg != NULL) 4120 firmware_put(rcfg, FIRMWARE_UNLOAD); 4121 unload_fw_module(sc, dcfg, NULL); 4122 return (rc); 4123 } 4124 4125 struct caps_allowed { 4126 uint16_t nbmcaps; 4127 uint16_t linkcaps; 4128 uint16_t switchcaps; 4129 uint16_t niccaps; 4130 uint16_t toecaps; 4131 uint16_t rdmacaps; 4132 uint16_t cryptocaps; 4133 uint16_t iscsicaps; 4134 uint16_t fcoecaps; 4135 }; 4136 4137 #define FW_PARAM_DEV(param) \ 4138 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 4139 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 4140 #define FW_PARAM_PFVF(param) \ 4141 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 4142 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 4143 4144 /* 4145 * Provide a configuration profile to the firmware and have it initialize the 4146 * chip accordingly. This may involve uploading a configuration file to the 4147 * card. 4148 */ 4149 static int 4150 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 4151 const struct caps_allowed *caps_allowed) 4152 { 4153 int rc; 4154 struct fw_caps_config_cmd caps; 4155 uint32_t mtype, moff, finicsum, cfcsum, param, val; 4156 4157 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 4158 if (rc != 0) { 4159 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 4160 return (rc); 4161 } 4162 4163 bzero(&caps, sizeof(caps)); 4164 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4165 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4166 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 4167 mtype = 0; 4168 moff = 0; 4169 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4170 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 4171 mtype = FW_MEMTYPE_FLASH; 4172 moff = t4_flash_cfg_addr(sc); 4173 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4174 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4175 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4176 FW_LEN16(caps)); 4177 } else { 4178 /* 4179 * Ask the firmware where it wants us to upload the config file. 4180 */ 4181 param = FW_PARAM_DEV(CF); 4182 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4183 if (rc != 0) { 4184 /* No support for config file? Shouldn't happen. */ 4185 device_printf(sc->dev, 4186 "failed to query config file location: %d.\n", rc); 4187 goto done; 4188 } 4189 mtype = G_FW_PARAMS_PARAM_Y(val); 4190 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 4191 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4192 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4193 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4194 FW_LEN16(caps)); 4195 4196 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 4197 if (rc != 0) { 4198 device_printf(sc->dev, 4199 "failed to upload config file to card: %d.\n", rc); 4200 goto done; 4201 } 4202 } 4203 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4204 if (rc != 0) { 4205 device_printf(sc->dev, "failed to pre-process config file: %d " 4206 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 4207 goto done; 4208 } 4209 4210 finicsum = be32toh(caps.finicsum); 4211 cfcsum = be32toh(caps.cfcsum); /* actual */ 4212 if (finicsum != cfcsum) { 4213 device_printf(sc->dev, 4214 "WARNING: config file checksum mismatch: %08x %08x\n", 4215 finicsum, cfcsum); 4216 } 4217 sc->cfcsum = cfcsum; 4218 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 4219 4220 /* 4221 * Let the firmware know what features will (not) be used so it can tune 4222 * things accordingly. 4223 */ 4224 #define LIMIT_CAPS(x) do { \ 4225 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 4226 } while (0) 4227 LIMIT_CAPS(nbm); 4228 LIMIT_CAPS(link); 4229 LIMIT_CAPS(switch); 4230 LIMIT_CAPS(nic); 4231 LIMIT_CAPS(toe); 4232 LIMIT_CAPS(rdma); 4233 LIMIT_CAPS(crypto); 4234 LIMIT_CAPS(iscsi); 4235 LIMIT_CAPS(fcoe); 4236 #undef LIMIT_CAPS 4237 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 4238 /* 4239 * TOE and hashfilters are mutually exclusive. It is a config 4240 * file or firmware bug if both are reported as available. Try 4241 * to cope with the situation in non-debug builds by disabling 4242 * TOE. 4243 */ 4244 MPASS(caps.toecaps == 0); 4245 4246 caps.toecaps = 0; 4247 caps.rdmacaps = 0; 4248 caps.iscsicaps = 0; 4249 } 4250 4251 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4252 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 4253 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4254 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 4255 if (rc != 0) { 4256 device_printf(sc->dev, 4257 "failed to process config file: %d.\n", rc); 4258 goto done; 4259 } 4260 4261 t4_tweak_chip_settings(sc); 4262 set_params__pre_init(sc); 4263 4264 /* get basic stuff going */ 4265 rc = -t4_fw_initialize(sc, sc->mbox); 4266 if (rc != 0) { 4267 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 4268 goto done; 4269 } 4270 done: 4271 return (rc); 4272 } 4273 4274 /* 4275 * Partition chip resources for use between various PFs, VFs, etc. 4276 */ 4277 static int 4278 partition_resources(struct adapter *sc) 4279 { 4280 char cfg_file[sizeof(t4_cfg_file)]; 4281 struct caps_allowed caps_allowed; 4282 int rc; 4283 bool fallback; 4284 4285 /* Only the master driver gets to configure the chip resources. */ 4286 MPASS(sc->flags & MASTER_PF); 4287 4288 #define COPY_CAPS(x) do { \ 4289 caps_allowed.x##caps = t4_##x##caps_allowed; \ 4290 } while (0) 4291 bzero(&caps_allowed, sizeof(caps_allowed)); 4292 COPY_CAPS(nbm); 4293 COPY_CAPS(link); 4294 COPY_CAPS(switch); 4295 COPY_CAPS(nic); 4296 COPY_CAPS(toe); 4297 COPY_CAPS(rdma); 4298 COPY_CAPS(crypto); 4299 COPY_CAPS(iscsi); 4300 COPY_CAPS(fcoe); 4301 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 4302 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 4303 retry: 4304 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 4305 if (rc != 0 && fallback) { 4306 device_printf(sc->dev, 4307 "failed (%d) to configure card with \"%s\" profile, " 4308 "will fall back to a basic configuration and retry.\n", 4309 rc, cfg_file); 4310 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 4311 bzero(&caps_allowed, sizeof(caps_allowed)); 4312 COPY_CAPS(switch); 4313 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 4314 fallback = false; 4315 goto retry; 4316 } 4317 #undef COPY_CAPS 4318 return (rc); 4319 } 4320 4321 /* 4322 * Retrieve parameters that are needed (or nice to have) very early. 4323 */ 4324 static int 4325 get_params__pre_init(struct adapter *sc) 4326 { 4327 int rc; 4328 uint32_t param[2], val[2]; 4329 4330 t4_get_version_info(sc); 4331 4332 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 4333 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 4334 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 4335 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 4336 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 4337 4338 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 4339 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 4340 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 4341 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 4342 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 4343 4344 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 4345 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 4346 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 4347 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 4348 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 4349 4350 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 4351 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 4352 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 4353 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 4354 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 4355 4356 param[0] = FW_PARAM_DEV(PORTVEC); 4357 param[1] = FW_PARAM_DEV(CCLK); 4358 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4359 if (rc != 0) { 4360 device_printf(sc->dev, 4361 "failed to query parameters (pre_init): %d.\n", rc); 4362 return (rc); 4363 } 4364 4365 sc->params.portvec = val[0]; 4366 sc->params.nports = bitcount32(val[0]); 4367 sc->params.vpd.cclk = val[1]; 4368 4369 /* Read device log parameters. */ 4370 rc = -t4_init_devlog_params(sc, 1); 4371 if (rc == 0) 4372 fixup_devlog_params(sc); 4373 else { 4374 device_printf(sc->dev, 4375 "failed to get devlog parameters: %d.\n", rc); 4376 rc = 0; /* devlog isn't critical for device operation */ 4377 } 4378 4379 return (rc); 4380 } 4381 4382 /* 4383 * Any params that need to be set before FW_INITIALIZE. 4384 */ 4385 static int 4386 set_params__pre_init(struct adapter *sc) 4387 { 4388 int rc = 0; 4389 uint32_t param, val; 4390 4391 if (chip_id(sc) >= CHELSIO_T6) { 4392 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 4393 val = 1; 4394 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4395 /* firmwares < 1.20.1.0 do not have this param. */ 4396 if (rc == FW_EINVAL && 4397 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) { 4398 rc = 0; 4399 } 4400 if (rc != 0) { 4401 device_printf(sc->dev, 4402 "failed to enable high priority filters :%d.\n", 4403 rc); 4404 } 4405 } 4406 4407 /* Enable opaque VIIDs with firmwares that support it. */ 4408 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 4409 val = 1; 4410 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4411 if (rc == 0 && val == 1) 4412 sc->params.viid_smt_extn_support = true; 4413 else 4414 sc->params.viid_smt_extn_support = false; 4415 4416 return (rc); 4417 } 4418 4419 /* 4420 * Retrieve various parameters that are of interest to the driver. The device 4421 * has been initialized by the firmware at this point. 4422 */ 4423 static int 4424 get_params__post_init(struct adapter *sc) 4425 { 4426 int rc; 4427 uint32_t param[7], val[7]; 4428 struct fw_caps_config_cmd caps; 4429 4430 param[0] = FW_PARAM_PFVF(IQFLINT_START); 4431 param[1] = FW_PARAM_PFVF(EQ_START); 4432 param[2] = FW_PARAM_PFVF(FILTER_START); 4433 param[3] = FW_PARAM_PFVF(FILTER_END); 4434 param[4] = FW_PARAM_PFVF(L2T_START); 4435 param[5] = FW_PARAM_PFVF(L2T_END); 4436 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 4437 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 4438 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 4439 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 4440 if (rc != 0) { 4441 device_printf(sc->dev, 4442 "failed to query parameters (post_init): %d.\n", rc); 4443 return (rc); 4444 } 4445 4446 sc->sge.iq_start = val[0]; 4447 sc->sge.eq_start = val[1]; 4448 if ((int)val[3] > (int)val[2]) { 4449 sc->tids.ftid_base = val[2]; 4450 sc->tids.ftid_end = val[3]; 4451 sc->tids.nftids = val[3] - val[2] + 1; 4452 } 4453 sc->vres.l2t.start = val[4]; 4454 sc->vres.l2t.size = val[5] - val[4] + 1; 4455 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 4456 ("%s: L2 table size (%u) larger than expected (%u)", 4457 __func__, sc->vres.l2t.size, L2T_SIZE)); 4458 sc->params.core_vdd = val[6]; 4459 4460 if (chip_id(sc) >= CHELSIO_T6) { 4461 4462 sc->tids.tid_base = t4_read_reg(sc, 4463 A_LE_DB_ACTIVE_TABLE_START_INDEX); 4464 4465 param[0] = FW_PARAM_PFVF(HPFILTER_START); 4466 param[1] = FW_PARAM_PFVF(HPFILTER_END); 4467 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4468 if (rc != 0) { 4469 device_printf(sc->dev, 4470 "failed to query hpfilter parameters: %d.\n", rc); 4471 return (rc); 4472 } 4473 if ((int)val[1] > (int)val[0]) { 4474 sc->tids.hpftid_base = val[0]; 4475 sc->tids.hpftid_end = val[1]; 4476 sc->tids.nhpftids = val[1] - val[0] + 1; 4477 4478 /* 4479 * These should go off if the layout changes and the 4480 * driver needs to catch up. 4481 */ 4482 MPASS(sc->tids.hpftid_base == 0); 4483 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 4484 } 4485 4486 param[0] = FW_PARAM_PFVF(RAWF_START); 4487 param[1] = FW_PARAM_PFVF(RAWF_END); 4488 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4489 if (rc != 0) { 4490 device_printf(sc->dev, 4491 "failed to query rawf parameters: %d.\n", rc); 4492 return (rc); 4493 } 4494 if ((int)val[1] > (int)val[0]) { 4495 sc->rawf_base = val[0]; 4496 sc->nrawf = val[1] - val[0] + 1; 4497 } 4498 } 4499 4500 /* 4501 * MPSBGMAP is queried separately because only recent firmwares support 4502 * it as a parameter and we don't want the compound query above to fail 4503 * on older firmwares. 4504 */ 4505 param[0] = FW_PARAM_DEV(MPSBGMAP); 4506 val[0] = 0; 4507 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4508 if (rc == 0) 4509 sc->params.mps_bg_map = val[0]; 4510 else 4511 sc->params.mps_bg_map = 0; 4512 4513 /* 4514 * Determine whether the firmware supports the filter2 work request. 4515 * This is queried separately for the same reason as MPSBGMAP above. 4516 */ 4517 param[0] = FW_PARAM_DEV(FILTER2_WR); 4518 val[0] = 0; 4519 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4520 if (rc == 0) 4521 sc->params.filter2_wr_support = val[0] != 0; 4522 else 4523 sc->params.filter2_wr_support = 0; 4524 4525 /* 4526 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 4527 * This is queried separately for the same reason as other params above. 4528 */ 4529 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4530 val[0] = 0; 4531 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4532 if (rc == 0) 4533 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 4534 else 4535 sc->params.ulptx_memwrite_dsgl = false; 4536 4537 /* FW_RI_FR_NSMR_TPTE_WR support */ 4538 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 4539 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4540 if (rc == 0) 4541 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0; 4542 else 4543 sc->params.fr_nsmr_tpte_wr_support = false; 4544 4545 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 4546 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4547 if (rc == 0) 4548 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0]; 4549 else 4550 sc->params.max_pkts_per_eth_tx_pkts_wr = 15; 4551 4552 /* get capabilites */ 4553 bzero(&caps, sizeof(caps)); 4554 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4555 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4556 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4557 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4558 if (rc != 0) { 4559 device_printf(sc->dev, 4560 "failed to get card capabilities: %d.\n", rc); 4561 return (rc); 4562 } 4563 4564 #define READ_CAPS(x) do { \ 4565 sc->x = htobe16(caps.x); \ 4566 } while (0) 4567 READ_CAPS(nbmcaps); 4568 READ_CAPS(linkcaps); 4569 READ_CAPS(switchcaps); 4570 READ_CAPS(niccaps); 4571 READ_CAPS(toecaps); 4572 READ_CAPS(rdmacaps); 4573 READ_CAPS(cryptocaps); 4574 READ_CAPS(iscsicaps); 4575 READ_CAPS(fcoecaps); 4576 4577 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 4578 MPASS(chip_id(sc) > CHELSIO_T4); 4579 MPASS(sc->toecaps == 0); 4580 sc->toecaps = 0; 4581 4582 param[0] = FW_PARAM_DEV(NTID); 4583 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4584 if (rc != 0) { 4585 device_printf(sc->dev, 4586 "failed to query HASHFILTER parameters: %d.\n", rc); 4587 return (rc); 4588 } 4589 sc->tids.ntids = val[0]; 4590 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 4591 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4592 sc->tids.ntids -= sc->tids.nhpftids; 4593 } 4594 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4595 sc->params.hash_filter = 1; 4596 } 4597 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 4598 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 4599 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 4600 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4601 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 4602 if (rc != 0) { 4603 device_printf(sc->dev, 4604 "failed to query NIC parameters: %d.\n", rc); 4605 return (rc); 4606 } 4607 if ((int)val[1] > (int)val[0]) { 4608 sc->tids.etid_base = val[0]; 4609 sc->tids.etid_end = val[1]; 4610 sc->tids.netids = val[1] - val[0] + 1; 4611 sc->params.eo_wr_cred = val[2]; 4612 sc->params.ethoffload = 1; 4613 } 4614 } 4615 if (sc->toecaps) { 4616 /* query offload-related parameters */ 4617 param[0] = FW_PARAM_DEV(NTID); 4618 param[1] = FW_PARAM_PFVF(SERVER_START); 4619 param[2] = FW_PARAM_PFVF(SERVER_END); 4620 param[3] = FW_PARAM_PFVF(TDDP_START); 4621 param[4] = FW_PARAM_PFVF(TDDP_END); 4622 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4623 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4624 if (rc != 0) { 4625 device_printf(sc->dev, 4626 "failed to query TOE parameters: %d.\n", rc); 4627 return (rc); 4628 } 4629 sc->tids.ntids = val[0]; 4630 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 4631 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4632 sc->tids.ntids -= sc->tids.nhpftids; 4633 } 4634 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4635 if ((int)val[2] > (int)val[1]) { 4636 sc->tids.stid_base = val[1]; 4637 sc->tids.nstids = val[2] - val[1] + 1; 4638 } 4639 sc->vres.ddp.start = val[3]; 4640 sc->vres.ddp.size = val[4] - val[3] + 1; 4641 sc->params.ofldq_wr_cred = val[5]; 4642 sc->params.offload = 1; 4643 } else { 4644 /* 4645 * The firmware attempts memfree TOE configuration for -SO cards 4646 * and will report toecaps=0 if it runs out of resources (this 4647 * depends on the config file). It may not report 0 for other 4648 * capabilities dependent on the TOE in this case. Set them to 4649 * 0 here so that the driver doesn't bother tracking resources 4650 * that will never be used. 4651 */ 4652 sc->iscsicaps = 0; 4653 sc->rdmacaps = 0; 4654 } 4655 if (sc->rdmacaps) { 4656 param[0] = FW_PARAM_PFVF(STAG_START); 4657 param[1] = FW_PARAM_PFVF(STAG_END); 4658 param[2] = FW_PARAM_PFVF(RQ_START); 4659 param[3] = FW_PARAM_PFVF(RQ_END); 4660 param[4] = FW_PARAM_PFVF(PBL_START); 4661 param[5] = FW_PARAM_PFVF(PBL_END); 4662 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4663 if (rc != 0) { 4664 device_printf(sc->dev, 4665 "failed to query RDMA parameters(1): %d.\n", rc); 4666 return (rc); 4667 } 4668 sc->vres.stag.start = val[0]; 4669 sc->vres.stag.size = val[1] - val[0] + 1; 4670 sc->vres.rq.start = val[2]; 4671 sc->vres.rq.size = val[3] - val[2] + 1; 4672 sc->vres.pbl.start = val[4]; 4673 sc->vres.pbl.size = val[5] - val[4] + 1; 4674 4675 param[0] = FW_PARAM_PFVF(SQRQ_START); 4676 param[1] = FW_PARAM_PFVF(SQRQ_END); 4677 param[2] = FW_PARAM_PFVF(CQ_START); 4678 param[3] = FW_PARAM_PFVF(CQ_END); 4679 param[4] = FW_PARAM_PFVF(OCQ_START); 4680 param[5] = FW_PARAM_PFVF(OCQ_END); 4681 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4682 if (rc != 0) { 4683 device_printf(sc->dev, 4684 "failed to query RDMA parameters(2): %d.\n", rc); 4685 return (rc); 4686 } 4687 sc->vres.qp.start = val[0]; 4688 sc->vres.qp.size = val[1] - val[0] + 1; 4689 sc->vres.cq.start = val[2]; 4690 sc->vres.cq.size = val[3] - val[2] + 1; 4691 sc->vres.ocq.start = val[4]; 4692 sc->vres.ocq.size = val[5] - val[4] + 1; 4693 4694 param[0] = FW_PARAM_PFVF(SRQ_START); 4695 param[1] = FW_PARAM_PFVF(SRQ_END); 4696 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4697 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4698 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4699 if (rc != 0) { 4700 device_printf(sc->dev, 4701 "failed to query RDMA parameters(3): %d.\n", rc); 4702 return (rc); 4703 } 4704 sc->vres.srq.start = val[0]; 4705 sc->vres.srq.size = val[1] - val[0] + 1; 4706 sc->params.max_ordird_qp = val[2]; 4707 sc->params.max_ird_adapter = val[3]; 4708 } 4709 if (sc->iscsicaps) { 4710 param[0] = FW_PARAM_PFVF(ISCSI_START); 4711 param[1] = FW_PARAM_PFVF(ISCSI_END); 4712 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4713 if (rc != 0) { 4714 device_printf(sc->dev, 4715 "failed to query iSCSI parameters: %d.\n", rc); 4716 return (rc); 4717 } 4718 sc->vres.iscsi.start = val[0]; 4719 sc->vres.iscsi.size = val[1] - val[0] + 1; 4720 } 4721 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4722 param[0] = FW_PARAM_PFVF(TLS_START); 4723 param[1] = FW_PARAM_PFVF(TLS_END); 4724 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4725 if (rc != 0) { 4726 device_printf(sc->dev, 4727 "failed to query TLS parameters: %d.\n", rc); 4728 return (rc); 4729 } 4730 sc->vres.key.start = val[0]; 4731 sc->vres.key.size = val[1] - val[0] + 1; 4732 } 4733 4734 t4_init_sge_params(sc); 4735 4736 /* 4737 * We've got the params we wanted to query via the firmware. Now grab 4738 * some others directly from the chip. 4739 */ 4740 rc = t4_read_chip_settings(sc); 4741 4742 return (rc); 4743 } 4744 4745 #ifdef KERN_TLS 4746 static void 4747 ktls_tick(void *arg) 4748 { 4749 struct adapter *sc; 4750 uint32_t tstamp; 4751 4752 sc = arg; 4753 4754 tstamp = tcp_ts_getticks(); 4755 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1); 4756 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31); 4757 4758 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK); 4759 } 4760 4761 static void 4762 t4_enable_kern_tls(struct adapter *sc) 4763 { 4764 uint32_t m, v; 4765 4766 m = F_ENABLECBYP; 4767 v = F_ENABLECBYP; 4768 t4_set_reg_field(sc, A_TP_PARA_REG6, m, v); 4769 4770 m = F_CPL_FLAGS_UPDATE_EN | F_SEQ_UPDATE_EN; 4771 v = F_CPL_FLAGS_UPDATE_EN | F_SEQ_UPDATE_EN; 4772 t4_set_reg_field(sc, A_ULP_TX_CONFIG, m, v); 4773 4774 m = F_NICMODE; 4775 v = F_NICMODE; 4776 t4_set_reg_field(sc, A_TP_IN_CONFIG, m, v); 4777 4778 m = F_LOOKUPEVERYPKT; 4779 v = 0; 4780 t4_set_reg_field(sc, A_TP_INGRESS_CONFIG, m, v); 4781 4782 m = F_TXDEFERENABLE | F_DISABLEWINDOWPSH | F_DISABLESEPPSHFLAG; 4783 v = F_DISABLEWINDOWPSH; 4784 t4_set_reg_field(sc, A_TP_PC_CONFIG, m, v); 4785 4786 m = V_TIMESTAMPRESOLUTION(M_TIMESTAMPRESOLUTION); 4787 v = V_TIMESTAMPRESOLUTION(0x1f); 4788 t4_set_reg_field(sc, A_TP_TIMER_RESOLUTION, m, v); 4789 4790 sc->flags |= KERN_TLS_OK; 4791 4792 sc->tlst.inline_keys = t4_tls_inline_keys; 4793 sc->tlst.combo_wrs = t4_tls_combo_wrs; 4794 } 4795 #endif 4796 4797 static int 4798 set_params__post_init(struct adapter *sc) 4799 { 4800 uint32_t mask, param, val; 4801 #ifdef TCP_OFFLOAD 4802 int i, v, shift; 4803 #endif 4804 4805 /* ask for encapsulated CPLs */ 4806 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4807 val = 1; 4808 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4809 4810 /* Enable 32b port caps if the firmware supports it. */ 4811 param = FW_PARAM_PFVF(PORT_CAPS32); 4812 val = 1; 4813 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 4814 sc->params.port_caps32 = 1; 4815 4816 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 4817 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 4818 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 4819 V_MASKFILTER(val - 1)); 4820 4821 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER | 4822 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN | 4823 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 4824 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM; 4825 val = 0; 4826 if (t4_attack_filter != 0) { 4827 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE, 4828 F_ATTACKFILTERENABLE); 4829 val |= F_DROPERRORATTACK; 4830 } 4831 if (t4_drop_ip_fragments != 0) { 4832 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP, 4833 F_FRAGMENTDROP); 4834 val |= F_DROPERRORFRAG; 4835 } 4836 if (t4_drop_pkts_with_l2_errors != 0) 4837 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN; 4838 if (t4_drop_pkts_with_l3_errors != 0) { 4839 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN | 4840 F_DROPERRORCSUMIP; 4841 } 4842 if (t4_drop_pkts_with_l4_errors != 0) { 4843 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 4844 F_DROPERRORTCPOPT | F_DROPERRORCSUM; 4845 } 4846 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val); 4847 4848 #ifdef TCP_OFFLOAD 4849 /* 4850 * Override the TOE timers with user provided tunables. This is not the 4851 * recommended way to change the timers (the firmware config file is) so 4852 * these tunables are not documented. 4853 * 4854 * All the timer tunables are in microseconds. 4855 */ 4856 if (t4_toe_keepalive_idle != 0) { 4857 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4858 v &= M_KEEPALIVEIDLE; 4859 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4860 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4861 } 4862 if (t4_toe_keepalive_interval != 0) { 4863 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4864 v &= M_KEEPALIVEINTVL; 4865 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4866 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4867 } 4868 if (t4_toe_keepalive_count != 0) { 4869 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4870 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4871 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4872 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4873 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4874 } 4875 if (t4_toe_rexmt_min != 0) { 4876 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4877 v &= M_RXTMIN; 4878 t4_set_reg_field(sc, A_TP_RXT_MIN, 4879 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4880 } 4881 if (t4_toe_rexmt_max != 0) { 4882 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4883 v &= M_RXTMAX; 4884 t4_set_reg_field(sc, A_TP_RXT_MAX, 4885 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4886 } 4887 if (t4_toe_rexmt_count != 0) { 4888 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4889 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4890 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4891 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4892 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4893 } 4894 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4895 if (t4_toe_rexmt_backoff[i] != -1) { 4896 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4897 shift = (i & 3) << 3; 4898 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4899 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4900 } 4901 } 4902 #endif 4903 4904 #ifdef KERN_TLS 4905 if (t4_kern_tls != 0 && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 4906 sc->toecaps & FW_CAPS_CONFIG_TOE) 4907 t4_enable_kern_tls(sc); 4908 #endif 4909 return (0); 4910 } 4911 4912 #undef FW_PARAM_PFVF 4913 #undef FW_PARAM_DEV 4914 4915 static void 4916 t4_set_desc(struct adapter *sc) 4917 { 4918 char buf[128]; 4919 struct adapter_params *p = &sc->params; 4920 4921 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4922 4923 device_set_desc_copy(sc->dev, buf); 4924 } 4925 4926 static inline void 4927 ifmedia_add4(struct ifmedia *ifm, int m) 4928 { 4929 4930 ifmedia_add(ifm, m, 0, NULL); 4931 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4932 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4933 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4934 } 4935 4936 /* 4937 * This is the selected media, which is not quite the same as the active media. 4938 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 4939 * and active are not the same, and "media: Ethernet selected" otherwise. 4940 */ 4941 static void 4942 set_current_media(struct port_info *pi) 4943 { 4944 struct link_config *lc; 4945 struct ifmedia *ifm; 4946 int mword; 4947 u_int speed; 4948 4949 PORT_LOCK_ASSERT_OWNED(pi); 4950 4951 /* Leave current media alone if it's already set to IFM_NONE. */ 4952 ifm = &pi->media; 4953 if (ifm->ifm_cur != NULL && 4954 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4955 return; 4956 4957 lc = &pi->link_cfg; 4958 if (lc->requested_aneg != AUTONEG_DISABLE && 4959 lc->pcaps & FW_PORT_CAP32_ANEG) { 4960 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4961 return; 4962 } 4963 mword = IFM_ETHER | IFM_FDX; 4964 if (lc->requested_fc & PAUSE_TX) 4965 mword |= IFM_ETH_TXPAUSE; 4966 if (lc->requested_fc & PAUSE_RX) 4967 mword |= IFM_ETH_RXPAUSE; 4968 if (lc->requested_speed == 0) 4969 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 4970 else 4971 speed = lc->requested_speed; 4972 mword |= port_mword(pi, speed_to_fwcap(speed)); 4973 ifmedia_set(ifm, mword); 4974 } 4975 4976 /* 4977 * Returns true if the ifmedia list for the port cannot change. 4978 */ 4979 static bool 4980 fixed_ifmedia(struct port_info *pi) 4981 { 4982 4983 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 4984 pi->port_type == FW_PORT_TYPE_BT_XFI || 4985 pi->port_type == FW_PORT_TYPE_BT_XAUI || 4986 pi->port_type == FW_PORT_TYPE_KX4 || 4987 pi->port_type == FW_PORT_TYPE_KX || 4988 pi->port_type == FW_PORT_TYPE_KR || 4989 pi->port_type == FW_PORT_TYPE_BP_AP || 4990 pi->port_type == FW_PORT_TYPE_BP4_AP || 4991 pi->port_type == FW_PORT_TYPE_BP40_BA || 4992 pi->port_type == FW_PORT_TYPE_KR4_100G || 4993 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 4994 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 4995 } 4996 4997 static void 4998 build_medialist(struct port_info *pi) 4999 { 5000 uint32_t ss, speed; 5001 int unknown, mword, bit; 5002 struct link_config *lc; 5003 struct ifmedia *ifm; 5004 5005 PORT_LOCK_ASSERT_OWNED(pi); 5006 5007 if (pi->flags & FIXED_IFMEDIA) 5008 return; 5009 5010 /* 5011 * Rebuild the ifmedia list. 5012 */ 5013 ifm = &pi->media; 5014 ifmedia_removeall(ifm); 5015 lc = &pi->link_cfg; 5016 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */ 5017 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 5018 MPASS(ss != 0); 5019 no_media: 5020 MPASS(LIST_EMPTY(&ifm->ifm_list)); 5021 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 5022 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 5023 return; 5024 } 5025 5026 unknown = 0; 5027 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 5028 speed = 1 << bit; 5029 MPASS(speed & M_FW_PORT_CAP32_SPEED); 5030 if (ss & speed) { 5031 mword = port_mword(pi, speed); 5032 if (mword == IFM_NONE) { 5033 goto no_media; 5034 } else if (mword == IFM_UNKNOWN) 5035 unknown++; 5036 else 5037 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 5038 } 5039 } 5040 if (unknown > 0) /* Add one unknown for all unknown media types. */ 5041 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 5042 if (lc->pcaps & FW_PORT_CAP32_ANEG) 5043 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 5044 5045 set_current_media(pi); 5046 } 5047 5048 /* 5049 * Initialize the requested fields in the link config based on driver tunables. 5050 */ 5051 static void 5052 init_link_config(struct port_info *pi) 5053 { 5054 struct link_config *lc = &pi->link_cfg; 5055 5056 PORT_LOCK_ASSERT_OWNED(pi); 5057 5058 lc->requested_speed = 0; 5059 5060 if (t4_autoneg == 0) 5061 lc->requested_aneg = AUTONEG_DISABLE; 5062 else if (t4_autoneg == 1) 5063 lc->requested_aneg = AUTONEG_ENABLE; 5064 else 5065 lc->requested_aneg = AUTONEG_AUTO; 5066 5067 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 5068 PAUSE_AUTONEG); 5069 5070 if (t4_fec & FEC_AUTO) 5071 lc->requested_fec = FEC_AUTO; 5072 else if (t4_fec == 0) 5073 lc->requested_fec = FEC_NONE; 5074 else { 5075 /* -1 is handled by the FEC_AUTO block above and not here. */ 5076 lc->requested_fec = t4_fec & 5077 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE); 5078 if (lc->requested_fec == 0) 5079 lc->requested_fec = FEC_AUTO; 5080 } 5081 } 5082 5083 /* 5084 * Makes sure that all requested settings comply with what's supported by the 5085 * port. Returns the number of settings that were invalid and had to be fixed. 5086 */ 5087 static int 5088 fixup_link_config(struct port_info *pi) 5089 { 5090 int n = 0; 5091 struct link_config *lc = &pi->link_cfg; 5092 uint32_t fwspeed; 5093 5094 PORT_LOCK_ASSERT_OWNED(pi); 5095 5096 /* Speed (when not autonegotiating) */ 5097 if (lc->requested_speed != 0) { 5098 fwspeed = speed_to_fwcap(lc->requested_speed); 5099 if ((fwspeed & lc->pcaps) == 0) { 5100 n++; 5101 lc->requested_speed = 0; 5102 } 5103 } 5104 5105 /* Link autonegotiation */ 5106 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 5107 lc->requested_aneg == AUTONEG_DISABLE || 5108 lc->requested_aneg == AUTONEG_AUTO); 5109 if (lc->requested_aneg == AUTONEG_ENABLE && 5110 !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 5111 n++; 5112 lc->requested_aneg = AUTONEG_AUTO; 5113 } 5114 5115 /* Flow control */ 5116 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 5117 if (lc->requested_fc & PAUSE_TX && 5118 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) { 5119 n++; 5120 lc->requested_fc &= ~PAUSE_TX; 5121 } 5122 if (lc->requested_fc & PAUSE_RX && 5123 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) { 5124 n++; 5125 lc->requested_fc &= ~PAUSE_RX; 5126 } 5127 if (!(lc->requested_fc & PAUSE_AUTONEG) && 5128 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) { 5129 n++; 5130 lc->requested_fc |= PAUSE_AUTONEG; 5131 } 5132 5133 /* FEC */ 5134 if ((lc->requested_fec & FEC_RS && 5135 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) || 5136 (lc->requested_fec & FEC_BASER_RS && 5137 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) { 5138 n++; 5139 lc->requested_fec = FEC_AUTO; 5140 } 5141 5142 return (n); 5143 } 5144 5145 /* 5146 * Apply the requested L1 settings, which are expected to be valid, to the 5147 * hardware. 5148 */ 5149 static int 5150 apply_link_config(struct port_info *pi) 5151 { 5152 struct adapter *sc = pi->adapter; 5153 struct link_config *lc = &pi->link_cfg; 5154 int rc; 5155 5156 #ifdef INVARIANTS 5157 ASSERT_SYNCHRONIZED_OP(sc); 5158 PORT_LOCK_ASSERT_OWNED(pi); 5159 5160 if (lc->requested_aneg == AUTONEG_ENABLE) 5161 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG); 5162 if (!(lc->requested_fc & PAUSE_AUTONEG)) 5163 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE); 5164 if (lc->requested_fc & PAUSE_TX) 5165 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX); 5166 if (lc->requested_fc & PAUSE_RX) 5167 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX); 5168 if (lc->requested_fec & FEC_RS) 5169 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS); 5170 if (lc->requested_fec & FEC_BASER_RS) 5171 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS); 5172 #endif 5173 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5174 if (rc != 0) { 5175 /* Don't complain if the VF driver gets back an EPERM. */ 5176 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 5177 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 5178 } else { 5179 /* 5180 * An L1_CFG will almost always result in a link-change event if 5181 * the link is up, and the driver will refresh the actual 5182 * fec/fc/etc. when the notification is processed. If the link 5183 * is down then the actual settings are meaningless. 5184 * 5185 * This takes care of the case where a change in the L1 settings 5186 * may not result in a notification. 5187 */ 5188 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 5189 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 5190 } 5191 return (rc); 5192 } 5193 5194 #define FW_MAC_EXACT_CHUNK 7 5195 struct mcaddr_ctx { 5196 struct ifnet *ifp; 5197 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 5198 uint64_t hash; 5199 int i; 5200 int del; 5201 int rc; 5202 }; 5203 5204 static u_int 5205 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 5206 { 5207 struct mcaddr_ctx *ctx = arg; 5208 struct vi_info *vi = ctx->ifp->if_softc; 5209 struct port_info *pi = vi->pi; 5210 struct adapter *sc = pi->adapter; 5211 5212 if (ctx->rc < 0) 5213 return (0); 5214 5215 ctx->mcaddr[ctx->i] = LLADDR(sdl); 5216 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i])); 5217 ctx->i++; 5218 5219 if (ctx->i == FW_MAC_EXACT_CHUNK) { 5220 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del, 5221 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0); 5222 if (ctx->rc < 0) { 5223 int j; 5224 5225 for (j = 0; j < ctx->i; j++) { 5226 if_printf(ctx->ifp, 5227 "failed to add mc address" 5228 " %02x:%02x:%02x:" 5229 "%02x:%02x:%02x rc=%d\n", 5230 ctx->mcaddr[j][0], ctx->mcaddr[j][1], 5231 ctx->mcaddr[j][2], ctx->mcaddr[j][3], 5232 ctx->mcaddr[j][4], ctx->mcaddr[j][5], 5233 -ctx->rc); 5234 } 5235 return (0); 5236 } 5237 ctx->del = 0; 5238 ctx->i = 0; 5239 } 5240 5241 return (1); 5242 } 5243 5244 /* 5245 * Program the port's XGMAC based on parameters in ifnet. The caller also 5246 * indicates which parameters should be programmed (the rest are left alone). 5247 */ 5248 int 5249 update_mac_settings(struct ifnet *ifp, int flags) 5250 { 5251 int rc = 0; 5252 struct vi_info *vi = ifp->if_softc; 5253 struct port_info *pi = vi->pi; 5254 struct adapter *sc = pi->adapter; 5255 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 5256 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 5257 5258 ASSERT_SYNCHRONIZED_OP(sc); 5259 KASSERT(flags, ("%s: not told what to update.", __func__)); 5260 5261 if (flags & XGMAC_MTU) 5262 mtu = ifp->if_mtu; 5263 5264 if (flags & XGMAC_PROMISC) 5265 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 5266 5267 if (flags & XGMAC_ALLMULTI) 5268 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 5269 5270 if (flags & XGMAC_VLANEX) 5271 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 5272 5273 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 5274 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 5275 allmulti, 1, vlanex, false); 5276 if (rc) { 5277 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 5278 rc); 5279 return (rc); 5280 } 5281 } 5282 5283 if (flags & XGMAC_UCADDR) { 5284 uint8_t ucaddr[ETHER_ADDR_LEN]; 5285 5286 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 5287 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 5288 ucaddr, true, &vi->smt_idx); 5289 if (rc < 0) { 5290 rc = -rc; 5291 if_printf(ifp, "change_mac failed: %d\n", rc); 5292 return (rc); 5293 } else { 5294 vi->xact_addr_filt = rc; 5295 rc = 0; 5296 } 5297 } 5298 5299 if (flags & XGMAC_MCADDRS) { 5300 struct epoch_tracker et; 5301 struct mcaddr_ctx ctx; 5302 int j; 5303 5304 ctx.ifp = ifp; 5305 ctx.hash = 0; 5306 ctx.i = 0; 5307 ctx.del = 1; 5308 ctx.rc = 0; 5309 /* 5310 * Unlike other drivers, we accumulate list of pointers into 5311 * interface address lists and we need to keep it safe even 5312 * after if_foreach_llmaddr() returns, thus we must enter the 5313 * network epoch. 5314 */ 5315 NET_EPOCH_ENTER(et); 5316 if_foreach_llmaddr(ifp, add_maddr, &ctx); 5317 if (ctx.rc < 0) { 5318 NET_EPOCH_EXIT(et); 5319 rc = -ctx.rc; 5320 return (rc); 5321 } 5322 if (ctx.i > 0) { 5323 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 5324 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0); 5325 NET_EPOCH_EXIT(et); 5326 if (rc < 0) { 5327 rc = -rc; 5328 for (j = 0; j < ctx.i; j++) { 5329 if_printf(ifp, 5330 "failed to add mcast address" 5331 " %02x:%02x:%02x:" 5332 "%02x:%02x:%02x rc=%d\n", 5333 ctx.mcaddr[j][0], ctx.mcaddr[j][1], 5334 ctx.mcaddr[j][2], ctx.mcaddr[j][3], 5335 ctx.mcaddr[j][4], ctx.mcaddr[j][5], 5336 rc); 5337 } 5338 return (rc); 5339 } 5340 ctx.del = 0; 5341 } else 5342 NET_EPOCH_EXIT(et); 5343 5344 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0); 5345 if (rc != 0) 5346 if_printf(ifp, "failed to set mcast address hash: %d\n", 5347 rc); 5348 if (ctx.del == 0) { 5349 /* We clobbered the VXLAN entry if there was one. */ 5350 pi->vxlan_tcam_entry = false; 5351 } 5352 } 5353 5354 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 && 5355 pi->vxlan_tcam_entry == false) { 5356 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac, 5357 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 5358 true); 5359 if (rc < 0) { 5360 rc = -rc; 5361 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n", 5362 rc); 5363 } else { 5364 MPASS(rc == sc->rawf_base + pi->port_id); 5365 rc = 0; 5366 pi->vxlan_tcam_entry = true; 5367 } 5368 } 5369 5370 return (rc); 5371 } 5372 5373 /* 5374 * {begin|end}_synchronized_op must be called from the same thread. 5375 */ 5376 int 5377 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 5378 char *wmesg) 5379 { 5380 int rc, pri; 5381 5382 #ifdef WITNESS 5383 /* the caller thinks it's ok to sleep, but is it really? */ 5384 if (flags & SLEEP_OK) 5385 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 5386 "begin_synchronized_op"); 5387 #endif 5388 5389 if (INTR_OK) 5390 pri = PCATCH; 5391 else 5392 pri = 0; 5393 5394 ADAPTER_LOCK(sc); 5395 for (;;) { 5396 5397 if (vi && IS_DOOMED(vi)) { 5398 rc = ENXIO; 5399 goto done; 5400 } 5401 5402 if (!IS_BUSY(sc)) { 5403 rc = 0; 5404 break; 5405 } 5406 5407 if (!(flags & SLEEP_OK)) { 5408 rc = EBUSY; 5409 goto done; 5410 } 5411 5412 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 5413 rc = EINTR; 5414 goto done; 5415 } 5416 } 5417 5418 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 5419 SET_BUSY(sc); 5420 #ifdef INVARIANTS 5421 sc->last_op = wmesg; 5422 sc->last_op_thr = curthread; 5423 sc->last_op_flags = flags; 5424 #endif 5425 5426 done: 5427 if (!(flags & HOLD_LOCK) || rc) 5428 ADAPTER_UNLOCK(sc); 5429 5430 return (rc); 5431 } 5432 5433 /* 5434 * Tell if_ioctl and if_init that the VI is going away. This is 5435 * special variant of begin_synchronized_op and must be paired with a 5436 * call to end_synchronized_op. 5437 */ 5438 void 5439 doom_vi(struct adapter *sc, struct vi_info *vi) 5440 { 5441 5442 ADAPTER_LOCK(sc); 5443 SET_DOOMED(vi); 5444 wakeup(&sc->flags); 5445 while (IS_BUSY(sc)) 5446 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 5447 SET_BUSY(sc); 5448 #ifdef INVARIANTS 5449 sc->last_op = "t4detach"; 5450 sc->last_op_thr = curthread; 5451 sc->last_op_flags = 0; 5452 #endif 5453 ADAPTER_UNLOCK(sc); 5454 } 5455 5456 /* 5457 * {begin|end}_synchronized_op must be called from the same thread. 5458 */ 5459 void 5460 end_synchronized_op(struct adapter *sc, int flags) 5461 { 5462 5463 if (flags & LOCK_HELD) 5464 ADAPTER_LOCK_ASSERT_OWNED(sc); 5465 else 5466 ADAPTER_LOCK(sc); 5467 5468 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 5469 CLR_BUSY(sc); 5470 wakeup(&sc->flags); 5471 ADAPTER_UNLOCK(sc); 5472 } 5473 5474 static int 5475 cxgbe_init_synchronized(struct vi_info *vi) 5476 { 5477 struct port_info *pi = vi->pi; 5478 struct adapter *sc = pi->adapter; 5479 struct ifnet *ifp = vi->ifp; 5480 int rc = 0, i; 5481 struct sge_txq *txq; 5482 5483 ASSERT_SYNCHRONIZED_OP(sc); 5484 5485 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5486 return (0); /* already running */ 5487 5488 if (!(sc->flags & FULL_INIT_DONE) && 5489 ((rc = adapter_full_init(sc)) != 0)) 5490 return (rc); /* error message displayed already */ 5491 5492 if (!(vi->flags & VI_INIT_DONE) && 5493 ((rc = vi_full_init(vi)) != 0)) 5494 return (rc); /* error message displayed already */ 5495 5496 rc = update_mac_settings(ifp, XGMAC_ALL); 5497 if (rc) 5498 goto done; /* error message displayed already */ 5499 5500 PORT_LOCK(pi); 5501 if (pi->up_vis == 0) { 5502 t4_update_port_info(pi); 5503 fixup_link_config(pi); 5504 build_medialist(pi); 5505 apply_link_config(pi); 5506 } 5507 5508 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 5509 if (rc != 0) { 5510 if_printf(ifp, "enable_vi failed: %d\n", rc); 5511 PORT_UNLOCK(pi); 5512 goto done; 5513 } 5514 5515 /* 5516 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 5517 * if this changes. 5518 */ 5519 5520 for_each_txq(vi, i, txq) { 5521 TXQ_LOCK(txq); 5522 txq->eq.flags |= EQ_ENABLED; 5523 TXQ_UNLOCK(txq); 5524 } 5525 5526 /* 5527 * The first iq of the first port to come up is used for tracing. 5528 */ 5529 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 5530 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 5531 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 5532 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 5533 V_QUEUENUMBER(sc->traceq)); 5534 pi->flags |= HAS_TRACEQ; 5535 } 5536 5537 /* all ok */ 5538 pi->up_vis++; 5539 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5540 5541 if (pi->nvi > 1 || sc->flags & IS_VF) 5542 callout_reset(&vi->tick, hz, vi_tick, vi); 5543 else 5544 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 5545 if (pi->link_cfg.link_ok) 5546 t4_os_link_changed(pi); 5547 PORT_UNLOCK(pi); 5548 done: 5549 if (rc != 0) 5550 cxgbe_uninit_synchronized(vi); 5551 5552 return (rc); 5553 } 5554 5555 /* 5556 * Idempotent. 5557 */ 5558 static int 5559 cxgbe_uninit_synchronized(struct vi_info *vi) 5560 { 5561 struct port_info *pi = vi->pi; 5562 struct adapter *sc = pi->adapter; 5563 struct ifnet *ifp = vi->ifp; 5564 int rc, i; 5565 struct sge_txq *txq; 5566 5567 ASSERT_SYNCHRONIZED_OP(sc); 5568 5569 if (!(vi->flags & VI_INIT_DONE)) { 5570 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5571 KASSERT(0, ("uninited VI is running")); 5572 if_printf(ifp, "uninited VI with running ifnet. " 5573 "vi->flags 0x%016lx, if_flags 0x%08x, " 5574 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 5575 ifp->if_drv_flags); 5576 } 5577 return (0); 5578 } 5579 5580 /* 5581 * Disable the VI so that all its data in either direction is discarded 5582 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 5583 * tick) intact as the TP can deliver negative advice or data that it's 5584 * holding in its RAM (for an offloaded connection) even after the VI is 5585 * disabled. 5586 */ 5587 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 5588 if (rc) { 5589 if_printf(ifp, "disable_vi failed: %d\n", rc); 5590 return (rc); 5591 } 5592 5593 for_each_txq(vi, i, txq) { 5594 TXQ_LOCK(txq); 5595 txq->eq.flags &= ~EQ_ENABLED; 5596 TXQ_UNLOCK(txq); 5597 } 5598 5599 PORT_LOCK(pi); 5600 if (pi->nvi > 1 || sc->flags & IS_VF) 5601 callout_stop(&vi->tick); 5602 else 5603 callout_stop(&pi->tick); 5604 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5605 PORT_UNLOCK(pi); 5606 return (0); 5607 } 5608 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5609 pi->up_vis--; 5610 if (pi->up_vis > 0) { 5611 PORT_UNLOCK(pi); 5612 return (0); 5613 } 5614 5615 pi->link_cfg.link_ok = false; 5616 pi->link_cfg.speed = 0; 5617 pi->link_cfg.link_down_rc = 255; 5618 t4_os_link_changed(pi); 5619 PORT_UNLOCK(pi); 5620 5621 return (0); 5622 } 5623 5624 /* 5625 * It is ok for this function to fail midway and return right away. t4_detach 5626 * will walk the entire sc->irq list and clean up whatever is valid. 5627 */ 5628 int 5629 t4_setup_intr_handlers(struct adapter *sc) 5630 { 5631 int rc, rid, p, q, v; 5632 char s[8]; 5633 struct irq *irq; 5634 struct port_info *pi; 5635 struct vi_info *vi; 5636 struct sge *sge = &sc->sge; 5637 struct sge_rxq *rxq; 5638 #ifdef TCP_OFFLOAD 5639 struct sge_ofld_rxq *ofld_rxq; 5640 #endif 5641 #ifdef DEV_NETMAP 5642 struct sge_nm_rxq *nm_rxq; 5643 #endif 5644 #ifdef RSS 5645 int nbuckets = rss_getnumbuckets(); 5646 #endif 5647 5648 /* 5649 * Setup interrupts. 5650 */ 5651 irq = &sc->irq[0]; 5652 rid = sc->intr_type == INTR_INTX ? 0 : 1; 5653 if (forwarding_intr_to_fwq(sc)) 5654 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 5655 5656 /* Multiple interrupts. */ 5657 if (sc->flags & IS_VF) 5658 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 5659 ("%s: too few intr.", __func__)); 5660 else 5661 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 5662 ("%s: too few intr.", __func__)); 5663 5664 /* The first one is always error intr on PFs */ 5665 if (!(sc->flags & IS_VF)) { 5666 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 5667 if (rc != 0) 5668 return (rc); 5669 irq++; 5670 rid++; 5671 } 5672 5673 /* The second one is always the firmware event queue (first on VFs) */ 5674 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 5675 if (rc != 0) 5676 return (rc); 5677 irq++; 5678 rid++; 5679 5680 for_each_port(sc, p) { 5681 pi = sc->port[p]; 5682 for_each_vi(pi, v, vi) { 5683 vi->first_intr = rid - 1; 5684 5685 if (vi->nnmrxq > 0) { 5686 int n = max(vi->nrxq, vi->nnmrxq); 5687 5688 rxq = &sge->rxq[vi->first_rxq]; 5689 #ifdef DEV_NETMAP 5690 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 5691 #endif 5692 for (q = 0; q < n; q++) { 5693 snprintf(s, sizeof(s), "%x%c%x", p, 5694 'a' + v, q); 5695 if (q < vi->nrxq) 5696 irq->rxq = rxq++; 5697 #ifdef DEV_NETMAP 5698 if (q < vi->nnmrxq) 5699 irq->nm_rxq = nm_rxq++; 5700 5701 if (irq->nm_rxq != NULL && 5702 irq->rxq == NULL) { 5703 /* Netmap rx only */ 5704 rc = t4_alloc_irq(sc, irq, rid, 5705 t4_nm_intr, irq->nm_rxq, s); 5706 } 5707 if (irq->nm_rxq != NULL && 5708 irq->rxq != NULL) { 5709 /* NIC and Netmap rx */ 5710 rc = t4_alloc_irq(sc, irq, rid, 5711 t4_vi_intr, irq, s); 5712 } 5713 #endif 5714 if (irq->rxq != NULL && 5715 irq->nm_rxq == NULL) { 5716 /* NIC rx only */ 5717 rc = t4_alloc_irq(sc, irq, rid, 5718 t4_intr, irq->rxq, s); 5719 } 5720 if (rc != 0) 5721 return (rc); 5722 #ifdef RSS 5723 if (q < vi->nrxq) { 5724 bus_bind_intr(sc->dev, irq->res, 5725 rss_getcpu(q % nbuckets)); 5726 } 5727 #endif 5728 irq++; 5729 rid++; 5730 vi->nintr++; 5731 } 5732 } else { 5733 for_each_rxq(vi, q, rxq) { 5734 snprintf(s, sizeof(s), "%x%c%x", p, 5735 'a' + v, q); 5736 rc = t4_alloc_irq(sc, irq, rid, 5737 t4_intr, rxq, s); 5738 if (rc != 0) 5739 return (rc); 5740 #ifdef RSS 5741 bus_bind_intr(sc->dev, irq->res, 5742 rss_getcpu(q % nbuckets)); 5743 #endif 5744 irq++; 5745 rid++; 5746 vi->nintr++; 5747 } 5748 } 5749 #ifdef TCP_OFFLOAD 5750 for_each_ofld_rxq(vi, q, ofld_rxq) { 5751 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 5752 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 5753 ofld_rxq, s); 5754 if (rc != 0) 5755 return (rc); 5756 irq++; 5757 rid++; 5758 vi->nintr++; 5759 } 5760 #endif 5761 } 5762 } 5763 MPASS(irq == &sc->irq[sc->intr_count]); 5764 5765 return (0); 5766 } 5767 5768 int 5769 adapter_full_init(struct adapter *sc) 5770 { 5771 int rc, i; 5772 #ifdef RSS 5773 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5774 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5775 #endif 5776 5777 ASSERT_SYNCHRONIZED_OP(sc); 5778 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5779 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 5780 ("%s: FULL_INIT_DONE already", __func__)); 5781 5782 /* 5783 * queues that belong to the adapter (not any particular port). 5784 */ 5785 rc = t4_setup_adapter_queues(sc); 5786 if (rc != 0) 5787 goto done; 5788 5789 for (i = 0; i < nitems(sc->tq); i++) { 5790 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 5791 taskqueue_thread_enqueue, &sc->tq[i]); 5792 if (sc->tq[i] == NULL) { 5793 device_printf(sc->dev, 5794 "failed to allocate task queue %d\n", i); 5795 rc = ENOMEM; 5796 goto done; 5797 } 5798 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 5799 device_get_nameunit(sc->dev), i); 5800 } 5801 #ifdef RSS 5802 MPASS(RSS_KEYSIZE == 40); 5803 rss_getkey((void *)&raw_rss_key[0]); 5804 for (i = 0; i < nitems(rss_key); i++) { 5805 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 5806 } 5807 t4_write_rss_key(sc, &rss_key[0], -1, 1); 5808 #endif 5809 5810 if (!(sc->flags & IS_VF)) 5811 t4_intr_enable(sc); 5812 #ifdef KERN_TLS 5813 if (sc->flags & KERN_TLS_OK) 5814 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc, 5815 C_HARDCLOCK); 5816 #endif 5817 sc->flags |= FULL_INIT_DONE; 5818 done: 5819 if (rc != 0) 5820 adapter_full_uninit(sc); 5821 5822 return (rc); 5823 } 5824 5825 int 5826 adapter_full_uninit(struct adapter *sc) 5827 { 5828 int i; 5829 5830 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5831 5832 t4_teardown_adapter_queues(sc); 5833 5834 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 5835 taskqueue_free(sc->tq[i]); 5836 sc->tq[i] = NULL; 5837 } 5838 5839 sc->flags &= ~FULL_INIT_DONE; 5840 5841 return (0); 5842 } 5843 5844 #ifdef RSS 5845 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 5846 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 5847 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 5848 RSS_HASHTYPE_RSS_UDP_IPV6) 5849 5850 /* Translates kernel hash types to hardware. */ 5851 static int 5852 hashconfig_to_hashen(int hashconfig) 5853 { 5854 int hashen = 0; 5855 5856 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 5857 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 5858 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 5859 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 5860 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 5861 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5862 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5863 } 5864 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 5865 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5866 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5867 } 5868 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 5869 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5870 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 5871 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5872 5873 return (hashen); 5874 } 5875 5876 /* Translates hardware hash types to kernel. */ 5877 static int 5878 hashen_to_hashconfig(int hashen) 5879 { 5880 int hashconfig = 0; 5881 5882 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 5883 /* 5884 * If UDP hashing was enabled it must have been enabled for 5885 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 5886 * enabling any 4-tuple hash is nonsense configuration. 5887 */ 5888 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5889 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 5890 5891 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5892 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 5893 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5894 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 5895 } 5896 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5897 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 5898 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5899 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 5900 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 5901 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 5902 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 5903 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 5904 5905 return (hashconfig); 5906 } 5907 #endif 5908 5909 int 5910 vi_full_init(struct vi_info *vi) 5911 { 5912 struct adapter *sc = vi->adapter; 5913 struct ifnet *ifp = vi->ifp; 5914 uint16_t *rss; 5915 struct sge_rxq *rxq; 5916 int rc, i, j; 5917 #ifdef RSS 5918 int nbuckets = rss_getnumbuckets(); 5919 int hashconfig = rss_gethashconfig(); 5920 int extra; 5921 #endif 5922 5923 ASSERT_SYNCHRONIZED_OP(sc); 5924 KASSERT((vi->flags & VI_INIT_DONE) == 0, 5925 ("%s: VI_INIT_DONE already", __func__)); 5926 5927 sysctl_ctx_init(&vi->ctx); 5928 vi->flags |= VI_SYSCTL_CTX; 5929 5930 /* 5931 * Allocate tx/rx/fl queues for this VI. 5932 */ 5933 rc = t4_setup_vi_queues(vi); 5934 if (rc != 0) 5935 goto done; /* error message displayed already */ 5936 5937 /* 5938 * Setup RSS for this VI. Save a copy of the RSS table for later use. 5939 */ 5940 if (vi->nrxq > vi->rss_size) { 5941 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 5942 "some queues will never receive traffic.\n", vi->nrxq, 5943 vi->rss_size); 5944 } else if (vi->rss_size % vi->nrxq) { 5945 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 5946 "expect uneven traffic distribution.\n", vi->nrxq, 5947 vi->rss_size); 5948 } 5949 #ifdef RSS 5950 if (vi->nrxq != nbuckets) { 5951 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5952 "performance will be impacted.\n", vi->nrxq, nbuckets); 5953 } 5954 #endif 5955 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5956 for (i = 0; i < vi->rss_size;) { 5957 #ifdef RSS 5958 j = rss_get_indirection_to_bucket(i); 5959 j %= vi->nrxq; 5960 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5961 rss[i++] = rxq->iq.abs_id; 5962 #else 5963 for_each_rxq(vi, j, rxq) { 5964 rss[i++] = rxq->iq.abs_id; 5965 if (i == vi->rss_size) 5966 break; 5967 } 5968 #endif 5969 } 5970 5971 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5972 vi->rss_size); 5973 if (rc != 0) { 5974 free(rss, M_CXGBE); 5975 if_printf(ifp, "rss_config failed: %d\n", rc); 5976 goto done; 5977 } 5978 5979 #ifdef RSS 5980 vi->hashen = hashconfig_to_hashen(hashconfig); 5981 5982 /* 5983 * We may have had to enable some hashes even though the global config 5984 * wants them disabled. This is a potential problem that must be 5985 * reported to the user. 5986 */ 5987 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 5988 5989 /* 5990 * If we consider only the supported hash types, then the enabled hashes 5991 * are a superset of the requested hashes. In other words, there cannot 5992 * be any supported hash that was requested but not enabled, but there 5993 * can be hashes that were not requested but had to be enabled. 5994 */ 5995 extra &= SUPPORTED_RSS_HASHTYPES; 5996 MPASS((extra & hashconfig) == 0); 5997 5998 if (extra) { 5999 if_printf(ifp, 6000 "global RSS config (0x%x) cannot be accommodated.\n", 6001 hashconfig); 6002 } 6003 if (extra & RSS_HASHTYPE_RSS_IPV4) 6004 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 6005 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 6006 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 6007 if (extra & RSS_HASHTYPE_RSS_IPV6) 6008 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 6009 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 6010 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 6011 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 6012 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 6013 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 6014 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 6015 #else 6016 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 6017 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 6018 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6019 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 6020 #endif 6021 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0); 6022 if (rc != 0) { 6023 free(rss, M_CXGBE); 6024 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 6025 goto done; 6026 } 6027 6028 vi->rss = rss; 6029 vi->flags |= VI_INIT_DONE; 6030 done: 6031 if (rc != 0) 6032 vi_full_uninit(vi); 6033 6034 return (rc); 6035 } 6036 6037 /* 6038 * Idempotent. 6039 */ 6040 int 6041 vi_full_uninit(struct vi_info *vi) 6042 { 6043 struct port_info *pi = vi->pi; 6044 struct adapter *sc = pi->adapter; 6045 int i; 6046 struct sge_rxq *rxq; 6047 struct sge_txq *txq; 6048 #ifdef TCP_OFFLOAD 6049 struct sge_ofld_rxq *ofld_rxq; 6050 #endif 6051 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 6052 struct sge_wrq *ofld_txq; 6053 #endif 6054 6055 if (vi->flags & VI_INIT_DONE) { 6056 6057 /* Need to quiesce queues. */ 6058 6059 /* XXX: Only for the first VI? */ 6060 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 6061 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 6062 6063 for_each_txq(vi, i, txq) { 6064 quiesce_txq(sc, txq); 6065 } 6066 6067 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 6068 for_each_ofld_txq(vi, i, ofld_txq) { 6069 quiesce_wrq(sc, ofld_txq); 6070 } 6071 #endif 6072 6073 for_each_rxq(vi, i, rxq) { 6074 quiesce_iq(sc, &rxq->iq); 6075 quiesce_fl(sc, &rxq->fl); 6076 } 6077 6078 #ifdef TCP_OFFLOAD 6079 for_each_ofld_rxq(vi, i, ofld_rxq) { 6080 quiesce_iq(sc, &ofld_rxq->iq); 6081 quiesce_fl(sc, &ofld_rxq->fl); 6082 } 6083 #endif 6084 free(vi->rss, M_CXGBE); 6085 free(vi->nm_rss, M_CXGBE); 6086 } 6087 6088 t4_teardown_vi_queues(vi); 6089 vi->flags &= ~VI_INIT_DONE; 6090 6091 return (0); 6092 } 6093 6094 static void 6095 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 6096 { 6097 struct sge_eq *eq = &txq->eq; 6098 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6099 6100 (void) sc; /* unused */ 6101 6102 #ifdef INVARIANTS 6103 TXQ_LOCK(txq); 6104 MPASS((eq->flags & EQ_ENABLED) == 0); 6105 TXQ_UNLOCK(txq); 6106 #endif 6107 6108 /* Wait for the mp_ring to empty. */ 6109 while (!mp_ring_is_idle(txq->r)) { 6110 mp_ring_check_drainage(txq->r, 4096); 6111 pause("rquiesce", 1); 6112 } 6113 6114 /* Then wait for the hardware to finish. */ 6115 while (spg->cidx != htobe16(eq->pidx)) 6116 pause("equiesce", 1); 6117 6118 /* Finally, wait for the driver to reclaim all descriptors. */ 6119 while (eq->cidx != eq->pidx) 6120 pause("dquiesce", 1); 6121 } 6122 6123 static void 6124 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 6125 { 6126 6127 /* XXXTX */ 6128 } 6129 6130 static void 6131 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 6132 { 6133 (void) sc; /* unused */ 6134 6135 /* Synchronize with the interrupt handler */ 6136 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 6137 pause("iqfree", 1); 6138 } 6139 6140 static void 6141 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 6142 { 6143 mtx_lock(&sc->sfl_lock); 6144 FL_LOCK(fl); 6145 fl->flags |= FL_DOOMED; 6146 FL_UNLOCK(fl); 6147 callout_stop(&sc->sfl_callout); 6148 mtx_unlock(&sc->sfl_lock); 6149 6150 KASSERT((fl->flags & FL_STARVING) == 0, 6151 ("%s: still starving", __func__)); 6152 } 6153 6154 static int 6155 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 6156 driver_intr_t *handler, void *arg, char *name) 6157 { 6158 int rc; 6159 6160 irq->rid = rid; 6161 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 6162 RF_SHAREABLE | RF_ACTIVE); 6163 if (irq->res == NULL) { 6164 device_printf(sc->dev, 6165 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 6166 return (ENOMEM); 6167 } 6168 6169 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 6170 NULL, handler, arg, &irq->tag); 6171 if (rc != 0) { 6172 device_printf(sc->dev, 6173 "failed to setup interrupt for rid %d, name %s: %d\n", 6174 rid, name, rc); 6175 } else if (name) 6176 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 6177 6178 return (rc); 6179 } 6180 6181 static int 6182 t4_free_irq(struct adapter *sc, struct irq *irq) 6183 { 6184 if (irq->tag) 6185 bus_teardown_intr(sc->dev, irq->res, irq->tag); 6186 if (irq->res) 6187 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 6188 6189 bzero(irq, sizeof(*irq)); 6190 6191 return (0); 6192 } 6193 6194 static void 6195 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 6196 { 6197 6198 regs->version = chip_id(sc) | chip_rev(sc) << 10; 6199 t4_get_regs(sc, buf, regs->len); 6200 } 6201 6202 #define A_PL_INDIR_CMD 0x1f8 6203 6204 #define S_PL_AUTOINC 31 6205 #define M_PL_AUTOINC 0x1U 6206 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 6207 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 6208 6209 #define S_PL_VFID 20 6210 #define M_PL_VFID 0xffU 6211 #define V_PL_VFID(x) ((x) << S_PL_VFID) 6212 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 6213 6214 #define S_PL_ADDR 0 6215 #define M_PL_ADDR 0xfffffU 6216 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 6217 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 6218 6219 #define A_PL_INDIR_DATA 0x1fc 6220 6221 static uint64_t 6222 read_vf_stat(struct adapter *sc, u_int vin, int reg) 6223 { 6224 u32 stats[2]; 6225 6226 mtx_assert(&sc->reg_lock, MA_OWNED); 6227 if (sc->flags & IS_VF) { 6228 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 6229 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 6230 } else { 6231 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 6232 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 6233 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 6234 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 6235 } 6236 return (((uint64_t)stats[1]) << 32 | stats[0]); 6237 } 6238 6239 static void 6240 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 6241 { 6242 6243 #define GET_STAT(name) \ 6244 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 6245 6246 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 6247 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 6248 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 6249 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 6250 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 6251 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 6252 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 6253 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 6254 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 6255 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 6256 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 6257 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 6258 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 6259 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 6260 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 6261 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 6262 6263 #undef GET_STAT 6264 } 6265 6266 static void 6267 t4_clr_vi_stats(struct adapter *sc, u_int vin) 6268 { 6269 int reg; 6270 6271 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 6272 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 6273 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 6274 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 6275 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 6276 } 6277 6278 static void 6279 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 6280 { 6281 struct timeval tv; 6282 const struct timeval interval = {0, 250000}; /* 250ms */ 6283 6284 if (!(vi->flags & VI_INIT_DONE)) 6285 return; 6286 6287 getmicrotime(&tv); 6288 timevalsub(&tv, &interval); 6289 if (timevalcmp(&tv, &vi->last_refreshed, <)) 6290 return; 6291 6292 mtx_lock(&sc->reg_lock); 6293 t4_get_vi_stats(sc, vi->vin, &vi->stats); 6294 getmicrotime(&vi->last_refreshed); 6295 mtx_unlock(&sc->reg_lock); 6296 } 6297 6298 static void 6299 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 6300 { 6301 u_int i, v, tnl_cong_drops, chan_map; 6302 struct timeval tv; 6303 const struct timeval interval = {0, 250000}; /* 250ms */ 6304 6305 getmicrotime(&tv); 6306 timevalsub(&tv, &interval); 6307 if (timevalcmp(&tv, &pi->last_refreshed, <)) 6308 return; 6309 6310 tnl_cong_drops = 0; 6311 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 6312 chan_map = pi->rx_e_chan_map; 6313 while (chan_map) { 6314 i = ffs(chan_map) - 1; 6315 mtx_lock(&sc->reg_lock); 6316 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 6317 A_TP_MIB_TNL_CNG_DROP_0 + i); 6318 mtx_unlock(&sc->reg_lock); 6319 tnl_cong_drops += v; 6320 chan_map &= ~(1 << i); 6321 } 6322 pi->tnl_cong_drops = tnl_cong_drops; 6323 getmicrotime(&pi->last_refreshed); 6324 } 6325 6326 static void 6327 cxgbe_tick(void *arg) 6328 { 6329 struct port_info *pi = arg; 6330 struct adapter *sc = pi->adapter; 6331 6332 PORT_LOCK_ASSERT_OWNED(pi); 6333 cxgbe_refresh_stats(sc, pi); 6334 6335 callout_schedule(&pi->tick, hz); 6336 } 6337 6338 void 6339 vi_tick(void *arg) 6340 { 6341 struct vi_info *vi = arg; 6342 struct adapter *sc = vi->adapter; 6343 6344 vi_refresh_stats(sc, vi); 6345 6346 callout_schedule(&vi->tick, hz); 6347 } 6348 6349 /* 6350 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 6351 */ 6352 static char *caps_decoder[] = { 6353 "\20\001IPMI\002NCSI", /* 0: NBM */ 6354 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 6355 "\20\001INGRESS\002EGRESS", /* 2: switch */ 6356 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 6357 "\006HASHFILTER\007ETHOFLD", 6358 "\20\001TOE", /* 4: TOE */ 6359 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 6360 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 6361 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 6362 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 6363 "\007T10DIF" 6364 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 6365 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 6366 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 6367 "\004PO_INITIATOR\005PO_TARGET", 6368 }; 6369 6370 void 6371 t4_sysctls(struct adapter *sc) 6372 { 6373 struct sysctl_ctx_list *ctx; 6374 struct sysctl_oid *oid; 6375 struct sysctl_oid_list *children, *c0; 6376 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 6377 6378 ctx = device_get_sysctl_ctx(sc->dev); 6379 6380 /* 6381 * dev.t4nex.X. 6382 */ 6383 oid = device_get_sysctl_tree(sc->dev); 6384 c0 = children = SYSCTL_CHILDREN(oid); 6385 6386 sc->sc_do_rxcopy = 1; 6387 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 6388 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 6389 6390 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 6391 sc->params.nports, "# of ports"); 6392 6393 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 6394 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells, 6395 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A", 6396 "available doorbells"); 6397 6398 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 6399 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 6400 6401 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 6402 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 6403 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val), 6404 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 6405 6406 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 6407 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 6408 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val), 6409 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 6410 6411 t4_sge_sysctls(sc, ctx, children); 6412 6413 sc->lro_timeout = 100; 6414 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 6415 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 6416 6417 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 6418 &sc->debug_flags, 0, "flags to enable runtime debugging"); 6419 6420 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 6421 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 6422 6423 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 6424 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 6425 6426 if (sc->flags & IS_VF) 6427 return; 6428 6429 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 6430 NULL, chip_rev(sc), "chip hardware revision"); 6431 6432 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 6433 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 6434 6435 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 6436 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 6437 6438 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 6439 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 6440 6441 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 6442 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 6443 6444 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 6445 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 6446 6447 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 6448 sc->er_version, 0, "expansion ROM version"); 6449 6450 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 6451 sc->bs_version, 0, "bootstrap firmware version"); 6452 6453 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 6454 NULL, sc->params.scfg_vers, "serial config version"); 6455 6456 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 6457 NULL, sc->params.vpd_vers, "VPD version"); 6458 6459 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 6460 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 6461 6462 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 6463 sc->cfcsum, "config file checksum"); 6464 6465 #define SYSCTL_CAP(name, n, text) \ 6466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 6467 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \ 6468 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \ 6469 "available " text " capabilities") 6470 6471 SYSCTL_CAP(nbmcaps, 0, "NBM"); 6472 SYSCTL_CAP(linkcaps, 1, "link"); 6473 SYSCTL_CAP(switchcaps, 2, "switch"); 6474 SYSCTL_CAP(niccaps, 3, "NIC"); 6475 SYSCTL_CAP(toecaps, 4, "TCP offload"); 6476 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 6477 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 6478 SYSCTL_CAP(cryptocaps, 7, "crypto"); 6479 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 6480 #undef SYSCTL_CAP 6481 6482 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 6483 NULL, sc->tids.nftids, "number of filters"); 6484 6485 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6486 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6487 sysctl_temperature, "I", "chip temperature (in Celsius)"); 6488 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", 6489 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 6490 sysctl_reset_sensor, "I", "reset the chip's temperature sensor."); 6491 6492 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", 6493 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6494 sysctl_loadavg, "A", 6495 "microprocessor load averages (debug firmwares only)"); 6496 6497 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", 6498 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd, 6499 "I", "core Vdd (in mV)"); 6500 6501 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 6502 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS, 6503 sysctl_cpus, "A", "local CPUs"); 6504 6505 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 6506 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS, 6507 sysctl_cpus, "A", "preferred CPUs for interrupts"); 6508 6509 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 6510 &sc->swintr, 0, "software triggered interrupts"); 6511 6512 /* 6513 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 6514 */ 6515 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 6516 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL, 6517 "logs and miscellaneous information"); 6518 children = SYSCTL_CHILDREN(oid); 6519 6520 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 6521 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6522 sysctl_cctrl, "A", "congestion control"); 6523 6524 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 6525 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6526 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 6527 6528 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 6529 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 6530 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 6531 6532 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 6533 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 6534 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 6535 6536 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 6537 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3, 6538 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 6539 6540 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 6541 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4, 6542 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 6543 6544 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 6545 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5, 6546 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 6547 6548 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 6549 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6550 sysctl_cim_la, "A", "CIM logic analyzer"); 6551 6552 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 6553 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6554 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 6555 6556 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 6557 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6558 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 6559 6560 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 6561 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6562 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 6563 6564 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 6565 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6566 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 6567 6568 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 6569 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6570 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 6571 6572 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 6573 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6574 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 6575 6576 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 6577 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6578 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 6579 6580 if (chip_id(sc) > CHELSIO_T4) { 6581 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 6582 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6583 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 6584 "CIM OBQ 6 (SGE0-RX)"); 6585 6586 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 6587 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6588 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 6589 "CIM OBQ 7 (SGE1-RX)"); 6590 } 6591 6592 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 6593 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6594 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 6595 6596 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 6597 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6598 sysctl_cim_qcfg, "A", "CIM queue configuration"); 6599 6600 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 6601 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6602 sysctl_cpl_stats, "A", "CPL statistics"); 6603 6604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 6605 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6606 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 6607 6608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 6609 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6610 sysctl_devlog, "A", "firmware's device log"); 6611 6612 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 6613 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6614 sysctl_fcoe_stats, "A", "FCoE statistics"); 6615 6616 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 6617 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6618 sysctl_hw_sched, "A", "hardware scheduler "); 6619 6620 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 6621 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6622 sysctl_l2t, "A", "hardware L2 table"); 6623 6624 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 6625 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6626 sysctl_smt, "A", "hardware source MAC table"); 6627 6628 #ifdef INET6 6629 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 6630 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6631 sysctl_clip, "A", "active CLIP table entries"); 6632 #endif 6633 6634 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 6635 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6636 sysctl_lb_stats, "A", "loopback statistics"); 6637 6638 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 6639 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6640 sysctl_meminfo, "A", "memory regions"); 6641 6642 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 6643 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6644 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 6645 "A", "MPS TCAM entries"); 6646 6647 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 6648 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6649 sysctl_path_mtus, "A", "path MTUs"); 6650 6651 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 6652 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6653 sysctl_pm_stats, "A", "PM statistics"); 6654 6655 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 6656 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6657 sysctl_rdma_stats, "A", "RDMA statistics"); 6658 6659 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 6660 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6661 sysctl_tcp_stats, "A", "TCP statistics"); 6662 6663 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 6664 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6665 sysctl_tids, "A", "TID information"); 6666 6667 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 6668 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6669 sysctl_tp_err_stats, "A", "TP error statistics"); 6670 6671 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 6672 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 6673 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask"); 6674 6675 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 6676 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6677 sysctl_tp_la, "A", "TP logic analyzer"); 6678 6679 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 6680 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6681 sysctl_tx_rate, "A", "Tx rate"); 6682 6683 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 6684 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6685 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 6686 6687 if (chip_id(sc) >= CHELSIO_T5) { 6688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 6689 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6690 sysctl_wcwr_stats, "A", "write combined work requests"); 6691 } 6692 6693 #ifdef KERN_TLS 6694 if (sc->flags & KERN_TLS_OK) { 6695 /* 6696 * dev.t4nex.0.tls. 6697 */ 6698 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", 6699 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters"); 6700 children = SYSCTL_CHILDREN(oid); 6701 6702 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys", 6703 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS " 6704 "keys in work requests (1) or attempt to store TLS keys " 6705 "in card memory."); 6706 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs", 6707 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to combine " 6708 "TCB field updates with TLS record work requests."); 6709 } 6710 #endif 6711 6712 #ifdef TCP_OFFLOAD 6713 if (is_offload(sc)) { 6714 int i; 6715 char s[4]; 6716 6717 /* 6718 * dev.t4nex.X.toe. 6719 */ 6720 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", 6721 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters"); 6722 children = SYSCTL_CHILDREN(oid); 6723 6724 sc->tt.cong_algorithm = -1; 6725 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 6726 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 6727 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 6728 "3 = highspeed)"); 6729 6730 sc->tt.sndbuf = -1; 6731 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 6732 &sc->tt.sndbuf, 0, "hardware send buffer"); 6733 6734 sc->tt.ddp = 0; 6735 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", 6736 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, ""); 6737 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW, 6738 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)"); 6739 6740 sc->tt.rx_coalesce = -1; 6741 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 6742 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 6743 6744 sc->tt.tls = 0; 6745 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT | 6746 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I", 6747 "Inline TLS allowed"); 6748 6749 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 6750 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 6751 sysctl_tls_rx_ports, "I", 6752 "TCP ports that use inline TLS+TOE RX"); 6753 6754 sc->tt.tx_align = -1; 6755 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 6756 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 6757 6758 sc->tt.tx_zcopy = 0; 6759 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 6760 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 6761 "Enable zero-copy aio_write(2)"); 6762 6763 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 6764 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6765 "cop_managed_offloading", CTLFLAG_RW, 6766 &sc->tt.cop_managed_offloading, 0, 6767 "COP (Connection Offload Policy) controls all TOE offload"); 6768 6769 sc->tt.autorcvbuf_inc = 16 * 1024; 6770 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 6771 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 6772 "autorcvbuf increment"); 6773 6774 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 6775 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6776 sysctl_tp_tick, "A", "TP timer tick (us)"); 6777 6778 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 6779 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 6780 sysctl_tp_tick, "A", "TCP timestamp tick (us)"); 6781 6782 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 6783 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 6784 sysctl_tp_tick, "A", "DACK tick (us)"); 6785 6786 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 6787 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 6788 sysctl_tp_dack_timer, "IU", "DACK timer (us)"); 6789 6790 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 6791 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6792 A_TP_RXT_MIN, sysctl_tp_timer, "LU", 6793 "Minimum retransmit interval (us)"); 6794 6795 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 6796 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6797 A_TP_RXT_MAX, sysctl_tp_timer, "LU", 6798 "Maximum retransmit interval (us)"); 6799 6800 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 6801 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6802 A_TP_PERS_MIN, sysctl_tp_timer, "LU", 6803 "Persist timer min (us)"); 6804 6805 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 6806 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6807 A_TP_PERS_MAX, sysctl_tp_timer, "LU", 6808 "Persist timer max (us)"); 6809 6810 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 6811 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6812 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU", 6813 "Keepalive idle timer (us)"); 6814 6815 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 6816 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6817 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU", 6818 "Keepalive interval timer (us)"); 6819 6820 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 6821 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6822 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)"); 6823 6824 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 6825 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6826 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU", 6827 "FINWAIT2 timer (us)"); 6828 6829 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 6830 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6831 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU", 6832 "Number of SYN retransmissions before abort"); 6833 6834 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 6835 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6836 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU", 6837 "Number of retransmissions before abort"); 6838 6839 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 6840 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6841 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU", 6842 "Number of keepalive probes before abort"); 6843 6844 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 6845 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 6846 "TOE retransmit backoffs"); 6847 children = SYSCTL_CHILDREN(oid); 6848 for (i = 0; i < 16; i++) { 6849 snprintf(s, sizeof(s), "%u", i); 6850 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 6851 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 6852 i, sysctl_tp_backoff, "IU", 6853 "TOE retransmit backoff"); 6854 } 6855 } 6856 #endif 6857 } 6858 6859 void 6860 vi_sysctls(struct vi_info *vi) 6861 { 6862 struct sysctl_ctx_list *ctx; 6863 struct sysctl_oid *oid; 6864 struct sysctl_oid_list *children; 6865 6866 ctx = device_get_sysctl_ctx(vi->dev); 6867 6868 /* 6869 * dev.v?(cxgbe|cxl).X. 6870 */ 6871 oid = device_get_sysctl_tree(vi->dev); 6872 children = SYSCTL_CHILDREN(oid); 6873 6874 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 6875 vi->viid, "VI identifer"); 6876 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 6877 &vi->nrxq, 0, "# of rx queues"); 6878 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 6879 &vi->ntxq, 0, "# of tx queues"); 6880 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 6881 &vi->first_rxq, 0, "index of first rx queue"); 6882 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 6883 &vi->first_txq, 0, "index of first tx queue"); 6884 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 6885 vi->rss_base, "start of RSS indirection table"); 6886 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 6887 vi->rss_size, "size of RSS indirection table"); 6888 6889 if (IS_MAIN_VI(vi)) { 6890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 6891 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 6892 sysctl_noflowq, "IU", 6893 "Reserve queue 0 for non-flowid packets"); 6894 } 6895 6896 if (vi->adapter->flags & IS_VF) { 6897 MPASS(vi->flags & TX_USES_VM_WR); 6898 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD, 6899 NULL, 1, "use VM work requests for transmit"); 6900 } else { 6901 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr", 6902 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 6903 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit"); 6904 } 6905 6906 #ifdef TCP_OFFLOAD 6907 if (vi->nofldrxq != 0) { 6908 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 6909 &vi->nofldrxq, 0, 6910 "# of rx queues for offloaded TCP connections"); 6911 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 6912 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 6913 "index of first TOE rx queue"); 6914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 6915 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 6916 sysctl_holdoff_tmr_idx_ofld, "I", 6917 "holdoff timer index for TOE queues"); 6918 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 6919 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 6920 sysctl_holdoff_pktc_idx_ofld, "I", 6921 "holdoff packet counter index for TOE queues"); 6922 } 6923 #endif 6924 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 6925 if (vi->nofldtxq != 0) { 6926 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 6927 &vi->nofldtxq, 0, 6928 "# of tx queues for TOE/ETHOFLD"); 6929 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 6930 CTLFLAG_RD, &vi->first_ofld_txq, 0, 6931 "index of first TOE/ETHOFLD tx queue"); 6932 } 6933 #endif 6934 #ifdef DEV_NETMAP 6935 if (vi->nnmrxq != 0) { 6936 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 6937 &vi->nnmrxq, 0, "# of netmap rx queues"); 6938 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 6939 &vi->nnmtxq, 0, "# of netmap tx queues"); 6940 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 6941 CTLFLAG_RD, &vi->first_nm_rxq, 0, 6942 "index of first netmap rx queue"); 6943 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 6944 CTLFLAG_RD, &vi->first_nm_txq, 0, 6945 "index of first netmap tx queue"); 6946 } 6947 #endif 6948 6949 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 6950 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 6951 sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); 6952 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 6953 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 6954 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); 6955 6956 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 6957 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 6958 sysctl_qsize_rxq, "I", "rx queue size"); 6959 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 6960 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 6961 sysctl_qsize_txq, "I", "tx queue size"); 6962 } 6963 6964 static void 6965 cxgbe_sysctls(struct port_info *pi) 6966 { 6967 struct sysctl_ctx_list *ctx; 6968 struct sysctl_oid *oid; 6969 struct sysctl_oid_list *children, *children2; 6970 struct adapter *sc = pi->adapter; 6971 int i; 6972 char name[16]; 6973 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"}; 6974 6975 ctx = device_get_sysctl_ctx(pi->dev); 6976 6977 /* 6978 * dev.cxgbe.X. 6979 */ 6980 oid = device_get_sysctl_tree(pi->dev); 6981 children = SYSCTL_CHILDREN(oid); 6982 6983 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", 6984 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 6985 sysctl_linkdnrc, "A", "reason why link is down"); 6986 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 6987 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6988 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 6989 sysctl_btphy, "I", "PHY temperature (in Celsius)"); 6990 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 6991 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1, 6992 sysctl_btphy, "I", "PHY firmware version"); 6993 } 6994 6995 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 6996 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 6997 sysctl_pause_settings, "A", 6998 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 6999 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 7000 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7001 sysctl_fec, "A", 7002 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)"); 7003 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec", 7004 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A", 7005 "FEC recommended by the cable/transceiver"); 7006 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 7007 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7008 sysctl_autoneg, "I", 7009 "autonegotiation (-1 = not supported)"); 7010 7011 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD, 7012 &pi->link_cfg.pcaps, 0, "port capabilities"); 7013 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD, 7014 &pi->link_cfg.acaps, 0, "advertised capabilities"); 7015 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD, 7016 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities"); 7017 7018 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 7019 port_top_speed(pi), "max speed (in Gbps)"); 7020 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 7021 pi->mps_bg_map, "MPS buffer group map"); 7022 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 7023 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 7024 7025 if (sc->flags & IS_VF) 7026 return; 7027 7028 /* 7029 * dev.(cxgbe|cxl).X.tc. 7030 */ 7031 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", 7032 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7033 "Tx scheduler traffic classes (cl_rl)"); 7034 children2 = SYSCTL_CHILDREN(oid); 7035 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 7036 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 7037 "pktsize for per-flow cl-rl (0 means up to the driver )"); 7038 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 7039 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 7040 "burstsize for per-flow cl-rl (0 means up to the driver)"); 7041 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 7042 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 7043 7044 snprintf(name, sizeof(name), "%d", i); 7045 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 7046 SYSCTL_CHILDREN(oid), OID_AUTO, name, 7047 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class")); 7048 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 7049 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags, 7050 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags"); 7051 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 7052 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 7053 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 7054 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7055 (pi->port_id << 16) | i, sysctl_tc_params, "A", 7056 "traffic class parameters"); 7057 } 7058 7059 /* 7060 * dev.cxgbe.X.stats. 7061 */ 7062 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 7063 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics"); 7064 children = SYSCTL_CHILDREN(oid); 7065 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 7066 &pi->tx_parse_error, 0, 7067 "# of tx packets with invalid length or # of segments"); 7068 7069 #define T4_REGSTAT(name, stat, desc) \ 7070 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \ 7071 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \ 7072 (is_t4(sc) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L) : \ 7073 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L)), \ 7074 sysctl_handle_t4_reg64, "QU", desc) 7075 7076 /* We get these from port_stats and they may be stale by up to 1s */ 7077 #define T4_PORTSTAT(name, desc) \ 7078 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 7079 &pi->stats.name, desc) 7080 7081 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames"); 7082 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames"); 7083 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames"); 7084 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames"); 7085 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames"); 7086 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames"); 7087 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range"); 7088 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range"); 7089 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range"); 7090 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range"); 7091 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range"); 7092 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range"); 7093 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range"); 7094 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames"); 7095 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted"); 7096 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted"); 7097 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted"); 7098 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted"); 7099 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted"); 7100 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted"); 7101 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted"); 7102 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted"); 7103 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted"); 7104 7105 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames"); 7106 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames"); 7107 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames"); 7108 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames"); 7109 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames"); 7110 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU"); 7111 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames"); 7112 if (is_t6(sc)) { 7113 T4_PORTSTAT(rx_fcs_err, 7114 "# of frames received with bad FCS since last link up"); 7115 } else { 7116 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR, 7117 "# of frames received with bad FCS"); 7118 } 7119 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error"); 7120 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors"); 7121 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received"); 7122 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range"); 7123 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range"); 7124 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range"); 7125 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range"); 7126 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range"); 7127 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range"); 7128 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range"); 7129 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received"); 7130 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received"); 7131 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received"); 7132 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received"); 7133 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received"); 7134 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received"); 7135 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received"); 7136 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received"); 7137 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received"); 7138 7139 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows"); 7140 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows"); 7141 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows"); 7142 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows"); 7143 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets"); 7144 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets"); 7145 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets"); 7146 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets"); 7147 7148 #undef T4_REGSTAT 7149 #undef T4_PORTSTAT 7150 7151 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_toe_tls_records", 7152 CTLFLAG_RD, &pi->tx_toe_tls_records, 7153 "# of TOE TLS records transmitted"); 7154 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_toe_tls_octets", 7155 CTLFLAG_RD, &pi->tx_toe_tls_octets, 7156 "# of payload octets in transmitted TOE TLS records"); 7157 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_toe_tls_records", 7158 CTLFLAG_RD, &pi->rx_toe_tls_records, 7159 "# of TOE TLS records received"); 7160 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_toe_tls_octets", 7161 CTLFLAG_RD, &pi->rx_toe_tls_octets, 7162 "# of payload octets in received TOE TLS records"); 7163 } 7164 7165 static int 7166 sysctl_int_array(SYSCTL_HANDLER_ARGS) 7167 { 7168 int rc, *i, space = 0; 7169 struct sbuf sb; 7170 7171 sbuf_new_for_sysctl(&sb, NULL, 64, req); 7172 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 7173 if (space) 7174 sbuf_printf(&sb, " "); 7175 sbuf_printf(&sb, "%d", *i); 7176 space = 1; 7177 } 7178 rc = sbuf_finish(&sb); 7179 sbuf_delete(&sb); 7180 return (rc); 7181 } 7182 7183 static int 7184 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 7185 { 7186 int rc; 7187 struct sbuf *sb; 7188 7189 rc = sysctl_wire_old_buffer(req, 0); 7190 if (rc != 0) 7191 return(rc); 7192 7193 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7194 if (sb == NULL) 7195 return (ENOMEM); 7196 7197 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 7198 rc = sbuf_finish(sb); 7199 sbuf_delete(sb); 7200 7201 return (rc); 7202 } 7203 7204 static int 7205 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 7206 { 7207 int rc; 7208 struct sbuf *sb; 7209 7210 rc = sysctl_wire_old_buffer(req, 0); 7211 if (rc != 0) 7212 return(rc); 7213 7214 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7215 if (sb == NULL) 7216 return (ENOMEM); 7217 7218 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 7219 rc = sbuf_finish(sb); 7220 sbuf_delete(sb); 7221 7222 return (rc); 7223 } 7224 7225 static int 7226 sysctl_btphy(SYSCTL_HANDLER_ARGS) 7227 { 7228 struct port_info *pi = arg1; 7229 int op = arg2; 7230 struct adapter *sc = pi->adapter; 7231 u_int v; 7232 int rc; 7233 7234 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 7235 if (rc) 7236 return (rc); 7237 /* XXX: magic numbers */ 7238 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 7239 &v); 7240 end_synchronized_op(sc, 0); 7241 if (rc) 7242 return (rc); 7243 if (op == 0) 7244 v /= 256; 7245 7246 rc = sysctl_handle_int(oidp, &v, 0, req); 7247 return (rc); 7248 } 7249 7250 static int 7251 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 7252 { 7253 struct vi_info *vi = arg1; 7254 int rc, val; 7255 7256 val = vi->rsrv_noflowq; 7257 rc = sysctl_handle_int(oidp, &val, 0, req); 7258 if (rc != 0 || req->newptr == NULL) 7259 return (rc); 7260 7261 if ((val >= 1) && (vi->ntxq > 1)) 7262 vi->rsrv_noflowq = 1; 7263 else 7264 vi->rsrv_noflowq = 0; 7265 7266 return (rc); 7267 } 7268 7269 static int 7270 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS) 7271 { 7272 struct vi_info *vi = arg1; 7273 struct adapter *sc = vi->adapter; 7274 int rc, val, i; 7275 7276 MPASS(!(sc->flags & IS_VF)); 7277 7278 val = vi->flags & TX_USES_VM_WR ? 1 : 0; 7279 rc = sysctl_handle_int(oidp, &val, 0, req); 7280 if (rc != 0 || req->newptr == NULL) 7281 return (rc); 7282 7283 if (val != 0 && val != 1) 7284 return (EINVAL); 7285 7286 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 7287 "t4txvm"); 7288 if (rc) 7289 return (rc); 7290 if (vi->ifp->if_drv_flags & IFF_DRV_RUNNING) { 7291 /* 7292 * We don't want parse_pkt to run with one setting (VF or PF) 7293 * and then eth_tx to see a different setting but still use 7294 * stale information calculated by parse_pkt. 7295 */ 7296 rc = EBUSY; 7297 } else { 7298 struct port_info *pi = vi->pi; 7299 struct sge_txq *txq; 7300 uint32_t ctrl0; 7301 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr; 7302 7303 if (val) { 7304 vi->flags |= TX_USES_VM_WR; 7305 vi->ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_VM_TSO; 7306 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 7307 V_TXPKT_INTF(pi->tx_chan)); 7308 if (!(sc->flags & IS_VF)) 7309 npkt--; 7310 } else { 7311 vi->flags &= ~TX_USES_VM_WR; 7312 vi->ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 7313 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 7314 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 7315 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 7316 } 7317 for_each_txq(vi, i, txq) { 7318 txq->cpl_ctrl0 = ctrl0; 7319 txq->txp.max_npkt = npkt; 7320 } 7321 } 7322 end_synchronized_op(sc, LOCK_HELD); 7323 return (rc); 7324 } 7325 7326 static int 7327 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 7328 { 7329 struct vi_info *vi = arg1; 7330 struct adapter *sc = vi->adapter; 7331 int idx, rc, i; 7332 struct sge_rxq *rxq; 7333 uint8_t v; 7334 7335 idx = vi->tmr_idx; 7336 7337 rc = sysctl_handle_int(oidp, &idx, 0, req); 7338 if (rc != 0 || req->newptr == NULL) 7339 return (rc); 7340 7341 if (idx < 0 || idx >= SGE_NTIMERS) 7342 return (EINVAL); 7343 7344 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 7345 "t4tmr"); 7346 if (rc) 7347 return (rc); 7348 7349 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 7350 for_each_rxq(vi, i, rxq) { 7351 #ifdef atomic_store_rel_8 7352 atomic_store_rel_8(&rxq->iq.intr_params, v); 7353 #else 7354 rxq->iq.intr_params = v; 7355 #endif 7356 } 7357 vi->tmr_idx = idx; 7358 7359 end_synchronized_op(sc, LOCK_HELD); 7360 return (0); 7361 } 7362 7363 static int 7364 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 7365 { 7366 struct vi_info *vi = arg1; 7367 struct adapter *sc = vi->adapter; 7368 int idx, rc; 7369 7370 idx = vi->pktc_idx; 7371 7372 rc = sysctl_handle_int(oidp, &idx, 0, req); 7373 if (rc != 0 || req->newptr == NULL) 7374 return (rc); 7375 7376 if (idx < -1 || idx >= SGE_NCOUNTERS) 7377 return (EINVAL); 7378 7379 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 7380 "t4pktc"); 7381 if (rc) 7382 return (rc); 7383 7384 if (vi->flags & VI_INIT_DONE) 7385 rc = EBUSY; /* cannot be changed once the queues are created */ 7386 else 7387 vi->pktc_idx = idx; 7388 7389 end_synchronized_op(sc, LOCK_HELD); 7390 return (rc); 7391 } 7392 7393 static int 7394 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 7395 { 7396 struct vi_info *vi = arg1; 7397 struct adapter *sc = vi->adapter; 7398 int qsize, rc; 7399 7400 qsize = vi->qsize_rxq; 7401 7402 rc = sysctl_handle_int(oidp, &qsize, 0, req); 7403 if (rc != 0 || req->newptr == NULL) 7404 return (rc); 7405 7406 if (qsize < 128 || (qsize & 7)) 7407 return (EINVAL); 7408 7409 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 7410 "t4rxqs"); 7411 if (rc) 7412 return (rc); 7413 7414 if (vi->flags & VI_INIT_DONE) 7415 rc = EBUSY; /* cannot be changed once the queues are created */ 7416 else 7417 vi->qsize_rxq = qsize; 7418 7419 end_synchronized_op(sc, LOCK_HELD); 7420 return (rc); 7421 } 7422 7423 static int 7424 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 7425 { 7426 struct vi_info *vi = arg1; 7427 struct adapter *sc = vi->adapter; 7428 int qsize, rc; 7429 7430 qsize = vi->qsize_txq; 7431 7432 rc = sysctl_handle_int(oidp, &qsize, 0, req); 7433 if (rc != 0 || req->newptr == NULL) 7434 return (rc); 7435 7436 if (qsize < 128 || qsize > 65536) 7437 return (EINVAL); 7438 7439 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 7440 "t4txqs"); 7441 if (rc) 7442 return (rc); 7443 7444 if (vi->flags & VI_INIT_DONE) 7445 rc = EBUSY; /* cannot be changed once the queues are created */ 7446 else 7447 vi->qsize_txq = qsize; 7448 7449 end_synchronized_op(sc, LOCK_HELD); 7450 return (rc); 7451 } 7452 7453 static int 7454 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 7455 { 7456 struct port_info *pi = arg1; 7457 struct adapter *sc = pi->adapter; 7458 struct link_config *lc = &pi->link_cfg; 7459 int rc; 7460 7461 if (req->newptr == NULL) { 7462 struct sbuf *sb; 7463 static char *bits = "\20\1RX\2TX\3AUTO"; 7464 7465 rc = sysctl_wire_old_buffer(req, 0); 7466 if (rc != 0) 7467 return(rc); 7468 7469 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7470 if (sb == NULL) 7471 return (ENOMEM); 7472 7473 if (lc->link_ok) { 7474 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 7475 (lc->requested_fc & PAUSE_AUTONEG), bits); 7476 } else { 7477 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 7478 PAUSE_RX | PAUSE_AUTONEG), bits); 7479 } 7480 rc = sbuf_finish(sb); 7481 sbuf_delete(sb); 7482 } else { 7483 char s[2]; 7484 int n; 7485 7486 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 7487 PAUSE_AUTONEG)); 7488 s[1] = 0; 7489 7490 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 7491 if (rc != 0) 7492 return(rc); 7493 7494 if (s[1] != 0) 7495 return (EINVAL); 7496 if (s[0] < '0' || s[0] > '9') 7497 return (EINVAL); /* not a number */ 7498 n = s[0] - '0'; 7499 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 7500 return (EINVAL); /* some other bit is set too */ 7501 7502 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7503 "t4PAUSE"); 7504 if (rc) 7505 return (rc); 7506 PORT_LOCK(pi); 7507 lc->requested_fc = n; 7508 fixup_link_config(pi); 7509 if (pi->up_vis > 0) 7510 rc = apply_link_config(pi); 7511 set_current_media(pi); 7512 PORT_UNLOCK(pi); 7513 end_synchronized_op(sc, 0); 7514 } 7515 7516 return (rc); 7517 } 7518 7519 static int 7520 sysctl_fec(SYSCTL_HANDLER_ARGS) 7521 { 7522 struct port_info *pi = arg1; 7523 struct adapter *sc = pi->adapter; 7524 struct link_config *lc = &pi->link_cfg; 7525 int rc; 7526 int8_t old; 7527 7528 if (req->newptr == NULL) { 7529 struct sbuf *sb; 7530 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2" 7531 "\5RSVD3\6auto\7module"; 7532 7533 rc = sysctl_wire_old_buffer(req, 0); 7534 if (rc != 0) 7535 return(rc); 7536 7537 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7538 if (sb == NULL) 7539 return (ENOMEM); 7540 7541 /* 7542 * Display the requested_fec when the link is down -- the actual 7543 * FEC makes sense only when the link is up. 7544 */ 7545 if (lc->link_ok) { 7546 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) | 7547 (lc->requested_fec & (FEC_AUTO | FEC_MODULE)), 7548 bits); 7549 } else { 7550 sbuf_printf(sb, "%b", lc->requested_fec, bits); 7551 } 7552 rc = sbuf_finish(sb); 7553 sbuf_delete(sb); 7554 } else { 7555 char s[8]; 7556 int n; 7557 7558 snprintf(s, sizeof(s), "%d", 7559 lc->requested_fec == FEC_AUTO ? -1 : 7560 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE)); 7561 7562 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 7563 if (rc != 0) 7564 return(rc); 7565 7566 n = strtol(&s[0], NULL, 0); 7567 if (n < 0 || n & FEC_AUTO) 7568 n = FEC_AUTO; 7569 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE)) 7570 return (EINVAL);/* some other bit is set too */ 7571 7572 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7573 "t4fec"); 7574 if (rc) 7575 return (rc); 7576 PORT_LOCK(pi); 7577 old = lc->requested_fec; 7578 if (n == FEC_AUTO) 7579 lc->requested_fec = FEC_AUTO; 7580 else if (n == 0 || n == FEC_NONE) 7581 lc->requested_fec = FEC_NONE; 7582 else { 7583 if ((lc->pcaps | 7584 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) != 7585 lc->pcaps) { 7586 rc = ENOTSUP; 7587 goto done; 7588 } 7589 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC | 7590 FEC_MODULE); 7591 } 7592 fixup_link_config(pi); 7593 if (pi->up_vis > 0) { 7594 rc = apply_link_config(pi); 7595 if (rc != 0) { 7596 lc->requested_fec = old; 7597 if (rc == FW_EPROTO) 7598 rc = ENOTSUP; 7599 } 7600 } 7601 done: 7602 PORT_UNLOCK(pi); 7603 end_synchronized_op(sc, 0); 7604 } 7605 7606 return (rc); 7607 } 7608 7609 static int 7610 sysctl_module_fec(SYSCTL_HANDLER_ARGS) 7611 { 7612 struct port_info *pi = arg1; 7613 struct adapter *sc = pi->adapter; 7614 struct link_config *lc = &pi->link_cfg; 7615 int rc; 7616 int8_t fec; 7617 struct sbuf *sb; 7618 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3"; 7619 7620 rc = sysctl_wire_old_buffer(req, 0); 7621 if (rc != 0) 7622 return (rc); 7623 7624 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7625 if (sb == NULL) 7626 return (ENOMEM); 7627 7628 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) 7629 return (EBUSY); 7630 PORT_LOCK(pi); 7631 if (pi->up_vis == 0) { 7632 /* 7633 * If all the interfaces are administratively down the firmware 7634 * does not report transceiver changes. Refresh port info here. 7635 * This is the only reason we have a synchronized op in this 7636 * function. Just PORT_LOCK would have been enough otherwise. 7637 */ 7638 t4_update_port_info(pi); 7639 } 7640 7641 fec = lc->fec_hint; 7642 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE || 7643 !fec_supported(lc->pcaps)) { 7644 sbuf_printf(sb, "n/a"); 7645 } else { 7646 if (fec == 0) 7647 fec = FEC_NONE; 7648 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits); 7649 } 7650 rc = sbuf_finish(sb); 7651 sbuf_delete(sb); 7652 7653 PORT_UNLOCK(pi); 7654 end_synchronized_op(sc, 0); 7655 7656 return (rc); 7657 } 7658 7659 static int 7660 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 7661 { 7662 struct port_info *pi = arg1; 7663 struct adapter *sc = pi->adapter; 7664 struct link_config *lc = &pi->link_cfg; 7665 int rc, val; 7666 7667 if (lc->pcaps & FW_PORT_CAP32_ANEG) 7668 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 7669 else 7670 val = -1; 7671 rc = sysctl_handle_int(oidp, &val, 0, req); 7672 if (rc != 0 || req->newptr == NULL) 7673 return (rc); 7674 if (val == 0) 7675 val = AUTONEG_DISABLE; 7676 else if (val == 1) 7677 val = AUTONEG_ENABLE; 7678 else 7679 val = AUTONEG_AUTO; 7680 7681 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7682 "t4aneg"); 7683 if (rc) 7684 return (rc); 7685 PORT_LOCK(pi); 7686 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 7687 rc = ENOTSUP; 7688 goto done; 7689 } 7690 lc->requested_aneg = val; 7691 fixup_link_config(pi); 7692 if (pi->up_vis > 0) 7693 rc = apply_link_config(pi); 7694 set_current_media(pi); 7695 done: 7696 PORT_UNLOCK(pi); 7697 end_synchronized_op(sc, 0); 7698 return (rc); 7699 } 7700 7701 static int 7702 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 7703 { 7704 struct adapter *sc = arg1; 7705 int reg = arg2; 7706 uint64_t val; 7707 7708 val = t4_read_reg64(sc, reg); 7709 7710 return (sysctl_handle_64(oidp, &val, 0, req)); 7711 } 7712 7713 static int 7714 sysctl_temperature(SYSCTL_HANDLER_ARGS) 7715 { 7716 struct adapter *sc = arg1; 7717 int rc, t; 7718 uint32_t param, val; 7719 7720 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 7721 if (rc) 7722 return (rc); 7723 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7724 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7725 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 7726 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7727 end_synchronized_op(sc, 0); 7728 if (rc) 7729 return (rc); 7730 7731 /* unknown is returned as 0 but we display -1 in that case */ 7732 t = val == 0 ? -1 : val; 7733 7734 rc = sysctl_handle_int(oidp, &t, 0, req); 7735 return (rc); 7736 } 7737 7738 static int 7739 sysctl_vdd(SYSCTL_HANDLER_ARGS) 7740 { 7741 struct adapter *sc = arg1; 7742 int rc; 7743 uint32_t param, val; 7744 7745 if (sc->params.core_vdd == 0) { 7746 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7747 "t4vdd"); 7748 if (rc) 7749 return (rc); 7750 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7751 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7752 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 7753 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7754 end_synchronized_op(sc, 0); 7755 if (rc) 7756 return (rc); 7757 sc->params.core_vdd = val; 7758 } 7759 7760 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req)); 7761 } 7762 7763 static int 7764 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS) 7765 { 7766 struct adapter *sc = arg1; 7767 int rc, v; 7768 uint32_t param, val; 7769 7770 v = sc->sensor_resets; 7771 rc = sysctl_handle_int(oidp, &v, 0, req); 7772 if (rc != 0 || req->newptr == NULL || v <= 0) 7773 return (rc); 7774 7775 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) || 7776 chip_id(sc) < CHELSIO_T5) 7777 return (ENOTSUP); 7778 7779 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst"); 7780 if (rc) 7781 return (rc); 7782 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7783 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7784 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR)); 7785 val = 1; 7786 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7787 end_synchronized_op(sc, 0); 7788 if (rc == 0) 7789 sc->sensor_resets++; 7790 return (rc); 7791 } 7792 7793 static int 7794 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 7795 { 7796 struct adapter *sc = arg1; 7797 struct sbuf *sb; 7798 int rc; 7799 uint32_t param, val; 7800 7801 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 7802 if (rc) 7803 return (rc); 7804 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7805 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 7806 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7807 end_synchronized_op(sc, 0); 7808 if (rc) 7809 return (rc); 7810 7811 rc = sysctl_wire_old_buffer(req, 0); 7812 if (rc != 0) 7813 return (rc); 7814 7815 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7816 if (sb == NULL) 7817 return (ENOMEM); 7818 7819 if (val == 0xffffffff) { 7820 /* Only debug and custom firmwares report load averages. */ 7821 sbuf_printf(sb, "not available"); 7822 } else { 7823 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 7824 (val >> 16) & 0xff); 7825 } 7826 rc = sbuf_finish(sb); 7827 sbuf_delete(sb); 7828 7829 return (rc); 7830 } 7831 7832 static int 7833 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 7834 { 7835 struct adapter *sc = arg1; 7836 struct sbuf *sb; 7837 int rc, i; 7838 uint16_t incr[NMTUS][NCCTRL_WIN]; 7839 static const char *dec_fac[] = { 7840 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 7841 "0.9375" 7842 }; 7843 7844 rc = sysctl_wire_old_buffer(req, 0); 7845 if (rc != 0) 7846 return (rc); 7847 7848 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7849 if (sb == NULL) 7850 return (ENOMEM); 7851 7852 t4_read_cong_tbl(sc, incr); 7853 7854 for (i = 0; i < NCCTRL_WIN; ++i) { 7855 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 7856 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 7857 incr[5][i], incr[6][i], incr[7][i]); 7858 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 7859 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 7860 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 7861 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 7862 } 7863 7864 rc = sbuf_finish(sb); 7865 sbuf_delete(sb); 7866 7867 return (rc); 7868 } 7869 7870 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 7871 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 7872 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 7873 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 7874 }; 7875 7876 static int 7877 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 7878 { 7879 struct adapter *sc = arg1; 7880 struct sbuf *sb; 7881 int rc, i, n, qid = arg2; 7882 uint32_t *buf, *p; 7883 char *qtype; 7884 u_int cim_num_obq = sc->chip_params->cim_num_obq; 7885 7886 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 7887 ("%s: bad qid %d\n", __func__, qid)); 7888 7889 if (qid < CIM_NUM_IBQ) { 7890 /* inbound queue */ 7891 qtype = "IBQ"; 7892 n = 4 * CIM_IBQ_SIZE; 7893 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7894 rc = t4_read_cim_ibq(sc, qid, buf, n); 7895 } else { 7896 /* outbound queue */ 7897 qtype = "OBQ"; 7898 qid -= CIM_NUM_IBQ; 7899 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 7900 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7901 rc = t4_read_cim_obq(sc, qid, buf, n); 7902 } 7903 7904 if (rc < 0) { 7905 rc = -rc; 7906 goto done; 7907 } 7908 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 7909 7910 rc = sysctl_wire_old_buffer(req, 0); 7911 if (rc != 0) 7912 goto done; 7913 7914 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7915 if (sb == NULL) { 7916 rc = ENOMEM; 7917 goto done; 7918 } 7919 7920 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 7921 for (i = 0, p = buf; i < n; i += 16, p += 4) 7922 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 7923 p[2], p[3]); 7924 7925 rc = sbuf_finish(sb); 7926 sbuf_delete(sb); 7927 done: 7928 free(buf, M_CXGBE); 7929 return (rc); 7930 } 7931 7932 static void 7933 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7934 { 7935 uint32_t *p; 7936 7937 sbuf_printf(sb, "Status Data PC%s", 7938 cfg & F_UPDBGLACAPTPCONLY ? "" : 7939 " LS0Stat LS0Addr LS0Data"); 7940 7941 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 7942 if (cfg & F_UPDBGLACAPTPCONLY) { 7943 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 7944 p[6], p[7]); 7945 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 7946 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 7947 p[4] & 0xff, p[5] >> 8); 7948 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 7949 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7950 p[1] & 0xf, p[2] >> 4); 7951 } else { 7952 sbuf_printf(sb, 7953 "\n %02x %x%07x %x%07x %08x %08x " 7954 "%08x%08x%08x%08x", 7955 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7956 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 7957 p[6], p[7]); 7958 } 7959 } 7960 } 7961 7962 static void 7963 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7964 { 7965 uint32_t *p; 7966 7967 sbuf_printf(sb, "Status Inst Data PC%s", 7968 cfg & F_UPDBGLACAPTPCONLY ? "" : 7969 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 7970 7971 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 7972 if (cfg & F_UPDBGLACAPTPCONLY) { 7973 sbuf_printf(sb, "\n %02x %08x %08x %08x", 7974 p[3] & 0xff, p[2], p[1], p[0]); 7975 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 7976 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 7977 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 7978 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 7979 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 7980 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 7981 p[6] >> 16); 7982 } else { 7983 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 7984 "%08x %08x %08x %08x %08x %08x", 7985 (p[9] >> 16) & 0xff, 7986 p[9] & 0xffff, p[8] >> 16, 7987 p[8] & 0xffff, p[7] >> 16, 7988 p[7] & 0xffff, p[6] >> 16, 7989 p[2], p[1], p[0], p[5], p[4], p[3]); 7990 } 7991 } 7992 } 7993 7994 static int 7995 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 7996 { 7997 uint32_t cfg, *buf; 7998 int rc; 7999 8000 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 8001 if (rc != 0) 8002 return (rc); 8003 8004 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 8005 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 8006 M_ZERO | flags); 8007 if (buf == NULL) 8008 return (ENOMEM); 8009 8010 rc = -t4_cim_read_la(sc, buf, NULL); 8011 if (rc != 0) 8012 goto done; 8013 if (chip_id(sc) < CHELSIO_T6) 8014 sbuf_cim_la4(sc, sb, buf, cfg); 8015 else 8016 sbuf_cim_la6(sc, sb, buf, cfg); 8017 8018 done: 8019 free(buf, M_CXGBE); 8020 return (rc); 8021 } 8022 8023 static int 8024 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 8025 { 8026 struct adapter *sc = arg1; 8027 struct sbuf *sb; 8028 int rc; 8029 8030 rc = sysctl_wire_old_buffer(req, 0); 8031 if (rc != 0) 8032 return (rc); 8033 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8034 if (sb == NULL) 8035 return (ENOMEM); 8036 8037 rc = sbuf_cim_la(sc, sb, M_WAITOK); 8038 if (rc == 0) 8039 rc = sbuf_finish(sb); 8040 sbuf_delete(sb); 8041 return (rc); 8042 } 8043 8044 bool 8045 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose) 8046 { 8047 struct sbuf sb; 8048 int rc; 8049 8050 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 8051 return (false); 8052 rc = sbuf_cim_la(sc, &sb, M_NOWAIT); 8053 if (rc == 0) { 8054 rc = sbuf_finish(&sb); 8055 if (rc == 0) { 8056 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s", 8057 device_get_nameunit(sc->dev), sbuf_data(&sb)); 8058 } 8059 } 8060 sbuf_delete(&sb); 8061 return (false); 8062 } 8063 8064 static int 8065 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 8066 { 8067 struct adapter *sc = arg1; 8068 u_int i; 8069 struct sbuf *sb; 8070 uint32_t *buf, *p; 8071 int rc; 8072 8073 rc = sysctl_wire_old_buffer(req, 0); 8074 if (rc != 0) 8075 return (rc); 8076 8077 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8078 if (sb == NULL) 8079 return (ENOMEM); 8080 8081 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 8082 M_ZERO | M_WAITOK); 8083 8084 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 8085 p = buf; 8086 8087 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 8088 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 8089 p[1], p[0]); 8090 } 8091 8092 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 8093 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 8094 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 8095 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 8096 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 8097 (p[1] >> 2) | ((p[2] & 3) << 30), 8098 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 8099 p[0] & 1); 8100 } 8101 8102 rc = sbuf_finish(sb); 8103 sbuf_delete(sb); 8104 free(buf, M_CXGBE); 8105 return (rc); 8106 } 8107 8108 static int 8109 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 8110 { 8111 struct adapter *sc = arg1; 8112 u_int i; 8113 struct sbuf *sb; 8114 uint32_t *buf, *p; 8115 int rc; 8116 8117 rc = sysctl_wire_old_buffer(req, 0); 8118 if (rc != 0) 8119 return (rc); 8120 8121 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8122 if (sb == NULL) 8123 return (ENOMEM); 8124 8125 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 8126 M_ZERO | M_WAITOK); 8127 8128 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 8129 p = buf; 8130 8131 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 8132 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 8133 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 8134 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 8135 p[4], p[3], p[2], p[1], p[0]); 8136 } 8137 8138 sbuf_printf(sb, "\n\nCntl ID Data"); 8139 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 8140 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 8141 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 8142 } 8143 8144 rc = sbuf_finish(sb); 8145 sbuf_delete(sb); 8146 free(buf, M_CXGBE); 8147 return (rc); 8148 } 8149 8150 static int 8151 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 8152 { 8153 struct adapter *sc = arg1; 8154 struct sbuf *sb; 8155 int rc, i; 8156 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 8157 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 8158 uint16_t thres[CIM_NUM_IBQ]; 8159 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 8160 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 8161 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 8162 8163 cim_num_obq = sc->chip_params->cim_num_obq; 8164 if (is_t4(sc)) { 8165 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 8166 obq_rdaddr = A_UP_OBQ_0_REALADDR; 8167 } else { 8168 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 8169 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 8170 } 8171 nq = CIM_NUM_IBQ + cim_num_obq; 8172 8173 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 8174 if (rc == 0) 8175 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 8176 if (rc != 0) 8177 return (rc); 8178 8179 t4_read_cimq_cfg(sc, base, size, thres); 8180 8181 rc = sysctl_wire_old_buffer(req, 0); 8182 if (rc != 0) 8183 return (rc); 8184 8185 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 8186 if (sb == NULL) 8187 return (ENOMEM); 8188 8189 sbuf_printf(sb, 8190 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 8191 8192 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 8193 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 8194 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 8195 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 8196 G_QUEREMFLITS(p[2]) * 16); 8197 for ( ; i < nq; i++, p += 4, wr += 2) 8198 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 8199 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 8200 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 8201 G_QUEREMFLITS(p[2]) * 16); 8202 8203 rc = sbuf_finish(sb); 8204 sbuf_delete(sb); 8205 8206 return (rc); 8207 } 8208 8209 static int 8210 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 8211 { 8212 struct adapter *sc = arg1; 8213 struct sbuf *sb; 8214 int rc; 8215 struct tp_cpl_stats stats; 8216 8217 rc = sysctl_wire_old_buffer(req, 0); 8218 if (rc != 0) 8219 return (rc); 8220 8221 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8222 if (sb == NULL) 8223 return (ENOMEM); 8224 8225 mtx_lock(&sc->reg_lock); 8226 t4_tp_get_cpl_stats(sc, &stats, 0); 8227 mtx_unlock(&sc->reg_lock); 8228 8229 if (sc->chip_params->nchan > 2) { 8230 sbuf_printf(sb, " channel 0 channel 1" 8231 " channel 2 channel 3"); 8232 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 8233 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 8234 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 8235 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 8236 } else { 8237 sbuf_printf(sb, " channel 0 channel 1"); 8238 sbuf_printf(sb, "\nCPL requests: %10u %10u", 8239 stats.req[0], stats.req[1]); 8240 sbuf_printf(sb, "\nCPL responses: %10u %10u", 8241 stats.rsp[0], stats.rsp[1]); 8242 } 8243 8244 rc = sbuf_finish(sb); 8245 sbuf_delete(sb); 8246 8247 return (rc); 8248 } 8249 8250 static int 8251 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 8252 { 8253 struct adapter *sc = arg1; 8254 struct sbuf *sb; 8255 int rc; 8256 struct tp_usm_stats stats; 8257 8258 rc = sysctl_wire_old_buffer(req, 0); 8259 if (rc != 0) 8260 return(rc); 8261 8262 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8263 if (sb == NULL) 8264 return (ENOMEM); 8265 8266 t4_get_usm_stats(sc, &stats, 1); 8267 8268 sbuf_printf(sb, "Frames: %u\n", stats.frames); 8269 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 8270 sbuf_printf(sb, "Drops: %u", stats.drops); 8271 8272 rc = sbuf_finish(sb); 8273 sbuf_delete(sb); 8274 8275 return (rc); 8276 } 8277 8278 static const char * const devlog_level_strings[] = { 8279 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 8280 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 8281 [FW_DEVLOG_LEVEL_ERR] = "ERR", 8282 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 8283 [FW_DEVLOG_LEVEL_INFO] = "INFO", 8284 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 8285 }; 8286 8287 static const char * const devlog_facility_strings[] = { 8288 [FW_DEVLOG_FACILITY_CORE] = "CORE", 8289 [FW_DEVLOG_FACILITY_CF] = "CF", 8290 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 8291 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 8292 [FW_DEVLOG_FACILITY_RES] = "RES", 8293 [FW_DEVLOG_FACILITY_HW] = "HW", 8294 [FW_DEVLOG_FACILITY_FLR] = "FLR", 8295 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 8296 [FW_DEVLOG_FACILITY_PHY] = "PHY", 8297 [FW_DEVLOG_FACILITY_MAC] = "MAC", 8298 [FW_DEVLOG_FACILITY_PORT] = "PORT", 8299 [FW_DEVLOG_FACILITY_VI] = "VI", 8300 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 8301 [FW_DEVLOG_FACILITY_ACL] = "ACL", 8302 [FW_DEVLOG_FACILITY_TM] = "TM", 8303 [FW_DEVLOG_FACILITY_QFC] = "QFC", 8304 [FW_DEVLOG_FACILITY_DCB] = "DCB", 8305 [FW_DEVLOG_FACILITY_ETH] = "ETH", 8306 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 8307 [FW_DEVLOG_FACILITY_RI] = "RI", 8308 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 8309 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 8310 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 8311 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 8312 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 8313 }; 8314 8315 static int 8316 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 8317 { 8318 int i, j, rc, nentries, first = 0; 8319 struct devlog_params *dparams = &sc->params.devlog; 8320 struct fw_devlog_e *buf, *e; 8321 uint64_t ftstamp = UINT64_MAX; 8322 8323 if (dparams->addr == 0) 8324 return (ENXIO); 8325 8326 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 8327 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 8328 if (buf == NULL) 8329 return (ENOMEM); 8330 8331 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 8332 if (rc != 0) 8333 goto done; 8334 8335 nentries = dparams->size / sizeof(struct fw_devlog_e); 8336 for (i = 0; i < nentries; i++) { 8337 e = &buf[i]; 8338 8339 if (e->timestamp == 0) 8340 break; /* end */ 8341 8342 e->timestamp = be64toh(e->timestamp); 8343 e->seqno = be32toh(e->seqno); 8344 for (j = 0; j < 8; j++) 8345 e->params[j] = be32toh(e->params[j]); 8346 8347 if (e->timestamp < ftstamp) { 8348 ftstamp = e->timestamp; 8349 first = i; 8350 } 8351 } 8352 8353 if (buf[first].timestamp == 0) 8354 goto done; /* nothing in the log */ 8355 8356 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 8357 "Seq#", "Tstamp", "Level", "Facility", "Message"); 8358 8359 i = first; 8360 do { 8361 e = &buf[i]; 8362 if (e->timestamp == 0) 8363 break; /* end */ 8364 8365 sbuf_printf(sb, "%10d %15ju %8s %8s ", 8366 e->seqno, e->timestamp, 8367 (e->level < nitems(devlog_level_strings) ? 8368 devlog_level_strings[e->level] : "UNKNOWN"), 8369 (e->facility < nitems(devlog_facility_strings) ? 8370 devlog_facility_strings[e->facility] : "UNKNOWN")); 8371 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 8372 e->params[2], e->params[3], e->params[4], 8373 e->params[5], e->params[6], e->params[7]); 8374 8375 if (++i == nentries) 8376 i = 0; 8377 } while (i != first); 8378 done: 8379 free(buf, M_CXGBE); 8380 return (rc); 8381 } 8382 8383 static int 8384 sysctl_devlog(SYSCTL_HANDLER_ARGS) 8385 { 8386 struct adapter *sc = arg1; 8387 int rc; 8388 struct sbuf *sb; 8389 8390 rc = sysctl_wire_old_buffer(req, 0); 8391 if (rc != 0) 8392 return (rc); 8393 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8394 if (sb == NULL) 8395 return (ENOMEM); 8396 8397 rc = sbuf_devlog(sc, sb, M_WAITOK); 8398 if (rc == 0) 8399 rc = sbuf_finish(sb); 8400 sbuf_delete(sb); 8401 return (rc); 8402 } 8403 8404 void 8405 t4_os_dump_devlog(struct adapter *sc) 8406 { 8407 int rc; 8408 struct sbuf sb; 8409 8410 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 8411 return; 8412 rc = sbuf_devlog(sc, &sb, M_NOWAIT); 8413 if (rc == 0) { 8414 rc = sbuf_finish(&sb); 8415 if (rc == 0) { 8416 log(LOG_DEBUG, "%s: device log follows.\n%s", 8417 device_get_nameunit(sc->dev), sbuf_data(&sb)); 8418 } 8419 } 8420 sbuf_delete(&sb); 8421 } 8422 8423 static int 8424 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 8425 { 8426 struct adapter *sc = arg1; 8427 struct sbuf *sb; 8428 int rc; 8429 struct tp_fcoe_stats stats[MAX_NCHAN]; 8430 int i, nchan = sc->chip_params->nchan; 8431 8432 rc = sysctl_wire_old_buffer(req, 0); 8433 if (rc != 0) 8434 return (rc); 8435 8436 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8437 if (sb == NULL) 8438 return (ENOMEM); 8439 8440 for (i = 0; i < nchan; i++) 8441 t4_get_fcoe_stats(sc, i, &stats[i], 1); 8442 8443 if (nchan > 2) { 8444 sbuf_printf(sb, " channel 0 channel 1" 8445 " channel 2 channel 3"); 8446 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 8447 stats[0].octets_ddp, stats[1].octets_ddp, 8448 stats[2].octets_ddp, stats[3].octets_ddp); 8449 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 8450 stats[0].frames_ddp, stats[1].frames_ddp, 8451 stats[2].frames_ddp, stats[3].frames_ddp); 8452 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 8453 stats[0].frames_drop, stats[1].frames_drop, 8454 stats[2].frames_drop, stats[3].frames_drop); 8455 } else { 8456 sbuf_printf(sb, " channel 0 channel 1"); 8457 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 8458 stats[0].octets_ddp, stats[1].octets_ddp); 8459 sbuf_printf(sb, "\nframesDDP: %16u %16u", 8460 stats[0].frames_ddp, stats[1].frames_ddp); 8461 sbuf_printf(sb, "\nframesDrop: %16u %16u", 8462 stats[0].frames_drop, stats[1].frames_drop); 8463 } 8464 8465 rc = sbuf_finish(sb); 8466 sbuf_delete(sb); 8467 8468 return (rc); 8469 } 8470 8471 static int 8472 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 8473 { 8474 struct adapter *sc = arg1; 8475 struct sbuf *sb; 8476 int rc, i; 8477 unsigned int map, kbps, ipg, mode; 8478 unsigned int pace_tab[NTX_SCHED]; 8479 8480 rc = sysctl_wire_old_buffer(req, 0); 8481 if (rc != 0) 8482 return (rc); 8483 8484 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8485 if (sb == NULL) 8486 return (ENOMEM); 8487 8488 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 8489 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 8490 t4_read_pace_tbl(sc, pace_tab); 8491 8492 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 8493 "Class IPG (0.1 ns) Flow IPG (us)"); 8494 8495 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 8496 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 8497 sbuf_printf(sb, "\n %u %-5s %u ", i, 8498 (mode & (1 << i)) ? "flow" : "class", map & 3); 8499 if (kbps) 8500 sbuf_printf(sb, "%9u ", kbps); 8501 else 8502 sbuf_printf(sb, " disabled "); 8503 8504 if (ipg) 8505 sbuf_printf(sb, "%13u ", ipg); 8506 else 8507 sbuf_printf(sb, " disabled "); 8508 8509 if (pace_tab[i]) 8510 sbuf_printf(sb, "%10u", pace_tab[i]); 8511 else 8512 sbuf_printf(sb, " disabled"); 8513 } 8514 8515 rc = sbuf_finish(sb); 8516 sbuf_delete(sb); 8517 8518 return (rc); 8519 } 8520 8521 static int 8522 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 8523 { 8524 struct adapter *sc = arg1; 8525 struct sbuf *sb; 8526 int rc, i, j; 8527 uint64_t *p0, *p1; 8528 struct lb_port_stats s[2]; 8529 static const char *stat_name[] = { 8530 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 8531 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 8532 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 8533 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 8534 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 8535 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 8536 "BG2FramesTrunc:", "BG3FramesTrunc:" 8537 }; 8538 8539 rc = sysctl_wire_old_buffer(req, 0); 8540 if (rc != 0) 8541 return (rc); 8542 8543 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8544 if (sb == NULL) 8545 return (ENOMEM); 8546 8547 memset(s, 0, sizeof(s)); 8548 8549 for (i = 0; i < sc->chip_params->nchan; i += 2) { 8550 t4_get_lb_stats(sc, i, &s[0]); 8551 t4_get_lb_stats(sc, i + 1, &s[1]); 8552 8553 p0 = &s[0].octets; 8554 p1 = &s[1].octets; 8555 sbuf_printf(sb, "%s Loopback %u" 8556 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 8557 8558 for (j = 0; j < nitems(stat_name); j++) 8559 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 8560 *p0++, *p1++); 8561 } 8562 8563 rc = sbuf_finish(sb); 8564 sbuf_delete(sb); 8565 8566 return (rc); 8567 } 8568 8569 static int 8570 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 8571 { 8572 int rc = 0; 8573 struct port_info *pi = arg1; 8574 struct link_config *lc = &pi->link_cfg; 8575 struct sbuf *sb; 8576 8577 rc = sysctl_wire_old_buffer(req, 0); 8578 if (rc != 0) 8579 return(rc); 8580 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 8581 if (sb == NULL) 8582 return (ENOMEM); 8583 8584 if (lc->link_ok || lc->link_down_rc == 255) 8585 sbuf_printf(sb, "n/a"); 8586 else 8587 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 8588 8589 rc = sbuf_finish(sb); 8590 sbuf_delete(sb); 8591 8592 return (rc); 8593 } 8594 8595 struct mem_desc { 8596 unsigned int base; 8597 unsigned int limit; 8598 unsigned int idx; 8599 }; 8600 8601 static int 8602 mem_desc_cmp(const void *a, const void *b) 8603 { 8604 return ((const struct mem_desc *)a)->base - 8605 ((const struct mem_desc *)b)->base; 8606 } 8607 8608 static void 8609 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 8610 unsigned int to) 8611 { 8612 unsigned int size; 8613 8614 if (from == to) 8615 return; 8616 8617 size = to - from + 1; 8618 if (size == 0) 8619 return; 8620 8621 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 8622 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 8623 } 8624 8625 static int 8626 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 8627 { 8628 struct adapter *sc = arg1; 8629 struct sbuf *sb; 8630 int rc, i, n; 8631 uint32_t lo, hi, used, alloc; 8632 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 8633 static const char *region[] = { 8634 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 8635 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 8636 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 8637 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 8638 "RQUDP region:", "PBL region:", "TXPBL region:", 8639 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 8640 "On-chip queues:", "TLS keys:", 8641 }; 8642 struct mem_desc avail[4]; 8643 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 8644 struct mem_desc *md = mem; 8645 8646 rc = sysctl_wire_old_buffer(req, 0); 8647 if (rc != 0) 8648 return (rc); 8649 8650 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8651 if (sb == NULL) 8652 return (ENOMEM); 8653 8654 for (i = 0; i < nitems(mem); i++) { 8655 mem[i].limit = 0; 8656 mem[i].idx = i; 8657 } 8658 8659 /* Find and sort the populated memory ranges */ 8660 i = 0; 8661 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 8662 if (lo & F_EDRAM0_ENABLE) { 8663 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 8664 avail[i].base = G_EDRAM0_BASE(hi) << 20; 8665 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 8666 avail[i].idx = 0; 8667 i++; 8668 } 8669 if (lo & F_EDRAM1_ENABLE) { 8670 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 8671 avail[i].base = G_EDRAM1_BASE(hi) << 20; 8672 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 8673 avail[i].idx = 1; 8674 i++; 8675 } 8676 if (lo & F_EXT_MEM_ENABLE) { 8677 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 8678 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 8679 avail[i].limit = avail[i].base + 8680 (G_EXT_MEM_SIZE(hi) << 20); 8681 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 8682 i++; 8683 } 8684 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 8685 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 8686 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 8687 avail[i].limit = avail[i].base + 8688 (G_EXT_MEM1_SIZE(hi) << 20); 8689 avail[i].idx = 4; 8690 i++; 8691 } 8692 if (!i) /* no memory available */ 8693 return 0; 8694 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 8695 8696 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 8697 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 8698 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 8699 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 8700 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 8701 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 8702 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 8703 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 8704 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 8705 8706 /* the next few have explicit upper bounds */ 8707 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 8708 md->limit = md->base - 1 + 8709 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 8710 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 8711 md++; 8712 8713 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 8714 md->limit = md->base - 1 + 8715 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 8716 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 8717 md++; 8718 8719 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8720 if (chip_id(sc) <= CHELSIO_T5) 8721 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 8722 else 8723 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 8724 md->limit = 0; 8725 } else { 8726 md->base = 0; 8727 md->idx = nitems(region); /* hide it */ 8728 } 8729 md++; 8730 8731 #define ulp_region(reg) \ 8732 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 8733 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 8734 8735 ulp_region(RX_ISCSI); 8736 ulp_region(RX_TDDP); 8737 ulp_region(TX_TPT); 8738 ulp_region(RX_STAG); 8739 ulp_region(RX_RQ); 8740 ulp_region(RX_RQUDP); 8741 ulp_region(RX_PBL); 8742 ulp_region(TX_PBL); 8743 #undef ulp_region 8744 8745 md->base = 0; 8746 md->idx = nitems(region); 8747 if (!is_t4(sc)) { 8748 uint32_t size = 0; 8749 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 8750 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 8751 8752 if (is_t5(sc)) { 8753 if (sge_ctrl & F_VFIFO_ENABLE) 8754 size = G_DBVFIFO_SIZE(fifo_size); 8755 } else 8756 size = G_T6_DBVFIFO_SIZE(fifo_size); 8757 8758 if (size) { 8759 md->base = G_BASEADDR(t4_read_reg(sc, 8760 A_SGE_DBVFIFO_BADDR)); 8761 md->limit = md->base + (size << 2) - 1; 8762 } 8763 } 8764 md++; 8765 8766 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 8767 md->limit = 0; 8768 md++; 8769 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 8770 md->limit = 0; 8771 md++; 8772 8773 md->base = sc->vres.ocq.start; 8774 if (sc->vres.ocq.size) 8775 md->limit = md->base + sc->vres.ocq.size - 1; 8776 else 8777 md->idx = nitems(region); /* hide it */ 8778 md++; 8779 8780 md->base = sc->vres.key.start; 8781 if (sc->vres.key.size) 8782 md->limit = md->base + sc->vres.key.size - 1; 8783 else 8784 md->idx = nitems(region); /* hide it */ 8785 md++; 8786 8787 /* add any address-space holes, there can be up to 3 */ 8788 for (n = 0; n < i - 1; n++) 8789 if (avail[n].limit < avail[n + 1].base) 8790 (md++)->base = avail[n].limit; 8791 if (avail[n].limit) 8792 (md++)->base = avail[n].limit; 8793 8794 n = md - mem; 8795 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 8796 8797 for (lo = 0; lo < i; lo++) 8798 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 8799 avail[lo].limit - 1); 8800 8801 sbuf_printf(sb, "\n"); 8802 for (i = 0; i < n; i++) { 8803 if (mem[i].idx >= nitems(region)) 8804 continue; /* skip holes */ 8805 if (!mem[i].limit) 8806 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 8807 mem_region_show(sb, region[mem[i].idx], mem[i].base, 8808 mem[i].limit); 8809 } 8810 8811 sbuf_printf(sb, "\n"); 8812 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 8813 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 8814 mem_region_show(sb, "uP RAM:", lo, hi); 8815 8816 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 8817 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 8818 mem_region_show(sb, "uP Extmem2:", lo, hi); 8819 8820 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 8821 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 8822 G_PMRXMAXPAGE(lo), 8823 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 8824 (lo & F_PMRXNUMCHN) ? 2 : 1); 8825 8826 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 8827 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 8828 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 8829 G_PMTXMAXPAGE(lo), 8830 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 8831 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 8832 sbuf_printf(sb, "%u p-structs\n", 8833 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 8834 8835 for (i = 0; i < 4; i++) { 8836 if (chip_id(sc) > CHELSIO_T5) 8837 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 8838 else 8839 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 8840 if (is_t5(sc)) { 8841 used = G_T5_USED(lo); 8842 alloc = G_T5_ALLOC(lo); 8843 } else { 8844 used = G_USED(lo); 8845 alloc = G_ALLOC(lo); 8846 } 8847 /* For T6 these are MAC buffer groups */ 8848 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 8849 i, used, alloc); 8850 } 8851 for (i = 0; i < sc->chip_params->nchan; i++) { 8852 if (chip_id(sc) > CHELSIO_T5) 8853 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 8854 else 8855 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 8856 if (is_t5(sc)) { 8857 used = G_T5_USED(lo); 8858 alloc = G_T5_ALLOC(lo); 8859 } else { 8860 used = G_USED(lo); 8861 alloc = G_ALLOC(lo); 8862 } 8863 /* For T6 these are MAC buffer groups */ 8864 sbuf_printf(sb, 8865 "\nLoopback %d using %u pages out of %u allocated", 8866 i, used, alloc); 8867 } 8868 8869 rc = sbuf_finish(sb); 8870 sbuf_delete(sb); 8871 8872 return (rc); 8873 } 8874 8875 static inline void 8876 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 8877 { 8878 *mask = x | y; 8879 y = htobe64(y); 8880 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 8881 } 8882 8883 static int 8884 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 8885 { 8886 struct adapter *sc = arg1; 8887 struct sbuf *sb; 8888 int rc, i; 8889 8890 MPASS(chip_id(sc) <= CHELSIO_T5); 8891 8892 rc = sysctl_wire_old_buffer(req, 0); 8893 if (rc != 0) 8894 return (rc); 8895 8896 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8897 if (sb == NULL) 8898 return (ENOMEM); 8899 8900 sbuf_printf(sb, 8901 "Idx Ethernet address Mask Vld Ports PF" 8902 " VF Replication P0 P1 P2 P3 ML"); 8903 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8904 uint64_t tcamx, tcamy, mask; 8905 uint32_t cls_lo, cls_hi; 8906 uint8_t addr[ETHER_ADDR_LEN]; 8907 8908 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 8909 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 8910 if (tcamx & tcamy) 8911 continue; 8912 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8913 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8914 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8915 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 8916 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 8917 addr[3], addr[4], addr[5], (uintmax_t)mask, 8918 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 8919 G_PORTMAP(cls_hi), G_PF(cls_lo), 8920 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 8921 8922 if (cls_lo & F_REPLICATE) { 8923 struct fw_ldst_cmd ldst_cmd; 8924 8925 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8926 ldst_cmd.op_to_addrspace = 8927 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8928 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8929 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8930 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8931 ldst_cmd.u.mps.rplc.fid_idx = 8932 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8933 V_FW_LDST_CMD_IDX(i)); 8934 8935 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8936 "t4mps"); 8937 if (rc) 8938 break; 8939 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8940 sizeof(ldst_cmd), &ldst_cmd); 8941 end_synchronized_op(sc, 0); 8942 8943 if (rc != 0) { 8944 sbuf_printf(sb, "%36d", rc); 8945 rc = 0; 8946 } else { 8947 sbuf_printf(sb, " %08x %08x %08x %08x", 8948 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8949 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8950 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8951 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8952 } 8953 } else 8954 sbuf_printf(sb, "%36s", ""); 8955 8956 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 8957 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 8958 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 8959 } 8960 8961 if (rc) 8962 (void) sbuf_finish(sb); 8963 else 8964 rc = sbuf_finish(sb); 8965 sbuf_delete(sb); 8966 8967 return (rc); 8968 } 8969 8970 static int 8971 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 8972 { 8973 struct adapter *sc = arg1; 8974 struct sbuf *sb; 8975 int rc, i; 8976 8977 MPASS(chip_id(sc) > CHELSIO_T5); 8978 8979 rc = sysctl_wire_old_buffer(req, 0); 8980 if (rc != 0) 8981 return (rc); 8982 8983 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8984 if (sb == NULL) 8985 return (ENOMEM); 8986 8987 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 8988 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 8989 " Replication" 8990 " P0 P1 P2 P3 ML\n"); 8991 8992 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8993 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 8994 uint16_t ivlan; 8995 uint64_t tcamx, tcamy, val, mask; 8996 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 8997 uint8_t addr[ETHER_ADDR_LEN]; 8998 8999 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 9000 if (i < 256) 9001 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 9002 else 9003 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 9004 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 9005 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 9006 tcamy = G_DMACH(val) << 32; 9007 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 9008 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 9009 lookup_type = G_DATALKPTYPE(data2); 9010 port_num = G_DATAPORTNUM(data2); 9011 if (lookup_type && lookup_type != M_DATALKPTYPE) { 9012 /* Inner header VNI */ 9013 vniy = ((data2 & F_DATAVIDH2) << 23) | 9014 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 9015 dip_hit = data2 & F_DATADIPHIT; 9016 vlan_vld = 0; 9017 } else { 9018 vniy = 0; 9019 dip_hit = 0; 9020 vlan_vld = data2 & F_DATAVIDH2; 9021 ivlan = G_VIDL(val); 9022 } 9023 9024 ctl |= V_CTLXYBITSEL(1); 9025 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 9026 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 9027 tcamx = G_DMACH(val) << 32; 9028 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 9029 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 9030 if (lookup_type && lookup_type != M_DATALKPTYPE) { 9031 /* Inner header VNI mask */ 9032 vnix = ((data2 & F_DATAVIDH2) << 23) | 9033 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 9034 } else 9035 vnix = 0; 9036 9037 if (tcamx & tcamy) 9038 continue; 9039 tcamxy2valmask(tcamx, tcamy, addr, &mask); 9040 9041 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 9042 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 9043 9044 if (lookup_type && lookup_type != M_DATALKPTYPE) { 9045 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 9046 "%012jx %06x %06x - - %3c" 9047 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 9048 addr[1], addr[2], addr[3], addr[4], addr[5], 9049 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 9050 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 9051 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 9052 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 9053 } else { 9054 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 9055 "%012jx - - ", i, addr[0], addr[1], 9056 addr[2], addr[3], addr[4], addr[5], 9057 (uintmax_t)mask); 9058 9059 if (vlan_vld) 9060 sbuf_printf(sb, "%4u Y ", ivlan); 9061 else 9062 sbuf_printf(sb, " - N "); 9063 9064 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 9065 lookup_type ? 'I' : 'O', port_num, 9066 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 9067 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 9068 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 9069 } 9070 9071 9072 if (cls_lo & F_T6_REPLICATE) { 9073 struct fw_ldst_cmd ldst_cmd; 9074 9075 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 9076 ldst_cmd.op_to_addrspace = 9077 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 9078 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9079 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 9080 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 9081 ldst_cmd.u.mps.rplc.fid_idx = 9082 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 9083 V_FW_LDST_CMD_IDX(i)); 9084 9085 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 9086 "t6mps"); 9087 if (rc) 9088 break; 9089 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 9090 sizeof(ldst_cmd), &ldst_cmd); 9091 end_synchronized_op(sc, 0); 9092 9093 if (rc != 0) { 9094 sbuf_printf(sb, "%72d", rc); 9095 rc = 0; 9096 } else { 9097 sbuf_printf(sb, " %08x %08x %08x %08x" 9098 " %08x %08x %08x %08x", 9099 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 9100 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 9101 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 9102 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 9103 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 9104 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 9105 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 9106 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 9107 } 9108 } else 9109 sbuf_printf(sb, "%72s", ""); 9110 9111 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 9112 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 9113 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 9114 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 9115 } 9116 9117 if (rc) 9118 (void) sbuf_finish(sb); 9119 else 9120 rc = sbuf_finish(sb); 9121 sbuf_delete(sb); 9122 9123 return (rc); 9124 } 9125 9126 static int 9127 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 9128 { 9129 struct adapter *sc = arg1; 9130 struct sbuf *sb; 9131 int rc; 9132 uint16_t mtus[NMTUS]; 9133 9134 rc = sysctl_wire_old_buffer(req, 0); 9135 if (rc != 0) 9136 return (rc); 9137 9138 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9139 if (sb == NULL) 9140 return (ENOMEM); 9141 9142 t4_read_mtu_tbl(sc, mtus, NULL); 9143 9144 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 9145 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 9146 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 9147 mtus[14], mtus[15]); 9148 9149 rc = sbuf_finish(sb); 9150 sbuf_delete(sb); 9151 9152 return (rc); 9153 } 9154 9155 static int 9156 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 9157 { 9158 struct adapter *sc = arg1; 9159 struct sbuf *sb; 9160 int rc, i; 9161 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 9162 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 9163 static const char *tx_stats[MAX_PM_NSTATS] = { 9164 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 9165 "Tx FIFO wait", NULL, "Tx latency" 9166 }; 9167 static const char *rx_stats[MAX_PM_NSTATS] = { 9168 "Read:", "Write bypass:", "Write mem:", "Flush:", 9169 "Rx FIFO wait", NULL, "Rx latency" 9170 }; 9171 9172 rc = sysctl_wire_old_buffer(req, 0); 9173 if (rc != 0) 9174 return (rc); 9175 9176 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9177 if (sb == NULL) 9178 return (ENOMEM); 9179 9180 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 9181 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 9182 9183 sbuf_printf(sb, " Tx pcmds Tx bytes"); 9184 for (i = 0; i < 4; i++) { 9185 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 9186 tx_cyc[i]); 9187 } 9188 9189 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 9190 for (i = 0; i < 4; i++) { 9191 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 9192 rx_cyc[i]); 9193 } 9194 9195 if (chip_id(sc) > CHELSIO_T5) { 9196 sbuf_printf(sb, 9197 "\n Total wait Total occupancy"); 9198 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 9199 tx_cyc[i]); 9200 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 9201 rx_cyc[i]); 9202 9203 i += 2; 9204 MPASS(i < nitems(tx_stats)); 9205 9206 sbuf_printf(sb, 9207 "\n Reads Total wait"); 9208 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 9209 tx_cyc[i]); 9210 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 9211 rx_cyc[i]); 9212 } 9213 9214 rc = sbuf_finish(sb); 9215 sbuf_delete(sb); 9216 9217 return (rc); 9218 } 9219 9220 static int 9221 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 9222 { 9223 struct adapter *sc = arg1; 9224 struct sbuf *sb; 9225 int rc; 9226 struct tp_rdma_stats stats; 9227 9228 rc = sysctl_wire_old_buffer(req, 0); 9229 if (rc != 0) 9230 return (rc); 9231 9232 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9233 if (sb == NULL) 9234 return (ENOMEM); 9235 9236 mtx_lock(&sc->reg_lock); 9237 t4_tp_get_rdma_stats(sc, &stats, 0); 9238 mtx_unlock(&sc->reg_lock); 9239 9240 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 9241 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 9242 9243 rc = sbuf_finish(sb); 9244 sbuf_delete(sb); 9245 9246 return (rc); 9247 } 9248 9249 static int 9250 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 9251 { 9252 struct adapter *sc = arg1; 9253 struct sbuf *sb; 9254 int rc; 9255 struct tp_tcp_stats v4, v6; 9256 9257 rc = sysctl_wire_old_buffer(req, 0); 9258 if (rc != 0) 9259 return (rc); 9260 9261 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9262 if (sb == NULL) 9263 return (ENOMEM); 9264 9265 mtx_lock(&sc->reg_lock); 9266 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 9267 mtx_unlock(&sc->reg_lock); 9268 9269 sbuf_printf(sb, 9270 " IP IPv6\n"); 9271 sbuf_printf(sb, "OutRsts: %20u %20u\n", 9272 v4.tcp_out_rsts, v6.tcp_out_rsts); 9273 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 9274 v4.tcp_in_segs, v6.tcp_in_segs); 9275 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 9276 v4.tcp_out_segs, v6.tcp_out_segs); 9277 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 9278 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 9279 9280 rc = sbuf_finish(sb); 9281 sbuf_delete(sb); 9282 9283 return (rc); 9284 } 9285 9286 static int 9287 sysctl_tids(SYSCTL_HANDLER_ARGS) 9288 { 9289 struct adapter *sc = arg1; 9290 struct sbuf *sb; 9291 int rc; 9292 struct tid_info *t = &sc->tids; 9293 9294 rc = sysctl_wire_old_buffer(req, 0); 9295 if (rc != 0) 9296 return (rc); 9297 9298 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9299 if (sb == NULL) 9300 return (ENOMEM); 9301 9302 if (t->natids) { 9303 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 9304 t->atids_in_use); 9305 } 9306 9307 if (t->nhpftids) { 9308 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 9309 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 9310 } 9311 9312 if (t->ntids) { 9313 sbuf_printf(sb, "TID range: "); 9314 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 9315 uint32_t b, hb; 9316 9317 if (chip_id(sc) <= CHELSIO_T5) { 9318 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 9319 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 9320 } else { 9321 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 9322 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 9323 } 9324 9325 if (b) 9326 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1); 9327 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 9328 } else 9329 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1); 9330 sbuf_printf(sb, ", in use: %u\n", 9331 atomic_load_acq_int(&t->tids_in_use)); 9332 } 9333 9334 if (t->nstids) { 9335 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 9336 t->stid_base + t->nstids - 1, t->stids_in_use); 9337 } 9338 9339 if (t->nftids) { 9340 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 9341 t->ftid_end, t->ftids_in_use); 9342 } 9343 9344 if (t->netids) { 9345 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 9346 t->etid_base + t->netids - 1, t->etids_in_use); 9347 } 9348 9349 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 9350 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 9351 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 9352 9353 rc = sbuf_finish(sb); 9354 sbuf_delete(sb); 9355 9356 return (rc); 9357 } 9358 9359 static int 9360 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 9361 { 9362 struct adapter *sc = arg1; 9363 struct sbuf *sb; 9364 int rc; 9365 struct tp_err_stats stats; 9366 9367 rc = sysctl_wire_old_buffer(req, 0); 9368 if (rc != 0) 9369 return (rc); 9370 9371 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9372 if (sb == NULL) 9373 return (ENOMEM); 9374 9375 mtx_lock(&sc->reg_lock); 9376 t4_tp_get_err_stats(sc, &stats, 0); 9377 mtx_unlock(&sc->reg_lock); 9378 9379 if (sc->chip_params->nchan > 2) { 9380 sbuf_printf(sb, " channel 0 channel 1" 9381 " channel 2 channel 3\n"); 9382 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 9383 stats.mac_in_errs[0], stats.mac_in_errs[1], 9384 stats.mac_in_errs[2], stats.mac_in_errs[3]); 9385 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 9386 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 9387 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 9388 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 9389 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 9390 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 9391 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 9392 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 9393 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 9394 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 9395 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 9396 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 9397 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 9398 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 9399 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 9400 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 9401 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 9402 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 9403 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 9404 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 9405 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 9406 } else { 9407 sbuf_printf(sb, " channel 0 channel 1\n"); 9408 sbuf_printf(sb, "macInErrs: %10u %10u\n", 9409 stats.mac_in_errs[0], stats.mac_in_errs[1]); 9410 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 9411 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 9412 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 9413 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 9414 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 9415 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 9416 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 9417 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 9418 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 9419 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 9420 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 9421 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 9422 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 9423 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 9424 } 9425 9426 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 9427 stats.ofld_no_neigh, stats.ofld_cong_defer); 9428 9429 rc = sbuf_finish(sb); 9430 sbuf_delete(sb); 9431 9432 return (rc); 9433 } 9434 9435 static int 9436 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 9437 { 9438 struct adapter *sc = arg1; 9439 struct tp_params *tpp = &sc->params.tp; 9440 u_int mask; 9441 int rc; 9442 9443 mask = tpp->la_mask >> 16; 9444 rc = sysctl_handle_int(oidp, &mask, 0, req); 9445 if (rc != 0 || req->newptr == NULL) 9446 return (rc); 9447 if (mask > 0xffff) 9448 return (EINVAL); 9449 tpp->la_mask = mask << 16; 9450 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 9451 9452 return (0); 9453 } 9454 9455 struct field_desc { 9456 const char *name; 9457 u_int start; 9458 u_int width; 9459 }; 9460 9461 static void 9462 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 9463 { 9464 char buf[32]; 9465 int line_size = 0; 9466 9467 while (f->name) { 9468 uint64_t mask = (1ULL << f->width) - 1; 9469 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 9470 ((uintmax_t)v >> f->start) & mask); 9471 9472 if (line_size + len >= 79) { 9473 line_size = 8; 9474 sbuf_printf(sb, "\n "); 9475 } 9476 sbuf_printf(sb, "%s ", buf); 9477 line_size += len + 1; 9478 f++; 9479 } 9480 sbuf_printf(sb, "\n"); 9481 } 9482 9483 static const struct field_desc tp_la0[] = { 9484 { "RcfOpCodeOut", 60, 4 }, 9485 { "State", 56, 4 }, 9486 { "WcfState", 52, 4 }, 9487 { "RcfOpcSrcOut", 50, 2 }, 9488 { "CRxError", 49, 1 }, 9489 { "ERxError", 48, 1 }, 9490 { "SanityFailed", 47, 1 }, 9491 { "SpuriousMsg", 46, 1 }, 9492 { "FlushInputMsg", 45, 1 }, 9493 { "FlushInputCpl", 44, 1 }, 9494 { "RssUpBit", 43, 1 }, 9495 { "RssFilterHit", 42, 1 }, 9496 { "Tid", 32, 10 }, 9497 { "InitTcb", 31, 1 }, 9498 { "LineNumber", 24, 7 }, 9499 { "Emsg", 23, 1 }, 9500 { "EdataOut", 22, 1 }, 9501 { "Cmsg", 21, 1 }, 9502 { "CdataOut", 20, 1 }, 9503 { "EreadPdu", 19, 1 }, 9504 { "CreadPdu", 18, 1 }, 9505 { "TunnelPkt", 17, 1 }, 9506 { "RcfPeerFin", 16, 1 }, 9507 { "RcfReasonOut", 12, 4 }, 9508 { "TxCchannel", 10, 2 }, 9509 { "RcfTxChannel", 8, 2 }, 9510 { "RxEchannel", 6, 2 }, 9511 { "RcfRxChannel", 5, 1 }, 9512 { "RcfDataOutSrdy", 4, 1 }, 9513 { "RxDvld", 3, 1 }, 9514 { "RxOoDvld", 2, 1 }, 9515 { "RxCongestion", 1, 1 }, 9516 { "TxCongestion", 0, 1 }, 9517 { NULL } 9518 }; 9519 9520 static const struct field_desc tp_la1[] = { 9521 { "CplCmdIn", 56, 8 }, 9522 { "CplCmdOut", 48, 8 }, 9523 { "ESynOut", 47, 1 }, 9524 { "EAckOut", 46, 1 }, 9525 { "EFinOut", 45, 1 }, 9526 { "ERstOut", 44, 1 }, 9527 { "SynIn", 43, 1 }, 9528 { "AckIn", 42, 1 }, 9529 { "FinIn", 41, 1 }, 9530 { "RstIn", 40, 1 }, 9531 { "DataIn", 39, 1 }, 9532 { "DataInVld", 38, 1 }, 9533 { "PadIn", 37, 1 }, 9534 { "RxBufEmpty", 36, 1 }, 9535 { "RxDdp", 35, 1 }, 9536 { "RxFbCongestion", 34, 1 }, 9537 { "TxFbCongestion", 33, 1 }, 9538 { "TxPktSumSrdy", 32, 1 }, 9539 { "RcfUlpType", 28, 4 }, 9540 { "Eread", 27, 1 }, 9541 { "Ebypass", 26, 1 }, 9542 { "Esave", 25, 1 }, 9543 { "Static0", 24, 1 }, 9544 { "Cread", 23, 1 }, 9545 { "Cbypass", 22, 1 }, 9546 { "Csave", 21, 1 }, 9547 { "CPktOut", 20, 1 }, 9548 { "RxPagePoolFull", 18, 2 }, 9549 { "RxLpbkPkt", 17, 1 }, 9550 { "TxLpbkPkt", 16, 1 }, 9551 { "RxVfValid", 15, 1 }, 9552 { "SynLearned", 14, 1 }, 9553 { "SetDelEntry", 13, 1 }, 9554 { "SetInvEntry", 12, 1 }, 9555 { "CpcmdDvld", 11, 1 }, 9556 { "CpcmdSave", 10, 1 }, 9557 { "RxPstructsFull", 8, 2 }, 9558 { "EpcmdDvld", 7, 1 }, 9559 { "EpcmdFlush", 6, 1 }, 9560 { "EpcmdTrimPrefix", 5, 1 }, 9561 { "EpcmdTrimPostfix", 4, 1 }, 9562 { "ERssIp4Pkt", 3, 1 }, 9563 { "ERssIp6Pkt", 2, 1 }, 9564 { "ERssTcpUdpPkt", 1, 1 }, 9565 { "ERssFceFipPkt", 0, 1 }, 9566 { NULL } 9567 }; 9568 9569 static const struct field_desc tp_la2[] = { 9570 { "CplCmdIn", 56, 8 }, 9571 { "MpsVfVld", 55, 1 }, 9572 { "MpsPf", 52, 3 }, 9573 { "MpsVf", 44, 8 }, 9574 { "SynIn", 43, 1 }, 9575 { "AckIn", 42, 1 }, 9576 { "FinIn", 41, 1 }, 9577 { "RstIn", 40, 1 }, 9578 { "DataIn", 39, 1 }, 9579 { "DataInVld", 38, 1 }, 9580 { "PadIn", 37, 1 }, 9581 { "RxBufEmpty", 36, 1 }, 9582 { "RxDdp", 35, 1 }, 9583 { "RxFbCongestion", 34, 1 }, 9584 { "TxFbCongestion", 33, 1 }, 9585 { "TxPktSumSrdy", 32, 1 }, 9586 { "RcfUlpType", 28, 4 }, 9587 { "Eread", 27, 1 }, 9588 { "Ebypass", 26, 1 }, 9589 { "Esave", 25, 1 }, 9590 { "Static0", 24, 1 }, 9591 { "Cread", 23, 1 }, 9592 { "Cbypass", 22, 1 }, 9593 { "Csave", 21, 1 }, 9594 { "CPktOut", 20, 1 }, 9595 { "RxPagePoolFull", 18, 2 }, 9596 { "RxLpbkPkt", 17, 1 }, 9597 { "TxLpbkPkt", 16, 1 }, 9598 { "RxVfValid", 15, 1 }, 9599 { "SynLearned", 14, 1 }, 9600 { "SetDelEntry", 13, 1 }, 9601 { "SetInvEntry", 12, 1 }, 9602 { "CpcmdDvld", 11, 1 }, 9603 { "CpcmdSave", 10, 1 }, 9604 { "RxPstructsFull", 8, 2 }, 9605 { "EpcmdDvld", 7, 1 }, 9606 { "EpcmdFlush", 6, 1 }, 9607 { "EpcmdTrimPrefix", 5, 1 }, 9608 { "EpcmdTrimPostfix", 4, 1 }, 9609 { "ERssIp4Pkt", 3, 1 }, 9610 { "ERssIp6Pkt", 2, 1 }, 9611 { "ERssTcpUdpPkt", 1, 1 }, 9612 { "ERssFceFipPkt", 0, 1 }, 9613 { NULL } 9614 }; 9615 9616 static void 9617 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 9618 { 9619 9620 field_desc_show(sb, *p, tp_la0); 9621 } 9622 9623 static void 9624 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 9625 { 9626 9627 if (idx) 9628 sbuf_printf(sb, "\n"); 9629 field_desc_show(sb, p[0], tp_la0); 9630 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9631 field_desc_show(sb, p[1], tp_la0); 9632 } 9633 9634 static void 9635 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 9636 { 9637 9638 if (idx) 9639 sbuf_printf(sb, "\n"); 9640 field_desc_show(sb, p[0], tp_la0); 9641 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9642 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 9643 } 9644 9645 static int 9646 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 9647 { 9648 struct adapter *sc = arg1; 9649 struct sbuf *sb; 9650 uint64_t *buf, *p; 9651 int rc; 9652 u_int i, inc; 9653 void (*show_func)(struct sbuf *, uint64_t *, int); 9654 9655 rc = sysctl_wire_old_buffer(req, 0); 9656 if (rc != 0) 9657 return (rc); 9658 9659 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9660 if (sb == NULL) 9661 return (ENOMEM); 9662 9663 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 9664 9665 t4_tp_read_la(sc, buf, NULL); 9666 p = buf; 9667 9668 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 9669 case 2: 9670 inc = 2; 9671 show_func = tp_la_show2; 9672 break; 9673 case 3: 9674 inc = 2; 9675 show_func = tp_la_show3; 9676 break; 9677 default: 9678 inc = 1; 9679 show_func = tp_la_show; 9680 } 9681 9682 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 9683 (*show_func)(sb, p, i); 9684 9685 rc = sbuf_finish(sb); 9686 sbuf_delete(sb); 9687 free(buf, M_CXGBE); 9688 return (rc); 9689 } 9690 9691 static int 9692 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 9693 { 9694 struct adapter *sc = arg1; 9695 struct sbuf *sb; 9696 int rc; 9697 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 9698 9699 rc = sysctl_wire_old_buffer(req, 0); 9700 if (rc != 0) 9701 return (rc); 9702 9703 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9704 if (sb == NULL) 9705 return (ENOMEM); 9706 9707 t4_get_chan_txrate(sc, nrate, orate); 9708 9709 if (sc->chip_params->nchan > 2) { 9710 sbuf_printf(sb, " channel 0 channel 1" 9711 " channel 2 channel 3\n"); 9712 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 9713 nrate[0], nrate[1], nrate[2], nrate[3]); 9714 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 9715 orate[0], orate[1], orate[2], orate[3]); 9716 } else { 9717 sbuf_printf(sb, " channel 0 channel 1\n"); 9718 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 9719 nrate[0], nrate[1]); 9720 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 9721 orate[0], orate[1]); 9722 } 9723 9724 rc = sbuf_finish(sb); 9725 sbuf_delete(sb); 9726 9727 return (rc); 9728 } 9729 9730 static int 9731 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 9732 { 9733 struct adapter *sc = arg1; 9734 struct sbuf *sb; 9735 uint32_t *buf, *p; 9736 int rc, i; 9737 9738 rc = sysctl_wire_old_buffer(req, 0); 9739 if (rc != 0) 9740 return (rc); 9741 9742 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9743 if (sb == NULL) 9744 return (ENOMEM); 9745 9746 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 9747 M_ZERO | M_WAITOK); 9748 9749 t4_ulprx_read_la(sc, buf); 9750 p = buf; 9751 9752 sbuf_printf(sb, " Pcmd Type Message" 9753 " Data"); 9754 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 9755 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 9756 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 9757 } 9758 9759 rc = sbuf_finish(sb); 9760 sbuf_delete(sb); 9761 free(buf, M_CXGBE); 9762 return (rc); 9763 } 9764 9765 static int 9766 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 9767 { 9768 struct adapter *sc = arg1; 9769 struct sbuf *sb; 9770 int rc, v; 9771 9772 MPASS(chip_id(sc) >= CHELSIO_T5); 9773 9774 rc = sysctl_wire_old_buffer(req, 0); 9775 if (rc != 0) 9776 return (rc); 9777 9778 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9779 if (sb == NULL) 9780 return (ENOMEM); 9781 9782 v = t4_read_reg(sc, A_SGE_STAT_CFG); 9783 if (G_STATSOURCE_T5(v) == 7) { 9784 int mode; 9785 9786 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 9787 if (mode == 0) { 9788 sbuf_printf(sb, "total %d, incomplete %d", 9789 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9790 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9791 } else if (mode == 1) { 9792 sbuf_printf(sb, "total %d, data overflow %d", 9793 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9794 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9795 } else { 9796 sbuf_printf(sb, "unknown mode %d", mode); 9797 } 9798 } 9799 rc = sbuf_finish(sb); 9800 sbuf_delete(sb); 9801 9802 return (rc); 9803 } 9804 9805 static int 9806 sysctl_cpus(SYSCTL_HANDLER_ARGS) 9807 { 9808 struct adapter *sc = arg1; 9809 enum cpu_sets op = arg2; 9810 cpuset_t cpuset; 9811 struct sbuf *sb; 9812 int i, rc; 9813 9814 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 9815 9816 CPU_ZERO(&cpuset); 9817 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 9818 if (rc != 0) 9819 return (rc); 9820 9821 rc = sysctl_wire_old_buffer(req, 0); 9822 if (rc != 0) 9823 return (rc); 9824 9825 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9826 if (sb == NULL) 9827 return (ENOMEM); 9828 9829 CPU_FOREACH(i) 9830 sbuf_printf(sb, "%d ", i); 9831 rc = sbuf_finish(sb); 9832 sbuf_delete(sb); 9833 9834 return (rc); 9835 } 9836 9837 #ifdef TCP_OFFLOAD 9838 static int 9839 sysctl_tls(SYSCTL_HANDLER_ARGS) 9840 { 9841 struct adapter *sc = arg1; 9842 int i, j, v, rc; 9843 struct vi_info *vi; 9844 9845 v = sc->tt.tls; 9846 rc = sysctl_handle_int(oidp, &v, 0, req); 9847 if (rc != 0 || req->newptr == NULL) 9848 return (rc); 9849 9850 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 9851 return (ENOTSUP); 9852 9853 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls"); 9854 if (rc) 9855 return (rc); 9856 sc->tt.tls = !!v; 9857 for_each_port(sc, i) { 9858 for_each_vi(sc->port[i], j, vi) { 9859 if (vi->flags & VI_INIT_DONE) 9860 t4_update_fl_bufsize(vi->ifp); 9861 } 9862 } 9863 end_synchronized_op(sc, 0); 9864 9865 return (0); 9866 9867 } 9868 9869 static int 9870 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 9871 { 9872 struct adapter *sc = arg1; 9873 int *old_ports, *new_ports; 9874 int i, new_count, rc; 9875 9876 if (req->newptr == NULL && req->oldptr == NULL) 9877 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 9878 sizeof(sc->tt.tls_rx_ports[0]))); 9879 9880 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 9881 if (rc) 9882 return (rc); 9883 9884 if (sc->tt.num_tls_rx_ports == 0) { 9885 i = -1; 9886 rc = SYSCTL_OUT(req, &i, sizeof(i)); 9887 } else 9888 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 9889 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 9890 if (rc == 0 && req->newptr != NULL) { 9891 new_count = req->newlen / sizeof(new_ports[0]); 9892 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 9893 M_WAITOK); 9894 rc = SYSCTL_IN(req, new_ports, new_count * 9895 sizeof(new_ports[0])); 9896 if (rc) 9897 goto err; 9898 9899 /* Allow setting to a single '-1' to clear the list. */ 9900 if (new_count == 1 && new_ports[0] == -1) { 9901 ADAPTER_LOCK(sc); 9902 old_ports = sc->tt.tls_rx_ports; 9903 sc->tt.tls_rx_ports = NULL; 9904 sc->tt.num_tls_rx_ports = 0; 9905 ADAPTER_UNLOCK(sc); 9906 free(old_ports, M_CXGBE); 9907 } else { 9908 for (i = 0; i < new_count; i++) { 9909 if (new_ports[i] < 1 || 9910 new_ports[i] > IPPORT_MAX) { 9911 rc = EINVAL; 9912 goto err; 9913 } 9914 } 9915 9916 ADAPTER_LOCK(sc); 9917 old_ports = sc->tt.tls_rx_ports; 9918 sc->tt.tls_rx_ports = new_ports; 9919 sc->tt.num_tls_rx_ports = new_count; 9920 ADAPTER_UNLOCK(sc); 9921 free(old_ports, M_CXGBE); 9922 new_ports = NULL; 9923 } 9924 err: 9925 free(new_ports, M_CXGBE); 9926 } 9927 end_synchronized_op(sc, 0); 9928 return (rc); 9929 } 9930 9931 static void 9932 unit_conv(char *buf, size_t len, u_int val, u_int factor) 9933 { 9934 u_int rem = val % factor; 9935 9936 if (rem == 0) 9937 snprintf(buf, len, "%u", val / factor); 9938 else { 9939 while (rem % 10 == 0) 9940 rem /= 10; 9941 snprintf(buf, len, "%u.%u", val / factor, rem); 9942 } 9943 } 9944 9945 static int 9946 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 9947 { 9948 struct adapter *sc = arg1; 9949 char buf[16]; 9950 u_int res, re; 9951 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9952 9953 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9954 switch (arg2) { 9955 case 0: 9956 /* timer_tick */ 9957 re = G_TIMERRESOLUTION(res); 9958 break; 9959 case 1: 9960 /* TCP timestamp tick */ 9961 re = G_TIMESTAMPRESOLUTION(res); 9962 break; 9963 case 2: 9964 /* DACK tick */ 9965 re = G_DELAYEDACKRESOLUTION(res); 9966 break; 9967 default: 9968 return (EDOOFUS); 9969 } 9970 9971 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 9972 9973 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 9974 } 9975 9976 static int 9977 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 9978 { 9979 struct adapter *sc = arg1; 9980 u_int res, dack_re, v; 9981 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9982 9983 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9984 dack_re = G_DELAYEDACKRESOLUTION(res); 9985 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 9986 9987 return (sysctl_handle_int(oidp, &v, 0, req)); 9988 } 9989 9990 static int 9991 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 9992 { 9993 struct adapter *sc = arg1; 9994 int reg = arg2; 9995 u_int tre; 9996 u_long tp_tick_us, v; 9997 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9998 9999 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 10000 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 10001 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 10002 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 10003 10004 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 10005 tp_tick_us = (cclk_ps << tre) / 1000000; 10006 10007 if (reg == A_TP_INIT_SRTT) 10008 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 10009 else 10010 v = tp_tick_us * t4_read_reg(sc, reg); 10011 10012 return (sysctl_handle_long(oidp, &v, 0, req)); 10013 } 10014 10015 /* 10016 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 10017 * passed to this function. 10018 */ 10019 static int 10020 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 10021 { 10022 struct adapter *sc = arg1; 10023 int idx = arg2; 10024 u_int v; 10025 10026 MPASS(idx >= 0 && idx <= 24); 10027 10028 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 10029 10030 return (sysctl_handle_int(oidp, &v, 0, req)); 10031 } 10032 10033 static int 10034 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 10035 { 10036 struct adapter *sc = arg1; 10037 int idx = arg2; 10038 u_int shift, v, r; 10039 10040 MPASS(idx >= 0 && idx < 16); 10041 10042 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 10043 shift = (idx & 3) << 3; 10044 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 10045 10046 return (sysctl_handle_int(oidp, &v, 0, req)); 10047 } 10048 10049 static int 10050 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 10051 { 10052 struct vi_info *vi = arg1; 10053 struct adapter *sc = vi->adapter; 10054 int idx, rc, i; 10055 struct sge_ofld_rxq *ofld_rxq; 10056 uint8_t v; 10057 10058 idx = vi->ofld_tmr_idx; 10059 10060 rc = sysctl_handle_int(oidp, &idx, 0, req); 10061 if (rc != 0 || req->newptr == NULL) 10062 return (rc); 10063 10064 if (idx < 0 || idx >= SGE_NTIMERS) 10065 return (EINVAL); 10066 10067 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 10068 "t4otmr"); 10069 if (rc) 10070 return (rc); 10071 10072 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 10073 for_each_ofld_rxq(vi, i, ofld_rxq) { 10074 #ifdef atomic_store_rel_8 10075 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 10076 #else 10077 ofld_rxq->iq.intr_params = v; 10078 #endif 10079 } 10080 vi->ofld_tmr_idx = idx; 10081 10082 end_synchronized_op(sc, LOCK_HELD); 10083 return (0); 10084 } 10085 10086 static int 10087 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 10088 { 10089 struct vi_info *vi = arg1; 10090 struct adapter *sc = vi->adapter; 10091 int idx, rc; 10092 10093 idx = vi->ofld_pktc_idx; 10094 10095 rc = sysctl_handle_int(oidp, &idx, 0, req); 10096 if (rc != 0 || req->newptr == NULL) 10097 return (rc); 10098 10099 if (idx < -1 || idx >= SGE_NCOUNTERS) 10100 return (EINVAL); 10101 10102 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 10103 "t4opktc"); 10104 if (rc) 10105 return (rc); 10106 10107 if (vi->flags & VI_INIT_DONE) 10108 rc = EBUSY; /* cannot be changed once the queues are created */ 10109 else 10110 vi->ofld_pktc_idx = idx; 10111 10112 end_synchronized_op(sc, LOCK_HELD); 10113 return (rc); 10114 } 10115 #endif 10116 10117 static int 10118 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 10119 { 10120 int rc; 10121 10122 if (cntxt->cid > M_CTXTQID) 10123 return (EINVAL); 10124 10125 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 10126 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 10127 return (EINVAL); 10128 10129 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 10130 if (rc) 10131 return (rc); 10132 10133 if (sc->flags & FW_OK) { 10134 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 10135 &cntxt->data[0]); 10136 if (rc == 0) 10137 goto done; 10138 } 10139 10140 /* 10141 * Read via firmware failed or wasn't even attempted. Read directly via 10142 * the backdoor. 10143 */ 10144 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 10145 done: 10146 end_synchronized_op(sc, 0); 10147 return (rc); 10148 } 10149 10150 static int 10151 load_fw(struct adapter *sc, struct t4_data *fw) 10152 { 10153 int rc; 10154 uint8_t *fw_data; 10155 10156 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 10157 if (rc) 10158 return (rc); 10159 10160 /* 10161 * The firmware, with the sole exception of the memory parity error 10162 * handler, runs from memory and not flash. It is almost always safe to 10163 * install a new firmware on a running system. Just set bit 1 in 10164 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 10165 */ 10166 if (sc->flags & FULL_INIT_DONE && 10167 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 10168 rc = EBUSY; 10169 goto done; 10170 } 10171 10172 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 10173 10174 rc = copyin(fw->data, fw_data, fw->len); 10175 if (rc == 0) 10176 rc = -t4_load_fw(sc, fw_data, fw->len); 10177 10178 free(fw_data, M_CXGBE); 10179 done: 10180 end_synchronized_op(sc, 0); 10181 return (rc); 10182 } 10183 10184 static int 10185 load_cfg(struct adapter *sc, struct t4_data *cfg) 10186 { 10187 int rc; 10188 uint8_t *cfg_data = NULL; 10189 10190 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 10191 if (rc) 10192 return (rc); 10193 10194 if (cfg->len == 0) { 10195 /* clear */ 10196 rc = -t4_load_cfg(sc, NULL, 0); 10197 goto done; 10198 } 10199 10200 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 10201 10202 rc = copyin(cfg->data, cfg_data, cfg->len); 10203 if (rc == 0) 10204 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 10205 10206 free(cfg_data, M_CXGBE); 10207 done: 10208 end_synchronized_op(sc, 0); 10209 return (rc); 10210 } 10211 10212 static int 10213 load_boot(struct adapter *sc, struct t4_bootrom *br) 10214 { 10215 int rc; 10216 uint8_t *br_data = NULL; 10217 u_int offset; 10218 10219 if (br->len > 1024 * 1024) 10220 return (EFBIG); 10221 10222 if (br->pf_offset == 0) { 10223 /* pfidx */ 10224 if (br->pfidx_addr > 7) 10225 return (EINVAL); 10226 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 10227 A_PCIE_PF_EXPROM_OFST))); 10228 } else if (br->pf_offset == 1) { 10229 /* offset */ 10230 offset = G_OFFSET(br->pfidx_addr); 10231 } else { 10232 return (EINVAL); 10233 } 10234 10235 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 10236 if (rc) 10237 return (rc); 10238 10239 if (br->len == 0) { 10240 /* clear */ 10241 rc = -t4_load_boot(sc, NULL, offset, 0); 10242 goto done; 10243 } 10244 10245 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 10246 10247 rc = copyin(br->data, br_data, br->len); 10248 if (rc == 0) 10249 rc = -t4_load_boot(sc, br_data, offset, br->len); 10250 10251 free(br_data, M_CXGBE); 10252 done: 10253 end_synchronized_op(sc, 0); 10254 return (rc); 10255 } 10256 10257 static int 10258 load_bootcfg(struct adapter *sc, struct t4_data *bc) 10259 { 10260 int rc; 10261 uint8_t *bc_data = NULL; 10262 10263 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 10264 if (rc) 10265 return (rc); 10266 10267 if (bc->len == 0) { 10268 /* clear */ 10269 rc = -t4_load_bootcfg(sc, NULL, 0); 10270 goto done; 10271 } 10272 10273 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 10274 10275 rc = copyin(bc->data, bc_data, bc->len); 10276 if (rc == 0) 10277 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 10278 10279 free(bc_data, M_CXGBE); 10280 done: 10281 end_synchronized_op(sc, 0); 10282 return (rc); 10283 } 10284 10285 static int 10286 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 10287 { 10288 int rc; 10289 struct cudbg_init *cudbg; 10290 void *handle, *buf; 10291 10292 /* buf is large, don't block if no memory is available */ 10293 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 10294 if (buf == NULL) 10295 return (ENOMEM); 10296 10297 handle = cudbg_alloc_handle(); 10298 if (handle == NULL) { 10299 rc = ENOMEM; 10300 goto done; 10301 } 10302 10303 cudbg = cudbg_get_init(handle); 10304 cudbg->adap = sc; 10305 cudbg->print = (cudbg_print_cb)printf; 10306 10307 #ifndef notyet 10308 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 10309 __func__, dump->wr_flash, dump->len, dump->data); 10310 #endif 10311 10312 if (dump->wr_flash) 10313 cudbg->use_flash = 1; 10314 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 10315 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 10316 10317 rc = cudbg_collect(handle, buf, &dump->len); 10318 if (rc != 0) 10319 goto done; 10320 10321 rc = copyout(buf, dump->data, dump->len); 10322 done: 10323 cudbg_free_handle(handle); 10324 free(buf, M_CXGBE); 10325 return (rc); 10326 } 10327 10328 static void 10329 free_offload_policy(struct t4_offload_policy *op) 10330 { 10331 struct offload_rule *r; 10332 int i; 10333 10334 if (op == NULL) 10335 return; 10336 10337 r = &op->rule[0]; 10338 for (i = 0; i < op->nrules; i++, r++) { 10339 free(r->bpf_prog.bf_insns, M_CXGBE); 10340 } 10341 free(op->rule, M_CXGBE); 10342 free(op, M_CXGBE); 10343 } 10344 10345 static int 10346 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 10347 { 10348 int i, rc, len; 10349 struct t4_offload_policy *op, *old; 10350 struct bpf_program *bf; 10351 const struct offload_settings *s; 10352 struct offload_rule *r; 10353 void *u; 10354 10355 if (!is_offload(sc)) 10356 return (ENODEV); 10357 10358 if (uop->nrules == 0) { 10359 /* Delete installed policies. */ 10360 op = NULL; 10361 goto set_policy; 10362 } else if (uop->nrules > 256) { /* arbitrary */ 10363 return (E2BIG); 10364 } 10365 10366 /* Copy userspace offload policy to kernel */ 10367 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 10368 op->nrules = uop->nrules; 10369 len = op->nrules * sizeof(struct offload_rule); 10370 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 10371 rc = copyin(uop->rule, op->rule, len); 10372 if (rc) { 10373 free(op->rule, M_CXGBE); 10374 free(op, M_CXGBE); 10375 return (rc); 10376 } 10377 10378 r = &op->rule[0]; 10379 for (i = 0; i < op->nrules; i++, r++) { 10380 10381 /* Validate open_type */ 10382 if (r->open_type != OPEN_TYPE_LISTEN && 10383 r->open_type != OPEN_TYPE_ACTIVE && 10384 r->open_type != OPEN_TYPE_PASSIVE && 10385 r->open_type != OPEN_TYPE_DONTCARE) { 10386 error: 10387 /* 10388 * Rules 0 to i have malloc'd filters that need to be 10389 * freed. Rules i+1 to nrules have userspace pointers 10390 * and should be left alone. 10391 */ 10392 op->nrules = i; 10393 free_offload_policy(op); 10394 return (rc); 10395 } 10396 10397 /* Validate settings */ 10398 s = &r->settings; 10399 if ((s->offload != 0 && s->offload != 1) || 10400 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 10401 s->sched_class < -1 || 10402 s->sched_class >= sc->chip_params->nsched_cls) { 10403 rc = EINVAL; 10404 goto error; 10405 } 10406 10407 bf = &r->bpf_prog; 10408 u = bf->bf_insns; /* userspace ptr */ 10409 bf->bf_insns = NULL; 10410 if (bf->bf_len == 0) { 10411 /* legal, matches everything */ 10412 continue; 10413 } 10414 len = bf->bf_len * sizeof(*bf->bf_insns); 10415 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 10416 rc = copyin(u, bf->bf_insns, len); 10417 if (rc != 0) 10418 goto error; 10419 10420 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 10421 rc = EINVAL; 10422 goto error; 10423 } 10424 } 10425 set_policy: 10426 rw_wlock(&sc->policy_lock); 10427 old = sc->policy; 10428 sc->policy = op; 10429 rw_wunlock(&sc->policy_lock); 10430 free_offload_policy(old); 10431 10432 return (0); 10433 } 10434 10435 #define MAX_READ_BUF_SIZE (128 * 1024) 10436 static int 10437 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 10438 { 10439 uint32_t addr, remaining, n; 10440 uint32_t *buf; 10441 int rc; 10442 uint8_t *dst; 10443 10444 rc = validate_mem_range(sc, mr->addr, mr->len); 10445 if (rc != 0) 10446 return (rc); 10447 10448 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 10449 addr = mr->addr; 10450 remaining = mr->len; 10451 dst = (void *)mr->data; 10452 10453 while (remaining) { 10454 n = min(remaining, MAX_READ_BUF_SIZE); 10455 read_via_memwin(sc, 2, addr, buf, n); 10456 10457 rc = copyout(buf, dst, n); 10458 if (rc != 0) 10459 break; 10460 10461 dst += n; 10462 remaining -= n; 10463 addr += n; 10464 } 10465 10466 free(buf, M_CXGBE); 10467 return (rc); 10468 } 10469 #undef MAX_READ_BUF_SIZE 10470 10471 static int 10472 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 10473 { 10474 int rc; 10475 10476 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 10477 return (EINVAL); 10478 10479 if (i2cd->len > sizeof(i2cd->data)) 10480 return (EFBIG); 10481 10482 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 10483 if (rc) 10484 return (rc); 10485 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 10486 i2cd->offset, i2cd->len, &i2cd->data[0]); 10487 end_synchronized_op(sc, 0); 10488 10489 return (rc); 10490 } 10491 10492 static int 10493 clear_stats(struct adapter *sc, u_int port_id) 10494 { 10495 int i, v, chan_map; 10496 struct port_info *pi; 10497 struct vi_info *vi; 10498 struct sge_rxq *rxq; 10499 struct sge_txq *txq; 10500 struct sge_wrq *wrq; 10501 #ifdef TCP_OFFLOAD 10502 struct sge_ofld_rxq *ofld_rxq; 10503 #endif 10504 10505 if (port_id >= sc->params.nports) 10506 return (EINVAL); 10507 pi = sc->port[port_id]; 10508 if (pi == NULL) 10509 return (EIO); 10510 10511 /* MAC stats */ 10512 t4_clr_port_stats(sc, pi->tx_chan); 10513 if (is_t6(sc)) { 10514 if (pi->fcs_reg != -1) 10515 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 10516 else 10517 pi->stats.rx_fcs_err = 0; 10518 } 10519 pi->tx_parse_error = 0; 10520 pi->tnl_cong_drops = 0; 10521 mtx_lock(&sc->reg_lock); 10522 for_each_vi(pi, v, vi) { 10523 if (vi->flags & VI_INIT_DONE) 10524 t4_clr_vi_stats(sc, vi->vin); 10525 } 10526 chan_map = pi->rx_e_chan_map; 10527 v = 0; /* reuse */ 10528 while (chan_map) { 10529 i = ffs(chan_map) - 1; 10530 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 10531 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 10532 chan_map &= ~(1 << i); 10533 } 10534 mtx_unlock(&sc->reg_lock); 10535 10536 /* 10537 * Since this command accepts a port, clear stats for 10538 * all VIs on this port. 10539 */ 10540 for_each_vi(pi, v, vi) { 10541 if (vi->flags & VI_INIT_DONE) { 10542 10543 for_each_rxq(vi, i, rxq) { 10544 #if defined(INET) || defined(INET6) 10545 rxq->lro.lro_queued = 0; 10546 rxq->lro.lro_flushed = 0; 10547 #endif 10548 rxq->rxcsum = 0; 10549 rxq->vlan_extraction = 0; 10550 rxq->vxlan_rxcsum = 0; 10551 10552 rxq->fl.cl_allocated = 0; 10553 rxq->fl.cl_recycled = 0; 10554 rxq->fl.cl_fast_recycled = 0; 10555 } 10556 10557 for_each_txq(vi, i, txq) { 10558 txq->txcsum = 0; 10559 txq->tso_wrs = 0; 10560 txq->vlan_insertion = 0; 10561 txq->imm_wrs = 0; 10562 txq->sgl_wrs = 0; 10563 txq->txpkt_wrs = 0; 10564 txq->txpkts0_wrs = 0; 10565 txq->txpkts1_wrs = 0; 10566 txq->txpkts0_pkts = 0; 10567 txq->txpkts1_pkts = 0; 10568 txq->raw_wrs = 0; 10569 txq->vxlan_tso_wrs = 0; 10570 txq->vxlan_txcsum = 0; 10571 txq->kern_tls_records = 0; 10572 txq->kern_tls_short = 0; 10573 txq->kern_tls_partial = 0; 10574 txq->kern_tls_full = 0; 10575 txq->kern_tls_octets = 0; 10576 txq->kern_tls_waste = 0; 10577 txq->kern_tls_options = 0; 10578 txq->kern_tls_header = 0; 10579 txq->kern_tls_fin = 0; 10580 txq->kern_tls_fin_short = 0; 10581 txq->kern_tls_cbc = 0; 10582 txq->kern_tls_gcm = 0; 10583 mp_ring_reset_stats(txq->r); 10584 } 10585 10586 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10587 for_each_ofld_txq(vi, i, wrq) { 10588 wrq->tx_wrs_direct = 0; 10589 wrq->tx_wrs_copied = 0; 10590 } 10591 #endif 10592 #ifdef TCP_OFFLOAD 10593 for_each_ofld_rxq(vi, i, ofld_rxq) { 10594 ofld_rxq->fl.cl_allocated = 0; 10595 ofld_rxq->fl.cl_recycled = 0; 10596 ofld_rxq->fl.cl_fast_recycled = 0; 10597 } 10598 #endif 10599 10600 if (IS_MAIN_VI(vi)) { 10601 wrq = &sc->sge.ctrlq[pi->port_id]; 10602 wrq->tx_wrs_direct = 0; 10603 wrq->tx_wrs_copied = 0; 10604 } 10605 } 10606 } 10607 10608 return (0); 10609 } 10610 10611 int 10612 t4_os_find_pci_capability(struct adapter *sc, int cap) 10613 { 10614 int i; 10615 10616 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 10617 } 10618 10619 int 10620 t4_os_pci_save_state(struct adapter *sc) 10621 { 10622 device_t dev; 10623 struct pci_devinfo *dinfo; 10624 10625 dev = sc->dev; 10626 dinfo = device_get_ivars(dev); 10627 10628 pci_cfg_save(dev, dinfo, 0); 10629 return (0); 10630 } 10631 10632 int 10633 t4_os_pci_restore_state(struct adapter *sc) 10634 { 10635 device_t dev; 10636 struct pci_devinfo *dinfo; 10637 10638 dev = sc->dev; 10639 dinfo = device_get_ivars(dev); 10640 10641 pci_cfg_restore(dev, dinfo); 10642 return (0); 10643 } 10644 10645 void 10646 t4_os_portmod_changed(struct port_info *pi) 10647 { 10648 struct adapter *sc = pi->adapter; 10649 struct vi_info *vi; 10650 struct ifnet *ifp; 10651 static const char *mod_str[] = { 10652 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 10653 }; 10654 10655 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 10656 ("%s: port_type %u", __func__, pi->port_type)); 10657 10658 vi = &pi->vi[0]; 10659 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 10660 PORT_LOCK(pi); 10661 build_medialist(pi); 10662 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 10663 fixup_link_config(pi); 10664 apply_link_config(pi); 10665 } 10666 PORT_UNLOCK(pi); 10667 end_synchronized_op(sc, LOCK_HELD); 10668 } 10669 10670 ifp = vi->ifp; 10671 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 10672 if_printf(ifp, "transceiver unplugged.\n"); 10673 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 10674 if_printf(ifp, "unknown transceiver inserted.\n"); 10675 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 10676 if_printf(ifp, "unsupported transceiver inserted.\n"); 10677 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 10678 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 10679 port_top_speed(pi), mod_str[pi->mod_type]); 10680 } else { 10681 if_printf(ifp, "transceiver (type %d) inserted.\n", 10682 pi->mod_type); 10683 } 10684 } 10685 10686 void 10687 t4_os_link_changed(struct port_info *pi) 10688 { 10689 struct vi_info *vi; 10690 struct ifnet *ifp; 10691 struct link_config *lc = &pi->link_cfg; 10692 struct adapter *sc = pi->adapter; 10693 int v; 10694 10695 PORT_LOCK_ASSERT_OWNED(pi); 10696 10697 if (is_t6(sc)) { 10698 if (lc->link_ok) { 10699 if (lc->speed > 25000 || 10700 (lc->speed == 25000 && lc->fec == FEC_RS)) { 10701 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 10702 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS); 10703 } else { 10704 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 10705 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS); 10706 } 10707 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 10708 pi->stats.rx_fcs_err = 0; 10709 } else { 10710 pi->fcs_reg = -1; 10711 } 10712 } else { 10713 MPASS(pi->fcs_reg != -1); 10714 MPASS(pi->fcs_base == 0); 10715 } 10716 10717 for_each_vi(pi, v, vi) { 10718 ifp = vi->ifp; 10719 if (ifp == NULL) 10720 continue; 10721 10722 if (lc->link_ok) { 10723 ifp->if_baudrate = IF_Mbps(lc->speed); 10724 if_link_state_change(ifp, LINK_STATE_UP); 10725 } else { 10726 if_link_state_change(ifp, LINK_STATE_DOWN); 10727 } 10728 } 10729 } 10730 10731 void 10732 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 10733 { 10734 struct adapter *sc; 10735 10736 sx_slock(&t4_list_lock); 10737 SLIST_FOREACH(sc, &t4_list, link) { 10738 /* 10739 * func should not make any assumptions about what state sc is 10740 * in - the only guarantee is that sc->sc_lock is a valid lock. 10741 */ 10742 func(sc, arg); 10743 } 10744 sx_sunlock(&t4_list_lock); 10745 } 10746 10747 static int 10748 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 10749 struct thread *td) 10750 { 10751 int rc; 10752 struct adapter *sc = dev->si_drv1; 10753 10754 rc = priv_check(td, PRIV_DRIVER); 10755 if (rc != 0) 10756 return (rc); 10757 10758 switch (cmd) { 10759 case CHELSIO_T4_GETREG: { 10760 struct t4_reg *edata = (struct t4_reg *)data; 10761 10762 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 10763 return (EFAULT); 10764 10765 if (edata->size == 4) 10766 edata->val = t4_read_reg(sc, edata->addr); 10767 else if (edata->size == 8) 10768 edata->val = t4_read_reg64(sc, edata->addr); 10769 else 10770 return (EINVAL); 10771 10772 break; 10773 } 10774 case CHELSIO_T4_SETREG: { 10775 struct t4_reg *edata = (struct t4_reg *)data; 10776 10777 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 10778 return (EFAULT); 10779 10780 if (edata->size == 4) { 10781 if (edata->val & 0xffffffff00000000) 10782 return (EINVAL); 10783 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 10784 } else if (edata->size == 8) 10785 t4_write_reg64(sc, edata->addr, edata->val); 10786 else 10787 return (EINVAL); 10788 break; 10789 } 10790 case CHELSIO_T4_REGDUMP: { 10791 struct t4_regdump *regs = (struct t4_regdump *)data; 10792 int reglen = t4_get_regs_len(sc); 10793 uint8_t *buf; 10794 10795 if (regs->len < reglen) { 10796 regs->len = reglen; /* hint to the caller */ 10797 return (ENOBUFS); 10798 } 10799 10800 regs->len = reglen; 10801 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 10802 get_regs(sc, regs, buf); 10803 rc = copyout(buf, regs->data, reglen); 10804 free(buf, M_CXGBE); 10805 break; 10806 } 10807 case CHELSIO_T4_GET_FILTER_MODE: 10808 rc = get_filter_mode(sc, (uint32_t *)data); 10809 break; 10810 case CHELSIO_T4_SET_FILTER_MODE: 10811 rc = set_filter_mode(sc, *(uint32_t *)data); 10812 break; 10813 case CHELSIO_T4_GET_FILTER: 10814 rc = get_filter(sc, (struct t4_filter *)data); 10815 break; 10816 case CHELSIO_T4_SET_FILTER: 10817 rc = set_filter(sc, (struct t4_filter *)data); 10818 break; 10819 case CHELSIO_T4_DEL_FILTER: 10820 rc = del_filter(sc, (struct t4_filter *)data); 10821 break; 10822 case CHELSIO_T4_GET_SGE_CONTEXT: 10823 rc = get_sge_context(sc, (struct t4_sge_context *)data); 10824 break; 10825 case CHELSIO_T4_LOAD_FW: 10826 rc = load_fw(sc, (struct t4_data *)data); 10827 break; 10828 case CHELSIO_T4_GET_MEM: 10829 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 10830 break; 10831 case CHELSIO_T4_GET_I2C: 10832 rc = read_i2c(sc, (struct t4_i2c_data *)data); 10833 break; 10834 case CHELSIO_T4_CLEAR_STATS: 10835 rc = clear_stats(sc, *(uint32_t *)data); 10836 break; 10837 case CHELSIO_T4_SCHED_CLASS: 10838 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 10839 break; 10840 case CHELSIO_T4_SCHED_QUEUE: 10841 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 10842 break; 10843 case CHELSIO_T4_GET_TRACER: 10844 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 10845 break; 10846 case CHELSIO_T4_SET_TRACER: 10847 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 10848 break; 10849 case CHELSIO_T4_LOAD_CFG: 10850 rc = load_cfg(sc, (struct t4_data *)data); 10851 break; 10852 case CHELSIO_T4_LOAD_BOOT: 10853 rc = load_boot(sc, (struct t4_bootrom *)data); 10854 break; 10855 case CHELSIO_T4_LOAD_BOOTCFG: 10856 rc = load_bootcfg(sc, (struct t4_data *)data); 10857 break; 10858 case CHELSIO_T4_CUDBG_DUMP: 10859 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 10860 break; 10861 case CHELSIO_T4_SET_OFLD_POLICY: 10862 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 10863 break; 10864 default: 10865 rc = ENOTTY; 10866 } 10867 10868 return (rc); 10869 } 10870 10871 #ifdef TCP_OFFLOAD 10872 static int 10873 toe_capability(struct vi_info *vi, int enable) 10874 { 10875 int rc; 10876 struct port_info *pi = vi->pi; 10877 struct adapter *sc = pi->adapter; 10878 10879 ASSERT_SYNCHRONIZED_OP(sc); 10880 10881 if (!is_offload(sc)) 10882 return (ENODEV); 10883 10884 if (enable) { 10885 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 10886 /* TOE is already enabled. */ 10887 return (0); 10888 } 10889 10890 /* 10891 * We need the port's queues around so that we're able to send 10892 * and receive CPLs to/from the TOE even if the ifnet for this 10893 * port has never been UP'd administratively. 10894 */ 10895 if (!(vi->flags & VI_INIT_DONE)) { 10896 rc = vi_full_init(vi); 10897 if (rc) 10898 return (rc); 10899 } 10900 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 10901 rc = vi_full_init(&pi->vi[0]); 10902 if (rc) 10903 return (rc); 10904 } 10905 10906 if (isset(&sc->offload_map, pi->port_id)) { 10907 /* TOE is enabled on another VI of this port. */ 10908 pi->uld_vis++; 10909 return (0); 10910 } 10911 10912 if (!uld_active(sc, ULD_TOM)) { 10913 rc = t4_activate_uld(sc, ULD_TOM); 10914 if (rc == EAGAIN) { 10915 log(LOG_WARNING, 10916 "You must kldload t4_tom.ko before trying " 10917 "to enable TOE on a cxgbe interface.\n"); 10918 } 10919 if (rc != 0) 10920 return (rc); 10921 KASSERT(sc->tom_softc != NULL, 10922 ("%s: TOM activated but softc NULL", __func__)); 10923 KASSERT(uld_active(sc, ULD_TOM), 10924 ("%s: TOM activated but flag not set", __func__)); 10925 } 10926 10927 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 10928 if (!uld_active(sc, ULD_IWARP)) 10929 (void) t4_activate_uld(sc, ULD_IWARP); 10930 if (!uld_active(sc, ULD_ISCSI)) 10931 (void) t4_activate_uld(sc, ULD_ISCSI); 10932 10933 pi->uld_vis++; 10934 setbit(&sc->offload_map, pi->port_id); 10935 } else { 10936 pi->uld_vis--; 10937 10938 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 10939 return (0); 10940 10941 KASSERT(uld_active(sc, ULD_TOM), 10942 ("%s: TOM never initialized?", __func__)); 10943 clrbit(&sc->offload_map, pi->port_id); 10944 } 10945 10946 return (0); 10947 } 10948 10949 /* 10950 * Add an upper layer driver to the global list. 10951 */ 10952 int 10953 t4_register_uld(struct uld_info *ui) 10954 { 10955 int rc = 0; 10956 struct uld_info *u; 10957 10958 sx_xlock(&t4_uld_list_lock); 10959 SLIST_FOREACH(u, &t4_uld_list, link) { 10960 if (u->uld_id == ui->uld_id) { 10961 rc = EEXIST; 10962 goto done; 10963 } 10964 } 10965 10966 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 10967 ui->refcount = 0; 10968 done: 10969 sx_xunlock(&t4_uld_list_lock); 10970 return (rc); 10971 } 10972 10973 int 10974 t4_unregister_uld(struct uld_info *ui) 10975 { 10976 int rc = EINVAL; 10977 struct uld_info *u; 10978 10979 sx_xlock(&t4_uld_list_lock); 10980 10981 SLIST_FOREACH(u, &t4_uld_list, link) { 10982 if (u == ui) { 10983 if (ui->refcount > 0) { 10984 rc = EBUSY; 10985 goto done; 10986 } 10987 10988 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 10989 rc = 0; 10990 goto done; 10991 } 10992 } 10993 done: 10994 sx_xunlock(&t4_uld_list_lock); 10995 return (rc); 10996 } 10997 10998 int 10999 t4_activate_uld(struct adapter *sc, int id) 11000 { 11001 int rc; 11002 struct uld_info *ui; 11003 11004 ASSERT_SYNCHRONIZED_OP(sc); 11005 11006 if (id < 0 || id > ULD_MAX) 11007 return (EINVAL); 11008 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 11009 11010 sx_slock(&t4_uld_list_lock); 11011 11012 SLIST_FOREACH(ui, &t4_uld_list, link) { 11013 if (ui->uld_id == id) { 11014 if (!(sc->flags & FULL_INIT_DONE)) { 11015 rc = adapter_full_init(sc); 11016 if (rc != 0) 11017 break; 11018 } 11019 11020 rc = ui->activate(sc); 11021 if (rc == 0) { 11022 setbit(&sc->active_ulds, id); 11023 ui->refcount++; 11024 } 11025 break; 11026 } 11027 } 11028 11029 sx_sunlock(&t4_uld_list_lock); 11030 11031 return (rc); 11032 } 11033 11034 int 11035 t4_deactivate_uld(struct adapter *sc, int id) 11036 { 11037 int rc; 11038 struct uld_info *ui; 11039 11040 ASSERT_SYNCHRONIZED_OP(sc); 11041 11042 if (id < 0 || id > ULD_MAX) 11043 return (EINVAL); 11044 rc = ENXIO; 11045 11046 sx_slock(&t4_uld_list_lock); 11047 11048 SLIST_FOREACH(ui, &t4_uld_list, link) { 11049 if (ui->uld_id == id) { 11050 rc = ui->deactivate(sc); 11051 if (rc == 0) { 11052 clrbit(&sc->active_ulds, id); 11053 ui->refcount--; 11054 } 11055 break; 11056 } 11057 } 11058 11059 sx_sunlock(&t4_uld_list_lock); 11060 11061 return (rc); 11062 } 11063 11064 static void 11065 t4_async_event(void *arg, int n) 11066 { 11067 struct uld_info *ui; 11068 struct adapter *sc = (struct adapter *)arg; 11069 11070 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4async") != 0) 11071 return; 11072 sx_slock(&t4_uld_list_lock); 11073 SLIST_FOREACH(ui, &t4_uld_list, link) { 11074 if (ui->uld_id == ULD_IWARP) { 11075 ui->async_event(sc); 11076 break; 11077 } 11078 } 11079 sx_sunlock(&t4_uld_list_lock); 11080 end_synchronized_op(sc, 0); 11081 } 11082 11083 int 11084 uld_active(struct adapter *sc, int uld_id) 11085 { 11086 11087 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 11088 11089 return (isset(&sc->active_ulds, uld_id)); 11090 } 11091 #endif 11092 11093 /* 11094 * t = ptr to tunable. 11095 * nc = number of CPUs. 11096 * c = compiled in default for that tunable. 11097 */ 11098 static void 11099 calculate_nqueues(int *t, int nc, const int c) 11100 { 11101 int nq; 11102 11103 if (*t > 0) 11104 return; 11105 nq = *t < 0 ? -*t : c; 11106 *t = min(nc, nq); 11107 } 11108 11109 /* 11110 * Come up with reasonable defaults for some of the tunables, provided they're 11111 * not set by the user (in which case we'll use the values as is). 11112 */ 11113 static void 11114 tweak_tunables(void) 11115 { 11116 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 11117 11118 if (t4_ntxq < 1) { 11119 #ifdef RSS 11120 t4_ntxq = rss_getnumbuckets(); 11121 #else 11122 calculate_nqueues(&t4_ntxq, nc, NTXQ); 11123 #endif 11124 } 11125 11126 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 11127 11128 if (t4_nrxq < 1) { 11129 #ifdef RSS 11130 t4_nrxq = rss_getnumbuckets(); 11131 #else 11132 calculate_nqueues(&t4_nrxq, nc, NRXQ); 11133 #endif 11134 } 11135 11136 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 11137 11138 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 11139 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 11140 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 11141 #endif 11142 #ifdef TCP_OFFLOAD 11143 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 11144 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 11145 #endif 11146 11147 #if defined(TCP_OFFLOAD) || defined(KERN_TLS) 11148 if (t4_toecaps_allowed == -1) 11149 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 11150 #else 11151 if (t4_toecaps_allowed == -1) 11152 t4_toecaps_allowed = 0; 11153 #endif 11154 11155 #ifdef TCP_OFFLOAD 11156 if (t4_rdmacaps_allowed == -1) { 11157 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 11158 FW_CAPS_CONFIG_RDMA_RDMAC; 11159 } 11160 11161 if (t4_iscsicaps_allowed == -1) { 11162 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 11163 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 11164 FW_CAPS_CONFIG_ISCSI_T10DIF; 11165 } 11166 11167 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 11168 t4_tmr_idx_ofld = TMR_IDX_OFLD; 11169 11170 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 11171 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 11172 #else 11173 if (t4_rdmacaps_allowed == -1) 11174 t4_rdmacaps_allowed = 0; 11175 11176 if (t4_iscsicaps_allowed == -1) 11177 t4_iscsicaps_allowed = 0; 11178 #endif 11179 11180 #ifdef DEV_NETMAP 11181 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ); 11182 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ); 11183 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 11184 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 11185 #endif 11186 11187 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 11188 t4_tmr_idx = TMR_IDX; 11189 11190 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 11191 t4_pktc_idx = PKTC_IDX; 11192 11193 if (t4_qsize_txq < 128) 11194 t4_qsize_txq = 128; 11195 11196 if (t4_qsize_rxq < 128) 11197 t4_qsize_rxq = 128; 11198 while (t4_qsize_rxq & 7) 11199 t4_qsize_rxq++; 11200 11201 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 11202 11203 /* 11204 * Number of VIs to create per-port. The first VI is the "main" regular 11205 * VI for the port. The rest are additional virtual interfaces on the 11206 * same physical port. Note that the main VI does not have native 11207 * netmap support but the extra VIs do. 11208 * 11209 * Limit the number of VIs per port to the number of available 11210 * MAC addresses per port. 11211 */ 11212 if (t4_num_vis < 1) 11213 t4_num_vis = 1; 11214 if (t4_num_vis > nitems(vi_mac_funcs)) { 11215 t4_num_vis = nitems(vi_mac_funcs); 11216 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 11217 } 11218 11219 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 11220 pcie_relaxed_ordering = 1; 11221 #if defined(__i386__) || defined(__amd64__) 11222 if (cpu_vendor_id == CPU_VENDOR_INTEL) 11223 pcie_relaxed_ordering = 0; 11224 #endif 11225 } 11226 } 11227 11228 #ifdef DDB 11229 static void 11230 t4_dump_tcb(struct adapter *sc, int tid) 11231 { 11232 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 11233 11234 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 11235 save = t4_read_reg(sc, reg); 11236 base = sc->memwin[2].mw_base; 11237 11238 /* Dump TCB for the tid */ 11239 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 11240 tcb_addr += tid * TCB_SIZE; 11241 11242 if (is_t4(sc)) { 11243 pf = 0; 11244 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 11245 } else { 11246 pf = V_PFNUM(sc->pf); 11247 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 11248 } 11249 t4_write_reg(sc, reg, win_pos | pf); 11250 t4_read_reg(sc, reg); 11251 11252 off = tcb_addr - win_pos; 11253 for (i = 0; i < 4; i++) { 11254 uint32_t buf[8]; 11255 for (j = 0; j < 8; j++, off += 4) 11256 buf[j] = htonl(t4_read_reg(sc, base + off)); 11257 11258 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 11259 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 11260 buf[7]); 11261 } 11262 11263 t4_write_reg(sc, reg, save); 11264 t4_read_reg(sc, reg); 11265 } 11266 11267 static void 11268 t4_dump_devlog(struct adapter *sc) 11269 { 11270 struct devlog_params *dparams = &sc->params.devlog; 11271 struct fw_devlog_e e; 11272 int i, first, j, m, nentries, rc; 11273 uint64_t ftstamp = UINT64_MAX; 11274 11275 if (dparams->start == 0) { 11276 db_printf("devlog params not valid\n"); 11277 return; 11278 } 11279 11280 nentries = dparams->size / sizeof(struct fw_devlog_e); 11281 m = fwmtype_to_hwmtype(dparams->memtype); 11282 11283 /* Find the first entry. */ 11284 first = -1; 11285 for (i = 0; i < nentries && !db_pager_quit; i++) { 11286 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 11287 sizeof(e), (void *)&e); 11288 if (rc != 0) 11289 break; 11290 11291 if (e.timestamp == 0) 11292 break; 11293 11294 e.timestamp = be64toh(e.timestamp); 11295 if (e.timestamp < ftstamp) { 11296 ftstamp = e.timestamp; 11297 first = i; 11298 } 11299 } 11300 11301 if (first == -1) 11302 return; 11303 11304 i = first; 11305 do { 11306 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 11307 sizeof(e), (void *)&e); 11308 if (rc != 0) 11309 return; 11310 11311 if (e.timestamp == 0) 11312 return; 11313 11314 e.timestamp = be64toh(e.timestamp); 11315 e.seqno = be32toh(e.seqno); 11316 for (j = 0; j < 8; j++) 11317 e.params[j] = be32toh(e.params[j]); 11318 11319 db_printf("%10d %15ju %8s %8s ", 11320 e.seqno, e.timestamp, 11321 (e.level < nitems(devlog_level_strings) ? 11322 devlog_level_strings[e.level] : "UNKNOWN"), 11323 (e.facility < nitems(devlog_facility_strings) ? 11324 devlog_facility_strings[e.facility] : "UNKNOWN")); 11325 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 11326 e.params[3], e.params[4], e.params[5], e.params[6], 11327 e.params[7]); 11328 11329 if (++i == nentries) 11330 i = 0; 11331 } while (i != first && !db_pager_quit); 11332 } 11333 11334 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 11335 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 11336 11337 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 11338 { 11339 device_t dev; 11340 int t; 11341 bool valid; 11342 11343 valid = false; 11344 t = db_read_token(); 11345 if (t == tIDENT) { 11346 dev = device_lookup_by_name(db_tok_string); 11347 valid = true; 11348 } 11349 db_skip_to_eol(); 11350 if (!valid) { 11351 db_printf("usage: show t4 devlog <nexus>\n"); 11352 return; 11353 } 11354 11355 if (dev == NULL) { 11356 db_printf("device not found\n"); 11357 return; 11358 } 11359 11360 t4_dump_devlog(device_get_softc(dev)); 11361 } 11362 11363 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 11364 { 11365 device_t dev; 11366 int radix, tid, t; 11367 bool valid; 11368 11369 valid = false; 11370 radix = db_radix; 11371 db_radix = 10; 11372 t = db_read_token(); 11373 if (t == tIDENT) { 11374 dev = device_lookup_by_name(db_tok_string); 11375 t = db_read_token(); 11376 if (t == tNUMBER) { 11377 tid = db_tok_number; 11378 valid = true; 11379 } 11380 } 11381 db_radix = radix; 11382 db_skip_to_eol(); 11383 if (!valid) { 11384 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 11385 return; 11386 } 11387 11388 if (dev == NULL) { 11389 db_printf("device not found\n"); 11390 return; 11391 } 11392 if (tid < 0) { 11393 db_printf("invalid tid\n"); 11394 return; 11395 } 11396 11397 t4_dump_tcb(device_get_softc(dev), tid); 11398 } 11399 #endif 11400 11401 static eventhandler_tag vxlan_start_evtag; 11402 static eventhandler_tag vxlan_stop_evtag; 11403 11404 struct vxlan_evargs { 11405 struct ifnet *ifp; 11406 uint16_t port; 11407 }; 11408 11409 static void 11410 t4_vxlan_start(struct adapter *sc, void *arg) 11411 { 11412 struct vxlan_evargs *v = arg; 11413 struct port_info *pi; 11414 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 11415 int i, rc; 11416 11417 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 11418 return; 11419 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0) 11420 return; 11421 11422 if (sc->vxlan_refcount == 0) { 11423 sc->vxlan_port = v->port; 11424 sc->vxlan_refcount = 1; 11425 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, 11426 V_VXLAN(v->port) | F_VXLAN_EN); 11427 for_each_port(sc, i) { 11428 pi = sc->port[i]; 11429 if (pi->vxlan_tcam_entry == true) 11430 continue; 11431 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, 11432 match_all_mac, match_all_mac, 11433 sc->rawf_base + pi->port_id, 1, pi->port_id, true); 11434 if (rc < 0) { 11435 rc = -rc; 11436 log(LOG_ERR, 11437 "%s: failed to add VXLAN TCAM entry: %d.\n", 11438 device_get_name(pi->vi[0].dev), rc); 11439 } else { 11440 MPASS(rc == sc->rawf_base + pi->port_id); 11441 rc = 0; 11442 pi->vxlan_tcam_entry = true; 11443 } 11444 } 11445 } else if (sc->vxlan_port == v->port) { 11446 sc->vxlan_refcount++; 11447 } else { 11448 log(LOG_ERR, "%s: VXLAN already configured on port %d; " 11449 "ignoring attempt to configure it on port %d\n", 11450 device_get_nameunit(sc->dev), sc->vxlan_port, v->port); 11451 } 11452 end_synchronized_op(sc, 0); 11453 } 11454 11455 static void 11456 t4_vxlan_stop(struct adapter *sc, void *arg) 11457 { 11458 struct vxlan_evargs *v = arg; 11459 11460 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 11461 return; 11462 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0) 11463 return; 11464 11465 /* 11466 * VXLANs may have been configured before the driver was loaded so we 11467 * may see more stops than starts. This is not handled cleanly but at 11468 * least we keep the refcount sane. 11469 */ 11470 if (sc->vxlan_port != v->port) 11471 goto done; 11472 if (sc->vxlan_refcount == 0) { 11473 log(LOG_ERR, 11474 "%s: VXLAN operation on port %d was stopped earlier; " 11475 "ignoring attempt to stop it again.\n", 11476 device_get_nameunit(sc->dev), sc->vxlan_port); 11477 } else if (--sc->vxlan_refcount == 0) { 11478 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0); 11479 } 11480 done: 11481 end_synchronized_op(sc, 0); 11482 } 11483 11484 static void 11485 t4_vxlan_start_handler(void *arg __unused, struct ifnet *ifp, 11486 sa_family_t family, u_int port) 11487 { 11488 struct vxlan_evargs v; 11489 11490 MPASS(family == AF_INET || family == AF_INET6); 11491 v.ifp = ifp; 11492 v.port = port; 11493 11494 t4_iterate(t4_vxlan_start, &v); 11495 } 11496 11497 static void 11498 t4_vxlan_stop_handler(void *arg __unused, struct ifnet *ifp, sa_family_t family, 11499 u_int port) 11500 { 11501 struct vxlan_evargs v; 11502 11503 MPASS(family == AF_INET || family == AF_INET6); 11504 v.ifp = ifp; 11505 v.port = port; 11506 11507 t4_iterate(t4_vxlan_stop, &v); 11508 } 11509 11510 11511 static struct sx mlu; /* mod load unload */ 11512 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 11513 11514 static int 11515 mod_event(module_t mod, int cmd, void *arg) 11516 { 11517 int rc = 0; 11518 static int loaded = 0; 11519 11520 switch (cmd) { 11521 case MOD_LOAD: 11522 sx_xlock(&mlu); 11523 if (loaded++ == 0) { 11524 t4_sge_modload(); 11525 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 11526 t4_filter_rpl, CPL_COOKIE_FILTER); 11527 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 11528 do_l2t_write_rpl, CPL_COOKIE_FILTER); 11529 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 11530 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 11531 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 11532 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 11533 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 11534 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 11535 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 11536 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 11537 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 11538 do_smt_write_rpl); 11539 sx_init(&t4_list_lock, "T4/T5 adapters"); 11540 SLIST_INIT(&t4_list); 11541 callout_init(&fatal_callout, 1); 11542 #ifdef TCP_OFFLOAD 11543 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 11544 SLIST_INIT(&t4_uld_list); 11545 #endif 11546 #ifdef INET6 11547 t4_clip_modload(); 11548 #endif 11549 #ifdef KERN_TLS 11550 t6_ktls_modload(); 11551 #endif 11552 t4_tracer_modload(); 11553 tweak_tunables(); 11554 vxlan_start_evtag = 11555 EVENTHANDLER_REGISTER(vxlan_start, 11556 t4_vxlan_start_handler, NULL, 11557 EVENTHANDLER_PRI_ANY); 11558 vxlan_stop_evtag = 11559 EVENTHANDLER_REGISTER(vxlan_stop, 11560 t4_vxlan_stop_handler, NULL, 11561 EVENTHANDLER_PRI_ANY); 11562 } 11563 sx_xunlock(&mlu); 11564 break; 11565 11566 case MOD_UNLOAD: 11567 sx_xlock(&mlu); 11568 if (--loaded == 0) { 11569 int tries; 11570 11571 sx_slock(&t4_list_lock); 11572 if (!SLIST_EMPTY(&t4_list)) { 11573 rc = EBUSY; 11574 sx_sunlock(&t4_list_lock); 11575 goto done_unload; 11576 } 11577 #ifdef TCP_OFFLOAD 11578 sx_slock(&t4_uld_list_lock); 11579 if (!SLIST_EMPTY(&t4_uld_list)) { 11580 rc = EBUSY; 11581 sx_sunlock(&t4_uld_list_lock); 11582 sx_sunlock(&t4_list_lock); 11583 goto done_unload; 11584 } 11585 #endif 11586 tries = 0; 11587 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 11588 uprintf("%ju clusters with custom free routine " 11589 "still is use.\n", t4_sge_extfree_refs()); 11590 pause("t4unload", 2 * hz); 11591 } 11592 #ifdef TCP_OFFLOAD 11593 sx_sunlock(&t4_uld_list_lock); 11594 #endif 11595 sx_sunlock(&t4_list_lock); 11596 11597 if (t4_sge_extfree_refs() == 0) { 11598 EVENTHANDLER_DEREGISTER(vxlan_start, 11599 vxlan_start_evtag); 11600 EVENTHANDLER_DEREGISTER(vxlan_stop, 11601 vxlan_stop_evtag); 11602 t4_tracer_modunload(); 11603 #ifdef KERN_TLS 11604 t6_ktls_modunload(); 11605 #endif 11606 #ifdef INET6 11607 t4_clip_modunload(); 11608 #endif 11609 #ifdef TCP_OFFLOAD 11610 sx_destroy(&t4_uld_list_lock); 11611 #endif 11612 sx_destroy(&t4_list_lock); 11613 t4_sge_modunload(); 11614 loaded = 0; 11615 } else { 11616 rc = EBUSY; 11617 loaded++; /* undo earlier decrement */ 11618 } 11619 } 11620 done_unload: 11621 sx_xunlock(&mlu); 11622 break; 11623 } 11624 11625 return (rc); 11626 } 11627 11628 static devclass_t t4_devclass, t5_devclass, t6_devclass; 11629 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 11630 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 11631 11632 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 11633 MODULE_VERSION(t4nex, 1); 11634 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 11635 #ifdef DEV_NETMAP 11636 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 11637 #endif /* DEV_NETMAP */ 11638 11639 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 11640 MODULE_VERSION(t5nex, 1); 11641 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 11642 #ifdef DEV_NETMAP 11643 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 11644 #endif /* DEV_NETMAP */ 11645 11646 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 11647 MODULE_VERSION(t6nex, 1); 11648 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 11649 #ifdef DEV_NETMAP 11650 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 11651 #endif /* DEV_NETMAP */ 11652 11653 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 11654 MODULE_VERSION(cxgbe, 1); 11655 11656 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 11657 MODULE_VERSION(cxl, 1); 11658 11659 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 11660 MODULE_VERSION(cc, 1); 11661 11662 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 11663 MODULE_VERSION(vcxgbe, 1); 11664 11665 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 11666 MODULE_VERSION(vcxl, 1); 11667 11668 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 11669 MODULE_VERSION(vcc, 1); 11670