1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ddb.h" 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_rss.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/priv.h> 39 #include <sys/kernel.h> 40 #include <sys/bus.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pci_private.h> 49 #include <sys/firmware.h> 50 #include <sys/sbuf.h> 51 #include <sys/smp.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_types.h> 58 #include <net/if_dl.h> 59 #include <net/if_vlan_var.h> 60 #ifdef RSS 61 #include <net/rss_config.h> 62 #endif 63 #if defined(__i386__) || defined(__amd64__) 64 #include <vm/vm.h> 65 #include <vm/pmap.h> 66 #endif 67 #ifdef DDB 68 #include <ddb/ddb.h> 69 #include <ddb/db_lex.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_msg.h" 74 #include "common/t4_regs.h" 75 #include "common/t4_regs_values.h" 76 #include "t4_ioctl.h" 77 #include "t4_l2t.h" 78 #include "t4_mp_ring.h" 79 #include "t4_if.h" 80 81 /* T4 bus driver interface */ 82 static int t4_probe(device_t); 83 static int t4_attach(device_t); 84 static int t4_detach(device_t); 85 static int t4_ready(device_t); 86 static int t4_read_port_device(device_t, int, device_t *); 87 static device_method_t t4_methods[] = { 88 DEVMETHOD(device_probe, t4_probe), 89 DEVMETHOD(device_attach, t4_attach), 90 DEVMETHOD(device_detach, t4_detach), 91 92 DEVMETHOD(t4_is_main_ready, t4_ready), 93 DEVMETHOD(t4_read_port_device, t4_read_port_device), 94 95 DEVMETHOD_END 96 }; 97 static driver_t t4_driver = { 98 "t4nex", 99 t4_methods, 100 sizeof(struct adapter) 101 }; 102 103 104 /* T4 port (cxgbe) interface */ 105 static int cxgbe_probe(device_t); 106 static int cxgbe_attach(device_t); 107 static int cxgbe_detach(device_t); 108 device_method_t cxgbe_methods[] = { 109 DEVMETHOD(device_probe, cxgbe_probe), 110 DEVMETHOD(device_attach, cxgbe_attach), 111 DEVMETHOD(device_detach, cxgbe_detach), 112 { 0, 0 } 113 }; 114 static driver_t cxgbe_driver = { 115 "cxgbe", 116 cxgbe_methods, 117 sizeof(struct port_info) 118 }; 119 120 /* T4 VI (vcxgbe) interface */ 121 static int vcxgbe_probe(device_t); 122 static int vcxgbe_attach(device_t); 123 static int vcxgbe_detach(device_t); 124 static device_method_t vcxgbe_methods[] = { 125 DEVMETHOD(device_probe, vcxgbe_probe), 126 DEVMETHOD(device_attach, vcxgbe_attach), 127 DEVMETHOD(device_detach, vcxgbe_detach), 128 { 0, 0 } 129 }; 130 static driver_t vcxgbe_driver = { 131 "vcxgbe", 132 vcxgbe_methods, 133 sizeof(struct vi_info) 134 }; 135 136 static d_ioctl_t t4_ioctl; 137 138 static struct cdevsw t4_cdevsw = { 139 .d_version = D_VERSION, 140 .d_ioctl = t4_ioctl, 141 .d_name = "t4nex", 142 }; 143 144 /* T5 bus driver interface */ 145 static int t5_probe(device_t); 146 static device_method_t t5_methods[] = { 147 DEVMETHOD(device_probe, t5_probe), 148 DEVMETHOD(device_attach, t4_attach), 149 DEVMETHOD(device_detach, t4_detach), 150 151 DEVMETHOD(t4_is_main_ready, t4_ready), 152 DEVMETHOD(t4_read_port_device, t4_read_port_device), 153 154 DEVMETHOD_END 155 }; 156 static driver_t t5_driver = { 157 "t5nex", 158 t5_methods, 159 sizeof(struct adapter) 160 }; 161 162 163 /* T5 port (cxl) interface */ 164 static driver_t cxl_driver = { 165 "cxl", 166 cxgbe_methods, 167 sizeof(struct port_info) 168 }; 169 170 /* T5 VI (vcxl) interface */ 171 static driver_t vcxl_driver = { 172 "vcxl", 173 vcxgbe_methods, 174 sizeof(struct vi_info) 175 }; 176 177 /* T6 bus driver interface */ 178 static int t6_probe(device_t); 179 static device_method_t t6_methods[] = { 180 DEVMETHOD(device_probe, t6_probe), 181 DEVMETHOD(device_attach, t4_attach), 182 DEVMETHOD(device_detach, t4_detach), 183 184 DEVMETHOD(t4_is_main_ready, t4_ready), 185 DEVMETHOD(t4_read_port_device, t4_read_port_device), 186 187 DEVMETHOD_END 188 }; 189 static driver_t t6_driver = { 190 "t6nex", 191 t6_methods, 192 sizeof(struct adapter) 193 }; 194 195 196 /* T6 port (cc) interface */ 197 static driver_t cc_driver = { 198 "cc", 199 cxgbe_methods, 200 sizeof(struct port_info) 201 }; 202 203 /* T6 VI (vcc) interface */ 204 static driver_t vcc_driver = { 205 "vcc", 206 vcxgbe_methods, 207 sizeof(struct vi_info) 208 }; 209 210 /* ifnet + media interface */ 211 static void cxgbe_init(void *); 212 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 213 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 214 static void cxgbe_qflush(struct ifnet *); 215 static int cxgbe_media_change(struct ifnet *); 216 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 217 218 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 219 220 /* 221 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 222 * then ADAPTER_LOCK, then t4_uld_list_lock. 223 */ 224 static struct sx t4_list_lock; 225 SLIST_HEAD(, adapter) t4_list; 226 #ifdef TCP_OFFLOAD 227 static struct sx t4_uld_list_lock; 228 SLIST_HEAD(, uld_info) t4_uld_list; 229 #endif 230 231 /* 232 * Tunables. See tweak_tunables() too. 233 * 234 * Each tunable is set to a default value here if it's known at compile-time. 235 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should 236 * provide a reasonable default when the driver is loaded. 237 * 238 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 239 * T5 are under hw.cxl. 240 */ 241 242 /* 243 * Number of queues for tx and rx, 10G and 1G, NIC and offload. 244 */ 245 #define NTXQ_10G 16 246 int t4_ntxq10g = -1; 247 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g); 248 249 #define NRXQ_10G 8 250 int t4_nrxq10g = -1; 251 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g); 252 253 #define NTXQ_1G 4 254 int t4_ntxq1g = -1; 255 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g); 256 257 #define NRXQ_1G 2 258 int t4_nrxq1g = -1; 259 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g); 260 261 #define NTXQ_VI 1 262 static int t4_ntxq_vi = -1; 263 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi); 264 265 #define NRXQ_VI 1 266 static int t4_nrxq_vi = -1; 267 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi); 268 269 static int t4_rsrv_noflowq = 0; 270 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq); 271 272 #ifdef TCP_OFFLOAD 273 #define NOFLDTXQ_10G 8 274 static int t4_nofldtxq10g = -1; 275 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g); 276 277 #define NOFLDRXQ_10G 2 278 static int t4_nofldrxq10g = -1; 279 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g); 280 281 #define NOFLDTXQ_1G 2 282 static int t4_nofldtxq1g = -1; 283 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g); 284 285 #define NOFLDRXQ_1G 1 286 static int t4_nofldrxq1g = -1; 287 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g); 288 289 #define NOFLDTXQ_VI 1 290 static int t4_nofldtxq_vi = -1; 291 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi); 292 293 #define NOFLDRXQ_VI 1 294 static int t4_nofldrxq_vi = -1; 295 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi); 296 #endif 297 298 #ifdef DEV_NETMAP 299 #define NNMTXQ_VI 2 300 static int t4_nnmtxq_vi = -1; 301 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi); 302 303 #define NNMRXQ_VI 2 304 static int t4_nnmrxq_vi = -1; 305 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi); 306 #endif 307 308 /* 309 * Holdoff parameters for 10G and 1G ports. 310 */ 311 #define TMR_IDX_10G 1 312 int t4_tmr_idx_10g = TMR_IDX_10G; 313 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g); 314 315 #define PKTC_IDX_10G (-1) 316 int t4_pktc_idx_10g = PKTC_IDX_10G; 317 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g); 318 319 #define TMR_IDX_1G 1 320 int t4_tmr_idx_1g = TMR_IDX_1G; 321 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g); 322 323 #define PKTC_IDX_1G (-1) 324 int t4_pktc_idx_1g = PKTC_IDX_1G; 325 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g); 326 327 /* 328 * Size (# of entries) of each tx and rx queue. 329 */ 330 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 331 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 332 333 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 334 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 335 336 /* 337 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 338 */ 339 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 340 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 341 342 /* 343 * Configuration file. 344 */ 345 #define DEFAULT_CF "default" 346 #define FLASH_CF "flash" 347 #define UWIRE_CF "uwire" 348 #define FPGA_CF "fpga" 349 static char t4_cfg_file[32] = DEFAULT_CF; 350 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 351 352 /* 353 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively). 354 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 355 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 356 * mark or when signalled to do so, 0 to never emit PAUSE. 357 */ 358 static int t4_pause_settings = PAUSE_TX | PAUSE_RX; 359 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings); 360 361 /* 362 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 363 * encouraged respectively). 364 */ 365 static unsigned int t4_fw_install = 1; 366 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 367 368 /* 369 * ASIC features that will be used. Disable the ones you don't want so that the 370 * chip resources aren't wasted on features that will not be used. 371 */ 372 static int t4_nbmcaps_allowed = 0; 373 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed); 374 375 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 376 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 377 378 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 379 FW_CAPS_CONFIG_SWITCH_EGRESS; 380 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed); 381 382 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC; 383 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 384 385 static int t4_toecaps_allowed = -1; 386 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 387 388 static int t4_rdmacaps_allowed = -1; 389 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 390 391 static int t4_cryptocaps_allowed = 0; 392 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed); 393 394 static int t4_iscsicaps_allowed = -1; 395 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 396 397 static int t4_fcoecaps_allowed = 0; 398 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 399 400 static int t5_write_combine = 0; 401 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 402 403 static int t4_num_vis = 1; 404 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis); 405 406 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */ 407 static int vi_mac_funcs[] = { 408 FW_VI_FUNC_OFLD, 409 FW_VI_FUNC_IWARP, 410 FW_VI_FUNC_OPENISCSI, 411 FW_VI_FUNC_OPENFCOE, 412 FW_VI_FUNC_FOISCSI, 413 FW_VI_FUNC_FOFCOE, 414 }; 415 416 struct intrs_and_queues { 417 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 418 uint16_t nirq; /* Total # of vectors */ 419 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */ 420 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */ 421 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */ 422 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */ 423 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */ 424 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */ 425 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */ 426 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */ 427 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */ 428 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */ 429 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */ 430 431 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 432 uint16_t ntxq_vi; /* # of NIC txq's */ 433 uint16_t nrxq_vi; /* # of NIC rxq's */ 434 uint16_t nofldtxq_vi; /* # of TOE txq's */ 435 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 436 uint16_t nnmtxq_vi; /* # of netmap txq's */ 437 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 438 }; 439 440 struct filter_entry { 441 uint32_t valid:1; /* filter allocated and valid */ 442 uint32_t locked:1; /* filter is administratively locked */ 443 uint32_t pending:1; /* filter action is pending firmware reply */ 444 uint32_t smtidx:8; /* Source MAC Table index for smac */ 445 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 446 447 struct t4_filter_specification fs; 448 }; 449 450 static void setup_memwin(struct adapter *); 451 static void position_memwin(struct adapter *, int, uint32_t); 452 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 453 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *, 454 int); 455 static inline int write_via_memwin(struct adapter *, int, uint32_t, 456 const uint32_t *, int); 457 static int validate_mem_range(struct adapter *, uint32_t, int); 458 static int fwmtype_to_hwmtype(int); 459 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 460 uint32_t *); 461 static int fixup_devlog_params(struct adapter *); 462 static int cfg_itype_and_nqueues(struct adapter *, int, int, int, 463 struct intrs_and_queues *); 464 static int prep_firmware(struct adapter *); 465 static int partition_resources(struct adapter *, const struct firmware *, 466 const char *); 467 static int get_params__pre_init(struct adapter *); 468 static int get_params__post_init(struct adapter *); 469 static int set_params__post_init(struct adapter *); 470 static void t4_set_desc(struct adapter *); 471 static void build_medialist(struct port_info *, struct ifmedia *); 472 static int cxgbe_init_synchronized(struct vi_info *); 473 static int cxgbe_uninit_synchronized(struct vi_info *); 474 static void quiesce_txq(struct adapter *, struct sge_txq *); 475 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 476 static void quiesce_iq(struct adapter *, struct sge_iq *); 477 static void quiesce_fl(struct adapter *, struct sge_fl *); 478 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 479 driver_intr_t *, void *, char *); 480 static int t4_free_irq(struct adapter *, struct irq *); 481 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 482 static void vi_refresh_stats(struct adapter *, struct vi_info *); 483 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 484 static void cxgbe_tick(void *); 485 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 486 static void cxgbe_sysctls(struct port_info *); 487 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 488 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 489 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 490 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 491 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 492 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 493 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 494 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 495 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 496 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 497 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 498 #ifdef SBUF_DRAIN 499 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 500 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 501 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 502 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 503 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 504 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 505 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 506 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 507 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 508 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 509 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 510 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 511 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 512 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 513 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 514 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 515 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 516 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 517 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 518 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 519 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 520 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 521 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 522 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 523 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 524 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 525 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 526 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 527 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 528 #endif 529 #ifdef TCP_OFFLOAD 530 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 531 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 532 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 533 #endif 534 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t); 535 static uint32_t mode_to_fconf(uint32_t); 536 static uint32_t mode_to_iconf(uint32_t); 537 static int check_fspec_against_fconf_iconf(struct adapter *, 538 struct t4_filter_specification *); 539 static int get_filter_mode(struct adapter *, uint32_t *); 540 static int set_filter_mode(struct adapter *, uint32_t); 541 static inline uint64_t get_filter_hits(struct adapter *, uint32_t); 542 static int get_filter(struct adapter *, struct t4_filter *); 543 static int set_filter(struct adapter *, struct t4_filter *); 544 static int del_filter(struct adapter *, struct t4_filter *); 545 static void clear_filter(struct filter_entry *); 546 static int set_filter_wr(struct adapter *, int); 547 static int del_filter_wr(struct adapter *, int); 548 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *, 549 struct mbuf *); 550 static int get_sge_context(struct adapter *, struct t4_sge_context *); 551 static int load_fw(struct adapter *, struct t4_data *); 552 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 553 static int read_i2c(struct adapter *, struct t4_i2c_data *); 554 #ifdef TCP_OFFLOAD 555 static int toe_capability(struct vi_info *, int); 556 #endif 557 static int mod_event(module_t, int, void *); 558 static int notify_siblings(device_t, int); 559 560 struct { 561 uint16_t device; 562 char *desc; 563 } t4_pciids[] = { 564 {0xa000, "Chelsio Terminator 4 FPGA"}, 565 {0x4400, "Chelsio T440-dbg"}, 566 {0x4401, "Chelsio T420-CR"}, 567 {0x4402, "Chelsio T422-CR"}, 568 {0x4403, "Chelsio T440-CR"}, 569 {0x4404, "Chelsio T420-BCH"}, 570 {0x4405, "Chelsio T440-BCH"}, 571 {0x4406, "Chelsio T440-CH"}, 572 {0x4407, "Chelsio T420-SO"}, 573 {0x4408, "Chelsio T420-CX"}, 574 {0x4409, "Chelsio T420-BT"}, 575 {0x440a, "Chelsio T404-BT"}, 576 {0x440e, "Chelsio T440-LP-CR"}, 577 }, t5_pciids[] = { 578 {0xb000, "Chelsio Terminator 5 FPGA"}, 579 {0x5400, "Chelsio T580-dbg"}, 580 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 581 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 582 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 583 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 584 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 585 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 586 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 587 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 588 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 589 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 590 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 591 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 592 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 593 #ifdef notyet 594 {0x5404, "Chelsio T520-BCH"}, 595 {0x5405, "Chelsio T540-BCH"}, 596 {0x5406, "Chelsio T540-CH"}, 597 {0x5408, "Chelsio T520-CX"}, 598 {0x540b, "Chelsio B520-SR"}, 599 {0x540c, "Chelsio B504-BT"}, 600 {0x540f, "Chelsio Amsterdam"}, 601 {0x5413, "Chelsio T580-CHR"}, 602 #endif 603 }, t6_pciids[] = { 604 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 605 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 606 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 607 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 608 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 609 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 610 }; 611 612 #ifdef TCP_OFFLOAD 613 /* 614 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 615 * exactly the same for both rxq and ofld_rxq. 616 */ 617 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 618 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 619 #endif 620 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 621 622 static int 623 t4_probe(device_t dev) 624 { 625 int i; 626 uint16_t v = pci_get_vendor(dev); 627 uint16_t d = pci_get_device(dev); 628 uint8_t f = pci_get_function(dev); 629 630 if (v != PCI_VENDOR_ID_CHELSIO) 631 return (ENXIO); 632 633 /* Attach only to PF0 of the FPGA */ 634 if (d == 0xa000 && f != 0) 635 return (ENXIO); 636 637 for (i = 0; i < nitems(t4_pciids); i++) { 638 if (d == t4_pciids[i].device) { 639 device_set_desc(dev, t4_pciids[i].desc); 640 return (BUS_PROBE_DEFAULT); 641 } 642 } 643 644 return (ENXIO); 645 } 646 647 static int 648 t5_probe(device_t dev) 649 { 650 int i; 651 uint16_t v = pci_get_vendor(dev); 652 uint16_t d = pci_get_device(dev); 653 uint8_t f = pci_get_function(dev); 654 655 if (v != PCI_VENDOR_ID_CHELSIO) 656 return (ENXIO); 657 658 /* Attach only to PF0 of the FPGA */ 659 if (d == 0xb000 && f != 0) 660 return (ENXIO); 661 662 for (i = 0; i < nitems(t5_pciids); i++) { 663 if (d == t5_pciids[i].device) { 664 device_set_desc(dev, t5_pciids[i].desc); 665 return (BUS_PROBE_DEFAULT); 666 } 667 } 668 669 return (ENXIO); 670 } 671 672 static int 673 t6_probe(device_t dev) 674 { 675 int i; 676 uint16_t v = pci_get_vendor(dev); 677 uint16_t d = pci_get_device(dev); 678 679 if (v != PCI_VENDOR_ID_CHELSIO) 680 return (ENXIO); 681 682 for (i = 0; i < nitems(t6_pciids); i++) { 683 if (d == t6_pciids[i].device) { 684 device_set_desc(dev, t6_pciids[i].desc); 685 return (BUS_PROBE_DEFAULT); 686 } 687 } 688 689 return (ENXIO); 690 } 691 692 static void 693 t5_attribute_workaround(device_t dev) 694 { 695 device_t root_port; 696 uint32_t v; 697 698 /* 699 * The T5 chips do not properly echo the No Snoop and Relaxed 700 * Ordering attributes when replying to a TLP from a Root 701 * Port. As a workaround, find the parent Root Port and 702 * disable No Snoop and Relaxed Ordering. Note that this 703 * affects all devices under this root port. 704 */ 705 root_port = pci_find_pcie_root_port(dev); 706 if (root_port == NULL) { 707 device_printf(dev, "Unable to find parent root port\n"); 708 return; 709 } 710 711 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 712 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 713 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 714 0) 715 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 716 device_get_nameunit(root_port)); 717 } 718 719 static const struct devnames devnames[] = { 720 { 721 .nexus_name = "t4nex", 722 .ifnet_name = "cxgbe", 723 .vi_ifnet_name = "vcxgbe", 724 .pf03_drv_name = "t4iov", 725 .vf_nexus_name = "t4vf", 726 .vf_ifnet_name = "cxgbev" 727 }, { 728 .nexus_name = "t5nex", 729 .ifnet_name = "cxl", 730 .vi_ifnet_name = "vcxl", 731 .pf03_drv_name = "t5iov", 732 .vf_nexus_name = "t5vf", 733 .vf_ifnet_name = "cxlv" 734 }, { 735 .nexus_name = "t6nex", 736 .ifnet_name = "cc", 737 .vi_ifnet_name = "vcc", 738 .pf03_drv_name = "t6iov", 739 .vf_nexus_name = "t6vf", 740 .vf_ifnet_name = "ccv" 741 } 742 }; 743 744 void 745 t4_init_devnames(struct adapter *sc) 746 { 747 int id; 748 749 id = chip_id(sc); 750 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 751 sc->names = &devnames[id - CHELSIO_T4]; 752 else { 753 device_printf(sc->dev, "chip id %d is not supported.\n", id); 754 sc->names = NULL; 755 } 756 } 757 758 static int 759 t4_attach(device_t dev) 760 { 761 struct adapter *sc; 762 int rc = 0, i, j, n10g, n1g, rqidx, tqidx; 763 struct make_dev_args mda; 764 struct intrs_and_queues iaq; 765 struct sge *s; 766 uint8_t *buf; 767 #ifdef TCP_OFFLOAD 768 int ofld_rqidx, ofld_tqidx; 769 #endif 770 #ifdef DEV_NETMAP 771 int nm_rqidx, nm_tqidx; 772 #endif 773 int num_vis; 774 775 sc = device_get_softc(dev); 776 sc->dev = dev; 777 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 778 779 if ((pci_get_device(dev) & 0xff00) == 0x5400) 780 t5_attribute_workaround(dev); 781 pci_enable_busmaster(dev); 782 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 783 uint32_t v; 784 785 pci_set_max_read_req(dev, 4096); 786 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 787 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 788 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 789 790 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 791 } 792 793 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 794 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 795 sc->traceq = -1; 796 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 797 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 798 device_get_nameunit(dev)); 799 800 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 801 device_get_nameunit(dev)); 802 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 803 t4_add_adapter(sc); 804 805 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 806 TAILQ_INIT(&sc->sfl); 807 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 808 809 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 810 811 rc = t4_map_bars_0_and_4(sc); 812 if (rc != 0) 813 goto done; /* error message displayed already */ 814 815 /* 816 * This is the real PF# to which we're attaching. Works from within PCI 817 * passthrough environments too, where pci_get_function() could return a 818 * different PF# depending on the passthrough configuration. We need to 819 * use the real PF# in all our communication with the firmware. 820 */ 821 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI)); 822 sc->mbox = sc->pf; 823 824 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 825 826 /* Prepare the adapter for operation. */ 827 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 828 rc = -t4_prep_adapter(sc, buf); 829 free(buf, M_CXGBE); 830 if (rc != 0) { 831 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 832 goto done; 833 } 834 835 t4_init_devnames(sc); 836 if (sc->names == NULL) { 837 rc = ENOTSUP; 838 goto done; /* error message displayed already */ 839 } 840 841 /* 842 * Do this really early, with the memory windows set up even before the 843 * character device. The userland tool's register i/o and mem read 844 * will work even in "recovery mode". 845 */ 846 setup_memwin(sc); 847 if (t4_init_devlog_params(sc, 0) == 0) 848 fixup_devlog_params(sc); 849 make_dev_args_init(&mda); 850 mda.mda_devsw = &t4_cdevsw; 851 mda.mda_uid = UID_ROOT; 852 mda.mda_gid = GID_WHEEL; 853 mda.mda_mode = 0600; 854 mda.mda_si_drv1 = sc; 855 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 856 if (rc != 0) 857 device_printf(dev, "failed to create nexus char device: %d.\n", 858 rc); 859 860 /* Go no further if recovery mode has been requested. */ 861 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 862 device_printf(dev, "recovery mode.\n"); 863 goto done; 864 } 865 866 #if defined(__i386__) 867 if ((cpu_feature & CPUID_CX8) == 0) { 868 device_printf(dev, "64 bit atomics not available.\n"); 869 rc = ENOTSUP; 870 goto done; 871 } 872 #endif 873 874 /* Prepare the firmware for operation */ 875 rc = prep_firmware(sc); 876 if (rc != 0) 877 goto done; /* error message displayed already */ 878 879 rc = get_params__post_init(sc); 880 if (rc != 0) 881 goto done; /* error message displayed already */ 882 883 rc = set_params__post_init(sc); 884 if (rc != 0) 885 goto done; /* error message displayed already */ 886 887 rc = t4_map_bar_2(sc); 888 if (rc != 0) 889 goto done; /* error message displayed already */ 890 891 rc = t4_create_dma_tag(sc); 892 if (rc != 0) 893 goto done; /* error message displayed already */ 894 895 /* 896 * Number of VIs to create per-port. The first VI is the "main" regular 897 * VI for the port. The rest are additional virtual interfaces on the 898 * same physical port. Note that the main VI does not have native 899 * netmap support but the extra VIs do. 900 * 901 * Limit the number of VIs per port to the number of available 902 * MAC addresses per port. 903 */ 904 if (t4_num_vis >= 1) 905 num_vis = t4_num_vis; 906 else 907 num_vis = 1; 908 if (num_vis > nitems(vi_mac_funcs)) { 909 num_vis = nitems(vi_mac_funcs); 910 device_printf(dev, "Number of VIs limited to %d\n", num_vis); 911 } 912 913 /* 914 * First pass over all the ports - allocate VIs and initialize some 915 * basic parameters like mac address, port type, etc. We also figure 916 * out whether a port is 10G or 1G and use that information when 917 * calculating how many interrupts to attempt to allocate. 918 */ 919 n10g = n1g = 0; 920 for_each_port(sc, i) { 921 struct port_info *pi; 922 923 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 924 sc->port[i] = pi; 925 926 /* These must be set before t4_port_init */ 927 pi->adapter = sc; 928 pi->port_id = i; 929 /* 930 * XXX: vi[0] is special so we can't delay this allocation until 931 * pi->nvi's final value is known. 932 */ 933 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE, 934 M_ZERO | M_WAITOK); 935 936 /* 937 * Allocate the "main" VI and initialize parameters 938 * like mac addr. 939 */ 940 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 941 if (rc != 0) { 942 device_printf(dev, "unable to initialize port %d: %d\n", 943 i, rc); 944 free(pi->vi, M_CXGBE); 945 free(pi, M_CXGBE); 946 sc->port[i] = NULL; 947 goto done; 948 } 949 950 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX); 951 pi->link_cfg.requested_fc |= t4_pause_settings; 952 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX); 953 pi->link_cfg.fc |= t4_pause_settings; 954 955 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, &pi->link_cfg); 956 if (rc != 0) { 957 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc); 958 free(pi->vi, M_CXGBE); 959 free(pi, M_CXGBE); 960 sc->port[i] = NULL; 961 goto done; 962 } 963 964 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 965 device_get_nameunit(dev), i); 966 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 967 sc->chan_map[pi->tx_chan] = i; 968 969 pi->tc = malloc(sizeof(struct tx_sched_class) * 970 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK); 971 972 if (is_10G_port(pi) || is_40G_port(pi)) { 973 n10g++; 974 } else { 975 n1g++; 976 } 977 978 pi->linkdnrc = -1; 979 980 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1); 981 if (pi->dev == NULL) { 982 device_printf(dev, 983 "failed to add device for port %d.\n", i); 984 rc = ENXIO; 985 goto done; 986 } 987 pi->vi[0].dev = pi->dev; 988 device_set_softc(pi->dev, pi); 989 } 990 991 /* 992 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 993 */ 994 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq); 995 if (rc != 0) 996 goto done; /* error message displayed already */ 997 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0) 998 num_vis = 1; 999 1000 sc->intr_type = iaq.intr_type; 1001 sc->intr_count = iaq.nirq; 1002 1003 s = &sc->sge; 1004 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; 1005 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; 1006 if (num_vis > 1) { 1007 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi; 1008 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi; 1009 } 1010 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1011 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 1012 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1013 #ifdef TCP_OFFLOAD 1014 if (is_offload(sc)) { 1015 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g; 1016 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g; 1017 if (num_vis > 1) { 1018 s->nofldrxq += (n10g + n1g) * (num_vis - 1) * 1019 iaq.nofldrxq_vi; 1020 s->nofldtxq += (n10g + n1g) * (num_vis - 1) * 1021 iaq.nofldtxq_vi; 1022 } 1023 s->neq += s->nofldtxq + s->nofldrxq; 1024 s->niq += s->nofldrxq; 1025 1026 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1027 M_CXGBE, M_ZERO | M_WAITOK); 1028 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1029 M_CXGBE, M_ZERO | M_WAITOK); 1030 } 1031 #endif 1032 #ifdef DEV_NETMAP 1033 if (num_vis > 1) { 1034 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi; 1035 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi; 1036 } 1037 s->neq += s->nnmtxq + s->nnmrxq; 1038 s->niq += s->nnmrxq; 1039 1040 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1041 M_CXGBE, M_ZERO | M_WAITOK); 1042 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1043 M_CXGBE, M_ZERO | M_WAITOK); 1044 #endif 1045 1046 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE, 1047 M_ZERO | M_WAITOK); 1048 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1049 M_ZERO | M_WAITOK); 1050 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1051 M_ZERO | M_WAITOK); 1052 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1053 M_ZERO | M_WAITOK); 1054 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1055 M_ZERO | M_WAITOK); 1056 1057 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1058 M_ZERO | M_WAITOK); 1059 1060 t4_init_l2t(sc, M_WAITOK); 1061 1062 /* 1063 * Second pass over the ports. This time we know the number of rx and 1064 * tx queues that each port should get. 1065 */ 1066 rqidx = tqidx = 0; 1067 #ifdef TCP_OFFLOAD 1068 ofld_rqidx = ofld_tqidx = 0; 1069 #endif 1070 #ifdef DEV_NETMAP 1071 nm_rqidx = nm_tqidx = 0; 1072 #endif 1073 for_each_port(sc, i) { 1074 struct port_info *pi = sc->port[i]; 1075 struct vi_info *vi; 1076 1077 if (pi == NULL) 1078 continue; 1079 1080 pi->nvi = num_vis; 1081 for_each_vi(pi, j, vi) { 1082 vi->pi = pi; 1083 vi->qsize_rxq = t4_qsize_rxq; 1084 vi->qsize_txq = t4_qsize_txq; 1085 1086 vi->first_rxq = rqidx; 1087 vi->first_txq = tqidx; 1088 if (is_10G_port(pi) || is_40G_port(pi)) { 1089 vi->tmr_idx = t4_tmr_idx_10g; 1090 vi->pktc_idx = t4_pktc_idx_10g; 1091 vi->flags |= iaq.intr_flags_10g & INTR_RXQ; 1092 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi; 1093 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi; 1094 } else { 1095 vi->tmr_idx = t4_tmr_idx_1g; 1096 vi->pktc_idx = t4_pktc_idx_1g; 1097 vi->flags |= iaq.intr_flags_1g & INTR_RXQ; 1098 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi; 1099 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi; 1100 } 1101 rqidx += vi->nrxq; 1102 tqidx += vi->ntxq; 1103 1104 if (j == 0 && vi->ntxq > 1) 1105 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0; 1106 else 1107 vi->rsrv_noflowq = 0; 1108 1109 #ifdef TCP_OFFLOAD 1110 vi->first_ofld_rxq = ofld_rqidx; 1111 vi->first_ofld_txq = ofld_tqidx; 1112 if (is_10G_port(pi) || is_40G_port(pi)) { 1113 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ; 1114 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g : 1115 iaq.nofldrxq_vi; 1116 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g : 1117 iaq.nofldtxq_vi; 1118 } else { 1119 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ; 1120 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g : 1121 iaq.nofldrxq_vi; 1122 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g : 1123 iaq.nofldtxq_vi; 1124 } 1125 ofld_rqidx += vi->nofldrxq; 1126 ofld_tqidx += vi->nofldtxq; 1127 #endif 1128 #ifdef DEV_NETMAP 1129 if (j > 0) { 1130 vi->first_nm_rxq = nm_rqidx; 1131 vi->first_nm_txq = nm_tqidx; 1132 vi->nnmrxq = iaq.nnmrxq_vi; 1133 vi->nnmtxq = iaq.nnmtxq_vi; 1134 nm_rqidx += vi->nnmrxq; 1135 nm_tqidx += vi->nnmtxq; 1136 } 1137 #endif 1138 } 1139 } 1140 1141 rc = t4_setup_intr_handlers(sc); 1142 if (rc != 0) { 1143 device_printf(dev, 1144 "failed to setup interrupt handlers: %d\n", rc); 1145 goto done; 1146 } 1147 1148 rc = bus_generic_attach(dev); 1149 if (rc != 0) { 1150 device_printf(dev, 1151 "failed to attach all child ports: %d\n", rc); 1152 goto done; 1153 } 1154 1155 device_printf(dev, 1156 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1157 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1158 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1159 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1160 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1161 1162 t4_set_desc(sc); 1163 1164 notify_siblings(dev, 0); 1165 1166 done: 1167 if (rc != 0 && sc->cdev) { 1168 /* cdev was created and so cxgbetool works; recover that way. */ 1169 device_printf(dev, 1170 "error during attach, adapter is now in recovery mode.\n"); 1171 rc = 0; 1172 } 1173 1174 if (rc != 0) 1175 t4_detach_common(dev); 1176 else 1177 t4_sysctls(sc); 1178 1179 return (rc); 1180 } 1181 1182 static int 1183 t4_ready(device_t dev) 1184 { 1185 struct adapter *sc; 1186 1187 sc = device_get_softc(dev); 1188 if (sc->flags & FW_OK) 1189 return (0); 1190 return (ENXIO); 1191 } 1192 1193 static int 1194 t4_read_port_device(device_t dev, int port, device_t *child) 1195 { 1196 struct adapter *sc; 1197 struct port_info *pi; 1198 1199 sc = device_get_softc(dev); 1200 if (port < 0 || port >= MAX_NPORTS) 1201 return (EINVAL); 1202 pi = sc->port[port]; 1203 if (pi == NULL || pi->dev == NULL) 1204 return (ENXIO); 1205 *child = pi->dev; 1206 return (0); 1207 } 1208 1209 static int 1210 notify_siblings(device_t dev, int detaching) 1211 { 1212 device_t sibling; 1213 int error, i; 1214 1215 error = 0; 1216 for (i = 0; i < PCI_FUNCMAX; i++) { 1217 if (i == pci_get_function(dev)) 1218 continue; 1219 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1220 pci_get_slot(dev), i); 1221 if (sibling == NULL || !device_is_attached(sibling)) 1222 continue; 1223 if (detaching) 1224 error = T4_DETACH_CHILD(sibling); 1225 else 1226 (void)T4_ATTACH_CHILD(sibling); 1227 if (error) 1228 break; 1229 } 1230 return (error); 1231 } 1232 1233 /* 1234 * Idempotent 1235 */ 1236 static int 1237 t4_detach(device_t dev) 1238 { 1239 struct adapter *sc; 1240 int rc; 1241 1242 sc = device_get_softc(dev); 1243 1244 rc = notify_siblings(dev, 1); 1245 if (rc) { 1246 device_printf(dev, 1247 "failed to detach sibling devices: %d\n", rc); 1248 return (rc); 1249 } 1250 1251 return (t4_detach_common(dev)); 1252 } 1253 1254 int 1255 t4_detach_common(device_t dev) 1256 { 1257 struct adapter *sc; 1258 struct port_info *pi; 1259 int i, rc; 1260 1261 sc = device_get_softc(dev); 1262 1263 if (sc->flags & FULL_INIT_DONE) { 1264 if (!(sc->flags & IS_VF)) 1265 t4_intr_disable(sc); 1266 } 1267 1268 if (sc->cdev) { 1269 destroy_dev(sc->cdev); 1270 sc->cdev = NULL; 1271 } 1272 1273 if (device_is_attached(dev)) { 1274 rc = bus_generic_detach(dev); 1275 if (rc) { 1276 device_printf(dev, 1277 "failed to detach child devices: %d\n", rc); 1278 return (rc); 1279 } 1280 } 1281 1282 for (i = 0; i < sc->intr_count; i++) 1283 t4_free_irq(sc, &sc->irq[i]); 1284 1285 for (i = 0; i < MAX_NPORTS; i++) { 1286 pi = sc->port[i]; 1287 if (pi) { 1288 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1289 if (pi->dev) 1290 device_delete_child(dev, pi->dev); 1291 1292 mtx_destroy(&pi->pi_lock); 1293 free(pi->vi, M_CXGBE); 1294 free(pi->tc, M_CXGBE); 1295 free(pi, M_CXGBE); 1296 } 1297 } 1298 1299 if (sc->flags & FULL_INIT_DONE) 1300 adapter_full_uninit(sc); 1301 1302 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1303 t4_fw_bye(sc, sc->mbox); 1304 1305 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1306 pci_release_msi(dev); 1307 1308 if (sc->regs_res) 1309 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1310 sc->regs_res); 1311 1312 if (sc->udbs_res) 1313 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1314 sc->udbs_res); 1315 1316 if (sc->msix_res) 1317 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1318 sc->msix_res); 1319 1320 if (sc->l2t) 1321 t4_free_l2t(sc->l2t); 1322 1323 #ifdef TCP_OFFLOAD 1324 free(sc->sge.ofld_rxq, M_CXGBE); 1325 free(sc->sge.ofld_txq, M_CXGBE); 1326 #endif 1327 #ifdef DEV_NETMAP 1328 free(sc->sge.nm_rxq, M_CXGBE); 1329 free(sc->sge.nm_txq, M_CXGBE); 1330 #endif 1331 free(sc->irq, M_CXGBE); 1332 free(sc->sge.rxq, M_CXGBE); 1333 free(sc->sge.txq, M_CXGBE); 1334 free(sc->sge.ctrlq, M_CXGBE); 1335 free(sc->sge.iqmap, M_CXGBE); 1336 free(sc->sge.eqmap, M_CXGBE); 1337 free(sc->tids.ftid_tab, M_CXGBE); 1338 t4_destroy_dma_tag(sc); 1339 if (mtx_initialized(&sc->sc_lock)) { 1340 sx_xlock(&t4_list_lock); 1341 SLIST_REMOVE(&t4_list, sc, adapter, link); 1342 sx_xunlock(&t4_list_lock); 1343 mtx_destroy(&sc->sc_lock); 1344 } 1345 1346 callout_drain(&sc->sfl_callout); 1347 if (mtx_initialized(&sc->tids.ftid_lock)) 1348 mtx_destroy(&sc->tids.ftid_lock); 1349 if (mtx_initialized(&sc->sfl_lock)) 1350 mtx_destroy(&sc->sfl_lock); 1351 if (mtx_initialized(&sc->ifp_lock)) 1352 mtx_destroy(&sc->ifp_lock); 1353 if (mtx_initialized(&sc->reg_lock)) 1354 mtx_destroy(&sc->reg_lock); 1355 1356 for (i = 0; i < NUM_MEMWIN; i++) { 1357 struct memwin *mw = &sc->memwin[i]; 1358 1359 if (rw_initialized(&mw->mw_lock)) 1360 rw_destroy(&mw->mw_lock); 1361 } 1362 1363 bzero(sc, sizeof(*sc)); 1364 1365 return (0); 1366 } 1367 1368 static int 1369 cxgbe_probe(device_t dev) 1370 { 1371 char buf[128]; 1372 struct port_info *pi = device_get_softc(dev); 1373 1374 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1375 device_set_desc_copy(dev, buf); 1376 1377 return (BUS_PROBE_DEFAULT); 1378 } 1379 1380 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1381 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1382 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1383 #define T4_CAP_ENABLE (T4_CAP) 1384 1385 static int 1386 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1387 { 1388 struct ifnet *ifp; 1389 struct sbuf *sb; 1390 1391 vi->xact_addr_filt = -1; 1392 callout_init(&vi->tick, 1); 1393 1394 /* Allocate an ifnet and set it up */ 1395 ifp = if_alloc(IFT_ETHER); 1396 if (ifp == NULL) { 1397 device_printf(dev, "Cannot allocate ifnet\n"); 1398 return (ENOMEM); 1399 } 1400 vi->ifp = ifp; 1401 ifp->if_softc = vi; 1402 1403 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1404 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1405 1406 ifp->if_init = cxgbe_init; 1407 ifp->if_ioctl = cxgbe_ioctl; 1408 ifp->if_transmit = cxgbe_transmit; 1409 ifp->if_qflush = cxgbe_qflush; 1410 ifp->if_get_counter = cxgbe_get_counter; 1411 1412 ifp->if_capabilities = T4_CAP; 1413 #ifdef TCP_OFFLOAD 1414 if (vi->nofldrxq != 0) 1415 ifp->if_capabilities |= IFCAP_TOE; 1416 #endif 1417 ifp->if_capenable = T4_CAP_ENABLE; 1418 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1419 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1420 1421 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1422 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1423 ifp->if_hw_tsomaxsegsize = 65536; 1424 1425 /* Initialize ifmedia for this VI */ 1426 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change, 1427 cxgbe_media_status); 1428 build_medialist(vi->pi, &vi->media); 1429 1430 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1431 EVENTHANDLER_PRI_ANY); 1432 1433 ether_ifattach(ifp, vi->hw_addr); 1434 #ifdef DEV_NETMAP 1435 if (vi->nnmrxq != 0) 1436 cxgbe_nm_attach(vi); 1437 #endif 1438 sb = sbuf_new_auto(); 1439 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1440 #ifdef TCP_OFFLOAD 1441 if (ifp->if_capabilities & IFCAP_TOE) 1442 sbuf_printf(sb, "; %d txq, %d rxq (TOE)", 1443 vi->nofldtxq, vi->nofldrxq); 1444 #endif 1445 #ifdef DEV_NETMAP 1446 if (ifp->if_capabilities & IFCAP_NETMAP) 1447 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1448 vi->nnmtxq, vi->nnmrxq); 1449 #endif 1450 sbuf_finish(sb); 1451 device_printf(dev, "%s\n", sbuf_data(sb)); 1452 sbuf_delete(sb); 1453 1454 vi_sysctls(vi); 1455 1456 return (0); 1457 } 1458 1459 static int 1460 cxgbe_attach(device_t dev) 1461 { 1462 struct port_info *pi = device_get_softc(dev); 1463 struct adapter *sc = pi->adapter; 1464 struct vi_info *vi; 1465 int i, rc; 1466 1467 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1468 1469 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1470 if (rc) 1471 return (rc); 1472 1473 for_each_vi(pi, i, vi) { 1474 if (i == 0) 1475 continue; 1476 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1477 if (vi->dev == NULL) { 1478 device_printf(dev, "failed to add VI %d\n", i); 1479 continue; 1480 } 1481 device_set_softc(vi->dev, vi); 1482 } 1483 1484 cxgbe_sysctls(pi); 1485 1486 bus_generic_attach(dev); 1487 1488 return (0); 1489 } 1490 1491 static void 1492 cxgbe_vi_detach(struct vi_info *vi) 1493 { 1494 struct ifnet *ifp = vi->ifp; 1495 1496 ether_ifdetach(ifp); 1497 1498 if (vi->vlan_c) 1499 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1500 1501 /* Let detach proceed even if these fail. */ 1502 #ifdef DEV_NETMAP 1503 if (ifp->if_capabilities & IFCAP_NETMAP) 1504 cxgbe_nm_detach(vi); 1505 #endif 1506 cxgbe_uninit_synchronized(vi); 1507 callout_drain(&vi->tick); 1508 vi_full_uninit(vi); 1509 1510 ifmedia_removeall(&vi->media); 1511 if_free(vi->ifp); 1512 vi->ifp = NULL; 1513 } 1514 1515 static int 1516 cxgbe_detach(device_t dev) 1517 { 1518 struct port_info *pi = device_get_softc(dev); 1519 struct adapter *sc = pi->adapter; 1520 int rc; 1521 1522 /* Detach the extra VIs first. */ 1523 rc = bus_generic_detach(dev); 1524 if (rc) 1525 return (rc); 1526 device_delete_children(dev); 1527 1528 doom_vi(sc, &pi->vi[0]); 1529 1530 if (pi->flags & HAS_TRACEQ) { 1531 sc->traceq = -1; /* cloner should not create ifnet */ 1532 t4_tracer_port_detach(sc); 1533 } 1534 1535 cxgbe_vi_detach(&pi->vi[0]); 1536 callout_drain(&pi->tick); 1537 1538 end_synchronized_op(sc, 0); 1539 1540 return (0); 1541 } 1542 1543 static void 1544 cxgbe_init(void *arg) 1545 { 1546 struct vi_info *vi = arg; 1547 struct adapter *sc = vi->pi->adapter; 1548 1549 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1550 return; 1551 cxgbe_init_synchronized(vi); 1552 end_synchronized_op(sc, 0); 1553 } 1554 1555 static int 1556 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1557 { 1558 int rc = 0, mtu, flags, can_sleep; 1559 struct vi_info *vi = ifp->if_softc; 1560 struct adapter *sc = vi->pi->adapter; 1561 struct ifreq *ifr = (struct ifreq *)data; 1562 uint32_t mask; 1563 1564 switch (cmd) { 1565 case SIOCSIFMTU: 1566 mtu = ifr->ifr_mtu; 1567 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) 1568 return (EINVAL); 1569 1570 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1571 if (rc) 1572 return (rc); 1573 ifp->if_mtu = mtu; 1574 if (vi->flags & VI_INIT_DONE) { 1575 t4_update_fl_bufsize(ifp); 1576 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1577 rc = update_mac_settings(ifp, XGMAC_MTU); 1578 } 1579 end_synchronized_op(sc, 0); 1580 break; 1581 1582 case SIOCSIFFLAGS: 1583 can_sleep = 0; 1584 redo_sifflags: 1585 rc = begin_synchronized_op(sc, vi, 1586 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1587 if (rc) 1588 return (rc); 1589 1590 if (ifp->if_flags & IFF_UP) { 1591 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1592 flags = vi->if_flags; 1593 if ((ifp->if_flags ^ flags) & 1594 (IFF_PROMISC | IFF_ALLMULTI)) { 1595 if (can_sleep == 1) { 1596 end_synchronized_op(sc, 0); 1597 can_sleep = 0; 1598 goto redo_sifflags; 1599 } 1600 rc = update_mac_settings(ifp, 1601 XGMAC_PROMISC | XGMAC_ALLMULTI); 1602 } 1603 } else { 1604 if (can_sleep == 0) { 1605 end_synchronized_op(sc, LOCK_HELD); 1606 can_sleep = 1; 1607 goto redo_sifflags; 1608 } 1609 rc = cxgbe_init_synchronized(vi); 1610 } 1611 vi->if_flags = ifp->if_flags; 1612 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1613 if (can_sleep == 0) { 1614 end_synchronized_op(sc, LOCK_HELD); 1615 can_sleep = 1; 1616 goto redo_sifflags; 1617 } 1618 rc = cxgbe_uninit_synchronized(vi); 1619 } 1620 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1621 break; 1622 1623 case SIOCADDMULTI: 1624 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1625 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1626 if (rc) 1627 return (rc); 1628 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1629 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1630 end_synchronized_op(sc, LOCK_HELD); 1631 break; 1632 1633 case SIOCSIFCAP: 1634 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1635 if (rc) 1636 return (rc); 1637 1638 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1639 if (mask & IFCAP_TXCSUM) { 1640 ifp->if_capenable ^= IFCAP_TXCSUM; 1641 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1642 1643 if (IFCAP_TSO4 & ifp->if_capenable && 1644 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1645 ifp->if_capenable &= ~IFCAP_TSO4; 1646 if_printf(ifp, 1647 "tso4 disabled due to -txcsum.\n"); 1648 } 1649 } 1650 if (mask & IFCAP_TXCSUM_IPV6) { 1651 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1652 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1653 1654 if (IFCAP_TSO6 & ifp->if_capenable && 1655 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1656 ifp->if_capenable &= ~IFCAP_TSO6; 1657 if_printf(ifp, 1658 "tso6 disabled due to -txcsum6.\n"); 1659 } 1660 } 1661 if (mask & IFCAP_RXCSUM) 1662 ifp->if_capenable ^= IFCAP_RXCSUM; 1663 if (mask & IFCAP_RXCSUM_IPV6) 1664 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1665 1666 /* 1667 * Note that we leave CSUM_TSO alone (it is always set). The 1668 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1669 * sending a TSO request our way, so it's sufficient to toggle 1670 * IFCAP_TSOx only. 1671 */ 1672 if (mask & IFCAP_TSO4) { 1673 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1674 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1675 if_printf(ifp, "enable txcsum first.\n"); 1676 rc = EAGAIN; 1677 goto fail; 1678 } 1679 ifp->if_capenable ^= IFCAP_TSO4; 1680 } 1681 if (mask & IFCAP_TSO6) { 1682 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1683 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1684 if_printf(ifp, "enable txcsum6 first.\n"); 1685 rc = EAGAIN; 1686 goto fail; 1687 } 1688 ifp->if_capenable ^= IFCAP_TSO6; 1689 } 1690 if (mask & IFCAP_LRO) { 1691 #if defined(INET) || defined(INET6) 1692 int i; 1693 struct sge_rxq *rxq; 1694 1695 ifp->if_capenable ^= IFCAP_LRO; 1696 for_each_rxq(vi, i, rxq) { 1697 if (ifp->if_capenable & IFCAP_LRO) 1698 rxq->iq.flags |= IQ_LRO_ENABLED; 1699 else 1700 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1701 } 1702 #endif 1703 } 1704 #ifdef TCP_OFFLOAD 1705 if (mask & IFCAP_TOE) { 1706 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1707 1708 rc = toe_capability(vi, enable); 1709 if (rc != 0) 1710 goto fail; 1711 1712 ifp->if_capenable ^= mask; 1713 } 1714 #endif 1715 if (mask & IFCAP_VLAN_HWTAGGING) { 1716 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1717 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1718 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1719 } 1720 if (mask & IFCAP_VLAN_MTU) { 1721 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1722 1723 /* Need to find out how to disable auto-mtu-inflation */ 1724 } 1725 if (mask & IFCAP_VLAN_HWTSO) 1726 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1727 if (mask & IFCAP_VLAN_HWCSUM) 1728 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1729 1730 #ifdef VLAN_CAPABILITIES 1731 VLAN_CAPABILITIES(ifp); 1732 #endif 1733 fail: 1734 end_synchronized_op(sc, 0); 1735 break; 1736 1737 case SIOCSIFMEDIA: 1738 case SIOCGIFMEDIA: 1739 ifmedia_ioctl(ifp, ifr, &vi->media, cmd); 1740 break; 1741 1742 case SIOCGI2C: { 1743 struct ifi2creq i2c; 1744 1745 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 1746 if (rc != 0) 1747 break; 1748 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1749 rc = EPERM; 1750 break; 1751 } 1752 if (i2c.len > sizeof(i2c.data)) { 1753 rc = EINVAL; 1754 break; 1755 } 1756 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1757 if (rc) 1758 return (rc); 1759 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr, 1760 i2c.offset, i2c.len, &i2c.data[0]); 1761 end_synchronized_op(sc, 0); 1762 if (rc == 0) 1763 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 1764 break; 1765 } 1766 1767 default: 1768 rc = ether_ioctl(ifp, cmd, data); 1769 } 1770 1771 return (rc); 1772 } 1773 1774 static int 1775 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1776 { 1777 struct vi_info *vi = ifp->if_softc; 1778 struct port_info *pi = vi->pi; 1779 struct adapter *sc = pi->adapter; 1780 struct sge_txq *txq; 1781 void *items[1]; 1782 int rc; 1783 1784 M_ASSERTPKTHDR(m); 1785 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1786 1787 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1788 m_freem(m); 1789 return (ENETDOWN); 1790 } 1791 1792 rc = parse_pkt(sc, &m); 1793 if (__predict_false(rc != 0)) { 1794 MPASS(m == NULL); /* was freed already */ 1795 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1796 return (rc); 1797 } 1798 1799 /* Select a txq. */ 1800 txq = &sc->sge.txq[vi->first_txq]; 1801 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1802 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1803 vi->rsrv_noflowq); 1804 1805 items[0] = m; 1806 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 1807 if (__predict_false(rc != 0)) 1808 m_freem(m); 1809 1810 return (rc); 1811 } 1812 1813 static void 1814 cxgbe_qflush(struct ifnet *ifp) 1815 { 1816 struct vi_info *vi = ifp->if_softc; 1817 struct sge_txq *txq; 1818 int i; 1819 1820 /* queues do not exist if !VI_INIT_DONE. */ 1821 if (vi->flags & VI_INIT_DONE) { 1822 for_each_txq(vi, i, txq) { 1823 TXQ_LOCK(txq); 1824 txq->eq.flags &= ~EQ_ENABLED; 1825 TXQ_UNLOCK(txq); 1826 while (!mp_ring_is_idle(txq->r)) { 1827 mp_ring_check_drainage(txq->r, 0); 1828 pause("qflush", 1); 1829 } 1830 } 1831 } 1832 if_qflush(ifp); 1833 } 1834 1835 static uint64_t 1836 vi_get_counter(struct ifnet *ifp, ift_counter c) 1837 { 1838 struct vi_info *vi = ifp->if_softc; 1839 struct fw_vi_stats_vf *s = &vi->stats; 1840 1841 vi_refresh_stats(vi->pi->adapter, vi); 1842 1843 switch (c) { 1844 case IFCOUNTER_IPACKETS: 1845 return (s->rx_bcast_frames + s->rx_mcast_frames + 1846 s->rx_ucast_frames); 1847 case IFCOUNTER_IERRORS: 1848 return (s->rx_err_frames); 1849 case IFCOUNTER_OPACKETS: 1850 return (s->tx_bcast_frames + s->tx_mcast_frames + 1851 s->tx_ucast_frames + s->tx_offload_frames); 1852 case IFCOUNTER_OERRORS: 1853 return (s->tx_drop_frames); 1854 case IFCOUNTER_IBYTES: 1855 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 1856 s->rx_ucast_bytes); 1857 case IFCOUNTER_OBYTES: 1858 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 1859 s->tx_ucast_bytes + s->tx_offload_bytes); 1860 case IFCOUNTER_IMCASTS: 1861 return (s->rx_mcast_frames); 1862 case IFCOUNTER_OMCASTS: 1863 return (s->tx_mcast_frames); 1864 case IFCOUNTER_OQDROPS: { 1865 uint64_t drops; 1866 1867 drops = 0; 1868 if (vi->flags & VI_INIT_DONE) { 1869 int i; 1870 struct sge_txq *txq; 1871 1872 for_each_txq(vi, i, txq) 1873 drops += counter_u64_fetch(txq->r->drops); 1874 } 1875 1876 return (drops); 1877 1878 } 1879 1880 default: 1881 return (if_get_counter_default(ifp, c)); 1882 } 1883 } 1884 1885 uint64_t 1886 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 1887 { 1888 struct vi_info *vi = ifp->if_softc; 1889 struct port_info *pi = vi->pi; 1890 struct adapter *sc = pi->adapter; 1891 struct port_stats *s = &pi->stats; 1892 1893 if (pi->nvi > 1 || sc->flags & IS_VF) 1894 return (vi_get_counter(ifp, c)); 1895 1896 cxgbe_refresh_stats(sc, pi); 1897 1898 switch (c) { 1899 case IFCOUNTER_IPACKETS: 1900 return (s->rx_frames); 1901 1902 case IFCOUNTER_IERRORS: 1903 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 1904 s->rx_fcs_err + s->rx_len_err); 1905 1906 case IFCOUNTER_OPACKETS: 1907 return (s->tx_frames); 1908 1909 case IFCOUNTER_OERRORS: 1910 return (s->tx_error_frames); 1911 1912 case IFCOUNTER_IBYTES: 1913 return (s->rx_octets); 1914 1915 case IFCOUNTER_OBYTES: 1916 return (s->tx_octets); 1917 1918 case IFCOUNTER_IMCASTS: 1919 return (s->rx_mcast_frames); 1920 1921 case IFCOUNTER_OMCASTS: 1922 return (s->tx_mcast_frames); 1923 1924 case IFCOUNTER_IQDROPS: 1925 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 1926 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 1927 s->rx_trunc3 + pi->tnl_cong_drops); 1928 1929 case IFCOUNTER_OQDROPS: { 1930 uint64_t drops; 1931 1932 drops = s->tx_drop; 1933 if (vi->flags & VI_INIT_DONE) { 1934 int i; 1935 struct sge_txq *txq; 1936 1937 for_each_txq(vi, i, txq) 1938 drops += counter_u64_fetch(txq->r->drops); 1939 } 1940 1941 return (drops); 1942 1943 } 1944 1945 default: 1946 return (if_get_counter_default(ifp, c)); 1947 } 1948 } 1949 1950 static int 1951 cxgbe_media_change(struct ifnet *ifp) 1952 { 1953 struct vi_info *vi = ifp->if_softc; 1954 1955 device_printf(vi->dev, "%s unimplemented.\n", __func__); 1956 1957 return (EOPNOTSUPP); 1958 } 1959 1960 static void 1961 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1962 { 1963 struct vi_info *vi = ifp->if_softc; 1964 struct port_info *pi = vi->pi; 1965 struct ifmedia_entry *cur; 1966 int speed = pi->link_cfg.speed; 1967 1968 cur = vi->media.ifm_cur; 1969 1970 ifmr->ifm_status = IFM_AVALID; 1971 if (!pi->link_cfg.link_ok) 1972 return; 1973 1974 ifmr->ifm_status |= IFM_ACTIVE; 1975 1976 /* active and current will differ iff current media is autoselect. */ 1977 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 1978 return; 1979 1980 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 1981 if (speed == 10000) 1982 ifmr->ifm_active |= IFM_10G_T; 1983 else if (speed == 1000) 1984 ifmr->ifm_active |= IFM_1000_T; 1985 else if (speed == 100) 1986 ifmr->ifm_active |= IFM_100_TX; 1987 else if (speed == 10) 1988 ifmr->ifm_active |= IFM_10_T; 1989 else 1990 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 1991 speed)); 1992 } 1993 1994 static int 1995 vcxgbe_probe(device_t dev) 1996 { 1997 char buf[128]; 1998 struct vi_info *vi = device_get_softc(dev); 1999 2000 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2001 vi - vi->pi->vi); 2002 device_set_desc_copy(dev, buf); 2003 2004 return (BUS_PROBE_DEFAULT); 2005 } 2006 2007 static int 2008 vcxgbe_attach(device_t dev) 2009 { 2010 struct vi_info *vi; 2011 struct port_info *pi; 2012 struct adapter *sc; 2013 int func, index, rc; 2014 u32 param, val; 2015 2016 vi = device_get_softc(dev); 2017 pi = vi->pi; 2018 sc = pi->adapter; 2019 2020 index = vi - pi->vi; 2021 KASSERT(index < nitems(vi_mac_funcs), 2022 ("%s: VI %s doesn't have a MAC func", __func__, 2023 device_get_nameunit(dev))); 2024 func = vi_mac_funcs[index]; 2025 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2026 vi->hw_addr, &vi->rss_size, func, 0); 2027 if (rc < 0) { 2028 device_printf(dev, "Failed to allocate virtual interface " 2029 "for port %d: %d\n", pi->port_id, -rc); 2030 return (-rc); 2031 } 2032 vi->viid = rc; 2033 if (chip_id(sc) <= CHELSIO_T5) 2034 vi->smt_idx = (rc & 0x7f) << 1; 2035 else 2036 vi->smt_idx = (rc & 0x7f); 2037 2038 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2039 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2040 V_FW_PARAMS_PARAM_YZ(vi->viid); 2041 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2042 if (rc) 2043 vi->rss_base = 0xffff; 2044 else { 2045 /* MPASS((val >> 16) == rss_size); */ 2046 vi->rss_base = val & 0xffff; 2047 } 2048 2049 rc = cxgbe_vi_attach(dev, vi); 2050 if (rc) { 2051 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2052 return (rc); 2053 } 2054 return (0); 2055 } 2056 2057 static int 2058 vcxgbe_detach(device_t dev) 2059 { 2060 struct vi_info *vi; 2061 struct adapter *sc; 2062 2063 vi = device_get_softc(dev); 2064 sc = vi->pi->adapter; 2065 2066 doom_vi(sc, vi); 2067 2068 cxgbe_vi_detach(vi); 2069 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2070 2071 end_synchronized_op(sc, 0); 2072 2073 return (0); 2074 } 2075 2076 void 2077 t4_fatal_err(struct adapter *sc) 2078 { 2079 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2080 t4_intr_disable(sc); 2081 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2082 device_get_nameunit(sc->dev)); 2083 } 2084 2085 void 2086 t4_add_adapter(struct adapter *sc) 2087 { 2088 sx_xlock(&t4_list_lock); 2089 SLIST_INSERT_HEAD(&t4_list, sc, link); 2090 sx_xunlock(&t4_list_lock); 2091 } 2092 2093 int 2094 t4_map_bars_0_and_4(struct adapter *sc) 2095 { 2096 sc->regs_rid = PCIR_BAR(0); 2097 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2098 &sc->regs_rid, RF_ACTIVE); 2099 if (sc->regs_res == NULL) { 2100 device_printf(sc->dev, "cannot map registers.\n"); 2101 return (ENXIO); 2102 } 2103 sc->bt = rman_get_bustag(sc->regs_res); 2104 sc->bh = rman_get_bushandle(sc->regs_res); 2105 sc->mmio_len = rman_get_size(sc->regs_res); 2106 setbit(&sc->doorbells, DOORBELL_KDB); 2107 2108 sc->msix_rid = PCIR_BAR(4); 2109 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2110 &sc->msix_rid, RF_ACTIVE); 2111 if (sc->msix_res == NULL) { 2112 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2113 return (ENXIO); 2114 } 2115 2116 return (0); 2117 } 2118 2119 int 2120 t4_map_bar_2(struct adapter *sc) 2121 { 2122 2123 /* 2124 * T4: only iWARP driver uses the userspace doorbells. There is no need 2125 * to map it if RDMA is disabled. 2126 */ 2127 if (is_t4(sc) && sc->rdmacaps == 0) 2128 return (0); 2129 2130 sc->udbs_rid = PCIR_BAR(2); 2131 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2132 &sc->udbs_rid, RF_ACTIVE); 2133 if (sc->udbs_res == NULL) { 2134 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2135 return (ENXIO); 2136 } 2137 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2138 2139 if (chip_id(sc) >= CHELSIO_T5) { 2140 setbit(&sc->doorbells, DOORBELL_UDB); 2141 #if defined(__i386__) || defined(__amd64__) 2142 if (t5_write_combine) { 2143 int rc, mode; 2144 2145 /* 2146 * Enable write combining on BAR2. This is the 2147 * userspace doorbell BAR and is split into 128B 2148 * (UDBS_SEG_SIZE) doorbell regions, each associated 2149 * with an egress queue. The first 64B has the doorbell 2150 * and the second 64B can be used to submit a tx work 2151 * request with an implicit doorbell. 2152 */ 2153 2154 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2155 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2156 if (rc == 0) { 2157 clrbit(&sc->doorbells, DOORBELL_UDB); 2158 setbit(&sc->doorbells, DOORBELL_WCWR); 2159 setbit(&sc->doorbells, DOORBELL_UDBWC); 2160 } else { 2161 device_printf(sc->dev, 2162 "couldn't enable write combining: %d\n", 2163 rc); 2164 } 2165 2166 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2167 t4_write_reg(sc, A_SGE_STAT_CFG, 2168 V_STATSOURCE_T5(7) | mode); 2169 } 2170 #endif 2171 } 2172 2173 return (0); 2174 } 2175 2176 struct memwin_init { 2177 uint32_t base; 2178 uint32_t aperture; 2179 }; 2180 2181 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2182 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2183 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2184 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2185 }; 2186 2187 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2188 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2189 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2190 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2191 }; 2192 2193 static void 2194 setup_memwin(struct adapter *sc) 2195 { 2196 const struct memwin_init *mw_init; 2197 struct memwin *mw; 2198 int i; 2199 uint32_t bar0; 2200 2201 if (is_t4(sc)) { 2202 /* 2203 * Read low 32b of bar0 indirectly via the hardware backdoor 2204 * mechanism. Works from within PCI passthrough environments 2205 * too, where rman_get_start() can return a different value. We 2206 * need to program the T4 memory window decoders with the actual 2207 * addresses that will be coming across the PCIe link. 2208 */ 2209 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2210 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2211 2212 mw_init = &t4_memwin[0]; 2213 } else { 2214 /* T5+ use the relative offset inside the PCIe BAR */ 2215 bar0 = 0; 2216 2217 mw_init = &t5_memwin[0]; 2218 } 2219 2220 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2221 rw_init(&mw->mw_lock, "memory window access"); 2222 mw->mw_base = mw_init->base; 2223 mw->mw_aperture = mw_init->aperture; 2224 mw->mw_curpos = 0; 2225 t4_write_reg(sc, 2226 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2227 (mw->mw_base + bar0) | V_BIR(0) | 2228 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2229 rw_wlock(&mw->mw_lock); 2230 position_memwin(sc, i, 0); 2231 rw_wunlock(&mw->mw_lock); 2232 } 2233 2234 /* flush */ 2235 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2236 } 2237 2238 /* 2239 * Positions the memory window at the given address in the card's address space. 2240 * There are some alignment requirements and the actual position may be at an 2241 * address prior to the requested address. mw->mw_curpos always has the actual 2242 * position of the window. 2243 */ 2244 static void 2245 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2246 { 2247 struct memwin *mw; 2248 uint32_t pf; 2249 uint32_t reg; 2250 2251 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2252 mw = &sc->memwin[idx]; 2253 rw_assert(&mw->mw_lock, RA_WLOCKED); 2254 2255 if (is_t4(sc)) { 2256 pf = 0; 2257 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2258 } else { 2259 pf = V_PFNUM(sc->pf); 2260 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2261 } 2262 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2263 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2264 t4_read_reg(sc, reg); /* flush */ 2265 } 2266 2267 static int 2268 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2269 int len, int rw) 2270 { 2271 struct memwin *mw; 2272 uint32_t mw_end, v; 2273 2274 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2275 2276 /* Memory can only be accessed in naturally aligned 4 byte units */ 2277 if (addr & 3 || len & 3 || len <= 0) 2278 return (EINVAL); 2279 2280 mw = &sc->memwin[idx]; 2281 while (len > 0) { 2282 rw_rlock(&mw->mw_lock); 2283 mw_end = mw->mw_curpos + mw->mw_aperture; 2284 if (addr >= mw_end || addr < mw->mw_curpos) { 2285 /* Will need to reposition the window */ 2286 if (!rw_try_upgrade(&mw->mw_lock)) { 2287 rw_runlock(&mw->mw_lock); 2288 rw_wlock(&mw->mw_lock); 2289 } 2290 rw_assert(&mw->mw_lock, RA_WLOCKED); 2291 position_memwin(sc, idx, addr); 2292 rw_downgrade(&mw->mw_lock); 2293 mw_end = mw->mw_curpos + mw->mw_aperture; 2294 } 2295 rw_assert(&mw->mw_lock, RA_RLOCKED); 2296 while (addr < mw_end && len > 0) { 2297 if (rw == 0) { 2298 v = t4_read_reg(sc, mw->mw_base + addr - 2299 mw->mw_curpos); 2300 *val++ = le32toh(v); 2301 } else { 2302 v = *val++; 2303 t4_write_reg(sc, mw->mw_base + addr - 2304 mw->mw_curpos, htole32(v)); 2305 } 2306 addr += 4; 2307 len -= 4; 2308 } 2309 rw_runlock(&mw->mw_lock); 2310 } 2311 2312 return (0); 2313 } 2314 2315 static inline int 2316 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2317 int len) 2318 { 2319 2320 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 2321 } 2322 2323 static inline int 2324 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 2325 const uint32_t *val, int len) 2326 { 2327 2328 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 2329 } 2330 2331 static int 2332 t4_range_cmp(const void *a, const void *b) 2333 { 2334 return ((const struct t4_range *)a)->start - 2335 ((const struct t4_range *)b)->start; 2336 } 2337 2338 /* 2339 * Verify that the memory range specified by the addr/len pair is valid within 2340 * the card's address space. 2341 */ 2342 static int 2343 validate_mem_range(struct adapter *sc, uint32_t addr, int len) 2344 { 2345 struct t4_range mem_ranges[4], *r, *next; 2346 uint32_t em, addr_len; 2347 int i, n, remaining; 2348 2349 /* Memory can only be accessed in naturally aligned 4 byte units */ 2350 if (addr & 3 || len & 3 || len <= 0) 2351 return (EINVAL); 2352 2353 /* Enabled memories */ 2354 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2355 2356 r = &mem_ranges[0]; 2357 n = 0; 2358 bzero(r, sizeof(mem_ranges)); 2359 if (em & F_EDRAM0_ENABLE) { 2360 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2361 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2362 if (r->size > 0) { 2363 r->start = G_EDRAM0_BASE(addr_len) << 20; 2364 if (addr >= r->start && 2365 addr + len <= r->start + r->size) 2366 return (0); 2367 r++; 2368 n++; 2369 } 2370 } 2371 if (em & F_EDRAM1_ENABLE) { 2372 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2373 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2374 if (r->size > 0) { 2375 r->start = G_EDRAM1_BASE(addr_len) << 20; 2376 if (addr >= r->start && 2377 addr + len <= r->start + r->size) 2378 return (0); 2379 r++; 2380 n++; 2381 } 2382 } 2383 if (em & F_EXT_MEM_ENABLE) { 2384 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2385 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2386 if (r->size > 0) { 2387 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2388 if (addr >= r->start && 2389 addr + len <= r->start + r->size) 2390 return (0); 2391 r++; 2392 n++; 2393 } 2394 } 2395 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2396 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2397 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2398 if (r->size > 0) { 2399 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2400 if (addr >= r->start && 2401 addr + len <= r->start + r->size) 2402 return (0); 2403 r++; 2404 n++; 2405 } 2406 } 2407 MPASS(n <= nitems(mem_ranges)); 2408 2409 if (n > 1) { 2410 /* Sort and merge the ranges. */ 2411 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2412 2413 /* Start from index 0 and examine the next n - 1 entries. */ 2414 r = &mem_ranges[0]; 2415 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2416 2417 MPASS(r->size > 0); /* r is a valid entry. */ 2418 next = r + 1; 2419 MPASS(next->size > 0); /* and so is the next one. */ 2420 2421 while (r->start + r->size >= next->start) { 2422 /* Merge the next one into the current entry. */ 2423 r->size = max(r->start + r->size, 2424 next->start + next->size) - r->start; 2425 n--; /* One fewer entry in total. */ 2426 if (--remaining == 0) 2427 goto done; /* short circuit */ 2428 next++; 2429 } 2430 if (next != r + 1) { 2431 /* 2432 * Some entries were merged into r and next 2433 * points to the first valid entry that couldn't 2434 * be merged. 2435 */ 2436 MPASS(next->size > 0); /* must be valid */ 2437 memcpy(r + 1, next, remaining * sizeof(*r)); 2438 #ifdef INVARIANTS 2439 /* 2440 * This so that the foo->size assertion in the 2441 * next iteration of the loop do the right 2442 * thing for entries that were pulled up and are 2443 * no longer valid. 2444 */ 2445 MPASS(n < nitems(mem_ranges)); 2446 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2447 sizeof(struct t4_range)); 2448 #endif 2449 } 2450 } 2451 done: 2452 /* Done merging the ranges. */ 2453 MPASS(n > 0); 2454 r = &mem_ranges[0]; 2455 for (i = 0; i < n; i++, r++) { 2456 if (addr >= r->start && 2457 addr + len <= r->start + r->size) 2458 return (0); 2459 } 2460 } 2461 2462 return (EFAULT); 2463 } 2464 2465 static int 2466 fwmtype_to_hwmtype(int mtype) 2467 { 2468 2469 switch (mtype) { 2470 case FW_MEMTYPE_EDC0: 2471 return (MEM_EDC0); 2472 case FW_MEMTYPE_EDC1: 2473 return (MEM_EDC1); 2474 case FW_MEMTYPE_EXTMEM: 2475 return (MEM_MC0); 2476 case FW_MEMTYPE_EXTMEM1: 2477 return (MEM_MC1); 2478 default: 2479 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2480 } 2481 } 2482 2483 /* 2484 * Verify that the memory range specified by the memtype/offset/len pair is 2485 * valid and lies entirely within the memtype specified. The global address of 2486 * the start of the range is returned in addr. 2487 */ 2488 static int 2489 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 2490 uint32_t *addr) 2491 { 2492 uint32_t em, addr_len, maddr; 2493 2494 /* Memory can only be accessed in naturally aligned 4 byte units */ 2495 if (off & 3 || len & 3 || len == 0) 2496 return (EINVAL); 2497 2498 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2499 switch (fwmtype_to_hwmtype(mtype)) { 2500 case MEM_EDC0: 2501 if (!(em & F_EDRAM0_ENABLE)) 2502 return (EINVAL); 2503 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2504 maddr = G_EDRAM0_BASE(addr_len) << 20; 2505 break; 2506 case MEM_EDC1: 2507 if (!(em & F_EDRAM1_ENABLE)) 2508 return (EINVAL); 2509 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2510 maddr = G_EDRAM1_BASE(addr_len) << 20; 2511 break; 2512 case MEM_MC: 2513 if (!(em & F_EXT_MEM_ENABLE)) 2514 return (EINVAL); 2515 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2516 maddr = G_EXT_MEM_BASE(addr_len) << 20; 2517 break; 2518 case MEM_MC1: 2519 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 2520 return (EINVAL); 2521 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2522 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 2523 break; 2524 default: 2525 return (EINVAL); 2526 } 2527 2528 *addr = maddr + off; /* global address */ 2529 return (validate_mem_range(sc, *addr, len)); 2530 } 2531 2532 static int 2533 fixup_devlog_params(struct adapter *sc) 2534 { 2535 struct devlog_params *dparams = &sc->params.devlog; 2536 int rc; 2537 2538 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 2539 dparams->size, &dparams->addr); 2540 2541 return (rc); 2542 } 2543 2544 static int 2545 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis, 2546 struct intrs_and_queues *iaq) 2547 { 2548 int rc, itype, navail, nrxq10g, nrxq1g, n; 2549 int nofldrxq10g = 0, nofldrxq1g = 0; 2550 2551 bzero(iaq, sizeof(*iaq)); 2552 2553 iaq->ntxq10g = t4_ntxq10g; 2554 iaq->ntxq1g = t4_ntxq1g; 2555 iaq->ntxq_vi = t4_ntxq_vi; 2556 iaq->nrxq10g = nrxq10g = t4_nrxq10g; 2557 iaq->nrxq1g = nrxq1g = t4_nrxq1g; 2558 iaq->nrxq_vi = t4_nrxq_vi; 2559 iaq->rsrv_noflowq = t4_rsrv_noflowq; 2560 #ifdef TCP_OFFLOAD 2561 if (is_offload(sc)) { 2562 iaq->nofldtxq10g = t4_nofldtxq10g; 2563 iaq->nofldtxq1g = t4_nofldtxq1g; 2564 iaq->nofldtxq_vi = t4_nofldtxq_vi; 2565 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g; 2566 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g; 2567 iaq->nofldrxq_vi = t4_nofldrxq_vi; 2568 } 2569 #endif 2570 #ifdef DEV_NETMAP 2571 iaq->nnmtxq_vi = t4_nnmtxq_vi; 2572 iaq->nnmrxq_vi = t4_nnmrxq_vi; 2573 #endif 2574 2575 for (itype = INTR_MSIX; itype; itype >>= 1) { 2576 2577 if ((itype & t4_intr_types) == 0) 2578 continue; /* not allowed */ 2579 2580 if (itype == INTR_MSIX) 2581 navail = pci_msix_count(sc->dev); 2582 else if (itype == INTR_MSI) 2583 navail = pci_msi_count(sc->dev); 2584 else 2585 navail = 1; 2586 restart: 2587 if (navail == 0) 2588 continue; 2589 2590 iaq->intr_type = itype; 2591 iaq->intr_flags_10g = 0; 2592 iaq->intr_flags_1g = 0; 2593 2594 /* 2595 * Best option: an interrupt vector for errors, one for the 2596 * firmware event queue, and one for every rxq (NIC and TOE) of 2597 * every VI. The VIs that support netmap use the same 2598 * interrupts for the NIC rx queues and the netmap rx queues 2599 * because only one set of queues is active at a time. 2600 */ 2601 iaq->nirq = T4_EXTRA_INTR; 2602 iaq->nirq += n10g * (nrxq10g + nofldrxq10g); 2603 iaq->nirq += n1g * (nrxq1g + nofldrxq1g); 2604 iaq->nirq += (n10g + n1g) * (num_vis - 1) * 2605 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */ 2606 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi; 2607 if (iaq->nirq <= navail && 2608 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2609 iaq->intr_flags_10g = INTR_ALL; 2610 iaq->intr_flags_1g = INTR_ALL; 2611 goto allocate; 2612 } 2613 2614 /* Disable the VIs (and netmap) if there aren't enough intrs */ 2615 if (num_vis > 1) { 2616 device_printf(sc->dev, "virtual interfaces disabled " 2617 "because num_vis=%u with current settings " 2618 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, " 2619 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, " 2620 "nnmrxq_vi=%u) would need %u interrupts but " 2621 "only %u are available.\n", num_vis, nrxq10g, 2622 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi, 2623 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq, 2624 navail); 2625 num_vis = 1; 2626 iaq->ntxq_vi = iaq->nrxq_vi = 0; 2627 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 2628 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 2629 goto restart; 2630 } 2631 2632 /* 2633 * Second best option: a vector for errors, one for the firmware 2634 * event queue, and vectors for either all the NIC rx queues or 2635 * all the TOE rx queues. The queues that don't get vectors 2636 * will forward their interrupts to those that do. 2637 */ 2638 iaq->nirq = T4_EXTRA_INTR; 2639 if (nrxq10g >= nofldrxq10g) { 2640 iaq->intr_flags_10g = INTR_RXQ; 2641 iaq->nirq += n10g * nrxq10g; 2642 } else { 2643 iaq->intr_flags_10g = INTR_OFLD_RXQ; 2644 iaq->nirq += n10g * nofldrxq10g; 2645 } 2646 if (nrxq1g >= nofldrxq1g) { 2647 iaq->intr_flags_1g = INTR_RXQ; 2648 iaq->nirq += n1g * nrxq1g; 2649 } else { 2650 iaq->intr_flags_1g = INTR_OFLD_RXQ; 2651 iaq->nirq += n1g * nofldrxq1g; 2652 } 2653 if (iaq->nirq <= navail && 2654 (itype != INTR_MSI || powerof2(iaq->nirq))) 2655 goto allocate; 2656 2657 /* 2658 * Next best option: an interrupt vector for errors, one for the 2659 * firmware event queue, and at least one per main-VI. At this 2660 * point we know we'll have to downsize nrxq and/or nofldrxq to 2661 * fit what's available to us. 2662 */ 2663 iaq->nirq = T4_EXTRA_INTR; 2664 iaq->nirq += n10g + n1g; 2665 if (iaq->nirq <= navail) { 2666 int leftover = navail - iaq->nirq; 2667 2668 if (n10g > 0) { 2669 int target = max(nrxq10g, nofldrxq10g); 2670 2671 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ? 2672 INTR_RXQ : INTR_OFLD_RXQ; 2673 2674 n = 1; 2675 while (n < target && leftover >= n10g) { 2676 leftover -= n10g; 2677 iaq->nirq += n10g; 2678 n++; 2679 } 2680 iaq->nrxq10g = min(n, nrxq10g); 2681 #ifdef TCP_OFFLOAD 2682 iaq->nofldrxq10g = min(n, nofldrxq10g); 2683 #endif 2684 } 2685 2686 if (n1g > 0) { 2687 int target = max(nrxq1g, nofldrxq1g); 2688 2689 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ? 2690 INTR_RXQ : INTR_OFLD_RXQ; 2691 2692 n = 1; 2693 while (n < target && leftover >= n1g) { 2694 leftover -= n1g; 2695 iaq->nirq += n1g; 2696 n++; 2697 } 2698 iaq->nrxq1g = min(n, nrxq1g); 2699 #ifdef TCP_OFFLOAD 2700 iaq->nofldrxq1g = min(n, nofldrxq1g); 2701 #endif 2702 } 2703 2704 if (itype != INTR_MSI || powerof2(iaq->nirq)) 2705 goto allocate; 2706 } 2707 2708 /* 2709 * Least desirable option: one interrupt vector for everything. 2710 */ 2711 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1; 2712 iaq->intr_flags_10g = iaq->intr_flags_1g = 0; 2713 #ifdef TCP_OFFLOAD 2714 if (is_offload(sc)) 2715 iaq->nofldrxq10g = iaq->nofldrxq1g = 1; 2716 #endif 2717 allocate: 2718 navail = iaq->nirq; 2719 rc = 0; 2720 if (itype == INTR_MSIX) 2721 rc = pci_alloc_msix(sc->dev, &navail); 2722 else if (itype == INTR_MSI) 2723 rc = pci_alloc_msi(sc->dev, &navail); 2724 2725 if (rc == 0) { 2726 if (navail == iaq->nirq) 2727 return (0); 2728 2729 /* 2730 * Didn't get the number requested. Use whatever number 2731 * the kernel is willing to allocate (it's in navail). 2732 */ 2733 device_printf(sc->dev, "fewer vectors than requested, " 2734 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 2735 itype, iaq->nirq, navail); 2736 pci_release_msi(sc->dev); 2737 goto restart; 2738 } 2739 2740 device_printf(sc->dev, 2741 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 2742 itype, rc, iaq->nirq, navail); 2743 } 2744 2745 device_printf(sc->dev, 2746 "failed to find a usable interrupt type. " 2747 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 2748 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 2749 2750 return (ENXIO); 2751 } 2752 2753 #define FW_VERSION(chip) ( \ 2754 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 2755 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 2756 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 2757 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 2758 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 2759 2760 struct fw_info { 2761 uint8_t chip; 2762 char *kld_name; 2763 char *fw_mod_name; 2764 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 2765 } fw_info[] = { 2766 { 2767 .chip = CHELSIO_T4, 2768 .kld_name = "t4fw_cfg", 2769 .fw_mod_name = "t4fw", 2770 .fw_hdr = { 2771 .chip = FW_HDR_CHIP_T4, 2772 .fw_ver = htobe32_const(FW_VERSION(T4)), 2773 .intfver_nic = FW_INTFVER(T4, NIC), 2774 .intfver_vnic = FW_INTFVER(T4, VNIC), 2775 .intfver_ofld = FW_INTFVER(T4, OFLD), 2776 .intfver_ri = FW_INTFVER(T4, RI), 2777 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 2778 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 2779 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 2780 .intfver_fcoe = FW_INTFVER(T4, FCOE), 2781 }, 2782 }, { 2783 .chip = CHELSIO_T5, 2784 .kld_name = "t5fw_cfg", 2785 .fw_mod_name = "t5fw", 2786 .fw_hdr = { 2787 .chip = FW_HDR_CHIP_T5, 2788 .fw_ver = htobe32_const(FW_VERSION(T5)), 2789 .intfver_nic = FW_INTFVER(T5, NIC), 2790 .intfver_vnic = FW_INTFVER(T5, VNIC), 2791 .intfver_ofld = FW_INTFVER(T5, OFLD), 2792 .intfver_ri = FW_INTFVER(T5, RI), 2793 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 2794 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 2795 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 2796 .intfver_fcoe = FW_INTFVER(T5, FCOE), 2797 }, 2798 }, { 2799 .chip = CHELSIO_T6, 2800 .kld_name = "t6fw_cfg", 2801 .fw_mod_name = "t6fw", 2802 .fw_hdr = { 2803 .chip = FW_HDR_CHIP_T6, 2804 .fw_ver = htobe32_const(FW_VERSION(T6)), 2805 .intfver_nic = FW_INTFVER(T6, NIC), 2806 .intfver_vnic = FW_INTFVER(T6, VNIC), 2807 .intfver_ofld = FW_INTFVER(T6, OFLD), 2808 .intfver_ri = FW_INTFVER(T6, RI), 2809 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 2810 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 2811 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 2812 .intfver_fcoe = FW_INTFVER(T6, FCOE), 2813 }, 2814 } 2815 }; 2816 2817 static struct fw_info * 2818 find_fw_info(int chip) 2819 { 2820 int i; 2821 2822 for (i = 0; i < nitems(fw_info); i++) { 2823 if (fw_info[i].chip == chip) 2824 return (&fw_info[i]); 2825 } 2826 return (NULL); 2827 } 2828 2829 /* 2830 * Is the given firmware API compatible with the one the driver was compiled 2831 * with? 2832 */ 2833 static int 2834 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 2835 { 2836 2837 /* short circuit if it's the exact same firmware version */ 2838 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 2839 return (1); 2840 2841 /* 2842 * XXX: Is this too conservative? Perhaps I should limit this to the 2843 * features that are supported in the driver. 2844 */ 2845 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 2846 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 2847 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 2848 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 2849 return (1); 2850 #undef SAME_INTF 2851 2852 return (0); 2853 } 2854 2855 /* 2856 * The firmware in the KLD is usable, but should it be installed? This routine 2857 * explains itself in detail if it indicates the KLD firmware should be 2858 * installed. 2859 */ 2860 static int 2861 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 2862 { 2863 const char *reason; 2864 2865 if (!card_fw_usable) { 2866 reason = "incompatible or unusable"; 2867 goto install; 2868 } 2869 2870 if (k > c) { 2871 reason = "older than the version bundled with this driver"; 2872 goto install; 2873 } 2874 2875 if (t4_fw_install == 2 && k != c) { 2876 reason = "different than the version bundled with this driver"; 2877 goto install; 2878 } 2879 2880 return (0); 2881 2882 install: 2883 if (t4_fw_install == 0) { 2884 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2885 "but the driver is prohibited from installing a different " 2886 "firmware on the card.\n", 2887 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2888 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 2889 2890 return (0); 2891 } 2892 2893 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2894 "installing firmware %u.%u.%u.%u on card.\n", 2895 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2896 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 2897 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 2898 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 2899 2900 return (1); 2901 } 2902 /* 2903 * Establish contact with the firmware and determine if we are the master driver 2904 * or not, and whether we are responsible for chip initialization. 2905 */ 2906 static int 2907 prep_firmware(struct adapter *sc) 2908 { 2909 const struct firmware *fw = NULL, *default_cfg; 2910 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 2911 enum dev_state state; 2912 struct fw_info *fw_info; 2913 struct fw_hdr *card_fw; /* fw on the card */ 2914 const struct fw_hdr *kld_fw; /* fw in the KLD */ 2915 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 2916 against */ 2917 2918 /* Contact firmware. */ 2919 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 2920 if (rc < 0 || state == DEV_STATE_ERR) { 2921 rc = -rc; 2922 device_printf(sc->dev, 2923 "failed to connect to the firmware: %d, %d.\n", rc, state); 2924 return (rc); 2925 } 2926 pf = rc; 2927 if (pf == sc->mbox) 2928 sc->flags |= MASTER_PF; 2929 else if (state == DEV_STATE_UNINIT) { 2930 /* 2931 * We didn't get to be the master so we definitely won't be 2932 * configuring the chip. It's a bug if someone else hasn't 2933 * configured it already. 2934 */ 2935 device_printf(sc->dev, "couldn't be master(%d), " 2936 "device not already initialized either(%d).\n", rc, state); 2937 return (EDOOFUS); 2938 } 2939 2940 /* This is the firmware whose headers the driver was compiled against */ 2941 fw_info = find_fw_info(chip_id(sc)); 2942 if (fw_info == NULL) { 2943 device_printf(sc->dev, 2944 "unable to look up firmware information for chip %d.\n", 2945 chip_id(sc)); 2946 return (EINVAL); 2947 } 2948 drv_fw = &fw_info->fw_hdr; 2949 2950 /* 2951 * The firmware KLD contains many modules. The KLD name is also the 2952 * name of the module that contains the default config file. 2953 */ 2954 default_cfg = firmware_get(fw_info->kld_name); 2955 2956 /* Read the header of the firmware on the card */ 2957 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 2958 rc = -t4_read_flash(sc, FLASH_FW_START, 2959 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 2960 if (rc == 0) 2961 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 2962 else { 2963 device_printf(sc->dev, 2964 "Unable to read card's firmware header: %d\n", rc); 2965 card_fw_usable = 0; 2966 } 2967 2968 /* This is the firmware in the KLD */ 2969 fw = firmware_get(fw_info->fw_mod_name); 2970 if (fw != NULL) { 2971 kld_fw = (const void *)fw->data; 2972 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 2973 } else { 2974 kld_fw = NULL; 2975 kld_fw_usable = 0; 2976 } 2977 2978 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 2979 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 2980 /* 2981 * Common case: the firmware on the card is an exact match and 2982 * the KLD is an exact match too, or the KLD is 2983 * absent/incompatible. Note that t4_fw_install = 2 is ignored 2984 * here -- use cxgbetool loadfw if you want to reinstall the 2985 * same firmware as the one on the card. 2986 */ 2987 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 2988 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 2989 be32toh(card_fw->fw_ver))) { 2990 2991 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 2992 if (rc != 0) { 2993 device_printf(sc->dev, 2994 "failed to install firmware: %d\n", rc); 2995 goto done; 2996 } 2997 2998 /* Installed successfully, update the cached header too. */ 2999 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3000 card_fw_usable = 1; 3001 need_fw_reset = 0; /* already reset as part of load_fw */ 3002 } 3003 3004 if (!card_fw_usable) { 3005 uint32_t d, c, k; 3006 3007 d = ntohl(drv_fw->fw_ver); 3008 c = ntohl(card_fw->fw_ver); 3009 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3010 3011 device_printf(sc->dev, "Cannot find a usable firmware: " 3012 "fw_install %d, chip state %d, " 3013 "driver compiled with %d.%d.%d.%d, " 3014 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3015 t4_fw_install, state, 3016 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3017 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3018 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3019 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3020 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3021 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3022 rc = EINVAL; 3023 goto done; 3024 } 3025 3026 /* Reset device */ 3027 if (need_fw_reset && 3028 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3029 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3030 if (rc != ETIMEDOUT && rc != EIO) 3031 t4_fw_bye(sc, sc->mbox); 3032 goto done; 3033 } 3034 sc->flags |= FW_OK; 3035 3036 rc = get_params__pre_init(sc); 3037 if (rc != 0) 3038 goto done; /* error message displayed already */ 3039 3040 /* Partition adapter resources as specified in the config file. */ 3041 if (state == DEV_STATE_UNINIT) { 3042 3043 KASSERT(sc->flags & MASTER_PF, 3044 ("%s: trying to change chip settings when not master.", 3045 __func__)); 3046 3047 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3048 if (rc != 0) 3049 goto done; /* error message displayed already */ 3050 3051 t4_tweak_chip_settings(sc); 3052 3053 /* get basic stuff going */ 3054 rc = -t4_fw_initialize(sc, sc->mbox); 3055 if (rc != 0) { 3056 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3057 goto done; 3058 } 3059 } else { 3060 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3061 sc->cfcsum = 0; 3062 } 3063 3064 done: 3065 free(card_fw, M_CXGBE); 3066 if (fw != NULL) 3067 firmware_put(fw, FIRMWARE_UNLOAD); 3068 if (default_cfg != NULL) 3069 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3070 3071 return (rc); 3072 } 3073 3074 #define FW_PARAM_DEV(param) \ 3075 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3076 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3077 #define FW_PARAM_PFVF(param) \ 3078 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3079 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3080 3081 /* 3082 * Partition chip resources for use between various PFs, VFs, etc. 3083 */ 3084 static int 3085 partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3086 const char *name_prefix) 3087 { 3088 const struct firmware *cfg = NULL; 3089 int rc = 0; 3090 struct fw_caps_config_cmd caps; 3091 uint32_t mtype, moff, finicsum, cfcsum; 3092 3093 /* 3094 * Figure out what configuration file to use. Pick the default config 3095 * file for the card if the user hasn't specified one explicitly. 3096 */ 3097 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3098 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3099 /* Card specific overrides go here. */ 3100 if (pci_get_device(sc->dev) == 0x440a) 3101 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3102 if (is_fpga(sc)) 3103 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3104 } 3105 3106 /* 3107 * We need to load another module if the profile is anything except 3108 * "default" or "flash". 3109 */ 3110 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3111 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3112 char s[32]; 3113 3114 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3115 cfg = firmware_get(s); 3116 if (cfg == NULL) { 3117 if (default_cfg != NULL) { 3118 device_printf(sc->dev, 3119 "unable to load module \"%s\" for " 3120 "configuration profile \"%s\", will use " 3121 "the default config file instead.\n", 3122 s, sc->cfg_file); 3123 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3124 "%s", DEFAULT_CF); 3125 } else { 3126 device_printf(sc->dev, 3127 "unable to load module \"%s\" for " 3128 "configuration profile \"%s\", will use " 3129 "the config file on the card's flash " 3130 "instead.\n", s, sc->cfg_file); 3131 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3132 "%s", FLASH_CF); 3133 } 3134 } 3135 } 3136 3137 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3138 default_cfg == NULL) { 3139 device_printf(sc->dev, 3140 "default config file not available, will use the config " 3141 "file on the card's flash instead.\n"); 3142 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3143 } 3144 3145 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3146 u_int cflen; 3147 const uint32_t *cfdata; 3148 uint32_t param, val, addr; 3149 3150 KASSERT(cfg != NULL || default_cfg != NULL, 3151 ("%s: no config to upload", __func__)); 3152 3153 /* 3154 * Ask the firmware where it wants us to upload the config file. 3155 */ 3156 param = FW_PARAM_DEV(CF); 3157 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3158 if (rc != 0) { 3159 /* No support for config file? Shouldn't happen. */ 3160 device_printf(sc->dev, 3161 "failed to query config file location: %d.\n", rc); 3162 goto done; 3163 } 3164 mtype = G_FW_PARAMS_PARAM_Y(val); 3165 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3166 3167 /* 3168 * XXX: sheer laziness. We deliberately added 4 bytes of 3169 * useless stuffing/comments at the end of the config file so 3170 * it's ok to simply throw away the last remaining bytes when 3171 * the config file is not an exact multiple of 4. This also 3172 * helps with the validate_mt_off_len check. 3173 */ 3174 if (cfg != NULL) { 3175 cflen = cfg->datasize & ~3; 3176 cfdata = cfg->data; 3177 } else { 3178 cflen = default_cfg->datasize & ~3; 3179 cfdata = default_cfg->data; 3180 } 3181 3182 if (cflen > FLASH_CFG_MAX_SIZE) { 3183 device_printf(sc->dev, 3184 "config file too long (%d, max allowed is %d). " 3185 "Will try to use the config on the card, if any.\n", 3186 cflen, FLASH_CFG_MAX_SIZE); 3187 goto use_config_on_flash; 3188 } 3189 3190 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3191 if (rc != 0) { 3192 device_printf(sc->dev, 3193 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3194 "Will try to use the config on the card, if any.\n", 3195 __func__, mtype, moff, cflen, rc); 3196 goto use_config_on_flash; 3197 } 3198 write_via_memwin(sc, 2, addr, cfdata, cflen); 3199 } else { 3200 use_config_on_flash: 3201 mtype = FW_MEMTYPE_FLASH; 3202 moff = t4_flash_cfg_addr(sc); 3203 } 3204 3205 bzero(&caps, sizeof(caps)); 3206 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3207 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3208 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3209 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3210 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3211 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3212 if (rc != 0) { 3213 device_printf(sc->dev, 3214 "failed to pre-process config file: %d " 3215 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3216 goto done; 3217 } 3218 3219 finicsum = be32toh(caps.finicsum); 3220 cfcsum = be32toh(caps.cfcsum); 3221 if (finicsum != cfcsum) { 3222 device_printf(sc->dev, 3223 "WARNING: config file checksum mismatch: %08x %08x\n", 3224 finicsum, cfcsum); 3225 } 3226 sc->cfcsum = cfcsum; 3227 3228 #define LIMIT_CAPS(x) do { \ 3229 caps.x &= htobe16(t4_##x##_allowed); \ 3230 } while (0) 3231 3232 /* 3233 * Let the firmware know what features will (not) be used so it can tune 3234 * things accordingly. 3235 */ 3236 LIMIT_CAPS(nbmcaps); 3237 LIMIT_CAPS(linkcaps); 3238 LIMIT_CAPS(switchcaps); 3239 LIMIT_CAPS(niccaps); 3240 LIMIT_CAPS(toecaps); 3241 LIMIT_CAPS(rdmacaps); 3242 LIMIT_CAPS(cryptocaps); 3243 LIMIT_CAPS(iscsicaps); 3244 LIMIT_CAPS(fcoecaps); 3245 #undef LIMIT_CAPS 3246 3247 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3248 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3249 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3250 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3251 if (rc != 0) { 3252 device_printf(sc->dev, 3253 "failed to process config file: %d.\n", rc); 3254 } 3255 done: 3256 if (cfg != NULL) 3257 firmware_put(cfg, FIRMWARE_UNLOAD); 3258 return (rc); 3259 } 3260 3261 /* 3262 * Retrieve parameters that are needed (or nice to have) very early. 3263 */ 3264 static int 3265 get_params__pre_init(struct adapter *sc) 3266 { 3267 int rc; 3268 uint32_t param[2], val[2]; 3269 3270 t4_get_version_info(sc); 3271 3272 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3273 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3274 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3275 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3276 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3277 3278 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3279 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3280 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3281 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3282 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3283 3284 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3285 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3286 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3287 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3288 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3289 3290 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3291 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3292 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3293 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3294 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3295 3296 param[0] = FW_PARAM_DEV(PORTVEC); 3297 param[1] = FW_PARAM_DEV(CCLK); 3298 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3299 if (rc != 0) { 3300 device_printf(sc->dev, 3301 "failed to query parameters (pre_init): %d.\n", rc); 3302 return (rc); 3303 } 3304 3305 sc->params.portvec = val[0]; 3306 sc->params.nports = bitcount32(val[0]); 3307 sc->params.vpd.cclk = val[1]; 3308 3309 /* Read device log parameters. */ 3310 rc = -t4_init_devlog_params(sc, 1); 3311 if (rc == 0) 3312 fixup_devlog_params(sc); 3313 else { 3314 device_printf(sc->dev, 3315 "failed to get devlog parameters: %d.\n", rc); 3316 rc = 0; /* devlog isn't critical for device operation */ 3317 } 3318 3319 return (rc); 3320 } 3321 3322 /* 3323 * Retrieve various parameters that are of interest to the driver. The device 3324 * has been initialized by the firmware at this point. 3325 */ 3326 static int 3327 get_params__post_init(struct adapter *sc) 3328 { 3329 int rc; 3330 uint32_t param[7], val[7]; 3331 struct fw_caps_config_cmd caps; 3332 3333 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3334 param[1] = FW_PARAM_PFVF(EQ_START); 3335 param[2] = FW_PARAM_PFVF(FILTER_START); 3336 param[3] = FW_PARAM_PFVF(FILTER_END); 3337 param[4] = FW_PARAM_PFVF(L2T_START); 3338 param[5] = FW_PARAM_PFVF(L2T_END); 3339 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3340 if (rc != 0) { 3341 device_printf(sc->dev, 3342 "failed to query parameters (post_init): %d.\n", rc); 3343 return (rc); 3344 } 3345 3346 sc->sge.iq_start = val[0]; 3347 sc->sge.eq_start = val[1]; 3348 sc->tids.ftid_base = val[2]; 3349 sc->tids.nftids = val[3] - val[2] + 1; 3350 sc->params.ftid_min = val[2]; 3351 sc->params.ftid_max = val[3]; 3352 sc->vres.l2t.start = val[4]; 3353 sc->vres.l2t.size = val[5] - val[4] + 1; 3354 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3355 ("%s: L2 table size (%u) larger than expected (%u)", 3356 __func__, sc->vres.l2t.size, L2T_SIZE)); 3357 3358 /* get capabilites */ 3359 bzero(&caps, sizeof(caps)); 3360 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3361 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3362 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3363 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3364 if (rc != 0) { 3365 device_printf(sc->dev, 3366 "failed to get card capabilities: %d.\n", rc); 3367 return (rc); 3368 } 3369 3370 #define READ_CAPS(x) do { \ 3371 sc->x = htobe16(caps.x); \ 3372 } while (0) 3373 READ_CAPS(nbmcaps); 3374 READ_CAPS(linkcaps); 3375 READ_CAPS(switchcaps); 3376 READ_CAPS(niccaps); 3377 READ_CAPS(toecaps); 3378 READ_CAPS(rdmacaps); 3379 READ_CAPS(cryptocaps); 3380 READ_CAPS(iscsicaps); 3381 READ_CAPS(fcoecaps); 3382 3383 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 3384 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 3385 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 3386 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3387 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 3388 if (rc != 0) { 3389 device_printf(sc->dev, 3390 "failed to query NIC parameters: %d.\n", rc); 3391 return (rc); 3392 } 3393 sc->tids.etid_base = val[0]; 3394 sc->params.etid_min = val[0]; 3395 sc->tids.netids = val[1] - val[0] + 1; 3396 sc->params.netids = sc->tids.netids; 3397 sc->params.eo_wr_cred = val[2]; 3398 sc->params.ethoffload = 1; 3399 } 3400 3401 if (sc->toecaps) { 3402 /* query offload-related parameters */ 3403 param[0] = FW_PARAM_DEV(NTID); 3404 param[1] = FW_PARAM_PFVF(SERVER_START); 3405 param[2] = FW_PARAM_PFVF(SERVER_END); 3406 param[3] = FW_PARAM_PFVF(TDDP_START); 3407 param[4] = FW_PARAM_PFVF(TDDP_END); 3408 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3409 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3410 if (rc != 0) { 3411 device_printf(sc->dev, 3412 "failed to query TOE parameters: %d.\n", rc); 3413 return (rc); 3414 } 3415 sc->tids.ntids = val[0]; 3416 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3417 sc->tids.stid_base = val[1]; 3418 sc->tids.nstids = val[2] - val[1] + 1; 3419 sc->vres.ddp.start = val[3]; 3420 sc->vres.ddp.size = val[4] - val[3] + 1; 3421 sc->params.ofldq_wr_cred = val[5]; 3422 sc->params.offload = 1; 3423 } 3424 if (sc->rdmacaps) { 3425 param[0] = FW_PARAM_PFVF(STAG_START); 3426 param[1] = FW_PARAM_PFVF(STAG_END); 3427 param[2] = FW_PARAM_PFVF(RQ_START); 3428 param[3] = FW_PARAM_PFVF(RQ_END); 3429 param[4] = FW_PARAM_PFVF(PBL_START); 3430 param[5] = FW_PARAM_PFVF(PBL_END); 3431 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3432 if (rc != 0) { 3433 device_printf(sc->dev, 3434 "failed to query RDMA parameters(1): %d.\n", rc); 3435 return (rc); 3436 } 3437 sc->vres.stag.start = val[0]; 3438 sc->vres.stag.size = val[1] - val[0] + 1; 3439 sc->vres.rq.start = val[2]; 3440 sc->vres.rq.size = val[3] - val[2] + 1; 3441 sc->vres.pbl.start = val[4]; 3442 sc->vres.pbl.size = val[5] - val[4] + 1; 3443 3444 param[0] = FW_PARAM_PFVF(SQRQ_START); 3445 param[1] = FW_PARAM_PFVF(SQRQ_END); 3446 param[2] = FW_PARAM_PFVF(CQ_START); 3447 param[3] = FW_PARAM_PFVF(CQ_END); 3448 param[4] = FW_PARAM_PFVF(OCQ_START); 3449 param[5] = FW_PARAM_PFVF(OCQ_END); 3450 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3451 if (rc != 0) { 3452 device_printf(sc->dev, 3453 "failed to query RDMA parameters(2): %d.\n", rc); 3454 return (rc); 3455 } 3456 sc->vres.qp.start = val[0]; 3457 sc->vres.qp.size = val[1] - val[0] + 1; 3458 sc->vres.cq.start = val[2]; 3459 sc->vres.cq.size = val[3] - val[2] + 1; 3460 sc->vres.ocq.start = val[4]; 3461 sc->vres.ocq.size = val[5] - val[4] + 1; 3462 } 3463 if (sc->iscsicaps) { 3464 param[0] = FW_PARAM_PFVF(ISCSI_START); 3465 param[1] = FW_PARAM_PFVF(ISCSI_END); 3466 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3467 if (rc != 0) { 3468 device_printf(sc->dev, 3469 "failed to query iSCSI parameters: %d.\n", rc); 3470 return (rc); 3471 } 3472 sc->vres.iscsi.start = val[0]; 3473 sc->vres.iscsi.size = val[1] - val[0] + 1; 3474 } 3475 3476 t4_init_sge_params(sc); 3477 3478 /* 3479 * We've got the params we wanted to query via the firmware. Now grab 3480 * some others directly from the chip. 3481 */ 3482 rc = t4_read_chip_settings(sc); 3483 3484 return (rc); 3485 } 3486 3487 static int 3488 set_params__post_init(struct adapter *sc) 3489 { 3490 uint32_t param, val; 3491 3492 /* ask for encapsulated CPLs */ 3493 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3494 val = 1; 3495 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3496 3497 return (0); 3498 } 3499 3500 #undef FW_PARAM_PFVF 3501 #undef FW_PARAM_DEV 3502 3503 static void 3504 t4_set_desc(struct adapter *sc) 3505 { 3506 char buf[128]; 3507 struct adapter_params *p = &sc->params; 3508 3509 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 3510 3511 device_set_desc_copy(sc->dev, buf); 3512 } 3513 3514 static void 3515 build_medialist(struct port_info *pi, struct ifmedia *media) 3516 { 3517 int m; 3518 3519 PORT_LOCK(pi); 3520 3521 ifmedia_removeall(media); 3522 3523 m = IFM_ETHER | IFM_FDX; 3524 3525 switch(pi->port_type) { 3526 case FW_PORT_TYPE_BT_XFI: 3527 case FW_PORT_TYPE_BT_XAUI: 3528 ifmedia_add(media, m | IFM_10G_T, 0, NULL); 3529 /* fall through */ 3530 3531 case FW_PORT_TYPE_BT_SGMII: 3532 ifmedia_add(media, m | IFM_1000_T, 0, NULL); 3533 ifmedia_add(media, m | IFM_100_TX, 0, NULL); 3534 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL); 3535 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 3536 break; 3537 3538 case FW_PORT_TYPE_CX4: 3539 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL); 3540 ifmedia_set(media, m | IFM_10G_CX4); 3541 break; 3542 3543 case FW_PORT_TYPE_QSFP_10G: 3544 case FW_PORT_TYPE_SFP: 3545 case FW_PORT_TYPE_FIBER_XFI: 3546 case FW_PORT_TYPE_FIBER_XAUI: 3547 switch (pi->mod_type) { 3548 3549 case FW_PORT_MOD_TYPE_LR: 3550 ifmedia_add(media, m | IFM_10G_LR, 0, NULL); 3551 ifmedia_set(media, m | IFM_10G_LR); 3552 break; 3553 3554 case FW_PORT_MOD_TYPE_SR: 3555 ifmedia_add(media, m | IFM_10G_SR, 0, NULL); 3556 ifmedia_set(media, m | IFM_10G_SR); 3557 break; 3558 3559 case FW_PORT_MOD_TYPE_LRM: 3560 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL); 3561 ifmedia_set(media, m | IFM_10G_LRM); 3562 break; 3563 3564 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3565 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3566 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL); 3567 ifmedia_set(media, m | IFM_10G_TWINAX); 3568 break; 3569 3570 case FW_PORT_MOD_TYPE_NONE: 3571 m &= ~IFM_FDX; 3572 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3573 ifmedia_set(media, m | IFM_NONE); 3574 break; 3575 3576 case FW_PORT_MOD_TYPE_NA: 3577 case FW_PORT_MOD_TYPE_ER: 3578 default: 3579 device_printf(pi->dev, 3580 "unknown port_type (%d), mod_type (%d)\n", 3581 pi->port_type, pi->mod_type); 3582 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3583 ifmedia_set(media, m | IFM_UNKNOWN); 3584 break; 3585 } 3586 break; 3587 3588 case FW_PORT_TYPE_CR_QSFP: 3589 case FW_PORT_TYPE_SFP28: 3590 switch (pi->mod_type) { 3591 3592 case FW_PORT_MOD_TYPE_SR: 3593 MPASS(pi->port_type == FW_PORT_TYPE_SFP28); 3594 ifmedia_add(media, m | IFM_25G_SR, 0, NULL); 3595 ifmedia_set(media, m | IFM_25G_SR); 3596 break; 3597 3598 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3599 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3600 ifmedia_add(media, m | IFM_25G_CR, 0, NULL); 3601 ifmedia_set(media, m | IFM_25G_CR); 3602 break; 3603 3604 case FW_PORT_MOD_TYPE_NONE: 3605 m &= ~IFM_FDX; 3606 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3607 ifmedia_set(media, m | IFM_NONE); 3608 break; 3609 3610 default: 3611 device_printf(pi->dev, 3612 "unknown port_type (%d), mod_type (%d)\n", 3613 pi->port_type, pi->mod_type); 3614 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3615 ifmedia_set(media, m | IFM_UNKNOWN); 3616 break; 3617 } 3618 break; 3619 3620 case FW_PORT_TYPE_QSFP: 3621 switch (pi->mod_type) { 3622 3623 case FW_PORT_MOD_TYPE_LR: 3624 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL); 3625 ifmedia_set(media, m | IFM_40G_LR4); 3626 break; 3627 3628 case FW_PORT_MOD_TYPE_SR: 3629 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL); 3630 ifmedia_set(media, m | IFM_40G_SR4); 3631 break; 3632 3633 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3634 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3635 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL); 3636 ifmedia_set(media, m | IFM_40G_CR4); 3637 break; 3638 3639 case FW_PORT_MOD_TYPE_NONE: 3640 m &= ~IFM_FDX; 3641 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3642 ifmedia_set(media, m | IFM_NONE); 3643 break; 3644 3645 default: 3646 device_printf(pi->dev, 3647 "unknown port_type (%d), mod_type (%d)\n", 3648 pi->port_type, pi->mod_type); 3649 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3650 ifmedia_set(media, m | IFM_UNKNOWN); 3651 break; 3652 } 3653 break; 3654 3655 case FW_PORT_TYPE_CR2_QSFP: 3656 switch (pi->mod_type) { 3657 3658 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3659 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3660 ifmedia_add(media, m | IFM_50G_CR2, 0, NULL); 3661 ifmedia_set(media, m | IFM_50G_CR2); 3662 break; 3663 3664 case FW_PORT_MOD_TYPE_NONE: 3665 m &= ~IFM_FDX; 3666 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3667 ifmedia_set(media, m | IFM_NONE); 3668 break; 3669 3670 default: 3671 device_printf(pi->dev, 3672 "unknown port_type (%d), mod_type (%d)\n", 3673 pi->port_type, pi->mod_type); 3674 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3675 ifmedia_set(media, m | IFM_UNKNOWN); 3676 break; 3677 } 3678 break; 3679 3680 case FW_PORT_TYPE_KR4_100G: 3681 case FW_PORT_TYPE_CR4_QSFP: 3682 switch (pi->mod_type) { 3683 3684 case FW_PORT_MOD_TYPE_LR: 3685 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL); 3686 ifmedia_set(media, m | IFM_100G_LR4); 3687 break; 3688 3689 case FW_PORT_MOD_TYPE_SR: 3690 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL); 3691 ifmedia_set(media, m | IFM_100G_SR4); 3692 break; 3693 3694 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3695 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3696 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL); 3697 ifmedia_set(media, m | IFM_100G_CR4); 3698 break; 3699 3700 case FW_PORT_MOD_TYPE_NONE: 3701 m &= ~IFM_FDX; 3702 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3703 ifmedia_set(media, m | IFM_NONE); 3704 break; 3705 3706 default: 3707 device_printf(pi->dev, 3708 "unknown port_type (%d), mod_type (%d)\n", 3709 pi->port_type, pi->mod_type); 3710 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3711 ifmedia_set(media, m | IFM_UNKNOWN); 3712 break; 3713 } 3714 break; 3715 3716 default: 3717 device_printf(pi->dev, 3718 "unknown port_type (%d), mod_type (%d)\n", pi->port_type, 3719 pi->mod_type); 3720 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3721 ifmedia_set(media, m | IFM_UNKNOWN); 3722 break; 3723 } 3724 3725 PORT_UNLOCK(pi); 3726 } 3727 3728 #define FW_MAC_EXACT_CHUNK 7 3729 3730 /* 3731 * Program the port's XGMAC based on parameters in ifnet. The caller also 3732 * indicates which parameters should be programmed (the rest are left alone). 3733 */ 3734 int 3735 update_mac_settings(struct ifnet *ifp, int flags) 3736 { 3737 int rc = 0; 3738 struct vi_info *vi = ifp->if_softc; 3739 struct port_info *pi = vi->pi; 3740 struct adapter *sc = pi->adapter; 3741 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 3742 3743 ASSERT_SYNCHRONIZED_OP(sc); 3744 KASSERT(flags, ("%s: not told what to update.", __func__)); 3745 3746 if (flags & XGMAC_MTU) 3747 mtu = ifp->if_mtu; 3748 3749 if (flags & XGMAC_PROMISC) 3750 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 3751 3752 if (flags & XGMAC_ALLMULTI) 3753 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 3754 3755 if (flags & XGMAC_VLANEX) 3756 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 3757 3758 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 3759 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 3760 allmulti, 1, vlanex, false); 3761 if (rc) { 3762 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 3763 rc); 3764 return (rc); 3765 } 3766 } 3767 3768 if (flags & XGMAC_UCADDR) { 3769 uint8_t ucaddr[ETHER_ADDR_LEN]; 3770 3771 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 3772 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 3773 ucaddr, true, true); 3774 if (rc < 0) { 3775 rc = -rc; 3776 if_printf(ifp, "change_mac failed: %d\n", rc); 3777 return (rc); 3778 } else { 3779 vi->xact_addr_filt = rc; 3780 rc = 0; 3781 } 3782 } 3783 3784 if (flags & XGMAC_MCADDRS) { 3785 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 3786 int del = 1; 3787 uint64_t hash = 0; 3788 struct ifmultiaddr *ifma; 3789 int i = 0, j; 3790 3791 if_maddr_rlock(ifp); 3792 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 3793 if (ifma->ifma_addr->sa_family != AF_LINK) 3794 continue; 3795 mcaddr[i] = 3796 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 3797 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 3798 i++; 3799 3800 if (i == FW_MAC_EXACT_CHUNK) { 3801 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 3802 del, i, mcaddr, NULL, &hash, 0); 3803 if (rc < 0) { 3804 rc = -rc; 3805 for (j = 0; j < i; j++) { 3806 if_printf(ifp, 3807 "failed to add mc address" 3808 " %02x:%02x:%02x:" 3809 "%02x:%02x:%02x rc=%d\n", 3810 mcaddr[j][0], mcaddr[j][1], 3811 mcaddr[j][2], mcaddr[j][3], 3812 mcaddr[j][4], mcaddr[j][5], 3813 rc); 3814 } 3815 goto mcfail; 3816 } 3817 del = 0; 3818 i = 0; 3819 } 3820 } 3821 if (i > 0) { 3822 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 3823 mcaddr, NULL, &hash, 0); 3824 if (rc < 0) { 3825 rc = -rc; 3826 for (j = 0; j < i; j++) { 3827 if_printf(ifp, 3828 "failed to add mc address" 3829 " %02x:%02x:%02x:" 3830 "%02x:%02x:%02x rc=%d\n", 3831 mcaddr[j][0], mcaddr[j][1], 3832 mcaddr[j][2], mcaddr[j][3], 3833 mcaddr[j][4], mcaddr[j][5], 3834 rc); 3835 } 3836 goto mcfail; 3837 } 3838 } 3839 3840 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 3841 if (rc != 0) 3842 if_printf(ifp, "failed to set mc address hash: %d", rc); 3843 mcfail: 3844 if_maddr_runlock(ifp); 3845 } 3846 3847 return (rc); 3848 } 3849 3850 /* 3851 * {begin|end}_synchronized_op must be called from the same thread. 3852 */ 3853 int 3854 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 3855 char *wmesg) 3856 { 3857 int rc, pri; 3858 3859 #ifdef WITNESS 3860 /* the caller thinks it's ok to sleep, but is it really? */ 3861 if (flags & SLEEP_OK) 3862 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 3863 "begin_synchronized_op"); 3864 #endif 3865 3866 if (INTR_OK) 3867 pri = PCATCH; 3868 else 3869 pri = 0; 3870 3871 ADAPTER_LOCK(sc); 3872 for (;;) { 3873 3874 if (vi && IS_DOOMED(vi)) { 3875 rc = ENXIO; 3876 goto done; 3877 } 3878 3879 if (!IS_BUSY(sc)) { 3880 rc = 0; 3881 break; 3882 } 3883 3884 if (!(flags & SLEEP_OK)) { 3885 rc = EBUSY; 3886 goto done; 3887 } 3888 3889 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 3890 rc = EINTR; 3891 goto done; 3892 } 3893 } 3894 3895 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 3896 SET_BUSY(sc); 3897 #ifdef INVARIANTS 3898 sc->last_op = wmesg; 3899 sc->last_op_thr = curthread; 3900 sc->last_op_flags = flags; 3901 #endif 3902 3903 done: 3904 if (!(flags & HOLD_LOCK) || rc) 3905 ADAPTER_UNLOCK(sc); 3906 3907 return (rc); 3908 } 3909 3910 /* 3911 * Tell if_ioctl and if_init that the VI is going away. This is 3912 * special variant of begin_synchronized_op and must be paired with a 3913 * call to end_synchronized_op. 3914 */ 3915 void 3916 doom_vi(struct adapter *sc, struct vi_info *vi) 3917 { 3918 3919 ADAPTER_LOCK(sc); 3920 SET_DOOMED(vi); 3921 wakeup(&sc->flags); 3922 while (IS_BUSY(sc)) 3923 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 3924 SET_BUSY(sc); 3925 #ifdef INVARIANTS 3926 sc->last_op = "t4detach"; 3927 sc->last_op_thr = curthread; 3928 sc->last_op_flags = 0; 3929 #endif 3930 ADAPTER_UNLOCK(sc); 3931 } 3932 3933 /* 3934 * {begin|end}_synchronized_op must be called from the same thread. 3935 */ 3936 void 3937 end_synchronized_op(struct adapter *sc, int flags) 3938 { 3939 3940 if (flags & LOCK_HELD) 3941 ADAPTER_LOCK_ASSERT_OWNED(sc); 3942 else 3943 ADAPTER_LOCK(sc); 3944 3945 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 3946 CLR_BUSY(sc); 3947 wakeup(&sc->flags); 3948 ADAPTER_UNLOCK(sc); 3949 } 3950 3951 static int 3952 cxgbe_init_synchronized(struct vi_info *vi) 3953 { 3954 struct port_info *pi = vi->pi; 3955 struct adapter *sc = pi->adapter; 3956 struct ifnet *ifp = vi->ifp; 3957 int rc = 0, i; 3958 struct sge_txq *txq; 3959 3960 ASSERT_SYNCHRONIZED_OP(sc); 3961 3962 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3963 return (0); /* already running */ 3964 3965 if (!(sc->flags & FULL_INIT_DONE) && 3966 ((rc = adapter_full_init(sc)) != 0)) 3967 return (rc); /* error message displayed already */ 3968 3969 if (!(vi->flags & VI_INIT_DONE) && 3970 ((rc = vi_full_init(vi)) != 0)) 3971 return (rc); /* error message displayed already */ 3972 3973 rc = update_mac_settings(ifp, XGMAC_ALL); 3974 if (rc) 3975 goto done; /* error message displayed already */ 3976 3977 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 3978 if (rc != 0) { 3979 if_printf(ifp, "enable_vi failed: %d\n", rc); 3980 goto done; 3981 } 3982 3983 /* 3984 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 3985 * if this changes. 3986 */ 3987 3988 for_each_txq(vi, i, txq) { 3989 TXQ_LOCK(txq); 3990 txq->eq.flags |= EQ_ENABLED; 3991 TXQ_UNLOCK(txq); 3992 } 3993 3994 /* 3995 * The first iq of the first port to come up is used for tracing. 3996 */ 3997 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 3998 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 3999 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4000 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4001 V_QUEUENUMBER(sc->traceq)); 4002 pi->flags |= HAS_TRACEQ; 4003 } 4004 4005 /* all ok */ 4006 PORT_LOCK(pi); 4007 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4008 pi->up_vis++; 4009 4010 if (pi->nvi > 1 || sc->flags & IS_VF) 4011 callout_reset(&vi->tick, hz, vi_tick, vi); 4012 else 4013 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4014 PORT_UNLOCK(pi); 4015 done: 4016 if (rc != 0) 4017 cxgbe_uninit_synchronized(vi); 4018 4019 return (rc); 4020 } 4021 4022 /* 4023 * Idempotent. 4024 */ 4025 static int 4026 cxgbe_uninit_synchronized(struct vi_info *vi) 4027 { 4028 struct port_info *pi = vi->pi; 4029 struct adapter *sc = pi->adapter; 4030 struct ifnet *ifp = vi->ifp; 4031 int rc, i; 4032 struct sge_txq *txq; 4033 4034 ASSERT_SYNCHRONIZED_OP(sc); 4035 4036 if (!(vi->flags & VI_INIT_DONE)) { 4037 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING), 4038 ("uninited VI is running")); 4039 return (0); 4040 } 4041 4042 /* 4043 * Disable the VI so that all its data in either direction is discarded 4044 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4045 * tick) intact as the TP can deliver negative advice or data that it's 4046 * holding in its RAM (for an offloaded connection) even after the VI is 4047 * disabled. 4048 */ 4049 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4050 if (rc) { 4051 if_printf(ifp, "disable_vi failed: %d\n", rc); 4052 return (rc); 4053 } 4054 4055 for_each_txq(vi, i, txq) { 4056 TXQ_LOCK(txq); 4057 txq->eq.flags &= ~EQ_ENABLED; 4058 TXQ_UNLOCK(txq); 4059 } 4060 4061 PORT_LOCK(pi); 4062 if (pi->nvi > 1 || sc->flags & IS_VF) 4063 callout_stop(&vi->tick); 4064 else 4065 callout_stop(&pi->tick); 4066 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4067 PORT_UNLOCK(pi); 4068 return (0); 4069 } 4070 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4071 pi->up_vis--; 4072 if (pi->up_vis > 0) { 4073 PORT_UNLOCK(pi); 4074 return (0); 4075 } 4076 PORT_UNLOCK(pi); 4077 4078 pi->link_cfg.link_ok = 0; 4079 pi->link_cfg.speed = 0; 4080 pi->linkdnrc = -1; 4081 t4_os_link_changed(sc, pi->port_id, 0, -1); 4082 4083 return (0); 4084 } 4085 4086 /* 4087 * It is ok for this function to fail midway and return right away. t4_detach 4088 * will walk the entire sc->irq list and clean up whatever is valid. 4089 */ 4090 int 4091 t4_setup_intr_handlers(struct adapter *sc) 4092 { 4093 int rc, rid, p, q, v; 4094 char s[8]; 4095 struct irq *irq; 4096 struct port_info *pi; 4097 struct vi_info *vi; 4098 struct sge *sge = &sc->sge; 4099 struct sge_rxq *rxq; 4100 #ifdef TCP_OFFLOAD 4101 struct sge_ofld_rxq *ofld_rxq; 4102 #endif 4103 #ifdef DEV_NETMAP 4104 struct sge_nm_rxq *nm_rxq; 4105 #endif 4106 #ifdef RSS 4107 int nbuckets = rss_getnumbuckets(); 4108 #endif 4109 4110 /* 4111 * Setup interrupts. 4112 */ 4113 irq = &sc->irq[0]; 4114 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4115 if (sc->intr_count == 1) 4116 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4117 4118 /* Multiple interrupts. */ 4119 if (sc->flags & IS_VF) 4120 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4121 ("%s: too few intr.", __func__)); 4122 else 4123 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4124 ("%s: too few intr.", __func__)); 4125 4126 /* The first one is always error intr on PFs */ 4127 if (!(sc->flags & IS_VF)) { 4128 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4129 if (rc != 0) 4130 return (rc); 4131 irq++; 4132 rid++; 4133 } 4134 4135 /* The second one is always the firmware event queue (first on VFs) */ 4136 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4137 if (rc != 0) 4138 return (rc); 4139 irq++; 4140 rid++; 4141 4142 for_each_port(sc, p) { 4143 pi = sc->port[p]; 4144 for_each_vi(pi, v, vi) { 4145 vi->first_intr = rid - 1; 4146 4147 if (vi->nnmrxq > 0) { 4148 int n = max(vi->nrxq, vi->nnmrxq); 4149 4150 MPASS(vi->flags & INTR_RXQ); 4151 4152 rxq = &sge->rxq[vi->first_rxq]; 4153 #ifdef DEV_NETMAP 4154 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4155 #endif 4156 for (q = 0; q < n; q++) { 4157 snprintf(s, sizeof(s), "%x%c%x", p, 4158 'a' + v, q); 4159 if (q < vi->nrxq) 4160 irq->rxq = rxq++; 4161 #ifdef DEV_NETMAP 4162 if (q < vi->nnmrxq) 4163 irq->nm_rxq = nm_rxq++; 4164 #endif 4165 rc = t4_alloc_irq(sc, irq, rid, 4166 t4_vi_intr, irq, s); 4167 if (rc != 0) 4168 return (rc); 4169 irq++; 4170 rid++; 4171 vi->nintr++; 4172 } 4173 } else if (vi->flags & INTR_RXQ) { 4174 for_each_rxq(vi, q, rxq) { 4175 snprintf(s, sizeof(s), "%x%c%x", p, 4176 'a' + v, q); 4177 rc = t4_alloc_irq(sc, irq, rid, 4178 t4_intr, rxq, s); 4179 if (rc != 0) 4180 return (rc); 4181 #ifdef RSS 4182 bus_bind_intr(sc->dev, irq->res, 4183 rss_getcpu(q % nbuckets)); 4184 #endif 4185 irq++; 4186 rid++; 4187 vi->nintr++; 4188 } 4189 } 4190 #ifdef TCP_OFFLOAD 4191 if (vi->flags & INTR_OFLD_RXQ) { 4192 for_each_ofld_rxq(vi, q, ofld_rxq) { 4193 snprintf(s, sizeof(s), "%x%c%x", p, 4194 'A' + v, q); 4195 rc = t4_alloc_irq(sc, irq, rid, 4196 t4_intr, ofld_rxq, s); 4197 if (rc != 0) 4198 return (rc); 4199 irq++; 4200 rid++; 4201 vi->nintr++; 4202 } 4203 } 4204 #endif 4205 } 4206 } 4207 MPASS(irq == &sc->irq[sc->intr_count]); 4208 4209 return (0); 4210 } 4211 4212 int 4213 adapter_full_init(struct adapter *sc) 4214 { 4215 int rc, i; 4216 4217 ASSERT_SYNCHRONIZED_OP(sc); 4218 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4219 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 4220 ("%s: FULL_INIT_DONE already", __func__)); 4221 4222 /* 4223 * queues that belong to the adapter (not any particular port). 4224 */ 4225 rc = t4_setup_adapter_queues(sc); 4226 if (rc != 0) 4227 goto done; 4228 4229 for (i = 0; i < nitems(sc->tq); i++) { 4230 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 4231 taskqueue_thread_enqueue, &sc->tq[i]); 4232 if (sc->tq[i] == NULL) { 4233 device_printf(sc->dev, 4234 "failed to allocate task queue %d\n", i); 4235 rc = ENOMEM; 4236 goto done; 4237 } 4238 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 4239 device_get_nameunit(sc->dev), i); 4240 } 4241 4242 if (!(sc->flags & IS_VF)) 4243 t4_intr_enable(sc); 4244 sc->flags |= FULL_INIT_DONE; 4245 done: 4246 if (rc != 0) 4247 adapter_full_uninit(sc); 4248 4249 return (rc); 4250 } 4251 4252 int 4253 adapter_full_uninit(struct adapter *sc) 4254 { 4255 int i; 4256 4257 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4258 4259 t4_teardown_adapter_queues(sc); 4260 4261 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 4262 taskqueue_free(sc->tq[i]); 4263 sc->tq[i] = NULL; 4264 } 4265 4266 sc->flags &= ~FULL_INIT_DONE; 4267 4268 return (0); 4269 } 4270 4271 #ifdef RSS 4272 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 4273 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 4274 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 4275 RSS_HASHTYPE_RSS_UDP_IPV6) 4276 4277 /* Translates kernel hash types to hardware. */ 4278 static int 4279 hashconfig_to_hashen(int hashconfig) 4280 { 4281 int hashen = 0; 4282 4283 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 4284 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 4285 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 4286 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 4287 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 4288 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4289 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4290 } 4291 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 4292 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4293 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4294 } 4295 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 4296 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4297 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 4298 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4299 4300 return (hashen); 4301 } 4302 4303 /* Translates hardware hash types to kernel. */ 4304 static int 4305 hashen_to_hashconfig(int hashen) 4306 { 4307 int hashconfig = 0; 4308 4309 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 4310 /* 4311 * If UDP hashing was enabled it must have been enabled for 4312 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 4313 * enabling any 4-tuple hash is nonsense configuration. 4314 */ 4315 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4316 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 4317 4318 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4319 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 4320 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4321 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 4322 } 4323 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4324 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 4325 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4326 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 4327 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 4328 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 4329 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 4330 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 4331 4332 return (hashconfig); 4333 } 4334 #endif 4335 4336 int 4337 vi_full_init(struct vi_info *vi) 4338 { 4339 struct adapter *sc = vi->pi->adapter; 4340 struct ifnet *ifp = vi->ifp; 4341 uint16_t *rss; 4342 struct sge_rxq *rxq; 4343 int rc, i, j, hashen; 4344 #ifdef RSS 4345 int nbuckets = rss_getnumbuckets(); 4346 int hashconfig = rss_gethashconfig(); 4347 int extra; 4348 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4349 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4350 #endif 4351 4352 ASSERT_SYNCHRONIZED_OP(sc); 4353 KASSERT((vi->flags & VI_INIT_DONE) == 0, 4354 ("%s: VI_INIT_DONE already", __func__)); 4355 4356 sysctl_ctx_init(&vi->ctx); 4357 vi->flags |= VI_SYSCTL_CTX; 4358 4359 /* 4360 * Allocate tx/rx/fl queues for this VI. 4361 */ 4362 rc = t4_setup_vi_queues(vi); 4363 if (rc != 0) 4364 goto done; /* error message displayed already */ 4365 4366 /* 4367 * Setup RSS for this VI. Save a copy of the RSS table for later use. 4368 */ 4369 if (vi->nrxq > vi->rss_size) { 4370 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 4371 "some queues will never receive traffic.\n", vi->nrxq, 4372 vi->rss_size); 4373 } else if (vi->rss_size % vi->nrxq) { 4374 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 4375 "expect uneven traffic distribution.\n", vi->nrxq, 4376 vi->rss_size); 4377 } 4378 #ifdef RSS 4379 MPASS(RSS_KEYSIZE == 40); 4380 if (vi->nrxq != nbuckets) { 4381 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 4382 "performance will be impacted.\n", vi->nrxq, nbuckets); 4383 } 4384 4385 rss_getkey((void *)&raw_rss_key[0]); 4386 for (i = 0; i < nitems(rss_key); i++) { 4387 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 4388 } 4389 t4_write_rss_key(sc, &rss_key[0], -1); 4390 #endif 4391 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 4392 for (i = 0; i < vi->rss_size;) { 4393 #ifdef RSS 4394 j = rss_get_indirection_to_bucket(i); 4395 j %= vi->nrxq; 4396 rxq = &sc->sge.rxq[vi->first_rxq + j]; 4397 rss[i++] = rxq->iq.abs_id; 4398 #else 4399 for_each_rxq(vi, j, rxq) { 4400 rss[i++] = rxq->iq.abs_id; 4401 if (i == vi->rss_size) 4402 break; 4403 } 4404 #endif 4405 } 4406 4407 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 4408 vi->rss_size); 4409 if (rc != 0) { 4410 if_printf(ifp, "rss_config failed: %d\n", rc); 4411 goto done; 4412 } 4413 4414 #ifdef RSS 4415 hashen = hashconfig_to_hashen(hashconfig); 4416 4417 /* 4418 * We may have had to enable some hashes even though the global config 4419 * wants them disabled. This is a potential problem that must be 4420 * reported to the user. 4421 */ 4422 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 4423 4424 /* 4425 * If we consider only the supported hash types, then the enabled hashes 4426 * are a superset of the requested hashes. In other words, there cannot 4427 * be any supported hash that was requested but not enabled, but there 4428 * can be hashes that were not requested but had to be enabled. 4429 */ 4430 extra &= SUPPORTED_RSS_HASHTYPES; 4431 MPASS((extra & hashconfig) == 0); 4432 4433 if (extra) { 4434 if_printf(ifp, 4435 "global RSS config (0x%x) cannot be accommodated.\n", 4436 hashconfig); 4437 } 4438 if (extra & RSS_HASHTYPE_RSS_IPV4) 4439 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 4440 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 4441 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 4442 if (extra & RSS_HASHTYPE_RSS_IPV6) 4443 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 4444 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 4445 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 4446 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 4447 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 4448 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 4449 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 4450 #else 4451 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 4452 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 4453 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4454 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 4455 #endif 4456 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]); 4457 if (rc != 0) { 4458 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 4459 goto done; 4460 } 4461 4462 vi->rss = rss; 4463 vi->flags |= VI_INIT_DONE; 4464 done: 4465 if (rc != 0) 4466 vi_full_uninit(vi); 4467 4468 return (rc); 4469 } 4470 4471 /* 4472 * Idempotent. 4473 */ 4474 int 4475 vi_full_uninit(struct vi_info *vi) 4476 { 4477 struct port_info *pi = vi->pi; 4478 struct adapter *sc = pi->adapter; 4479 int i; 4480 struct sge_rxq *rxq; 4481 struct sge_txq *txq; 4482 #ifdef TCP_OFFLOAD 4483 struct sge_ofld_rxq *ofld_rxq; 4484 struct sge_wrq *ofld_txq; 4485 #endif 4486 4487 if (vi->flags & VI_INIT_DONE) { 4488 4489 /* Need to quiesce queues. */ 4490 4491 /* XXX: Only for the first VI? */ 4492 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 4493 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 4494 4495 for_each_txq(vi, i, txq) { 4496 quiesce_txq(sc, txq); 4497 } 4498 4499 #ifdef TCP_OFFLOAD 4500 for_each_ofld_txq(vi, i, ofld_txq) { 4501 quiesce_wrq(sc, ofld_txq); 4502 } 4503 #endif 4504 4505 for_each_rxq(vi, i, rxq) { 4506 quiesce_iq(sc, &rxq->iq); 4507 quiesce_fl(sc, &rxq->fl); 4508 } 4509 4510 #ifdef TCP_OFFLOAD 4511 for_each_ofld_rxq(vi, i, ofld_rxq) { 4512 quiesce_iq(sc, &ofld_rxq->iq); 4513 quiesce_fl(sc, &ofld_rxq->fl); 4514 } 4515 #endif 4516 free(vi->rss, M_CXGBE); 4517 free(vi->nm_rss, M_CXGBE); 4518 } 4519 4520 t4_teardown_vi_queues(vi); 4521 vi->flags &= ~VI_INIT_DONE; 4522 4523 return (0); 4524 } 4525 4526 static void 4527 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 4528 { 4529 struct sge_eq *eq = &txq->eq; 4530 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4531 4532 (void) sc; /* unused */ 4533 4534 #ifdef INVARIANTS 4535 TXQ_LOCK(txq); 4536 MPASS((eq->flags & EQ_ENABLED) == 0); 4537 TXQ_UNLOCK(txq); 4538 #endif 4539 4540 /* Wait for the mp_ring to empty. */ 4541 while (!mp_ring_is_idle(txq->r)) { 4542 mp_ring_check_drainage(txq->r, 0); 4543 pause("rquiesce", 1); 4544 } 4545 4546 /* Then wait for the hardware to finish. */ 4547 while (spg->cidx != htobe16(eq->pidx)) 4548 pause("equiesce", 1); 4549 4550 /* Finally, wait for the driver to reclaim all descriptors. */ 4551 while (eq->cidx != eq->pidx) 4552 pause("dquiesce", 1); 4553 } 4554 4555 static void 4556 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 4557 { 4558 4559 /* XXXTX */ 4560 } 4561 4562 static void 4563 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 4564 { 4565 (void) sc; /* unused */ 4566 4567 /* Synchronize with the interrupt handler */ 4568 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 4569 pause("iqfree", 1); 4570 } 4571 4572 static void 4573 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 4574 { 4575 mtx_lock(&sc->sfl_lock); 4576 FL_LOCK(fl); 4577 fl->flags |= FL_DOOMED; 4578 FL_UNLOCK(fl); 4579 callout_stop(&sc->sfl_callout); 4580 mtx_unlock(&sc->sfl_lock); 4581 4582 KASSERT((fl->flags & FL_STARVING) == 0, 4583 ("%s: still starving", __func__)); 4584 } 4585 4586 static int 4587 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 4588 driver_intr_t *handler, void *arg, char *name) 4589 { 4590 int rc; 4591 4592 irq->rid = rid; 4593 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 4594 RF_SHAREABLE | RF_ACTIVE); 4595 if (irq->res == NULL) { 4596 device_printf(sc->dev, 4597 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 4598 return (ENOMEM); 4599 } 4600 4601 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 4602 NULL, handler, arg, &irq->tag); 4603 if (rc != 0) { 4604 device_printf(sc->dev, 4605 "failed to setup interrupt for rid %d, name %s: %d\n", 4606 rid, name, rc); 4607 } else if (name) 4608 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 4609 4610 return (rc); 4611 } 4612 4613 static int 4614 t4_free_irq(struct adapter *sc, struct irq *irq) 4615 { 4616 if (irq->tag) 4617 bus_teardown_intr(sc->dev, irq->res, irq->tag); 4618 if (irq->res) 4619 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 4620 4621 bzero(irq, sizeof(*irq)); 4622 4623 return (0); 4624 } 4625 4626 static void 4627 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 4628 { 4629 4630 regs->version = chip_id(sc) | chip_rev(sc) << 10; 4631 t4_get_regs(sc, buf, regs->len); 4632 } 4633 4634 #define A_PL_INDIR_CMD 0x1f8 4635 4636 #define S_PL_AUTOINC 31 4637 #define M_PL_AUTOINC 0x1U 4638 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 4639 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 4640 4641 #define S_PL_VFID 20 4642 #define M_PL_VFID 0xffU 4643 #define V_PL_VFID(x) ((x) << S_PL_VFID) 4644 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 4645 4646 #define S_PL_ADDR 0 4647 #define M_PL_ADDR 0xfffffU 4648 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 4649 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 4650 4651 #define A_PL_INDIR_DATA 0x1fc 4652 4653 static uint64_t 4654 read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 4655 { 4656 u32 stats[2]; 4657 4658 mtx_assert(&sc->reg_lock, MA_OWNED); 4659 if (sc->flags & IS_VF) { 4660 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 4661 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 4662 } else { 4663 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4664 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4665 V_PL_ADDR(VF_MPS_REG(reg))); 4666 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 4667 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 4668 } 4669 return (((uint64_t)stats[1]) << 32 | stats[0]); 4670 } 4671 4672 static void 4673 t4_get_vi_stats(struct adapter *sc, unsigned int viid, 4674 struct fw_vi_stats_vf *stats) 4675 { 4676 4677 #define GET_STAT(name) \ 4678 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 4679 4680 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 4681 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 4682 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 4683 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 4684 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 4685 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 4686 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 4687 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 4688 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 4689 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 4690 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 4691 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 4692 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 4693 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 4694 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 4695 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 4696 4697 #undef GET_STAT 4698 } 4699 4700 static void 4701 t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 4702 { 4703 int reg; 4704 4705 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4706 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4707 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 4708 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 4709 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 4710 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 4711 } 4712 4713 static void 4714 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 4715 { 4716 struct timeval tv; 4717 const struct timeval interval = {0, 250000}; /* 250ms */ 4718 4719 if (!(vi->flags & VI_INIT_DONE)) 4720 return; 4721 4722 getmicrotime(&tv); 4723 timevalsub(&tv, &interval); 4724 if (timevalcmp(&tv, &vi->last_refreshed, <)) 4725 return; 4726 4727 mtx_lock(&sc->reg_lock); 4728 t4_get_vi_stats(sc, vi->viid, &vi->stats); 4729 getmicrotime(&vi->last_refreshed); 4730 mtx_unlock(&sc->reg_lock); 4731 } 4732 4733 static void 4734 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 4735 { 4736 int i; 4737 u_int v, tnl_cong_drops; 4738 struct timeval tv; 4739 const struct timeval interval = {0, 250000}; /* 250ms */ 4740 4741 getmicrotime(&tv); 4742 timevalsub(&tv, &interval); 4743 if (timevalcmp(&tv, &pi->last_refreshed, <)) 4744 return; 4745 4746 tnl_cong_drops = 0; 4747 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 4748 for (i = 0; i < sc->chip_params->nchan; i++) { 4749 if (pi->rx_chan_map & (1 << i)) { 4750 mtx_lock(&sc->reg_lock); 4751 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 4752 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 4753 mtx_unlock(&sc->reg_lock); 4754 tnl_cong_drops += v; 4755 } 4756 } 4757 pi->tnl_cong_drops = tnl_cong_drops; 4758 getmicrotime(&pi->last_refreshed); 4759 } 4760 4761 static void 4762 cxgbe_tick(void *arg) 4763 { 4764 struct port_info *pi = arg; 4765 struct adapter *sc = pi->adapter; 4766 4767 PORT_LOCK_ASSERT_OWNED(pi); 4768 cxgbe_refresh_stats(sc, pi); 4769 4770 callout_schedule(&pi->tick, hz); 4771 } 4772 4773 void 4774 vi_tick(void *arg) 4775 { 4776 struct vi_info *vi = arg; 4777 struct adapter *sc = vi->pi->adapter; 4778 4779 vi_refresh_stats(sc, vi); 4780 4781 callout_schedule(&vi->tick, hz); 4782 } 4783 4784 static void 4785 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 4786 { 4787 struct ifnet *vlan; 4788 4789 if (arg != ifp || ifp->if_type != IFT_ETHER) 4790 return; 4791 4792 vlan = VLAN_DEVAT(ifp, vid); 4793 VLAN_SETCOOKIE(vlan, ifp); 4794 } 4795 4796 /* 4797 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 4798 */ 4799 static char *caps_decoder[] = { 4800 "\20\001IPMI\002NCSI", /* 0: NBM */ 4801 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 4802 "\20\001INGRESS\002EGRESS", /* 2: switch */ 4803 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 4804 "\006HASHFILTER\007ETHOFLD", 4805 "\20\001TOE", /* 4: TOE */ 4806 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 4807 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 4808 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 4809 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 4810 "\007T10DIF" 4811 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 4812 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 4813 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 4814 "\004PO_INITIATOR\005PO_TARGET", 4815 }; 4816 4817 void 4818 t4_sysctls(struct adapter *sc) 4819 { 4820 struct sysctl_ctx_list *ctx; 4821 struct sysctl_oid *oid; 4822 struct sysctl_oid_list *children, *c0; 4823 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 4824 4825 ctx = device_get_sysctl_ctx(sc->dev); 4826 4827 /* 4828 * dev.t4nex.X. 4829 */ 4830 oid = device_get_sysctl_tree(sc->dev); 4831 c0 = children = SYSCTL_CHILDREN(oid); 4832 4833 sc->sc_do_rxcopy = 1; 4834 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 4835 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 4836 4837 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 4838 sc->params.nports, "# of ports"); 4839 4840 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 4841 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 4842 sysctl_bitfield, "A", "available doorbells"); 4843 4844 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 4845 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 4846 4847 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 4848 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 4849 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 4850 "interrupt holdoff timer values (us)"); 4851 4852 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 4853 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 4854 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 4855 "interrupt holdoff packet counter values"); 4856 4857 t4_sge_sysctls(sc, ctx, children); 4858 4859 sc->lro_timeout = 100; 4860 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 4861 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 4862 4863 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 4864 &sc->debug_flags, 0, "flags to enable runtime debugging"); 4865 4866 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 4867 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 4868 4869 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 4870 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 4871 4872 if (sc->flags & IS_VF) 4873 return; 4874 4875 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 4876 NULL, chip_rev(sc), "chip hardware revision"); 4877 4878 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 4879 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 4880 4881 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 4882 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 4883 4884 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 4885 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 4886 4887 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 4888 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 4889 4890 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 4891 sc->er_version, 0, "expansion ROM version"); 4892 4893 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 4894 sc->bs_version, 0, "bootstrap firmware version"); 4895 4896 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 4897 NULL, sc->params.scfg_vers, "serial config version"); 4898 4899 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 4900 NULL, sc->params.vpd_vers, "VPD version"); 4901 4902 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 4903 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 4904 4905 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 4906 sc->cfcsum, "config file checksum"); 4907 4908 #define SYSCTL_CAP(name, n, text) \ 4909 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 4910 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \ 4911 sysctl_bitfield, "A", "available " text " capabilities") 4912 4913 SYSCTL_CAP(nbmcaps, 0, "NBM"); 4914 SYSCTL_CAP(linkcaps, 1, "link"); 4915 SYSCTL_CAP(switchcaps, 2, "switch"); 4916 SYSCTL_CAP(niccaps, 3, "NIC"); 4917 SYSCTL_CAP(toecaps, 4, "TCP offload"); 4918 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 4919 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 4920 SYSCTL_CAP(cryptocaps, 7, "crypto"); 4921 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 4922 #undef SYSCTL_CAP 4923 4924 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 4925 NULL, sc->tids.nftids, "number of filters"); 4926 4927 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 4928 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 4929 "chip temperature (in Celsius)"); 4930 4931 #ifdef SBUF_DRAIN 4932 /* 4933 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 4934 */ 4935 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 4936 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 4937 "logs and miscellaneous information"); 4938 children = SYSCTL_CHILDREN(oid); 4939 4940 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 4941 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4942 sysctl_cctrl, "A", "congestion control"); 4943 4944 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 4945 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4946 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 4947 4948 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 4949 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 4950 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 4951 4952 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 4953 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 4954 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 4955 4956 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 4957 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 4958 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 4959 4960 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 4961 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 4962 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 4963 4964 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 4965 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 4966 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 4967 4968 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 4969 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4970 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 4971 "A", "CIM logic analyzer"); 4972 4973 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 4974 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4975 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 4976 4977 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 4978 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 4979 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 4980 4981 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 4982 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 4983 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 4984 4985 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 4986 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 4987 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 4988 4989 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 4990 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 4991 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 4992 4993 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 4994 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 4995 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 4996 4997 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 4998 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 4999 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5000 5001 if (chip_id(sc) > CHELSIO_T4) { 5002 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5003 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5004 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5005 5006 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5007 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5008 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5009 } 5010 5011 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5012 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5013 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5014 5015 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5016 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5017 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5018 5019 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5020 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5021 sysctl_cpl_stats, "A", "CPL statistics"); 5022 5023 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5024 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5025 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5026 5027 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5028 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5029 sysctl_devlog, "A", "firmware's device log"); 5030 5031 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5032 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5033 sysctl_fcoe_stats, "A", "FCoE statistics"); 5034 5035 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5036 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5037 sysctl_hw_sched, "A", "hardware scheduler "); 5038 5039 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5040 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5041 sysctl_l2t, "A", "hardware L2 table"); 5042 5043 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5044 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5045 sysctl_lb_stats, "A", "loopback statistics"); 5046 5047 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5048 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5049 sysctl_meminfo, "A", "memory regions"); 5050 5051 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5052 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5053 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5054 "A", "MPS TCAM entries"); 5055 5056 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5057 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5058 sysctl_path_mtus, "A", "path MTUs"); 5059 5060 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5061 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5062 sysctl_pm_stats, "A", "PM statistics"); 5063 5064 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5065 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5066 sysctl_rdma_stats, "A", "RDMA statistics"); 5067 5068 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5069 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5070 sysctl_tcp_stats, "A", "TCP statistics"); 5071 5072 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5073 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5074 sysctl_tids, "A", "TID information"); 5075 5076 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5077 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5078 sysctl_tp_err_stats, "A", "TP error statistics"); 5079 5080 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5081 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5082 "TP logic analyzer event capture mask"); 5083 5084 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5085 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5086 sysctl_tp_la, "A", "TP logic analyzer"); 5087 5088 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5089 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5090 sysctl_tx_rate, "A", "Tx rate"); 5091 5092 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5093 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5094 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5095 5096 if (is_t5(sc)) { 5097 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5098 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5099 sysctl_wcwr_stats, "A", "write combined work requests"); 5100 } 5101 #endif 5102 5103 #ifdef TCP_OFFLOAD 5104 if (is_offload(sc)) { 5105 /* 5106 * dev.t4nex.X.toe. 5107 */ 5108 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5109 NULL, "TOE parameters"); 5110 children = SYSCTL_CHILDREN(oid); 5111 5112 sc->tt.sndbuf = 256 * 1024; 5113 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 5114 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 5115 5116 sc->tt.ddp = 0; 5117 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 5118 &sc->tt.ddp, 0, "DDP allowed"); 5119 5120 sc->tt.rx_coalesce = 1; 5121 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 5122 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 5123 5124 sc->tt.tx_align = 1; 5125 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 5126 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 5127 5128 sc->tt.tx_zcopy = 0; 5129 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 5130 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 5131 "Enable zero-copy aio_write(2)"); 5132 5133 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 5134 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 5135 "TP timer tick (us)"); 5136 5137 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 5138 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 5139 "TCP timestamp tick (us)"); 5140 5141 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 5142 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 5143 "DACK tick (us)"); 5144 5145 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 5146 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 5147 "IU", "DACK timer (us)"); 5148 5149 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 5150 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 5151 sysctl_tp_timer, "LU", "Retransmit min (us)"); 5152 5153 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 5154 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 5155 sysctl_tp_timer, "LU", "Retransmit max (us)"); 5156 5157 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 5158 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 5159 sysctl_tp_timer, "LU", "Persist timer min (us)"); 5160 5161 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 5162 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 5163 sysctl_tp_timer, "LU", "Persist timer max (us)"); 5164 5165 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 5166 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 5167 sysctl_tp_timer, "LU", "Keepidle idle timer (us)"); 5168 5169 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl", 5170 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 5171 sysctl_tp_timer, "LU", "Keepidle interval (us)"); 5172 5173 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 5174 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 5175 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 5176 5177 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 5178 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 5179 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 5180 } 5181 #endif 5182 } 5183 5184 void 5185 vi_sysctls(struct vi_info *vi) 5186 { 5187 struct sysctl_ctx_list *ctx; 5188 struct sysctl_oid *oid; 5189 struct sysctl_oid_list *children; 5190 5191 ctx = device_get_sysctl_ctx(vi->dev); 5192 5193 /* 5194 * dev.v?(cxgbe|cxl).X. 5195 */ 5196 oid = device_get_sysctl_tree(vi->dev); 5197 children = SYSCTL_CHILDREN(oid); 5198 5199 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 5200 vi->viid, "VI identifer"); 5201 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 5202 &vi->nrxq, 0, "# of rx queues"); 5203 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 5204 &vi->ntxq, 0, "# of tx queues"); 5205 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 5206 &vi->first_rxq, 0, "index of first rx queue"); 5207 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 5208 &vi->first_txq, 0, "index of first tx queue"); 5209 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 5210 vi->rss_size, "size of RSS indirection table"); 5211 5212 if (IS_MAIN_VI(vi)) { 5213 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 5214 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 5215 "Reserve queue 0 for non-flowid packets"); 5216 } 5217 5218 #ifdef TCP_OFFLOAD 5219 if (vi->nofldrxq != 0) { 5220 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 5221 &vi->nofldrxq, 0, 5222 "# of rx queues for offloaded TCP connections"); 5223 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 5224 &vi->nofldtxq, 0, 5225 "# of tx queues for offloaded TCP connections"); 5226 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 5227 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 5228 "index of first TOE rx queue"); 5229 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 5230 CTLFLAG_RD, &vi->first_ofld_txq, 0, 5231 "index of first TOE tx queue"); 5232 } 5233 #endif 5234 #ifdef DEV_NETMAP 5235 if (vi->nnmrxq != 0) { 5236 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 5237 &vi->nnmrxq, 0, "# of netmap rx queues"); 5238 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 5239 &vi->nnmtxq, 0, "# of netmap tx queues"); 5240 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 5241 CTLFLAG_RD, &vi->first_nm_rxq, 0, 5242 "index of first netmap rx queue"); 5243 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 5244 CTLFLAG_RD, &vi->first_nm_txq, 0, 5245 "index of first netmap tx queue"); 5246 } 5247 #endif 5248 5249 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 5250 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 5251 "holdoff timer index"); 5252 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 5253 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 5254 "holdoff packet counter index"); 5255 5256 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 5257 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 5258 "rx queue size"); 5259 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 5260 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 5261 "tx queue size"); 5262 } 5263 5264 static void 5265 cxgbe_sysctls(struct port_info *pi) 5266 { 5267 struct sysctl_ctx_list *ctx; 5268 struct sysctl_oid *oid; 5269 struct sysctl_oid_list *children, *children2; 5270 struct adapter *sc = pi->adapter; 5271 int i; 5272 char name[16]; 5273 5274 ctx = device_get_sysctl_ctx(pi->dev); 5275 5276 /* 5277 * dev.cxgbe.X. 5278 */ 5279 oid = device_get_sysctl_tree(pi->dev); 5280 children = SYSCTL_CHILDREN(oid); 5281 5282 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 5283 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 5284 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 5285 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 5286 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 5287 "PHY temperature (in Celsius)"); 5288 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 5289 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 5290 "PHY firmware version"); 5291 } 5292 5293 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 5294 CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings, 5295 "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)"); 5296 5297 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 5298 port_top_speed(pi), "max speed (in Gbps)"); 5299 5300 if (sc->flags & IS_VF) 5301 return; 5302 5303 /* 5304 * dev.(cxgbe|cxl).X.tc. 5305 */ 5306 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 5307 "Tx scheduler traffic classes"); 5308 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 5309 struct tx_sched_class *tc = &pi->tc[i]; 5310 5311 snprintf(name, sizeof(name), "%d", i); 5312 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 5313 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 5314 "traffic class")); 5315 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD, 5316 &tc->flags, 0, "flags"); 5317 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 5318 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 5319 #ifdef SBUF_DRAIN 5320 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 5321 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 5322 sysctl_tc_params, "A", "traffic class parameters"); 5323 #endif 5324 } 5325 5326 /* 5327 * dev.cxgbe.X.stats. 5328 */ 5329 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 5330 NULL, "port statistics"); 5331 children = SYSCTL_CHILDREN(oid); 5332 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 5333 &pi->tx_parse_error, 0, 5334 "# of tx packets with invalid length or # of segments"); 5335 5336 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 5337 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 5338 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 5339 sysctl_handle_t4_reg64, "QU", desc) 5340 5341 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 5342 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 5343 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 5344 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 5345 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 5346 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 5347 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 5348 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 5349 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 5350 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 5351 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 5352 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 5353 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 5354 "# of tx frames in this range", 5355 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 5356 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 5357 "# of tx frames in this range", 5358 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 5359 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 5360 "# of tx frames in this range", 5361 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 5362 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 5363 "# of tx frames in this range", 5364 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 5365 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 5366 "# of tx frames in this range", 5367 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 5368 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 5369 "# of tx frames in this range", 5370 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 5371 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 5372 "# of tx frames in this range", 5373 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 5374 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 5375 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 5376 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 5377 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 5378 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 5379 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 5380 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 5381 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 5382 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 5383 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 5384 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 5385 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 5386 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 5387 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 5388 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 5389 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 5390 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 5391 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 5392 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 5393 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 5394 5395 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 5396 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 5397 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 5398 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 5399 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 5400 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 5401 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 5402 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 5403 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 5404 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 5405 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 5406 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 5407 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 5408 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 5409 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 5410 "# of frames received with bad FCS", 5411 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 5412 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 5413 "# of frames received with length error", 5414 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 5415 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 5416 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 5417 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 5418 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 5419 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 5420 "# of rx frames in this range", 5421 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 5422 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 5423 "# of rx frames in this range", 5424 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 5425 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 5426 "# of rx frames in this range", 5427 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 5428 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 5429 "# of rx frames in this range", 5430 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 5431 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 5432 "# of rx frames in this range", 5433 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 5434 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 5435 "# of rx frames in this range", 5436 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 5437 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 5438 "# of rx frames in this range", 5439 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 5440 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 5441 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 5442 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 5443 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 5444 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 5445 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 5446 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 5447 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 5448 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 5449 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 5450 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 5451 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 5452 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 5453 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 5454 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 5455 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 5456 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 5457 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 5458 5459 #undef SYSCTL_ADD_T4_REG64 5460 5461 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 5462 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 5463 &pi->stats.name, desc) 5464 5465 /* We get these from port_stats and they may be stale by up to 1s */ 5466 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 5467 "# drops due to buffer-group 0 overflows"); 5468 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 5469 "# drops due to buffer-group 1 overflows"); 5470 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 5471 "# drops due to buffer-group 2 overflows"); 5472 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 5473 "# drops due to buffer-group 3 overflows"); 5474 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 5475 "# of buffer-group 0 truncated packets"); 5476 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 5477 "# of buffer-group 1 truncated packets"); 5478 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 5479 "# of buffer-group 2 truncated packets"); 5480 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 5481 "# of buffer-group 3 truncated packets"); 5482 5483 #undef SYSCTL_ADD_T4_PORTSTAT 5484 } 5485 5486 static int 5487 sysctl_int_array(SYSCTL_HANDLER_ARGS) 5488 { 5489 int rc, *i, space = 0; 5490 struct sbuf sb; 5491 5492 sbuf_new_for_sysctl(&sb, NULL, 64, req); 5493 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 5494 if (space) 5495 sbuf_printf(&sb, " "); 5496 sbuf_printf(&sb, "%d", *i); 5497 space = 1; 5498 } 5499 rc = sbuf_finish(&sb); 5500 sbuf_delete(&sb); 5501 return (rc); 5502 } 5503 5504 static int 5505 sysctl_bitfield(SYSCTL_HANDLER_ARGS) 5506 { 5507 int rc; 5508 struct sbuf *sb; 5509 5510 rc = sysctl_wire_old_buffer(req, 0); 5511 if (rc != 0) 5512 return(rc); 5513 5514 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5515 if (sb == NULL) 5516 return (ENOMEM); 5517 5518 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 5519 rc = sbuf_finish(sb); 5520 sbuf_delete(sb); 5521 5522 return (rc); 5523 } 5524 5525 static int 5526 sysctl_btphy(SYSCTL_HANDLER_ARGS) 5527 { 5528 struct port_info *pi = arg1; 5529 int op = arg2; 5530 struct adapter *sc = pi->adapter; 5531 u_int v; 5532 int rc; 5533 5534 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 5535 if (rc) 5536 return (rc); 5537 /* XXX: magic numbers */ 5538 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 5539 &v); 5540 end_synchronized_op(sc, 0); 5541 if (rc) 5542 return (rc); 5543 if (op == 0) 5544 v /= 256; 5545 5546 rc = sysctl_handle_int(oidp, &v, 0, req); 5547 return (rc); 5548 } 5549 5550 static int 5551 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 5552 { 5553 struct vi_info *vi = arg1; 5554 int rc, val; 5555 5556 val = vi->rsrv_noflowq; 5557 rc = sysctl_handle_int(oidp, &val, 0, req); 5558 if (rc != 0 || req->newptr == NULL) 5559 return (rc); 5560 5561 if ((val >= 1) && (vi->ntxq > 1)) 5562 vi->rsrv_noflowq = 1; 5563 else 5564 vi->rsrv_noflowq = 0; 5565 5566 return (rc); 5567 } 5568 5569 static int 5570 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 5571 { 5572 struct vi_info *vi = arg1; 5573 struct adapter *sc = vi->pi->adapter; 5574 int idx, rc, i; 5575 struct sge_rxq *rxq; 5576 #ifdef TCP_OFFLOAD 5577 struct sge_ofld_rxq *ofld_rxq; 5578 #endif 5579 uint8_t v; 5580 5581 idx = vi->tmr_idx; 5582 5583 rc = sysctl_handle_int(oidp, &idx, 0, req); 5584 if (rc != 0 || req->newptr == NULL) 5585 return (rc); 5586 5587 if (idx < 0 || idx >= SGE_NTIMERS) 5588 return (EINVAL); 5589 5590 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5591 "t4tmr"); 5592 if (rc) 5593 return (rc); 5594 5595 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 5596 for_each_rxq(vi, i, rxq) { 5597 #ifdef atomic_store_rel_8 5598 atomic_store_rel_8(&rxq->iq.intr_params, v); 5599 #else 5600 rxq->iq.intr_params = v; 5601 #endif 5602 } 5603 #ifdef TCP_OFFLOAD 5604 for_each_ofld_rxq(vi, i, ofld_rxq) { 5605 #ifdef atomic_store_rel_8 5606 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 5607 #else 5608 ofld_rxq->iq.intr_params = v; 5609 #endif 5610 } 5611 #endif 5612 vi->tmr_idx = idx; 5613 5614 end_synchronized_op(sc, LOCK_HELD); 5615 return (0); 5616 } 5617 5618 static int 5619 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 5620 { 5621 struct vi_info *vi = arg1; 5622 struct adapter *sc = vi->pi->adapter; 5623 int idx, rc; 5624 5625 idx = vi->pktc_idx; 5626 5627 rc = sysctl_handle_int(oidp, &idx, 0, req); 5628 if (rc != 0 || req->newptr == NULL) 5629 return (rc); 5630 5631 if (idx < -1 || idx >= SGE_NCOUNTERS) 5632 return (EINVAL); 5633 5634 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5635 "t4pktc"); 5636 if (rc) 5637 return (rc); 5638 5639 if (vi->flags & VI_INIT_DONE) 5640 rc = EBUSY; /* cannot be changed once the queues are created */ 5641 else 5642 vi->pktc_idx = idx; 5643 5644 end_synchronized_op(sc, LOCK_HELD); 5645 return (rc); 5646 } 5647 5648 static int 5649 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 5650 { 5651 struct vi_info *vi = arg1; 5652 struct adapter *sc = vi->pi->adapter; 5653 int qsize, rc; 5654 5655 qsize = vi->qsize_rxq; 5656 5657 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5658 if (rc != 0 || req->newptr == NULL) 5659 return (rc); 5660 5661 if (qsize < 128 || (qsize & 7)) 5662 return (EINVAL); 5663 5664 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5665 "t4rxqs"); 5666 if (rc) 5667 return (rc); 5668 5669 if (vi->flags & VI_INIT_DONE) 5670 rc = EBUSY; /* cannot be changed once the queues are created */ 5671 else 5672 vi->qsize_rxq = qsize; 5673 5674 end_synchronized_op(sc, LOCK_HELD); 5675 return (rc); 5676 } 5677 5678 static int 5679 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 5680 { 5681 struct vi_info *vi = arg1; 5682 struct adapter *sc = vi->pi->adapter; 5683 int qsize, rc; 5684 5685 qsize = vi->qsize_txq; 5686 5687 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5688 if (rc != 0 || req->newptr == NULL) 5689 return (rc); 5690 5691 if (qsize < 128 || qsize > 65536) 5692 return (EINVAL); 5693 5694 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5695 "t4txqs"); 5696 if (rc) 5697 return (rc); 5698 5699 if (vi->flags & VI_INIT_DONE) 5700 rc = EBUSY; /* cannot be changed once the queues are created */ 5701 else 5702 vi->qsize_txq = qsize; 5703 5704 end_synchronized_op(sc, LOCK_HELD); 5705 return (rc); 5706 } 5707 5708 static int 5709 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 5710 { 5711 struct port_info *pi = arg1; 5712 struct adapter *sc = pi->adapter; 5713 struct link_config *lc = &pi->link_cfg; 5714 int rc; 5715 5716 if (req->newptr == NULL) { 5717 struct sbuf *sb; 5718 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX"; 5719 5720 rc = sysctl_wire_old_buffer(req, 0); 5721 if (rc != 0) 5722 return(rc); 5723 5724 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5725 if (sb == NULL) 5726 return (ENOMEM); 5727 5728 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits); 5729 rc = sbuf_finish(sb); 5730 sbuf_delete(sb); 5731 } else { 5732 char s[2]; 5733 int n; 5734 5735 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX)); 5736 s[1] = 0; 5737 5738 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 5739 if (rc != 0) 5740 return(rc); 5741 5742 if (s[1] != 0) 5743 return (EINVAL); 5744 if (s[0] < '0' || s[0] > '9') 5745 return (EINVAL); /* not a number */ 5746 n = s[0] - '0'; 5747 if (n & ~(PAUSE_TX | PAUSE_RX)) 5748 return (EINVAL); /* some other bit is set too */ 5749 5750 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 5751 "t4PAUSE"); 5752 if (rc) 5753 return (rc); 5754 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) { 5755 int link_ok = lc->link_ok; 5756 5757 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 5758 lc->requested_fc |= n; 5759 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5760 lc->link_ok = link_ok; /* restore */ 5761 } 5762 end_synchronized_op(sc, 0); 5763 } 5764 5765 return (rc); 5766 } 5767 5768 static int 5769 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 5770 { 5771 struct adapter *sc = arg1; 5772 int reg = arg2; 5773 uint64_t val; 5774 5775 val = t4_read_reg64(sc, reg); 5776 5777 return (sysctl_handle_64(oidp, &val, 0, req)); 5778 } 5779 5780 static int 5781 sysctl_temperature(SYSCTL_HANDLER_ARGS) 5782 { 5783 struct adapter *sc = arg1; 5784 int rc, t; 5785 uint32_t param, val; 5786 5787 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 5788 if (rc) 5789 return (rc); 5790 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5791 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5792 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 5793 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5794 end_synchronized_op(sc, 0); 5795 if (rc) 5796 return (rc); 5797 5798 /* unknown is returned as 0 but we display -1 in that case */ 5799 t = val == 0 ? -1 : val; 5800 5801 rc = sysctl_handle_int(oidp, &t, 0, req); 5802 return (rc); 5803 } 5804 5805 #ifdef SBUF_DRAIN 5806 static int 5807 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 5808 { 5809 struct adapter *sc = arg1; 5810 struct sbuf *sb; 5811 int rc, i; 5812 uint16_t incr[NMTUS][NCCTRL_WIN]; 5813 static const char *dec_fac[] = { 5814 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 5815 "0.9375" 5816 }; 5817 5818 rc = sysctl_wire_old_buffer(req, 0); 5819 if (rc != 0) 5820 return (rc); 5821 5822 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5823 if (sb == NULL) 5824 return (ENOMEM); 5825 5826 t4_read_cong_tbl(sc, incr); 5827 5828 for (i = 0; i < NCCTRL_WIN; ++i) { 5829 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 5830 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 5831 incr[5][i], incr[6][i], incr[7][i]); 5832 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 5833 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 5834 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 5835 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 5836 } 5837 5838 rc = sbuf_finish(sb); 5839 sbuf_delete(sb); 5840 5841 return (rc); 5842 } 5843 5844 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 5845 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 5846 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 5847 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 5848 }; 5849 5850 static int 5851 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 5852 { 5853 struct adapter *sc = arg1; 5854 struct sbuf *sb; 5855 int rc, i, n, qid = arg2; 5856 uint32_t *buf, *p; 5857 char *qtype; 5858 u_int cim_num_obq = sc->chip_params->cim_num_obq; 5859 5860 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 5861 ("%s: bad qid %d\n", __func__, qid)); 5862 5863 if (qid < CIM_NUM_IBQ) { 5864 /* inbound queue */ 5865 qtype = "IBQ"; 5866 n = 4 * CIM_IBQ_SIZE; 5867 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5868 rc = t4_read_cim_ibq(sc, qid, buf, n); 5869 } else { 5870 /* outbound queue */ 5871 qtype = "OBQ"; 5872 qid -= CIM_NUM_IBQ; 5873 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 5874 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5875 rc = t4_read_cim_obq(sc, qid, buf, n); 5876 } 5877 5878 if (rc < 0) { 5879 rc = -rc; 5880 goto done; 5881 } 5882 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 5883 5884 rc = sysctl_wire_old_buffer(req, 0); 5885 if (rc != 0) 5886 goto done; 5887 5888 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 5889 if (sb == NULL) { 5890 rc = ENOMEM; 5891 goto done; 5892 } 5893 5894 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 5895 for (i = 0, p = buf; i < n; i += 16, p += 4) 5896 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 5897 p[2], p[3]); 5898 5899 rc = sbuf_finish(sb); 5900 sbuf_delete(sb); 5901 done: 5902 free(buf, M_CXGBE); 5903 return (rc); 5904 } 5905 5906 static int 5907 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 5908 { 5909 struct adapter *sc = arg1; 5910 u_int cfg; 5911 struct sbuf *sb; 5912 uint32_t *buf, *p; 5913 int rc; 5914 5915 MPASS(chip_id(sc) <= CHELSIO_T5); 5916 5917 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 5918 if (rc != 0) 5919 return (rc); 5920 5921 rc = sysctl_wire_old_buffer(req, 0); 5922 if (rc != 0) 5923 return (rc); 5924 5925 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5926 if (sb == NULL) 5927 return (ENOMEM); 5928 5929 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 5930 M_ZERO | M_WAITOK); 5931 5932 rc = -t4_cim_read_la(sc, buf, NULL); 5933 if (rc != 0) 5934 goto done; 5935 5936 sbuf_printf(sb, "Status Data PC%s", 5937 cfg & F_UPDBGLACAPTPCONLY ? "" : 5938 " LS0Stat LS0Addr LS0Data"); 5939 5940 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 5941 if (cfg & F_UPDBGLACAPTPCONLY) { 5942 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 5943 p[6], p[7]); 5944 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 5945 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 5946 p[4] & 0xff, p[5] >> 8); 5947 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 5948 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 5949 p[1] & 0xf, p[2] >> 4); 5950 } else { 5951 sbuf_printf(sb, 5952 "\n %02x %x%07x %x%07x %08x %08x " 5953 "%08x%08x%08x%08x", 5954 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 5955 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 5956 p[6], p[7]); 5957 } 5958 } 5959 5960 rc = sbuf_finish(sb); 5961 sbuf_delete(sb); 5962 done: 5963 free(buf, M_CXGBE); 5964 return (rc); 5965 } 5966 5967 static int 5968 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 5969 { 5970 struct adapter *sc = arg1; 5971 u_int cfg; 5972 struct sbuf *sb; 5973 uint32_t *buf, *p; 5974 int rc; 5975 5976 MPASS(chip_id(sc) > CHELSIO_T5); 5977 5978 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 5979 if (rc != 0) 5980 return (rc); 5981 5982 rc = sysctl_wire_old_buffer(req, 0); 5983 if (rc != 0) 5984 return (rc); 5985 5986 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5987 if (sb == NULL) 5988 return (ENOMEM); 5989 5990 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 5991 M_ZERO | M_WAITOK); 5992 5993 rc = -t4_cim_read_la(sc, buf, NULL); 5994 if (rc != 0) 5995 goto done; 5996 5997 sbuf_printf(sb, "Status Inst Data PC%s", 5998 cfg & F_UPDBGLACAPTPCONLY ? "" : 5999 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 6000 6001 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 6002 if (cfg & F_UPDBGLACAPTPCONLY) { 6003 sbuf_printf(sb, "\n %02x %08x %08x %08x", 6004 p[3] & 0xff, p[2], p[1], p[0]); 6005 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 6006 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 6007 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 6008 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 6009 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 6010 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 6011 p[6] >> 16); 6012 } else { 6013 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 6014 "%08x %08x %08x %08x %08x %08x", 6015 (p[9] >> 16) & 0xff, 6016 p[9] & 0xffff, p[8] >> 16, 6017 p[8] & 0xffff, p[7] >> 16, 6018 p[7] & 0xffff, p[6] >> 16, 6019 p[2], p[1], p[0], p[5], p[4], p[3]); 6020 } 6021 } 6022 6023 rc = sbuf_finish(sb); 6024 sbuf_delete(sb); 6025 done: 6026 free(buf, M_CXGBE); 6027 return (rc); 6028 } 6029 6030 static int 6031 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 6032 { 6033 struct adapter *sc = arg1; 6034 u_int i; 6035 struct sbuf *sb; 6036 uint32_t *buf, *p; 6037 int rc; 6038 6039 rc = sysctl_wire_old_buffer(req, 0); 6040 if (rc != 0) 6041 return (rc); 6042 6043 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6044 if (sb == NULL) 6045 return (ENOMEM); 6046 6047 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 6048 M_ZERO | M_WAITOK); 6049 6050 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 6051 p = buf; 6052 6053 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6054 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 6055 p[1], p[0]); 6056 } 6057 6058 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 6059 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6060 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 6061 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 6062 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 6063 (p[1] >> 2) | ((p[2] & 3) << 30), 6064 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 6065 p[0] & 1); 6066 } 6067 6068 rc = sbuf_finish(sb); 6069 sbuf_delete(sb); 6070 free(buf, M_CXGBE); 6071 return (rc); 6072 } 6073 6074 static int 6075 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 6076 { 6077 struct adapter *sc = arg1; 6078 u_int i; 6079 struct sbuf *sb; 6080 uint32_t *buf, *p; 6081 int rc; 6082 6083 rc = sysctl_wire_old_buffer(req, 0); 6084 if (rc != 0) 6085 return (rc); 6086 6087 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6088 if (sb == NULL) 6089 return (ENOMEM); 6090 6091 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 6092 M_ZERO | M_WAITOK); 6093 6094 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 6095 p = buf; 6096 6097 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 6098 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6099 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 6100 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 6101 p[4], p[3], p[2], p[1], p[0]); 6102 } 6103 6104 sbuf_printf(sb, "\n\nCntl ID Data"); 6105 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6106 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 6107 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 6108 } 6109 6110 rc = sbuf_finish(sb); 6111 sbuf_delete(sb); 6112 free(buf, M_CXGBE); 6113 return (rc); 6114 } 6115 6116 static int 6117 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 6118 { 6119 struct adapter *sc = arg1; 6120 struct sbuf *sb; 6121 int rc, i; 6122 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6123 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6124 uint16_t thres[CIM_NUM_IBQ]; 6125 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 6126 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 6127 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 6128 6129 cim_num_obq = sc->chip_params->cim_num_obq; 6130 if (is_t4(sc)) { 6131 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 6132 obq_rdaddr = A_UP_OBQ_0_REALADDR; 6133 } else { 6134 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 6135 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 6136 } 6137 nq = CIM_NUM_IBQ + cim_num_obq; 6138 6139 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 6140 if (rc == 0) 6141 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 6142 if (rc != 0) 6143 return (rc); 6144 6145 t4_read_cimq_cfg(sc, base, size, thres); 6146 6147 rc = sysctl_wire_old_buffer(req, 0); 6148 if (rc != 0) 6149 return (rc); 6150 6151 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6152 if (sb == NULL) 6153 return (ENOMEM); 6154 6155 sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 6156 6157 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 6158 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 6159 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 6160 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6161 G_QUEREMFLITS(p[2]) * 16); 6162 for ( ; i < nq; i++, p += 4, wr += 2) 6163 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 6164 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 6165 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6166 G_QUEREMFLITS(p[2]) * 16); 6167 6168 rc = sbuf_finish(sb); 6169 sbuf_delete(sb); 6170 6171 return (rc); 6172 } 6173 6174 static int 6175 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 6176 { 6177 struct adapter *sc = arg1; 6178 struct sbuf *sb; 6179 int rc; 6180 struct tp_cpl_stats stats; 6181 6182 rc = sysctl_wire_old_buffer(req, 0); 6183 if (rc != 0) 6184 return (rc); 6185 6186 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6187 if (sb == NULL) 6188 return (ENOMEM); 6189 6190 mtx_lock(&sc->reg_lock); 6191 t4_tp_get_cpl_stats(sc, &stats); 6192 mtx_unlock(&sc->reg_lock); 6193 6194 if (sc->chip_params->nchan > 2) { 6195 sbuf_printf(sb, " channel 0 channel 1" 6196 " channel 2 channel 3"); 6197 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 6198 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 6199 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 6200 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 6201 } else { 6202 sbuf_printf(sb, " channel 0 channel 1"); 6203 sbuf_printf(sb, "\nCPL requests: %10u %10u", 6204 stats.req[0], stats.req[1]); 6205 sbuf_printf(sb, "\nCPL responses: %10u %10u", 6206 stats.rsp[0], stats.rsp[1]); 6207 } 6208 6209 rc = sbuf_finish(sb); 6210 sbuf_delete(sb); 6211 6212 return (rc); 6213 } 6214 6215 static int 6216 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 6217 { 6218 struct adapter *sc = arg1; 6219 struct sbuf *sb; 6220 int rc; 6221 struct tp_usm_stats stats; 6222 6223 rc = sysctl_wire_old_buffer(req, 0); 6224 if (rc != 0) 6225 return(rc); 6226 6227 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6228 if (sb == NULL) 6229 return (ENOMEM); 6230 6231 t4_get_usm_stats(sc, &stats); 6232 6233 sbuf_printf(sb, "Frames: %u\n", stats.frames); 6234 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 6235 sbuf_printf(sb, "Drops: %u", stats.drops); 6236 6237 rc = sbuf_finish(sb); 6238 sbuf_delete(sb); 6239 6240 return (rc); 6241 } 6242 6243 static const char * const devlog_level_strings[] = { 6244 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 6245 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 6246 [FW_DEVLOG_LEVEL_ERR] = "ERR", 6247 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 6248 [FW_DEVLOG_LEVEL_INFO] = "INFO", 6249 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 6250 }; 6251 6252 static const char * const devlog_facility_strings[] = { 6253 [FW_DEVLOG_FACILITY_CORE] = "CORE", 6254 [FW_DEVLOG_FACILITY_CF] = "CF", 6255 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 6256 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 6257 [FW_DEVLOG_FACILITY_RES] = "RES", 6258 [FW_DEVLOG_FACILITY_HW] = "HW", 6259 [FW_DEVLOG_FACILITY_FLR] = "FLR", 6260 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 6261 [FW_DEVLOG_FACILITY_PHY] = "PHY", 6262 [FW_DEVLOG_FACILITY_MAC] = "MAC", 6263 [FW_DEVLOG_FACILITY_PORT] = "PORT", 6264 [FW_DEVLOG_FACILITY_VI] = "VI", 6265 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 6266 [FW_DEVLOG_FACILITY_ACL] = "ACL", 6267 [FW_DEVLOG_FACILITY_TM] = "TM", 6268 [FW_DEVLOG_FACILITY_QFC] = "QFC", 6269 [FW_DEVLOG_FACILITY_DCB] = "DCB", 6270 [FW_DEVLOG_FACILITY_ETH] = "ETH", 6271 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 6272 [FW_DEVLOG_FACILITY_RI] = "RI", 6273 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 6274 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 6275 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 6276 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 6277 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 6278 }; 6279 6280 static int 6281 sysctl_devlog(SYSCTL_HANDLER_ARGS) 6282 { 6283 struct adapter *sc = arg1; 6284 struct devlog_params *dparams = &sc->params.devlog; 6285 struct fw_devlog_e *buf, *e; 6286 int i, j, rc, nentries, first = 0; 6287 struct sbuf *sb; 6288 uint64_t ftstamp = UINT64_MAX; 6289 6290 if (dparams->addr == 0) 6291 return (ENXIO); 6292 6293 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 6294 if (buf == NULL) 6295 return (ENOMEM); 6296 6297 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 6298 if (rc != 0) 6299 goto done; 6300 6301 nentries = dparams->size / sizeof(struct fw_devlog_e); 6302 for (i = 0; i < nentries; i++) { 6303 e = &buf[i]; 6304 6305 if (e->timestamp == 0) 6306 break; /* end */ 6307 6308 e->timestamp = be64toh(e->timestamp); 6309 e->seqno = be32toh(e->seqno); 6310 for (j = 0; j < 8; j++) 6311 e->params[j] = be32toh(e->params[j]); 6312 6313 if (e->timestamp < ftstamp) { 6314 ftstamp = e->timestamp; 6315 first = i; 6316 } 6317 } 6318 6319 if (buf[first].timestamp == 0) 6320 goto done; /* nothing in the log */ 6321 6322 rc = sysctl_wire_old_buffer(req, 0); 6323 if (rc != 0) 6324 goto done; 6325 6326 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6327 if (sb == NULL) { 6328 rc = ENOMEM; 6329 goto done; 6330 } 6331 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 6332 "Seq#", "Tstamp", "Level", "Facility", "Message"); 6333 6334 i = first; 6335 do { 6336 e = &buf[i]; 6337 if (e->timestamp == 0) 6338 break; /* end */ 6339 6340 sbuf_printf(sb, "%10d %15ju %8s %8s ", 6341 e->seqno, e->timestamp, 6342 (e->level < nitems(devlog_level_strings) ? 6343 devlog_level_strings[e->level] : "UNKNOWN"), 6344 (e->facility < nitems(devlog_facility_strings) ? 6345 devlog_facility_strings[e->facility] : "UNKNOWN")); 6346 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 6347 e->params[2], e->params[3], e->params[4], 6348 e->params[5], e->params[6], e->params[7]); 6349 6350 if (++i == nentries) 6351 i = 0; 6352 } while (i != first); 6353 6354 rc = sbuf_finish(sb); 6355 sbuf_delete(sb); 6356 done: 6357 free(buf, M_CXGBE); 6358 return (rc); 6359 } 6360 6361 static int 6362 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 6363 { 6364 struct adapter *sc = arg1; 6365 struct sbuf *sb; 6366 int rc; 6367 struct tp_fcoe_stats stats[MAX_NCHAN]; 6368 int i, nchan = sc->chip_params->nchan; 6369 6370 rc = sysctl_wire_old_buffer(req, 0); 6371 if (rc != 0) 6372 return (rc); 6373 6374 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6375 if (sb == NULL) 6376 return (ENOMEM); 6377 6378 for (i = 0; i < nchan; i++) 6379 t4_get_fcoe_stats(sc, i, &stats[i]); 6380 6381 if (nchan > 2) { 6382 sbuf_printf(sb, " channel 0 channel 1" 6383 " channel 2 channel 3"); 6384 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 6385 stats[0].octets_ddp, stats[1].octets_ddp, 6386 stats[2].octets_ddp, stats[3].octets_ddp); 6387 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 6388 stats[0].frames_ddp, stats[1].frames_ddp, 6389 stats[2].frames_ddp, stats[3].frames_ddp); 6390 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 6391 stats[0].frames_drop, stats[1].frames_drop, 6392 stats[2].frames_drop, stats[3].frames_drop); 6393 } else { 6394 sbuf_printf(sb, " channel 0 channel 1"); 6395 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 6396 stats[0].octets_ddp, stats[1].octets_ddp); 6397 sbuf_printf(sb, "\nframesDDP: %16u %16u", 6398 stats[0].frames_ddp, stats[1].frames_ddp); 6399 sbuf_printf(sb, "\nframesDrop: %16u %16u", 6400 stats[0].frames_drop, stats[1].frames_drop); 6401 } 6402 6403 rc = sbuf_finish(sb); 6404 sbuf_delete(sb); 6405 6406 return (rc); 6407 } 6408 6409 static int 6410 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 6411 { 6412 struct adapter *sc = arg1; 6413 struct sbuf *sb; 6414 int rc, i; 6415 unsigned int map, kbps, ipg, mode; 6416 unsigned int pace_tab[NTX_SCHED]; 6417 6418 rc = sysctl_wire_old_buffer(req, 0); 6419 if (rc != 0) 6420 return (rc); 6421 6422 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6423 if (sb == NULL) 6424 return (ENOMEM); 6425 6426 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 6427 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 6428 t4_read_pace_tbl(sc, pace_tab); 6429 6430 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 6431 "Class IPG (0.1 ns) Flow IPG (us)"); 6432 6433 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 6434 t4_get_tx_sched(sc, i, &kbps, &ipg); 6435 sbuf_printf(sb, "\n %u %-5s %u ", i, 6436 (mode & (1 << i)) ? "flow" : "class", map & 3); 6437 if (kbps) 6438 sbuf_printf(sb, "%9u ", kbps); 6439 else 6440 sbuf_printf(sb, " disabled "); 6441 6442 if (ipg) 6443 sbuf_printf(sb, "%13u ", ipg); 6444 else 6445 sbuf_printf(sb, " disabled "); 6446 6447 if (pace_tab[i]) 6448 sbuf_printf(sb, "%10u", pace_tab[i]); 6449 else 6450 sbuf_printf(sb, " disabled"); 6451 } 6452 6453 rc = sbuf_finish(sb); 6454 sbuf_delete(sb); 6455 6456 return (rc); 6457 } 6458 6459 static int 6460 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 6461 { 6462 struct adapter *sc = arg1; 6463 struct sbuf *sb; 6464 int rc, i, j; 6465 uint64_t *p0, *p1; 6466 struct lb_port_stats s[2]; 6467 static const char *stat_name[] = { 6468 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 6469 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 6470 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 6471 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 6472 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 6473 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 6474 "BG2FramesTrunc:", "BG3FramesTrunc:" 6475 }; 6476 6477 rc = sysctl_wire_old_buffer(req, 0); 6478 if (rc != 0) 6479 return (rc); 6480 6481 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6482 if (sb == NULL) 6483 return (ENOMEM); 6484 6485 memset(s, 0, sizeof(s)); 6486 6487 for (i = 0; i < sc->chip_params->nchan; i += 2) { 6488 t4_get_lb_stats(sc, i, &s[0]); 6489 t4_get_lb_stats(sc, i + 1, &s[1]); 6490 6491 p0 = &s[0].octets; 6492 p1 = &s[1].octets; 6493 sbuf_printf(sb, "%s Loopback %u" 6494 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 6495 6496 for (j = 0; j < nitems(stat_name); j++) 6497 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 6498 *p0++, *p1++); 6499 } 6500 6501 rc = sbuf_finish(sb); 6502 sbuf_delete(sb); 6503 6504 return (rc); 6505 } 6506 6507 static int 6508 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 6509 { 6510 int rc = 0; 6511 struct port_info *pi = arg1; 6512 struct sbuf *sb; 6513 6514 rc = sysctl_wire_old_buffer(req, 0); 6515 if (rc != 0) 6516 return(rc); 6517 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 6518 if (sb == NULL) 6519 return (ENOMEM); 6520 6521 if (pi->linkdnrc < 0) 6522 sbuf_printf(sb, "n/a"); 6523 else 6524 sbuf_printf(sb, "%s", t4_link_down_rc_str(pi->linkdnrc)); 6525 6526 rc = sbuf_finish(sb); 6527 sbuf_delete(sb); 6528 6529 return (rc); 6530 } 6531 6532 struct mem_desc { 6533 unsigned int base; 6534 unsigned int limit; 6535 unsigned int idx; 6536 }; 6537 6538 static int 6539 mem_desc_cmp(const void *a, const void *b) 6540 { 6541 return ((const struct mem_desc *)a)->base - 6542 ((const struct mem_desc *)b)->base; 6543 } 6544 6545 static void 6546 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 6547 unsigned int to) 6548 { 6549 unsigned int size; 6550 6551 if (from == to) 6552 return; 6553 6554 size = to - from + 1; 6555 if (size == 0) 6556 return; 6557 6558 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 6559 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 6560 } 6561 6562 static int 6563 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 6564 { 6565 struct adapter *sc = arg1; 6566 struct sbuf *sb; 6567 int rc, i, n; 6568 uint32_t lo, hi, used, alloc; 6569 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 6570 static const char *region[] = { 6571 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 6572 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 6573 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 6574 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 6575 "RQUDP region:", "PBL region:", "TXPBL region:", 6576 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 6577 "On-chip queues:" 6578 }; 6579 struct mem_desc avail[4]; 6580 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 6581 struct mem_desc *md = mem; 6582 6583 rc = sysctl_wire_old_buffer(req, 0); 6584 if (rc != 0) 6585 return (rc); 6586 6587 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6588 if (sb == NULL) 6589 return (ENOMEM); 6590 6591 for (i = 0; i < nitems(mem); i++) { 6592 mem[i].limit = 0; 6593 mem[i].idx = i; 6594 } 6595 6596 /* Find and sort the populated memory ranges */ 6597 i = 0; 6598 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 6599 if (lo & F_EDRAM0_ENABLE) { 6600 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 6601 avail[i].base = G_EDRAM0_BASE(hi) << 20; 6602 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 6603 avail[i].idx = 0; 6604 i++; 6605 } 6606 if (lo & F_EDRAM1_ENABLE) { 6607 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 6608 avail[i].base = G_EDRAM1_BASE(hi) << 20; 6609 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 6610 avail[i].idx = 1; 6611 i++; 6612 } 6613 if (lo & F_EXT_MEM_ENABLE) { 6614 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 6615 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 6616 avail[i].limit = avail[i].base + 6617 (G_EXT_MEM_SIZE(hi) << 20); 6618 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 6619 i++; 6620 } 6621 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 6622 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 6623 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 6624 avail[i].limit = avail[i].base + 6625 (G_EXT_MEM1_SIZE(hi) << 20); 6626 avail[i].idx = 4; 6627 i++; 6628 } 6629 if (!i) /* no memory available */ 6630 return 0; 6631 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 6632 6633 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 6634 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 6635 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 6636 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 6637 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 6638 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 6639 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 6640 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 6641 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 6642 6643 /* the next few have explicit upper bounds */ 6644 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 6645 md->limit = md->base - 1 + 6646 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 6647 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 6648 md++; 6649 6650 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 6651 md->limit = md->base - 1 + 6652 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 6653 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 6654 md++; 6655 6656 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 6657 if (chip_id(sc) <= CHELSIO_T5) 6658 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 6659 else 6660 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 6661 md->limit = 0; 6662 } else { 6663 md->base = 0; 6664 md->idx = nitems(region); /* hide it */ 6665 } 6666 md++; 6667 6668 #define ulp_region(reg) \ 6669 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 6670 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 6671 6672 ulp_region(RX_ISCSI); 6673 ulp_region(RX_TDDP); 6674 ulp_region(TX_TPT); 6675 ulp_region(RX_STAG); 6676 ulp_region(RX_RQ); 6677 ulp_region(RX_RQUDP); 6678 ulp_region(RX_PBL); 6679 ulp_region(TX_PBL); 6680 #undef ulp_region 6681 6682 md->base = 0; 6683 md->idx = nitems(region); 6684 if (!is_t4(sc)) { 6685 uint32_t size = 0; 6686 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 6687 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 6688 6689 if (is_t5(sc)) { 6690 if (sge_ctrl & F_VFIFO_ENABLE) 6691 size = G_DBVFIFO_SIZE(fifo_size); 6692 } else 6693 size = G_T6_DBVFIFO_SIZE(fifo_size); 6694 6695 if (size) { 6696 md->base = G_BASEADDR(t4_read_reg(sc, 6697 A_SGE_DBVFIFO_BADDR)); 6698 md->limit = md->base + (size << 2) - 1; 6699 } 6700 } 6701 md++; 6702 6703 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 6704 md->limit = 0; 6705 md++; 6706 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 6707 md->limit = 0; 6708 md++; 6709 6710 md->base = sc->vres.ocq.start; 6711 if (sc->vres.ocq.size) 6712 md->limit = md->base + sc->vres.ocq.size - 1; 6713 else 6714 md->idx = nitems(region); /* hide it */ 6715 md++; 6716 6717 /* add any address-space holes, there can be up to 3 */ 6718 for (n = 0; n < i - 1; n++) 6719 if (avail[n].limit < avail[n + 1].base) 6720 (md++)->base = avail[n].limit; 6721 if (avail[n].limit) 6722 (md++)->base = avail[n].limit; 6723 6724 n = md - mem; 6725 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 6726 6727 for (lo = 0; lo < i; lo++) 6728 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 6729 avail[lo].limit - 1); 6730 6731 sbuf_printf(sb, "\n"); 6732 for (i = 0; i < n; i++) { 6733 if (mem[i].idx >= nitems(region)) 6734 continue; /* skip holes */ 6735 if (!mem[i].limit) 6736 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 6737 mem_region_show(sb, region[mem[i].idx], mem[i].base, 6738 mem[i].limit); 6739 } 6740 6741 sbuf_printf(sb, "\n"); 6742 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 6743 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 6744 mem_region_show(sb, "uP RAM:", lo, hi); 6745 6746 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 6747 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 6748 mem_region_show(sb, "uP Extmem2:", lo, hi); 6749 6750 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 6751 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 6752 G_PMRXMAXPAGE(lo), 6753 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 6754 (lo & F_PMRXNUMCHN) ? 2 : 1); 6755 6756 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 6757 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 6758 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 6759 G_PMTXMAXPAGE(lo), 6760 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 6761 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 6762 sbuf_printf(sb, "%u p-structs\n", 6763 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 6764 6765 for (i = 0; i < 4; i++) { 6766 if (chip_id(sc) > CHELSIO_T5) 6767 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 6768 else 6769 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 6770 if (is_t5(sc)) { 6771 used = G_T5_USED(lo); 6772 alloc = G_T5_ALLOC(lo); 6773 } else { 6774 used = G_USED(lo); 6775 alloc = G_ALLOC(lo); 6776 } 6777 /* For T6 these are MAC buffer groups */ 6778 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 6779 i, used, alloc); 6780 } 6781 for (i = 0; i < sc->chip_params->nchan; i++) { 6782 if (chip_id(sc) > CHELSIO_T5) 6783 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 6784 else 6785 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 6786 if (is_t5(sc)) { 6787 used = G_T5_USED(lo); 6788 alloc = G_T5_ALLOC(lo); 6789 } else { 6790 used = G_USED(lo); 6791 alloc = G_ALLOC(lo); 6792 } 6793 /* For T6 these are MAC buffer groups */ 6794 sbuf_printf(sb, 6795 "\nLoopback %d using %u pages out of %u allocated", 6796 i, used, alloc); 6797 } 6798 6799 rc = sbuf_finish(sb); 6800 sbuf_delete(sb); 6801 6802 return (rc); 6803 } 6804 6805 static inline void 6806 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 6807 { 6808 *mask = x | y; 6809 y = htobe64(y); 6810 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 6811 } 6812 6813 static int 6814 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 6815 { 6816 struct adapter *sc = arg1; 6817 struct sbuf *sb; 6818 int rc, i; 6819 6820 MPASS(chip_id(sc) <= CHELSIO_T5); 6821 6822 rc = sysctl_wire_old_buffer(req, 0); 6823 if (rc != 0) 6824 return (rc); 6825 6826 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6827 if (sb == NULL) 6828 return (ENOMEM); 6829 6830 sbuf_printf(sb, 6831 "Idx Ethernet address Mask Vld Ports PF" 6832 " VF Replication P0 P1 P2 P3 ML"); 6833 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 6834 uint64_t tcamx, tcamy, mask; 6835 uint32_t cls_lo, cls_hi; 6836 uint8_t addr[ETHER_ADDR_LEN]; 6837 6838 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 6839 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 6840 if (tcamx & tcamy) 6841 continue; 6842 tcamxy2valmask(tcamx, tcamy, addr, &mask); 6843 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 6844 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 6845 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 6846 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 6847 addr[3], addr[4], addr[5], (uintmax_t)mask, 6848 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 6849 G_PORTMAP(cls_hi), G_PF(cls_lo), 6850 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 6851 6852 if (cls_lo & F_REPLICATE) { 6853 struct fw_ldst_cmd ldst_cmd; 6854 6855 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 6856 ldst_cmd.op_to_addrspace = 6857 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 6858 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6859 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 6860 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 6861 ldst_cmd.u.mps.rplc.fid_idx = 6862 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 6863 V_FW_LDST_CMD_IDX(i)); 6864 6865 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 6866 "t4mps"); 6867 if (rc) 6868 break; 6869 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 6870 sizeof(ldst_cmd), &ldst_cmd); 6871 end_synchronized_op(sc, 0); 6872 6873 if (rc != 0) { 6874 sbuf_printf(sb, "%36d", rc); 6875 rc = 0; 6876 } else { 6877 sbuf_printf(sb, " %08x %08x %08x %08x", 6878 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 6879 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 6880 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 6881 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 6882 } 6883 } else 6884 sbuf_printf(sb, "%36s", ""); 6885 6886 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 6887 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 6888 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 6889 } 6890 6891 if (rc) 6892 (void) sbuf_finish(sb); 6893 else 6894 rc = sbuf_finish(sb); 6895 sbuf_delete(sb); 6896 6897 return (rc); 6898 } 6899 6900 static int 6901 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 6902 { 6903 struct adapter *sc = arg1; 6904 struct sbuf *sb; 6905 int rc, i; 6906 6907 MPASS(chip_id(sc) > CHELSIO_T5); 6908 6909 rc = sysctl_wire_old_buffer(req, 0); 6910 if (rc != 0) 6911 return (rc); 6912 6913 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6914 if (sb == NULL) 6915 return (ENOMEM); 6916 6917 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 6918 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 6919 " Replication" 6920 " P0 P1 P2 P3 ML\n"); 6921 6922 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 6923 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 6924 uint16_t ivlan; 6925 uint64_t tcamx, tcamy, val, mask; 6926 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 6927 uint8_t addr[ETHER_ADDR_LEN]; 6928 6929 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 6930 if (i < 256) 6931 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 6932 else 6933 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 6934 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 6935 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 6936 tcamy = G_DMACH(val) << 32; 6937 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 6938 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 6939 lookup_type = G_DATALKPTYPE(data2); 6940 port_num = G_DATAPORTNUM(data2); 6941 if (lookup_type && lookup_type != M_DATALKPTYPE) { 6942 /* Inner header VNI */ 6943 vniy = ((data2 & F_DATAVIDH2) << 23) | 6944 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 6945 dip_hit = data2 & F_DATADIPHIT; 6946 vlan_vld = 0; 6947 } else { 6948 vniy = 0; 6949 dip_hit = 0; 6950 vlan_vld = data2 & F_DATAVIDH2; 6951 ivlan = G_VIDL(val); 6952 } 6953 6954 ctl |= V_CTLXYBITSEL(1); 6955 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 6956 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 6957 tcamx = G_DMACH(val) << 32; 6958 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 6959 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 6960 if (lookup_type && lookup_type != M_DATALKPTYPE) { 6961 /* Inner header VNI mask */ 6962 vnix = ((data2 & F_DATAVIDH2) << 23) | 6963 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 6964 } else 6965 vnix = 0; 6966 6967 if (tcamx & tcamy) 6968 continue; 6969 tcamxy2valmask(tcamx, tcamy, addr, &mask); 6970 6971 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 6972 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 6973 6974 if (lookup_type && lookup_type != M_DATALKPTYPE) { 6975 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 6976 "%012jx %06x %06x - - %3c" 6977 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 6978 addr[1], addr[2], addr[3], addr[4], addr[5], 6979 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 6980 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 6981 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 6982 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 6983 } else { 6984 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 6985 "%012jx - - ", i, addr[0], addr[1], 6986 addr[2], addr[3], addr[4], addr[5], 6987 (uintmax_t)mask); 6988 6989 if (vlan_vld) 6990 sbuf_printf(sb, "%4u Y ", ivlan); 6991 else 6992 sbuf_printf(sb, " - N "); 6993 6994 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 6995 lookup_type ? 'I' : 'O', port_num, 6996 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 6997 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 6998 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 6999 } 7000 7001 7002 if (cls_lo & F_T6_REPLICATE) { 7003 struct fw_ldst_cmd ldst_cmd; 7004 7005 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7006 ldst_cmd.op_to_addrspace = 7007 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7008 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7009 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7010 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7011 ldst_cmd.u.mps.rplc.fid_idx = 7012 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7013 V_FW_LDST_CMD_IDX(i)); 7014 7015 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7016 "t6mps"); 7017 if (rc) 7018 break; 7019 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7020 sizeof(ldst_cmd), &ldst_cmd); 7021 end_synchronized_op(sc, 0); 7022 7023 if (rc != 0) { 7024 sbuf_printf(sb, "%72d", rc); 7025 rc = 0; 7026 } else { 7027 sbuf_printf(sb, " %08x %08x %08x %08x" 7028 " %08x %08x %08x %08x", 7029 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 7030 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 7031 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 7032 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 7033 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7034 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7035 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7036 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7037 } 7038 } else 7039 sbuf_printf(sb, "%72s", ""); 7040 7041 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 7042 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 7043 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 7044 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 7045 } 7046 7047 if (rc) 7048 (void) sbuf_finish(sb); 7049 else 7050 rc = sbuf_finish(sb); 7051 sbuf_delete(sb); 7052 7053 return (rc); 7054 } 7055 7056 static int 7057 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 7058 { 7059 struct adapter *sc = arg1; 7060 struct sbuf *sb; 7061 int rc; 7062 uint16_t mtus[NMTUS]; 7063 7064 rc = sysctl_wire_old_buffer(req, 0); 7065 if (rc != 0) 7066 return (rc); 7067 7068 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7069 if (sb == NULL) 7070 return (ENOMEM); 7071 7072 t4_read_mtu_tbl(sc, mtus, NULL); 7073 7074 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 7075 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 7076 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 7077 mtus[14], mtus[15]); 7078 7079 rc = sbuf_finish(sb); 7080 sbuf_delete(sb); 7081 7082 return (rc); 7083 } 7084 7085 static int 7086 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 7087 { 7088 struct adapter *sc = arg1; 7089 struct sbuf *sb; 7090 int rc, i; 7091 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 7092 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 7093 static const char *tx_stats[MAX_PM_NSTATS] = { 7094 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 7095 "Tx FIFO wait", NULL, "Tx latency" 7096 }; 7097 static const char *rx_stats[MAX_PM_NSTATS] = { 7098 "Read:", "Write bypass:", "Write mem:", "Flush:", 7099 " Rx FIFO wait", NULL, "Rx latency" 7100 }; 7101 7102 rc = sysctl_wire_old_buffer(req, 0); 7103 if (rc != 0) 7104 return (rc); 7105 7106 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7107 if (sb == NULL) 7108 return (ENOMEM); 7109 7110 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 7111 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 7112 7113 sbuf_printf(sb, " Tx pcmds Tx bytes"); 7114 for (i = 0; i < 4; i++) { 7115 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7116 tx_cyc[i]); 7117 } 7118 7119 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 7120 for (i = 0; i < 4; i++) { 7121 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7122 rx_cyc[i]); 7123 } 7124 7125 if (chip_id(sc) > CHELSIO_T5) { 7126 sbuf_printf(sb, 7127 "\n Total wait Total occupancy"); 7128 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7129 tx_cyc[i]); 7130 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7131 rx_cyc[i]); 7132 7133 i += 2; 7134 MPASS(i < nitems(tx_stats)); 7135 7136 sbuf_printf(sb, 7137 "\n Reads Total wait"); 7138 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7139 tx_cyc[i]); 7140 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7141 rx_cyc[i]); 7142 } 7143 7144 rc = sbuf_finish(sb); 7145 sbuf_delete(sb); 7146 7147 return (rc); 7148 } 7149 7150 static int 7151 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 7152 { 7153 struct adapter *sc = arg1; 7154 struct sbuf *sb; 7155 int rc; 7156 struct tp_rdma_stats stats; 7157 7158 rc = sysctl_wire_old_buffer(req, 0); 7159 if (rc != 0) 7160 return (rc); 7161 7162 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7163 if (sb == NULL) 7164 return (ENOMEM); 7165 7166 mtx_lock(&sc->reg_lock); 7167 t4_tp_get_rdma_stats(sc, &stats); 7168 mtx_unlock(&sc->reg_lock); 7169 7170 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 7171 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 7172 7173 rc = sbuf_finish(sb); 7174 sbuf_delete(sb); 7175 7176 return (rc); 7177 } 7178 7179 static int 7180 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 7181 { 7182 struct adapter *sc = arg1; 7183 struct sbuf *sb; 7184 int rc; 7185 struct tp_tcp_stats v4, v6; 7186 7187 rc = sysctl_wire_old_buffer(req, 0); 7188 if (rc != 0) 7189 return (rc); 7190 7191 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7192 if (sb == NULL) 7193 return (ENOMEM); 7194 7195 mtx_lock(&sc->reg_lock); 7196 t4_tp_get_tcp_stats(sc, &v4, &v6); 7197 mtx_unlock(&sc->reg_lock); 7198 7199 sbuf_printf(sb, 7200 " IP IPv6\n"); 7201 sbuf_printf(sb, "OutRsts: %20u %20u\n", 7202 v4.tcp_out_rsts, v6.tcp_out_rsts); 7203 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 7204 v4.tcp_in_segs, v6.tcp_in_segs); 7205 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 7206 v4.tcp_out_segs, v6.tcp_out_segs); 7207 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 7208 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 7209 7210 rc = sbuf_finish(sb); 7211 sbuf_delete(sb); 7212 7213 return (rc); 7214 } 7215 7216 static int 7217 sysctl_tids(SYSCTL_HANDLER_ARGS) 7218 { 7219 struct adapter *sc = arg1; 7220 struct sbuf *sb; 7221 int rc; 7222 struct tid_info *t = &sc->tids; 7223 7224 rc = sysctl_wire_old_buffer(req, 0); 7225 if (rc != 0) 7226 return (rc); 7227 7228 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7229 if (sb == NULL) 7230 return (ENOMEM); 7231 7232 if (t->natids) { 7233 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 7234 t->atids_in_use); 7235 } 7236 7237 if (t->ntids) { 7238 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7239 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 7240 7241 if (b) { 7242 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1, 7243 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4, 7244 t->ntids - 1); 7245 } else { 7246 sbuf_printf(sb, "TID range: %u-%u", 7247 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4, 7248 t->ntids - 1); 7249 } 7250 } else 7251 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1); 7252 sbuf_printf(sb, ", in use: %u\n", 7253 atomic_load_acq_int(&t->tids_in_use)); 7254 } 7255 7256 if (t->nstids) { 7257 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 7258 t->stid_base + t->nstids - 1, t->stids_in_use); 7259 } 7260 7261 if (t->nftids) { 7262 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 7263 t->ftid_base + t->nftids - 1); 7264 } 7265 7266 if (t->netids) { 7267 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 7268 t->etid_base + t->netids - 1); 7269 } 7270 7271 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 7272 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 7273 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 7274 7275 rc = sbuf_finish(sb); 7276 sbuf_delete(sb); 7277 7278 return (rc); 7279 } 7280 7281 static int 7282 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 7283 { 7284 struct adapter *sc = arg1; 7285 struct sbuf *sb; 7286 int rc; 7287 struct tp_err_stats stats; 7288 7289 rc = sysctl_wire_old_buffer(req, 0); 7290 if (rc != 0) 7291 return (rc); 7292 7293 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7294 if (sb == NULL) 7295 return (ENOMEM); 7296 7297 mtx_lock(&sc->reg_lock); 7298 t4_tp_get_err_stats(sc, &stats); 7299 mtx_unlock(&sc->reg_lock); 7300 7301 if (sc->chip_params->nchan > 2) { 7302 sbuf_printf(sb, " channel 0 channel 1" 7303 " channel 2 channel 3\n"); 7304 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 7305 stats.mac_in_errs[0], stats.mac_in_errs[1], 7306 stats.mac_in_errs[2], stats.mac_in_errs[3]); 7307 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 7308 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 7309 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 7310 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 7311 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 7312 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 7313 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 7314 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 7315 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 7316 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 7317 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 7318 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 7319 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 7320 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 7321 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 7322 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 7323 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 7324 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 7325 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 7326 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 7327 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 7328 } else { 7329 sbuf_printf(sb, " channel 0 channel 1\n"); 7330 sbuf_printf(sb, "macInErrs: %10u %10u\n", 7331 stats.mac_in_errs[0], stats.mac_in_errs[1]); 7332 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 7333 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 7334 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 7335 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 7336 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 7337 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 7338 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 7339 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 7340 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 7341 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 7342 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 7343 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 7344 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 7345 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 7346 } 7347 7348 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 7349 stats.ofld_no_neigh, stats.ofld_cong_defer); 7350 7351 rc = sbuf_finish(sb); 7352 sbuf_delete(sb); 7353 7354 return (rc); 7355 } 7356 7357 static int 7358 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 7359 { 7360 struct adapter *sc = arg1; 7361 struct tp_params *tpp = &sc->params.tp; 7362 u_int mask; 7363 int rc; 7364 7365 mask = tpp->la_mask >> 16; 7366 rc = sysctl_handle_int(oidp, &mask, 0, req); 7367 if (rc != 0 || req->newptr == NULL) 7368 return (rc); 7369 if (mask > 0xffff) 7370 return (EINVAL); 7371 tpp->la_mask = mask << 16; 7372 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 7373 7374 return (0); 7375 } 7376 7377 struct field_desc { 7378 const char *name; 7379 u_int start; 7380 u_int width; 7381 }; 7382 7383 static void 7384 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 7385 { 7386 char buf[32]; 7387 int line_size = 0; 7388 7389 while (f->name) { 7390 uint64_t mask = (1ULL << f->width) - 1; 7391 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 7392 ((uintmax_t)v >> f->start) & mask); 7393 7394 if (line_size + len >= 79) { 7395 line_size = 8; 7396 sbuf_printf(sb, "\n "); 7397 } 7398 sbuf_printf(sb, "%s ", buf); 7399 line_size += len + 1; 7400 f++; 7401 } 7402 sbuf_printf(sb, "\n"); 7403 } 7404 7405 static const struct field_desc tp_la0[] = { 7406 { "RcfOpCodeOut", 60, 4 }, 7407 { "State", 56, 4 }, 7408 { "WcfState", 52, 4 }, 7409 { "RcfOpcSrcOut", 50, 2 }, 7410 { "CRxError", 49, 1 }, 7411 { "ERxError", 48, 1 }, 7412 { "SanityFailed", 47, 1 }, 7413 { "SpuriousMsg", 46, 1 }, 7414 { "FlushInputMsg", 45, 1 }, 7415 { "FlushInputCpl", 44, 1 }, 7416 { "RssUpBit", 43, 1 }, 7417 { "RssFilterHit", 42, 1 }, 7418 { "Tid", 32, 10 }, 7419 { "InitTcb", 31, 1 }, 7420 { "LineNumber", 24, 7 }, 7421 { "Emsg", 23, 1 }, 7422 { "EdataOut", 22, 1 }, 7423 { "Cmsg", 21, 1 }, 7424 { "CdataOut", 20, 1 }, 7425 { "EreadPdu", 19, 1 }, 7426 { "CreadPdu", 18, 1 }, 7427 { "TunnelPkt", 17, 1 }, 7428 { "RcfPeerFin", 16, 1 }, 7429 { "RcfReasonOut", 12, 4 }, 7430 { "TxCchannel", 10, 2 }, 7431 { "RcfTxChannel", 8, 2 }, 7432 { "RxEchannel", 6, 2 }, 7433 { "RcfRxChannel", 5, 1 }, 7434 { "RcfDataOutSrdy", 4, 1 }, 7435 { "RxDvld", 3, 1 }, 7436 { "RxOoDvld", 2, 1 }, 7437 { "RxCongestion", 1, 1 }, 7438 { "TxCongestion", 0, 1 }, 7439 { NULL } 7440 }; 7441 7442 static const struct field_desc tp_la1[] = { 7443 { "CplCmdIn", 56, 8 }, 7444 { "CplCmdOut", 48, 8 }, 7445 { "ESynOut", 47, 1 }, 7446 { "EAckOut", 46, 1 }, 7447 { "EFinOut", 45, 1 }, 7448 { "ERstOut", 44, 1 }, 7449 { "SynIn", 43, 1 }, 7450 { "AckIn", 42, 1 }, 7451 { "FinIn", 41, 1 }, 7452 { "RstIn", 40, 1 }, 7453 { "DataIn", 39, 1 }, 7454 { "DataInVld", 38, 1 }, 7455 { "PadIn", 37, 1 }, 7456 { "RxBufEmpty", 36, 1 }, 7457 { "RxDdp", 35, 1 }, 7458 { "RxFbCongestion", 34, 1 }, 7459 { "TxFbCongestion", 33, 1 }, 7460 { "TxPktSumSrdy", 32, 1 }, 7461 { "RcfUlpType", 28, 4 }, 7462 { "Eread", 27, 1 }, 7463 { "Ebypass", 26, 1 }, 7464 { "Esave", 25, 1 }, 7465 { "Static0", 24, 1 }, 7466 { "Cread", 23, 1 }, 7467 { "Cbypass", 22, 1 }, 7468 { "Csave", 21, 1 }, 7469 { "CPktOut", 20, 1 }, 7470 { "RxPagePoolFull", 18, 2 }, 7471 { "RxLpbkPkt", 17, 1 }, 7472 { "TxLpbkPkt", 16, 1 }, 7473 { "RxVfValid", 15, 1 }, 7474 { "SynLearned", 14, 1 }, 7475 { "SetDelEntry", 13, 1 }, 7476 { "SetInvEntry", 12, 1 }, 7477 { "CpcmdDvld", 11, 1 }, 7478 { "CpcmdSave", 10, 1 }, 7479 { "RxPstructsFull", 8, 2 }, 7480 { "EpcmdDvld", 7, 1 }, 7481 { "EpcmdFlush", 6, 1 }, 7482 { "EpcmdTrimPrefix", 5, 1 }, 7483 { "EpcmdTrimPostfix", 4, 1 }, 7484 { "ERssIp4Pkt", 3, 1 }, 7485 { "ERssIp6Pkt", 2, 1 }, 7486 { "ERssTcpUdpPkt", 1, 1 }, 7487 { "ERssFceFipPkt", 0, 1 }, 7488 { NULL } 7489 }; 7490 7491 static const struct field_desc tp_la2[] = { 7492 { "CplCmdIn", 56, 8 }, 7493 { "MpsVfVld", 55, 1 }, 7494 { "MpsPf", 52, 3 }, 7495 { "MpsVf", 44, 8 }, 7496 { "SynIn", 43, 1 }, 7497 { "AckIn", 42, 1 }, 7498 { "FinIn", 41, 1 }, 7499 { "RstIn", 40, 1 }, 7500 { "DataIn", 39, 1 }, 7501 { "DataInVld", 38, 1 }, 7502 { "PadIn", 37, 1 }, 7503 { "RxBufEmpty", 36, 1 }, 7504 { "RxDdp", 35, 1 }, 7505 { "RxFbCongestion", 34, 1 }, 7506 { "TxFbCongestion", 33, 1 }, 7507 { "TxPktSumSrdy", 32, 1 }, 7508 { "RcfUlpType", 28, 4 }, 7509 { "Eread", 27, 1 }, 7510 { "Ebypass", 26, 1 }, 7511 { "Esave", 25, 1 }, 7512 { "Static0", 24, 1 }, 7513 { "Cread", 23, 1 }, 7514 { "Cbypass", 22, 1 }, 7515 { "Csave", 21, 1 }, 7516 { "CPktOut", 20, 1 }, 7517 { "RxPagePoolFull", 18, 2 }, 7518 { "RxLpbkPkt", 17, 1 }, 7519 { "TxLpbkPkt", 16, 1 }, 7520 { "RxVfValid", 15, 1 }, 7521 { "SynLearned", 14, 1 }, 7522 { "SetDelEntry", 13, 1 }, 7523 { "SetInvEntry", 12, 1 }, 7524 { "CpcmdDvld", 11, 1 }, 7525 { "CpcmdSave", 10, 1 }, 7526 { "RxPstructsFull", 8, 2 }, 7527 { "EpcmdDvld", 7, 1 }, 7528 { "EpcmdFlush", 6, 1 }, 7529 { "EpcmdTrimPrefix", 5, 1 }, 7530 { "EpcmdTrimPostfix", 4, 1 }, 7531 { "ERssIp4Pkt", 3, 1 }, 7532 { "ERssIp6Pkt", 2, 1 }, 7533 { "ERssTcpUdpPkt", 1, 1 }, 7534 { "ERssFceFipPkt", 0, 1 }, 7535 { NULL } 7536 }; 7537 7538 static void 7539 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 7540 { 7541 7542 field_desc_show(sb, *p, tp_la0); 7543 } 7544 7545 static void 7546 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 7547 { 7548 7549 if (idx) 7550 sbuf_printf(sb, "\n"); 7551 field_desc_show(sb, p[0], tp_la0); 7552 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7553 field_desc_show(sb, p[1], tp_la0); 7554 } 7555 7556 static void 7557 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 7558 { 7559 7560 if (idx) 7561 sbuf_printf(sb, "\n"); 7562 field_desc_show(sb, p[0], tp_la0); 7563 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7564 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 7565 } 7566 7567 static int 7568 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 7569 { 7570 struct adapter *sc = arg1; 7571 struct sbuf *sb; 7572 uint64_t *buf, *p; 7573 int rc; 7574 u_int i, inc; 7575 void (*show_func)(struct sbuf *, uint64_t *, int); 7576 7577 rc = sysctl_wire_old_buffer(req, 0); 7578 if (rc != 0) 7579 return (rc); 7580 7581 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7582 if (sb == NULL) 7583 return (ENOMEM); 7584 7585 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 7586 7587 t4_tp_read_la(sc, buf, NULL); 7588 p = buf; 7589 7590 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 7591 case 2: 7592 inc = 2; 7593 show_func = tp_la_show2; 7594 break; 7595 case 3: 7596 inc = 2; 7597 show_func = tp_la_show3; 7598 break; 7599 default: 7600 inc = 1; 7601 show_func = tp_la_show; 7602 } 7603 7604 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 7605 (*show_func)(sb, p, i); 7606 7607 rc = sbuf_finish(sb); 7608 sbuf_delete(sb); 7609 free(buf, M_CXGBE); 7610 return (rc); 7611 } 7612 7613 static int 7614 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 7615 { 7616 struct adapter *sc = arg1; 7617 struct sbuf *sb; 7618 int rc; 7619 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 7620 7621 rc = sysctl_wire_old_buffer(req, 0); 7622 if (rc != 0) 7623 return (rc); 7624 7625 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7626 if (sb == NULL) 7627 return (ENOMEM); 7628 7629 t4_get_chan_txrate(sc, nrate, orate); 7630 7631 if (sc->chip_params->nchan > 2) { 7632 sbuf_printf(sb, " channel 0 channel 1" 7633 " channel 2 channel 3\n"); 7634 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 7635 nrate[0], nrate[1], nrate[2], nrate[3]); 7636 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 7637 orate[0], orate[1], orate[2], orate[3]); 7638 } else { 7639 sbuf_printf(sb, " channel 0 channel 1\n"); 7640 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 7641 nrate[0], nrate[1]); 7642 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 7643 orate[0], orate[1]); 7644 } 7645 7646 rc = sbuf_finish(sb); 7647 sbuf_delete(sb); 7648 7649 return (rc); 7650 } 7651 7652 static int 7653 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 7654 { 7655 struct adapter *sc = arg1; 7656 struct sbuf *sb; 7657 uint32_t *buf, *p; 7658 int rc, i; 7659 7660 rc = sysctl_wire_old_buffer(req, 0); 7661 if (rc != 0) 7662 return (rc); 7663 7664 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7665 if (sb == NULL) 7666 return (ENOMEM); 7667 7668 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 7669 M_ZERO | M_WAITOK); 7670 7671 t4_ulprx_read_la(sc, buf); 7672 p = buf; 7673 7674 sbuf_printf(sb, " Pcmd Type Message" 7675 " Data"); 7676 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 7677 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 7678 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 7679 } 7680 7681 rc = sbuf_finish(sb); 7682 sbuf_delete(sb); 7683 free(buf, M_CXGBE); 7684 return (rc); 7685 } 7686 7687 static int 7688 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 7689 { 7690 struct adapter *sc = arg1; 7691 struct sbuf *sb; 7692 int rc, v; 7693 7694 MPASS(chip_id(sc) >= CHELSIO_T5); 7695 7696 rc = sysctl_wire_old_buffer(req, 0); 7697 if (rc != 0) 7698 return (rc); 7699 7700 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7701 if (sb == NULL) 7702 return (ENOMEM); 7703 7704 v = t4_read_reg(sc, A_SGE_STAT_CFG); 7705 if (G_STATSOURCE_T5(v) == 7) { 7706 int mode; 7707 7708 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 7709 if (mode == 0) { 7710 sbuf_printf(sb, "total %d, incomplete %d", 7711 t4_read_reg(sc, A_SGE_STAT_TOTAL), 7712 t4_read_reg(sc, A_SGE_STAT_MATCH)); 7713 } else if (mode == 1) { 7714 sbuf_printf(sb, "total %d, data overflow %d", 7715 t4_read_reg(sc, A_SGE_STAT_TOTAL), 7716 t4_read_reg(sc, A_SGE_STAT_MATCH)); 7717 } else { 7718 sbuf_printf(sb, "unknown mode %d", mode); 7719 } 7720 } 7721 rc = sbuf_finish(sb); 7722 sbuf_delete(sb); 7723 7724 return (rc); 7725 } 7726 7727 static int 7728 sysctl_tc_params(SYSCTL_HANDLER_ARGS) 7729 { 7730 struct adapter *sc = arg1; 7731 struct tx_sched_class *tc; 7732 struct t4_sched_class_params p; 7733 struct sbuf *sb; 7734 int i, rc, port_id, flags, mbps, gbps; 7735 7736 rc = sysctl_wire_old_buffer(req, 0); 7737 if (rc != 0) 7738 return (rc); 7739 7740 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7741 if (sb == NULL) 7742 return (ENOMEM); 7743 7744 port_id = arg2 >> 16; 7745 MPASS(port_id < sc->params.nports); 7746 MPASS(sc->port[port_id] != NULL); 7747 i = arg2 & 0xffff; 7748 MPASS(i < sc->chip_params->nsched_cls); 7749 tc = &sc->port[port_id]->tc[i]; 7750 7751 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 7752 "t4tc_p"); 7753 if (rc) 7754 goto done; 7755 flags = tc->flags; 7756 p = tc->params; 7757 end_synchronized_op(sc, LOCK_HELD); 7758 7759 if ((flags & TX_SC_OK) == 0) { 7760 sbuf_printf(sb, "none"); 7761 goto done; 7762 } 7763 7764 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) { 7765 sbuf_printf(sb, "cl-wrr weight %u", p.weight); 7766 goto done; 7767 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL) 7768 sbuf_printf(sb, "cl-rl"); 7769 else if (p.level == SCHED_CLASS_LEVEL_CH_RL) 7770 sbuf_printf(sb, "ch-rl"); 7771 else { 7772 rc = ENXIO; 7773 goto done; 7774 } 7775 7776 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) { 7777 /* XXX: top speed or actual link speed? */ 7778 gbps = port_top_speed(sc->port[port_id]); 7779 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps); 7780 } 7781 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) { 7782 switch (p.rateunit) { 7783 case SCHED_CLASS_RATEUNIT_BITS: 7784 mbps = p.maxrate / 1000; 7785 gbps = p.maxrate / 1000000; 7786 if (p.maxrate == gbps * 1000000) 7787 sbuf_printf(sb, " %uGbps", gbps); 7788 else if (p.maxrate == mbps * 1000) 7789 sbuf_printf(sb, " %uMbps", mbps); 7790 else 7791 sbuf_printf(sb, " %uKbps", p.maxrate); 7792 break; 7793 case SCHED_CLASS_RATEUNIT_PKTS: 7794 sbuf_printf(sb, " %upps", p.maxrate); 7795 break; 7796 default: 7797 rc = ENXIO; 7798 goto done; 7799 } 7800 } 7801 7802 switch (p.mode) { 7803 case SCHED_CLASS_MODE_CLASS: 7804 sbuf_printf(sb, " aggregate"); 7805 break; 7806 case SCHED_CLASS_MODE_FLOW: 7807 sbuf_printf(sb, " per-flow"); 7808 break; 7809 default: 7810 rc = ENXIO; 7811 goto done; 7812 } 7813 7814 done: 7815 if (rc == 0) 7816 rc = sbuf_finish(sb); 7817 sbuf_delete(sb); 7818 7819 return (rc); 7820 } 7821 #endif 7822 7823 #ifdef TCP_OFFLOAD 7824 static void 7825 unit_conv(char *buf, size_t len, u_int val, u_int factor) 7826 { 7827 u_int rem = val % factor; 7828 7829 if (rem == 0) 7830 snprintf(buf, len, "%u", val / factor); 7831 else { 7832 while (rem % 10 == 0) 7833 rem /= 10; 7834 snprintf(buf, len, "%u.%u", val / factor, rem); 7835 } 7836 } 7837 7838 static int 7839 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 7840 { 7841 struct adapter *sc = arg1; 7842 char buf[16]; 7843 u_int res, re; 7844 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7845 7846 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 7847 switch (arg2) { 7848 case 0: 7849 /* timer_tick */ 7850 re = G_TIMERRESOLUTION(res); 7851 break; 7852 case 1: 7853 /* TCP timestamp tick */ 7854 re = G_TIMESTAMPRESOLUTION(res); 7855 break; 7856 case 2: 7857 /* DACK tick */ 7858 re = G_DELAYEDACKRESOLUTION(res); 7859 break; 7860 default: 7861 return (EDOOFUS); 7862 } 7863 7864 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 7865 7866 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 7867 } 7868 7869 static int 7870 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 7871 { 7872 struct adapter *sc = arg1; 7873 u_int res, dack_re, v; 7874 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7875 7876 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 7877 dack_re = G_DELAYEDACKRESOLUTION(res); 7878 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 7879 7880 return (sysctl_handle_int(oidp, &v, 0, req)); 7881 } 7882 7883 static int 7884 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 7885 { 7886 struct adapter *sc = arg1; 7887 int reg = arg2; 7888 u_int tre; 7889 u_long tp_tick_us, v; 7890 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7891 7892 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 7893 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 7894 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT || 7895 reg == A_TP_FINWAIT2_TIMER); 7896 7897 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 7898 tp_tick_us = (cclk_ps << tre) / 1000000; 7899 7900 if (reg == A_TP_INIT_SRTT) 7901 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 7902 else 7903 v = tp_tick_us * t4_read_reg(sc, reg); 7904 7905 return (sysctl_handle_long(oidp, &v, 0, req)); 7906 } 7907 #endif 7908 7909 static uint32_t 7910 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf) 7911 { 7912 uint32_t mode; 7913 7914 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR | 7915 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT; 7916 7917 if (fconf & F_FRAGMENTATION) 7918 mode |= T4_FILTER_IP_FRAGMENT; 7919 7920 if (fconf & F_MPSHITTYPE) 7921 mode |= T4_FILTER_MPS_HIT_TYPE; 7922 7923 if (fconf & F_MACMATCH) 7924 mode |= T4_FILTER_MAC_IDX; 7925 7926 if (fconf & F_ETHERTYPE) 7927 mode |= T4_FILTER_ETH_TYPE; 7928 7929 if (fconf & F_PROTOCOL) 7930 mode |= T4_FILTER_IP_PROTO; 7931 7932 if (fconf & F_TOS) 7933 mode |= T4_FILTER_IP_TOS; 7934 7935 if (fconf & F_VLAN) 7936 mode |= T4_FILTER_VLAN; 7937 7938 if (fconf & F_VNIC_ID) { 7939 mode |= T4_FILTER_VNIC; 7940 if (iconf & F_VNIC) 7941 mode |= T4_FILTER_IC_VNIC; 7942 } 7943 7944 if (fconf & F_PORT) 7945 mode |= T4_FILTER_PORT; 7946 7947 if (fconf & F_FCOE) 7948 mode |= T4_FILTER_FCoE; 7949 7950 return (mode); 7951 } 7952 7953 static uint32_t 7954 mode_to_fconf(uint32_t mode) 7955 { 7956 uint32_t fconf = 0; 7957 7958 if (mode & T4_FILTER_IP_FRAGMENT) 7959 fconf |= F_FRAGMENTATION; 7960 7961 if (mode & T4_FILTER_MPS_HIT_TYPE) 7962 fconf |= F_MPSHITTYPE; 7963 7964 if (mode & T4_FILTER_MAC_IDX) 7965 fconf |= F_MACMATCH; 7966 7967 if (mode & T4_FILTER_ETH_TYPE) 7968 fconf |= F_ETHERTYPE; 7969 7970 if (mode & T4_FILTER_IP_PROTO) 7971 fconf |= F_PROTOCOL; 7972 7973 if (mode & T4_FILTER_IP_TOS) 7974 fconf |= F_TOS; 7975 7976 if (mode & T4_FILTER_VLAN) 7977 fconf |= F_VLAN; 7978 7979 if (mode & T4_FILTER_VNIC) 7980 fconf |= F_VNIC_ID; 7981 7982 if (mode & T4_FILTER_PORT) 7983 fconf |= F_PORT; 7984 7985 if (mode & T4_FILTER_FCoE) 7986 fconf |= F_FCOE; 7987 7988 return (fconf); 7989 } 7990 7991 static uint32_t 7992 mode_to_iconf(uint32_t mode) 7993 { 7994 7995 if (mode & T4_FILTER_IC_VNIC) 7996 return (F_VNIC); 7997 return (0); 7998 } 7999 8000 static int check_fspec_against_fconf_iconf(struct adapter *sc, 8001 struct t4_filter_specification *fs) 8002 { 8003 struct tp_params *tpp = &sc->params.tp; 8004 uint32_t fconf = 0; 8005 8006 if (fs->val.frag || fs->mask.frag) 8007 fconf |= F_FRAGMENTATION; 8008 8009 if (fs->val.matchtype || fs->mask.matchtype) 8010 fconf |= F_MPSHITTYPE; 8011 8012 if (fs->val.macidx || fs->mask.macidx) 8013 fconf |= F_MACMATCH; 8014 8015 if (fs->val.ethtype || fs->mask.ethtype) 8016 fconf |= F_ETHERTYPE; 8017 8018 if (fs->val.proto || fs->mask.proto) 8019 fconf |= F_PROTOCOL; 8020 8021 if (fs->val.tos || fs->mask.tos) 8022 fconf |= F_TOS; 8023 8024 if (fs->val.vlan_vld || fs->mask.vlan_vld) 8025 fconf |= F_VLAN; 8026 8027 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) { 8028 fconf |= F_VNIC_ID; 8029 if (tpp->ingress_config & F_VNIC) 8030 return (EINVAL); 8031 } 8032 8033 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) { 8034 fconf |= F_VNIC_ID; 8035 if ((tpp->ingress_config & F_VNIC) == 0) 8036 return (EINVAL); 8037 } 8038 8039 if (fs->val.iport || fs->mask.iport) 8040 fconf |= F_PORT; 8041 8042 if (fs->val.fcoe || fs->mask.fcoe) 8043 fconf |= F_FCOE; 8044 8045 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map) 8046 return (E2BIG); 8047 8048 return (0); 8049 } 8050 8051 static int 8052 get_filter_mode(struct adapter *sc, uint32_t *mode) 8053 { 8054 struct tp_params *tpp = &sc->params.tp; 8055 8056 /* 8057 * We trust the cached values of the relevant TP registers. This means 8058 * things work reliably only if writes to those registers are always via 8059 * t4_set_filter_mode. 8060 */ 8061 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config); 8062 8063 return (0); 8064 } 8065 8066 static int 8067 set_filter_mode(struct adapter *sc, uint32_t mode) 8068 { 8069 struct tp_params *tpp = &sc->params.tp; 8070 uint32_t fconf, iconf; 8071 int rc; 8072 8073 iconf = mode_to_iconf(mode); 8074 if ((iconf ^ tpp->ingress_config) & F_VNIC) { 8075 /* 8076 * For now we just complain if A_TP_INGRESS_CONFIG is not 8077 * already set to the correct value for the requested filter 8078 * mode. It's not clear if it's safe to write to this register 8079 * on the fly. (And we trust the cached value of the register). 8080 */ 8081 return (EBUSY); 8082 } 8083 8084 fconf = mode_to_fconf(mode); 8085 8086 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8087 "t4setfm"); 8088 if (rc) 8089 return (rc); 8090 8091 if (sc->tids.ftids_in_use > 0) { 8092 rc = EBUSY; 8093 goto done; 8094 } 8095 8096 #ifdef TCP_OFFLOAD 8097 if (uld_active(sc, ULD_TOM)) { 8098 rc = EBUSY; 8099 goto done; 8100 } 8101 #endif 8102 8103 rc = -t4_set_filter_mode(sc, fconf); 8104 done: 8105 end_synchronized_op(sc, LOCK_HELD); 8106 return (rc); 8107 } 8108 8109 static inline uint64_t 8110 get_filter_hits(struct adapter *sc, uint32_t fid) 8111 { 8112 uint32_t tcb_addr; 8113 8114 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) + 8115 (fid + sc->tids.ftid_base) * TCB_SIZE; 8116 8117 if (is_t4(sc)) { 8118 uint64_t hits; 8119 8120 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8); 8121 return (be64toh(hits)); 8122 } else { 8123 uint32_t hits; 8124 8125 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4); 8126 return (be32toh(hits)); 8127 } 8128 } 8129 8130 static int 8131 get_filter(struct adapter *sc, struct t4_filter *t) 8132 { 8133 int i, rc, nfilters = sc->tids.nftids; 8134 struct filter_entry *f; 8135 8136 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8137 "t4getf"); 8138 if (rc) 8139 return (rc); 8140 8141 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL || 8142 t->idx >= nfilters) { 8143 t->idx = 0xffffffff; 8144 goto done; 8145 } 8146 8147 f = &sc->tids.ftid_tab[t->idx]; 8148 for (i = t->idx; i < nfilters; i++, f++) { 8149 if (f->valid) { 8150 t->idx = i; 8151 t->l2tidx = f->l2t ? f->l2t->idx : 0; 8152 t->smtidx = f->smtidx; 8153 if (f->fs.hitcnts) 8154 t->hits = get_filter_hits(sc, t->idx); 8155 else 8156 t->hits = UINT64_MAX; 8157 t->fs = f->fs; 8158 8159 goto done; 8160 } 8161 } 8162 8163 t->idx = 0xffffffff; 8164 done: 8165 end_synchronized_op(sc, LOCK_HELD); 8166 return (0); 8167 } 8168 8169 static int 8170 set_filter(struct adapter *sc, struct t4_filter *t) 8171 { 8172 unsigned int nfilters, nports; 8173 struct filter_entry *f; 8174 int i, rc; 8175 8176 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf"); 8177 if (rc) 8178 return (rc); 8179 8180 nfilters = sc->tids.nftids; 8181 nports = sc->params.nports; 8182 8183 if (nfilters == 0) { 8184 rc = ENOTSUP; 8185 goto done; 8186 } 8187 8188 if (t->idx >= nfilters) { 8189 rc = EINVAL; 8190 goto done; 8191 } 8192 8193 /* Validate against the global filter mode and ingress config */ 8194 rc = check_fspec_against_fconf_iconf(sc, &t->fs); 8195 if (rc != 0) 8196 goto done; 8197 8198 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) { 8199 rc = EINVAL; 8200 goto done; 8201 } 8202 8203 if (t->fs.val.iport >= nports) { 8204 rc = EINVAL; 8205 goto done; 8206 } 8207 8208 /* Can't specify an iq if not steering to it */ 8209 if (!t->fs.dirsteer && t->fs.iq) { 8210 rc = EINVAL; 8211 goto done; 8212 } 8213 8214 /* IPv6 filter idx must be 4 aligned */ 8215 if (t->fs.type == 1 && 8216 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) { 8217 rc = EINVAL; 8218 goto done; 8219 } 8220 8221 if (!(sc->flags & FULL_INIT_DONE) && 8222 ((rc = adapter_full_init(sc)) != 0)) 8223 goto done; 8224 8225 if (sc->tids.ftid_tab == NULL) { 8226 KASSERT(sc->tids.ftids_in_use == 0, 8227 ("%s: no memory allocated but filters_in_use > 0", 8228 __func__)); 8229 8230 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) * 8231 nfilters, M_CXGBE, M_NOWAIT | M_ZERO); 8232 if (sc->tids.ftid_tab == NULL) { 8233 rc = ENOMEM; 8234 goto done; 8235 } 8236 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF); 8237 } 8238 8239 for (i = 0; i < 4; i++) { 8240 f = &sc->tids.ftid_tab[t->idx + i]; 8241 8242 if (f->pending || f->valid) { 8243 rc = EBUSY; 8244 goto done; 8245 } 8246 if (f->locked) { 8247 rc = EPERM; 8248 goto done; 8249 } 8250 8251 if (t->fs.type == 0) 8252 break; 8253 } 8254 8255 f = &sc->tids.ftid_tab[t->idx]; 8256 f->fs = t->fs; 8257 8258 rc = set_filter_wr(sc, t->idx); 8259 done: 8260 end_synchronized_op(sc, 0); 8261 8262 if (rc == 0) { 8263 mtx_lock(&sc->tids.ftid_lock); 8264 for (;;) { 8265 if (f->pending == 0) { 8266 rc = f->valid ? 0 : EIO; 8267 break; 8268 } 8269 8270 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8271 PCATCH, "t4setfw", 0)) { 8272 rc = EINPROGRESS; 8273 break; 8274 } 8275 } 8276 mtx_unlock(&sc->tids.ftid_lock); 8277 } 8278 return (rc); 8279 } 8280 8281 static int 8282 del_filter(struct adapter *sc, struct t4_filter *t) 8283 { 8284 unsigned int nfilters; 8285 struct filter_entry *f; 8286 int rc; 8287 8288 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf"); 8289 if (rc) 8290 return (rc); 8291 8292 nfilters = sc->tids.nftids; 8293 8294 if (nfilters == 0) { 8295 rc = ENOTSUP; 8296 goto done; 8297 } 8298 8299 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 || 8300 t->idx >= nfilters) { 8301 rc = EINVAL; 8302 goto done; 8303 } 8304 8305 if (!(sc->flags & FULL_INIT_DONE)) { 8306 rc = EAGAIN; 8307 goto done; 8308 } 8309 8310 f = &sc->tids.ftid_tab[t->idx]; 8311 8312 if (f->pending) { 8313 rc = EBUSY; 8314 goto done; 8315 } 8316 if (f->locked) { 8317 rc = EPERM; 8318 goto done; 8319 } 8320 8321 if (f->valid) { 8322 t->fs = f->fs; /* extra info for the caller */ 8323 rc = del_filter_wr(sc, t->idx); 8324 } 8325 8326 done: 8327 end_synchronized_op(sc, 0); 8328 8329 if (rc == 0) { 8330 mtx_lock(&sc->tids.ftid_lock); 8331 for (;;) { 8332 if (f->pending == 0) { 8333 rc = f->valid ? EIO : 0; 8334 break; 8335 } 8336 8337 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8338 PCATCH, "t4delfw", 0)) { 8339 rc = EINPROGRESS; 8340 break; 8341 } 8342 } 8343 mtx_unlock(&sc->tids.ftid_lock); 8344 } 8345 8346 return (rc); 8347 } 8348 8349 static void 8350 clear_filter(struct filter_entry *f) 8351 { 8352 if (f->l2t) 8353 t4_l2t_release(f->l2t); 8354 8355 bzero(f, sizeof (*f)); 8356 } 8357 8358 static int 8359 set_filter_wr(struct adapter *sc, int fidx) 8360 { 8361 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8362 struct fw_filter_wr *fwr; 8363 unsigned int ftid, vnic_vld, vnic_vld_mask; 8364 struct wrq_cookie cookie; 8365 8366 ASSERT_SYNCHRONIZED_OP(sc); 8367 8368 if (f->fs.newdmac || f->fs.newvlan) { 8369 /* This filter needs an L2T entry; allocate one. */ 8370 f->l2t = t4_l2t_alloc_switching(sc->l2t); 8371 if (f->l2t == NULL) 8372 return (EAGAIN); 8373 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport, 8374 f->fs.dmac)) { 8375 t4_l2t_release(f->l2t); 8376 f->l2t = NULL; 8377 return (ENOMEM); 8378 } 8379 } 8380 8381 /* Already validated against fconf, iconf */ 8382 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0); 8383 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0); 8384 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld) 8385 vnic_vld = 1; 8386 else 8387 vnic_vld = 0; 8388 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld) 8389 vnic_vld_mask = 1; 8390 else 8391 vnic_vld_mask = 0; 8392 8393 ftid = sc->tids.ftid_base + fidx; 8394 8395 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8396 if (fwr == NULL) 8397 return (ENOMEM); 8398 bzero(fwr, sizeof(*fwr)); 8399 8400 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR)); 8401 fwr->len16_pkd = htobe32(FW_LEN16(*fwr)); 8402 fwr->tid_to_iq = 8403 htobe32(V_FW_FILTER_WR_TID(ftid) | 8404 V_FW_FILTER_WR_RQTYPE(f->fs.type) | 8405 V_FW_FILTER_WR_NOREPLY(0) | 8406 V_FW_FILTER_WR_IQ(f->fs.iq)); 8407 fwr->del_filter_to_l2tix = 8408 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) | 8409 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) | 8410 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) | 8411 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) | 8412 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) | 8413 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) | 8414 V_FW_FILTER_WR_DMAC(f->fs.newdmac) | 8415 V_FW_FILTER_WR_SMAC(f->fs.newsmac) | 8416 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT || 8417 f->fs.newvlan == VLAN_REWRITE) | 8418 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE || 8419 f->fs.newvlan == VLAN_REWRITE) | 8420 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) | 8421 V_FW_FILTER_WR_TXCHAN(f->fs.eport) | 8422 V_FW_FILTER_WR_PRIO(f->fs.prio) | 8423 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0)); 8424 fwr->ethtype = htobe16(f->fs.val.ethtype); 8425 fwr->ethtypem = htobe16(f->fs.mask.ethtype); 8426 fwr->frag_to_ovlan_vldm = 8427 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) | 8428 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) | 8429 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) | 8430 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) | 8431 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) | 8432 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask)); 8433 fwr->smac_sel = 0; 8434 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) | 8435 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id)); 8436 fwr->maci_to_matchtypem = 8437 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) | 8438 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) | 8439 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) | 8440 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) | 8441 V_FW_FILTER_WR_PORT(f->fs.val.iport) | 8442 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) | 8443 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) | 8444 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype)); 8445 fwr->ptcl = f->fs.val.proto; 8446 fwr->ptclm = f->fs.mask.proto; 8447 fwr->ttyp = f->fs.val.tos; 8448 fwr->ttypm = f->fs.mask.tos; 8449 fwr->ivlan = htobe16(f->fs.val.vlan); 8450 fwr->ivlanm = htobe16(f->fs.mask.vlan); 8451 fwr->ovlan = htobe16(f->fs.val.vnic); 8452 fwr->ovlanm = htobe16(f->fs.mask.vnic); 8453 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip)); 8454 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm)); 8455 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip)); 8456 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm)); 8457 fwr->lp = htobe16(f->fs.val.dport); 8458 fwr->lpm = htobe16(f->fs.mask.dport); 8459 fwr->fp = htobe16(f->fs.val.sport); 8460 fwr->fpm = htobe16(f->fs.mask.sport); 8461 if (f->fs.newsmac) 8462 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma)); 8463 8464 f->pending = 1; 8465 sc->tids.ftids_in_use++; 8466 8467 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8468 return (0); 8469 } 8470 8471 static int 8472 del_filter_wr(struct adapter *sc, int fidx) 8473 { 8474 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8475 struct fw_filter_wr *fwr; 8476 unsigned int ftid; 8477 struct wrq_cookie cookie; 8478 8479 ftid = sc->tids.ftid_base + fidx; 8480 8481 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8482 if (fwr == NULL) 8483 return (ENOMEM); 8484 bzero(fwr, sizeof (*fwr)); 8485 8486 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id); 8487 8488 f->pending = 1; 8489 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8490 return (0); 8491 } 8492 8493 int 8494 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8495 { 8496 struct adapter *sc = iq->adapter; 8497 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1); 8498 unsigned int idx = GET_TID(rpl); 8499 unsigned int rc; 8500 struct filter_entry *f; 8501 8502 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 8503 rss->opcode)); 8504 MPASS(iq == &sc->sge.fwq); 8505 MPASS(is_ftid(sc, idx)); 8506 8507 idx -= sc->tids.ftid_base; 8508 f = &sc->tids.ftid_tab[idx]; 8509 rc = G_COOKIE(rpl->cookie); 8510 8511 mtx_lock(&sc->tids.ftid_lock); 8512 if (rc == FW_FILTER_WR_FLT_ADDED) { 8513 KASSERT(f->pending, ("%s: filter[%u] isn't pending.", 8514 __func__, idx)); 8515 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; 8516 f->pending = 0; /* asynchronous setup completed */ 8517 f->valid = 1; 8518 } else { 8519 if (rc != FW_FILTER_WR_FLT_DELETED) { 8520 /* Add or delete failed, display an error */ 8521 log(LOG_ERR, 8522 "filter %u setup failed with error %u\n", 8523 idx, rc); 8524 } 8525 8526 clear_filter(f); 8527 sc->tids.ftids_in_use--; 8528 } 8529 wakeup(&sc->tids.ftid_tab); 8530 mtx_unlock(&sc->tids.ftid_lock); 8531 8532 return (0); 8533 } 8534 8535 static int 8536 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8537 { 8538 8539 MPASS(iq->set_tcb_rpl != NULL); 8540 return (iq->set_tcb_rpl(iq, rss, m)); 8541 } 8542 8543 static int 8544 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8545 { 8546 8547 MPASS(iq->l2t_write_rpl != NULL); 8548 return (iq->l2t_write_rpl(iq, rss, m)); 8549 } 8550 8551 static int 8552 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 8553 { 8554 int rc; 8555 8556 if (cntxt->cid > M_CTXTQID) 8557 return (EINVAL); 8558 8559 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 8560 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 8561 return (EINVAL); 8562 8563 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 8564 if (rc) 8565 return (rc); 8566 8567 if (sc->flags & FW_OK) { 8568 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 8569 &cntxt->data[0]); 8570 if (rc == 0) 8571 goto done; 8572 } 8573 8574 /* 8575 * Read via firmware failed or wasn't even attempted. Read directly via 8576 * the backdoor. 8577 */ 8578 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 8579 done: 8580 end_synchronized_op(sc, 0); 8581 return (rc); 8582 } 8583 8584 static int 8585 load_fw(struct adapter *sc, struct t4_data *fw) 8586 { 8587 int rc; 8588 uint8_t *fw_data; 8589 8590 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 8591 if (rc) 8592 return (rc); 8593 8594 if (sc->flags & FULL_INIT_DONE) { 8595 rc = EBUSY; 8596 goto done; 8597 } 8598 8599 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 8600 if (fw_data == NULL) { 8601 rc = ENOMEM; 8602 goto done; 8603 } 8604 8605 rc = copyin(fw->data, fw_data, fw->len); 8606 if (rc == 0) 8607 rc = -t4_load_fw(sc, fw_data, fw->len); 8608 8609 free(fw_data, M_CXGBE); 8610 done: 8611 end_synchronized_op(sc, 0); 8612 return (rc); 8613 } 8614 8615 #define MAX_READ_BUF_SIZE (128 * 1024) 8616 static int 8617 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 8618 { 8619 uint32_t addr, remaining, n; 8620 uint32_t *buf; 8621 int rc; 8622 uint8_t *dst; 8623 8624 rc = validate_mem_range(sc, mr->addr, mr->len); 8625 if (rc != 0) 8626 return (rc); 8627 8628 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 8629 addr = mr->addr; 8630 remaining = mr->len; 8631 dst = (void *)mr->data; 8632 8633 while (remaining) { 8634 n = min(remaining, MAX_READ_BUF_SIZE); 8635 read_via_memwin(sc, 2, addr, buf, n); 8636 8637 rc = copyout(buf, dst, n); 8638 if (rc != 0) 8639 break; 8640 8641 dst += n; 8642 remaining -= n; 8643 addr += n; 8644 } 8645 8646 free(buf, M_CXGBE); 8647 return (rc); 8648 } 8649 #undef MAX_READ_BUF_SIZE 8650 8651 static int 8652 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 8653 { 8654 int rc; 8655 8656 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 8657 return (EINVAL); 8658 8659 if (i2cd->len > sizeof(i2cd->data)) 8660 return (EFBIG); 8661 8662 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 8663 if (rc) 8664 return (rc); 8665 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 8666 i2cd->offset, i2cd->len, &i2cd->data[0]); 8667 end_synchronized_op(sc, 0); 8668 8669 return (rc); 8670 } 8671 8672 static int 8673 in_range(int val, int lo, int hi) 8674 { 8675 8676 return (val < 0 || (val <= hi && val >= lo)); 8677 } 8678 8679 static int 8680 set_sched_class_config(struct adapter *sc, int minmax) 8681 { 8682 int rc; 8683 8684 if (minmax < 0) 8685 return (EINVAL); 8686 8687 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc"); 8688 if (rc) 8689 return (rc); 8690 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1); 8691 end_synchronized_op(sc, 0); 8692 8693 return (rc); 8694 } 8695 8696 static int 8697 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p, 8698 int sleep_ok) 8699 { 8700 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode; 8701 struct port_info *pi; 8702 struct tx_sched_class *tc; 8703 8704 if (p->level == SCHED_CLASS_LEVEL_CL_RL) 8705 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL; 8706 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR) 8707 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 8708 else if (p->level == SCHED_CLASS_LEVEL_CH_RL) 8709 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL; 8710 else 8711 return (EINVAL); 8712 8713 if (p->mode == SCHED_CLASS_MODE_CLASS) 8714 fw_mode = FW_SCHED_PARAMS_MODE_CLASS; 8715 else if (p->mode == SCHED_CLASS_MODE_FLOW) 8716 fw_mode = FW_SCHED_PARAMS_MODE_FLOW; 8717 else 8718 return (EINVAL); 8719 8720 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS) 8721 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE; 8722 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS) 8723 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE; 8724 else 8725 return (EINVAL); 8726 8727 if (p->ratemode == SCHED_CLASS_RATEMODE_REL) 8728 fw_ratemode = FW_SCHED_PARAMS_RATE_REL; 8729 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS) 8730 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS; 8731 else 8732 return (EINVAL); 8733 8734 /* Vet our parameters ... */ 8735 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1)) 8736 return (ERANGE); 8737 8738 pi = sc->port[sc->chan_map[p->channel]]; 8739 if (pi == NULL) 8740 return (ENXIO); 8741 MPASS(pi->tx_chan == p->channel); 8742 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */ 8743 8744 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) || 8745 !in_range(p->minrate, 0, top_speed) || 8746 !in_range(p->maxrate, 0, top_speed) || 8747 !in_range(p->weight, 0, 100)) 8748 return (ERANGE); 8749 8750 /* 8751 * Translate any unset parameters into the firmware's 8752 * nomenclature and/or fail the call if the parameters 8753 * are required ... 8754 */ 8755 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0) 8756 return (EINVAL); 8757 8758 if (p->minrate < 0) 8759 p->minrate = 0; 8760 if (p->maxrate < 0) { 8761 if (p->level == SCHED_CLASS_LEVEL_CL_RL || 8762 p->level == SCHED_CLASS_LEVEL_CH_RL) 8763 return (EINVAL); 8764 else 8765 p->maxrate = 0; 8766 } 8767 if (p->weight < 0) { 8768 if (p->level == SCHED_CLASS_LEVEL_CL_WRR) 8769 return (EINVAL); 8770 else 8771 p->weight = 0; 8772 } 8773 if (p->pktsize < 0) { 8774 if (p->level == SCHED_CLASS_LEVEL_CL_RL || 8775 p->level == SCHED_CLASS_LEVEL_CH_RL) 8776 return (EINVAL); 8777 else 8778 p->pktsize = 0; 8779 } 8780 8781 rc = begin_synchronized_op(sc, NULL, 8782 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp"); 8783 if (rc) 8784 return (rc); 8785 tc = &pi->tc[p->cl]; 8786 tc->params = *p; 8787 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode, 8788 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate, 8789 p->weight, p->pktsize, sleep_ok); 8790 if (rc == 0) 8791 tc->flags |= TX_SC_OK; 8792 else { 8793 /* 8794 * Unknown state at this point, see tc->params for what was 8795 * attempted. 8796 */ 8797 tc->flags &= ~TX_SC_OK; 8798 } 8799 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD); 8800 8801 return (rc); 8802 } 8803 8804 int 8805 t4_set_sched_class(struct adapter *sc, struct t4_sched_params *p) 8806 { 8807 8808 if (p->type != SCHED_CLASS_TYPE_PACKET) 8809 return (EINVAL); 8810 8811 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG) 8812 return (set_sched_class_config(sc, p->u.config.minmax)); 8813 8814 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS) 8815 return (set_sched_class_params(sc, &p->u.params, 1)); 8816 8817 return (EINVAL); 8818 } 8819 8820 int 8821 t4_set_sched_queue(struct adapter *sc, struct t4_sched_queue *p) 8822 { 8823 struct port_info *pi = NULL; 8824 struct vi_info *vi; 8825 struct sge_txq *txq; 8826 uint32_t fw_mnem, fw_queue, fw_class; 8827 int i, rc; 8828 8829 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq"); 8830 if (rc) 8831 return (rc); 8832 8833 if (p->port >= sc->params.nports) { 8834 rc = EINVAL; 8835 goto done; 8836 } 8837 8838 /* XXX: Only supported for the main VI. */ 8839 pi = sc->port[p->port]; 8840 vi = &pi->vi[0]; 8841 if (!(vi->flags & VI_INIT_DONE)) { 8842 /* tx queues not set up yet */ 8843 rc = EAGAIN; 8844 goto done; 8845 } 8846 8847 if (!in_range(p->queue, 0, vi->ntxq - 1) || 8848 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) { 8849 rc = EINVAL; 8850 goto done; 8851 } 8852 8853 /* 8854 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX 8855 * Scheduling Class in this case). 8856 */ 8857 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 8858 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH)); 8859 fw_class = p->cl < 0 ? 0xffffffff : p->cl; 8860 8861 /* 8862 * If op.queue is non-negative, then we're only changing the scheduling 8863 * on a single specified TX queue. 8864 */ 8865 if (p->queue >= 0) { 8866 txq = &sc->sge.txq[vi->first_txq + p->queue]; 8867 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 8868 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 8869 &fw_class); 8870 goto done; 8871 } 8872 8873 /* 8874 * Change the scheduling on all the TX queues for the 8875 * interface. 8876 */ 8877 for_each_txq(vi, i, txq) { 8878 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 8879 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 8880 &fw_class); 8881 if (rc) 8882 goto done; 8883 } 8884 8885 rc = 0; 8886 done: 8887 end_synchronized_op(sc, 0); 8888 return (rc); 8889 } 8890 8891 int 8892 t4_os_find_pci_capability(struct adapter *sc, int cap) 8893 { 8894 int i; 8895 8896 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 8897 } 8898 8899 int 8900 t4_os_pci_save_state(struct adapter *sc) 8901 { 8902 device_t dev; 8903 struct pci_devinfo *dinfo; 8904 8905 dev = sc->dev; 8906 dinfo = device_get_ivars(dev); 8907 8908 pci_cfg_save(dev, dinfo, 0); 8909 return (0); 8910 } 8911 8912 int 8913 t4_os_pci_restore_state(struct adapter *sc) 8914 { 8915 device_t dev; 8916 struct pci_devinfo *dinfo; 8917 8918 dev = sc->dev; 8919 dinfo = device_get_ivars(dev); 8920 8921 pci_cfg_restore(dev, dinfo); 8922 return (0); 8923 } 8924 8925 void 8926 t4_os_portmod_changed(const struct adapter *sc, int idx) 8927 { 8928 struct port_info *pi = sc->port[idx]; 8929 struct vi_info *vi; 8930 struct ifnet *ifp; 8931 int v; 8932 static const char *mod_str[] = { 8933 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 8934 }; 8935 8936 for_each_vi(pi, v, vi) { 8937 build_medialist(pi, &vi->media); 8938 } 8939 8940 ifp = pi->vi[0].ifp; 8941 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 8942 if_printf(ifp, "transceiver unplugged.\n"); 8943 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 8944 if_printf(ifp, "unknown transceiver inserted.\n"); 8945 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 8946 if_printf(ifp, "unsupported transceiver inserted.\n"); 8947 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 8948 if_printf(ifp, "%s transceiver inserted.\n", 8949 mod_str[pi->mod_type]); 8950 } else { 8951 if_printf(ifp, "transceiver (type %d) inserted.\n", 8952 pi->mod_type); 8953 } 8954 } 8955 8956 void 8957 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason) 8958 { 8959 struct port_info *pi = sc->port[idx]; 8960 struct vi_info *vi; 8961 struct ifnet *ifp; 8962 int v; 8963 8964 if (link_stat) 8965 pi->linkdnrc = -1; 8966 else { 8967 if (reason >= 0) 8968 pi->linkdnrc = reason; 8969 } 8970 for_each_vi(pi, v, vi) { 8971 ifp = vi->ifp; 8972 if (ifp == NULL) 8973 continue; 8974 8975 if (link_stat) { 8976 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed); 8977 if_link_state_change(ifp, LINK_STATE_UP); 8978 } else { 8979 if_link_state_change(ifp, LINK_STATE_DOWN); 8980 } 8981 } 8982 } 8983 8984 void 8985 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 8986 { 8987 struct adapter *sc; 8988 8989 sx_slock(&t4_list_lock); 8990 SLIST_FOREACH(sc, &t4_list, link) { 8991 /* 8992 * func should not make any assumptions about what state sc is 8993 * in - the only guarantee is that sc->sc_lock is a valid lock. 8994 */ 8995 func(sc, arg); 8996 } 8997 sx_sunlock(&t4_list_lock); 8998 } 8999 9000 static int 9001 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9002 struct thread *td) 9003 { 9004 int rc; 9005 struct adapter *sc = dev->si_drv1; 9006 9007 rc = priv_check(td, PRIV_DRIVER); 9008 if (rc != 0) 9009 return (rc); 9010 9011 switch (cmd) { 9012 case CHELSIO_T4_GETREG: { 9013 struct t4_reg *edata = (struct t4_reg *)data; 9014 9015 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9016 return (EFAULT); 9017 9018 if (edata->size == 4) 9019 edata->val = t4_read_reg(sc, edata->addr); 9020 else if (edata->size == 8) 9021 edata->val = t4_read_reg64(sc, edata->addr); 9022 else 9023 return (EINVAL); 9024 9025 break; 9026 } 9027 case CHELSIO_T4_SETREG: { 9028 struct t4_reg *edata = (struct t4_reg *)data; 9029 9030 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9031 return (EFAULT); 9032 9033 if (edata->size == 4) { 9034 if (edata->val & 0xffffffff00000000) 9035 return (EINVAL); 9036 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9037 } else if (edata->size == 8) 9038 t4_write_reg64(sc, edata->addr, edata->val); 9039 else 9040 return (EINVAL); 9041 break; 9042 } 9043 case CHELSIO_T4_REGDUMP: { 9044 struct t4_regdump *regs = (struct t4_regdump *)data; 9045 int reglen = t4_get_regs_len(sc); 9046 uint8_t *buf; 9047 9048 if (regs->len < reglen) { 9049 regs->len = reglen; /* hint to the caller */ 9050 return (ENOBUFS); 9051 } 9052 9053 regs->len = reglen; 9054 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9055 get_regs(sc, regs, buf); 9056 rc = copyout(buf, regs->data, reglen); 9057 free(buf, M_CXGBE); 9058 break; 9059 } 9060 case CHELSIO_T4_GET_FILTER_MODE: 9061 rc = get_filter_mode(sc, (uint32_t *)data); 9062 break; 9063 case CHELSIO_T4_SET_FILTER_MODE: 9064 rc = set_filter_mode(sc, *(uint32_t *)data); 9065 break; 9066 case CHELSIO_T4_GET_FILTER: 9067 rc = get_filter(sc, (struct t4_filter *)data); 9068 break; 9069 case CHELSIO_T4_SET_FILTER: 9070 rc = set_filter(sc, (struct t4_filter *)data); 9071 break; 9072 case CHELSIO_T4_DEL_FILTER: 9073 rc = del_filter(sc, (struct t4_filter *)data); 9074 break; 9075 case CHELSIO_T4_GET_SGE_CONTEXT: 9076 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9077 break; 9078 case CHELSIO_T4_LOAD_FW: 9079 rc = load_fw(sc, (struct t4_data *)data); 9080 break; 9081 case CHELSIO_T4_GET_MEM: 9082 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9083 break; 9084 case CHELSIO_T4_GET_I2C: 9085 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9086 break; 9087 case CHELSIO_T4_CLEAR_STATS: { 9088 int i, v; 9089 u_int port_id = *(uint32_t *)data; 9090 struct port_info *pi; 9091 struct vi_info *vi; 9092 9093 if (port_id >= sc->params.nports) 9094 return (EINVAL); 9095 pi = sc->port[port_id]; 9096 if (pi == NULL) 9097 return (EIO); 9098 9099 /* MAC stats */ 9100 t4_clr_port_stats(sc, pi->tx_chan); 9101 pi->tx_parse_error = 0; 9102 mtx_lock(&sc->reg_lock); 9103 for_each_vi(pi, v, vi) { 9104 if (vi->flags & VI_INIT_DONE) 9105 t4_clr_vi_stats(sc, vi->viid); 9106 } 9107 mtx_unlock(&sc->reg_lock); 9108 9109 /* 9110 * Since this command accepts a port, clear stats for 9111 * all VIs on this port. 9112 */ 9113 for_each_vi(pi, v, vi) { 9114 if (vi->flags & VI_INIT_DONE) { 9115 struct sge_rxq *rxq; 9116 struct sge_txq *txq; 9117 struct sge_wrq *wrq; 9118 9119 for_each_rxq(vi, i, rxq) { 9120 #if defined(INET) || defined(INET6) 9121 rxq->lro.lro_queued = 0; 9122 rxq->lro.lro_flushed = 0; 9123 #endif 9124 rxq->rxcsum = 0; 9125 rxq->vlan_extraction = 0; 9126 } 9127 9128 for_each_txq(vi, i, txq) { 9129 txq->txcsum = 0; 9130 txq->tso_wrs = 0; 9131 txq->vlan_insertion = 0; 9132 txq->imm_wrs = 0; 9133 txq->sgl_wrs = 0; 9134 txq->txpkt_wrs = 0; 9135 txq->txpkts0_wrs = 0; 9136 txq->txpkts1_wrs = 0; 9137 txq->txpkts0_pkts = 0; 9138 txq->txpkts1_pkts = 0; 9139 mp_ring_reset_stats(txq->r); 9140 } 9141 9142 #ifdef TCP_OFFLOAD 9143 /* nothing to clear for each ofld_rxq */ 9144 9145 for_each_ofld_txq(vi, i, wrq) { 9146 wrq->tx_wrs_direct = 0; 9147 wrq->tx_wrs_copied = 0; 9148 } 9149 #endif 9150 9151 if (IS_MAIN_VI(vi)) { 9152 wrq = &sc->sge.ctrlq[pi->port_id]; 9153 wrq->tx_wrs_direct = 0; 9154 wrq->tx_wrs_copied = 0; 9155 } 9156 } 9157 } 9158 break; 9159 } 9160 case CHELSIO_T4_SCHED_CLASS: 9161 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9162 break; 9163 case CHELSIO_T4_SCHED_QUEUE: 9164 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9165 break; 9166 case CHELSIO_T4_GET_TRACER: 9167 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9168 break; 9169 case CHELSIO_T4_SET_TRACER: 9170 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9171 break; 9172 default: 9173 rc = ENOTTY; 9174 } 9175 9176 return (rc); 9177 } 9178 9179 void 9180 t4_db_full(struct adapter *sc) 9181 { 9182 9183 CXGBE_UNIMPLEMENTED(__func__); 9184 } 9185 9186 void 9187 t4_db_dropped(struct adapter *sc) 9188 { 9189 9190 CXGBE_UNIMPLEMENTED(__func__); 9191 } 9192 9193 #ifdef TCP_OFFLOAD 9194 static int 9195 toe_capability(struct vi_info *vi, int enable) 9196 { 9197 int rc; 9198 struct port_info *pi = vi->pi; 9199 struct adapter *sc = pi->adapter; 9200 9201 ASSERT_SYNCHRONIZED_OP(sc); 9202 9203 if (!is_offload(sc)) 9204 return (ENODEV); 9205 9206 if (enable) { 9207 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9208 /* TOE is already enabled. */ 9209 return (0); 9210 } 9211 9212 /* 9213 * We need the port's queues around so that we're able to send 9214 * and receive CPLs to/from the TOE even if the ifnet for this 9215 * port has never been UP'd administratively. 9216 */ 9217 if (!(vi->flags & VI_INIT_DONE)) { 9218 rc = vi_full_init(vi); 9219 if (rc) 9220 return (rc); 9221 } 9222 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9223 rc = vi_full_init(&pi->vi[0]); 9224 if (rc) 9225 return (rc); 9226 } 9227 9228 if (isset(&sc->offload_map, pi->port_id)) { 9229 /* TOE is enabled on another VI of this port. */ 9230 pi->uld_vis++; 9231 return (0); 9232 } 9233 9234 if (!uld_active(sc, ULD_TOM)) { 9235 rc = t4_activate_uld(sc, ULD_TOM); 9236 if (rc == EAGAIN) { 9237 log(LOG_WARNING, 9238 "You must kldload t4_tom.ko before trying " 9239 "to enable TOE on a cxgbe interface.\n"); 9240 } 9241 if (rc != 0) 9242 return (rc); 9243 KASSERT(sc->tom_softc != NULL, 9244 ("%s: TOM activated but softc NULL", __func__)); 9245 KASSERT(uld_active(sc, ULD_TOM), 9246 ("%s: TOM activated but flag not set", __func__)); 9247 } 9248 9249 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9250 if (!uld_active(sc, ULD_IWARP)) 9251 (void) t4_activate_uld(sc, ULD_IWARP); 9252 if (!uld_active(sc, ULD_ISCSI)) 9253 (void) t4_activate_uld(sc, ULD_ISCSI); 9254 9255 pi->uld_vis++; 9256 setbit(&sc->offload_map, pi->port_id); 9257 } else { 9258 pi->uld_vis--; 9259 9260 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9261 return (0); 9262 9263 KASSERT(uld_active(sc, ULD_TOM), 9264 ("%s: TOM never initialized?", __func__)); 9265 clrbit(&sc->offload_map, pi->port_id); 9266 } 9267 9268 return (0); 9269 } 9270 9271 /* 9272 * Add an upper layer driver to the global list. 9273 */ 9274 int 9275 t4_register_uld(struct uld_info *ui) 9276 { 9277 int rc = 0; 9278 struct uld_info *u; 9279 9280 sx_xlock(&t4_uld_list_lock); 9281 SLIST_FOREACH(u, &t4_uld_list, link) { 9282 if (u->uld_id == ui->uld_id) { 9283 rc = EEXIST; 9284 goto done; 9285 } 9286 } 9287 9288 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9289 ui->refcount = 0; 9290 done: 9291 sx_xunlock(&t4_uld_list_lock); 9292 return (rc); 9293 } 9294 9295 int 9296 t4_unregister_uld(struct uld_info *ui) 9297 { 9298 int rc = EINVAL; 9299 struct uld_info *u; 9300 9301 sx_xlock(&t4_uld_list_lock); 9302 9303 SLIST_FOREACH(u, &t4_uld_list, link) { 9304 if (u == ui) { 9305 if (ui->refcount > 0) { 9306 rc = EBUSY; 9307 goto done; 9308 } 9309 9310 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 9311 rc = 0; 9312 goto done; 9313 } 9314 } 9315 done: 9316 sx_xunlock(&t4_uld_list_lock); 9317 return (rc); 9318 } 9319 9320 int 9321 t4_activate_uld(struct adapter *sc, int id) 9322 { 9323 int rc; 9324 struct uld_info *ui; 9325 9326 ASSERT_SYNCHRONIZED_OP(sc); 9327 9328 if (id < 0 || id > ULD_MAX) 9329 return (EINVAL); 9330 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 9331 9332 sx_slock(&t4_uld_list_lock); 9333 9334 SLIST_FOREACH(ui, &t4_uld_list, link) { 9335 if (ui->uld_id == id) { 9336 if (!(sc->flags & FULL_INIT_DONE)) { 9337 rc = adapter_full_init(sc); 9338 if (rc != 0) 9339 break; 9340 } 9341 9342 rc = ui->activate(sc); 9343 if (rc == 0) { 9344 setbit(&sc->active_ulds, id); 9345 ui->refcount++; 9346 } 9347 break; 9348 } 9349 } 9350 9351 sx_sunlock(&t4_uld_list_lock); 9352 9353 return (rc); 9354 } 9355 9356 int 9357 t4_deactivate_uld(struct adapter *sc, int id) 9358 { 9359 int rc; 9360 struct uld_info *ui; 9361 9362 ASSERT_SYNCHRONIZED_OP(sc); 9363 9364 if (id < 0 || id > ULD_MAX) 9365 return (EINVAL); 9366 rc = ENXIO; 9367 9368 sx_slock(&t4_uld_list_lock); 9369 9370 SLIST_FOREACH(ui, &t4_uld_list, link) { 9371 if (ui->uld_id == id) { 9372 rc = ui->deactivate(sc); 9373 if (rc == 0) { 9374 clrbit(&sc->active_ulds, id); 9375 ui->refcount--; 9376 } 9377 break; 9378 } 9379 } 9380 9381 sx_sunlock(&t4_uld_list_lock); 9382 9383 return (rc); 9384 } 9385 9386 int 9387 uld_active(struct adapter *sc, int uld_id) 9388 { 9389 9390 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 9391 9392 return (isset(&sc->active_ulds, uld_id)); 9393 } 9394 #endif 9395 9396 /* 9397 * Come up with reasonable defaults for some of the tunables, provided they're 9398 * not set by the user (in which case we'll use the values as is). 9399 */ 9400 static void 9401 tweak_tunables(void) 9402 { 9403 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 9404 9405 if (t4_ntxq10g < 1) { 9406 #ifdef RSS 9407 t4_ntxq10g = rss_getnumbuckets(); 9408 #else 9409 t4_ntxq10g = min(nc, NTXQ_10G); 9410 #endif 9411 } 9412 9413 if (t4_ntxq1g < 1) { 9414 #ifdef RSS 9415 /* XXX: way too many for 1GbE? */ 9416 t4_ntxq1g = rss_getnumbuckets(); 9417 #else 9418 t4_ntxq1g = min(nc, NTXQ_1G); 9419 #endif 9420 } 9421 9422 if (t4_ntxq_vi < 1) 9423 t4_ntxq_vi = min(nc, NTXQ_VI); 9424 9425 if (t4_nrxq10g < 1) { 9426 #ifdef RSS 9427 t4_nrxq10g = rss_getnumbuckets(); 9428 #else 9429 t4_nrxq10g = min(nc, NRXQ_10G); 9430 #endif 9431 } 9432 9433 if (t4_nrxq1g < 1) { 9434 #ifdef RSS 9435 /* XXX: way too many for 1GbE? */ 9436 t4_nrxq1g = rss_getnumbuckets(); 9437 #else 9438 t4_nrxq1g = min(nc, NRXQ_1G); 9439 #endif 9440 } 9441 9442 if (t4_nrxq_vi < 1) 9443 t4_nrxq_vi = min(nc, NRXQ_VI); 9444 9445 #ifdef TCP_OFFLOAD 9446 if (t4_nofldtxq10g < 1) 9447 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G); 9448 9449 if (t4_nofldtxq1g < 1) 9450 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G); 9451 9452 if (t4_nofldtxq_vi < 1) 9453 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI); 9454 9455 if (t4_nofldrxq10g < 1) 9456 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G); 9457 9458 if (t4_nofldrxq1g < 1) 9459 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G); 9460 9461 if (t4_nofldrxq_vi < 1) 9462 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI); 9463 9464 if (t4_toecaps_allowed == -1) 9465 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 9466 9467 if (t4_rdmacaps_allowed == -1) { 9468 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 9469 FW_CAPS_CONFIG_RDMA_RDMAC; 9470 } 9471 9472 if (t4_iscsicaps_allowed == -1) { 9473 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 9474 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 9475 FW_CAPS_CONFIG_ISCSI_T10DIF; 9476 } 9477 #else 9478 if (t4_toecaps_allowed == -1) 9479 t4_toecaps_allowed = 0; 9480 9481 if (t4_rdmacaps_allowed == -1) 9482 t4_rdmacaps_allowed = 0; 9483 9484 if (t4_iscsicaps_allowed == -1) 9485 t4_iscsicaps_allowed = 0; 9486 #endif 9487 9488 #ifdef DEV_NETMAP 9489 if (t4_nnmtxq_vi < 1) 9490 t4_nnmtxq_vi = min(nc, NNMTXQ_VI); 9491 9492 if (t4_nnmrxq_vi < 1) 9493 t4_nnmrxq_vi = min(nc, NNMRXQ_VI); 9494 #endif 9495 9496 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS) 9497 t4_tmr_idx_10g = TMR_IDX_10G; 9498 9499 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS) 9500 t4_pktc_idx_10g = PKTC_IDX_10G; 9501 9502 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS) 9503 t4_tmr_idx_1g = TMR_IDX_1G; 9504 9505 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS) 9506 t4_pktc_idx_1g = PKTC_IDX_1G; 9507 9508 if (t4_qsize_txq < 128) 9509 t4_qsize_txq = 128; 9510 9511 if (t4_qsize_rxq < 128) 9512 t4_qsize_rxq = 128; 9513 while (t4_qsize_rxq & 7) 9514 t4_qsize_rxq++; 9515 9516 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 9517 } 9518 9519 #ifdef DDB 9520 static void 9521 t4_dump_tcb(struct adapter *sc, int tid) 9522 { 9523 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 9524 9525 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 9526 save = t4_read_reg(sc, reg); 9527 base = sc->memwin[2].mw_base; 9528 9529 /* Dump TCB for the tid */ 9530 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9531 tcb_addr += tid * TCB_SIZE; 9532 9533 if (is_t4(sc)) { 9534 pf = 0; 9535 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 9536 } else { 9537 pf = V_PFNUM(sc->pf); 9538 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 9539 } 9540 t4_write_reg(sc, reg, win_pos | pf); 9541 t4_read_reg(sc, reg); 9542 9543 off = tcb_addr - win_pos; 9544 for (i = 0; i < 4; i++) { 9545 uint32_t buf[8]; 9546 for (j = 0; j < 8; j++, off += 4) 9547 buf[j] = htonl(t4_read_reg(sc, base + off)); 9548 9549 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 9550 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 9551 buf[7]); 9552 } 9553 9554 t4_write_reg(sc, reg, save); 9555 t4_read_reg(sc, reg); 9556 } 9557 9558 static void 9559 t4_dump_devlog(struct adapter *sc) 9560 { 9561 struct devlog_params *dparams = &sc->params.devlog; 9562 struct fw_devlog_e e; 9563 int i, first, j, m, nentries, rc; 9564 uint64_t ftstamp = UINT64_MAX; 9565 9566 if (dparams->start == 0) { 9567 db_printf("devlog params not valid\n"); 9568 return; 9569 } 9570 9571 nentries = dparams->size / sizeof(struct fw_devlog_e); 9572 m = fwmtype_to_hwmtype(dparams->memtype); 9573 9574 /* Find the first entry. */ 9575 first = -1; 9576 for (i = 0; i < nentries && !db_pager_quit; i++) { 9577 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9578 sizeof(e), (void *)&e); 9579 if (rc != 0) 9580 break; 9581 9582 if (e.timestamp == 0) 9583 break; 9584 9585 e.timestamp = be64toh(e.timestamp); 9586 if (e.timestamp < ftstamp) { 9587 ftstamp = e.timestamp; 9588 first = i; 9589 } 9590 } 9591 9592 if (first == -1) 9593 return; 9594 9595 i = first; 9596 do { 9597 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9598 sizeof(e), (void *)&e); 9599 if (rc != 0) 9600 return; 9601 9602 if (e.timestamp == 0) 9603 return; 9604 9605 e.timestamp = be64toh(e.timestamp); 9606 e.seqno = be32toh(e.seqno); 9607 for (j = 0; j < 8; j++) 9608 e.params[j] = be32toh(e.params[j]); 9609 9610 db_printf("%10d %15ju %8s %8s ", 9611 e.seqno, e.timestamp, 9612 (e.level < nitems(devlog_level_strings) ? 9613 devlog_level_strings[e.level] : "UNKNOWN"), 9614 (e.facility < nitems(devlog_facility_strings) ? 9615 devlog_facility_strings[e.facility] : "UNKNOWN")); 9616 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 9617 e.params[3], e.params[4], e.params[5], e.params[6], 9618 e.params[7]); 9619 9620 if (++i == nentries) 9621 i = 0; 9622 } while (i != first && !db_pager_quit); 9623 } 9624 9625 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 9626 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 9627 9628 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 9629 { 9630 device_t dev; 9631 int t; 9632 bool valid; 9633 9634 valid = false; 9635 t = db_read_token(); 9636 if (t == tIDENT) { 9637 dev = device_lookup_by_name(db_tok_string); 9638 valid = true; 9639 } 9640 db_skip_to_eol(); 9641 if (!valid) { 9642 db_printf("usage: show t4 devlog <nexus>\n"); 9643 return; 9644 } 9645 9646 if (dev == NULL) { 9647 db_printf("device not found\n"); 9648 return; 9649 } 9650 9651 t4_dump_devlog(device_get_softc(dev)); 9652 } 9653 9654 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 9655 { 9656 device_t dev; 9657 int radix, tid, t; 9658 bool valid; 9659 9660 valid = false; 9661 radix = db_radix; 9662 db_radix = 10; 9663 t = db_read_token(); 9664 if (t == tIDENT) { 9665 dev = device_lookup_by_name(db_tok_string); 9666 t = db_read_token(); 9667 if (t == tNUMBER) { 9668 tid = db_tok_number; 9669 valid = true; 9670 } 9671 } 9672 db_radix = radix; 9673 db_skip_to_eol(); 9674 if (!valid) { 9675 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 9676 return; 9677 } 9678 9679 if (dev == NULL) { 9680 db_printf("device not found\n"); 9681 return; 9682 } 9683 if (tid < 0) { 9684 db_printf("invalid tid\n"); 9685 return; 9686 } 9687 9688 t4_dump_tcb(device_get_softc(dev), tid); 9689 } 9690 #endif 9691 9692 static struct sx mlu; /* mod load unload */ 9693 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 9694 9695 static int 9696 mod_event(module_t mod, int cmd, void *arg) 9697 { 9698 int rc = 0; 9699 static int loaded = 0; 9700 9701 switch (cmd) { 9702 case MOD_LOAD: 9703 sx_xlock(&mlu); 9704 if (loaded++ == 0) { 9705 t4_sge_modload(); 9706 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl); 9707 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl); 9708 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 9709 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 9710 sx_init(&t4_list_lock, "T4/T5 adapters"); 9711 SLIST_INIT(&t4_list); 9712 #ifdef TCP_OFFLOAD 9713 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 9714 SLIST_INIT(&t4_uld_list); 9715 #endif 9716 t4_tracer_modload(); 9717 tweak_tunables(); 9718 } 9719 sx_xunlock(&mlu); 9720 break; 9721 9722 case MOD_UNLOAD: 9723 sx_xlock(&mlu); 9724 if (--loaded == 0) { 9725 int tries; 9726 9727 sx_slock(&t4_list_lock); 9728 if (!SLIST_EMPTY(&t4_list)) { 9729 rc = EBUSY; 9730 sx_sunlock(&t4_list_lock); 9731 goto done_unload; 9732 } 9733 #ifdef TCP_OFFLOAD 9734 sx_slock(&t4_uld_list_lock); 9735 if (!SLIST_EMPTY(&t4_uld_list)) { 9736 rc = EBUSY; 9737 sx_sunlock(&t4_uld_list_lock); 9738 sx_sunlock(&t4_list_lock); 9739 goto done_unload; 9740 } 9741 #endif 9742 tries = 0; 9743 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 9744 uprintf("%ju clusters with custom free routine " 9745 "still is use.\n", t4_sge_extfree_refs()); 9746 pause("t4unload", 2 * hz); 9747 } 9748 #ifdef TCP_OFFLOAD 9749 sx_sunlock(&t4_uld_list_lock); 9750 #endif 9751 sx_sunlock(&t4_list_lock); 9752 9753 if (t4_sge_extfree_refs() == 0) { 9754 t4_tracer_modunload(); 9755 #ifdef TCP_OFFLOAD 9756 sx_destroy(&t4_uld_list_lock); 9757 #endif 9758 sx_destroy(&t4_list_lock); 9759 t4_sge_modunload(); 9760 loaded = 0; 9761 } else { 9762 rc = EBUSY; 9763 loaded++; /* undo earlier decrement */ 9764 } 9765 } 9766 done_unload: 9767 sx_xunlock(&mlu); 9768 break; 9769 } 9770 9771 return (rc); 9772 } 9773 9774 static devclass_t t4_devclass, t5_devclass, t6_devclass; 9775 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 9776 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 9777 9778 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 9779 MODULE_VERSION(t4nex, 1); 9780 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 9781 #ifdef DEV_NETMAP 9782 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 9783 #endif /* DEV_NETMAP */ 9784 9785 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 9786 MODULE_VERSION(t5nex, 1); 9787 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 9788 #ifdef DEV_NETMAP 9789 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 9790 #endif /* DEV_NETMAP */ 9791 9792 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 9793 MODULE_VERSION(t6nex, 1); 9794 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 9795 #ifdef DEV_NETMAP 9796 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 9797 #endif /* DEV_NETMAP */ 9798 9799 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 9800 MODULE_VERSION(cxgbe, 1); 9801 9802 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 9803 MODULE_VERSION(cxl, 1); 9804 9805 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 9806 MODULE_VERSION(cc, 1); 9807 9808 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 9809 MODULE_VERSION(vcxgbe, 1); 9810 9811 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 9812 MODULE_VERSION(vcxl, 1); 9813 9814 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 9815 MODULE_VERSION(vcc, 1); 9816