1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "opt_ddb.h" 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_kern_tls.h" 35 #include "opt_ratelimit.h" 36 #include "opt_rss.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/priv.h> 41 #include <sys/kernel.h> 42 #include <sys/bus.h> 43 #include <sys/eventhandler.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #ifdef KERN_TLS 69 #include <netinet/tcp_seq.h> 70 #endif 71 #if defined(__i386__) || defined(__amd64__) 72 #include <machine/md_var.h> 73 #include <machine/cputypes.h> 74 #include <vm/vm.h> 75 #include <vm/pmap.h> 76 #endif 77 #ifdef DDB 78 #include <ddb/ddb.h> 79 #include <ddb/db_lex.h> 80 #endif 81 82 #include "common/common.h" 83 #include "common/t4_msg.h" 84 #include "common/t4_regs.h" 85 #include "common/t4_regs_values.h" 86 #include "cudbg/cudbg.h" 87 #include "t4_clip.h" 88 #include "t4_ioctl.h" 89 #include "t4_l2t.h" 90 #include "t4_mp_ring.h" 91 #include "t4_if.h" 92 #include "t4_smt.h" 93 94 /* T4 bus driver interface */ 95 static int t4_probe(device_t); 96 static int t4_attach(device_t); 97 static int t4_detach(device_t); 98 static int t4_child_location(device_t, device_t, struct sbuf *); 99 static int t4_ready(device_t); 100 static int t4_read_port_device(device_t, int, device_t *); 101 static int t4_suspend(device_t); 102 static int t4_resume(device_t); 103 static int t4_reset_prepare(device_t, device_t); 104 static int t4_reset_post(device_t, device_t); 105 static device_method_t t4_methods[] = { 106 DEVMETHOD(device_probe, t4_probe), 107 DEVMETHOD(device_attach, t4_attach), 108 DEVMETHOD(device_detach, t4_detach), 109 DEVMETHOD(device_suspend, t4_suspend), 110 DEVMETHOD(device_resume, t4_resume), 111 112 DEVMETHOD(bus_child_location, t4_child_location), 113 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 114 DEVMETHOD(bus_reset_post, t4_reset_post), 115 116 DEVMETHOD(t4_is_main_ready, t4_ready), 117 DEVMETHOD(t4_read_port_device, t4_read_port_device), 118 119 DEVMETHOD_END 120 }; 121 static driver_t t4_driver = { 122 "t4nex", 123 t4_methods, 124 sizeof(struct adapter) 125 }; 126 127 128 /* T4 port (cxgbe) interface */ 129 static int cxgbe_probe(device_t); 130 static int cxgbe_attach(device_t); 131 static int cxgbe_detach(device_t); 132 device_method_t cxgbe_methods[] = { 133 DEVMETHOD(device_probe, cxgbe_probe), 134 DEVMETHOD(device_attach, cxgbe_attach), 135 DEVMETHOD(device_detach, cxgbe_detach), 136 { 0, 0 } 137 }; 138 static driver_t cxgbe_driver = { 139 "cxgbe", 140 cxgbe_methods, 141 sizeof(struct port_info) 142 }; 143 144 /* T4 VI (vcxgbe) interface */ 145 static int vcxgbe_probe(device_t); 146 static int vcxgbe_attach(device_t); 147 static int vcxgbe_detach(device_t); 148 static device_method_t vcxgbe_methods[] = { 149 DEVMETHOD(device_probe, vcxgbe_probe), 150 DEVMETHOD(device_attach, vcxgbe_attach), 151 DEVMETHOD(device_detach, vcxgbe_detach), 152 { 0, 0 } 153 }; 154 static driver_t vcxgbe_driver = { 155 "vcxgbe", 156 vcxgbe_methods, 157 sizeof(struct vi_info) 158 }; 159 160 static d_ioctl_t t4_ioctl; 161 162 static struct cdevsw t4_cdevsw = { 163 .d_version = D_VERSION, 164 .d_ioctl = t4_ioctl, 165 .d_name = "t4nex", 166 }; 167 168 /* T5 bus driver interface */ 169 static int t5_probe(device_t); 170 static device_method_t t5_methods[] = { 171 DEVMETHOD(device_probe, t5_probe), 172 DEVMETHOD(device_attach, t4_attach), 173 DEVMETHOD(device_detach, t4_detach), 174 DEVMETHOD(device_suspend, t4_suspend), 175 DEVMETHOD(device_resume, t4_resume), 176 177 DEVMETHOD(bus_child_location, t4_child_location), 178 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 179 DEVMETHOD(bus_reset_post, t4_reset_post), 180 181 DEVMETHOD(t4_is_main_ready, t4_ready), 182 DEVMETHOD(t4_read_port_device, t4_read_port_device), 183 184 DEVMETHOD_END 185 }; 186 static driver_t t5_driver = { 187 "t5nex", 188 t5_methods, 189 sizeof(struct adapter) 190 }; 191 192 193 /* T5 port (cxl) interface */ 194 static driver_t cxl_driver = { 195 "cxl", 196 cxgbe_methods, 197 sizeof(struct port_info) 198 }; 199 200 /* T5 VI (vcxl) interface */ 201 static driver_t vcxl_driver = { 202 "vcxl", 203 vcxgbe_methods, 204 sizeof(struct vi_info) 205 }; 206 207 /* T6 bus driver interface */ 208 static int t6_probe(device_t); 209 static device_method_t t6_methods[] = { 210 DEVMETHOD(device_probe, t6_probe), 211 DEVMETHOD(device_attach, t4_attach), 212 DEVMETHOD(device_detach, t4_detach), 213 DEVMETHOD(device_suspend, t4_suspend), 214 DEVMETHOD(device_resume, t4_resume), 215 216 DEVMETHOD(bus_child_location, t4_child_location), 217 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 218 DEVMETHOD(bus_reset_post, t4_reset_post), 219 220 DEVMETHOD(t4_is_main_ready, t4_ready), 221 DEVMETHOD(t4_read_port_device, t4_read_port_device), 222 223 DEVMETHOD_END 224 }; 225 static driver_t t6_driver = { 226 "t6nex", 227 t6_methods, 228 sizeof(struct adapter) 229 }; 230 231 232 /* T6 port (cc) interface */ 233 static driver_t cc_driver = { 234 "cc", 235 cxgbe_methods, 236 sizeof(struct port_info) 237 }; 238 239 /* T6 VI (vcc) interface */ 240 static driver_t vcc_driver = { 241 "vcc", 242 vcxgbe_methods, 243 sizeof(struct vi_info) 244 }; 245 246 /* ifnet interface */ 247 static void cxgbe_init(void *); 248 static int cxgbe_ioctl(if_t, unsigned long, caddr_t); 249 static int cxgbe_transmit(if_t, struct mbuf *); 250 static void cxgbe_qflush(if_t); 251 #if defined(KERN_TLS) || defined(RATELIMIT) 252 static int cxgbe_snd_tag_alloc(if_t, union if_snd_tag_alloc_params *, 253 struct m_snd_tag **); 254 #endif 255 256 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 257 258 /* 259 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 260 * then ADAPTER_LOCK, then t4_uld_list_lock. 261 */ 262 static struct sx t4_list_lock; 263 SLIST_HEAD(, adapter) t4_list; 264 #ifdef TCP_OFFLOAD 265 static struct sx t4_uld_list_lock; 266 struct uld_info *t4_uld_list[ULD_MAX + 1]; 267 #endif 268 269 /* 270 * Tunables. See tweak_tunables() too. 271 * 272 * Each tunable is set to a default value here if it's known at compile-time. 273 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 274 * provide a reasonable default (upto n) when the driver is loaded. 275 * 276 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 277 * T5 are under hw.cxl. 278 */ 279 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 280 "cxgbe(4) parameters"); 281 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 282 "cxgbe(4) T5+ parameters"); 283 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 284 "cxgbe(4) TOE parameters"); 285 286 /* 287 * Number of queues for tx and rx, NIC and offload. 288 */ 289 #define NTXQ 16 290 int t4_ntxq = -NTXQ; 291 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 292 "Number of TX queues per port"); 293 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 294 295 #define NRXQ 8 296 int t4_nrxq = -NRXQ; 297 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 298 "Number of RX queues per port"); 299 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 300 301 #define NTXQ_VI 1 302 static int t4_ntxq_vi = -NTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 304 "Number of TX queues per VI"); 305 306 #define NRXQ_VI 1 307 static int t4_nrxq_vi = -NRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 309 "Number of RX queues per VI"); 310 311 static int t4_rsrv_noflowq = 0; 312 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 313 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 314 315 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 316 #define NOFLDTXQ 8 317 static int t4_nofldtxq = -NOFLDTXQ; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 319 "Number of offload TX queues per port"); 320 321 #define NOFLDRXQ 2 322 static int t4_nofldrxq = -NOFLDRXQ; 323 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 324 "Number of offload RX queues per port"); 325 326 #define NOFLDTXQ_VI 1 327 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 328 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 329 "Number of offload TX queues per VI"); 330 331 #define NOFLDRXQ_VI 1 332 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 333 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 334 "Number of offload RX queues per VI"); 335 336 #define TMR_IDX_OFLD 1 337 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 338 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 339 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 340 341 #define PKTC_IDX_OFLD (-1) 342 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 343 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 344 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 345 346 /* 0 means chip/fw default, non-zero number is value in microseconds */ 347 static u_long t4_toe_keepalive_idle = 0; 348 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 349 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 350 351 /* 0 means chip/fw default, non-zero number is value in microseconds */ 352 static u_long t4_toe_keepalive_interval = 0; 353 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 354 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 355 356 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 357 static int t4_toe_keepalive_count = 0; 358 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 359 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 360 361 /* 0 means chip/fw default, non-zero number is value in microseconds */ 362 static u_long t4_toe_rexmt_min = 0; 363 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 365 366 /* 0 means chip/fw default, non-zero number is value in microseconds */ 367 static u_long t4_toe_rexmt_max = 0; 368 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 369 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 370 371 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 372 static int t4_toe_rexmt_count = 0; 373 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 375 376 /* -1 means chip/fw default, other values are raw backoff values to use */ 377 static int t4_toe_rexmt_backoff[16] = { 378 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 379 }; 380 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, 381 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 382 "cxgbe(4) TOE retransmit backoff values"); 383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[0], 0, ""); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[1], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[2], 0, ""); 389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 390 &t4_toe_rexmt_backoff[3], 0, ""); 391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 392 &t4_toe_rexmt_backoff[4], 0, ""); 393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 394 &t4_toe_rexmt_backoff[5], 0, ""); 395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 396 &t4_toe_rexmt_backoff[6], 0, ""); 397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 398 &t4_toe_rexmt_backoff[7], 0, ""); 399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 400 &t4_toe_rexmt_backoff[8], 0, ""); 401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 402 &t4_toe_rexmt_backoff[9], 0, ""); 403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 404 &t4_toe_rexmt_backoff[10], 0, ""); 405 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 406 &t4_toe_rexmt_backoff[11], 0, ""); 407 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 408 &t4_toe_rexmt_backoff[12], 0, ""); 409 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 410 &t4_toe_rexmt_backoff[13], 0, ""); 411 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 412 &t4_toe_rexmt_backoff[14], 0, ""); 413 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 414 &t4_toe_rexmt_backoff[15], 0, ""); 415 416 int t4_ddp_rcvbuf_len = 256 * 1024; 417 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_len, CTLFLAG_RWTUN, 418 &t4_ddp_rcvbuf_len, 0, "length of each DDP RX buffer"); 419 420 unsigned int t4_ddp_rcvbuf_cache = 4; 421 SYSCTL_UINT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_cache, CTLFLAG_RWTUN, 422 &t4_ddp_rcvbuf_cache, 0, 423 "maximum number of free DDP RX buffers to cache per connection"); 424 #endif 425 426 #ifdef DEV_NETMAP 427 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */ 428 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */ 429 static int t4_native_netmap = NN_EXTRA_VI; 430 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap, 431 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs"); 432 433 #define NNMTXQ 8 434 static int t4_nnmtxq = -NNMTXQ; 435 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0, 436 "Number of netmap TX queues"); 437 438 #define NNMRXQ 8 439 static int t4_nnmrxq = -NNMRXQ; 440 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0, 441 "Number of netmap RX queues"); 442 443 #define NNMTXQ_VI 2 444 static int t4_nnmtxq_vi = -NNMTXQ_VI; 445 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 446 "Number of netmap TX queues per VI"); 447 448 #define NNMRXQ_VI 2 449 static int t4_nnmrxq_vi = -NNMRXQ_VI; 450 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 451 "Number of netmap RX queues per VI"); 452 #endif 453 454 /* 455 * Holdoff parameters for ports. 456 */ 457 #define TMR_IDX 1 458 int t4_tmr_idx = TMR_IDX; 459 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 460 0, "Holdoff timer index"); 461 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 462 463 #define PKTC_IDX (-1) 464 int t4_pktc_idx = PKTC_IDX; 465 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 466 0, "Holdoff packet counter index"); 467 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 468 469 /* 470 * Size (# of entries) of each tx and rx queue. 471 */ 472 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 473 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 474 "Number of descriptors in each TX queue"); 475 476 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 477 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 478 "Number of descriptors in each RX queue"); 479 480 /* 481 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 482 */ 483 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 484 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 485 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 486 487 /* 488 * Configuration file. All the _CF names here are special. 489 */ 490 #define DEFAULT_CF "default" 491 #define BUILTIN_CF "built-in" 492 #define FLASH_CF "flash" 493 #define UWIRE_CF "uwire" 494 #define FPGA_CF "fpga" 495 static char t4_cfg_file[32] = DEFAULT_CF; 496 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 497 sizeof(t4_cfg_file), "Firmware configuration file"); 498 499 /* 500 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 501 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 502 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 503 * mark or when signalled to do so, 0 to never emit PAUSE. 504 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 505 * negotiated settings will override rx_pause/tx_pause. 506 * Otherwise rx_pause/tx_pause are applied forcibly. 507 */ 508 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 509 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 510 &t4_pause_settings, 0, 511 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 512 513 /* 514 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 515 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 516 * 0 to disable FEC. 517 */ 518 static int t4_fec = -1; 519 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 520 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 521 522 /* 523 * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it 524 * issues to the firmware. If the firmware doesn't support FORCE_FEC then the 525 * driver runs as if this is set to 0. 526 * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay. 527 * 0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the 528 * transceiver. Multiple FEC bits may not be okay but will be passed on to 529 * the firmware anyway (may result in l1cfg errors with old firmwares). 530 * 1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO 531 * means set all FEC bits that are valid for the speed. 532 */ 533 static int t4_force_fec = -1; 534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0, 535 "Controls the use of FORCE_FEC bit in L1 configuration."); 536 537 /* 538 * Link autonegotiation. 539 * -1 to run with the firmware default. 540 * 0 to disable. 541 * 1 to enable. 542 */ 543 static int t4_autoneg = -1; 544 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 545 "Link autonegotiation"); 546 547 /* 548 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 549 * encouraged respectively). '-n' is the same as 'n' except the firmware 550 * version used in the checks is read from the firmware bundled with the driver. 551 */ 552 static int t4_fw_install = 1; 553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 554 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 555 556 /* 557 * ASIC features that will be used. Disable the ones you don't want so that the 558 * chip resources aren't wasted on features that will not be used. 559 */ 560 static int t4_nbmcaps_allowed = 0; 561 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 562 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 563 564 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 565 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 566 &t4_linkcaps_allowed, 0, "Default link capabilities"); 567 568 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 569 FW_CAPS_CONFIG_SWITCH_EGRESS; 570 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 571 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 572 573 #ifdef RATELIMIT 574 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 575 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 576 #else 577 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 578 FW_CAPS_CONFIG_NIC_HASHFILTER; 579 #endif 580 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 581 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 582 583 static int t4_toecaps_allowed = -1; 584 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 585 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 586 587 static int t4_rdmacaps_allowed = -1; 588 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 589 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 590 591 static int t4_cryptocaps_allowed = -1; 592 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 593 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 594 595 static int t4_iscsicaps_allowed = -1; 596 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 597 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 598 599 static int t4_fcoecaps_allowed = 0; 600 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 601 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 602 603 static int t5_write_combine = 0; 604 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 605 0, "Use WC instead of UC for BAR2"); 606 607 /* From t4_sysctls: doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"} */ 608 static int t4_doorbells_allowed = 0xf; 609 SYSCTL_INT(_hw_cxgbe, OID_AUTO, doorbells_allowed, CTLFLAG_RDTUN, 610 &t4_doorbells_allowed, 0, "Limit tx queues to these doorbells"); 611 612 static int t4_num_vis = 1; 613 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 614 "Number of VIs per port"); 615 616 /* 617 * PCIe Relaxed Ordering. 618 * -1: driver should figure out a good value. 619 * 0: disable RO. 620 * 1: enable RO. 621 * 2: leave RO alone. 622 */ 623 static int pcie_relaxed_ordering = -1; 624 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 625 &pcie_relaxed_ordering, 0, 626 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 627 628 static int t4_panic_on_fatal_err = 0; 629 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN, 630 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 631 632 static int t4_reset_on_fatal_err = 0; 633 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN, 634 &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors"); 635 636 static int t4_clock_gate_on_suspend = 0; 637 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN, 638 &t4_clock_gate_on_suspend, 0, "gate the clock on suspend"); 639 640 static int t4_tx_vm_wr = 0; 641 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0, 642 "Use VM work requests to transmit packets."); 643 644 /* 645 * Set to non-zero to enable the attack filter. A packet that matches any of 646 * these conditions will get dropped on ingress: 647 * 1) IP && source address == destination address. 648 * 2) TCP/IP && source address is not a unicast address. 649 * 3) TCP/IP && destination address is not a unicast address. 650 * 4) IP && source address is loopback (127.x.y.z). 651 * 5) IP && destination address is loopback (127.x.y.z). 652 * 6) IPv6 && source address == destination address. 653 * 7) IPv6 && source address is not a unicast address. 654 * 8) IPv6 && source address is loopback (::1/128). 655 * 9) IPv6 && destination address is loopback (::1/128). 656 * 10) IPv6 && source address is unspecified (::/128). 657 * 11) IPv6 && destination address is unspecified (::/128). 658 * 12) TCP/IPv6 && source address is multicast (ff00::/8). 659 * 13) TCP/IPv6 && destination address is multicast (ff00::/8). 660 */ 661 static int t4_attack_filter = 0; 662 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN, 663 &t4_attack_filter, 0, "Drop suspicious traffic"); 664 665 static int t4_drop_ip_fragments = 0; 666 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN, 667 &t4_drop_ip_fragments, 0, "Drop IP fragments"); 668 669 static int t4_drop_pkts_with_l2_errors = 1; 670 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN, 671 &t4_drop_pkts_with_l2_errors, 0, 672 "Drop all frames with Layer 2 length or checksum errors"); 673 674 static int t4_drop_pkts_with_l3_errors = 0; 675 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN, 676 &t4_drop_pkts_with_l3_errors, 0, 677 "Drop all frames with IP version, length, or checksum errors"); 678 679 static int t4_drop_pkts_with_l4_errors = 0; 680 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN, 681 &t4_drop_pkts_with_l4_errors, 0, 682 "Drop all frames with Layer 4 length, checksum, or other errors"); 683 684 #ifdef TCP_OFFLOAD 685 /* 686 * TOE tunables. 687 */ 688 static int t4_cop_managed_offloading = 0; 689 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 690 &t4_cop_managed_offloading, 0, 691 "COP (Connection Offload Policy) controls all TOE offload"); 692 #endif 693 694 #ifdef KERN_TLS 695 /* 696 * This enables KERN_TLS for all adapters if set. 697 */ 698 static int t4_kern_tls = 0; 699 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0, 700 "Enable KERN_TLS mode for T6 adapters"); 701 702 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 703 "cxgbe(4) KERN_TLS parameters"); 704 705 static int t4_tls_inline_keys = 0; 706 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN, 707 &t4_tls_inline_keys, 0, 708 "Always pass TLS keys in work requests (1) or attempt to store TLS keys " 709 "in card memory."); 710 711 static int t4_tls_combo_wrs = 0; 712 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs, 713 0, "Attempt to combine TCB field updates with TLS record work requests."); 714 #endif 715 716 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 717 static int vi_mac_funcs[] = { 718 FW_VI_FUNC_ETH, 719 FW_VI_FUNC_OFLD, 720 FW_VI_FUNC_IWARP, 721 FW_VI_FUNC_OPENISCSI, 722 FW_VI_FUNC_OPENFCOE, 723 FW_VI_FUNC_FOISCSI, 724 FW_VI_FUNC_FOFCOE, 725 }; 726 727 struct intrs_and_queues { 728 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 729 uint16_t num_vis; /* number of VIs for each port */ 730 uint16_t nirq; /* Total # of vectors */ 731 uint16_t ntxq; /* # of NIC txq's for each port */ 732 uint16_t nrxq; /* # of NIC rxq's for each port */ 733 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 734 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 735 uint16_t nnmtxq; /* # of netmap txq's */ 736 uint16_t nnmrxq; /* # of netmap rxq's */ 737 738 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 739 uint16_t ntxq_vi; /* # of NIC txq's */ 740 uint16_t nrxq_vi; /* # of NIC rxq's */ 741 uint16_t nofldtxq_vi; /* # of TOE txq's */ 742 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 743 uint16_t nnmtxq_vi; /* # of netmap txq's */ 744 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 745 }; 746 747 static void setup_memwin(struct adapter *); 748 static void position_memwin(struct adapter *, int, uint32_t); 749 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 750 static int fwmtype_to_hwmtype(int); 751 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 752 uint32_t *); 753 static int fixup_devlog_params(struct adapter *); 754 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 755 static int contact_firmware(struct adapter *); 756 static int partition_resources(struct adapter *); 757 static int get_params__pre_init(struct adapter *); 758 static int set_params__pre_init(struct adapter *); 759 static int get_params__post_init(struct adapter *); 760 static int set_params__post_init(struct adapter *); 761 static void t4_set_desc(struct adapter *); 762 static bool fixed_ifmedia(struct port_info *); 763 static void build_medialist(struct port_info *); 764 static void init_link_config(struct port_info *); 765 static int fixup_link_config(struct port_info *); 766 static int apply_link_config(struct port_info *); 767 static int cxgbe_init_synchronized(struct vi_info *); 768 static int cxgbe_uninit_synchronized(struct vi_info *); 769 static int adapter_full_init(struct adapter *); 770 static void adapter_full_uninit(struct adapter *); 771 static int vi_full_init(struct vi_info *); 772 static void vi_full_uninit(struct vi_info *); 773 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *); 774 static void quiesce_txq(struct sge_txq *); 775 static void quiesce_wrq(struct sge_wrq *); 776 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 777 static void quiesce_vi(struct vi_info *); 778 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 779 driver_intr_t *, void *, char *); 780 static int t4_free_irq(struct adapter *, struct irq *); 781 static void t4_init_atid_table(struct adapter *); 782 static void t4_free_atid_table(struct adapter *); 783 static void stop_atid_allocator(struct adapter *); 784 static void restart_atid_allocator(struct adapter *); 785 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 786 static void vi_refresh_stats(struct vi_info *); 787 static void cxgbe_refresh_stats(struct vi_info *); 788 static void cxgbe_tick(void *); 789 static void vi_tick(void *); 790 static void cxgbe_sysctls(struct port_info *); 791 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 792 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 793 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 794 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 795 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 796 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS); 797 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 798 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 799 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 800 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 801 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 802 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS); 803 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS); 804 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS); 805 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 806 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS); 807 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 808 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 809 static int sysctl_vdd(SYSCTL_HANDLER_ARGS); 810 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS); 811 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 812 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 813 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 814 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 815 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 816 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 817 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 818 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 819 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 820 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS); 821 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 822 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 823 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 824 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 825 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 826 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 827 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 828 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 829 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 830 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 831 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 832 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 833 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 834 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 835 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS); 836 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 837 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 838 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 839 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 840 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 841 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 842 static int sysctl_reset(SYSCTL_HANDLER_ARGS); 843 #ifdef TCP_OFFLOAD 844 static int sysctl_tls(SYSCTL_HANDLER_ARGS); 845 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 846 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 847 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 848 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 849 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 850 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 851 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 852 #endif 853 static int get_sge_context(struct adapter *, struct t4_sge_context *); 854 static int load_fw(struct adapter *, struct t4_data *); 855 static int load_cfg(struct adapter *, struct t4_data *); 856 static int load_boot(struct adapter *, struct t4_bootrom *); 857 static int load_bootcfg(struct adapter *, struct t4_data *); 858 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 859 static void free_offload_policy(struct t4_offload_policy *); 860 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 861 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 862 static int read_i2c(struct adapter *, struct t4_i2c_data *); 863 static int clear_stats(struct adapter *, u_int); 864 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *); 865 static int release_clip_addr(struct adapter *, struct t4_clip_addr *); 866 static inline int stop_adapter(struct adapter *); 867 static inline void set_adapter_hwstatus(struct adapter *, const bool); 868 static int stop_lld(struct adapter *); 869 static inline int restart_adapter(struct adapter *); 870 static int restart_lld(struct adapter *); 871 #ifdef TCP_OFFLOAD 872 static int toe_capability(struct vi_info *, bool); 873 static int deactivate_all_uld(struct adapter *); 874 static void stop_all_uld(struct adapter *); 875 static void restart_all_uld(struct adapter *); 876 #endif 877 #ifdef KERN_TLS 878 static int ktls_capability(struct adapter *, bool); 879 #endif 880 static int mod_event(module_t, int, void *); 881 static int notify_siblings(device_t, int); 882 static uint64_t vi_get_counter(if_t, ift_counter); 883 static uint64_t cxgbe_get_counter(if_t, ift_counter); 884 static void enable_vxlan_rx(struct adapter *); 885 static void reset_adapter_task(void *, int); 886 static void fatal_error_task(void *, int); 887 static void dump_devlog(struct adapter *); 888 static void dump_cim_regs(struct adapter *); 889 static void dump_cimla(struct adapter *); 890 891 struct { 892 uint16_t device; 893 char *desc; 894 } t4_pciids[] = { 895 {0xa000, "Chelsio Terminator 4 FPGA"}, 896 {0x4400, "Chelsio T440-dbg"}, 897 {0x4401, "Chelsio T420-CR"}, 898 {0x4402, "Chelsio T422-CR"}, 899 {0x4403, "Chelsio T440-CR"}, 900 {0x4404, "Chelsio T420-BCH"}, 901 {0x4405, "Chelsio T440-BCH"}, 902 {0x4406, "Chelsio T440-CH"}, 903 {0x4407, "Chelsio T420-SO"}, 904 {0x4408, "Chelsio T420-CX"}, 905 {0x4409, "Chelsio T420-BT"}, 906 {0x440a, "Chelsio T404-BT"}, 907 {0x440e, "Chelsio T440-LP-CR"}, 908 }, t5_pciids[] = { 909 {0xb000, "Chelsio Terminator 5 FPGA"}, 910 {0x5400, "Chelsio T580-dbg"}, 911 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 912 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 913 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 914 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 915 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 916 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 917 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 918 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 919 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 920 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 921 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 922 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 923 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 924 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 925 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 926 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 927 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 928 929 /* Custom */ 930 {0x5483, "Custom T540-CR"}, 931 {0x5484, "Custom T540-BT"}, 932 }, t6_pciids[] = { 933 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 934 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 935 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 936 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 937 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 938 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 939 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 940 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 941 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 942 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 943 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 944 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 945 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 946 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 947 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 948 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 949 950 /* Custom */ 951 {0x6480, "Custom T6225-CR"}, 952 {0x6481, "Custom T62100-CR"}, 953 {0x6482, "Custom T6225-CR"}, 954 {0x6483, "Custom T62100-CR"}, 955 {0x6484, "Custom T64100-CR"}, 956 {0x6485, "Custom T6240-SO"}, 957 {0x6486, "Custom T6225-SO-CR"}, 958 {0x6487, "Custom T6225-CR"}, 959 }; 960 961 #ifdef TCP_OFFLOAD 962 /* 963 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 964 * be exactly the same for both rxq and ofld_rxq. 965 */ 966 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 967 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 968 #endif 969 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 970 971 static int 972 t4_probe(device_t dev) 973 { 974 int i; 975 uint16_t v = pci_get_vendor(dev); 976 uint16_t d = pci_get_device(dev); 977 uint8_t f = pci_get_function(dev); 978 979 if (v != PCI_VENDOR_ID_CHELSIO) 980 return (ENXIO); 981 982 /* Attach only to PF0 of the FPGA */ 983 if (d == 0xa000 && f != 0) 984 return (ENXIO); 985 986 for (i = 0; i < nitems(t4_pciids); i++) { 987 if (d == t4_pciids[i].device) { 988 device_set_desc(dev, t4_pciids[i].desc); 989 return (BUS_PROBE_DEFAULT); 990 } 991 } 992 993 return (ENXIO); 994 } 995 996 static int 997 t5_probe(device_t dev) 998 { 999 int i; 1000 uint16_t v = pci_get_vendor(dev); 1001 uint16_t d = pci_get_device(dev); 1002 uint8_t f = pci_get_function(dev); 1003 1004 if (v != PCI_VENDOR_ID_CHELSIO) 1005 return (ENXIO); 1006 1007 /* Attach only to PF0 of the FPGA */ 1008 if (d == 0xb000 && f != 0) 1009 return (ENXIO); 1010 1011 for (i = 0; i < nitems(t5_pciids); i++) { 1012 if (d == t5_pciids[i].device) { 1013 device_set_desc(dev, t5_pciids[i].desc); 1014 return (BUS_PROBE_DEFAULT); 1015 } 1016 } 1017 1018 return (ENXIO); 1019 } 1020 1021 static int 1022 t6_probe(device_t dev) 1023 { 1024 int i; 1025 uint16_t v = pci_get_vendor(dev); 1026 uint16_t d = pci_get_device(dev); 1027 1028 if (v != PCI_VENDOR_ID_CHELSIO) 1029 return (ENXIO); 1030 1031 for (i = 0; i < nitems(t6_pciids); i++) { 1032 if (d == t6_pciids[i].device) { 1033 device_set_desc(dev, t6_pciids[i].desc); 1034 return (BUS_PROBE_DEFAULT); 1035 } 1036 } 1037 1038 return (ENXIO); 1039 } 1040 1041 static void 1042 t5_attribute_workaround(device_t dev) 1043 { 1044 device_t root_port; 1045 uint32_t v; 1046 1047 /* 1048 * The T5 chips do not properly echo the No Snoop and Relaxed 1049 * Ordering attributes when replying to a TLP from a Root 1050 * Port. As a workaround, find the parent Root Port and 1051 * disable No Snoop and Relaxed Ordering. Note that this 1052 * affects all devices under this root port. 1053 */ 1054 root_port = pci_find_pcie_root_port(dev); 1055 if (root_port == NULL) { 1056 device_printf(dev, "Unable to find parent root port\n"); 1057 return; 1058 } 1059 1060 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 1061 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 1062 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 1063 0) 1064 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 1065 device_get_nameunit(root_port)); 1066 } 1067 1068 static const struct devnames devnames[] = { 1069 { 1070 .nexus_name = "t4nex", 1071 .ifnet_name = "cxgbe", 1072 .vi_ifnet_name = "vcxgbe", 1073 .pf03_drv_name = "t4iov", 1074 .vf_nexus_name = "t4vf", 1075 .vf_ifnet_name = "cxgbev" 1076 }, { 1077 .nexus_name = "t5nex", 1078 .ifnet_name = "cxl", 1079 .vi_ifnet_name = "vcxl", 1080 .pf03_drv_name = "t5iov", 1081 .vf_nexus_name = "t5vf", 1082 .vf_ifnet_name = "cxlv" 1083 }, { 1084 .nexus_name = "t6nex", 1085 .ifnet_name = "cc", 1086 .vi_ifnet_name = "vcc", 1087 .pf03_drv_name = "t6iov", 1088 .vf_nexus_name = "t6vf", 1089 .vf_ifnet_name = "ccv" 1090 } 1091 }; 1092 1093 void 1094 t4_init_devnames(struct adapter *sc) 1095 { 1096 int id; 1097 1098 id = chip_id(sc); 1099 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 1100 sc->names = &devnames[id - CHELSIO_T4]; 1101 else { 1102 device_printf(sc->dev, "chip id %d is not supported.\n", id); 1103 sc->names = NULL; 1104 } 1105 } 1106 1107 static int 1108 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 1109 { 1110 const char *parent, *name; 1111 long value; 1112 int line, unit; 1113 1114 line = 0; 1115 parent = device_get_nameunit(sc->dev); 1116 name = sc->names->ifnet_name; 1117 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 1118 if (resource_long_value(name, unit, "port", &value) == 0 && 1119 value == pi->port_id) 1120 return (unit); 1121 } 1122 return (-1); 1123 } 1124 1125 static void 1126 t4_calibration(void *arg) 1127 { 1128 struct adapter *sc; 1129 struct clock_sync *cur, *nex; 1130 uint64_t hw; 1131 sbintime_t sbt; 1132 int next_up; 1133 1134 sc = (struct adapter *)arg; 1135 1136 KASSERT((hw_off_limits(sc) == 0), ("hw_off_limits at t4_calibration")); 1137 hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO); 1138 sbt = sbinuptime(); 1139 1140 cur = &sc->cal_info[sc->cal_current]; 1141 next_up = (sc->cal_current + 1) % CNT_CAL_INFO; 1142 nex = &sc->cal_info[next_up]; 1143 if (__predict_false(sc->cal_count == 0)) { 1144 /* First time in, just get the values in */ 1145 cur->hw_cur = hw; 1146 cur->sbt_cur = sbt; 1147 sc->cal_count++; 1148 goto done; 1149 } 1150 1151 if (cur->hw_cur == hw) { 1152 /* The clock is not advancing? */ 1153 sc->cal_count = 0; 1154 atomic_store_rel_int(&cur->gen, 0); 1155 goto done; 1156 } 1157 1158 seqc_write_begin(&nex->gen); 1159 nex->hw_prev = cur->hw_cur; 1160 nex->sbt_prev = cur->sbt_cur; 1161 nex->hw_cur = hw; 1162 nex->sbt_cur = sbt; 1163 seqc_write_end(&nex->gen); 1164 sc->cal_current = next_up; 1165 done: 1166 callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration, 1167 sc, C_DIRECT_EXEC); 1168 } 1169 1170 static void 1171 t4_calibration_start(struct adapter *sc) 1172 { 1173 /* 1174 * Here if we have not done a calibration 1175 * then do so otherwise start the appropriate 1176 * timer. 1177 */ 1178 int i; 1179 1180 for (i = 0; i < CNT_CAL_INFO; i++) { 1181 sc->cal_info[i].gen = 0; 1182 } 1183 sc->cal_current = 0; 1184 sc->cal_count = 0; 1185 sc->cal_gen = 0; 1186 t4_calibration(sc); 1187 } 1188 1189 static int 1190 t4_attach(device_t dev) 1191 { 1192 struct adapter *sc; 1193 int rc = 0, i, j, rqidx, tqidx, nports; 1194 struct make_dev_args mda; 1195 struct intrs_and_queues iaq; 1196 struct sge *s; 1197 uint32_t *buf; 1198 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1199 int ofld_tqidx; 1200 #endif 1201 #ifdef TCP_OFFLOAD 1202 int ofld_rqidx; 1203 #endif 1204 #ifdef DEV_NETMAP 1205 int nm_rqidx, nm_tqidx; 1206 #endif 1207 int num_vis; 1208 1209 sc = device_get_softc(dev); 1210 sc->dev = dev; 1211 sysctl_ctx_init(&sc->ctx); 1212 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 1213 1214 if ((pci_get_device(dev) & 0xff00) == 0x5400) 1215 t5_attribute_workaround(dev); 1216 pci_enable_busmaster(dev); 1217 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 1218 uint32_t v; 1219 1220 pci_set_max_read_req(dev, 4096); 1221 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 1222 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 1223 if (pcie_relaxed_ordering == 0 && 1224 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 1225 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 1226 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1227 } else if (pcie_relaxed_ordering == 1 && 1228 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 1229 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 1230 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1231 } 1232 } 1233 1234 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 1235 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 1236 sc->traceq = -1; 1237 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 1238 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 1239 device_get_nameunit(dev)); 1240 1241 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 1242 device_get_nameunit(dev)); 1243 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 1244 t4_add_adapter(sc); 1245 1246 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 1247 TAILQ_INIT(&sc->sfl); 1248 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 1249 1250 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 1251 1252 sc->policy = NULL; 1253 rw_init(&sc->policy_lock, "connection offload policy"); 1254 1255 callout_init(&sc->ktls_tick, 1); 1256 1257 callout_init(&sc->cal_callout, 1); 1258 1259 refcount_init(&sc->vxlan_refcount, 0); 1260 1261 TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc); 1262 TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc); 1263 1264 sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1265 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq", 1266 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 1267 sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1268 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq", 1269 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 1270 1271 rc = t4_map_bars_0_and_4(sc); 1272 if (rc != 0) 1273 goto done; /* error message displayed already */ 1274 1275 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1276 1277 /* Prepare the adapter for operation. */ 1278 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1279 rc = -t4_prep_adapter(sc, buf); 1280 free(buf, M_CXGBE); 1281 if (rc != 0) { 1282 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1283 goto done; 1284 } 1285 1286 /* 1287 * This is the real PF# to which we're attaching. Works from within PCI 1288 * passthrough environments too, where pci_get_function() could return a 1289 * different PF# depending on the passthrough configuration. We need to 1290 * use the real PF# in all our communication with the firmware. 1291 */ 1292 j = t4_read_reg(sc, A_PL_WHOAMI); 1293 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1294 sc->mbox = sc->pf; 1295 1296 t4_init_devnames(sc); 1297 if (sc->names == NULL) { 1298 rc = ENOTSUP; 1299 goto done; /* error message displayed already */ 1300 } 1301 1302 /* 1303 * Do this really early, with the memory windows set up even before the 1304 * character device. The userland tool's register i/o and mem read 1305 * will work even in "recovery mode". 1306 */ 1307 setup_memwin(sc); 1308 if (t4_init_devlog_params(sc, 0) == 0) 1309 fixup_devlog_params(sc); 1310 make_dev_args_init(&mda); 1311 mda.mda_devsw = &t4_cdevsw; 1312 mda.mda_uid = UID_ROOT; 1313 mda.mda_gid = GID_WHEEL; 1314 mda.mda_mode = 0600; 1315 mda.mda_si_drv1 = sc; 1316 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1317 if (rc != 0) 1318 device_printf(dev, "failed to create nexus char device: %d.\n", 1319 rc); 1320 1321 /* Go no further if recovery mode has been requested. */ 1322 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1323 device_printf(dev, "recovery mode.\n"); 1324 goto done; 1325 } 1326 1327 #if defined(__i386__) 1328 if ((cpu_feature & CPUID_CX8) == 0) { 1329 device_printf(dev, "64 bit atomics not available.\n"); 1330 rc = ENOTSUP; 1331 goto done; 1332 } 1333 #endif 1334 1335 /* Contact the firmware and try to become the master driver. */ 1336 rc = contact_firmware(sc); 1337 if (rc != 0) 1338 goto done; /* error message displayed already */ 1339 MPASS(sc->flags & FW_OK); 1340 1341 rc = get_params__pre_init(sc); 1342 if (rc != 0) 1343 goto done; /* error message displayed already */ 1344 1345 if (sc->flags & MASTER_PF) { 1346 rc = partition_resources(sc); 1347 if (rc != 0) 1348 goto done; /* error message displayed already */ 1349 } 1350 1351 rc = get_params__post_init(sc); 1352 if (rc != 0) 1353 goto done; /* error message displayed already */ 1354 1355 rc = set_params__post_init(sc); 1356 if (rc != 0) 1357 goto done; /* error message displayed already */ 1358 1359 rc = t4_map_bar_2(sc); 1360 if (rc != 0) 1361 goto done; /* error message displayed already */ 1362 1363 rc = t4_adj_doorbells(sc); 1364 if (rc != 0) 1365 goto done; /* error message displayed already */ 1366 1367 rc = t4_create_dma_tag(sc); 1368 if (rc != 0) 1369 goto done; /* error message displayed already */ 1370 1371 /* 1372 * First pass over all the ports - allocate VIs and initialize some 1373 * basic parameters like mac address, port type, etc. 1374 */ 1375 for_each_port(sc, i) { 1376 struct port_info *pi; 1377 1378 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1379 sc->port[i] = pi; 1380 1381 /* These must be set before t4_port_init */ 1382 pi->adapter = sc; 1383 pi->port_id = i; 1384 /* 1385 * XXX: vi[0] is special so we can't delay this allocation until 1386 * pi->nvi's final value is known. 1387 */ 1388 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1389 M_ZERO | M_WAITOK); 1390 1391 /* 1392 * Allocate the "main" VI and initialize parameters 1393 * like mac addr. 1394 */ 1395 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1396 if (rc != 0) { 1397 device_printf(dev, "unable to initialize port %d: %d\n", 1398 i, rc); 1399 free(pi->vi, M_CXGBE); 1400 free(pi, M_CXGBE); 1401 sc->port[i] = NULL; 1402 goto done; 1403 } 1404 1405 if (is_bt(pi->port_type)) 1406 setbit(&sc->bt_map, pi->tx_chan); 1407 else 1408 MPASS(!isset(&sc->bt_map, pi->tx_chan)); 1409 1410 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1411 device_get_nameunit(dev), i); 1412 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1413 sc->chan_map[pi->tx_chan] = i; 1414 1415 /* 1416 * The MPS counter for FCS errors doesn't work correctly on the 1417 * T6 so we use the MAC counter here. Which MAC is in use 1418 * depends on the link settings which will be known when the 1419 * link comes up. 1420 */ 1421 if (is_t6(sc)) 1422 pi->fcs_reg = -1; 1423 else { 1424 pi->fcs_reg = t4_port_reg(sc, pi->tx_chan, 1425 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1426 } 1427 pi->fcs_base = 0; 1428 1429 /* All VIs on this port share this media. */ 1430 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1431 cxgbe_media_status); 1432 1433 PORT_LOCK(pi); 1434 init_link_config(pi); 1435 fixup_link_config(pi); 1436 build_medialist(pi); 1437 if (fixed_ifmedia(pi)) 1438 pi->flags |= FIXED_IFMEDIA; 1439 PORT_UNLOCK(pi); 1440 1441 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1442 t4_ifnet_unit(sc, pi)); 1443 if (pi->dev == NULL) { 1444 device_printf(dev, 1445 "failed to add device for port %d.\n", i); 1446 rc = ENXIO; 1447 goto done; 1448 } 1449 pi->vi[0].dev = pi->dev; 1450 device_set_softc(pi->dev, pi); 1451 } 1452 1453 /* 1454 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1455 */ 1456 nports = sc->params.nports; 1457 rc = cfg_itype_and_nqueues(sc, &iaq); 1458 if (rc != 0) 1459 goto done; /* error message displayed already */ 1460 1461 num_vis = iaq.num_vis; 1462 sc->intr_type = iaq.intr_type; 1463 sc->intr_count = iaq.nirq; 1464 1465 s = &sc->sge; 1466 s->nrxq = nports * iaq.nrxq; 1467 s->ntxq = nports * iaq.ntxq; 1468 if (num_vis > 1) { 1469 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1470 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1471 } 1472 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1473 s->neq += nports; /* ctrl queues: 1 per port */ 1474 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1475 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1476 if (is_offload(sc) || is_ethoffload(sc)) { 1477 s->nofldtxq = nports * iaq.nofldtxq; 1478 if (num_vis > 1) 1479 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1480 s->neq += s->nofldtxq; 1481 1482 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq), 1483 M_CXGBE, M_ZERO | M_WAITOK); 1484 } 1485 #endif 1486 #ifdef TCP_OFFLOAD 1487 if (is_offload(sc)) { 1488 s->nofldrxq = nports * iaq.nofldrxq; 1489 if (num_vis > 1) 1490 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1491 s->neq += s->nofldrxq; /* free list */ 1492 s->niq += s->nofldrxq; 1493 1494 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1495 M_CXGBE, M_ZERO | M_WAITOK); 1496 } 1497 #endif 1498 #ifdef DEV_NETMAP 1499 s->nnmrxq = 0; 1500 s->nnmtxq = 0; 1501 if (t4_native_netmap & NN_MAIN_VI) { 1502 s->nnmrxq += nports * iaq.nnmrxq; 1503 s->nnmtxq += nports * iaq.nnmtxq; 1504 } 1505 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) { 1506 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi; 1507 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi; 1508 } 1509 s->neq += s->nnmtxq + s->nnmrxq; 1510 s->niq += s->nnmrxq; 1511 1512 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1513 M_CXGBE, M_ZERO | M_WAITOK); 1514 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1515 M_CXGBE, M_ZERO | M_WAITOK); 1516 #endif 1517 MPASS(s->niq <= s->iqmap_sz); 1518 MPASS(s->neq <= s->eqmap_sz); 1519 1520 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1521 M_ZERO | M_WAITOK); 1522 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1523 M_ZERO | M_WAITOK); 1524 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1525 M_ZERO | M_WAITOK); 1526 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE, 1527 M_ZERO | M_WAITOK); 1528 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE, 1529 M_ZERO | M_WAITOK); 1530 1531 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1532 M_ZERO | M_WAITOK); 1533 1534 t4_init_l2t(sc, M_WAITOK); 1535 t4_init_smt(sc, M_WAITOK); 1536 t4_init_tx_sched(sc); 1537 t4_init_atid_table(sc); 1538 #ifdef RATELIMIT 1539 t4_init_etid_table(sc); 1540 #endif 1541 #ifdef INET6 1542 t4_init_clip_table(sc); 1543 #endif 1544 if (sc->vres.key.size != 0) 1545 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1546 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1547 1548 /* 1549 * Second pass over the ports. This time we know the number of rx and 1550 * tx queues that each port should get. 1551 */ 1552 rqidx = tqidx = 0; 1553 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1554 ofld_tqidx = 0; 1555 #endif 1556 #ifdef TCP_OFFLOAD 1557 ofld_rqidx = 0; 1558 #endif 1559 #ifdef DEV_NETMAP 1560 nm_rqidx = nm_tqidx = 0; 1561 #endif 1562 for_each_port(sc, i) { 1563 struct port_info *pi = sc->port[i]; 1564 struct vi_info *vi; 1565 1566 if (pi == NULL) 1567 continue; 1568 1569 pi->nvi = num_vis; 1570 for_each_vi(pi, j, vi) { 1571 vi->pi = pi; 1572 vi->adapter = sc; 1573 vi->first_intr = -1; 1574 vi->qsize_rxq = t4_qsize_rxq; 1575 vi->qsize_txq = t4_qsize_txq; 1576 1577 vi->first_rxq = rqidx; 1578 vi->first_txq = tqidx; 1579 vi->tmr_idx = t4_tmr_idx; 1580 vi->pktc_idx = t4_pktc_idx; 1581 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1582 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1583 1584 rqidx += vi->nrxq; 1585 tqidx += vi->ntxq; 1586 1587 if (j == 0 && vi->ntxq > 1) 1588 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1589 else 1590 vi->rsrv_noflowq = 0; 1591 1592 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1593 vi->first_ofld_txq = ofld_tqidx; 1594 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1595 ofld_tqidx += vi->nofldtxq; 1596 #endif 1597 #ifdef TCP_OFFLOAD 1598 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1599 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1600 vi->first_ofld_rxq = ofld_rqidx; 1601 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1602 1603 ofld_rqidx += vi->nofldrxq; 1604 #endif 1605 #ifdef DEV_NETMAP 1606 vi->first_nm_rxq = nm_rqidx; 1607 vi->first_nm_txq = nm_tqidx; 1608 if (j == 0) { 1609 vi->nnmrxq = iaq.nnmrxq; 1610 vi->nnmtxq = iaq.nnmtxq; 1611 } else { 1612 vi->nnmrxq = iaq.nnmrxq_vi; 1613 vi->nnmtxq = iaq.nnmtxq_vi; 1614 } 1615 nm_rqidx += vi->nnmrxq; 1616 nm_tqidx += vi->nnmtxq; 1617 #endif 1618 } 1619 } 1620 1621 rc = t4_setup_intr_handlers(sc); 1622 if (rc != 0) { 1623 device_printf(dev, 1624 "failed to setup interrupt handlers: %d\n", rc); 1625 goto done; 1626 } 1627 1628 rc = bus_generic_probe(dev); 1629 if (rc != 0) { 1630 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1631 goto done; 1632 } 1633 1634 /* 1635 * Ensure thread-safe mailbox access (in debug builds). 1636 * 1637 * So far this was the only thread accessing the mailbox but various 1638 * ifnets and sysctls are about to be created and their handlers/ioctls 1639 * will access the mailbox from different threads. 1640 */ 1641 sc->flags |= CHK_MBOX_ACCESS; 1642 1643 rc = bus_generic_attach(dev); 1644 if (rc != 0) { 1645 device_printf(dev, 1646 "failed to attach all child ports: %d\n", rc); 1647 goto done; 1648 } 1649 t4_calibration_start(sc); 1650 1651 device_printf(dev, 1652 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1653 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1654 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1655 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1656 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1657 1658 t4_set_desc(sc); 1659 1660 notify_siblings(dev, 0); 1661 1662 done: 1663 if (rc != 0 && sc->cdev) { 1664 /* cdev was created and so cxgbetool works; recover that way. */ 1665 device_printf(dev, 1666 "error during attach, adapter is now in recovery mode.\n"); 1667 rc = 0; 1668 } 1669 1670 if (rc != 0) 1671 t4_detach_common(dev); 1672 else 1673 t4_sysctls(sc); 1674 1675 return (rc); 1676 } 1677 1678 static int 1679 t4_child_location(device_t bus, device_t dev, struct sbuf *sb) 1680 { 1681 struct adapter *sc; 1682 struct port_info *pi; 1683 int i; 1684 1685 sc = device_get_softc(bus); 1686 for_each_port(sc, i) { 1687 pi = sc->port[i]; 1688 if (pi != NULL && pi->dev == dev) { 1689 sbuf_printf(sb, "port=%d", pi->port_id); 1690 break; 1691 } 1692 } 1693 return (0); 1694 } 1695 1696 static int 1697 t4_ready(device_t dev) 1698 { 1699 struct adapter *sc; 1700 1701 sc = device_get_softc(dev); 1702 if (sc->flags & FW_OK) 1703 return (0); 1704 return (ENXIO); 1705 } 1706 1707 static int 1708 t4_read_port_device(device_t dev, int port, device_t *child) 1709 { 1710 struct adapter *sc; 1711 struct port_info *pi; 1712 1713 sc = device_get_softc(dev); 1714 if (port < 0 || port >= MAX_NPORTS) 1715 return (EINVAL); 1716 pi = sc->port[port]; 1717 if (pi == NULL || pi->dev == NULL) 1718 return (ENXIO); 1719 *child = pi->dev; 1720 return (0); 1721 } 1722 1723 static int 1724 notify_siblings(device_t dev, int detaching) 1725 { 1726 device_t sibling; 1727 int error, i; 1728 1729 error = 0; 1730 for (i = 0; i < PCI_FUNCMAX; i++) { 1731 if (i == pci_get_function(dev)) 1732 continue; 1733 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1734 pci_get_slot(dev), i); 1735 if (sibling == NULL || !device_is_attached(sibling)) 1736 continue; 1737 if (detaching) 1738 error = T4_DETACH_CHILD(sibling); 1739 else 1740 (void)T4_ATTACH_CHILD(sibling); 1741 if (error) 1742 break; 1743 } 1744 return (error); 1745 } 1746 1747 /* 1748 * Idempotent 1749 */ 1750 static int 1751 t4_detach(device_t dev) 1752 { 1753 int rc; 1754 1755 rc = notify_siblings(dev, 1); 1756 if (rc) { 1757 device_printf(dev, 1758 "failed to detach sibling devices: %d\n", rc); 1759 return (rc); 1760 } 1761 1762 return (t4_detach_common(dev)); 1763 } 1764 1765 int 1766 t4_detach_common(device_t dev) 1767 { 1768 struct adapter *sc; 1769 struct port_info *pi; 1770 int i, rc; 1771 1772 sc = device_get_softc(dev); 1773 1774 #ifdef TCP_OFFLOAD 1775 rc = deactivate_all_uld(sc); 1776 if (rc) { 1777 device_printf(dev, 1778 "failed to detach upper layer drivers: %d\n", rc); 1779 return (rc); 1780 } 1781 #endif 1782 1783 if (sc->cdev) { 1784 destroy_dev(sc->cdev); 1785 sc->cdev = NULL; 1786 } 1787 1788 sx_xlock(&t4_list_lock); 1789 SLIST_REMOVE(&t4_list, sc, adapter, link); 1790 sx_xunlock(&t4_list_lock); 1791 1792 sc->flags &= ~CHK_MBOX_ACCESS; 1793 if (sc->flags & FULL_INIT_DONE) { 1794 if (!(sc->flags & IS_VF)) 1795 t4_intr_disable(sc); 1796 } 1797 1798 if (device_is_attached(dev)) { 1799 rc = bus_generic_detach(dev); 1800 if (rc) { 1801 device_printf(dev, 1802 "failed to detach child devices: %d\n", rc); 1803 return (rc); 1804 } 1805 } 1806 1807 for (i = 0; i < sc->intr_count; i++) 1808 t4_free_irq(sc, &sc->irq[i]); 1809 1810 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1811 t4_free_tx_sched(sc); 1812 1813 for (i = 0; i < MAX_NPORTS; i++) { 1814 pi = sc->port[i]; 1815 if (pi) { 1816 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1817 if (pi->dev) 1818 device_delete_child(dev, pi->dev); 1819 1820 mtx_destroy(&pi->pi_lock); 1821 free(pi->vi, M_CXGBE); 1822 free(pi, M_CXGBE); 1823 } 1824 } 1825 callout_stop(&sc->cal_callout); 1826 callout_drain(&sc->cal_callout); 1827 device_delete_children(dev); 1828 sysctl_ctx_free(&sc->ctx); 1829 adapter_full_uninit(sc); 1830 1831 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1832 t4_fw_bye(sc, sc->mbox); 1833 1834 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1835 pci_release_msi(dev); 1836 1837 if (sc->regs_res) 1838 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1839 sc->regs_res); 1840 1841 if (sc->udbs_res) 1842 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1843 sc->udbs_res); 1844 1845 if (sc->msix_res) 1846 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1847 sc->msix_res); 1848 1849 if (sc->l2t) 1850 t4_free_l2t(sc); 1851 if (sc->smt) 1852 t4_free_smt(sc->smt); 1853 t4_free_atid_table(sc); 1854 #ifdef RATELIMIT 1855 t4_free_etid_table(sc); 1856 #endif 1857 if (sc->key_map) 1858 vmem_destroy(sc->key_map); 1859 #ifdef INET6 1860 t4_destroy_clip_table(sc); 1861 #endif 1862 1863 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1864 free(sc->sge.ofld_txq, M_CXGBE); 1865 #endif 1866 #ifdef TCP_OFFLOAD 1867 free(sc->sge.ofld_rxq, M_CXGBE); 1868 #endif 1869 #ifdef DEV_NETMAP 1870 free(sc->sge.nm_rxq, M_CXGBE); 1871 free(sc->sge.nm_txq, M_CXGBE); 1872 #endif 1873 free(sc->irq, M_CXGBE); 1874 free(sc->sge.rxq, M_CXGBE); 1875 free(sc->sge.txq, M_CXGBE); 1876 free(sc->sge.ctrlq, M_CXGBE); 1877 free(sc->sge.iqmap, M_CXGBE); 1878 free(sc->sge.eqmap, M_CXGBE); 1879 free(sc->tids.ftid_tab, M_CXGBE); 1880 free(sc->tids.hpftid_tab, M_CXGBE); 1881 free_hftid_hash(&sc->tids); 1882 free(sc->tids.tid_tab, M_CXGBE); 1883 t4_destroy_dma_tag(sc); 1884 1885 callout_drain(&sc->ktls_tick); 1886 callout_drain(&sc->sfl_callout); 1887 if (mtx_initialized(&sc->tids.ftid_lock)) { 1888 mtx_destroy(&sc->tids.ftid_lock); 1889 cv_destroy(&sc->tids.ftid_cv); 1890 } 1891 if (mtx_initialized(&sc->tids.atid_lock)) 1892 mtx_destroy(&sc->tids.atid_lock); 1893 if (mtx_initialized(&sc->ifp_lock)) 1894 mtx_destroy(&sc->ifp_lock); 1895 1896 if (rw_initialized(&sc->policy_lock)) { 1897 rw_destroy(&sc->policy_lock); 1898 #ifdef TCP_OFFLOAD 1899 if (sc->policy != NULL) 1900 free_offload_policy(sc->policy); 1901 #endif 1902 } 1903 1904 for (i = 0; i < NUM_MEMWIN; i++) { 1905 struct memwin *mw = &sc->memwin[i]; 1906 1907 if (rw_initialized(&mw->mw_lock)) 1908 rw_destroy(&mw->mw_lock); 1909 } 1910 1911 mtx_destroy(&sc->sfl_lock); 1912 mtx_destroy(&sc->reg_lock); 1913 mtx_destroy(&sc->sc_lock); 1914 1915 bzero(sc, sizeof(*sc)); 1916 1917 return (0); 1918 } 1919 1920 static inline int 1921 stop_adapter(struct adapter *sc) 1922 { 1923 struct port_info *pi; 1924 int i; 1925 1926 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) { 1927 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n", 1928 __func__, curthread, sc->flags, sc->error_flags); 1929 return (EALREADY); 1930 } 1931 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread, 1932 sc->flags, sc->error_flags); 1933 t4_shutdown_adapter(sc); 1934 for_each_port(sc, i) { 1935 pi = sc->port[i]; 1936 PORT_LOCK(pi); 1937 if (pi->up_vis > 0 && pi->link_cfg.link_ok) { 1938 /* 1939 * t4_shutdown_adapter has already shut down all the 1940 * PHYs but it also disables interrupts and DMA so there 1941 * won't be a link interrupt. Update the state manually 1942 * if the link was up previously and inform the kernel. 1943 */ 1944 pi->link_cfg.link_ok = false; 1945 t4_os_link_changed(pi); 1946 } 1947 PORT_UNLOCK(pi); 1948 } 1949 1950 return (0); 1951 } 1952 1953 static inline int 1954 restart_adapter(struct adapter *sc) 1955 { 1956 uint32_t val; 1957 1958 if (!atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_STOPPED))) { 1959 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n", 1960 __func__, curthread, sc->flags, sc->error_flags); 1961 return (EALREADY); 1962 } 1963 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread, 1964 sc->flags, sc->error_flags); 1965 1966 MPASS(hw_off_limits(sc)); 1967 MPASS((sc->flags & FW_OK) == 0); 1968 MPASS((sc->flags & MASTER_PF) == 0); 1969 MPASS(sc->reset_thread == NULL); 1970 1971 /* 1972 * The adapter is supposed to be back on PCIE with its config space and 1973 * BARs restored to their state before reset. Register access via 1974 * t4_read_reg BAR0 should just work. 1975 */ 1976 sc->reset_thread = curthread; 1977 val = t4_read_reg(sc, A_PL_WHOAMI); 1978 if (val == 0xffffffff || val == 0xeeeeeeee) { 1979 CH_ERR(sc, "%s: device registers not readable.\n", __func__); 1980 sc->reset_thread = NULL; 1981 atomic_set_int(&sc->error_flags, ADAP_STOPPED); 1982 return (ENXIO); 1983 } 1984 atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR); 1985 atomic_add_int(&sc->incarnation, 1); 1986 atomic_add_int(&sc->num_resets, 1); 1987 1988 return (0); 1989 } 1990 1991 static inline void 1992 set_adapter_hwstatus(struct adapter *sc, const bool usable) 1993 { 1994 mtx_lock(&sc->reg_lock); 1995 if (usable) { 1996 /* Must be marked reusable by the designated thread. */ 1997 MPASS(sc->reset_thread == curthread); 1998 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 1999 } else { 2000 /* Mark the adapter totally off limits. */ 2001 atomic_set_int(&sc->error_flags, HW_OFF_LIMITS); 2002 sc->flags &= ~(FW_OK | MASTER_PF); 2003 sc->reset_thread = NULL; 2004 } 2005 mtx_unlock(&sc->reg_lock); 2006 } 2007 2008 static int 2009 stop_lld(struct adapter *sc) 2010 { 2011 struct port_info *pi; 2012 struct vi_info *vi; 2013 if_t ifp; 2014 struct sge_rxq *rxq; 2015 struct sge_txq *txq; 2016 struct sge_wrq *wrq; 2017 #ifdef TCP_OFFLOAD 2018 struct sge_ofld_rxq *ofld_rxq; 2019 #endif 2020 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2021 struct sge_ofld_txq *ofld_txq; 2022 #endif 2023 int rc, i, j, k; 2024 2025 /* 2026 * XXX: Can there be a synch_op in progress that will hang because 2027 * hardware has been stopped? We'll hang too and the solution will be 2028 * to use a version of begin_synch_op that wakes up existing synch_op 2029 * with errors. Maybe stop_adapter should do this wakeup? 2030 * 2031 * I don't think any synch_op could get stranded waiting for DMA or 2032 * interrupt so I think we're okay here. Remove this comment block 2033 * after testing. 2034 */ 2035 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4slld"); 2036 if (rc != 0) 2037 return (ENXIO); 2038 2039 /* Quiesce all activity. */ 2040 for_each_port(sc, i) { 2041 pi = sc->port[i]; 2042 pi->vxlan_tcam_entry = false; 2043 for_each_vi(pi, j, vi) { 2044 vi->xact_addr_filt = -1; 2045 mtx_lock(&vi->tick_mtx); 2046 vi->flags |= VI_SKIP_STATS; 2047 mtx_unlock(&vi->tick_mtx); 2048 if (!(vi->flags & VI_INIT_DONE)) 2049 continue; 2050 2051 ifp = vi->ifp; 2052 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2053 mtx_lock(&vi->tick_mtx); 2054 callout_stop(&vi->tick); 2055 mtx_unlock(&vi->tick_mtx); 2056 callout_drain(&vi->tick); 2057 } 2058 2059 /* 2060 * Note that the HW is not available. 2061 */ 2062 for_each_txq(vi, k, txq) { 2063 TXQ_LOCK(txq); 2064 txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED); 2065 TXQ_UNLOCK(txq); 2066 } 2067 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2068 for_each_ofld_txq(vi, k, ofld_txq) { 2069 TXQ_LOCK(&ofld_txq->wrq); 2070 ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED; 2071 TXQ_UNLOCK(&ofld_txq->wrq); 2072 } 2073 #endif 2074 for_each_rxq(vi, k, rxq) { 2075 rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2076 } 2077 #if defined(TCP_OFFLOAD) 2078 for_each_ofld_rxq(vi, k, ofld_rxq) { 2079 ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2080 } 2081 #endif 2082 2083 quiesce_vi(vi); 2084 } 2085 2086 if (sc->flags & FULL_INIT_DONE) { 2087 /* Control queue */ 2088 wrq = &sc->sge.ctrlq[i]; 2089 TXQ_LOCK(wrq); 2090 wrq->eq.flags &= ~EQ_HW_ALLOCATED; 2091 TXQ_UNLOCK(wrq); 2092 quiesce_wrq(wrq); 2093 } 2094 2095 if (pi->flags & HAS_TRACEQ) { 2096 pi->flags &= ~HAS_TRACEQ; 2097 sc->traceq = -1; 2098 } 2099 } 2100 if (sc->flags & FULL_INIT_DONE) { 2101 /* Firmware event queue */ 2102 sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED; 2103 quiesce_iq_fl(sc, &sc->sge.fwq, NULL); 2104 } 2105 2106 /* Stop calibration */ 2107 callout_stop(&sc->cal_callout); 2108 callout_drain(&sc->cal_callout); 2109 2110 if (t4_clock_gate_on_suspend) { 2111 t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN | 2112 F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN | 2113 F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0); 2114 } 2115 2116 end_synchronized_op(sc, 0); 2117 2118 stop_atid_allocator(sc); 2119 t4_stop_l2t(sc); 2120 2121 return (rc); 2122 } 2123 2124 int 2125 suspend_adapter(struct adapter *sc) 2126 { 2127 stop_adapter(sc); 2128 stop_lld(sc); 2129 #ifdef TCP_OFFLOAD 2130 stop_all_uld(sc); 2131 #endif 2132 set_adapter_hwstatus(sc, false); 2133 2134 return (0); 2135 } 2136 2137 static int 2138 t4_suspend(device_t dev) 2139 { 2140 struct adapter *sc = device_get_softc(dev); 2141 int rc; 2142 2143 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2144 rc = suspend_adapter(sc); 2145 CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread); 2146 2147 return (rc); 2148 } 2149 2150 struct adapter_pre_reset_state { 2151 u_int flags; 2152 uint16_t nbmcaps; 2153 uint16_t linkcaps; 2154 uint16_t switchcaps; 2155 uint16_t niccaps; 2156 uint16_t toecaps; 2157 uint16_t rdmacaps; 2158 uint16_t cryptocaps; 2159 uint16_t iscsicaps; 2160 uint16_t fcoecaps; 2161 2162 u_int cfcsum; 2163 char cfg_file[32]; 2164 2165 struct adapter_params params; 2166 struct t4_virt_res vres; 2167 struct tid_info tids; 2168 struct sge sge; 2169 2170 int rawf_base; 2171 int nrawf; 2172 2173 }; 2174 2175 static void 2176 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2177 { 2178 2179 ASSERT_SYNCHRONIZED_OP(sc); 2180 2181 o->flags = sc->flags; 2182 2183 o->nbmcaps = sc->nbmcaps; 2184 o->linkcaps = sc->linkcaps; 2185 o->switchcaps = sc->switchcaps; 2186 o->niccaps = sc->niccaps; 2187 o->toecaps = sc->toecaps; 2188 o->rdmacaps = sc->rdmacaps; 2189 o->cryptocaps = sc->cryptocaps; 2190 o->iscsicaps = sc->iscsicaps; 2191 o->fcoecaps = sc->fcoecaps; 2192 2193 o->cfcsum = sc->cfcsum; 2194 MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file)); 2195 memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file)); 2196 2197 o->params = sc->params; 2198 o->vres = sc->vres; 2199 o->tids = sc->tids; 2200 o->sge = sc->sge; 2201 2202 o->rawf_base = sc->rawf_base; 2203 o->nrawf = sc->nrawf; 2204 } 2205 2206 static int 2207 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2208 { 2209 int rc = 0; 2210 2211 ASSERT_SYNCHRONIZED_OP(sc); 2212 2213 /* Capabilities */ 2214 #define COMPARE_CAPS(c) do { \ 2215 if (o->c##caps != sc->c##caps) { \ 2216 CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \ 2217 sc->c##caps); \ 2218 rc = EINVAL; \ 2219 } \ 2220 } while (0) 2221 COMPARE_CAPS(nbm); 2222 COMPARE_CAPS(link); 2223 COMPARE_CAPS(switch); 2224 COMPARE_CAPS(nic); 2225 COMPARE_CAPS(toe); 2226 COMPARE_CAPS(rdma); 2227 COMPARE_CAPS(crypto); 2228 COMPARE_CAPS(iscsi); 2229 COMPARE_CAPS(fcoe); 2230 #undef COMPARE_CAPS 2231 2232 /* Firmware config file */ 2233 if (o->cfcsum != sc->cfcsum) { 2234 CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file, 2235 o->cfcsum, sc->cfg_file, sc->cfcsum); 2236 rc = EINVAL; 2237 } 2238 2239 #define COMPARE_PARAM(p, name) do { \ 2240 if (o->p != sc->p) { \ 2241 CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \ 2242 rc = EINVAL; \ 2243 } \ 2244 } while (0) 2245 COMPARE_PARAM(sge.iq_start, iq_start); 2246 COMPARE_PARAM(sge.eq_start, eq_start); 2247 COMPARE_PARAM(tids.ftid_base, ftid_base); 2248 COMPARE_PARAM(tids.ftid_end, ftid_end); 2249 COMPARE_PARAM(tids.nftids, nftids); 2250 COMPARE_PARAM(vres.l2t.start, l2t_start); 2251 COMPARE_PARAM(vres.l2t.size, l2t_size); 2252 COMPARE_PARAM(sge.iqmap_sz, iqmap_sz); 2253 COMPARE_PARAM(sge.eqmap_sz, eqmap_sz); 2254 COMPARE_PARAM(tids.tid_base, tid_base); 2255 COMPARE_PARAM(tids.hpftid_base, hpftid_base); 2256 COMPARE_PARAM(tids.hpftid_end, hpftid_end); 2257 COMPARE_PARAM(tids.nhpftids, nhpftids); 2258 COMPARE_PARAM(rawf_base, rawf_base); 2259 COMPARE_PARAM(nrawf, nrawf); 2260 COMPARE_PARAM(params.mps_bg_map, mps_bg_map); 2261 COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support); 2262 COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl); 2263 COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support); 2264 COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr); 2265 COMPARE_PARAM(tids.ntids, ntids); 2266 COMPARE_PARAM(tids.etid_base, etid_base); 2267 COMPARE_PARAM(tids.etid_end, etid_end); 2268 COMPARE_PARAM(tids.netids, netids); 2269 COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred); 2270 COMPARE_PARAM(params.ethoffload, ethoffload); 2271 COMPARE_PARAM(tids.natids, natids); 2272 COMPARE_PARAM(tids.stid_base, stid_base); 2273 COMPARE_PARAM(vres.ddp.start, ddp_start); 2274 COMPARE_PARAM(vres.ddp.size, ddp_size); 2275 COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred); 2276 COMPARE_PARAM(vres.stag.start, stag_start); 2277 COMPARE_PARAM(vres.stag.size, stag_size); 2278 COMPARE_PARAM(vres.rq.start, rq_start); 2279 COMPARE_PARAM(vres.rq.size, rq_size); 2280 COMPARE_PARAM(vres.pbl.start, pbl_start); 2281 COMPARE_PARAM(vres.pbl.size, pbl_size); 2282 COMPARE_PARAM(vres.qp.start, qp_start); 2283 COMPARE_PARAM(vres.qp.size, qp_size); 2284 COMPARE_PARAM(vres.cq.start, cq_start); 2285 COMPARE_PARAM(vres.cq.size, cq_size); 2286 COMPARE_PARAM(vres.ocq.start, ocq_start); 2287 COMPARE_PARAM(vres.ocq.size, ocq_size); 2288 COMPARE_PARAM(vres.srq.start, srq_start); 2289 COMPARE_PARAM(vres.srq.size, srq_size); 2290 COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp); 2291 COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter); 2292 COMPARE_PARAM(vres.iscsi.start, iscsi_start); 2293 COMPARE_PARAM(vres.iscsi.size, iscsi_size); 2294 COMPARE_PARAM(vres.key.start, key_start); 2295 COMPARE_PARAM(vres.key.size, key_size); 2296 #undef COMPARE_PARAM 2297 2298 return (rc); 2299 } 2300 2301 static int 2302 restart_lld(struct adapter *sc) 2303 { 2304 struct adapter_pre_reset_state *old_state = NULL; 2305 struct port_info *pi; 2306 struct vi_info *vi; 2307 if_t ifp; 2308 struct sge_txq *txq; 2309 int rc, i, j, k; 2310 2311 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rlld"); 2312 if (rc != 0) 2313 return (ENXIO); 2314 2315 /* Restore memory window. */ 2316 setup_memwin(sc); 2317 2318 /* Go no further if recovery mode has been requested. */ 2319 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 2320 CH_ALERT(sc, "%s: recovery mode during restart.\n", __func__); 2321 rc = 0; 2322 set_adapter_hwstatus(sc, true); 2323 goto done; 2324 } 2325 2326 old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK); 2327 save_caps_and_params(sc, old_state); 2328 2329 /* Reestablish contact with firmware and become the primary PF. */ 2330 rc = contact_firmware(sc); 2331 if (rc != 0) 2332 goto done; /* error message displayed already */ 2333 MPASS(sc->flags & FW_OK); 2334 2335 if (sc->flags & MASTER_PF) { 2336 rc = partition_resources(sc); 2337 if (rc != 0) 2338 goto done; /* error message displayed already */ 2339 } 2340 2341 rc = get_params__post_init(sc); 2342 if (rc != 0) 2343 goto done; /* error message displayed already */ 2344 2345 rc = set_params__post_init(sc); 2346 if (rc != 0) 2347 goto done; /* error message displayed already */ 2348 2349 rc = compare_caps_and_params(sc, old_state); 2350 if (rc != 0) 2351 goto done; /* error message displayed already */ 2352 2353 for_each_port(sc, i) { 2354 pi = sc->port[i]; 2355 MPASS(pi != NULL); 2356 MPASS(pi->vi != NULL); 2357 MPASS(pi->vi[0].dev == pi->dev); 2358 2359 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 2360 if (rc != 0) { 2361 CH_ERR(sc, 2362 "failed to re-initialize port %d: %d\n", i, rc); 2363 goto done; 2364 } 2365 MPASS(sc->chan_map[pi->tx_chan] == i); 2366 2367 PORT_LOCK(pi); 2368 fixup_link_config(pi); 2369 build_medialist(pi); 2370 PORT_UNLOCK(pi); 2371 for_each_vi(pi, j, vi) { 2372 if (IS_MAIN_VI(vi)) 2373 continue; 2374 rc = alloc_extra_vi(sc, pi, vi); 2375 if (rc != 0) { 2376 CH_ERR(vi, 2377 "failed to re-allocate extra VI: %d\n", rc); 2378 goto done; 2379 } 2380 } 2381 } 2382 2383 /* 2384 * Interrupts and queues are about to be enabled and other threads will 2385 * want to access the hardware too. It is safe to do so. Note that 2386 * this thread is still in the middle of a synchronized_op. 2387 */ 2388 set_adapter_hwstatus(sc, true); 2389 2390 if (sc->flags & FULL_INIT_DONE) { 2391 rc = adapter_full_init(sc); 2392 if (rc != 0) { 2393 CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc); 2394 goto done; 2395 } 2396 2397 if (sc->vxlan_refcount > 0) 2398 enable_vxlan_rx(sc); 2399 2400 for_each_port(sc, i) { 2401 pi = sc->port[i]; 2402 for_each_vi(pi, j, vi) { 2403 mtx_lock(&vi->tick_mtx); 2404 vi->flags &= ~VI_SKIP_STATS; 2405 mtx_unlock(&vi->tick_mtx); 2406 if (!(vi->flags & VI_INIT_DONE)) 2407 continue; 2408 rc = vi_full_init(vi); 2409 if (rc != 0) { 2410 CH_ERR(vi, "failed to re-initialize " 2411 "interface: %d\n", rc); 2412 goto done; 2413 } 2414 2415 ifp = vi->ifp; 2416 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2417 continue; 2418 /* 2419 * Note that we do not setup multicast addresses 2420 * in the first pass. This ensures that the 2421 * unicast DMACs for all VIs on all ports get an 2422 * MPS TCAM entry. 2423 */ 2424 rc = update_mac_settings(ifp, XGMAC_ALL & 2425 ~XGMAC_MCADDRS); 2426 if (rc != 0) { 2427 CH_ERR(vi, "failed to re-configure MAC: %d\n", rc); 2428 goto done; 2429 } 2430 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, 2431 true); 2432 if (rc != 0) { 2433 CH_ERR(vi, "failed to re-enable VI: %d\n", rc); 2434 goto done; 2435 } 2436 for_each_txq(vi, k, txq) { 2437 TXQ_LOCK(txq); 2438 txq->eq.flags |= EQ_ENABLED; 2439 TXQ_UNLOCK(txq); 2440 } 2441 mtx_lock(&vi->tick_mtx); 2442 callout_schedule(&vi->tick, hz); 2443 mtx_unlock(&vi->tick_mtx); 2444 } 2445 PORT_LOCK(pi); 2446 if (pi->up_vis > 0) { 2447 t4_update_port_info(pi); 2448 fixup_link_config(pi); 2449 build_medialist(pi); 2450 apply_link_config(pi); 2451 if (pi->link_cfg.link_ok) 2452 t4_os_link_changed(pi); 2453 } 2454 PORT_UNLOCK(pi); 2455 } 2456 2457 /* Now reprogram the L2 multicast addresses. */ 2458 for_each_port(sc, i) { 2459 pi = sc->port[i]; 2460 for_each_vi(pi, j, vi) { 2461 if (!(vi->flags & VI_INIT_DONE)) 2462 continue; 2463 ifp = vi->ifp; 2464 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2465 continue; 2466 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2467 if (rc != 0) { 2468 CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc); 2469 rc = 0; /* carry on */ 2470 } 2471 } 2472 } 2473 } 2474 2475 /* Reset all calibration */ 2476 t4_calibration_start(sc); 2477 done: 2478 end_synchronized_op(sc, 0); 2479 free(old_state, M_CXGBE); 2480 2481 restart_atid_allocator(sc); 2482 t4_restart_l2t(sc); 2483 2484 return (rc); 2485 } 2486 2487 int 2488 resume_adapter(struct adapter *sc) 2489 { 2490 restart_adapter(sc); 2491 restart_lld(sc); 2492 #ifdef TCP_OFFLOAD 2493 restart_all_uld(sc); 2494 #endif 2495 return (0); 2496 } 2497 2498 static int 2499 t4_resume(device_t dev) 2500 { 2501 struct adapter *sc = device_get_softc(dev); 2502 int rc; 2503 2504 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2505 rc = resume_adapter(sc); 2506 CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread); 2507 2508 return (rc); 2509 } 2510 2511 static int 2512 t4_reset_prepare(device_t dev, device_t child) 2513 { 2514 struct adapter *sc = device_get_softc(dev); 2515 2516 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2517 return (0); 2518 } 2519 2520 static int 2521 t4_reset_post(device_t dev, device_t child) 2522 { 2523 struct adapter *sc = device_get_softc(dev); 2524 2525 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2526 return (0); 2527 } 2528 2529 static int 2530 reset_adapter_with_pci_bus_reset(struct adapter *sc) 2531 { 2532 int rc; 2533 2534 mtx_lock(&Giant); 2535 rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0); 2536 mtx_unlock(&Giant); 2537 return (rc); 2538 } 2539 2540 static int 2541 reset_adapter_with_pl_rst(struct adapter *sc) 2542 { 2543 suspend_adapter(sc); 2544 2545 /* This is a t4_write_reg without the hw_off_limits check. */ 2546 MPASS(sc->error_flags & HW_OFF_LIMITS); 2547 bus_space_write_4(sc->bt, sc->bh, A_PL_RST, 2548 F_PIORSTMODE | F_PIORST | F_AUTOPCIEPAUSE); 2549 pause("pl_rst", 1 * hz); /* Wait 1s for reset */ 2550 2551 resume_adapter(sc); 2552 2553 return (0); 2554 } 2555 2556 static inline int 2557 reset_adapter(struct adapter *sc) 2558 { 2559 if (vm_guest == 0) 2560 return (reset_adapter_with_pci_bus_reset(sc)); 2561 else 2562 return (reset_adapter_with_pl_rst(sc)); 2563 } 2564 2565 static void 2566 reset_adapter_task(void *arg, int pending) 2567 { 2568 struct adapter *sc = arg; 2569 const int flags = sc->flags; 2570 const int eflags = sc->error_flags; 2571 int rc; 2572 2573 if (pending > 1) 2574 CH_ALERT(sc, "%s: pending %d\n", __func__, pending); 2575 rc = reset_adapter(sc); 2576 if (rc != 0) { 2577 CH_ERR(sc, "adapter did not reset properly, rc = %d, " 2578 "flags 0x%08x -> 0x%08x, err_flags 0x%08x -> 0x%08x.\n", 2579 rc, flags, sc->flags, eflags, sc->error_flags); 2580 } 2581 } 2582 2583 static int 2584 cxgbe_probe(device_t dev) 2585 { 2586 struct port_info *pi = device_get_softc(dev); 2587 2588 device_set_descf(dev, "port %d", pi->port_id); 2589 2590 return (BUS_PROBE_DEFAULT); 2591 } 2592 2593 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 2594 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 2595 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 2596 IFCAP_HWRXTSTMP | IFCAP_MEXTPG) 2597 #define T4_CAP_ENABLE (T4_CAP) 2598 2599 static void 2600 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 2601 { 2602 if_t ifp; 2603 struct sbuf *sb; 2604 struct sysctl_ctx_list *ctx = &vi->ctx; 2605 struct sysctl_oid_list *children; 2606 struct pfil_head_args pa; 2607 struct adapter *sc = vi->adapter; 2608 2609 sysctl_ctx_init(ctx); 2610 children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev)); 2611 vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq", 2612 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues"); 2613 vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq", 2614 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues"); 2615 #ifdef DEV_NETMAP 2616 vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq", 2617 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues"); 2618 vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq", 2619 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues"); 2620 #endif 2621 #ifdef TCP_OFFLOAD 2622 vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq", 2623 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues"); 2624 #endif 2625 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2626 vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq", 2627 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues"); 2628 #endif 2629 2630 vi->xact_addr_filt = -1; 2631 mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF); 2632 callout_init_mtx(&vi->tick, &vi->tick_mtx, 0); 2633 if (sc->flags & IS_VF || t4_tx_vm_wr != 0) 2634 vi->flags |= TX_USES_VM_WR; 2635 2636 /* Allocate an ifnet and set it up */ 2637 ifp = if_alloc_dev(IFT_ETHER, dev); 2638 vi->ifp = ifp; 2639 if_setsoftc(ifp, vi); 2640 2641 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2642 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2643 2644 if_setinitfn(ifp, cxgbe_init); 2645 if_setioctlfn(ifp, cxgbe_ioctl); 2646 if_settransmitfn(ifp, cxgbe_transmit); 2647 if_setqflushfn(ifp, cxgbe_qflush); 2648 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 2649 if_setgetcounterfn(ifp, vi_get_counter); 2650 else 2651 if_setgetcounterfn(ifp, cxgbe_get_counter); 2652 #if defined(KERN_TLS) || defined(RATELIMIT) 2653 if_setsndtagallocfn(ifp, cxgbe_snd_tag_alloc); 2654 #endif 2655 #ifdef RATELIMIT 2656 if_setratelimitqueryfn(ifp, cxgbe_ratelimit_query); 2657 #endif 2658 2659 if_setcapabilities(ifp, T4_CAP); 2660 if_setcapenable(ifp, T4_CAP_ENABLE); 2661 if_sethwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 2662 CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2663 if (chip_id(sc) >= CHELSIO_T6) { 2664 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2665 if_setcapenablebit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2666 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 2667 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2668 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN, 0); 2669 } 2670 2671 #ifdef TCP_OFFLOAD 2672 if (vi->nofldrxq != 0) 2673 if_setcapabilitiesbit(ifp, IFCAP_TOE, 0); 2674 #endif 2675 #ifdef RATELIMIT 2676 if (is_ethoffload(sc) && vi->nofldtxq != 0) { 2677 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0); 2678 if_setcapenablebit(ifp, IFCAP_TXRTLMT, 0); 2679 } 2680 #endif 2681 2682 if_sethwtsomax(ifp, IP_MAXPACKET); 2683 if (vi->flags & TX_USES_VM_WR) 2684 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_VM_TSO); 2685 else 2686 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_TSO); 2687 #ifdef RATELIMIT 2688 if (is_ethoffload(sc) && vi->nofldtxq != 0) 2689 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_EO_TSO); 2690 #endif 2691 if_sethwtsomaxsegsize(ifp, 65536); 2692 #ifdef KERN_TLS 2693 if (is_ktls(sc)) { 2694 if_setcapabilitiesbit(ifp, IFCAP_TXTLS, 0); 2695 if (sc->flags & KERN_TLS_ON || !is_t6(sc)) 2696 if_setcapenablebit(ifp, IFCAP_TXTLS, 0); 2697 } 2698 #endif 2699 2700 ether_ifattach(ifp, vi->hw_addr); 2701 #ifdef DEV_NETMAP 2702 if (vi->nnmrxq != 0) 2703 cxgbe_nm_attach(vi); 2704 #endif 2705 sb = sbuf_new_auto(); 2706 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 2707 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2708 switch (if_getcapabilities(ifp) & (IFCAP_TOE | IFCAP_TXRTLMT)) { 2709 case IFCAP_TOE: 2710 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 2711 break; 2712 case IFCAP_TOE | IFCAP_TXRTLMT: 2713 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 2714 break; 2715 case IFCAP_TXRTLMT: 2716 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 2717 break; 2718 } 2719 #endif 2720 #ifdef TCP_OFFLOAD 2721 if (if_getcapabilities(ifp) & IFCAP_TOE) 2722 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 2723 #endif 2724 #ifdef DEV_NETMAP 2725 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2726 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 2727 vi->nnmtxq, vi->nnmrxq); 2728 #endif 2729 sbuf_finish(sb); 2730 device_printf(dev, "%s\n", sbuf_data(sb)); 2731 sbuf_delete(sb); 2732 2733 vi_sysctls(vi); 2734 2735 pa.pa_version = PFIL_VERSION; 2736 pa.pa_flags = PFIL_IN; 2737 pa.pa_type = PFIL_TYPE_ETHERNET; 2738 pa.pa_headname = if_name(ifp); 2739 vi->pfil = pfil_head_register(&pa); 2740 } 2741 2742 static int 2743 cxgbe_attach(device_t dev) 2744 { 2745 struct port_info *pi = device_get_softc(dev); 2746 struct adapter *sc = pi->adapter; 2747 struct vi_info *vi; 2748 int i; 2749 2750 sysctl_ctx_init(&pi->ctx); 2751 2752 cxgbe_vi_attach(dev, &pi->vi[0]); 2753 2754 for_each_vi(pi, i, vi) { 2755 if (i == 0) 2756 continue; 2757 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, DEVICE_UNIT_ANY); 2758 if (vi->dev == NULL) { 2759 device_printf(dev, "failed to add VI %d\n", i); 2760 continue; 2761 } 2762 device_set_softc(vi->dev, vi); 2763 } 2764 2765 cxgbe_sysctls(pi); 2766 2767 bus_generic_attach(dev); 2768 2769 return (0); 2770 } 2771 2772 static void 2773 cxgbe_vi_detach(struct vi_info *vi) 2774 { 2775 if_t ifp = vi->ifp; 2776 2777 if (vi->pfil != NULL) { 2778 pfil_head_unregister(vi->pfil); 2779 vi->pfil = NULL; 2780 } 2781 2782 ether_ifdetach(ifp); 2783 2784 /* Let detach proceed even if these fail. */ 2785 #ifdef DEV_NETMAP 2786 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2787 cxgbe_nm_detach(vi); 2788 #endif 2789 cxgbe_uninit_synchronized(vi); 2790 callout_drain(&vi->tick); 2791 mtx_destroy(&vi->tick_mtx); 2792 sysctl_ctx_free(&vi->ctx); 2793 vi_full_uninit(vi); 2794 2795 if_free(vi->ifp); 2796 vi->ifp = NULL; 2797 } 2798 2799 static int 2800 cxgbe_detach(device_t dev) 2801 { 2802 struct port_info *pi = device_get_softc(dev); 2803 struct adapter *sc = pi->adapter; 2804 int rc; 2805 2806 /* Detach the extra VIs first. */ 2807 rc = bus_generic_detach(dev); 2808 if (rc) 2809 return (rc); 2810 device_delete_children(dev); 2811 2812 sysctl_ctx_free(&pi->ctx); 2813 begin_vi_detach(sc, &pi->vi[0]); 2814 if (pi->flags & HAS_TRACEQ) { 2815 sc->traceq = -1; /* cloner should not create ifnet */ 2816 t4_tracer_port_detach(sc); 2817 } 2818 cxgbe_vi_detach(&pi->vi[0]); 2819 ifmedia_removeall(&pi->media); 2820 end_vi_detach(sc, &pi->vi[0]); 2821 2822 return (0); 2823 } 2824 2825 static void 2826 cxgbe_init(void *arg) 2827 { 2828 struct vi_info *vi = arg; 2829 struct adapter *sc = vi->adapter; 2830 2831 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 2832 return; 2833 cxgbe_init_synchronized(vi); 2834 end_synchronized_op(sc, 0); 2835 } 2836 2837 static int 2838 cxgbe_ioctl(if_t ifp, unsigned long cmd, caddr_t data) 2839 { 2840 int rc = 0, mtu, flags; 2841 struct vi_info *vi = if_getsoftc(ifp); 2842 struct port_info *pi = vi->pi; 2843 struct adapter *sc = pi->adapter; 2844 struct ifreq *ifr = (struct ifreq *)data; 2845 uint32_t mask; 2846 2847 switch (cmd) { 2848 case SIOCSIFMTU: 2849 mtu = ifr->ifr_mtu; 2850 if (mtu < ETHERMIN || mtu > MAX_MTU) 2851 return (EINVAL); 2852 2853 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 2854 if (rc) 2855 return (rc); 2856 if_setmtu(ifp, mtu); 2857 if (vi->flags & VI_INIT_DONE) { 2858 t4_update_fl_bufsize(ifp); 2859 if (!hw_off_limits(sc) && 2860 if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2861 rc = update_mac_settings(ifp, XGMAC_MTU); 2862 } 2863 end_synchronized_op(sc, 0); 2864 break; 2865 2866 case SIOCSIFFLAGS: 2867 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 2868 if (rc) 2869 return (rc); 2870 2871 if (hw_off_limits(sc)) { 2872 rc = ENXIO; 2873 goto fail; 2874 } 2875 2876 if (if_getflags(ifp) & IFF_UP) { 2877 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2878 flags = vi->if_flags; 2879 if ((if_getflags(ifp) ^ flags) & 2880 (IFF_PROMISC | IFF_ALLMULTI)) { 2881 rc = update_mac_settings(ifp, 2882 XGMAC_PROMISC | XGMAC_ALLMULTI); 2883 } 2884 } else { 2885 rc = cxgbe_init_synchronized(vi); 2886 } 2887 vi->if_flags = if_getflags(ifp); 2888 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2889 rc = cxgbe_uninit_synchronized(vi); 2890 } 2891 end_synchronized_op(sc, 0); 2892 break; 2893 2894 case SIOCADDMULTI: 2895 case SIOCDELMULTI: 2896 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 2897 if (rc) 2898 return (rc); 2899 if (!hw_off_limits(sc) && if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2900 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2901 end_synchronized_op(sc, 0); 2902 break; 2903 2904 case SIOCSIFCAP: 2905 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 2906 if (rc) 2907 return (rc); 2908 2909 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2910 if (mask & IFCAP_TXCSUM) { 2911 if_togglecapenable(ifp, IFCAP_TXCSUM); 2912 if_togglehwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP); 2913 2914 if (IFCAP_TSO4 & if_getcapenable(ifp) && 2915 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2916 mask &= ~IFCAP_TSO4; 2917 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 2918 if_printf(ifp, 2919 "tso4 disabled due to -txcsum.\n"); 2920 } 2921 } 2922 if (mask & IFCAP_TXCSUM_IPV6) { 2923 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 2924 if_togglehwassist(ifp, CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2925 2926 if (IFCAP_TSO6 & if_getcapenable(ifp) && 2927 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2928 mask &= ~IFCAP_TSO6; 2929 if_setcapenablebit(ifp, 0, IFCAP_TSO6); 2930 if_printf(ifp, 2931 "tso6 disabled due to -txcsum6.\n"); 2932 } 2933 } 2934 if (mask & IFCAP_RXCSUM) 2935 if_togglecapenable(ifp, IFCAP_RXCSUM); 2936 if (mask & IFCAP_RXCSUM_IPV6) 2937 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 2938 2939 /* 2940 * Note that we leave CSUM_TSO alone (it is always set). The 2941 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 2942 * sending a TSO request our way, so it's sufficient to toggle 2943 * IFCAP_TSOx only. 2944 */ 2945 if (mask & IFCAP_TSO4) { 2946 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) && 2947 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2948 if_printf(ifp, "enable txcsum first.\n"); 2949 rc = EAGAIN; 2950 goto fail; 2951 } 2952 if_togglecapenable(ifp, IFCAP_TSO4); 2953 } 2954 if (mask & IFCAP_TSO6) { 2955 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) && 2956 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2957 if_printf(ifp, "enable txcsum6 first.\n"); 2958 rc = EAGAIN; 2959 goto fail; 2960 } 2961 if_togglecapenable(ifp, IFCAP_TSO6); 2962 } 2963 if (mask & IFCAP_LRO) { 2964 #if defined(INET) || defined(INET6) 2965 int i; 2966 struct sge_rxq *rxq; 2967 2968 if_togglecapenable(ifp, IFCAP_LRO); 2969 for_each_rxq(vi, i, rxq) { 2970 if (if_getcapenable(ifp) & IFCAP_LRO) 2971 rxq->iq.flags |= IQ_LRO_ENABLED; 2972 else 2973 rxq->iq.flags &= ~IQ_LRO_ENABLED; 2974 } 2975 #endif 2976 } 2977 #ifdef TCP_OFFLOAD 2978 if (mask & IFCAP_TOE) { 2979 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TOE; 2980 2981 rc = toe_capability(vi, enable); 2982 if (rc != 0) 2983 goto fail; 2984 2985 if_togglecapenable(ifp, mask); 2986 } 2987 #endif 2988 if (mask & IFCAP_VLAN_HWTAGGING) { 2989 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2990 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2991 rc = update_mac_settings(ifp, XGMAC_VLANEX); 2992 } 2993 if (mask & IFCAP_VLAN_MTU) { 2994 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 2995 2996 /* Need to find out how to disable auto-mtu-inflation */ 2997 } 2998 if (mask & IFCAP_VLAN_HWTSO) 2999 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3000 if (mask & IFCAP_VLAN_HWCSUM) 3001 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3002 #ifdef RATELIMIT 3003 if (mask & IFCAP_TXRTLMT) 3004 if_togglecapenable(ifp, IFCAP_TXRTLMT); 3005 #endif 3006 if (mask & IFCAP_HWRXTSTMP) { 3007 int i; 3008 struct sge_rxq *rxq; 3009 3010 if_togglecapenable(ifp, IFCAP_HWRXTSTMP); 3011 for_each_rxq(vi, i, rxq) { 3012 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) 3013 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3014 else 3015 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 3016 } 3017 } 3018 if (mask & IFCAP_MEXTPG) 3019 if_togglecapenable(ifp, IFCAP_MEXTPG); 3020 3021 #ifdef KERN_TLS 3022 if (mask & IFCAP_TXTLS) { 3023 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TXTLS; 3024 3025 rc = ktls_capability(sc, enable); 3026 if (rc != 0) 3027 goto fail; 3028 3029 if_togglecapenable(ifp, mask & IFCAP_TXTLS); 3030 } 3031 #endif 3032 if (mask & IFCAP_VXLAN_HWCSUM) { 3033 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM); 3034 if_togglehwassist(ifp, CSUM_INNER_IP6_UDP | 3035 CSUM_INNER_IP6_TCP | CSUM_INNER_IP | 3036 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP); 3037 } 3038 if (mask & IFCAP_VXLAN_HWTSO) { 3039 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO); 3040 if_togglehwassist(ifp, CSUM_INNER_IP6_TSO | 3041 CSUM_INNER_IP_TSO); 3042 } 3043 3044 #ifdef VLAN_CAPABILITIES 3045 VLAN_CAPABILITIES(ifp); 3046 #endif 3047 fail: 3048 end_synchronized_op(sc, 0); 3049 break; 3050 3051 case SIOCSIFMEDIA: 3052 case SIOCGIFMEDIA: 3053 case SIOCGIFXMEDIA: 3054 rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 3055 break; 3056 3057 case SIOCGI2C: { 3058 struct ifi2creq i2c; 3059 3060 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3061 if (rc != 0) 3062 break; 3063 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3064 rc = EPERM; 3065 break; 3066 } 3067 if (i2c.len > sizeof(i2c.data)) { 3068 rc = EINVAL; 3069 break; 3070 } 3071 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 3072 if (rc) 3073 return (rc); 3074 if (hw_off_limits(sc)) 3075 rc = ENXIO; 3076 else 3077 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 3078 i2c.offset, i2c.len, &i2c.data[0]); 3079 end_synchronized_op(sc, 0); 3080 if (rc == 0) 3081 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3082 break; 3083 } 3084 3085 default: 3086 rc = ether_ioctl(ifp, cmd, data); 3087 } 3088 3089 return (rc); 3090 } 3091 3092 static int 3093 cxgbe_transmit(if_t ifp, struct mbuf *m) 3094 { 3095 struct vi_info *vi = if_getsoftc(ifp); 3096 struct port_info *pi = vi->pi; 3097 struct adapter *sc; 3098 struct sge_txq *txq; 3099 void *items[1]; 3100 int rc; 3101 3102 M_ASSERTPKTHDR(m); 3103 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 3104 #if defined(KERN_TLS) || defined(RATELIMIT) 3105 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) 3106 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 3107 #endif 3108 3109 if (__predict_false(pi->link_cfg.link_ok == false)) { 3110 m_freem(m); 3111 return (ENETDOWN); 3112 } 3113 3114 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR); 3115 if (__predict_false(rc != 0)) { 3116 if (__predict_true(rc == EINPROGRESS)) { 3117 /* queued by parse_pkt */ 3118 MPASS(m != NULL); 3119 return (0); 3120 } 3121 3122 MPASS(m == NULL); /* was freed already */ 3123 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 3124 return (rc); 3125 } 3126 3127 /* Select a txq. */ 3128 sc = vi->adapter; 3129 txq = &sc->sge.txq[vi->first_txq]; 3130 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 3131 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 3132 vi->rsrv_noflowq); 3133 3134 items[0] = m; 3135 rc = mp_ring_enqueue(txq->r, items, 1, 256); 3136 if (__predict_false(rc != 0)) 3137 m_freem(m); 3138 3139 return (rc); 3140 } 3141 3142 static void 3143 cxgbe_qflush(if_t ifp) 3144 { 3145 struct vi_info *vi = if_getsoftc(ifp); 3146 struct sge_txq *txq; 3147 int i; 3148 3149 /* queues do not exist if !VI_INIT_DONE. */ 3150 if (vi->flags & VI_INIT_DONE) { 3151 for_each_txq(vi, i, txq) { 3152 TXQ_LOCK(txq); 3153 txq->eq.flags |= EQ_QFLUSH; 3154 TXQ_UNLOCK(txq); 3155 while (!mp_ring_is_idle(txq->r)) { 3156 mp_ring_check_drainage(txq->r, 4096); 3157 pause("qflush", 1); 3158 } 3159 TXQ_LOCK(txq); 3160 txq->eq.flags &= ~EQ_QFLUSH; 3161 TXQ_UNLOCK(txq); 3162 } 3163 } 3164 if_qflush(ifp); 3165 } 3166 3167 static uint64_t 3168 vi_get_counter(if_t ifp, ift_counter c) 3169 { 3170 struct vi_info *vi = if_getsoftc(ifp); 3171 struct fw_vi_stats_vf *s = &vi->stats; 3172 3173 mtx_lock(&vi->tick_mtx); 3174 vi_refresh_stats(vi); 3175 mtx_unlock(&vi->tick_mtx); 3176 3177 switch (c) { 3178 case IFCOUNTER_IPACKETS: 3179 return (s->rx_bcast_frames + s->rx_mcast_frames + 3180 s->rx_ucast_frames); 3181 case IFCOUNTER_IERRORS: 3182 return (s->rx_err_frames); 3183 case IFCOUNTER_OPACKETS: 3184 return (s->tx_bcast_frames + s->tx_mcast_frames + 3185 s->tx_ucast_frames + s->tx_offload_frames); 3186 case IFCOUNTER_OERRORS: 3187 return (s->tx_drop_frames); 3188 case IFCOUNTER_IBYTES: 3189 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 3190 s->rx_ucast_bytes); 3191 case IFCOUNTER_OBYTES: 3192 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 3193 s->tx_ucast_bytes + s->tx_offload_bytes); 3194 case IFCOUNTER_IMCASTS: 3195 return (s->rx_mcast_frames); 3196 case IFCOUNTER_OMCASTS: 3197 return (s->tx_mcast_frames); 3198 case IFCOUNTER_OQDROPS: { 3199 uint64_t drops; 3200 3201 drops = 0; 3202 if (vi->flags & VI_INIT_DONE) { 3203 int i; 3204 struct sge_txq *txq; 3205 3206 for_each_txq(vi, i, txq) 3207 drops += counter_u64_fetch(txq->r->dropped); 3208 } 3209 3210 return (drops); 3211 3212 } 3213 3214 default: 3215 return (if_get_counter_default(ifp, c)); 3216 } 3217 } 3218 3219 static uint64_t 3220 cxgbe_get_counter(if_t ifp, ift_counter c) 3221 { 3222 struct vi_info *vi = if_getsoftc(ifp); 3223 struct port_info *pi = vi->pi; 3224 struct port_stats *s = &pi->stats; 3225 3226 mtx_lock(&vi->tick_mtx); 3227 cxgbe_refresh_stats(vi); 3228 mtx_unlock(&vi->tick_mtx); 3229 3230 switch (c) { 3231 case IFCOUNTER_IPACKETS: 3232 return (s->rx_frames); 3233 3234 case IFCOUNTER_IERRORS: 3235 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 3236 s->rx_fcs_err + s->rx_len_err); 3237 3238 case IFCOUNTER_OPACKETS: 3239 return (s->tx_frames); 3240 3241 case IFCOUNTER_OERRORS: 3242 return (s->tx_error_frames); 3243 3244 case IFCOUNTER_IBYTES: 3245 return (s->rx_octets); 3246 3247 case IFCOUNTER_OBYTES: 3248 return (s->tx_octets); 3249 3250 case IFCOUNTER_IMCASTS: 3251 return (s->rx_mcast_frames); 3252 3253 case IFCOUNTER_OMCASTS: 3254 return (s->tx_mcast_frames); 3255 3256 case IFCOUNTER_IQDROPS: 3257 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 3258 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 3259 s->rx_trunc3 + pi->tnl_cong_drops); 3260 3261 case IFCOUNTER_OQDROPS: { 3262 uint64_t drops; 3263 3264 drops = s->tx_drop; 3265 if (vi->flags & VI_INIT_DONE) { 3266 int i; 3267 struct sge_txq *txq; 3268 3269 for_each_txq(vi, i, txq) 3270 drops += counter_u64_fetch(txq->r->dropped); 3271 } 3272 3273 return (drops); 3274 3275 } 3276 3277 default: 3278 return (if_get_counter_default(ifp, c)); 3279 } 3280 } 3281 3282 #if defined(KERN_TLS) || defined(RATELIMIT) 3283 static int 3284 cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params, 3285 struct m_snd_tag **pt) 3286 { 3287 int error; 3288 3289 switch (params->hdr.type) { 3290 #ifdef RATELIMIT 3291 case IF_SND_TAG_TYPE_RATE_LIMIT: 3292 error = cxgbe_rate_tag_alloc(ifp, params, pt); 3293 break; 3294 #endif 3295 #ifdef KERN_TLS 3296 case IF_SND_TAG_TYPE_TLS: 3297 { 3298 struct vi_info *vi = if_getsoftc(ifp); 3299 3300 if (is_t6(vi->pi->adapter)) 3301 error = t6_tls_tag_alloc(ifp, params, pt); 3302 else 3303 error = EOPNOTSUPP; 3304 break; 3305 } 3306 #endif 3307 default: 3308 error = EOPNOTSUPP; 3309 } 3310 return (error); 3311 } 3312 #endif 3313 3314 /* 3315 * The kernel picks a media from the list we had provided but we still validate 3316 * the requeste. 3317 */ 3318 int 3319 cxgbe_media_change(if_t ifp) 3320 { 3321 struct vi_info *vi = if_getsoftc(ifp); 3322 struct port_info *pi = vi->pi; 3323 struct ifmedia *ifm = &pi->media; 3324 struct link_config *lc = &pi->link_cfg; 3325 struct adapter *sc = pi->adapter; 3326 int rc; 3327 3328 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 3329 if (rc != 0) 3330 return (rc); 3331 PORT_LOCK(pi); 3332 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 3333 /* ifconfig .. media autoselect */ 3334 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { 3335 rc = ENOTSUP; /* AN not supported by transceiver */ 3336 goto done; 3337 } 3338 lc->requested_aneg = AUTONEG_ENABLE; 3339 lc->requested_speed = 0; 3340 lc->requested_fc |= PAUSE_AUTONEG; 3341 } else { 3342 lc->requested_aneg = AUTONEG_DISABLE; 3343 lc->requested_speed = 3344 ifmedia_baudrate(ifm->ifm_media) / 1000000; 3345 lc->requested_fc = 0; 3346 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 3347 lc->requested_fc |= PAUSE_RX; 3348 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 3349 lc->requested_fc |= PAUSE_TX; 3350 } 3351 if (pi->up_vis > 0 && !hw_off_limits(sc)) { 3352 fixup_link_config(pi); 3353 rc = apply_link_config(pi); 3354 } 3355 done: 3356 PORT_UNLOCK(pi); 3357 end_synchronized_op(sc, 0); 3358 return (rc); 3359 } 3360 3361 /* 3362 * Base media word (without ETHER, pause, link active, etc.) for the port at the 3363 * given speed. 3364 */ 3365 static int 3366 port_mword(struct port_info *pi, uint32_t speed) 3367 { 3368 3369 MPASS(speed & M_FW_PORT_CAP32_SPEED); 3370 MPASS(powerof2(speed)); 3371 3372 switch(pi->port_type) { 3373 case FW_PORT_TYPE_BT_SGMII: 3374 case FW_PORT_TYPE_BT_XFI: 3375 case FW_PORT_TYPE_BT_XAUI: 3376 /* BaseT */ 3377 switch (speed) { 3378 case FW_PORT_CAP32_SPEED_100M: 3379 return (IFM_100_T); 3380 case FW_PORT_CAP32_SPEED_1G: 3381 return (IFM_1000_T); 3382 case FW_PORT_CAP32_SPEED_10G: 3383 return (IFM_10G_T); 3384 } 3385 break; 3386 case FW_PORT_TYPE_KX4: 3387 if (speed == FW_PORT_CAP32_SPEED_10G) 3388 return (IFM_10G_KX4); 3389 break; 3390 case FW_PORT_TYPE_CX4: 3391 if (speed == FW_PORT_CAP32_SPEED_10G) 3392 return (IFM_10G_CX4); 3393 break; 3394 case FW_PORT_TYPE_KX: 3395 if (speed == FW_PORT_CAP32_SPEED_1G) 3396 return (IFM_1000_KX); 3397 break; 3398 case FW_PORT_TYPE_KR: 3399 case FW_PORT_TYPE_BP_AP: 3400 case FW_PORT_TYPE_BP4_AP: 3401 case FW_PORT_TYPE_BP40_BA: 3402 case FW_PORT_TYPE_KR4_100G: 3403 case FW_PORT_TYPE_KR_SFP28: 3404 case FW_PORT_TYPE_KR_XLAUI: 3405 switch (speed) { 3406 case FW_PORT_CAP32_SPEED_1G: 3407 return (IFM_1000_KX); 3408 case FW_PORT_CAP32_SPEED_10G: 3409 return (IFM_10G_KR); 3410 case FW_PORT_CAP32_SPEED_25G: 3411 return (IFM_25G_KR); 3412 case FW_PORT_CAP32_SPEED_40G: 3413 return (IFM_40G_KR4); 3414 case FW_PORT_CAP32_SPEED_50G: 3415 return (IFM_50G_KR2); 3416 case FW_PORT_CAP32_SPEED_100G: 3417 return (IFM_100G_KR4); 3418 } 3419 break; 3420 case FW_PORT_TYPE_FIBER_XFI: 3421 case FW_PORT_TYPE_FIBER_XAUI: 3422 case FW_PORT_TYPE_SFP: 3423 case FW_PORT_TYPE_QSFP_10G: 3424 case FW_PORT_TYPE_QSA: 3425 case FW_PORT_TYPE_QSFP: 3426 case FW_PORT_TYPE_CR4_QSFP: 3427 case FW_PORT_TYPE_CR_QSFP: 3428 case FW_PORT_TYPE_CR2_QSFP: 3429 case FW_PORT_TYPE_SFP28: 3430 /* Pluggable transceiver */ 3431 switch (pi->mod_type) { 3432 case FW_PORT_MOD_TYPE_LR: 3433 switch (speed) { 3434 case FW_PORT_CAP32_SPEED_1G: 3435 return (IFM_1000_LX); 3436 case FW_PORT_CAP32_SPEED_10G: 3437 return (IFM_10G_LR); 3438 case FW_PORT_CAP32_SPEED_25G: 3439 return (IFM_25G_LR); 3440 case FW_PORT_CAP32_SPEED_40G: 3441 return (IFM_40G_LR4); 3442 case FW_PORT_CAP32_SPEED_50G: 3443 return (IFM_50G_LR2); 3444 case FW_PORT_CAP32_SPEED_100G: 3445 return (IFM_100G_LR4); 3446 } 3447 break; 3448 case FW_PORT_MOD_TYPE_SR: 3449 switch (speed) { 3450 case FW_PORT_CAP32_SPEED_1G: 3451 return (IFM_1000_SX); 3452 case FW_PORT_CAP32_SPEED_10G: 3453 return (IFM_10G_SR); 3454 case FW_PORT_CAP32_SPEED_25G: 3455 return (IFM_25G_SR); 3456 case FW_PORT_CAP32_SPEED_40G: 3457 return (IFM_40G_SR4); 3458 case FW_PORT_CAP32_SPEED_50G: 3459 return (IFM_50G_SR2); 3460 case FW_PORT_CAP32_SPEED_100G: 3461 return (IFM_100G_SR4); 3462 } 3463 break; 3464 case FW_PORT_MOD_TYPE_ER: 3465 if (speed == FW_PORT_CAP32_SPEED_10G) 3466 return (IFM_10G_ER); 3467 break; 3468 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3469 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3470 switch (speed) { 3471 case FW_PORT_CAP32_SPEED_1G: 3472 return (IFM_1000_CX); 3473 case FW_PORT_CAP32_SPEED_10G: 3474 return (IFM_10G_TWINAX); 3475 case FW_PORT_CAP32_SPEED_25G: 3476 return (IFM_25G_CR); 3477 case FW_PORT_CAP32_SPEED_40G: 3478 return (IFM_40G_CR4); 3479 case FW_PORT_CAP32_SPEED_50G: 3480 return (IFM_50G_CR2); 3481 case FW_PORT_CAP32_SPEED_100G: 3482 return (IFM_100G_CR4); 3483 } 3484 break; 3485 case FW_PORT_MOD_TYPE_LRM: 3486 if (speed == FW_PORT_CAP32_SPEED_10G) 3487 return (IFM_10G_LRM); 3488 break; 3489 case FW_PORT_MOD_TYPE_NA: 3490 MPASS(0); /* Not pluggable? */ 3491 /* fall throough */ 3492 case FW_PORT_MOD_TYPE_ERROR: 3493 case FW_PORT_MOD_TYPE_UNKNOWN: 3494 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 3495 break; 3496 case FW_PORT_MOD_TYPE_NONE: 3497 return (IFM_NONE); 3498 } 3499 break; 3500 case FW_PORT_TYPE_NONE: 3501 return (IFM_NONE); 3502 } 3503 3504 return (IFM_UNKNOWN); 3505 } 3506 3507 void 3508 cxgbe_media_status(if_t ifp, struct ifmediareq *ifmr) 3509 { 3510 struct vi_info *vi = if_getsoftc(ifp); 3511 struct port_info *pi = vi->pi; 3512 struct adapter *sc = pi->adapter; 3513 struct link_config *lc = &pi->link_cfg; 3514 3515 if (begin_synchronized_op(sc, vi , SLEEP_OK | INTR_OK, "t4med") != 0) 3516 return; 3517 PORT_LOCK(pi); 3518 3519 if (pi->up_vis == 0 && !hw_off_limits(sc)) { 3520 /* 3521 * If all the interfaces are administratively down the firmware 3522 * does not report transceiver changes. Refresh port info here 3523 * so that ifconfig displays accurate ifmedia at all times. 3524 * This is the only reason we have a synchronized op in this 3525 * function. Just PORT_LOCK would have been enough otherwise. 3526 */ 3527 t4_update_port_info(pi); 3528 build_medialist(pi); 3529 } 3530 3531 /* ifm_status */ 3532 ifmr->ifm_status = IFM_AVALID; 3533 if (lc->link_ok == false) 3534 goto done; 3535 ifmr->ifm_status |= IFM_ACTIVE; 3536 3537 /* ifm_active */ 3538 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 3539 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 3540 if (lc->fc & PAUSE_RX) 3541 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3542 if (lc->fc & PAUSE_TX) 3543 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3544 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 3545 done: 3546 PORT_UNLOCK(pi); 3547 end_synchronized_op(sc, 0); 3548 } 3549 3550 static int 3551 vcxgbe_probe(device_t dev) 3552 { 3553 struct vi_info *vi = device_get_softc(dev); 3554 3555 device_set_descf(dev, "port %d vi %td", vi->pi->port_id, 3556 vi - vi->pi->vi); 3557 3558 return (BUS_PROBE_DEFAULT); 3559 } 3560 3561 static int 3562 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 3563 { 3564 int func, index, rc; 3565 uint32_t param, val; 3566 3567 ASSERT_SYNCHRONIZED_OP(sc); 3568 3569 index = vi - pi->vi; 3570 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 3571 KASSERT(index < nitems(vi_mac_funcs), 3572 ("%s: VI %s doesn't have a MAC func", __func__, 3573 device_get_nameunit(vi->dev))); 3574 func = vi_mac_funcs[index]; 3575 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 3576 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 3577 if (rc < 0) { 3578 CH_ERR(vi, "failed to allocate virtual interface %d" 3579 "for port %d: %d\n", index, pi->port_id, -rc); 3580 return (-rc); 3581 } 3582 vi->viid = rc; 3583 3584 if (vi->rss_size == 1) { 3585 /* 3586 * This VI didn't get a slice of the RSS table. Reduce the 3587 * number of VIs being created (hw.cxgbe.num_vis) or modify the 3588 * configuration file (nvi, rssnvi for this PF) if this is a 3589 * problem. 3590 */ 3591 device_printf(vi->dev, "RSS table not available.\n"); 3592 vi->rss_base = 0xffff; 3593 3594 return (0); 3595 } 3596 3597 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3598 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 3599 V_FW_PARAMS_PARAM_YZ(vi->viid); 3600 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3601 if (rc) 3602 vi->rss_base = 0xffff; 3603 else { 3604 MPASS((val >> 16) == vi->rss_size); 3605 vi->rss_base = val & 0xffff; 3606 } 3607 3608 return (0); 3609 } 3610 3611 static int 3612 vcxgbe_attach(device_t dev) 3613 { 3614 struct vi_info *vi; 3615 struct port_info *pi; 3616 struct adapter *sc; 3617 int rc; 3618 3619 vi = device_get_softc(dev); 3620 pi = vi->pi; 3621 sc = pi->adapter; 3622 3623 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 3624 if (rc) 3625 return (rc); 3626 rc = alloc_extra_vi(sc, pi, vi); 3627 end_synchronized_op(sc, 0); 3628 if (rc) 3629 return (rc); 3630 3631 cxgbe_vi_attach(dev, vi); 3632 3633 return (0); 3634 } 3635 3636 static int 3637 vcxgbe_detach(device_t dev) 3638 { 3639 struct vi_info *vi; 3640 struct adapter *sc; 3641 3642 vi = device_get_softc(dev); 3643 sc = vi->adapter; 3644 3645 begin_vi_detach(sc, vi); 3646 cxgbe_vi_detach(vi); 3647 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3648 end_vi_detach(sc, vi); 3649 3650 return (0); 3651 } 3652 3653 static struct callout fatal_callout; 3654 static struct taskqueue *reset_tq; 3655 3656 static void 3657 delayed_panic(void *arg) 3658 { 3659 struct adapter *sc = arg; 3660 3661 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 3662 } 3663 3664 static void 3665 fatal_error_task(void *arg, int pending) 3666 { 3667 struct adapter *sc = arg; 3668 int rc; 3669 3670 if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) { 3671 dump_cim_regs(sc); 3672 dump_cimla(sc); 3673 dump_devlog(sc); 3674 } 3675 3676 if (t4_reset_on_fatal_err) { 3677 CH_ALERT(sc, "resetting adapter after fatal error.\n"); 3678 rc = reset_adapter(sc); 3679 if (rc == 0 && t4_panic_on_fatal_err) { 3680 CH_ALERT(sc, "reset was successful, " 3681 "system will NOT panic.\n"); 3682 return; 3683 } 3684 } 3685 3686 if (t4_panic_on_fatal_err) { 3687 CH_ALERT(sc, "panicking on fatal error (after 30s).\n"); 3688 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 3689 } 3690 } 3691 3692 void 3693 t4_fatal_err(struct adapter *sc, bool fw_error) 3694 { 3695 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 3696 3697 stop_adapter(sc); 3698 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR))) 3699 return; 3700 if (fw_error) { 3701 /* 3702 * We are here because of a firmware error/timeout and not 3703 * because of a hardware interrupt. It is possible (although 3704 * not very likely) that an error interrupt was also raised but 3705 * this thread ran first and inhibited t4_intr_err. We walk the 3706 * main INT_CAUSE registers here to make sure we haven't missed 3707 * anything interesting. 3708 */ 3709 t4_slow_intr_handler(sc, verbose); 3710 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 3711 } 3712 t4_report_fw_error(sc); 3713 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n", 3714 device_get_nameunit(sc->dev), fw_error); 3715 taskqueue_enqueue(reset_tq, &sc->fatal_error_task); 3716 } 3717 3718 void 3719 t4_add_adapter(struct adapter *sc) 3720 { 3721 sx_xlock(&t4_list_lock); 3722 SLIST_INSERT_HEAD(&t4_list, sc, link); 3723 sx_xunlock(&t4_list_lock); 3724 } 3725 3726 int 3727 t4_map_bars_0_and_4(struct adapter *sc) 3728 { 3729 sc->regs_rid = PCIR_BAR(0); 3730 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3731 &sc->regs_rid, RF_ACTIVE); 3732 if (sc->regs_res == NULL) { 3733 device_printf(sc->dev, "cannot map registers.\n"); 3734 return (ENXIO); 3735 } 3736 sc->bt = rman_get_bustag(sc->regs_res); 3737 sc->bh = rman_get_bushandle(sc->regs_res); 3738 sc->mmio_len = rman_get_size(sc->regs_res); 3739 setbit(&sc->doorbells, DOORBELL_KDB); 3740 3741 sc->msix_rid = PCIR_BAR(4); 3742 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3743 &sc->msix_rid, RF_ACTIVE); 3744 if (sc->msix_res == NULL) { 3745 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 3746 return (ENXIO); 3747 } 3748 3749 return (0); 3750 } 3751 3752 int 3753 t4_map_bar_2(struct adapter *sc) 3754 { 3755 3756 /* 3757 * T4: only iWARP driver uses the userspace doorbells. There is no need 3758 * to map it if RDMA is disabled. 3759 */ 3760 if (is_t4(sc) && sc->rdmacaps == 0) 3761 return (0); 3762 3763 sc->udbs_rid = PCIR_BAR(2); 3764 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3765 &sc->udbs_rid, RF_ACTIVE); 3766 if (sc->udbs_res == NULL) { 3767 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 3768 return (ENXIO); 3769 } 3770 sc->udbs_base = rman_get_virtual(sc->udbs_res); 3771 3772 if (chip_id(sc) >= CHELSIO_T5) { 3773 setbit(&sc->doorbells, DOORBELL_UDB); 3774 #if defined(__i386__) || defined(__amd64__) 3775 if (t5_write_combine) { 3776 int rc, mode; 3777 3778 /* 3779 * Enable write combining on BAR2. This is the 3780 * userspace doorbell BAR and is split into 128B 3781 * (UDBS_SEG_SIZE) doorbell regions, each associated 3782 * with an egress queue. The first 64B has the doorbell 3783 * and the second 64B can be used to submit a tx work 3784 * request with an implicit doorbell. 3785 */ 3786 3787 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 3788 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 3789 if (rc == 0) { 3790 clrbit(&sc->doorbells, DOORBELL_UDB); 3791 setbit(&sc->doorbells, DOORBELL_WCWR); 3792 setbit(&sc->doorbells, DOORBELL_UDBWC); 3793 } else { 3794 device_printf(sc->dev, 3795 "couldn't enable write combining: %d\n", 3796 rc); 3797 } 3798 3799 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 3800 t4_write_reg(sc, A_SGE_STAT_CFG, 3801 V_STATSOURCE_T5(7) | mode); 3802 } 3803 #endif 3804 } 3805 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 3806 3807 return (0); 3808 } 3809 3810 int 3811 t4_adj_doorbells(struct adapter *sc) 3812 { 3813 if ((sc->doorbells & t4_doorbells_allowed) != 0) { 3814 sc->doorbells &= t4_doorbells_allowed; 3815 return (0); 3816 } 3817 CH_ERR(sc, "No usable doorbell (available = 0x%x, allowed = 0x%x).\n", 3818 sc->doorbells, t4_doorbells_allowed); 3819 return (EINVAL); 3820 } 3821 3822 struct memwin_init { 3823 uint32_t base; 3824 uint32_t aperture; 3825 }; 3826 3827 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 3828 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3829 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3830 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 3831 }; 3832 3833 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 3834 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3835 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3836 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 3837 }; 3838 3839 static void 3840 setup_memwin(struct adapter *sc) 3841 { 3842 const struct memwin_init *mw_init; 3843 struct memwin *mw; 3844 int i; 3845 uint32_t bar0; 3846 3847 if (is_t4(sc)) { 3848 /* 3849 * Read low 32b of bar0 indirectly via the hardware backdoor 3850 * mechanism. Works from within PCI passthrough environments 3851 * too, where rman_get_start() can return a different value. We 3852 * need to program the T4 memory window decoders with the actual 3853 * addresses that will be coming across the PCIe link. 3854 */ 3855 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 3856 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 3857 3858 mw_init = &t4_memwin[0]; 3859 } else { 3860 /* T5+ use the relative offset inside the PCIe BAR */ 3861 bar0 = 0; 3862 3863 mw_init = &t5_memwin[0]; 3864 } 3865 3866 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 3867 if (!rw_initialized(&mw->mw_lock)) { 3868 rw_init(&mw->mw_lock, "memory window access"); 3869 mw->mw_base = mw_init->base; 3870 mw->mw_aperture = mw_init->aperture; 3871 mw->mw_curpos = 0; 3872 } 3873 t4_write_reg(sc, 3874 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 3875 (mw->mw_base + bar0) | V_BIR(0) | 3876 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 3877 rw_wlock(&mw->mw_lock); 3878 position_memwin(sc, i, mw->mw_curpos); 3879 rw_wunlock(&mw->mw_lock); 3880 } 3881 3882 /* flush */ 3883 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 3884 } 3885 3886 /* 3887 * Positions the memory window at the given address in the card's address space. 3888 * There are some alignment requirements and the actual position may be at an 3889 * address prior to the requested address. mw->mw_curpos always has the actual 3890 * position of the window. 3891 */ 3892 static void 3893 position_memwin(struct adapter *sc, int idx, uint32_t addr) 3894 { 3895 struct memwin *mw; 3896 uint32_t pf; 3897 uint32_t reg; 3898 3899 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3900 mw = &sc->memwin[idx]; 3901 rw_assert(&mw->mw_lock, RA_WLOCKED); 3902 3903 if (is_t4(sc)) { 3904 pf = 0; 3905 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 3906 } else { 3907 pf = V_PFNUM(sc->pf); 3908 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 3909 } 3910 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 3911 t4_write_reg(sc, reg, mw->mw_curpos | pf); 3912 t4_read_reg(sc, reg); /* flush */ 3913 } 3914 3915 int 3916 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 3917 int len, int rw) 3918 { 3919 struct memwin *mw; 3920 uint32_t mw_end, v; 3921 3922 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3923 3924 /* Memory can only be accessed in naturally aligned 4 byte units */ 3925 if (addr & 3 || len & 3 || len <= 0) 3926 return (EINVAL); 3927 3928 mw = &sc->memwin[idx]; 3929 while (len > 0) { 3930 rw_rlock(&mw->mw_lock); 3931 mw_end = mw->mw_curpos + mw->mw_aperture; 3932 if (addr >= mw_end || addr < mw->mw_curpos) { 3933 /* Will need to reposition the window */ 3934 if (!rw_try_upgrade(&mw->mw_lock)) { 3935 rw_runlock(&mw->mw_lock); 3936 rw_wlock(&mw->mw_lock); 3937 } 3938 rw_assert(&mw->mw_lock, RA_WLOCKED); 3939 position_memwin(sc, idx, addr); 3940 rw_downgrade(&mw->mw_lock); 3941 mw_end = mw->mw_curpos + mw->mw_aperture; 3942 } 3943 rw_assert(&mw->mw_lock, RA_RLOCKED); 3944 while (addr < mw_end && len > 0) { 3945 if (rw == 0) { 3946 v = t4_read_reg(sc, mw->mw_base + addr - 3947 mw->mw_curpos); 3948 *val++ = le32toh(v); 3949 } else { 3950 v = *val++; 3951 t4_write_reg(sc, mw->mw_base + addr - 3952 mw->mw_curpos, htole32(v)); 3953 } 3954 addr += 4; 3955 len -= 4; 3956 } 3957 rw_runlock(&mw->mw_lock); 3958 } 3959 3960 return (0); 3961 } 3962 3963 CTASSERT(M_TID_COOKIE == M_COOKIE); 3964 CTASSERT(MAX_ATIDS <= (M_TID_TID + 1)); 3965 3966 static void 3967 t4_init_atid_table(struct adapter *sc) 3968 { 3969 struct tid_info *t; 3970 int i; 3971 3972 t = &sc->tids; 3973 if (t->natids == 0) 3974 return; 3975 3976 MPASS(t->atid_tab == NULL); 3977 3978 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 3979 M_ZERO | M_WAITOK); 3980 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 3981 t->afree = t->atid_tab; 3982 t->atids_in_use = 0; 3983 t->atid_alloc_stopped = false; 3984 for (i = 1; i < t->natids; i++) 3985 t->atid_tab[i - 1].next = &t->atid_tab[i]; 3986 t->atid_tab[t->natids - 1].next = NULL; 3987 } 3988 3989 static void 3990 t4_free_atid_table(struct adapter *sc) 3991 { 3992 struct tid_info *t; 3993 3994 t = &sc->tids; 3995 3996 KASSERT(t->atids_in_use == 0, 3997 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 3998 3999 if (mtx_initialized(&t->atid_lock)) 4000 mtx_destroy(&t->atid_lock); 4001 free(t->atid_tab, M_CXGBE); 4002 t->atid_tab = NULL; 4003 } 4004 4005 static void 4006 stop_atid_allocator(struct adapter *sc) 4007 { 4008 struct tid_info *t = &sc->tids; 4009 4010 mtx_lock(&t->atid_lock); 4011 t->atid_alloc_stopped = true; 4012 mtx_unlock(&t->atid_lock); 4013 } 4014 4015 static void 4016 restart_atid_allocator(struct adapter *sc) 4017 { 4018 struct tid_info *t = &sc->tids; 4019 4020 mtx_lock(&t->atid_lock); 4021 KASSERT(t->atids_in_use == 0, 4022 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 4023 t->atid_alloc_stopped = false; 4024 mtx_unlock(&t->atid_lock); 4025 } 4026 4027 int 4028 alloc_atid(struct adapter *sc, void *ctx) 4029 { 4030 struct tid_info *t = &sc->tids; 4031 int atid = -1; 4032 4033 mtx_lock(&t->atid_lock); 4034 if (t->afree && !t->atid_alloc_stopped) { 4035 union aopen_entry *p = t->afree; 4036 4037 atid = p - t->atid_tab; 4038 MPASS(atid <= M_TID_TID); 4039 t->afree = p->next; 4040 p->data = ctx; 4041 t->atids_in_use++; 4042 } 4043 mtx_unlock(&t->atid_lock); 4044 return (atid); 4045 } 4046 4047 void * 4048 lookup_atid(struct adapter *sc, int atid) 4049 { 4050 struct tid_info *t = &sc->tids; 4051 4052 return (t->atid_tab[atid].data); 4053 } 4054 4055 void 4056 free_atid(struct adapter *sc, int atid) 4057 { 4058 struct tid_info *t = &sc->tids; 4059 union aopen_entry *p = &t->atid_tab[atid]; 4060 4061 mtx_lock(&t->atid_lock); 4062 p->next = t->afree; 4063 t->afree = p; 4064 t->atids_in_use--; 4065 mtx_unlock(&t->atid_lock); 4066 } 4067 4068 static void 4069 queue_tid_release(struct adapter *sc, int tid) 4070 { 4071 4072 CXGBE_UNIMPLEMENTED("deferred tid release"); 4073 } 4074 4075 void 4076 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 4077 { 4078 struct wrqe *wr; 4079 struct cpl_tid_release *req; 4080 4081 wr = alloc_wrqe(sizeof(*req), ctrlq); 4082 if (wr == NULL) { 4083 queue_tid_release(sc, tid); /* defer */ 4084 return; 4085 } 4086 req = wrtod(wr); 4087 4088 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 4089 4090 t4_wrq_tx(sc, wr); 4091 } 4092 4093 static int 4094 t4_range_cmp(const void *a, const void *b) 4095 { 4096 return ((const struct t4_range *)a)->start - 4097 ((const struct t4_range *)b)->start; 4098 } 4099 4100 /* 4101 * Verify that the memory range specified by the addr/len pair is valid within 4102 * the card's address space. 4103 */ 4104 static int 4105 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 4106 { 4107 struct t4_range mem_ranges[4], *r, *next; 4108 uint32_t em, addr_len; 4109 int i, n, remaining; 4110 4111 /* Memory can only be accessed in naturally aligned 4 byte units */ 4112 if (addr & 3 || len & 3 || len == 0) 4113 return (EINVAL); 4114 4115 /* Enabled memories */ 4116 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4117 4118 r = &mem_ranges[0]; 4119 n = 0; 4120 bzero(r, sizeof(mem_ranges)); 4121 if (em & F_EDRAM0_ENABLE) { 4122 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4123 r->size = G_EDRAM0_SIZE(addr_len) << 20; 4124 if (r->size > 0) { 4125 r->start = G_EDRAM0_BASE(addr_len) << 20; 4126 if (addr >= r->start && 4127 addr + len <= r->start + r->size) 4128 return (0); 4129 r++; 4130 n++; 4131 } 4132 } 4133 if (em & F_EDRAM1_ENABLE) { 4134 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4135 r->size = G_EDRAM1_SIZE(addr_len) << 20; 4136 if (r->size > 0) { 4137 r->start = G_EDRAM1_BASE(addr_len) << 20; 4138 if (addr >= r->start && 4139 addr + len <= r->start + r->size) 4140 return (0); 4141 r++; 4142 n++; 4143 } 4144 } 4145 if (em & F_EXT_MEM_ENABLE) { 4146 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4147 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 4148 if (r->size > 0) { 4149 r->start = G_EXT_MEM_BASE(addr_len) << 20; 4150 if (addr >= r->start && 4151 addr + len <= r->start + r->size) 4152 return (0); 4153 r++; 4154 n++; 4155 } 4156 } 4157 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 4158 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4159 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 4160 if (r->size > 0) { 4161 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 4162 if (addr >= r->start && 4163 addr + len <= r->start + r->size) 4164 return (0); 4165 r++; 4166 n++; 4167 } 4168 } 4169 MPASS(n <= nitems(mem_ranges)); 4170 4171 if (n > 1) { 4172 /* Sort and merge the ranges. */ 4173 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 4174 4175 /* Start from index 0 and examine the next n - 1 entries. */ 4176 r = &mem_ranges[0]; 4177 for (remaining = n - 1; remaining > 0; remaining--, r++) { 4178 4179 MPASS(r->size > 0); /* r is a valid entry. */ 4180 next = r + 1; 4181 MPASS(next->size > 0); /* and so is the next one. */ 4182 4183 while (r->start + r->size >= next->start) { 4184 /* Merge the next one into the current entry. */ 4185 r->size = max(r->start + r->size, 4186 next->start + next->size) - r->start; 4187 n--; /* One fewer entry in total. */ 4188 if (--remaining == 0) 4189 goto done; /* short circuit */ 4190 next++; 4191 } 4192 if (next != r + 1) { 4193 /* 4194 * Some entries were merged into r and next 4195 * points to the first valid entry that couldn't 4196 * be merged. 4197 */ 4198 MPASS(next->size > 0); /* must be valid */ 4199 memcpy(r + 1, next, remaining * sizeof(*r)); 4200 #ifdef INVARIANTS 4201 /* 4202 * This so that the foo->size assertion in the 4203 * next iteration of the loop do the right 4204 * thing for entries that were pulled up and are 4205 * no longer valid. 4206 */ 4207 MPASS(n < nitems(mem_ranges)); 4208 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 4209 sizeof(struct t4_range)); 4210 #endif 4211 } 4212 } 4213 done: 4214 /* Done merging the ranges. */ 4215 MPASS(n > 0); 4216 r = &mem_ranges[0]; 4217 for (i = 0; i < n; i++, r++) { 4218 if (addr >= r->start && 4219 addr + len <= r->start + r->size) 4220 return (0); 4221 } 4222 } 4223 4224 return (EFAULT); 4225 } 4226 4227 static int 4228 fwmtype_to_hwmtype(int mtype) 4229 { 4230 4231 switch (mtype) { 4232 case FW_MEMTYPE_EDC0: 4233 return (MEM_EDC0); 4234 case FW_MEMTYPE_EDC1: 4235 return (MEM_EDC1); 4236 case FW_MEMTYPE_EXTMEM: 4237 return (MEM_MC0); 4238 case FW_MEMTYPE_EXTMEM1: 4239 return (MEM_MC1); 4240 default: 4241 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 4242 } 4243 } 4244 4245 /* 4246 * Verify that the memory range specified by the memtype/offset/len pair is 4247 * valid and lies entirely within the memtype specified. The global address of 4248 * the start of the range is returned in addr. 4249 */ 4250 static int 4251 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 4252 uint32_t *addr) 4253 { 4254 uint32_t em, addr_len, maddr; 4255 4256 /* Memory can only be accessed in naturally aligned 4 byte units */ 4257 if (off & 3 || len & 3 || len == 0) 4258 return (EINVAL); 4259 4260 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4261 switch (fwmtype_to_hwmtype(mtype)) { 4262 case MEM_EDC0: 4263 if (!(em & F_EDRAM0_ENABLE)) 4264 return (EINVAL); 4265 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4266 maddr = G_EDRAM0_BASE(addr_len) << 20; 4267 break; 4268 case MEM_EDC1: 4269 if (!(em & F_EDRAM1_ENABLE)) 4270 return (EINVAL); 4271 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4272 maddr = G_EDRAM1_BASE(addr_len) << 20; 4273 break; 4274 case MEM_MC: 4275 if (!(em & F_EXT_MEM_ENABLE)) 4276 return (EINVAL); 4277 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4278 maddr = G_EXT_MEM_BASE(addr_len) << 20; 4279 break; 4280 case MEM_MC1: 4281 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 4282 return (EINVAL); 4283 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4284 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 4285 break; 4286 default: 4287 return (EINVAL); 4288 } 4289 4290 *addr = maddr + off; /* global address */ 4291 return (validate_mem_range(sc, *addr, len)); 4292 } 4293 4294 static int 4295 fixup_devlog_params(struct adapter *sc) 4296 { 4297 struct devlog_params *dparams = &sc->params.devlog; 4298 int rc; 4299 4300 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 4301 dparams->size, &dparams->addr); 4302 4303 return (rc); 4304 } 4305 4306 static void 4307 update_nirq(struct intrs_and_queues *iaq, int nports) 4308 { 4309 4310 iaq->nirq = T4_EXTRA_INTR; 4311 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq); 4312 iaq->nirq += nports * iaq->nofldrxq; 4313 iaq->nirq += nports * (iaq->num_vis - 1) * 4314 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 4315 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 4316 } 4317 4318 /* 4319 * Adjust requirements to fit the number of interrupts available. 4320 */ 4321 static void 4322 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 4323 int navail) 4324 { 4325 int old_nirq; 4326 const int nports = sc->params.nports; 4327 4328 MPASS(nports > 0); 4329 MPASS(navail > 0); 4330 4331 bzero(iaq, sizeof(*iaq)); 4332 iaq->intr_type = itype; 4333 iaq->num_vis = t4_num_vis; 4334 iaq->ntxq = t4_ntxq; 4335 iaq->ntxq_vi = t4_ntxq_vi; 4336 iaq->nrxq = t4_nrxq; 4337 iaq->nrxq_vi = t4_nrxq_vi; 4338 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4339 if (is_offload(sc) || is_ethoffload(sc)) { 4340 iaq->nofldtxq = t4_nofldtxq; 4341 iaq->nofldtxq_vi = t4_nofldtxq_vi; 4342 } 4343 #endif 4344 #ifdef TCP_OFFLOAD 4345 if (is_offload(sc)) { 4346 iaq->nofldrxq = t4_nofldrxq; 4347 iaq->nofldrxq_vi = t4_nofldrxq_vi; 4348 } 4349 #endif 4350 #ifdef DEV_NETMAP 4351 if (t4_native_netmap & NN_MAIN_VI) { 4352 iaq->nnmtxq = t4_nnmtxq; 4353 iaq->nnmrxq = t4_nnmrxq; 4354 } 4355 if (t4_native_netmap & NN_EXTRA_VI) { 4356 iaq->nnmtxq_vi = t4_nnmtxq_vi; 4357 iaq->nnmrxq_vi = t4_nnmrxq_vi; 4358 } 4359 #endif 4360 4361 update_nirq(iaq, nports); 4362 if (iaq->nirq <= navail && 4363 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4364 /* 4365 * This is the normal case -- there are enough interrupts for 4366 * everything. 4367 */ 4368 goto done; 4369 } 4370 4371 /* 4372 * If extra VIs have been configured try reducing their count and see if 4373 * that works. 4374 */ 4375 while (iaq->num_vis > 1) { 4376 iaq->num_vis--; 4377 update_nirq(iaq, nports); 4378 if (iaq->nirq <= navail && 4379 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4380 device_printf(sc->dev, "virtual interfaces per port " 4381 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 4382 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 4383 "itype %d, navail %u, nirq %d.\n", 4384 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 4385 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 4386 itype, navail, iaq->nirq); 4387 goto done; 4388 } 4389 } 4390 4391 /* 4392 * Extra VIs will not be created. Log a message if they were requested. 4393 */ 4394 MPASS(iaq->num_vis == 1); 4395 iaq->ntxq_vi = iaq->nrxq_vi = 0; 4396 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 4397 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 4398 if (iaq->num_vis != t4_num_vis) { 4399 device_printf(sc->dev, "extra virtual interfaces disabled. " 4400 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 4401 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 4402 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 4403 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 4404 } 4405 4406 /* 4407 * Keep reducing the number of NIC rx queues to the next lower power of 4408 * 2 (for even RSS distribution) and halving the TOE rx queues and see 4409 * if that works. 4410 */ 4411 do { 4412 if (iaq->nrxq > 1) { 4413 iaq->nrxq = rounddown_pow_of_two(iaq->nrxq - 1); 4414 if (iaq->nnmrxq > iaq->nrxq) 4415 iaq->nnmrxq = iaq->nrxq; 4416 } 4417 if (iaq->nofldrxq > 1) 4418 iaq->nofldrxq >>= 1; 4419 4420 old_nirq = iaq->nirq; 4421 update_nirq(iaq, nports); 4422 if (iaq->nirq <= navail && 4423 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4424 device_printf(sc->dev, "running with reduced number of " 4425 "rx queues because of shortage of interrupts. " 4426 "nrxq=%u, nofldrxq=%u. " 4427 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 4428 iaq->nofldrxq, itype, navail, iaq->nirq); 4429 goto done; 4430 } 4431 } while (old_nirq != iaq->nirq); 4432 4433 /* One interrupt for everything. Ugh. */ 4434 device_printf(sc->dev, "running with minimal number of queues. " 4435 "itype %d, navail %u.\n", itype, navail); 4436 iaq->nirq = 1; 4437 iaq->nrxq = 1; 4438 iaq->ntxq = 1; 4439 if (iaq->nofldrxq > 0) { 4440 iaq->nofldrxq = 1; 4441 iaq->nofldtxq = 1; 4442 } 4443 iaq->nnmtxq = 0; 4444 iaq->nnmrxq = 0; 4445 done: 4446 MPASS(iaq->num_vis > 0); 4447 if (iaq->num_vis > 1) { 4448 MPASS(iaq->nrxq_vi > 0); 4449 MPASS(iaq->ntxq_vi > 0); 4450 } 4451 MPASS(iaq->nirq > 0); 4452 MPASS(iaq->nrxq > 0); 4453 MPASS(iaq->ntxq > 0); 4454 if (itype == INTR_MSI) { 4455 MPASS(powerof2(iaq->nirq)); 4456 } 4457 } 4458 4459 static int 4460 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 4461 { 4462 int rc, itype, navail, nalloc; 4463 4464 for (itype = INTR_MSIX; itype; itype >>= 1) { 4465 4466 if ((itype & t4_intr_types) == 0) 4467 continue; /* not allowed */ 4468 4469 if (itype == INTR_MSIX) 4470 navail = pci_msix_count(sc->dev); 4471 else if (itype == INTR_MSI) 4472 navail = pci_msi_count(sc->dev); 4473 else 4474 navail = 1; 4475 restart: 4476 if (navail == 0) 4477 continue; 4478 4479 calculate_iaq(sc, iaq, itype, navail); 4480 nalloc = iaq->nirq; 4481 rc = 0; 4482 if (itype == INTR_MSIX) 4483 rc = pci_alloc_msix(sc->dev, &nalloc); 4484 else if (itype == INTR_MSI) 4485 rc = pci_alloc_msi(sc->dev, &nalloc); 4486 4487 if (rc == 0 && nalloc > 0) { 4488 if (nalloc == iaq->nirq) 4489 return (0); 4490 4491 /* 4492 * Didn't get the number requested. Use whatever number 4493 * the kernel is willing to allocate. 4494 */ 4495 device_printf(sc->dev, "fewer vectors than requested, " 4496 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 4497 itype, iaq->nirq, nalloc); 4498 pci_release_msi(sc->dev); 4499 navail = nalloc; 4500 goto restart; 4501 } 4502 4503 device_printf(sc->dev, 4504 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 4505 itype, rc, iaq->nirq, nalloc); 4506 } 4507 4508 device_printf(sc->dev, 4509 "failed to find a usable interrupt type. " 4510 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 4511 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 4512 4513 return (ENXIO); 4514 } 4515 4516 #define FW_VERSION(chip) ( \ 4517 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 4518 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 4519 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 4520 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 4521 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 4522 4523 /* Just enough of fw_hdr to cover all version info. */ 4524 struct fw_h { 4525 __u8 ver; 4526 __u8 chip; 4527 __be16 len512; 4528 __be32 fw_ver; 4529 __be32 tp_microcode_ver; 4530 __u8 intfver_nic; 4531 __u8 intfver_vnic; 4532 __u8 intfver_ofld; 4533 __u8 intfver_ri; 4534 __u8 intfver_iscsipdu; 4535 __u8 intfver_iscsi; 4536 __u8 intfver_fcoepdu; 4537 __u8 intfver_fcoe; 4538 }; 4539 /* Spot check a couple of fields. */ 4540 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 4541 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 4542 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 4543 4544 struct fw_info { 4545 uint8_t chip; 4546 char *kld_name; 4547 char *fw_mod_name; 4548 struct fw_h fw_h; 4549 } fw_info[] = { 4550 { 4551 .chip = CHELSIO_T4, 4552 .kld_name = "t4fw_cfg", 4553 .fw_mod_name = "t4fw", 4554 .fw_h = { 4555 .chip = FW_HDR_CHIP_T4, 4556 .fw_ver = htobe32(FW_VERSION(T4)), 4557 .intfver_nic = FW_INTFVER(T4, NIC), 4558 .intfver_vnic = FW_INTFVER(T4, VNIC), 4559 .intfver_ofld = FW_INTFVER(T4, OFLD), 4560 .intfver_ri = FW_INTFVER(T4, RI), 4561 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 4562 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4563 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 4564 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4565 }, 4566 }, { 4567 .chip = CHELSIO_T5, 4568 .kld_name = "t5fw_cfg", 4569 .fw_mod_name = "t5fw", 4570 .fw_h = { 4571 .chip = FW_HDR_CHIP_T5, 4572 .fw_ver = htobe32(FW_VERSION(T5)), 4573 .intfver_nic = FW_INTFVER(T5, NIC), 4574 .intfver_vnic = FW_INTFVER(T5, VNIC), 4575 .intfver_ofld = FW_INTFVER(T5, OFLD), 4576 .intfver_ri = FW_INTFVER(T5, RI), 4577 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 4578 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4579 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 4580 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4581 }, 4582 }, { 4583 .chip = CHELSIO_T6, 4584 .kld_name = "t6fw_cfg", 4585 .fw_mod_name = "t6fw", 4586 .fw_h = { 4587 .chip = FW_HDR_CHIP_T6, 4588 .fw_ver = htobe32(FW_VERSION(T6)), 4589 .intfver_nic = FW_INTFVER(T6, NIC), 4590 .intfver_vnic = FW_INTFVER(T6, VNIC), 4591 .intfver_ofld = FW_INTFVER(T6, OFLD), 4592 .intfver_ri = FW_INTFVER(T6, RI), 4593 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4594 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4595 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4596 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4597 }, 4598 } 4599 }; 4600 4601 static struct fw_info * 4602 find_fw_info(int chip) 4603 { 4604 int i; 4605 4606 for (i = 0; i < nitems(fw_info); i++) { 4607 if (fw_info[i].chip == chip) 4608 return (&fw_info[i]); 4609 } 4610 return (NULL); 4611 } 4612 4613 /* 4614 * Is the given firmware API compatible with the one the driver was compiled 4615 * with? 4616 */ 4617 static int 4618 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 4619 { 4620 4621 /* short circuit if it's the exact same firmware version */ 4622 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 4623 return (1); 4624 4625 /* 4626 * XXX: Is this too conservative? Perhaps I should limit this to the 4627 * features that are supported in the driver. 4628 */ 4629 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 4630 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 4631 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 4632 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 4633 return (1); 4634 #undef SAME_INTF 4635 4636 return (0); 4637 } 4638 4639 static int 4640 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 4641 const struct firmware **fw) 4642 { 4643 struct fw_info *fw_info; 4644 4645 *dcfg = NULL; 4646 if (fw != NULL) 4647 *fw = NULL; 4648 4649 fw_info = find_fw_info(chip_id(sc)); 4650 if (fw_info == NULL) { 4651 device_printf(sc->dev, 4652 "unable to look up firmware information for chip %d.\n", 4653 chip_id(sc)); 4654 return (EINVAL); 4655 } 4656 4657 *dcfg = firmware_get(fw_info->kld_name); 4658 if (*dcfg != NULL) { 4659 if (fw != NULL) 4660 *fw = firmware_get(fw_info->fw_mod_name); 4661 return (0); 4662 } 4663 4664 return (ENOENT); 4665 } 4666 4667 static void 4668 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 4669 const struct firmware *fw) 4670 { 4671 4672 if (fw != NULL) 4673 firmware_put(fw, FIRMWARE_UNLOAD); 4674 if (dcfg != NULL) 4675 firmware_put(dcfg, FIRMWARE_UNLOAD); 4676 } 4677 4678 /* 4679 * Return values: 4680 * 0 means no firmware install attempted. 4681 * ERESTART means a firmware install was attempted and was successful. 4682 * +ve errno means a firmware install was attempted but failed. 4683 */ 4684 static int 4685 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 4686 const struct fw_h *drv_fw, const char *reason, int *already) 4687 { 4688 const struct firmware *cfg, *fw; 4689 const uint32_t c = be32toh(card_fw->fw_ver); 4690 uint32_t d, k; 4691 int rc, fw_install; 4692 struct fw_h bundled_fw; 4693 bool load_attempted; 4694 4695 cfg = fw = NULL; 4696 load_attempted = false; 4697 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 4698 4699 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 4700 if (t4_fw_install < 0) { 4701 rc = load_fw_module(sc, &cfg, &fw); 4702 if (rc != 0 || fw == NULL) { 4703 device_printf(sc->dev, 4704 "failed to load firmware module: %d. cfg %p, fw %p;" 4705 " will use compiled-in firmware version for" 4706 "hw.cxgbe.fw_install checks.\n", 4707 rc, cfg, fw); 4708 } else { 4709 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 4710 } 4711 load_attempted = true; 4712 } 4713 d = be32toh(bundled_fw.fw_ver); 4714 4715 if (reason != NULL) 4716 goto install; 4717 4718 if ((sc->flags & FW_OK) == 0) { 4719 4720 if (c == 0xffffffff) { 4721 reason = "missing"; 4722 goto install; 4723 } 4724 4725 rc = 0; 4726 goto done; 4727 } 4728 4729 if (!fw_compatible(card_fw, &bundled_fw)) { 4730 reason = "incompatible or unusable"; 4731 goto install; 4732 } 4733 4734 if (d > c) { 4735 reason = "older than the version bundled with this driver"; 4736 goto install; 4737 } 4738 4739 if (fw_install == 2 && d != c) { 4740 reason = "different than the version bundled with this driver"; 4741 goto install; 4742 } 4743 4744 /* No reason to do anything to the firmware already on the card. */ 4745 rc = 0; 4746 goto done; 4747 4748 install: 4749 rc = 0; 4750 if ((*already)++) 4751 goto done; 4752 4753 if (fw_install == 0) { 4754 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4755 "but the driver is prohibited from installing a firmware " 4756 "on the card.\n", 4757 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4758 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4759 4760 goto done; 4761 } 4762 4763 /* 4764 * We'll attempt to install a firmware. Load the module first (if it 4765 * hasn't been loaded already). 4766 */ 4767 if (!load_attempted) { 4768 rc = load_fw_module(sc, &cfg, &fw); 4769 if (rc != 0 || fw == NULL) { 4770 device_printf(sc->dev, 4771 "failed to load firmware module: %d. cfg %p, fw %p\n", 4772 rc, cfg, fw); 4773 /* carry on */ 4774 } 4775 } 4776 if (fw == NULL) { 4777 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4778 "but the driver cannot take corrective action because it " 4779 "is unable to load the firmware module.\n", 4780 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4781 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4782 rc = sc->flags & FW_OK ? 0 : ENOENT; 4783 goto done; 4784 } 4785 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 4786 if (k != d) { 4787 MPASS(t4_fw_install > 0); 4788 device_printf(sc->dev, 4789 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 4790 "expecting (%u.%u.%u.%u) and will not be used.\n", 4791 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 4792 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 4793 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4794 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4795 rc = sc->flags & FW_OK ? 0 : EINVAL; 4796 goto done; 4797 } 4798 4799 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4800 "installing firmware %u.%u.%u.%u on card.\n", 4801 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4802 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 4803 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4804 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4805 4806 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 4807 if (rc != 0) { 4808 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 4809 } else { 4810 /* Installed successfully, update the cached header too. */ 4811 rc = ERESTART; 4812 memcpy(card_fw, fw->data, sizeof(*card_fw)); 4813 } 4814 done: 4815 unload_fw_module(sc, cfg, fw); 4816 4817 return (rc); 4818 } 4819 4820 /* 4821 * Establish contact with the firmware and attempt to become the master driver. 4822 * 4823 * A firmware will be installed to the card if needed (if the driver is allowed 4824 * to do so). 4825 */ 4826 static int 4827 contact_firmware(struct adapter *sc) 4828 { 4829 int rc, already = 0; 4830 enum dev_state state; 4831 struct fw_info *fw_info; 4832 struct fw_hdr *card_fw; /* fw on the card */ 4833 const struct fw_h *drv_fw; 4834 4835 fw_info = find_fw_info(chip_id(sc)); 4836 if (fw_info == NULL) { 4837 device_printf(sc->dev, 4838 "unable to look up firmware information for chip %d.\n", 4839 chip_id(sc)); 4840 return (EINVAL); 4841 } 4842 drv_fw = &fw_info->fw_h; 4843 4844 /* Read the header of the firmware on the card */ 4845 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 4846 restart: 4847 rc = -t4_get_fw_hdr(sc, card_fw); 4848 if (rc != 0) { 4849 device_printf(sc->dev, 4850 "unable to read firmware header from card's flash: %d\n", 4851 rc); 4852 goto done; 4853 } 4854 4855 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 4856 &already); 4857 if (rc == ERESTART) 4858 goto restart; 4859 if (rc != 0) 4860 goto done; 4861 4862 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 4863 if (rc < 0 || state == DEV_STATE_ERR) { 4864 rc = -rc; 4865 device_printf(sc->dev, 4866 "failed to connect to the firmware: %d, %d. " 4867 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4868 #if 0 4869 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4870 "not responding properly to HELLO", &already) == ERESTART) 4871 goto restart; 4872 #endif 4873 goto done; 4874 } 4875 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 4876 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 4877 4878 if (rc == sc->pf) { 4879 sc->flags |= MASTER_PF; 4880 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4881 NULL, &already); 4882 if (rc == ERESTART) 4883 rc = 0; 4884 else if (rc != 0) 4885 goto done; 4886 } else if (state == DEV_STATE_UNINIT) { 4887 /* 4888 * We didn't get to be the master so we definitely won't be 4889 * configuring the chip. It's a bug if someone else hasn't 4890 * configured it already. 4891 */ 4892 device_printf(sc->dev, "couldn't be master(%d), " 4893 "device not already initialized either(%d). " 4894 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4895 rc = EPROTO; 4896 goto done; 4897 } else { 4898 /* 4899 * Some other PF is the master and has configured the chip. 4900 * This is allowed but untested. 4901 */ 4902 device_printf(sc->dev, "PF%d is master, device state %d. " 4903 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4904 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 4905 sc->cfcsum = 0; 4906 rc = 0; 4907 } 4908 done: 4909 if (rc != 0 && sc->flags & FW_OK) { 4910 t4_fw_bye(sc, sc->mbox); 4911 sc->flags &= ~FW_OK; 4912 } 4913 free(card_fw, M_CXGBE); 4914 return (rc); 4915 } 4916 4917 static int 4918 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 4919 uint32_t mtype, uint32_t moff) 4920 { 4921 struct fw_info *fw_info; 4922 const struct firmware *dcfg, *rcfg = NULL; 4923 const uint32_t *cfdata; 4924 uint32_t cflen, addr; 4925 int rc; 4926 4927 load_fw_module(sc, &dcfg, NULL); 4928 4929 /* Card specific interpretation of "default". */ 4930 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4931 if (pci_get_device(sc->dev) == 0x440a) 4932 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 4933 if (is_fpga(sc)) 4934 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 4935 } 4936 4937 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4938 if (dcfg == NULL) { 4939 device_printf(sc->dev, 4940 "KLD with default config is not available.\n"); 4941 rc = ENOENT; 4942 goto done; 4943 } 4944 cfdata = dcfg->data; 4945 cflen = dcfg->datasize & ~3; 4946 } else { 4947 char s[32]; 4948 4949 fw_info = find_fw_info(chip_id(sc)); 4950 if (fw_info == NULL) { 4951 device_printf(sc->dev, 4952 "unable to look up firmware information for chip %d.\n", 4953 chip_id(sc)); 4954 rc = EINVAL; 4955 goto done; 4956 } 4957 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 4958 4959 rcfg = firmware_get(s); 4960 if (rcfg == NULL) { 4961 device_printf(sc->dev, 4962 "unable to load module \"%s\" for configuration " 4963 "profile \"%s\".\n", s, cfg_file); 4964 rc = ENOENT; 4965 goto done; 4966 } 4967 cfdata = rcfg->data; 4968 cflen = rcfg->datasize & ~3; 4969 } 4970 4971 if (cflen > FLASH_CFG_MAX_SIZE) { 4972 device_printf(sc->dev, 4973 "config file too long (%d, max allowed is %d).\n", 4974 cflen, FLASH_CFG_MAX_SIZE); 4975 rc = EINVAL; 4976 goto done; 4977 } 4978 4979 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 4980 if (rc != 0) { 4981 device_printf(sc->dev, 4982 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 4983 __func__, mtype, moff, cflen, rc); 4984 rc = EINVAL; 4985 goto done; 4986 } 4987 write_via_memwin(sc, 2, addr, cfdata, cflen); 4988 done: 4989 if (rcfg != NULL) 4990 firmware_put(rcfg, FIRMWARE_UNLOAD); 4991 unload_fw_module(sc, dcfg, NULL); 4992 return (rc); 4993 } 4994 4995 struct caps_allowed { 4996 uint16_t nbmcaps; 4997 uint16_t linkcaps; 4998 uint16_t switchcaps; 4999 uint16_t niccaps; 5000 uint16_t toecaps; 5001 uint16_t rdmacaps; 5002 uint16_t cryptocaps; 5003 uint16_t iscsicaps; 5004 uint16_t fcoecaps; 5005 }; 5006 5007 #define FW_PARAM_DEV(param) \ 5008 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 5009 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 5010 #define FW_PARAM_PFVF(param) \ 5011 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 5012 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 5013 5014 /* 5015 * Provide a configuration profile to the firmware and have it initialize the 5016 * chip accordingly. This may involve uploading a configuration file to the 5017 * card. 5018 */ 5019 static int 5020 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 5021 const struct caps_allowed *caps_allowed) 5022 { 5023 int rc; 5024 struct fw_caps_config_cmd caps; 5025 uint32_t mtype, moff, finicsum, cfcsum, param, val; 5026 5027 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 5028 if (rc != 0) { 5029 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 5030 return (rc); 5031 } 5032 5033 bzero(&caps, sizeof(caps)); 5034 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5035 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5036 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 5037 mtype = 0; 5038 moff = 0; 5039 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5040 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 5041 mtype = FW_MEMTYPE_FLASH; 5042 moff = t4_flash_cfg_addr(sc); 5043 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 5044 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 5045 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 5046 FW_LEN16(caps)); 5047 } else { 5048 /* 5049 * Ask the firmware where it wants us to upload the config file. 5050 */ 5051 param = FW_PARAM_DEV(CF); 5052 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5053 if (rc != 0) { 5054 /* No support for config file? Shouldn't happen. */ 5055 device_printf(sc->dev, 5056 "failed to query config file location: %d.\n", rc); 5057 goto done; 5058 } 5059 mtype = G_FW_PARAMS_PARAM_Y(val); 5060 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 5061 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 5062 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 5063 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 5064 FW_LEN16(caps)); 5065 5066 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 5067 if (rc != 0) { 5068 device_printf(sc->dev, 5069 "failed to upload config file to card: %d.\n", rc); 5070 goto done; 5071 } 5072 } 5073 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5074 if (rc != 0) { 5075 device_printf(sc->dev, "failed to pre-process config file: %d " 5076 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 5077 goto done; 5078 } 5079 5080 finicsum = be32toh(caps.finicsum); 5081 cfcsum = be32toh(caps.cfcsum); /* actual */ 5082 if (finicsum != cfcsum) { 5083 device_printf(sc->dev, 5084 "WARNING: config file checksum mismatch: %08x %08x\n", 5085 finicsum, cfcsum); 5086 } 5087 sc->cfcsum = cfcsum; 5088 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 5089 5090 /* 5091 * Let the firmware know what features will (not) be used so it can tune 5092 * things accordingly. 5093 */ 5094 #define LIMIT_CAPS(x) do { \ 5095 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 5096 } while (0) 5097 LIMIT_CAPS(nbm); 5098 LIMIT_CAPS(link); 5099 LIMIT_CAPS(switch); 5100 LIMIT_CAPS(nic); 5101 LIMIT_CAPS(toe); 5102 LIMIT_CAPS(rdma); 5103 LIMIT_CAPS(crypto); 5104 LIMIT_CAPS(iscsi); 5105 LIMIT_CAPS(fcoe); 5106 #undef LIMIT_CAPS 5107 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 5108 /* 5109 * TOE and hashfilters are mutually exclusive. It is a config 5110 * file or firmware bug if both are reported as available. Try 5111 * to cope with the situation in non-debug builds by disabling 5112 * TOE. 5113 */ 5114 MPASS(caps.toecaps == 0); 5115 5116 caps.toecaps = 0; 5117 caps.rdmacaps = 0; 5118 caps.iscsicaps = 0; 5119 } 5120 5121 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5122 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5123 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5124 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 5125 if (rc != 0) { 5126 device_printf(sc->dev, 5127 "failed to process config file: %d.\n", rc); 5128 goto done; 5129 } 5130 5131 t4_tweak_chip_settings(sc); 5132 set_params__pre_init(sc); 5133 5134 /* get basic stuff going */ 5135 rc = -t4_fw_initialize(sc, sc->mbox); 5136 if (rc != 0) { 5137 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 5138 goto done; 5139 } 5140 done: 5141 return (rc); 5142 } 5143 5144 /* 5145 * Partition chip resources for use between various PFs, VFs, etc. 5146 */ 5147 static int 5148 partition_resources(struct adapter *sc) 5149 { 5150 char cfg_file[sizeof(t4_cfg_file)]; 5151 struct caps_allowed caps_allowed; 5152 int rc; 5153 bool fallback; 5154 5155 /* Only the master driver gets to configure the chip resources. */ 5156 MPASS(sc->flags & MASTER_PF); 5157 5158 #define COPY_CAPS(x) do { \ 5159 caps_allowed.x##caps = t4_##x##caps_allowed; \ 5160 } while (0) 5161 bzero(&caps_allowed, sizeof(caps_allowed)); 5162 COPY_CAPS(nbm); 5163 COPY_CAPS(link); 5164 COPY_CAPS(switch); 5165 COPY_CAPS(nic); 5166 COPY_CAPS(toe); 5167 COPY_CAPS(rdma); 5168 COPY_CAPS(crypto); 5169 COPY_CAPS(iscsi); 5170 COPY_CAPS(fcoe); 5171 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 5172 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 5173 retry: 5174 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 5175 if (rc != 0 && fallback) { 5176 dump_devlog(sc); 5177 device_printf(sc->dev, 5178 "failed (%d) to configure card with \"%s\" profile, " 5179 "will fall back to a basic configuration and retry.\n", 5180 rc, cfg_file); 5181 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 5182 bzero(&caps_allowed, sizeof(caps_allowed)); 5183 COPY_CAPS(switch); 5184 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 5185 fallback = false; 5186 goto retry; 5187 } 5188 #undef COPY_CAPS 5189 return (rc); 5190 } 5191 5192 /* 5193 * Retrieve parameters that are needed (or nice to have) very early. 5194 */ 5195 static int 5196 get_params__pre_init(struct adapter *sc) 5197 { 5198 int rc; 5199 uint32_t param[2], val[2]; 5200 5201 t4_get_version_info(sc); 5202 5203 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 5204 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 5205 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 5206 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 5207 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 5208 5209 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 5210 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 5211 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 5212 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 5213 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 5214 5215 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 5216 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 5217 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 5218 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 5219 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 5220 5221 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 5222 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 5223 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 5224 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 5225 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 5226 5227 param[0] = FW_PARAM_DEV(PORTVEC); 5228 param[1] = FW_PARAM_DEV(CCLK); 5229 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5230 if (rc != 0) { 5231 device_printf(sc->dev, 5232 "failed to query parameters (pre_init): %d.\n", rc); 5233 return (rc); 5234 } 5235 5236 sc->params.portvec = val[0]; 5237 sc->params.nports = bitcount32(val[0]); 5238 sc->params.vpd.cclk = val[1]; 5239 5240 /* Read device log parameters. */ 5241 rc = -t4_init_devlog_params(sc, 1); 5242 if (rc == 0) 5243 fixup_devlog_params(sc); 5244 else { 5245 device_printf(sc->dev, 5246 "failed to get devlog parameters: %d.\n", rc); 5247 rc = 0; /* devlog isn't critical for device operation */ 5248 } 5249 5250 return (rc); 5251 } 5252 5253 /* 5254 * Any params that need to be set before FW_INITIALIZE. 5255 */ 5256 static int 5257 set_params__pre_init(struct adapter *sc) 5258 { 5259 int rc = 0; 5260 uint32_t param, val; 5261 5262 if (chip_id(sc) >= CHELSIO_T6) { 5263 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 5264 val = 1; 5265 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5266 /* firmwares < 1.20.1.0 do not have this param. */ 5267 if (rc == FW_EINVAL && 5268 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) { 5269 rc = 0; 5270 } 5271 if (rc != 0) { 5272 device_printf(sc->dev, 5273 "failed to enable high priority filters :%d.\n", 5274 rc); 5275 } 5276 5277 param = FW_PARAM_DEV(PPOD_EDRAM); 5278 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5279 if (rc == 0 && val == 1) { 5280 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, 5281 &val); 5282 if (rc != 0) { 5283 device_printf(sc->dev, 5284 "failed to set PPOD_EDRAM: %d.\n", rc); 5285 } 5286 } 5287 } 5288 5289 /* Enable opaque VIIDs with firmwares that support it. */ 5290 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 5291 val = 1; 5292 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5293 if (rc == 0 && val == 1) 5294 sc->params.viid_smt_extn_support = true; 5295 else 5296 sc->params.viid_smt_extn_support = false; 5297 5298 return (rc); 5299 } 5300 5301 /* 5302 * Retrieve various parameters that are of interest to the driver. The device 5303 * has been initialized by the firmware at this point. 5304 */ 5305 static int 5306 get_params__post_init(struct adapter *sc) 5307 { 5308 int rc; 5309 uint32_t param[7], val[7]; 5310 struct fw_caps_config_cmd caps; 5311 5312 param[0] = FW_PARAM_PFVF(IQFLINT_START); 5313 param[1] = FW_PARAM_PFVF(EQ_START); 5314 param[2] = FW_PARAM_PFVF(FILTER_START); 5315 param[3] = FW_PARAM_PFVF(FILTER_END); 5316 param[4] = FW_PARAM_PFVF(L2T_START); 5317 param[5] = FW_PARAM_PFVF(L2T_END); 5318 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5319 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5320 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 5321 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 5322 if (rc != 0) { 5323 device_printf(sc->dev, 5324 "failed to query parameters (post_init): %d.\n", rc); 5325 return (rc); 5326 } 5327 5328 sc->sge.iq_start = val[0]; 5329 sc->sge.eq_start = val[1]; 5330 if ((int)val[3] > (int)val[2]) { 5331 sc->tids.ftid_base = val[2]; 5332 sc->tids.ftid_end = val[3]; 5333 sc->tids.nftids = val[3] - val[2] + 1; 5334 } 5335 sc->vres.l2t.start = val[4]; 5336 sc->vres.l2t.size = val[5] - val[4] + 1; 5337 /* val[5] is the last hwidx and it must not collide with F_SYNC_WR */ 5338 if (sc->vres.l2t.size > 0) 5339 MPASS(fls(val[5]) <= S_SYNC_WR); 5340 sc->params.core_vdd = val[6]; 5341 5342 param[0] = FW_PARAM_PFVF(IQFLINT_END); 5343 param[1] = FW_PARAM_PFVF(EQ_END); 5344 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5345 if (rc != 0) { 5346 device_printf(sc->dev, 5347 "failed to query parameters (post_init2): %d.\n", rc); 5348 return (rc); 5349 } 5350 MPASS((int)val[0] >= sc->sge.iq_start); 5351 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1; 5352 MPASS((int)val[1] >= sc->sge.eq_start); 5353 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1; 5354 5355 if (chip_id(sc) >= CHELSIO_T6) { 5356 5357 sc->tids.tid_base = t4_read_reg(sc, 5358 A_LE_DB_ACTIVE_TABLE_START_INDEX); 5359 5360 param[0] = FW_PARAM_PFVF(HPFILTER_START); 5361 param[1] = FW_PARAM_PFVF(HPFILTER_END); 5362 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5363 if (rc != 0) { 5364 device_printf(sc->dev, 5365 "failed to query hpfilter parameters: %d.\n", rc); 5366 return (rc); 5367 } 5368 if ((int)val[1] > (int)val[0]) { 5369 sc->tids.hpftid_base = val[0]; 5370 sc->tids.hpftid_end = val[1]; 5371 sc->tids.nhpftids = val[1] - val[0] + 1; 5372 5373 /* 5374 * These should go off if the layout changes and the 5375 * driver needs to catch up. 5376 */ 5377 MPASS(sc->tids.hpftid_base == 0); 5378 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 5379 } 5380 5381 param[0] = FW_PARAM_PFVF(RAWF_START); 5382 param[1] = FW_PARAM_PFVF(RAWF_END); 5383 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5384 if (rc != 0) { 5385 device_printf(sc->dev, 5386 "failed to query rawf parameters: %d.\n", rc); 5387 return (rc); 5388 } 5389 if ((int)val[1] > (int)val[0]) { 5390 sc->rawf_base = val[0]; 5391 sc->nrawf = val[1] - val[0] + 1; 5392 } 5393 } 5394 5395 /* 5396 * The parameters that follow may not be available on all firmwares. We 5397 * query them individually rather than in a compound query because old 5398 * firmwares fail the entire query if an unknown parameter is queried. 5399 */ 5400 5401 /* 5402 * MPS buffer group configuration. 5403 */ 5404 param[0] = FW_PARAM_DEV(MPSBGMAP); 5405 val[0] = 0; 5406 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5407 if (rc == 0) 5408 sc->params.mps_bg_map = val[0]; 5409 else 5410 sc->params.mps_bg_map = UINT32_MAX; /* Not a legal value. */ 5411 5412 param[0] = FW_PARAM_DEV(TPCHMAP); 5413 val[0] = 0; 5414 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5415 if (rc == 0) 5416 sc->params.tp_ch_map = val[0]; 5417 else 5418 sc->params.tp_ch_map = UINT32_MAX; /* Not a legal value. */ 5419 5420 /* 5421 * Determine whether the firmware supports the filter2 work request. 5422 */ 5423 param[0] = FW_PARAM_DEV(FILTER2_WR); 5424 val[0] = 0; 5425 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5426 if (rc == 0) 5427 sc->params.filter2_wr_support = val[0] != 0; 5428 else 5429 sc->params.filter2_wr_support = 0; 5430 5431 /* 5432 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 5433 */ 5434 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 5435 val[0] = 0; 5436 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5437 if (rc == 0) 5438 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 5439 else 5440 sc->params.ulptx_memwrite_dsgl = false; 5441 5442 /* FW_RI_FR_NSMR_TPTE_WR support */ 5443 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 5444 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5445 if (rc == 0) 5446 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0; 5447 else 5448 sc->params.fr_nsmr_tpte_wr_support = false; 5449 5450 /* Support for 512 SGL entries per FR MR. */ 5451 param[0] = FW_PARAM_DEV(DEV_512SGL_MR); 5452 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5453 if (rc == 0) 5454 sc->params.dev_512sgl_mr = val[0] != 0; 5455 else 5456 sc->params.dev_512sgl_mr = false; 5457 5458 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 5459 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5460 if (rc == 0) 5461 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0]; 5462 else 5463 sc->params.max_pkts_per_eth_tx_pkts_wr = 15; 5464 5465 param[0] = FW_PARAM_DEV(NUM_TM_CLASS); 5466 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5467 if (rc == 0) { 5468 MPASS(val[0] > 0 && val[0] < 256); /* nsched_cls is 8b */ 5469 sc->params.nsched_cls = val[0]; 5470 } else 5471 sc->params.nsched_cls = sc->chip_params->nsched_cls; 5472 5473 /* get capabilites */ 5474 bzero(&caps, sizeof(caps)); 5475 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5476 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5477 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5478 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5479 if (rc != 0) { 5480 device_printf(sc->dev, 5481 "failed to get card capabilities: %d.\n", rc); 5482 return (rc); 5483 } 5484 5485 #define READ_CAPS(x) do { \ 5486 sc->x = htobe16(caps.x); \ 5487 } while (0) 5488 READ_CAPS(nbmcaps); 5489 READ_CAPS(linkcaps); 5490 READ_CAPS(switchcaps); 5491 READ_CAPS(niccaps); 5492 READ_CAPS(toecaps); 5493 READ_CAPS(rdmacaps); 5494 READ_CAPS(cryptocaps); 5495 READ_CAPS(iscsicaps); 5496 READ_CAPS(fcoecaps); 5497 5498 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 5499 MPASS(chip_id(sc) > CHELSIO_T4); 5500 MPASS(sc->toecaps == 0); 5501 sc->toecaps = 0; 5502 5503 param[0] = FW_PARAM_DEV(NTID); 5504 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5505 if (rc != 0) { 5506 device_printf(sc->dev, 5507 "failed to query HASHFILTER parameters: %d.\n", rc); 5508 return (rc); 5509 } 5510 sc->tids.ntids = val[0]; 5511 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5512 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5513 sc->tids.ntids -= sc->tids.nhpftids; 5514 } 5515 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5516 sc->params.hash_filter = 1; 5517 } 5518 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 5519 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 5520 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 5521 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5522 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 5523 if (rc != 0) { 5524 device_printf(sc->dev, 5525 "failed to query NIC parameters: %d.\n", rc); 5526 return (rc); 5527 } 5528 if ((int)val[1] > (int)val[0]) { 5529 sc->tids.etid_base = val[0]; 5530 sc->tids.etid_end = val[1]; 5531 sc->tids.netids = val[1] - val[0] + 1; 5532 sc->params.eo_wr_cred = val[2]; 5533 sc->params.ethoffload = 1; 5534 } 5535 } 5536 if (sc->toecaps) { 5537 /* query offload-related parameters */ 5538 param[0] = FW_PARAM_DEV(NTID); 5539 param[1] = FW_PARAM_PFVF(SERVER_START); 5540 param[2] = FW_PARAM_PFVF(SERVER_END); 5541 param[3] = FW_PARAM_PFVF(TDDP_START); 5542 param[4] = FW_PARAM_PFVF(TDDP_END); 5543 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5544 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5545 if (rc != 0) { 5546 device_printf(sc->dev, 5547 "failed to query TOE parameters: %d.\n", rc); 5548 return (rc); 5549 } 5550 sc->tids.ntids = val[0]; 5551 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5552 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5553 sc->tids.ntids -= sc->tids.nhpftids; 5554 } 5555 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5556 if ((int)val[2] > (int)val[1]) { 5557 sc->tids.stid_base = val[1]; 5558 sc->tids.nstids = val[2] - val[1] + 1; 5559 } 5560 sc->vres.ddp.start = val[3]; 5561 sc->vres.ddp.size = val[4] - val[3] + 1; 5562 sc->params.ofldq_wr_cred = val[5]; 5563 sc->params.offload = 1; 5564 } else { 5565 /* 5566 * The firmware attempts memfree TOE configuration for -SO cards 5567 * and will report toecaps=0 if it runs out of resources (this 5568 * depends on the config file). It may not report 0 for other 5569 * capabilities dependent on the TOE in this case. Set them to 5570 * 0 here so that the driver doesn't bother tracking resources 5571 * that will never be used. 5572 */ 5573 sc->iscsicaps = 0; 5574 sc->rdmacaps = 0; 5575 } 5576 if (sc->rdmacaps) { 5577 param[0] = FW_PARAM_PFVF(STAG_START); 5578 param[1] = FW_PARAM_PFVF(STAG_END); 5579 param[2] = FW_PARAM_PFVF(RQ_START); 5580 param[3] = FW_PARAM_PFVF(RQ_END); 5581 param[4] = FW_PARAM_PFVF(PBL_START); 5582 param[5] = FW_PARAM_PFVF(PBL_END); 5583 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5584 if (rc != 0) { 5585 device_printf(sc->dev, 5586 "failed to query RDMA parameters(1): %d.\n", rc); 5587 return (rc); 5588 } 5589 sc->vres.stag.start = val[0]; 5590 sc->vres.stag.size = val[1] - val[0] + 1; 5591 sc->vres.rq.start = val[2]; 5592 sc->vres.rq.size = val[3] - val[2] + 1; 5593 sc->vres.pbl.start = val[4]; 5594 sc->vres.pbl.size = val[5] - val[4] + 1; 5595 5596 param[0] = FW_PARAM_PFVF(SQRQ_START); 5597 param[1] = FW_PARAM_PFVF(SQRQ_END); 5598 param[2] = FW_PARAM_PFVF(CQ_START); 5599 param[3] = FW_PARAM_PFVF(CQ_END); 5600 param[4] = FW_PARAM_PFVF(OCQ_START); 5601 param[5] = FW_PARAM_PFVF(OCQ_END); 5602 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5603 if (rc != 0) { 5604 device_printf(sc->dev, 5605 "failed to query RDMA parameters(2): %d.\n", rc); 5606 return (rc); 5607 } 5608 sc->vres.qp.start = val[0]; 5609 sc->vres.qp.size = val[1] - val[0] + 1; 5610 sc->vres.cq.start = val[2]; 5611 sc->vres.cq.size = val[3] - val[2] + 1; 5612 sc->vres.ocq.start = val[4]; 5613 sc->vres.ocq.size = val[5] - val[4] + 1; 5614 5615 param[0] = FW_PARAM_PFVF(SRQ_START); 5616 param[1] = FW_PARAM_PFVF(SRQ_END); 5617 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 5618 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 5619 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 5620 if (rc != 0) { 5621 device_printf(sc->dev, 5622 "failed to query RDMA parameters(3): %d.\n", rc); 5623 return (rc); 5624 } 5625 sc->vres.srq.start = val[0]; 5626 sc->vres.srq.size = val[1] - val[0] + 1; 5627 sc->params.max_ordird_qp = val[2]; 5628 sc->params.max_ird_adapter = val[3]; 5629 } 5630 if (sc->iscsicaps) { 5631 param[0] = FW_PARAM_PFVF(ISCSI_START); 5632 param[1] = FW_PARAM_PFVF(ISCSI_END); 5633 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5634 if (rc != 0) { 5635 device_printf(sc->dev, 5636 "failed to query iSCSI parameters: %d.\n", rc); 5637 return (rc); 5638 } 5639 sc->vres.iscsi.start = val[0]; 5640 sc->vres.iscsi.size = val[1] - val[0] + 1; 5641 } 5642 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 5643 param[0] = FW_PARAM_PFVF(TLS_START); 5644 param[1] = FW_PARAM_PFVF(TLS_END); 5645 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5646 if (rc != 0) { 5647 device_printf(sc->dev, 5648 "failed to query TLS parameters: %d.\n", rc); 5649 return (rc); 5650 } 5651 sc->vres.key.start = val[0]; 5652 sc->vres.key.size = val[1] - val[0] + 1; 5653 } 5654 5655 /* 5656 * We've got the params we wanted to query directly from the firmware. 5657 * Grab some others via other means. 5658 */ 5659 t4_init_sge_params(sc); 5660 t4_init_tp_params(sc); 5661 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 5662 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 5663 5664 rc = t4_verify_chip_settings(sc); 5665 if (rc != 0) 5666 return (rc); 5667 t4_init_rx_buf_info(sc); 5668 5669 return (rc); 5670 } 5671 5672 #ifdef KERN_TLS 5673 static void 5674 ktls_tick(void *arg) 5675 { 5676 struct adapter *sc; 5677 uint32_t tstamp; 5678 5679 sc = arg; 5680 tstamp = tcp_ts_getticks(); 5681 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1); 5682 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31); 5683 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK); 5684 } 5685 5686 static int 5687 t6_config_kern_tls(struct adapter *sc, bool enable) 5688 { 5689 int rc; 5690 uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5691 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) | 5692 V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) | 5693 V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE); 5694 5695 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, ¶m); 5696 if (rc != 0) { 5697 CH_ERR(sc, "failed to %s NIC TLS: %d\n", 5698 enable ? "enable" : "disable", rc); 5699 return (rc); 5700 } 5701 5702 if (enable) { 5703 sc->flags |= KERN_TLS_ON; 5704 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc, 5705 C_HARDCLOCK); 5706 } else { 5707 sc->flags &= ~KERN_TLS_ON; 5708 callout_stop(&sc->ktls_tick); 5709 } 5710 5711 return (rc); 5712 } 5713 #endif 5714 5715 static int 5716 set_params__post_init(struct adapter *sc) 5717 { 5718 uint32_t mask, param, val; 5719 #ifdef TCP_OFFLOAD 5720 int i, v, shift; 5721 #endif 5722 5723 /* ask for encapsulated CPLs */ 5724 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 5725 val = 1; 5726 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5727 5728 /* Enable 32b port caps if the firmware supports it. */ 5729 param = FW_PARAM_PFVF(PORT_CAPS32); 5730 val = 1; 5731 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 5732 sc->params.port_caps32 = 1; 5733 5734 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 5735 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 5736 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 5737 V_MASKFILTER(val - 1)); 5738 5739 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER | 5740 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN | 5741 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5742 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM; 5743 val = 0; 5744 if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) { 5745 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE, 5746 F_ATTACKFILTERENABLE); 5747 val |= F_DROPERRORATTACK; 5748 } 5749 if (t4_drop_ip_fragments != 0) { 5750 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP, 5751 F_FRAGMENTDROP); 5752 val |= F_DROPERRORFRAG; 5753 } 5754 if (t4_drop_pkts_with_l2_errors != 0) 5755 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN; 5756 if (t4_drop_pkts_with_l3_errors != 0) { 5757 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN | 5758 F_DROPERRORCSUMIP; 5759 } 5760 if (t4_drop_pkts_with_l4_errors != 0) { 5761 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5762 F_DROPERRORTCPOPT | F_DROPERRORCSUM; 5763 } 5764 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val); 5765 5766 #ifdef TCP_OFFLOAD 5767 /* 5768 * Override the TOE timers with user provided tunables. This is not the 5769 * recommended way to change the timers (the firmware config file is) so 5770 * these tunables are not documented. 5771 * 5772 * All the timer tunables are in microseconds. 5773 */ 5774 if (t4_toe_keepalive_idle != 0) { 5775 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 5776 v &= M_KEEPALIVEIDLE; 5777 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 5778 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 5779 } 5780 if (t4_toe_keepalive_interval != 0) { 5781 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 5782 v &= M_KEEPALIVEINTVL; 5783 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 5784 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 5785 } 5786 if (t4_toe_keepalive_count != 0) { 5787 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 5788 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5789 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 5790 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 5791 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 5792 } 5793 if (t4_toe_rexmt_min != 0) { 5794 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 5795 v &= M_RXTMIN; 5796 t4_set_reg_field(sc, A_TP_RXT_MIN, 5797 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 5798 } 5799 if (t4_toe_rexmt_max != 0) { 5800 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 5801 v &= M_RXTMAX; 5802 t4_set_reg_field(sc, A_TP_RXT_MAX, 5803 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 5804 } 5805 if (t4_toe_rexmt_count != 0) { 5806 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 5807 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5808 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 5809 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 5810 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 5811 } 5812 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 5813 if (t4_toe_rexmt_backoff[i] != -1) { 5814 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 5815 shift = (i & 3) << 3; 5816 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 5817 M_TIMERBACKOFFINDEX0 << shift, v << shift); 5818 } 5819 } 5820 #endif 5821 5822 /* 5823 * Limit TOE connections to 2 reassembly "islands". This is 5824 * required to permit migrating TOE connections to either 5825 * ULP_MODE_TCPDDP or UPL_MODE_TLS. 5826 */ 5827 t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, V_PASSMODE(M_PASSMODE), 5828 V_PASSMODE(2)); 5829 5830 #ifdef KERN_TLS 5831 if (is_ktls(sc)) { 5832 sc->tlst.inline_keys = t4_tls_inline_keys; 5833 sc->tlst.combo_wrs = t4_tls_combo_wrs; 5834 if (t4_kern_tls != 0 && is_t6(sc)) 5835 t6_config_kern_tls(sc, true); 5836 } 5837 #endif 5838 return (0); 5839 } 5840 5841 #undef FW_PARAM_PFVF 5842 #undef FW_PARAM_DEV 5843 5844 static void 5845 t4_set_desc(struct adapter *sc) 5846 { 5847 struct adapter_params *p = &sc->params; 5848 5849 device_set_descf(sc->dev, "Chelsio %s", p->vpd.id); 5850 } 5851 5852 static inline void 5853 ifmedia_add4(struct ifmedia *ifm, int m) 5854 { 5855 5856 ifmedia_add(ifm, m, 0, NULL); 5857 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 5858 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 5859 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 5860 } 5861 5862 /* 5863 * This is the selected media, which is not quite the same as the active media. 5864 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 5865 * and active are not the same, and "media: Ethernet selected" otherwise. 5866 */ 5867 static void 5868 set_current_media(struct port_info *pi) 5869 { 5870 struct link_config *lc; 5871 struct ifmedia *ifm; 5872 int mword; 5873 u_int speed; 5874 5875 PORT_LOCK_ASSERT_OWNED(pi); 5876 5877 /* Leave current media alone if it's already set to IFM_NONE. */ 5878 ifm = &pi->media; 5879 if (ifm->ifm_cur != NULL && 5880 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 5881 return; 5882 5883 lc = &pi->link_cfg; 5884 if (lc->requested_aneg != AUTONEG_DISABLE && 5885 lc->pcaps & FW_PORT_CAP32_ANEG) { 5886 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 5887 return; 5888 } 5889 mword = IFM_ETHER | IFM_FDX; 5890 if (lc->requested_fc & PAUSE_TX) 5891 mword |= IFM_ETH_TXPAUSE; 5892 if (lc->requested_fc & PAUSE_RX) 5893 mword |= IFM_ETH_RXPAUSE; 5894 if (lc->requested_speed == 0) 5895 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 5896 else 5897 speed = lc->requested_speed; 5898 mword |= port_mword(pi, speed_to_fwcap(speed)); 5899 ifmedia_set(ifm, mword); 5900 } 5901 5902 /* 5903 * Returns true if the ifmedia list for the port cannot change. 5904 */ 5905 static bool 5906 fixed_ifmedia(struct port_info *pi) 5907 { 5908 5909 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 5910 pi->port_type == FW_PORT_TYPE_BT_XFI || 5911 pi->port_type == FW_PORT_TYPE_BT_XAUI || 5912 pi->port_type == FW_PORT_TYPE_KX4 || 5913 pi->port_type == FW_PORT_TYPE_KX || 5914 pi->port_type == FW_PORT_TYPE_KR || 5915 pi->port_type == FW_PORT_TYPE_BP_AP || 5916 pi->port_type == FW_PORT_TYPE_BP4_AP || 5917 pi->port_type == FW_PORT_TYPE_BP40_BA || 5918 pi->port_type == FW_PORT_TYPE_KR4_100G || 5919 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 5920 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 5921 } 5922 5923 static void 5924 build_medialist(struct port_info *pi) 5925 { 5926 uint32_t ss, speed; 5927 int unknown, mword, bit; 5928 struct link_config *lc; 5929 struct ifmedia *ifm; 5930 5931 PORT_LOCK_ASSERT_OWNED(pi); 5932 5933 if (pi->flags & FIXED_IFMEDIA) 5934 return; 5935 5936 /* 5937 * Rebuild the ifmedia list. 5938 */ 5939 ifm = &pi->media; 5940 ifmedia_removeall(ifm); 5941 lc = &pi->link_cfg; 5942 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */ 5943 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 5944 MPASS(ss != 0); 5945 no_media: 5946 MPASS(LIST_EMPTY(&ifm->ifm_list)); 5947 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 5948 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 5949 return; 5950 } 5951 5952 unknown = 0; 5953 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 5954 speed = 1 << bit; 5955 MPASS(speed & M_FW_PORT_CAP32_SPEED); 5956 if (ss & speed) { 5957 mword = port_mword(pi, speed); 5958 if (mword == IFM_NONE) { 5959 goto no_media; 5960 } else if (mword == IFM_UNKNOWN) 5961 unknown++; 5962 else 5963 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 5964 } 5965 } 5966 if (unknown > 0) /* Add one unknown for all unknown media types. */ 5967 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 5968 if (lc->pcaps & FW_PORT_CAP32_ANEG) 5969 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 5970 5971 set_current_media(pi); 5972 } 5973 5974 /* 5975 * Initialize the requested fields in the link config based on driver tunables. 5976 */ 5977 static void 5978 init_link_config(struct port_info *pi) 5979 { 5980 struct link_config *lc = &pi->link_cfg; 5981 5982 PORT_LOCK_ASSERT_OWNED(pi); 5983 5984 lc->requested_caps = 0; 5985 lc->requested_speed = 0; 5986 5987 if (t4_autoneg == 0) 5988 lc->requested_aneg = AUTONEG_DISABLE; 5989 else if (t4_autoneg == 1) 5990 lc->requested_aneg = AUTONEG_ENABLE; 5991 else 5992 lc->requested_aneg = AUTONEG_AUTO; 5993 5994 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 5995 PAUSE_AUTONEG); 5996 5997 if (t4_fec & FEC_AUTO) 5998 lc->requested_fec = FEC_AUTO; 5999 else if (t4_fec == 0) 6000 lc->requested_fec = FEC_NONE; 6001 else { 6002 /* -1 is handled by the FEC_AUTO block above and not here. */ 6003 lc->requested_fec = t4_fec & 6004 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE); 6005 if (lc->requested_fec == 0) 6006 lc->requested_fec = FEC_AUTO; 6007 } 6008 if (t4_force_fec < 0) 6009 lc->force_fec = -1; 6010 else if (t4_force_fec > 0) 6011 lc->force_fec = 1; 6012 else 6013 lc->force_fec = 0; 6014 } 6015 6016 /* 6017 * Makes sure that all requested settings comply with what's supported by the 6018 * port. Returns the number of settings that were invalid and had to be fixed. 6019 */ 6020 static int 6021 fixup_link_config(struct port_info *pi) 6022 { 6023 int n = 0; 6024 struct link_config *lc = &pi->link_cfg; 6025 uint32_t fwspeed; 6026 6027 PORT_LOCK_ASSERT_OWNED(pi); 6028 6029 /* Speed (when not autonegotiating) */ 6030 if (lc->requested_speed != 0) { 6031 fwspeed = speed_to_fwcap(lc->requested_speed); 6032 if ((fwspeed & lc->pcaps) == 0) { 6033 n++; 6034 lc->requested_speed = 0; 6035 } 6036 } 6037 6038 /* Link autonegotiation */ 6039 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 6040 lc->requested_aneg == AUTONEG_DISABLE || 6041 lc->requested_aneg == AUTONEG_AUTO); 6042 if (lc->requested_aneg == AUTONEG_ENABLE && 6043 !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 6044 n++; 6045 lc->requested_aneg = AUTONEG_AUTO; 6046 } 6047 6048 /* Flow control */ 6049 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 6050 if (lc->requested_fc & PAUSE_TX && 6051 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) { 6052 n++; 6053 lc->requested_fc &= ~PAUSE_TX; 6054 } 6055 if (lc->requested_fc & PAUSE_RX && 6056 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) { 6057 n++; 6058 lc->requested_fc &= ~PAUSE_RX; 6059 } 6060 if (!(lc->requested_fc & PAUSE_AUTONEG) && 6061 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) { 6062 n++; 6063 lc->requested_fc |= PAUSE_AUTONEG; 6064 } 6065 6066 /* FEC */ 6067 if ((lc->requested_fec & FEC_RS && 6068 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) || 6069 (lc->requested_fec & FEC_BASER_RS && 6070 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) { 6071 n++; 6072 lc->requested_fec = FEC_AUTO; 6073 } 6074 6075 return (n); 6076 } 6077 6078 /* 6079 * Apply the requested L1 settings, which are expected to be valid, to the 6080 * hardware. 6081 */ 6082 static int 6083 apply_link_config(struct port_info *pi) 6084 { 6085 struct adapter *sc = pi->adapter; 6086 struct link_config *lc = &pi->link_cfg; 6087 int rc; 6088 6089 #ifdef INVARIANTS 6090 ASSERT_SYNCHRONIZED_OP(sc); 6091 PORT_LOCK_ASSERT_OWNED(pi); 6092 6093 if (lc->requested_aneg == AUTONEG_ENABLE) 6094 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG); 6095 if (!(lc->requested_fc & PAUSE_AUTONEG)) 6096 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE); 6097 if (lc->requested_fc & PAUSE_TX) 6098 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX); 6099 if (lc->requested_fc & PAUSE_RX) 6100 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX); 6101 if (lc->requested_fec & FEC_RS) 6102 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS); 6103 if (lc->requested_fec & FEC_BASER_RS) 6104 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS); 6105 #endif 6106 if (!(sc->flags & IS_VF)) { 6107 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6108 if (rc != 0) { 6109 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 6110 return (rc); 6111 } 6112 } 6113 6114 /* 6115 * An L1_CFG will almost always result in a link-change event if the 6116 * link is up, and the driver will refresh the actual fec/fc/etc. when 6117 * the notification is processed. If the link is down then the actual 6118 * settings are meaningless. 6119 * 6120 * This takes care of the case where a change in the L1 settings may not 6121 * result in a notification. 6122 */ 6123 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 6124 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 6125 6126 return (0); 6127 } 6128 6129 #define FW_MAC_EXACT_CHUNK 7 6130 struct mcaddr_ctx { 6131 if_t ifp; 6132 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 6133 uint64_t hash; 6134 int i; 6135 int del; 6136 int rc; 6137 }; 6138 6139 static u_int 6140 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 6141 { 6142 struct mcaddr_ctx *ctx = arg; 6143 struct vi_info *vi = if_getsoftc(ctx->ifp); 6144 struct port_info *pi = vi->pi; 6145 struct adapter *sc = pi->adapter; 6146 6147 if (ctx->rc < 0) 6148 return (0); 6149 6150 ctx->mcaddr[ctx->i] = LLADDR(sdl); 6151 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i])); 6152 ctx->i++; 6153 6154 if (ctx->i == FW_MAC_EXACT_CHUNK) { 6155 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del, 6156 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0); 6157 if (ctx->rc < 0) { 6158 int j; 6159 6160 for (j = 0; j < ctx->i; j++) { 6161 if_printf(ctx->ifp, 6162 "failed to add mc address" 6163 " %02x:%02x:%02x:" 6164 "%02x:%02x:%02x rc=%d\n", 6165 ctx->mcaddr[j][0], ctx->mcaddr[j][1], 6166 ctx->mcaddr[j][2], ctx->mcaddr[j][3], 6167 ctx->mcaddr[j][4], ctx->mcaddr[j][5], 6168 -ctx->rc); 6169 } 6170 return (0); 6171 } 6172 ctx->del = 0; 6173 ctx->i = 0; 6174 } 6175 6176 return (1); 6177 } 6178 6179 /* 6180 * Program the port's XGMAC based on parameters in ifnet. The caller also 6181 * indicates which parameters should be programmed (the rest are left alone). 6182 */ 6183 int 6184 update_mac_settings(if_t ifp, int flags) 6185 { 6186 int rc = 0; 6187 struct vi_info *vi = if_getsoftc(ifp); 6188 struct port_info *pi = vi->pi; 6189 struct adapter *sc = pi->adapter; 6190 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 6191 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 6192 6193 ASSERT_SYNCHRONIZED_OP(sc); 6194 KASSERT(flags, ("%s: not told what to update.", __func__)); 6195 6196 if (flags & XGMAC_MTU) 6197 mtu = if_getmtu(ifp); 6198 6199 if (flags & XGMAC_PROMISC) 6200 promisc = if_getflags(ifp) & IFF_PROMISC ? 1 : 0; 6201 6202 if (flags & XGMAC_ALLMULTI) 6203 allmulti = if_getflags(ifp) & IFF_ALLMULTI ? 1 : 0; 6204 6205 if (flags & XGMAC_VLANEX) 6206 vlanex = if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING ? 1 : 0; 6207 6208 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 6209 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 6210 allmulti, 1, vlanex, false); 6211 if (rc) { 6212 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 6213 rc); 6214 return (rc); 6215 } 6216 } 6217 6218 if (flags & XGMAC_UCADDR) { 6219 uint8_t ucaddr[ETHER_ADDR_LEN]; 6220 6221 bcopy(if_getlladdr(ifp), ucaddr, sizeof(ucaddr)); 6222 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 6223 ucaddr, true, &vi->smt_idx); 6224 if (rc < 0) { 6225 rc = -rc; 6226 if_printf(ifp, "change_mac failed: %d\n", rc); 6227 return (rc); 6228 } else { 6229 vi->xact_addr_filt = rc; 6230 rc = 0; 6231 } 6232 } 6233 6234 if (flags & XGMAC_MCADDRS) { 6235 struct epoch_tracker et; 6236 struct mcaddr_ctx ctx; 6237 int j; 6238 6239 ctx.ifp = ifp; 6240 ctx.hash = 0; 6241 ctx.i = 0; 6242 ctx.del = 1; 6243 ctx.rc = 0; 6244 /* 6245 * Unlike other drivers, we accumulate list of pointers into 6246 * interface address lists and we need to keep it safe even 6247 * after if_foreach_llmaddr() returns, thus we must enter the 6248 * network epoch. 6249 */ 6250 NET_EPOCH_ENTER(et); 6251 if_foreach_llmaddr(ifp, add_maddr, &ctx); 6252 if (ctx.rc < 0) { 6253 NET_EPOCH_EXIT(et); 6254 rc = -ctx.rc; 6255 return (rc); 6256 } 6257 if (ctx.i > 0) { 6258 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 6259 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0); 6260 NET_EPOCH_EXIT(et); 6261 if (rc < 0) { 6262 rc = -rc; 6263 for (j = 0; j < ctx.i; j++) { 6264 if_printf(ifp, 6265 "failed to add mcast address" 6266 " %02x:%02x:%02x:" 6267 "%02x:%02x:%02x rc=%d\n", 6268 ctx.mcaddr[j][0], ctx.mcaddr[j][1], 6269 ctx.mcaddr[j][2], ctx.mcaddr[j][3], 6270 ctx.mcaddr[j][4], ctx.mcaddr[j][5], 6271 rc); 6272 } 6273 return (rc); 6274 } 6275 ctx.del = 0; 6276 } else 6277 NET_EPOCH_EXIT(et); 6278 6279 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0); 6280 if (rc != 0) 6281 if_printf(ifp, "failed to set mcast address hash: %d\n", 6282 rc); 6283 if (ctx.del == 0) { 6284 /* We clobbered the VXLAN entry if there was one. */ 6285 pi->vxlan_tcam_entry = false; 6286 } 6287 } 6288 6289 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 && 6290 pi->vxlan_tcam_entry == false) { 6291 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac, 6292 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 6293 true); 6294 if (rc < 0) { 6295 rc = -rc; 6296 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n", 6297 rc); 6298 } else { 6299 MPASS(rc == sc->rawf_base + pi->port_id); 6300 rc = 0; 6301 pi->vxlan_tcam_entry = true; 6302 } 6303 } 6304 6305 return (rc); 6306 } 6307 6308 /* 6309 * {begin|end}_synchronized_op must be called from the same thread. 6310 */ 6311 int 6312 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 6313 char *wmesg) 6314 { 6315 int rc, pri; 6316 6317 #ifdef WITNESS 6318 /* the caller thinks it's ok to sleep, but is it really? */ 6319 if (flags & SLEEP_OK) 6320 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 6321 "begin_synchronized_op"); 6322 #endif 6323 6324 if (INTR_OK) 6325 pri = PCATCH; 6326 else 6327 pri = 0; 6328 6329 ADAPTER_LOCK(sc); 6330 for (;;) { 6331 6332 if (vi && IS_DETACHING(vi)) { 6333 rc = ENXIO; 6334 goto done; 6335 } 6336 6337 if (!IS_BUSY(sc)) { 6338 rc = 0; 6339 break; 6340 } 6341 6342 if (!(flags & SLEEP_OK)) { 6343 rc = EBUSY; 6344 goto done; 6345 } 6346 6347 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 6348 rc = EINTR; 6349 goto done; 6350 } 6351 } 6352 6353 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 6354 SET_BUSY(sc); 6355 #ifdef INVARIANTS 6356 sc->last_op = wmesg; 6357 sc->last_op_thr = curthread; 6358 sc->last_op_flags = flags; 6359 #endif 6360 6361 done: 6362 if (!(flags & HOLD_LOCK) || rc) 6363 ADAPTER_UNLOCK(sc); 6364 6365 return (rc); 6366 } 6367 6368 /* 6369 * Tell if_ioctl and if_init that the VI is going away. This is 6370 * special variant of begin_synchronized_op and must be paired with a 6371 * call to end_vi_detach. 6372 */ 6373 void 6374 begin_vi_detach(struct adapter *sc, struct vi_info *vi) 6375 { 6376 ADAPTER_LOCK(sc); 6377 SET_DETACHING(vi); 6378 wakeup(&sc->flags); 6379 while (IS_BUSY(sc)) 6380 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 6381 SET_BUSY(sc); 6382 #ifdef INVARIANTS 6383 sc->last_op = "t4detach"; 6384 sc->last_op_thr = curthread; 6385 sc->last_op_flags = 0; 6386 #endif 6387 ADAPTER_UNLOCK(sc); 6388 } 6389 6390 void 6391 end_vi_detach(struct adapter *sc, struct vi_info *vi) 6392 { 6393 ADAPTER_LOCK(sc); 6394 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6395 CLR_BUSY(sc); 6396 CLR_DETACHING(vi); 6397 wakeup(&sc->flags); 6398 ADAPTER_UNLOCK(sc); 6399 } 6400 6401 /* 6402 * {begin|end}_synchronized_op must be called from the same thread. 6403 */ 6404 void 6405 end_synchronized_op(struct adapter *sc, int flags) 6406 { 6407 6408 if (flags & LOCK_HELD) 6409 ADAPTER_LOCK_ASSERT_OWNED(sc); 6410 else 6411 ADAPTER_LOCK(sc); 6412 6413 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6414 CLR_BUSY(sc); 6415 wakeup(&sc->flags); 6416 ADAPTER_UNLOCK(sc); 6417 } 6418 6419 static int 6420 cxgbe_init_synchronized(struct vi_info *vi) 6421 { 6422 struct port_info *pi = vi->pi; 6423 struct adapter *sc = pi->adapter; 6424 if_t ifp = vi->ifp; 6425 int rc = 0, i; 6426 struct sge_txq *txq; 6427 6428 ASSERT_SYNCHRONIZED_OP(sc); 6429 6430 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6431 return (0); /* already running */ 6432 6433 if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0)) 6434 return (rc); /* error message displayed already */ 6435 6436 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 6437 return (rc); /* error message displayed already */ 6438 6439 rc = update_mac_settings(ifp, XGMAC_ALL); 6440 if (rc) 6441 goto done; /* error message displayed already */ 6442 6443 PORT_LOCK(pi); 6444 if (pi->up_vis == 0) { 6445 t4_update_port_info(pi); 6446 fixup_link_config(pi); 6447 build_medialist(pi); 6448 apply_link_config(pi); 6449 } 6450 6451 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 6452 if (rc != 0) { 6453 if_printf(ifp, "enable_vi failed: %d\n", rc); 6454 PORT_UNLOCK(pi); 6455 goto done; 6456 } 6457 6458 /* 6459 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 6460 * if this changes. 6461 */ 6462 6463 for_each_txq(vi, i, txq) { 6464 TXQ_LOCK(txq); 6465 txq->eq.flags |= EQ_ENABLED; 6466 TXQ_UNLOCK(txq); 6467 } 6468 6469 /* 6470 * The first iq of the first port to come up is used for tracing. 6471 */ 6472 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 6473 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 6474 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 6475 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 6476 V_QUEUENUMBER(sc->traceq)); 6477 pi->flags |= HAS_TRACEQ; 6478 } 6479 6480 /* all ok */ 6481 pi->up_vis++; 6482 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 6483 if (pi->link_cfg.link_ok) 6484 t4_os_link_changed(pi); 6485 PORT_UNLOCK(pi); 6486 6487 mtx_lock(&vi->tick_mtx); 6488 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 6489 callout_reset(&vi->tick, hz, vi_tick, vi); 6490 else 6491 callout_reset(&vi->tick, hz, cxgbe_tick, vi); 6492 mtx_unlock(&vi->tick_mtx); 6493 done: 6494 if (rc != 0) 6495 cxgbe_uninit_synchronized(vi); 6496 6497 return (rc); 6498 } 6499 6500 /* 6501 * Idempotent. 6502 */ 6503 static int 6504 cxgbe_uninit_synchronized(struct vi_info *vi) 6505 { 6506 struct port_info *pi = vi->pi; 6507 struct adapter *sc = pi->adapter; 6508 if_t ifp = vi->ifp; 6509 int rc, i; 6510 struct sge_txq *txq; 6511 6512 ASSERT_SYNCHRONIZED_OP(sc); 6513 6514 if (!(vi->flags & VI_INIT_DONE)) { 6515 if (__predict_false(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6516 KASSERT(0, ("uninited VI is running")); 6517 if_printf(ifp, "uninited VI with running ifnet. " 6518 "vi->flags 0x%016lx, if_flags 0x%08x, " 6519 "if_drv_flags 0x%08x\n", vi->flags, if_getflags(ifp), 6520 if_getdrvflags(ifp)); 6521 } 6522 return (0); 6523 } 6524 6525 /* 6526 * Disable the VI so that all its data in either direction is discarded 6527 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 6528 * tick) intact as the TP can deliver negative advice or data that it's 6529 * holding in its RAM (for an offloaded connection) even after the VI is 6530 * disabled. 6531 */ 6532 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 6533 if (rc) { 6534 if_printf(ifp, "disable_vi failed: %d\n", rc); 6535 return (rc); 6536 } 6537 6538 for_each_txq(vi, i, txq) { 6539 TXQ_LOCK(txq); 6540 txq->eq.flags &= ~EQ_ENABLED; 6541 TXQ_UNLOCK(txq); 6542 } 6543 6544 mtx_lock(&vi->tick_mtx); 6545 callout_stop(&vi->tick); 6546 mtx_unlock(&vi->tick_mtx); 6547 6548 PORT_LOCK(pi); 6549 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6550 PORT_UNLOCK(pi); 6551 return (0); 6552 } 6553 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 6554 pi->up_vis--; 6555 if (pi->up_vis > 0) { 6556 PORT_UNLOCK(pi); 6557 return (0); 6558 } 6559 6560 pi->link_cfg.link_ok = false; 6561 pi->link_cfg.speed = 0; 6562 pi->link_cfg.link_down_rc = 255; 6563 t4_os_link_changed(pi); 6564 PORT_UNLOCK(pi); 6565 6566 return (0); 6567 } 6568 6569 /* 6570 * It is ok for this function to fail midway and return right away. t4_detach 6571 * will walk the entire sc->irq list and clean up whatever is valid. 6572 */ 6573 int 6574 t4_setup_intr_handlers(struct adapter *sc) 6575 { 6576 int rc, rid, p, q, v; 6577 char s[8]; 6578 struct irq *irq; 6579 struct port_info *pi; 6580 struct vi_info *vi; 6581 struct sge *sge = &sc->sge; 6582 struct sge_rxq *rxq; 6583 #ifdef TCP_OFFLOAD 6584 struct sge_ofld_rxq *ofld_rxq; 6585 #endif 6586 #ifdef DEV_NETMAP 6587 struct sge_nm_rxq *nm_rxq; 6588 #endif 6589 #ifdef RSS 6590 int nbuckets = rss_getnumbuckets(); 6591 #endif 6592 6593 /* 6594 * Setup interrupts. 6595 */ 6596 irq = &sc->irq[0]; 6597 rid = sc->intr_type == INTR_INTX ? 0 : 1; 6598 if (forwarding_intr_to_fwq(sc)) 6599 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 6600 6601 /* Multiple interrupts. */ 6602 if (sc->flags & IS_VF) 6603 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 6604 ("%s: too few intr.", __func__)); 6605 else 6606 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 6607 ("%s: too few intr.", __func__)); 6608 6609 /* The first one is always error intr on PFs */ 6610 if (!(sc->flags & IS_VF)) { 6611 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 6612 if (rc != 0) 6613 return (rc); 6614 irq++; 6615 rid++; 6616 } 6617 6618 /* The second one is always the firmware event queue (first on VFs) */ 6619 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 6620 if (rc != 0) 6621 return (rc); 6622 irq++; 6623 rid++; 6624 6625 for_each_port(sc, p) { 6626 pi = sc->port[p]; 6627 for_each_vi(pi, v, vi) { 6628 vi->first_intr = rid - 1; 6629 6630 if (vi->nnmrxq > 0) { 6631 int n = max(vi->nrxq, vi->nnmrxq); 6632 6633 rxq = &sge->rxq[vi->first_rxq]; 6634 #ifdef DEV_NETMAP 6635 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 6636 #endif 6637 for (q = 0; q < n; q++) { 6638 snprintf(s, sizeof(s), "%x%c%x", p, 6639 'a' + v, q); 6640 if (q < vi->nrxq) 6641 irq->rxq = rxq++; 6642 #ifdef DEV_NETMAP 6643 if (q < vi->nnmrxq) 6644 irq->nm_rxq = nm_rxq++; 6645 6646 if (irq->nm_rxq != NULL && 6647 irq->rxq == NULL) { 6648 /* Netmap rx only */ 6649 rc = t4_alloc_irq(sc, irq, rid, 6650 t4_nm_intr, irq->nm_rxq, s); 6651 } 6652 if (irq->nm_rxq != NULL && 6653 irq->rxq != NULL) { 6654 /* NIC and Netmap rx */ 6655 rc = t4_alloc_irq(sc, irq, rid, 6656 t4_vi_intr, irq, s); 6657 } 6658 #endif 6659 if (irq->rxq != NULL && 6660 irq->nm_rxq == NULL) { 6661 /* NIC rx only */ 6662 rc = t4_alloc_irq(sc, irq, rid, 6663 t4_intr, irq->rxq, s); 6664 } 6665 if (rc != 0) 6666 return (rc); 6667 #ifdef RSS 6668 if (q < vi->nrxq) { 6669 bus_bind_intr(sc->dev, irq->res, 6670 rss_getcpu(q % nbuckets)); 6671 } 6672 #endif 6673 irq++; 6674 rid++; 6675 vi->nintr++; 6676 } 6677 } else { 6678 for_each_rxq(vi, q, rxq) { 6679 snprintf(s, sizeof(s), "%x%c%x", p, 6680 'a' + v, q); 6681 rc = t4_alloc_irq(sc, irq, rid, 6682 t4_intr, rxq, s); 6683 if (rc != 0) 6684 return (rc); 6685 #ifdef RSS 6686 bus_bind_intr(sc->dev, irq->res, 6687 rss_getcpu(q % nbuckets)); 6688 #endif 6689 irq++; 6690 rid++; 6691 vi->nintr++; 6692 } 6693 } 6694 #ifdef TCP_OFFLOAD 6695 for_each_ofld_rxq(vi, q, ofld_rxq) { 6696 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 6697 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 6698 ofld_rxq, s); 6699 if (rc != 0) 6700 return (rc); 6701 irq++; 6702 rid++; 6703 vi->nintr++; 6704 } 6705 #endif 6706 } 6707 } 6708 MPASS(irq == &sc->irq[sc->intr_count]); 6709 6710 return (0); 6711 } 6712 6713 static void 6714 write_global_rss_key(struct adapter *sc) 6715 { 6716 #ifdef RSS 6717 int i; 6718 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6719 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6720 6721 CTASSERT(RSS_KEYSIZE == 40); 6722 6723 rss_getkey((void *)&raw_rss_key[0]); 6724 for (i = 0; i < nitems(rss_key); i++) { 6725 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 6726 } 6727 t4_write_rss_key(sc, &rss_key[0], -1, 1); 6728 #endif 6729 } 6730 6731 /* 6732 * Idempotent. 6733 */ 6734 static int 6735 adapter_full_init(struct adapter *sc) 6736 { 6737 int rc, i; 6738 6739 ASSERT_SYNCHRONIZED_OP(sc); 6740 6741 /* 6742 * queues that belong to the adapter (not any particular port). 6743 */ 6744 rc = t4_setup_adapter_queues(sc); 6745 if (rc != 0) 6746 return (rc); 6747 6748 MPASS(sc->params.nports <= nitems(sc->tq)); 6749 for (i = 0; i < sc->params.nports; i++) { 6750 if (sc->tq[i] != NULL) 6751 continue; 6752 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 6753 taskqueue_thread_enqueue, &sc->tq[i]); 6754 if (sc->tq[i] == NULL) { 6755 CH_ERR(sc, "failed to allocate task queue %d\n", i); 6756 return (ENOMEM); 6757 } 6758 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 6759 device_get_nameunit(sc->dev), i); 6760 } 6761 6762 if (!(sc->flags & IS_VF)) { 6763 write_global_rss_key(sc); 6764 t4_intr_enable(sc); 6765 } 6766 return (0); 6767 } 6768 6769 int 6770 adapter_init(struct adapter *sc) 6771 { 6772 int rc; 6773 6774 ASSERT_SYNCHRONIZED_OP(sc); 6775 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 6776 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 6777 ("%s: FULL_INIT_DONE already", __func__)); 6778 6779 rc = adapter_full_init(sc); 6780 if (rc != 0) 6781 adapter_full_uninit(sc); 6782 else 6783 sc->flags |= FULL_INIT_DONE; 6784 6785 return (rc); 6786 } 6787 6788 /* 6789 * Idempotent. 6790 */ 6791 static void 6792 adapter_full_uninit(struct adapter *sc) 6793 { 6794 int i; 6795 6796 t4_teardown_adapter_queues(sc); 6797 6798 for (i = 0; i < nitems(sc->tq); i++) { 6799 if (sc->tq[i] == NULL) 6800 continue; 6801 taskqueue_free(sc->tq[i]); 6802 sc->tq[i] = NULL; 6803 } 6804 6805 sc->flags &= ~FULL_INIT_DONE; 6806 } 6807 6808 #ifdef RSS 6809 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 6810 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 6811 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 6812 RSS_HASHTYPE_RSS_UDP_IPV6) 6813 6814 /* Translates kernel hash types to hardware. */ 6815 static int 6816 hashconfig_to_hashen(int hashconfig) 6817 { 6818 int hashen = 0; 6819 6820 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 6821 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 6822 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 6823 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 6824 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 6825 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6826 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6827 } 6828 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 6829 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6830 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6831 } 6832 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 6833 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6834 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 6835 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6836 6837 return (hashen); 6838 } 6839 6840 /* Translates hardware hash types to kernel. */ 6841 static int 6842 hashen_to_hashconfig(int hashen) 6843 { 6844 int hashconfig = 0; 6845 6846 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 6847 /* 6848 * If UDP hashing was enabled it must have been enabled for 6849 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 6850 * enabling any 4-tuple hash is nonsense configuration. 6851 */ 6852 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6853 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 6854 6855 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6856 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 6857 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6858 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 6859 } 6860 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6861 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 6862 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6863 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 6864 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6865 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 6866 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6867 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 6868 6869 return (hashconfig); 6870 } 6871 #endif 6872 6873 /* 6874 * Idempotent. 6875 */ 6876 static int 6877 vi_full_init(struct vi_info *vi) 6878 { 6879 struct adapter *sc = vi->adapter; 6880 struct sge_rxq *rxq; 6881 int rc, i, j; 6882 #ifdef RSS 6883 int nbuckets = rss_getnumbuckets(); 6884 int hashconfig = rss_gethashconfig(); 6885 int extra; 6886 #endif 6887 6888 ASSERT_SYNCHRONIZED_OP(sc); 6889 6890 /* 6891 * Allocate tx/rx/fl queues for this VI. 6892 */ 6893 rc = t4_setup_vi_queues(vi); 6894 if (rc != 0) 6895 return (rc); 6896 6897 /* 6898 * Setup RSS for this VI. Save a copy of the RSS table for later use. 6899 */ 6900 if (vi->nrxq > vi->rss_size) { 6901 CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); " 6902 "some queues will never receive traffic.\n", vi->nrxq, 6903 vi->rss_size); 6904 } else if (vi->rss_size % vi->nrxq) { 6905 CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); " 6906 "expect uneven traffic distribution.\n", vi->nrxq, 6907 vi->rss_size); 6908 } 6909 #ifdef RSS 6910 if (vi->nrxq != nbuckets) { 6911 CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);" 6912 "performance will be impacted.\n", vi->nrxq, nbuckets); 6913 } 6914 #endif 6915 if (vi->rss == NULL) 6916 vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE, 6917 M_ZERO | M_WAITOK); 6918 for (i = 0; i < vi->rss_size;) { 6919 #ifdef RSS 6920 j = rss_get_indirection_to_bucket(i); 6921 j %= vi->nrxq; 6922 rxq = &sc->sge.rxq[vi->first_rxq + j]; 6923 vi->rss[i++] = rxq->iq.abs_id; 6924 #else 6925 for_each_rxq(vi, j, rxq) { 6926 vi->rss[i++] = rxq->iq.abs_id; 6927 if (i == vi->rss_size) 6928 break; 6929 } 6930 #endif 6931 } 6932 6933 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 6934 vi->rss, vi->rss_size); 6935 if (rc != 0) { 6936 CH_ERR(vi, "rss_config failed: %d\n", rc); 6937 return (rc); 6938 } 6939 6940 #ifdef RSS 6941 vi->hashen = hashconfig_to_hashen(hashconfig); 6942 6943 /* 6944 * We may have had to enable some hashes even though the global config 6945 * wants them disabled. This is a potential problem that must be 6946 * reported to the user. 6947 */ 6948 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 6949 6950 /* 6951 * If we consider only the supported hash types, then the enabled hashes 6952 * are a superset of the requested hashes. In other words, there cannot 6953 * be any supported hash that was requested but not enabled, but there 6954 * can be hashes that were not requested but had to be enabled. 6955 */ 6956 extra &= SUPPORTED_RSS_HASHTYPES; 6957 MPASS((extra & hashconfig) == 0); 6958 6959 if (extra) { 6960 CH_ALERT(vi, 6961 "global RSS config (0x%x) cannot be accommodated.\n", 6962 hashconfig); 6963 } 6964 if (extra & RSS_HASHTYPE_RSS_IPV4) 6965 CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n"); 6966 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 6967 CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n"); 6968 if (extra & RSS_HASHTYPE_RSS_IPV6) 6969 CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n"); 6970 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 6971 CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n"); 6972 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 6973 CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n"); 6974 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 6975 CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n"); 6976 #else 6977 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 6978 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 6979 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6980 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 6981 #endif 6982 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 6983 0, 0); 6984 if (rc != 0) { 6985 CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc); 6986 return (rc); 6987 } 6988 6989 return (0); 6990 } 6991 6992 int 6993 vi_init(struct vi_info *vi) 6994 { 6995 int rc; 6996 6997 ASSERT_SYNCHRONIZED_OP(vi->adapter); 6998 KASSERT((vi->flags & VI_INIT_DONE) == 0, 6999 ("%s: VI_INIT_DONE already", __func__)); 7000 7001 rc = vi_full_init(vi); 7002 if (rc != 0) 7003 vi_full_uninit(vi); 7004 else 7005 vi->flags |= VI_INIT_DONE; 7006 7007 return (rc); 7008 } 7009 7010 /* 7011 * Idempotent. 7012 */ 7013 static void 7014 vi_full_uninit(struct vi_info *vi) 7015 { 7016 7017 if (vi->flags & VI_INIT_DONE) { 7018 quiesce_vi(vi); 7019 free(vi->rss, M_CXGBE); 7020 free(vi->nm_rss, M_CXGBE); 7021 } 7022 7023 t4_teardown_vi_queues(vi); 7024 vi->flags &= ~VI_INIT_DONE; 7025 } 7026 7027 static void 7028 quiesce_txq(struct sge_txq *txq) 7029 { 7030 struct sge_eq *eq = &txq->eq; 7031 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 7032 7033 MPASS(eq->flags & EQ_SW_ALLOCATED); 7034 MPASS(!(eq->flags & EQ_ENABLED)); 7035 7036 /* Wait for the mp_ring to empty. */ 7037 while (!mp_ring_is_idle(txq->r)) { 7038 mp_ring_check_drainage(txq->r, 4096); 7039 pause("rquiesce", 1); 7040 } 7041 MPASS(txq->txp.npkt == 0); 7042 7043 if (eq->flags & EQ_HW_ALLOCATED) { 7044 /* 7045 * Hardware is alive and working normally. Wait for it to 7046 * finish and then wait for the driver to catch up and reclaim 7047 * all descriptors. 7048 */ 7049 while (spg->cidx != htobe16(eq->pidx)) 7050 pause("equiesce", 1); 7051 while (eq->cidx != eq->pidx) 7052 pause("dquiesce", 1); 7053 } else { 7054 /* 7055 * Hardware is unavailable. Discard all pending tx and reclaim 7056 * descriptors directly. 7057 */ 7058 TXQ_LOCK(txq); 7059 while (eq->cidx != eq->pidx) { 7060 struct mbuf *m, *nextpkt; 7061 struct tx_sdesc *txsd; 7062 7063 txsd = &txq->sdesc[eq->cidx]; 7064 for (m = txsd->m; m != NULL; m = nextpkt) { 7065 nextpkt = m->m_nextpkt; 7066 m->m_nextpkt = NULL; 7067 m_freem(m); 7068 } 7069 IDXINCR(eq->cidx, txsd->desc_used, eq->sidx); 7070 } 7071 spg->pidx = spg->cidx = htobe16(eq->cidx); 7072 TXQ_UNLOCK(txq); 7073 } 7074 } 7075 7076 static void 7077 quiesce_wrq(struct sge_wrq *wrq) 7078 { 7079 struct wrqe *wr; 7080 7081 TXQ_LOCK(wrq); 7082 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 7083 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 7084 #ifdef INVARIANTS 7085 wrq->nwr_pending--; 7086 wrq->ndesc_needed -= howmany(wr->wr_len, EQ_ESIZE); 7087 #endif 7088 free(wr, M_CXGBE); 7089 } 7090 MPASS(wrq->nwr_pending == 0); 7091 MPASS(wrq->ndesc_needed == 0); 7092 wrq->nwr_pending = 0; 7093 wrq->ndesc_needed = 0; 7094 TXQ_UNLOCK(wrq); 7095 } 7096 7097 static void 7098 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 7099 { 7100 /* Synchronize with the interrupt handler */ 7101 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 7102 pause("iqfree", 1); 7103 7104 if (fl != NULL) { 7105 MPASS(iq->flags & IQ_HAS_FL); 7106 7107 mtx_lock(&sc->sfl_lock); 7108 FL_LOCK(fl); 7109 fl->flags |= FL_DOOMED; 7110 FL_UNLOCK(fl); 7111 callout_stop(&sc->sfl_callout); 7112 mtx_unlock(&sc->sfl_lock); 7113 7114 KASSERT((fl->flags & FL_STARVING) == 0, 7115 ("%s: still starving", __func__)); 7116 7117 /* Release all buffers if hardware is no longer available. */ 7118 if (!(iq->flags & IQ_HW_ALLOCATED)) 7119 free_fl_buffers(sc, fl); 7120 } 7121 } 7122 7123 /* 7124 * Wait for all activity on all the queues of the VI to complete. It is assumed 7125 * that no new work is being enqueued by the hardware or the driver. That part 7126 * should be arranged before calling this function. 7127 */ 7128 static void 7129 quiesce_vi(struct vi_info *vi) 7130 { 7131 int i; 7132 struct adapter *sc = vi->adapter; 7133 struct sge_rxq *rxq; 7134 struct sge_txq *txq; 7135 #ifdef TCP_OFFLOAD 7136 struct sge_ofld_rxq *ofld_rxq; 7137 #endif 7138 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7139 struct sge_ofld_txq *ofld_txq; 7140 #endif 7141 7142 if (!(vi->flags & VI_INIT_DONE)) 7143 return; 7144 7145 for_each_txq(vi, i, txq) { 7146 quiesce_txq(txq); 7147 } 7148 7149 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7150 for_each_ofld_txq(vi, i, ofld_txq) { 7151 quiesce_wrq(&ofld_txq->wrq); 7152 } 7153 #endif 7154 7155 for_each_rxq(vi, i, rxq) { 7156 quiesce_iq_fl(sc, &rxq->iq, &rxq->fl); 7157 } 7158 7159 #ifdef TCP_OFFLOAD 7160 for_each_ofld_rxq(vi, i, ofld_rxq) { 7161 quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl); 7162 } 7163 #endif 7164 } 7165 7166 static int 7167 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 7168 driver_intr_t *handler, void *arg, char *name) 7169 { 7170 int rc; 7171 7172 irq->rid = rid; 7173 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 7174 RF_SHAREABLE | RF_ACTIVE); 7175 if (irq->res == NULL) { 7176 device_printf(sc->dev, 7177 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 7178 return (ENOMEM); 7179 } 7180 7181 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 7182 NULL, handler, arg, &irq->tag); 7183 if (rc != 0) { 7184 device_printf(sc->dev, 7185 "failed to setup interrupt for rid %d, name %s: %d\n", 7186 rid, name, rc); 7187 } else if (name) 7188 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 7189 7190 return (rc); 7191 } 7192 7193 static int 7194 t4_free_irq(struct adapter *sc, struct irq *irq) 7195 { 7196 if (irq->tag) 7197 bus_teardown_intr(sc->dev, irq->res, irq->tag); 7198 if (irq->res) 7199 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 7200 7201 bzero(irq, sizeof(*irq)); 7202 7203 return (0); 7204 } 7205 7206 static void 7207 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 7208 { 7209 7210 regs->version = chip_id(sc) | chip_rev(sc) << 10; 7211 t4_get_regs(sc, buf, regs->len); 7212 } 7213 7214 #define A_PL_INDIR_CMD 0x1f8 7215 7216 #define S_PL_AUTOINC 31 7217 #define M_PL_AUTOINC 0x1U 7218 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 7219 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 7220 7221 #define S_PL_VFID 20 7222 #define M_PL_VFID 0xffU 7223 #define V_PL_VFID(x) ((x) << S_PL_VFID) 7224 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 7225 7226 #define S_PL_ADDR 0 7227 #define M_PL_ADDR 0xfffffU 7228 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 7229 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 7230 7231 #define A_PL_INDIR_DATA 0x1fc 7232 7233 static uint64_t 7234 read_vf_stat(struct adapter *sc, u_int vin, int reg) 7235 { 7236 u32 stats[2]; 7237 7238 if (sc->flags & IS_VF) { 7239 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 7240 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 7241 } else { 7242 mtx_assert(&sc->reg_lock, MA_OWNED); 7243 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 7244 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 7245 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 7246 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 7247 } 7248 return (((uint64_t)stats[1]) << 32 | stats[0]); 7249 } 7250 7251 static void 7252 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 7253 { 7254 7255 #define GET_STAT(name) \ 7256 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 7257 7258 if (!(sc->flags & IS_VF)) 7259 mtx_lock(&sc->reg_lock); 7260 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 7261 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 7262 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 7263 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 7264 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 7265 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 7266 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 7267 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 7268 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 7269 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 7270 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 7271 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 7272 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 7273 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 7274 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 7275 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 7276 if (!(sc->flags & IS_VF)) 7277 mtx_unlock(&sc->reg_lock); 7278 7279 #undef GET_STAT 7280 } 7281 7282 static void 7283 t4_clr_vi_stats(struct adapter *sc, u_int vin) 7284 { 7285 int reg; 7286 7287 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 7288 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 7289 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 7290 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 7291 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 7292 } 7293 7294 static void 7295 vi_refresh_stats(struct vi_info *vi) 7296 { 7297 struct timeval tv; 7298 const struct timeval interval = {0, 250000}; /* 250ms */ 7299 7300 mtx_assert(&vi->tick_mtx, MA_OWNED); 7301 7302 if (vi->flags & VI_SKIP_STATS) 7303 return; 7304 7305 getmicrotime(&tv); 7306 timevalsub(&tv, &interval); 7307 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7308 return; 7309 7310 t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats); 7311 getmicrotime(&vi->last_refreshed); 7312 } 7313 7314 static void 7315 cxgbe_refresh_stats(struct vi_info *vi) 7316 { 7317 u_int i, v, tnl_cong_drops, chan_map; 7318 struct timeval tv; 7319 const struct timeval interval = {0, 250000}; /* 250ms */ 7320 struct port_info *pi; 7321 struct adapter *sc; 7322 7323 mtx_assert(&vi->tick_mtx, MA_OWNED); 7324 7325 if (vi->flags & VI_SKIP_STATS) 7326 return; 7327 7328 getmicrotime(&tv); 7329 timevalsub(&tv, &interval); 7330 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7331 return; 7332 7333 pi = vi->pi; 7334 sc = vi->adapter; 7335 tnl_cong_drops = 0; 7336 t4_get_port_stats(sc, pi->port_id, &pi->stats); 7337 chan_map = pi->rx_e_chan_map; 7338 while (chan_map) { 7339 i = ffs(chan_map) - 1; 7340 mtx_lock(&sc->reg_lock); 7341 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 7342 A_TP_MIB_TNL_CNG_DROP_0 + i); 7343 mtx_unlock(&sc->reg_lock); 7344 tnl_cong_drops += v; 7345 chan_map &= ~(1 << i); 7346 } 7347 pi->tnl_cong_drops = tnl_cong_drops; 7348 getmicrotime(&vi->last_refreshed); 7349 } 7350 7351 static void 7352 cxgbe_tick(void *arg) 7353 { 7354 struct vi_info *vi = arg; 7355 7356 MPASS(IS_MAIN_VI(vi)); 7357 mtx_assert(&vi->tick_mtx, MA_OWNED); 7358 7359 cxgbe_refresh_stats(vi); 7360 callout_schedule(&vi->tick, hz); 7361 } 7362 7363 static void 7364 vi_tick(void *arg) 7365 { 7366 struct vi_info *vi = arg; 7367 7368 mtx_assert(&vi->tick_mtx, MA_OWNED); 7369 7370 vi_refresh_stats(vi); 7371 callout_schedule(&vi->tick, hz); 7372 } 7373 7374 /* 7375 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 7376 */ 7377 static char *caps_decoder[] = { 7378 "\20\001IPMI\002NCSI", /* 0: NBM */ 7379 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 7380 "\20\001INGRESS\002EGRESS", /* 2: switch */ 7381 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 7382 "\006HASHFILTER\007ETHOFLD", 7383 "\20\001TOE", /* 4: TOE */ 7384 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 7385 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 7386 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 7387 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 7388 "\007T10DIF" 7389 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 7390 "\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE" /* 7: Crypto */ 7391 "\004TLS_HW", 7392 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 7393 "\004PO_INITIATOR\005PO_TARGET", 7394 }; 7395 7396 void 7397 t4_sysctls(struct adapter *sc) 7398 { 7399 struct sysctl_ctx_list *ctx = &sc->ctx; 7400 struct sysctl_oid *oid; 7401 struct sysctl_oid_list *children, *c0; 7402 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 7403 7404 /* 7405 * dev.t4nex.X. 7406 */ 7407 oid = device_get_sysctl_tree(sc->dev); 7408 c0 = children = SYSCTL_CHILDREN(oid); 7409 7410 sc->sc_do_rxcopy = 1; 7411 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 7412 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 7413 7414 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 7415 sc->params.nports, "# of ports"); 7416 7417 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 7418 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells, 7419 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A", 7420 "available doorbells"); 7421 7422 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 7423 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 7424 7425 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 7426 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7427 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val), 7428 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 7429 7430 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 7431 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7432 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val), 7433 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 7434 7435 t4_sge_sysctls(sc, ctx, children); 7436 7437 sc->lro_timeout = 100; 7438 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 7439 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 7440 7441 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 7442 &sc->debug_flags, 0, "flags to enable runtime debugging"); 7443 7444 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 7445 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 7446 7447 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 7448 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 7449 7450 if (sc->flags & IS_VF) 7451 return; 7452 7453 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 7454 NULL, chip_rev(sc), "chip hardware revision"); 7455 7456 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 7457 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 7458 7459 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 7460 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 7461 7462 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 7463 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 7464 7465 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 7466 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 7467 7468 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 7469 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 7470 7471 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 7472 sc->er_version, 0, "expansion ROM version"); 7473 7474 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 7475 sc->bs_version, 0, "bootstrap firmware version"); 7476 7477 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 7478 NULL, sc->params.scfg_vers, "serial config version"); 7479 7480 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 7481 NULL, sc->params.vpd_vers, "VPD version"); 7482 7483 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 7484 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 7485 7486 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 7487 sc->cfcsum, "config file checksum"); 7488 7489 #define SYSCTL_CAP(name, n, text) \ 7490 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 7491 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \ 7492 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \ 7493 "available " text " capabilities") 7494 7495 SYSCTL_CAP(nbmcaps, 0, "NBM"); 7496 SYSCTL_CAP(linkcaps, 1, "link"); 7497 SYSCTL_CAP(switchcaps, 2, "switch"); 7498 SYSCTL_CAP(niccaps, 3, "NIC"); 7499 SYSCTL_CAP(toecaps, 4, "TCP offload"); 7500 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 7501 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 7502 SYSCTL_CAP(cryptocaps, 7, "crypto"); 7503 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 7504 #undef SYSCTL_CAP 7505 7506 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 7507 NULL, sc->tids.nftids, "number of filters"); 7508 7509 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7510 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7511 sysctl_temperature, "I", "chip temperature (in Celsius)"); 7512 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", 7513 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7514 sysctl_reset_sensor, "I", "reset the chip's temperature sensor."); 7515 7516 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", 7517 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7518 sysctl_loadavg, "A", 7519 "microprocessor load averages (debug firmwares only)"); 7520 7521 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", 7522 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd, 7523 "I", "core Vdd (in mV)"); 7524 7525 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 7526 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS, 7527 sysctl_cpus, "A", "local CPUs"); 7528 7529 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 7530 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS, 7531 sysctl_cpus, "A", "preferred CPUs for interrupts"); 7532 7533 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 7534 &sc->swintr, 0, "software triggered interrupts"); 7535 7536 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset", 7537 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I", 7538 "1 = reset adapter, 0 = zero reset counter"); 7539 7540 /* 7541 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 7542 */ 7543 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 7544 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL, 7545 "logs and miscellaneous information"); 7546 children = SYSCTL_CHILDREN(oid); 7547 7548 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 7549 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7550 sysctl_cctrl, "A", "congestion control"); 7551 7552 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 7553 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7554 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 7555 7556 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 7557 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7558 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 7559 7560 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 7561 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7562 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 7563 7564 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 7565 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3, 7566 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 7567 7568 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 7569 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4, 7570 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 7571 7572 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 7573 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5, 7574 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 7575 7576 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 7577 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7578 sysctl_cim_la, "A", "CIM logic analyzer"); 7579 7580 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 7581 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7582 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 7583 7584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 7585 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7586 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 7587 7588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 7589 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7590 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 7591 7592 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 7593 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7594 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 7595 7596 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 7597 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7598 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 7599 7600 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 7601 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7602 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 7603 7604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 7605 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7606 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 7607 7608 if (chip_id(sc) > CHELSIO_T4) { 7609 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 7610 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7611 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7612 "CIM OBQ 6 (SGE0-RX)"); 7613 7614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 7615 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7616 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7617 "CIM OBQ 7 (SGE1-RX)"); 7618 } 7619 7620 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 7621 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7622 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 7623 7624 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 7625 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7626 sysctl_cim_qcfg, "A", "CIM queue configuration"); 7627 7628 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 7629 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7630 sysctl_cpl_stats, "A", "CPL statistics"); 7631 7632 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 7633 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7634 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 7635 7636 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats", 7637 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7638 sysctl_tid_stats, "A", "tid stats"); 7639 7640 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 7641 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7642 sysctl_devlog, "A", "firmware's device log"); 7643 7644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 7645 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7646 sysctl_fcoe_stats, "A", "FCoE statistics"); 7647 7648 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 7649 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7650 sysctl_hw_sched, "A", "hardware scheduler "); 7651 7652 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 7653 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7654 sysctl_l2t, "A", "hardware L2 table"); 7655 7656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 7657 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7658 sysctl_smt, "A", "hardware source MAC table"); 7659 7660 #ifdef INET6 7661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 7662 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7663 sysctl_clip, "A", "active CLIP table entries"); 7664 #endif 7665 7666 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 7667 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7668 sysctl_lb_stats, "A", "loopback statistics"); 7669 7670 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 7671 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7672 sysctl_meminfo, "A", "memory regions"); 7673 7674 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 7675 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7676 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 7677 "A", "MPS TCAM entries"); 7678 7679 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 7680 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7681 sysctl_path_mtus, "A", "path MTUs"); 7682 7683 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 7684 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7685 sysctl_pm_stats, "A", "PM statistics"); 7686 7687 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 7688 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7689 sysctl_rdma_stats, "A", "RDMA statistics"); 7690 7691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 7692 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7693 sysctl_tcp_stats, "A", "TCP statistics"); 7694 7695 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 7696 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7697 sysctl_tids, "A", "TID information"); 7698 7699 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 7700 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7701 sysctl_tp_err_stats, "A", "TP error statistics"); 7702 7703 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats", 7704 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7705 sysctl_tnl_stats, "A", "TP tunnel statistics"); 7706 7707 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 7708 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7709 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask"); 7710 7711 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 7712 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7713 sysctl_tp_la, "A", "TP logic analyzer"); 7714 7715 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 7716 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7717 sysctl_tx_rate, "A", "Tx rate"); 7718 7719 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 7720 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7721 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 7722 7723 if (chip_id(sc) >= CHELSIO_T5) { 7724 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 7725 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7726 sysctl_wcwr_stats, "A", "write combined work requests"); 7727 } 7728 7729 #ifdef KERN_TLS 7730 if (is_ktls(sc)) { 7731 /* 7732 * dev.t4nex.0.tls. 7733 */ 7734 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", 7735 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters"); 7736 children = SYSCTL_CHILDREN(oid); 7737 7738 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys", 7739 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS " 7740 "keys in work requests (1) or attempt to store TLS keys " 7741 "in card memory."); 7742 7743 if (is_t6(sc)) 7744 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs", 7745 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to " 7746 "combine TCB field updates with TLS record work " 7747 "requests."); 7748 } 7749 #endif 7750 7751 #ifdef TCP_OFFLOAD 7752 if (is_offload(sc)) { 7753 int i; 7754 char s[4]; 7755 7756 /* 7757 * dev.t4nex.X.toe. 7758 */ 7759 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", 7760 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters"); 7761 children = SYSCTL_CHILDREN(oid); 7762 7763 sc->tt.cong_algorithm = -1; 7764 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 7765 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 7766 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 7767 "3 = highspeed)"); 7768 7769 sc->tt.sndbuf = -1; 7770 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 7771 &sc->tt.sndbuf, 0, "hardware send buffer"); 7772 7773 sc->tt.ddp = 0; 7774 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", 7775 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, ""); 7776 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW, 7777 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)"); 7778 7779 sc->tt.rx_coalesce = -1; 7780 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 7781 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 7782 7783 sc->tt.tls = 0; 7784 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT | 7785 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I", 7786 "Inline TLS allowed"); 7787 7788 sc->tt.tx_align = -1; 7789 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 7790 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 7791 7792 sc->tt.tx_zcopy = 0; 7793 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 7794 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 7795 "Enable zero-copy aio_write(2)"); 7796 7797 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 7798 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7799 "cop_managed_offloading", CTLFLAG_RW, 7800 &sc->tt.cop_managed_offloading, 0, 7801 "COP (Connection Offload Policy) controls all TOE offload"); 7802 7803 sc->tt.autorcvbuf_inc = 16 * 1024; 7804 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 7805 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 7806 "autorcvbuf increment"); 7807 7808 sc->tt.update_hc_on_pmtu_change = 1; 7809 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7810 "update_hc_on_pmtu_change", CTLFLAG_RW, 7811 &sc->tt.update_hc_on_pmtu_change, 0, 7812 "Update hostcache entry if the PMTU changes"); 7813 7814 sc->tt.iso = 1; 7815 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW, 7816 &sc->tt.iso, 0, "Enable iSCSI segmentation offload"); 7817 7818 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 7819 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7820 sysctl_tp_tick, "A", "TP timer tick (us)"); 7821 7822 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 7823 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7824 sysctl_tp_tick, "A", "TCP timestamp tick (us)"); 7825 7826 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 7827 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7828 sysctl_tp_tick, "A", "DACK tick (us)"); 7829 7830 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 7831 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7832 sysctl_tp_dack_timer, "IU", "DACK timer (us)"); 7833 7834 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 7835 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7836 A_TP_RXT_MIN, sysctl_tp_timer, "LU", 7837 "Minimum retransmit interval (us)"); 7838 7839 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 7840 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7841 A_TP_RXT_MAX, sysctl_tp_timer, "LU", 7842 "Maximum retransmit interval (us)"); 7843 7844 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 7845 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7846 A_TP_PERS_MIN, sysctl_tp_timer, "LU", 7847 "Persist timer min (us)"); 7848 7849 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 7850 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7851 A_TP_PERS_MAX, sysctl_tp_timer, "LU", 7852 "Persist timer max (us)"); 7853 7854 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 7855 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7856 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU", 7857 "Keepalive idle timer (us)"); 7858 7859 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 7860 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7861 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU", 7862 "Keepalive interval timer (us)"); 7863 7864 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 7865 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7866 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)"); 7867 7868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 7869 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7870 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU", 7871 "FINWAIT2 timer (us)"); 7872 7873 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 7874 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7875 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU", 7876 "Number of SYN retransmissions before abort"); 7877 7878 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 7879 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7880 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU", 7881 "Number of retransmissions before abort"); 7882 7883 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 7884 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7885 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU", 7886 "Number of keepalive probes before abort"); 7887 7888 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 7889 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7890 "TOE retransmit backoffs"); 7891 children = SYSCTL_CHILDREN(oid); 7892 for (i = 0; i < 16; i++) { 7893 snprintf(s, sizeof(s), "%u", i); 7894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 7895 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7896 i, sysctl_tp_backoff, "IU", 7897 "TOE retransmit backoff"); 7898 } 7899 } 7900 #endif 7901 } 7902 7903 void 7904 vi_sysctls(struct vi_info *vi) 7905 { 7906 struct sysctl_ctx_list *ctx = &vi->ctx; 7907 struct sysctl_oid *oid; 7908 struct sysctl_oid_list *children; 7909 7910 /* 7911 * dev.v?(cxgbe|cxl).X. 7912 */ 7913 oid = device_get_sysctl_tree(vi->dev); 7914 children = SYSCTL_CHILDREN(oid); 7915 7916 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 7917 vi->viid, "VI identifer"); 7918 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 7919 &vi->nrxq, 0, "# of rx queues"); 7920 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 7921 &vi->ntxq, 0, "# of tx queues"); 7922 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 7923 &vi->first_rxq, 0, "index of first rx queue"); 7924 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 7925 &vi->first_txq, 0, "index of first tx queue"); 7926 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 7927 vi->rss_base, "start of RSS indirection table"); 7928 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 7929 vi->rss_size, "size of RSS indirection table"); 7930 7931 if (IS_MAIN_VI(vi)) { 7932 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 7933 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7934 sysctl_noflowq, "IU", 7935 "Reserve queue 0 for non-flowid packets"); 7936 } 7937 7938 if (vi->adapter->flags & IS_VF) { 7939 MPASS(vi->flags & TX_USES_VM_WR); 7940 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD, 7941 NULL, 1, "use VM work requests for transmit"); 7942 } else { 7943 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr", 7944 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7945 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit"); 7946 } 7947 7948 #ifdef TCP_OFFLOAD 7949 if (vi->nofldrxq != 0) { 7950 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 7951 &vi->nofldrxq, 0, 7952 "# of rx queues for offloaded TCP connections"); 7953 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 7954 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 7955 "index of first TOE rx queue"); 7956 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 7957 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7958 sysctl_holdoff_tmr_idx_ofld, "I", 7959 "holdoff timer index for TOE queues"); 7960 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 7961 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7962 sysctl_holdoff_pktc_idx_ofld, "I", 7963 "holdoff packet counter index for TOE queues"); 7964 } 7965 #endif 7966 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7967 if (vi->nofldtxq != 0) { 7968 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 7969 &vi->nofldtxq, 0, 7970 "# of tx queues for TOE/ETHOFLD"); 7971 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 7972 CTLFLAG_RD, &vi->first_ofld_txq, 0, 7973 "index of first TOE/ETHOFLD tx queue"); 7974 } 7975 #endif 7976 #ifdef DEV_NETMAP 7977 if (vi->nnmrxq != 0) { 7978 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 7979 &vi->nnmrxq, 0, "# of netmap rx queues"); 7980 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 7981 &vi->nnmtxq, 0, "# of netmap tx queues"); 7982 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 7983 CTLFLAG_RD, &vi->first_nm_rxq, 0, 7984 "index of first netmap rx queue"); 7985 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 7986 CTLFLAG_RD, &vi->first_nm_txq, 0, 7987 "index of first netmap tx queue"); 7988 } 7989 #endif 7990 7991 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 7992 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7993 sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); 7994 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 7995 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7996 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); 7997 7998 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 7999 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 8000 sysctl_qsize_rxq, "I", "rx queue size"); 8001 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 8002 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 8003 sysctl_qsize_txq, "I", "tx queue size"); 8004 } 8005 8006 static void 8007 cxgbe_sysctls(struct port_info *pi) 8008 { 8009 struct sysctl_ctx_list *ctx = &pi->ctx; 8010 struct sysctl_oid *oid; 8011 struct sysctl_oid_list *children, *children2; 8012 struct adapter *sc = pi->adapter; 8013 int i; 8014 char name[16]; 8015 static char *tc_flags = {"\20\1USER"}; 8016 8017 /* 8018 * dev.cxgbe.X. 8019 */ 8020 oid = device_get_sysctl_tree(pi->dev); 8021 children = SYSCTL_CHILDREN(oid); 8022 8023 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", 8024 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 8025 sysctl_linkdnrc, "A", "reason why link is down"); 8026 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 8027 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 8028 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 8029 sysctl_btphy, "I", "PHY temperature (in Celsius)"); 8030 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 8031 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1, 8032 sysctl_btphy, "I", "PHY firmware version"); 8033 } 8034 8035 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 8036 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8037 sysctl_pause_settings, "A", 8038 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 8039 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec", 8040 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A", 8041 "FEC in use on the link"); 8042 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec", 8043 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8044 sysctl_requested_fec, "A", 8045 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)"); 8046 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec", 8047 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A", 8048 "FEC recommended by the cable/transceiver"); 8049 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 8050 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8051 sysctl_autoneg, "I", 8052 "autonegotiation (-1 = not supported)"); 8053 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec", 8054 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8055 sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config"); 8056 8057 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD, 8058 &pi->link_cfg.requested_caps, 0, "L1 config requested by driver"); 8059 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD, 8060 &pi->link_cfg.pcaps, 0, "port capabilities"); 8061 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD, 8062 &pi->link_cfg.acaps, 0, "advertised capabilities"); 8063 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD, 8064 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities"); 8065 8066 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 8067 port_top_speed(pi), "max speed (in Gbps)"); 8068 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 8069 pi->mps_bg_map, "MPS buffer group map"); 8070 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 8071 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 8072 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_chan", CTLFLAG_RD, NULL, 8073 pi->tx_chan, "TP tx c-channel"); 8074 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_chan", CTLFLAG_RD, NULL, 8075 pi->rx_chan, "TP rx c-channel"); 8076 8077 if (sc->flags & IS_VF) 8078 return; 8079 8080 /* 8081 * dev.(cxgbe|cxl).X.tc. 8082 */ 8083 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", 8084 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 8085 "Tx scheduler traffic classes (cl_rl)"); 8086 children2 = SYSCTL_CHILDREN(oid); 8087 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 8088 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 8089 "pktsize for per-flow cl-rl (0 means up to the driver )"); 8090 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 8091 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 8092 "burstsize for per-flow cl-rl (0 means up to the driver)"); 8093 for (i = 0; i < sc->params.nsched_cls; i++) { 8094 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 8095 8096 snprintf(name, sizeof(name), "%d", i); 8097 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 8098 SYSCTL_CHILDREN(oid), OID_AUTO, name, 8099 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class")); 8100 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state", 8101 CTLFLAG_RD, &tc->state, 0, "current state"); 8102 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 8103 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags, 8104 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags"); 8105 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 8106 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 8107 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 8108 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 8109 (pi->port_id << 16) | i, sysctl_tc_params, "A", 8110 "traffic class parameters"); 8111 } 8112 8113 /* 8114 * dev.cxgbe.X.stats. 8115 */ 8116 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 8117 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics"); 8118 children = SYSCTL_CHILDREN(oid); 8119 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 8120 &pi->tx_parse_error, 0, 8121 "# of tx packets with invalid length or # of segments"); 8122 8123 #define T4_REGSTAT(name, stat, desc) \ 8124 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \ 8125 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \ 8126 t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \ 8127 sysctl_handle_t4_reg64, "QU", desc) 8128 8129 /* We get these from port_stats and they may be stale by up to 1s */ 8130 #define T4_PORTSTAT(name, desc) \ 8131 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 8132 &pi->stats.name, desc) 8133 8134 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames"); 8135 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames"); 8136 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames"); 8137 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames"); 8138 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames"); 8139 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames"); 8140 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range"); 8141 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range"); 8142 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range"); 8143 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range"); 8144 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range"); 8145 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range"); 8146 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range"); 8147 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames"); 8148 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted"); 8149 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted"); 8150 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted"); 8151 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted"); 8152 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted"); 8153 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted"); 8154 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted"); 8155 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted"); 8156 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted"); 8157 8158 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames"); 8159 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames"); 8160 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames"); 8161 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames"); 8162 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames"); 8163 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU"); 8164 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames"); 8165 if (is_t6(sc)) { 8166 T4_PORTSTAT(rx_fcs_err, 8167 "# of frames received with bad FCS since last link up"); 8168 } else { 8169 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR, 8170 "# of frames received with bad FCS"); 8171 } 8172 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error"); 8173 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors"); 8174 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received"); 8175 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range"); 8176 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range"); 8177 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range"); 8178 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range"); 8179 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range"); 8180 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range"); 8181 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range"); 8182 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received"); 8183 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received"); 8184 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received"); 8185 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received"); 8186 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received"); 8187 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received"); 8188 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received"); 8189 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received"); 8190 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received"); 8191 8192 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows"); 8193 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows"); 8194 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows"); 8195 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows"); 8196 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets"); 8197 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets"); 8198 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets"); 8199 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets"); 8200 8201 #undef T4_REGSTAT 8202 #undef T4_PORTSTAT 8203 } 8204 8205 static int 8206 sysctl_int_array(SYSCTL_HANDLER_ARGS) 8207 { 8208 int rc, *i, space = 0; 8209 struct sbuf sb; 8210 8211 sbuf_new_for_sysctl(&sb, NULL, 64, req); 8212 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 8213 if (space) 8214 sbuf_printf(&sb, " "); 8215 sbuf_printf(&sb, "%d", *i); 8216 space = 1; 8217 } 8218 rc = sbuf_finish(&sb); 8219 sbuf_delete(&sb); 8220 return (rc); 8221 } 8222 8223 static int 8224 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 8225 { 8226 int rc; 8227 struct sbuf *sb; 8228 8229 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8230 if (sb == NULL) 8231 return (ENOMEM); 8232 8233 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 8234 rc = sbuf_finish(sb); 8235 sbuf_delete(sb); 8236 8237 return (rc); 8238 } 8239 8240 static int 8241 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 8242 { 8243 int rc; 8244 struct sbuf *sb; 8245 8246 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8247 if (sb == NULL) 8248 return (ENOMEM); 8249 8250 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 8251 rc = sbuf_finish(sb); 8252 sbuf_delete(sb); 8253 8254 return (rc); 8255 } 8256 8257 static int 8258 sysctl_btphy(SYSCTL_HANDLER_ARGS) 8259 { 8260 struct port_info *pi = arg1; 8261 int op = arg2; 8262 struct adapter *sc = pi->adapter; 8263 u_int v; 8264 int rc; 8265 8266 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 8267 if (rc) 8268 return (rc); 8269 if (hw_off_limits(sc)) 8270 rc = ENXIO; 8271 else { 8272 /* XXX: magic numbers */ 8273 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, 8274 op ? 0x20 : 0xc820, &v); 8275 } 8276 end_synchronized_op(sc, 0); 8277 if (rc) 8278 return (rc); 8279 if (op == 0) 8280 v /= 256; 8281 8282 rc = sysctl_handle_int(oidp, &v, 0, req); 8283 return (rc); 8284 } 8285 8286 static int 8287 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 8288 { 8289 struct vi_info *vi = arg1; 8290 int rc, val; 8291 8292 val = vi->rsrv_noflowq; 8293 rc = sysctl_handle_int(oidp, &val, 0, req); 8294 if (rc != 0 || req->newptr == NULL) 8295 return (rc); 8296 8297 if ((val >= 1) && (vi->ntxq > 1)) 8298 vi->rsrv_noflowq = 1; 8299 else 8300 vi->rsrv_noflowq = 0; 8301 8302 return (rc); 8303 } 8304 8305 static int 8306 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS) 8307 { 8308 struct vi_info *vi = arg1; 8309 struct adapter *sc = vi->adapter; 8310 int rc, val, i; 8311 8312 MPASS(!(sc->flags & IS_VF)); 8313 8314 val = vi->flags & TX_USES_VM_WR ? 1 : 0; 8315 rc = sysctl_handle_int(oidp, &val, 0, req); 8316 if (rc != 0 || req->newptr == NULL) 8317 return (rc); 8318 8319 if (val != 0 && val != 1) 8320 return (EINVAL); 8321 8322 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8323 "t4txvm"); 8324 if (rc) 8325 return (rc); 8326 if (hw_off_limits(sc)) 8327 rc = ENXIO; 8328 else if (if_getdrvflags(vi->ifp) & IFF_DRV_RUNNING) { 8329 /* 8330 * We don't want parse_pkt to run with one setting (VF or PF) 8331 * and then eth_tx to see a different setting but still use 8332 * stale information calculated by parse_pkt. 8333 */ 8334 rc = EBUSY; 8335 } else { 8336 struct port_info *pi = vi->pi; 8337 struct sge_txq *txq; 8338 uint32_t ctrl0; 8339 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr; 8340 8341 if (val) { 8342 vi->flags |= TX_USES_VM_WR; 8343 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO); 8344 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8345 V_TXPKT_INTF(pi->tx_chan)); 8346 if (!(sc->flags & IS_VF)) 8347 npkt--; 8348 } else { 8349 vi->flags &= ~TX_USES_VM_WR; 8350 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO); 8351 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8352 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 8353 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 8354 } 8355 for_each_txq(vi, i, txq) { 8356 txq->cpl_ctrl0 = ctrl0; 8357 txq->txp.max_npkt = npkt; 8358 } 8359 } 8360 end_synchronized_op(sc, LOCK_HELD); 8361 return (rc); 8362 } 8363 8364 static int 8365 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 8366 { 8367 struct vi_info *vi = arg1; 8368 struct adapter *sc = vi->adapter; 8369 int idx, rc, i; 8370 struct sge_rxq *rxq; 8371 uint8_t v; 8372 8373 idx = vi->tmr_idx; 8374 8375 rc = sysctl_handle_int(oidp, &idx, 0, req); 8376 if (rc != 0 || req->newptr == NULL) 8377 return (rc); 8378 8379 if (idx < 0 || idx >= SGE_NTIMERS) 8380 return (EINVAL); 8381 8382 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8383 "t4tmr"); 8384 if (rc) 8385 return (rc); 8386 8387 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 8388 for_each_rxq(vi, i, rxq) { 8389 #ifdef atomic_store_rel_8 8390 atomic_store_rel_8(&rxq->iq.intr_params, v); 8391 #else 8392 rxq->iq.intr_params = v; 8393 #endif 8394 } 8395 vi->tmr_idx = idx; 8396 8397 end_synchronized_op(sc, LOCK_HELD); 8398 return (0); 8399 } 8400 8401 static int 8402 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 8403 { 8404 struct vi_info *vi = arg1; 8405 struct adapter *sc = vi->adapter; 8406 int idx, rc; 8407 8408 idx = vi->pktc_idx; 8409 8410 rc = sysctl_handle_int(oidp, &idx, 0, req); 8411 if (rc != 0 || req->newptr == NULL) 8412 return (rc); 8413 8414 if (idx < -1 || idx >= SGE_NCOUNTERS) 8415 return (EINVAL); 8416 8417 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8418 "t4pktc"); 8419 if (rc) 8420 return (rc); 8421 8422 if (vi->flags & VI_INIT_DONE) 8423 rc = EBUSY; /* cannot be changed once the queues are created */ 8424 else 8425 vi->pktc_idx = idx; 8426 8427 end_synchronized_op(sc, LOCK_HELD); 8428 return (rc); 8429 } 8430 8431 static int 8432 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 8433 { 8434 struct vi_info *vi = arg1; 8435 struct adapter *sc = vi->adapter; 8436 int qsize, rc; 8437 8438 qsize = vi->qsize_rxq; 8439 8440 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8441 if (rc != 0 || req->newptr == NULL) 8442 return (rc); 8443 8444 if (qsize < 128 || (qsize & 7)) 8445 return (EINVAL); 8446 8447 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8448 "t4rxqs"); 8449 if (rc) 8450 return (rc); 8451 8452 if (vi->flags & VI_INIT_DONE) 8453 rc = EBUSY; /* cannot be changed once the queues are created */ 8454 else 8455 vi->qsize_rxq = qsize; 8456 8457 end_synchronized_op(sc, LOCK_HELD); 8458 return (rc); 8459 } 8460 8461 static int 8462 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 8463 { 8464 struct vi_info *vi = arg1; 8465 struct adapter *sc = vi->adapter; 8466 int qsize, rc; 8467 8468 qsize = vi->qsize_txq; 8469 8470 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8471 if (rc != 0 || req->newptr == NULL) 8472 return (rc); 8473 8474 if (qsize < 128 || qsize > 65536) 8475 return (EINVAL); 8476 8477 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8478 "t4txqs"); 8479 if (rc) 8480 return (rc); 8481 8482 if (vi->flags & VI_INIT_DONE) 8483 rc = EBUSY; /* cannot be changed once the queues are created */ 8484 else 8485 vi->qsize_txq = qsize; 8486 8487 end_synchronized_op(sc, LOCK_HELD); 8488 return (rc); 8489 } 8490 8491 static int 8492 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 8493 { 8494 struct port_info *pi = arg1; 8495 struct adapter *sc = pi->adapter; 8496 struct link_config *lc = &pi->link_cfg; 8497 int rc; 8498 8499 if (req->newptr == NULL) { 8500 struct sbuf *sb; 8501 static char *bits = "\20\1RX\2TX\3AUTO"; 8502 8503 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8504 if (sb == NULL) 8505 return (ENOMEM); 8506 8507 if (lc->link_ok) { 8508 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 8509 (lc->requested_fc & PAUSE_AUTONEG), bits); 8510 } else { 8511 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 8512 PAUSE_RX | PAUSE_AUTONEG), bits); 8513 } 8514 rc = sbuf_finish(sb); 8515 sbuf_delete(sb); 8516 } else { 8517 char s[2]; 8518 int n; 8519 8520 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 8521 PAUSE_AUTONEG)); 8522 s[1] = 0; 8523 8524 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8525 if (rc != 0) 8526 return(rc); 8527 8528 if (s[1] != 0) 8529 return (EINVAL); 8530 if (s[0] < '0' || s[0] > '9') 8531 return (EINVAL); /* not a number */ 8532 n = s[0] - '0'; 8533 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 8534 return (EINVAL); /* some other bit is set too */ 8535 8536 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8537 "t4PAUSE"); 8538 if (rc) 8539 return (rc); 8540 if (!hw_off_limits(sc)) { 8541 PORT_LOCK(pi); 8542 lc->requested_fc = n; 8543 fixup_link_config(pi); 8544 if (pi->up_vis > 0) 8545 rc = apply_link_config(pi); 8546 set_current_media(pi); 8547 PORT_UNLOCK(pi); 8548 } 8549 end_synchronized_op(sc, 0); 8550 } 8551 8552 return (rc); 8553 } 8554 8555 static int 8556 sysctl_link_fec(SYSCTL_HANDLER_ARGS) 8557 { 8558 struct port_info *pi = arg1; 8559 struct link_config *lc = &pi->link_cfg; 8560 int rc; 8561 struct sbuf *sb; 8562 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2"; 8563 8564 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8565 if (sb == NULL) 8566 return (ENOMEM); 8567 if (lc->link_ok) 8568 sbuf_printf(sb, "%b", lc->fec, bits); 8569 else 8570 sbuf_printf(sb, "no link"); 8571 rc = sbuf_finish(sb); 8572 sbuf_delete(sb); 8573 8574 return (rc); 8575 } 8576 8577 static int 8578 sysctl_requested_fec(SYSCTL_HANDLER_ARGS) 8579 { 8580 struct port_info *pi = arg1; 8581 struct adapter *sc = pi->adapter; 8582 struct link_config *lc = &pi->link_cfg; 8583 int rc; 8584 int8_t old; 8585 8586 if (req->newptr == NULL) { 8587 struct sbuf *sb; 8588 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2" 8589 "\5RSVD3\6auto\7module"; 8590 8591 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8592 if (sb == NULL) 8593 return (ENOMEM); 8594 8595 sbuf_printf(sb, "%b", lc->requested_fec, bits); 8596 rc = sbuf_finish(sb); 8597 sbuf_delete(sb); 8598 } else { 8599 char s[8]; 8600 int n; 8601 8602 snprintf(s, sizeof(s), "%d", 8603 lc->requested_fec == FEC_AUTO ? -1 : 8604 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE)); 8605 8606 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8607 if (rc != 0) 8608 return(rc); 8609 8610 n = strtol(&s[0], NULL, 0); 8611 if (n < 0 || n & FEC_AUTO) 8612 n = FEC_AUTO; 8613 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE)) 8614 return (EINVAL);/* some other bit is set too */ 8615 8616 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8617 "t4reqf"); 8618 if (rc) 8619 return (rc); 8620 PORT_LOCK(pi); 8621 old = lc->requested_fec; 8622 if (n == FEC_AUTO) 8623 lc->requested_fec = FEC_AUTO; 8624 else if (n == 0 || n == FEC_NONE) 8625 lc->requested_fec = FEC_NONE; 8626 else { 8627 if ((lc->pcaps | 8628 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) != 8629 lc->pcaps) { 8630 rc = ENOTSUP; 8631 goto done; 8632 } 8633 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC | 8634 FEC_MODULE); 8635 } 8636 if (!hw_off_limits(sc)) { 8637 fixup_link_config(pi); 8638 if (pi->up_vis > 0) { 8639 rc = apply_link_config(pi); 8640 if (rc != 0) { 8641 lc->requested_fec = old; 8642 if (rc == FW_EPROTO) 8643 rc = ENOTSUP; 8644 } 8645 } 8646 } 8647 done: 8648 PORT_UNLOCK(pi); 8649 end_synchronized_op(sc, 0); 8650 } 8651 8652 return (rc); 8653 } 8654 8655 static int 8656 sysctl_module_fec(SYSCTL_HANDLER_ARGS) 8657 { 8658 struct port_info *pi = arg1; 8659 struct adapter *sc = pi->adapter; 8660 struct link_config *lc = &pi->link_cfg; 8661 int rc; 8662 int8_t fec; 8663 struct sbuf *sb; 8664 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3"; 8665 8666 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8667 if (sb == NULL) 8668 return (ENOMEM); 8669 8670 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) { 8671 rc = EBUSY; 8672 goto done; 8673 } 8674 if (hw_off_limits(sc)) { 8675 rc = ENXIO; 8676 goto done; 8677 } 8678 PORT_LOCK(pi); 8679 if (pi->up_vis == 0) { 8680 /* 8681 * If all the interfaces are administratively down the firmware 8682 * does not report transceiver changes. Refresh port info here. 8683 * This is the only reason we have a synchronized op in this 8684 * function. Just PORT_LOCK would have been enough otherwise. 8685 */ 8686 t4_update_port_info(pi); 8687 } 8688 8689 fec = lc->fec_hint; 8690 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE || 8691 !fec_supported(lc->pcaps)) { 8692 PORT_UNLOCK(pi); 8693 sbuf_printf(sb, "n/a"); 8694 } else { 8695 if (fec == 0) 8696 fec = FEC_NONE; 8697 PORT_UNLOCK(pi); 8698 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits); 8699 } 8700 rc = sbuf_finish(sb); 8701 done: 8702 sbuf_delete(sb); 8703 end_synchronized_op(sc, 0); 8704 8705 return (rc); 8706 } 8707 8708 static int 8709 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 8710 { 8711 struct port_info *pi = arg1; 8712 struct adapter *sc = pi->adapter; 8713 struct link_config *lc = &pi->link_cfg; 8714 int rc, val; 8715 8716 if (lc->pcaps & FW_PORT_CAP32_ANEG) 8717 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 8718 else 8719 val = -1; 8720 rc = sysctl_handle_int(oidp, &val, 0, req); 8721 if (rc != 0 || req->newptr == NULL) 8722 return (rc); 8723 if (val == 0) 8724 val = AUTONEG_DISABLE; 8725 else if (val == 1) 8726 val = AUTONEG_ENABLE; 8727 else 8728 val = AUTONEG_AUTO; 8729 8730 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8731 "t4aneg"); 8732 if (rc) 8733 return (rc); 8734 PORT_LOCK(pi); 8735 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 8736 rc = ENOTSUP; 8737 goto done; 8738 } 8739 lc->requested_aneg = val; 8740 if (!hw_off_limits(sc)) { 8741 fixup_link_config(pi); 8742 if (pi->up_vis > 0) 8743 rc = apply_link_config(pi); 8744 set_current_media(pi); 8745 } 8746 done: 8747 PORT_UNLOCK(pi); 8748 end_synchronized_op(sc, 0); 8749 return (rc); 8750 } 8751 8752 static int 8753 sysctl_force_fec(SYSCTL_HANDLER_ARGS) 8754 { 8755 struct port_info *pi = arg1; 8756 struct adapter *sc = pi->adapter; 8757 struct link_config *lc = &pi->link_cfg; 8758 int rc, val; 8759 8760 val = lc->force_fec; 8761 MPASS(val >= -1 && val <= 1); 8762 rc = sysctl_handle_int(oidp, &val, 0, req); 8763 if (rc != 0 || req->newptr == NULL) 8764 return (rc); 8765 if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC)) 8766 return (ENOTSUP); 8767 if (val < -1 || val > 1) 8768 return (EINVAL); 8769 8770 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff"); 8771 if (rc) 8772 return (rc); 8773 PORT_LOCK(pi); 8774 lc->force_fec = val; 8775 if (!hw_off_limits(sc)) { 8776 fixup_link_config(pi); 8777 if (pi->up_vis > 0) 8778 rc = apply_link_config(pi); 8779 } 8780 PORT_UNLOCK(pi); 8781 end_synchronized_op(sc, 0); 8782 return (rc); 8783 } 8784 8785 static int 8786 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 8787 { 8788 struct adapter *sc = arg1; 8789 int rc, reg = arg2; 8790 uint64_t val; 8791 8792 mtx_lock(&sc->reg_lock); 8793 if (hw_off_limits(sc)) 8794 rc = ENXIO; 8795 else { 8796 rc = 0; 8797 val = t4_read_reg64(sc, reg); 8798 } 8799 mtx_unlock(&sc->reg_lock); 8800 if (rc == 0) 8801 rc = sysctl_handle_64(oidp, &val, 0, req); 8802 return (rc); 8803 } 8804 8805 static int 8806 sysctl_temperature(SYSCTL_HANDLER_ARGS) 8807 { 8808 struct adapter *sc = arg1; 8809 int rc, t; 8810 uint32_t param, val; 8811 8812 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 8813 if (rc) 8814 return (rc); 8815 if (hw_off_limits(sc)) 8816 rc = ENXIO; 8817 else { 8818 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8819 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8820 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 8821 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8822 } 8823 end_synchronized_op(sc, 0); 8824 if (rc) 8825 return (rc); 8826 8827 /* unknown is returned as 0 but we display -1 in that case */ 8828 t = val == 0 ? -1 : val; 8829 8830 rc = sysctl_handle_int(oidp, &t, 0, req); 8831 return (rc); 8832 } 8833 8834 static int 8835 sysctl_vdd(SYSCTL_HANDLER_ARGS) 8836 { 8837 struct adapter *sc = arg1; 8838 int rc; 8839 uint32_t param, val; 8840 8841 if (sc->params.core_vdd == 0) { 8842 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8843 "t4vdd"); 8844 if (rc) 8845 return (rc); 8846 if (hw_off_limits(sc)) 8847 rc = ENXIO; 8848 else { 8849 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8850 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8851 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 8852 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, 8853 ¶m, &val); 8854 } 8855 end_synchronized_op(sc, 0); 8856 if (rc) 8857 return (rc); 8858 sc->params.core_vdd = val; 8859 } 8860 8861 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req)); 8862 } 8863 8864 static int 8865 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS) 8866 { 8867 struct adapter *sc = arg1; 8868 int rc, v; 8869 uint32_t param, val; 8870 8871 v = sc->sensor_resets; 8872 rc = sysctl_handle_int(oidp, &v, 0, req); 8873 if (rc != 0 || req->newptr == NULL || v <= 0) 8874 return (rc); 8875 8876 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) || 8877 chip_id(sc) < CHELSIO_T5) 8878 return (ENOTSUP); 8879 8880 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst"); 8881 if (rc) 8882 return (rc); 8883 if (hw_off_limits(sc)) 8884 rc = ENXIO; 8885 else { 8886 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8887 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8888 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR)); 8889 val = 1; 8890 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8891 } 8892 end_synchronized_op(sc, 0); 8893 if (rc == 0) 8894 sc->sensor_resets++; 8895 return (rc); 8896 } 8897 8898 static int 8899 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 8900 { 8901 struct adapter *sc = arg1; 8902 struct sbuf *sb; 8903 int rc; 8904 uint32_t param, val; 8905 8906 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 8907 if (rc) 8908 return (rc); 8909 if (hw_off_limits(sc)) 8910 rc = ENXIO; 8911 else { 8912 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8913 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 8914 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8915 } 8916 end_synchronized_op(sc, 0); 8917 if (rc) 8918 return (rc); 8919 8920 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8921 if (sb == NULL) 8922 return (ENOMEM); 8923 8924 if (val == 0xffffffff) { 8925 /* Only debug and custom firmwares report load averages. */ 8926 sbuf_printf(sb, "not available"); 8927 } else { 8928 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 8929 (val >> 16) & 0xff); 8930 } 8931 rc = sbuf_finish(sb); 8932 sbuf_delete(sb); 8933 8934 return (rc); 8935 } 8936 8937 static int 8938 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 8939 { 8940 struct adapter *sc = arg1; 8941 struct sbuf *sb; 8942 int rc, i; 8943 uint16_t incr[NMTUS][NCCTRL_WIN]; 8944 static const char *dec_fac[] = { 8945 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 8946 "0.9375" 8947 }; 8948 8949 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8950 if (sb == NULL) 8951 return (ENOMEM); 8952 8953 rc = 0; 8954 mtx_lock(&sc->reg_lock); 8955 if (hw_off_limits(sc)) 8956 rc = ENXIO; 8957 else 8958 t4_read_cong_tbl(sc, incr); 8959 mtx_unlock(&sc->reg_lock); 8960 if (rc) 8961 goto done; 8962 8963 for (i = 0; i < NCCTRL_WIN; ++i) { 8964 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 8965 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 8966 incr[5][i], incr[6][i], incr[7][i]); 8967 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 8968 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 8969 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 8970 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 8971 } 8972 8973 rc = sbuf_finish(sb); 8974 done: 8975 sbuf_delete(sb); 8976 return (rc); 8977 } 8978 8979 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 8980 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 8981 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 8982 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 8983 }; 8984 8985 static int 8986 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 8987 { 8988 struct adapter *sc = arg1; 8989 struct sbuf *sb; 8990 int rc, i, n, qid = arg2; 8991 uint32_t *buf, *p; 8992 char *qtype; 8993 u_int cim_num_obq = sc->chip_params->cim_num_obq; 8994 8995 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 8996 ("%s: bad qid %d\n", __func__, qid)); 8997 8998 if (qid < CIM_NUM_IBQ) { 8999 /* inbound queue */ 9000 qtype = "IBQ"; 9001 n = 4 * CIM_IBQ_SIZE; 9002 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 9003 mtx_lock(&sc->reg_lock); 9004 if (hw_off_limits(sc)) 9005 rc = -ENXIO; 9006 else 9007 rc = t4_read_cim_ibq(sc, qid, buf, n); 9008 mtx_unlock(&sc->reg_lock); 9009 } else { 9010 /* outbound queue */ 9011 qtype = "OBQ"; 9012 qid -= CIM_NUM_IBQ; 9013 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 9014 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 9015 mtx_lock(&sc->reg_lock); 9016 if (hw_off_limits(sc)) 9017 rc = -ENXIO; 9018 else 9019 rc = t4_read_cim_obq(sc, qid, buf, n); 9020 mtx_unlock(&sc->reg_lock); 9021 } 9022 9023 if (rc < 0) { 9024 rc = -rc; 9025 goto done; 9026 } 9027 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 9028 9029 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9030 if (sb == NULL) { 9031 rc = ENOMEM; 9032 goto done; 9033 } 9034 9035 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 9036 for (i = 0, p = buf; i < n; i += 16, p += 4) 9037 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 9038 p[2], p[3]); 9039 9040 rc = sbuf_finish(sb); 9041 sbuf_delete(sb); 9042 done: 9043 free(buf, M_CXGBE); 9044 return (rc); 9045 } 9046 9047 static void 9048 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9049 { 9050 uint32_t *p; 9051 9052 sbuf_printf(sb, "Status Data PC%s", 9053 cfg & F_UPDBGLACAPTPCONLY ? "" : 9054 " LS0Stat LS0Addr LS0Data"); 9055 9056 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 9057 if (cfg & F_UPDBGLACAPTPCONLY) { 9058 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 9059 p[6], p[7]); 9060 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 9061 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 9062 p[4] & 0xff, p[5] >> 8); 9063 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 9064 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9065 p[1] & 0xf, p[2] >> 4); 9066 } else { 9067 sbuf_printf(sb, 9068 "\n %02x %x%07x %x%07x %08x %08x " 9069 "%08x%08x%08x%08x", 9070 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9071 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 9072 p[6], p[7]); 9073 } 9074 } 9075 } 9076 9077 static void 9078 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9079 { 9080 uint32_t *p; 9081 9082 sbuf_printf(sb, "Status Inst Data PC%s", 9083 cfg & F_UPDBGLACAPTPCONLY ? "" : 9084 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 9085 9086 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 9087 if (cfg & F_UPDBGLACAPTPCONLY) { 9088 sbuf_printf(sb, "\n %02x %08x %08x %08x", 9089 p[3] & 0xff, p[2], p[1], p[0]); 9090 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 9091 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 9092 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 9093 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 9094 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 9095 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 9096 p[6] >> 16); 9097 } else { 9098 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 9099 "%08x %08x %08x %08x %08x %08x", 9100 (p[9] >> 16) & 0xff, 9101 p[9] & 0xffff, p[8] >> 16, 9102 p[8] & 0xffff, p[7] >> 16, 9103 p[7] & 0xffff, p[6] >> 16, 9104 p[2], p[1], p[0], p[5], p[4], p[3]); 9105 } 9106 } 9107 } 9108 9109 static int 9110 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 9111 { 9112 uint32_t cfg, *buf; 9113 int rc; 9114 9115 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9116 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 9117 M_ZERO | flags); 9118 if (buf == NULL) 9119 return (ENOMEM); 9120 9121 mtx_lock(&sc->reg_lock); 9122 if (hw_off_limits(sc)) 9123 rc = ENXIO; 9124 else { 9125 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9126 if (rc == 0) 9127 rc = -t4_cim_read_la(sc, buf, NULL); 9128 } 9129 mtx_unlock(&sc->reg_lock); 9130 if (rc == 0) { 9131 if (chip_id(sc) < CHELSIO_T6) 9132 sbuf_cim_la4(sc, sb, buf, cfg); 9133 else 9134 sbuf_cim_la6(sc, sb, buf, cfg); 9135 } 9136 free(buf, M_CXGBE); 9137 return (rc); 9138 } 9139 9140 static int 9141 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 9142 { 9143 struct adapter *sc = arg1; 9144 struct sbuf *sb; 9145 int rc; 9146 9147 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9148 if (sb == NULL) 9149 return (ENOMEM); 9150 9151 rc = sbuf_cim_la(sc, sb, M_WAITOK); 9152 if (rc == 0) 9153 rc = sbuf_finish(sb); 9154 sbuf_delete(sb); 9155 return (rc); 9156 } 9157 9158 static void 9159 dump_cim_regs(struct adapter *sc) 9160 { 9161 log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n", 9162 device_get_nameunit(sc->dev), 9163 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9164 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9165 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2), 9166 t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN), 9167 t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA)); 9168 log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n", 9169 device_get_nameunit(sc->dev), 9170 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9171 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9172 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800), 9173 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800), 9174 t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN)); 9175 } 9176 9177 static void 9178 dump_cimla(struct adapter *sc) 9179 { 9180 struct sbuf sb; 9181 int rc; 9182 9183 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9184 log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n", 9185 device_get_nameunit(sc->dev)); 9186 return; 9187 } 9188 rc = sbuf_cim_la(sc, &sb, M_WAITOK); 9189 if (rc == 0) { 9190 rc = sbuf_finish(&sb); 9191 if (rc == 0) { 9192 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n", 9193 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9194 } 9195 } 9196 sbuf_delete(&sb); 9197 } 9198 9199 void 9200 t4_os_cim_err(struct adapter *sc) 9201 { 9202 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 9203 } 9204 9205 static int 9206 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 9207 { 9208 struct adapter *sc = arg1; 9209 u_int i; 9210 struct sbuf *sb; 9211 uint32_t *buf, *p; 9212 int rc; 9213 9214 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9215 if (sb == NULL) 9216 return (ENOMEM); 9217 9218 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 9219 M_ZERO | M_WAITOK); 9220 9221 rc = 0; 9222 mtx_lock(&sc->reg_lock); 9223 if (hw_off_limits(sc)) 9224 rc = ENXIO; 9225 else 9226 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 9227 mtx_unlock(&sc->reg_lock); 9228 if (rc) 9229 goto done; 9230 9231 p = buf; 9232 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9233 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 9234 p[1], p[0]); 9235 } 9236 9237 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 9238 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9239 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 9240 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 9241 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 9242 (p[1] >> 2) | ((p[2] & 3) << 30), 9243 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 9244 p[0] & 1); 9245 } 9246 rc = sbuf_finish(sb); 9247 done: 9248 sbuf_delete(sb); 9249 free(buf, M_CXGBE); 9250 return (rc); 9251 } 9252 9253 static int 9254 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 9255 { 9256 struct adapter *sc = arg1; 9257 u_int i; 9258 struct sbuf *sb; 9259 uint32_t *buf, *p; 9260 int rc; 9261 9262 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9263 if (sb == NULL) 9264 return (ENOMEM); 9265 9266 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 9267 M_ZERO | M_WAITOK); 9268 9269 rc = 0; 9270 mtx_lock(&sc->reg_lock); 9271 if (hw_off_limits(sc)) 9272 rc = ENXIO; 9273 else 9274 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 9275 mtx_unlock(&sc->reg_lock); 9276 if (rc) 9277 goto done; 9278 9279 p = buf; 9280 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 9281 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9282 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 9283 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 9284 p[4], p[3], p[2], p[1], p[0]); 9285 } 9286 9287 sbuf_printf(sb, "\n\nCntl ID Data"); 9288 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9289 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 9290 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 9291 } 9292 9293 rc = sbuf_finish(sb); 9294 done: 9295 sbuf_delete(sb); 9296 free(buf, M_CXGBE); 9297 return (rc); 9298 } 9299 9300 static int 9301 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 9302 { 9303 struct adapter *sc = arg1; 9304 struct sbuf *sb; 9305 int rc, i; 9306 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9307 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9308 uint16_t thres[CIM_NUM_IBQ]; 9309 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 9310 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 9311 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 9312 9313 cim_num_obq = sc->chip_params->cim_num_obq; 9314 if (is_t4(sc)) { 9315 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 9316 obq_rdaddr = A_UP_OBQ_0_REALADDR; 9317 } else { 9318 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 9319 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 9320 } 9321 nq = CIM_NUM_IBQ + cim_num_obq; 9322 9323 mtx_lock(&sc->reg_lock); 9324 if (hw_off_limits(sc)) 9325 rc = ENXIO; 9326 else { 9327 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 9328 if (rc == 0) { 9329 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, 9330 obq_wr); 9331 if (rc == 0) 9332 t4_read_cimq_cfg(sc, base, size, thres); 9333 } 9334 } 9335 mtx_unlock(&sc->reg_lock); 9336 if (rc) 9337 return (rc); 9338 9339 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9340 if (sb == NULL) 9341 return (ENOMEM); 9342 9343 sbuf_printf(sb, 9344 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 9345 9346 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 9347 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 9348 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 9349 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9350 G_QUEREMFLITS(p[2]) * 16); 9351 for ( ; i < nq; i++, p += 4, wr += 2) 9352 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 9353 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 9354 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9355 G_QUEREMFLITS(p[2]) * 16); 9356 9357 rc = sbuf_finish(sb); 9358 sbuf_delete(sb); 9359 9360 return (rc); 9361 } 9362 9363 static int 9364 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 9365 { 9366 struct adapter *sc = arg1; 9367 struct sbuf *sb; 9368 int rc; 9369 struct tp_cpl_stats stats; 9370 9371 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9372 if (sb == NULL) 9373 return (ENOMEM); 9374 9375 rc = 0; 9376 mtx_lock(&sc->reg_lock); 9377 if (hw_off_limits(sc)) 9378 rc = ENXIO; 9379 else 9380 t4_tp_get_cpl_stats(sc, &stats, 0); 9381 mtx_unlock(&sc->reg_lock); 9382 if (rc) 9383 goto done; 9384 9385 if (sc->chip_params->nchan > 2) { 9386 sbuf_printf(sb, " channel 0 channel 1" 9387 " channel 2 channel 3"); 9388 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 9389 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 9390 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 9391 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 9392 } else { 9393 sbuf_printf(sb, " channel 0 channel 1"); 9394 sbuf_printf(sb, "\nCPL requests: %10u %10u", 9395 stats.req[0], stats.req[1]); 9396 sbuf_printf(sb, "\nCPL responses: %10u %10u", 9397 stats.rsp[0], stats.rsp[1]); 9398 } 9399 9400 rc = sbuf_finish(sb); 9401 done: 9402 sbuf_delete(sb); 9403 return (rc); 9404 } 9405 9406 static int 9407 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 9408 { 9409 struct adapter *sc = arg1; 9410 struct sbuf *sb; 9411 int rc; 9412 struct tp_usm_stats stats; 9413 9414 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9415 if (sb == NULL) 9416 return (ENOMEM); 9417 9418 rc = 0; 9419 mtx_lock(&sc->reg_lock); 9420 if (hw_off_limits(sc)) 9421 rc = ENXIO; 9422 else 9423 t4_get_usm_stats(sc, &stats, 1); 9424 mtx_unlock(&sc->reg_lock); 9425 if (rc == 0) { 9426 sbuf_printf(sb, "Frames: %u\n", stats.frames); 9427 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 9428 sbuf_printf(sb, "Drops: %u", stats.drops); 9429 rc = sbuf_finish(sb); 9430 } 9431 sbuf_delete(sb); 9432 9433 return (rc); 9434 } 9435 9436 static int 9437 sysctl_tid_stats(SYSCTL_HANDLER_ARGS) 9438 { 9439 struct adapter *sc = arg1; 9440 struct sbuf *sb; 9441 int rc; 9442 struct tp_tid_stats stats; 9443 9444 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9445 if (sb == NULL) 9446 return (ENOMEM); 9447 9448 rc = 0; 9449 mtx_lock(&sc->reg_lock); 9450 if (hw_off_limits(sc)) 9451 rc = ENXIO; 9452 else 9453 t4_tp_get_tid_stats(sc, &stats, 1); 9454 mtx_unlock(&sc->reg_lock); 9455 if (rc == 0) { 9456 sbuf_printf(sb, "Delete: %u\n", stats.del); 9457 sbuf_printf(sb, "Invalidate: %u\n", stats.inv); 9458 sbuf_printf(sb, "Active: %u\n", stats.act); 9459 sbuf_printf(sb, "Passive: %u", stats.pas); 9460 rc = sbuf_finish(sb); 9461 } 9462 sbuf_delete(sb); 9463 9464 return (rc); 9465 } 9466 9467 static const char * const devlog_level_strings[] = { 9468 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 9469 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 9470 [FW_DEVLOG_LEVEL_ERR] = "ERR", 9471 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 9472 [FW_DEVLOG_LEVEL_INFO] = "INFO", 9473 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 9474 }; 9475 9476 static const char * const devlog_facility_strings[] = { 9477 [FW_DEVLOG_FACILITY_CORE] = "CORE", 9478 [FW_DEVLOG_FACILITY_CF] = "CF", 9479 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 9480 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 9481 [FW_DEVLOG_FACILITY_RES] = "RES", 9482 [FW_DEVLOG_FACILITY_HW] = "HW", 9483 [FW_DEVLOG_FACILITY_FLR] = "FLR", 9484 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 9485 [FW_DEVLOG_FACILITY_PHY] = "PHY", 9486 [FW_DEVLOG_FACILITY_MAC] = "MAC", 9487 [FW_DEVLOG_FACILITY_PORT] = "PORT", 9488 [FW_DEVLOG_FACILITY_VI] = "VI", 9489 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 9490 [FW_DEVLOG_FACILITY_ACL] = "ACL", 9491 [FW_DEVLOG_FACILITY_TM] = "TM", 9492 [FW_DEVLOG_FACILITY_QFC] = "QFC", 9493 [FW_DEVLOG_FACILITY_DCB] = "DCB", 9494 [FW_DEVLOG_FACILITY_ETH] = "ETH", 9495 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 9496 [FW_DEVLOG_FACILITY_RI] = "RI", 9497 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 9498 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 9499 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 9500 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 9501 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 9502 }; 9503 9504 static int 9505 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 9506 { 9507 int i, j, rc, nentries, first = 0; 9508 struct devlog_params *dparams = &sc->params.devlog; 9509 struct fw_devlog_e *buf, *e; 9510 uint64_t ftstamp = UINT64_MAX; 9511 9512 if (dparams->addr == 0) 9513 return (ENXIO); 9514 9515 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9516 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 9517 if (buf == NULL) 9518 return (ENOMEM); 9519 9520 mtx_lock(&sc->reg_lock); 9521 if (hw_off_limits(sc)) 9522 rc = ENXIO; 9523 else 9524 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, 9525 dparams->size); 9526 mtx_unlock(&sc->reg_lock); 9527 if (rc != 0) 9528 goto done; 9529 9530 nentries = dparams->size / sizeof(struct fw_devlog_e); 9531 for (i = 0; i < nentries; i++) { 9532 e = &buf[i]; 9533 9534 if (e->timestamp == 0) 9535 break; /* end */ 9536 9537 e->timestamp = be64toh(e->timestamp); 9538 e->seqno = be32toh(e->seqno); 9539 for (j = 0; j < 8; j++) 9540 e->params[j] = be32toh(e->params[j]); 9541 9542 if (e->timestamp < ftstamp) { 9543 ftstamp = e->timestamp; 9544 first = i; 9545 } 9546 } 9547 9548 if (buf[first].timestamp == 0) 9549 goto done; /* nothing in the log */ 9550 9551 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 9552 "Seq#", "Tstamp", "Level", "Facility", "Message"); 9553 9554 i = first; 9555 do { 9556 e = &buf[i]; 9557 if (e->timestamp == 0) 9558 break; /* end */ 9559 9560 sbuf_printf(sb, "%10d %15ju %8s %8s ", 9561 e->seqno, e->timestamp, 9562 (e->level < nitems(devlog_level_strings) ? 9563 devlog_level_strings[e->level] : "UNKNOWN"), 9564 (e->facility < nitems(devlog_facility_strings) ? 9565 devlog_facility_strings[e->facility] : "UNKNOWN")); 9566 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 9567 e->params[2], e->params[3], e->params[4], 9568 e->params[5], e->params[6], e->params[7]); 9569 9570 if (++i == nentries) 9571 i = 0; 9572 } while (i != first); 9573 done: 9574 free(buf, M_CXGBE); 9575 return (rc); 9576 } 9577 9578 static int 9579 sysctl_devlog(SYSCTL_HANDLER_ARGS) 9580 { 9581 struct adapter *sc = arg1; 9582 int rc; 9583 struct sbuf *sb; 9584 9585 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9586 if (sb == NULL) 9587 return (ENOMEM); 9588 9589 rc = sbuf_devlog(sc, sb, M_WAITOK); 9590 if (rc == 0) 9591 rc = sbuf_finish(sb); 9592 sbuf_delete(sb); 9593 return (rc); 9594 } 9595 9596 static void 9597 dump_devlog(struct adapter *sc) 9598 { 9599 int rc; 9600 struct sbuf sb; 9601 9602 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9603 log(LOG_DEBUG, "%s: failed to generate devlog dump.\n", 9604 device_get_nameunit(sc->dev)); 9605 return; 9606 } 9607 rc = sbuf_devlog(sc, &sb, M_WAITOK); 9608 if (rc == 0) { 9609 rc = sbuf_finish(&sb); 9610 if (rc == 0) { 9611 log(LOG_DEBUG, "%s: device log follows.\n%s", 9612 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9613 } 9614 } 9615 sbuf_delete(&sb); 9616 } 9617 9618 static int 9619 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 9620 { 9621 struct adapter *sc = arg1; 9622 struct sbuf *sb; 9623 int rc; 9624 struct tp_fcoe_stats stats[MAX_NCHAN]; 9625 int i, nchan = sc->chip_params->nchan; 9626 9627 rc = 0; 9628 mtx_lock(&sc->reg_lock); 9629 if (hw_off_limits(sc)) 9630 rc = ENXIO; 9631 else { 9632 for (i = 0; i < nchan; i++) 9633 t4_get_fcoe_stats(sc, i, &stats[i], 1); 9634 } 9635 mtx_unlock(&sc->reg_lock); 9636 if (rc != 0) 9637 return (rc); 9638 9639 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9640 if (sb == NULL) 9641 return (ENOMEM); 9642 9643 if (nchan > 2) { 9644 sbuf_printf(sb, " channel 0 channel 1" 9645 " channel 2 channel 3"); 9646 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 9647 stats[0].octets_ddp, stats[1].octets_ddp, 9648 stats[2].octets_ddp, stats[3].octets_ddp); 9649 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 9650 stats[0].frames_ddp, stats[1].frames_ddp, 9651 stats[2].frames_ddp, stats[3].frames_ddp); 9652 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 9653 stats[0].frames_drop, stats[1].frames_drop, 9654 stats[2].frames_drop, stats[3].frames_drop); 9655 } else { 9656 sbuf_printf(sb, " channel 0 channel 1"); 9657 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 9658 stats[0].octets_ddp, stats[1].octets_ddp); 9659 sbuf_printf(sb, "\nframesDDP: %16u %16u", 9660 stats[0].frames_ddp, stats[1].frames_ddp); 9661 sbuf_printf(sb, "\nframesDrop: %16u %16u", 9662 stats[0].frames_drop, stats[1].frames_drop); 9663 } 9664 9665 rc = sbuf_finish(sb); 9666 sbuf_delete(sb); 9667 9668 return (rc); 9669 } 9670 9671 static int 9672 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 9673 { 9674 struct adapter *sc = arg1; 9675 struct sbuf *sb; 9676 int rc, i; 9677 unsigned int map, kbps, ipg, mode; 9678 unsigned int pace_tab[NTX_SCHED]; 9679 9680 sb = sbuf_new_for_sysctl(NULL, NULL, 512, req); 9681 if (sb == NULL) 9682 return (ENOMEM); 9683 9684 mtx_lock(&sc->reg_lock); 9685 if (hw_off_limits(sc)) { 9686 mtx_unlock(&sc->reg_lock); 9687 rc = ENXIO; 9688 goto done; 9689 } 9690 9691 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 9692 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 9693 t4_read_pace_tbl(sc, pace_tab); 9694 mtx_unlock(&sc->reg_lock); 9695 9696 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 9697 "Class IPG (0.1 ns) Flow IPG (us)"); 9698 9699 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 9700 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 9701 sbuf_printf(sb, "\n %u %-5s %u ", i, 9702 (mode & (1 << i)) ? "flow" : "class", map & 3); 9703 if (kbps) 9704 sbuf_printf(sb, "%9u ", kbps); 9705 else 9706 sbuf_printf(sb, " disabled "); 9707 9708 if (ipg) 9709 sbuf_printf(sb, "%13u ", ipg); 9710 else 9711 sbuf_printf(sb, " disabled "); 9712 9713 if (pace_tab[i]) 9714 sbuf_printf(sb, "%10u", pace_tab[i]); 9715 else 9716 sbuf_printf(sb, " disabled"); 9717 } 9718 rc = sbuf_finish(sb); 9719 done: 9720 sbuf_delete(sb); 9721 return (rc); 9722 } 9723 9724 static int 9725 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 9726 { 9727 struct adapter *sc = arg1; 9728 struct sbuf *sb; 9729 int rc, i, j; 9730 uint64_t *p0, *p1; 9731 struct lb_port_stats s[2]; 9732 static const char *stat_name[] = { 9733 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 9734 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 9735 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 9736 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 9737 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 9738 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 9739 "BG2FramesTrunc:", "BG3FramesTrunc:" 9740 }; 9741 9742 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9743 if (sb == NULL) 9744 return (ENOMEM); 9745 9746 memset(s, 0, sizeof(s)); 9747 9748 rc = 0; 9749 for (i = 0; i < sc->chip_params->nchan; i += 2) { 9750 mtx_lock(&sc->reg_lock); 9751 if (hw_off_limits(sc)) 9752 rc = ENXIO; 9753 else { 9754 t4_get_lb_stats(sc, i, &s[0]); 9755 t4_get_lb_stats(sc, i + 1, &s[1]); 9756 } 9757 mtx_unlock(&sc->reg_lock); 9758 if (rc != 0) 9759 break; 9760 9761 p0 = &s[0].octets; 9762 p1 = &s[1].octets; 9763 sbuf_printf(sb, "%s Loopback %u" 9764 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 9765 9766 for (j = 0; j < nitems(stat_name); j++) 9767 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 9768 *p0++, *p1++); 9769 } 9770 9771 if (rc == 0) 9772 rc = sbuf_finish(sb); 9773 sbuf_delete(sb); 9774 9775 return (rc); 9776 } 9777 9778 static int 9779 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 9780 { 9781 int rc = 0; 9782 struct port_info *pi = arg1; 9783 struct link_config *lc = &pi->link_cfg; 9784 struct sbuf *sb; 9785 9786 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 9787 if (sb == NULL) 9788 return (ENOMEM); 9789 9790 if (lc->link_ok || lc->link_down_rc == 255) 9791 sbuf_printf(sb, "n/a"); 9792 else 9793 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 9794 9795 rc = sbuf_finish(sb); 9796 sbuf_delete(sb); 9797 9798 return (rc); 9799 } 9800 9801 struct mem_desc { 9802 u_int base; 9803 u_int limit; 9804 u_int idx; 9805 }; 9806 9807 static int 9808 mem_desc_cmp(const void *a, const void *b) 9809 { 9810 const u_int v1 = ((const struct mem_desc *)a)->base; 9811 const u_int v2 = ((const struct mem_desc *)b)->base; 9812 9813 if (v1 < v2) 9814 return (-1); 9815 else if (v1 > v2) 9816 return (1); 9817 9818 return (0); 9819 } 9820 9821 static void 9822 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 9823 unsigned int to) 9824 { 9825 unsigned int size; 9826 9827 if (from == to) 9828 return; 9829 9830 size = to - from + 1; 9831 if (size == 0) 9832 return; 9833 9834 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 9835 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 9836 } 9837 9838 static int 9839 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 9840 { 9841 struct adapter *sc = arg1; 9842 struct sbuf *sb; 9843 int rc, i, n; 9844 uint32_t lo, hi, used, free, alloc; 9845 static const char *memory[] = { 9846 "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:" 9847 }; 9848 static const char *region[] = { 9849 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 9850 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 9851 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 9852 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 9853 "RQUDP region:", "PBL region:", "TXPBL region:", 9854 "TLSKey region:", "DBVFIFO region:", "ULPRX state:", 9855 "ULPTX state:", "On-chip queues:", 9856 }; 9857 struct mem_desc avail[4]; 9858 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 9859 struct mem_desc *md = mem; 9860 9861 rc = sysctl_wire_old_buffer(req, 0); 9862 if (rc != 0) 9863 return (rc); 9864 9865 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9866 if (sb == NULL) 9867 return (ENOMEM); 9868 9869 for (i = 0; i < nitems(mem); i++) { 9870 mem[i].limit = 0; 9871 mem[i].idx = i; 9872 } 9873 9874 mtx_lock(&sc->reg_lock); 9875 if (hw_off_limits(sc)) { 9876 rc = ENXIO; 9877 goto done; 9878 } 9879 9880 /* Find and sort the populated memory ranges */ 9881 i = 0; 9882 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 9883 if (lo & F_EDRAM0_ENABLE) { 9884 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 9885 avail[i].base = G_EDRAM0_BASE(hi) << 20; 9886 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 9887 avail[i].idx = 0; 9888 i++; 9889 } 9890 if (lo & F_EDRAM1_ENABLE) { 9891 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 9892 avail[i].base = G_EDRAM1_BASE(hi) << 20; 9893 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 9894 avail[i].idx = 1; 9895 i++; 9896 } 9897 if (lo & F_EXT_MEM_ENABLE) { 9898 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 9899 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 9900 avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20); 9901 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 9902 i++; 9903 } 9904 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 9905 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9906 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9907 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9908 avail[i].idx = 4; 9909 i++; 9910 } 9911 if (is_t6(sc) && lo & F_HMA_MUX) { 9912 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9913 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9914 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9915 avail[i].idx = 5; 9916 i++; 9917 } 9918 MPASS(i <= nitems(avail)); 9919 if (!i) /* no memory available */ 9920 goto done; 9921 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 9922 9923 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 9924 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 9925 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 9926 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9927 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 9928 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 9929 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 9930 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 9931 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 9932 9933 /* the next few have explicit upper bounds */ 9934 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 9935 md->limit = md->base - 1 + 9936 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 9937 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 9938 md++; 9939 9940 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 9941 md->limit = md->base - 1 + 9942 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 9943 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 9944 md++; 9945 9946 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 9947 if (chip_id(sc) <= CHELSIO_T5) 9948 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 9949 else 9950 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 9951 md->limit = 0; 9952 } else { 9953 md->base = 0; 9954 md->idx = nitems(region); /* hide it */ 9955 } 9956 md++; 9957 9958 #define ulp_region(reg) \ 9959 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 9960 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 9961 9962 ulp_region(RX_ISCSI); 9963 ulp_region(RX_TDDP); 9964 ulp_region(TX_TPT); 9965 ulp_region(RX_STAG); 9966 ulp_region(RX_RQ); 9967 ulp_region(RX_RQUDP); 9968 ulp_region(RX_PBL); 9969 ulp_region(TX_PBL); 9970 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 9971 ulp_region(RX_TLS_KEY); 9972 } 9973 #undef ulp_region 9974 9975 md->base = 0; 9976 if (is_t4(sc)) 9977 md->idx = nitems(region); 9978 else { 9979 uint32_t size = 0; 9980 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 9981 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 9982 9983 if (is_t5(sc)) { 9984 if (sge_ctrl & F_VFIFO_ENABLE) 9985 size = fifo_size << 2; 9986 } else 9987 size = G_T6_DBVFIFO_SIZE(fifo_size) << 6; 9988 9989 if (size) { 9990 md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR); 9991 md->limit = md->base + size - 1; 9992 } else 9993 md->idx = nitems(region); 9994 } 9995 md++; 9996 9997 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 9998 md->limit = 0; 9999 md++; 10000 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 10001 md->limit = 0; 10002 md++; 10003 10004 md->base = sc->vres.ocq.start; 10005 if (sc->vres.ocq.size) 10006 md->limit = md->base + sc->vres.ocq.size - 1; 10007 else 10008 md->idx = nitems(region); /* hide it */ 10009 md++; 10010 10011 /* add any address-space holes, there can be up to 3 */ 10012 for (n = 0; n < i - 1; n++) 10013 if (avail[n].limit < avail[n + 1].base) 10014 (md++)->base = avail[n].limit; 10015 if (avail[n].limit) 10016 (md++)->base = avail[n].limit; 10017 10018 n = md - mem; 10019 MPASS(n <= nitems(mem)); 10020 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 10021 10022 for (lo = 0; lo < i; lo++) 10023 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 10024 avail[lo].limit - 1); 10025 10026 sbuf_printf(sb, "\n"); 10027 for (i = 0; i < n; i++) { 10028 if (mem[i].idx >= nitems(region)) 10029 continue; /* skip holes */ 10030 if (!mem[i].limit) 10031 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 10032 mem_region_show(sb, region[mem[i].idx], mem[i].base, 10033 mem[i].limit); 10034 } 10035 10036 sbuf_printf(sb, "\n"); 10037 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 10038 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 10039 mem_region_show(sb, "uP RAM:", lo, hi); 10040 10041 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 10042 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 10043 mem_region_show(sb, "uP Extmem2:", lo, hi); 10044 10045 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 10046 for (i = 0, free = 0; i < 2; i++) 10047 free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT)); 10048 sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n", 10049 G_PMRXMAXPAGE(lo), free, 10050 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 10051 (lo & F_PMRXNUMCHN) ? 2 : 1); 10052 10053 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 10054 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 10055 for (i = 0, free = 0; i < 4; i++) 10056 free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT)); 10057 sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n", 10058 G_PMTXMAXPAGE(lo), free, 10059 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 10060 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 10061 sbuf_printf(sb, "%u p-structs (%u free)\n", 10062 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT), 10063 G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT))); 10064 10065 for (i = 0; i < 4; i++) { 10066 if (chip_id(sc) > CHELSIO_T5) 10067 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 10068 else 10069 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 10070 if (is_t5(sc)) { 10071 used = G_T5_USED(lo); 10072 alloc = G_T5_ALLOC(lo); 10073 } else { 10074 used = G_USED(lo); 10075 alloc = G_ALLOC(lo); 10076 } 10077 /* For T6 these are MAC buffer groups */ 10078 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 10079 i, used, alloc); 10080 } 10081 for (i = 0; i < sc->chip_params->nchan; i++) { 10082 if (chip_id(sc) > CHELSIO_T5) 10083 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 10084 else 10085 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 10086 if (is_t5(sc)) { 10087 used = G_T5_USED(lo); 10088 alloc = G_T5_ALLOC(lo); 10089 } else { 10090 used = G_USED(lo); 10091 alloc = G_ALLOC(lo); 10092 } 10093 /* For T6 these are MAC buffer groups */ 10094 sbuf_printf(sb, 10095 "\nLoopback %d using %u pages out of %u allocated", 10096 i, used, alloc); 10097 } 10098 done: 10099 mtx_unlock(&sc->reg_lock); 10100 if (rc == 0) 10101 rc = sbuf_finish(sb); 10102 sbuf_delete(sb); 10103 return (rc); 10104 } 10105 10106 static inline void 10107 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 10108 { 10109 *mask = x | y; 10110 y = htobe64(y); 10111 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 10112 } 10113 10114 static int 10115 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 10116 { 10117 struct adapter *sc = arg1; 10118 struct sbuf *sb; 10119 int rc, i; 10120 10121 MPASS(chip_id(sc) <= CHELSIO_T5); 10122 10123 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10124 if (sb == NULL) 10125 return (ENOMEM); 10126 10127 sbuf_printf(sb, 10128 "Idx Ethernet address Mask Vld Ports PF" 10129 " VF Replication P0 P1 P2 P3 ML"); 10130 rc = 0; 10131 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10132 uint64_t tcamx, tcamy, mask; 10133 uint32_t cls_lo, cls_hi; 10134 uint8_t addr[ETHER_ADDR_LEN]; 10135 10136 mtx_lock(&sc->reg_lock); 10137 if (hw_off_limits(sc)) 10138 rc = ENXIO; 10139 else { 10140 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 10141 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 10142 } 10143 mtx_unlock(&sc->reg_lock); 10144 if (rc != 0) 10145 break; 10146 if (tcamx & tcamy) 10147 continue; 10148 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10149 mtx_lock(&sc->reg_lock); 10150 if (hw_off_limits(sc)) 10151 rc = ENXIO; 10152 else { 10153 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10154 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10155 } 10156 mtx_unlock(&sc->reg_lock); 10157 if (rc != 0) 10158 break; 10159 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 10160 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 10161 addr[3], addr[4], addr[5], (uintmax_t)mask, 10162 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 10163 G_PORTMAP(cls_hi), G_PF(cls_lo), 10164 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 10165 10166 if (cls_lo & F_REPLICATE) { 10167 struct fw_ldst_cmd ldst_cmd; 10168 10169 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10170 ldst_cmd.op_to_addrspace = 10171 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10172 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10173 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10174 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10175 ldst_cmd.u.mps.rplc.fid_idx = 10176 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10177 V_FW_LDST_CMD_IDX(i)); 10178 10179 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10180 "t4mps"); 10181 if (rc) 10182 break; 10183 if (hw_off_limits(sc)) 10184 rc = ENXIO; 10185 else 10186 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10187 sizeof(ldst_cmd), &ldst_cmd); 10188 end_synchronized_op(sc, 0); 10189 if (rc != 0) 10190 break; 10191 else { 10192 sbuf_printf(sb, " %08x %08x %08x %08x", 10193 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10194 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10195 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10196 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10197 } 10198 } else 10199 sbuf_printf(sb, "%36s", ""); 10200 10201 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 10202 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 10203 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 10204 } 10205 10206 if (rc) 10207 (void) sbuf_finish(sb); 10208 else 10209 rc = sbuf_finish(sb); 10210 sbuf_delete(sb); 10211 10212 return (rc); 10213 } 10214 10215 static int 10216 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 10217 { 10218 struct adapter *sc = arg1; 10219 struct sbuf *sb; 10220 int rc, i; 10221 10222 MPASS(chip_id(sc) > CHELSIO_T5); 10223 10224 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10225 if (sb == NULL) 10226 return (ENOMEM); 10227 10228 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 10229 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 10230 " Replication" 10231 " P0 P1 P2 P3 ML\n"); 10232 10233 rc = 0; 10234 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10235 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 10236 uint16_t ivlan; 10237 uint64_t tcamx, tcamy, val, mask; 10238 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 10239 uint8_t addr[ETHER_ADDR_LEN]; 10240 10241 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 10242 if (i < 256) 10243 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 10244 else 10245 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 10246 mtx_lock(&sc->reg_lock); 10247 if (hw_off_limits(sc)) 10248 rc = ENXIO; 10249 else { 10250 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10251 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10252 tcamy = G_DMACH(val) << 32; 10253 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10254 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10255 } 10256 mtx_unlock(&sc->reg_lock); 10257 if (rc != 0) 10258 break; 10259 10260 lookup_type = G_DATALKPTYPE(data2); 10261 port_num = G_DATAPORTNUM(data2); 10262 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10263 /* Inner header VNI */ 10264 vniy = ((data2 & F_DATAVIDH2) << 23) | 10265 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10266 dip_hit = data2 & F_DATADIPHIT; 10267 vlan_vld = 0; 10268 } else { 10269 vniy = 0; 10270 dip_hit = 0; 10271 vlan_vld = data2 & F_DATAVIDH2; 10272 ivlan = G_VIDL(val); 10273 } 10274 10275 ctl |= V_CTLXYBITSEL(1); 10276 mtx_lock(&sc->reg_lock); 10277 if (hw_off_limits(sc)) 10278 rc = ENXIO; 10279 else { 10280 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10281 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10282 tcamx = G_DMACH(val) << 32; 10283 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10284 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10285 } 10286 mtx_unlock(&sc->reg_lock); 10287 if (rc != 0) 10288 break; 10289 10290 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10291 /* Inner header VNI mask */ 10292 vnix = ((data2 & F_DATAVIDH2) << 23) | 10293 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10294 } else 10295 vnix = 0; 10296 10297 if (tcamx & tcamy) 10298 continue; 10299 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10300 10301 mtx_lock(&sc->reg_lock); 10302 if (hw_off_limits(sc)) 10303 rc = ENXIO; 10304 else { 10305 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10306 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10307 } 10308 mtx_unlock(&sc->reg_lock); 10309 if (rc != 0) 10310 break; 10311 10312 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10313 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10314 "%012jx %06x %06x - - %3c" 10315 " I %4x %3c %#x%4u%4d", i, addr[0], 10316 addr[1], addr[2], addr[3], addr[4], addr[5], 10317 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 10318 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10319 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10320 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10321 } else { 10322 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10323 "%012jx - - ", i, addr[0], addr[1], 10324 addr[2], addr[3], addr[4], addr[5], 10325 (uintmax_t)mask); 10326 10327 if (vlan_vld) 10328 sbuf_printf(sb, "%4u Y ", ivlan); 10329 else 10330 sbuf_printf(sb, " - N "); 10331 10332 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 10333 lookup_type ? 'I' : 'O', port_num, 10334 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10335 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10336 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10337 } 10338 10339 10340 if (cls_lo & F_T6_REPLICATE) { 10341 struct fw_ldst_cmd ldst_cmd; 10342 10343 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10344 ldst_cmd.op_to_addrspace = 10345 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10346 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10347 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10348 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10349 ldst_cmd.u.mps.rplc.fid_idx = 10350 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10351 V_FW_LDST_CMD_IDX(i)); 10352 10353 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10354 "t6mps"); 10355 if (rc) 10356 break; 10357 if (hw_off_limits(sc)) 10358 rc = ENXIO; 10359 else 10360 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10361 sizeof(ldst_cmd), &ldst_cmd); 10362 end_synchronized_op(sc, 0); 10363 if (rc != 0) 10364 break; 10365 else { 10366 sbuf_printf(sb, " %08x %08x %08x %08x" 10367 " %08x %08x %08x %08x", 10368 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 10369 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 10370 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 10371 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 10372 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10373 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10374 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10375 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10376 } 10377 } else 10378 sbuf_printf(sb, "%72s", ""); 10379 10380 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 10381 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 10382 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 10383 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 10384 } 10385 10386 if (rc) 10387 (void) sbuf_finish(sb); 10388 else 10389 rc = sbuf_finish(sb); 10390 sbuf_delete(sb); 10391 10392 return (rc); 10393 } 10394 10395 static int 10396 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 10397 { 10398 struct adapter *sc = arg1; 10399 struct sbuf *sb; 10400 int rc; 10401 uint16_t mtus[NMTUS]; 10402 10403 rc = 0; 10404 mtx_lock(&sc->reg_lock); 10405 if (hw_off_limits(sc)) 10406 rc = ENXIO; 10407 else 10408 t4_read_mtu_tbl(sc, mtus, NULL); 10409 mtx_unlock(&sc->reg_lock); 10410 if (rc != 0) 10411 return (rc); 10412 10413 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10414 if (sb == NULL) 10415 return (ENOMEM); 10416 10417 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 10418 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 10419 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 10420 mtus[14], mtus[15]); 10421 10422 rc = sbuf_finish(sb); 10423 sbuf_delete(sb); 10424 10425 return (rc); 10426 } 10427 10428 static int 10429 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 10430 { 10431 struct adapter *sc = arg1; 10432 struct sbuf *sb; 10433 int rc, i; 10434 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 10435 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 10436 static const char *tx_stats[MAX_PM_NSTATS] = { 10437 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 10438 "Tx FIFO wait", NULL, "Tx latency" 10439 }; 10440 static const char *rx_stats[MAX_PM_NSTATS] = { 10441 "Read:", "Write bypass:", "Write mem:", "Flush:", 10442 "Rx FIFO wait", NULL, "Rx latency" 10443 }; 10444 10445 rc = 0; 10446 mtx_lock(&sc->reg_lock); 10447 if (hw_off_limits(sc)) 10448 rc = ENXIO; 10449 else { 10450 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 10451 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 10452 } 10453 mtx_unlock(&sc->reg_lock); 10454 if (rc != 0) 10455 return (rc); 10456 10457 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10458 if (sb == NULL) 10459 return (ENOMEM); 10460 10461 sbuf_printf(sb, " Tx pcmds Tx bytes"); 10462 for (i = 0; i < 4; i++) { 10463 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10464 tx_cyc[i]); 10465 } 10466 10467 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 10468 for (i = 0; i < 4; i++) { 10469 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10470 rx_cyc[i]); 10471 } 10472 10473 if (chip_id(sc) > CHELSIO_T5) { 10474 sbuf_printf(sb, 10475 "\n Total wait Total occupancy"); 10476 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10477 tx_cyc[i]); 10478 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10479 rx_cyc[i]); 10480 10481 i += 2; 10482 MPASS(i < nitems(tx_stats)); 10483 10484 sbuf_printf(sb, 10485 "\n Reads Total wait"); 10486 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10487 tx_cyc[i]); 10488 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10489 rx_cyc[i]); 10490 } 10491 10492 rc = sbuf_finish(sb); 10493 sbuf_delete(sb); 10494 10495 return (rc); 10496 } 10497 10498 static int 10499 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 10500 { 10501 struct adapter *sc = arg1; 10502 struct sbuf *sb; 10503 int rc; 10504 struct tp_rdma_stats stats; 10505 10506 rc = 0; 10507 mtx_lock(&sc->reg_lock); 10508 if (hw_off_limits(sc)) 10509 rc = ENXIO; 10510 else 10511 t4_tp_get_rdma_stats(sc, &stats, 0); 10512 mtx_unlock(&sc->reg_lock); 10513 if (rc != 0) 10514 return (rc); 10515 10516 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10517 if (sb == NULL) 10518 return (ENOMEM); 10519 10520 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 10521 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 10522 10523 rc = sbuf_finish(sb); 10524 sbuf_delete(sb); 10525 10526 return (rc); 10527 } 10528 10529 static int 10530 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 10531 { 10532 struct adapter *sc = arg1; 10533 struct sbuf *sb; 10534 int rc; 10535 struct tp_tcp_stats v4, v6; 10536 10537 rc = 0; 10538 mtx_lock(&sc->reg_lock); 10539 if (hw_off_limits(sc)) 10540 rc = ENXIO; 10541 else 10542 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 10543 mtx_unlock(&sc->reg_lock); 10544 if (rc != 0) 10545 return (rc); 10546 10547 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10548 if (sb == NULL) 10549 return (ENOMEM); 10550 10551 sbuf_printf(sb, 10552 " IP IPv6\n"); 10553 sbuf_printf(sb, "OutRsts: %20u %20u\n", 10554 v4.tcp_out_rsts, v6.tcp_out_rsts); 10555 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 10556 v4.tcp_in_segs, v6.tcp_in_segs); 10557 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 10558 v4.tcp_out_segs, v6.tcp_out_segs); 10559 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 10560 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 10561 10562 rc = sbuf_finish(sb); 10563 sbuf_delete(sb); 10564 10565 return (rc); 10566 } 10567 10568 static int 10569 sysctl_tids(SYSCTL_HANDLER_ARGS) 10570 { 10571 struct adapter *sc = arg1; 10572 struct sbuf *sb; 10573 int rc; 10574 uint32_t x, y; 10575 struct tid_info *t = &sc->tids; 10576 10577 rc = 0; 10578 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10579 if (sb == NULL) 10580 return (ENOMEM); 10581 10582 if (t->natids) { 10583 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 10584 t->atids_in_use); 10585 } 10586 10587 if (t->nhpftids) { 10588 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 10589 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 10590 } 10591 10592 if (t->ntids) { 10593 bool hashen = false; 10594 10595 mtx_lock(&sc->reg_lock); 10596 if (hw_off_limits(sc)) 10597 rc = ENXIO; 10598 else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 10599 hashen = true; 10600 if (chip_id(sc) <= CHELSIO_T5) { 10601 x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 10602 y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 10603 } else { 10604 x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 10605 y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 10606 } 10607 } 10608 mtx_unlock(&sc->reg_lock); 10609 if (rc != 0) 10610 goto done; 10611 10612 sbuf_printf(sb, "TID range: "); 10613 if (hashen) { 10614 if (x) 10615 sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1); 10616 sbuf_printf(sb, "%u-%u", y, t->ntids - 1); 10617 } else { 10618 sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base + 10619 t->ntids - 1); 10620 } 10621 sbuf_printf(sb, ", in use: %u\n", 10622 atomic_load_acq_int(&t->tids_in_use)); 10623 } 10624 10625 if (t->nstids) { 10626 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 10627 t->stid_base + t->nstids - 1, t->stids_in_use); 10628 } 10629 10630 if (t->nftids) { 10631 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 10632 t->ftid_end, t->ftids_in_use); 10633 } 10634 10635 if (t->netids) { 10636 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 10637 t->etid_base + t->netids - 1, t->etids_in_use); 10638 } 10639 10640 mtx_lock(&sc->reg_lock); 10641 if (hw_off_limits(sc)) 10642 rc = ENXIO; 10643 else { 10644 x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4); 10645 y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6); 10646 } 10647 mtx_unlock(&sc->reg_lock); 10648 if (rc != 0) 10649 goto done; 10650 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y); 10651 done: 10652 if (rc == 0) 10653 rc = sbuf_finish(sb); 10654 else 10655 (void)sbuf_finish(sb); 10656 sbuf_delete(sb); 10657 10658 return (rc); 10659 } 10660 10661 static int 10662 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 10663 { 10664 struct adapter *sc = arg1; 10665 struct sbuf *sb; 10666 int rc; 10667 struct tp_err_stats stats; 10668 10669 rc = 0; 10670 mtx_lock(&sc->reg_lock); 10671 if (hw_off_limits(sc)) 10672 rc = ENXIO; 10673 else 10674 t4_tp_get_err_stats(sc, &stats, 0); 10675 mtx_unlock(&sc->reg_lock); 10676 if (rc != 0) 10677 return (rc); 10678 10679 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10680 if (sb == NULL) 10681 return (ENOMEM); 10682 10683 if (sc->chip_params->nchan > 2) { 10684 sbuf_printf(sb, " channel 0 channel 1" 10685 " channel 2 channel 3\n"); 10686 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 10687 stats.mac_in_errs[0], stats.mac_in_errs[1], 10688 stats.mac_in_errs[2], stats.mac_in_errs[3]); 10689 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 10690 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 10691 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 10692 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 10693 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 10694 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 10695 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 10696 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 10697 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 10698 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 10699 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 10700 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 10701 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 10702 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 10703 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 10704 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 10705 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 10706 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 10707 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 10708 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 10709 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 10710 } else { 10711 sbuf_printf(sb, " channel 0 channel 1\n"); 10712 sbuf_printf(sb, "macInErrs: %10u %10u\n", 10713 stats.mac_in_errs[0], stats.mac_in_errs[1]); 10714 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 10715 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 10716 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 10717 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 10718 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 10719 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 10720 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 10721 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 10722 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 10723 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 10724 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 10725 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 10726 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 10727 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 10728 } 10729 10730 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 10731 stats.ofld_no_neigh, stats.ofld_cong_defer); 10732 10733 rc = sbuf_finish(sb); 10734 sbuf_delete(sb); 10735 10736 return (rc); 10737 } 10738 10739 static int 10740 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS) 10741 { 10742 struct adapter *sc = arg1; 10743 struct sbuf *sb; 10744 int rc; 10745 struct tp_tnl_stats stats; 10746 10747 rc = 0; 10748 mtx_lock(&sc->reg_lock); 10749 if (hw_off_limits(sc)) 10750 rc = ENXIO; 10751 else 10752 t4_tp_get_tnl_stats(sc, &stats, 1); 10753 mtx_unlock(&sc->reg_lock); 10754 if (rc != 0) 10755 return (rc); 10756 10757 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10758 if (sb == NULL) 10759 return (ENOMEM); 10760 10761 if (sc->chip_params->nchan > 2) { 10762 sbuf_printf(sb, " channel 0 channel 1" 10763 " channel 2 channel 3\n"); 10764 sbuf_printf(sb, "OutPkts: %10u %10u %10u %10u\n", 10765 stats.out_pkt[0], stats.out_pkt[1], 10766 stats.out_pkt[2], stats.out_pkt[3]); 10767 sbuf_printf(sb, "InPkts: %10u %10u %10u %10u", 10768 stats.in_pkt[0], stats.in_pkt[1], 10769 stats.in_pkt[2], stats.in_pkt[3]); 10770 } else { 10771 sbuf_printf(sb, " channel 0 channel 1\n"); 10772 sbuf_printf(sb, "OutPkts: %10u %10u\n", 10773 stats.out_pkt[0], stats.out_pkt[1]); 10774 sbuf_printf(sb, "InPkts: %10u %10u", 10775 stats.in_pkt[0], stats.in_pkt[1]); 10776 } 10777 10778 rc = sbuf_finish(sb); 10779 sbuf_delete(sb); 10780 10781 return (rc); 10782 } 10783 10784 static int 10785 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 10786 { 10787 struct adapter *sc = arg1; 10788 struct tp_params *tpp = &sc->params.tp; 10789 u_int mask; 10790 int rc; 10791 10792 mask = tpp->la_mask >> 16; 10793 rc = sysctl_handle_int(oidp, &mask, 0, req); 10794 if (rc != 0 || req->newptr == NULL) 10795 return (rc); 10796 if (mask > 0xffff) 10797 return (EINVAL); 10798 mtx_lock(&sc->reg_lock); 10799 if (hw_off_limits(sc)) 10800 rc = ENXIO; 10801 else { 10802 tpp->la_mask = mask << 16; 10803 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, 10804 tpp->la_mask); 10805 } 10806 mtx_unlock(&sc->reg_lock); 10807 10808 return (rc); 10809 } 10810 10811 struct field_desc { 10812 const char *name; 10813 u_int start; 10814 u_int width; 10815 }; 10816 10817 static void 10818 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 10819 { 10820 char buf[32]; 10821 int line_size = 0; 10822 10823 while (f->name) { 10824 uint64_t mask = (1ULL << f->width) - 1; 10825 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 10826 ((uintmax_t)v >> f->start) & mask); 10827 10828 if (line_size + len >= 79) { 10829 line_size = 8; 10830 sbuf_printf(sb, "\n "); 10831 } 10832 sbuf_printf(sb, "%s ", buf); 10833 line_size += len + 1; 10834 f++; 10835 } 10836 sbuf_printf(sb, "\n"); 10837 } 10838 10839 static const struct field_desc tp_la0[] = { 10840 { "RcfOpCodeOut", 60, 4 }, 10841 { "State", 56, 4 }, 10842 { "WcfState", 52, 4 }, 10843 { "RcfOpcSrcOut", 50, 2 }, 10844 { "CRxError", 49, 1 }, 10845 { "ERxError", 48, 1 }, 10846 { "SanityFailed", 47, 1 }, 10847 { "SpuriousMsg", 46, 1 }, 10848 { "FlushInputMsg", 45, 1 }, 10849 { "FlushInputCpl", 44, 1 }, 10850 { "RssUpBit", 43, 1 }, 10851 { "RssFilterHit", 42, 1 }, 10852 { "Tid", 32, 10 }, 10853 { "InitTcb", 31, 1 }, 10854 { "LineNumber", 24, 7 }, 10855 { "Emsg", 23, 1 }, 10856 { "EdataOut", 22, 1 }, 10857 { "Cmsg", 21, 1 }, 10858 { "CdataOut", 20, 1 }, 10859 { "EreadPdu", 19, 1 }, 10860 { "CreadPdu", 18, 1 }, 10861 { "TunnelPkt", 17, 1 }, 10862 { "RcfPeerFin", 16, 1 }, 10863 { "RcfReasonOut", 12, 4 }, 10864 { "TxCchannel", 10, 2 }, 10865 { "RcfTxChannel", 8, 2 }, 10866 { "RxEchannel", 6, 2 }, 10867 { "RcfRxChannel", 5, 1 }, 10868 { "RcfDataOutSrdy", 4, 1 }, 10869 { "RxDvld", 3, 1 }, 10870 { "RxOoDvld", 2, 1 }, 10871 { "RxCongestion", 1, 1 }, 10872 { "TxCongestion", 0, 1 }, 10873 { NULL } 10874 }; 10875 10876 static const struct field_desc tp_la1[] = { 10877 { "CplCmdIn", 56, 8 }, 10878 { "CplCmdOut", 48, 8 }, 10879 { "ESynOut", 47, 1 }, 10880 { "EAckOut", 46, 1 }, 10881 { "EFinOut", 45, 1 }, 10882 { "ERstOut", 44, 1 }, 10883 { "SynIn", 43, 1 }, 10884 { "AckIn", 42, 1 }, 10885 { "FinIn", 41, 1 }, 10886 { "RstIn", 40, 1 }, 10887 { "DataIn", 39, 1 }, 10888 { "DataInVld", 38, 1 }, 10889 { "PadIn", 37, 1 }, 10890 { "RxBufEmpty", 36, 1 }, 10891 { "RxDdp", 35, 1 }, 10892 { "RxFbCongestion", 34, 1 }, 10893 { "TxFbCongestion", 33, 1 }, 10894 { "TxPktSumSrdy", 32, 1 }, 10895 { "RcfUlpType", 28, 4 }, 10896 { "Eread", 27, 1 }, 10897 { "Ebypass", 26, 1 }, 10898 { "Esave", 25, 1 }, 10899 { "Static0", 24, 1 }, 10900 { "Cread", 23, 1 }, 10901 { "Cbypass", 22, 1 }, 10902 { "Csave", 21, 1 }, 10903 { "CPktOut", 20, 1 }, 10904 { "RxPagePoolFull", 18, 2 }, 10905 { "RxLpbkPkt", 17, 1 }, 10906 { "TxLpbkPkt", 16, 1 }, 10907 { "RxVfValid", 15, 1 }, 10908 { "SynLearned", 14, 1 }, 10909 { "SetDelEntry", 13, 1 }, 10910 { "SetInvEntry", 12, 1 }, 10911 { "CpcmdDvld", 11, 1 }, 10912 { "CpcmdSave", 10, 1 }, 10913 { "RxPstructsFull", 8, 2 }, 10914 { "EpcmdDvld", 7, 1 }, 10915 { "EpcmdFlush", 6, 1 }, 10916 { "EpcmdTrimPrefix", 5, 1 }, 10917 { "EpcmdTrimPostfix", 4, 1 }, 10918 { "ERssIp4Pkt", 3, 1 }, 10919 { "ERssIp6Pkt", 2, 1 }, 10920 { "ERssTcpUdpPkt", 1, 1 }, 10921 { "ERssFceFipPkt", 0, 1 }, 10922 { NULL } 10923 }; 10924 10925 static const struct field_desc tp_la2[] = { 10926 { "CplCmdIn", 56, 8 }, 10927 { "MpsVfVld", 55, 1 }, 10928 { "MpsPf", 52, 3 }, 10929 { "MpsVf", 44, 8 }, 10930 { "SynIn", 43, 1 }, 10931 { "AckIn", 42, 1 }, 10932 { "FinIn", 41, 1 }, 10933 { "RstIn", 40, 1 }, 10934 { "DataIn", 39, 1 }, 10935 { "DataInVld", 38, 1 }, 10936 { "PadIn", 37, 1 }, 10937 { "RxBufEmpty", 36, 1 }, 10938 { "RxDdp", 35, 1 }, 10939 { "RxFbCongestion", 34, 1 }, 10940 { "TxFbCongestion", 33, 1 }, 10941 { "TxPktSumSrdy", 32, 1 }, 10942 { "RcfUlpType", 28, 4 }, 10943 { "Eread", 27, 1 }, 10944 { "Ebypass", 26, 1 }, 10945 { "Esave", 25, 1 }, 10946 { "Static0", 24, 1 }, 10947 { "Cread", 23, 1 }, 10948 { "Cbypass", 22, 1 }, 10949 { "Csave", 21, 1 }, 10950 { "CPktOut", 20, 1 }, 10951 { "RxPagePoolFull", 18, 2 }, 10952 { "RxLpbkPkt", 17, 1 }, 10953 { "TxLpbkPkt", 16, 1 }, 10954 { "RxVfValid", 15, 1 }, 10955 { "SynLearned", 14, 1 }, 10956 { "SetDelEntry", 13, 1 }, 10957 { "SetInvEntry", 12, 1 }, 10958 { "CpcmdDvld", 11, 1 }, 10959 { "CpcmdSave", 10, 1 }, 10960 { "RxPstructsFull", 8, 2 }, 10961 { "EpcmdDvld", 7, 1 }, 10962 { "EpcmdFlush", 6, 1 }, 10963 { "EpcmdTrimPrefix", 5, 1 }, 10964 { "EpcmdTrimPostfix", 4, 1 }, 10965 { "ERssIp4Pkt", 3, 1 }, 10966 { "ERssIp6Pkt", 2, 1 }, 10967 { "ERssTcpUdpPkt", 1, 1 }, 10968 { "ERssFceFipPkt", 0, 1 }, 10969 { NULL } 10970 }; 10971 10972 static void 10973 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 10974 { 10975 10976 field_desc_show(sb, *p, tp_la0); 10977 } 10978 10979 static void 10980 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 10981 { 10982 10983 if (idx) 10984 sbuf_printf(sb, "\n"); 10985 field_desc_show(sb, p[0], tp_la0); 10986 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10987 field_desc_show(sb, p[1], tp_la0); 10988 } 10989 10990 static void 10991 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 10992 { 10993 10994 if (idx) 10995 sbuf_printf(sb, "\n"); 10996 field_desc_show(sb, p[0], tp_la0); 10997 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10998 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 10999 } 11000 11001 static int 11002 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 11003 { 11004 struct adapter *sc = arg1; 11005 struct sbuf *sb; 11006 uint64_t *buf, *p; 11007 int rc; 11008 u_int i, inc; 11009 void (*show_func)(struct sbuf *, uint64_t *, int); 11010 11011 rc = 0; 11012 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11013 if (sb == NULL) 11014 return (ENOMEM); 11015 11016 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 11017 11018 mtx_lock(&sc->reg_lock); 11019 if (hw_off_limits(sc)) 11020 rc = ENXIO; 11021 else { 11022 t4_tp_read_la(sc, buf, NULL); 11023 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 11024 case 2: 11025 inc = 2; 11026 show_func = tp_la_show2; 11027 break; 11028 case 3: 11029 inc = 2; 11030 show_func = tp_la_show3; 11031 break; 11032 default: 11033 inc = 1; 11034 show_func = tp_la_show; 11035 } 11036 } 11037 mtx_unlock(&sc->reg_lock); 11038 if (rc != 0) 11039 goto done; 11040 11041 p = buf; 11042 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 11043 (*show_func)(sb, p, i); 11044 rc = sbuf_finish(sb); 11045 done: 11046 sbuf_delete(sb); 11047 free(buf, M_CXGBE); 11048 return (rc); 11049 } 11050 11051 static int 11052 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 11053 { 11054 struct adapter *sc = arg1; 11055 struct sbuf *sb; 11056 int rc; 11057 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 11058 11059 rc = 0; 11060 mtx_lock(&sc->reg_lock); 11061 if (hw_off_limits(sc)) 11062 rc = ENXIO; 11063 else 11064 t4_get_chan_txrate(sc, nrate, orate); 11065 mtx_unlock(&sc->reg_lock); 11066 if (rc != 0) 11067 return (rc); 11068 11069 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 11070 if (sb == NULL) 11071 return (ENOMEM); 11072 11073 if (sc->chip_params->nchan > 2) { 11074 sbuf_printf(sb, " channel 0 channel 1" 11075 " channel 2 channel 3\n"); 11076 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 11077 nrate[0], nrate[1], nrate[2], nrate[3]); 11078 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 11079 orate[0], orate[1], orate[2], orate[3]); 11080 } else { 11081 sbuf_printf(sb, " channel 0 channel 1\n"); 11082 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 11083 nrate[0], nrate[1]); 11084 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 11085 orate[0], orate[1]); 11086 } 11087 11088 rc = sbuf_finish(sb); 11089 sbuf_delete(sb); 11090 11091 return (rc); 11092 } 11093 11094 static int 11095 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 11096 { 11097 struct adapter *sc = arg1; 11098 struct sbuf *sb; 11099 uint32_t *buf, *p; 11100 int rc, i; 11101 11102 rc = 0; 11103 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11104 if (sb == NULL) 11105 return (ENOMEM); 11106 11107 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 11108 M_ZERO | M_WAITOK); 11109 11110 mtx_lock(&sc->reg_lock); 11111 if (hw_off_limits(sc)) 11112 rc = ENXIO; 11113 else 11114 t4_ulprx_read_la(sc, buf); 11115 mtx_unlock(&sc->reg_lock); 11116 if (rc != 0) 11117 goto done; 11118 11119 p = buf; 11120 sbuf_printf(sb, " Pcmd Type Message" 11121 " Data"); 11122 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 11123 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 11124 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 11125 } 11126 rc = sbuf_finish(sb); 11127 done: 11128 sbuf_delete(sb); 11129 free(buf, M_CXGBE); 11130 return (rc); 11131 } 11132 11133 static int 11134 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 11135 { 11136 struct adapter *sc = arg1; 11137 struct sbuf *sb; 11138 int rc; 11139 uint32_t cfg, s1, s2; 11140 11141 MPASS(chip_id(sc) >= CHELSIO_T5); 11142 11143 rc = 0; 11144 mtx_lock(&sc->reg_lock); 11145 if (hw_off_limits(sc)) 11146 rc = ENXIO; 11147 else { 11148 cfg = t4_read_reg(sc, A_SGE_STAT_CFG); 11149 s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL); 11150 s2 = t4_read_reg(sc, A_SGE_STAT_MATCH); 11151 } 11152 mtx_unlock(&sc->reg_lock); 11153 if (rc != 0) 11154 return (rc); 11155 11156 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11157 if (sb == NULL) 11158 return (ENOMEM); 11159 11160 if (G_STATSOURCE_T5(cfg) == 7) { 11161 int mode; 11162 11163 mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg); 11164 if (mode == 0) 11165 sbuf_printf(sb, "total %d, incomplete %d", s1, s2); 11166 else if (mode == 1) 11167 sbuf_printf(sb, "total %d, data overflow %d", s1, s2); 11168 else 11169 sbuf_printf(sb, "unknown mode %d", mode); 11170 } 11171 rc = sbuf_finish(sb); 11172 sbuf_delete(sb); 11173 11174 return (rc); 11175 } 11176 11177 static int 11178 sysctl_cpus(SYSCTL_HANDLER_ARGS) 11179 { 11180 struct adapter *sc = arg1; 11181 enum cpu_sets op = arg2; 11182 cpuset_t cpuset; 11183 struct sbuf *sb; 11184 int i, rc; 11185 11186 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 11187 11188 CPU_ZERO(&cpuset); 11189 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 11190 if (rc != 0) 11191 return (rc); 11192 11193 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11194 if (sb == NULL) 11195 return (ENOMEM); 11196 11197 CPU_FOREACH(i) 11198 sbuf_printf(sb, "%d ", i); 11199 rc = sbuf_finish(sb); 11200 sbuf_delete(sb); 11201 11202 return (rc); 11203 } 11204 11205 static int 11206 sysctl_reset(SYSCTL_HANDLER_ARGS) 11207 { 11208 struct adapter *sc = arg1; 11209 u_int val; 11210 int rc; 11211 11212 val = atomic_load_int(&sc->num_resets); 11213 rc = sysctl_handle_int(oidp, &val, 0, req); 11214 if (rc != 0 || req->newptr == NULL) 11215 return (rc); 11216 11217 if (val == 0) { 11218 /* Zero out the counter that tracks reset. */ 11219 atomic_store_int(&sc->num_resets, 0); 11220 return (0); 11221 } 11222 11223 if (val != 1) 11224 return (EINVAL); /* 0 or 1 are the only legal values */ 11225 11226 if (hw_off_limits(sc)) /* harmless race */ 11227 return (EALREADY); 11228 11229 taskqueue_enqueue(reset_tq, &sc->reset_task); 11230 return (0); 11231 } 11232 11233 #ifdef TCP_OFFLOAD 11234 static int 11235 sysctl_tls(SYSCTL_HANDLER_ARGS) 11236 { 11237 struct adapter *sc = arg1; 11238 int i, j, v, rc; 11239 struct vi_info *vi; 11240 11241 v = sc->tt.tls; 11242 rc = sysctl_handle_int(oidp, &v, 0, req); 11243 if (rc != 0 || req->newptr == NULL) 11244 return (rc); 11245 11246 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 11247 return (ENOTSUP); 11248 11249 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls"); 11250 if (rc) 11251 return (rc); 11252 if (hw_off_limits(sc)) 11253 rc = ENXIO; 11254 else { 11255 sc->tt.tls = !!v; 11256 for_each_port(sc, i) { 11257 for_each_vi(sc->port[i], j, vi) { 11258 if (vi->flags & VI_INIT_DONE) 11259 t4_update_fl_bufsize(vi->ifp); 11260 } 11261 } 11262 } 11263 end_synchronized_op(sc, 0); 11264 11265 return (rc); 11266 11267 } 11268 11269 static void 11270 unit_conv(char *buf, size_t len, u_int val, u_int factor) 11271 { 11272 u_int rem = val % factor; 11273 11274 if (rem == 0) 11275 snprintf(buf, len, "%u", val / factor); 11276 else { 11277 while (rem % 10 == 0) 11278 rem /= 10; 11279 snprintf(buf, len, "%u.%u", val / factor, rem); 11280 } 11281 } 11282 11283 static int 11284 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 11285 { 11286 struct adapter *sc = arg1; 11287 char buf[16]; 11288 u_int res, re; 11289 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11290 11291 mtx_lock(&sc->reg_lock); 11292 if (hw_off_limits(sc)) 11293 res = (u_int)-1; 11294 else 11295 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 11296 mtx_unlock(&sc->reg_lock); 11297 if (res == (u_int)-1) 11298 return (ENXIO); 11299 11300 switch (arg2) { 11301 case 0: 11302 /* timer_tick */ 11303 re = G_TIMERRESOLUTION(res); 11304 break; 11305 case 1: 11306 /* TCP timestamp tick */ 11307 re = G_TIMESTAMPRESOLUTION(res); 11308 break; 11309 case 2: 11310 /* DACK tick */ 11311 re = G_DELAYEDACKRESOLUTION(res); 11312 break; 11313 default: 11314 return (EDOOFUS); 11315 } 11316 11317 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 11318 11319 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 11320 } 11321 11322 static int 11323 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 11324 { 11325 struct adapter *sc = arg1; 11326 int rc; 11327 u_int dack_tmr, dack_re, v; 11328 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11329 11330 mtx_lock(&sc->reg_lock); 11331 if (hw_off_limits(sc)) 11332 rc = ENXIO; 11333 else { 11334 rc = 0; 11335 dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc, 11336 A_TP_TIMER_RESOLUTION)); 11337 dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER); 11338 } 11339 mtx_unlock(&sc->reg_lock); 11340 if (rc != 0) 11341 return (rc); 11342 11343 v = ((cclk_ps << dack_re) / 1000000) * dack_tmr; 11344 11345 return (sysctl_handle_int(oidp, &v, 0, req)); 11346 } 11347 11348 static int 11349 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 11350 { 11351 struct adapter *sc = arg1; 11352 int rc, reg = arg2; 11353 u_int tre; 11354 u_long tp_tick_us, v; 11355 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11356 11357 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 11358 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 11359 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 11360 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 11361 11362 mtx_lock(&sc->reg_lock); 11363 if (hw_off_limits(sc)) 11364 rc = ENXIO; 11365 else { 11366 rc = 0; 11367 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 11368 tp_tick_us = (cclk_ps << tre) / 1000000; 11369 if (reg == A_TP_INIT_SRTT) 11370 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 11371 else 11372 v = tp_tick_us * t4_read_reg(sc, reg); 11373 } 11374 mtx_unlock(&sc->reg_lock); 11375 if (rc != 0) 11376 return (rc); 11377 else 11378 return (sysctl_handle_long(oidp, &v, 0, req)); 11379 } 11380 11381 /* 11382 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 11383 * passed to this function. 11384 */ 11385 static int 11386 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 11387 { 11388 struct adapter *sc = arg1; 11389 int rc, idx = arg2; 11390 u_int v; 11391 11392 MPASS(idx >= 0 && idx <= 24); 11393 11394 mtx_lock(&sc->reg_lock); 11395 if (hw_off_limits(sc)) 11396 rc = ENXIO; 11397 else { 11398 rc = 0; 11399 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 11400 } 11401 mtx_unlock(&sc->reg_lock); 11402 if (rc != 0) 11403 return (rc); 11404 else 11405 return (sysctl_handle_int(oidp, &v, 0, req)); 11406 } 11407 11408 static int 11409 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 11410 { 11411 struct adapter *sc = arg1; 11412 int rc, idx = arg2; 11413 u_int shift, v, r; 11414 11415 MPASS(idx >= 0 && idx < 16); 11416 11417 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 11418 shift = (idx & 3) << 3; 11419 mtx_lock(&sc->reg_lock); 11420 if (hw_off_limits(sc)) 11421 rc = ENXIO; 11422 else { 11423 rc = 0; 11424 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 11425 } 11426 mtx_unlock(&sc->reg_lock); 11427 if (rc != 0) 11428 return (rc); 11429 else 11430 return (sysctl_handle_int(oidp, &v, 0, req)); 11431 } 11432 11433 static int 11434 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 11435 { 11436 struct vi_info *vi = arg1; 11437 struct adapter *sc = vi->adapter; 11438 int idx, rc, i; 11439 struct sge_ofld_rxq *ofld_rxq; 11440 uint8_t v; 11441 11442 idx = vi->ofld_tmr_idx; 11443 11444 rc = sysctl_handle_int(oidp, &idx, 0, req); 11445 if (rc != 0 || req->newptr == NULL) 11446 return (rc); 11447 11448 if (idx < 0 || idx >= SGE_NTIMERS) 11449 return (EINVAL); 11450 11451 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11452 "t4otmr"); 11453 if (rc) 11454 return (rc); 11455 11456 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 11457 for_each_ofld_rxq(vi, i, ofld_rxq) { 11458 #ifdef atomic_store_rel_8 11459 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 11460 #else 11461 ofld_rxq->iq.intr_params = v; 11462 #endif 11463 } 11464 vi->ofld_tmr_idx = idx; 11465 11466 end_synchronized_op(sc, LOCK_HELD); 11467 return (0); 11468 } 11469 11470 static int 11471 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 11472 { 11473 struct vi_info *vi = arg1; 11474 struct adapter *sc = vi->adapter; 11475 int idx, rc; 11476 11477 idx = vi->ofld_pktc_idx; 11478 11479 rc = sysctl_handle_int(oidp, &idx, 0, req); 11480 if (rc != 0 || req->newptr == NULL) 11481 return (rc); 11482 11483 if (idx < -1 || idx >= SGE_NCOUNTERS) 11484 return (EINVAL); 11485 11486 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11487 "t4opktc"); 11488 if (rc) 11489 return (rc); 11490 11491 if (vi->flags & VI_INIT_DONE) 11492 rc = EBUSY; /* cannot be changed once the queues are created */ 11493 else 11494 vi->ofld_pktc_idx = idx; 11495 11496 end_synchronized_op(sc, LOCK_HELD); 11497 return (rc); 11498 } 11499 #endif 11500 11501 static int 11502 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 11503 { 11504 int rc; 11505 11506 if (cntxt->cid > M_CTXTQID) 11507 return (EINVAL); 11508 11509 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 11510 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 11511 return (EINVAL); 11512 11513 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 11514 if (rc) 11515 return (rc); 11516 11517 if (hw_off_limits(sc)) { 11518 rc = ENXIO; 11519 goto done; 11520 } 11521 11522 if (sc->flags & FW_OK) { 11523 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 11524 &cntxt->data[0]); 11525 if (rc == 0) 11526 goto done; 11527 } 11528 11529 /* 11530 * Read via firmware failed or wasn't even attempted. Read directly via 11531 * the backdoor. 11532 */ 11533 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 11534 done: 11535 end_synchronized_op(sc, 0); 11536 return (rc); 11537 } 11538 11539 static int 11540 load_fw(struct adapter *sc, struct t4_data *fw) 11541 { 11542 int rc; 11543 uint8_t *fw_data; 11544 11545 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 11546 if (rc) 11547 return (rc); 11548 11549 if (hw_off_limits(sc)) { 11550 rc = ENXIO; 11551 goto done; 11552 } 11553 11554 /* 11555 * The firmware, with the sole exception of the memory parity error 11556 * handler, runs from memory and not flash. It is almost always safe to 11557 * install a new firmware on a running system. Just set bit 1 in 11558 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 11559 */ 11560 if (sc->flags & FULL_INIT_DONE && 11561 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 11562 rc = EBUSY; 11563 goto done; 11564 } 11565 11566 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 11567 11568 rc = copyin(fw->data, fw_data, fw->len); 11569 if (rc == 0) 11570 rc = -t4_load_fw(sc, fw_data, fw->len); 11571 11572 free(fw_data, M_CXGBE); 11573 done: 11574 end_synchronized_op(sc, 0); 11575 return (rc); 11576 } 11577 11578 static int 11579 load_cfg(struct adapter *sc, struct t4_data *cfg) 11580 { 11581 int rc; 11582 uint8_t *cfg_data = NULL; 11583 11584 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11585 if (rc) 11586 return (rc); 11587 11588 if (hw_off_limits(sc)) { 11589 rc = ENXIO; 11590 goto done; 11591 } 11592 11593 if (cfg->len == 0) { 11594 /* clear */ 11595 rc = -t4_load_cfg(sc, NULL, 0); 11596 goto done; 11597 } 11598 11599 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 11600 11601 rc = copyin(cfg->data, cfg_data, cfg->len); 11602 if (rc == 0) 11603 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 11604 11605 free(cfg_data, M_CXGBE); 11606 done: 11607 end_synchronized_op(sc, 0); 11608 return (rc); 11609 } 11610 11611 static int 11612 load_boot(struct adapter *sc, struct t4_bootrom *br) 11613 { 11614 int rc; 11615 uint8_t *br_data = NULL; 11616 u_int offset; 11617 11618 if (br->len > 1024 * 1024) 11619 return (EFBIG); 11620 11621 if (br->pf_offset == 0) { 11622 /* pfidx */ 11623 if (br->pfidx_addr > 7) 11624 return (EINVAL); 11625 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 11626 A_PCIE_PF_EXPROM_OFST))); 11627 } else if (br->pf_offset == 1) { 11628 /* offset */ 11629 offset = G_OFFSET(br->pfidx_addr); 11630 } else { 11631 return (EINVAL); 11632 } 11633 11634 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 11635 if (rc) 11636 return (rc); 11637 11638 if (hw_off_limits(sc)) { 11639 rc = ENXIO; 11640 goto done; 11641 } 11642 11643 if (br->len == 0) { 11644 /* clear */ 11645 rc = -t4_load_boot(sc, NULL, offset, 0); 11646 goto done; 11647 } 11648 11649 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 11650 11651 rc = copyin(br->data, br_data, br->len); 11652 if (rc == 0) 11653 rc = -t4_load_boot(sc, br_data, offset, br->len); 11654 11655 free(br_data, M_CXGBE); 11656 done: 11657 end_synchronized_op(sc, 0); 11658 return (rc); 11659 } 11660 11661 static int 11662 load_bootcfg(struct adapter *sc, struct t4_data *bc) 11663 { 11664 int rc; 11665 uint8_t *bc_data = NULL; 11666 11667 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11668 if (rc) 11669 return (rc); 11670 11671 if (hw_off_limits(sc)) { 11672 rc = ENXIO; 11673 goto done; 11674 } 11675 11676 if (bc->len == 0) { 11677 /* clear */ 11678 rc = -t4_load_bootcfg(sc, NULL, 0); 11679 goto done; 11680 } 11681 11682 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 11683 11684 rc = copyin(bc->data, bc_data, bc->len); 11685 if (rc == 0) 11686 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 11687 11688 free(bc_data, M_CXGBE); 11689 done: 11690 end_synchronized_op(sc, 0); 11691 return (rc); 11692 } 11693 11694 static int 11695 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 11696 { 11697 int rc; 11698 struct cudbg_init *cudbg; 11699 void *handle, *buf; 11700 11701 /* buf is large, don't block if no memory is available */ 11702 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 11703 if (buf == NULL) 11704 return (ENOMEM); 11705 11706 handle = cudbg_alloc_handle(); 11707 if (handle == NULL) { 11708 rc = ENOMEM; 11709 goto done; 11710 } 11711 11712 cudbg = cudbg_get_init(handle); 11713 cudbg->adap = sc; 11714 cudbg->print = (cudbg_print_cb)printf; 11715 11716 #ifndef notyet 11717 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 11718 __func__, dump->wr_flash, dump->len, dump->data); 11719 #endif 11720 11721 if (dump->wr_flash) 11722 cudbg->use_flash = 1; 11723 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 11724 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 11725 11726 rc = cudbg_collect(handle, buf, &dump->len); 11727 if (rc != 0) 11728 goto done; 11729 11730 rc = copyout(buf, dump->data, dump->len); 11731 done: 11732 cudbg_free_handle(handle); 11733 free(buf, M_CXGBE); 11734 return (rc); 11735 } 11736 11737 static void 11738 free_offload_policy(struct t4_offload_policy *op) 11739 { 11740 struct offload_rule *r; 11741 int i; 11742 11743 if (op == NULL) 11744 return; 11745 11746 r = &op->rule[0]; 11747 for (i = 0; i < op->nrules; i++, r++) { 11748 free(r->bpf_prog.bf_insns, M_CXGBE); 11749 } 11750 free(op->rule, M_CXGBE); 11751 free(op, M_CXGBE); 11752 } 11753 11754 static int 11755 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 11756 { 11757 int i, rc, len; 11758 struct t4_offload_policy *op, *old; 11759 struct bpf_program *bf; 11760 const struct offload_settings *s; 11761 struct offload_rule *r; 11762 void *u; 11763 11764 if (!is_offload(sc)) 11765 return (ENODEV); 11766 11767 if (uop->nrules == 0) { 11768 /* Delete installed policies. */ 11769 op = NULL; 11770 goto set_policy; 11771 } else if (uop->nrules > 256) { /* arbitrary */ 11772 return (E2BIG); 11773 } 11774 11775 /* Copy userspace offload policy to kernel */ 11776 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 11777 op->nrules = uop->nrules; 11778 len = op->nrules * sizeof(struct offload_rule); 11779 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11780 rc = copyin(uop->rule, op->rule, len); 11781 if (rc) { 11782 free(op->rule, M_CXGBE); 11783 free(op, M_CXGBE); 11784 return (rc); 11785 } 11786 11787 r = &op->rule[0]; 11788 for (i = 0; i < op->nrules; i++, r++) { 11789 11790 /* Validate open_type */ 11791 if (r->open_type != OPEN_TYPE_LISTEN && 11792 r->open_type != OPEN_TYPE_ACTIVE && 11793 r->open_type != OPEN_TYPE_PASSIVE && 11794 r->open_type != OPEN_TYPE_DONTCARE) { 11795 error: 11796 /* 11797 * Rules 0 to i have malloc'd filters that need to be 11798 * freed. Rules i+1 to nrules have userspace pointers 11799 * and should be left alone. 11800 */ 11801 op->nrules = i; 11802 free_offload_policy(op); 11803 return (rc); 11804 } 11805 11806 /* Validate settings */ 11807 s = &r->settings; 11808 if ((s->offload != 0 && s->offload != 1) || 11809 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 11810 s->sched_class < -1 || 11811 s->sched_class >= sc->params.nsched_cls) { 11812 rc = EINVAL; 11813 goto error; 11814 } 11815 11816 bf = &r->bpf_prog; 11817 u = bf->bf_insns; /* userspace ptr */ 11818 bf->bf_insns = NULL; 11819 if (bf->bf_len == 0) { 11820 /* legal, matches everything */ 11821 continue; 11822 } 11823 len = bf->bf_len * sizeof(*bf->bf_insns); 11824 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11825 rc = copyin(u, bf->bf_insns, len); 11826 if (rc != 0) 11827 goto error; 11828 11829 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 11830 rc = EINVAL; 11831 goto error; 11832 } 11833 } 11834 set_policy: 11835 rw_wlock(&sc->policy_lock); 11836 old = sc->policy; 11837 sc->policy = op; 11838 rw_wunlock(&sc->policy_lock); 11839 free_offload_policy(old); 11840 11841 return (0); 11842 } 11843 11844 #define MAX_READ_BUF_SIZE (128 * 1024) 11845 static int 11846 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 11847 { 11848 uint32_t addr, remaining, n; 11849 uint32_t *buf; 11850 int rc; 11851 uint8_t *dst; 11852 11853 mtx_lock(&sc->reg_lock); 11854 if (hw_off_limits(sc)) 11855 rc = ENXIO; 11856 else 11857 rc = validate_mem_range(sc, mr->addr, mr->len); 11858 mtx_unlock(&sc->reg_lock); 11859 if (rc != 0) 11860 return (rc); 11861 11862 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 11863 addr = mr->addr; 11864 remaining = mr->len; 11865 dst = (void *)mr->data; 11866 11867 while (remaining) { 11868 n = min(remaining, MAX_READ_BUF_SIZE); 11869 mtx_lock(&sc->reg_lock); 11870 if (hw_off_limits(sc)) 11871 rc = ENXIO; 11872 else 11873 read_via_memwin(sc, 2, addr, buf, n); 11874 mtx_unlock(&sc->reg_lock); 11875 if (rc != 0) 11876 break; 11877 11878 rc = copyout(buf, dst, n); 11879 if (rc != 0) 11880 break; 11881 11882 dst += n; 11883 remaining -= n; 11884 addr += n; 11885 } 11886 11887 free(buf, M_CXGBE); 11888 return (rc); 11889 } 11890 #undef MAX_READ_BUF_SIZE 11891 11892 static int 11893 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 11894 { 11895 int rc; 11896 11897 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 11898 return (EINVAL); 11899 11900 if (i2cd->len > sizeof(i2cd->data)) 11901 return (EFBIG); 11902 11903 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 11904 if (rc) 11905 return (rc); 11906 if (hw_off_limits(sc)) 11907 rc = ENXIO; 11908 else 11909 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 11910 i2cd->offset, i2cd->len, &i2cd->data[0]); 11911 end_synchronized_op(sc, 0); 11912 11913 return (rc); 11914 } 11915 11916 static int 11917 clear_stats(struct adapter *sc, u_int port_id) 11918 { 11919 int i, v, chan_map; 11920 struct port_info *pi; 11921 struct vi_info *vi; 11922 struct sge_rxq *rxq; 11923 struct sge_txq *txq; 11924 struct sge_wrq *wrq; 11925 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 11926 struct sge_ofld_txq *ofld_txq; 11927 #endif 11928 #ifdef TCP_OFFLOAD 11929 struct sge_ofld_rxq *ofld_rxq; 11930 #endif 11931 11932 if (port_id >= sc->params.nports) 11933 return (EINVAL); 11934 pi = sc->port[port_id]; 11935 if (pi == NULL) 11936 return (EIO); 11937 11938 mtx_lock(&sc->reg_lock); 11939 if (!hw_off_limits(sc)) { 11940 /* MAC stats */ 11941 t4_clr_port_stats(sc, pi->tx_chan); 11942 if (is_t6(sc)) { 11943 if (pi->fcs_reg != -1) 11944 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 11945 else 11946 pi->stats.rx_fcs_err = 0; 11947 } 11948 for_each_vi(pi, v, vi) { 11949 if (vi->flags & VI_INIT_DONE) 11950 t4_clr_vi_stats(sc, vi->vin); 11951 } 11952 chan_map = pi->rx_e_chan_map; 11953 v = 0; /* reuse */ 11954 while (chan_map) { 11955 i = ffs(chan_map) - 1; 11956 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 11957 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 11958 chan_map &= ~(1 << i); 11959 } 11960 } 11961 mtx_unlock(&sc->reg_lock); 11962 pi->tx_parse_error = 0; 11963 pi->tnl_cong_drops = 0; 11964 11965 /* 11966 * Since this command accepts a port, clear stats for 11967 * all VIs on this port. 11968 */ 11969 for_each_vi(pi, v, vi) { 11970 if (vi->flags & VI_INIT_DONE) { 11971 11972 for_each_rxq(vi, i, rxq) { 11973 #if defined(INET) || defined(INET6) 11974 rxq->lro.lro_queued = 0; 11975 rxq->lro.lro_flushed = 0; 11976 #endif 11977 rxq->rxcsum = 0; 11978 rxq->vlan_extraction = 0; 11979 rxq->vxlan_rxcsum = 0; 11980 11981 rxq->fl.cl_allocated = 0; 11982 rxq->fl.cl_recycled = 0; 11983 rxq->fl.cl_fast_recycled = 0; 11984 } 11985 11986 for_each_txq(vi, i, txq) { 11987 txq->txcsum = 0; 11988 txq->tso_wrs = 0; 11989 txq->vlan_insertion = 0; 11990 txq->imm_wrs = 0; 11991 txq->sgl_wrs = 0; 11992 txq->txpkt_wrs = 0; 11993 txq->txpkts0_wrs = 0; 11994 txq->txpkts1_wrs = 0; 11995 txq->txpkts0_pkts = 0; 11996 txq->txpkts1_pkts = 0; 11997 txq->txpkts_flush = 0; 11998 txq->raw_wrs = 0; 11999 txq->vxlan_tso_wrs = 0; 12000 txq->vxlan_txcsum = 0; 12001 txq->kern_tls_records = 0; 12002 txq->kern_tls_short = 0; 12003 txq->kern_tls_partial = 0; 12004 txq->kern_tls_full = 0; 12005 txq->kern_tls_octets = 0; 12006 txq->kern_tls_waste = 0; 12007 txq->kern_tls_options = 0; 12008 txq->kern_tls_header = 0; 12009 txq->kern_tls_fin = 0; 12010 txq->kern_tls_fin_short = 0; 12011 txq->kern_tls_cbc = 0; 12012 txq->kern_tls_gcm = 0; 12013 mp_ring_reset_stats(txq->r); 12014 } 12015 12016 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12017 for_each_ofld_txq(vi, i, ofld_txq) { 12018 ofld_txq->wrq.tx_wrs_direct = 0; 12019 ofld_txq->wrq.tx_wrs_copied = 0; 12020 counter_u64_zero(ofld_txq->tx_iscsi_pdus); 12021 counter_u64_zero(ofld_txq->tx_iscsi_octets); 12022 counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs); 12023 counter_u64_zero(ofld_txq->tx_aio_jobs); 12024 counter_u64_zero(ofld_txq->tx_aio_octets); 12025 counter_u64_zero(ofld_txq->tx_toe_tls_records); 12026 counter_u64_zero(ofld_txq->tx_toe_tls_octets); 12027 } 12028 #endif 12029 #ifdef TCP_OFFLOAD 12030 for_each_ofld_rxq(vi, i, ofld_rxq) { 12031 ofld_rxq->fl.cl_allocated = 0; 12032 ofld_rxq->fl.cl_recycled = 0; 12033 ofld_rxq->fl.cl_fast_recycled = 0; 12034 counter_u64_zero( 12035 ofld_rxq->rx_iscsi_ddp_setup_ok); 12036 counter_u64_zero( 12037 ofld_rxq->rx_iscsi_ddp_setup_error); 12038 ofld_rxq->rx_iscsi_ddp_pdus = 0; 12039 ofld_rxq->rx_iscsi_ddp_octets = 0; 12040 ofld_rxq->rx_iscsi_fl_pdus = 0; 12041 ofld_rxq->rx_iscsi_fl_octets = 0; 12042 ofld_rxq->rx_aio_ddp_jobs = 0; 12043 ofld_rxq->rx_aio_ddp_octets = 0; 12044 ofld_rxq->rx_toe_tls_records = 0; 12045 ofld_rxq->rx_toe_tls_octets = 0; 12046 ofld_rxq->rx_toe_ddp_octets = 0; 12047 counter_u64_zero(ofld_rxq->ddp_buffer_alloc); 12048 counter_u64_zero(ofld_rxq->ddp_buffer_reuse); 12049 counter_u64_zero(ofld_rxq->ddp_buffer_free); 12050 } 12051 #endif 12052 12053 if (IS_MAIN_VI(vi)) { 12054 wrq = &sc->sge.ctrlq[pi->port_id]; 12055 wrq->tx_wrs_direct = 0; 12056 wrq->tx_wrs_copied = 0; 12057 } 12058 } 12059 } 12060 12061 return (0); 12062 } 12063 12064 static int 12065 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12066 { 12067 #ifdef INET6 12068 struct in6_addr in6; 12069 12070 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12071 if (t4_get_clip_entry(sc, &in6, true) != NULL) 12072 return (0); 12073 else 12074 return (EIO); 12075 #else 12076 return (ENOTSUP); 12077 #endif 12078 } 12079 12080 static int 12081 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12082 { 12083 #ifdef INET6 12084 struct in6_addr in6; 12085 12086 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12087 return (t4_release_clip_addr(sc, &in6)); 12088 #else 12089 return (ENOTSUP); 12090 #endif 12091 } 12092 12093 int 12094 t4_os_find_pci_capability(struct adapter *sc, int cap) 12095 { 12096 int i; 12097 12098 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 12099 } 12100 12101 int 12102 t4_os_pci_save_state(struct adapter *sc) 12103 { 12104 device_t dev; 12105 struct pci_devinfo *dinfo; 12106 12107 dev = sc->dev; 12108 dinfo = device_get_ivars(dev); 12109 12110 pci_cfg_save(dev, dinfo, 0); 12111 return (0); 12112 } 12113 12114 int 12115 t4_os_pci_restore_state(struct adapter *sc) 12116 { 12117 device_t dev; 12118 struct pci_devinfo *dinfo; 12119 12120 dev = sc->dev; 12121 dinfo = device_get_ivars(dev); 12122 12123 pci_cfg_restore(dev, dinfo); 12124 return (0); 12125 } 12126 12127 void 12128 t4_os_portmod_changed(struct port_info *pi) 12129 { 12130 struct adapter *sc = pi->adapter; 12131 struct vi_info *vi; 12132 if_t ifp; 12133 static const char *mod_str[] = { 12134 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 12135 }; 12136 12137 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 12138 ("%s: port_type %u", __func__, pi->port_type)); 12139 12140 vi = &pi->vi[0]; 12141 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 12142 PORT_LOCK(pi); 12143 build_medialist(pi); 12144 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 12145 fixup_link_config(pi); 12146 apply_link_config(pi); 12147 } 12148 PORT_UNLOCK(pi); 12149 end_synchronized_op(sc, LOCK_HELD); 12150 } 12151 12152 ifp = vi->ifp; 12153 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 12154 if_printf(ifp, "transceiver unplugged.\n"); 12155 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 12156 if_printf(ifp, "unknown transceiver inserted.\n"); 12157 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 12158 if_printf(ifp, "unsupported transceiver inserted.\n"); 12159 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 12160 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 12161 port_top_speed(pi), mod_str[pi->mod_type]); 12162 } else { 12163 if_printf(ifp, "transceiver (type %d) inserted.\n", 12164 pi->mod_type); 12165 } 12166 } 12167 12168 void 12169 t4_os_link_changed(struct port_info *pi) 12170 { 12171 struct vi_info *vi; 12172 if_t ifp; 12173 struct link_config *lc = &pi->link_cfg; 12174 struct adapter *sc = pi->adapter; 12175 int v; 12176 12177 PORT_LOCK_ASSERT_OWNED(pi); 12178 12179 if (is_t6(sc)) { 12180 if (lc->link_ok) { 12181 if (lc->speed > 25000 || 12182 (lc->speed == 25000 && lc->fec == FEC_RS)) { 12183 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12184 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS); 12185 } else { 12186 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12187 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS); 12188 } 12189 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 12190 pi->stats.rx_fcs_err = 0; 12191 } else { 12192 pi->fcs_reg = -1; 12193 } 12194 } else { 12195 MPASS(pi->fcs_reg != -1); 12196 MPASS(pi->fcs_base == 0); 12197 } 12198 12199 for_each_vi(pi, v, vi) { 12200 ifp = vi->ifp; 12201 if (ifp == NULL || IS_DETACHING(vi)) 12202 continue; 12203 12204 if (lc->link_ok) { 12205 if_setbaudrate(ifp, IF_Mbps(lc->speed)); 12206 if_link_state_change(ifp, LINK_STATE_UP); 12207 } else { 12208 if_link_state_change(ifp, LINK_STATE_DOWN); 12209 } 12210 } 12211 } 12212 12213 void 12214 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 12215 { 12216 struct adapter *sc; 12217 12218 sx_slock(&t4_list_lock); 12219 SLIST_FOREACH(sc, &t4_list, link) { 12220 /* 12221 * func should not make any assumptions about what state sc is 12222 * in - the only guarantee is that sc->sc_lock is a valid lock. 12223 */ 12224 func(sc, arg); 12225 } 12226 sx_sunlock(&t4_list_lock); 12227 } 12228 12229 static int 12230 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 12231 struct thread *td) 12232 { 12233 int rc; 12234 struct adapter *sc = dev->si_drv1; 12235 12236 rc = priv_check(td, PRIV_DRIVER); 12237 if (rc != 0) 12238 return (rc); 12239 12240 switch (cmd) { 12241 case CHELSIO_T4_GETREG: { 12242 struct t4_reg *edata = (struct t4_reg *)data; 12243 12244 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12245 return (EFAULT); 12246 12247 mtx_lock(&sc->reg_lock); 12248 if (hw_off_limits(sc)) 12249 rc = ENXIO; 12250 else if (edata->size == 4) 12251 edata->val = t4_read_reg(sc, edata->addr); 12252 else if (edata->size == 8) 12253 edata->val = t4_read_reg64(sc, edata->addr); 12254 else 12255 rc = EINVAL; 12256 mtx_unlock(&sc->reg_lock); 12257 12258 break; 12259 } 12260 case CHELSIO_T4_SETREG: { 12261 struct t4_reg *edata = (struct t4_reg *)data; 12262 12263 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12264 return (EFAULT); 12265 12266 mtx_lock(&sc->reg_lock); 12267 if (hw_off_limits(sc)) 12268 rc = ENXIO; 12269 else if (edata->size == 4) { 12270 if (edata->val & 0xffffffff00000000) 12271 rc = EINVAL; 12272 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 12273 } else if (edata->size == 8) 12274 t4_write_reg64(sc, edata->addr, edata->val); 12275 else 12276 rc = EINVAL; 12277 mtx_unlock(&sc->reg_lock); 12278 12279 break; 12280 } 12281 case CHELSIO_T4_REGDUMP: { 12282 struct t4_regdump *regs = (struct t4_regdump *)data; 12283 int reglen = t4_get_regs_len(sc); 12284 uint8_t *buf; 12285 12286 if (regs->len < reglen) { 12287 regs->len = reglen; /* hint to the caller */ 12288 return (ENOBUFS); 12289 } 12290 12291 regs->len = reglen; 12292 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 12293 mtx_lock(&sc->reg_lock); 12294 if (hw_off_limits(sc)) 12295 rc = ENXIO; 12296 else 12297 get_regs(sc, regs, buf); 12298 mtx_unlock(&sc->reg_lock); 12299 if (rc == 0) 12300 rc = copyout(buf, regs->data, reglen); 12301 free(buf, M_CXGBE); 12302 break; 12303 } 12304 case CHELSIO_T4_GET_FILTER_MODE: 12305 rc = get_filter_mode(sc, (uint32_t *)data); 12306 break; 12307 case CHELSIO_T4_SET_FILTER_MODE: 12308 rc = set_filter_mode(sc, *(uint32_t *)data); 12309 break; 12310 case CHELSIO_T4_SET_FILTER_MASK: 12311 rc = set_filter_mask(sc, *(uint32_t *)data); 12312 break; 12313 case CHELSIO_T4_GET_FILTER: 12314 rc = get_filter(sc, (struct t4_filter *)data); 12315 break; 12316 case CHELSIO_T4_SET_FILTER: 12317 rc = set_filter(sc, (struct t4_filter *)data); 12318 break; 12319 case CHELSIO_T4_DEL_FILTER: 12320 rc = del_filter(sc, (struct t4_filter *)data); 12321 break; 12322 case CHELSIO_T4_GET_SGE_CONTEXT: 12323 rc = get_sge_context(sc, (struct t4_sge_context *)data); 12324 break; 12325 case CHELSIO_T4_LOAD_FW: 12326 rc = load_fw(sc, (struct t4_data *)data); 12327 break; 12328 case CHELSIO_T4_GET_MEM: 12329 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 12330 break; 12331 case CHELSIO_T4_GET_I2C: 12332 rc = read_i2c(sc, (struct t4_i2c_data *)data); 12333 break; 12334 case CHELSIO_T4_CLEAR_STATS: 12335 rc = clear_stats(sc, *(uint32_t *)data); 12336 break; 12337 case CHELSIO_T4_SCHED_CLASS: 12338 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 12339 break; 12340 case CHELSIO_T4_SCHED_QUEUE: 12341 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 12342 break; 12343 case CHELSIO_T4_GET_TRACER: 12344 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 12345 break; 12346 case CHELSIO_T4_SET_TRACER: 12347 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 12348 break; 12349 case CHELSIO_T4_LOAD_CFG: 12350 rc = load_cfg(sc, (struct t4_data *)data); 12351 break; 12352 case CHELSIO_T4_LOAD_BOOT: 12353 rc = load_boot(sc, (struct t4_bootrom *)data); 12354 break; 12355 case CHELSIO_T4_LOAD_BOOTCFG: 12356 rc = load_bootcfg(sc, (struct t4_data *)data); 12357 break; 12358 case CHELSIO_T4_CUDBG_DUMP: 12359 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 12360 break; 12361 case CHELSIO_T4_SET_OFLD_POLICY: 12362 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 12363 break; 12364 case CHELSIO_T4_HOLD_CLIP_ADDR: 12365 rc = hold_clip_addr(sc, (struct t4_clip_addr *)data); 12366 break; 12367 case CHELSIO_T4_RELEASE_CLIP_ADDR: 12368 rc = release_clip_addr(sc, (struct t4_clip_addr *)data); 12369 break; 12370 default: 12371 rc = ENOTTY; 12372 } 12373 12374 return (rc); 12375 } 12376 12377 #ifdef TCP_OFFLOAD 12378 static int 12379 toe_capability(struct vi_info *vi, bool enable) 12380 { 12381 int rc; 12382 struct port_info *pi = vi->pi; 12383 struct adapter *sc = pi->adapter; 12384 12385 ASSERT_SYNCHRONIZED_OP(sc); 12386 12387 if (!is_offload(sc)) 12388 return (ENODEV); 12389 if (hw_off_limits(sc)) 12390 return (ENXIO); 12391 12392 if (enable) { 12393 #ifdef KERN_TLS 12394 if (sc->flags & KERN_TLS_ON && is_t6(sc)) { 12395 int i, j, n; 12396 struct port_info *p; 12397 struct vi_info *v; 12398 12399 /* 12400 * Reconfigure hardware for TOE if TXTLS is not enabled 12401 * on any ifnet. 12402 */ 12403 n = 0; 12404 for_each_port(sc, i) { 12405 p = sc->port[i]; 12406 for_each_vi(p, j, v) { 12407 if (if_getcapenable(v->ifp) & IFCAP_TXTLS) { 12408 CH_WARN(sc, 12409 "%s has NIC TLS enabled.\n", 12410 device_get_nameunit(v->dev)); 12411 n++; 12412 } 12413 } 12414 } 12415 if (n > 0) { 12416 CH_WARN(sc, "Disable NIC TLS on all interfaces " 12417 "associated with this adapter before " 12418 "trying to enable TOE.\n"); 12419 return (EAGAIN); 12420 } 12421 rc = t6_config_kern_tls(sc, false); 12422 if (rc) 12423 return (rc); 12424 } 12425 #endif 12426 if ((if_getcapenable(vi->ifp) & IFCAP_TOE) != 0) { 12427 /* TOE is already enabled. */ 12428 return (0); 12429 } 12430 12431 /* 12432 * We need the port's queues around so that we're able to send 12433 * and receive CPLs to/from the TOE even if the ifnet for this 12434 * port has never been UP'd administratively. 12435 */ 12436 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 12437 return (rc); 12438 if (!(pi->vi[0].flags & VI_INIT_DONE) && 12439 ((rc = vi_init(&pi->vi[0])) != 0)) 12440 return (rc); 12441 12442 if (isset(&sc->offload_map, pi->port_id)) { 12443 /* TOE is enabled on another VI of this port. */ 12444 pi->uld_vis++; 12445 return (0); 12446 } 12447 12448 if (!uld_active(sc, ULD_TOM)) { 12449 rc = t4_activate_uld(sc, ULD_TOM); 12450 if (rc == EAGAIN) { 12451 log(LOG_WARNING, 12452 "You must kldload t4_tom.ko before trying " 12453 "to enable TOE on a cxgbe interface.\n"); 12454 } 12455 if (rc != 0) 12456 return (rc); 12457 KASSERT(sc->tom_softc != NULL, 12458 ("%s: TOM activated but softc NULL", __func__)); 12459 KASSERT(uld_active(sc, ULD_TOM), 12460 ("%s: TOM activated but flag not set", __func__)); 12461 } 12462 12463 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 12464 if (!uld_active(sc, ULD_IWARP)) 12465 (void) t4_activate_uld(sc, ULD_IWARP); 12466 if (!uld_active(sc, ULD_ISCSI)) 12467 (void) t4_activate_uld(sc, ULD_ISCSI); 12468 12469 pi->uld_vis++; 12470 setbit(&sc->offload_map, pi->port_id); 12471 } else { 12472 pi->uld_vis--; 12473 12474 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 12475 return (0); 12476 12477 KASSERT(uld_active(sc, ULD_TOM), 12478 ("%s: TOM never initialized?", __func__)); 12479 clrbit(&sc->offload_map, pi->port_id); 12480 } 12481 12482 return (0); 12483 } 12484 12485 /* 12486 * Add an upper layer driver to the global list. 12487 */ 12488 int 12489 t4_register_uld(struct uld_info *ui, int id) 12490 { 12491 int rc; 12492 12493 if (id < 0 || id > ULD_MAX) 12494 return (EINVAL); 12495 sx_xlock(&t4_uld_list_lock); 12496 if (t4_uld_list[id] != NULL) 12497 rc = EEXIST; 12498 else { 12499 t4_uld_list[id] = ui; 12500 rc = 0; 12501 } 12502 sx_xunlock(&t4_uld_list_lock); 12503 return (rc); 12504 } 12505 12506 int 12507 t4_unregister_uld(struct uld_info *ui, int id) 12508 { 12509 12510 if (id < 0 || id > ULD_MAX) 12511 return (EINVAL); 12512 sx_xlock(&t4_uld_list_lock); 12513 MPASS(t4_uld_list[id] == ui); 12514 t4_uld_list[id] = NULL; 12515 sx_xunlock(&t4_uld_list_lock); 12516 return (0); 12517 } 12518 12519 int 12520 t4_activate_uld(struct adapter *sc, int id) 12521 { 12522 int rc; 12523 12524 ASSERT_SYNCHRONIZED_OP(sc); 12525 12526 if (id < 0 || id > ULD_MAX) 12527 return (EINVAL); 12528 12529 /* Adapter needs to be initialized before any ULD can be activated. */ 12530 if (!(sc->flags & FULL_INIT_DONE)) { 12531 rc = adapter_init(sc); 12532 if (rc != 0) 12533 return (rc); 12534 } 12535 12536 sx_slock(&t4_uld_list_lock); 12537 if (t4_uld_list[id] == NULL) 12538 rc = EAGAIN; /* load the KLD with this ULD and try again. */ 12539 else { 12540 rc = t4_uld_list[id]->uld_activate(sc); 12541 if (rc == 0) 12542 setbit(&sc->active_ulds, id); 12543 } 12544 sx_sunlock(&t4_uld_list_lock); 12545 12546 return (rc); 12547 } 12548 12549 int 12550 t4_deactivate_uld(struct adapter *sc, int id) 12551 { 12552 int rc; 12553 12554 ASSERT_SYNCHRONIZED_OP(sc); 12555 12556 if (id < 0 || id > ULD_MAX) 12557 return (EINVAL); 12558 12559 sx_slock(&t4_uld_list_lock); 12560 if (t4_uld_list[id] == NULL) 12561 rc = ENXIO; 12562 else { 12563 rc = t4_uld_list[id]->uld_deactivate(sc); 12564 if (rc == 0) 12565 clrbit(&sc->active_ulds, id); 12566 } 12567 sx_sunlock(&t4_uld_list_lock); 12568 12569 return (rc); 12570 } 12571 12572 static int 12573 deactivate_all_uld(struct adapter *sc) 12574 { 12575 int i, rc; 12576 12577 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld"); 12578 if (rc != 0) 12579 return (ENXIO); 12580 sx_slock(&t4_uld_list_lock); 12581 for (i = 0; i <= ULD_MAX; i++) { 12582 if (t4_uld_list[i] == NULL || !uld_active(sc, i)) 12583 continue; 12584 rc = t4_uld_list[i]->uld_deactivate(sc); 12585 if (rc != 0) 12586 break; 12587 clrbit(&sc->active_ulds, i); 12588 } 12589 sx_sunlock(&t4_uld_list_lock); 12590 end_synchronized_op(sc, 0); 12591 12592 return (rc); 12593 } 12594 12595 static void 12596 stop_all_uld(struct adapter *sc) 12597 { 12598 int i; 12599 12600 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldst") != 0) 12601 return; 12602 sx_slock(&t4_uld_list_lock); 12603 for (i = 0; i <= ULD_MAX; i++) { 12604 if (t4_uld_list[i] == NULL || !uld_active(sc, i) || 12605 t4_uld_list[i]->uld_stop == NULL) 12606 continue; 12607 (void) t4_uld_list[i]->uld_stop(sc); 12608 } 12609 sx_sunlock(&t4_uld_list_lock); 12610 end_synchronized_op(sc, 0); 12611 } 12612 12613 static void 12614 restart_all_uld(struct adapter *sc) 12615 { 12616 int i; 12617 12618 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldre") != 0) 12619 return; 12620 sx_slock(&t4_uld_list_lock); 12621 for (i = 0; i <= ULD_MAX; i++) { 12622 if (t4_uld_list[i] == NULL || !uld_active(sc, i) || 12623 t4_uld_list[i]->uld_restart == NULL) 12624 continue; 12625 (void) t4_uld_list[i]->uld_restart(sc); 12626 } 12627 sx_sunlock(&t4_uld_list_lock); 12628 end_synchronized_op(sc, 0); 12629 } 12630 12631 int 12632 uld_active(struct adapter *sc, int id) 12633 { 12634 12635 MPASS(id >= 0 && id <= ULD_MAX); 12636 12637 return (isset(&sc->active_ulds, id)); 12638 } 12639 #endif 12640 12641 #ifdef KERN_TLS 12642 static int 12643 ktls_capability(struct adapter *sc, bool enable) 12644 { 12645 ASSERT_SYNCHRONIZED_OP(sc); 12646 12647 if (!is_ktls(sc)) 12648 return (ENODEV); 12649 if (!is_t6(sc)) 12650 return (0); 12651 if (hw_off_limits(sc)) 12652 return (ENXIO); 12653 12654 if (enable) { 12655 if (sc->flags & KERN_TLS_ON) 12656 return (0); /* already on */ 12657 if (sc->offload_map != 0) { 12658 CH_WARN(sc, 12659 "Disable TOE on all interfaces associated with " 12660 "this adapter before trying to enable NIC TLS.\n"); 12661 return (EAGAIN); 12662 } 12663 return (t6_config_kern_tls(sc, true)); 12664 } else { 12665 /* 12666 * Nothing to do for disable. If TOE is enabled sometime later 12667 * then toe_capability will reconfigure the hardware. 12668 */ 12669 return (0); 12670 } 12671 } 12672 #endif 12673 12674 /* 12675 * t = ptr to tunable. 12676 * nc = number of CPUs. 12677 * c = compiled in default for that tunable. 12678 */ 12679 static void 12680 calculate_nqueues(int *t, int nc, const int c) 12681 { 12682 int nq; 12683 12684 if (*t > 0) 12685 return; 12686 nq = *t < 0 ? -*t : c; 12687 *t = min(nc, nq); 12688 } 12689 12690 /* 12691 * Come up with reasonable defaults for some of the tunables, provided they're 12692 * not set by the user (in which case we'll use the values as is). 12693 */ 12694 static void 12695 tweak_tunables(void) 12696 { 12697 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 12698 12699 if (t4_ntxq < 1) { 12700 #ifdef RSS 12701 t4_ntxq = rss_getnumbuckets(); 12702 #else 12703 calculate_nqueues(&t4_ntxq, nc, NTXQ); 12704 #endif 12705 } 12706 12707 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 12708 12709 if (t4_nrxq < 1) { 12710 #ifdef RSS 12711 t4_nrxq = rss_getnumbuckets(); 12712 #else 12713 calculate_nqueues(&t4_nrxq, nc, NRXQ); 12714 #endif 12715 } 12716 12717 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 12718 12719 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12720 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 12721 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 12722 #endif 12723 #ifdef TCP_OFFLOAD 12724 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 12725 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 12726 #endif 12727 12728 #if defined(TCP_OFFLOAD) || defined(KERN_TLS) 12729 if (t4_toecaps_allowed == -1) 12730 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 12731 #else 12732 if (t4_toecaps_allowed == -1) 12733 t4_toecaps_allowed = 0; 12734 #endif 12735 12736 #ifdef TCP_OFFLOAD 12737 if (t4_rdmacaps_allowed == -1) { 12738 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 12739 FW_CAPS_CONFIG_RDMA_RDMAC; 12740 } 12741 12742 if (t4_iscsicaps_allowed == -1) { 12743 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 12744 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 12745 FW_CAPS_CONFIG_ISCSI_T10DIF; 12746 } 12747 12748 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 12749 t4_tmr_idx_ofld = TMR_IDX_OFLD; 12750 12751 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 12752 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 12753 #else 12754 if (t4_rdmacaps_allowed == -1) 12755 t4_rdmacaps_allowed = 0; 12756 12757 if (t4_iscsicaps_allowed == -1) 12758 t4_iscsicaps_allowed = 0; 12759 #endif 12760 12761 #ifdef DEV_NETMAP 12762 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ); 12763 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ); 12764 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 12765 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 12766 #endif 12767 12768 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 12769 t4_tmr_idx = TMR_IDX; 12770 12771 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 12772 t4_pktc_idx = PKTC_IDX; 12773 12774 if (t4_qsize_txq < 128) 12775 t4_qsize_txq = 128; 12776 12777 if (t4_qsize_rxq < 128) 12778 t4_qsize_rxq = 128; 12779 while (t4_qsize_rxq & 7) 12780 t4_qsize_rxq++; 12781 12782 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 12783 12784 /* 12785 * Number of VIs to create per-port. The first VI is the "main" regular 12786 * VI for the port. The rest are additional virtual interfaces on the 12787 * same physical port. Note that the main VI does not have native 12788 * netmap support but the extra VIs do. 12789 * 12790 * Limit the number of VIs per port to the number of available 12791 * MAC addresses per port. 12792 */ 12793 if (t4_num_vis < 1) 12794 t4_num_vis = 1; 12795 if (t4_num_vis > nitems(vi_mac_funcs)) { 12796 t4_num_vis = nitems(vi_mac_funcs); 12797 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 12798 } 12799 12800 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 12801 pcie_relaxed_ordering = 1; 12802 #if defined(__i386__) || defined(__amd64__) 12803 if (cpu_vendor_id == CPU_VENDOR_INTEL) 12804 pcie_relaxed_ordering = 0; 12805 #endif 12806 } 12807 } 12808 12809 #ifdef DDB 12810 static void 12811 t4_dump_mem(struct adapter *sc, u_int addr, u_int len) 12812 { 12813 uint32_t base, j, off, pf, reg, save, win_pos; 12814 12815 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 12816 save = t4_read_reg(sc, reg); 12817 base = sc->memwin[2].mw_base; 12818 12819 if (is_t4(sc)) { 12820 pf = 0; 12821 win_pos = addr & ~0xf; /* start must be 16B aligned */ 12822 } else { 12823 pf = V_PFNUM(sc->pf); 12824 win_pos = addr & ~0x7f; /* start must be 128B aligned */ 12825 } 12826 off = addr - win_pos; 12827 t4_write_reg(sc, reg, win_pos | pf); 12828 t4_read_reg(sc, reg); 12829 12830 while (len > 0 && !db_pager_quit) { 12831 uint32_t buf[8]; 12832 for (j = 0; j < 8; j++, off += 4) 12833 buf[j] = htonl(t4_read_reg(sc, base + off)); 12834 12835 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 12836 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 12837 buf[7]); 12838 if (len <= sizeof(buf)) 12839 len = 0; 12840 else 12841 len -= sizeof(buf); 12842 } 12843 12844 t4_write_reg(sc, reg, save); 12845 t4_read_reg(sc, reg); 12846 } 12847 12848 static void 12849 t4_dump_tcb(struct adapter *sc, int tid) 12850 { 12851 uint32_t tcb_addr; 12852 12853 /* Dump TCB for the tid */ 12854 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 12855 tcb_addr += tid * TCB_SIZE; 12856 t4_dump_mem(sc, tcb_addr, TCB_SIZE); 12857 } 12858 12859 static void 12860 t4_dump_devlog(struct adapter *sc) 12861 { 12862 struct devlog_params *dparams = &sc->params.devlog; 12863 struct fw_devlog_e e; 12864 int i, first, j, m, nentries, rc; 12865 uint64_t ftstamp = UINT64_MAX; 12866 12867 if (dparams->start == 0) { 12868 db_printf("devlog params not valid\n"); 12869 return; 12870 } 12871 12872 nentries = dparams->size / sizeof(struct fw_devlog_e); 12873 m = fwmtype_to_hwmtype(dparams->memtype); 12874 12875 /* Find the first entry. */ 12876 first = -1; 12877 for (i = 0; i < nentries && !db_pager_quit; i++) { 12878 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12879 sizeof(e), (void *)&e); 12880 if (rc != 0) 12881 break; 12882 12883 if (e.timestamp == 0) 12884 break; 12885 12886 e.timestamp = be64toh(e.timestamp); 12887 if (e.timestamp < ftstamp) { 12888 ftstamp = e.timestamp; 12889 first = i; 12890 } 12891 } 12892 12893 if (first == -1) 12894 return; 12895 12896 i = first; 12897 do { 12898 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12899 sizeof(e), (void *)&e); 12900 if (rc != 0) 12901 return; 12902 12903 if (e.timestamp == 0) 12904 return; 12905 12906 e.timestamp = be64toh(e.timestamp); 12907 e.seqno = be32toh(e.seqno); 12908 for (j = 0; j < 8; j++) 12909 e.params[j] = be32toh(e.params[j]); 12910 12911 db_printf("%10d %15ju %8s %8s ", 12912 e.seqno, e.timestamp, 12913 (e.level < nitems(devlog_level_strings) ? 12914 devlog_level_strings[e.level] : "UNKNOWN"), 12915 (e.facility < nitems(devlog_facility_strings) ? 12916 devlog_facility_strings[e.facility] : "UNKNOWN")); 12917 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 12918 e.params[3], e.params[4], e.params[5], e.params[6], 12919 e.params[7]); 12920 12921 if (++i == nentries) 12922 i = 0; 12923 } while (i != first && !db_pager_quit); 12924 } 12925 12926 static DB_DEFINE_TABLE(show, t4, show_t4); 12927 12928 DB_TABLE_COMMAND_FLAGS(show_t4, devlog, db_show_devlog, CS_OWN) 12929 { 12930 device_t dev; 12931 int t; 12932 bool valid; 12933 12934 valid = false; 12935 t = db_read_token(); 12936 if (t == tIDENT) { 12937 dev = device_lookup_by_name(db_tok_string); 12938 valid = true; 12939 } 12940 db_skip_to_eol(); 12941 if (!valid) { 12942 db_printf("usage: show t4 devlog <nexus>\n"); 12943 return; 12944 } 12945 12946 if (dev == NULL) { 12947 db_printf("device not found\n"); 12948 return; 12949 } 12950 12951 t4_dump_devlog(device_get_softc(dev)); 12952 } 12953 12954 DB_TABLE_COMMAND_FLAGS(show_t4, tcb, db_show_t4tcb, CS_OWN) 12955 { 12956 device_t dev; 12957 int radix, tid, t; 12958 bool valid; 12959 12960 valid = false; 12961 radix = db_radix; 12962 db_radix = 10; 12963 t = db_read_token(); 12964 if (t == tIDENT) { 12965 dev = device_lookup_by_name(db_tok_string); 12966 t = db_read_token(); 12967 if (t == tNUMBER) { 12968 tid = db_tok_number; 12969 valid = true; 12970 } 12971 } 12972 db_radix = radix; 12973 db_skip_to_eol(); 12974 if (!valid) { 12975 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 12976 return; 12977 } 12978 12979 if (dev == NULL) { 12980 db_printf("device not found\n"); 12981 return; 12982 } 12983 if (tid < 0) { 12984 db_printf("invalid tid\n"); 12985 return; 12986 } 12987 12988 t4_dump_tcb(device_get_softc(dev), tid); 12989 } 12990 12991 DB_TABLE_COMMAND_FLAGS(show_t4, memdump, db_show_memdump, CS_OWN) 12992 { 12993 device_t dev; 12994 int radix, t; 12995 bool valid; 12996 12997 valid = false; 12998 radix = db_radix; 12999 db_radix = 10; 13000 t = db_read_token(); 13001 if (t == tIDENT) { 13002 dev = device_lookup_by_name(db_tok_string); 13003 t = db_read_token(); 13004 if (t == tNUMBER) { 13005 addr = db_tok_number; 13006 t = db_read_token(); 13007 if (t == tNUMBER) { 13008 count = db_tok_number; 13009 valid = true; 13010 } 13011 } 13012 } 13013 db_radix = radix; 13014 db_skip_to_eol(); 13015 if (!valid) { 13016 db_printf("usage: show t4 memdump <nexus> <addr> <len>\n"); 13017 return; 13018 } 13019 13020 if (dev == NULL) { 13021 db_printf("device not found\n"); 13022 return; 13023 } 13024 if (addr < 0) { 13025 db_printf("invalid address\n"); 13026 return; 13027 } 13028 if (count <= 0) { 13029 db_printf("invalid length\n"); 13030 return; 13031 } 13032 13033 t4_dump_mem(device_get_softc(dev), addr, count); 13034 } 13035 #endif 13036 13037 static eventhandler_tag vxlan_start_evtag; 13038 static eventhandler_tag vxlan_stop_evtag; 13039 13040 struct vxlan_evargs { 13041 if_t ifp; 13042 uint16_t port; 13043 }; 13044 13045 static void 13046 enable_vxlan_rx(struct adapter *sc) 13047 { 13048 int i, rc; 13049 struct port_info *pi; 13050 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 13051 13052 ASSERT_SYNCHRONIZED_OP(sc); 13053 13054 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) | 13055 F_VXLAN_EN); 13056 for_each_port(sc, i) { 13057 pi = sc->port[i]; 13058 if (pi->vxlan_tcam_entry == true) 13059 continue; 13060 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac, 13061 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 13062 true); 13063 if (rc < 0) { 13064 rc = -rc; 13065 CH_ERR(&pi->vi[0], 13066 "failed to add VXLAN TCAM entry: %d.\n", rc); 13067 } else { 13068 MPASS(rc == sc->rawf_base + pi->port_id); 13069 pi->vxlan_tcam_entry = true; 13070 } 13071 } 13072 } 13073 13074 static void 13075 t4_vxlan_start(struct adapter *sc, void *arg) 13076 { 13077 struct vxlan_evargs *v = arg; 13078 13079 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13080 return; 13081 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0) 13082 return; 13083 13084 if (sc->vxlan_refcount == 0) { 13085 sc->vxlan_port = v->port; 13086 sc->vxlan_refcount = 1; 13087 if (!hw_off_limits(sc)) 13088 enable_vxlan_rx(sc); 13089 } else if (sc->vxlan_port == v->port) { 13090 sc->vxlan_refcount++; 13091 } else { 13092 CH_ERR(sc, "VXLAN already configured on port %d; " 13093 "ignoring attempt to configure it on port %d\n", 13094 sc->vxlan_port, v->port); 13095 } 13096 end_synchronized_op(sc, 0); 13097 } 13098 13099 static void 13100 t4_vxlan_stop(struct adapter *sc, void *arg) 13101 { 13102 struct vxlan_evargs *v = arg; 13103 13104 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13105 return; 13106 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0) 13107 return; 13108 13109 /* 13110 * VXLANs may have been configured before the driver was loaded so we 13111 * may see more stops than starts. This is not handled cleanly but at 13112 * least we keep the refcount sane. 13113 */ 13114 if (sc->vxlan_port != v->port) 13115 goto done; 13116 if (sc->vxlan_refcount == 0) { 13117 CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; " 13118 "ignoring attempt to stop it again.\n", sc->vxlan_port); 13119 } else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc)) 13120 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0); 13121 done: 13122 end_synchronized_op(sc, 0); 13123 } 13124 13125 static void 13126 t4_vxlan_start_handler(void *arg __unused, if_t ifp, 13127 sa_family_t family, u_int port) 13128 { 13129 struct vxlan_evargs v; 13130 13131 MPASS(family == AF_INET || family == AF_INET6); 13132 v.ifp = ifp; 13133 v.port = port; 13134 13135 t4_iterate(t4_vxlan_start, &v); 13136 } 13137 13138 static void 13139 t4_vxlan_stop_handler(void *arg __unused, if_t ifp, sa_family_t family, 13140 u_int port) 13141 { 13142 struct vxlan_evargs v; 13143 13144 MPASS(family == AF_INET || family == AF_INET6); 13145 v.ifp = ifp; 13146 v.port = port; 13147 13148 t4_iterate(t4_vxlan_stop, &v); 13149 } 13150 13151 13152 static struct sx mlu; /* mod load unload */ 13153 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 13154 13155 static int 13156 mod_event(module_t mod, int cmd, void *arg) 13157 { 13158 int rc = 0; 13159 static int loaded = 0; 13160 13161 switch (cmd) { 13162 case MOD_LOAD: 13163 sx_xlock(&mlu); 13164 if (loaded++ == 0) { 13165 t4_sge_modload(); 13166 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13167 t4_filter_rpl, CPL_COOKIE_FILTER); 13168 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 13169 do_l2t_write_rpl, CPL_COOKIE_FILTER); 13170 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 13171 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 13172 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13173 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 13174 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 13175 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 13176 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 13177 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 13178 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 13179 do_smt_write_rpl); 13180 sx_init(&t4_list_lock, "T4/T5 adapters"); 13181 SLIST_INIT(&t4_list); 13182 callout_init(&fatal_callout, 1); 13183 #ifdef TCP_OFFLOAD 13184 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 13185 #endif 13186 #ifdef INET6 13187 t4_clip_modload(); 13188 #endif 13189 #ifdef KERN_TLS 13190 t6_ktls_modload(); 13191 #endif 13192 t4_tracer_modload(); 13193 tweak_tunables(); 13194 vxlan_start_evtag = 13195 EVENTHANDLER_REGISTER(vxlan_start, 13196 t4_vxlan_start_handler, NULL, 13197 EVENTHANDLER_PRI_ANY); 13198 vxlan_stop_evtag = 13199 EVENTHANDLER_REGISTER(vxlan_stop, 13200 t4_vxlan_stop_handler, NULL, 13201 EVENTHANDLER_PRI_ANY); 13202 reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK, 13203 taskqueue_thread_enqueue, &reset_tq); 13204 taskqueue_start_threads(&reset_tq, 1, PI_SOFT, 13205 "t4_rst_thr"); 13206 } 13207 sx_xunlock(&mlu); 13208 break; 13209 13210 case MOD_UNLOAD: 13211 sx_xlock(&mlu); 13212 if (--loaded == 0) { 13213 #ifdef TCP_OFFLOAD 13214 int i; 13215 #endif 13216 int tries; 13217 13218 taskqueue_free(reset_tq); 13219 13220 tries = 0; 13221 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 13222 uprintf("%ju clusters with custom free routine " 13223 "still is use.\n", t4_sge_extfree_refs()); 13224 pause("t4unload", 2 * hz); 13225 } 13226 13227 sx_slock(&t4_list_lock); 13228 if (!SLIST_EMPTY(&t4_list)) { 13229 rc = EBUSY; 13230 sx_sunlock(&t4_list_lock); 13231 goto done_unload; 13232 } 13233 #ifdef TCP_OFFLOAD 13234 sx_slock(&t4_uld_list_lock); 13235 for (i = 0; i <= ULD_MAX; i++) { 13236 if (t4_uld_list[i] != NULL) { 13237 rc = EBUSY; 13238 sx_sunlock(&t4_uld_list_lock); 13239 sx_sunlock(&t4_list_lock); 13240 goto done_unload; 13241 } 13242 } 13243 sx_sunlock(&t4_uld_list_lock); 13244 #endif 13245 sx_sunlock(&t4_list_lock); 13246 13247 if (t4_sge_extfree_refs() == 0) { 13248 EVENTHANDLER_DEREGISTER(vxlan_start, 13249 vxlan_start_evtag); 13250 EVENTHANDLER_DEREGISTER(vxlan_stop, 13251 vxlan_stop_evtag); 13252 t4_tracer_modunload(); 13253 #ifdef KERN_TLS 13254 t6_ktls_modunload(); 13255 #endif 13256 #ifdef INET6 13257 t4_clip_modunload(); 13258 #endif 13259 #ifdef TCP_OFFLOAD 13260 sx_destroy(&t4_uld_list_lock); 13261 #endif 13262 sx_destroy(&t4_list_lock); 13263 t4_sge_modunload(); 13264 loaded = 0; 13265 } else { 13266 rc = EBUSY; 13267 loaded++; /* undo earlier decrement */ 13268 } 13269 } 13270 done_unload: 13271 sx_xunlock(&mlu); 13272 break; 13273 } 13274 13275 return (rc); 13276 } 13277 13278 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0); 13279 MODULE_VERSION(t4nex, 1); 13280 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 13281 #ifdef DEV_NETMAP 13282 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 13283 #endif /* DEV_NETMAP */ 13284 13285 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0); 13286 MODULE_VERSION(t5nex, 1); 13287 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 13288 #ifdef DEV_NETMAP 13289 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 13290 #endif /* DEV_NETMAP */ 13291 13292 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0); 13293 MODULE_VERSION(t6nex, 1); 13294 MODULE_DEPEND(t6nex, crypto, 1, 1, 1); 13295 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 13296 #ifdef DEV_NETMAP 13297 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 13298 #endif /* DEV_NETMAP */ 13299 13300 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0); 13301 MODULE_VERSION(cxgbe, 1); 13302 13303 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0); 13304 MODULE_VERSION(cxl, 1); 13305 13306 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0); 13307 MODULE_VERSION(cc, 1); 13308 13309 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0); 13310 MODULE_VERSION(vcxgbe, 1); 13311 13312 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0); 13313 MODULE_VERSION(vcxl, 1); 13314 13315 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0); 13316 MODULE_VERSION(vcc, 1); 13317