1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_rss.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/priv.h> 41 #include <sys/kernel.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/queue.h> 46 #include <sys/taskqueue.h> 47 #include <sys/pciio.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pci_private.h> 51 #include <sys/firmware.h> 52 #include <sys/sbuf.h> 53 #include <sys/smp.h> 54 #include <sys/socket.h> 55 #include <sys/sockio.h> 56 #include <sys/sysctl.h> 57 #include <net/ethernet.h> 58 #include <net/if.h> 59 #include <net/if_types.h> 60 #include <net/if_dl.h> 61 #include <net/if_vlan_var.h> 62 #ifdef RSS 63 #include <net/rss_config.h> 64 #endif 65 #if defined(__i386__) || defined(__amd64__) 66 #include <machine/md_var.h> 67 #include <machine/cputypes.h> 68 #include <vm/vm.h> 69 #include <vm/pmap.h> 70 #endif 71 #include <crypto/rijndael/rijndael.h> 72 #ifdef DDB 73 #include <ddb/ddb.h> 74 #include <ddb/db_lex.h> 75 #endif 76 77 #include "common/common.h" 78 #include "common/t4_msg.h" 79 #include "common/t4_regs.h" 80 #include "common/t4_regs_values.h" 81 #include "cudbg/cudbg.h" 82 #include "t4_ioctl.h" 83 #include "t4_l2t.h" 84 #include "t4_mp_ring.h" 85 #include "t4_if.h" 86 87 /* T4 bus driver interface */ 88 static int t4_probe(device_t); 89 static int t4_attach(device_t); 90 static int t4_detach(device_t); 91 static int t4_ready(device_t); 92 static int t4_read_port_device(device_t, int, device_t *); 93 static device_method_t t4_methods[] = { 94 DEVMETHOD(device_probe, t4_probe), 95 DEVMETHOD(device_attach, t4_attach), 96 DEVMETHOD(device_detach, t4_detach), 97 98 DEVMETHOD(t4_is_main_ready, t4_ready), 99 DEVMETHOD(t4_read_port_device, t4_read_port_device), 100 101 DEVMETHOD_END 102 }; 103 static driver_t t4_driver = { 104 "t4nex", 105 t4_methods, 106 sizeof(struct adapter) 107 }; 108 109 110 /* T4 port (cxgbe) interface */ 111 static int cxgbe_probe(device_t); 112 static int cxgbe_attach(device_t); 113 static int cxgbe_detach(device_t); 114 device_method_t cxgbe_methods[] = { 115 DEVMETHOD(device_probe, cxgbe_probe), 116 DEVMETHOD(device_attach, cxgbe_attach), 117 DEVMETHOD(device_detach, cxgbe_detach), 118 { 0, 0 } 119 }; 120 static driver_t cxgbe_driver = { 121 "cxgbe", 122 cxgbe_methods, 123 sizeof(struct port_info) 124 }; 125 126 /* T4 VI (vcxgbe) interface */ 127 static int vcxgbe_probe(device_t); 128 static int vcxgbe_attach(device_t); 129 static int vcxgbe_detach(device_t); 130 static device_method_t vcxgbe_methods[] = { 131 DEVMETHOD(device_probe, vcxgbe_probe), 132 DEVMETHOD(device_attach, vcxgbe_attach), 133 DEVMETHOD(device_detach, vcxgbe_detach), 134 { 0, 0 } 135 }; 136 static driver_t vcxgbe_driver = { 137 "vcxgbe", 138 vcxgbe_methods, 139 sizeof(struct vi_info) 140 }; 141 142 static d_ioctl_t t4_ioctl; 143 144 static struct cdevsw t4_cdevsw = { 145 .d_version = D_VERSION, 146 .d_ioctl = t4_ioctl, 147 .d_name = "t4nex", 148 }; 149 150 /* T5 bus driver interface */ 151 static int t5_probe(device_t); 152 static device_method_t t5_methods[] = { 153 DEVMETHOD(device_probe, t5_probe), 154 DEVMETHOD(device_attach, t4_attach), 155 DEVMETHOD(device_detach, t4_detach), 156 157 DEVMETHOD(t4_is_main_ready, t4_ready), 158 DEVMETHOD(t4_read_port_device, t4_read_port_device), 159 160 DEVMETHOD_END 161 }; 162 static driver_t t5_driver = { 163 "t5nex", 164 t5_methods, 165 sizeof(struct adapter) 166 }; 167 168 169 /* T5 port (cxl) interface */ 170 static driver_t cxl_driver = { 171 "cxl", 172 cxgbe_methods, 173 sizeof(struct port_info) 174 }; 175 176 /* T5 VI (vcxl) interface */ 177 static driver_t vcxl_driver = { 178 "vcxl", 179 vcxgbe_methods, 180 sizeof(struct vi_info) 181 }; 182 183 /* T6 bus driver interface */ 184 static int t6_probe(device_t); 185 static device_method_t t6_methods[] = { 186 DEVMETHOD(device_probe, t6_probe), 187 DEVMETHOD(device_attach, t4_attach), 188 DEVMETHOD(device_detach, t4_detach), 189 190 DEVMETHOD(t4_is_main_ready, t4_ready), 191 DEVMETHOD(t4_read_port_device, t4_read_port_device), 192 193 DEVMETHOD_END 194 }; 195 static driver_t t6_driver = { 196 "t6nex", 197 t6_methods, 198 sizeof(struct adapter) 199 }; 200 201 202 /* T6 port (cc) interface */ 203 static driver_t cc_driver = { 204 "cc", 205 cxgbe_methods, 206 sizeof(struct port_info) 207 }; 208 209 /* T6 VI (vcc) interface */ 210 static driver_t vcc_driver = { 211 "vcc", 212 vcxgbe_methods, 213 sizeof(struct vi_info) 214 }; 215 216 /* ifnet + media interface */ 217 static void cxgbe_init(void *); 218 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 219 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 220 static void cxgbe_qflush(struct ifnet *); 221 static int cxgbe_media_change(struct ifnet *); 222 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 223 224 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 225 226 /* 227 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 228 * then ADAPTER_LOCK, then t4_uld_list_lock. 229 */ 230 static struct sx t4_list_lock; 231 SLIST_HEAD(, adapter) t4_list; 232 #ifdef TCP_OFFLOAD 233 static struct sx t4_uld_list_lock; 234 SLIST_HEAD(, uld_info) t4_uld_list; 235 #endif 236 237 /* 238 * Tunables. See tweak_tunables() too. 239 * 240 * Each tunable is set to a default value here if it's known at compile-time. 241 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 242 * provide a reasonable default (upto n) when the driver is loaded. 243 * 244 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 245 * T5 are under hw.cxl. 246 */ 247 248 /* 249 * Number of queues for tx and rx, NIC and offload. 250 */ 251 #define NTXQ 16 252 int t4_ntxq = -NTXQ; 253 TUNABLE_INT("hw.cxgbe.ntxq", &t4_ntxq); 254 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 255 256 #define NRXQ 8 257 int t4_nrxq = -NRXQ; 258 TUNABLE_INT("hw.cxgbe.nrxq", &t4_nrxq); 259 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 260 261 #define NTXQ_VI 1 262 static int t4_ntxq_vi = -NTXQ_VI; 263 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi); 264 265 #define NRXQ_VI 1 266 static int t4_nrxq_vi = -NRXQ_VI; 267 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi); 268 269 static int t4_rsrv_noflowq = 0; 270 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq); 271 272 #ifdef TCP_OFFLOAD 273 #define NOFLDTXQ 8 274 static int t4_nofldtxq = -NOFLDTXQ; 275 TUNABLE_INT("hw.cxgbe.nofldtxq", &t4_nofldtxq); 276 277 #define NOFLDRXQ 2 278 static int t4_nofldrxq = -NOFLDRXQ; 279 TUNABLE_INT("hw.cxgbe.nofldrxq", &t4_nofldrxq); 280 281 #define NOFLDTXQ_VI 1 282 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 283 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi); 284 285 #define NOFLDRXQ_VI 1 286 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 287 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi); 288 289 #define TMR_IDX_OFLD 1 290 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 291 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_ofld", &t4_tmr_idx_ofld); 292 293 #define PKTC_IDX_OFLD (-1) 294 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 295 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_ofld", &t4_pktc_idx_ofld); 296 297 /* 0 means chip/fw default, non-zero number is value in microseconds */ 298 static u_long t4_toe_keepalive_idle = 0; 299 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_idle", &t4_toe_keepalive_idle); 300 301 /* 0 means chip/fw default, non-zero number is value in microseconds */ 302 static u_long t4_toe_keepalive_interval = 0; 303 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_interval", &t4_toe_keepalive_interval); 304 305 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 306 static int t4_toe_keepalive_count = 0; 307 TUNABLE_INT("hw.cxgbe.toe.keepalive_count", &t4_toe_keepalive_count); 308 309 /* 0 means chip/fw default, non-zero number is value in microseconds */ 310 static u_long t4_toe_rexmt_min = 0; 311 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_min", &t4_toe_rexmt_min); 312 313 /* 0 means chip/fw default, non-zero number is value in microseconds */ 314 static u_long t4_toe_rexmt_max = 0; 315 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_max", &t4_toe_rexmt_max); 316 317 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 318 static int t4_toe_rexmt_count = 0; 319 TUNABLE_INT("hw.cxgbe.toe.rexmt_count", &t4_toe_rexmt_count); 320 321 /* -1 means chip/fw default, other values are raw backoff values to use */ 322 static int t4_toe_rexmt_backoff[16] = { 323 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 324 }; 325 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.0", &t4_toe_rexmt_backoff[0]); 326 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.1", &t4_toe_rexmt_backoff[1]); 327 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.2", &t4_toe_rexmt_backoff[2]); 328 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.3", &t4_toe_rexmt_backoff[3]); 329 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.4", &t4_toe_rexmt_backoff[4]); 330 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.5", &t4_toe_rexmt_backoff[5]); 331 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.6", &t4_toe_rexmt_backoff[6]); 332 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.7", &t4_toe_rexmt_backoff[7]); 333 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.8", &t4_toe_rexmt_backoff[8]); 334 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.9", &t4_toe_rexmt_backoff[9]); 335 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.10", &t4_toe_rexmt_backoff[10]); 336 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.11", &t4_toe_rexmt_backoff[11]); 337 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.12", &t4_toe_rexmt_backoff[12]); 338 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.13", &t4_toe_rexmt_backoff[13]); 339 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.14", &t4_toe_rexmt_backoff[14]); 340 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.15", &t4_toe_rexmt_backoff[15]); 341 #endif 342 343 #ifdef DEV_NETMAP 344 #define NNMTXQ_VI 2 345 static int t4_nnmtxq_vi = -NNMTXQ_VI; 346 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi); 347 348 #define NNMRXQ_VI 2 349 static int t4_nnmrxq_vi = -NNMRXQ_VI; 350 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi); 351 #endif 352 353 /* 354 * Holdoff parameters for ports. 355 */ 356 #define TMR_IDX 1 357 int t4_tmr_idx = TMR_IDX; 358 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx", &t4_tmr_idx); 359 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 360 361 #define PKTC_IDX (-1) 362 int t4_pktc_idx = PKTC_IDX; 363 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx", &t4_pktc_idx); 364 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 365 366 /* 367 * Size (# of entries) of each tx and rx queue. 368 */ 369 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 370 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 371 372 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 373 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 374 375 /* 376 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 377 */ 378 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 379 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 380 381 /* 382 * Configuration file. 383 */ 384 #define DEFAULT_CF "default" 385 #define FLASH_CF "flash" 386 #define UWIRE_CF "uwire" 387 #define FPGA_CF "fpga" 388 static char t4_cfg_file[32] = DEFAULT_CF; 389 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 390 391 /* 392 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively). 393 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 394 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 395 * mark or when signalled to do so, 0 to never emit PAUSE. 396 */ 397 static int t4_pause_settings = PAUSE_TX | PAUSE_RX; 398 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings); 399 400 /* 401 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS, 402 * FEC_RESERVED respectively). 403 * -1 to run with the firmware default. 404 * 0 to disable FEC. 405 */ 406 static int t4_fec = -1; 407 TUNABLE_INT("hw.cxgbe.fec", &t4_fec); 408 409 /* 410 * Link autonegotiation. 411 * -1 to run with the firmware default. 412 * 0 to disable. 413 * 1 to enable. 414 */ 415 static int t4_autoneg = -1; 416 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg); 417 418 /* 419 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 420 * encouraged respectively). 421 */ 422 static unsigned int t4_fw_install = 1; 423 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 424 425 /* 426 * ASIC features that will be used. Disable the ones you don't want so that the 427 * chip resources aren't wasted on features that will not be used. 428 */ 429 static int t4_nbmcaps_allowed = 0; 430 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed); 431 432 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 433 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 434 435 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 436 FW_CAPS_CONFIG_SWITCH_EGRESS; 437 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed); 438 439 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC; 440 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 441 442 static int t4_toecaps_allowed = -1; 443 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 444 445 static int t4_rdmacaps_allowed = -1; 446 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 447 448 static int t4_cryptocaps_allowed = -1; 449 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed); 450 451 static int t4_iscsicaps_allowed = -1; 452 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 453 454 static int t4_fcoecaps_allowed = 0; 455 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 456 457 static int t5_write_combine = 1; 458 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 459 460 static int t4_num_vis = 1; 461 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis); 462 /* 463 * PCIe Relaxed Ordering. 464 * -1: driver should figure out a good value. 465 * 0: disable RO. 466 * 1: enable RO. 467 * 2: leave RO alone. 468 */ 469 static int pcie_relaxed_ordering = -1; 470 TUNABLE_INT("hw.cxgbe.pcie_relaxed_ordering", &pcie_relaxed_ordering); 471 472 473 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 474 static int vi_mac_funcs[] = { 475 FW_VI_FUNC_ETH, 476 FW_VI_FUNC_OFLD, 477 FW_VI_FUNC_IWARP, 478 FW_VI_FUNC_OPENISCSI, 479 FW_VI_FUNC_OPENFCOE, 480 FW_VI_FUNC_FOISCSI, 481 FW_VI_FUNC_FOFCOE, 482 }; 483 484 struct intrs_and_queues { 485 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 486 uint16_t num_vis; /* number of VIs for each port */ 487 uint16_t nirq; /* Total # of vectors */ 488 uint16_t ntxq; /* # of NIC txq's for each port */ 489 uint16_t nrxq; /* # of NIC rxq's for each port */ 490 uint16_t nofldtxq; /* # of TOE txq's for each port */ 491 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 492 493 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 494 uint16_t ntxq_vi; /* # of NIC txq's */ 495 uint16_t nrxq_vi; /* # of NIC rxq's */ 496 uint16_t nofldtxq_vi; /* # of TOE txq's */ 497 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 498 uint16_t nnmtxq_vi; /* # of netmap txq's */ 499 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 500 }; 501 502 struct filter_entry { 503 uint32_t valid:1; /* filter allocated and valid */ 504 uint32_t locked:1; /* filter is administratively locked */ 505 uint32_t pending:1; /* filter action is pending firmware reply */ 506 uint32_t smtidx:8; /* Source MAC Table index for smac */ 507 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 508 509 struct t4_filter_specification fs; 510 }; 511 512 static void setup_memwin(struct adapter *); 513 static void position_memwin(struct adapter *, int, uint32_t); 514 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 515 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *, 516 int); 517 static inline int write_via_memwin(struct adapter *, int, uint32_t, 518 const uint32_t *, int); 519 static int validate_mem_range(struct adapter *, uint32_t, int); 520 static int fwmtype_to_hwmtype(int); 521 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 522 uint32_t *); 523 static int fixup_devlog_params(struct adapter *); 524 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 525 static int prep_firmware(struct adapter *); 526 static int partition_resources(struct adapter *, const struct firmware *, 527 const char *); 528 static int get_params__pre_init(struct adapter *); 529 static int get_params__post_init(struct adapter *); 530 static int set_params__post_init(struct adapter *); 531 static void t4_set_desc(struct adapter *); 532 static void build_medialist(struct port_info *, struct ifmedia *); 533 static void init_l1cfg(struct port_info *); 534 static int cxgbe_init_synchronized(struct vi_info *); 535 static int cxgbe_uninit_synchronized(struct vi_info *); 536 static void quiesce_txq(struct adapter *, struct sge_txq *); 537 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 538 static void quiesce_iq(struct adapter *, struct sge_iq *); 539 static void quiesce_fl(struct adapter *, struct sge_fl *); 540 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 541 driver_intr_t *, void *, char *); 542 static int t4_free_irq(struct adapter *, struct irq *); 543 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 544 static void vi_refresh_stats(struct adapter *, struct vi_info *); 545 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 546 static void cxgbe_tick(void *); 547 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 548 static void cxgbe_sysctls(struct port_info *); 549 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 550 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 551 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 552 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 553 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 554 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 555 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 556 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 557 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 558 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 559 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 560 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 561 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 562 #ifdef SBUF_DRAIN 563 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 564 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 565 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 566 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 567 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 568 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 569 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 570 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 571 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 572 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 573 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 574 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 575 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 576 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 577 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 578 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 579 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 580 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 581 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 582 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 583 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 584 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 585 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 586 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 587 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 588 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 589 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 590 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 591 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 592 #endif 593 #ifdef TCP_OFFLOAD 594 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 595 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 596 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 597 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 598 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 599 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 600 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 601 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 602 #endif 603 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t); 604 static uint32_t mode_to_fconf(uint32_t); 605 static uint32_t mode_to_iconf(uint32_t); 606 static int check_fspec_against_fconf_iconf(struct adapter *, 607 struct t4_filter_specification *); 608 static int get_filter_mode(struct adapter *, uint32_t *); 609 static int set_filter_mode(struct adapter *, uint32_t); 610 static inline uint64_t get_filter_hits(struct adapter *, uint32_t); 611 static int get_filter(struct adapter *, struct t4_filter *); 612 static int set_filter(struct adapter *, struct t4_filter *); 613 static int del_filter(struct adapter *, struct t4_filter *); 614 static void clear_filter(struct filter_entry *); 615 static int set_filter_wr(struct adapter *, int); 616 static int del_filter_wr(struct adapter *, int); 617 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *, 618 struct mbuf *); 619 static int get_sge_context(struct adapter *, struct t4_sge_context *); 620 static int load_fw(struct adapter *, struct t4_data *); 621 static int load_cfg(struct adapter *, struct t4_data *); 622 static int load_boot(struct adapter *, struct t4_bootrom *); 623 static int load_bootcfg(struct adapter *, struct t4_data *); 624 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 625 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 626 static int read_i2c(struct adapter *, struct t4_i2c_data *); 627 #ifdef TCP_OFFLOAD 628 static int toe_capability(struct vi_info *, int); 629 #endif 630 static int mod_event(module_t, int, void *); 631 static int notify_siblings(device_t, int); 632 633 struct { 634 uint16_t device; 635 char *desc; 636 } t4_pciids[] = { 637 {0xa000, "Chelsio Terminator 4 FPGA"}, 638 {0x4400, "Chelsio T440-dbg"}, 639 {0x4401, "Chelsio T420-CR"}, 640 {0x4402, "Chelsio T422-CR"}, 641 {0x4403, "Chelsio T440-CR"}, 642 {0x4404, "Chelsio T420-BCH"}, 643 {0x4405, "Chelsio T440-BCH"}, 644 {0x4406, "Chelsio T440-CH"}, 645 {0x4407, "Chelsio T420-SO"}, 646 {0x4408, "Chelsio T420-CX"}, 647 {0x4409, "Chelsio T420-BT"}, 648 {0x440a, "Chelsio T404-BT"}, 649 {0x440e, "Chelsio T440-LP-CR"}, 650 }, t5_pciids[] = { 651 {0xb000, "Chelsio Terminator 5 FPGA"}, 652 {0x5400, "Chelsio T580-dbg"}, 653 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 654 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 655 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 656 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 657 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 658 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 659 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 660 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 661 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 662 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 663 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 664 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 665 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 666 #ifdef notyet 667 {0x5404, "Chelsio T520-BCH"}, 668 {0x5405, "Chelsio T540-BCH"}, 669 {0x5406, "Chelsio T540-CH"}, 670 {0x5408, "Chelsio T520-CX"}, 671 {0x540b, "Chelsio B520-SR"}, 672 {0x540c, "Chelsio B504-BT"}, 673 {0x540f, "Chelsio Amsterdam"}, 674 {0x5413, "Chelsio T580-CHR"}, 675 #endif 676 }, t6_pciids[] = { 677 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 678 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 679 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 680 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 681 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 682 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 683 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 684 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 685 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 686 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 687 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 688 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 689 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 690 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 691 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 692 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 693 694 /* Custom */ 695 {0x6480, "Chelsio T6225 80"}, 696 {0x6481, "Chelsio T62100 81"}, 697 {0x6484, "Chelsio T62100 84"}, 698 }; 699 700 #ifdef TCP_OFFLOAD 701 /* 702 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 703 * exactly the same for both rxq and ofld_rxq. 704 */ 705 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 706 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 707 #endif 708 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 709 710 static int 711 t4_probe(device_t dev) 712 { 713 int i; 714 uint16_t v = pci_get_vendor(dev); 715 uint16_t d = pci_get_device(dev); 716 uint8_t f = pci_get_function(dev); 717 718 if (v != PCI_VENDOR_ID_CHELSIO) 719 return (ENXIO); 720 721 /* Attach only to PF0 of the FPGA */ 722 if (d == 0xa000 && f != 0) 723 return (ENXIO); 724 725 for (i = 0; i < nitems(t4_pciids); i++) { 726 if (d == t4_pciids[i].device) { 727 device_set_desc(dev, t4_pciids[i].desc); 728 return (BUS_PROBE_DEFAULT); 729 } 730 } 731 732 return (ENXIO); 733 } 734 735 static int 736 t5_probe(device_t dev) 737 { 738 int i; 739 uint16_t v = pci_get_vendor(dev); 740 uint16_t d = pci_get_device(dev); 741 uint8_t f = pci_get_function(dev); 742 743 if (v != PCI_VENDOR_ID_CHELSIO) 744 return (ENXIO); 745 746 /* Attach only to PF0 of the FPGA */ 747 if (d == 0xb000 && f != 0) 748 return (ENXIO); 749 750 for (i = 0; i < nitems(t5_pciids); i++) { 751 if (d == t5_pciids[i].device) { 752 device_set_desc(dev, t5_pciids[i].desc); 753 return (BUS_PROBE_DEFAULT); 754 } 755 } 756 757 return (ENXIO); 758 } 759 760 static int 761 t6_probe(device_t dev) 762 { 763 int i; 764 uint16_t v = pci_get_vendor(dev); 765 uint16_t d = pci_get_device(dev); 766 767 if (v != PCI_VENDOR_ID_CHELSIO) 768 return (ENXIO); 769 770 for (i = 0; i < nitems(t6_pciids); i++) { 771 if (d == t6_pciids[i].device) { 772 device_set_desc(dev, t6_pciids[i].desc); 773 return (BUS_PROBE_DEFAULT); 774 } 775 } 776 777 return (ENXIO); 778 } 779 780 static void 781 t5_attribute_workaround(device_t dev) 782 { 783 device_t root_port; 784 uint32_t v; 785 786 /* 787 * The T5 chips do not properly echo the No Snoop and Relaxed 788 * Ordering attributes when replying to a TLP from a Root 789 * Port. As a workaround, find the parent Root Port and 790 * disable No Snoop and Relaxed Ordering. Note that this 791 * affects all devices under this root port. 792 */ 793 root_port = pci_find_pcie_root_port(dev); 794 if (root_port == NULL) { 795 device_printf(dev, "Unable to find parent root port\n"); 796 return; 797 } 798 799 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 800 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 801 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 802 0) 803 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 804 device_get_nameunit(root_port)); 805 } 806 807 static const struct devnames devnames[] = { 808 { 809 .nexus_name = "t4nex", 810 .ifnet_name = "cxgbe", 811 .vi_ifnet_name = "vcxgbe", 812 .pf03_drv_name = "t4iov", 813 .vf_nexus_name = "t4vf", 814 .vf_ifnet_name = "cxgbev" 815 }, { 816 .nexus_name = "t5nex", 817 .ifnet_name = "cxl", 818 .vi_ifnet_name = "vcxl", 819 .pf03_drv_name = "t5iov", 820 .vf_nexus_name = "t5vf", 821 .vf_ifnet_name = "cxlv" 822 }, { 823 .nexus_name = "t6nex", 824 .ifnet_name = "cc", 825 .vi_ifnet_name = "vcc", 826 .pf03_drv_name = "t6iov", 827 .vf_nexus_name = "t6vf", 828 .vf_ifnet_name = "ccv" 829 } 830 }; 831 832 void 833 t4_init_devnames(struct adapter *sc) 834 { 835 int id; 836 837 id = chip_id(sc); 838 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 839 sc->names = &devnames[id - CHELSIO_T4]; 840 else { 841 device_printf(sc->dev, "chip id %d is not supported.\n", id); 842 sc->names = NULL; 843 } 844 } 845 846 static int 847 t4_attach(device_t dev) 848 { 849 struct adapter *sc; 850 int rc = 0, i, j, rqidx, tqidx, nports; 851 struct make_dev_args mda; 852 struct intrs_and_queues iaq; 853 struct sge *s; 854 uint32_t *buf; 855 #ifdef TCP_OFFLOAD 856 int ofld_rqidx, ofld_tqidx; 857 #endif 858 #ifdef DEV_NETMAP 859 int nm_rqidx, nm_tqidx; 860 #endif 861 int num_vis; 862 863 sc = device_get_softc(dev); 864 sc->dev = dev; 865 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 866 867 if ((pci_get_device(dev) & 0xff00) == 0x5400) 868 t5_attribute_workaround(dev); 869 pci_enable_busmaster(dev); 870 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 871 uint32_t v; 872 873 pci_set_max_read_req(dev, 4096); 874 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 875 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 876 if (pcie_relaxed_ordering == 0 && 877 (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 878 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 879 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 880 } else if (pcie_relaxed_ordering == 1 && 881 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 882 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 883 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 884 } 885 } 886 887 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 888 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 889 sc->traceq = -1; 890 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 891 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 892 device_get_nameunit(dev)); 893 894 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 895 device_get_nameunit(dev)); 896 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 897 t4_add_adapter(sc); 898 899 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 900 TAILQ_INIT(&sc->sfl); 901 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 902 903 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 904 905 rc = t4_map_bars_0_and_4(sc); 906 if (rc != 0) 907 goto done; /* error message displayed already */ 908 909 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 910 911 /* Prepare the adapter for operation. */ 912 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 913 rc = -t4_prep_adapter(sc, buf); 914 free(buf, M_CXGBE); 915 if (rc != 0) { 916 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 917 goto done; 918 } 919 920 /* 921 * This is the real PF# to which we're attaching. Works from within PCI 922 * passthrough environments too, where pci_get_function() could return a 923 * different PF# depending on the passthrough configuration. We need to 924 * use the real PF# in all our communication with the firmware. 925 */ 926 j = t4_read_reg(sc, A_PL_WHOAMI); 927 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 928 sc->mbox = sc->pf; 929 930 t4_init_devnames(sc); 931 if (sc->names == NULL) { 932 rc = ENOTSUP; 933 goto done; /* error message displayed already */ 934 } 935 936 /* 937 * Do this really early, with the memory windows set up even before the 938 * character device. The userland tool's register i/o and mem read 939 * will work even in "recovery mode". 940 */ 941 setup_memwin(sc); 942 if (t4_init_devlog_params(sc, 0) == 0) 943 fixup_devlog_params(sc); 944 make_dev_args_init(&mda); 945 mda.mda_devsw = &t4_cdevsw; 946 mda.mda_uid = UID_ROOT; 947 mda.mda_gid = GID_WHEEL; 948 mda.mda_mode = 0600; 949 mda.mda_si_drv1 = sc; 950 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 951 if (rc != 0) 952 device_printf(dev, "failed to create nexus char device: %d.\n", 953 rc); 954 955 /* Go no further if recovery mode has been requested. */ 956 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 957 device_printf(dev, "recovery mode.\n"); 958 goto done; 959 } 960 961 #if defined(__i386__) 962 if ((cpu_feature & CPUID_CX8) == 0) { 963 device_printf(dev, "64 bit atomics not available.\n"); 964 rc = ENOTSUP; 965 goto done; 966 } 967 #endif 968 969 /* Prepare the firmware for operation */ 970 rc = prep_firmware(sc); 971 if (rc != 0) 972 goto done; /* error message displayed already */ 973 974 rc = get_params__post_init(sc); 975 if (rc != 0) 976 goto done; /* error message displayed already */ 977 978 rc = set_params__post_init(sc); 979 if (rc != 0) 980 goto done; /* error message displayed already */ 981 982 rc = t4_map_bar_2(sc); 983 if (rc != 0) 984 goto done; /* error message displayed already */ 985 986 rc = t4_create_dma_tag(sc); 987 if (rc != 0) 988 goto done; /* error message displayed already */ 989 990 /* 991 * First pass over all the ports - allocate VIs and initialize some 992 * basic parameters like mac address, port type, etc. 993 */ 994 for_each_port(sc, i) { 995 struct port_info *pi; 996 997 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 998 sc->port[i] = pi; 999 1000 /* These must be set before t4_port_init */ 1001 pi->adapter = sc; 1002 pi->port_id = i; 1003 /* 1004 * XXX: vi[0] is special so we can't delay this allocation until 1005 * pi->nvi's final value is known. 1006 */ 1007 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1008 M_ZERO | M_WAITOK); 1009 1010 /* 1011 * Allocate the "main" VI and initialize parameters 1012 * like mac addr. 1013 */ 1014 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1015 if (rc != 0) { 1016 device_printf(dev, "unable to initialize port %d: %d\n", 1017 i, rc); 1018 free(pi->vi, M_CXGBE); 1019 free(pi, M_CXGBE); 1020 sc->port[i] = NULL; 1021 goto done; 1022 } 1023 1024 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1025 device_get_nameunit(dev), i); 1026 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1027 sc->chan_map[pi->tx_chan] = i; 1028 1029 /* All VIs on this port share this media. */ 1030 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1031 cxgbe_media_status); 1032 1033 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1); 1034 if (pi->dev == NULL) { 1035 device_printf(dev, 1036 "failed to add device for port %d.\n", i); 1037 rc = ENXIO; 1038 goto done; 1039 } 1040 pi->vi[0].dev = pi->dev; 1041 device_set_softc(pi->dev, pi); 1042 } 1043 1044 /* 1045 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1046 */ 1047 nports = sc->params.nports; 1048 rc = cfg_itype_and_nqueues(sc, &iaq); 1049 if (rc != 0) 1050 goto done; /* error message displayed already */ 1051 1052 num_vis = iaq.num_vis; 1053 sc->intr_type = iaq.intr_type; 1054 sc->intr_count = iaq.nirq; 1055 1056 s = &sc->sge; 1057 s->nrxq = nports * iaq.nrxq; 1058 s->ntxq = nports * iaq.ntxq; 1059 if (num_vis > 1) { 1060 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1061 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1062 } 1063 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1064 s->neq += nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 1065 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1066 #ifdef TCP_OFFLOAD 1067 if (is_offload(sc)) { 1068 s->nofldrxq = nports * iaq.nofldrxq; 1069 s->nofldtxq = nports * iaq.nofldtxq; 1070 if (num_vis > 1) { 1071 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1072 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1073 } 1074 s->neq += s->nofldtxq + s->nofldrxq; 1075 s->niq += s->nofldrxq; 1076 1077 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1078 M_CXGBE, M_ZERO | M_WAITOK); 1079 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1080 M_CXGBE, M_ZERO | M_WAITOK); 1081 } 1082 #endif 1083 #ifdef DEV_NETMAP 1084 if (num_vis > 1) { 1085 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1086 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1087 } 1088 s->neq += s->nnmtxq + s->nnmrxq; 1089 s->niq += s->nnmrxq; 1090 1091 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1092 M_CXGBE, M_ZERO | M_WAITOK); 1093 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1094 M_CXGBE, M_ZERO | M_WAITOK); 1095 #endif 1096 1097 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1098 M_ZERO | M_WAITOK); 1099 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1100 M_ZERO | M_WAITOK); 1101 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1102 M_ZERO | M_WAITOK); 1103 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1104 M_ZERO | M_WAITOK); 1105 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1106 M_ZERO | M_WAITOK); 1107 1108 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1109 M_ZERO | M_WAITOK); 1110 1111 t4_init_l2t(sc, M_WAITOK); 1112 t4_init_tx_sched(sc); 1113 1114 /* 1115 * Second pass over the ports. This time we know the number of rx and 1116 * tx queues that each port should get. 1117 */ 1118 rqidx = tqidx = 0; 1119 #ifdef TCP_OFFLOAD 1120 ofld_rqidx = ofld_tqidx = 0; 1121 #endif 1122 #ifdef DEV_NETMAP 1123 nm_rqidx = nm_tqidx = 0; 1124 #endif 1125 for_each_port(sc, i) { 1126 struct port_info *pi = sc->port[i]; 1127 struct vi_info *vi; 1128 1129 if (pi == NULL) 1130 continue; 1131 1132 pi->nvi = num_vis; 1133 for_each_vi(pi, j, vi) { 1134 vi->pi = pi; 1135 vi->qsize_rxq = t4_qsize_rxq; 1136 vi->qsize_txq = t4_qsize_txq; 1137 1138 vi->first_rxq = rqidx; 1139 vi->first_txq = tqidx; 1140 vi->tmr_idx = t4_tmr_idx; 1141 vi->pktc_idx = t4_pktc_idx; 1142 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1143 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1144 1145 rqidx += vi->nrxq; 1146 tqidx += vi->ntxq; 1147 1148 if (j == 0 && vi->ntxq > 1) 1149 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1150 else 1151 vi->rsrv_noflowq = 0; 1152 1153 #ifdef TCP_OFFLOAD 1154 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1155 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1156 vi->first_ofld_rxq = ofld_rqidx; 1157 vi->first_ofld_txq = ofld_tqidx; 1158 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1159 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1160 1161 ofld_rqidx += vi->nofldrxq; 1162 ofld_tqidx += vi->nofldtxq; 1163 #endif 1164 #ifdef DEV_NETMAP 1165 if (j > 0) { 1166 vi->first_nm_rxq = nm_rqidx; 1167 vi->first_nm_txq = nm_tqidx; 1168 vi->nnmrxq = iaq.nnmrxq_vi; 1169 vi->nnmtxq = iaq.nnmtxq_vi; 1170 nm_rqidx += vi->nnmrxq; 1171 nm_tqidx += vi->nnmtxq; 1172 } 1173 #endif 1174 } 1175 } 1176 1177 rc = t4_setup_intr_handlers(sc); 1178 if (rc != 0) { 1179 device_printf(dev, 1180 "failed to setup interrupt handlers: %d\n", rc); 1181 goto done; 1182 } 1183 1184 rc = bus_generic_probe(dev); 1185 if (rc != 0) { 1186 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1187 goto done; 1188 } 1189 1190 /* 1191 * Ensure thread-safe mailbox access (in debug builds). 1192 * 1193 * So far this was the only thread accessing the mailbox but various 1194 * ifnets and sysctls are about to be created and their handlers/ioctls 1195 * will access the mailbox from different threads. 1196 */ 1197 sc->flags |= CHK_MBOX_ACCESS; 1198 1199 rc = bus_generic_attach(dev); 1200 if (rc != 0) { 1201 device_printf(dev, 1202 "failed to attach all child ports: %d\n", rc); 1203 goto done; 1204 } 1205 1206 device_printf(dev, 1207 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1208 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1209 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1210 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1211 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1212 1213 t4_set_desc(sc); 1214 1215 notify_siblings(dev, 0); 1216 1217 done: 1218 if (rc != 0 && sc->cdev) { 1219 /* cdev was created and so cxgbetool works; recover that way. */ 1220 device_printf(dev, 1221 "error during attach, adapter is now in recovery mode.\n"); 1222 rc = 0; 1223 } 1224 1225 if (rc != 0) 1226 t4_detach_common(dev); 1227 else 1228 t4_sysctls(sc); 1229 1230 return (rc); 1231 } 1232 1233 static int 1234 t4_ready(device_t dev) 1235 { 1236 struct adapter *sc; 1237 1238 sc = device_get_softc(dev); 1239 if (sc->flags & FW_OK) 1240 return (0); 1241 return (ENXIO); 1242 } 1243 1244 static int 1245 t4_read_port_device(device_t dev, int port, device_t *child) 1246 { 1247 struct adapter *sc; 1248 struct port_info *pi; 1249 1250 sc = device_get_softc(dev); 1251 if (port < 0 || port >= MAX_NPORTS) 1252 return (EINVAL); 1253 pi = sc->port[port]; 1254 if (pi == NULL || pi->dev == NULL) 1255 return (ENXIO); 1256 *child = pi->dev; 1257 return (0); 1258 } 1259 1260 static int 1261 notify_siblings(device_t dev, int detaching) 1262 { 1263 device_t sibling; 1264 int error, i; 1265 1266 error = 0; 1267 for (i = 0; i < PCI_FUNCMAX; i++) { 1268 if (i == pci_get_function(dev)) 1269 continue; 1270 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1271 pci_get_slot(dev), i); 1272 if (sibling == NULL || !device_is_attached(sibling)) 1273 continue; 1274 if (detaching) 1275 error = T4_DETACH_CHILD(sibling); 1276 else 1277 (void)T4_ATTACH_CHILD(sibling); 1278 if (error) 1279 break; 1280 } 1281 return (error); 1282 } 1283 1284 /* 1285 * Idempotent 1286 */ 1287 static int 1288 t4_detach(device_t dev) 1289 { 1290 struct adapter *sc; 1291 int rc; 1292 1293 sc = device_get_softc(dev); 1294 1295 rc = notify_siblings(dev, 1); 1296 if (rc) { 1297 device_printf(dev, 1298 "failed to detach sibling devices: %d\n", rc); 1299 return (rc); 1300 } 1301 1302 return (t4_detach_common(dev)); 1303 } 1304 1305 int 1306 t4_detach_common(device_t dev) 1307 { 1308 struct adapter *sc; 1309 struct port_info *pi; 1310 int i, rc; 1311 1312 sc = device_get_softc(dev); 1313 1314 sc->flags &= ~CHK_MBOX_ACCESS; 1315 if (sc->flags & FULL_INIT_DONE) { 1316 if (!(sc->flags & IS_VF)) 1317 t4_intr_disable(sc); 1318 } 1319 1320 if (sc->cdev) { 1321 destroy_dev(sc->cdev); 1322 sc->cdev = NULL; 1323 } 1324 1325 if (device_is_attached(dev)) { 1326 rc = bus_generic_detach(dev); 1327 if (rc) { 1328 device_printf(dev, 1329 "failed to detach child devices: %d\n", rc); 1330 return (rc); 1331 } 1332 } 1333 1334 for (i = 0; i < sc->intr_count; i++) 1335 t4_free_irq(sc, &sc->irq[i]); 1336 1337 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1338 t4_free_tx_sched(sc); 1339 1340 for (i = 0; i < MAX_NPORTS; i++) { 1341 pi = sc->port[i]; 1342 if (pi) { 1343 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1344 if (pi->dev) 1345 device_delete_child(dev, pi->dev); 1346 1347 mtx_destroy(&pi->pi_lock); 1348 free(pi->vi, M_CXGBE); 1349 free(pi, M_CXGBE); 1350 } 1351 } 1352 1353 device_delete_children(dev); 1354 1355 if (sc->flags & FULL_INIT_DONE) 1356 adapter_full_uninit(sc); 1357 1358 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1359 t4_fw_bye(sc, sc->mbox); 1360 1361 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1362 pci_release_msi(dev); 1363 1364 if (sc->regs_res) 1365 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1366 sc->regs_res); 1367 1368 if (sc->udbs_res) 1369 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1370 sc->udbs_res); 1371 1372 if (sc->msix_res) 1373 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1374 sc->msix_res); 1375 1376 if (sc->l2t) 1377 t4_free_l2t(sc->l2t); 1378 1379 #ifdef TCP_OFFLOAD 1380 free(sc->sge.ofld_rxq, M_CXGBE); 1381 free(sc->sge.ofld_txq, M_CXGBE); 1382 #endif 1383 #ifdef DEV_NETMAP 1384 free(sc->sge.nm_rxq, M_CXGBE); 1385 free(sc->sge.nm_txq, M_CXGBE); 1386 #endif 1387 free(sc->irq, M_CXGBE); 1388 free(sc->sge.rxq, M_CXGBE); 1389 free(sc->sge.txq, M_CXGBE); 1390 free(sc->sge.ctrlq, M_CXGBE); 1391 free(sc->sge.iqmap, M_CXGBE); 1392 free(sc->sge.eqmap, M_CXGBE); 1393 free(sc->tids.ftid_tab, M_CXGBE); 1394 free(sc->tt.tls_rx_ports, M_CXGBE); 1395 t4_destroy_dma_tag(sc); 1396 if (mtx_initialized(&sc->sc_lock)) { 1397 sx_xlock(&t4_list_lock); 1398 SLIST_REMOVE(&t4_list, sc, adapter, link); 1399 sx_xunlock(&t4_list_lock); 1400 mtx_destroy(&sc->sc_lock); 1401 } 1402 1403 callout_drain(&sc->sfl_callout); 1404 if (mtx_initialized(&sc->tids.ftid_lock)) 1405 mtx_destroy(&sc->tids.ftid_lock); 1406 if (mtx_initialized(&sc->sfl_lock)) 1407 mtx_destroy(&sc->sfl_lock); 1408 if (mtx_initialized(&sc->ifp_lock)) 1409 mtx_destroy(&sc->ifp_lock); 1410 if (mtx_initialized(&sc->reg_lock)) 1411 mtx_destroy(&sc->reg_lock); 1412 1413 for (i = 0; i < NUM_MEMWIN; i++) { 1414 struct memwin *mw = &sc->memwin[i]; 1415 1416 if (rw_initialized(&mw->mw_lock)) 1417 rw_destroy(&mw->mw_lock); 1418 } 1419 1420 bzero(sc, sizeof(*sc)); 1421 1422 return (0); 1423 } 1424 1425 static int 1426 cxgbe_probe(device_t dev) 1427 { 1428 char buf[128]; 1429 struct port_info *pi = device_get_softc(dev); 1430 1431 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1432 device_set_desc_copy(dev, buf); 1433 1434 return (BUS_PROBE_DEFAULT); 1435 } 1436 1437 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1438 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1439 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1440 #define T4_CAP_ENABLE (T4_CAP) 1441 1442 static int 1443 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1444 { 1445 struct ifnet *ifp; 1446 struct sbuf *sb; 1447 1448 vi->xact_addr_filt = -1; 1449 callout_init(&vi->tick, 1); 1450 1451 /* Allocate an ifnet and set it up */ 1452 ifp = if_alloc(IFT_ETHER); 1453 if (ifp == NULL) { 1454 device_printf(dev, "Cannot allocate ifnet\n"); 1455 return (ENOMEM); 1456 } 1457 vi->ifp = ifp; 1458 ifp->if_softc = vi; 1459 1460 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1461 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1462 1463 ifp->if_init = cxgbe_init; 1464 ifp->if_ioctl = cxgbe_ioctl; 1465 ifp->if_transmit = cxgbe_transmit; 1466 ifp->if_qflush = cxgbe_qflush; 1467 ifp->if_get_counter = cxgbe_get_counter; 1468 1469 ifp->if_capabilities = T4_CAP; 1470 #ifdef TCP_OFFLOAD 1471 if (vi->nofldrxq != 0) 1472 ifp->if_capabilities |= IFCAP_TOE; 1473 #endif 1474 #ifdef DEV_NETMAP 1475 if (vi->nnmrxq != 0) 1476 ifp->if_capabilities |= IFCAP_NETMAP; 1477 #endif 1478 ifp->if_capenable = T4_CAP_ENABLE; 1479 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1480 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1481 1482 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1483 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1484 ifp->if_hw_tsomaxsegsize = 65536; 1485 1486 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1487 EVENTHANDLER_PRI_ANY); 1488 1489 ether_ifattach(ifp, vi->hw_addr); 1490 #ifdef DEV_NETMAP 1491 if (ifp->if_capabilities & IFCAP_NETMAP) 1492 cxgbe_nm_attach(vi); 1493 #endif 1494 sb = sbuf_new_auto(); 1495 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1496 #ifdef TCP_OFFLOAD 1497 if (ifp->if_capabilities & IFCAP_TOE) 1498 sbuf_printf(sb, "; %d txq, %d rxq (TOE)", 1499 vi->nofldtxq, vi->nofldrxq); 1500 #endif 1501 #ifdef DEV_NETMAP 1502 if (ifp->if_capabilities & IFCAP_NETMAP) 1503 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1504 vi->nnmtxq, vi->nnmrxq); 1505 #endif 1506 sbuf_finish(sb); 1507 device_printf(dev, "%s\n", sbuf_data(sb)); 1508 sbuf_delete(sb); 1509 1510 vi_sysctls(vi); 1511 1512 return (0); 1513 } 1514 1515 static int 1516 cxgbe_attach(device_t dev) 1517 { 1518 struct port_info *pi = device_get_softc(dev); 1519 struct adapter *sc = pi->adapter; 1520 struct vi_info *vi; 1521 int i, rc; 1522 1523 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1524 1525 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1526 if (rc) 1527 return (rc); 1528 1529 for_each_vi(pi, i, vi) { 1530 if (i == 0) 1531 continue; 1532 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1533 if (vi->dev == NULL) { 1534 device_printf(dev, "failed to add VI %d\n", i); 1535 continue; 1536 } 1537 device_set_softc(vi->dev, vi); 1538 } 1539 1540 cxgbe_sysctls(pi); 1541 1542 bus_generic_attach(dev); 1543 1544 return (0); 1545 } 1546 1547 static void 1548 cxgbe_vi_detach(struct vi_info *vi) 1549 { 1550 struct ifnet *ifp = vi->ifp; 1551 1552 ether_ifdetach(ifp); 1553 1554 if (vi->vlan_c) 1555 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1556 1557 /* Let detach proceed even if these fail. */ 1558 #ifdef DEV_NETMAP 1559 if (ifp->if_capabilities & IFCAP_NETMAP) 1560 cxgbe_nm_detach(vi); 1561 #endif 1562 cxgbe_uninit_synchronized(vi); 1563 callout_drain(&vi->tick); 1564 vi_full_uninit(vi); 1565 1566 if_free(vi->ifp); 1567 vi->ifp = NULL; 1568 } 1569 1570 static int 1571 cxgbe_detach(device_t dev) 1572 { 1573 struct port_info *pi = device_get_softc(dev); 1574 struct adapter *sc = pi->adapter; 1575 int rc; 1576 1577 /* Detach the extra VIs first. */ 1578 rc = bus_generic_detach(dev); 1579 if (rc) 1580 return (rc); 1581 device_delete_children(dev); 1582 1583 doom_vi(sc, &pi->vi[0]); 1584 1585 if (pi->flags & HAS_TRACEQ) { 1586 sc->traceq = -1; /* cloner should not create ifnet */ 1587 t4_tracer_port_detach(sc); 1588 } 1589 1590 cxgbe_vi_detach(&pi->vi[0]); 1591 callout_drain(&pi->tick); 1592 ifmedia_removeall(&pi->media); 1593 1594 end_synchronized_op(sc, 0); 1595 1596 return (0); 1597 } 1598 1599 static void 1600 cxgbe_init(void *arg) 1601 { 1602 struct vi_info *vi = arg; 1603 struct adapter *sc = vi->pi->adapter; 1604 1605 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1606 return; 1607 cxgbe_init_synchronized(vi); 1608 end_synchronized_op(sc, 0); 1609 } 1610 1611 static int 1612 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1613 { 1614 int rc = 0, mtu, flags, can_sleep; 1615 struct vi_info *vi = ifp->if_softc; 1616 struct port_info *pi = vi->pi; 1617 struct adapter *sc = pi->adapter; 1618 struct ifreq *ifr = (struct ifreq *)data; 1619 uint32_t mask; 1620 1621 switch (cmd) { 1622 case SIOCSIFMTU: 1623 mtu = ifr->ifr_mtu; 1624 if (mtu < ETHERMIN || mtu > MAX_MTU) 1625 return (EINVAL); 1626 1627 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1628 if (rc) 1629 return (rc); 1630 ifp->if_mtu = mtu; 1631 if (vi->flags & VI_INIT_DONE) { 1632 t4_update_fl_bufsize(ifp); 1633 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1634 rc = update_mac_settings(ifp, XGMAC_MTU); 1635 } 1636 end_synchronized_op(sc, 0); 1637 break; 1638 1639 case SIOCSIFFLAGS: 1640 can_sleep = 0; 1641 redo_sifflags: 1642 rc = begin_synchronized_op(sc, vi, 1643 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1644 if (rc) 1645 return (rc); 1646 1647 if (ifp->if_flags & IFF_UP) { 1648 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1649 flags = vi->if_flags; 1650 if ((ifp->if_flags ^ flags) & 1651 (IFF_PROMISC | IFF_ALLMULTI)) { 1652 if (can_sleep == 1) { 1653 end_synchronized_op(sc, 0); 1654 can_sleep = 0; 1655 goto redo_sifflags; 1656 } 1657 rc = update_mac_settings(ifp, 1658 XGMAC_PROMISC | XGMAC_ALLMULTI); 1659 } 1660 } else { 1661 if (can_sleep == 0) { 1662 end_synchronized_op(sc, LOCK_HELD); 1663 can_sleep = 1; 1664 goto redo_sifflags; 1665 } 1666 rc = cxgbe_init_synchronized(vi); 1667 } 1668 vi->if_flags = ifp->if_flags; 1669 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1670 if (can_sleep == 0) { 1671 end_synchronized_op(sc, LOCK_HELD); 1672 can_sleep = 1; 1673 goto redo_sifflags; 1674 } 1675 rc = cxgbe_uninit_synchronized(vi); 1676 } 1677 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1678 break; 1679 1680 case SIOCADDMULTI: 1681 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1682 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1683 if (rc) 1684 return (rc); 1685 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1686 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1687 end_synchronized_op(sc, LOCK_HELD); 1688 break; 1689 1690 case SIOCSIFCAP: 1691 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1692 if (rc) 1693 return (rc); 1694 1695 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1696 if (mask & IFCAP_TXCSUM) { 1697 ifp->if_capenable ^= IFCAP_TXCSUM; 1698 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1699 1700 if (IFCAP_TSO4 & ifp->if_capenable && 1701 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1702 ifp->if_capenable &= ~IFCAP_TSO4; 1703 if_printf(ifp, 1704 "tso4 disabled due to -txcsum.\n"); 1705 } 1706 } 1707 if (mask & IFCAP_TXCSUM_IPV6) { 1708 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1709 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1710 1711 if (IFCAP_TSO6 & ifp->if_capenable && 1712 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1713 ifp->if_capenable &= ~IFCAP_TSO6; 1714 if_printf(ifp, 1715 "tso6 disabled due to -txcsum6.\n"); 1716 } 1717 } 1718 if (mask & IFCAP_RXCSUM) 1719 ifp->if_capenable ^= IFCAP_RXCSUM; 1720 if (mask & IFCAP_RXCSUM_IPV6) 1721 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1722 1723 /* 1724 * Note that we leave CSUM_TSO alone (it is always set). The 1725 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1726 * sending a TSO request our way, so it's sufficient to toggle 1727 * IFCAP_TSOx only. 1728 */ 1729 if (mask & IFCAP_TSO4) { 1730 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1731 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1732 if_printf(ifp, "enable txcsum first.\n"); 1733 rc = EAGAIN; 1734 goto fail; 1735 } 1736 ifp->if_capenable ^= IFCAP_TSO4; 1737 } 1738 if (mask & IFCAP_TSO6) { 1739 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1740 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1741 if_printf(ifp, "enable txcsum6 first.\n"); 1742 rc = EAGAIN; 1743 goto fail; 1744 } 1745 ifp->if_capenable ^= IFCAP_TSO6; 1746 } 1747 if (mask & IFCAP_LRO) { 1748 #if defined(INET) || defined(INET6) 1749 int i; 1750 struct sge_rxq *rxq; 1751 1752 ifp->if_capenable ^= IFCAP_LRO; 1753 for_each_rxq(vi, i, rxq) { 1754 if (ifp->if_capenable & IFCAP_LRO) 1755 rxq->iq.flags |= IQ_LRO_ENABLED; 1756 else 1757 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1758 } 1759 #endif 1760 } 1761 #ifdef TCP_OFFLOAD 1762 if (mask & IFCAP_TOE) { 1763 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1764 1765 rc = toe_capability(vi, enable); 1766 if (rc != 0) 1767 goto fail; 1768 1769 ifp->if_capenable ^= mask; 1770 } 1771 #endif 1772 if (mask & IFCAP_VLAN_HWTAGGING) { 1773 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1774 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1775 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1776 } 1777 if (mask & IFCAP_VLAN_MTU) { 1778 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1779 1780 /* Need to find out how to disable auto-mtu-inflation */ 1781 } 1782 if (mask & IFCAP_VLAN_HWTSO) 1783 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1784 if (mask & IFCAP_VLAN_HWCSUM) 1785 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1786 1787 #ifdef VLAN_CAPABILITIES 1788 VLAN_CAPABILITIES(ifp); 1789 #endif 1790 fail: 1791 end_synchronized_op(sc, 0); 1792 break; 1793 1794 case SIOCSIFMEDIA: 1795 case SIOCGIFMEDIA: 1796 case SIOCGIFXMEDIA: 1797 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 1798 break; 1799 1800 case SIOCGI2C: { 1801 struct ifi2creq i2c; 1802 1803 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 1804 if (rc != 0) 1805 break; 1806 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1807 rc = EPERM; 1808 break; 1809 } 1810 if (i2c.len > sizeof(i2c.data)) { 1811 rc = EINVAL; 1812 break; 1813 } 1814 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1815 if (rc) 1816 return (rc); 1817 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 1818 i2c.offset, i2c.len, &i2c.data[0]); 1819 end_synchronized_op(sc, 0); 1820 if (rc == 0) 1821 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 1822 break; 1823 } 1824 1825 default: 1826 rc = ether_ioctl(ifp, cmd, data); 1827 } 1828 1829 return (rc); 1830 } 1831 1832 static int 1833 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1834 { 1835 struct vi_info *vi = ifp->if_softc; 1836 struct port_info *pi = vi->pi; 1837 struct adapter *sc = pi->adapter; 1838 struct sge_txq *txq; 1839 void *items[1]; 1840 int rc; 1841 1842 M_ASSERTPKTHDR(m); 1843 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1844 1845 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1846 m_freem(m); 1847 return (ENETDOWN); 1848 } 1849 1850 rc = parse_pkt(sc, &m); 1851 if (__predict_false(rc != 0)) { 1852 MPASS(m == NULL); /* was freed already */ 1853 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1854 return (rc); 1855 } 1856 1857 /* Select a txq. */ 1858 txq = &sc->sge.txq[vi->first_txq]; 1859 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1860 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1861 vi->rsrv_noflowq); 1862 1863 items[0] = m; 1864 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 1865 if (__predict_false(rc != 0)) 1866 m_freem(m); 1867 1868 return (rc); 1869 } 1870 1871 static void 1872 cxgbe_qflush(struct ifnet *ifp) 1873 { 1874 struct vi_info *vi = ifp->if_softc; 1875 struct sge_txq *txq; 1876 int i; 1877 1878 /* queues do not exist if !VI_INIT_DONE. */ 1879 if (vi->flags & VI_INIT_DONE) { 1880 for_each_txq(vi, i, txq) { 1881 TXQ_LOCK(txq); 1882 txq->eq.flags |= EQ_QFLUSH; 1883 TXQ_UNLOCK(txq); 1884 while (!mp_ring_is_idle(txq->r)) { 1885 mp_ring_check_drainage(txq->r, 0); 1886 pause("qflush", 1); 1887 } 1888 TXQ_LOCK(txq); 1889 txq->eq.flags &= ~EQ_QFLUSH; 1890 TXQ_UNLOCK(txq); 1891 } 1892 } 1893 if_qflush(ifp); 1894 } 1895 1896 static uint64_t 1897 vi_get_counter(struct ifnet *ifp, ift_counter c) 1898 { 1899 struct vi_info *vi = ifp->if_softc; 1900 struct fw_vi_stats_vf *s = &vi->stats; 1901 1902 vi_refresh_stats(vi->pi->adapter, vi); 1903 1904 switch (c) { 1905 case IFCOUNTER_IPACKETS: 1906 return (s->rx_bcast_frames + s->rx_mcast_frames + 1907 s->rx_ucast_frames); 1908 case IFCOUNTER_IERRORS: 1909 return (s->rx_err_frames); 1910 case IFCOUNTER_OPACKETS: 1911 return (s->tx_bcast_frames + s->tx_mcast_frames + 1912 s->tx_ucast_frames + s->tx_offload_frames); 1913 case IFCOUNTER_OERRORS: 1914 return (s->tx_drop_frames); 1915 case IFCOUNTER_IBYTES: 1916 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 1917 s->rx_ucast_bytes); 1918 case IFCOUNTER_OBYTES: 1919 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 1920 s->tx_ucast_bytes + s->tx_offload_bytes); 1921 case IFCOUNTER_IMCASTS: 1922 return (s->rx_mcast_frames); 1923 case IFCOUNTER_OMCASTS: 1924 return (s->tx_mcast_frames); 1925 case IFCOUNTER_OQDROPS: { 1926 uint64_t drops; 1927 1928 drops = 0; 1929 if (vi->flags & VI_INIT_DONE) { 1930 int i; 1931 struct sge_txq *txq; 1932 1933 for_each_txq(vi, i, txq) 1934 drops += counter_u64_fetch(txq->r->drops); 1935 } 1936 1937 return (drops); 1938 1939 } 1940 1941 default: 1942 return (if_get_counter_default(ifp, c)); 1943 } 1944 } 1945 1946 uint64_t 1947 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 1948 { 1949 struct vi_info *vi = ifp->if_softc; 1950 struct port_info *pi = vi->pi; 1951 struct adapter *sc = pi->adapter; 1952 struct port_stats *s = &pi->stats; 1953 1954 if (pi->nvi > 1 || sc->flags & IS_VF) 1955 return (vi_get_counter(ifp, c)); 1956 1957 cxgbe_refresh_stats(sc, pi); 1958 1959 switch (c) { 1960 case IFCOUNTER_IPACKETS: 1961 return (s->rx_frames); 1962 1963 case IFCOUNTER_IERRORS: 1964 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 1965 s->rx_fcs_err + s->rx_len_err); 1966 1967 case IFCOUNTER_OPACKETS: 1968 return (s->tx_frames); 1969 1970 case IFCOUNTER_OERRORS: 1971 return (s->tx_error_frames); 1972 1973 case IFCOUNTER_IBYTES: 1974 return (s->rx_octets); 1975 1976 case IFCOUNTER_OBYTES: 1977 return (s->tx_octets); 1978 1979 case IFCOUNTER_IMCASTS: 1980 return (s->rx_mcast_frames); 1981 1982 case IFCOUNTER_OMCASTS: 1983 return (s->tx_mcast_frames); 1984 1985 case IFCOUNTER_IQDROPS: 1986 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 1987 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 1988 s->rx_trunc3 + pi->tnl_cong_drops); 1989 1990 case IFCOUNTER_OQDROPS: { 1991 uint64_t drops; 1992 1993 drops = s->tx_drop; 1994 if (vi->flags & VI_INIT_DONE) { 1995 int i; 1996 struct sge_txq *txq; 1997 1998 for_each_txq(vi, i, txq) 1999 drops += counter_u64_fetch(txq->r->drops); 2000 } 2001 2002 return (drops); 2003 2004 } 2005 2006 default: 2007 return (if_get_counter_default(ifp, c)); 2008 } 2009 } 2010 2011 static int 2012 cxgbe_media_change(struct ifnet *ifp) 2013 { 2014 struct vi_info *vi = ifp->if_softc; 2015 2016 device_printf(vi->dev, "%s unimplemented.\n", __func__); 2017 2018 return (EOPNOTSUPP); 2019 } 2020 2021 static void 2022 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2023 { 2024 struct vi_info *vi = ifp->if_softc; 2025 struct port_info *pi = vi->pi; 2026 struct ifmedia_entry *cur; 2027 struct link_config *lc = &pi->link_cfg; 2028 2029 /* 2030 * If all the interfaces are administratively down the firmware does not 2031 * report transceiver changes. Refresh port info here so that ifconfig 2032 * displays accurate information at all times. 2033 */ 2034 if (begin_synchronized_op(pi->adapter, NULL, SLEEP_OK | INTR_OK, 2035 "t4med") == 0) { 2036 PORT_LOCK(pi); 2037 if (pi->up_vis == 0) { 2038 t4_update_port_info(pi); 2039 build_medialist(pi, &pi->media); 2040 } 2041 PORT_UNLOCK(pi); 2042 end_synchronized_op(pi->adapter, 0); 2043 } 2044 2045 ifmr->ifm_status = IFM_AVALID; 2046 if (lc->link_ok == 0) 2047 return; 2048 2049 ifmr->ifm_status |= IFM_ACTIVE; 2050 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2051 if (lc->fc & PAUSE_RX) 2052 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2053 if (lc->fc & PAUSE_TX) 2054 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2055 2056 /* active and current will differ iff current media is autoselect. */ 2057 cur = pi->media.ifm_cur; 2058 if (cur != NULL && IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 2059 return; 2060 2061 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2062 if (lc->fc & PAUSE_RX) 2063 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2064 if (lc->fc & PAUSE_TX) 2065 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2066 switch (lc->speed) { 2067 case 10000: 2068 ifmr->ifm_active |= IFM_10G_T; 2069 break; 2070 case 1000: 2071 ifmr->ifm_active |= IFM_1000_T; 2072 break; 2073 case 100: 2074 ifmr->ifm_active |= IFM_100_TX; 2075 break; 2076 case 10: 2077 ifmr->ifm_active |= IFM_10_T; 2078 break; 2079 default: 2080 device_printf(vi->dev, "link up but speed unknown (%u)\n", 2081 lc->speed); 2082 } 2083 } 2084 2085 static int 2086 vcxgbe_probe(device_t dev) 2087 { 2088 char buf[128]; 2089 struct vi_info *vi = device_get_softc(dev); 2090 2091 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2092 vi - vi->pi->vi); 2093 device_set_desc_copy(dev, buf); 2094 2095 return (BUS_PROBE_DEFAULT); 2096 } 2097 2098 static int 2099 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2100 { 2101 int func, index, rc; 2102 uint32_t param, val; 2103 2104 ASSERT_SYNCHRONIZED_OP(sc); 2105 2106 index = vi - pi->vi; 2107 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2108 KASSERT(index < nitems(vi_mac_funcs), 2109 ("%s: VI %s doesn't have a MAC func", __func__, 2110 device_get_nameunit(vi->dev))); 2111 func = vi_mac_funcs[index]; 2112 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2113 vi->hw_addr, &vi->rss_size, func, 0); 2114 if (rc < 0) { 2115 device_printf(vi->dev, "failed to allocate virtual interface %d" 2116 "for port %d: %d\n", index, pi->port_id, -rc); 2117 return (-rc); 2118 } 2119 vi->viid = rc; 2120 if (chip_id(sc) <= CHELSIO_T5) 2121 vi->smt_idx = (rc & 0x7f) << 1; 2122 else 2123 vi->smt_idx = (rc & 0x7f); 2124 2125 if (vi->rss_size == 1) { 2126 /* 2127 * This VI didn't get a slice of the RSS table. Reduce the 2128 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2129 * configuration file (nvi, rssnvi for this PF) if this is a 2130 * problem. 2131 */ 2132 device_printf(vi->dev, "RSS table not available.\n"); 2133 vi->rss_base = 0xffff; 2134 2135 return (0); 2136 } 2137 2138 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2139 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2140 V_FW_PARAMS_PARAM_YZ(vi->viid); 2141 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2142 if (rc) 2143 vi->rss_base = 0xffff; 2144 else { 2145 MPASS((val >> 16) == vi->rss_size); 2146 vi->rss_base = val & 0xffff; 2147 } 2148 2149 return (0); 2150 } 2151 2152 static int 2153 vcxgbe_attach(device_t dev) 2154 { 2155 struct vi_info *vi; 2156 struct port_info *pi; 2157 struct adapter *sc; 2158 int rc; 2159 2160 vi = device_get_softc(dev); 2161 pi = vi->pi; 2162 sc = pi->adapter; 2163 2164 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2165 if (rc) 2166 return (rc); 2167 rc = alloc_extra_vi(sc, pi, vi); 2168 end_synchronized_op(sc, 0); 2169 if (rc) 2170 return (rc); 2171 2172 rc = cxgbe_vi_attach(dev, vi); 2173 if (rc) { 2174 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2175 return (rc); 2176 } 2177 return (0); 2178 } 2179 2180 static int 2181 vcxgbe_detach(device_t dev) 2182 { 2183 struct vi_info *vi; 2184 struct adapter *sc; 2185 2186 vi = device_get_softc(dev); 2187 sc = vi->pi->adapter; 2188 2189 doom_vi(sc, vi); 2190 2191 cxgbe_vi_detach(vi); 2192 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2193 2194 end_synchronized_op(sc, 0); 2195 2196 return (0); 2197 } 2198 2199 void 2200 t4_fatal_err(struct adapter *sc) 2201 { 2202 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2203 t4_intr_disable(sc); 2204 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2205 device_get_nameunit(sc->dev)); 2206 } 2207 2208 void 2209 t4_add_adapter(struct adapter *sc) 2210 { 2211 sx_xlock(&t4_list_lock); 2212 SLIST_INSERT_HEAD(&t4_list, sc, link); 2213 sx_xunlock(&t4_list_lock); 2214 } 2215 2216 int 2217 t4_map_bars_0_and_4(struct adapter *sc) 2218 { 2219 sc->regs_rid = PCIR_BAR(0); 2220 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2221 &sc->regs_rid, RF_ACTIVE); 2222 if (sc->regs_res == NULL) { 2223 device_printf(sc->dev, "cannot map registers.\n"); 2224 return (ENXIO); 2225 } 2226 sc->bt = rman_get_bustag(sc->regs_res); 2227 sc->bh = rman_get_bushandle(sc->regs_res); 2228 sc->mmio_len = rman_get_size(sc->regs_res); 2229 setbit(&sc->doorbells, DOORBELL_KDB); 2230 2231 sc->msix_rid = PCIR_BAR(4); 2232 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2233 &sc->msix_rid, RF_ACTIVE); 2234 if (sc->msix_res == NULL) { 2235 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2236 return (ENXIO); 2237 } 2238 2239 return (0); 2240 } 2241 2242 int 2243 t4_map_bar_2(struct adapter *sc) 2244 { 2245 2246 /* 2247 * T4: only iWARP driver uses the userspace doorbells. There is no need 2248 * to map it if RDMA is disabled. 2249 */ 2250 if (is_t4(sc) && sc->rdmacaps == 0) 2251 return (0); 2252 2253 sc->udbs_rid = PCIR_BAR(2); 2254 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2255 &sc->udbs_rid, RF_ACTIVE); 2256 if (sc->udbs_res == NULL) { 2257 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2258 return (ENXIO); 2259 } 2260 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2261 2262 if (chip_id(sc) >= CHELSIO_T5) { 2263 setbit(&sc->doorbells, DOORBELL_UDB); 2264 #if defined(__i386__) || defined(__amd64__) 2265 if (t5_write_combine) { 2266 int rc, mode; 2267 2268 /* 2269 * Enable write combining on BAR2. This is the 2270 * userspace doorbell BAR and is split into 128B 2271 * (UDBS_SEG_SIZE) doorbell regions, each associated 2272 * with an egress queue. The first 64B has the doorbell 2273 * and the second 64B can be used to submit a tx work 2274 * request with an implicit doorbell. 2275 */ 2276 2277 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2278 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2279 if (rc == 0) { 2280 clrbit(&sc->doorbells, DOORBELL_UDB); 2281 setbit(&sc->doorbells, DOORBELL_WCWR); 2282 setbit(&sc->doorbells, DOORBELL_UDBWC); 2283 } else { 2284 t5_write_combine = 0; 2285 device_printf(sc->dev, 2286 "couldn't enable write combining: %d\n", 2287 rc); 2288 } 2289 2290 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2291 t4_write_reg(sc, A_SGE_STAT_CFG, 2292 V_STATSOURCE_T5(7) | mode); 2293 } 2294 #else 2295 t5_write_combine = 0; 2296 #endif 2297 sc->iwt.wc_en = t5_write_combine; 2298 } 2299 2300 return (0); 2301 } 2302 2303 struct memwin_init { 2304 uint32_t base; 2305 uint32_t aperture; 2306 }; 2307 2308 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2309 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2310 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2311 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2312 }; 2313 2314 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2315 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2316 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2317 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2318 }; 2319 2320 static void 2321 setup_memwin(struct adapter *sc) 2322 { 2323 const struct memwin_init *mw_init; 2324 struct memwin *mw; 2325 int i; 2326 uint32_t bar0; 2327 2328 if (is_t4(sc)) { 2329 /* 2330 * Read low 32b of bar0 indirectly via the hardware backdoor 2331 * mechanism. Works from within PCI passthrough environments 2332 * too, where rman_get_start() can return a different value. We 2333 * need to program the T4 memory window decoders with the actual 2334 * addresses that will be coming across the PCIe link. 2335 */ 2336 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2337 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2338 2339 mw_init = &t4_memwin[0]; 2340 } else { 2341 /* T5+ use the relative offset inside the PCIe BAR */ 2342 bar0 = 0; 2343 2344 mw_init = &t5_memwin[0]; 2345 } 2346 2347 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2348 rw_init(&mw->mw_lock, "memory window access"); 2349 mw->mw_base = mw_init->base; 2350 mw->mw_aperture = mw_init->aperture; 2351 mw->mw_curpos = 0; 2352 t4_write_reg(sc, 2353 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2354 (mw->mw_base + bar0) | V_BIR(0) | 2355 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2356 rw_wlock(&mw->mw_lock); 2357 position_memwin(sc, i, 0); 2358 rw_wunlock(&mw->mw_lock); 2359 } 2360 2361 /* flush */ 2362 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2363 } 2364 2365 /* 2366 * Positions the memory window at the given address in the card's address space. 2367 * There are some alignment requirements and the actual position may be at an 2368 * address prior to the requested address. mw->mw_curpos always has the actual 2369 * position of the window. 2370 */ 2371 static void 2372 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2373 { 2374 struct memwin *mw; 2375 uint32_t pf; 2376 uint32_t reg; 2377 2378 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2379 mw = &sc->memwin[idx]; 2380 rw_assert(&mw->mw_lock, RA_WLOCKED); 2381 2382 if (is_t4(sc)) { 2383 pf = 0; 2384 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2385 } else { 2386 pf = V_PFNUM(sc->pf); 2387 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2388 } 2389 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2390 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2391 t4_read_reg(sc, reg); /* flush */ 2392 } 2393 2394 static int 2395 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2396 int len, int rw) 2397 { 2398 struct memwin *mw; 2399 uint32_t mw_end, v; 2400 2401 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2402 2403 /* Memory can only be accessed in naturally aligned 4 byte units */ 2404 if (addr & 3 || len & 3 || len <= 0) 2405 return (EINVAL); 2406 2407 mw = &sc->memwin[idx]; 2408 while (len > 0) { 2409 rw_rlock(&mw->mw_lock); 2410 mw_end = mw->mw_curpos + mw->mw_aperture; 2411 if (addr >= mw_end || addr < mw->mw_curpos) { 2412 /* Will need to reposition the window */ 2413 if (!rw_try_upgrade(&mw->mw_lock)) { 2414 rw_runlock(&mw->mw_lock); 2415 rw_wlock(&mw->mw_lock); 2416 } 2417 rw_assert(&mw->mw_lock, RA_WLOCKED); 2418 position_memwin(sc, idx, addr); 2419 rw_downgrade(&mw->mw_lock); 2420 mw_end = mw->mw_curpos + mw->mw_aperture; 2421 } 2422 rw_assert(&mw->mw_lock, RA_RLOCKED); 2423 while (addr < mw_end && len > 0) { 2424 if (rw == 0) { 2425 v = t4_read_reg(sc, mw->mw_base + addr - 2426 mw->mw_curpos); 2427 *val++ = le32toh(v); 2428 } else { 2429 v = *val++; 2430 t4_write_reg(sc, mw->mw_base + addr - 2431 mw->mw_curpos, htole32(v)); 2432 } 2433 addr += 4; 2434 len -= 4; 2435 } 2436 rw_runlock(&mw->mw_lock); 2437 } 2438 2439 return (0); 2440 } 2441 2442 static inline int 2443 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2444 int len) 2445 { 2446 2447 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 2448 } 2449 2450 static inline int 2451 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 2452 const uint32_t *val, int len) 2453 { 2454 2455 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 2456 } 2457 2458 static int 2459 t4_range_cmp(const void *a, const void *b) 2460 { 2461 return ((const struct t4_range *)a)->start - 2462 ((const struct t4_range *)b)->start; 2463 } 2464 2465 /* 2466 * Verify that the memory range specified by the addr/len pair is valid within 2467 * the card's address space. 2468 */ 2469 static int 2470 validate_mem_range(struct adapter *sc, uint32_t addr, int len) 2471 { 2472 struct t4_range mem_ranges[4], *r, *next; 2473 uint32_t em, addr_len; 2474 int i, n, remaining; 2475 2476 /* Memory can only be accessed in naturally aligned 4 byte units */ 2477 if (addr & 3 || len & 3 || len <= 0) 2478 return (EINVAL); 2479 2480 /* Enabled memories */ 2481 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2482 2483 r = &mem_ranges[0]; 2484 n = 0; 2485 bzero(r, sizeof(mem_ranges)); 2486 if (em & F_EDRAM0_ENABLE) { 2487 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2488 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2489 if (r->size > 0) { 2490 r->start = G_EDRAM0_BASE(addr_len) << 20; 2491 if (addr >= r->start && 2492 addr + len <= r->start + r->size) 2493 return (0); 2494 r++; 2495 n++; 2496 } 2497 } 2498 if (em & F_EDRAM1_ENABLE) { 2499 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2500 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2501 if (r->size > 0) { 2502 r->start = G_EDRAM1_BASE(addr_len) << 20; 2503 if (addr >= r->start && 2504 addr + len <= r->start + r->size) 2505 return (0); 2506 r++; 2507 n++; 2508 } 2509 } 2510 if (em & F_EXT_MEM_ENABLE) { 2511 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2512 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2513 if (r->size > 0) { 2514 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2515 if (addr >= r->start && 2516 addr + len <= r->start + r->size) 2517 return (0); 2518 r++; 2519 n++; 2520 } 2521 } 2522 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2523 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2524 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2525 if (r->size > 0) { 2526 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2527 if (addr >= r->start && 2528 addr + len <= r->start + r->size) 2529 return (0); 2530 r++; 2531 n++; 2532 } 2533 } 2534 MPASS(n <= nitems(mem_ranges)); 2535 2536 if (n > 1) { 2537 /* Sort and merge the ranges. */ 2538 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2539 2540 /* Start from index 0 and examine the next n - 1 entries. */ 2541 r = &mem_ranges[0]; 2542 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2543 2544 MPASS(r->size > 0); /* r is a valid entry. */ 2545 next = r + 1; 2546 MPASS(next->size > 0); /* and so is the next one. */ 2547 2548 while (r->start + r->size >= next->start) { 2549 /* Merge the next one into the current entry. */ 2550 r->size = max(r->start + r->size, 2551 next->start + next->size) - r->start; 2552 n--; /* One fewer entry in total. */ 2553 if (--remaining == 0) 2554 goto done; /* short circuit */ 2555 next++; 2556 } 2557 if (next != r + 1) { 2558 /* 2559 * Some entries were merged into r and next 2560 * points to the first valid entry that couldn't 2561 * be merged. 2562 */ 2563 MPASS(next->size > 0); /* must be valid */ 2564 memcpy(r + 1, next, remaining * sizeof(*r)); 2565 #ifdef INVARIANTS 2566 /* 2567 * This so that the foo->size assertion in the 2568 * next iteration of the loop do the right 2569 * thing for entries that were pulled up and are 2570 * no longer valid. 2571 */ 2572 MPASS(n < nitems(mem_ranges)); 2573 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2574 sizeof(struct t4_range)); 2575 #endif 2576 } 2577 } 2578 done: 2579 /* Done merging the ranges. */ 2580 MPASS(n > 0); 2581 r = &mem_ranges[0]; 2582 for (i = 0; i < n; i++, r++) { 2583 if (addr >= r->start && 2584 addr + len <= r->start + r->size) 2585 return (0); 2586 } 2587 } 2588 2589 return (EFAULT); 2590 } 2591 2592 static int 2593 fwmtype_to_hwmtype(int mtype) 2594 { 2595 2596 switch (mtype) { 2597 case FW_MEMTYPE_EDC0: 2598 return (MEM_EDC0); 2599 case FW_MEMTYPE_EDC1: 2600 return (MEM_EDC1); 2601 case FW_MEMTYPE_EXTMEM: 2602 return (MEM_MC0); 2603 case FW_MEMTYPE_EXTMEM1: 2604 return (MEM_MC1); 2605 default: 2606 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2607 } 2608 } 2609 2610 /* 2611 * Verify that the memory range specified by the memtype/offset/len pair is 2612 * valid and lies entirely within the memtype specified. The global address of 2613 * the start of the range is returned in addr. 2614 */ 2615 static int 2616 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 2617 uint32_t *addr) 2618 { 2619 uint32_t em, addr_len, maddr; 2620 2621 /* Memory can only be accessed in naturally aligned 4 byte units */ 2622 if (off & 3 || len & 3 || len == 0) 2623 return (EINVAL); 2624 2625 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2626 switch (fwmtype_to_hwmtype(mtype)) { 2627 case MEM_EDC0: 2628 if (!(em & F_EDRAM0_ENABLE)) 2629 return (EINVAL); 2630 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2631 maddr = G_EDRAM0_BASE(addr_len) << 20; 2632 break; 2633 case MEM_EDC1: 2634 if (!(em & F_EDRAM1_ENABLE)) 2635 return (EINVAL); 2636 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2637 maddr = G_EDRAM1_BASE(addr_len) << 20; 2638 break; 2639 case MEM_MC: 2640 if (!(em & F_EXT_MEM_ENABLE)) 2641 return (EINVAL); 2642 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2643 maddr = G_EXT_MEM_BASE(addr_len) << 20; 2644 break; 2645 case MEM_MC1: 2646 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 2647 return (EINVAL); 2648 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2649 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 2650 break; 2651 default: 2652 return (EINVAL); 2653 } 2654 2655 *addr = maddr + off; /* global address */ 2656 return (validate_mem_range(sc, *addr, len)); 2657 } 2658 2659 static int 2660 fixup_devlog_params(struct adapter *sc) 2661 { 2662 struct devlog_params *dparams = &sc->params.devlog; 2663 int rc; 2664 2665 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 2666 dparams->size, &dparams->addr); 2667 2668 return (rc); 2669 } 2670 2671 static void 2672 update_nirq(struct intrs_and_queues *iaq, int nports) 2673 { 2674 int extra = T4_EXTRA_INTR; 2675 2676 iaq->nirq = extra; 2677 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 2678 iaq->nirq += nports * (iaq->num_vis - 1) * 2679 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 2680 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 2681 } 2682 2683 /* 2684 * Adjust requirements to fit the number of interrupts available. 2685 */ 2686 static void 2687 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 2688 int navail) 2689 { 2690 int old_nirq; 2691 const int nports = sc->params.nports; 2692 2693 MPASS(nports > 0); 2694 MPASS(navail > 0); 2695 2696 bzero(iaq, sizeof(*iaq)); 2697 iaq->intr_type = itype; 2698 iaq->num_vis = t4_num_vis; 2699 iaq->ntxq = t4_ntxq; 2700 iaq->ntxq_vi = t4_ntxq_vi; 2701 iaq->nrxq = t4_nrxq; 2702 iaq->nrxq_vi = t4_nrxq_vi; 2703 #ifdef TCP_OFFLOAD 2704 if (is_offload(sc)) { 2705 iaq->nofldtxq = t4_nofldtxq; 2706 iaq->nofldtxq_vi = t4_nofldtxq_vi; 2707 iaq->nofldrxq = t4_nofldrxq; 2708 iaq->nofldrxq_vi = t4_nofldrxq_vi; 2709 } 2710 #endif 2711 #ifdef DEV_NETMAP 2712 iaq->nnmtxq_vi = t4_nnmtxq_vi; 2713 iaq->nnmrxq_vi = t4_nnmrxq_vi; 2714 #endif 2715 2716 update_nirq(iaq, nports); 2717 if (iaq->nirq <= navail && 2718 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2719 /* 2720 * This is the normal case -- there are enough interrupts for 2721 * everything. 2722 */ 2723 goto done; 2724 } 2725 2726 /* 2727 * If extra VIs have been configured try reducing their count and see if 2728 * that works. 2729 */ 2730 while (iaq->num_vis > 1) { 2731 iaq->num_vis--; 2732 update_nirq(iaq, nports); 2733 if (iaq->nirq <= navail && 2734 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2735 device_printf(sc->dev, "virtual interfaces per port " 2736 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 2737 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 2738 "itype %d, navail %u, nirq %d.\n", 2739 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 2740 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 2741 itype, navail, iaq->nirq); 2742 goto done; 2743 } 2744 } 2745 2746 /* 2747 * Extra VIs will not be created. Log a message if they were requested. 2748 */ 2749 MPASS(iaq->num_vis == 1); 2750 iaq->ntxq_vi = iaq->nrxq_vi = 0; 2751 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 2752 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 2753 if (iaq->num_vis != t4_num_vis) { 2754 device_printf(sc->dev, "extra virtual interfaces disabled. " 2755 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 2756 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 2757 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 2758 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 2759 } 2760 2761 /* 2762 * Keep reducing the number of NIC rx queues to the next lower power of 2763 * 2 (for even RSS distribution) and halving the TOE rx queues and see 2764 * if that works. 2765 */ 2766 do { 2767 if (iaq->nrxq > 1) { 2768 do { 2769 iaq->nrxq--; 2770 } while (!powerof2(iaq->nrxq)); 2771 } 2772 if (iaq->nofldrxq > 1) 2773 iaq->nofldrxq >>= 1; 2774 2775 old_nirq = iaq->nirq; 2776 update_nirq(iaq, nports); 2777 if (iaq->nirq <= navail && 2778 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2779 device_printf(sc->dev, "running with reduced number of " 2780 "rx queues because of shortage of interrupts. " 2781 "nrxq=%u, nofldrxq=%u. " 2782 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 2783 iaq->nofldrxq, itype, navail, iaq->nirq); 2784 goto done; 2785 } 2786 } while (old_nirq != iaq->nirq); 2787 2788 /* One interrupt for everything. Ugh. */ 2789 device_printf(sc->dev, "running with minimal number of queues. " 2790 "itype %d, navail %u.\n", itype, navail); 2791 iaq->nirq = 1; 2792 MPASS(iaq->nrxq == 1); 2793 iaq->ntxq = 1; 2794 if (iaq->nofldrxq > 1) 2795 iaq->nofldtxq = 1; 2796 done: 2797 MPASS(iaq->num_vis > 0); 2798 if (iaq->num_vis > 1) { 2799 MPASS(iaq->nrxq_vi > 0); 2800 MPASS(iaq->ntxq_vi > 0); 2801 } 2802 MPASS(iaq->nirq > 0); 2803 MPASS(iaq->nrxq > 0); 2804 MPASS(iaq->ntxq > 0); 2805 if (itype == INTR_MSI) { 2806 MPASS(powerof2(iaq->nirq)); 2807 } 2808 } 2809 2810 static int 2811 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 2812 { 2813 int rc, itype, navail, nalloc; 2814 2815 for (itype = INTR_MSIX; itype; itype >>= 1) { 2816 2817 if ((itype & t4_intr_types) == 0) 2818 continue; /* not allowed */ 2819 2820 if (itype == INTR_MSIX) 2821 navail = pci_msix_count(sc->dev); 2822 else if (itype == INTR_MSI) 2823 navail = pci_msi_count(sc->dev); 2824 else 2825 navail = 1; 2826 restart: 2827 if (navail == 0) 2828 continue; 2829 2830 calculate_iaq(sc, iaq, itype, navail); 2831 nalloc = iaq->nirq; 2832 rc = 0; 2833 if (itype == INTR_MSIX) 2834 rc = pci_alloc_msix(sc->dev, &nalloc); 2835 else if (itype == INTR_MSI) 2836 rc = pci_alloc_msi(sc->dev, &nalloc); 2837 2838 if (rc == 0 && nalloc > 0) { 2839 if (nalloc == iaq->nirq) 2840 return (0); 2841 2842 /* 2843 * Didn't get the number requested. Use whatever number 2844 * the kernel is willing to allocate. 2845 */ 2846 device_printf(sc->dev, "fewer vectors than requested, " 2847 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 2848 itype, iaq->nirq, nalloc); 2849 pci_release_msi(sc->dev); 2850 navail = nalloc; 2851 goto restart; 2852 } 2853 2854 device_printf(sc->dev, 2855 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 2856 itype, rc, iaq->nirq, nalloc); 2857 } 2858 2859 device_printf(sc->dev, 2860 "failed to find a usable interrupt type. " 2861 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 2862 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 2863 2864 return (ENXIO); 2865 } 2866 2867 #define FW_VERSION(chip) ( \ 2868 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 2869 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 2870 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 2871 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 2872 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 2873 2874 struct fw_info { 2875 uint8_t chip; 2876 char *kld_name; 2877 char *fw_mod_name; 2878 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 2879 } fw_info[] = { 2880 { 2881 .chip = CHELSIO_T4, 2882 .kld_name = "t4fw_cfg", 2883 .fw_mod_name = "t4fw", 2884 .fw_hdr = { 2885 .chip = FW_HDR_CHIP_T4, 2886 .fw_ver = htobe32_const(FW_VERSION(T4)), 2887 .intfver_nic = FW_INTFVER(T4, NIC), 2888 .intfver_vnic = FW_INTFVER(T4, VNIC), 2889 .intfver_ofld = FW_INTFVER(T4, OFLD), 2890 .intfver_ri = FW_INTFVER(T4, RI), 2891 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 2892 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 2893 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 2894 .intfver_fcoe = FW_INTFVER(T4, FCOE), 2895 }, 2896 }, { 2897 .chip = CHELSIO_T5, 2898 .kld_name = "t5fw_cfg", 2899 .fw_mod_name = "t5fw", 2900 .fw_hdr = { 2901 .chip = FW_HDR_CHIP_T5, 2902 .fw_ver = htobe32_const(FW_VERSION(T5)), 2903 .intfver_nic = FW_INTFVER(T5, NIC), 2904 .intfver_vnic = FW_INTFVER(T5, VNIC), 2905 .intfver_ofld = FW_INTFVER(T5, OFLD), 2906 .intfver_ri = FW_INTFVER(T5, RI), 2907 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 2908 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 2909 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 2910 .intfver_fcoe = FW_INTFVER(T5, FCOE), 2911 }, 2912 }, { 2913 .chip = CHELSIO_T6, 2914 .kld_name = "t6fw_cfg", 2915 .fw_mod_name = "t6fw", 2916 .fw_hdr = { 2917 .chip = FW_HDR_CHIP_T6, 2918 .fw_ver = htobe32_const(FW_VERSION(T6)), 2919 .intfver_nic = FW_INTFVER(T6, NIC), 2920 .intfver_vnic = FW_INTFVER(T6, VNIC), 2921 .intfver_ofld = FW_INTFVER(T6, OFLD), 2922 .intfver_ri = FW_INTFVER(T6, RI), 2923 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 2924 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 2925 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 2926 .intfver_fcoe = FW_INTFVER(T6, FCOE), 2927 }, 2928 } 2929 }; 2930 2931 static struct fw_info * 2932 find_fw_info(int chip) 2933 { 2934 int i; 2935 2936 for (i = 0; i < nitems(fw_info); i++) { 2937 if (fw_info[i].chip == chip) 2938 return (&fw_info[i]); 2939 } 2940 return (NULL); 2941 } 2942 2943 /* 2944 * Is the given firmware API compatible with the one the driver was compiled 2945 * with? 2946 */ 2947 static int 2948 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 2949 { 2950 2951 /* short circuit if it's the exact same firmware version */ 2952 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 2953 return (1); 2954 2955 /* 2956 * XXX: Is this too conservative? Perhaps I should limit this to the 2957 * features that are supported in the driver. 2958 */ 2959 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 2960 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 2961 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 2962 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 2963 return (1); 2964 #undef SAME_INTF 2965 2966 return (0); 2967 } 2968 2969 /* 2970 * The firmware in the KLD is usable, but should it be installed? This routine 2971 * explains itself in detail if it indicates the KLD firmware should be 2972 * installed. 2973 */ 2974 static int 2975 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 2976 { 2977 const char *reason; 2978 2979 if (!card_fw_usable) { 2980 reason = "incompatible or unusable"; 2981 goto install; 2982 } 2983 2984 if (k > c) { 2985 reason = "older than the version bundled with this driver"; 2986 goto install; 2987 } 2988 2989 if (t4_fw_install == 2 && k != c) { 2990 reason = "different than the version bundled with this driver"; 2991 goto install; 2992 } 2993 2994 return (0); 2995 2996 install: 2997 if (t4_fw_install == 0) { 2998 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2999 "but the driver is prohibited from installing a different " 3000 "firmware on the card.\n", 3001 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3002 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3003 3004 return (0); 3005 } 3006 3007 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3008 "installing firmware %u.%u.%u.%u on card.\n", 3009 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3010 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3011 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3012 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3013 3014 return (1); 3015 } 3016 3017 /* 3018 * Establish contact with the firmware and determine if we are the master driver 3019 * or not, and whether we are responsible for chip initialization. 3020 */ 3021 static int 3022 prep_firmware(struct adapter *sc) 3023 { 3024 const struct firmware *fw = NULL, *default_cfg; 3025 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 3026 enum dev_state state; 3027 struct fw_info *fw_info; 3028 struct fw_hdr *card_fw; /* fw on the card */ 3029 const struct fw_hdr *kld_fw; /* fw in the KLD */ 3030 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 3031 against */ 3032 3033 /* This is the firmware whose headers the driver was compiled against */ 3034 fw_info = find_fw_info(chip_id(sc)); 3035 if (fw_info == NULL) { 3036 device_printf(sc->dev, 3037 "unable to look up firmware information for chip %d.\n", 3038 chip_id(sc)); 3039 return (EINVAL); 3040 } 3041 drv_fw = &fw_info->fw_hdr; 3042 3043 /* 3044 * The firmware KLD contains many modules. The KLD name is also the 3045 * name of the module that contains the default config file. 3046 */ 3047 default_cfg = firmware_get(fw_info->kld_name); 3048 3049 /* This is the firmware in the KLD */ 3050 fw = firmware_get(fw_info->fw_mod_name); 3051 if (fw != NULL) { 3052 kld_fw = (const void *)fw->data; 3053 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 3054 } else { 3055 kld_fw = NULL; 3056 kld_fw_usable = 0; 3057 } 3058 3059 /* Read the header of the firmware on the card */ 3060 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3061 rc = -t4_read_flash(sc, FLASH_FW_START, 3062 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 3063 if (rc == 0) { 3064 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 3065 if (card_fw->fw_ver == be32toh(0xffffffff)) { 3066 uint32_t d = be32toh(kld_fw->fw_ver); 3067 3068 if (!kld_fw_usable) { 3069 device_printf(sc->dev, 3070 "no firmware on the card and no usable " 3071 "firmware bundled with the driver.\n"); 3072 rc = EIO; 3073 goto done; 3074 } else if (t4_fw_install == 0) { 3075 device_printf(sc->dev, 3076 "no firmware on the card and the driver " 3077 "is prohibited from installing new " 3078 "firmware.\n"); 3079 rc = EIO; 3080 goto done; 3081 } 3082 3083 device_printf(sc->dev, "no firmware on the card, " 3084 "installing firmware %d.%d.%d.%d\n", 3085 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3086 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3087 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize); 3088 if (rc < 0) { 3089 rc = -rc; 3090 device_printf(sc->dev, 3091 "firmware install failed: %d.\n", rc); 3092 goto done; 3093 } 3094 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3095 card_fw_usable = 1; 3096 need_fw_reset = 0; 3097 } 3098 } else { 3099 device_printf(sc->dev, 3100 "Unable to read card's firmware header: %d\n", rc); 3101 card_fw_usable = 0; 3102 } 3103 3104 /* Contact firmware. */ 3105 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3106 if (rc < 0 || state == DEV_STATE_ERR) { 3107 rc = -rc; 3108 device_printf(sc->dev, 3109 "failed to connect to the firmware: %d, %d.\n", rc, state); 3110 goto done; 3111 } 3112 pf = rc; 3113 if (pf == sc->mbox) 3114 sc->flags |= MASTER_PF; 3115 else if (state == DEV_STATE_UNINIT) { 3116 /* 3117 * We didn't get to be the master so we definitely won't be 3118 * configuring the chip. It's a bug if someone else hasn't 3119 * configured it already. 3120 */ 3121 device_printf(sc->dev, "couldn't be master(%d), " 3122 "device not already initialized either(%d).\n", rc, state); 3123 rc = EPROTO; 3124 goto done; 3125 } 3126 3127 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 3128 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 3129 /* 3130 * Common case: the firmware on the card is an exact match and 3131 * the KLD is an exact match too, or the KLD is 3132 * absent/incompatible. Note that t4_fw_install = 2 is ignored 3133 * here -- use cxgbetool loadfw if you want to reinstall the 3134 * same firmware as the one on the card. 3135 */ 3136 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 3137 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 3138 be32toh(card_fw->fw_ver))) { 3139 3140 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3141 if (rc != 0) { 3142 device_printf(sc->dev, 3143 "failed to install firmware: %d\n", rc); 3144 goto done; 3145 } 3146 3147 /* Installed successfully, update the cached header too. */ 3148 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3149 card_fw_usable = 1; 3150 need_fw_reset = 0; /* already reset as part of load_fw */ 3151 } 3152 3153 if (!card_fw_usable) { 3154 uint32_t d, c, k; 3155 3156 d = ntohl(drv_fw->fw_ver); 3157 c = ntohl(card_fw->fw_ver); 3158 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3159 3160 device_printf(sc->dev, "Cannot find a usable firmware: " 3161 "fw_install %d, chip state %d, " 3162 "driver compiled with %d.%d.%d.%d, " 3163 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3164 t4_fw_install, state, 3165 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3166 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3167 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3168 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3169 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3170 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3171 rc = EINVAL; 3172 goto done; 3173 } 3174 3175 /* Reset device */ 3176 if (need_fw_reset && 3177 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3178 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3179 if (rc != ETIMEDOUT && rc != EIO) 3180 t4_fw_bye(sc, sc->mbox); 3181 goto done; 3182 } 3183 sc->flags |= FW_OK; 3184 3185 rc = get_params__pre_init(sc); 3186 if (rc != 0) 3187 goto done; /* error message displayed already */ 3188 3189 /* Partition adapter resources as specified in the config file. */ 3190 if (state == DEV_STATE_UNINIT) { 3191 3192 KASSERT(sc->flags & MASTER_PF, 3193 ("%s: trying to change chip settings when not master.", 3194 __func__)); 3195 3196 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3197 if (rc != 0) 3198 goto done; /* error message displayed already */ 3199 3200 t4_tweak_chip_settings(sc); 3201 3202 /* get basic stuff going */ 3203 rc = -t4_fw_initialize(sc, sc->mbox); 3204 if (rc != 0) { 3205 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3206 goto done; 3207 } 3208 } else { 3209 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3210 sc->cfcsum = 0; 3211 } 3212 3213 done: 3214 free(card_fw, M_CXGBE); 3215 if (fw != NULL) 3216 firmware_put(fw, FIRMWARE_UNLOAD); 3217 if (default_cfg != NULL) 3218 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3219 3220 return (rc); 3221 } 3222 3223 #define FW_PARAM_DEV(param) \ 3224 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3225 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3226 #define FW_PARAM_PFVF(param) \ 3227 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3228 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3229 3230 /* 3231 * Partition chip resources for use between various PFs, VFs, etc. 3232 */ 3233 static int 3234 partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3235 const char *name_prefix) 3236 { 3237 const struct firmware *cfg = NULL; 3238 int rc = 0; 3239 struct fw_caps_config_cmd caps; 3240 uint32_t mtype, moff, finicsum, cfcsum; 3241 3242 /* 3243 * Figure out what configuration file to use. Pick the default config 3244 * file for the card if the user hasn't specified one explicitly. 3245 */ 3246 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3247 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3248 /* Card specific overrides go here. */ 3249 if (pci_get_device(sc->dev) == 0x440a) 3250 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3251 if (is_fpga(sc)) 3252 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3253 } 3254 3255 /* 3256 * We need to load another module if the profile is anything except 3257 * "default" or "flash". 3258 */ 3259 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3260 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3261 char s[32]; 3262 3263 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3264 cfg = firmware_get(s); 3265 if (cfg == NULL) { 3266 if (default_cfg != NULL) { 3267 device_printf(sc->dev, 3268 "unable to load module \"%s\" for " 3269 "configuration profile \"%s\", will use " 3270 "the default config file instead.\n", 3271 s, sc->cfg_file); 3272 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3273 "%s", DEFAULT_CF); 3274 } else { 3275 device_printf(sc->dev, 3276 "unable to load module \"%s\" for " 3277 "configuration profile \"%s\", will use " 3278 "the config file on the card's flash " 3279 "instead.\n", s, sc->cfg_file); 3280 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3281 "%s", FLASH_CF); 3282 } 3283 } 3284 } 3285 3286 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3287 default_cfg == NULL) { 3288 device_printf(sc->dev, 3289 "default config file not available, will use the config " 3290 "file on the card's flash instead.\n"); 3291 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3292 } 3293 3294 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3295 u_int cflen; 3296 const uint32_t *cfdata; 3297 uint32_t param, val, addr; 3298 3299 KASSERT(cfg != NULL || default_cfg != NULL, 3300 ("%s: no config to upload", __func__)); 3301 3302 /* 3303 * Ask the firmware where it wants us to upload the config file. 3304 */ 3305 param = FW_PARAM_DEV(CF); 3306 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3307 if (rc != 0) { 3308 /* No support for config file? Shouldn't happen. */ 3309 device_printf(sc->dev, 3310 "failed to query config file location: %d.\n", rc); 3311 goto done; 3312 } 3313 mtype = G_FW_PARAMS_PARAM_Y(val); 3314 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3315 3316 /* 3317 * XXX: sheer laziness. We deliberately added 4 bytes of 3318 * useless stuffing/comments at the end of the config file so 3319 * it's ok to simply throw away the last remaining bytes when 3320 * the config file is not an exact multiple of 4. This also 3321 * helps with the validate_mt_off_len check. 3322 */ 3323 if (cfg != NULL) { 3324 cflen = cfg->datasize & ~3; 3325 cfdata = cfg->data; 3326 } else { 3327 cflen = default_cfg->datasize & ~3; 3328 cfdata = default_cfg->data; 3329 } 3330 3331 if (cflen > FLASH_CFG_MAX_SIZE) { 3332 device_printf(sc->dev, 3333 "config file too long (%d, max allowed is %d). " 3334 "Will try to use the config on the card, if any.\n", 3335 cflen, FLASH_CFG_MAX_SIZE); 3336 goto use_config_on_flash; 3337 } 3338 3339 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3340 if (rc != 0) { 3341 device_printf(sc->dev, 3342 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3343 "Will try to use the config on the card, if any.\n", 3344 __func__, mtype, moff, cflen, rc); 3345 goto use_config_on_flash; 3346 } 3347 write_via_memwin(sc, 2, addr, cfdata, cflen); 3348 } else { 3349 use_config_on_flash: 3350 mtype = FW_MEMTYPE_FLASH; 3351 moff = t4_flash_cfg_addr(sc); 3352 } 3353 3354 bzero(&caps, sizeof(caps)); 3355 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3356 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3357 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3358 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3359 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3360 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3361 if (rc != 0) { 3362 device_printf(sc->dev, 3363 "failed to pre-process config file: %d " 3364 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3365 goto done; 3366 } 3367 3368 finicsum = be32toh(caps.finicsum); 3369 cfcsum = be32toh(caps.cfcsum); 3370 if (finicsum != cfcsum) { 3371 device_printf(sc->dev, 3372 "WARNING: config file checksum mismatch: %08x %08x\n", 3373 finicsum, cfcsum); 3374 } 3375 sc->cfcsum = cfcsum; 3376 3377 #define LIMIT_CAPS(x) do { \ 3378 caps.x &= htobe16(t4_##x##_allowed); \ 3379 } while (0) 3380 3381 /* 3382 * Let the firmware know what features will (not) be used so it can tune 3383 * things accordingly. 3384 */ 3385 LIMIT_CAPS(nbmcaps); 3386 LIMIT_CAPS(linkcaps); 3387 LIMIT_CAPS(switchcaps); 3388 LIMIT_CAPS(niccaps); 3389 LIMIT_CAPS(toecaps); 3390 LIMIT_CAPS(rdmacaps); 3391 LIMIT_CAPS(cryptocaps); 3392 LIMIT_CAPS(iscsicaps); 3393 LIMIT_CAPS(fcoecaps); 3394 #undef LIMIT_CAPS 3395 3396 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3397 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3398 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3399 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3400 if (rc != 0) { 3401 device_printf(sc->dev, 3402 "failed to process config file: %d.\n", rc); 3403 } 3404 done: 3405 if (cfg != NULL) 3406 firmware_put(cfg, FIRMWARE_UNLOAD); 3407 return (rc); 3408 } 3409 3410 /* 3411 * Retrieve parameters that are needed (or nice to have) very early. 3412 */ 3413 static int 3414 get_params__pre_init(struct adapter *sc) 3415 { 3416 int rc; 3417 uint32_t param[2], val[2]; 3418 3419 t4_get_version_info(sc); 3420 3421 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3422 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3423 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3424 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3425 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3426 3427 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3428 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3429 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3430 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3431 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3432 3433 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3434 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3435 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3436 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3437 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3438 3439 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3440 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3441 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3442 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3443 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3444 3445 param[0] = FW_PARAM_DEV(PORTVEC); 3446 param[1] = FW_PARAM_DEV(CCLK); 3447 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3448 if (rc != 0) { 3449 device_printf(sc->dev, 3450 "failed to query parameters (pre_init): %d.\n", rc); 3451 return (rc); 3452 } 3453 3454 sc->params.portvec = val[0]; 3455 sc->params.nports = bitcount32(val[0]); 3456 sc->params.vpd.cclk = val[1]; 3457 3458 /* Read device log parameters. */ 3459 rc = -t4_init_devlog_params(sc, 1); 3460 if (rc == 0) 3461 fixup_devlog_params(sc); 3462 else { 3463 device_printf(sc->dev, 3464 "failed to get devlog parameters: %d.\n", rc); 3465 rc = 0; /* devlog isn't critical for device operation */ 3466 } 3467 3468 return (rc); 3469 } 3470 3471 /* 3472 * Retrieve various parameters that are of interest to the driver. The device 3473 * has been initialized by the firmware at this point. 3474 */ 3475 static int 3476 get_params__post_init(struct adapter *sc) 3477 { 3478 int rc; 3479 uint32_t param[7], val[7]; 3480 struct fw_caps_config_cmd caps; 3481 3482 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3483 param[1] = FW_PARAM_PFVF(EQ_START); 3484 param[2] = FW_PARAM_PFVF(FILTER_START); 3485 param[3] = FW_PARAM_PFVF(FILTER_END); 3486 param[4] = FW_PARAM_PFVF(L2T_START); 3487 param[5] = FW_PARAM_PFVF(L2T_END); 3488 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3489 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 3490 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 3491 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 3492 if (rc != 0) { 3493 device_printf(sc->dev, 3494 "failed to query parameters (post_init): %d.\n", rc); 3495 return (rc); 3496 } 3497 3498 sc->sge.iq_start = val[0]; 3499 sc->sge.eq_start = val[1]; 3500 sc->tids.ftid_base = val[2]; 3501 sc->tids.nftids = val[3] - val[2] + 1; 3502 sc->params.ftid_min = val[2]; 3503 sc->params.ftid_max = val[3]; 3504 sc->vres.l2t.start = val[4]; 3505 sc->vres.l2t.size = val[5] - val[4] + 1; 3506 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3507 ("%s: L2 table size (%u) larger than expected (%u)", 3508 __func__, sc->vres.l2t.size, L2T_SIZE)); 3509 sc->params.core_vdd = val[6]; 3510 3511 /* 3512 * MPSBGMAP is queried separately because only recent firmwares support 3513 * it as a parameter and we don't want the compound query above to fail 3514 * on older firmwares. 3515 */ 3516 param[0] = FW_PARAM_DEV(MPSBGMAP); 3517 val[0] = 0; 3518 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3519 if (rc == 0) 3520 sc->params.mps_bg_map = val[0]; 3521 else 3522 sc->params.mps_bg_map = 0; 3523 3524 /* get capabilites */ 3525 bzero(&caps, sizeof(caps)); 3526 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3527 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3528 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3529 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3530 if (rc != 0) { 3531 device_printf(sc->dev, 3532 "failed to get card capabilities: %d.\n", rc); 3533 return (rc); 3534 } 3535 3536 #define READ_CAPS(x) do { \ 3537 sc->x = htobe16(caps.x); \ 3538 } while (0) 3539 READ_CAPS(nbmcaps); 3540 READ_CAPS(linkcaps); 3541 READ_CAPS(switchcaps); 3542 READ_CAPS(niccaps); 3543 READ_CAPS(toecaps); 3544 READ_CAPS(rdmacaps); 3545 READ_CAPS(cryptocaps); 3546 READ_CAPS(iscsicaps); 3547 READ_CAPS(fcoecaps); 3548 3549 /* 3550 * The firmware attempts memfree TOE configuration for -SO cards and 3551 * will report toecaps=0 if it runs out of resources (this depends on 3552 * the config file). It may not report 0 for other capabilities 3553 * dependent on the TOE in this case. Set them to 0 here so that the 3554 * driver doesn't bother tracking resources that will never be used. 3555 */ 3556 if (sc->toecaps == 0) { 3557 sc->iscsicaps = 0; 3558 sc->rdmacaps = 0; 3559 } 3560 3561 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 3562 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 3563 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 3564 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3565 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 3566 if (rc != 0) { 3567 device_printf(sc->dev, 3568 "failed to query NIC parameters: %d.\n", rc); 3569 return (rc); 3570 } 3571 sc->tids.etid_base = val[0]; 3572 sc->params.etid_min = val[0]; 3573 sc->tids.netids = val[1] - val[0] + 1; 3574 sc->params.netids = sc->tids.netids; 3575 sc->params.eo_wr_cred = val[2]; 3576 sc->params.ethoffload = 1; 3577 } 3578 3579 if (sc->toecaps) { 3580 /* query offload-related parameters */ 3581 param[0] = FW_PARAM_DEV(NTID); 3582 param[1] = FW_PARAM_PFVF(SERVER_START); 3583 param[2] = FW_PARAM_PFVF(SERVER_END); 3584 param[3] = FW_PARAM_PFVF(TDDP_START); 3585 param[4] = FW_PARAM_PFVF(TDDP_END); 3586 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3587 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3588 if (rc != 0) { 3589 device_printf(sc->dev, 3590 "failed to query TOE parameters: %d.\n", rc); 3591 return (rc); 3592 } 3593 sc->tids.ntids = val[0]; 3594 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3595 sc->tids.stid_base = val[1]; 3596 sc->tids.nstids = val[2] - val[1] + 1; 3597 sc->vres.ddp.start = val[3]; 3598 sc->vres.ddp.size = val[4] - val[3] + 1; 3599 sc->params.ofldq_wr_cred = val[5]; 3600 sc->params.offload = 1; 3601 } 3602 if (sc->rdmacaps) { 3603 param[0] = FW_PARAM_PFVF(STAG_START); 3604 param[1] = FW_PARAM_PFVF(STAG_END); 3605 param[2] = FW_PARAM_PFVF(RQ_START); 3606 param[3] = FW_PARAM_PFVF(RQ_END); 3607 param[4] = FW_PARAM_PFVF(PBL_START); 3608 param[5] = FW_PARAM_PFVF(PBL_END); 3609 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3610 if (rc != 0) { 3611 device_printf(sc->dev, 3612 "failed to query RDMA parameters(1): %d.\n", rc); 3613 return (rc); 3614 } 3615 sc->vres.stag.start = val[0]; 3616 sc->vres.stag.size = val[1] - val[0] + 1; 3617 sc->vres.rq.start = val[2]; 3618 sc->vres.rq.size = val[3] - val[2] + 1; 3619 sc->vres.pbl.start = val[4]; 3620 sc->vres.pbl.size = val[5] - val[4] + 1; 3621 3622 param[0] = FW_PARAM_PFVF(SQRQ_START); 3623 param[1] = FW_PARAM_PFVF(SQRQ_END); 3624 param[2] = FW_PARAM_PFVF(CQ_START); 3625 param[3] = FW_PARAM_PFVF(CQ_END); 3626 param[4] = FW_PARAM_PFVF(OCQ_START); 3627 param[5] = FW_PARAM_PFVF(OCQ_END); 3628 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3629 if (rc != 0) { 3630 device_printf(sc->dev, 3631 "failed to query RDMA parameters(2): %d.\n", rc); 3632 return (rc); 3633 } 3634 sc->vres.qp.start = val[0]; 3635 sc->vres.qp.size = val[1] - val[0] + 1; 3636 sc->vres.cq.start = val[2]; 3637 sc->vres.cq.size = val[3] - val[2] + 1; 3638 sc->vres.ocq.start = val[4]; 3639 sc->vres.ocq.size = val[5] - val[4] + 1; 3640 3641 param[0] = FW_PARAM_PFVF(SRQ_START); 3642 param[1] = FW_PARAM_PFVF(SRQ_END); 3643 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 3644 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 3645 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 3646 if (rc != 0) { 3647 device_printf(sc->dev, 3648 "failed to query RDMA parameters(3): %d.\n", rc); 3649 return (rc); 3650 } 3651 sc->vres.srq.start = val[0]; 3652 sc->vres.srq.size = val[1] - val[0] + 1; 3653 sc->params.max_ordird_qp = val[2]; 3654 sc->params.max_ird_adapter = val[3]; 3655 } 3656 if (sc->iscsicaps) { 3657 param[0] = FW_PARAM_PFVF(ISCSI_START); 3658 param[1] = FW_PARAM_PFVF(ISCSI_END); 3659 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3660 if (rc != 0) { 3661 device_printf(sc->dev, 3662 "failed to query iSCSI parameters: %d.\n", rc); 3663 return (rc); 3664 } 3665 sc->vres.iscsi.start = val[0]; 3666 sc->vres.iscsi.size = val[1] - val[0] + 1; 3667 } 3668 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 3669 param[0] = FW_PARAM_PFVF(TLS_START); 3670 param[1] = FW_PARAM_PFVF(TLS_END); 3671 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3672 if (rc != 0) { 3673 device_printf(sc->dev, 3674 "failed to query TLS parameters: %d.\n", rc); 3675 return (rc); 3676 } 3677 sc->vres.key.start = val[0]; 3678 sc->vres.key.size = val[1] - val[0] + 1; 3679 } 3680 3681 t4_init_sge_params(sc); 3682 3683 /* 3684 * We've got the params we wanted to query via the firmware. Now grab 3685 * some others directly from the chip. 3686 */ 3687 rc = t4_read_chip_settings(sc); 3688 3689 return (rc); 3690 } 3691 3692 static int 3693 set_params__post_init(struct adapter *sc) 3694 { 3695 uint32_t param, val; 3696 #ifdef TCP_OFFLOAD 3697 int i, v, shift; 3698 #endif 3699 3700 /* ask for encapsulated CPLs */ 3701 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3702 val = 1; 3703 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3704 3705 #ifdef TCP_OFFLOAD 3706 /* 3707 * Override the TOE timers with user provided tunables. This is not the 3708 * recommended way to change the timers (the firmware config file is) so 3709 * these tunables are not documented. 3710 * 3711 * All the timer tunables are in microseconds. 3712 */ 3713 if (t4_toe_keepalive_idle != 0) { 3714 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 3715 v &= M_KEEPALIVEIDLE; 3716 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 3717 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 3718 } 3719 if (t4_toe_keepalive_interval != 0) { 3720 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 3721 v &= M_KEEPALIVEINTVL; 3722 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 3723 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 3724 } 3725 if (t4_toe_keepalive_count != 0) { 3726 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 3727 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 3728 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 3729 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 3730 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 3731 } 3732 if (t4_toe_rexmt_min != 0) { 3733 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 3734 v &= M_RXTMIN; 3735 t4_set_reg_field(sc, A_TP_RXT_MIN, 3736 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 3737 } 3738 if (t4_toe_rexmt_max != 0) { 3739 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 3740 v &= M_RXTMAX; 3741 t4_set_reg_field(sc, A_TP_RXT_MAX, 3742 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 3743 } 3744 if (t4_toe_rexmt_count != 0) { 3745 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 3746 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 3747 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 3748 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 3749 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 3750 } 3751 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 3752 if (t4_toe_rexmt_backoff[i] != -1) { 3753 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 3754 shift = (i & 3) << 3; 3755 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 3756 M_TIMERBACKOFFINDEX0 << shift, v << shift); 3757 } 3758 } 3759 #endif 3760 return (0); 3761 } 3762 3763 #undef FW_PARAM_PFVF 3764 #undef FW_PARAM_DEV 3765 3766 static void 3767 t4_set_desc(struct adapter *sc) 3768 { 3769 char buf[128]; 3770 struct adapter_params *p = &sc->params; 3771 3772 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 3773 3774 device_set_desc_copy(sc->dev, buf); 3775 } 3776 3777 static void 3778 build_medialist(struct port_info *pi, struct ifmedia *media) 3779 { 3780 int m; 3781 3782 PORT_LOCK_ASSERT_OWNED(pi); 3783 3784 ifmedia_removeall(media); 3785 3786 /* 3787 * XXX: Would it be better to ifmedia_add all 4 combinations of pause 3788 * settings for every speed instead of just txpause|rxpause? ifconfig 3789 * media display looks much better if autoselect is the only case where 3790 * ifm_current is different from ifm_active. If the user picks anything 3791 * except txpause|rxpause the display is ugly. 3792 */ 3793 m = IFM_ETHER | IFM_FDX | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 3794 3795 switch(pi->port_type) { 3796 case FW_PORT_TYPE_BT_XFI: 3797 case FW_PORT_TYPE_BT_XAUI: 3798 ifmedia_add(media, m | IFM_10G_T, 0, NULL); 3799 /* fall through */ 3800 3801 case FW_PORT_TYPE_BT_SGMII: 3802 ifmedia_add(media, m | IFM_1000_T, 0, NULL); 3803 ifmedia_add(media, m | IFM_100_TX, 0, NULL); 3804 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL); 3805 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 3806 break; 3807 3808 case FW_PORT_TYPE_CX4: 3809 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL); 3810 ifmedia_set(media, m | IFM_10G_CX4); 3811 break; 3812 3813 case FW_PORT_TYPE_QSFP_10G: 3814 case FW_PORT_TYPE_SFP: 3815 case FW_PORT_TYPE_FIBER_XFI: 3816 case FW_PORT_TYPE_FIBER_XAUI: 3817 switch (pi->mod_type) { 3818 3819 case FW_PORT_MOD_TYPE_LR: 3820 ifmedia_add(media, m | IFM_10G_LR, 0, NULL); 3821 ifmedia_set(media, m | IFM_10G_LR); 3822 break; 3823 3824 case FW_PORT_MOD_TYPE_SR: 3825 ifmedia_add(media, m | IFM_10G_SR, 0, NULL); 3826 ifmedia_set(media, m | IFM_10G_SR); 3827 break; 3828 3829 case FW_PORT_MOD_TYPE_LRM: 3830 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL); 3831 ifmedia_set(media, m | IFM_10G_LRM); 3832 break; 3833 3834 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3835 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3836 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL); 3837 ifmedia_set(media, m | IFM_10G_TWINAX); 3838 break; 3839 3840 case FW_PORT_MOD_TYPE_NONE: 3841 m &= ~IFM_FDX; 3842 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3843 ifmedia_set(media, m | IFM_NONE); 3844 break; 3845 3846 case FW_PORT_MOD_TYPE_NA: 3847 case FW_PORT_MOD_TYPE_ER: 3848 default: 3849 device_printf(pi->dev, 3850 "unknown port_type (%d), mod_type (%d)\n", 3851 pi->port_type, pi->mod_type); 3852 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3853 ifmedia_set(media, m | IFM_UNKNOWN); 3854 break; 3855 } 3856 break; 3857 3858 case FW_PORT_TYPE_CR_QSFP: 3859 case FW_PORT_TYPE_SFP28: 3860 case FW_PORT_TYPE_KR_SFP28: 3861 switch (pi->mod_type) { 3862 3863 case FW_PORT_MOD_TYPE_SR: 3864 ifmedia_add(media, m | IFM_25G_SR, 0, NULL); 3865 ifmedia_set(media, m | IFM_25G_SR); 3866 break; 3867 3868 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3869 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3870 ifmedia_add(media, m | IFM_25G_CR, 0, NULL); 3871 ifmedia_set(media, m | IFM_25G_CR); 3872 break; 3873 3874 case FW_PORT_MOD_TYPE_NONE: 3875 m &= ~IFM_FDX; 3876 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3877 ifmedia_set(media, m | IFM_NONE); 3878 break; 3879 3880 default: 3881 device_printf(pi->dev, 3882 "unknown port_type (%d), mod_type (%d)\n", 3883 pi->port_type, pi->mod_type); 3884 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3885 ifmedia_set(media, m | IFM_UNKNOWN); 3886 break; 3887 } 3888 break; 3889 3890 case FW_PORT_TYPE_QSFP: 3891 switch (pi->mod_type) { 3892 3893 case FW_PORT_MOD_TYPE_LR: 3894 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL); 3895 ifmedia_set(media, m | IFM_40G_LR4); 3896 break; 3897 3898 case FW_PORT_MOD_TYPE_SR: 3899 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL); 3900 ifmedia_set(media, m | IFM_40G_SR4); 3901 break; 3902 3903 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3904 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3905 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL); 3906 ifmedia_set(media, m | IFM_40G_CR4); 3907 break; 3908 3909 case FW_PORT_MOD_TYPE_NONE: 3910 m &= ~IFM_FDX; 3911 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3912 ifmedia_set(media, m | IFM_NONE); 3913 break; 3914 3915 default: 3916 device_printf(pi->dev, 3917 "unknown port_type (%d), mod_type (%d)\n", 3918 pi->port_type, pi->mod_type); 3919 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3920 ifmedia_set(media, m | IFM_UNKNOWN); 3921 break; 3922 } 3923 break; 3924 3925 case FW_PORT_TYPE_KR4_100G: 3926 case FW_PORT_TYPE_CR4_QSFP: 3927 switch (pi->mod_type) { 3928 3929 case FW_PORT_MOD_TYPE_LR: 3930 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL); 3931 ifmedia_set(media, m | IFM_100G_LR4); 3932 break; 3933 3934 case FW_PORT_MOD_TYPE_SR: 3935 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL); 3936 ifmedia_set(media, m | IFM_100G_SR4); 3937 break; 3938 3939 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3940 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3941 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL); 3942 ifmedia_set(media, m | IFM_100G_CR4); 3943 break; 3944 3945 case FW_PORT_MOD_TYPE_NONE: 3946 m &= ~IFM_FDX; 3947 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3948 ifmedia_set(media, m | IFM_NONE); 3949 break; 3950 3951 default: 3952 device_printf(pi->dev, 3953 "unknown port_type (%d), mod_type (%d)\n", 3954 pi->port_type, pi->mod_type); 3955 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3956 ifmedia_set(media, m | IFM_UNKNOWN); 3957 break; 3958 } 3959 break; 3960 3961 default: 3962 device_printf(pi->dev, 3963 "unknown port_type (%d), mod_type (%d)\n", pi->port_type, 3964 pi->mod_type); 3965 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3966 ifmedia_set(media, m | IFM_UNKNOWN); 3967 break; 3968 } 3969 } 3970 3971 /* 3972 * Update all the requested_* fields in the link config and then send a mailbox 3973 * command to apply the settings. 3974 */ 3975 static void 3976 init_l1cfg(struct port_info *pi) 3977 { 3978 struct adapter *sc = pi->adapter; 3979 struct link_config *lc = &pi->link_cfg; 3980 int rc; 3981 3982 ASSERT_SYNCHRONIZED_OP(sc); 3983 3984 if (t4_autoneg != 0 && lc->supported & FW_PORT_CAP_ANEG) { 3985 lc->requested_aneg = AUTONEG_ENABLE; 3986 lc->requested_speed = 0; 3987 } else { 3988 lc->requested_aneg = AUTONEG_DISABLE; 3989 lc->requested_speed = port_top_speed(pi); /* in Gbps */ 3990 } 3991 3992 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX); 3993 3994 if (t4_fec != -1) { 3995 lc->requested_fec = t4_fec & (FEC_RS | FEC_BASER_RS | 3996 FEC_RESERVED); 3997 } else { 3998 /* Use the suggested value provided by the firmware in acaps */ 3999 if (lc->advertising & FW_PORT_CAP_FEC_RS) 4000 lc->requested_fec = FEC_RS; 4001 else if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS) 4002 lc->requested_fec = FEC_BASER_RS; 4003 else if (lc->advertising & FW_PORT_CAP_FEC_RESERVED) 4004 lc->requested_fec = FEC_RESERVED; 4005 else 4006 lc->requested_fec = 0; 4007 } 4008 4009 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4010 if (rc != 0) { 4011 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4012 } else { 4013 lc->fc = lc->requested_fc; 4014 lc->fec = lc->requested_fec; 4015 } 4016 } 4017 4018 #define FW_MAC_EXACT_CHUNK 7 4019 4020 /* 4021 * Program the port's XGMAC based on parameters in ifnet. The caller also 4022 * indicates which parameters should be programmed (the rest are left alone). 4023 */ 4024 int 4025 update_mac_settings(struct ifnet *ifp, int flags) 4026 { 4027 int rc = 0; 4028 struct vi_info *vi = ifp->if_softc; 4029 struct port_info *pi = vi->pi; 4030 struct adapter *sc = pi->adapter; 4031 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4032 4033 ASSERT_SYNCHRONIZED_OP(sc); 4034 KASSERT(flags, ("%s: not told what to update.", __func__)); 4035 4036 if (flags & XGMAC_MTU) 4037 mtu = ifp->if_mtu; 4038 4039 if (flags & XGMAC_PROMISC) 4040 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4041 4042 if (flags & XGMAC_ALLMULTI) 4043 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4044 4045 if (flags & XGMAC_VLANEX) 4046 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4047 4048 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4049 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4050 allmulti, 1, vlanex, false); 4051 if (rc) { 4052 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4053 rc); 4054 return (rc); 4055 } 4056 } 4057 4058 if (flags & XGMAC_UCADDR) { 4059 uint8_t ucaddr[ETHER_ADDR_LEN]; 4060 4061 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4062 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4063 ucaddr, true, true); 4064 if (rc < 0) { 4065 rc = -rc; 4066 if_printf(ifp, "change_mac failed: %d\n", rc); 4067 return (rc); 4068 } else { 4069 vi->xact_addr_filt = rc; 4070 rc = 0; 4071 } 4072 } 4073 4074 if (flags & XGMAC_MCADDRS) { 4075 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4076 int del = 1; 4077 uint64_t hash = 0; 4078 struct ifmultiaddr *ifma; 4079 int i = 0, j; 4080 4081 if_maddr_rlock(ifp); 4082 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4083 if (ifma->ifma_addr->sa_family != AF_LINK) 4084 continue; 4085 mcaddr[i] = 4086 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4087 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4088 i++; 4089 4090 if (i == FW_MAC_EXACT_CHUNK) { 4091 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4092 del, i, mcaddr, NULL, &hash, 0); 4093 if (rc < 0) { 4094 rc = -rc; 4095 for (j = 0; j < i; j++) { 4096 if_printf(ifp, 4097 "failed to add mc address" 4098 " %02x:%02x:%02x:" 4099 "%02x:%02x:%02x rc=%d\n", 4100 mcaddr[j][0], mcaddr[j][1], 4101 mcaddr[j][2], mcaddr[j][3], 4102 mcaddr[j][4], mcaddr[j][5], 4103 rc); 4104 } 4105 goto mcfail; 4106 } 4107 del = 0; 4108 i = 0; 4109 } 4110 } 4111 if (i > 0) { 4112 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4113 mcaddr, NULL, &hash, 0); 4114 if (rc < 0) { 4115 rc = -rc; 4116 for (j = 0; j < i; j++) { 4117 if_printf(ifp, 4118 "failed to add mc address" 4119 " %02x:%02x:%02x:" 4120 "%02x:%02x:%02x rc=%d\n", 4121 mcaddr[j][0], mcaddr[j][1], 4122 mcaddr[j][2], mcaddr[j][3], 4123 mcaddr[j][4], mcaddr[j][5], 4124 rc); 4125 } 4126 goto mcfail; 4127 } 4128 } 4129 4130 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4131 if (rc != 0) 4132 if_printf(ifp, "failed to set mc address hash: %d", rc); 4133 mcfail: 4134 if_maddr_runlock(ifp); 4135 } 4136 4137 return (rc); 4138 } 4139 4140 /* 4141 * {begin|end}_synchronized_op must be called from the same thread. 4142 */ 4143 int 4144 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4145 char *wmesg) 4146 { 4147 int rc, pri; 4148 4149 #ifdef WITNESS 4150 /* the caller thinks it's ok to sleep, but is it really? */ 4151 if (flags & SLEEP_OK) 4152 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4153 "begin_synchronized_op"); 4154 #endif 4155 4156 if (INTR_OK) 4157 pri = PCATCH; 4158 else 4159 pri = 0; 4160 4161 ADAPTER_LOCK(sc); 4162 for (;;) { 4163 4164 if (vi && IS_DOOMED(vi)) { 4165 rc = ENXIO; 4166 goto done; 4167 } 4168 4169 if (!IS_BUSY(sc)) { 4170 rc = 0; 4171 break; 4172 } 4173 4174 if (!(flags & SLEEP_OK)) { 4175 rc = EBUSY; 4176 goto done; 4177 } 4178 4179 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4180 rc = EINTR; 4181 goto done; 4182 } 4183 } 4184 4185 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4186 SET_BUSY(sc); 4187 #ifdef INVARIANTS 4188 sc->last_op = wmesg; 4189 sc->last_op_thr = curthread; 4190 sc->last_op_flags = flags; 4191 #endif 4192 4193 done: 4194 if (!(flags & HOLD_LOCK) || rc) 4195 ADAPTER_UNLOCK(sc); 4196 4197 return (rc); 4198 } 4199 4200 /* 4201 * Tell if_ioctl and if_init that the VI is going away. This is 4202 * special variant of begin_synchronized_op and must be paired with a 4203 * call to end_synchronized_op. 4204 */ 4205 void 4206 doom_vi(struct adapter *sc, struct vi_info *vi) 4207 { 4208 4209 ADAPTER_LOCK(sc); 4210 SET_DOOMED(vi); 4211 wakeup(&sc->flags); 4212 while (IS_BUSY(sc)) 4213 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4214 SET_BUSY(sc); 4215 #ifdef INVARIANTS 4216 sc->last_op = "t4detach"; 4217 sc->last_op_thr = curthread; 4218 sc->last_op_flags = 0; 4219 #endif 4220 ADAPTER_UNLOCK(sc); 4221 } 4222 4223 /* 4224 * {begin|end}_synchronized_op must be called from the same thread. 4225 */ 4226 void 4227 end_synchronized_op(struct adapter *sc, int flags) 4228 { 4229 4230 if (flags & LOCK_HELD) 4231 ADAPTER_LOCK_ASSERT_OWNED(sc); 4232 else 4233 ADAPTER_LOCK(sc); 4234 4235 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 4236 CLR_BUSY(sc); 4237 wakeup(&sc->flags); 4238 ADAPTER_UNLOCK(sc); 4239 } 4240 4241 static int 4242 cxgbe_init_synchronized(struct vi_info *vi) 4243 { 4244 struct port_info *pi = vi->pi; 4245 struct adapter *sc = pi->adapter; 4246 struct ifnet *ifp = vi->ifp; 4247 int rc = 0, i; 4248 struct sge_txq *txq; 4249 4250 ASSERT_SYNCHRONIZED_OP(sc); 4251 4252 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4253 return (0); /* already running */ 4254 4255 if (!(sc->flags & FULL_INIT_DONE) && 4256 ((rc = adapter_full_init(sc)) != 0)) 4257 return (rc); /* error message displayed already */ 4258 4259 if (!(vi->flags & VI_INIT_DONE) && 4260 ((rc = vi_full_init(vi)) != 0)) 4261 return (rc); /* error message displayed already */ 4262 4263 rc = update_mac_settings(ifp, XGMAC_ALL); 4264 if (rc) 4265 goto done; /* error message displayed already */ 4266 4267 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 4268 if (rc != 0) { 4269 if_printf(ifp, "enable_vi failed: %d\n", rc); 4270 goto done; 4271 } 4272 4273 /* 4274 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 4275 * if this changes. 4276 */ 4277 4278 for_each_txq(vi, i, txq) { 4279 TXQ_LOCK(txq); 4280 txq->eq.flags |= EQ_ENABLED; 4281 TXQ_UNLOCK(txq); 4282 } 4283 4284 /* 4285 * The first iq of the first port to come up is used for tracing. 4286 */ 4287 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 4288 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 4289 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4290 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4291 V_QUEUENUMBER(sc->traceq)); 4292 pi->flags |= HAS_TRACEQ; 4293 } 4294 4295 /* all ok */ 4296 PORT_LOCK(pi); 4297 if (pi->up_vis++ == 0) { 4298 t4_update_port_info(pi); 4299 build_medialist(pi, &pi->media); 4300 init_l1cfg(pi); 4301 } 4302 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4303 4304 if (pi->nvi > 1 || sc->flags & IS_VF) 4305 callout_reset(&vi->tick, hz, vi_tick, vi); 4306 else 4307 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4308 PORT_UNLOCK(pi); 4309 done: 4310 if (rc != 0) 4311 cxgbe_uninit_synchronized(vi); 4312 4313 return (rc); 4314 } 4315 4316 /* 4317 * Idempotent. 4318 */ 4319 static int 4320 cxgbe_uninit_synchronized(struct vi_info *vi) 4321 { 4322 struct port_info *pi = vi->pi; 4323 struct adapter *sc = pi->adapter; 4324 struct ifnet *ifp = vi->ifp; 4325 int rc, i; 4326 struct sge_txq *txq; 4327 4328 ASSERT_SYNCHRONIZED_OP(sc); 4329 4330 if (!(vi->flags & VI_INIT_DONE)) { 4331 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING), 4332 ("uninited VI is running")); 4333 return (0); 4334 } 4335 4336 /* 4337 * Disable the VI so that all its data in either direction is discarded 4338 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4339 * tick) intact as the TP can deliver negative advice or data that it's 4340 * holding in its RAM (for an offloaded connection) even after the VI is 4341 * disabled. 4342 */ 4343 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4344 if (rc) { 4345 if_printf(ifp, "disable_vi failed: %d\n", rc); 4346 return (rc); 4347 } 4348 4349 for_each_txq(vi, i, txq) { 4350 TXQ_LOCK(txq); 4351 txq->eq.flags &= ~EQ_ENABLED; 4352 TXQ_UNLOCK(txq); 4353 } 4354 4355 PORT_LOCK(pi); 4356 if (pi->nvi > 1 || sc->flags & IS_VF) 4357 callout_stop(&vi->tick); 4358 else 4359 callout_stop(&pi->tick); 4360 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4361 PORT_UNLOCK(pi); 4362 return (0); 4363 } 4364 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4365 pi->up_vis--; 4366 if (pi->up_vis > 0) { 4367 PORT_UNLOCK(pi); 4368 return (0); 4369 } 4370 PORT_UNLOCK(pi); 4371 4372 pi->link_cfg.link_ok = 0; 4373 pi->link_cfg.speed = 0; 4374 pi->link_cfg.link_down_rc = 255; 4375 t4_os_link_changed(pi); 4376 pi->old_link_cfg = pi->link_cfg; 4377 4378 return (0); 4379 } 4380 4381 /* 4382 * It is ok for this function to fail midway and return right away. t4_detach 4383 * will walk the entire sc->irq list and clean up whatever is valid. 4384 */ 4385 int 4386 t4_setup_intr_handlers(struct adapter *sc) 4387 { 4388 int rc, rid, p, q, v; 4389 char s[8]; 4390 struct irq *irq; 4391 struct port_info *pi; 4392 struct vi_info *vi; 4393 struct sge *sge = &sc->sge; 4394 struct sge_rxq *rxq; 4395 #ifdef TCP_OFFLOAD 4396 struct sge_ofld_rxq *ofld_rxq; 4397 #endif 4398 #ifdef DEV_NETMAP 4399 struct sge_nm_rxq *nm_rxq; 4400 #endif 4401 #ifdef RSS 4402 int nbuckets = rss_getnumbuckets(); 4403 #endif 4404 4405 /* 4406 * Setup interrupts. 4407 */ 4408 irq = &sc->irq[0]; 4409 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4410 if (forwarding_intr_to_fwq(sc)) 4411 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4412 4413 /* Multiple interrupts. */ 4414 if (sc->flags & IS_VF) 4415 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4416 ("%s: too few intr.", __func__)); 4417 else 4418 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4419 ("%s: too few intr.", __func__)); 4420 4421 /* The first one is always error intr on PFs */ 4422 if (!(sc->flags & IS_VF)) { 4423 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4424 if (rc != 0) 4425 return (rc); 4426 irq++; 4427 rid++; 4428 } 4429 4430 /* The second one is always the firmware event queue (first on VFs) */ 4431 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4432 if (rc != 0) 4433 return (rc); 4434 irq++; 4435 rid++; 4436 4437 for_each_port(sc, p) { 4438 pi = sc->port[p]; 4439 for_each_vi(pi, v, vi) { 4440 vi->first_intr = rid - 1; 4441 4442 if (vi->nnmrxq > 0) { 4443 int n = max(vi->nrxq, vi->nnmrxq); 4444 4445 rxq = &sge->rxq[vi->first_rxq]; 4446 #ifdef DEV_NETMAP 4447 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4448 #endif 4449 for (q = 0; q < n; q++) { 4450 snprintf(s, sizeof(s), "%x%c%x", p, 4451 'a' + v, q); 4452 if (q < vi->nrxq) 4453 irq->rxq = rxq++; 4454 #ifdef DEV_NETMAP 4455 if (q < vi->nnmrxq) 4456 irq->nm_rxq = nm_rxq++; 4457 #endif 4458 rc = t4_alloc_irq(sc, irq, rid, 4459 t4_vi_intr, irq, s); 4460 if (rc != 0) 4461 return (rc); 4462 #ifdef RSS 4463 if (q < vi->nrxq) { 4464 bus_bind_intr(sc->dev, irq->res, 4465 rss_getcpu(q % nbuckets)); 4466 } 4467 #endif 4468 irq++; 4469 rid++; 4470 vi->nintr++; 4471 } 4472 } else { 4473 for_each_rxq(vi, q, rxq) { 4474 snprintf(s, sizeof(s), "%x%c%x", p, 4475 'a' + v, q); 4476 rc = t4_alloc_irq(sc, irq, rid, 4477 t4_intr, rxq, s); 4478 if (rc != 0) 4479 return (rc); 4480 #ifdef RSS 4481 bus_bind_intr(sc->dev, irq->res, 4482 rss_getcpu(q % nbuckets)); 4483 #endif 4484 irq++; 4485 rid++; 4486 vi->nintr++; 4487 } 4488 } 4489 #ifdef TCP_OFFLOAD 4490 for_each_ofld_rxq(vi, q, ofld_rxq) { 4491 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 4492 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 4493 ofld_rxq, s); 4494 if (rc != 0) 4495 return (rc); 4496 irq++; 4497 rid++; 4498 vi->nintr++; 4499 } 4500 #endif 4501 } 4502 } 4503 MPASS(irq == &sc->irq[sc->intr_count]); 4504 4505 return (0); 4506 } 4507 4508 int 4509 adapter_full_init(struct adapter *sc) 4510 { 4511 int rc, i; 4512 #ifdef RSS 4513 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4514 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4515 #endif 4516 4517 ASSERT_SYNCHRONIZED_OP(sc); 4518 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4519 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 4520 ("%s: FULL_INIT_DONE already", __func__)); 4521 4522 /* 4523 * queues that belong to the adapter (not any particular port). 4524 */ 4525 rc = t4_setup_adapter_queues(sc); 4526 if (rc != 0) 4527 goto done; 4528 4529 for (i = 0; i < nitems(sc->tq); i++) { 4530 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 4531 taskqueue_thread_enqueue, &sc->tq[i]); 4532 if (sc->tq[i] == NULL) { 4533 device_printf(sc->dev, 4534 "failed to allocate task queue %d\n", i); 4535 rc = ENOMEM; 4536 goto done; 4537 } 4538 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 4539 device_get_nameunit(sc->dev), i); 4540 } 4541 #ifdef RSS 4542 MPASS(RSS_KEYSIZE == 40); 4543 rss_getkey((void *)&raw_rss_key[0]); 4544 for (i = 0; i < nitems(rss_key); i++) { 4545 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 4546 } 4547 t4_write_rss_key(sc, &rss_key[0], -1, 1); 4548 #endif 4549 4550 if (!(sc->flags & IS_VF)) 4551 t4_intr_enable(sc); 4552 sc->flags |= FULL_INIT_DONE; 4553 done: 4554 if (rc != 0) 4555 adapter_full_uninit(sc); 4556 4557 return (rc); 4558 } 4559 4560 int 4561 adapter_full_uninit(struct adapter *sc) 4562 { 4563 int i; 4564 4565 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4566 4567 t4_teardown_adapter_queues(sc); 4568 4569 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 4570 taskqueue_free(sc->tq[i]); 4571 sc->tq[i] = NULL; 4572 } 4573 4574 sc->flags &= ~FULL_INIT_DONE; 4575 4576 return (0); 4577 } 4578 4579 #ifdef RSS 4580 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 4581 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 4582 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 4583 RSS_HASHTYPE_RSS_UDP_IPV6) 4584 4585 /* Translates kernel hash types to hardware. */ 4586 static int 4587 hashconfig_to_hashen(int hashconfig) 4588 { 4589 int hashen = 0; 4590 4591 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 4592 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 4593 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 4594 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 4595 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 4596 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4597 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4598 } 4599 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 4600 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4601 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4602 } 4603 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 4604 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4605 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 4606 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4607 4608 return (hashen); 4609 } 4610 4611 /* Translates hardware hash types to kernel. */ 4612 static int 4613 hashen_to_hashconfig(int hashen) 4614 { 4615 int hashconfig = 0; 4616 4617 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 4618 /* 4619 * If UDP hashing was enabled it must have been enabled for 4620 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 4621 * enabling any 4-tuple hash is nonsense configuration. 4622 */ 4623 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4624 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 4625 4626 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4627 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 4628 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4629 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 4630 } 4631 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4632 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 4633 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4634 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 4635 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 4636 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 4637 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 4638 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 4639 4640 return (hashconfig); 4641 } 4642 #endif 4643 4644 int 4645 vi_full_init(struct vi_info *vi) 4646 { 4647 struct adapter *sc = vi->pi->adapter; 4648 struct ifnet *ifp = vi->ifp; 4649 uint16_t *rss; 4650 struct sge_rxq *rxq; 4651 int rc, i, j, hashen; 4652 #ifdef RSS 4653 int nbuckets = rss_getnumbuckets(); 4654 int hashconfig = rss_gethashconfig(); 4655 int extra; 4656 #endif 4657 4658 ASSERT_SYNCHRONIZED_OP(sc); 4659 KASSERT((vi->flags & VI_INIT_DONE) == 0, 4660 ("%s: VI_INIT_DONE already", __func__)); 4661 4662 sysctl_ctx_init(&vi->ctx); 4663 vi->flags |= VI_SYSCTL_CTX; 4664 4665 /* 4666 * Allocate tx/rx/fl queues for this VI. 4667 */ 4668 rc = t4_setup_vi_queues(vi); 4669 if (rc != 0) 4670 goto done; /* error message displayed already */ 4671 4672 /* 4673 * Setup RSS for this VI. Save a copy of the RSS table for later use. 4674 */ 4675 if (vi->nrxq > vi->rss_size) { 4676 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 4677 "some queues will never receive traffic.\n", vi->nrxq, 4678 vi->rss_size); 4679 } else if (vi->rss_size % vi->nrxq) { 4680 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 4681 "expect uneven traffic distribution.\n", vi->nrxq, 4682 vi->rss_size); 4683 } 4684 #ifdef RSS 4685 if (vi->nrxq != nbuckets) { 4686 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 4687 "performance will be impacted.\n", vi->nrxq, nbuckets); 4688 } 4689 #endif 4690 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 4691 for (i = 0; i < vi->rss_size;) { 4692 #ifdef RSS 4693 j = rss_get_indirection_to_bucket(i); 4694 j %= vi->nrxq; 4695 rxq = &sc->sge.rxq[vi->first_rxq + j]; 4696 rss[i++] = rxq->iq.abs_id; 4697 #else 4698 for_each_rxq(vi, j, rxq) { 4699 rss[i++] = rxq->iq.abs_id; 4700 if (i == vi->rss_size) 4701 break; 4702 } 4703 #endif 4704 } 4705 4706 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 4707 vi->rss_size); 4708 if (rc != 0) { 4709 if_printf(ifp, "rss_config failed: %d\n", rc); 4710 goto done; 4711 } 4712 4713 #ifdef RSS 4714 hashen = hashconfig_to_hashen(hashconfig); 4715 4716 /* 4717 * We may have had to enable some hashes even though the global config 4718 * wants them disabled. This is a potential problem that must be 4719 * reported to the user. 4720 */ 4721 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 4722 4723 /* 4724 * If we consider only the supported hash types, then the enabled hashes 4725 * are a superset of the requested hashes. In other words, there cannot 4726 * be any supported hash that was requested but not enabled, but there 4727 * can be hashes that were not requested but had to be enabled. 4728 */ 4729 extra &= SUPPORTED_RSS_HASHTYPES; 4730 MPASS((extra & hashconfig) == 0); 4731 4732 if (extra) { 4733 if_printf(ifp, 4734 "global RSS config (0x%x) cannot be accommodated.\n", 4735 hashconfig); 4736 } 4737 if (extra & RSS_HASHTYPE_RSS_IPV4) 4738 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 4739 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 4740 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 4741 if (extra & RSS_HASHTYPE_RSS_IPV6) 4742 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 4743 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 4744 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 4745 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 4746 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 4747 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 4748 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 4749 #else 4750 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 4751 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 4752 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4753 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 4754 #endif 4755 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0); 4756 if (rc != 0) { 4757 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 4758 goto done; 4759 } 4760 4761 vi->rss = rss; 4762 vi->flags |= VI_INIT_DONE; 4763 done: 4764 if (rc != 0) 4765 vi_full_uninit(vi); 4766 4767 return (rc); 4768 } 4769 4770 /* 4771 * Idempotent. 4772 */ 4773 int 4774 vi_full_uninit(struct vi_info *vi) 4775 { 4776 struct port_info *pi = vi->pi; 4777 struct adapter *sc = pi->adapter; 4778 int i; 4779 struct sge_rxq *rxq; 4780 struct sge_txq *txq; 4781 #ifdef TCP_OFFLOAD 4782 struct sge_ofld_rxq *ofld_rxq; 4783 struct sge_wrq *ofld_txq; 4784 #endif 4785 4786 if (vi->flags & VI_INIT_DONE) { 4787 4788 /* Need to quiesce queues. */ 4789 4790 /* XXX: Only for the first VI? */ 4791 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 4792 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 4793 4794 for_each_txq(vi, i, txq) { 4795 quiesce_txq(sc, txq); 4796 } 4797 4798 #ifdef TCP_OFFLOAD 4799 for_each_ofld_txq(vi, i, ofld_txq) { 4800 quiesce_wrq(sc, ofld_txq); 4801 } 4802 #endif 4803 4804 for_each_rxq(vi, i, rxq) { 4805 quiesce_iq(sc, &rxq->iq); 4806 quiesce_fl(sc, &rxq->fl); 4807 } 4808 4809 #ifdef TCP_OFFLOAD 4810 for_each_ofld_rxq(vi, i, ofld_rxq) { 4811 quiesce_iq(sc, &ofld_rxq->iq); 4812 quiesce_fl(sc, &ofld_rxq->fl); 4813 } 4814 #endif 4815 free(vi->rss, M_CXGBE); 4816 free(vi->nm_rss, M_CXGBE); 4817 } 4818 4819 t4_teardown_vi_queues(vi); 4820 vi->flags &= ~VI_INIT_DONE; 4821 4822 return (0); 4823 } 4824 4825 static void 4826 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 4827 { 4828 struct sge_eq *eq = &txq->eq; 4829 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4830 4831 (void) sc; /* unused */ 4832 4833 #ifdef INVARIANTS 4834 TXQ_LOCK(txq); 4835 MPASS((eq->flags & EQ_ENABLED) == 0); 4836 TXQ_UNLOCK(txq); 4837 #endif 4838 4839 /* Wait for the mp_ring to empty. */ 4840 while (!mp_ring_is_idle(txq->r)) { 4841 mp_ring_check_drainage(txq->r, 0); 4842 pause("rquiesce", 1); 4843 } 4844 4845 /* Then wait for the hardware to finish. */ 4846 while (spg->cidx != htobe16(eq->pidx)) 4847 pause("equiesce", 1); 4848 4849 /* Finally, wait for the driver to reclaim all descriptors. */ 4850 while (eq->cidx != eq->pidx) 4851 pause("dquiesce", 1); 4852 } 4853 4854 static void 4855 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 4856 { 4857 4858 /* XXXTX */ 4859 } 4860 4861 static void 4862 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 4863 { 4864 (void) sc; /* unused */ 4865 4866 /* Synchronize with the interrupt handler */ 4867 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 4868 pause("iqfree", 1); 4869 } 4870 4871 static void 4872 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 4873 { 4874 mtx_lock(&sc->sfl_lock); 4875 FL_LOCK(fl); 4876 fl->flags |= FL_DOOMED; 4877 FL_UNLOCK(fl); 4878 callout_stop(&sc->sfl_callout); 4879 mtx_unlock(&sc->sfl_lock); 4880 4881 KASSERT((fl->flags & FL_STARVING) == 0, 4882 ("%s: still starving", __func__)); 4883 } 4884 4885 static int 4886 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 4887 driver_intr_t *handler, void *arg, char *name) 4888 { 4889 int rc; 4890 4891 irq->rid = rid; 4892 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 4893 RF_SHAREABLE | RF_ACTIVE); 4894 if (irq->res == NULL) { 4895 device_printf(sc->dev, 4896 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 4897 return (ENOMEM); 4898 } 4899 4900 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 4901 NULL, handler, arg, &irq->tag); 4902 if (rc != 0) { 4903 device_printf(sc->dev, 4904 "failed to setup interrupt for rid %d, name %s: %d\n", 4905 rid, name, rc); 4906 } else if (name) 4907 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 4908 4909 return (rc); 4910 } 4911 4912 static int 4913 t4_free_irq(struct adapter *sc, struct irq *irq) 4914 { 4915 if (irq->tag) 4916 bus_teardown_intr(sc->dev, irq->res, irq->tag); 4917 if (irq->res) 4918 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 4919 4920 bzero(irq, sizeof(*irq)); 4921 4922 return (0); 4923 } 4924 4925 static void 4926 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 4927 { 4928 4929 regs->version = chip_id(sc) | chip_rev(sc) << 10; 4930 t4_get_regs(sc, buf, regs->len); 4931 } 4932 4933 #define A_PL_INDIR_CMD 0x1f8 4934 4935 #define S_PL_AUTOINC 31 4936 #define M_PL_AUTOINC 0x1U 4937 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 4938 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 4939 4940 #define S_PL_VFID 20 4941 #define M_PL_VFID 0xffU 4942 #define V_PL_VFID(x) ((x) << S_PL_VFID) 4943 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 4944 4945 #define S_PL_ADDR 0 4946 #define M_PL_ADDR 0xfffffU 4947 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 4948 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 4949 4950 #define A_PL_INDIR_DATA 0x1fc 4951 4952 static uint64_t 4953 read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 4954 { 4955 u32 stats[2]; 4956 4957 mtx_assert(&sc->reg_lock, MA_OWNED); 4958 if (sc->flags & IS_VF) { 4959 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 4960 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 4961 } else { 4962 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4963 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4964 V_PL_ADDR(VF_MPS_REG(reg))); 4965 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 4966 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 4967 } 4968 return (((uint64_t)stats[1]) << 32 | stats[0]); 4969 } 4970 4971 static void 4972 t4_get_vi_stats(struct adapter *sc, unsigned int viid, 4973 struct fw_vi_stats_vf *stats) 4974 { 4975 4976 #define GET_STAT(name) \ 4977 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 4978 4979 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 4980 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 4981 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 4982 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 4983 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 4984 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 4985 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 4986 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 4987 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 4988 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 4989 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 4990 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 4991 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 4992 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 4993 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 4994 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 4995 4996 #undef GET_STAT 4997 } 4998 4999 static void 5000 t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 5001 { 5002 int reg; 5003 5004 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5005 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5006 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5007 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5008 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5009 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5010 } 5011 5012 static void 5013 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5014 { 5015 struct timeval tv; 5016 const struct timeval interval = {0, 250000}; /* 250ms */ 5017 5018 if (!(vi->flags & VI_INIT_DONE)) 5019 return; 5020 5021 getmicrotime(&tv); 5022 timevalsub(&tv, &interval); 5023 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5024 return; 5025 5026 mtx_lock(&sc->reg_lock); 5027 t4_get_vi_stats(sc, vi->viid, &vi->stats); 5028 getmicrotime(&vi->last_refreshed); 5029 mtx_unlock(&sc->reg_lock); 5030 } 5031 5032 static void 5033 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5034 { 5035 u_int i, v, tnl_cong_drops, bg_map; 5036 struct timeval tv; 5037 const struct timeval interval = {0, 250000}; /* 250ms */ 5038 5039 getmicrotime(&tv); 5040 timevalsub(&tv, &interval); 5041 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5042 return; 5043 5044 tnl_cong_drops = 0; 5045 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5046 bg_map = pi->mps_bg_map; 5047 while (bg_map) { 5048 i = ffs(bg_map) - 1; 5049 mtx_lock(&sc->reg_lock); 5050 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5051 A_TP_MIB_TNL_CNG_DROP_0 + i); 5052 mtx_unlock(&sc->reg_lock); 5053 tnl_cong_drops += v; 5054 bg_map &= ~(1 << i); 5055 } 5056 pi->tnl_cong_drops = tnl_cong_drops; 5057 getmicrotime(&pi->last_refreshed); 5058 } 5059 5060 static void 5061 cxgbe_tick(void *arg) 5062 { 5063 struct port_info *pi = arg; 5064 struct adapter *sc = pi->adapter; 5065 5066 PORT_LOCK_ASSERT_OWNED(pi); 5067 cxgbe_refresh_stats(sc, pi); 5068 5069 callout_schedule(&pi->tick, hz); 5070 } 5071 5072 void 5073 vi_tick(void *arg) 5074 { 5075 struct vi_info *vi = arg; 5076 struct adapter *sc = vi->pi->adapter; 5077 5078 vi_refresh_stats(sc, vi); 5079 5080 callout_schedule(&vi->tick, hz); 5081 } 5082 5083 static void 5084 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 5085 { 5086 struct ifnet *vlan; 5087 5088 if (arg != ifp || ifp->if_type != IFT_ETHER) 5089 return; 5090 5091 vlan = VLAN_DEVAT(ifp, vid); 5092 VLAN_SETCOOKIE(vlan, ifp); 5093 } 5094 5095 /* 5096 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5097 */ 5098 static char *caps_decoder[] = { 5099 "\20\001IPMI\002NCSI", /* 0: NBM */ 5100 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5101 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5102 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5103 "\006HASHFILTER\007ETHOFLD", 5104 "\20\001TOE", /* 4: TOE */ 5105 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5106 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5107 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5108 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5109 "\007T10DIF" 5110 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5111 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5112 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5113 "\004PO_INITIATOR\005PO_TARGET", 5114 }; 5115 5116 void 5117 t4_sysctls(struct adapter *sc) 5118 { 5119 struct sysctl_ctx_list *ctx; 5120 struct sysctl_oid *oid; 5121 struct sysctl_oid_list *children, *c0; 5122 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5123 5124 ctx = device_get_sysctl_ctx(sc->dev); 5125 5126 /* 5127 * dev.t4nex.X. 5128 */ 5129 oid = device_get_sysctl_tree(sc->dev); 5130 c0 = children = SYSCTL_CHILDREN(oid); 5131 5132 sc->sc_do_rxcopy = 1; 5133 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5134 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5135 5136 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5137 sc->params.nports, "# of ports"); 5138 5139 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5140 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 5141 sysctl_bitfield, "A", "available doorbells"); 5142 5143 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5144 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5145 5146 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5147 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5148 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5149 "interrupt holdoff timer values (us)"); 5150 5151 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5152 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5153 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5154 "interrupt holdoff packet counter values"); 5155 5156 t4_sge_sysctls(sc, ctx, children); 5157 5158 sc->lro_timeout = 100; 5159 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5160 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5161 5162 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5163 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5164 5165 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5166 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5167 5168 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5169 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5170 5171 if (sc->flags & IS_VF) 5172 return; 5173 5174 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5175 NULL, chip_rev(sc), "chip hardware revision"); 5176 5177 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5178 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5179 5180 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5181 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5182 5183 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5184 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5185 5186 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5187 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5188 5189 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5190 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5191 5192 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5193 sc->er_version, 0, "expansion ROM version"); 5194 5195 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5196 sc->bs_version, 0, "bootstrap firmware version"); 5197 5198 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5199 NULL, sc->params.scfg_vers, "serial config version"); 5200 5201 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5202 NULL, sc->params.vpd_vers, "VPD version"); 5203 5204 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5205 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5206 5207 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5208 sc->cfcsum, "config file checksum"); 5209 5210 #define SYSCTL_CAP(name, n, text) \ 5211 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5212 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \ 5213 sysctl_bitfield, "A", "available " text " capabilities") 5214 5215 SYSCTL_CAP(nbmcaps, 0, "NBM"); 5216 SYSCTL_CAP(linkcaps, 1, "link"); 5217 SYSCTL_CAP(switchcaps, 2, "switch"); 5218 SYSCTL_CAP(niccaps, 3, "NIC"); 5219 SYSCTL_CAP(toecaps, 4, "TCP offload"); 5220 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 5221 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 5222 SYSCTL_CAP(cryptocaps, 7, "crypto"); 5223 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 5224 #undef SYSCTL_CAP 5225 5226 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 5227 NULL, sc->tids.nftids, "number of filters"); 5228 5229 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 5230 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 5231 "chip temperature (in Celsius)"); 5232 5233 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 5234 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 5235 5236 #ifdef SBUF_DRAIN 5237 /* 5238 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 5239 */ 5240 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 5241 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 5242 "logs and miscellaneous information"); 5243 children = SYSCTL_CHILDREN(oid); 5244 5245 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 5246 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5247 sysctl_cctrl, "A", "congestion control"); 5248 5249 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 5250 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5251 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 5252 5253 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 5254 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 5255 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 5256 5257 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 5258 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 5259 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 5260 5261 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 5262 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 5263 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 5264 5265 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 5266 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 5267 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 5268 5269 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 5270 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 5271 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 5272 5273 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 5274 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5275 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 5276 "A", "CIM logic analyzer"); 5277 5278 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 5279 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5280 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 5281 5282 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 5283 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 5284 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 5285 5286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 5287 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 5288 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 5289 5290 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 5291 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 5292 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 5293 5294 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 5295 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 5296 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 5297 5298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 5299 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 5300 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 5301 5302 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 5303 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 5304 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5305 5306 if (chip_id(sc) > CHELSIO_T4) { 5307 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5308 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5309 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5310 5311 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5312 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5313 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5314 } 5315 5316 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5317 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5318 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5319 5320 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5321 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5322 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5323 5324 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5325 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5326 sysctl_cpl_stats, "A", "CPL statistics"); 5327 5328 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5329 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5330 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5331 5332 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5333 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5334 sysctl_devlog, "A", "firmware's device log"); 5335 5336 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5337 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5338 sysctl_fcoe_stats, "A", "FCoE statistics"); 5339 5340 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5341 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5342 sysctl_hw_sched, "A", "hardware scheduler "); 5343 5344 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5345 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5346 sysctl_l2t, "A", "hardware L2 table"); 5347 5348 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5349 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5350 sysctl_lb_stats, "A", "loopback statistics"); 5351 5352 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5353 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5354 sysctl_meminfo, "A", "memory regions"); 5355 5356 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5357 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5358 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5359 "A", "MPS TCAM entries"); 5360 5361 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5362 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5363 sysctl_path_mtus, "A", "path MTUs"); 5364 5365 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5366 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5367 sysctl_pm_stats, "A", "PM statistics"); 5368 5369 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5370 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5371 sysctl_rdma_stats, "A", "RDMA statistics"); 5372 5373 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5374 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5375 sysctl_tcp_stats, "A", "TCP statistics"); 5376 5377 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5378 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5379 sysctl_tids, "A", "TID information"); 5380 5381 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5382 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5383 sysctl_tp_err_stats, "A", "TP error statistics"); 5384 5385 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5386 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5387 "TP logic analyzer event capture mask"); 5388 5389 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5390 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5391 sysctl_tp_la, "A", "TP logic analyzer"); 5392 5393 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5394 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5395 sysctl_tx_rate, "A", "Tx rate"); 5396 5397 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5398 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5399 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5400 5401 if (chip_id(sc) >= CHELSIO_T5) { 5402 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5403 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5404 sysctl_wcwr_stats, "A", "write combined work requests"); 5405 } 5406 #endif 5407 5408 #ifdef TCP_OFFLOAD 5409 if (is_offload(sc)) { 5410 int i; 5411 char s[4]; 5412 5413 /* 5414 * dev.t4nex.X.toe. 5415 */ 5416 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5417 NULL, "TOE parameters"); 5418 children = SYSCTL_CHILDREN(oid); 5419 5420 sc->tt.cong_algorithm = -1; 5421 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 5422 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 5423 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 5424 "3 = highspeed)"); 5425 5426 sc->tt.sndbuf = 256 * 1024; 5427 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 5428 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 5429 5430 sc->tt.ddp = 0; 5431 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 5432 &sc->tt.ddp, 0, "DDP allowed"); 5433 5434 sc->tt.rx_coalesce = 1; 5435 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 5436 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 5437 5438 sc->tt.tls = 0; 5439 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 5440 &sc->tt.tls, 0, "Inline TLS allowed"); 5441 5442 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 5443 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 5444 "I", "TCP ports that use inline TLS+TOE RX"); 5445 5446 sc->tt.tx_align = 1; 5447 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 5448 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 5449 5450 sc->tt.tx_zcopy = 0; 5451 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 5452 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 5453 "Enable zero-copy aio_write(2)"); 5454 5455 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 5456 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 5457 "TP timer tick (us)"); 5458 5459 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 5460 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 5461 "TCP timestamp tick (us)"); 5462 5463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 5464 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 5465 "DACK tick (us)"); 5466 5467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 5468 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 5469 "IU", "DACK timer (us)"); 5470 5471 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 5472 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 5473 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 5474 5475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 5476 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 5477 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 5478 5479 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 5480 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 5481 sysctl_tp_timer, "LU", "Persist timer min (us)"); 5482 5483 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 5484 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 5485 sysctl_tp_timer, "LU", "Persist timer max (us)"); 5486 5487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 5488 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 5489 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 5490 5491 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 5492 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 5493 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 5494 5495 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 5496 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 5497 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 5498 5499 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 5500 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 5501 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 5502 5503 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 5504 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 5505 sysctl_tp_shift_cnt, "IU", 5506 "Number of SYN retransmissions before abort"); 5507 5508 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 5509 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 5510 sysctl_tp_shift_cnt, "IU", 5511 "Number of retransmissions before abort"); 5512 5513 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 5514 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 5515 sysctl_tp_shift_cnt, "IU", 5516 "Number of keepalive probes before abort"); 5517 5518 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 5519 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 5520 children = SYSCTL_CHILDREN(oid); 5521 for (i = 0; i < 16; i++) { 5522 snprintf(s, sizeof(s), "%u", i); 5523 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 5524 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 5525 "IU", "TOE retransmit backoff"); 5526 } 5527 } 5528 #endif 5529 } 5530 5531 void 5532 vi_sysctls(struct vi_info *vi) 5533 { 5534 struct sysctl_ctx_list *ctx; 5535 struct sysctl_oid *oid; 5536 struct sysctl_oid_list *children; 5537 5538 ctx = device_get_sysctl_ctx(vi->dev); 5539 5540 /* 5541 * dev.v?(cxgbe|cxl).X. 5542 */ 5543 oid = device_get_sysctl_tree(vi->dev); 5544 children = SYSCTL_CHILDREN(oid); 5545 5546 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 5547 vi->viid, "VI identifer"); 5548 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 5549 &vi->nrxq, 0, "# of rx queues"); 5550 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 5551 &vi->ntxq, 0, "# of tx queues"); 5552 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 5553 &vi->first_rxq, 0, "index of first rx queue"); 5554 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 5555 &vi->first_txq, 0, "index of first tx queue"); 5556 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 5557 vi->rss_size, "size of RSS indirection table"); 5558 5559 if (IS_MAIN_VI(vi)) { 5560 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 5561 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 5562 "Reserve queue 0 for non-flowid packets"); 5563 } 5564 5565 #ifdef TCP_OFFLOAD 5566 if (vi->nofldrxq != 0) { 5567 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 5568 &vi->nofldrxq, 0, 5569 "# of rx queues for offloaded TCP connections"); 5570 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 5571 &vi->nofldtxq, 0, 5572 "# of tx queues for offloaded TCP connections"); 5573 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 5574 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 5575 "index of first TOE rx queue"); 5576 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 5577 CTLFLAG_RD, &vi->first_ofld_txq, 0, 5578 "index of first TOE tx queue"); 5579 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 5580 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5581 sysctl_holdoff_tmr_idx_ofld, "I", 5582 "holdoff timer index for TOE queues"); 5583 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 5584 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5585 sysctl_holdoff_pktc_idx_ofld, "I", 5586 "holdoff packet counter index for TOE queues"); 5587 } 5588 #endif 5589 #ifdef DEV_NETMAP 5590 if (vi->nnmrxq != 0) { 5591 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 5592 &vi->nnmrxq, 0, "# of netmap rx queues"); 5593 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 5594 &vi->nnmtxq, 0, "# of netmap tx queues"); 5595 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 5596 CTLFLAG_RD, &vi->first_nm_rxq, 0, 5597 "index of first netmap rx queue"); 5598 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 5599 CTLFLAG_RD, &vi->first_nm_txq, 0, 5600 "index of first netmap tx queue"); 5601 } 5602 #endif 5603 5604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 5605 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 5606 "holdoff timer index"); 5607 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 5608 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 5609 "holdoff packet counter index"); 5610 5611 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 5612 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 5613 "rx queue size"); 5614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 5615 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 5616 "tx queue size"); 5617 } 5618 5619 static void 5620 cxgbe_sysctls(struct port_info *pi) 5621 { 5622 struct sysctl_ctx_list *ctx; 5623 struct sysctl_oid *oid; 5624 struct sysctl_oid_list *children, *children2; 5625 struct adapter *sc = pi->adapter; 5626 int i; 5627 char name[16]; 5628 5629 ctx = device_get_sysctl_ctx(pi->dev); 5630 5631 /* 5632 * dev.cxgbe.X. 5633 */ 5634 oid = device_get_sysctl_tree(pi->dev); 5635 children = SYSCTL_CHILDREN(oid); 5636 5637 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 5638 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 5639 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 5640 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 5641 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 5642 "PHY temperature (in Celsius)"); 5643 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 5644 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 5645 "PHY firmware version"); 5646 } 5647 5648 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 5649 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 5650 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)"); 5651 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 5652 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 5653 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 5654 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 5655 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 5656 "autonegotiation (-1 = not supported)"); 5657 5658 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 5659 port_top_speed(pi), "max speed (in Gbps)"); 5660 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 5661 pi->mps_bg_map, "MPS buffer group map"); 5662 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 5663 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 5664 5665 if (sc->flags & IS_VF) 5666 return; 5667 5668 /* 5669 * dev.(cxgbe|cxl).X.tc. 5670 */ 5671 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 5672 "Tx scheduler traffic classes (cl_rl)"); 5673 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 5674 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 5675 5676 snprintf(name, sizeof(name), "%d", i); 5677 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 5678 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 5679 "traffic class")); 5680 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD, 5681 &tc->flags, 0, "flags"); 5682 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 5683 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 5684 #ifdef SBUF_DRAIN 5685 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 5686 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 5687 sysctl_tc_params, "A", "traffic class parameters"); 5688 #endif 5689 } 5690 5691 /* 5692 * dev.cxgbe.X.stats. 5693 */ 5694 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 5695 NULL, "port statistics"); 5696 children = SYSCTL_CHILDREN(oid); 5697 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 5698 &pi->tx_parse_error, 0, 5699 "# of tx packets with invalid length or # of segments"); 5700 5701 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 5702 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 5703 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 5704 sysctl_handle_t4_reg64, "QU", desc) 5705 5706 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 5707 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 5708 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 5709 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 5710 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 5711 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 5712 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 5713 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 5714 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 5715 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 5716 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 5717 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 5718 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 5719 "# of tx frames in this range", 5720 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 5721 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 5722 "# of tx frames in this range", 5723 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 5724 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 5725 "# of tx frames in this range", 5726 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 5727 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 5728 "# of tx frames in this range", 5729 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 5730 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 5731 "# of tx frames in this range", 5732 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 5733 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 5734 "# of tx frames in this range", 5735 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 5736 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 5737 "# of tx frames in this range", 5738 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 5739 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 5740 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 5741 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 5742 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 5743 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 5744 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 5745 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 5746 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 5747 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 5748 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 5749 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 5750 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 5751 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 5752 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 5753 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 5754 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 5755 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 5756 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 5757 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 5758 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 5759 5760 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 5761 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 5762 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 5763 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 5764 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 5765 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 5766 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 5767 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 5768 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 5769 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 5770 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 5771 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 5772 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 5773 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 5774 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 5775 "# of frames received with bad FCS", 5776 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 5777 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 5778 "# of frames received with length error", 5779 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 5780 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 5781 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 5782 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 5783 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 5784 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 5785 "# of rx frames in this range", 5786 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 5787 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 5788 "# of rx frames in this range", 5789 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 5790 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 5791 "# of rx frames in this range", 5792 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 5793 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 5794 "# of rx frames in this range", 5795 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 5796 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 5797 "# of rx frames in this range", 5798 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 5799 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 5800 "# of rx frames in this range", 5801 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 5802 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 5803 "# of rx frames in this range", 5804 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 5805 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 5806 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 5807 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 5808 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 5809 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 5810 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 5811 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 5812 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 5813 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 5814 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 5815 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 5816 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 5817 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 5818 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 5819 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 5820 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 5821 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 5822 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 5823 5824 #undef SYSCTL_ADD_T4_REG64 5825 5826 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 5827 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 5828 &pi->stats.name, desc) 5829 5830 /* We get these from port_stats and they may be stale by up to 1s */ 5831 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 5832 "# drops due to buffer-group 0 overflows"); 5833 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 5834 "# drops due to buffer-group 1 overflows"); 5835 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 5836 "# drops due to buffer-group 2 overflows"); 5837 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 5838 "# drops due to buffer-group 3 overflows"); 5839 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 5840 "# of buffer-group 0 truncated packets"); 5841 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 5842 "# of buffer-group 1 truncated packets"); 5843 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 5844 "# of buffer-group 2 truncated packets"); 5845 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 5846 "# of buffer-group 3 truncated packets"); 5847 5848 #undef SYSCTL_ADD_T4_PORTSTAT 5849 5850 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 5851 CTLFLAG_RD, &pi->tx_tls_records, 5852 "# of TLS records transmitted"); 5853 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 5854 CTLFLAG_RD, &pi->tx_tls_octets, 5855 "# of payload octets in transmitted TLS records"); 5856 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 5857 CTLFLAG_RD, &pi->rx_tls_records, 5858 "# of TLS records received"); 5859 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 5860 CTLFLAG_RD, &pi->rx_tls_octets, 5861 "# of payload octets in received TLS records"); 5862 } 5863 5864 static int 5865 sysctl_int_array(SYSCTL_HANDLER_ARGS) 5866 { 5867 int rc, *i, space = 0; 5868 struct sbuf sb; 5869 5870 sbuf_new_for_sysctl(&sb, NULL, 64, req); 5871 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 5872 if (space) 5873 sbuf_printf(&sb, " "); 5874 sbuf_printf(&sb, "%d", *i); 5875 space = 1; 5876 } 5877 rc = sbuf_finish(&sb); 5878 sbuf_delete(&sb); 5879 return (rc); 5880 } 5881 5882 static int 5883 sysctl_bitfield(SYSCTL_HANDLER_ARGS) 5884 { 5885 int rc; 5886 struct sbuf *sb; 5887 5888 rc = sysctl_wire_old_buffer(req, 0); 5889 if (rc != 0) 5890 return(rc); 5891 5892 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5893 if (sb == NULL) 5894 return (ENOMEM); 5895 5896 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 5897 rc = sbuf_finish(sb); 5898 sbuf_delete(sb); 5899 5900 return (rc); 5901 } 5902 5903 static int 5904 sysctl_btphy(SYSCTL_HANDLER_ARGS) 5905 { 5906 struct port_info *pi = arg1; 5907 int op = arg2; 5908 struct adapter *sc = pi->adapter; 5909 u_int v; 5910 int rc; 5911 5912 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 5913 if (rc) 5914 return (rc); 5915 /* XXX: magic numbers */ 5916 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 5917 &v); 5918 end_synchronized_op(sc, 0); 5919 if (rc) 5920 return (rc); 5921 if (op == 0) 5922 v /= 256; 5923 5924 rc = sysctl_handle_int(oidp, &v, 0, req); 5925 return (rc); 5926 } 5927 5928 static int 5929 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 5930 { 5931 struct vi_info *vi = arg1; 5932 int rc, val; 5933 5934 val = vi->rsrv_noflowq; 5935 rc = sysctl_handle_int(oidp, &val, 0, req); 5936 if (rc != 0 || req->newptr == NULL) 5937 return (rc); 5938 5939 if ((val >= 1) && (vi->ntxq > 1)) 5940 vi->rsrv_noflowq = 1; 5941 else 5942 vi->rsrv_noflowq = 0; 5943 5944 return (rc); 5945 } 5946 5947 static int 5948 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 5949 { 5950 struct vi_info *vi = arg1; 5951 struct adapter *sc = vi->pi->adapter; 5952 int idx, rc, i; 5953 struct sge_rxq *rxq; 5954 uint8_t v; 5955 5956 idx = vi->tmr_idx; 5957 5958 rc = sysctl_handle_int(oidp, &idx, 0, req); 5959 if (rc != 0 || req->newptr == NULL) 5960 return (rc); 5961 5962 if (idx < 0 || idx >= SGE_NTIMERS) 5963 return (EINVAL); 5964 5965 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5966 "t4tmr"); 5967 if (rc) 5968 return (rc); 5969 5970 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 5971 for_each_rxq(vi, i, rxq) { 5972 #ifdef atomic_store_rel_8 5973 atomic_store_rel_8(&rxq->iq.intr_params, v); 5974 #else 5975 rxq->iq.intr_params = v; 5976 #endif 5977 } 5978 vi->tmr_idx = idx; 5979 5980 end_synchronized_op(sc, LOCK_HELD); 5981 return (0); 5982 } 5983 5984 static int 5985 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 5986 { 5987 struct vi_info *vi = arg1; 5988 struct adapter *sc = vi->pi->adapter; 5989 int idx, rc; 5990 5991 idx = vi->pktc_idx; 5992 5993 rc = sysctl_handle_int(oidp, &idx, 0, req); 5994 if (rc != 0 || req->newptr == NULL) 5995 return (rc); 5996 5997 if (idx < -1 || idx >= SGE_NCOUNTERS) 5998 return (EINVAL); 5999 6000 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6001 "t4pktc"); 6002 if (rc) 6003 return (rc); 6004 6005 if (vi->flags & VI_INIT_DONE) 6006 rc = EBUSY; /* cannot be changed once the queues are created */ 6007 else 6008 vi->pktc_idx = idx; 6009 6010 end_synchronized_op(sc, LOCK_HELD); 6011 return (rc); 6012 } 6013 6014 static int 6015 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6016 { 6017 struct vi_info *vi = arg1; 6018 struct adapter *sc = vi->pi->adapter; 6019 int qsize, rc; 6020 6021 qsize = vi->qsize_rxq; 6022 6023 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6024 if (rc != 0 || req->newptr == NULL) 6025 return (rc); 6026 6027 if (qsize < 128 || (qsize & 7)) 6028 return (EINVAL); 6029 6030 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6031 "t4rxqs"); 6032 if (rc) 6033 return (rc); 6034 6035 if (vi->flags & VI_INIT_DONE) 6036 rc = EBUSY; /* cannot be changed once the queues are created */ 6037 else 6038 vi->qsize_rxq = qsize; 6039 6040 end_synchronized_op(sc, LOCK_HELD); 6041 return (rc); 6042 } 6043 6044 static int 6045 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6046 { 6047 struct vi_info *vi = arg1; 6048 struct adapter *sc = vi->pi->adapter; 6049 int qsize, rc; 6050 6051 qsize = vi->qsize_txq; 6052 6053 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6054 if (rc != 0 || req->newptr == NULL) 6055 return (rc); 6056 6057 if (qsize < 128 || qsize > 65536) 6058 return (EINVAL); 6059 6060 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6061 "t4txqs"); 6062 if (rc) 6063 return (rc); 6064 6065 if (vi->flags & VI_INIT_DONE) 6066 rc = EBUSY; /* cannot be changed once the queues are created */ 6067 else 6068 vi->qsize_txq = qsize; 6069 6070 end_synchronized_op(sc, LOCK_HELD); 6071 return (rc); 6072 } 6073 6074 static int 6075 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6076 { 6077 struct port_info *pi = arg1; 6078 struct adapter *sc = pi->adapter; 6079 struct link_config *lc = &pi->link_cfg; 6080 int rc; 6081 6082 if (req->newptr == NULL) { 6083 struct sbuf *sb; 6084 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX"; 6085 6086 rc = sysctl_wire_old_buffer(req, 0); 6087 if (rc != 0) 6088 return(rc); 6089 6090 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6091 if (sb == NULL) 6092 return (ENOMEM); 6093 6094 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits); 6095 rc = sbuf_finish(sb); 6096 sbuf_delete(sb); 6097 } else { 6098 char s[2]; 6099 int n; 6100 6101 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX)); 6102 s[1] = 0; 6103 6104 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6105 if (rc != 0) 6106 return(rc); 6107 6108 if (s[1] != 0) 6109 return (EINVAL); 6110 if (s[0] < '0' || s[0] > '9') 6111 return (EINVAL); /* not a number */ 6112 n = s[0] - '0'; 6113 if (n & ~(PAUSE_TX | PAUSE_RX)) 6114 return (EINVAL); /* some other bit is set too */ 6115 6116 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6117 "t4PAUSE"); 6118 if (rc) 6119 return (rc); 6120 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) { 6121 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 6122 lc->requested_fc |= n; 6123 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6124 if (rc == 0) { 6125 lc->fc = lc->requested_fc; 6126 } 6127 } 6128 end_synchronized_op(sc, 0); 6129 } 6130 6131 return (rc); 6132 } 6133 6134 static int 6135 sysctl_fec(SYSCTL_HANDLER_ARGS) 6136 { 6137 struct port_info *pi = arg1; 6138 struct adapter *sc = pi->adapter; 6139 struct link_config *lc = &pi->link_cfg; 6140 int rc; 6141 6142 if (req->newptr == NULL) { 6143 struct sbuf *sb; 6144 static char *bits = "\20\1RS\2BASER_RS\3RESERVED"; 6145 6146 rc = sysctl_wire_old_buffer(req, 0); 6147 if (rc != 0) 6148 return(rc); 6149 6150 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6151 if (sb == NULL) 6152 return (ENOMEM); 6153 6154 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits); 6155 rc = sbuf_finish(sb); 6156 sbuf_delete(sb); 6157 } else { 6158 char s[2]; 6159 int n; 6160 6161 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC); 6162 s[1] = 0; 6163 6164 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6165 if (rc != 0) 6166 return(rc); 6167 6168 if (s[1] != 0) 6169 return (EINVAL); 6170 if (s[0] < '0' || s[0] > '9') 6171 return (EINVAL); /* not a number */ 6172 n = s[0] - '0'; 6173 if (n & ~M_FW_PORT_CAP_FEC) 6174 return (EINVAL); /* some other bit is set too */ 6175 6176 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6177 "t4fec"); 6178 if (rc) 6179 return (rc); 6180 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) { 6181 lc->requested_fec = n & 6182 G_FW_PORT_CAP_FEC(lc->supported); 6183 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6184 if (rc == 0) { 6185 lc->fec = lc->requested_fec; 6186 } 6187 } 6188 end_synchronized_op(sc, 0); 6189 } 6190 6191 return (rc); 6192 } 6193 6194 static int 6195 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 6196 { 6197 struct port_info *pi = arg1; 6198 struct adapter *sc = pi->adapter; 6199 struct link_config *lc = &pi->link_cfg; 6200 int rc, val, old; 6201 6202 if (lc->supported & FW_PORT_CAP_ANEG) 6203 val = lc->requested_aneg == AUTONEG_ENABLE ? 1 : 0; 6204 else 6205 val = -1; 6206 rc = sysctl_handle_int(oidp, &val, 0, req); 6207 if (rc != 0 || req->newptr == NULL) 6208 return (rc); 6209 if ((lc->supported & FW_PORT_CAP_ANEG) == 0) 6210 return (ENOTSUP); 6211 6212 if (val == 0) 6213 val = AUTONEG_DISABLE; 6214 else if (val == 1) 6215 val = AUTONEG_ENABLE; 6216 else 6217 return (EINVAL); 6218 if (lc->requested_aneg == val) 6219 return (0); /* no change */ 6220 6221 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6222 "t4aneg"); 6223 if (rc) 6224 return (rc); 6225 old = lc->requested_aneg; 6226 lc->requested_aneg = val; 6227 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6228 if (rc != 0) 6229 lc->requested_aneg = old; 6230 end_synchronized_op(sc, 0); 6231 return (rc); 6232 } 6233 6234 static int 6235 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 6236 { 6237 struct adapter *sc = arg1; 6238 int reg = arg2; 6239 uint64_t val; 6240 6241 val = t4_read_reg64(sc, reg); 6242 6243 return (sysctl_handle_64(oidp, &val, 0, req)); 6244 } 6245 6246 static int 6247 sysctl_temperature(SYSCTL_HANDLER_ARGS) 6248 { 6249 struct adapter *sc = arg1; 6250 int rc, t; 6251 uint32_t param, val; 6252 6253 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 6254 if (rc) 6255 return (rc); 6256 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6257 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 6258 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 6259 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6260 end_synchronized_op(sc, 0); 6261 if (rc) 6262 return (rc); 6263 6264 /* unknown is returned as 0 but we display -1 in that case */ 6265 t = val == 0 ? -1 : val; 6266 6267 rc = sysctl_handle_int(oidp, &t, 0, req); 6268 return (rc); 6269 } 6270 6271 #ifdef SBUF_DRAIN 6272 static int 6273 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 6274 { 6275 struct adapter *sc = arg1; 6276 struct sbuf *sb; 6277 int rc, i; 6278 uint16_t incr[NMTUS][NCCTRL_WIN]; 6279 static const char *dec_fac[] = { 6280 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 6281 "0.9375" 6282 }; 6283 6284 rc = sysctl_wire_old_buffer(req, 0); 6285 if (rc != 0) 6286 return (rc); 6287 6288 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6289 if (sb == NULL) 6290 return (ENOMEM); 6291 6292 t4_read_cong_tbl(sc, incr); 6293 6294 for (i = 0; i < NCCTRL_WIN; ++i) { 6295 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 6296 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 6297 incr[5][i], incr[6][i], incr[7][i]); 6298 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 6299 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 6300 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 6301 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 6302 } 6303 6304 rc = sbuf_finish(sb); 6305 sbuf_delete(sb); 6306 6307 return (rc); 6308 } 6309 6310 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 6311 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 6312 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 6313 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 6314 }; 6315 6316 static int 6317 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 6318 { 6319 struct adapter *sc = arg1; 6320 struct sbuf *sb; 6321 int rc, i, n, qid = arg2; 6322 uint32_t *buf, *p; 6323 char *qtype; 6324 u_int cim_num_obq = sc->chip_params->cim_num_obq; 6325 6326 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 6327 ("%s: bad qid %d\n", __func__, qid)); 6328 6329 if (qid < CIM_NUM_IBQ) { 6330 /* inbound queue */ 6331 qtype = "IBQ"; 6332 n = 4 * CIM_IBQ_SIZE; 6333 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6334 rc = t4_read_cim_ibq(sc, qid, buf, n); 6335 } else { 6336 /* outbound queue */ 6337 qtype = "OBQ"; 6338 qid -= CIM_NUM_IBQ; 6339 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 6340 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6341 rc = t4_read_cim_obq(sc, qid, buf, n); 6342 } 6343 6344 if (rc < 0) { 6345 rc = -rc; 6346 goto done; 6347 } 6348 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 6349 6350 rc = sysctl_wire_old_buffer(req, 0); 6351 if (rc != 0) 6352 goto done; 6353 6354 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6355 if (sb == NULL) { 6356 rc = ENOMEM; 6357 goto done; 6358 } 6359 6360 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 6361 for (i = 0, p = buf; i < n; i += 16, p += 4) 6362 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 6363 p[2], p[3]); 6364 6365 rc = sbuf_finish(sb); 6366 sbuf_delete(sb); 6367 done: 6368 free(buf, M_CXGBE); 6369 return (rc); 6370 } 6371 6372 static int 6373 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 6374 { 6375 struct adapter *sc = arg1; 6376 u_int cfg; 6377 struct sbuf *sb; 6378 uint32_t *buf, *p; 6379 int rc; 6380 6381 MPASS(chip_id(sc) <= CHELSIO_T5); 6382 6383 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6384 if (rc != 0) 6385 return (rc); 6386 6387 rc = sysctl_wire_old_buffer(req, 0); 6388 if (rc != 0) 6389 return (rc); 6390 6391 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6392 if (sb == NULL) 6393 return (ENOMEM); 6394 6395 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6396 M_ZERO | M_WAITOK); 6397 6398 rc = -t4_cim_read_la(sc, buf, NULL); 6399 if (rc != 0) 6400 goto done; 6401 6402 sbuf_printf(sb, "Status Data PC%s", 6403 cfg & F_UPDBGLACAPTPCONLY ? "" : 6404 " LS0Stat LS0Addr LS0Data"); 6405 6406 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 6407 if (cfg & F_UPDBGLACAPTPCONLY) { 6408 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 6409 p[6], p[7]); 6410 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 6411 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 6412 p[4] & 0xff, p[5] >> 8); 6413 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 6414 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6415 p[1] & 0xf, p[2] >> 4); 6416 } else { 6417 sbuf_printf(sb, 6418 "\n %02x %x%07x %x%07x %08x %08x " 6419 "%08x%08x%08x%08x", 6420 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6421 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 6422 p[6], p[7]); 6423 } 6424 } 6425 6426 rc = sbuf_finish(sb); 6427 sbuf_delete(sb); 6428 done: 6429 free(buf, M_CXGBE); 6430 return (rc); 6431 } 6432 6433 static int 6434 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 6435 { 6436 struct adapter *sc = arg1; 6437 u_int cfg; 6438 struct sbuf *sb; 6439 uint32_t *buf, *p; 6440 int rc; 6441 6442 MPASS(chip_id(sc) > CHELSIO_T5); 6443 6444 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6445 if (rc != 0) 6446 return (rc); 6447 6448 rc = sysctl_wire_old_buffer(req, 0); 6449 if (rc != 0) 6450 return (rc); 6451 6452 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6453 if (sb == NULL) 6454 return (ENOMEM); 6455 6456 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6457 M_ZERO | M_WAITOK); 6458 6459 rc = -t4_cim_read_la(sc, buf, NULL); 6460 if (rc != 0) 6461 goto done; 6462 6463 sbuf_printf(sb, "Status Inst Data PC%s", 6464 cfg & F_UPDBGLACAPTPCONLY ? "" : 6465 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 6466 6467 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 6468 if (cfg & F_UPDBGLACAPTPCONLY) { 6469 sbuf_printf(sb, "\n %02x %08x %08x %08x", 6470 p[3] & 0xff, p[2], p[1], p[0]); 6471 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 6472 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 6473 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 6474 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 6475 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 6476 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 6477 p[6] >> 16); 6478 } else { 6479 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 6480 "%08x %08x %08x %08x %08x %08x", 6481 (p[9] >> 16) & 0xff, 6482 p[9] & 0xffff, p[8] >> 16, 6483 p[8] & 0xffff, p[7] >> 16, 6484 p[7] & 0xffff, p[6] >> 16, 6485 p[2], p[1], p[0], p[5], p[4], p[3]); 6486 } 6487 } 6488 6489 rc = sbuf_finish(sb); 6490 sbuf_delete(sb); 6491 done: 6492 free(buf, M_CXGBE); 6493 return (rc); 6494 } 6495 6496 static int 6497 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 6498 { 6499 struct adapter *sc = arg1; 6500 u_int i; 6501 struct sbuf *sb; 6502 uint32_t *buf, *p; 6503 int rc; 6504 6505 rc = sysctl_wire_old_buffer(req, 0); 6506 if (rc != 0) 6507 return (rc); 6508 6509 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6510 if (sb == NULL) 6511 return (ENOMEM); 6512 6513 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 6514 M_ZERO | M_WAITOK); 6515 6516 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 6517 p = buf; 6518 6519 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6520 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 6521 p[1], p[0]); 6522 } 6523 6524 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 6525 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6526 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 6527 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 6528 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 6529 (p[1] >> 2) | ((p[2] & 3) << 30), 6530 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 6531 p[0] & 1); 6532 } 6533 6534 rc = sbuf_finish(sb); 6535 sbuf_delete(sb); 6536 free(buf, M_CXGBE); 6537 return (rc); 6538 } 6539 6540 static int 6541 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 6542 { 6543 struct adapter *sc = arg1; 6544 u_int i; 6545 struct sbuf *sb; 6546 uint32_t *buf, *p; 6547 int rc; 6548 6549 rc = sysctl_wire_old_buffer(req, 0); 6550 if (rc != 0) 6551 return (rc); 6552 6553 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6554 if (sb == NULL) 6555 return (ENOMEM); 6556 6557 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 6558 M_ZERO | M_WAITOK); 6559 6560 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 6561 p = buf; 6562 6563 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 6564 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6565 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 6566 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 6567 p[4], p[3], p[2], p[1], p[0]); 6568 } 6569 6570 sbuf_printf(sb, "\n\nCntl ID Data"); 6571 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6572 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 6573 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 6574 } 6575 6576 rc = sbuf_finish(sb); 6577 sbuf_delete(sb); 6578 free(buf, M_CXGBE); 6579 return (rc); 6580 } 6581 6582 static int 6583 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 6584 { 6585 struct adapter *sc = arg1; 6586 struct sbuf *sb; 6587 int rc, i; 6588 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6589 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6590 uint16_t thres[CIM_NUM_IBQ]; 6591 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 6592 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 6593 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 6594 6595 cim_num_obq = sc->chip_params->cim_num_obq; 6596 if (is_t4(sc)) { 6597 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 6598 obq_rdaddr = A_UP_OBQ_0_REALADDR; 6599 } else { 6600 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 6601 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 6602 } 6603 nq = CIM_NUM_IBQ + cim_num_obq; 6604 6605 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 6606 if (rc == 0) 6607 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 6608 if (rc != 0) 6609 return (rc); 6610 6611 t4_read_cimq_cfg(sc, base, size, thres); 6612 6613 rc = sysctl_wire_old_buffer(req, 0); 6614 if (rc != 0) 6615 return (rc); 6616 6617 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6618 if (sb == NULL) 6619 return (ENOMEM); 6620 6621 sbuf_printf(sb, 6622 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 6623 6624 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 6625 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 6626 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 6627 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6628 G_QUEREMFLITS(p[2]) * 16); 6629 for ( ; i < nq; i++, p += 4, wr += 2) 6630 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 6631 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 6632 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6633 G_QUEREMFLITS(p[2]) * 16); 6634 6635 rc = sbuf_finish(sb); 6636 sbuf_delete(sb); 6637 6638 return (rc); 6639 } 6640 6641 static int 6642 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 6643 { 6644 struct adapter *sc = arg1; 6645 struct sbuf *sb; 6646 int rc; 6647 struct tp_cpl_stats stats; 6648 6649 rc = sysctl_wire_old_buffer(req, 0); 6650 if (rc != 0) 6651 return (rc); 6652 6653 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6654 if (sb == NULL) 6655 return (ENOMEM); 6656 6657 mtx_lock(&sc->reg_lock); 6658 t4_tp_get_cpl_stats(sc, &stats, 0); 6659 mtx_unlock(&sc->reg_lock); 6660 6661 if (sc->chip_params->nchan > 2) { 6662 sbuf_printf(sb, " channel 0 channel 1" 6663 " channel 2 channel 3"); 6664 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 6665 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 6666 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 6667 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 6668 } else { 6669 sbuf_printf(sb, " channel 0 channel 1"); 6670 sbuf_printf(sb, "\nCPL requests: %10u %10u", 6671 stats.req[0], stats.req[1]); 6672 sbuf_printf(sb, "\nCPL responses: %10u %10u", 6673 stats.rsp[0], stats.rsp[1]); 6674 } 6675 6676 rc = sbuf_finish(sb); 6677 sbuf_delete(sb); 6678 6679 return (rc); 6680 } 6681 6682 static int 6683 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 6684 { 6685 struct adapter *sc = arg1; 6686 struct sbuf *sb; 6687 int rc; 6688 struct tp_usm_stats stats; 6689 6690 rc = sysctl_wire_old_buffer(req, 0); 6691 if (rc != 0) 6692 return(rc); 6693 6694 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6695 if (sb == NULL) 6696 return (ENOMEM); 6697 6698 t4_get_usm_stats(sc, &stats, 1); 6699 6700 sbuf_printf(sb, "Frames: %u\n", stats.frames); 6701 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 6702 sbuf_printf(sb, "Drops: %u", stats.drops); 6703 6704 rc = sbuf_finish(sb); 6705 sbuf_delete(sb); 6706 6707 return (rc); 6708 } 6709 6710 static const char * const devlog_level_strings[] = { 6711 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 6712 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 6713 [FW_DEVLOG_LEVEL_ERR] = "ERR", 6714 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 6715 [FW_DEVLOG_LEVEL_INFO] = "INFO", 6716 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 6717 }; 6718 6719 static const char * const devlog_facility_strings[] = { 6720 [FW_DEVLOG_FACILITY_CORE] = "CORE", 6721 [FW_DEVLOG_FACILITY_CF] = "CF", 6722 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 6723 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 6724 [FW_DEVLOG_FACILITY_RES] = "RES", 6725 [FW_DEVLOG_FACILITY_HW] = "HW", 6726 [FW_DEVLOG_FACILITY_FLR] = "FLR", 6727 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 6728 [FW_DEVLOG_FACILITY_PHY] = "PHY", 6729 [FW_DEVLOG_FACILITY_MAC] = "MAC", 6730 [FW_DEVLOG_FACILITY_PORT] = "PORT", 6731 [FW_DEVLOG_FACILITY_VI] = "VI", 6732 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 6733 [FW_DEVLOG_FACILITY_ACL] = "ACL", 6734 [FW_DEVLOG_FACILITY_TM] = "TM", 6735 [FW_DEVLOG_FACILITY_QFC] = "QFC", 6736 [FW_DEVLOG_FACILITY_DCB] = "DCB", 6737 [FW_DEVLOG_FACILITY_ETH] = "ETH", 6738 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 6739 [FW_DEVLOG_FACILITY_RI] = "RI", 6740 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 6741 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 6742 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 6743 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 6744 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 6745 }; 6746 6747 static int 6748 sysctl_devlog(SYSCTL_HANDLER_ARGS) 6749 { 6750 struct adapter *sc = arg1; 6751 struct devlog_params *dparams = &sc->params.devlog; 6752 struct fw_devlog_e *buf, *e; 6753 int i, j, rc, nentries, first = 0; 6754 struct sbuf *sb; 6755 uint64_t ftstamp = UINT64_MAX; 6756 6757 if (dparams->addr == 0) 6758 return (ENXIO); 6759 6760 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 6761 if (buf == NULL) 6762 return (ENOMEM); 6763 6764 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 6765 if (rc != 0) 6766 goto done; 6767 6768 nentries = dparams->size / sizeof(struct fw_devlog_e); 6769 for (i = 0; i < nentries; i++) { 6770 e = &buf[i]; 6771 6772 if (e->timestamp == 0) 6773 break; /* end */ 6774 6775 e->timestamp = be64toh(e->timestamp); 6776 e->seqno = be32toh(e->seqno); 6777 for (j = 0; j < 8; j++) 6778 e->params[j] = be32toh(e->params[j]); 6779 6780 if (e->timestamp < ftstamp) { 6781 ftstamp = e->timestamp; 6782 first = i; 6783 } 6784 } 6785 6786 if (buf[first].timestamp == 0) 6787 goto done; /* nothing in the log */ 6788 6789 rc = sysctl_wire_old_buffer(req, 0); 6790 if (rc != 0) 6791 goto done; 6792 6793 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6794 if (sb == NULL) { 6795 rc = ENOMEM; 6796 goto done; 6797 } 6798 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 6799 "Seq#", "Tstamp", "Level", "Facility", "Message"); 6800 6801 i = first; 6802 do { 6803 e = &buf[i]; 6804 if (e->timestamp == 0) 6805 break; /* end */ 6806 6807 sbuf_printf(sb, "%10d %15ju %8s %8s ", 6808 e->seqno, e->timestamp, 6809 (e->level < nitems(devlog_level_strings) ? 6810 devlog_level_strings[e->level] : "UNKNOWN"), 6811 (e->facility < nitems(devlog_facility_strings) ? 6812 devlog_facility_strings[e->facility] : "UNKNOWN")); 6813 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 6814 e->params[2], e->params[3], e->params[4], 6815 e->params[5], e->params[6], e->params[7]); 6816 6817 if (++i == nentries) 6818 i = 0; 6819 } while (i != first); 6820 6821 rc = sbuf_finish(sb); 6822 sbuf_delete(sb); 6823 done: 6824 free(buf, M_CXGBE); 6825 return (rc); 6826 } 6827 6828 static int 6829 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 6830 { 6831 struct adapter *sc = arg1; 6832 struct sbuf *sb; 6833 int rc; 6834 struct tp_fcoe_stats stats[MAX_NCHAN]; 6835 int i, nchan = sc->chip_params->nchan; 6836 6837 rc = sysctl_wire_old_buffer(req, 0); 6838 if (rc != 0) 6839 return (rc); 6840 6841 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6842 if (sb == NULL) 6843 return (ENOMEM); 6844 6845 for (i = 0; i < nchan; i++) 6846 t4_get_fcoe_stats(sc, i, &stats[i], 1); 6847 6848 if (nchan > 2) { 6849 sbuf_printf(sb, " channel 0 channel 1" 6850 " channel 2 channel 3"); 6851 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 6852 stats[0].octets_ddp, stats[1].octets_ddp, 6853 stats[2].octets_ddp, stats[3].octets_ddp); 6854 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 6855 stats[0].frames_ddp, stats[1].frames_ddp, 6856 stats[2].frames_ddp, stats[3].frames_ddp); 6857 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 6858 stats[0].frames_drop, stats[1].frames_drop, 6859 stats[2].frames_drop, stats[3].frames_drop); 6860 } else { 6861 sbuf_printf(sb, " channel 0 channel 1"); 6862 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 6863 stats[0].octets_ddp, stats[1].octets_ddp); 6864 sbuf_printf(sb, "\nframesDDP: %16u %16u", 6865 stats[0].frames_ddp, stats[1].frames_ddp); 6866 sbuf_printf(sb, "\nframesDrop: %16u %16u", 6867 stats[0].frames_drop, stats[1].frames_drop); 6868 } 6869 6870 rc = sbuf_finish(sb); 6871 sbuf_delete(sb); 6872 6873 return (rc); 6874 } 6875 6876 static int 6877 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 6878 { 6879 struct adapter *sc = arg1; 6880 struct sbuf *sb; 6881 int rc, i; 6882 unsigned int map, kbps, ipg, mode; 6883 unsigned int pace_tab[NTX_SCHED]; 6884 6885 rc = sysctl_wire_old_buffer(req, 0); 6886 if (rc != 0) 6887 return (rc); 6888 6889 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6890 if (sb == NULL) 6891 return (ENOMEM); 6892 6893 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 6894 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 6895 t4_read_pace_tbl(sc, pace_tab); 6896 6897 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 6898 "Class IPG (0.1 ns) Flow IPG (us)"); 6899 6900 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 6901 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 6902 sbuf_printf(sb, "\n %u %-5s %u ", i, 6903 (mode & (1 << i)) ? "flow" : "class", map & 3); 6904 if (kbps) 6905 sbuf_printf(sb, "%9u ", kbps); 6906 else 6907 sbuf_printf(sb, " disabled "); 6908 6909 if (ipg) 6910 sbuf_printf(sb, "%13u ", ipg); 6911 else 6912 sbuf_printf(sb, " disabled "); 6913 6914 if (pace_tab[i]) 6915 sbuf_printf(sb, "%10u", pace_tab[i]); 6916 else 6917 sbuf_printf(sb, " disabled"); 6918 } 6919 6920 rc = sbuf_finish(sb); 6921 sbuf_delete(sb); 6922 6923 return (rc); 6924 } 6925 6926 static int 6927 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 6928 { 6929 struct adapter *sc = arg1; 6930 struct sbuf *sb; 6931 int rc, i, j; 6932 uint64_t *p0, *p1; 6933 struct lb_port_stats s[2]; 6934 static const char *stat_name[] = { 6935 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 6936 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 6937 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 6938 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 6939 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 6940 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 6941 "BG2FramesTrunc:", "BG3FramesTrunc:" 6942 }; 6943 6944 rc = sysctl_wire_old_buffer(req, 0); 6945 if (rc != 0) 6946 return (rc); 6947 6948 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6949 if (sb == NULL) 6950 return (ENOMEM); 6951 6952 memset(s, 0, sizeof(s)); 6953 6954 for (i = 0; i < sc->chip_params->nchan; i += 2) { 6955 t4_get_lb_stats(sc, i, &s[0]); 6956 t4_get_lb_stats(sc, i + 1, &s[1]); 6957 6958 p0 = &s[0].octets; 6959 p1 = &s[1].octets; 6960 sbuf_printf(sb, "%s Loopback %u" 6961 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 6962 6963 for (j = 0; j < nitems(stat_name); j++) 6964 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 6965 *p0++, *p1++); 6966 } 6967 6968 rc = sbuf_finish(sb); 6969 sbuf_delete(sb); 6970 6971 return (rc); 6972 } 6973 6974 static int 6975 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 6976 { 6977 int rc = 0; 6978 struct port_info *pi = arg1; 6979 struct link_config *lc = &pi->link_cfg; 6980 struct sbuf *sb; 6981 6982 rc = sysctl_wire_old_buffer(req, 0); 6983 if (rc != 0) 6984 return(rc); 6985 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 6986 if (sb == NULL) 6987 return (ENOMEM); 6988 6989 if (lc->link_ok || lc->link_down_rc == 255) 6990 sbuf_printf(sb, "n/a"); 6991 else 6992 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 6993 6994 rc = sbuf_finish(sb); 6995 sbuf_delete(sb); 6996 6997 return (rc); 6998 } 6999 7000 struct mem_desc { 7001 unsigned int base; 7002 unsigned int limit; 7003 unsigned int idx; 7004 }; 7005 7006 static int 7007 mem_desc_cmp(const void *a, const void *b) 7008 { 7009 return ((const struct mem_desc *)a)->base - 7010 ((const struct mem_desc *)b)->base; 7011 } 7012 7013 static void 7014 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7015 unsigned int to) 7016 { 7017 unsigned int size; 7018 7019 if (from == to) 7020 return; 7021 7022 size = to - from + 1; 7023 if (size == 0) 7024 return; 7025 7026 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7027 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7028 } 7029 7030 static int 7031 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7032 { 7033 struct adapter *sc = arg1; 7034 struct sbuf *sb; 7035 int rc, i, n; 7036 uint32_t lo, hi, used, alloc; 7037 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 7038 static const char *region[] = { 7039 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 7040 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 7041 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 7042 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 7043 "RQUDP region:", "PBL region:", "TXPBL region:", 7044 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 7045 "On-chip queues:", "TLS keys:", 7046 }; 7047 struct mem_desc avail[4]; 7048 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 7049 struct mem_desc *md = mem; 7050 7051 rc = sysctl_wire_old_buffer(req, 0); 7052 if (rc != 0) 7053 return (rc); 7054 7055 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7056 if (sb == NULL) 7057 return (ENOMEM); 7058 7059 for (i = 0; i < nitems(mem); i++) { 7060 mem[i].limit = 0; 7061 mem[i].idx = i; 7062 } 7063 7064 /* Find and sort the populated memory ranges */ 7065 i = 0; 7066 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 7067 if (lo & F_EDRAM0_ENABLE) { 7068 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 7069 avail[i].base = G_EDRAM0_BASE(hi) << 20; 7070 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 7071 avail[i].idx = 0; 7072 i++; 7073 } 7074 if (lo & F_EDRAM1_ENABLE) { 7075 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 7076 avail[i].base = G_EDRAM1_BASE(hi) << 20; 7077 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 7078 avail[i].idx = 1; 7079 i++; 7080 } 7081 if (lo & F_EXT_MEM_ENABLE) { 7082 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 7083 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 7084 avail[i].limit = avail[i].base + 7085 (G_EXT_MEM_SIZE(hi) << 20); 7086 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 7087 i++; 7088 } 7089 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 7090 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 7091 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 7092 avail[i].limit = avail[i].base + 7093 (G_EXT_MEM1_SIZE(hi) << 20); 7094 avail[i].idx = 4; 7095 i++; 7096 } 7097 if (!i) /* no memory available */ 7098 return 0; 7099 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 7100 7101 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 7102 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 7103 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 7104 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 7105 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 7106 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 7107 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 7108 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 7109 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 7110 7111 /* the next few have explicit upper bounds */ 7112 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 7113 md->limit = md->base - 1 + 7114 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 7115 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 7116 md++; 7117 7118 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 7119 md->limit = md->base - 1 + 7120 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 7121 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 7122 md++; 7123 7124 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7125 if (chip_id(sc) <= CHELSIO_T5) 7126 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 7127 else 7128 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 7129 md->limit = 0; 7130 } else { 7131 md->base = 0; 7132 md->idx = nitems(region); /* hide it */ 7133 } 7134 md++; 7135 7136 #define ulp_region(reg) \ 7137 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 7138 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 7139 7140 ulp_region(RX_ISCSI); 7141 ulp_region(RX_TDDP); 7142 ulp_region(TX_TPT); 7143 ulp_region(RX_STAG); 7144 ulp_region(RX_RQ); 7145 ulp_region(RX_RQUDP); 7146 ulp_region(RX_PBL); 7147 ulp_region(TX_PBL); 7148 #undef ulp_region 7149 7150 md->base = 0; 7151 md->idx = nitems(region); 7152 if (!is_t4(sc)) { 7153 uint32_t size = 0; 7154 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 7155 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 7156 7157 if (is_t5(sc)) { 7158 if (sge_ctrl & F_VFIFO_ENABLE) 7159 size = G_DBVFIFO_SIZE(fifo_size); 7160 } else 7161 size = G_T6_DBVFIFO_SIZE(fifo_size); 7162 7163 if (size) { 7164 md->base = G_BASEADDR(t4_read_reg(sc, 7165 A_SGE_DBVFIFO_BADDR)); 7166 md->limit = md->base + (size << 2) - 1; 7167 } 7168 } 7169 md++; 7170 7171 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 7172 md->limit = 0; 7173 md++; 7174 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 7175 md->limit = 0; 7176 md++; 7177 7178 md->base = sc->vres.ocq.start; 7179 if (sc->vres.ocq.size) 7180 md->limit = md->base + sc->vres.ocq.size - 1; 7181 else 7182 md->idx = nitems(region); /* hide it */ 7183 md++; 7184 7185 md->base = sc->vres.key.start; 7186 if (sc->vres.key.size) 7187 md->limit = md->base + sc->vres.key.size - 1; 7188 else 7189 md->idx = nitems(region); /* hide it */ 7190 md++; 7191 7192 /* add any address-space holes, there can be up to 3 */ 7193 for (n = 0; n < i - 1; n++) 7194 if (avail[n].limit < avail[n + 1].base) 7195 (md++)->base = avail[n].limit; 7196 if (avail[n].limit) 7197 (md++)->base = avail[n].limit; 7198 7199 n = md - mem; 7200 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 7201 7202 for (lo = 0; lo < i; lo++) 7203 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 7204 avail[lo].limit - 1); 7205 7206 sbuf_printf(sb, "\n"); 7207 for (i = 0; i < n; i++) { 7208 if (mem[i].idx >= nitems(region)) 7209 continue; /* skip holes */ 7210 if (!mem[i].limit) 7211 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 7212 mem_region_show(sb, region[mem[i].idx], mem[i].base, 7213 mem[i].limit); 7214 } 7215 7216 sbuf_printf(sb, "\n"); 7217 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 7218 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 7219 mem_region_show(sb, "uP RAM:", lo, hi); 7220 7221 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 7222 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 7223 mem_region_show(sb, "uP Extmem2:", lo, hi); 7224 7225 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 7226 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 7227 G_PMRXMAXPAGE(lo), 7228 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 7229 (lo & F_PMRXNUMCHN) ? 2 : 1); 7230 7231 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 7232 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 7233 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 7234 G_PMTXMAXPAGE(lo), 7235 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 7236 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 7237 sbuf_printf(sb, "%u p-structs\n", 7238 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 7239 7240 for (i = 0; i < 4; i++) { 7241 if (chip_id(sc) > CHELSIO_T5) 7242 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 7243 else 7244 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 7245 if (is_t5(sc)) { 7246 used = G_T5_USED(lo); 7247 alloc = G_T5_ALLOC(lo); 7248 } else { 7249 used = G_USED(lo); 7250 alloc = G_ALLOC(lo); 7251 } 7252 /* For T6 these are MAC buffer groups */ 7253 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 7254 i, used, alloc); 7255 } 7256 for (i = 0; i < sc->chip_params->nchan; i++) { 7257 if (chip_id(sc) > CHELSIO_T5) 7258 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 7259 else 7260 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 7261 if (is_t5(sc)) { 7262 used = G_T5_USED(lo); 7263 alloc = G_T5_ALLOC(lo); 7264 } else { 7265 used = G_USED(lo); 7266 alloc = G_ALLOC(lo); 7267 } 7268 /* For T6 these are MAC buffer groups */ 7269 sbuf_printf(sb, 7270 "\nLoopback %d using %u pages out of %u allocated", 7271 i, used, alloc); 7272 } 7273 7274 rc = sbuf_finish(sb); 7275 sbuf_delete(sb); 7276 7277 return (rc); 7278 } 7279 7280 static inline void 7281 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 7282 { 7283 *mask = x | y; 7284 y = htobe64(y); 7285 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 7286 } 7287 7288 static int 7289 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 7290 { 7291 struct adapter *sc = arg1; 7292 struct sbuf *sb; 7293 int rc, i; 7294 7295 MPASS(chip_id(sc) <= CHELSIO_T5); 7296 7297 rc = sysctl_wire_old_buffer(req, 0); 7298 if (rc != 0) 7299 return (rc); 7300 7301 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7302 if (sb == NULL) 7303 return (ENOMEM); 7304 7305 sbuf_printf(sb, 7306 "Idx Ethernet address Mask Vld Ports PF" 7307 " VF Replication P0 P1 P2 P3 ML"); 7308 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7309 uint64_t tcamx, tcamy, mask; 7310 uint32_t cls_lo, cls_hi; 7311 uint8_t addr[ETHER_ADDR_LEN]; 7312 7313 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 7314 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 7315 if (tcamx & tcamy) 7316 continue; 7317 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7318 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7319 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7320 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 7321 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 7322 addr[3], addr[4], addr[5], (uintmax_t)mask, 7323 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 7324 G_PORTMAP(cls_hi), G_PF(cls_lo), 7325 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 7326 7327 if (cls_lo & F_REPLICATE) { 7328 struct fw_ldst_cmd ldst_cmd; 7329 7330 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7331 ldst_cmd.op_to_addrspace = 7332 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7333 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7334 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7335 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7336 ldst_cmd.u.mps.rplc.fid_idx = 7337 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7338 V_FW_LDST_CMD_IDX(i)); 7339 7340 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7341 "t4mps"); 7342 if (rc) 7343 break; 7344 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7345 sizeof(ldst_cmd), &ldst_cmd); 7346 end_synchronized_op(sc, 0); 7347 7348 if (rc != 0) { 7349 sbuf_printf(sb, "%36d", rc); 7350 rc = 0; 7351 } else { 7352 sbuf_printf(sb, " %08x %08x %08x %08x", 7353 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7354 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7355 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7356 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7357 } 7358 } else 7359 sbuf_printf(sb, "%36s", ""); 7360 7361 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 7362 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 7363 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 7364 } 7365 7366 if (rc) 7367 (void) sbuf_finish(sb); 7368 else 7369 rc = sbuf_finish(sb); 7370 sbuf_delete(sb); 7371 7372 return (rc); 7373 } 7374 7375 static int 7376 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 7377 { 7378 struct adapter *sc = arg1; 7379 struct sbuf *sb; 7380 int rc, i; 7381 7382 MPASS(chip_id(sc) > CHELSIO_T5); 7383 7384 rc = sysctl_wire_old_buffer(req, 0); 7385 if (rc != 0) 7386 return (rc); 7387 7388 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7389 if (sb == NULL) 7390 return (ENOMEM); 7391 7392 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 7393 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 7394 " Replication" 7395 " P0 P1 P2 P3 ML\n"); 7396 7397 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7398 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 7399 uint16_t ivlan; 7400 uint64_t tcamx, tcamy, val, mask; 7401 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 7402 uint8_t addr[ETHER_ADDR_LEN]; 7403 7404 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 7405 if (i < 256) 7406 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 7407 else 7408 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 7409 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7410 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7411 tcamy = G_DMACH(val) << 32; 7412 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7413 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7414 lookup_type = G_DATALKPTYPE(data2); 7415 port_num = G_DATAPORTNUM(data2); 7416 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7417 /* Inner header VNI */ 7418 vniy = ((data2 & F_DATAVIDH2) << 23) | 7419 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7420 dip_hit = data2 & F_DATADIPHIT; 7421 vlan_vld = 0; 7422 } else { 7423 vniy = 0; 7424 dip_hit = 0; 7425 vlan_vld = data2 & F_DATAVIDH2; 7426 ivlan = G_VIDL(val); 7427 } 7428 7429 ctl |= V_CTLXYBITSEL(1); 7430 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7431 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7432 tcamx = G_DMACH(val) << 32; 7433 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7434 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7435 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7436 /* Inner header VNI mask */ 7437 vnix = ((data2 & F_DATAVIDH2) << 23) | 7438 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7439 } else 7440 vnix = 0; 7441 7442 if (tcamx & tcamy) 7443 continue; 7444 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7445 7446 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7447 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7448 7449 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7450 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7451 "%012jx %06x %06x - - %3c" 7452 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 7453 addr[1], addr[2], addr[3], addr[4], addr[5], 7454 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 7455 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7456 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7457 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7458 } else { 7459 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7460 "%012jx - - ", i, addr[0], addr[1], 7461 addr[2], addr[3], addr[4], addr[5], 7462 (uintmax_t)mask); 7463 7464 if (vlan_vld) 7465 sbuf_printf(sb, "%4u Y ", ivlan); 7466 else 7467 sbuf_printf(sb, " - N "); 7468 7469 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 7470 lookup_type ? 'I' : 'O', port_num, 7471 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7472 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7473 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7474 } 7475 7476 7477 if (cls_lo & F_T6_REPLICATE) { 7478 struct fw_ldst_cmd ldst_cmd; 7479 7480 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7481 ldst_cmd.op_to_addrspace = 7482 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7483 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7484 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7485 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7486 ldst_cmd.u.mps.rplc.fid_idx = 7487 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7488 V_FW_LDST_CMD_IDX(i)); 7489 7490 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7491 "t6mps"); 7492 if (rc) 7493 break; 7494 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7495 sizeof(ldst_cmd), &ldst_cmd); 7496 end_synchronized_op(sc, 0); 7497 7498 if (rc != 0) { 7499 sbuf_printf(sb, "%72d", rc); 7500 rc = 0; 7501 } else { 7502 sbuf_printf(sb, " %08x %08x %08x %08x" 7503 " %08x %08x %08x %08x", 7504 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 7505 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 7506 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 7507 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 7508 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7509 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7510 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7511 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7512 } 7513 } else 7514 sbuf_printf(sb, "%72s", ""); 7515 7516 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 7517 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 7518 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 7519 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 7520 } 7521 7522 if (rc) 7523 (void) sbuf_finish(sb); 7524 else 7525 rc = sbuf_finish(sb); 7526 sbuf_delete(sb); 7527 7528 return (rc); 7529 } 7530 7531 static int 7532 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 7533 { 7534 struct adapter *sc = arg1; 7535 struct sbuf *sb; 7536 int rc; 7537 uint16_t mtus[NMTUS]; 7538 7539 rc = sysctl_wire_old_buffer(req, 0); 7540 if (rc != 0) 7541 return (rc); 7542 7543 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7544 if (sb == NULL) 7545 return (ENOMEM); 7546 7547 t4_read_mtu_tbl(sc, mtus, NULL); 7548 7549 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 7550 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 7551 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 7552 mtus[14], mtus[15]); 7553 7554 rc = sbuf_finish(sb); 7555 sbuf_delete(sb); 7556 7557 return (rc); 7558 } 7559 7560 static int 7561 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 7562 { 7563 struct adapter *sc = arg1; 7564 struct sbuf *sb; 7565 int rc, i; 7566 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 7567 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 7568 static const char *tx_stats[MAX_PM_NSTATS] = { 7569 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 7570 "Tx FIFO wait", NULL, "Tx latency" 7571 }; 7572 static const char *rx_stats[MAX_PM_NSTATS] = { 7573 "Read:", "Write bypass:", "Write mem:", "Flush:", 7574 "Rx FIFO wait", NULL, "Rx latency" 7575 }; 7576 7577 rc = sysctl_wire_old_buffer(req, 0); 7578 if (rc != 0) 7579 return (rc); 7580 7581 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7582 if (sb == NULL) 7583 return (ENOMEM); 7584 7585 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 7586 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 7587 7588 sbuf_printf(sb, " Tx pcmds Tx bytes"); 7589 for (i = 0; i < 4; i++) { 7590 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7591 tx_cyc[i]); 7592 } 7593 7594 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 7595 for (i = 0; i < 4; i++) { 7596 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7597 rx_cyc[i]); 7598 } 7599 7600 if (chip_id(sc) > CHELSIO_T5) { 7601 sbuf_printf(sb, 7602 "\n Total wait Total occupancy"); 7603 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7604 tx_cyc[i]); 7605 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7606 rx_cyc[i]); 7607 7608 i += 2; 7609 MPASS(i < nitems(tx_stats)); 7610 7611 sbuf_printf(sb, 7612 "\n Reads Total wait"); 7613 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7614 tx_cyc[i]); 7615 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7616 rx_cyc[i]); 7617 } 7618 7619 rc = sbuf_finish(sb); 7620 sbuf_delete(sb); 7621 7622 return (rc); 7623 } 7624 7625 static int 7626 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 7627 { 7628 struct adapter *sc = arg1; 7629 struct sbuf *sb; 7630 int rc; 7631 struct tp_rdma_stats stats; 7632 7633 rc = sysctl_wire_old_buffer(req, 0); 7634 if (rc != 0) 7635 return (rc); 7636 7637 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7638 if (sb == NULL) 7639 return (ENOMEM); 7640 7641 mtx_lock(&sc->reg_lock); 7642 t4_tp_get_rdma_stats(sc, &stats, 0); 7643 mtx_unlock(&sc->reg_lock); 7644 7645 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 7646 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 7647 7648 rc = sbuf_finish(sb); 7649 sbuf_delete(sb); 7650 7651 return (rc); 7652 } 7653 7654 static int 7655 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 7656 { 7657 struct adapter *sc = arg1; 7658 struct sbuf *sb; 7659 int rc; 7660 struct tp_tcp_stats v4, v6; 7661 7662 rc = sysctl_wire_old_buffer(req, 0); 7663 if (rc != 0) 7664 return (rc); 7665 7666 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7667 if (sb == NULL) 7668 return (ENOMEM); 7669 7670 mtx_lock(&sc->reg_lock); 7671 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 7672 mtx_unlock(&sc->reg_lock); 7673 7674 sbuf_printf(sb, 7675 " IP IPv6\n"); 7676 sbuf_printf(sb, "OutRsts: %20u %20u\n", 7677 v4.tcp_out_rsts, v6.tcp_out_rsts); 7678 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 7679 v4.tcp_in_segs, v6.tcp_in_segs); 7680 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 7681 v4.tcp_out_segs, v6.tcp_out_segs); 7682 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 7683 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 7684 7685 rc = sbuf_finish(sb); 7686 sbuf_delete(sb); 7687 7688 return (rc); 7689 } 7690 7691 static int 7692 sysctl_tids(SYSCTL_HANDLER_ARGS) 7693 { 7694 struct adapter *sc = arg1; 7695 struct sbuf *sb; 7696 int rc; 7697 struct tid_info *t = &sc->tids; 7698 7699 rc = sysctl_wire_old_buffer(req, 0); 7700 if (rc != 0) 7701 return (rc); 7702 7703 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7704 if (sb == NULL) 7705 return (ENOMEM); 7706 7707 if (t->natids) { 7708 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 7709 t->atids_in_use); 7710 } 7711 7712 if (t->ntids) { 7713 sbuf_printf(sb, "TID range: "); 7714 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7715 uint32_t b, hb; 7716 7717 if (chip_id(sc) <= CHELSIO_T5) { 7718 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 7719 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 7720 } else { 7721 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 7722 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 7723 } 7724 7725 if (b) 7726 sbuf_printf(sb, "0-%u, ", b - 1); 7727 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 7728 } else 7729 sbuf_printf(sb, "0-%u", t->ntids - 1); 7730 sbuf_printf(sb, ", in use: %u\n", 7731 atomic_load_acq_int(&t->tids_in_use)); 7732 } 7733 7734 if (t->nstids) { 7735 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 7736 t->stid_base + t->nstids - 1, t->stids_in_use); 7737 } 7738 7739 if (t->nftids) { 7740 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 7741 t->ftid_base + t->nftids - 1); 7742 } 7743 7744 if (t->netids) { 7745 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 7746 t->etid_base + t->netids - 1); 7747 } 7748 7749 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 7750 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 7751 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 7752 7753 rc = sbuf_finish(sb); 7754 sbuf_delete(sb); 7755 7756 return (rc); 7757 } 7758 7759 static int 7760 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 7761 { 7762 struct adapter *sc = arg1; 7763 struct sbuf *sb; 7764 int rc; 7765 struct tp_err_stats stats; 7766 7767 rc = sysctl_wire_old_buffer(req, 0); 7768 if (rc != 0) 7769 return (rc); 7770 7771 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7772 if (sb == NULL) 7773 return (ENOMEM); 7774 7775 mtx_lock(&sc->reg_lock); 7776 t4_tp_get_err_stats(sc, &stats, 0); 7777 mtx_unlock(&sc->reg_lock); 7778 7779 if (sc->chip_params->nchan > 2) { 7780 sbuf_printf(sb, " channel 0 channel 1" 7781 " channel 2 channel 3\n"); 7782 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 7783 stats.mac_in_errs[0], stats.mac_in_errs[1], 7784 stats.mac_in_errs[2], stats.mac_in_errs[3]); 7785 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 7786 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 7787 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 7788 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 7789 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 7790 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 7791 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 7792 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 7793 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 7794 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 7795 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 7796 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 7797 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 7798 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 7799 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 7800 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 7801 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 7802 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 7803 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 7804 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 7805 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 7806 } else { 7807 sbuf_printf(sb, " channel 0 channel 1\n"); 7808 sbuf_printf(sb, "macInErrs: %10u %10u\n", 7809 stats.mac_in_errs[0], stats.mac_in_errs[1]); 7810 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 7811 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 7812 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 7813 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 7814 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 7815 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 7816 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 7817 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 7818 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 7819 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 7820 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 7821 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 7822 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 7823 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 7824 } 7825 7826 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 7827 stats.ofld_no_neigh, stats.ofld_cong_defer); 7828 7829 rc = sbuf_finish(sb); 7830 sbuf_delete(sb); 7831 7832 return (rc); 7833 } 7834 7835 static int 7836 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 7837 { 7838 struct adapter *sc = arg1; 7839 struct tp_params *tpp = &sc->params.tp; 7840 u_int mask; 7841 int rc; 7842 7843 mask = tpp->la_mask >> 16; 7844 rc = sysctl_handle_int(oidp, &mask, 0, req); 7845 if (rc != 0 || req->newptr == NULL) 7846 return (rc); 7847 if (mask > 0xffff) 7848 return (EINVAL); 7849 tpp->la_mask = mask << 16; 7850 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 7851 7852 return (0); 7853 } 7854 7855 struct field_desc { 7856 const char *name; 7857 u_int start; 7858 u_int width; 7859 }; 7860 7861 static void 7862 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 7863 { 7864 char buf[32]; 7865 int line_size = 0; 7866 7867 while (f->name) { 7868 uint64_t mask = (1ULL << f->width) - 1; 7869 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 7870 ((uintmax_t)v >> f->start) & mask); 7871 7872 if (line_size + len >= 79) { 7873 line_size = 8; 7874 sbuf_printf(sb, "\n "); 7875 } 7876 sbuf_printf(sb, "%s ", buf); 7877 line_size += len + 1; 7878 f++; 7879 } 7880 sbuf_printf(sb, "\n"); 7881 } 7882 7883 static const struct field_desc tp_la0[] = { 7884 { "RcfOpCodeOut", 60, 4 }, 7885 { "State", 56, 4 }, 7886 { "WcfState", 52, 4 }, 7887 { "RcfOpcSrcOut", 50, 2 }, 7888 { "CRxError", 49, 1 }, 7889 { "ERxError", 48, 1 }, 7890 { "SanityFailed", 47, 1 }, 7891 { "SpuriousMsg", 46, 1 }, 7892 { "FlushInputMsg", 45, 1 }, 7893 { "FlushInputCpl", 44, 1 }, 7894 { "RssUpBit", 43, 1 }, 7895 { "RssFilterHit", 42, 1 }, 7896 { "Tid", 32, 10 }, 7897 { "InitTcb", 31, 1 }, 7898 { "LineNumber", 24, 7 }, 7899 { "Emsg", 23, 1 }, 7900 { "EdataOut", 22, 1 }, 7901 { "Cmsg", 21, 1 }, 7902 { "CdataOut", 20, 1 }, 7903 { "EreadPdu", 19, 1 }, 7904 { "CreadPdu", 18, 1 }, 7905 { "TunnelPkt", 17, 1 }, 7906 { "RcfPeerFin", 16, 1 }, 7907 { "RcfReasonOut", 12, 4 }, 7908 { "TxCchannel", 10, 2 }, 7909 { "RcfTxChannel", 8, 2 }, 7910 { "RxEchannel", 6, 2 }, 7911 { "RcfRxChannel", 5, 1 }, 7912 { "RcfDataOutSrdy", 4, 1 }, 7913 { "RxDvld", 3, 1 }, 7914 { "RxOoDvld", 2, 1 }, 7915 { "RxCongestion", 1, 1 }, 7916 { "TxCongestion", 0, 1 }, 7917 { NULL } 7918 }; 7919 7920 static const struct field_desc tp_la1[] = { 7921 { "CplCmdIn", 56, 8 }, 7922 { "CplCmdOut", 48, 8 }, 7923 { "ESynOut", 47, 1 }, 7924 { "EAckOut", 46, 1 }, 7925 { "EFinOut", 45, 1 }, 7926 { "ERstOut", 44, 1 }, 7927 { "SynIn", 43, 1 }, 7928 { "AckIn", 42, 1 }, 7929 { "FinIn", 41, 1 }, 7930 { "RstIn", 40, 1 }, 7931 { "DataIn", 39, 1 }, 7932 { "DataInVld", 38, 1 }, 7933 { "PadIn", 37, 1 }, 7934 { "RxBufEmpty", 36, 1 }, 7935 { "RxDdp", 35, 1 }, 7936 { "RxFbCongestion", 34, 1 }, 7937 { "TxFbCongestion", 33, 1 }, 7938 { "TxPktSumSrdy", 32, 1 }, 7939 { "RcfUlpType", 28, 4 }, 7940 { "Eread", 27, 1 }, 7941 { "Ebypass", 26, 1 }, 7942 { "Esave", 25, 1 }, 7943 { "Static0", 24, 1 }, 7944 { "Cread", 23, 1 }, 7945 { "Cbypass", 22, 1 }, 7946 { "Csave", 21, 1 }, 7947 { "CPktOut", 20, 1 }, 7948 { "RxPagePoolFull", 18, 2 }, 7949 { "RxLpbkPkt", 17, 1 }, 7950 { "TxLpbkPkt", 16, 1 }, 7951 { "RxVfValid", 15, 1 }, 7952 { "SynLearned", 14, 1 }, 7953 { "SetDelEntry", 13, 1 }, 7954 { "SetInvEntry", 12, 1 }, 7955 { "CpcmdDvld", 11, 1 }, 7956 { "CpcmdSave", 10, 1 }, 7957 { "RxPstructsFull", 8, 2 }, 7958 { "EpcmdDvld", 7, 1 }, 7959 { "EpcmdFlush", 6, 1 }, 7960 { "EpcmdTrimPrefix", 5, 1 }, 7961 { "EpcmdTrimPostfix", 4, 1 }, 7962 { "ERssIp4Pkt", 3, 1 }, 7963 { "ERssIp6Pkt", 2, 1 }, 7964 { "ERssTcpUdpPkt", 1, 1 }, 7965 { "ERssFceFipPkt", 0, 1 }, 7966 { NULL } 7967 }; 7968 7969 static const struct field_desc tp_la2[] = { 7970 { "CplCmdIn", 56, 8 }, 7971 { "MpsVfVld", 55, 1 }, 7972 { "MpsPf", 52, 3 }, 7973 { "MpsVf", 44, 8 }, 7974 { "SynIn", 43, 1 }, 7975 { "AckIn", 42, 1 }, 7976 { "FinIn", 41, 1 }, 7977 { "RstIn", 40, 1 }, 7978 { "DataIn", 39, 1 }, 7979 { "DataInVld", 38, 1 }, 7980 { "PadIn", 37, 1 }, 7981 { "RxBufEmpty", 36, 1 }, 7982 { "RxDdp", 35, 1 }, 7983 { "RxFbCongestion", 34, 1 }, 7984 { "TxFbCongestion", 33, 1 }, 7985 { "TxPktSumSrdy", 32, 1 }, 7986 { "RcfUlpType", 28, 4 }, 7987 { "Eread", 27, 1 }, 7988 { "Ebypass", 26, 1 }, 7989 { "Esave", 25, 1 }, 7990 { "Static0", 24, 1 }, 7991 { "Cread", 23, 1 }, 7992 { "Cbypass", 22, 1 }, 7993 { "Csave", 21, 1 }, 7994 { "CPktOut", 20, 1 }, 7995 { "RxPagePoolFull", 18, 2 }, 7996 { "RxLpbkPkt", 17, 1 }, 7997 { "TxLpbkPkt", 16, 1 }, 7998 { "RxVfValid", 15, 1 }, 7999 { "SynLearned", 14, 1 }, 8000 { "SetDelEntry", 13, 1 }, 8001 { "SetInvEntry", 12, 1 }, 8002 { "CpcmdDvld", 11, 1 }, 8003 { "CpcmdSave", 10, 1 }, 8004 { "RxPstructsFull", 8, 2 }, 8005 { "EpcmdDvld", 7, 1 }, 8006 { "EpcmdFlush", 6, 1 }, 8007 { "EpcmdTrimPrefix", 5, 1 }, 8008 { "EpcmdTrimPostfix", 4, 1 }, 8009 { "ERssIp4Pkt", 3, 1 }, 8010 { "ERssIp6Pkt", 2, 1 }, 8011 { "ERssTcpUdpPkt", 1, 1 }, 8012 { "ERssFceFipPkt", 0, 1 }, 8013 { NULL } 8014 }; 8015 8016 static void 8017 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8018 { 8019 8020 field_desc_show(sb, *p, tp_la0); 8021 } 8022 8023 static void 8024 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8025 { 8026 8027 if (idx) 8028 sbuf_printf(sb, "\n"); 8029 field_desc_show(sb, p[0], tp_la0); 8030 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8031 field_desc_show(sb, p[1], tp_la0); 8032 } 8033 8034 static void 8035 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 8036 { 8037 8038 if (idx) 8039 sbuf_printf(sb, "\n"); 8040 field_desc_show(sb, p[0], tp_la0); 8041 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8042 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 8043 } 8044 8045 static int 8046 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 8047 { 8048 struct adapter *sc = arg1; 8049 struct sbuf *sb; 8050 uint64_t *buf, *p; 8051 int rc; 8052 u_int i, inc; 8053 void (*show_func)(struct sbuf *, uint64_t *, int); 8054 8055 rc = sysctl_wire_old_buffer(req, 0); 8056 if (rc != 0) 8057 return (rc); 8058 8059 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8060 if (sb == NULL) 8061 return (ENOMEM); 8062 8063 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 8064 8065 t4_tp_read_la(sc, buf, NULL); 8066 p = buf; 8067 8068 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 8069 case 2: 8070 inc = 2; 8071 show_func = tp_la_show2; 8072 break; 8073 case 3: 8074 inc = 2; 8075 show_func = tp_la_show3; 8076 break; 8077 default: 8078 inc = 1; 8079 show_func = tp_la_show; 8080 } 8081 8082 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 8083 (*show_func)(sb, p, i); 8084 8085 rc = sbuf_finish(sb); 8086 sbuf_delete(sb); 8087 free(buf, M_CXGBE); 8088 return (rc); 8089 } 8090 8091 static int 8092 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 8093 { 8094 struct adapter *sc = arg1; 8095 struct sbuf *sb; 8096 int rc; 8097 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 8098 8099 rc = sysctl_wire_old_buffer(req, 0); 8100 if (rc != 0) 8101 return (rc); 8102 8103 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8104 if (sb == NULL) 8105 return (ENOMEM); 8106 8107 t4_get_chan_txrate(sc, nrate, orate); 8108 8109 if (sc->chip_params->nchan > 2) { 8110 sbuf_printf(sb, " channel 0 channel 1" 8111 " channel 2 channel 3\n"); 8112 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 8113 nrate[0], nrate[1], nrate[2], nrate[3]); 8114 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 8115 orate[0], orate[1], orate[2], orate[3]); 8116 } else { 8117 sbuf_printf(sb, " channel 0 channel 1\n"); 8118 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 8119 nrate[0], nrate[1]); 8120 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 8121 orate[0], orate[1]); 8122 } 8123 8124 rc = sbuf_finish(sb); 8125 sbuf_delete(sb); 8126 8127 return (rc); 8128 } 8129 8130 static int 8131 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 8132 { 8133 struct adapter *sc = arg1; 8134 struct sbuf *sb; 8135 uint32_t *buf, *p; 8136 int rc, i; 8137 8138 rc = sysctl_wire_old_buffer(req, 0); 8139 if (rc != 0) 8140 return (rc); 8141 8142 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8143 if (sb == NULL) 8144 return (ENOMEM); 8145 8146 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 8147 M_ZERO | M_WAITOK); 8148 8149 t4_ulprx_read_la(sc, buf); 8150 p = buf; 8151 8152 sbuf_printf(sb, " Pcmd Type Message" 8153 " Data"); 8154 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 8155 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 8156 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 8157 } 8158 8159 rc = sbuf_finish(sb); 8160 sbuf_delete(sb); 8161 free(buf, M_CXGBE); 8162 return (rc); 8163 } 8164 8165 static int 8166 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 8167 { 8168 struct adapter *sc = arg1; 8169 struct sbuf *sb; 8170 int rc, v; 8171 8172 MPASS(chip_id(sc) >= CHELSIO_T5); 8173 8174 rc = sysctl_wire_old_buffer(req, 0); 8175 if (rc != 0) 8176 return (rc); 8177 8178 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8179 if (sb == NULL) 8180 return (ENOMEM); 8181 8182 v = t4_read_reg(sc, A_SGE_STAT_CFG); 8183 if (G_STATSOURCE_T5(v) == 7) { 8184 int mode; 8185 8186 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 8187 if (mode == 0) { 8188 sbuf_printf(sb, "total %d, incomplete %d", 8189 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8190 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8191 } else if (mode == 1) { 8192 sbuf_printf(sb, "total %d, data overflow %d", 8193 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8194 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8195 } else { 8196 sbuf_printf(sb, "unknown mode %d", mode); 8197 } 8198 } 8199 rc = sbuf_finish(sb); 8200 sbuf_delete(sb); 8201 8202 return (rc); 8203 } 8204 8205 static int 8206 sysctl_tc_params(SYSCTL_HANDLER_ARGS) 8207 { 8208 struct adapter *sc = arg1; 8209 struct tx_cl_rl_params tc; 8210 struct sbuf *sb; 8211 int i, rc, port_id, mbps, gbps; 8212 8213 rc = sysctl_wire_old_buffer(req, 0); 8214 if (rc != 0) 8215 return (rc); 8216 8217 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8218 if (sb == NULL) 8219 return (ENOMEM); 8220 8221 port_id = arg2 >> 16; 8222 MPASS(port_id < sc->params.nports); 8223 MPASS(sc->port[port_id] != NULL); 8224 i = arg2 & 0xffff; 8225 MPASS(i < sc->chip_params->nsched_cls); 8226 8227 mtx_lock(&sc->tc_lock); 8228 tc = sc->port[port_id]->sched_params->cl_rl[i]; 8229 mtx_unlock(&sc->tc_lock); 8230 8231 if (tc.flags & TX_CLRL_ERROR) { 8232 sbuf_printf(sb, "error"); 8233 goto done; 8234 } 8235 8236 if (tc.ratemode == SCHED_CLASS_RATEMODE_REL) { 8237 /* XXX: top speed or actual link speed? */ 8238 gbps = port_top_speed(sc->port[port_id]); 8239 sbuf_printf(sb, " %u%% of %uGbps", tc.maxrate, gbps); 8240 } else if (tc.ratemode == SCHED_CLASS_RATEMODE_ABS) { 8241 switch (tc.rateunit) { 8242 case SCHED_CLASS_RATEUNIT_BITS: 8243 mbps = tc.maxrate / 1000; 8244 gbps = tc.maxrate / 1000000; 8245 if (tc.maxrate == gbps * 1000000) 8246 sbuf_printf(sb, " %uGbps", gbps); 8247 else if (tc.maxrate == mbps * 1000) 8248 sbuf_printf(sb, " %uMbps", mbps); 8249 else 8250 sbuf_printf(sb, " %uKbps", tc.maxrate); 8251 break; 8252 case SCHED_CLASS_RATEUNIT_PKTS: 8253 sbuf_printf(sb, " %upps", tc.maxrate); 8254 break; 8255 default: 8256 rc = ENXIO; 8257 goto done; 8258 } 8259 } 8260 8261 switch (tc.mode) { 8262 case SCHED_CLASS_MODE_CLASS: 8263 sbuf_printf(sb, " aggregate"); 8264 break; 8265 case SCHED_CLASS_MODE_FLOW: 8266 sbuf_printf(sb, " per-flow"); 8267 break; 8268 default: 8269 rc = ENXIO; 8270 goto done; 8271 } 8272 8273 done: 8274 if (rc == 0) 8275 rc = sbuf_finish(sb); 8276 sbuf_delete(sb); 8277 8278 return (rc); 8279 } 8280 #endif 8281 8282 #ifdef TCP_OFFLOAD 8283 static int 8284 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 8285 { 8286 struct adapter *sc = arg1; 8287 int *old_ports, *new_ports; 8288 int i, new_count, rc; 8289 8290 if (req->newptr == NULL && req->oldptr == NULL) 8291 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 8292 sizeof(sc->tt.tls_rx_ports[0]))); 8293 8294 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 8295 if (rc) 8296 return (rc); 8297 8298 if (sc->tt.num_tls_rx_ports == 0) { 8299 i = -1; 8300 rc = SYSCTL_OUT(req, &i, sizeof(i)); 8301 } else 8302 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 8303 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 8304 if (rc == 0 && req->newptr != NULL) { 8305 new_count = req->newlen / sizeof(new_ports[0]); 8306 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 8307 M_WAITOK); 8308 rc = SYSCTL_IN(req, new_ports, new_count * 8309 sizeof(new_ports[0])); 8310 if (rc) 8311 goto err; 8312 8313 /* Allow setting to a single '-1' to clear the list. */ 8314 if (new_count == 1 && new_ports[0] == -1) { 8315 ADAPTER_LOCK(sc); 8316 old_ports = sc->tt.tls_rx_ports; 8317 sc->tt.tls_rx_ports = NULL; 8318 sc->tt.num_tls_rx_ports = 0; 8319 ADAPTER_UNLOCK(sc); 8320 free(old_ports, M_CXGBE); 8321 } else { 8322 for (i = 0; i < new_count; i++) { 8323 if (new_ports[i] < 1 || 8324 new_ports[i] > IPPORT_MAX) { 8325 rc = EINVAL; 8326 goto err; 8327 } 8328 } 8329 8330 ADAPTER_LOCK(sc); 8331 old_ports = sc->tt.tls_rx_ports; 8332 sc->tt.tls_rx_ports = new_ports; 8333 sc->tt.num_tls_rx_ports = new_count; 8334 ADAPTER_UNLOCK(sc); 8335 free(old_ports, M_CXGBE); 8336 new_ports = NULL; 8337 } 8338 err: 8339 free(new_ports, M_CXGBE); 8340 } 8341 end_synchronized_op(sc, 0); 8342 return (rc); 8343 } 8344 8345 static void 8346 unit_conv(char *buf, size_t len, u_int val, u_int factor) 8347 { 8348 u_int rem = val % factor; 8349 8350 if (rem == 0) 8351 snprintf(buf, len, "%u", val / factor); 8352 else { 8353 while (rem % 10 == 0) 8354 rem /= 10; 8355 snprintf(buf, len, "%u.%u", val / factor, rem); 8356 } 8357 } 8358 8359 static int 8360 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 8361 { 8362 struct adapter *sc = arg1; 8363 char buf[16]; 8364 u_int res, re; 8365 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8366 8367 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8368 switch (arg2) { 8369 case 0: 8370 /* timer_tick */ 8371 re = G_TIMERRESOLUTION(res); 8372 break; 8373 case 1: 8374 /* TCP timestamp tick */ 8375 re = G_TIMESTAMPRESOLUTION(res); 8376 break; 8377 case 2: 8378 /* DACK tick */ 8379 re = G_DELAYEDACKRESOLUTION(res); 8380 break; 8381 default: 8382 return (EDOOFUS); 8383 } 8384 8385 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 8386 8387 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 8388 } 8389 8390 static int 8391 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 8392 { 8393 struct adapter *sc = arg1; 8394 u_int res, dack_re, v; 8395 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8396 8397 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8398 dack_re = G_DELAYEDACKRESOLUTION(res); 8399 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 8400 8401 return (sysctl_handle_int(oidp, &v, 0, req)); 8402 } 8403 8404 static int 8405 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 8406 { 8407 struct adapter *sc = arg1; 8408 int reg = arg2; 8409 u_int tre; 8410 u_long tp_tick_us, v; 8411 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8412 8413 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 8414 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 8415 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 8416 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 8417 8418 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 8419 tp_tick_us = (cclk_ps << tre) / 1000000; 8420 8421 if (reg == A_TP_INIT_SRTT) 8422 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 8423 else 8424 v = tp_tick_us * t4_read_reg(sc, reg); 8425 8426 return (sysctl_handle_long(oidp, &v, 0, req)); 8427 } 8428 8429 /* 8430 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 8431 * passed to this function. 8432 */ 8433 static int 8434 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 8435 { 8436 struct adapter *sc = arg1; 8437 int idx = arg2; 8438 u_int v; 8439 8440 MPASS(idx >= 0 && idx <= 24); 8441 8442 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 8443 8444 return (sysctl_handle_int(oidp, &v, 0, req)); 8445 } 8446 8447 static int 8448 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 8449 { 8450 struct adapter *sc = arg1; 8451 int idx = arg2; 8452 u_int shift, v, r; 8453 8454 MPASS(idx >= 0 && idx < 16); 8455 8456 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 8457 shift = (idx & 3) << 3; 8458 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 8459 8460 return (sysctl_handle_int(oidp, &v, 0, req)); 8461 } 8462 8463 static int 8464 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 8465 { 8466 struct vi_info *vi = arg1; 8467 struct adapter *sc = vi->pi->adapter; 8468 int idx, rc, i; 8469 struct sge_ofld_rxq *ofld_rxq; 8470 uint8_t v; 8471 8472 idx = vi->ofld_tmr_idx; 8473 8474 rc = sysctl_handle_int(oidp, &idx, 0, req); 8475 if (rc != 0 || req->newptr == NULL) 8476 return (rc); 8477 8478 if (idx < 0 || idx >= SGE_NTIMERS) 8479 return (EINVAL); 8480 8481 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8482 "t4otmr"); 8483 if (rc) 8484 return (rc); 8485 8486 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 8487 for_each_ofld_rxq(vi, i, ofld_rxq) { 8488 #ifdef atomic_store_rel_8 8489 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 8490 #else 8491 ofld_rxq->iq.intr_params = v; 8492 #endif 8493 } 8494 vi->ofld_tmr_idx = idx; 8495 8496 end_synchronized_op(sc, LOCK_HELD); 8497 return (0); 8498 } 8499 8500 static int 8501 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 8502 { 8503 struct vi_info *vi = arg1; 8504 struct adapter *sc = vi->pi->adapter; 8505 int idx, rc; 8506 8507 idx = vi->ofld_pktc_idx; 8508 8509 rc = sysctl_handle_int(oidp, &idx, 0, req); 8510 if (rc != 0 || req->newptr == NULL) 8511 return (rc); 8512 8513 if (idx < -1 || idx >= SGE_NCOUNTERS) 8514 return (EINVAL); 8515 8516 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8517 "t4opktc"); 8518 if (rc) 8519 return (rc); 8520 8521 if (vi->flags & VI_INIT_DONE) 8522 rc = EBUSY; /* cannot be changed once the queues are created */ 8523 else 8524 vi->ofld_pktc_idx = idx; 8525 8526 end_synchronized_op(sc, LOCK_HELD); 8527 return (rc); 8528 } 8529 #endif 8530 8531 static uint32_t 8532 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf) 8533 { 8534 uint32_t mode; 8535 8536 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR | 8537 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT; 8538 8539 if (fconf & F_FRAGMENTATION) 8540 mode |= T4_FILTER_IP_FRAGMENT; 8541 8542 if (fconf & F_MPSHITTYPE) 8543 mode |= T4_FILTER_MPS_HIT_TYPE; 8544 8545 if (fconf & F_MACMATCH) 8546 mode |= T4_FILTER_MAC_IDX; 8547 8548 if (fconf & F_ETHERTYPE) 8549 mode |= T4_FILTER_ETH_TYPE; 8550 8551 if (fconf & F_PROTOCOL) 8552 mode |= T4_FILTER_IP_PROTO; 8553 8554 if (fconf & F_TOS) 8555 mode |= T4_FILTER_IP_TOS; 8556 8557 if (fconf & F_VLAN) 8558 mode |= T4_FILTER_VLAN; 8559 8560 if (fconf & F_VNIC_ID) { 8561 mode |= T4_FILTER_VNIC; 8562 if (iconf & F_VNIC) 8563 mode |= T4_FILTER_IC_VNIC; 8564 } 8565 8566 if (fconf & F_PORT) 8567 mode |= T4_FILTER_PORT; 8568 8569 if (fconf & F_FCOE) 8570 mode |= T4_FILTER_FCoE; 8571 8572 return (mode); 8573 } 8574 8575 static uint32_t 8576 mode_to_fconf(uint32_t mode) 8577 { 8578 uint32_t fconf = 0; 8579 8580 if (mode & T4_FILTER_IP_FRAGMENT) 8581 fconf |= F_FRAGMENTATION; 8582 8583 if (mode & T4_FILTER_MPS_HIT_TYPE) 8584 fconf |= F_MPSHITTYPE; 8585 8586 if (mode & T4_FILTER_MAC_IDX) 8587 fconf |= F_MACMATCH; 8588 8589 if (mode & T4_FILTER_ETH_TYPE) 8590 fconf |= F_ETHERTYPE; 8591 8592 if (mode & T4_FILTER_IP_PROTO) 8593 fconf |= F_PROTOCOL; 8594 8595 if (mode & T4_FILTER_IP_TOS) 8596 fconf |= F_TOS; 8597 8598 if (mode & T4_FILTER_VLAN) 8599 fconf |= F_VLAN; 8600 8601 if (mode & T4_FILTER_VNIC) 8602 fconf |= F_VNIC_ID; 8603 8604 if (mode & T4_FILTER_PORT) 8605 fconf |= F_PORT; 8606 8607 if (mode & T4_FILTER_FCoE) 8608 fconf |= F_FCOE; 8609 8610 return (fconf); 8611 } 8612 8613 static uint32_t 8614 mode_to_iconf(uint32_t mode) 8615 { 8616 8617 if (mode & T4_FILTER_IC_VNIC) 8618 return (F_VNIC); 8619 return (0); 8620 } 8621 8622 static int check_fspec_against_fconf_iconf(struct adapter *sc, 8623 struct t4_filter_specification *fs) 8624 { 8625 struct tp_params *tpp = &sc->params.tp; 8626 uint32_t fconf = 0; 8627 8628 if (fs->val.frag || fs->mask.frag) 8629 fconf |= F_FRAGMENTATION; 8630 8631 if (fs->val.matchtype || fs->mask.matchtype) 8632 fconf |= F_MPSHITTYPE; 8633 8634 if (fs->val.macidx || fs->mask.macidx) 8635 fconf |= F_MACMATCH; 8636 8637 if (fs->val.ethtype || fs->mask.ethtype) 8638 fconf |= F_ETHERTYPE; 8639 8640 if (fs->val.proto || fs->mask.proto) 8641 fconf |= F_PROTOCOL; 8642 8643 if (fs->val.tos || fs->mask.tos) 8644 fconf |= F_TOS; 8645 8646 if (fs->val.vlan_vld || fs->mask.vlan_vld) 8647 fconf |= F_VLAN; 8648 8649 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) { 8650 fconf |= F_VNIC_ID; 8651 if (tpp->ingress_config & F_VNIC) 8652 return (EINVAL); 8653 } 8654 8655 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) { 8656 fconf |= F_VNIC_ID; 8657 if ((tpp->ingress_config & F_VNIC) == 0) 8658 return (EINVAL); 8659 } 8660 8661 if (fs->val.iport || fs->mask.iport) 8662 fconf |= F_PORT; 8663 8664 if (fs->val.fcoe || fs->mask.fcoe) 8665 fconf |= F_FCOE; 8666 8667 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map) 8668 return (E2BIG); 8669 8670 return (0); 8671 } 8672 8673 static int 8674 get_filter_mode(struct adapter *sc, uint32_t *mode) 8675 { 8676 struct tp_params *tpp = &sc->params.tp; 8677 8678 /* 8679 * We trust the cached values of the relevant TP registers. This means 8680 * things work reliably only if writes to those registers are always via 8681 * t4_set_filter_mode. 8682 */ 8683 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config); 8684 8685 return (0); 8686 } 8687 8688 static int 8689 set_filter_mode(struct adapter *sc, uint32_t mode) 8690 { 8691 struct tp_params *tpp = &sc->params.tp; 8692 uint32_t fconf, iconf; 8693 int rc; 8694 8695 iconf = mode_to_iconf(mode); 8696 if ((iconf ^ tpp->ingress_config) & F_VNIC) { 8697 /* 8698 * For now we just complain if A_TP_INGRESS_CONFIG is not 8699 * already set to the correct value for the requested filter 8700 * mode. It's not clear if it's safe to write to this register 8701 * on the fly. (And we trust the cached value of the register). 8702 */ 8703 return (EBUSY); 8704 } 8705 8706 fconf = mode_to_fconf(mode); 8707 8708 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8709 "t4setfm"); 8710 if (rc) 8711 return (rc); 8712 8713 if (sc->tids.ftids_in_use > 0) { 8714 rc = EBUSY; 8715 goto done; 8716 } 8717 8718 #ifdef TCP_OFFLOAD 8719 if (uld_active(sc, ULD_TOM)) { 8720 rc = EBUSY; 8721 goto done; 8722 } 8723 #endif 8724 8725 rc = -t4_set_filter_mode(sc, fconf, true); 8726 done: 8727 end_synchronized_op(sc, LOCK_HELD); 8728 return (rc); 8729 } 8730 8731 static inline uint64_t 8732 get_filter_hits(struct adapter *sc, uint32_t fid) 8733 { 8734 uint32_t tcb_addr; 8735 8736 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) + 8737 (fid + sc->tids.ftid_base) * TCB_SIZE; 8738 8739 if (is_t4(sc)) { 8740 uint64_t hits; 8741 8742 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8); 8743 return (be64toh(hits)); 8744 } else { 8745 uint32_t hits; 8746 8747 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4); 8748 return (be32toh(hits)); 8749 } 8750 } 8751 8752 static int 8753 get_filter(struct adapter *sc, struct t4_filter *t) 8754 { 8755 int i, rc, nfilters = sc->tids.nftids; 8756 struct filter_entry *f; 8757 8758 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8759 "t4getf"); 8760 if (rc) 8761 return (rc); 8762 8763 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL || 8764 t->idx >= nfilters) { 8765 t->idx = 0xffffffff; 8766 goto done; 8767 } 8768 8769 f = &sc->tids.ftid_tab[t->idx]; 8770 for (i = t->idx; i < nfilters; i++, f++) { 8771 if (f->valid) { 8772 t->idx = i; 8773 t->l2tidx = f->l2t ? f->l2t->idx : 0; 8774 t->smtidx = f->smtidx; 8775 if (f->fs.hitcnts) 8776 t->hits = get_filter_hits(sc, t->idx); 8777 else 8778 t->hits = UINT64_MAX; 8779 t->fs = f->fs; 8780 8781 goto done; 8782 } 8783 } 8784 8785 t->idx = 0xffffffff; 8786 done: 8787 end_synchronized_op(sc, LOCK_HELD); 8788 return (0); 8789 } 8790 8791 static int 8792 set_filter(struct adapter *sc, struct t4_filter *t) 8793 { 8794 unsigned int nfilters, nports; 8795 struct filter_entry *f; 8796 int i, rc; 8797 8798 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf"); 8799 if (rc) 8800 return (rc); 8801 8802 nfilters = sc->tids.nftids; 8803 nports = sc->params.nports; 8804 8805 if (nfilters == 0) { 8806 rc = ENOTSUP; 8807 goto done; 8808 } 8809 8810 if (t->idx >= nfilters) { 8811 rc = EINVAL; 8812 goto done; 8813 } 8814 8815 /* Validate against the global filter mode and ingress config */ 8816 rc = check_fspec_against_fconf_iconf(sc, &t->fs); 8817 if (rc != 0) 8818 goto done; 8819 8820 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) { 8821 rc = EINVAL; 8822 goto done; 8823 } 8824 8825 if (t->fs.val.iport >= nports) { 8826 rc = EINVAL; 8827 goto done; 8828 } 8829 8830 /* Can't specify an iq if not steering to it */ 8831 if (!t->fs.dirsteer && t->fs.iq) { 8832 rc = EINVAL; 8833 goto done; 8834 } 8835 8836 /* IPv6 filter idx must be 4 aligned */ 8837 if (t->fs.type == 1 && 8838 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) { 8839 rc = EINVAL; 8840 goto done; 8841 } 8842 8843 if (!(sc->flags & FULL_INIT_DONE) && 8844 ((rc = adapter_full_init(sc)) != 0)) 8845 goto done; 8846 8847 if (sc->tids.ftid_tab == NULL) { 8848 KASSERT(sc->tids.ftids_in_use == 0, 8849 ("%s: no memory allocated but filters_in_use > 0", 8850 __func__)); 8851 8852 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) * 8853 nfilters, M_CXGBE, M_NOWAIT | M_ZERO); 8854 if (sc->tids.ftid_tab == NULL) { 8855 rc = ENOMEM; 8856 goto done; 8857 } 8858 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF); 8859 } 8860 8861 for (i = 0; i < 4; i++) { 8862 f = &sc->tids.ftid_tab[t->idx + i]; 8863 8864 if (f->pending || f->valid) { 8865 rc = EBUSY; 8866 goto done; 8867 } 8868 if (f->locked) { 8869 rc = EPERM; 8870 goto done; 8871 } 8872 8873 if (t->fs.type == 0) 8874 break; 8875 } 8876 8877 f = &sc->tids.ftid_tab[t->idx]; 8878 f->fs = t->fs; 8879 8880 rc = set_filter_wr(sc, t->idx); 8881 done: 8882 end_synchronized_op(sc, 0); 8883 8884 if (rc == 0) { 8885 mtx_lock(&sc->tids.ftid_lock); 8886 for (;;) { 8887 if (f->pending == 0) { 8888 rc = f->valid ? 0 : EIO; 8889 break; 8890 } 8891 8892 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8893 PCATCH, "t4setfw", 0)) { 8894 rc = EINPROGRESS; 8895 break; 8896 } 8897 } 8898 mtx_unlock(&sc->tids.ftid_lock); 8899 } 8900 return (rc); 8901 } 8902 8903 static int 8904 del_filter(struct adapter *sc, struct t4_filter *t) 8905 { 8906 unsigned int nfilters; 8907 struct filter_entry *f; 8908 int rc; 8909 8910 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf"); 8911 if (rc) 8912 return (rc); 8913 8914 nfilters = sc->tids.nftids; 8915 8916 if (nfilters == 0) { 8917 rc = ENOTSUP; 8918 goto done; 8919 } 8920 8921 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 || 8922 t->idx >= nfilters) { 8923 rc = EINVAL; 8924 goto done; 8925 } 8926 8927 if (!(sc->flags & FULL_INIT_DONE)) { 8928 rc = EAGAIN; 8929 goto done; 8930 } 8931 8932 f = &sc->tids.ftid_tab[t->idx]; 8933 8934 if (f->pending) { 8935 rc = EBUSY; 8936 goto done; 8937 } 8938 if (f->locked) { 8939 rc = EPERM; 8940 goto done; 8941 } 8942 8943 if (f->valid) { 8944 t->fs = f->fs; /* extra info for the caller */ 8945 rc = del_filter_wr(sc, t->idx); 8946 } 8947 8948 done: 8949 end_synchronized_op(sc, 0); 8950 8951 if (rc == 0) { 8952 mtx_lock(&sc->tids.ftid_lock); 8953 for (;;) { 8954 if (f->pending == 0) { 8955 rc = f->valid ? EIO : 0; 8956 break; 8957 } 8958 8959 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8960 PCATCH, "t4delfw", 0)) { 8961 rc = EINPROGRESS; 8962 break; 8963 } 8964 } 8965 mtx_unlock(&sc->tids.ftid_lock); 8966 } 8967 8968 return (rc); 8969 } 8970 8971 static void 8972 clear_filter(struct filter_entry *f) 8973 { 8974 if (f->l2t) 8975 t4_l2t_release(f->l2t); 8976 8977 bzero(f, sizeof (*f)); 8978 } 8979 8980 static int 8981 set_filter_wr(struct adapter *sc, int fidx) 8982 { 8983 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8984 struct fw_filter_wr *fwr; 8985 unsigned int ftid, vnic_vld, vnic_vld_mask; 8986 struct wrq_cookie cookie; 8987 8988 ASSERT_SYNCHRONIZED_OP(sc); 8989 8990 if (f->fs.newdmac || f->fs.newvlan) { 8991 /* This filter needs an L2T entry; allocate one. */ 8992 f->l2t = t4_l2t_alloc_switching(sc->l2t); 8993 if (f->l2t == NULL) 8994 return (EAGAIN); 8995 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport, 8996 f->fs.dmac)) { 8997 t4_l2t_release(f->l2t); 8998 f->l2t = NULL; 8999 return (ENOMEM); 9000 } 9001 } 9002 9003 /* Already validated against fconf, iconf */ 9004 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0); 9005 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0); 9006 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld) 9007 vnic_vld = 1; 9008 else 9009 vnic_vld = 0; 9010 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld) 9011 vnic_vld_mask = 1; 9012 else 9013 vnic_vld_mask = 0; 9014 9015 ftid = sc->tids.ftid_base + fidx; 9016 9017 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 9018 if (fwr == NULL) 9019 return (ENOMEM); 9020 bzero(fwr, sizeof(*fwr)); 9021 9022 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR)); 9023 fwr->len16_pkd = htobe32(FW_LEN16(*fwr)); 9024 fwr->tid_to_iq = 9025 htobe32(V_FW_FILTER_WR_TID(ftid) | 9026 V_FW_FILTER_WR_RQTYPE(f->fs.type) | 9027 V_FW_FILTER_WR_NOREPLY(0) | 9028 V_FW_FILTER_WR_IQ(f->fs.iq)); 9029 fwr->del_filter_to_l2tix = 9030 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) | 9031 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) | 9032 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) | 9033 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) | 9034 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) | 9035 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) | 9036 V_FW_FILTER_WR_DMAC(f->fs.newdmac) | 9037 V_FW_FILTER_WR_SMAC(f->fs.newsmac) | 9038 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT || 9039 f->fs.newvlan == VLAN_REWRITE) | 9040 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE || 9041 f->fs.newvlan == VLAN_REWRITE) | 9042 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) | 9043 V_FW_FILTER_WR_TXCHAN(f->fs.eport) | 9044 V_FW_FILTER_WR_PRIO(f->fs.prio) | 9045 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0)); 9046 fwr->ethtype = htobe16(f->fs.val.ethtype); 9047 fwr->ethtypem = htobe16(f->fs.mask.ethtype); 9048 fwr->frag_to_ovlan_vldm = 9049 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) | 9050 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) | 9051 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) | 9052 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) | 9053 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) | 9054 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask)); 9055 fwr->smac_sel = 0; 9056 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) | 9057 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id)); 9058 fwr->maci_to_matchtypem = 9059 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) | 9060 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) | 9061 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) | 9062 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) | 9063 V_FW_FILTER_WR_PORT(f->fs.val.iport) | 9064 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) | 9065 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) | 9066 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype)); 9067 fwr->ptcl = f->fs.val.proto; 9068 fwr->ptclm = f->fs.mask.proto; 9069 fwr->ttyp = f->fs.val.tos; 9070 fwr->ttypm = f->fs.mask.tos; 9071 fwr->ivlan = htobe16(f->fs.val.vlan); 9072 fwr->ivlanm = htobe16(f->fs.mask.vlan); 9073 fwr->ovlan = htobe16(f->fs.val.vnic); 9074 fwr->ovlanm = htobe16(f->fs.mask.vnic); 9075 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip)); 9076 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm)); 9077 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip)); 9078 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm)); 9079 fwr->lp = htobe16(f->fs.val.dport); 9080 fwr->lpm = htobe16(f->fs.mask.dport); 9081 fwr->fp = htobe16(f->fs.val.sport); 9082 fwr->fpm = htobe16(f->fs.mask.sport); 9083 if (f->fs.newsmac) 9084 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma)); 9085 9086 f->pending = 1; 9087 sc->tids.ftids_in_use++; 9088 9089 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 9090 return (0); 9091 } 9092 9093 static int 9094 del_filter_wr(struct adapter *sc, int fidx) 9095 { 9096 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 9097 struct fw_filter_wr *fwr; 9098 unsigned int ftid; 9099 struct wrq_cookie cookie; 9100 9101 ftid = sc->tids.ftid_base + fidx; 9102 9103 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 9104 if (fwr == NULL) 9105 return (ENOMEM); 9106 bzero(fwr, sizeof (*fwr)); 9107 9108 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id); 9109 9110 f->pending = 1; 9111 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 9112 return (0); 9113 } 9114 9115 int 9116 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 9117 { 9118 struct adapter *sc = iq->adapter; 9119 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1); 9120 unsigned int idx = GET_TID(rpl); 9121 unsigned int rc; 9122 struct filter_entry *f; 9123 9124 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 9125 rss->opcode)); 9126 MPASS(iq == &sc->sge.fwq); 9127 MPASS(is_ftid(sc, idx)); 9128 9129 idx -= sc->tids.ftid_base; 9130 f = &sc->tids.ftid_tab[idx]; 9131 rc = G_COOKIE(rpl->cookie); 9132 9133 mtx_lock(&sc->tids.ftid_lock); 9134 if (rc == FW_FILTER_WR_FLT_ADDED) { 9135 KASSERT(f->pending, ("%s: filter[%u] isn't pending.", 9136 __func__, idx)); 9137 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; 9138 f->pending = 0; /* asynchronous setup completed */ 9139 f->valid = 1; 9140 } else { 9141 if (rc != FW_FILTER_WR_FLT_DELETED) { 9142 /* Add or delete failed, display an error */ 9143 log(LOG_ERR, 9144 "filter %u setup failed with error %u\n", 9145 idx, rc); 9146 } 9147 9148 clear_filter(f); 9149 sc->tids.ftids_in_use--; 9150 } 9151 wakeup(&sc->tids.ftid_tab); 9152 mtx_unlock(&sc->tids.ftid_lock); 9153 9154 return (0); 9155 } 9156 9157 static int 9158 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 9159 { 9160 9161 MPASS(iq->set_tcb_rpl != NULL); 9162 return (iq->set_tcb_rpl(iq, rss, m)); 9163 } 9164 9165 static int 9166 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 9167 { 9168 9169 MPASS(iq->l2t_write_rpl != NULL); 9170 return (iq->l2t_write_rpl(iq, rss, m)); 9171 } 9172 9173 static int 9174 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 9175 { 9176 int rc; 9177 9178 if (cntxt->cid > M_CTXTQID) 9179 return (EINVAL); 9180 9181 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 9182 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 9183 return (EINVAL); 9184 9185 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 9186 if (rc) 9187 return (rc); 9188 9189 if (sc->flags & FW_OK) { 9190 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 9191 &cntxt->data[0]); 9192 if (rc == 0) 9193 goto done; 9194 } 9195 9196 /* 9197 * Read via firmware failed or wasn't even attempted. Read directly via 9198 * the backdoor. 9199 */ 9200 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 9201 done: 9202 end_synchronized_op(sc, 0); 9203 return (rc); 9204 } 9205 9206 static int 9207 load_fw(struct adapter *sc, struct t4_data *fw) 9208 { 9209 int rc; 9210 uint8_t *fw_data; 9211 9212 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 9213 if (rc) 9214 return (rc); 9215 9216 /* 9217 * The firmware, with the sole exception of the memory parity error 9218 * handler, runs from memory and not flash. It is almost always safe to 9219 * install a new firmware on a running system. Just set bit 1 in 9220 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 9221 */ 9222 if (sc->flags & FULL_INIT_DONE && 9223 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 9224 rc = EBUSY; 9225 goto done; 9226 } 9227 9228 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9229 if (fw_data == NULL) { 9230 rc = ENOMEM; 9231 goto done; 9232 } 9233 9234 rc = copyin(fw->data, fw_data, fw->len); 9235 if (rc == 0) 9236 rc = -t4_load_fw(sc, fw_data, fw->len); 9237 9238 free(fw_data, M_CXGBE); 9239 done: 9240 end_synchronized_op(sc, 0); 9241 return (rc); 9242 } 9243 9244 static int 9245 load_cfg(struct adapter *sc, struct t4_data *cfg) 9246 { 9247 int rc; 9248 uint8_t *cfg_data = NULL; 9249 9250 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9251 if (rc) 9252 return (rc); 9253 9254 if (cfg->len == 0) { 9255 /* clear */ 9256 rc = -t4_load_cfg(sc, NULL, 0); 9257 goto done; 9258 } 9259 9260 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9261 if (cfg_data == NULL) { 9262 rc = ENOMEM; 9263 goto done; 9264 } 9265 9266 rc = copyin(cfg->data, cfg_data, cfg->len); 9267 if (rc == 0) 9268 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9269 9270 free(cfg_data, M_CXGBE); 9271 done: 9272 end_synchronized_op(sc, 0); 9273 return (rc); 9274 } 9275 9276 static int 9277 load_boot(struct adapter *sc, struct t4_bootrom *br) 9278 { 9279 int rc; 9280 uint8_t *br_data = NULL; 9281 u_int offset; 9282 9283 if (br->len > 1024 * 1024) 9284 return (EFBIG); 9285 9286 if (br->pf_offset == 0) { 9287 /* pfidx */ 9288 if (br->pfidx_addr > 7) 9289 return (EINVAL); 9290 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9291 A_PCIE_PF_EXPROM_OFST))); 9292 } else if (br->pf_offset == 1) { 9293 /* offset */ 9294 offset = G_OFFSET(br->pfidx_addr); 9295 } else { 9296 return (EINVAL); 9297 } 9298 9299 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9300 if (rc) 9301 return (rc); 9302 9303 if (br->len == 0) { 9304 /* clear */ 9305 rc = -t4_load_boot(sc, NULL, offset, 0); 9306 goto done; 9307 } 9308 9309 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9310 if (br_data == NULL) { 9311 rc = ENOMEM; 9312 goto done; 9313 } 9314 9315 rc = copyin(br->data, br_data, br->len); 9316 if (rc == 0) 9317 rc = -t4_load_boot(sc, br_data, offset, br->len); 9318 9319 free(br_data, M_CXGBE); 9320 done: 9321 end_synchronized_op(sc, 0); 9322 return (rc); 9323 } 9324 9325 static int 9326 load_bootcfg(struct adapter *sc, struct t4_data *bc) 9327 { 9328 int rc; 9329 uint8_t *bc_data = NULL; 9330 9331 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9332 if (rc) 9333 return (rc); 9334 9335 if (bc->len == 0) { 9336 /* clear */ 9337 rc = -t4_load_bootcfg(sc, NULL, 0); 9338 goto done; 9339 } 9340 9341 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9342 if (bc_data == NULL) { 9343 rc = ENOMEM; 9344 goto done; 9345 } 9346 9347 rc = copyin(bc->data, bc_data, bc->len); 9348 if (rc == 0) 9349 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9350 9351 free(bc_data, M_CXGBE); 9352 done: 9353 end_synchronized_op(sc, 0); 9354 return (rc); 9355 } 9356 9357 static int 9358 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9359 { 9360 int rc; 9361 struct cudbg_init *cudbg; 9362 void *handle, *buf; 9363 9364 /* buf is large, don't block if no memory is available */ 9365 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9366 if (buf == NULL) 9367 return (ENOMEM); 9368 9369 handle = cudbg_alloc_handle(); 9370 if (handle == NULL) { 9371 rc = ENOMEM; 9372 goto done; 9373 } 9374 9375 cudbg = cudbg_get_init(handle); 9376 cudbg->adap = sc; 9377 cudbg->print = (cudbg_print_cb)printf; 9378 9379 #ifndef notyet 9380 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9381 __func__, dump->wr_flash, dump->len, dump->data); 9382 #endif 9383 9384 if (dump->wr_flash) 9385 cudbg->use_flash = 1; 9386 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9387 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9388 9389 rc = cudbg_collect(handle, buf, &dump->len); 9390 if (rc != 0) 9391 goto done; 9392 9393 rc = copyout(buf, dump->data, dump->len); 9394 done: 9395 cudbg_free_handle(handle); 9396 free(buf, M_CXGBE); 9397 return (rc); 9398 } 9399 9400 #define MAX_READ_BUF_SIZE (128 * 1024) 9401 static int 9402 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9403 { 9404 uint32_t addr, remaining, n; 9405 uint32_t *buf; 9406 int rc; 9407 uint8_t *dst; 9408 9409 rc = validate_mem_range(sc, mr->addr, mr->len); 9410 if (rc != 0) 9411 return (rc); 9412 9413 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9414 addr = mr->addr; 9415 remaining = mr->len; 9416 dst = (void *)mr->data; 9417 9418 while (remaining) { 9419 n = min(remaining, MAX_READ_BUF_SIZE); 9420 read_via_memwin(sc, 2, addr, buf, n); 9421 9422 rc = copyout(buf, dst, n); 9423 if (rc != 0) 9424 break; 9425 9426 dst += n; 9427 remaining -= n; 9428 addr += n; 9429 } 9430 9431 free(buf, M_CXGBE); 9432 return (rc); 9433 } 9434 #undef MAX_READ_BUF_SIZE 9435 9436 static int 9437 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9438 { 9439 int rc; 9440 9441 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9442 return (EINVAL); 9443 9444 if (i2cd->len > sizeof(i2cd->data)) 9445 return (EFBIG); 9446 9447 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9448 if (rc) 9449 return (rc); 9450 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9451 i2cd->offset, i2cd->len, &i2cd->data[0]); 9452 end_synchronized_op(sc, 0); 9453 9454 return (rc); 9455 } 9456 9457 int 9458 t4_os_find_pci_capability(struct adapter *sc, int cap) 9459 { 9460 int i; 9461 9462 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9463 } 9464 9465 int 9466 t4_os_pci_save_state(struct adapter *sc) 9467 { 9468 device_t dev; 9469 struct pci_devinfo *dinfo; 9470 9471 dev = sc->dev; 9472 dinfo = device_get_ivars(dev); 9473 9474 pci_cfg_save(dev, dinfo, 0); 9475 return (0); 9476 } 9477 9478 int 9479 t4_os_pci_restore_state(struct adapter *sc) 9480 { 9481 device_t dev; 9482 struct pci_devinfo *dinfo; 9483 9484 dev = sc->dev; 9485 dinfo = device_get_ivars(dev); 9486 9487 pci_cfg_restore(dev, dinfo); 9488 return (0); 9489 } 9490 9491 void 9492 t4_os_portmod_changed(struct port_info *pi) 9493 { 9494 struct adapter *sc = pi->adapter; 9495 struct vi_info *vi; 9496 struct ifnet *ifp; 9497 static const char *mod_str[] = { 9498 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9499 }; 9500 9501 PORT_LOCK(pi); 9502 build_medialist(pi, &pi->media); 9503 PORT_UNLOCK(pi); 9504 vi = &pi->vi[0]; 9505 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9506 init_l1cfg(pi); 9507 end_synchronized_op(sc, LOCK_HELD); 9508 } 9509 9510 ifp = vi->ifp; 9511 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9512 if_printf(ifp, "transceiver unplugged.\n"); 9513 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9514 if_printf(ifp, "unknown transceiver inserted.\n"); 9515 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9516 if_printf(ifp, "unsupported transceiver inserted.\n"); 9517 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9518 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9519 port_top_speed(pi), mod_str[pi->mod_type]); 9520 } else { 9521 if_printf(ifp, "transceiver (type %d) inserted.\n", 9522 pi->mod_type); 9523 } 9524 } 9525 9526 void 9527 t4_os_link_changed(struct port_info *pi) 9528 { 9529 struct vi_info *vi; 9530 struct ifnet *ifp; 9531 struct link_config *lc; 9532 int v; 9533 9534 for_each_vi(pi, v, vi) { 9535 ifp = vi->ifp; 9536 if (ifp == NULL) 9537 continue; 9538 9539 lc = &pi->link_cfg; 9540 if (lc->link_ok) { 9541 ifp->if_baudrate = IF_Mbps(lc->speed); 9542 if_link_state_change(ifp, LINK_STATE_UP); 9543 } else { 9544 if_link_state_change(ifp, LINK_STATE_DOWN); 9545 } 9546 } 9547 } 9548 9549 void 9550 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9551 { 9552 struct adapter *sc; 9553 9554 sx_slock(&t4_list_lock); 9555 SLIST_FOREACH(sc, &t4_list, link) { 9556 /* 9557 * func should not make any assumptions about what state sc is 9558 * in - the only guarantee is that sc->sc_lock is a valid lock. 9559 */ 9560 func(sc, arg); 9561 } 9562 sx_sunlock(&t4_list_lock); 9563 } 9564 9565 static int 9566 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9567 struct thread *td) 9568 { 9569 int rc; 9570 struct adapter *sc = dev->si_drv1; 9571 9572 rc = priv_check(td, PRIV_DRIVER); 9573 if (rc != 0) 9574 return (rc); 9575 9576 switch (cmd) { 9577 case CHELSIO_T4_GETREG: { 9578 struct t4_reg *edata = (struct t4_reg *)data; 9579 9580 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9581 return (EFAULT); 9582 9583 if (edata->size == 4) 9584 edata->val = t4_read_reg(sc, edata->addr); 9585 else if (edata->size == 8) 9586 edata->val = t4_read_reg64(sc, edata->addr); 9587 else 9588 return (EINVAL); 9589 9590 break; 9591 } 9592 case CHELSIO_T4_SETREG: { 9593 struct t4_reg *edata = (struct t4_reg *)data; 9594 9595 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9596 return (EFAULT); 9597 9598 if (edata->size == 4) { 9599 if (edata->val & 0xffffffff00000000) 9600 return (EINVAL); 9601 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9602 } else if (edata->size == 8) 9603 t4_write_reg64(sc, edata->addr, edata->val); 9604 else 9605 return (EINVAL); 9606 break; 9607 } 9608 case CHELSIO_T4_REGDUMP: { 9609 struct t4_regdump *regs = (struct t4_regdump *)data; 9610 int reglen = t4_get_regs_len(sc); 9611 uint8_t *buf; 9612 9613 if (regs->len < reglen) { 9614 regs->len = reglen; /* hint to the caller */ 9615 return (ENOBUFS); 9616 } 9617 9618 regs->len = reglen; 9619 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9620 get_regs(sc, regs, buf); 9621 rc = copyout(buf, regs->data, reglen); 9622 free(buf, M_CXGBE); 9623 break; 9624 } 9625 case CHELSIO_T4_GET_FILTER_MODE: 9626 rc = get_filter_mode(sc, (uint32_t *)data); 9627 break; 9628 case CHELSIO_T4_SET_FILTER_MODE: 9629 rc = set_filter_mode(sc, *(uint32_t *)data); 9630 break; 9631 case CHELSIO_T4_GET_FILTER: 9632 rc = get_filter(sc, (struct t4_filter *)data); 9633 break; 9634 case CHELSIO_T4_SET_FILTER: 9635 rc = set_filter(sc, (struct t4_filter *)data); 9636 break; 9637 case CHELSIO_T4_DEL_FILTER: 9638 rc = del_filter(sc, (struct t4_filter *)data); 9639 break; 9640 case CHELSIO_T4_GET_SGE_CONTEXT: 9641 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9642 break; 9643 case CHELSIO_T4_LOAD_FW: 9644 rc = load_fw(sc, (struct t4_data *)data); 9645 break; 9646 case CHELSIO_T4_GET_MEM: 9647 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9648 break; 9649 case CHELSIO_T4_GET_I2C: 9650 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9651 break; 9652 case CHELSIO_T4_CLEAR_STATS: { 9653 int i, v; 9654 u_int port_id = *(uint32_t *)data; 9655 struct port_info *pi; 9656 struct vi_info *vi; 9657 9658 if (port_id >= sc->params.nports) 9659 return (EINVAL); 9660 pi = sc->port[port_id]; 9661 if (pi == NULL) 9662 return (EIO); 9663 9664 /* MAC stats */ 9665 t4_clr_port_stats(sc, pi->tx_chan); 9666 pi->tx_parse_error = 0; 9667 mtx_lock(&sc->reg_lock); 9668 for_each_vi(pi, v, vi) { 9669 if (vi->flags & VI_INIT_DONE) 9670 t4_clr_vi_stats(sc, vi->viid); 9671 } 9672 mtx_unlock(&sc->reg_lock); 9673 9674 /* 9675 * Since this command accepts a port, clear stats for 9676 * all VIs on this port. 9677 */ 9678 for_each_vi(pi, v, vi) { 9679 if (vi->flags & VI_INIT_DONE) { 9680 struct sge_rxq *rxq; 9681 struct sge_txq *txq; 9682 struct sge_wrq *wrq; 9683 9684 for_each_rxq(vi, i, rxq) { 9685 #if defined(INET) || defined(INET6) 9686 rxq->lro.lro_queued = 0; 9687 rxq->lro.lro_flushed = 0; 9688 #endif 9689 rxq->rxcsum = 0; 9690 rxq->vlan_extraction = 0; 9691 } 9692 9693 for_each_txq(vi, i, txq) { 9694 txq->txcsum = 0; 9695 txq->tso_wrs = 0; 9696 txq->vlan_insertion = 0; 9697 txq->imm_wrs = 0; 9698 txq->sgl_wrs = 0; 9699 txq->txpkt_wrs = 0; 9700 txq->txpkts0_wrs = 0; 9701 txq->txpkts1_wrs = 0; 9702 txq->txpkts0_pkts = 0; 9703 txq->txpkts1_pkts = 0; 9704 mp_ring_reset_stats(txq->r); 9705 } 9706 9707 #ifdef TCP_OFFLOAD 9708 /* nothing to clear for each ofld_rxq */ 9709 9710 for_each_ofld_txq(vi, i, wrq) { 9711 wrq->tx_wrs_direct = 0; 9712 wrq->tx_wrs_copied = 0; 9713 } 9714 #endif 9715 9716 if (IS_MAIN_VI(vi)) { 9717 wrq = &sc->sge.ctrlq[pi->port_id]; 9718 wrq->tx_wrs_direct = 0; 9719 wrq->tx_wrs_copied = 0; 9720 } 9721 } 9722 } 9723 break; 9724 } 9725 case CHELSIO_T4_SCHED_CLASS: 9726 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9727 break; 9728 case CHELSIO_T4_SCHED_QUEUE: 9729 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9730 break; 9731 case CHELSIO_T4_GET_TRACER: 9732 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9733 break; 9734 case CHELSIO_T4_SET_TRACER: 9735 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9736 break; 9737 case CHELSIO_T4_LOAD_CFG: 9738 rc = load_cfg(sc, (struct t4_data *)data); 9739 break; 9740 case CHELSIO_T4_LOAD_BOOT: 9741 rc = load_boot(sc, (struct t4_bootrom *)data); 9742 break; 9743 case CHELSIO_T4_LOAD_BOOTCFG: 9744 rc = load_bootcfg(sc, (struct t4_data *)data); 9745 break; 9746 case CHELSIO_T4_CUDBG_DUMP: 9747 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 9748 break; 9749 default: 9750 rc = ENOTTY; 9751 } 9752 9753 return (rc); 9754 } 9755 9756 void 9757 t4_db_full(struct adapter *sc) 9758 { 9759 9760 CXGBE_UNIMPLEMENTED(__func__); 9761 } 9762 9763 void 9764 t4_db_dropped(struct adapter *sc) 9765 { 9766 9767 CXGBE_UNIMPLEMENTED(__func__); 9768 } 9769 9770 #ifdef TCP_OFFLOAD 9771 static int 9772 toe_capability(struct vi_info *vi, int enable) 9773 { 9774 int rc; 9775 struct port_info *pi = vi->pi; 9776 struct adapter *sc = pi->adapter; 9777 9778 ASSERT_SYNCHRONIZED_OP(sc); 9779 9780 if (!is_offload(sc)) 9781 return (ENODEV); 9782 9783 if (enable) { 9784 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9785 /* TOE is already enabled. */ 9786 return (0); 9787 } 9788 9789 /* 9790 * We need the port's queues around so that we're able to send 9791 * and receive CPLs to/from the TOE even if the ifnet for this 9792 * port has never been UP'd administratively. 9793 */ 9794 if (!(vi->flags & VI_INIT_DONE)) { 9795 rc = vi_full_init(vi); 9796 if (rc) 9797 return (rc); 9798 } 9799 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9800 rc = vi_full_init(&pi->vi[0]); 9801 if (rc) 9802 return (rc); 9803 } 9804 9805 if (isset(&sc->offload_map, pi->port_id)) { 9806 /* TOE is enabled on another VI of this port. */ 9807 pi->uld_vis++; 9808 return (0); 9809 } 9810 9811 if (!uld_active(sc, ULD_TOM)) { 9812 rc = t4_activate_uld(sc, ULD_TOM); 9813 if (rc == EAGAIN) { 9814 log(LOG_WARNING, 9815 "You must kldload t4_tom.ko before trying " 9816 "to enable TOE on a cxgbe interface.\n"); 9817 } 9818 if (rc != 0) 9819 return (rc); 9820 KASSERT(sc->tom_softc != NULL, 9821 ("%s: TOM activated but softc NULL", __func__)); 9822 KASSERT(uld_active(sc, ULD_TOM), 9823 ("%s: TOM activated but flag not set", __func__)); 9824 } 9825 9826 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9827 if (!uld_active(sc, ULD_IWARP)) 9828 (void) t4_activate_uld(sc, ULD_IWARP); 9829 if (!uld_active(sc, ULD_ISCSI)) 9830 (void) t4_activate_uld(sc, ULD_ISCSI); 9831 9832 pi->uld_vis++; 9833 setbit(&sc->offload_map, pi->port_id); 9834 } else { 9835 pi->uld_vis--; 9836 9837 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9838 return (0); 9839 9840 KASSERT(uld_active(sc, ULD_TOM), 9841 ("%s: TOM never initialized?", __func__)); 9842 clrbit(&sc->offload_map, pi->port_id); 9843 } 9844 9845 return (0); 9846 } 9847 9848 /* 9849 * Add an upper layer driver to the global list. 9850 */ 9851 int 9852 t4_register_uld(struct uld_info *ui) 9853 { 9854 int rc = 0; 9855 struct uld_info *u; 9856 9857 sx_xlock(&t4_uld_list_lock); 9858 SLIST_FOREACH(u, &t4_uld_list, link) { 9859 if (u->uld_id == ui->uld_id) { 9860 rc = EEXIST; 9861 goto done; 9862 } 9863 } 9864 9865 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9866 ui->refcount = 0; 9867 done: 9868 sx_xunlock(&t4_uld_list_lock); 9869 return (rc); 9870 } 9871 9872 int 9873 t4_unregister_uld(struct uld_info *ui) 9874 { 9875 int rc = EINVAL; 9876 struct uld_info *u; 9877 9878 sx_xlock(&t4_uld_list_lock); 9879 9880 SLIST_FOREACH(u, &t4_uld_list, link) { 9881 if (u == ui) { 9882 if (ui->refcount > 0) { 9883 rc = EBUSY; 9884 goto done; 9885 } 9886 9887 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 9888 rc = 0; 9889 goto done; 9890 } 9891 } 9892 done: 9893 sx_xunlock(&t4_uld_list_lock); 9894 return (rc); 9895 } 9896 9897 int 9898 t4_activate_uld(struct adapter *sc, int id) 9899 { 9900 int rc; 9901 struct uld_info *ui; 9902 9903 ASSERT_SYNCHRONIZED_OP(sc); 9904 9905 if (id < 0 || id > ULD_MAX) 9906 return (EINVAL); 9907 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 9908 9909 sx_slock(&t4_uld_list_lock); 9910 9911 SLIST_FOREACH(ui, &t4_uld_list, link) { 9912 if (ui->uld_id == id) { 9913 if (!(sc->flags & FULL_INIT_DONE)) { 9914 rc = adapter_full_init(sc); 9915 if (rc != 0) 9916 break; 9917 } 9918 9919 rc = ui->activate(sc); 9920 if (rc == 0) { 9921 setbit(&sc->active_ulds, id); 9922 ui->refcount++; 9923 } 9924 break; 9925 } 9926 } 9927 9928 sx_sunlock(&t4_uld_list_lock); 9929 9930 return (rc); 9931 } 9932 9933 int 9934 t4_deactivate_uld(struct adapter *sc, int id) 9935 { 9936 int rc; 9937 struct uld_info *ui; 9938 9939 ASSERT_SYNCHRONIZED_OP(sc); 9940 9941 if (id < 0 || id > ULD_MAX) 9942 return (EINVAL); 9943 rc = ENXIO; 9944 9945 sx_slock(&t4_uld_list_lock); 9946 9947 SLIST_FOREACH(ui, &t4_uld_list, link) { 9948 if (ui->uld_id == id) { 9949 rc = ui->deactivate(sc); 9950 if (rc == 0) { 9951 clrbit(&sc->active_ulds, id); 9952 ui->refcount--; 9953 } 9954 break; 9955 } 9956 } 9957 9958 sx_sunlock(&t4_uld_list_lock); 9959 9960 return (rc); 9961 } 9962 9963 int 9964 uld_active(struct adapter *sc, int uld_id) 9965 { 9966 9967 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 9968 9969 return (isset(&sc->active_ulds, uld_id)); 9970 } 9971 #endif 9972 9973 /* 9974 * t = ptr to tunable. 9975 * nc = number of CPUs. 9976 * c = compiled in default for that tunable. 9977 */ 9978 static void 9979 calculate_nqueues(int *t, int nc, const int c) 9980 { 9981 int nq; 9982 9983 if (*t > 0) 9984 return; 9985 nq = *t < 0 ? -*t : c; 9986 *t = min(nc, nq); 9987 } 9988 9989 /* 9990 * Come up with reasonable defaults for some of the tunables, provided they're 9991 * not set by the user (in which case we'll use the values as is). 9992 */ 9993 static void 9994 tweak_tunables(void) 9995 { 9996 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 9997 9998 if (t4_ntxq < 1) { 9999 #ifdef RSS 10000 t4_ntxq = rss_getnumbuckets(); 10001 #else 10002 calculate_nqueues(&t4_ntxq, nc, NTXQ); 10003 #endif 10004 } 10005 10006 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 10007 10008 if (t4_nrxq < 1) { 10009 #ifdef RSS 10010 t4_nrxq = rss_getnumbuckets(); 10011 #else 10012 calculate_nqueues(&t4_nrxq, nc, NRXQ); 10013 #endif 10014 } 10015 10016 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 10017 10018 #ifdef TCP_OFFLOAD 10019 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 10020 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 10021 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 10022 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 10023 10024 if (t4_toecaps_allowed == -1) 10025 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 10026 10027 if (t4_rdmacaps_allowed == -1) { 10028 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 10029 FW_CAPS_CONFIG_RDMA_RDMAC; 10030 } 10031 10032 if (t4_iscsicaps_allowed == -1) { 10033 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 10034 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 10035 FW_CAPS_CONFIG_ISCSI_T10DIF; 10036 } 10037 10038 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 10039 t4_tmr_idx_ofld = TMR_IDX_OFLD; 10040 10041 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 10042 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 10043 #else 10044 if (t4_toecaps_allowed == -1) 10045 t4_toecaps_allowed = 0; 10046 10047 if (t4_rdmacaps_allowed == -1) 10048 t4_rdmacaps_allowed = 0; 10049 10050 if (t4_iscsicaps_allowed == -1) 10051 t4_iscsicaps_allowed = 0; 10052 #endif 10053 10054 #ifdef DEV_NETMAP 10055 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 10056 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 10057 #endif 10058 10059 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 10060 t4_tmr_idx = TMR_IDX; 10061 10062 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 10063 t4_pktc_idx = PKTC_IDX; 10064 10065 if (t4_qsize_txq < 128) 10066 t4_qsize_txq = 128; 10067 10068 if (t4_qsize_rxq < 128) 10069 t4_qsize_rxq = 128; 10070 while (t4_qsize_rxq & 7) 10071 t4_qsize_rxq++; 10072 10073 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 10074 10075 /* 10076 * Number of VIs to create per-port. The first VI is the "main" regular 10077 * VI for the port. The rest are additional virtual interfaces on the 10078 * same physical port. Note that the main VI does not have native 10079 * netmap support but the extra VIs do. 10080 * 10081 * Limit the number of VIs per port to the number of available 10082 * MAC addresses per port. 10083 */ 10084 if (t4_num_vis < 1) 10085 t4_num_vis = 1; 10086 if (t4_num_vis > nitems(vi_mac_funcs)) { 10087 t4_num_vis = nitems(vi_mac_funcs); 10088 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 10089 } 10090 10091 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 10092 pcie_relaxed_ordering = 1; 10093 #if defined(__i386__) || defined(__amd64__) 10094 if (cpu_vendor_id == CPU_VENDOR_INTEL) 10095 pcie_relaxed_ordering = 0; 10096 #endif 10097 } 10098 } 10099 10100 #ifdef DDB 10101 static void 10102 t4_dump_tcb(struct adapter *sc, int tid) 10103 { 10104 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 10105 10106 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 10107 save = t4_read_reg(sc, reg); 10108 base = sc->memwin[2].mw_base; 10109 10110 /* Dump TCB for the tid */ 10111 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 10112 tcb_addr += tid * TCB_SIZE; 10113 10114 if (is_t4(sc)) { 10115 pf = 0; 10116 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 10117 } else { 10118 pf = V_PFNUM(sc->pf); 10119 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 10120 } 10121 t4_write_reg(sc, reg, win_pos | pf); 10122 t4_read_reg(sc, reg); 10123 10124 off = tcb_addr - win_pos; 10125 for (i = 0; i < 4; i++) { 10126 uint32_t buf[8]; 10127 for (j = 0; j < 8; j++, off += 4) 10128 buf[j] = htonl(t4_read_reg(sc, base + off)); 10129 10130 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 10131 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 10132 buf[7]); 10133 } 10134 10135 t4_write_reg(sc, reg, save); 10136 t4_read_reg(sc, reg); 10137 } 10138 10139 static void 10140 t4_dump_devlog(struct adapter *sc) 10141 { 10142 struct devlog_params *dparams = &sc->params.devlog; 10143 struct fw_devlog_e e; 10144 int i, first, j, m, nentries, rc; 10145 uint64_t ftstamp = UINT64_MAX; 10146 10147 if (dparams->start == 0) { 10148 db_printf("devlog params not valid\n"); 10149 return; 10150 } 10151 10152 nentries = dparams->size / sizeof(struct fw_devlog_e); 10153 m = fwmtype_to_hwmtype(dparams->memtype); 10154 10155 /* Find the first entry. */ 10156 first = -1; 10157 for (i = 0; i < nentries && !db_pager_quit; i++) { 10158 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10159 sizeof(e), (void *)&e); 10160 if (rc != 0) 10161 break; 10162 10163 if (e.timestamp == 0) 10164 break; 10165 10166 e.timestamp = be64toh(e.timestamp); 10167 if (e.timestamp < ftstamp) { 10168 ftstamp = e.timestamp; 10169 first = i; 10170 } 10171 } 10172 10173 if (first == -1) 10174 return; 10175 10176 i = first; 10177 do { 10178 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10179 sizeof(e), (void *)&e); 10180 if (rc != 0) 10181 return; 10182 10183 if (e.timestamp == 0) 10184 return; 10185 10186 e.timestamp = be64toh(e.timestamp); 10187 e.seqno = be32toh(e.seqno); 10188 for (j = 0; j < 8; j++) 10189 e.params[j] = be32toh(e.params[j]); 10190 10191 db_printf("%10d %15ju %8s %8s ", 10192 e.seqno, e.timestamp, 10193 (e.level < nitems(devlog_level_strings) ? 10194 devlog_level_strings[e.level] : "UNKNOWN"), 10195 (e.facility < nitems(devlog_facility_strings) ? 10196 devlog_facility_strings[e.facility] : "UNKNOWN")); 10197 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10198 e.params[3], e.params[4], e.params[5], e.params[6], 10199 e.params[7]); 10200 10201 if (++i == nentries) 10202 i = 0; 10203 } while (i != first && !db_pager_quit); 10204 } 10205 10206 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10207 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10208 10209 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10210 { 10211 device_t dev; 10212 int t; 10213 bool valid; 10214 10215 valid = false; 10216 t = db_read_token(); 10217 if (t == tIDENT) { 10218 dev = device_lookup_by_name(db_tok_string); 10219 valid = true; 10220 } 10221 db_skip_to_eol(); 10222 if (!valid) { 10223 db_printf("usage: show t4 devlog <nexus>\n"); 10224 return; 10225 } 10226 10227 if (dev == NULL) { 10228 db_printf("device not found\n"); 10229 return; 10230 } 10231 10232 t4_dump_devlog(device_get_softc(dev)); 10233 } 10234 10235 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10236 { 10237 device_t dev; 10238 int radix, tid, t; 10239 bool valid; 10240 10241 valid = false; 10242 radix = db_radix; 10243 db_radix = 10; 10244 t = db_read_token(); 10245 if (t == tIDENT) { 10246 dev = device_lookup_by_name(db_tok_string); 10247 t = db_read_token(); 10248 if (t == tNUMBER) { 10249 tid = db_tok_number; 10250 valid = true; 10251 } 10252 } 10253 db_radix = radix; 10254 db_skip_to_eol(); 10255 if (!valid) { 10256 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10257 return; 10258 } 10259 10260 if (dev == NULL) { 10261 db_printf("device not found\n"); 10262 return; 10263 } 10264 if (tid < 0) { 10265 db_printf("invalid tid\n"); 10266 return; 10267 } 10268 10269 t4_dump_tcb(device_get_softc(dev), tid); 10270 } 10271 #endif 10272 10273 /* 10274 * Borrowed from cesa_prep_aes_key(). 10275 * 10276 * NB: The crypto engine wants the words in the decryption key in reverse 10277 * order. 10278 */ 10279 void 10280 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 10281 { 10282 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 10283 uint32_t *dkey; 10284 int i; 10285 10286 rijndaelKeySetupEnc(ek, enc_key, kbits); 10287 dkey = dec_key; 10288 dkey += (kbits / 8) / 4; 10289 10290 switch (kbits) { 10291 case 128: 10292 for (i = 0; i < 4; i++) 10293 *--dkey = htobe32(ek[4 * 10 + i]); 10294 break; 10295 case 192: 10296 for (i = 0; i < 2; i++) 10297 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10298 for (i = 0; i < 4; i++) 10299 *--dkey = htobe32(ek[4 * 12 + i]); 10300 break; 10301 case 256: 10302 for (i = 0; i < 4; i++) 10303 *--dkey = htobe32(ek[4 * 13 + i]); 10304 for (i = 0; i < 4; i++) 10305 *--dkey = htobe32(ek[4 * 14 + i]); 10306 break; 10307 } 10308 MPASS(dkey == dec_key); 10309 } 10310 10311 static struct sx mlu; /* mod load unload */ 10312 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10313 10314 static int 10315 mod_event(module_t mod, int cmd, void *arg) 10316 { 10317 int rc = 0; 10318 static int loaded = 0; 10319 10320 switch (cmd) { 10321 case MOD_LOAD: 10322 sx_xlock(&mlu); 10323 if (loaded++ == 0) { 10324 t4_sge_modload(); 10325 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl); 10326 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl); 10327 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10328 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10329 sx_init(&t4_list_lock, "T4/T5 adapters"); 10330 SLIST_INIT(&t4_list); 10331 #ifdef TCP_OFFLOAD 10332 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10333 SLIST_INIT(&t4_uld_list); 10334 #endif 10335 t4_tracer_modload(); 10336 tweak_tunables(); 10337 } 10338 sx_xunlock(&mlu); 10339 break; 10340 10341 case MOD_UNLOAD: 10342 sx_xlock(&mlu); 10343 if (--loaded == 0) { 10344 int tries; 10345 10346 sx_slock(&t4_list_lock); 10347 if (!SLIST_EMPTY(&t4_list)) { 10348 rc = EBUSY; 10349 sx_sunlock(&t4_list_lock); 10350 goto done_unload; 10351 } 10352 #ifdef TCP_OFFLOAD 10353 sx_slock(&t4_uld_list_lock); 10354 if (!SLIST_EMPTY(&t4_uld_list)) { 10355 rc = EBUSY; 10356 sx_sunlock(&t4_uld_list_lock); 10357 sx_sunlock(&t4_list_lock); 10358 goto done_unload; 10359 } 10360 #endif 10361 tries = 0; 10362 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10363 uprintf("%ju clusters with custom free routine " 10364 "still is use.\n", t4_sge_extfree_refs()); 10365 pause("t4unload", 2 * hz); 10366 } 10367 #ifdef TCP_OFFLOAD 10368 sx_sunlock(&t4_uld_list_lock); 10369 #endif 10370 sx_sunlock(&t4_list_lock); 10371 10372 if (t4_sge_extfree_refs() == 0) { 10373 t4_tracer_modunload(); 10374 #ifdef TCP_OFFLOAD 10375 sx_destroy(&t4_uld_list_lock); 10376 #endif 10377 sx_destroy(&t4_list_lock); 10378 t4_sge_modunload(); 10379 loaded = 0; 10380 } else { 10381 rc = EBUSY; 10382 loaded++; /* undo earlier decrement */ 10383 } 10384 } 10385 done_unload: 10386 sx_xunlock(&mlu); 10387 break; 10388 } 10389 10390 return (rc); 10391 } 10392 10393 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10394 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10395 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10396 10397 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10398 MODULE_VERSION(t4nex, 1); 10399 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10400 #ifdef DEV_NETMAP 10401 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10402 #endif /* DEV_NETMAP */ 10403 10404 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10405 MODULE_VERSION(t5nex, 1); 10406 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10407 #ifdef DEV_NETMAP 10408 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10409 #endif /* DEV_NETMAP */ 10410 10411 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10412 MODULE_VERSION(t6nex, 1); 10413 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10414 #ifdef DEV_NETMAP 10415 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10416 #endif /* DEV_NETMAP */ 10417 10418 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10419 MODULE_VERSION(cxgbe, 1); 10420 10421 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10422 MODULE_VERSION(cxl, 1); 10423 10424 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10425 MODULE_VERSION(cc, 1); 10426 10427 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10428 MODULE_VERSION(vcxgbe, 1); 10429 10430 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10431 MODULE_VERSION(vcxl, 1); 10432 10433 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10434 MODULE_VERSION(vcc, 1); 10435