1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "opt_ddb.h" 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_kern_tls.h" 35 #include "opt_ratelimit.h" 36 #include "opt_rss.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/priv.h> 41 #include <sys/kernel.h> 42 #include <sys/bus.h> 43 #include <sys/eventhandler.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #ifdef KERN_TLS 69 #include <netinet/tcp_seq.h> 70 #endif 71 #if defined(__i386__) || defined(__amd64__) 72 #include <machine/md_var.h> 73 #include <machine/cputypes.h> 74 #include <vm/vm.h> 75 #include <vm/pmap.h> 76 #endif 77 #ifdef DDB 78 #include <ddb/ddb.h> 79 #include <ddb/db_lex.h> 80 #endif 81 82 #include "common/common.h" 83 #include "common/t4_msg.h" 84 #include "common/t4_regs.h" 85 #include "common/t4_regs_values.h" 86 #include "cudbg/cudbg.h" 87 #include "t4_clip.h" 88 #include "t4_ioctl.h" 89 #include "t4_l2t.h" 90 #include "t4_mp_ring.h" 91 #include "t4_if.h" 92 #include "t4_smt.h" 93 94 /* T4 bus driver interface */ 95 static int t4_probe(device_t); 96 static int t4_attach(device_t); 97 static int t4_detach(device_t); 98 static int t4_child_location(device_t, device_t, struct sbuf *); 99 static int t4_ready(device_t); 100 static int t4_read_port_device(device_t, int, device_t *); 101 static int t4_suspend(device_t); 102 static int t4_resume(device_t); 103 static int t4_reset_prepare(device_t, device_t); 104 static int t4_reset_post(device_t, device_t); 105 static device_method_t t4_methods[] = { 106 DEVMETHOD(device_probe, t4_probe), 107 DEVMETHOD(device_attach, t4_attach), 108 DEVMETHOD(device_detach, t4_detach), 109 DEVMETHOD(device_suspend, t4_suspend), 110 DEVMETHOD(device_resume, t4_resume), 111 112 DEVMETHOD(bus_child_location, t4_child_location), 113 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 114 DEVMETHOD(bus_reset_post, t4_reset_post), 115 116 DEVMETHOD(t4_is_main_ready, t4_ready), 117 DEVMETHOD(t4_read_port_device, t4_read_port_device), 118 119 DEVMETHOD_END 120 }; 121 static driver_t t4_driver = { 122 "t4nex", 123 t4_methods, 124 sizeof(struct adapter) 125 }; 126 127 128 /* T4 port (cxgbe) interface */ 129 static int cxgbe_probe(device_t); 130 static int cxgbe_attach(device_t); 131 static int cxgbe_detach(device_t); 132 device_method_t cxgbe_methods[] = { 133 DEVMETHOD(device_probe, cxgbe_probe), 134 DEVMETHOD(device_attach, cxgbe_attach), 135 DEVMETHOD(device_detach, cxgbe_detach), 136 { 0, 0 } 137 }; 138 static driver_t cxgbe_driver = { 139 "cxgbe", 140 cxgbe_methods, 141 sizeof(struct port_info) 142 }; 143 144 /* T4 VI (vcxgbe) interface */ 145 static int vcxgbe_probe(device_t); 146 static int vcxgbe_attach(device_t); 147 static int vcxgbe_detach(device_t); 148 static device_method_t vcxgbe_methods[] = { 149 DEVMETHOD(device_probe, vcxgbe_probe), 150 DEVMETHOD(device_attach, vcxgbe_attach), 151 DEVMETHOD(device_detach, vcxgbe_detach), 152 { 0, 0 } 153 }; 154 static driver_t vcxgbe_driver = { 155 "vcxgbe", 156 vcxgbe_methods, 157 sizeof(struct vi_info) 158 }; 159 160 static d_ioctl_t t4_ioctl; 161 162 static struct cdevsw t4_cdevsw = { 163 .d_version = D_VERSION, 164 .d_ioctl = t4_ioctl, 165 .d_name = "t4nex", 166 }; 167 168 /* T5 bus driver interface */ 169 static int t5_probe(device_t); 170 static device_method_t t5_methods[] = { 171 DEVMETHOD(device_probe, t5_probe), 172 DEVMETHOD(device_attach, t4_attach), 173 DEVMETHOD(device_detach, t4_detach), 174 DEVMETHOD(device_suspend, t4_suspend), 175 DEVMETHOD(device_resume, t4_resume), 176 177 DEVMETHOD(bus_child_location, t4_child_location), 178 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 179 DEVMETHOD(bus_reset_post, t4_reset_post), 180 181 DEVMETHOD(t4_is_main_ready, t4_ready), 182 DEVMETHOD(t4_read_port_device, t4_read_port_device), 183 184 DEVMETHOD_END 185 }; 186 static driver_t t5_driver = { 187 "t5nex", 188 t5_methods, 189 sizeof(struct adapter) 190 }; 191 192 193 /* T5 port (cxl) interface */ 194 static driver_t cxl_driver = { 195 "cxl", 196 cxgbe_methods, 197 sizeof(struct port_info) 198 }; 199 200 /* T5 VI (vcxl) interface */ 201 static driver_t vcxl_driver = { 202 "vcxl", 203 vcxgbe_methods, 204 sizeof(struct vi_info) 205 }; 206 207 /* T6 bus driver interface */ 208 static int t6_probe(device_t); 209 static device_method_t t6_methods[] = { 210 DEVMETHOD(device_probe, t6_probe), 211 DEVMETHOD(device_attach, t4_attach), 212 DEVMETHOD(device_detach, t4_detach), 213 DEVMETHOD(device_suspend, t4_suspend), 214 DEVMETHOD(device_resume, t4_resume), 215 216 DEVMETHOD(bus_child_location, t4_child_location), 217 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 218 DEVMETHOD(bus_reset_post, t4_reset_post), 219 220 DEVMETHOD(t4_is_main_ready, t4_ready), 221 DEVMETHOD(t4_read_port_device, t4_read_port_device), 222 223 DEVMETHOD_END 224 }; 225 static driver_t t6_driver = { 226 "t6nex", 227 t6_methods, 228 sizeof(struct adapter) 229 }; 230 231 232 /* T6 port (cc) interface */ 233 static driver_t cc_driver = { 234 "cc", 235 cxgbe_methods, 236 sizeof(struct port_info) 237 }; 238 239 /* T6 VI (vcc) interface */ 240 static driver_t vcc_driver = { 241 "vcc", 242 vcxgbe_methods, 243 sizeof(struct vi_info) 244 }; 245 246 /* ifnet interface */ 247 static void cxgbe_init(void *); 248 static int cxgbe_ioctl(if_t, unsigned long, caddr_t); 249 static int cxgbe_transmit(if_t, struct mbuf *); 250 static void cxgbe_qflush(if_t); 251 #if defined(KERN_TLS) || defined(RATELIMIT) 252 static int cxgbe_snd_tag_alloc(if_t, union if_snd_tag_alloc_params *, 253 struct m_snd_tag **); 254 #endif 255 256 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 257 258 /* 259 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 260 * then ADAPTER_LOCK, then t4_uld_list_lock. 261 */ 262 static struct sx t4_list_lock; 263 SLIST_HEAD(, adapter) t4_list; 264 #ifdef TCP_OFFLOAD 265 static struct sx t4_uld_list_lock; 266 SLIST_HEAD(, uld_info) t4_uld_list; 267 #endif 268 269 /* 270 * Tunables. See tweak_tunables() too. 271 * 272 * Each tunable is set to a default value here if it's known at compile-time. 273 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 274 * provide a reasonable default (upto n) when the driver is loaded. 275 * 276 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 277 * T5 are under hw.cxl. 278 */ 279 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 280 "cxgbe(4) parameters"); 281 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 282 "cxgbe(4) T5+ parameters"); 283 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 284 "cxgbe(4) TOE parameters"); 285 286 /* 287 * Number of queues for tx and rx, NIC and offload. 288 */ 289 #define NTXQ 16 290 int t4_ntxq = -NTXQ; 291 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 292 "Number of TX queues per port"); 293 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 294 295 #define NRXQ 8 296 int t4_nrxq = -NRXQ; 297 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 298 "Number of RX queues per port"); 299 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 300 301 #define NTXQ_VI 1 302 static int t4_ntxq_vi = -NTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 304 "Number of TX queues per VI"); 305 306 #define NRXQ_VI 1 307 static int t4_nrxq_vi = -NRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 309 "Number of RX queues per VI"); 310 311 static int t4_rsrv_noflowq = 0; 312 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 313 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 314 315 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 316 #define NOFLDTXQ 8 317 static int t4_nofldtxq = -NOFLDTXQ; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 319 "Number of offload TX queues per port"); 320 321 #define NOFLDRXQ 2 322 static int t4_nofldrxq = -NOFLDRXQ; 323 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 324 "Number of offload RX queues per port"); 325 326 #define NOFLDTXQ_VI 1 327 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 328 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 329 "Number of offload TX queues per VI"); 330 331 #define NOFLDRXQ_VI 1 332 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 333 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 334 "Number of offload RX queues per VI"); 335 336 #define TMR_IDX_OFLD 1 337 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 338 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 339 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 340 341 #define PKTC_IDX_OFLD (-1) 342 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 343 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 344 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 345 346 /* 0 means chip/fw default, non-zero number is value in microseconds */ 347 static u_long t4_toe_keepalive_idle = 0; 348 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 349 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 350 351 /* 0 means chip/fw default, non-zero number is value in microseconds */ 352 static u_long t4_toe_keepalive_interval = 0; 353 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 354 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 355 356 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 357 static int t4_toe_keepalive_count = 0; 358 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 359 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 360 361 /* 0 means chip/fw default, non-zero number is value in microseconds */ 362 static u_long t4_toe_rexmt_min = 0; 363 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 365 366 /* 0 means chip/fw default, non-zero number is value in microseconds */ 367 static u_long t4_toe_rexmt_max = 0; 368 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 369 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 370 371 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 372 static int t4_toe_rexmt_count = 0; 373 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 375 376 /* -1 means chip/fw default, other values are raw backoff values to use */ 377 static int t4_toe_rexmt_backoff[16] = { 378 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 379 }; 380 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, 381 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 382 "cxgbe(4) TOE retransmit backoff values"); 383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[0], 0, ""); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[1], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[2], 0, ""); 389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 390 &t4_toe_rexmt_backoff[3], 0, ""); 391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 392 &t4_toe_rexmt_backoff[4], 0, ""); 393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 394 &t4_toe_rexmt_backoff[5], 0, ""); 395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 396 &t4_toe_rexmt_backoff[6], 0, ""); 397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 398 &t4_toe_rexmt_backoff[7], 0, ""); 399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 400 &t4_toe_rexmt_backoff[8], 0, ""); 401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 402 &t4_toe_rexmt_backoff[9], 0, ""); 403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 404 &t4_toe_rexmt_backoff[10], 0, ""); 405 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 406 &t4_toe_rexmt_backoff[11], 0, ""); 407 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 408 &t4_toe_rexmt_backoff[12], 0, ""); 409 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 410 &t4_toe_rexmt_backoff[13], 0, ""); 411 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 412 &t4_toe_rexmt_backoff[14], 0, ""); 413 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 414 &t4_toe_rexmt_backoff[15], 0, ""); 415 #endif 416 417 #ifdef DEV_NETMAP 418 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */ 419 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */ 420 static int t4_native_netmap = NN_EXTRA_VI; 421 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap, 422 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs"); 423 424 #define NNMTXQ 8 425 static int t4_nnmtxq = -NNMTXQ; 426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0, 427 "Number of netmap TX queues"); 428 429 #define NNMRXQ 8 430 static int t4_nnmrxq = -NNMRXQ; 431 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0, 432 "Number of netmap RX queues"); 433 434 #define NNMTXQ_VI 2 435 static int t4_nnmtxq_vi = -NNMTXQ_VI; 436 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 437 "Number of netmap TX queues per VI"); 438 439 #define NNMRXQ_VI 2 440 static int t4_nnmrxq_vi = -NNMRXQ_VI; 441 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 442 "Number of netmap RX queues per VI"); 443 #endif 444 445 /* 446 * Holdoff parameters for ports. 447 */ 448 #define TMR_IDX 1 449 int t4_tmr_idx = TMR_IDX; 450 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 451 0, "Holdoff timer index"); 452 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 453 454 #define PKTC_IDX (-1) 455 int t4_pktc_idx = PKTC_IDX; 456 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 457 0, "Holdoff packet counter index"); 458 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 459 460 /* 461 * Size (# of entries) of each tx and rx queue. 462 */ 463 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 464 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 465 "Number of descriptors in each TX queue"); 466 467 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 469 "Number of descriptors in each RX queue"); 470 471 /* 472 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 473 */ 474 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 475 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 476 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 477 478 /* 479 * Configuration file. All the _CF names here are special. 480 */ 481 #define DEFAULT_CF "default" 482 #define BUILTIN_CF "built-in" 483 #define FLASH_CF "flash" 484 #define UWIRE_CF "uwire" 485 #define FPGA_CF "fpga" 486 static char t4_cfg_file[32] = DEFAULT_CF; 487 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 488 sizeof(t4_cfg_file), "Firmware configuration file"); 489 490 /* 491 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 492 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 493 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 494 * mark or when signalled to do so, 0 to never emit PAUSE. 495 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 496 * negotiated settings will override rx_pause/tx_pause. 497 * Otherwise rx_pause/tx_pause are applied forcibly. 498 */ 499 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 500 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 501 &t4_pause_settings, 0, 502 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 503 504 /* 505 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 506 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 507 * 0 to disable FEC. 508 */ 509 static int t4_fec = -1; 510 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 511 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 512 513 /* 514 * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it 515 * issues to the firmware. If the firmware doesn't support FORCE_FEC then the 516 * driver runs as if this is set to 0. 517 * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay. 518 * 0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the 519 * transceiver. Multiple FEC bits may not be okay but will be passed on to 520 * the firmware anyway (may result in l1cfg errors with old firmwares). 521 * 1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO 522 * means set all FEC bits that are valid for the speed. 523 */ 524 static int t4_force_fec = -1; 525 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0, 526 "Controls the use of FORCE_FEC bit in L1 configuration."); 527 528 /* 529 * Link autonegotiation. 530 * -1 to run with the firmware default. 531 * 0 to disable. 532 * 1 to enable. 533 */ 534 static int t4_autoneg = -1; 535 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 536 "Link autonegotiation"); 537 538 /* 539 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 540 * encouraged respectively). '-n' is the same as 'n' except the firmware 541 * version used in the checks is read from the firmware bundled with the driver. 542 */ 543 static int t4_fw_install = 1; 544 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 545 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 546 547 /* 548 * ASIC features that will be used. Disable the ones you don't want so that the 549 * chip resources aren't wasted on features that will not be used. 550 */ 551 static int t4_nbmcaps_allowed = 0; 552 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 553 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 554 555 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 556 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 557 &t4_linkcaps_allowed, 0, "Default link capabilities"); 558 559 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 560 FW_CAPS_CONFIG_SWITCH_EGRESS; 561 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 562 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 563 564 #ifdef RATELIMIT 565 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 566 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 567 #else 568 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 569 FW_CAPS_CONFIG_NIC_HASHFILTER; 570 #endif 571 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 572 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 573 574 static int t4_toecaps_allowed = -1; 575 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 576 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 577 578 static int t4_rdmacaps_allowed = -1; 579 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 580 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 581 582 static int t4_cryptocaps_allowed = -1; 583 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 584 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 585 586 static int t4_iscsicaps_allowed = -1; 587 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 588 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 589 590 static int t4_fcoecaps_allowed = 0; 591 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 592 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 593 594 static int t5_write_combine = 0; 595 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 596 0, "Use WC instead of UC for BAR2"); 597 598 static int t4_num_vis = 1; 599 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 600 "Number of VIs per port"); 601 602 /* 603 * PCIe Relaxed Ordering. 604 * -1: driver should figure out a good value. 605 * 0: disable RO. 606 * 1: enable RO. 607 * 2: leave RO alone. 608 */ 609 static int pcie_relaxed_ordering = -1; 610 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 611 &pcie_relaxed_ordering, 0, 612 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 613 614 static int t4_panic_on_fatal_err = 0; 615 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN, 616 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 617 618 static int t4_reset_on_fatal_err = 0; 619 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN, 620 &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors"); 621 622 static int t4_clock_gate_on_suspend = 0; 623 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN, 624 &t4_clock_gate_on_suspend, 0, "gate the clock on suspend"); 625 626 static int t4_tx_vm_wr = 0; 627 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0, 628 "Use VM work requests to transmit packets."); 629 630 /* 631 * Set to non-zero to enable the attack filter. A packet that matches any of 632 * these conditions will get dropped on ingress: 633 * 1) IP && source address == destination address. 634 * 2) TCP/IP && source address is not a unicast address. 635 * 3) TCP/IP && destination address is not a unicast address. 636 * 4) IP && source address is loopback (127.x.y.z). 637 * 5) IP && destination address is loopback (127.x.y.z). 638 * 6) IPv6 && source address == destination address. 639 * 7) IPv6 && source address is not a unicast address. 640 * 8) IPv6 && source address is loopback (::1/128). 641 * 9) IPv6 && destination address is loopback (::1/128). 642 * 10) IPv6 && source address is unspecified (::/128). 643 * 11) IPv6 && destination address is unspecified (::/128). 644 * 12) TCP/IPv6 && source address is multicast (ff00::/8). 645 * 13) TCP/IPv6 && destination address is multicast (ff00::/8). 646 */ 647 static int t4_attack_filter = 0; 648 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN, 649 &t4_attack_filter, 0, "Drop suspicious traffic"); 650 651 static int t4_drop_ip_fragments = 0; 652 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN, 653 &t4_drop_ip_fragments, 0, "Drop IP fragments"); 654 655 static int t4_drop_pkts_with_l2_errors = 1; 656 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN, 657 &t4_drop_pkts_with_l2_errors, 0, 658 "Drop all frames with Layer 2 length or checksum errors"); 659 660 static int t4_drop_pkts_with_l3_errors = 0; 661 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN, 662 &t4_drop_pkts_with_l3_errors, 0, 663 "Drop all frames with IP version, length, or checksum errors"); 664 665 static int t4_drop_pkts_with_l4_errors = 0; 666 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN, 667 &t4_drop_pkts_with_l4_errors, 0, 668 "Drop all frames with Layer 4 length, checksum, or other errors"); 669 670 #ifdef TCP_OFFLOAD 671 /* 672 * TOE tunables. 673 */ 674 static int t4_cop_managed_offloading = 0; 675 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 676 &t4_cop_managed_offloading, 0, 677 "COP (Connection Offload Policy) controls all TOE offload"); 678 #endif 679 680 #ifdef KERN_TLS 681 /* 682 * This enables KERN_TLS for all adapters if set. 683 */ 684 static int t4_kern_tls = 0; 685 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0, 686 "Enable KERN_TLS mode for T6 adapters"); 687 688 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 689 "cxgbe(4) KERN_TLS parameters"); 690 691 static int t4_tls_inline_keys = 0; 692 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN, 693 &t4_tls_inline_keys, 0, 694 "Always pass TLS keys in work requests (1) or attempt to store TLS keys " 695 "in card memory."); 696 697 static int t4_tls_combo_wrs = 0; 698 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs, 699 0, "Attempt to combine TCB field updates with TLS record work requests."); 700 #endif 701 702 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 703 static int vi_mac_funcs[] = { 704 FW_VI_FUNC_ETH, 705 FW_VI_FUNC_OFLD, 706 FW_VI_FUNC_IWARP, 707 FW_VI_FUNC_OPENISCSI, 708 FW_VI_FUNC_OPENFCOE, 709 FW_VI_FUNC_FOISCSI, 710 FW_VI_FUNC_FOFCOE, 711 }; 712 713 struct intrs_and_queues { 714 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 715 uint16_t num_vis; /* number of VIs for each port */ 716 uint16_t nirq; /* Total # of vectors */ 717 uint16_t ntxq; /* # of NIC txq's for each port */ 718 uint16_t nrxq; /* # of NIC rxq's for each port */ 719 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 720 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 721 uint16_t nnmtxq; /* # of netmap txq's */ 722 uint16_t nnmrxq; /* # of netmap rxq's */ 723 724 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 725 uint16_t ntxq_vi; /* # of NIC txq's */ 726 uint16_t nrxq_vi; /* # of NIC rxq's */ 727 uint16_t nofldtxq_vi; /* # of TOE txq's */ 728 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 729 uint16_t nnmtxq_vi; /* # of netmap txq's */ 730 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 731 }; 732 733 static void setup_memwin(struct adapter *); 734 static void position_memwin(struct adapter *, int, uint32_t); 735 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 736 static int fwmtype_to_hwmtype(int); 737 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 738 uint32_t *); 739 static int fixup_devlog_params(struct adapter *); 740 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 741 static int contact_firmware(struct adapter *); 742 static int partition_resources(struct adapter *); 743 static int get_params__pre_init(struct adapter *); 744 static int set_params__pre_init(struct adapter *); 745 static int get_params__post_init(struct adapter *); 746 static int set_params__post_init(struct adapter *); 747 static void t4_set_desc(struct adapter *); 748 static bool fixed_ifmedia(struct port_info *); 749 static void build_medialist(struct port_info *); 750 static void init_link_config(struct port_info *); 751 static int fixup_link_config(struct port_info *); 752 static int apply_link_config(struct port_info *); 753 static int cxgbe_init_synchronized(struct vi_info *); 754 static int cxgbe_uninit_synchronized(struct vi_info *); 755 static int adapter_full_init(struct adapter *); 756 static void adapter_full_uninit(struct adapter *); 757 static int vi_full_init(struct vi_info *); 758 static void vi_full_uninit(struct vi_info *); 759 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *); 760 static void quiesce_txq(struct sge_txq *); 761 static void quiesce_wrq(struct sge_wrq *); 762 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 763 static void quiesce_vi(struct vi_info *); 764 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 765 driver_intr_t *, void *, char *); 766 static int t4_free_irq(struct adapter *, struct irq *); 767 static void t4_init_atid_table(struct adapter *); 768 static void t4_free_atid_table(struct adapter *); 769 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 770 static void vi_refresh_stats(struct vi_info *); 771 static void cxgbe_refresh_stats(struct vi_info *); 772 static void cxgbe_tick(void *); 773 static void vi_tick(void *); 774 static void cxgbe_sysctls(struct port_info *); 775 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 776 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 777 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 778 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 779 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 780 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS); 781 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 782 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 783 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 784 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 785 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 786 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS); 787 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS); 788 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS); 789 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 790 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS); 791 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 792 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 793 static int sysctl_vdd(SYSCTL_HANDLER_ARGS); 794 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS); 795 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 796 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 797 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 798 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 799 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 800 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 801 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 802 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 803 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 804 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS); 805 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 806 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 807 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 808 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 809 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 810 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 811 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 812 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 813 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 814 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 815 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 816 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 817 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 818 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 819 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS); 820 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 821 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 822 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 823 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 824 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 825 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 826 static int sysctl_reset(SYSCTL_HANDLER_ARGS); 827 #ifdef TCP_OFFLOAD 828 static int sysctl_tls(SYSCTL_HANDLER_ARGS); 829 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 830 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 831 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 832 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 833 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 834 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 835 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 836 #endif 837 static int get_sge_context(struct adapter *, struct t4_sge_context *); 838 static int load_fw(struct adapter *, struct t4_data *); 839 static int load_cfg(struct adapter *, struct t4_data *); 840 static int load_boot(struct adapter *, struct t4_bootrom *); 841 static int load_bootcfg(struct adapter *, struct t4_data *); 842 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 843 static void free_offload_policy(struct t4_offload_policy *); 844 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 845 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 846 static int read_i2c(struct adapter *, struct t4_i2c_data *); 847 static int clear_stats(struct adapter *, u_int); 848 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *); 849 static int release_clip_addr(struct adapter *, struct t4_clip_addr *); 850 #ifdef TCP_OFFLOAD 851 static int toe_capability(struct vi_info *, bool); 852 static int t4_deactivate_all_uld(struct adapter *); 853 static void t4_async_event(struct adapter *); 854 #endif 855 #ifdef KERN_TLS 856 static int ktls_capability(struct adapter *, bool); 857 #endif 858 static int mod_event(module_t, int, void *); 859 static int notify_siblings(device_t, int); 860 static uint64_t vi_get_counter(if_t, ift_counter); 861 static uint64_t cxgbe_get_counter(if_t, ift_counter); 862 static void enable_vxlan_rx(struct adapter *); 863 static void reset_adapter_task(void *, int); 864 static void fatal_error_task(void *, int); 865 static void dump_devlog(struct adapter *); 866 static void dump_cim_regs(struct adapter *); 867 static void dump_cimla(struct adapter *); 868 869 struct { 870 uint16_t device; 871 char *desc; 872 } t4_pciids[] = { 873 {0xa000, "Chelsio Terminator 4 FPGA"}, 874 {0x4400, "Chelsio T440-dbg"}, 875 {0x4401, "Chelsio T420-CR"}, 876 {0x4402, "Chelsio T422-CR"}, 877 {0x4403, "Chelsio T440-CR"}, 878 {0x4404, "Chelsio T420-BCH"}, 879 {0x4405, "Chelsio T440-BCH"}, 880 {0x4406, "Chelsio T440-CH"}, 881 {0x4407, "Chelsio T420-SO"}, 882 {0x4408, "Chelsio T420-CX"}, 883 {0x4409, "Chelsio T420-BT"}, 884 {0x440a, "Chelsio T404-BT"}, 885 {0x440e, "Chelsio T440-LP-CR"}, 886 }, t5_pciids[] = { 887 {0xb000, "Chelsio Terminator 5 FPGA"}, 888 {0x5400, "Chelsio T580-dbg"}, 889 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 890 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 891 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 892 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 893 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 894 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 895 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 896 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 897 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 898 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 899 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 900 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 901 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 902 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 903 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 904 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 905 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 906 907 /* Custom */ 908 {0x5483, "Custom T540-CR"}, 909 {0x5484, "Custom T540-BT"}, 910 }, t6_pciids[] = { 911 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 912 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 913 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 914 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 915 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 916 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 917 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 918 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 919 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 920 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 921 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 922 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 923 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 924 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 925 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 926 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 927 928 /* Custom */ 929 {0x6480, "Custom T6225-CR"}, 930 {0x6481, "Custom T62100-CR"}, 931 {0x6482, "Custom T6225-CR"}, 932 {0x6483, "Custom T62100-CR"}, 933 {0x6484, "Custom T64100-CR"}, 934 {0x6485, "Custom T6240-SO"}, 935 {0x6486, "Custom T6225-SO-CR"}, 936 {0x6487, "Custom T6225-CR"}, 937 }; 938 939 #ifdef TCP_OFFLOAD 940 /* 941 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 942 * be exactly the same for both rxq and ofld_rxq. 943 */ 944 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 945 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 946 #endif 947 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 948 949 static int 950 t4_probe(device_t dev) 951 { 952 int i; 953 uint16_t v = pci_get_vendor(dev); 954 uint16_t d = pci_get_device(dev); 955 uint8_t f = pci_get_function(dev); 956 957 if (v != PCI_VENDOR_ID_CHELSIO) 958 return (ENXIO); 959 960 /* Attach only to PF0 of the FPGA */ 961 if (d == 0xa000 && f != 0) 962 return (ENXIO); 963 964 for (i = 0; i < nitems(t4_pciids); i++) { 965 if (d == t4_pciids[i].device) { 966 device_set_desc(dev, t4_pciids[i].desc); 967 return (BUS_PROBE_DEFAULT); 968 } 969 } 970 971 return (ENXIO); 972 } 973 974 static int 975 t5_probe(device_t dev) 976 { 977 int i; 978 uint16_t v = pci_get_vendor(dev); 979 uint16_t d = pci_get_device(dev); 980 uint8_t f = pci_get_function(dev); 981 982 if (v != PCI_VENDOR_ID_CHELSIO) 983 return (ENXIO); 984 985 /* Attach only to PF0 of the FPGA */ 986 if (d == 0xb000 && f != 0) 987 return (ENXIO); 988 989 for (i = 0; i < nitems(t5_pciids); i++) { 990 if (d == t5_pciids[i].device) { 991 device_set_desc(dev, t5_pciids[i].desc); 992 return (BUS_PROBE_DEFAULT); 993 } 994 } 995 996 return (ENXIO); 997 } 998 999 static int 1000 t6_probe(device_t dev) 1001 { 1002 int i; 1003 uint16_t v = pci_get_vendor(dev); 1004 uint16_t d = pci_get_device(dev); 1005 1006 if (v != PCI_VENDOR_ID_CHELSIO) 1007 return (ENXIO); 1008 1009 for (i = 0; i < nitems(t6_pciids); i++) { 1010 if (d == t6_pciids[i].device) { 1011 device_set_desc(dev, t6_pciids[i].desc); 1012 return (BUS_PROBE_DEFAULT); 1013 } 1014 } 1015 1016 return (ENXIO); 1017 } 1018 1019 static void 1020 t5_attribute_workaround(device_t dev) 1021 { 1022 device_t root_port; 1023 uint32_t v; 1024 1025 /* 1026 * The T5 chips do not properly echo the No Snoop and Relaxed 1027 * Ordering attributes when replying to a TLP from a Root 1028 * Port. As a workaround, find the parent Root Port and 1029 * disable No Snoop and Relaxed Ordering. Note that this 1030 * affects all devices under this root port. 1031 */ 1032 root_port = pci_find_pcie_root_port(dev); 1033 if (root_port == NULL) { 1034 device_printf(dev, "Unable to find parent root port\n"); 1035 return; 1036 } 1037 1038 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 1039 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 1040 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 1041 0) 1042 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 1043 device_get_nameunit(root_port)); 1044 } 1045 1046 static const struct devnames devnames[] = { 1047 { 1048 .nexus_name = "t4nex", 1049 .ifnet_name = "cxgbe", 1050 .vi_ifnet_name = "vcxgbe", 1051 .pf03_drv_name = "t4iov", 1052 .vf_nexus_name = "t4vf", 1053 .vf_ifnet_name = "cxgbev" 1054 }, { 1055 .nexus_name = "t5nex", 1056 .ifnet_name = "cxl", 1057 .vi_ifnet_name = "vcxl", 1058 .pf03_drv_name = "t5iov", 1059 .vf_nexus_name = "t5vf", 1060 .vf_ifnet_name = "cxlv" 1061 }, { 1062 .nexus_name = "t6nex", 1063 .ifnet_name = "cc", 1064 .vi_ifnet_name = "vcc", 1065 .pf03_drv_name = "t6iov", 1066 .vf_nexus_name = "t6vf", 1067 .vf_ifnet_name = "ccv" 1068 } 1069 }; 1070 1071 void 1072 t4_init_devnames(struct adapter *sc) 1073 { 1074 int id; 1075 1076 id = chip_id(sc); 1077 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 1078 sc->names = &devnames[id - CHELSIO_T4]; 1079 else { 1080 device_printf(sc->dev, "chip id %d is not supported.\n", id); 1081 sc->names = NULL; 1082 } 1083 } 1084 1085 static int 1086 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 1087 { 1088 const char *parent, *name; 1089 long value; 1090 int line, unit; 1091 1092 line = 0; 1093 parent = device_get_nameunit(sc->dev); 1094 name = sc->names->ifnet_name; 1095 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 1096 if (resource_long_value(name, unit, "port", &value) == 0 && 1097 value == pi->port_id) 1098 return (unit); 1099 } 1100 return (-1); 1101 } 1102 1103 static void 1104 t4_calibration(void *arg) 1105 { 1106 struct adapter *sc; 1107 struct clock_sync *cur, *nex; 1108 uint64_t hw; 1109 sbintime_t sbt; 1110 int next_up; 1111 1112 sc = (struct adapter *)arg; 1113 1114 KASSERT((hw_off_limits(sc) == 0), ("hw_off_limits at t4_calibration")); 1115 hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO); 1116 sbt = sbinuptime(); 1117 1118 cur = &sc->cal_info[sc->cal_current]; 1119 next_up = (sc->cal_current + 1) % CNT_CAL_INFO; 1120 nex = &sc->cal_info[next_up]; 1121 if (__predict_false(sc->cal_count == 0)) { 1122 /* First time in, just get the values in */ 1123 cur->hw_cur = hw; 1124 cur->sbt_cur = sbt; 1125 sc->cal_count++; 1126 goto done; 1127 } 1128 1129 if (cur->hw_cur == hw) { 1130 /* The clock is not advancing? */ 1131 sc->cal_count = 0; 1132 atomic_store_rel_int(&cur->gen, 0); 1133 goto done; 1134 } 1135 1136 seqc_write_begin(&nex->gen); 1137 nex->hw_prev = cur->hw_cur; 1138 nex->sbt_prev = cur->sbt_cur; 1139 nex->hw_cur = hw; 1140 nex->sbt_cur = sbt; 1141 seqc_write_end(&nex->gen); 1142 sc->cal_current = next_up; 1143 done: 1144 callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration, 1145 sc, C_DIRECT_EXEC); 1146 } 1147 1148 static void 1149 t4_calibration_start(struct adapter *sc) 1150 { 1151 /* 1152 * Here if we have not done a calibration 1153 * then do so otherwise start the appropriate 1154 * timer. 1155 */ 1156 int i; 1157 1158 for (i = 0; i < CNT_CAL_INFO; i++) { 1159 sc->cal_info[i].gen = 0; 1160 } 1161 sc->cal_current = 0; 1162 sc->cal_count = 0; 1163 sc->cal_gen = 0; 1164 t4_calibration(sc); 1165 } 1166 1167 static int 1168 t4_attach(device_t dev) 1169 { 1170 struct adapter *sc; 1171 int rc = 0, i, j, rqidx, tqidx, nports; 1172 struct make_dev_args mda; 1173 struct intrs_and_queues iaq; 1174 struct sge *s; 1175 uint32_t *buf; 1176 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1177 int ofld_tqidx; 1178 #endif 1179 #ifdef TCP_OFFLOAD 1180 int ofld_rqidx; 1181 #endif 1182 #ifdef DEV_NETMAP 1183 int nm_rqidx, nm_tqidx; 1184 #endif 1185 int num_vis; 1186 1187 sc = device_get_softc(dev); 1188 sc->dev = dev; 1189 sysctl_ctx_init(&sc->ctx); 1190 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 1191 1192 if ((pci_get_device(dev) & 0xff00) == 0x5400) 1193 t5_attribute_workaround(dev); 1194 pci_enable_busmaster(dev); 1195 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 1196 uint32_t v; 1197 1198 pci_set_max_read_req(dev, 4096); 1199 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 1200 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 1201 if (pcie_relaxed_ordering == 0 && 1202 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 1203 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 1204 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1205 } else if (pcie_relaxed_ordering == 1 && 1206 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 1207 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 1208 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1209 } 1210 } 1211 1212 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 1213 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 1214 sc->traceq = -1; 1215 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 1216 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 1217 device_get_nameunit(dev)); 1218 1219 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 1220 device_get_nameunit(dev)); 1221 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 1222 t4_add_adapter(sc); 1223 1224 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 1225 TAILQ_INIT(&sc->sfl); 1226 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 1227 1228 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 1229 1230 sc->policy = NULL; 1231 rw_init(&sc->policy_lock, "connection offload policy"); 1232 1233 callout_init(&sc->ktls_tick, 1); 1234 1235 callout_init(&sc->cal_callout, 1); 1236 1237 refcount_init(&sc->vxlan_refcount, 0); 1238 1239 TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc); 1240 TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc); 1241 1242 sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1243 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq", 1244 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 1245 sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1246 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq", 1247 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 1248 1249 rc = t4_map_bars_0_and_4(sc); 1250 if (rc != 0) 1251 goto done; /* error message displayed already */ 1252 1253 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1254 1255 /* Prepare the adapter for operation. */ 1256 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1257 rc = -t4_prep_adapter(sc, buf); 1258 free(buf, M_CXGBE); 1259 if (rc != 0) { 1260 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1261 goto done; 1262 } 1263 1264 /* 1265 * This is the real PF# to which we're attaching. Works from within PCI 1266 * passthrough environments too, where pci_get_function() could return a 1267 * different PF# depending on the passthrough configuration. We need to 1268 * use the real PF# in all our communication with the firmware. 1269 */ 1270 j = t4_read_reg(sc, A_PL_WHOAMI); 1271 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1272 sc->mbox = sc->pf; 1273 1274 t4_init_devnames(sc); 1275 if (sc->names == NULL) { 1276 rc = ENOTSUP; 1277 goto done; /* error message displayed already */ 1278 } 1279 1280 /* 1281 * Do this really early, with the memory windows set up even before the 1282 * character device. The userland tool's register i/o and mem read 1283 * will work even in "recovery mode". 1284 */ 1285 setup_memwin(sc); 1286 if (t4_init_devlog_params(sc, 0) == 0) 1287 fixup_devlog_params(sc); 1288 make_dev_args_init(&mda); 1289 mda.mda_devsw = &t4_cdevsw; 1290 mda.mda_uid = UID_ROOT; 1291 mda.mda_gid = GID_WHEEL; 1292 mda.mda_mode = 0600; 1293 mda.mda_si_drv1 = sc; 1294 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1295 if (rc != 0) 1296 device_printf(dev, "failed to create nexus char device: %d.\n", 1297 rc); 1298 1299 /* Go no further if recovery mode has been requested. */ 1300 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1301 device_printf(dev, "recovery mode.\n"); 1302 goto done; 1303 } 1304 1305 #if defined(__i386__) 1306 if ((cpu_feature & CPUID_CX8) == 0) { 1307 device_printf(dev, "64 bit atomics not available.\n"); 1308 rc = ENOTSUP; 1309 goto done; 1310 } 1311 #endif 1312 1313 /* Contact the firmware and try to become the master driver. */ 1314 rc = contact_firmware(sc); 1315 if (rc != 0) 1316 goto done; /* error message displayed already */ 1317 MPASS(sc->flags & FW_OK); 1318 1319 rc = get_params__pre_init(sc); 1320 if (rc != 0) 1321 goto done; /* error message displayed already */ 1322 1323 if (sc->flags & MASTER_PF) { 1324 rc = partition_resources(sc); 1325 if (rc != 0) 1326 goto done; /* error message displayed already */ 1327 t4_intr_clear(sc); 1328 } 1329 1330 rc = get_params__post_init(sc); 1331 if (rc != 0) 1332 goto done; /* error message displayed already */ 1333 1334 rc = set_params__post_init(sc); 1335 if (rc != 0) 1336 goto done; /* error message displayed already */ 1337 1338 rc = t4_map_bar_2(sc); 1339 if (rc != 0) 1340 goto done; /* error message displayed already */ 1341 1342 rc = t4_create_dma_tag(sc); 1343 if (rc != 0) 1344 goto done; /* error message displayed already */ 1345 1346 /* 1347 * First pass over all the ports - allocate VIs and initialize some 1348 * basic parameters like mac address, port type, etc. 1349 */ 1350 for_each_port(sc, i) { 1351 struct port_info *pi; 1352 1353 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1354 sc->port[i] = pi; 1355 1356 /* These must be set before t4_port_init */ 1357 pi->adapter = sc; 1358 pi->port_id = i; 1359 /* 1360 * XXX: vi[0] is special so we can't delay this allocation until 1361 * pi->nvi's final value is known. 1362 */ 1363 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1364 M_ZERO | M_WAITOK); 1365 1366 /* 1367 * Allocate the "main" VI and initialize parameters 1368 * like mac addr. 1369 */ 1370 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1371 if (rc != 0) { 1372 device_printf(dev, "unable to initialize port %d: %d\n", 1373 i, rc); 1374 free(pi->vi, M_CXGBE); 1375 free(pi, M_CXGBE); 1376 sc->port[i] = NULL; 1377 goto done; 1378 } 1379 1380 if (is_bt(pi->port_type)) 1381 setbit(&sc->bt_map, pi->tx_chan); 1382 else 1383 MPASS(!isset(&sc->bt_map, pi->tx_chan)); 1384 1385 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1386 device_get_nameunit(dev), i); 1387 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1388 sc->chan_map[pi->tx_chan] = i; 1389 1390 /* 1391 * The MPS counter for FCS errors doesn't work correctly on the 1392 * T6 so we use the MAC counter here. Which MAC is in use 1393 * depends on the link settings which will be known when the 1394 * link comes up. 1395 */ 1396 if (is_t6(sc)) { 1397 pi->fcs_reg = -1; 1398 } else if (is_t4(sc)) { 1399 pi->fcs_reg = PORT_REG(pi->tx_chan, 1400 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1401 } else { 1402 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 1403 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1404 } 1405 pi->fcs_base = 0; 1406 1407 /* All VIs on this port share this media. */ 1408 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1409 cxgbe_media_status); 1410 1411 PORT_LOCK(pi); 1412 init_link_config(pi); 1413 fixup_link_config(pi); 1414 build_medialist(pi); 1415 if (fixed_ifmedia(pi)) 1416 pi->flags |= FIXED_IFMEDIA; 1417 PORT_UNLOCK(pi); 1418 1419 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1420 t4_ifnet_unit(sc, pi)); 1421 if (pi->dev == NULL) { 1422 device_printf(dev, 1423 "failed to add device for port %d.\n", i); 1424 rc = ENXIO; 1425 goto done; 1426 } 1427 pi->vi[0].dev = pi->dev; 1428 device_set_softc(pi->dev, pi); 1429 } 1430 1431 /* 1432 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1433 */ 1434 nports = sc->params.nports; 1435 rc = cfg_itype_and_nqueues(sc, &iaq); 1436 if (rc != 0) 1437 goto done; /* error message displayed already */ 1438 1439 num_vis = iaq.num_vis; 1440 sc->intr_type = iaq.intr_type; 1441 sc->intr_count = iaq.nirq; 1442 1443 s = &sc->sge; 1444 s->nrxq = nports * iaq.nrxq; 1445 s->ntxq = nports * iaq.ntxq; 1446 if (num_vis > 1) { 1447 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1448 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1449 } 1450 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1451 s->neq += nports; /* ctrl queues: 1 per port */ 1452 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1453 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1454 if (is_offload(sc) || is_ethoffload(sc)) { 1455 s->nofldtxq = nports * iaq.nofldtxq; 1456 if (num_vis > 1) 1457 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1458 s->neq += s->nofldtxq; 1459 1460 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq), 1461 M_CXGBE, M_ZERO | M_WAITOK); 1462 } 1463 #endif 1464 #ifdef TCP_OFFLOAD 1465 if (is_offload(sc)) { 1466 s->nofldrxq = nports * iaq.nofldrxq; 1467 if (num_vis > 1) 1468 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1469 s->neq += s->nofldrxq; /* free list */ 1470 s->niq += s->nofldrxq; 1471 1472 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1473 M_CXGBE, M_ZERO | M_WAITOK); 1474 } 1475 #endif 1476 #ifdef DEV_NETMAP 1477 s->nnmrxq = 0; 1478 s->nnmtxq = 0; 1479 if (t4_native_netmap & NN_MAIN_VI) { 1480 s->nnmrxq += nports * iaq.nnmrxq; 1481 s->nnmtxq += nports * iaq.nnmtxq; 1482 } 1483 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) { 1484 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi; 1485 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi; 1486 } 1487 s->neq += s->nnmtxq + s->nnmrxq; 1488 s->niq += s->nnmrxq; 1489 1490 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1491 M_CXGBE, M_ZERO | M_WAITOK); 1492 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1493 M_CXGBE, M_ZERO | M_WAITOK); 1494 #endif 1495 MPASS(s->niq <= s->iqmap_sz); 1496 MPASS(s->neq <= s->eqmap_sz); 1497 1498 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1499 M_ZERO | M_WAITOK); 1500 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1501 M_ZERO | M_WAITOK); 1502 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1503 M_ZERO | M_WAITOK); 1504 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE, 1505 M_ZERO | M_WAITOK); 1506 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE, 1507 M_ZERO | M_WAITOK); 1508 1509 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1510 M_ZERO | M_WAITOK); 1511 1512 t4_init_l2t(sc, M_WAITOK); 1513 t4_init_smt(sc, M_WAITOK); 1514 t4_init_tx_sched(sc); 1515 t4_init_atid_table(sc); 1516 #ifdef RATELIMIT 1517 t4_init_etid_table(sc); 1518 #endif 1519 #ifdef INET6 1520 t4_init_clip_table(sc); 1521 #endif 1522 if (sc->vres.key.size != 0) 1523 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1524 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1525 1526 /* 1527 * Second pass over the ports. This time we know the number of rx and 1528 * tx queues that each port should get. 1529 */ 1530 rqidx = tqidx = 0; 1531 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1532 ofld_tqidx = 0; 1533 #endif 1534 #ifdef TCP_OFFLOAD 1535 ofld_rqidx = 0; 1536 #endif 1537 #ifdef DEV_NETMAP 1538 nm_rqidx = nm_tqidx = 0; 1539 #endif 1540 for_each_port(sc, i) { 1541 struct port_info *pi = sc->port[i]; 1542 struct vi_info *vi; 1543 1544 if (pi == NULL) 1545 continue; 1546 1547 pi->nvi = num_vis; 1548 for_each_vi(pi, j, vi) { 1549 vi->pi = pi; 1550 vi->adapter = sc; 1551 vi->first_intr = -1; 1552 vi->qsize_rxq = t4_qsize_rxq; 1553 vi->qsize_txq = t4_qsize_txq; 1554 1555 vi->first_rxq = rqidx; 1556 vi->first_txq = tqidx; 1557 vi->tmr_idx = t4_tmr_idx; 1558 vi->pktc_idx = t4_pktc_idx; 1559 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1560 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1561 1562 rqidx += vi->nrxq; 1563 tqidx += vi->ntxq; 1564 1565 if (j == 0 && vi->ntxq > 1) 1566 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1567 else 1568 vi->rsrv_noflowq = 0; 1569 1570 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1571 vi->first_ofld_txq = ofld_tqidx; 1572 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1573 ofld_tqidx += vi->nofldtxq; 1574 #endif 1575 #ifdef TCP_OFFLOAD 1576 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1577 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1578 vi->first_ofld_rxq = ofld_rqidx; 1579 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1580 1581 ofld_rqidx += vi->nofldrxq; 1582 #endif 1583 #ifdef DEV_NETMAP 1584 vi->first_nm_rxq = nm_rqidx; 1585 vi->first_nm_txq = nm_tqidx; 1586 if (j == 0) { 1587 vi->nnmrxq = iaq.nnmrxq; 1588 vi->nnmtxq = iaq.nnmtxq; 1589 } else { 1590 vi->nnmrxq = iaq.nnmrxq_vi; 1591 vi->nnmtxq = iaq.nnmtxq_vi; 1592 } 1593 nm_rqidx += vi->nnmrxq; 1594 nm_tqidx += vi->nnmtxq; 1595 #endif 1596 } 1597 } 1598 1599 rc = t4_setup_intr_handlers(sc); 1600 if (rc != 0) { 1601 device_printf(dev, 1602 "failed to setup interrupt handlers: %d\n", rc); 1603 goto done; 1604 } 1605 1606 rc = bus_generic_probe(dev); 1607 if (rc != 0) { 1608 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1609 goto done; 1610 } 1611 1612 /* 1613 * Ensure thread-safe mailbox access (in debug builds). 1614 * 1615 * So far this was the only thread accessing the mailbox but various 1616 * ifnets and sysctls are about to be created and their handlers/ioctls 1617 * will access the mailbox from different threads. 1618 */ 1619 sc->flags |= CHK_MBOX_ACCESS; 1620 1621 rc = bus_generic_attach(dev); 1622 if (rc != 0) { 1623 device_printf(dev, 1624 "failed to attach all child ports: %d\n", rc); 1625 goto done; 1626 } 1627 t4_calibration_start(sc); 1628 1629 device_printf(dev, 1630 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1631 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1632 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1633 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1634 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1635 1636 t4_set_desc(sc); 1637 1638 notify_siblings(dev, 0); 1639 1640 done: 1641 if (rc != 0 && sc->cdev) { 1642 /* cdev was created and so cxgbetool works; recover that way. */ 1643 device_printf(dev, 1644 "error during attach, adapter is now in recovery mode.\n"); 1645 rc = 0; 1646 } 1647 1648 if (rc != 0) 1649 t4_detach_common(dev); 1650 else 1651 t4_sysctls(sc); 1652 1653 return (rc); 1654 } 1655 1656 static int 1657 t4_child_location(device_t bus, device_t dev, struct sbuf *sb) 1658 { 1659 struct adapter *sc; 1660 struct port_info *pi; 1661 int i; 1662 1663 sc = device_get_softc(bus); 1664 for_each_port(sc, i) { 1665 pi = sc->port[i]; 1666 if (pi != NULL && pi->dev == dev) { 1667 sbuf_printf(sb, "port=%d", pi->port_id); 1668 break; 1669 } 1670 } 1671 return (0); 1672 } 1673 1674 static int 1675 t4_ready(device_t dev) 1676 { 1677 struct adapter *sc; 1678 1679 sc = device_get_softc(dev); 1680 if (sc->flags & FW_OK) 1681 return (0); 1682 return (ENXIO); 1683 } 1684 1685 static int 1686 t4_read_port_device(device_t dev, int port, device_t *child) 1687 { 1688 struct adapter *sc; 1689 struct port_info *pi; 1690 1691 sc = device_get_softc(dev); 1692 if (port < 0 || port >= MAX_NPORTS) 1693 return (EINVAL); 1694 pi = sc->port[port]; 1695 if (pi == NULL || pi->dev == NULL) 1696 return (ENXIO); 1697 *child = pi->dev; 1698 return (0); 1699 } 1700 1701 static int 1702 notify_siblings(device_t dev, int detaching) 1703 { 1704 device_t sibling; 1705 int error, i; 1706 1707 error = 0; 1708 for (i = 0; i < PCI_FUNCMAX; i++) { 1709 if (i == pci_get_function(dev)) 1710 continue; 1711 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1712 pci_get_slot(dev), i); 1713 if (sibling == NULL || !device_is_attached(sibling)) 1714 continue; 1715 if (detaching) 1716 error = T4_DETACH_CHILD(sibling); 1717 else 1718 (void)T4_ATTACH_CHILD(sibling); 1719 if (error) 1720 break; 1721 } 1722 return (error); 1723 } 1724 1725 /* 1726 * Idempotent 1727 */ 1728 static int 1729 t4_detach(device_t dev) 1730 { 1731 int rc; 1732 1733 rc = notify_siblings(dev, 1); 1734 if (rc) { 1735 device_printf(dev, 1736 "failed to detach sibling devices: %d\n", rc); 1737 return (rc); 1738 } 1739 1740 return (t4_detach_common(dev)); 1741 } 1742 1743 int 1744 t4_detach_common(device_t dev) 1745 { 1746 struct adapter *sc; 1747 struct port_info *pi; 1748 int i, rc; 1749 1750 sc = device_get_softc(dev); 1751 1752 #ifdef TCP_OFFLOAD 1753 rc = t4_deactivate_all_uld(sc); 1754 if (rc) { 1755 device_printf(dev, 1756 "failed to detach upper layer drivers: %d\n", rc); 1757 return (rc); 1758 } 1759 #endif 1760 1761 if (sc->cdev) { 1762 destroy_dev(sc->cdev); 1763 sc->cdev = NULL; 1764 } 1765 1766 sx_xlock(&t4_list_lock); 1767 SLIST_REMOVE(&t4_list, sc, adapter, link); 1768 sx_xunlock(&t4_list_lock); 1769 1770 sc->flags &= ~CHK_MBOX_ACCESS; 1771 if (sc->flags & FULL_INIT_DONE) { 1772 if (!(sc->flags & IS_VF)) 1773 t4_intr_disable(sc); 1774 } 1775 1776 if (device_is_attached(dev)) { 1777 rc = bus_generic_detach(dev); 1778 if (rc) { 1779 device_printf(dev, 1780 "failed to detach child devices: %d\n", rc); 1781 return (rc); 1782 } 1783 } 1784 1785 for (i = 0; i < sc->intr_count; i++) 1786 t4_free_irq(sc, &sc->irq[i]); 1787 1788 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1789 t4_free_tx_sched(sc); 1790 1791 for (i = 0; i < MAX_NPORTS; i++) { 1792 pi = sc->port[i]; 1793 if (pi) { 1794 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1795 if (pi->dev) 1796 device_delete_child(dev, pi->dev); 1797 1798 mtx_destroy(&pi->pi_lock); 1799 free(pi->vi, M_CXGBE); 1800 free(pi, M_CXGBE); 1801 } 1802 } 1803 callout_stop(&sc->cal_callout); 1804 callout_drain(&sc->cal_callout); 1805 device_delete_children(dev); 1806 sysctl_ctx_free(&sc->ctx); 1807 adapter_full_uninit(sc); 1808 1809 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1810 t4_fw_bye(sc, sc->mbox); 1811 1812 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1813 pci_release_msi(dev); 1814 1815 if (sc->regs_res) 1816 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1817 sc->regs_res); 1818 1819 if (sc->udbs_res) 1820 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1821 sc->udbs_res); 1822 1823 if (sc->msix_res) 1824 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1825 sc->msix_res); 1826 1827 if (sc->l2t) 1828 t4_free_l2t(sc->l2t); 1829 if (sc->smt) 1830 t4_free_smt(sc->smt); 1831 t4_free_atid_table(sc); 1832 #ifdef RATELIMIT 1833 t4_free_etid_table(sc); 1834 #endif 1835 if (sc->key_map) 1836 vmem_destroy(sc->key_map); 1837 #ifdef INET6 1838 t4_destroy_clip_table(sc); 1839 #endif 1840 1841 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1842 free(sc->sge.ofld_txq, M_CXGBE); 1843 #endif 1844 #ifdef TCP_OFFLOAD 1845 free(sc->sge.ofld_rxq, M_CXGBE); 1846 #endif 1847 #ifdef DEV_NETMAP 1848 free(sc->sge.nm_rxq, M_CXGBE); 1849 free(sc->sge.nm_txq, M_CXGBE); 1850 #endif 1851 free(sc->irq, M_CXGBE); 1852 free(sc->sge.rxq, M_CXGBE); 1853 free(sc->sge.txq, M_CXGBE); 1854 free(sc->sge.ctrlq, M_CXGBE); 1855 free(sc->sge.iqmap, M_CXGBE); 1856 free(sc->sge.eqmap, M_CXGBE); 1857 free(sc->tids.ftid_tab, M_CXGBE); 1858 free(sc->tids.hpftid_tab, M_CXGBE); 1859 free_hftid_hash(&sc->tids); 1860 free(sc->tids.tid_tab, M_CXGBE); 1861 t4_destroy_dma_tag(sc); 1862 1863 callout_drain(&sc->ktls_tick); 1864 callout_drain(&sc->sfl_callout); 1865 if (mtx_initialized(&sc->tids.ftid_lock)) { 1866 mtx_destroy(&sc->tids.ftid_lock); 1867 cv_destroy(&sc->tids.ftid_cv); 1868 } 1869 if (mtx_initialized(&sc->tids.atid_lock)) 1870 mtx_destroy(&sc->tids.atid_lock); 1871 if (mtx_initialized(&sc->ifp_lock)) 1872 mtx_destroy(&sc->ifp_lock); 1873 1874 if (rw_initialized(&sc->policy_lock)) { 1875 rw_destroy(&sc->policy_lock); 1876 #ifdef TCP_OFFLOAD 1877 if (sc->policy != NULL) 1878 free_offload_policy(sc->policy); 1879 #endif 1880 } 1881 1882 for (i = 0; i < NUM_MEMWIN; i++) { 1883 struct memwin *mw = &sc->memwin[i]; 1884 1885 if (rw_initialized(&mw->mw_lock)) 1886 rw_destroy(&mw->mw_lock); 1887 } 1888 1889 mtx_destroy(&sc->sfl_lock); 1890 mtx_destroy(&sc->reg_lock); 1891 mtx_destroy(&sc->sc_lock); 1892 1893 bzero(sc, sizeof(*sc)); 1894 1895 return (0); 1896 } 1897 1898 static inline bool 1899 ok_to_reset(struct adapter *sc) 1900 { 1901 struct tid_info *t = &sc->tids; 1902 struct port_info *pi; 1903 struct vi_info *vi; 1904 int i, j; 1905 int caps = IFCAP_TOE | IFCAP_NETMAP | IFCAP_TXRTLMT; 1906 1907 if (is_t6(sc)) 1908 caps |= IFCAP_TXTLS; 1909 1910 ASSERT_SYNCHRONIZED_OP(sc); 1911 MPASS(!(sc->flags & IS_VF)); 1912 1913 for_each_port(sc, i) { 1914 pi = sc->port[i]; 1915 for_each_vi(pi, j, vi) { 1916 if (if_getcapenable(vi->ifp) & caps) 1917 return (false); 1918 } 1919 } 1920 1921 if (atomic_load_int(&t->tids_in_use) > 0) 1922 return (false); 1923 if (atomic_load_int(&t->stids_in_use) > 0) 1924 return (false); 1925 if (atomic_load_int(&t->atids_in_use) > 0) 1926 return (false); 1927 if (atomic_load_int(&t->ftids_in_use) > 0) 1928 return (false); 1929 if (atomic_load_int(&t->hpftids_in_use) > 0) 1930 return (false); 1931 if (atomic_load_int(&t->etids_in_use) > 0) 1932 return (false); 1933 1934 return (true); 1935 } 1936 1937 static inline int 1938 stop_adapter(struct adapter *sc) 1939 { 1940 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) 1941 return (1); /* Already stopped. */ 1942 return (t4_shutdown_adapter(sc)); 1943 } 1944 1945 static int 1946 t4_suspend(device_t dev) 1947 { 1948 struct adapter *sc = device_get_softc(dev); 1949 struct port_info *pi; 1950 struct vi_info *vi; 1951 if_t ifp; 1952 struct sge_rxq *rxq; 1953 struct sge_txq *txq; 1954 struct sge_wrq *wrq; 1955 #ifdef TCP_OFFLOAD 1956 struct sge_ofld_rxq *ofld_rxq; 1957 #endif 1958 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1959 struct sge_ofld_txq *ofld_txq; 1960 #endif 1961 int rc, i, j, k; 1962 1963 CH_ALERT(sc, "suspend requested\n"); 1964 1965 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4sus"); 1966 if (rc != 0) 1967 return (ENXIO); 1968 1969 /* XXX: Can the kernel call suspend repeatedly without resume? */ 1970 MPASS(!hw_off_limits(sc)); 1971 1972 if (!ok_to_reset(sc)) { 1973 /* XXX: should list what resource is preventing suspend. */ 1974 CH_ERR(sc, "not safe to suspend.\n"); 1975 rc = EBUSY; 1976 goto done; 1977 } 1978 1979 /* No more DMA or interrupts. */ 1980 stop_adapter(sc); 1981 1982 /* Quiesce all activity. */ 1983 for_each_port(sc, i) { 1984 pi = sc->port[i]; 1985 pi->vxlan_tcam_entry = false; 1986 1987 PORT_LOCK(pi); 1988 if (pi->up_vis > 0) { 1989 /* 1990 * t4_shutdown_adapter has already shut down all the 1991 * PHYs but it also disables interrupts and DMA so there 1992 * won't be a link interrupt. So we update the state 1993 * manually and inform the kernel. 1994 */ 1995 pi->link_cfg.link_ok = false; 1996 t4_os_link_changed(pi); 1997 } 1998 PORT_UNLOCK(pi); 1999 2000 for_each_vi(pi, j, vi) { 2001 vi->xact_addr_filt = -1; 2002 mtx_lock(&vi->tick_mtx); 2003 vi->flags |= VI_SKIP_STATS; 2004 mtx_unlock(&vi->tick_mtx); 2005 if (!(vi->flags & VI_INIT_DONE)) 2006 continue; 2007 2008 ifp = vi->ifp; 2009 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2010 mtx_lock(&vi->tick_mtx); 2011 callout_stop(&vi->tick); 2012 mtx_unlock(&vi->tick_mtx); 2013 callout_drain(&vi->tick); 2014 } 2015 2016 /* 2017 * Note that the HW is not available. 2018 */ 2019 for_each_txq(vi, k, txq) { 2020 TXQ_LOCK(txq); 2021 txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED); 2022 TXQ_UNLOCK(txq); 2023 } 2024 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2025 for_each_ofld_txq(vi, k, ofld_txq) { 2026 ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED; 2027 } 2028 #endif 2029 for_each_rxq(vi, k, rxq) { 2030 rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2031 } 2032 #if defined(TCP_OFFLOAD) 2033 for_each_ofld_rxq(vi, k, ofld_rxq) { 2034 ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2035 } 2036 #endif 2037 2038 quiesce_vi(vi); 2039 } 2040 2041 if (sc->flags & FULL_INIT_DONE) { 2042 /* Control queue */ 2043 wrq = &sc->sge.ctrlq[i]; 2044 wrq->eq.flags &= ~EQ_HW_ALLOCATED; 2045 quiesce_wrq(wrq); 2046 } 2047 } 2048 if (sc->flags & FULL_INIT_DONE) { 2049 /* Firmware event queue */ 2050 sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED; 2051 quiesce_iq_fl(sc, &sc->sge.fwq, NULL); 2052 } 2053 2054 /* Stop calibration */ 2055 callout_stop(&sc->cal_callout); 2056 callout_drain(&sc->cal_callout); 2057 2058 /* Mark the adapter totally off limits. */ 2059 mtx_lock(&sc->reg_lock); 2060 atomic_set_int(&sc->error_flags, HW_OFF_LIMITS); 2061 sc->flags &= ~(FW_OK | MASTER_PF); 2062 sc->reset_thread = NULL; 2063 mtx_unlock(&sc->reg_lock); 2064 2065 if (t4_clock_gate_on_suspend) { 2066 t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN | 2067 F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN | 2068 F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0); 2069 } 2070 2071 CH_ALERT(sc, "suspend completed.\n"); 2072 done: 2073 end_synchronized_op(sc, 0); 2074 return (rc); 2075 } 2076 2077 struct adapter_pre_reset_state { 2078 u_int flags; 2079 uint16_t nbmcaps; 2080 uint16_t linkcaps; 2081 uint16_t switchcaps; 2082 uint16_t niccaps; 2083 uint16_t toecaps; 2084 uint16_t rdmacaps; 2085 uint16_t cryptocaps; 2086 uint16_t iscsicaps; 2087 uint16_t fcoecaps; 2088 2089 u_int cfcsum; 2090 char cfg_file[32]; 2091 2092 struct adapter_params params; 2093 struct t4_virt_res vres; 2094 struct tid_info tids; 2095 struct sge sge; 2096 2097 int rawf_base; 2098 int nrawf; 2099 2100 }; 2101 2102 static void 2103 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2104 { 2105 2106 ASSERT_SYNCHRONIZED_OP(sc); 2107 2108 o->flags = sc->flags; 2109 2110 o->nbmcaps = sc->nbmcaps; 2111 o->linkcaps = sc->linkcaps; 2112 o->switchcaps = sc->switchcaps; 2113 o->niccaps = sc->niccaps; 2114 o->toecaps = sc->toecaps; 2115 o->rdmacaps = sc->rdmacaps; 2116 o->cryptocaps = sc->cryptocaps; 2117 o->iscsicaps = sc->iscsicaps; 2118 o->fcoecaps = sc->fcoecaps; 2119 2120 o->cfcsum = sc->cfcsum; 2121 MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file)); 2122 memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file)); 2123 2124 o->params = sc->params; 2125 o->vres = sc->vres; 2126 o->tids = sc->tids; 2127 o->sge = sc->sge; 2128 2129 o->rawf_base = sc->rawf_base; 2130 o->nrawf = sc->nrawf; 2131 } 2132 2133 static int 2134 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2135 { 2136 int rc = 0; 2137 2138 ASSERT_SYNCHRONIZED_OP(sc); 2139 2140 /* Capabilities */ 2141 #define COMPARE_CAPS(c) do { \ 2142 if (o->c##caps != sc->c##caps) { \ 2143 CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \ 2144 sc->c##caps); \ 2145 rc = EINVAL; \ 2146 } \ 2147 } while (0) 2148 COMPARE_CAPS(nbm); 2149 COMPARE_CAPS(link); 2150 COMPARE_CAPS(switch); 2151 COMPARE_CAPS(nic); 2152 COMPARE_CAPS(toe); 2153 COMPARE_CAPS(rdma); 2154 COMPARE_CAPS(crypto); 2155 COMPARE_CAPS(iscsi); 2156 COMPARE_CAPS(fcoe); 2157 #undef COMPARE_CAPS 2158 2159 /* Firmware config file */ 2160 if (o->cfcsum != sc->cfcsum) { 2161 CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file, 2162 o->cfcsum, sc->cfg_file, sc->cfcsum); 2163 rc = EINVAL; 2164 } 2165 2166 #define COMPARE_PARAM(p, name) do { \ 2167 if (o->p != sc->p) { \ 2168 CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \ 2169 rc = EINVAL; \ 2170 } \ 2171 } while (0) 2172 COMPARE_PARAM(sge.iq_start, iq_start); 2173 COMPARE_PARAM(sge.eq_start, eq_start); 2174 COMPARE_PARAM(tids.ftid_base, ftid_base); 2175 COMPARE_PARAM(tids.ftid_end, ftid_end); 2176 COMPARE_PARAM(tids.nftids, nftids); 2177 COMPARE_PARAM(vres.l2t.start, l2t_start); 2178 COMPARE_PARAM(vres.l2t.size, l2t_size); 2179 COMPARE_PARAM(sge.iqmap_sz, iqmap_sz); 2180 COMPARE_PARAM(sge.eqmap_sz, eqmap_sz); 2181 COMPARE_PARAM(tids.tid_base, tid_base); 2182 COMPARE_PARAM(tids.hpftid_base, hpftid_base); 2183 COMPARE_PARAM(tids.hpftid_end, hpftid_end); 2184 COMPARE_PARAM(tids.nhpftids, nhpftids); 2185 COMPARE_PARAM(rawf_base, rawf_base); 2186 COMPARE_PARAM(nrawf, nrawf); 2187 COMPARE_PARAM(params.mps_bg_map, mps_bg_map); 2188 COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support); 2189 COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl); 2190 COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support); 2191 COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr); 2192 COMPARE_PARAM(tids.ntids, ntids); 2193 COMPARE_PARAM(tids.etid_base, etid_base); 2194 COMPARE_PARAM(tids.etid_end, etid_end); 2195 COMPARE_PARAM(tids.netids, netids); 2196 COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred); 2197 COMPARE_PARAM(params.ethoffload, ethoffload); 2198 COMPARE_PARAM(tids.natids, natids); 2199 COMPARE_PARAM(tids.stid_base, stid_base); 2200 COMPARE_PARAM(vres.ddp.start, ddp_start); 2201 COMPARE_PARAM(vres.ddp.size, ddp_size); 2202 COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred); 2203 COMPARE_PARAM(vres.stag.start, stag_start); 2204 COMPARE_PARAM(vres.stag.size, stag_size); 2205 COMPARE_PARAM(vres.rq.start, rq_start); 2206 COMPARE_PARAM(vres.rq.size, rq_size); 2207 COMPARE_PARAM(vres.pbl.start, pbl_start); 2208 COMPARE_PARAM(vres.pbl.size, pbl_size); 2209 COMPARE_PARAM(vres.qp.start, qp_start); 2210 COMPARE_PARAM(vres.qp.size, qp_size); 2211 COMPARE_PARAM(vres.cq.start, cq_start); 2212 COMPARE_PARAM(vres.cq.size, cq_size); 2213 COMPARE_PARAM(vres.ocq.start, ocq_start); 2214 COMPARE_PARAM(vres.ocq.size, ocq_size); 2215 COMPARE_PARAM(vres.srq.start, srq_start); 2216 COMPARE_PARAM(vres.srq.size, srq_size); 2217 COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp); 2218 COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter); 2219 COMPARE_PARAM(vres.iscsi.start, iscsi_start); 2220 COMPARE_PARAM(vres.iscsi.size, iscsi_size); 2221 COMPARE_PARAM(vres.key.start, key_start); 2222 COMPARE_PARAM(vres.key.size, key_size); 2223 #undef COMPARE_PARAM 2224 2225 return (rc); 2226 } 2227 2228 static int 2229 t4_resume(device_t dev) 2230 { 2231 struct adapter *sc = device_get_softc(dev); 2232 struct adapter_pre_reset_state *old_state = NULL; 2233 struct port_info *pi; 2234 struct vi_info *vi; 2235 if_t ifp; 2236 struct sge_txq *txq; 2237 int rc, i, j, k; 2238 2239 CH_ALERT(sc, "resume requested.\n"); 2240 2241 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4res"); 2242 if (rc != 0) 2243 return (ENXIO); 2244 MPASS(hw_off_limits(sc)); 2245 MPASS((sc->flags & FW_OK) == 0); 2246 MPASS((sc->flags & MASTER_PF) == 0); 2247 MPASS(sc->reset_thread == NULL); 2248 sc->reset_thread = curthread; 2249 2250 /* Register access is expected to work by the time we're here. */ 2251 if (t4_read_reg(sc, A_PL_WHOAMI) == 0xffffffff) { 2252 CH_ERR(sc, "%s: can't read device registers\n", __func__); 2253 rc = ENXIO; 2254 goto done; 2255 } 2256 2257 /* Note that HW_OFF_LIMITS is cleared a bit later. */ 2258 atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR | ADAP_STOPPED); 2259 2260 /* Restore memory window. */ 2261 setup_memwin(sc); 2262 2263 /* Go no further if recovery mode has been requested. */ 2264 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 2265 CH_ALERT(sc, "recovery mode on resume.\n"); 2266 rc = 0; 2267 mtx_lock(&sc->reg_lock); 2268 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 2269 mtx_unlock(&sc->reg_lock); 2270 goto done; 2271 } 2272 2273 old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK); 2274 save_caps_and_params(sc, old_state); 2275 2276 /* Reestablish contact with firmware and become the primary PF. */ 2277 rc = contact_firmware(sc); 2278 if (rc != 0) 2279 goto done; /* error message displayed already */ 2280 MPASS(sc->flags & FW_OK); 2281 2282 if (sc->flags & MASTER_PF) { 2283 rc = partition_resources(sc); 2284 if (rc != 0) 2285 goto done; /* error message displayed already */ 2286 t4_intr_clear(sc); 2287 } 2288 2289 rc = get_params__post_init(sc); 2290 if (rc != 0) 2291 goto done; /* error message displayed already */ 2292 2293 rc = set_params__post_init(sc); 2294 if (rc != 0) 2295 goto done; /* error message displayed already */ 2296 2297 rc = compare_caps_and_params(sc, old_state); 2298 if (rc != 0) 2299 goto done; /* error message displayed already */ 2300 2301 for_each_port(sc, i) { 2302 pi = sc->port[i]; 2303 MPASS(pi != NULL); 2304 MPASS(pi->vi != NULL); 2305 MPASS(pi->vi[0].dev == pi->dev); 2306 2307 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 2308 if (rc != 0) { 2309 CH_ERR(sc, 2310 "failed to re-initialize port %d: %d\n", i, rc); 2311 goto done; 2312 } 2313 MPASS(sc->chan_map[pi->tx_chan] == i); 2314 2315 PORT_LOCK(pi); 2316 fixup_link_config(pi); 2317 build_medialist(pi); 2318 PORT_UNLOCK(pi); 2319 for_each_vi(pi, j, vi) { 2320 if (IS_MAIN_VI(vi)) 2321 continue; 2322 rc = alloc_extra_vi(sc, pi, vi); 2323 if (rc != 0) { 2324 CH_ERR(vi, 2325 "failed to re-allocate extra VI: %d\n", rc); 2326 goto done; 2327 } 2328 } 2329 } 2330 2331 /* 2332 * Interrupts and queues are about to be enabled and other threads will 2333 * want to access the hardware too. It is safe to do so. Note that 2334 * this thread is still in the middle of a synchronized_op. 2335 */ 2336 mtx_lock(&sc->reg_lock); 2337 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 2338 mtx_unlock(&sc->reg_lock); 2339 2340 if (sc->flags & FULL_INIT_DONE) { 2341 rc = adapter_full_init(sc); 2342 if (rc != 0) { 2343 CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc); 2344 goto done; 2345 } 2346 2347 if (sc->vxlan_refcount > 0) 2348 enable_vxlan_rx(sc); 2349 2350 for_each_port(sc, i) { 2351 pi = sc->port[i]; 2352 for_each_vi(pi, j, vi) { 2353 mtx_lock(&vi->tick_mtx); 2354 vi->flags &= ~VI_SKIP_STATS; 2355 mtx_unlock(&vi->tick_mtx); 2356 if (!(vi->flags & VI_INIT_DONE)) 2357 continue; 2358 rc = vi_full_init(vi); 2359 if (rc != 0) { 2360 CH_ERR(vi, "failed to re-initialize " 2361 "interface: %d\n", rc); 2362 goto done; 2363 } 2364 2365 ifp = vi->ifp; 2366 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2367 continue; 2368 /* 2369 * Note that we do not setup multicast addresses 2370 * in the first pass. This ensures that the 2371 * unicast DMACs for all VIs on all ports get an 2372 * MPS TCAM entry. 2373 */ 2374 rc = update_mac_settings(ifp, XGMAC_ALL & 2375 ~XGMAC_MCADDRS); 2376 if (rc != 0) { 2377 CH_ERR(vi, "failed to re-configure MAC: %d\n", rc); 2378 goto done; 2379 } 2380 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, 2381 true); 2382 if (rc != 0) { 2383 CH_ERR(vi, "failed to re-enable VI: %d\n", rc); 2384 goto done; 2385 } 2386 for_each_txq(vi, k, txq) { 2387 TXQ_LOCK(txq); 2388 txq->eq.flags |= EQ_ENABLED; 2389 TXQ_UNLOCK(txq); 2390 } 2391 mtx_lock(&vi->tick_mtx); 2392 callout_schedule(&vi->tick, hz); 2393 mtx_unlock(&vi->tick_mtx); 2394 } 2395 PORT_LOCK(pi); 2396 if (pi->up_vis > 0) { 2397 t4_update_port_info(pi); 2398 fixup_link_config(pi); 2399 build_medialist(pi); 2400 apply_link_config(pi); 2401 if (pi->link_cfg.link_ok) 2402 t4_os_link_changed(pi); 2403 } 2404 PORT_UNLOCK(pi); 2405 } 2406 2407 /* Now reprogram the L2 multicast addresses. */ 2408 for_each_port(sc, i) { 2409 pi = sc->port[i]; 2410 for_each_vi(pi, j, vi) { 2411 if (!(vi->flags & VI_INIT_DONE)) 2412 continue; 2413 ifp = vi->ifp; 2414 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2415 continue; 2416 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2417 if (rc != 0) { 2418 CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc); 2419 rc = 0; /* carry on */ 2420 } 2421 } 2422 } 2423 } 2424 2425 /* Reset all calibration */ 2426 t4_calibration_start(sc); 2427 2428 done: 2429 if (rc == 0) { 2430 sc->incarnation++; 2431 CH_ALERT(sc, "resume completed.\n"); 2432 } 2433 end_synchronized_op(sc, 0); 2434 free(old_state, M_CXGBE); 2435 return (rc); 2436 } 2437 2438 static int 2439 t4_reset_prepare(device_t dev, device_t child) 2440 { 2441 struct adapter *sc = device_get_softc(dev); 2442 2443 CH_ALERT(sc, "reset_prepare.\n"); 2444 return (0); 2445 } 2446 2447 static int 2448 t4_reset_post(device_t dev, device_t child) 2449 { 2450 struct adapter *sc = device_get_softc(dev); 2451 2452 CH_ALERT(sc, "reset_post.\n"); 2453 return (0); 2454 } 2455 2456 static int 2457 reset_adapter(struct adapter *sc) 2458 { 2459 int rc, oldinc, error_flags; 2460 2461 CH_ALERT(sc, "reset requested.\n"); 2462 2463 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst1"); 2464 if (rc != 0) 2465 return (EBUSY); 2466 2467 if (hw_off_limits(sc)) { 2468 CH_ERR(sc, "adapter is suspended, use resume (not reset).\n"); 2469 rc = ENXIO; 2470 goto done; 2471 } 2472 2473 if (!ok_to_reset(sc)) { 2474 /* XXX: should list what resource is preventing reset. */ 2475 CH_ERR(sc, "not safe to reset.\n"); 2476 rc = EBUSY; 2477 goto done; 2478 } 2479 2480 done: 2481 oldinc = sc->incarnation; 2482 end_synchronized_op(sc, 0); 2483 if (rc != 0) 2484 return (rc); /* Error logged already. */ 2485 2486 atomic_add_int(&sc->num_resets, 1); 2487 mtx_lock(&Giant); 2488 rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0); 2489 mtx_unlock(&Giant); 2490 if (rc != 0) 2491 CH_ERR(sc, "bus_reset_child failed: %d.\n", rc); 2492 else { 2493 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst2"); 2494 if (rc != 0) 2495 return (EBUSY); 2496 error_flags = atomic_load_int(&sc->error_flags); 2497 if (sc->incarnation > oldinc && error_flags == 0) { 2498 CH_ALERT(sc, "bus_reset_child succeeded.\n"); 2499 } else { 2500 CH_ERR(sc, "adapter did not reset properly, flags " 2501 "0x%08x, error_flags 0x%08x.\n", sc->flags, 2502 error_flags); 2503 rc = ENXIO; 2504 } 2505 end_synchronized_op(sc, 0); 2506 } 2507 2508 return (rc); 2509 } 2510 2511 static void 2512 reset_adapter_task(void *arg, int pending) 2513 { 2514 /* XXX: t4_async_event here? */ 2515 reset_adapter(arg); 2516 } 2517 2518 static int 2519 cxgbe_probe(device_t dev) 2520 { 2521 char buf[128]; 2522 struct port_info *pi = device_get_softc(dev); 2523 2524 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 2525 device_set_desc_copy(dev, buf); 2526 2527 return (BUS_PROBE_DEFAULT); 2528 } 2529 2530 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 2531 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 2532 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 2533 IFCAP_HWRXTSTMP | IFCAP_MEXTPG) 2534 #define T4_CAP_ENABLE (T4_CAP) 2535 2536 static int 2537 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 2538 { 2539 if_t ifp; 2540 struct sbuf *sb; 2541 struct sysctl_ctx_list *ctx = &vi->ctx; 2542 struct sysctl_oid_list *children; 2543 struct pfil_head_args pa; 2544 struct adapter *sc = vi->adapter; 2545 2546 sysctl_ctx_init(ctx); 2547 children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev)); 2548 vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq", 2549 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues"); 2550 vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq", 2551 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues"); 2552 #ifdef DEV_NETMAP 2553 vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq", 2554 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues"); 2555 vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq", 2556 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues"); 2557 #endif 2558 #ifdef TCP_OFFLOAD 2559 vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq", 2560 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues"); 2561 #endif 2562 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2563 vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq", 2564 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues"); 2565 #endif 2566 2567 vi->xact_addr_filt = -1; 2568 mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF); 2569 callout_init_mtx(&vi->tick, &vi->tick_mtx, 0); 2570 if (sc->flags & IS_VF || t4_tx_vm_wr != 0) 2571 vi->flags |= TX_USES_VM_WR; 2572 2573 /* Allocate an ifnet and set it up */ 2574 ifp = if_alloc_dev(IFT_ETHER, dev); 2575 if (ifp == NULL) { 2576 device_printf(dev, "Cannot allocate ifnet\n"); 2577 return (ENOMEM); 2578 } 2579 vi->ifp = ifp; 2580 if_setsoftc(ifp, vi); 2581 2582 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2583 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2584 2585 if_setinitfn(ifp, cxgbe_init); 2586 if_setioctlfn(ifp, cxgbe_ioctl); 2587 if_settransmitfn(ifp, cxgbe_transmit); 2588 if_setqflushfn(ifp, cxgbe_qflush); 2589 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 2590 if_setgetcounterfn(ifp, vi_get_counter); 2591 else 2592 if_setgetcounterfn(ifp, cxgbe_get_counter); 2593 #if defined(KERN_TLS) || defined(RATELIMIT) 2594 if_setsndtagallocfn(ifp, cxgbe_snd_tag_alloc); 2595 #endif 2596 #ifdef RATELIMIT 2597 if_setratelimitqueryfn(ifp, cxgbe_ratelimit_query); 2598 #endif 2599 2600 if_setcapabilities(ifp, T4_CAP); 2601 if_setcapenable(ifp, T4_CAP_ENABLE); 2602 if_sethwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 2603 CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2604 if (chip_id(sc) >= CHELSIO_T6) { 2605 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2606 if_setcapenablebit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2607 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 2608 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2609 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN, 0); 2610 } 2611 2612 #ifdef TCP_OFFLOAD 2613 if (vi->nofldrxq != 0) 2614 if_setcapabilitiesbit(ifp, IFCAP_TOE, 0); 2615 #endif 2616 #ifdef RATELIMIT 2617 if (is_ethoffload(sc) && vi->nofldtxq != 0) { 2618 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0); 2619 if_setcapenablebit(ifp, IFCAP_TXRTLMT, 0); 2620 } 2621 #endif 2622 2623 if_sethwtsomax(ifp, IP_MAXPACKET); 2624 if (vi->flags & TX_USES_VM_WR) 2625 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_VM_TSO); 2626 else 2627 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_TSO); 2628 #ifdef RATELIMIT 2629 if (is_ethoffload(sc) && vi->nofldtxq != 0) 2630 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_EO_TSO); 2631 #endif 2632 if_sethwtsomaxsegsize(ifp, 65536); 2633 #ifdef KERN_TLS 2634 if (is_ktls(sc)) { 2635 if_setcapabilitiesbit(ifp, IFCAP_TXTLS, 0); 2636 if (sc->flags & KERN_TLS_ON || !is_t6(sc)) 2637 if_setcapenablebit(ifp, IFCAP_TXTLS, 0); 2638 } 2639 #endif 2640 2641 ether_ifattach(ifp, vi->hw_addr); 2642 #ifdef DEV_NETMAP 2643 if (vi->nnmrxq != 0) 2644 cxgbe_nm_attach(vi); 2645 #endif 2646 sb = sbuf_new_auto(); 2647 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 2648 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2649 switch (if_getcapabilities(ifp) & (IFCAP_TOE | IFCAP_TXRTLMT)) { 2650 case IFCAP_TOE: 2651 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 2652 break; 2653 case IFCAP_TOE | IFCAP_TXRTLMT: 2654 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 2655 break; 2656 case IFCAP_TXRTLMT: 2657 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 2658 break; 2659 } 2660 #endif 2661 #ifdef TCP_OFFLOAD 2662 if (if_getcapabilities(ifp) & IFCAP_TOE) 2663 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 2664 #endif 2665 #ifdef DEV_NETMAP 2666 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2667 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 2668 vi->nnmtxq, vi->nnmrxq); 2669 #endif 2670 sbuf_finish(sb); 2671 device_printf(dev, "%s\n", sbuf_data(sb)); 2672 sbuf_delete(sb); 2673 2674 vi_sysctls(vi); 2675 2676 pa.pa_version = PFIL_VERSION; 2677 pa.pa_flags = PFIL_IN; 2678 pa.pa_type = PFIL_TYPE_ETHERNET; 2679 pa.pa_headname = if_name(ifp); 2680 vi->pfil = pfil_head_register(&pa); 2681 2682 return (0); 2683 } 2684 2685 static int 2686 cxgbe_attach(device_t dev) 2687 { 2688 struct port_info *pi = device_get_softc(dev); 2689 struct adapter *sc = pi->adapter; 2690 struct vi_info *vi; 2691 int i, rc; 2692 2693 sysctl_ctx_init(&pi->ctx); 2694 2695 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 2696 if (rc) 2697 return (rc); 2698 2699 for_each_vi(pi, i, vi) { 2700 if (i == 0) 2701 continue; 2702 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 2703 if (vi->dev == NULL) { 2704 device_printf(dev, "failed to add VI %d\n", i); 2705 continue; 2706 } 2707 device_set_softc(vi->dev, vi); 2708 } 2709 2710 cxgbe_sysctls(pi); 2711 2712 bus_generic_attach(dev); 2713 2714 return (0); 2715 } 2716 2717 static void 2718 cxgbe_vi_detach(struct vi_info *vi) 2719 { 2720 if_t ifp = vi->ifp; 2721 2722 if (vi->pfil != NULL) { 2723 pfil_head_unregister(vi->pfil); 2724 vi->pfil = NULL; 2725 } 2726 2727 ether_ifdetach(ifp); 2728 2729 /* Let detach proceed even if these fail. */ 2730 #ifdef DEV_NETMAP 2731 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2732 cxgbe_nm_detach(vi); 2733 #endif 2734 cxgbe_uninit_synchronized(vi); 2735 callout_drain(&vi->tick); 2736 mtx_destroy(&vi->tick_mtx); 2737 sysctl_ctx_free(&vi->ctx); 2738 vi_full_uninit(vi); 2739 2740 if_free(vi->ifp); 2741 vi->ifp = NULL; 2742 } 2743 2744 static int 2745 cxgbe_detach(device_t dev) 2746 { 2747 struct port_info *pi = device_get_softc(dev); 2748 struct adapter *sc = pi->adapter; 2749 int rc; 2750 2751 /* Detach the extra VIs first. */ 2752 rc = bus_generic_detach(dev); 2753 if (rc) 2754 return (rc); 2755 device_delete_children(dev); 2756 2757 sysctl_ctx_free(&pi->ctx); 2758 begin_vi_detach(sc, &pi->vi[0]); 2759 if (pi->flags & HAS_TRACEQ) { 2760 sc->traceq = -1; /* cloner should not create ifnet */ 2761 t4_tracer_port_detach(sc); 2762 } 2763 cxgbe_vi_detach(&pi->vi[0]); 2764 ifmedia_removeall(&pi->media); 2765 end_vi_detach(sc, &pi->vi[0]); 2766 2767 return (0); 2768 } 2769 2770 static void 2771 cxgbe_init(void *arg) 2772 { 2773 struct vi_info *vi = arg; 2774 struct adapter *sc = vi->adapter; 2775 2776 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 2777 return; 2778 cxgbe_init_synchronized(vi); 2779 end_synchronized_op(sc, 0); 2780 } 2781 2782 static int 2783 cxgbe_ioctl(if_t ifp, unsigned long cmd, caddr_t data) 2784 { 2785 int rc = 0, mtu, flags; 2786 struct vi_info *vi = if_getsoftc(ifp); 2787 struct port_info *pi = vi->pi; 2788 struct adapter *sc = pi->adapter; 2789 struct ifreq *ifr = (struct ifreq *)data; 2790 uint32_t mask; 2791 2792 switch (cmd) { 2793 case SIOCSIFMTU: 2794 mtu = ifr->ifr_mtu; 2795 if (mtu < ETHERMIN || mtu > MAX_MTU) 2796 return (EINVAL); 2797 2798 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 2799 if (rc) 2800 return (rc); 2801 if_setmtu(ifp, mtu); 2802 if (vi->flags & VI_INIT_DONE) { 2803 t4_update_fl_bufsize(ifp); 2804 if (!hw_off_limits(sc) && 2805 if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2806 rc = update_mac_settings(ifp, XGMAC_MTU); 2807 } 2808 end_synchronized_op(sc, 0); 2809 break; 2810 2811 case SIOCSIFFLAGS: 2812 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 2813 if (rc) 2814 return (rc); 2815 2816 if (hw_off_limits(sc)) { 2817 rc = ENXIO; 2818 goto fail; 2819 } 2820 2821 if (if_getflags(ifp) & IFF_UP) { 2822 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2823 flags = vi->if_flags; 2824 if ((if_getflags(ifp) ^ flags) & 2825 (IFF_PROMISC | IFF_ALLMULTI)) { 2826 rc = update_mac_settings(ifp, 2827 XGMAC_PROMISC | XGMAC_ALLMULTI); 2828 } 2829 } else { 2830 rc = cxgbe_init_synchronized(vi); 2831 } 2832 vi->if_flags = if_getflags(ifp); 2833 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2834 rc = cxgbe_uninit_synchronized(vi); 2835 } 2836 end_synchronized_op(sc, 0); 2837 break; 2838 2839 case SIOCADDMULTI: 2840 case SIOCDELMULTI: 2841 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 2842 if (rc) 2843 return (rc); 2844 if (!hw_off_limits(sc) && if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2845 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2846 end_synchronized_op(sc, 0); 2847 break; 2848 2849 case SIOCSIFCAP: 2850 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 2851 if (rc) 2852 return (rc); 2853 2854 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2855 if (mask & IFCAP_TXCSUM) { 2856 if_togglecapenable(ifp, IFCAP_TXCSUM); 2857 if_togglehwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP); 2858 2859 if (IFCAP_TSO4 & if_getcapenable(ifp) && 2860 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2861 mask &= ~IFCAP_TSO4; 2862 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 2863 if_printf(ifp, 2864 "tso4 disabled due to -txcsum.\n"); 2865 } 2866 } 2867 if (mask & IFCAP_TXCSUM_IPV6) { 2868 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 2869 if_togglehwassist(ifp, CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2870 2871 if (IFCAP_TSO6 & if_getcapenable(ifp) && 2872 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2873 mask &= ~IFCAP_TSO6; 2874 if_setcapenablebit(ifp, 0, IFCAP_TSO6); 2875 if_printf(ifp, 2876 "tso6 disabled due to -txcsum6.\n"); 2877 } 2878 } 2879 if (mask & IFCAP_RXCSUM) 2880 if_togglecapenable(ifp, IFCAP_RXCSUM); 2881 if (mask & IFCAP_RXCSUM_IPV6) 2882 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 2883 2884 /* 2885 * Note that we leave CSUM_TSO alone (it is always set). The 2886 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 2887 * sending a TSO request our way, so it's sufficient to toggle 2888 * IFCAP_TSOx only. 2889 */ 2890 if (mask & IFCAP_TSO4) { 2891 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) && 2892 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2893 if_printf(ifp, "enable txcsum first.\n"); 2894 rc = EAGAIN; 2895 goto fail; 2896 } 2897 if_togglecapenable(ifp, IFCAP_TSO4); 2898 } 2899 if (mask & IFCAP_TSO6) { 2900 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) && 2901 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2902 if_printf(ifp, "enable txcsum6 first.\n"); 2903 rc = EAGAIN; 2904 goto fail; 2905 } 2906 if_togglecapenable(ifp, IFCAP_TSO6); 2907 } 2908 if (mask & IFCAP_LRO) { 2909 #if defined(INET) || defined(INET6) 2910 int i; 2911 struct sge_rxq *rxq; 2912 2913 if_togglecapenable(ifp, IFCAP_LRO); 2914 for_each_rxq(vi, i, rxq) { 2915 if (if_getcapenable(ifp) & IFCAP_LRO) 2916 rxq->iq.flags |= IQ_LRO_ENABLED; 2917 else 2918 rxq->iq.flags &= ~IQ_LRO_ENABLED; 2919 } 2920 #endif 2921 } 2922 #ifdef TCP_OFFLOAD 2923 if (mask & IFCAP_TOE) { 2924 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TOE; 2925 2926 rc = toe_capability(vi, enable); 2927 if (rc != 0) 2928 goto fail; 2929 2930 if_togglecapenable(ifp, mask); 2931 } 2932 #endif 2933 if (mask & IFCAP_VLAN_HWTAGGING) { 2934 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2935 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2936 rc = update_mac_settings(ifp, XGMAC_VLANEX); 2937 } 2938 if (mask & IFCAP_VLAN_MTU) { 2939 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 2940 2941 /* Need to find out how to disable auto-mtu-inflation */ 2942 } 2943 if (mask & IFCAP_VLAN_HWTSO) 2944 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2945 if (mask & IFCAP_VLAN_HWCSUM) 2946 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2947 #ifdef RATELIMIT 2948 if (mask & IFCAP_TXRTLMT) 2949 if_togglecapenable(ifp, IFCAP_TXRTLMT); 2950 #endif 2951 if (mask & IFCAP_HWRXTSTMP) { 2952 int i; 2953 struct sge_rxq *rxq; 2954 2955 if_togglecapenable(ifp, IFCAP_HWRXTSTMP); 2956 for_each_rxq(vi, i, rxq) { 2957 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) 2958 rxq->iq.flags |= IQ_RX_TIMESTAMP; 2959 else 2960 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 2961 } 2962 } 2963 if (mask & IFCAP_MEXTPG) 2964 if_togglecapenable(ifp, IFCAP_MEXTPG); 2965 2966 #ifdef KERN_TLS 2967 if (mask & IFCAP_TXTLS) { 2968 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TXTLS; 2969 2970 rc = ktls_capability(sc, enable); 2971 if (rc != 0) 2972 goto fail; 2973 2974 if_togglecapenable(ifp, mask & IFCAP_TXTLS); 2975 } 2976 #endif 2977 if (mask & IFCAP_VXLAN_HWCSUM) { 2978 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM); 2979 if_togglehwassist(ifp, CSUM_INNER_IP6_UDP | 2980 CSUM_INNER_IP6_TCP | CSUM_INNER_IP | 2981 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP); 2982 } 2983 if (mask & IFCAP_VXLAN_HWTSO) { 2984 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO); 2985 if_togglehwassist(ifp, CSUM_INNER_IP6_TSO | 2986 CSUM_INNER_IP_TSO); 2987 } 2988 2989 #ifdef VLAN_CAPABILITIES 2990 VLAN_CAPABILITIES(ifp); 2991 #endif 2992 fail: 2993 end_synchronized_op(sc, 0); 2994 break; 2995 2996 case SIOCSIFMEDIA: 2997 case SIOCGIFMEDIA: 2998 case SIOCGIFXMEDIA: 2999 rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 3000 break; 3001 3002 case SIOCGI2C: { 3003 struct ifi2creq i2c; 3004 3005 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3006 if (rc != 0) 3007 break; 3008 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3009 rc = EPERM; 3010 break; 3011 } 3012 if (i2c.len > sizeof(i2c.data)) { 3013 rc = EINVAL; 3014 break; 3015 } 3016 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 3017 if (rc) 3018 return (rc); 3019 if (hw_off_limits(sc)) 3020 rc = ENXIO; 3021 else 3022 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 3023 i2c.offset, i2c.len, &i2c.data[0]); 3024 end_synchronized_op(sc, 0); 3025 if (rc == 0) 3026 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3027 break; 3028 } 3029 3030 default: 3031 rc = ether_ioctl(ifp, cmd, data); 3032 } 3033 3034 return (rc); 3035 } 3036 3037 static int 3038 cxgbe_transmit(if_t ifp, struct mbuf *m) 3039 { 3040 struct vi_info *vi = if_getsoftc(ifp); 3041 struct port_info *pi = vi->pi; 3042 struct adapter *sc; 3043 struct sge_txq *txq; 3044 void *items[1]; 3045 int rc; 3046 3047 M_ASSERTPKTHDR(m); 3048 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 3049 #if defined(KERN_TLS) || defined(RATELIMIT) 3050 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) 3051 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 3052 #endif 3053 3054 if (__predict_false(pi->link_cfg.link_ok == false)) { 3055 m_freem(m); 3056 return (ENETDOWN); 3057 } 3058 3059 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR); 3060 if (__predict_false(rc != 0)) { 3061 if (__predict_true(rc == EINPROGRESS)) { 3062 /* queued by parse_pkt */ 3063 MPASS(m != NULL); 3064 return (0); 3065 } 3066 3067 MPASS(m == NULL); /* was freed already */ 3068 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 3069 return (rc); 3070 } 3071 3072 /* Select a txq. */ 3073 sc = vi->adapter; 3074 txq = &sc->sge.txq[vi->first_txq]; 3075 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 3076 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 3077 vi->rsrv_noflowq); 3078 3079 items[0] = m; 3080 rc = mp_ring_enqueue(txq->r, items, 1, 256); 3081 if (__predict_false(rc != 0)) 3082 m_freem(m); 3083 3084 return (rc); 3085 } 3086 3087 static void 3088 cxgbe_qflush(if_t ifp) 3089 { 3090 struct vi_info *vi = if_getsoftc(ifp); 3091 struct sge_txq *txq; 3092 int i; 3093 3094 /* queues do not exist if !VI_INIT_DONE. */ 3095 if (vi->flags & VI_INIT_DONE) { 3096 for_each_txq(vi, i, txq) { 3097 TXQ_LOCK(txq); 3098 txq->eq.flags |= EQ_QFLUSH; 3099 TXQ_UNLOCK(txq); 3100 while (!mp_ring_is_idle(txq->r)) { 3101 mp_ring_check_drainage(txq->r, 4096); 3102 pause("qflush", 1); 3103 } 3104 TXQ_LOCK(txq); 3105 txq->eq.flags &= ~EQ_QFLUSH; 3106 TXQ_UNLOCK(txq); 3107 } 3108 } 3109 if_qflush(ifp); 3110 } 3111 3112 static uint64_t 3113 vi_get_counter(if_t ifp, ift_counter c) 3114 { 3115 struct vi_info *vi = if_getsoftc(ifp); 3116 struct fw_vi_stats_vf *s = &vi->stats; 3117 3118 mtx_lock(&vi->tick_mtx); 3119 vi_refresh_stats(vi); 3120 mtx_unlock(&vi->tick_mtx); 3121 3122 switch (c) { 3123 case IFCOUNTER_IPACKETS: 3124 return (s->rx_bcast_frames + s->rx_mcast_frames + 3125 s->rx_ucast_frames); 3126 case IFCOUNTER_IERRORS: 3127 return (s->rx_err_frames); 3128 case IFCOUNTER_OPACKETS: 3129 return (s->tx_bcast_frames + s->tx_mcast_frames + 3130 s->tx_ucast_frames + s->tx_offload_frames); 3131 case IFCOUNTER_OERRORS: 3132 return (s->tx_drop_frames); 3133 case IFCOUNTER_IBYTES: 3134 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 3135 s->rx_ucast_bytes); 3136 case IFCOUNTER_OBYTES: 3137 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 3138 s->tx_ucast_bytes + s->tx_offload_bytes); 3139 case IFCOUNTER_IMCASTS: 3140 return (s->rx_mcast_frames); 3141 case IFCOUNTER_OMCASTS: 3142 return (s->tx_mcast_frames); 3143 case IFCOUNTER_OQDROPS: { 3144 uint64_t drops; 3145 3146 drops = 0; 3147 if (vi->flags & VI_INIT_DONE) { 3148 int i; 3149 struct sge_txq *txq; 3150 3151 for_each_txq(vi, i, txq) 3152 drops += counter_u64_fetch(txq->r->dropped); 3153 } 3154 3155 return (drops); 3156 3157 } 3158 3159 default: 3160 return (if_get_counter_default(ifp, c)); 3161 } 3162 } 3163 3164 static uint64_t 3165 cxgbe_get_counter(if_t ifp, ift_counter c) 3166 { 3167 struct vi_info *vi = if_getsoftc(ifp); 3168 struct port_info *pi = vi->pi; 3169 struct port_stats *s = &pi->stats; 3170 3171 mtx_lock(&vi->tick_mtx); 3172 cxgbe_refresh_stats(vi); 3173 mtx_unlock(&vi->tick_mtx); 3174 3175 switch (c) { 3176 case IFCOUNTER_IPACKETS: 3177 return (s->rx_frames); 3178 3179 case IFCOUNTER_IERRORS: 3180 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 3181 s->rx_fcs_err + s->rx_len_err); 3182 3183 case IFCOUNTER_OPACKETS: 3184 return (s->tx_frames); 3185 3186 case IFCOUNTER_OERRORS: 3187 return (s->tx_error_frames); 3188 3189 case IFCOUNTER_IBYTES: 3190 return (s->rx_octets); 3191 3192 case IFCOUNTER_OBYTES: 3193 return (s->tx_octets); 3194 3195 case IFCOUNTER_IMCASTS: 3196 return (s->rx_mcast_frames); 3197 3198 case IFCOUNTER_OMCASTS: 3199 return (s->tx_mcast_frames); 3200 3201 case IFCOUNTER_IQDROPS: 3202 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 3203 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 3204 s->rx_trunc3 + pi->tnl_cong_drops); 3205 3206 case IFCOUNTER_OQDROPS: { 3207 uint64_t drops; 3208 3209 drops = s->tx_drop; 3210 if (vi->flags & VI_INIT_DONE) { 3211 int i; 3212 struct sge_txq *txq; 3213 3214 for_each_txq(vi, i, txq) 3215 drops += counter_u64_fetch(txq->r->dropped); 3216 } 3217 3218 return (drops); 3219 3220 } 3221 3222 default: 3223 return (if_get_counter_default(ifp, c)); 3224 } 3225 } 3226 3227 #if defined(KERN_TLS) || defined(RATELIMIT) 3228 static int 3229 cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params, 3230 struct m_snd_tag **pt) 3231 { 3232 int error; 3233 3234 switch (params->hdr.type) { 3235 #ifdef RATELIMIT 3236 case IF_SND_TAG_TYPE_RATE_LIMIT: 3237 error = cxgbe_rate_tag_alloc(ifp, params, pt); 3238 break; 3239 #endif 3240 #ifdef KERN_TLS 3241 case IF_SND_TAG_TYPE_TLS: 3242 { 3243 struct vi_info *vi = if_getsoftc(ifp); 3244 3245 if (is_t6(vi->pi->adapter)) 3246 error = t6_tls_tag_alloc(ifp, params, pt); 3247 else 3248 error = EOPNOTSUPP; 3249 break; 3250 } 3251 #endif 3252 default: 3253 error = EOPNOTSUPP; 3254 } 3255 return (error); 3256 } 3257 #endif 3258 3259 /* 3260 * The kernel picks a media from the list we had provided but we still validate 3261 * the requeste. 3262 */ 3263 int 3264 cxgbe_media_change(if_t ifp) 3265 { 3266 struct vi_info *vi = if_getsoftc(ifp); 3267 struct port_info *pi = vi->pi; 3268 struct ifmedia *ifm = &pi->media; 3269 struct link_config *lc = &pi->link_cfg; 3270 struct adapter *sc = pi->adapter; 3271 int rc; 3272 3273 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 3274 if (rc != 0) 3275 return (rc); 3276 PORT_LOCK(pi); 3277 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 3278 /* ifconfig .. media autoselect */ 3279 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { 3280 rc = ENOTSUP; /* AN not supported by transceiver */ 3281 goto done; 3282 } 3283 lc->requested_aneg = AUTONEG_ENABLE; 3284 lc->requested_speed = 0; 3285 lc->requested_fc |= PAUSE_AUTONEG; 3286 } else { 3287 lc->requested_aneg = AUTONEG_DISABLE; 3288 lc->requested_speed = 3289 ifmedia_baudrate(ifm->ifm_media) / 1000000; 3290 lc->requested_fc = 0; 3291 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 3292 lc->requested_fc |= PAUSE_RX; 3293 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 3294 lc->requested_fc |= PAUSE_TX; 3295 } 3296 if (pi->up_vis > 0 && !hw_off_limits(sc)) { 3297 fixup_link_config(pi); 3298 rc = apply_link_config(pi); 3299 } 3300 done: 3301 PORT_UNLOCK(pi); 3302 end_synchronized_op(sc, 0); 3303 return (rc); 3304 } 3305 3306 /* 3307 * Base media word (without ETHER, pause, link active, etc.) for the port at the 3308 * given speed. 3309 */ 3310 static int 3311 port_mword(struct port_info *pi, uint32_t speed) 3312 { 3313 3314 MPASS(speed & M_FW_PORT_CAP32_SPEED); 3315 MPASS(powerof2(speed)); 3316 3317 switch(pi->port_type) { 3318 case FW_PORT_TYPE_BT_SGMII: 3319 case FW_PORT_TYPE_BT_XFI: 3320 case FW_PORT_TYPE_BT_XAUI: 3321 /* BaseT */ 3322 switch (speed) { 3323 case FW_PORT_CAP32_SPEED_100M: 3324 return (IFM_100_T); 3325 case FW_PORT_CAP32_SPEED_1G: 3326 return (IFM_1000_T); 3327 case FW_PORT_CAP32_SPEED_10G: 3328 return (IFM_10G_T); 3329 } 3330 break; 3331 case FW_PORT_TYPE_KX4: 3332 if (speed == FW_PORT_CAP32_SPEED_10G) 3333 return (IFM_10G_KX4); 3334 break; 3335 case FW_PORT_TYPE_CX4: 3336 if (speed == FW_PORT_CAP32_SPEED_10G) 3337 return (IFM_10G_CX4); 3338 break; 3339 case FW_PORT_TYPE_KX: 3340 if (speed == FW_PORT_CAP32_SPEED_1G) 3341 return (IFM_1000_KX); 3342 break; 3343 case FW_PORT_TYPE_KR: 3344 case FW_PORT_TYPE_BP_AP: 3345 case FW_PORT_TYPE_BP4_AP: 3346 case FW_PORT_TYPE_BP40_BA: 3347 case FW_PORT_TYPE_KR4_100G: 3348 case FW_PORT_TYPE_KR_SFP28: 3349 case FW_PORT_TYPE_KR_XLAUI: 3350 switch (speed) { 3351 case FW_PORT_CAP32_SPEED_1G: 3352 return (IFM_1000_KX); 3353 case FW_PORT_CAP32_SPEED_10G: 3354 return (IFM_10G_KR); 3355 case FW_PORT_CAP32_SPEED_25G: 3356 return (IFM_25G_KR); 3357 case FW_PORT_CAP32_SPEED_40G: 3358 return (IFM_40G_KR4); 3359 case FW_PORT_CAP32_SPEED_50G: 3360 return (IFM_50G_KR2); 3361 case FW_PORT_CAP32_SPEED_100G: 3362 return (IFM_100G_KR4); 3363 } 3364 break; 3365 case FW_PORT_TYPE_FIBER_XFI: 3366 case FW_PORT_TYPE_FIBER_XAUI: 3367 case FW_PORT_TYPE_SFP: 3368 case FW_PORT_TYPE_QSFP_10G: 3369 case FW_PORT_TYPE_QSA: 3370 case FW_PORT_TYPE_QSFP: 3371 case FW_PORT_TYPE_CR4_QSFP: 3372 case FW_PORT_TYPE_CR_QSFP: 3373 case FW_PORT_TYPE_CR2_QSFP: 3374 case FW_PORT_TYPE_SFP28: 3375 /* Pluggable transceiver */ 3376 switch (pi->mod_type) { 3377 case FW_PORT_MOD_TYPE_LR: 3378 switch (speed) { 3379 case FW_PORT_CAP32_SPEED_1G: 3380 return (IFM_1000_LX); 3381 case FW_PORT_CAP32_SPEED_10G: 3382 return (IFM_10G_LR); 3383 case FW_PORT_CAP32_SPEED_25G: 3384 return (IFM_25G_LR); 3385 case FW_PORT_CAP32_SPEED_40G: 3386 return (IFM_40G_LR4); 3387 case FW_PORT_CAP32_SPEED_50G: 3388 return (IFM_50G_LR2); 3389 case FW_PORT_CAP32_SPEED_100G: 3390 return (IFM_100G_LR4); 3391 } 3392 break; 3393 case FW_PORT_MOD_TYPE_SR: 3394 switch (speed) { 3395 case FW_PORT_CAP32_SPEED_1G: 3396 return (IFM_1000_SX); 3397 case FW_PORT_CAP32_SPEED_10G: 3398 return (IFM_10G_SR); 3399 case FW_PORT_CAP32_SPEED_25G: 3400 return (IFM_25G_SR); 3401 case FW_PORT_CAP32_SPEED_40G: 3402 return (IFM_40G_SR4); 3403 case FW_PORT_CAP32_SPEED_50G: 3404 return (IFM_50G_SR2); 3405 case FW_PORT_CAP32_SPEED_100G: 3406 return (IFM_100G_SR4); 3407 } 3408 break; 3409 case FW_PORT_MOD_TYPE_ER: 3410 if (speed == FW_PORT_CAP32_SPEED_10G) 3411 return (IFM_10G_ER); 3412 break; 3413 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3414 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3415 switch (speed) { 3416 case FW_PORT_CAP32_SPEED_1G: 3417 return (IFM_1000_CX); 3418 case FW_PORT_CAP32_SPEED_10G: 3419 return (IFM_10G_TWINAX); 3420 case FW_PORT_CAP32_SPEED_25G: 3421 return (IFM_25G_CR); 3422 case FW_PORT_CAP32_SPEED_40G: 3423 return (IFM_40G_CR4); 3424 case FW_PORT_CAP32_SPEED_50G: 3425 return (IFM_50G_CR2); 3426 case FW_PORT_CAP32_SPEED_100G: 3427 return (IFM_100G_CR4); 3428 } 3429 break; 3430 case FW_PORT_MOD_TYPE_LRM: 3431 if (speed == FW_PORT_CAP32_SPEED_10G) 3432 return (IFM_10G_LRM); 3433 break; 3434 case FW_PORT_MOD_TYPE_NA: 3435 MPASS(0); /* Not pluggable? */ 3436 /* fall throough */ 3437 case FW_PORT_MOD_TYPE_ERROR: 3438 case FW_PORT_MOD_TYPE_UNKNOWN: 3439 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 3440 break; 3441 case FW_PORT_MOD_TYPE_NONE: 3442 return (IFM_NONE); 3443 } 3444 break; 3445 case FW_PORT_TYPE_NONE: 3446 return (IFM_NONE); 3447 } 3448 3449 return (IFM_UNKNOWN); 3450 } 3451 3452 void 3453 cxgbe_media_status(if_t ifp, struct ifmediareq *ifmr) 3454 { 3455 struct vi_info *vi = if_getsoftc(ifp); 3456 struct port_info *pi = vi->pi; 3457 struct adapter *sc = pi->adapter; 3458 struct link_config *lc = &pi->link_cfg; 3459 3460 if (begin_synchronized_op(sc, vi , SLEEP_OK | INTR_OK, "t4med") != 0) 3461 return; 3462 PORT_LOCK(pi); 3463 3464 if (pi->up_vis == 0 && !hw_off_limits(sc)) { 3465 /* 3466 * If all the interfaces are administratively down the firmware 3467 * does not report transceiver changes. Refresh port info here 3468 * so that ifconfig displays accurate ifmedia at all times. 3469 * This is the only reason we have a synchronized op in this 3470 * function. Just PORT_LOCK would have been enough otherwise. 3471 */ 3472 t4_update_port_info(pi); 3473 build_medialist(pi); 3474 } 3475 3476 /* ifm_status */ 3477 ifmr->ifm_status = IFM_AVALID; 3478 if (lc->link_ok == false) 3479 goto done; 3480 ifmr->ifm_status |= IFM_ACTIVE; 3481 3482 /* ifm_active */ 3483 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 3484 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 3485 if (lc->fc & PAUSE_RX) 3486 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3487 if (lc->fc & PAUSE_TX) 3488 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3489 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 3490 done: 3491 PORT_UNLOCK(pi); 3492 end_synchronized_op(sc, 0); 3493 } 3494 3495 static int 3496 vcxgbe_probe(device_t dev) 3497 { 3498 char buf[128]; 3499 struct vi_info *vi = device_get_softc(dev); 3500 3501 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 3502 vi - vi->pi->vi); 3503 device_set_desc_copy(dev, buf); 3504 3505 return (BUS_PROBE_DEFAULT); 3506 } 3507 3508 static int 3509 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 3510 { 3511 int func, index, rc; 3512 uint32_t param, val; 3513 3514 ASSERT_SYNCHRONIZED_OP(sc); 3515 3516 index = vi - pi->vi; 3517 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 3518 KASSERT(index < nitems(vi_mac_funcs), 3519 ("%s: VI %s doesn't have a MAC func", __func__, 3520 device_get_nameunit(vi->dev))); 3521 func = vi_mac_funcs[index]; 3522 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 3523 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 3524 if (rc < 0) { 3525 CH_ERR(vi, "failed to allocate virtual interface %d" 3526 "for port %d: %d\n", index, pi->port_id, -rc); 3527 return (-rc); 3528 } 3529 vi->viid = rc; 3530 3531 if (vi->rss_size == 1) { 3532 /* 3533 * This VI didn't get a slice of the RSS table. Reduce the 3534 * number of VIs being created (hw.cxgbe.num_vis) or modify the 3535 * configuration file (nvi, rssnvi for this PF) if this is a 3536 * problem. 3537 */ 3538 device_printf(vi->dev, "RSS table not available.\n"); 3539 vi->rss_base = 0xffff; 3540 3541 return (0); 3542 } 3543 3544 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3545 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 3546 V_FW_PARAMS_PARAM_YZ(vi->viid); 3547 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3548 if (rc) 3549 vi->rss_base = 0xffff; 3550 else { 3551 MPASS((val >> 16) == vi->rss_size); 3552 vi->rss_base = val & 0xffff; 3553 } 3554 3555 return (0); 3556 } 3557 3558 static int 3559 vcxgbe_attach(device_t dev) 3560 { 3561 struct vi_info *vi; 3562 struct port_info *pi; 3563 struct adapter *sc; 3564 int rc; 3565 3566 vi = device_get_softc(dev); 3567 pi = vi->pi; 3568 sc = pi->adapter; 3569 3570 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 3571 if (rc) 3572 return (rc); 3573 rc = alloc_extra_vi(sc, pi, vi); 3574 end_synchronized_op(sc, 0); 3575 if (rc) 3576 return (rc); 3577 3578 rc = cxgbe_vi_attach(dev, vi); 3579 if (rc) { 3580 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3581 return (rc); 3582 } 3583 return (0); 3584 } 3585 3586 static int 3587 vcxgbe_detach(device_t dev) 3588 { 3589 struct vi_info *vi; 3590 struct adapter *sc; 3591 3592 vi = device_get_softc(dev); 3593 sc = vi->adapter; 3594 3595 begin_vi_detach(sc, vi); 3596 cxgbe_vi_detach(vi); 3597 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3598 end_vi_detach(sc, vi); 3599 3600 return (0); 3601 } 3602 3603 static struct callout fatal_callout; 3604 static struct taskqueue *reset_tq; 3605 3606 static void 3607 delayed_panic(void *arg) 3608 { 3609 struct adapter *sc = arg; 3610 3611 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 3612 } 3613 3614 static void 3615 fatal_error_task(void *arg, int pending) 3616 { 3617 struct adapter *sc = arg; 3618 int rc; 3619 3620 #ifdef TCP_OFFLOAD 3621 t4_async_event(sc); 3622 #endif 3623 if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) { 3624 dump_cim_regs(sc); 3625 dump_cimla(sc); 3626 dump_devlog(sc); 3627 } 3628 3629 if (t4_reset_on_fatal_err) { 3630 CH_ALERT(sc, "resetting on fatal error.\n"); 3631 rc = reset_adapter(sc); 3632 if (rc == 0 && t4_panic_on_fatal_err) { 3633 CH_ALERT(sc, "reset was successful, " 3634 "system will NOT panic.\n"); 3635 return; 3636 } 3637 } 3638 3639 if (t4_panic_on_fatal_err) { 3640 CH_ALERT(sc, "panicking on fatal error (after 30s).\n"); 3641 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 3642 } 3643 } 3644 3645 void 3646 t4_fatal_err(struct adapter *sc, bool fw_error) 3647 { 3648 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 3649 3650 stop_adapter(sc); 3651 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR))) 3652 return; 3653 if (fw_error) { 3654 /* 3655 * We are here because of a firmware error/timeout and not 3656 * because of a hardware interrupt. It is possible (although 3657 * not very likely) that an error interrupt was also raised but 3658 * this thread ran first and inhibited t4_intr_err. We walk the 3659 * main INT_CAUSE registers here to make sure we haven't missed 3660 * anything interesting. 3661 */ 3662 t4_slow_intr_handler(sc, verbose); 3663 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 3664 } 3665 t4_report_fw_error(sc); 3666 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n", 3667 device_get_nameunit(sc->dev), fw_error); 3668 taskqueue_enqueue(reset_tq, &sc->fatal_error_task); 3669 } 3670 3671 void 3672 t4_add_adapter(struct adapter *sc) 3673 { 3674 sx_xlock(&t4_list_lock); 3675 SLIST_INSERT_HEAD(&t4_list, sc, link); 3676 sx_xunlock(&t4_list_lock); 3677 } 3678 3679 int 3680 t4_map_bars_0_and_4(struct adapter *sc) 3681 { 3682 sc->regs_rid = PCIR_BAR(0); 3683 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3684 &sc->regs_rid, RF_ACTIVE); 3685 if (sc->regs_res == NULL) { 3686 device_printf(sc->dev, "cannot map registers.\n"); 3687 return (ENXIO); 3688 } 3689 sc->bt = rman_get_bustag(sc->regs_res); 3690 sc->bh = rman_get_bushandle(sc->regs_res); 3691 sc->mmio_len = rman_get_size(sc->regs_res); 3692 setbit(&sc->doorbells, DOORBELL_KDB); 3693 3694 sc->msix_rid = PCIR_BAR(4); 3695 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3696 &sc->msix_rid, RF_ACTIVE); 3697 if (sc->msix_res == NULL) { 3698 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 3699 return (ENXIO); 3700 } 3701 3702 return (0); 3703 } 3704 3705 int 3706 t4_map_bar_2(struct adapter *sc) 3707 { 3708 3709 /* 3710 * T4: only iWARP driver uses the userspace doorbells. There is no need 3711 * to map it if RDMA is disabled. 3712 */ 3713 if (is_t4(sc) && sc->rdmacaps == 0) 3714 return (0); 3715 3716 sc->udbs_rid = PCIR_BAR(2); 3717 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3718 &sc->udbs_rid, RF_ACTIVE); 3719 if (sc->udbs_res == NULL) { 3720 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 3721 return (ENXIO); 3722 } 3723 sc->udbs_base = rman_get_virtual(sc->udbs_res); 3724 3725 if (chip_id(sc) >= CHELSIO_T5) { 3726 setbit(&sc->doorbells, DOORBELL_UDB); 3727 #if defined(__i386__) || defined(__amd64__) 3728 if (t5_write_combine) { 3729 int rc, mode; 3730 3731 /* 3732 * Enable write combining on BAR2. This is the 3733 * userspace doorbell BAR and is split into 128B 3734 * (UDBS_SEG_SIZE) doorbell regions, each associated 3735 * with an egress queue. The first 64B has the doorbell 3736 * and the second 64B can be used to submit a tx work 3737 * request with an implicit doorbell. 3738 */ 3739 3740 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 3741 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 3742 if (rc == 0) { 3743 clrbit(&sc->doorbells, DOORBELL_UDB); 3744 setbit(&sc->doorbells, DOORBELL_WCWR); 3745 setbit(&sc->doorbells, DOORBELL_UDBWC); 3746 } else { 3747 device_printf(sc->dev, 3748 "couldn't enable write combining: %d\n", 3749 rc); 3750 } 3751 3752 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 3753 t4_write_reg(sc, A_SGE_STAT_CFG, 3754 V_STATSOURCE_T5(7) | mode); 3755 } 3756 #endif 3757 } 3758 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 3759 3760 return (0); 3761 } 3762 3763 struct memwin_init { 3764 uint32_t base; 3765 uint32_t aperture; 3766 }; 3767 3768 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 3769 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3770 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3771 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 3772 }; 3773 3774 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 3775 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3776 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3777 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 3778 }; 3779 3780 static void 3781 setup_memwin(struct adapter *sc) 3782 { 3783 const struct memwin_init *mw_init; 3784 struct memwin *mw; 3785 int i; 3786 uint32_t bar0; 3787 3788 if (is_t4(sc)) { 3789 /* 3790 * Read low 32b of bar0 indirectly via the hardware backdoor 3791 * mechanism. Works from within PCI passthrough environments 3792 * too, where rman_get_start() can return a different value. We 3793 * need to program the T4 memory window decoders with the actual 3794 * addresses that will be coming across the PCIe link. 3795 */ 3796 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 3797 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 3798 3799 mw_init = &t4_memwin[0]; 3800 } else { 3801 /* T5+ use the relative offset inside the PCIe BAR */ 3802 bar0 = 0; 3803 3804 mw_init = &t5_memwin[0]; 3805 } 3806 3807 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 3808 if (!rw_initialized(&mw->mw_lock)) { 3809 rw_init(&mw->mw_lock, "memory window access"); 3810 mw->mw_base = mw_init->base; 3811 mw->mw_aperture = mw_init->aperture; 3812 mw->mw_curpos = 0; 3813 } 3814 t4_write_reg(sc, 3815 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 3816 (mw->mw_base + bar0) | V_BIR(0) | 3817 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 3818 rw_wlock(&mw->mw_lock); 3819 position_memwin(sc, i, mw->mw_curpos); 3820 rw_wunlock(&mw->mw_lock); 3821 } 3822 3823 /* flush */ 3824 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 3825 } 3826 3827 /* 3828 * Positions the memory window at the given address in the card's address space. 3829 * There are some alignment requirements and the actual position may be at an 3830 * address prior to the requested address. mw->mw_curpos always has the actual 3831 * position of the window. 3832 */ 3833 static void 3834 position_memwin(struct adapter *sc, int idx, uint32_t addr) 3835 { 3836 struct memwin *mw; 3837 uint32_t pf; 3838 uint32_t reg; 3839 3840 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3841 mw = &sc->memwin[idx]; 3842 rw_assert(&mw->mw_lock, RA_WLOCKED); 3843 3844 if (is_t4(sc)) { 3845 pf = 0; 3846 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 3847 } else { 3848 pf = V_PFNUM(sc->pf); 3849 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 3850 } 3851 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 3852 t4_write_reg(sc, reg, mw->mw_curpos | pf); 3853 t4_read_reg(sc, reg); /* flush */ 3854 } 3855 3856 int 3857 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 3858 int len, int rw) 3859 { 3860 struct memwin *mw; 3861 uint32_t mw_end, v; 3862 3863 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3864 3865 /* Memory can only be accessed in naturally aligned 4 byte units */ 3866 if (addr & 3 || len & 3 || len <= 0) 3867 return (EINVAL); 3868 3869 mw = &sc->memwin[idx]; 3870 while (len > 0) { 3871 rw_rlock(&mw->mw_lock); 3872 mw_end = mw->mw_curpos + mw->mw_aperture; 3873 if (addr >= mw_end || addr < mw->mw_curpos) { 3874 /* Will need to reposition the window */ 3875 if (!rw_try_upgrade(&mw->mw_lock)) { 3876 rw_runlock(&mw->mw_lock); 3877 rw_wlock(&mw->mw_lock); 3878 } 3879 rw_assert(&mw->mw_lock, RA_WLOCKED); 3880 position_memwin(sc, idx, addr); 3881 rw_downgrade(&mw->mw_lock); 3882 mw_end = mw->mw_curpos + mw->mw_aperture; 3883 } 3884 rw_assert(&mw->mw_lock, RA_RLOCKED); 3885 while (addr < mw_end && len > 0) { 3886 if (rw == 0) { 3887 v = t4_read_reg(sc, mw->mw_base + addr - 3888 mw->mw_curpos); 3889 *val++ = le32toh(v); 3890 } else { 3891 v = *val++; 3892 t4_write_reg(sc, mw->mw_base + addr - 3893 mw->mw_curpos, htole32(v)); 3894 } 3895 addr += 4; 3896 len -= 4; 3897 } 3898 rw_runlock(&mw->mw_lock); 3899 } 3900 3901 return (0); 3902 } 3903 3904 static void 3905 t4_init_atid_table(struct adapter *sc) 3906 { 3907 struct tid_info *t; 3908 int i; 3909 3910 t = &sc->tids; 3911 if (t->natids == 0) 3912 return; 3913 3914 MPASS(t->atid_tab == NULL); 3915 3916 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 3917 M_ZERO | M_WAITOK); 3918 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 3919 t->afree = t->atid_tab; 3920 t->atids_in_use = 0; 3921 for (i = 1; i < t->natids; i++) 3922 t->atid_tab[i - 1].next = &t->atid_tab[i]; 3923 t->atid_tab[t->natids - 1].next = NULL; 3924 } 3925 3926 static void 3927 t4_free_atid_table(struct adapter *sc) 3928 { 3929 struct tid_info *t; 3930 3931 t = &sc->tids; 3932 3933 KASSERT(t->atids_in_use == 0, 3934 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 3935 3936 if (mtx_initialized(&t->atid_lock)) 3937 mtx_destroy(&t->atid_lock); 3938 free(t->atid_tab, M_CXGBE); 3939 t->atid_tab = NULL; 3940 } 3941 3942 int 3943 alloc_atid(struct adapter *sc, void *ctx) 3944 { 3945 struct tid_info *t = &sc->tids; 3946 int atid = -1; 3947 3948 mtx_lock(&t->atid_lock); 3949 if (t->afree) { 3950 union aopen_entry *p = t->afree; 3951 3952 atid = p - t->atid_tab; 3953 MPASS(atid <= M_TID_TID); 3954 t->afree = p->next; 3955 p->data = ctx; 3956 t->atids_in_use++; 3957 } 3958 mtx_unlock(&t->atid_lock); 3959 return (atid); 3960 } 3961 3962 void * 3963 lookup_atid(struct adapter *sc, int atid) 3964 { 3965 struct tid_info *t = &sc->tids; 3966 3967 return (t->atid_tab[atid].data); 3968 } 3969 3970 void 3971 free_atid(struct adapter *sc, int atid) 3972 { 3973 struct tid_info *t = &sc->tids; 3974 union aopen_entry *p = &t->atid_tab[atid]; 3975 3976 mtx_lock(&t->atid_lock); 3977 p->next = t->afree; 3978 t->afree = p; 3979 t->atids_in_use--; 3980 mtx_unlock(&t->atid_lock); 3981 } 3982 3983 static void 3984 queue_tid_release(struct adapter *sc, int tid) 3985 { 3986 3987 CXGBE_UNIMPLEMENTED("deferred tid release"); 3988 } 3989 3990 void 3991 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 3992 { 3993 struct wrqe *wr; 3994 struct cpl_tid_release *req; 3995 3996 wr = alloc_wrqe(sizeof(*req), ctrlq); 3997 if (wr == NULL) { 3998 queue_tid_release(sc, tid); /* defer */ 3999 return; 4000 } 4001 req = wrtod(wr); 4002 4003 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 4004 4005 t4_wrq_tx(sc, wr); 4006 } 4007 4008 static int 4009 t4_range_cmp(const void *a, const void *b) 4010 { 4011 return ((const struct t4_range *)a)->start - 4012 ((const struct t4_range *)b)->start; 4013 } 4014 4015 /* 4016 * Verify that the memory range specified by the addr/len pair is valid within 4017 * the card's address space. 4018 */ 4019 static int 4020 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 4021 { 4022 struct t4_range mem_ranges[4], *r, *next; 4023 uint32_t em, addr_len; 4024 int i, n, remaining; 4025 4026 /* Memory can only be accessed in naturally aligned 4 byte units */ 4027 if (addr & 3 || len & 3 || len == 0) 4028 return (EINVAL); 4029 4030 /* Enabled memories */ 4031 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4032 4033 r = &mem_ranges[0]; 4034 n = 0; 4035 bzero(r, sizeof(mem_ranges)); 4036 if (em & F_EDRAM0_ENABLE) { 4037 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4038 r->size = G_EDRAM0_SIZE(addr_len) << 20; 4039 if (r->size > 0) { 4040 r->start = G_EDRAM0_BASE(addr_len) << 20; 4041 if (addr >= r->start && 4042 addr + len <= r->start + r->size) 4043 return (0); 4044 r++; 4045 n++; 4046 } 4047 } 4048 if (em & F_EDRAM1_ENABLE) { 4049 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4050 r->size = G_EDRAM1_SIZE(addr_len) << 20; 4051 if (r->size > 0) { 4052 r->start = G_EDRAM1_BASE(addr_len) << 20; 4053 if (addr >= r->start && 4054 addr + len <= r->start + r->size) 4055 return (0); 4056 r++; 4057 n++; 4058 } 4059 } 4060 if (em & F_EXT_MEM_ENABLE) { 4061 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4062 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 4063 if (r->size > 0) { 4064 r->start = G_EXT_MEM_BASE(addr_len) << 20; 4065 if (addr >= r->start && 4066 addr + len <= r->start + r->size) 4067 return (0); 4068 r++; 4069 n++; 4070 } 4071 } 4072 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 4073 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4074 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 4075 if (r->size > 0) { 4076 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 4077 if (addr >= r->start && 4078 addr + len <= r->start + r->size) 4079 return (0); 4080 r++; 4081 n++; 4082 } 4083 } 4084 MPASS(n <= nitems(mem_ranges)); 4085 4086 if (n > 1) { 4087 /* Sort and merge the ranges. */ 4088 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 4089 4090 /* Start from index 0 and examine the next n - 1 entries. */ 4091 r = &mem_ranges[0]; 4092 for (remaining = n - 1; remaining > 0; remaining--, r++) { 4093 4094 MPASS(r->size > 0); /* r is a valid entry. */ 4095 next = r + 1; 4096 MPASS(next->size > 0); /* and so is the next one. */ 4097 4098 while (r->start + r->size >= next->start) { 4099 /* Merge the next one into the current entry. */ 4100 r->size = max(r->start + r->size, 4101 next->start + next->size) - r->start; 4102 n--; /* One fewer entry in total. */ 4103 if (--remaining == 0) 4104 goto done; /* short circuit */ 4105 next++; 4106 } 4107 if (next != r + 1) { 4108 /* 4109 * Some entries were merged into r and next 4110 * points to the first valid entry that couldn't 4111 * be merged. 4112 */ 4113 MPASS(next->size > 0); /* must be valid */ 4114 memcpy(r + 1, next, remaining * sizeof(*r)); 4115 #ifdef INVARIANTS 4116 /* 4117 * This so that the foo->size assertion in the 4118 * next iteration of the loop do the right 4119 * thing for entries that were pulled up and are 4120 * no longer valid. 4121 */ 4122 MPASS(n < nitems(mem_ranges)); 4123 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 4124 sizeof(struct t4_range)); 4125 #endif 4126 } 4127 } 4128 done: 4129 /* Done merging the ranges. */ 4130 MPASS(n > 0); 4131 r = &mem_ranges[0]; 4132 for (i = 0; i < n; i++, r++) { 4133 if (addr >= r->start && 4134 addr + len <= r->start + r->size) 4135 return (0); 4136 } 4137 } 4138 4139 return (EFAULT); 4140 } 4141 4142 static int 4143 fwmtype_to_hwmtype(int mtype) 4144 { 4145 4146 switch (mtype) { 4147 case FW_MEMTYPE_EDC0: 4148 return (MEM_EDC0); 4149 case FW_MEMTYPE_EDC1: 4150 return (MEM_EDC1); 4151 case FW_MEMTYPE_EXTMEM: 4152 return (MEM_MC0); 4153 case FW_MEMTYPE_EXTMEM1: 4154 return (MEM_MC1); 4155 default: 4156 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 4157 } 4158 } 4159 4160 /* 4161 * Verify that the memory range specified by the memtype/offset/len pair is 4162 * valid and lies entirely within the memtype specified. The global address of 4163 * the start of the range is returned in addr. 4164 */ 4165 static int 4166 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 4167 uint32_t *addr) 4168 { 4169 uint32_t em, addr_len, maddr; 4170 4171 /* Memory can only be accessed in naturally aligned 4 byte units */ 4172 if (off & 3 || len & 3 || len == 0) 4173 return (EINVAL); 4174 4175 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4176 switch (fwmtype_to_hwmtype(mtype)) { 4177 case MEM_EDC0: 4178 if (!(em & F_EDRAM0_ENABLE)) 4179 return (EINVAL); 4180 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4181 maddr = G_EDRAM0_BASE(addr_len) << 20; 4182 break; 4183 case MEM_EDC1: 4184 if (!(em & F_EDRAM1_ENABLE)) 4185 return (EINVAL); 4186 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4187 maddr = G_EDRAM1_BASE(addr_len) << 20; 4188 break; 4189 case MEM_MC: 4190 if (!(em & F_EXT_MEM_ENABLE)) 4191 return (EINVAL); 4192 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4193 maddr = G_EXT_MEM_BASE(addr_len) << 20; 4194 break; 4195 case MEM_MC1: 4196 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 4197 return (EINVAL); 4198 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4199 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 4200 break; 4201 default: 4202 return (EINVAL); 4203 } 4204 4205 *addr = maddr + off; /* global address */ 4206 return (validate_mem_range(sc, *addr, len)); 4207 } 4208 4209 static int 4210 fixup_devlog_params(struct adapter *sc) 4211 { 4212 struct devlog_params *dparams = &sc->params.devlog; 4213 int rc; 4214 4215 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 4216 dparams->size, &dparams->addr); 4217 4218 return (rc); 4219 } 4220 4221 static void 4222 update_nirq(struct intrs_and_queues *iaq, int nports) 4223 { 4224 4225 iaq->nirq = T4_EXTRA_INTR; 4226 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq); 4227 iaq->nirq += nports * iaq->nofldrxq; 4228 iaq->nirq += nports * (iaq->num_vis - 1) * 4229 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 4230 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 4231 } 4232 4233 /* 4234 * Adjust requirements to fit the number of interrupts available. 4235 */ 4236 static void 4237 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 4238 int navail) 4239 { 4240 int old_nirq; 4241 const int nports = sc->params.nports; 4242 4243 MPASS(nports > 0); 4244 MPASS(navail > 0); 4245 4246 bzero(iaq, sizeof(*iaq)); 4247 iaq->intr_type = itype; 4248 iaq->num_vis = t4_num_vis; 4249 iaq->ntxq = t4_ntxq; 4250 iaq->ntxq_vi = t4_ntxq_vi; 4251 iaq->nrxq = t4_nrxq; 4252 iaq->nrxq_vi = t4_nrxq_vi; 4253 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4254 if (is_offload(sc) || is_ethoffload(sc)) { 4255 iaq->nofldtxq = t4_nofldtxq; 4256 iaq->nofldtxq_vi = t4_nofldtxq_vi; 4257 } 4258 #endif 4259 #ifdef TCP_OFFLOAD 4260 if (is_offload(sc)) { 4261 iaq->nofldrxq = t4_nofldrxq; 4262 iaq->nofldrxq_vi = t4_nofldrxq_vi; 4263 } 4264 #endif 4265 #ifdef DEV_NETMAP 4266 if (t4_native_netmap & NN_MAIN_VI) { 4267 iaq->nnmtxq = t4_nnmtxq; 4268 iaq->nnmrxq = t4_nnmrxq; 4269 } 4270 if (t4_native_netmap & NN_EXTRA_VI) { 4271 iaq->nnmtxq_vi = t4_nnmtxq_vi; 4272 iaq->nnmrxq_vi = t4_nnmrxq_vi; 4273 } 4274 #endif 4275 4276 update_nirq(iaq, nports); 4277 if (iaq->nirq <= navail && 4278 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4279 /* 4280 * This is the normal case -- there are enough interrupts for 4281 * everything. 4282 */ 4283 goto done; 4284 } 4285 4286 /* 4287 * If extra VIs have been configured try reducing their count and see if 4288 * that works. 4289 */ 4290 while (iaq->num_vis > 1) { 4291 iaq->num_vis--; 4292 update_nirq(iaq, nports); 4293 if (iaq->nirq <= navail && 4294 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4295 device_printf(sc->dev, "virtual interfaces per port " 4296 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 4297 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 4298 "itype %d, navail %u, nirq %d.\n", 4299 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 4300 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 4301 itype, navail, iaq->nirq); 4302 goto done; 4303 } 4304 } 4305 4306 /* 4307 * Extra VIs will not be created. Log a message if they were requested. 4308 */ 4309 MPASS(iaq->num_vis == 1); 4310 iaq->ntxq_vi = iaq->nrxq_vi = 0; 4311 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 4312 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 4313 if (iaq->num_vis != t4_num_vis) { 4314 device_printf(sc->dev, "extra virtual interfaces disabled. " 4315 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 4316 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 4317 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 4318 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 4319 } 4320 4321 /* 4322 * Keep reducing the number of NIC rx queues to the next lower power of 4323 * 2 (for even RSS distribution) and halving the TOE rx queues and see 4324 * if that works. 4325 */ 4326 do { 4327 if (iaq->nrxq > 1) { 4328 do { 4329 iaq->nrxq--; 4330 } while (!powerof2(iaq->nrxq)); 4331 if (iaq->nnmrxq > iaq->nrxq) 4332 iaq->nnmrxq = iaq->nrxq; 4333 } 4334 if (iaq->nofldrxq > 1) 4335 iaq->nofldrxq >>= 1; 4336 4337 old_nirq = iaq->nirq; 4338 update_nirq(iaq, nports); 4339 if (iaq->nirq <= navail && 4340 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4341 device_printf(sc->dev, "running with reduced number of " 4342 "rx queues because of shortage of interrupts. " 4343 "nrxq=%u, nofldrxq=%u. " 4344 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 4345 iaq->nofldrxq, itype, navail, iaq->nirq); 4346 goto done; 4347 } 4348 } while (old_nirq != iaq->nirq); 4349 4350 /* One interrupt for everything. Ugh. */ 4351 device_printf(sc->dev, "running with minimal number of queues. " 4352 "itype %d, navail %u.\n", itype, navail); 4353 iaq->nirq = 1; 4354 iaq->nrxq = 1; 4355 iaq->ntxq = 1; 4356 if (iaq->nofldrxq > 0) { 4357 iaq->nofldrxq = 1; 4358 iaq->nofldtxq = 1; 4359 } 4360 iaq->nnmtxq = 0; 4361 iaq->nnmrxq = 0; 4362 done: 4363 MPASS(iaq->num_vis > 0); 4364 if (iaq->num_vis > 1) { 4365 MPASS(iaq->nrxq_vi > 0); 4366 MPASS(iaq->ntxq_vi > 0); 4367 } 4368 MPASS(iaq->nirq > 0); 4369 MPASS(iaq->nrxq > 0); 4370 MPASS(iaq->ntxq > 0); 4371 if (itype == INTR_MSI) { 4372 MPASS(powerof2(iaq->nirq)); 4373 } 4374 } 4375 4376 static int 4377 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 4378 { 4379 int rc, itype, navail, nalloc; 4380 4381 for (itype = INTR_MSIX; itype; itype >>= 1) { 4382 4383 if ((itype & t4_intr_types) == 0) 4384 continue; /* not allowed */ 4385 4386 if (itype == INTR_MSIX) 4387 navail = pci_msix_count(sc->dev); 4388 else if (itype == INTR_MSI) 4389 navail = pci_msi_count(sc->dev); 4390 else 4391 navail = 1; 4392 restart: 4393 if (navail == 0) 4394 continue; 4395 4396 calculate_iaq(sc, iaq, itype, navail); 4397 nalloc = iaq->nirq; 4398 rc = 0; 4399 if (itype == INTR_MSIX) 4400 rc = pci_alloc_msix(sc->dev, &nalloc); 4401 else if (itype == INTR_MSI) 4402 rc = pci_alloc_msi(sc->dev, &nalloc); 4403 4404 if (rc == 0 && nalloc > 0) { 4405 if (nalloc == iaq->nirq) 4406 return (0); 4407 4408 /* 4409 * Didn't get the number requested. Use whatever number 4410 * the kernel is willing to allocate. 4411 */ 4412 device_printf(sc->dev, "fewer vectors than requested, " 4413 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 4414 itype, iaq->nirq, nalloc); 4415 pci_release_msi(sc->dev); 4416 navail = nalloc; 4417 goto restart; 4418 } 4419 4420 device_printf(sc->dev, 4421 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 4422 itype, rc, iaq->nirq, nalloc); 4423 } 4424 4425 device_printf(sc->dev, 4426 "failed to find a usable interrupt type. " 4427 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 4428 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 4429 4430 return (ENXIO); 4431 } 4432 4433 #define FW_VERSION(chip) ( \ 4434 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 4435 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 4436 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 4437 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 4438 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 4439 4440 /* Just enough of fw_hdr to cover all version info. */ 4441 struct fw_h { 4442 __u8 ver; 4443 __u8 chip; 4444 __be16 len512; 4445 __be32 fw_ver; 4446 __be32 tp_microcode_ver; 4447 __u8 intfver_nic; 4448 __u8 intfver_vnic; 4449 __u8 intfver_ofld; 4450 __u8 intfver_ri; 4451 __u8 intfver_iscsipdu; 4452 __u8 intfver_iscsi; 4453 __u8 intfver_fcoepdu; 4454 __u8 intfver_fcoe; 4455 }; 4456 /* Spot check a couple of fields. */ 4457 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 4458 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 4459 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 4460 4461 struct fw_info { 4462 uint8_t chip; 4463 char *kld_name; 4464 char *fw_mod_name; 4465 struct fw_h fw_h; 4466 } fw_info[] = { 4467 { 4468 .chip = CHELSIO_T4, 4469 .kld_name = "t4fw_cfg", 4470 .fw_mod_name = "t4fw", 4471 .fw_h = { 4472 .chip = FW_HDR_CHIP_T4, 4473 .fw_ver = htobe32(FW_VERSION(T4)), 4474 .intfver_nic = FW_INTFVER(T4, NIC), 4475 .intfver_vnic = FW_INTFVER(T4, VNIC), 4476 .intfver_ofld = FW_INTFVER(T4, OFLD), 4477 .intfver_ri = FW_INTFVER(T4, RI), 4478 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 4479 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4480 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 4481 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4482 }, 4483 }, { 4484 .chip = CHELSIO_T5, 4485 .kld_name = "t5fw_cfg", 4486 .fw_mod_name = "t5fw", 4487 .fw_h = { 4488 .chip = FW_HDR_CHIP_T5, 4489 .fw_ver = htobe32(FW_VERSION(T5)), 4490 .intfver_nic = FW_INTFVER(T5, NIC), 4491 .intfver_vnic = FW_INTFVER(T5, VNIC), 4492 .intfver_ofld = FW_INTFVER(T5, OFLD), 4493 .intfver_ri = FW_INTFVER(T5, RI), 4494 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 4495 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4496 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 4497 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4498 }, 4499 }, { 4500 .chip = CHELSIO_T6, 4501 .kld_name = "t6fw_cfg", 4502 .fw_mod_name = "t6fw", 4503 .fw_h = { 4504 .chip = FW_HDR_CHIP_T6, 4505 .fw_ver = htobe32(FW_VERSION(T6)), 4506 .intfver_nic = FW_INTFVER(T6, NIC), 4507 .intfver_vnic = FW_INTFVER(T6, VNIC), 4508 .intfver_ofld = FW_INTFVER(T6, OFLD), 4509 .intfver_ri = FW_INTFVER(T6, RI), 4510 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4511 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4512 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4513 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4514 }, 4515 } 4516 }; 4517 4518 static struct fw_info * 4519 find_fw_info(int chip) 4520 { 4521 int i; 4522 4523 for (i = 0; i < nitems(fw_info); i++) { 4524 if (fw_info[i].chip == chip) 4525 return (&fw_info[i]); 4526 } 4527 return (NULL); 4528 } 4529 4530 /* 4531 * Is the given firmware API compatible with the one the driver was compiled 4532 * with? 4533 */ 4534 static int 4535 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 4536 { 4537 4538 /* short circuit if it's the exact same firmware version */ 4539 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 4540 return (1); 4541 4542 /* 4543 * XXX: Is this too conservative? Perhaps I should limit this to the 4544 * features that are supported in the driver. 4545 */ 4546 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 4547 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 4548 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 4549 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 4550 return (1); 4551 #undef SAME_INTF 4552 4553 return (0); 4554 } 4555 4556 static int 4557 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 4558 const struct firmware **fw) 4559 { 4560 struct fw_info *fw_info; 4561 4562 *dcfg = NULL; 4563 if (fw != NULL) 4564 *fw = NULL; 4565 4566 fw_info = find_fw_info(chip_id(sc)); 4567 if (fw_info == NULL) { 4568 device_printf(sc->dev, 4569 "unable to look up firmware information for chip %d.\n", 4570 chip_id(sc)); 4571 return (EINVAL); 4572 } 4573 4574 *dcfg = firmware_get(fw_info->kld_name); 4575 if (*dcfg != NULL) { 4576 if (fw != NULL) 4577 *fw = firmware_get(fw_info->fw_mod_name); 4578 return (0); 4579 } 4580 4581 return (ENOENT); 4582 } 4583 4584 static void 4585 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 4586 const struct firmware *fw) 4587 { 4588 4589 if (fw != NULL) 4590 firmware_put(fw, FIRMWARE_UNLOAD); 4591 if (dcfg != NULL) 4592 firmware_put(dcfg, FIRMWARE_UNLOAD); 4593 } 4594 4595 /* 4596 * Return values: 4597 * 0 means no firmware install attempted. 4598 * ERESTART means a firmware install was attempted and was successful. 4599 * +ve errno means a firmware install was attempted but failed. 4600 */ 4601 static int 4602 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 4603 const struct fw_h *drv_fw, const char *reason, int *already) 4604 { 4605 const struct firmware *cfg, *fw; 4606 const uint32_t c = be32toh(card_fw->fw_ver); 4607 uint32_t d, k; 4608 int rc, fw_install; 4609 struct fw_h bundled_fw; 4610 bool load_attempted; 4611 4612 cfg = fw = NULL; 4613 load_attempted = false; 4614 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 4615 4616 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 4617 if (t4_fw_install < 0) { 4618 rc = load_fw_module(sc, &cfg, &fw); 4619 if (rc != 0 || fw == NULL) { 4620 device_printf(sc->dev, 4621 "failed to load firmware module: %d. cfg %p, fw %p;" 4622 " will use compiled-in firmware version for" 4623 "hw.cxgbe.fw_install checks.\n", 4624 rc, cfg, fw); 4625 } else { 4626 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 4627 } 4628 load_attempted = true; 4629 } 4630 d = be32toh(bundled_fw.fw_ver); 4631 4632 if (reason != NULL) 4633 goto install; 4634 4635 if ((sc->flags & FW_OK) == 0) { 4636 4637 if (c == 0xffffffff) { 4638 reason = "missing"; 4639 goto install; 4640 } 4641 4642 rc = 0; 4643 goto done; 4644 } 4645 4646 if (!fw_compatible(card_fw, &bundled_fw)) { 4647 reason = "incompatible or unusable"; 4648 goto install; 4649 } 4650 4651 if (d > c) { 4652 reason = "older than the version bundled with this driver"; 4653 goto install; 4654 } 4655 4656 if (fw_install == 2 && d != c) { 4657 reason = "different than the version bundled with this driver"; 4658 goto install; 4659 } 4660 4661 /* No reason to do anything to the firmware already on the card. */ 4662 rc = 0; 4663 goto done; 4664 4665 install: 4666 rc = 0; 4667 if ((*already)++) 4668 goto done; 4669 4670 if (fw_install == 0) { 4671 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4672 "but the driver is prohibited from installing a firmware " 4673 "on the card.\n", 4674 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4675 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4676 4677 goto done; 4678 } 4679 4680 /* 4681 * We'll attempt to install a firmware. Load the module first (if it 4682 * hasn't been loaded already). 4683 */ 4684 if (!load_attempted) { 4685 rc = load_fw_module(sc, &cfg, &fw); 4686 if (rc != 0 || fw == NULL) { 4687 device_printf(sc->dev, 4688 "failed to load firmware module: %d. cfg %p, fw %p\n", 4689 rc, cfg, fw); 4690 /* carry on */ 4691 } 4692 } 4693 if (fw == NULL) { 4694 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4695 "but the driver cannot take corrective action because it " 4696 "is unable to load the firmware module.\n", 4697 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4698 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4699 rc = sc->flags & FW_OK ? 0 : ENOENT; 4700 goto done; 4701 } 4702 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 4703 if (k != d) { 4704 MPASS(t4_fw_install > 0); 4705 device_printf(sc->dev, 4706 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 4707 "expecting (%u.%u.%u.%u) and will not be used.\n", 4708 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 4709 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 4710 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4711 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4712 rc = sc->flags & FW_OK ? 0 : EINVAL; 4713 goto done; 4714 } 4715 4716 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4717 "installing firmware %u.%u.%u.%u on card.\n", 4718 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4719 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 4720 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4721 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4722 4723 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 4724 if (rc != 0) { 4725 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 4726 } else { 4727 /* Installed successfully, update the cached header too. */ 4728 rc = ERESTART; 4729 memcpy(card_fw, fw->data, sizeof(*card_fw)); 4730 } 4731 done: 4732 unload_fw_module(sc, cfg, fw); 4733 4734 return (rc); 4735 } 4736 4737 /* 4738 * Establish contact with the firmware and attempt to become the master driver. 4739 * 4740 * A firmware will be installed to the card if needed (if the driver is allowed 4741 * to do so). 4742 */ 4743 static int 4744 contact_firmware(struct adapter *sc) 4745 { 4746 int rc, already = 0; 4747 enum dev_state state; 4748 struct fw_info *fw_info; 4749 struct fw_hdr *card_fw; /* fw on the card */ 4750 const struct fw_h *drv_fw; 4751 4752 fw_info = find_fw_info(chip_id(sc)); 4753 if (fw_info == NULL) { 4754 device_printf(sc->dev, 4755 "unable to look up firmware information for chip %d.\n", 4756 chip_id(sc)); 4757 return (EINVAL); 4758 } 4759 drv_fw = &fw_info->fw_h; 4760 4761 /* Read the header of the firmware on the card */ 4762 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 4763 restart: 4764 rc = -t4_get_fw_hdr(sc, card_fw); 4765 if (rc != 0) { 4766 device_printf(sc->dev, 4767 "unable to read firmware header from card's flash: %d\n", 4768 rc); 4769 goto done; 4770 } 4771 4772 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 4773 &already); 4774 if (rc == ERESTART) 4775 goto restart; 4776 if (rc != 0) 4777 goto done; 4778 4779 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 4780 if (rc < 0 || state == DEV_STATE_ERR) { 4781 rc = -rc; 4782 device_printf(sc->dev, 4783 "failed to connect to the firmware: %d, %d. " 4784 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4785 #if 0 4786 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4787 "not responding properly to HELLO", &already) == ERESTART) 4788 goto restart; 4789 #endif 4790 goto done; 4791 } 4792 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 4793 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 4794 4795 if (rc == sc->pf) { 4796 sc->flags |= MASTER_PF; 4797 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4798 NULL, &already); 4799 if (rc == ERESTART) 4800 rc = 0; 4801 else if (rc != 0) 4802 goto done; 4803 } else if (state == DEV_STATE_UNINIT) { 4804 /* 4805 * We didn't get to be the master so we definitely won't be 4806 * configuring the chip. It's a bug if someone else hasn't 4807 * configured it already. 4808 */ 4809 device_printf(sc->dev, "couldn't be master(%d), " 4810 "device not already initialized either(%d). " 4811 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4812 rc = EPROTO; 4813 goto done; 4814 } else { 4815 /* 4816 * Some other PF is the master and has configured the chip. 4817 * This is allowed but untested. 4818 */ 4819 device_printf(sc->dev, "PF%d is master, device state %d. " 4820 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4821 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 4822 sc->cfcsum = 0; 4823 rc = 0; 4824 } 4825 done: 4826 if (rc != 0 && sc->flags & FW_OK) { 4827 t4_fw_bye(sc, sc->mbox); 4828 sc->flags &= ~FW_OK; 4829 } 4830 free(card_fw, M_CXGBE); 4831 return (rc); 4832 } 4833 4834 static int 4835 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 4836 uint32_t mtype, uint32_t moff) 4837 { 4838 struct fw_info *fw_info; 4839 const struct firmware *dcfg, *rcfg = NULL; 4840 const uint32_t *cfdata; 4841 uint32_t cflen, addr; 4842 int rc; 4843 4844 load_fw_module(sc, &dcfg, NULL); 4845 4846 /* Card specific interpretation of "default". */ 4847 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4848 if (pci_get_device(sc->dev) == 0x440a) 4849 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 4850 if (is_fpga(sc)) 4851 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 4852 } 4853 4854 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4855 if (dcfg == NULL) { 4856 device_printf(sc->dev, 4857 "KLD with default config is not available.\n"); 4858 rc = ENOENT; 4859 goto done; 4860 } 4861 cfdata = dcfg->data; 4862 cflen = dcfg->datasize & ~3; 4863 } else { 4864 char s[32]; 4865 4866 fw_info = find_fw_info(chip_id(sc)); 4867 if (fw_info == NULL) { 4868 device_printf(sc->dev, 4869 "unable to look up firmware information for chip %d.\n", 4870 chip_id(sc)); 4871 rc = EINVAL; 4872 goto done; 4873 } 4874 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 4875 4876 rcfg = firmware_get(s); 4877 if (rcfg == NULL) { 4878 device_printf(sc->dev, 4879 "unable to load module \"%s\" for configuration " 4880 "profile \"%s\".\n", s, cfg_file); 4881 rc = ENOENT; 4882 goto done; 4883 } 4884 cfdata = rcfg->data; 4885 cflen = rcfg->datasize & ~3; 4886 } 4887 4888 if (cflen > FLASH_CFG_MAX_SIZE) { 4889 device_printf(sc->dev, 4890 "config file too long (%d, max allowed is %d).\n", 4891 cflen, FLASH_CFG_MAX_SIZE); 4892 rc = EINVAL; 4893 goto done; 4894 } 4895 4896 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 4897 if (rc != 0) { 4898 device_printf(sc->dev, 4899 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 4900 __func__, mtype, moff, cflen, rc); 4901 rc = EINVAL; 4902 goto done; 4903 } 4904 write_via_memwin(sc, 2, addr, cfdata, cflen); 4905 done: 4906 if (rcfg != NULL) 4907 firmware_put(rcfg, FIRMWARE_UNLOAD); 4908 unload_fw_module(sc, dcfg, NULL); 4909 return (rc); 4910 } 4911 4912 struct caps_allowed { 4913 uint16_t nbmcaps; 4914 uint16_t linkcaps; 4915 uint16_t switchcaps; 4916 uint16_t niccaps; 4917 uint16_t toecaps; 4918 uint16_t rdmacaps; 4919 uint16_t cryptocaps; 4920 uint16_t iscsicaps; 4921 uint16_t fcoecaps; 4922 }; 4923 4924 #define FW_PARAM_DEV(param) \ 4925 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 4926 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 4927 #define FW_PARAM_PFVF(param) \ 4928 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 4929 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 4930 4931 /* 4932 * Provide a configuration profile to the firmware and have it initialize the 4933 * chip accordingly. This may involve uploading a configuration file to the 4934 * card. 4935 */ 4936 static int 4937 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 4938 const struct caps_allowed *caps_allowed) 4939 { 4940 int rc; 4941 struct fw_caps_config_cmd caps; 4942 uint32_t mtype, moff, finicsum, cfcsum, param, val; 4943 4944 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 4945 if (rc != 0) { 4946 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 4947 return (rc); 4948 } 4949 4950 bzero(&caps, sizeof(caps)); 4951 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4952 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4953 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 4954 mtype = 0; 4955 moff = 0; 4956 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4957 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 4958 mtype = FW_MEMTYPE_FLASH; 4959 moff = t4_flash_cfg_addr(sc); 4960 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4961 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4962 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4963 FW_LEN16(caps)); 4964 } else { 4965 /* 4966 * Ask the firmware where it wants us to upload the config file. 4967 */ 4968 param = FW_PARAM_DEV(CF); 4969 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4970 if (rc != 0) { 4971 /* No support for config file? Shouldn't happen. */ 4972 device_printf(sc->dev, 4973 "failed to query config file location: %d.\n", rc); 4974 goto done; 4975 } 4976 mtype = G_FW_PARAMS_PARAM_Y(val); 4977 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 4978 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4979 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4980 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4981 FW_LEN16(caps)); 4982 4983 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 4984 if (rc != 0) { 4985 device_printf(sc->dev, 4986 "failed to upload config file to card: %d.\n", rc); 4987 goto done; 4988 } 4989 } 4990 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4991 if (rc != 0) { 4992 device_printf(sc->dev, "failed to pre-process config file: %d " 4993 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 4994 goto done; 4995 } 4996 4997 finicsum = be32toh(caps.finicsum); 4998 cfcsum = be32toh(caps.cfcsum); /* actual */ 4999 if (finicsum != cfcsum) { 5000 device_printf(sc->dev, 5001 "WARNING: config file checksum mismatch: %08x %08x\n", 5002 finicsum, cfcsum); 5003 } 5004 sc->cfcsum = cfcsum; 5005 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 5006 5007 /* 5008 * Let the firmware know what features will (not) be used so it can tune 5009 * things accordingly. 5010 */ 5011 #define LIMIT_CAPS(x) do { \ 5012 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 5013 } while (0) 5014 LIMIT_CAPS(nbm); 5015 LIMIT_CAPS(link); 5016 LIMIT_CAPS(switch); 5017 LIMIT_CAPS(nic); 5018 LIMIT_CAPS(toe); 5019 LIMIT_CAPS(rdma); 5020 LIMIT_CAPS(crypto); 5021 LIMIT_CAPS(iscsi); 5022 LIMIT_CAPS(fcoe); 5023 #undef LIMIT_CAPS 5024 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 5025 /* 5026 * TOE and hashfilters are mutually exclusive. It is a config 5027 * file or firmware bug if both are reported as available. Try 5028 * to cope with the situation in non-debug builds by disabling 5029 * TOE. 5030 */ 5031 MPASS(caps.toecaps == 0); 5032 5033 caps.toecaps = 0; 5034 caps.rdmacaps = 0; 5035 caps.iscsicaps = 0; 5036 } 5037 5038 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5039 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5040 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5041 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 5042 if (rc != 0) { 5043 device_printf(sc->dev, 5044 "failed to process config file: %d.\n", rc); 5045 goto done; 5046 } 5047 5048 t4_tweak_chip_settings(sc); 5049 set_params__pre_init(sc); 5050 5051 /* get basic stuff going */ 5052 rc = -t4_fw_initialize(sc, sc->mbox); 5053 if (rc != 0) { 5054 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 5055 goto done; 5056 } 5057 done: 5058 return (rc); 5059 } 5060 5061 /* 5062 * Partition chip resources for use between various PFs, VFs, etc. 5063 */ 5064 static int 5065 partition_resources(struct adapter *sc) 5066 { 5067 char cfg_file[sizeof(t4_cfg_file)]; 5068 struct caps_allowed caps_allowed; 5069 int rc; 5070 bool fallback; 5071 5072 /* Only the master driver gets to configure the chip resources. */ 5073 MPASS(sc->flags & MASTER_PF); 5074 5075 #define COPY_CAPS(x) do { \ 5076 caps_allowed.x##caps = t4_##x##caps_allowed; \ 5077 } while (0) 5078 bzero(&caps_allowed, sizeof(caps_allowed)); 5079 COPY_CAPS(nbm); 5080 COPY_CAPS(link); 5081 COPY_CAPS(switch); 5082 COPY_CAPS(nic); 5083 COPY_CAPS(toe); 5084 COPY_CAPS(rdma); 5085 COPY_CAPS(crypto); 5086 COPY_CAPS(iscsi); 5087 COPY_CAPS(fcoe); 5088 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 5089 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 5090 retry: 5091 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 5092 if (rc != 0 && fallback) { 5093 dump_devlog(sc); 5094 device_printf(sc->dev, 5095 "failed (%d) to configure card with \"%s\" profile, " 5096 "will fall back to a basic configuration and retry.\n", 5097 rc, cfg_file); 5098 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 5099 bzero(&caps_allowed, sizeof(caps_allowed)); 5100 COPY_CAPS(switch); 5101 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 5102 fallback = false; 5103 goto retry; 5104 } 5105 #undef COPY_CAPS 5106 return (rc); 5107 } 5108 5109 /* 5110 * Retrieve parameters that are needed (or nice to have) very early. 5111 */ 5112 static int 5113 get_params__pre_init(struct adapter *sc) 5114 { 5115 int rc; 5116 uint32_t param[2], val[2]; 5117 5118 t4_get_version_info(sc); 5119 5120 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 5121 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 5122 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 5123 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 5124 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 5125 5126 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 5127 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 5128 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 5129 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 5130 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 5131 5132 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 5133 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 5134 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 5135 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 5136 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 5137 5138 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 5139 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 5140 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 5141 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 5142 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 5143 5144 param[0] = FW_PARAM_DEV(PORTVEC); 5145 param[1] = FW_PARAM_DEV(CCLK); 5146 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5147 if (rc != 0) { 5148 device_printf(sc->dev, 5149 "failed to query parameters (pre_init): %d.\n", rc); 5150 return (rc); 5151 } 5152 5153 sc->params.portvec = val[0]; 5154 sc->params.nports = bitcount32(val[0]); 5155 sc->params.vpd.cclk = val[1]; 5156 5157 /* Read device log parameters. */ 5158 rc = -t4_init_devlog_params(sc, 1); 5159 if (rc == 0) 5160 fixup_devlog_params(sc); 5161 else { 5162 device_printf(sc->dev, 5163 "failed to get devlog parameters: %d.\n", rc); 5164 rc = 0; /* devlog isn't critical for device operation */ 5165 } 5166 5167 return (rc); 5168 } 5169 5170 /* 5171 * Any params that need to be set before FW_INITIALIZE. 5172 */ 5173 static int 5174 set_params__pre_init(struct adapter *sc) 5175 { 5176 int rc = 0; 5177 uint32_t param, val; 5178 5179 if (chip_id(sc) >= CHELSIO_T6) { 5180 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 5181 val = 1; 5182 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5183 /* firmwares < 1.20.1.0 do not have this param. */ 5184 if (rc == FW_EINVAL && 5185 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) { 5186 rc = 0; 5187 } 5188 if (rc != 0) { 5189 device_printf(sc->dev, 5190 "failed to enable high priority filters :%d.\n", 5191 rc); 5192 } 5193 5194 param = FW_PARAM_DEV(PPOD_EDRAM); 5195 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5196 if (rc == 0 && val == 1) { 5197 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, 5198 &val); 5199 if (rc != 0) { 5200 device_printf(sc->dev, 5201 "failed to set PPOD_EDRAM: %d.\n", rc); 5202 } 5203 } 5204 } 5205 5206 /* Enable opaque VIIDs with firmwares that support it. */ 5207 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 5208 val = 1; 5209 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5210 if (rc == 0 && val == 1) 5211 sc->params.viid_smt_extn_support = true; 5212 else 5213 sc->params.viid_smt_extn_support = false; 5214 5215 return (rc); 5216 } 5217 5218 /* 5219 * Retrieve various parameters that are of interest to the driver. The device 5220 * has been initialized by the firmware at this point. 5221 */ 5222 static int 5223 get_params__post_init(struct adapter *sc) 5224 { 5225 int rc; 5226 uint32_t param[7], val[7]; 5227 struct fw_caps_config_cmd caps; 5228 5229 param[0] = FW_PARAM_PFVF(IQFLINT_START); 5230 param[1] = FW_PARAM_PFVF(EQ_START); 5231 param[2] = FW_PARAM_PFVF(FILTER_START); 5232 param[3] = FW_PARAM_PFVF(FILTER_END); 5233 param[4] = FW_PARAM_PFVF(L2T_START); 5234 param[5] = FW_PARAM_PFVF(L2T_END); 5235 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5236 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5237 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 5238 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 5239 if (rc != 0) { 5240 device_printf(sc->dev, 5241 "failed to query parameters (post_init): %d.\n", rc); 5242 return (rc); 5243 } 5244 5245 sc->sge.iq_start = val[0]; 5246 sc->sge.eq_start = val[1]; 5247 if ((int)val[3] > (int)val[2]) { 5248 sc->tids.ftid_base = val[2]; 5249 sc->tids.ftid_end = val[3]; 5250 sc->tids.nftids = val[3] - val[2] + 1; 5251 } 5252 sc->vres.l2t.start = val[4]; 5253 sc->vres.l2t.size = val[5] - val[4] + 1; 5254 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 5255 ("%s: L2 table size (%u) larger than expected (%u)", 5256 __func__, sc->vres.l2t.size, L2T_SIZE)); 5257 sc->params.core_vdd = val[6]; 5258 5259 param[0] = FW_PARAM_PFVF(IQFLINT_END); 5260 param[1] = FW_PARAM_PFVF(EQ_END); 5261 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5262 if (rc != 0) { 5263 device_printf(sc->dev, 5264 "failed to query parameters (post_init2): %d.\n", rc); 5265 return (rc); 5266 } 5267 MPASS((int)val[0] >= sc->sge.iq_start); 5268 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1; 5269 MPASS((int)val[1] >= sc->sge.eq_start); 5270 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1; 5271 5272 if (chip_id(sc) >= CHELSIO_T6) { 5273 5274 sc->tids.tid_base = t4_read_reg(sc, 5275 A_LE_DB_ACTIVE_TABLE_START_INDEX); 5276 5277 param[0] = FW_PARAM_PFVF(HPFILTER_START); 5278 param[1] = FW_PARAM_PFVF(HPFILTER_END); 5279 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5280 if (rc != 0) { 5281 device_printf(sc->dev, 5282 "failed to query hpfilter parameters: %d.\n", rc); 5283 return (rc); 5284 } 5285 if ((int)val[1] > (int)val[0]) { 5286 sc->tids.hpftid_base = val[0]; 5287 sc->tids.hpftid_end = val[1]; 5288 sc->tids.nhpftids = val[1] - val[0] + 1; 5289 5290 /* 5291 * These should go off if the layout changes and the 5292 * driver needs to catch up. 5293 */ 5294 MPASS(sc->tids.hpftid_base == 0); 5295 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 5296 } 5297 5298 param[0] = FW_PARAM_PFVF(RAWF_START); 5299 param[1] = FW_PARAM_PFVF(RAWF_END); 5300 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5301 if (rc != 0) { 5302 device_printf(sc->dev, 5303 "failed to query rawf parameters: %d.\n", rc); 5304 return (rc); 5305 } 5306 if ((int)val[1] > (int)val[0]) { 5307 sc->rawf_base = val[0]; 5308 sc->nrawf = val[1] - val[0] + 1; 5309 } 5310 } 5311 5312 /* 5313 * MPSBGMAP is queried separately because only recent firmwares support 5314 * it as a parameter and we don't want the compound query above to fail 5315 * on older firmwares. 5316 */ 5317 param[0] = FW_PARAM_DEV(MPSBGMAP); 5318 val[0] = 0; 5319 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5320 if (rc == 0) 5321 sc->params.mps_bg_map = val[0]; 5322 else 5323 sc->params.mps_bg_map = 0; 5324 5325 /* 5326 * Determine whether the firmware supports the filter2 work request. 5327 * This is queried separately for the same reason as MPSBGMAP above. 5328 */ 5329 param[0] = FW_PARAM_DEV(FILTER2_WR); 5330 val[0] = 0; 5331 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5332 if (rc == 0) 5333 sc->params.filter2_wr_support = val[0] != 0; 5334 else 5335 sc->params.filter2_wr_support = 0; 5336 5337 /* 5338 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 5339 * This is queried separately for the same reason as other params above. 5340 */ 5341 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 5342 val[0] = 0; 5343 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5344 if (rc == 0) 5345 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 5346 else 5347 sc->params.ulptx_memwrite_dsgl = false; 5348 5349 /* FW_RI_FR_NSMR_TPTE_WR support */ 5350 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 5351 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5352 if (rc == 0) 5353 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0; 5354 else 5355 sc->params.fr_nsmr_tpte_wr_support = false; 5356 5357 /* Support for 512 SGL entries per FR MR. */ 5358 param[0] = FW_PARAM_DEV(DEV_512SGL_MR); 5359 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5360 if (rc == 0) 5361 sc->params.dev_512sgl_mr = val[0] != 0; 5362 else 5363 sc->params.dev_512sgl_mr = false; 5364 5365 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 5366 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5367 if (rc == 0) 5368 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0]; 5369 else 5370 sc->params.max_pkts_per_eth_tx_pkts_wr = 15; 5371 5372 param[0] = FW_PARAM_DEV(NUM_TM_CLASS); 5373 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5374 if (rc == 0) { 5375 MPASS(val[0] > 0 && val[0] < 256); /* nsched_cls is 8b */ 5376 sc->params.nsched_cls = val[0]; 5377 } else 5378 sc->params.nsched_cls = sc->chip_params->nsched_cls; 5379 5380 /* get capabilites */ 5381 bzero(&caps, sizeof(caps)); 5382 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5383 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5384 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5385 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5386 if (rc != 0) { 5387 device_printf(sc->dev, 5388 "failed to get card capabilities: %d.\n", rc); 5389 return (rc); 5390 } 5391 5392 #define READ_CAPS(x) do { \ 5393 sc->x = htobe16(caps.x); \ 5394 } while (0) 5395 READ_CAPS(nbmcaps); 5396 READ_CAPS(linkcaps); 5397 READ_CAPS(switchcaps); 5398 READ_CAPS(niccaps); 5399 READ_CAPS(toecaps); 5400 READ_CAPS(rdmacaps); 5401 READ_CAPS(cryptocaps); 5402 READ_CAPS(iscsicaps); 5403 READ_CAPS(fcoecaps); 5404 5405 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 5406 MPASS(chip_id(sc) > CHELSIO_T4); 5407 MPASS(sc->toecaps == 0); 5408 sc->toecaps = 0; 5409 5410 param[0] = FW_PARAM_DEV(NTID); 5411 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5412 if (rc != 0) { 5413 device_printf(sc->dev, 5414 "failed to query HASHFILTER parameters: %d.\n", rc); 5415 return (rc); 5416 } 5417 sc->tids.ntids = val[0]; 5418 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5419 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5420 sc->tids.ntids -= sc->tids.nhpftids; 5421 } 5422 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5423 sc->params.hash_filter = 1; 5424 } 5425 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 5426 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 5427 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 5428 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5429 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 5430 if (rc != 0) { 5431 device_printf(sc->dev, 5432 "failed to query NIC parameters: %d.\n", rc); 5433 return (rc); 5434 } 5435 if ((int)val[1] > (int)val[0]) { 5436 sc->tids.etid_base = val[0]; 5437 sc->tids.etid_end = val[1]; 5438 sc->tids.netids = val[1] - val[0] + 1; 5439 sc->params.eo_wr_cred = val[2]; 5440 sc->params.ethoffload = 1; 5441 } 5442 } 5443 if (sc->toecaps) { 5444 /* query offload-related parameters */ 5445 param[0] = FW_PARAM_DEV(NTID); 5446 param[1] = FW_PARAM_PFVF(SERVER_START); 5447 param[2] = FW_PARAM_PFVF(SERVER_END); 5448 param[3] = FW_PARAM_PFVF(TDDP_START); 5449 param[4] = FW_PARAM_PFVF(TDDP_END); 5450 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5451 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5452 if (rc != 0) { 5453 device_printf(sc->dev, 5454 "failed to query TOE parameters: %d.\n", rc); 5455 return (rc); 5456 } 5457 sc->tids.ntids = val[0]; 5458 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5459 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5460 sc->tids.ntids -= sc->tids.nhpftids; 5461 } 5462 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5463 if ((int)val[2] > (int)val[1]) { 5464 sc->tids.stid_base = val[1]; 5465 sc->tids.nstids = val[2] - val[1] + 1; 5466 } 5467 sc->vres.ddp.start = val[3]; 5468 sc->vres.ddp.size = val[4] - val[3] + 1; 5469 sc->params.ofldq_wr_cred = val[5]; 5470 sc->params.offload = 1; 5471 } else { 5472 /* 5473 * The firmware attempts memfree TOE configuration for -SO cards 5474 * and will report toecaps=0 if it runs out of resources (this 5475 * depends on the config file). It may not report 0 for other 5476 * capabilities dependent on the TOE in this case. Set them to 5477 * 0 here so that the driver doesn't bother tracking resources 5478 * that will never be used. 5479 */ 5480 sc->iscsicaps = 0; 5481 sc->rdmacaps = 0; 5482 } 5483 if (sc->rdmacaps) { 5484 param[0] = FW_PARAM_PFVF(STAG_START); 5485 param[1] = FW_PARAM_PFVF(STAG_END); 5486 param[2] = FW_PARAM_PFVF(RQ_START); 5487 param[3] = FW_PARAM_PFVF(RQ_END); 5488 param[4] = FW_PARAM_PFVF(PBL_START); 5489 param[5] = FW_PARAM_PFVF(PBL_END); 5490 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5491 if (rc != 0) { 5492 device_printf(sc->dev, 5493 "failed to query RDMA parameters(1): %d.\n", rc); 5494 return (rc); 5495 } 5496 sc->vres.stag.start = val[0]; 5497 sc->vres.stag.size = val[1] - val[0] + 1; 5498 sc->vres.rq.start = val[2]; 5499 sc->vres.rq.size = val[3] - val[2] + 1; 5500 sc->vres.pbl.start = val[4]; 5501 sc->vres.pbl.size = val[5] - val[4] + 1; 5502 5503 param[0] = FW_PARAM_PFVF(SQRQ_START); 5504 param[1] = FW_PARAM_PFVF(SQRQ_END); 5505 param[2] = FW_PARAM_PFVF(CQ_START); 5506 param[3] = FW_PARAM_PFVF(CQ_END); 5507 param[4] = FW_PARAM_PFVF(OCQ_START); 5508 param[5] = FW_PARAM_PFVF(OCQ_END); 5509 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5510 if (rc != 0) { 5511 device_printf(sc->dev, 5512 "failed to query RDMA parameters(2): %d.\n", rc); 5513 return (rc); 5514 } 5515 sc->vres.qp.start = val[0]; 5516 sc->vres.qp.size = val[1] - val[0] + 1; 5517 sc->vres.cq.start = val[2]; 5518 sc->vres.cq.size = val[3] - val[2] + 1; 5519 sc->vres.ocq.start = val[4]; 5520 sc->vres.ocq.size = val[5] - val[4] + 1; 5521 5522 param[0] = FW_PARAM_PFVF(SRQ_START); 5523 param[1] = FW_PARAM_PFVF(SRQ_END); 5524 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 5525 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 5526 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 5527 if (rc != 0) { 5528 device_printf(sc->dev, 5529 "failed to query RDMA parameters(3): %d.\n", rc); 5530 return (rc); 5531 } 5532 sc->vres.srq.start = val[0]; 5533 sc->vres.srq.size = val[1] - val[0] + 1; 5534 sc->params.max_ordird_qp = val[2]; 5535 sc->params.max_ird_adapter = val[3]; 5536 } 5537 if (sc->iscsicaps) { 5538 param[0] = FW_PARAM_PFVF(ISCSI_START); 5539 param[1] = FW_PARAM_PFVF(ISCSI_END); 5540 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5541 if (rc != 0) { 5542 device_printf(sc->dev, 5543 "failed to query iSCSI parameters: %d.\n", rc); 5544 return (rc); 5545 } 5546 sc->vres.iscsi.start = val[0]; 5547 sc->vres.iscsi.size = val[1] - val[0] + 1; 5548 } 5549 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 5550 param[0] = FW_PARAM_PFVF(TLS_START); 5551 param[1] = FW_PARAM_PFVF(TLS_END); 5552 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5553 if (rc != 0) { 5554 device_printf(sc->dev, 5555 "failed to query TLS parameters: %d.\n", rc); 5556 return (rc); 5557 } 5558 sc->vres.key.start = val[0]; 5559 sc->vres.key.size = val[1] - val[0] + 1; 5560 } 5561 5562 /* 5563 * We've got the params we wanted to query directly from the firmware. 5564 * Grab some others via other means. 5565 */ 5566 t4_init_sge_params(sc); 5567 t4_init_tp_params(sc); 5568 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 5569 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 5570 5571 rc = t4_verify_chip_settings(sc); 5572 if (rc != 0) 5573 return (rc); 5574 t4_init_rx_buf_info(sc); 5575 5576 return (rc); 5577 } 5578 5579 #ifdef KERN_TLS 5580 static void 5581 ktls_tick(void *arg) 5582 { 5583 struct adapter *sc; 5584 uint32_t tstamp; 5585 5586 sc = arg; 5587 tstamp = tcp_ts_getticks(); 5588 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1); 5589 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31); 5590 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK); 5591 } 5592 5593 static int 5594 t6_config_kern_tls(struct adapter *sc, bool enable) 5595 { 5596 int rc; 5597 uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5598 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) | 5599 V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) | 5600 V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE); 5601 5602 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, ¶m); 5603 if (rc != 0) { 5604 CH_ERR(sc, "failed to %s NIC TLS: %d\n", 5605 enable ? "enable" : "disable", rc); 5606 return (rc); 5607 } 5608 5609 if (enable) { 5610 sc->flags |= KERN_TLS_ON; 5611 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc, 5612 C_HARDCLOCK); 5613 } else { 5614 sc->flags &= ~KERN_TLS_ON; 5615 callout_stop(&sc->ktls_tick); 5616 } 5617 5618 return (rc); 5619 } 5620 #endif 5621 5622 static int 5623 set_params__post_init(struct adapter *sc) 5624 { 5625 uint32_t mask, param, val; 5626 #ifdef TCP_OFFLOAD 5627 int i, v, shift; 5628 #endif 5629 5630 /* ask for encapsulated CPLs */ 5631 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 5632 val = 1; 5633 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5634 5635 /* Enable 32b port caps if the firmware supports it. */ 5636 param = FW_PARAM_PFVF(PORT_CAPS32); 5637 val = 1; 5638 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 5639 sc->params.port_caps32 = 1; 5640 5641 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 5642 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 5643 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 5644 V_MASKFILTER(val - 1)); 5645 5646 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER | 5647 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN | 5648 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5649 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM; 5650 val = 0; 5651 if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) { 5652 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE, 5653 F_ATTACKFILTERENABLE); 5654 val |= F_DROPERRORATTACK; 5655 } 5656 if (t4_drop_ip_fragments != 0) { 5657 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP, 5658 F_FRAGMENTDROP); 5659 val |= F_DROPERRORFRAG; 5660 } 5661 if (t4_drop_pkts_with_l2_errors != 0) 5662 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN; 5663 if (t4_drop_pkts_with_l3_errors != 0) { 5664 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN | 5665 F_DROPERRORCSUMIP; 5666 } 5667 if (t4_drop_pkts_with_l4_errors != 0) { 5668 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5669 F_DROPERRORTCPOPT | F_DROPERRORCSUM; 5670 } 5671 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val); 5672 5673 #ifdef TCP_OFFLOAD 5674 /* 5675 * Override the TOE timers with user provided tunables. This is not the 5676 * recommended way to change the timers (the firmware config file is) so 5677 * these tunables are not documented. 5678 * 5679 * All the timer tunables are in microseconds. 5680 */ 5681 if (t4_toe_keepalive_idle != 0) { 5682 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 5683 v &= M_KEEPALIVEIDLE; 5684 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 5685 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 5686 } 5687 if (t4_toe_keepalive_interval != 0) { 5688 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 5689 v &= M_KEEPALIVEINTVL; 5690 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 5691 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 5692 } 5693 if (t4_toe_keepalive_count != 0) { 5694 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 5695 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5696 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 5697 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 5698 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 5699 } 5700 if (t4_toe_rexmt_min != 0) { 5701 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 5702 v &= M_RXTMIN; 5703 t4_set_reg_field(sc, A_TP_RXT_MIN, 5704 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 5705 } 5706 if (t4_toe_rexmt_max != 0) { 5707 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 5708 v &= M_RXTMAX; 5709 t4_set_reg_field(sc, A_TP_RXT_MAX, 5710 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 5711 } 5712 if (t4_toe_rexmt_count != 0) { 5713 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 5714 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5715 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 5716 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 5717 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 5718 } 5719 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 5720 if (t4_toe_rexmt_backoff[i] != -1) { 5721 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 5722 shift = (i & 3) << 3; 5723 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 5724 M_TIMERBACKOFFINDEX0 << shift, v << shift); 5725 } 5726 } 5727 #endif 5728 5729 /* 5730 * Limit TOE connections to 2 reassembly "islands". This is 5731 * required to permit migrating TOE connections to either 5732 * ULP_MODE_TCPDDP or UPL_MODE_TLS. 5733 */ 5734 t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, V_PASSMODE(M_PASSMODE), 5735 V_PASSMODE(2)); 5736 5737 #ifdef KERN_TLS 5738 if (is_ktls(sc)) { 5739 sc->tlst.inline_keys = t4_tls_inline_keys; 5740 sc->tlst.combo_wrs = t4_tls_combo_wrs; 5741 if (t4_kern_tls != 0 && is_t6(sc)) 5742 t6_config_kern_tls(sc, true); 5743 } 5744 #endif 5745 return (0); 5746 } 5747 5748 #undef FW_PARAM_PFVF 5749 #undef FW_PARAM_DEV 5750 5751 static void 5752 t4_set_desc(struct adapter *sc) 5753 { 5754 char buf[128]; 5755 struct adapter_params *p = &sc->params; 5756 5757 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 5758 5759 device_set_desc_copy(sc->dev, buf); 5760 } 5761 5762 static inline void 5763 ifmedia_add4(struct ifmedia *ifm, int m) 5764 { 5765 5766 ifmedia_add(ifm, m, 0, NULL); 5767 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 5768 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 5769 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 5770 } 5771 5772 /* 5773 * This is the selected media, which is not quite the same as the active media. 5774 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 5775 * and active are not the same, and "media: Ethernet selected" otherwise. 5776 */ 5777 static void 5778 set_current_media(struct port_info *pi) 5779 { 5780 struct link_config *lc; 5781 struct ifmedia *ifm; 5782 int mword; 5783 u_int speed; 5784 5785 PORT_LOCK_ASSERT_OWNED(pi); 5786 5787 /* Leave current media alone if it's already set to IFM_NONE. */ 5788 ifm = &pi->media; 5789 if (ifm->ifm_cur != NULL && 5790 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 5791 return; 5792 5793 lc = &pi->link_cfg; 5794 if (lc->requested_aneg != AUTONEG_DISABLE && 5795 lc->pcaps & FW_PORT_CAP32_ANEG) { 5796 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 5797 return; 5798 } 5799 mword = IFM_ETHER | IFM_FDX; 5800 if (lc->requested_fc & PAUSE_TX) 5801 mword |= IFM_ETH_TXPAUSE; 5802 if (lc->requested_fc & PAUSE_RX) 5803 mword |= IFM_ETH_RXPAUSE; 5804 if (lc->requested_speed == 0) 5805 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 5806 else 5807 speed = lc->requested_speed; 5808 mword |= port_mword(pi, speed_to_fwcap(speed)); 5809 ifmedia_set(ifm, mword); 5810 } 5811 5812 /* 5813 * Returns true if the ifmedia list for the port cannot change. 5814 */ 5815 static bool 5816 fixed_ifmedia(struct port_info *pi) 5817 { 5818 5819 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 5820 pi->port_type == FW_PORT_TYPE_BT_XFI || 5821 pi->port_type == FW_PORT_TYPE_BT_XAUI || 5822 pi->port_type == FW_PORT_TYPE_KX4 || 5823 pi->port_type == FW_PORT_TYPE_KX || 5824 pi->port_type == FW_PORT_TYPE_KR || 5825 pi->port_type == FW_PORT_TYPE_BP_AP || 5826 pi->port_type == FW_PORT_TYPE_BP4_AP || 5827 pi->port_type == FW_PORT_TYPE_BP40_BA || 5828 pi->port_type == FW_PORT_TYPE_KR4_100G || 5829 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 5830 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 5831 } 5832 5833 static void 5834 build_medialist(struct port_info *pi) 5835 { 5836 uint32_t ss, speed; 5837 int unknown, mword, bit; 5838 struct link_config *lc; 5839 struct ifmedia *ifm; 5840 5841 PORT_LOCK_ASSERT_OWNED(pi); 5842 5843 if (pi->flags & FIXED_IFMEDIA) 5844 return; 5845 5846 /* 5847 * Rebuild the ifmedia list. 5848 */ 5849 ifm = &pi->media; 5850 ifmedia_removeall(ifm); 5851 lc = &pi->link_cfg; 5852 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */ 5853 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 5854 MPASS(ss != 0); 5855 no_media: 5856 MPASS(LIST_EMPTY(&ifm->ifm_list)); 5857 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 5858 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 5859 return; 5860 } 5861 5862 unknown = 0; 5863 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 5864 speed = 1 << bit; 5865 MPASS(speed & M_FW_PORT_CAP32_SPEED); 5866 if (ss & speed) { 5867 mword = port_mword(pi, speed); 5868 if (mword == IFM_NONE) { 5869 goto no_media; 5870 } else if (mword == IFM_UNKNOWN) 5871 unknown++; 5872 else 5873 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 5874 } 5875 } 5876 if (unknown > 0) /* Add one unknown for all unknown media types. */ 5877 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 5878 if (lc->pcaps & FW_PORT_CAP32_ANEG) 5879 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 5880 5881 set_current_media(pi); 5882 } 5883 5884 /* 5885 * Initialize the requested fields in the link config based on driver tunables. 5886 */ 5887 static void 5888 init_link_config(struct port_info *pi) 5889 { 5890 struct link_config *lc = &pi->link_cfg; 5891 5892 PORT_LOCK_ASSERT_OWNED(pi); 5893 5894 lc->requested_caps = 0; 5895 lc->requested_speed = 0; 5896 5897 if (t4_autoneg == 0) 5898 lc->requested_aneg = AUTONEG_DISABLE; 5899 else if (t4_autoneg == 1) 5900 lc->requested_aneg = AUTONEG_ENABLE; 5901 else 5902 lc->requested_aneg = AUTONEG_AUTO; 5903 5904 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 5905 PAUSE_AUTONEG); 5906 5907 if (t4_fec & FEC_AUTO) 5908 lc->requested_fec = FEC_AUTO; 5909 else if (t4_fec == 0) 5910 lc->requested_fec = FEC_NONE; 5911 else { 5912 /* -1 is handled by the FEC_AUTO block above and not here. */ 5913 lc->requested_fec = t4_fec & 5914 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE); 5915 if (lc->requested_fec == 0) 5916 lc->requested_fec = FEC_AUTO; 5917 } 5918 if (t4_force_fec < 0) 5919 lc->force_fec = -1; 5920 else if (t4_force_fec > 0) 5921 lc->force_fec = 1; 5922 else 5923 lc->force_fec = 0; 5924 } 5925 5926 /* 5927 * Makes sure that all requested settings comply with what's supported by the 5928 * port. Returns the number of settings that were invalid and had to be fixed. 5929 */ 5930 static int 5931 fixup_link_config(struct port_info *pi) 5932 { 5933 int n = 0; 5934 struct link_config *lc = &pi->link_cfg; 5935 uint32_t fwspeed; 5936 5937 PORT_LOCK_ASSERT_OWNED(pi); 5938 5939 /* Speed (when not autonegotiating) */ 5940 if (lc->requested_speed != 0) { 5941 fwspeed = speed_to_fwcap(lc->requested_speed); 5942 if ((fwspeed & lc->pcaps) == 0) { 5943 n++; 5944 lc->requested_speed = 0; 5945 } 5946 } 5947 5948 /* Link autonegotiation */ 5949 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 5950 lc->requested_aneg == AUTONEG_DISABLE || 5951 lc->requested_aneg == AUTONEG_AUTO); 5952 if (lc->requested_aneg == AUTONEG_ENABLE && 5953 !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 5954 n++; 5955 lc->requested_aneg = AUTONEG_AUTO; 5956 } 5957 5958 /* Flow control */ 5959 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 5960 if (lc->requested_fc & PAUSE_TX && 5961 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) { 5962 n++; 5963 lc->requested_fc &= ~PAUSE_TX; 5964 } 5965 if (lc->requested_fc & PAUSE_RX && 5966 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) { 5967 n++; 5968 lc->requested_fc &= ~PAUSE_RX; 5969 } 5970 if (!(lc->requested_fc & PAUSE_AUTONEG) && 5971 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) { 5972 n++; 5973 lc->requested_fc |= PAUSE_AUTONEG; 5974 } 5975 5976 /* FEC */ 5977 if ((lc->requested_fec & FEC_RS && 5978 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) || 5979 (lc->requested_fec & FEC_BASER_RS && 5980 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) { 5981 n++; 5982 lc->requested_fec = FEC_AUTO; 5983 } 5984 5985 return (n); 5986 } 5987 5988 /* 5989 * Apply the requested L1 settings, which are expected to be valid, to the 5990 * hardware. 5991 */ 5992 static int 5993 apply_link_config(struct port_info *pi) 5994 { 5995 struct adapter *sc = pi->adapter; 5996 struct link_config *lc = &pi->link_cfg; 5997 int rc; 5998 5999 #ifdef INVARIANTS 6000 ASSERT_SYNCHRONIZED_OP(sc); 6001 PORT_LOCK_ASSERT_OWNED(pi); 6002 6003 if (lc->requested_aneg == AUTONEG_ENABLE) 6004 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG); 6005 if (!(lc->requested_fc & PAUSE_AUTONEG)) 6006 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE); 6007 if (lc->requested_fc & PAUSE_TX) 6008 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX); 6009 if (lc->requested_fc & PAUSE_RX) 6010 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX); 6011 if (lc->requested_fec & FEC_RS) 6012 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS); 6013 if (lc->requested_fec & FEC_BASER_RS) 6014 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS); 6015 #endif 6016 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6017 if (rc != 0) { 6018 /* Don't complain if the VF driver gets back an EPERM. */ 6019 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 6020 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 6021 } else { 6022 /* 6023 * An L1_CFG will almost always result in a link-change event if 6024 * the link is up, and the driver will refresh the actual 6025 * fec/fc/etc. when the notification is processed. If the link 6026 * is down then the actual settings are meaningless. 6027 * 6028 * This takes care of the case where a change in the L1 settings 6029 * may not result in a notification. 6030 */ 6031 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 6032 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 6033 } 6034 return (rc); 6035 } 6036 6037 #define FW_MAC_EXACT_CHUNK 7 6038 struct mcaddr_ctx { 6039 if_t ifp; 6040 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 6041 uint64_t hash; 6042 int i; 6043 int del; 6044 int rc; 6045 }; 6046 6047 static u_int 6048 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 6049 { 6050 struct mcaddr_ctx *ctx = arg; 6051 struct vi_info *vi = if_getsoftc(ctx->ifp); 6052 struct port_info *pi = vi->pi; 6053 struct adapter *sc = pi->adapter; 6054 6055 if (ctx->rc < 0) 6056 return (0); 6057 6058 ctx->mcaddr[ctx->i] = LLADDR(sdl); 6059 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i])); 6060 ctx->i++; 6061 6062 if (ctx->i == FW_MAC_EXACT_CHUNK) { 6063 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del, 6064 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0); 6065 if (ctx->rc < 0) { 6066 int j; 6067 6068 for (j = 0; j < ctx->i; j++) { 6069 if_printf(ctx->ifp, 6070 "failed to add mc address" 6071 " %02x:%02x:%02x:" 6072 "%02x:%02x:%02x rc=%d\n", 6073 ctx->mcaddr[j][0], ctx->mcaddr[j][1], 6074 ctx->mcaddr[j][2], ctx->mcaddr[j][3], 6075 ctx->mcaddr[j][4], ctx->mcaddr[j][5], 6076 -ctx->rc); 6077 } 6078 return (0); 6079 } 6080 ctx->del = 0; 6081 ctx->i = 0; 6082 } 6083 6084 return (1); 6085 } 6086 6087 /* 6088 * Program the port's XGMAC based on parameters in ifnet. The caller also 6089 * indicates which parameters should be programmed (the rest are left alone). 6090 */ 6091 int 6092 update_mac_settings(if_t ifp, int flags) 6093 { 6094 int rc = 0; 6095 struct vi_info *vi = if_getsoftc(ifp); 6096 struct port_info *pi = vi->pi; 6097 struct adapter *sc = pi->adapter; 6098 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 6099 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 6100 6101 ASSERT_SYNCHRONIZED_OP(sc); 6102 KASSERT(flags, ("%s: not told what to update.", __func__)); 6103 6104 if (flags & XGMAC_MTU) 6105 mtu = if_getmtu(ifp); 6106 6107 if (flags & XGMAC_PROMISC) 6108 promisc = if_getflags(ifp) & IFF_PROMISC ? 1 : 0; 6109 6110 if (flags & XGMAC_ALLMULTI) 6111 allmulti = if_getflags(ifp) & IFF_ALLMULTI ? 1 : 0; 6112 6113 if (flags & XGMAC_VLANEX) 6114 vlanex = if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING ? 1 : 0; 6115 6116 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 6117 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 6118 allmulti, 1, vlanex, false); 6119 if (rc) { 6120 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 6121 rc); 6122 return (rc); 6123 } 6124 } 6125 6126 if (flags & XGMAC_UCADDR) { 6127 uint8_t ucaddr[ETHER_ADDR_LEN]; 6128 6129 bcopy(if_getlladdr(ifp), ucaddr, sizeof(ucaddr)); 6130 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 6131 ucaddr, true, &vi->smt_idx); 6132 if (rc < 0) { 6133 rc = -rc; 6134 if_printf(ifp, "change_mac failed: %d\n", rc); 6135 return (rc); 6136 } else { 6137 vi->xact_addr_filt = rc; 6138 rc = 0; 6139 } 6140 } 6141 6142 if (flags & XGMAC_MCADDRS) { 6143 struct epoch_tracker et; 6144 struct mcaddr_ctx ctx; 6145 int j; 6146 6147 ctx.ifp = ifp; 6148 ctx.hash = 0; 6149 ctx.i = 0; 6150 ctx.del = 1; 6151 ctx.rc = 0; 6152 /* 6153 * Unlike other drivers, we accumulate list of pointers into 6154 * interface address lists and we need to keep it safe even 6155 * after if_foreach_llmaddr() returns, thus we must enter the 6156 * network epoch. 6157 */ 6158 NET_EPOCH_ENTER(et); 6159 if_foreach_llmaddr(ifp, add_maddr, &ctx); 6160 if (ctx.rc < 0) { 6161 NET_EPOCH_EXIT(et); 6162 rc = -ctx.rc; 6163 return (rc); 6164 } 6165 if (ctx.i > 0) { 6166 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 6167 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0); 6168 NET_EPOCH_EXIT(et); 6169 if (rc < 0) { 6170 rc = -rc; 6171 for (j = 0; j < ctx.i; j++) { 6172 if_printf(ifp, 6173 "failed to add mcast address" 6174 " %02x:%02x:%02x:" 6175 "%02x:%02x:%02x rc=%d\n", 6176 ctx.mcaddr[j][0], ctx.mcaddr[j][1], 6177 ctx.mcaddr[j][2], ctx.mcaddr[j][3], 6178 ctx.mcaddr[j][4], ctx.mcaddr[j][5], 6179 rc); 6180 } 6181 return (rc); 6182 } 6183 ctx.del = 0; 6184 } else 6185 NET_EPOCH_EXIT(et); 6186 6187 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0); 6188 if (rc != 0) 6189 if_printf(ifp, "failed to set mcast address hash: %d\n", 6190 rc); 6191 if (ctx.del == 0) { 6192 /* We clobbered the VXLAN entry if there was one. */ 6193 pi->vxlan_tcam_entry = false; 6194 } 6195 } 6196 6197 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 && 6198 pi->vxlan_tcam_entry == false) { 6199 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac, 6200 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 6201 true); 6202 if (rc < 0) { 6203 rc = -rc; 6204 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n", 6205 rc); 6206 } else { 6207 MPASS(rc == sc->rawf_base + pi->port_id); 6208 rc = 0; 6209 pi->vxlan_tcam_entry = true; 6210 } 6211 } 6212 6213 return (rc); 6214 } 6215 6216 /* 6217 * {begin|end}_synchronized_op must be called from the same thread. 6218 */ 6219 int 6220 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 6221 char *wmesg) 6222 { 6223 int rc, pri; 6224 6225 #ifdef WITNESS 6226 /* the caller thinks it's ok to sleep, but is it really? */ 6227 if (flags & SLEEP_OK) 6228 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 6229 "begin_synchronized_op"); 6230 #endif 6231 6232 if (INTR_OK) 6233 pri = PCATCH; 6234 else 6235 pri = 0; 6236 6237 ADAPTER_LOCK(sc); 6238 for (;;) { 6239 6240 if (vi && IS_DETACHING(vi)) { 6241 rc = ENXIO; 6242 goto done; 6243 } 6244 6245 if (!IS_BUSY(sc)) { 6246 rc = 0; 6247 break; 6248 } 6249 6250 if (!(flags & SLEEP_OK)) { 6251 rc = EBUSY; 6252 goto done; 6253 } 6254 6255 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 6256 rc = EINTR; 6257 goto done; 6258 } 6259 } 6260 6261 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 6262 SET_BUSY(sc); 6263 #ifdef INVARIANTS 6264 sc->last_op = wmesg; 6265 sc->last_op_thr = curthread; 6266 sc->last_op_flags = flags; 6267 #endif 6268 6269 done: 6270 if (!(flags & HOLD_LOCK) || rc) 6271 ADAPTER_UNLOCK(sc); 6272 6273 return (rc); 6274 } 6275 6276 /* 6277 * Tell if_ioctl and if_init that the VI is going away. This is 6278 * special variant of begin_synchronized_op and must be paired with a 6279 * call to end_vi_detach. 6280 */ 6281 void 6282 begin_vi_detach(struct adapter *sc, struct vi_info *vi) 6283 { 6284 ADAPTER_LOCK(sc); 6285 SET_DETACHING(vi); 6286 wakeup(&sc->flags); 6287 while (IS_BUSY(sc)) 6288 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 6289 SET_BUSY(sc); 6290 #ifdef INVARIANTS 6291 sc->last_op = "t4detach"; 6292 sc->last_op_thr = curthread; 6293 sc->last_op_flags = 0; 6294 #endif 6295 ADAPTER_UNLOCK(sc); 6296 } 6297 6298 void 6299 end_vi_detach(struct adapter *sc, struct vi_info *vi) 6300 { 6301 ADAPTER_LOCK(sc); 6302 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6303 CLR_BUSY(sc); 6304 CLR_DETACHING(vi); 6305 wakeup(&sc->flags); 6306 ADAPTER_UNLOCK(sc); 6307 } 6308 6309 /* 6310 * {begin|end}_synchronized_op must be called from the same thread. 6311 */ 6312 void 6313 end_synchronized_op(struct adapter *sc, int flags) 6314 { 6315 6316 if (flags & LOCK_HELD) 6317 ADAPTER_LOCK_ASSERT_OWNED(sc); 6318 else 6319 ADAPTER_LOCK(sc); 6320 6321 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6322 CLR_BUSY(sc); 6323 wakeup(&sc->flags); 6324 ADAPTER_UNLOCK(sc); 6325 } 6326 6327 static int 6328 cxgbe_init_synchronized(struct vi_info *vi) 6329 { 6330 struct port_info *pi = vi->pi; 6331 struct adapter *sc = pi->adapter; 6332 if_t ifp = vi->ifp; 6333 int rc = 0, i; 6334 struct sge_txq *txq; 6335 6336 ASSERT_SYNCHRONIZED_OP(sc); 6337 6338 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6339 return (0); /* already running */ 6340 6341 if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0)) 6342 return (rc); /* error message displayed already */ 6343 6344 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 6345 return (rc); /* error message displayed already */ 6346 6347 rc = update_mac_settings(ifp, XGMAC_ALL); 6348 if (rc) 6349 goto done; /* error message displayed already */ 6350 6351 PORT_LOCK(pi); 6352 if (pi->up_vis == 0) { 6353 t4_update_port_info(pi); 6354 fixup_link_config(pi); 6355 build_medialist(pi); 6356 apply_link_config(pi); 6357 } 6358 6359 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 6360 if (rc != 0) { 6361 if_printf(ifp, "enable_vi failed: %d\n", rc); 6362 PORT_UNLOCK(pi); 6363 goto done; 6364 } 6365 6366 /* 6367 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 6368 * if this changes. 6369 */ 6370 6371 for_each_txq(vi, i, txq) { 6372 TXQ_LOCK(txq); 6373 txq->eq.flags |= EQ_ENABLED; 6374 TXQ_UNLOCK(txq); 6375 } 6376 6377 /* 6378 * The first iq of the first port to come up is used for tracing. 6379 */ 6380 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 6381 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 6382 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 6383 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 6384 V_QUEUENUMBER(sc->traceq)); 6385 pi->flags |= HAS_TRACEQ; 6386 } 6387 6388 /* all ok */ 6389 pi->up_vis++; 6390 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 6391 if (pi->link_cfg.link_ok) 6392 t4_os_link_changed(pi); 6393 PORT_UNLOCK(pi); 6394 6395 mtx_lock(&vi->tick_mtx); 6396 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 6397 callout_reset(&vi->tick, hz, vi_tick, vi); 6398 else 6399 callout_reset(&vi->tick, hz, cxgbe_tick, vi); 6400 mtx_unlock(&vi->tick_mtx); 6401 done: 6402 if (rc != 0) 6403 cxgbe_uninit_synchronized(vi); 6404 6405 return (rc); 6406 } 6407 6408 /* 6409 * Idempotent. 6410 */ 6411 static int 6412 cxgbe_uninit_synchronized(struct vi_info *vi) 6413 { 6414 struct port_info *pi = vi->pi; 6415 struct adapter *sc = pi->adapter; 6416 if_t ifp = vi->ifp; 6417 int rc, i; 6418 struct sge_txq *txq; 6419 6420 ASSERT_SYNCHRONIZED_OP(sc); 6421 6422 if (!(vi->flags & VI_INIT_DONE)) { 6423 if (__predict_false(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6424 KASSERT(0, ("uninited VI is running")); 6425 if_printf(ifp, "uninited VI with running ifnet. " 6426 "vi->flags 0x%016lx, if_flags 0x%08x, " 6427 "if_drv_flags 0x%08x\n", vi->flags, if_getflags(ifp), 6428 if_getdrvflags(ifp)); 6429 } 6430 return (0); 6431 } 6432 6433 /* 6434 * Disable the VI so that all its data in either direction is discarded 6435 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 6436 * tick) intact as the TP can deliver negative advice or data that it's 6437 * holding in its RAM (for an offloaded connection) even after the VI is 6438 * disabled. 6439 */ 6440 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 6441 if (rc) { 6442 if_printf(ifp, "disable_vi failed: %d\n", rc); 6443 return (rc); 6444 } 6445 6446 for_each_txq(vi, i, txq) { 6447 TXQ_LOCK(txq); 6448 txq->eq.flags &= ~EQ_ENABLED; 6449 TXQ_UNLOCK(txq); 6450 } 6451 6452 mtx_lock(&vi->tick_mtx); 6453 callout_stop(&vi->tick); 6454 mtx_unlock(&vi->tick_mtx); 6455 6456 PORT_LOCK(pi); 6457 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6458 PORT_UNLOCK(pi); 6459 return (0); 6460 } 6461 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 6462 pi->up_vis--; 6463 if (pi->up_vis > 0) { 6464 PORT_UNLOCK(pi); 6465 return (0); 6466 } 6467 6468 pi->link_cfg.link_ok = false; 6469 pi->link_cfg.speed = 0; 6470 pi->link_cfg.link_down_rc = 255; 6471 t4_os_link_changed(pi); 6472 PORT_UNLOCK(pi); 6473 6474 return (0); 6475 } 6476 6477 /* 6478 * It is ok for this function to fail midway and return right away. t4_detach 6479 * will walk the entire sc->irq list and clean up whatever is valid. 6480 */ 6481 int 6482 t4_setup_intr_handlers(struct adapter *sc) 6483 { 6484 int rc, rid, p, q, v; 6485 char s[8]; 6486 struct irq *irq; 6487 struct port_info *pi; 6488 struct vi_info *vi; 6489 struct sge *sge = &sc->sge; 6490 struct sge_rxq *rxq; 6491 #ifdef TCP_OFFLOAD 6492 struct sge_ofld_rxq *ofld_rxq; 6493 #endif 6494 #ifdef DEV_NETMAP 6495 struct sge_nm_rxq *nm_rxq; 6496 #endif 6497 #ifdef RSS 6498 int nbuckets = rss_getnumbuckets(); 6499 #endif 6500 6501 /* 6502 * Setup interrupts. 6503 */ 6504 irq = &sc->irq[0]; 6505 rid = sc->intr_type == INTR_INTX ? 0 : 1; 6506 if (forwarding_intr_to_fwq(sc)) 6507 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 6508 6509 /* Multiple interrupts. */ 6510 if (sc->flags & IS_VF) 6511 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 6512 ("%s: too few intr.", __func__)); 6513 else 6514 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 6515 ("%s: too few intr.", __func__)); 6516 6517 /* The first one is always error intr on PFs */ 6518 if (!(sc->flags & IS_VF)) { 6519 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 6520 if (rc != 0) 6521 return (rc); 6522 irq++; 6523 rid++; 6524 } 6525 6526 /* The second one is always the firmware event queue (first on VFs) */ 6527 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 6528 if (rc != 0) 6529 return (rc); 6530 irq++; 6531 rid++; 6532 6533 for_each_port(sc, p) { 6534 pi = sc->port[p]; 6535 for_each_vi(pi, v, vi) { 6536 vi->first_intr = rid - 1; 6537 6538 if (vi->nnmrxq > 0) { 6539 int n = max(vi->nrxq, vi->nnmrxq); 6540 6541 rxq = &sge->rxq[vi->first_rxq]; 6542 #ifdef DEV_NETMAP 6543 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 6544 #endif 6545 for (q = 0; q < n; q++) { 6546 snprintf(s, sizeof(s), "%x%c%x", p, 6547 'a' + v, q); 6548 if (q < vi->nrxq) 6549 irq->rxq = rxq++; 6550 #ifdef DEV_NETMAP 6551 if (q < vi->nnmrxq) 6552 irq->nm_rxq = nm_rxq++; 6553 6554 if (irq->nm_rxq != NULL && 6555 irq->rxq == NULL) { 6556 /* Netmap rx only */ 6557 rc = t4_alloc_irq(sc, irq, rid, 6558 t4_nm_intr, irq->nm_rxq, s); 6559 } 6560 if (irq->nm_rxq != NULL && 6561 irq->rxq != NULL) { 6562 /* NIC and Netmap rx */ 6563 rc = t4_alloc_irq(sc, irq, rid, 6564 t4_vi_intr, irq, s); 6565 } 6566 #endif 6567 if (irq->rxq != NULL && 6568 irq->nm_rxq == NULL) { 6569 /* NIC rx only */ 6570 rc = t4_alloc_irq(sc, irq, rid, 6571 t4_intr, irq->rxq, s); 6572 } 6573 if (rc != 0) 6574 return (rc); 6575 #ifdef RSS 6576 if (q < vi->nrxq) { 6577 bus_bind_intr(sc->dev, irq->res, 6578 rss_getcpu(q % nbuckets)); 6579 } 6580 #endif 6581 irq++; 6582 rid++; 6583 vi->nintr++; 6584 } 6585 } else { 6586 for_each_rxq(vi, q, rxq) { 6587 snprintf(s, sizeof(s), "%x%c%x", p, 6588 'a' + v, q); 6589 rc = t4_alloc_irq(sc, irq, rid, 6590 t4_intr, rxq, s); 6591 if (rc != 0) 6592 return (rc); 6593 #ifdef RSS 6594 bus_bind_intr(sc->dev, irq->res, 6595 rss_getcpu(q % nbuckets)); 6596 #endif 6597 irq++; 6598 rid++; 6599 vi->nintr++; 6600 } 6601 } 6602 #ifdef TCP_OFFLOAD 6603 for_each_ofld_rxq(vi, q, ofld_rxq) { 6604 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 6605 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 6606 ofld_rxq, s); 6607 if (rc != 0) 6608 return (rc); 6609 irq++; 6610 rid++; 6611 vi->nintr++; 6612 } 6613 #endif 6614 } 6615 } 6616 MPASS(irq == &sc->irq[sc->intr_count]); 6617 6618 return (0); 6619 } 6620 6621 static void 6622 write_global_rss_key(struct adapter *sc) 6623 { 6624 #ifdef RSS 6625 int i; 6626 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6627 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6628 6629 CTASSERT(RSS_KEYSIZE == 40); 6630 6631 rss_getkey((void *)&raw_rss_key[0]); 6632 for (i = 0; i < nitems(rss_key); i++) { 6633 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 6634 } 6635 t4_write_rss_key(sc, &rss_key[0], -1, 1); 6636 #endif 6637 } 6638 6639 /* 6640 * Idempotent. 6641 */ 6642 static int 6643 adapter_full_init(struct adapter *sc) 6644 { 6645 int rc, i; 6646 6647 ASSERT_SYNCHRONIZED_OP(sc); 6648 6649 /* 6650 * queues that belong to the adapter (not any particular port). 6651 */ 6652 rc = t4_setup_adapter_queues(sc); 6653 if (rc != 0) 6654 return (rc); 6655 6656 for (i = 0; i < nitems(sc->tq); i++) { 6657 if (sc->tq[i] != NULL) 6658 continue; 6659 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 6660 taskqueue_thread_enqueue, &sc->tq[i]); 6661 if (sc->tq[i] == NULL) { 6662 CH_ERR(sc, "failed to allocate task queue %d\n", i); 6663 return (ENOMEM); 6664 } 6665 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 6666 device_get_nameunit(sc->dev), i); 6667 } 6668 6669 if (!(sc->flags & IS_VF)) { 6670 write_global_rss_key(sc); 6671 t4_intr_enable(sc); 6672 } 6673 return (0); 6674 } 6675 6676 int 6677 adapter_init(struct adapter *sc) 6678 { 6679 int rc; 6680 6681 ASSERT_SYNCHRONIZED_OP(sc); 6682 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 6683 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 6684 ("%s: FULL_INIT_DONE already", __func__)); 6685 6686 rc = adapter_full_init(sc); 6687 if (rc != 0) 6688 adapter_full_uninit(sc); 6689 else 6690 sc->flags |= FULL_INIT_DONE; 6691 6692 return (rc); 6693 } 6694 6695 /* 6696 * Idempotent. 6697 */ 6698 static void 6699 adapter_full_uninit(struct adapter *sc) 6700 { 6701 int i; 6702 6703 t4_teardown_adapter_queues(sc); 6704 6705 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 6706 taskqueue_free(sc->tq[i]); 6707 sc->tq[i] = NULL; 6708 } 6709 6710 sc->flags &= ~FULL_INIT_DONE; 6711 } 6712 6713 #ifdef RSS 6714 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 6715 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 6716 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 6717 RSS_HASHTYPE_RSS_UDP_IPV6) 6718 6719 /* Translates kernel hash types to hardware. */ 6720 static int 6721 hashconfig_to_hashen(int hashconfig) 6722 { 6723 int hashen = 0; 6724 6725 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 6726 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 6727 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 6728 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 6729 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 6730 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6731 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6732 } 6733 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 6734 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6735 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6736 } 6737 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 6738 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6739 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 6740 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6741 6742 return (hashen); 6743 } 6744 6745 /* Translates hardware hash types to kernel. */ 6746 static int 6747 hashen_to_hashconfig(int hashen) 6748 { 6749 int hashconfig = 0; 6750 6751 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 6752 /* 6753 * If UDP hashing was enabled it must have been enabled for 6754 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 6755 * enabling any 4-tuple hash is nonsense configuration. 6756 */ 6757 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6758 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 6759 6760 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6761 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 6762 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6763 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 6764 } 6765 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6766 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 6767 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6768 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 6769 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6770 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 6771 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6772 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 6773 6774 return (hashconfig); 6775 } 6776 #endif 6777 6778 /* 6779 * Idempotent. 6780 */ 6781 static int 6782 vi_full_init(struct vi_info *vi) 6783 { 6784 struct adapter *sc = vi->adapter; 6785 struct sge_rxq *rxq; 6786 int rc, i, j; 6787 #ifdef RSS 6788 int nbuckets = rss_getnumbuckets(); 6789 int hashconfig = rss_gethashconfig(); 6790 int extra; 6791 #endif 6792 6793 ASSERT_SYNCHRONIZED_OP(sc); 6794 6795 /* 6796 * Allocate tx/rx/fl queues for this VI. 6797 */ 6798 rc = t4_setup_vi_queues(vi); 6799 if (rc != 0) 6800 return (rc); 6801 6802 /* 6803 * Setup RSS for this VI. Save a copy of the RSS table for later use. 6804 */ 6805 if (vi->nrxq > vi->rss_size) { 6806 CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); " 6807 "some queues will never receive traffic.\n", vi->nrxq, 6808 vi->rss_size); 6809 } else if (vi->rss_size % vi->nrxq) { 6810 CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); " 6811 "expect uneven traffic distribution.\n", vi->nrxq, 6812 vi->rss_size); 6813 } 6814 #ifdef RSS 6815 if (vi->nrxq != nbuckets) { 6816 CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);" 6817 "performance will be impacted.\n", vi->nrxq, nbuckets); 6818 } 6819 #endif 6820 if (vi->rss == NULL) 6821 vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE, 6822 M_ZERO | M_WAITOK); 6823 for (i = 0; i < vi->rss_size;) { 6824 #ifdef RSS 6825 j = rss_get_indirection_to_bucket(i); 6826 j %= vi->nrxq; 6827 rxq = &sc->sge.rxq[vi->first_rxq + j]; 6828 vi->rss[i++] = rxq->iq.abs_id; 6829 #else 6830 for_each_rxq(vi, j, rxq) { 6831 vi->rss[i++] = rxq->iq.abs_id; 6832 if (i == vi->rss_size) 6833 break; 6834 } 6835 #endif 6836 } 6837 6838 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 6839 vi->rss, vi->rss_size); 6840 if (rc != 0) { 6841 CH_ERR(vi, "rss_config failed: %d\n", rc); 6842 return (rc); 6843 } 6844 6845 #ifdef RSS 6846 vi->hashen = hashconfig_to_hashen(hashconfig); 6847 6848 /* 6849 * We may have had to enable some hashes even though the global config 6850 * wants them disabled. This is a potential problem that must be 6851 * reported to the user. 6852 */ 6853 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 6854 6855 /* 6856 * If we consider only the supported hash types, then the enabled hashes 6857 * are a superset of the requested hashes. In other words, there cannot 6858 * be any supported hash that was requested but not enabled, but there 6859 * can be hashes that were not requested but had to be enabled. 6860 */ 6861 extra &= SUPPORTED_RSS_HASHTYPES; 6862 MPASS((extra & hashconfig) == 0); 6863 6864 if (extra) { 6865 CH_ALERT(vi, 6866 "global RSS config (0x%x) cannot be accommodated.\n", 6867 hashconfig); 6868 } 6869 if (extra & RSS_HASHTYPE_RSS_IPV4) 6870 CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n"); 6871 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 6872 CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n"); 6873 if (extra & RSS_HASHTYPE_RSS_IPV6) 6874 CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n"); 6875 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 6876 CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n"); 6877 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 6878 CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n"); 6879 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 6880 CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n"); 6881 #else 6882 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 6883 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 6884 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6885 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 6886 #endif 6887 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 6888 0, 0); 6889 if (rc != 0) { 6890 CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc); 6891 return (rc); 6892 } 6893 6894 return (0); 6895 } 6896 6897 int 6898 vi_init(struct vi_info *vi) 6899 { 6900 int rc; 6901 6902 ASSERT_SYNCHRONIZED_OP(vi->adapter); 6903 KASSERT((vi->flags & VI_INIT_DONE) == 0, 6904 ("%s: VI_INIT_DONE already", __func__)); 6905 6906 rc = vi_full_init(vi); 6907 if (rc != 0) 6908 vi_full_uninit(vi); 6909 else 6910 vi->flags |= VI_INIT_DONE; 6911 6912 return (rc); 6913 } 6914 6915 /* 6916 * Idempotent. 6917 */ 6918 static void 6919 vi_full_uninit(struct vi_info *vi) 6920 { 6921 6922 if (vi->flags & VI_INIT_DONE) { 6923 quiesce_vi(vi); 6924 free(vi->rss, M_CXGBE); 6925 free(vi->nm_rss, M_CXGBE); 6926 } 6927 6928 t4_teardown_vi_queues(vi); 6929 vi->flags &= ~VI_INIT_DONE; 6930 } 6931 6932 static void 6933 quiesce_txq(struct sge_txq *txq) 6934 { 6935 struct sge_eq *eq = &txq->eq; 6936 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6937 6938 MPASS(eq->flags & EQ_SW_ALLOCATED); 6939 MPASS(!(eq->flags & EQ_ENABLED)); 6940 6941 /* Wait for the mp_ring to empty. */ 6942 while (!mp_ring_is_idle(txq->r)) { 6943 mp_ring_check_drainage(txq->r, 4096); 6944 pause("rquiesce", 1); 6945 } 6946 MPASS(txq->txp.npkt == 0); 6947 6948 if (eq->flags & EQ_HW_ALLOCATED) { 6949 /* 6950 * Hardware is alive and working normally. Wait for it to 6951 * finish and then wait for the driver to catch up and reclaim 6952 * all descriptors. 6953 */ 6954 while (spg->cidx != htobe16(eq->pidx)) 6955 pause("equiesce", 1); 6956 while (eq->cidx != eq->pidx) 6957 pause("dquiesce", 1); 6958 } else { 6959 /* 6960 * Hardware is unavailable. Discard all pending tx and reclaim 6961 * descriptors directly. 6962 */ 6963 TXQ_LOCK(txq); 6964 while (eq->cidx != eq->pidx) { 6965 struct mbuf *m, *nextpkt; 6966 struct tx_sdesc *txsd; 6967 6968 txsd = &txq->sdesc[eq->cidx]; 6969 for (m = txsd->m; m != NULL; m = nextpkt) { 6970 nextpkt = m->m_nextpkt; 6971 m->m_nextpkt = NULL; 6972 m_freem(m); 6973 } 6974 IDXINCR(eq->cidx, txsd->desc_used, eq->sidx); 6975 } 6976 spg->pidx = spg->cidx = htobe16(eq->cidx); 6977 TXQ_UNLOCK(txq); 6978 } 6979 } 6980 6981 static void 6982 quiesce_wrq(struct sge_wrq *wrq) 6983 { 6984 6985 /* XXXTX */ 6986 } 6987 6988 static void 6989 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 6990 { 6991 /* Synchronize with the interrupt handler */ 6992 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 6993 pause("iqfree", 1); 6994 6995 if (fl != NULL) { 6996 MPASS(iq->flags & IQ_HAS_FL); 6997 6998 mtx_lock(&sc->sfl_lock); 6999 FL_LOCK(fl); 7000 fl->flags |= FL_DOOMED; 7001 FL_UNLOCK(fl); 7002 callout_stop(&sc->sfl_callout); 7003 mtx_unlock(&sc->sfl_lock); 7004 7005 KASSERT((fl->flags & FL_STARVING) == 0, 7006 ("%s: still starving", __func__)); 7007 7008 /* Release all buffers if hardware is no longer available. */ 7009 if (!(iq->flags & IQ_HW_ALLOCATED)) 7010 free_fl_buffers(sc, fl); 7011 } 7012 } 7013 7014 /* 7015 * Wait for all activity on all the queues of the VI to complete. It is assumed 7016 * that no new work is being enqueued by the hardware or the driver. That part 7017 * should be arranged before calling this function. 7018 */ 7019 static void 7020 quiesce_vi(struct vi_info *vi) 7021 { 7022 int i; 7023 struct adapter *sc = vi->adapter; 7024 struct sge_rxq *rxq; 7025 struct sge_txq *txq; 7026 #ifdef TCP_OFFLOAD 7027 struct sge_ofld_rxq *ofld_rxq; 7028 #endif 7029 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7030 struct sge_ofld_txq *ofld_txq; 7031 #endif 7032 7033 if (!(vi->flags & VI_INIT_DONE)) 7034 return; 7035 7036 for_each_txq(vi, i, txq) { 7037 quiesce_txq(txq); 7038 } 7039 7040 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7041 for_each_ofld_txq(vi, i, ofld_txq) { 7042 quiesce_wrq(&ofld_txq->wrq); 7043 } 7044 #endif 7045 7046 for_each_rxq(vi, i, rxq) { 7047 quiesce_iq_fl(sc, &rxq->iq, &rxq->fl); 7048 } 7049 7050 #ifdef TCP_OFFLOAD 7051 for_each_ofld_rxq(vi, i, ofld_rxq) { 7052 quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl); 7053 } 7054 #endif 7055 } 7056 7057 static int 7058 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 7059 driver_intr_t *handler, void *arg, char *name) 7060 { 7061 int rc; 7062 7063 irq->rid = rid; 7064 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 7065 RF_SHAREABLE | RF_ACTIVE); 7066 if (irq->res == NULL) { 7067 device_printf(sc->dev, 7068 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 7069 return (ENOMEM); 7070 } 7071 7072 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 7073 NULL, handler, arg, &irq->tag); 7074 if (rc != 0) { 7075 device_printf(sc->dev, 7076 "failed to setup interrupt for rid %d, name %s: %d\n", 7077 rid, name, rc); 7078 } else if (name) 7079 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 7080 7081 return (rc); 7082 } 7083 7084 static int 7085 t4_free_irq(struct adapter *sc, struct irq *irq) 7086 { 7087 if (irq->tag) 7088 bus_teardown_intr(sc->dev, irq->res, irq->tag); 7089 if (irq->res) 7090 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 7091 7092 bzero(irq, sizeof(*irq)); 7093 7094 return (0); 7095 } 7096 7097 static void 7098 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 7099 { 7100 7101 regs->version = chip_id(sc) | chip_rev(sc) << 10; 7102 t4_get_regs(sc, buf, regs->len); 7103 } 7104 7105 #define A_PL_INDIR_CMD 0x1f8 7106 7107 #define S_PL_AUTOINC 31 7108 #define M_PL_AUTOINC 0x1U 7109 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 7110 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 7111 7112 #define S_PL_VFID 20 7113 #define M_PL_VFID 0xffU 7114 #define V_PL_VFID(x) ((x) << S_PL_VFID) 7115 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 7116 7117 #define S_PL_ADDR 0 7118 #define M_PL_ADDR 0xfffffU 7119 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 7120 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 7121 7122 #define A_PL_INDIR_DATA 0x1fc 7123 7124 static uint64_t 7125 read_vf_stat(struct adapter *sc, u_int vin, int reg) 7126 { 7127 u32 stats[2]; 7128 7129 if (sc->flags & IS_VF) { 7130 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 7131 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 7132 } else { 7133 mtx_assert(&sc->reg_lock, MA_OWNED); 7134 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 7135 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 7136 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 7137 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 7138 } 7139 return (((uint64_t)stats[1]) << 32 | stats[0]); 7140 } 7141 7142 static void 7143 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 7144 { 7145 7146 #define GET_STAT(name) \ 7147 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 7148 7149 if (!(sc->flags & IS_VF)) 7150 mtx_lock(&sc->reg_lock); 7151 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 7152 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 7153 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 7154 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 7155 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 7156 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 7157 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 7158 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 7159 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 7160 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 7161 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 7162 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 7163 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 7164 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 7165 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 7166 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 7167 if (!(sc->flags & IS_VF)) 7168 mtx_unlock(&sc->reg_lock); 7169 7170 #undef GET_STAT 7171 } 7172 7173 static void 7174 t4_clr_vi_stats(struct adapter *sc, u_int vin) 7175 { 7176 int reg; 7177 7178 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 7179 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 7180 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 7181 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 7182 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 7183 } 7184 7185 static void 7186 vi_refresh_stats(struct vi_info *vi) 7187 { 7188 struct timeval tv; 7189 const struct timeval interval = {0, 250000}; /* 250ms */ 7190 7191 mtx_assert(&vi->tick_mtx, MA_OWNED); 7192 7193 if (vi->flags & VI_SKIP_STATS) 7194 return; 7195 7196 getmicrotime(&tv); 7197 timevalsub(&tv, &interval); 7198 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7199 return; 7200 7201 t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats); 7202 getmicrotime(&vi->last_refreshed); 7203 } 7204 7205 static void 7206 cxgbe_refresh_stats(struct vi_info *vi) 7207 { 7208 u_int i, v, tnl_cong_drops, chan_map; 7209 struct timeval tv; 7210 const struct timeval interval = {0, 250000}; /* 250ms */ 7211 struct port_info *pi; 7212 struct adapter *sc; 7213 7214 mtx_assert(&vi->tick_mtx, MA_OWNED); 7215 7216 if (vi->flags & VI_SKIP_STATS) 7217 return; 7218 7219 getmicrotime(&tv); 7220 timevalsub(&tv, &interval); 7221 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7222 return; 7223 7224 pi = vi->pi; 7225 sc = vi->adapter; 7226 tnl_cong_drops = 0; 7227 t4_get_port_stats(sc, pi->port_id, &pi->stats); 7228 chan_map = pi->rx_e_chan_map; 7229 while (chan_map) { 7230 i = ffs(chan_map) - 1; 7231 mtx_lock(&sc->reg_lock); 7232 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 7233 A_TP_MIB_TNL_CNG_DROP_0 + i); 7234 mtx_unlock(&sc->reg_lock); 7235 tnl_cong_drops += v; 7236 chan_map &= ~(1 << i); 7237 } 7238 pi->tnl_cong_drops = tnl_cong_drops; 7239 getmicrotime(&vi->last_refreshed); 7240 } 7241 7242 static void 7243 cxgbe_tick(void *arg) 7244 { 7245 struct vi_info *vi = arg; 7246 7247 MPASS(IS_MAIN_VI(vi)); 7248 mtx_assert(&vi->tick_mtx, MA_OWNED); 7249 7250 cxgbe_refresh_stats(vi); 7251 callout_schedule(&vi->tick, hz); 7252 } 7253 7254 static void 7255 vi_tick(void *arg) 7256 { 7257 struct vi_info *vi = arg; 7258 7259 mtx_assert(&vi->tick_mtx, MA_OWNED); 7260 7261 vi_refresh_stats(vi); 7262 callout_schedule(&vi->tick, hz); 7263 } 7264 7265 /* 7266 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 7267 */ 7268 static char *caps_decoder[] = { 7269 "\20\001IPMI\002NCSI", /* 0: NBM */ 7270 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 7271 "\20\001INGRESS\002EGRESS", /* 2: switch */ 7272 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 7273 "\006HASHFILTER\007ETHOFLD", 7274 "\20\001TOE", /* 4: TOE */ 7275 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 7276 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 7277 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 7278 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 7279 "\007T10DIF" 7280 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 7281 "\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE" /* 7: Crypto */ 7282 "\004TLS_HW", 7283 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 7284 "\004PO_INITIATOR\005PO_TARGET", 7285 }; 7286 7287 void 7288 t4_sysctls(struct adapter *sc) 7289 { 7290 struct sysctl_ctx_list *ctx = &sc->ctx; 7291 struct sysctl_oid *oid; 7292 struct sysctl_oid_list *children, *c0; 7293 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 7294 7295 /* 7296 * dev.t4nex.X. 7297 */ 7298 oid = device_get_sysctl_tree(sc->dev); 7299 c0 = children = SYSCTL_CHILDREN(oid); 7300 7301 sc->sc_do_rxcopy = 1; 7302 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 7303 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 7304 7305 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 7306 sc->params.nports, "# of ports"); 7307 7308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 7309 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells, 7310 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A", 7311 "available doorbells"); 7312 7313 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 7314 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 7315 7316 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 7317 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7318 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val), 7319 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 7320 7321 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 7322 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7323 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val), 7324 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 7325 7326 t4_sge_sysctls(sc, ctx, children); 7327 7328 sc->lro_timeout = 100; 7329 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 7330 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 7331 7332 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 7333 &sc->debug_flags, 0, "flags to enable runtime debugging"); 7334 7335 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 7336 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 7337 7338 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 7339 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 7340 7341 if (sc->flags & IS_VF) 7342 return; 7343 7344 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 7345 NULL, chip_rev(sc), "chip hardware revision"); 7346 7347 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 7348 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 7349 7350 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 7351 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 7352 7353 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 7354 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 7355 7356 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 7357 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 7358 7359 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 7360 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 7361 7362 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 7363 sc->er_version, 0, "expansion ROM version"); 7364 7365 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 7366 sc->bs_version, 0, "bootstrap firmware version"); 7367 7368 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 7369 NULL, sc->params.scfg_vers, "serial config version"); 7370 7371 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 7372 NULL, sc->params.vpd_vers, "VPD version"); 7373 7374 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 7375 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 7376 7377 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 7378 sc->cfcsum, "config file checksum"); 7379 7380 #define SYSCTL_CAP(name, n, text) \ 7381 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 7382 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \ 7383 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \ 7384 "available " text " capabilities") 7385 7386 SYSCTL_CAP(nbmcaps, 0, "NBM"); 7387 SYSCTL_CAP(linkcaps, 1, "link"); 7388 SYSCTL_CAP(switchcaps, 2, "switch"); 7389 SYSCTL_CAP(niccaps, 3, "NIC"); 7390 SYSCTL_CAP(toecaps, 4, "TCP offload"); 7391 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 7392 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 7393 SYSCTL_CAP(cryptocaps, 7, "crypto"); 7394 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 7395 #undef SYSCTL_CAP 7396 7397 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 7398 NULL, sc->tids.nftids, "number of filters"); 7399 7400 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7401 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7402 sysctl_temperature, "I", "chip temperature (in Celsius)"); 7403 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", 7404 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7405 sysctl_reset_sensor, "I", "reset the chip's temperature sensor."); 7406 7407 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", 7408 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7409 sysctl_loadavg, "A", 7410 "microprocessor load averages (debug firmwares only)"); 7411 7412 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", 7413 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd, 7414 "I", "core Vdd (in mV)"); 7415 7416 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 7417 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS, 7418 sysctl_cpus, "A", "local CPUs"); 7419 7420 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 7421 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS, 7422 sysctl_cpus, "A", "preferred CPUs for interrupts"); 7423 7424 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 7425 &sc->swintr, 0, "software triggered interrupts"); 7426 7427 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset", 7428 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I", 7429 "1 = reset adapter, 0 = zero reset counter"); 7430 7431 /* 7432 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 7433 */ 7434 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 7435 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL, 7436 "logs and miscellaneous information"); 7437 children = SYSCTL_CHILDREN(oid); 7438 7439 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 7440 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7441 sysctl_cctrl, "A", "congestion control"); 7442 7443 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 7444 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7445 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 7446 7447 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 7448 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7449 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 7450 7451 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 7452 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7453 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 7454 7455 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 7456 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3, 7457 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 7458 7459 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 7460 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4, 7461 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 7462 7463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 7464 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5, 7465 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 7466 7467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 7468 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7469 sysctl_cim_la, "A", "CIM logic analyzer"); 7470 7471 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 7472 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7473 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 7474 7475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 7476 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7477 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 7478 7479 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 7480 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7481 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 7482 7483 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 7484 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7485 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 7486 7487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 7488 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7489 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 7490 7491 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 7492 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7493 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 7494 7495 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 7496 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7497 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 7498 7499 if (chip_id(sc) > CHELSIO_T4) { 7500 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 7501 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7502 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7503 "CIM OBQ 6 (SGE0-RX)"); 7504 7505 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 7506 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7507 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7508 "CIM OBQ 7 (SGE1-RX)"); 7509 } 7510 7511 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 7512 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7513 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 7514 7515 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 7516 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7517 sysctl_cim_qcfg, "A", "CIM queue configuration"); 7518 7519 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 7520 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7521 sysctl_cpl_stats, "A", "CPL statistics"); 7522 7523 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 7524 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7525 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 7526 7527 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats", 7528 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7529 sysctl_tid_stats, "A", "tid stats"); 7530 7531 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 7532 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7533 sysctl_devlog, "A", "firmware's device log"); 7534 7535 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 7536 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7537 sysctl_fcoe_stats, "A", "FCoE statistics"); 7538 7539 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 7540 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7541 sysctl_hw_sched, "A", "hardware scheduler "); 7542 7543 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 7544 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7545 sysctl_l2t, "A", "hardware L2 table"); 7546 7547 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 7548 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7549 sysctl_smt, "A", "hardware source MAC table"); 7550 7551 #ifdef INET6 7552 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 7553 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7554 sysctl_clip, "A", "active CLIP table entries"); 7555 #endif 7556 7557 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 7558 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7559 sysctl_lb_stats, "A", "loopback statistics"); 7560 7561 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 7562 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7563 sysctl_meminfo, "A", "memory regions"); 7564 7565 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 7566 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7567 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 7568 "A", "MPS TCAM entries"); 7569 7570 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 7571 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7572 sysctl_path_mtus, "A", "path MTUs"); 7573 7574 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 7575 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7576 sysctl_pm_stats, "A", "PM statistics"); 7577 7578 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 7579 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7580 sysctl_rdma_stats, "A", "RDMA statistics"); 7581 7582 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 7583 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7584 sysctl_tcp_stats, "A", "TCP statistics"); 7585 7586 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 7587 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7588 sysctl_tids, "A", "TID information"); 7589 7590 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 7591 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7592 sysctl_tp_err_stats, "A", "TP error statistics"); 7593 7594 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats", 7595 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7596 sysctl_tnl_stats, "A", "TP tunnel statistics"); 7597 7598 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 7599 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7600 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask"); 7601 7602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 7603 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7604 sysctl_tp_la, "A", "TP logic analyzer"); 7605 7606 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 7607 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7608 sysctl_tx_rate, "A", "Tx rate"); 7609 7610 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 7611 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7612 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 7613 7614 if (chip_id(sc) >= CHELSIO_T5) { 7615 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 7616 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7617 sysctl_wcwr_stats, "A", "write combined work requests"); 7618 } 7619 7620 #ifdef KERN_TLS 7621 if (is_ktls(sc)) { 7622 /* 7623 * dev.t4nex.0.tls. 7624 */ 7625 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", 7626 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters"); 7627 children = SYSCTL_CHILDREN(oid); 7628 7629 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys", 7630 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS " 7631 "keys in work requests (1) or attempt to store TLS keys " 7632 "in card memory."); 7633 7634 if (is_t6(sc)) 7635 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs", 7636 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to " 7637 "combine TCB field updates with TLS record work " 7638 "requests."); 7639 } 7640 #endif 7641 7642 #ifdef TCP_OFFLOAD 7643 if (is_offload(sc)) { 7644 int i; 7645 char s[4]; 7646 7647 /* 7648 * dev.t4nex.X.toe. 7649 */ 7650 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", 7651 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters"); 7652 children = SYSCTL_CHILDREN(oid); 7653 7654 sc->tt.cong_algorithm = -1; 7655 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 7656 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 7657 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 7658 "3 = highspeed)"); 7659 7660 sc->tt.sndbuf = -1; 7661 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 7662 &sc->tt.sndbuf, 0, "hardware send buffer"); 7663 7664 sc->tt.ddp = 0; 7665 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", 7666 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, ""); 7667 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW, 7668 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)"); 7669 7670 sc->tt.rx_coalesce = -1; 7671 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 7672 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 7673 7674 sc->tt.tls = 0; 7675 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT | 7676 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I", 7677 "Inline TLS allowed"); 7678 7679 sc->tt.tx_align = -1; 7680 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 7681 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 7682 7683 sc->tt.tx_zcopy = 0; 7684 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 7685 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 7686 "Enable zero-copy aio_write(2)"); 7687 7688 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 7689 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7690 "cop_managed_offloading", CTLFLAG_RW, 7691 &sc->tt.cop_managed_offloading, 0, 7692 "COP (Connection Offload Policy) controls all TOE offload"); 7693 7694 sc->tt.autorcvbuf_inc = 16 * 1024; 7695 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 7696 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 7697 "autorcvbuf increment"); 7698 7699 sc->tt.update_hc_on_pmtu_change = 1; 7700 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7701 "update_hc_on_pmtu_change", CTLFLAG_RW, 7702 &sc->tt.update_hc_on_pmtu_change, 0, 7703 "Update hostcache entry if the PMTU changes"); 7704 7705 sc->tt.iso = 1; 7706 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW, 7707 &sc->tt.iso, 0, "Enable iSCSI segmentation offload"); 7708 7709 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 7710 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7711 sysctl_tp_tick, "A", "TP timer tick (us)"); 7712 7713 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 7714 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7715 sysctl_tp_tick, "A", "TCP timestamp tick (us)"); 7716 7717 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 7718 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7719 sysctl_tp_tick, "A", "DACK tick (us)"); 7720 7721 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 7722 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7723 sysctl_tp_dack_timer, "IU", "DACK timer (us)"); 7724 7725 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 7726 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7727 A_TP_RXT_MIN, sysctl_tp_timer, "LU", 7728 "Minimum retransmit interval (us)"); 7729 7730 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 7731 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7732 A_TP_RXT_MAX, sysctl_tp_timer, "LU", 7733 "Maximum retransmit interval (us)"); 7734 7735 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 7736 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7737 A_TP_PERS_MIN, sysctl_tp_timer, "LU", 7738 "Persist timer min (us)"); 7739 7740 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 7741 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7742 A_TP_PERS_MAX, sysctl_tp_timer, "LU", 7743 "Persist timer max (us)"); 7744 7745 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 7746 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7747 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU", 7748 "Keepalive idle timer (us)"); 7749 7750 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 7751 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7752 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU", 7753 "Keepalive interval timer (us)"); 7754 7755 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 7756 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7757 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)"); 7758 7759 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 7760 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7761 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU", 7762 "FINWAIT2 timer (us)"); 7763 7764 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 7765 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7766 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU", 7767 "Number of SYN retransmissions before abort"); 7768 7769 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 7770 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7771 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU", 7772 "Number of retransmissions before abort"); 7773 7774 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 7775 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7776 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU", 7777 "Number of keepalive probes before abort"); 7778 7779 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 7780 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7781 "TOE retransmit backoffs"); 7782 children = SYSCTL_CHILDREN(oid); 7783 for (i = 0; i < 16; i++) { 7784 snprintf(s, sizeof(s), "%u", i); 7785 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 7786 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7787 i, sysctl_tp_backoff, "IU", 7788 "TOE retransmit backoff"); 7789 } 7790 } 7791 #endif 7792 } 7793 7794 void 7795 vi_sysctls(struct vi_info *vi) 7796 { 7797 struct sysctl_ctx_list *ctx = &vi->ctx; 7798 struct sysctl_oid *oid; 7799 struct sysctl_oid_list *children; 7800 7801 /* 7802 * dev.v?(cxgbe|cxl).X. 7803 */ 7804 oid = device_get_sysctl_tree(vi->dev); 7805 children = SYSCTL_CHILDREN(oid); 7806 7807 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 7808 vi->viid, "VI identifer"); 7809 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 7810 &vi->nrxq, 0, "# of rx queues"); 7811 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 7812 &vi->ntxq, 0, "# of tx queues"); 7813 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 7814 &vi->first_rxq, 0, "index of first rx queue"); 7815 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 7816 &vi->first_txq, 0, "index of first tx queue"); 7817 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 7818 vi->rss_base, "start of RSS indirection table"); 7819 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 7820 vi->rss_size, "size of RSS indirection table"); 7821 7822 if (IS_MAIN_VI(vi)) { 7823 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 7824 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7825 sysctl_noflowq, "IU", 7826 "Reserve queue 0 for non-flowid packets"); 7827 } 7828 7829 if (vi->adapter->flags & IS_VF) { 7830 MPASS(vi->flags & TX_USES_VM_WR); 7831 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD, 7832 NULL, 1, "use VM work requests for transmit"); 7833 } else { 7834 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr", 7835 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7836 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit"); 7837 } 7838 7839 #ifdef TCP_OFFLOAD 7840 if (vi->nofldrxq != 0) { 7841 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 7842 &vi->nofldrxq, 0, 7843 "# of rx queues for offloaded TCP connections"); 7844 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 7845 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 7846 "index of first TOE rx queue"); 7847 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 7848 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7849 sysctl_holdoff_tmr_idx_ofld, "I", 7850 "holdoff timer index for TOE queues"); 7851 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 7852 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7853 sysctl_holdoff_pktc_idx_ofld, "I", 7854 "holdoff packet counter index for TOE queues"); 7855 } 7856 #endif 7857 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7858 if (vi->nofldtxq != 0) { 7859 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 7860 &vi->nofldtxq, 0, 7861 "# of tx queues for TOE/ETHOFLD"); 7862 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 7863 CTLFLAG_RD, &vi->first_ofld_txq, 0, 7864 "index of first TOE/ETHOFLD tx queue"); 7865 } 7866 #endif 7867 #ifdef DEV_NETMAP 7868 if (vi->nnmrxq != 0) { 7869 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 7870 &vi->nnmrxq, 0, "# of netmap rx queues"); 7871 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 7872 &vi->nnmtxq, 0, "# of netmap tx queues"); 7873 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 7874 CTLFLAG_RD, &vi->first_nm_rxq, 0, 7875 "index of first netmap rx queue"); 7876 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 7877 CTLFLAG_RD, &vi->first_nm_txq, 0, 7878 "index of first netmap tx queue"); 7879 } 7880 #endif 7881 7882 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 7883 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7884 sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); 7885 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 7886 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7887 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); 7888 7889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 7890 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7891 sysctl_qsize_rxq, "I", "rx queue size"); 7892 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 7893 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7894 sysctl_qsize_txq, "I", "tx queue size"); 7895 } 7896 7897 static void 7898 cxgbe_sysctls(struct port_info *pi) 7899 { 7900 struct sysctl_ctx_list *ctx = &pi->ctx; 7901 struct sysctl_oid *oid; 7902 struct sysctl_oid_list *children, *children2; 7903 struct adapter *sc = pi->adapter; 7904 int i; 7905 char name[16]; 7906 static char *tc_flags = {"\20\1USER"}; 7907 7908 /* 7909 * dev.cxgbe.X. 7910 */ 7911 oid = device_get_sysctl_tree(pi->dev); 7912 children = SYSCTL_CHILDREN(oid); 7913 7914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", 7915 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 7916 sysctl_linkdnrc, "A", "reason why link is down"); 7917 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 7918 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7919 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 7920 sysctl_btphy, "I", "PHY temperature (in Celsius)"); 7921 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 7922 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1, 7923 sysctl_btphy, "I", "PHY firmware version"); 7924 } 7925 7926 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 7927 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7928 sysctl_pause_settings, "A", 7929 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 7930 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec", 7931 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A", 7932 "FEC in use on the link"); 7933 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec", 7934 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7935 sysctl_requested_fec, "A", 7936 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)"); 7937 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec", 7938 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A", 7939 "FEC recommended by the cable/transceiver"); 7940 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 7941 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7942 sysctl_autoneg, "I", 7943 "autonegotiation (-1 = not supported)"); 7944 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec", 7945 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7946 sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config"); 7947 7948 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD, 7949 &pi->link_cfg.requested_caps, 0, "L1 config requested by driver"); 7950 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD, 7951 &pi->link_cfg.pcaps, 0, "port capabilities"); 7952 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD, 7953 &pi->link_cfg.acaps, 0, "advertised capabilities"); 7954 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD, 7955 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities"); 7956 7957 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 7958 port_top_speed(pi), "max speed (in Gbps)"); 7959 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 7960 pi->mps_bg_map, "MPS buffer group map"); 7961 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 7962 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 7963 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_c_chan", CTLFLAG_RD, NULL, 7964 pi->rx_c_chan, "TP rx c-channel"); 7965 7966 if (sc->flags & IS_VF) 7967 return; 7968 7969 /* 7970 * dev.(cxgbe|cxl).X.tc. 7971 */ 7972 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", 7973 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7974 "Tx scheduler traffic classes (cl_rl)"); 7975 children2 = SYSCTL_CHILDREN(oid); 7976 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 7977 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 7978 "pktsize for per-flow cl-rl (0 means up to the driver )"); 7979 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 7980 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 7981 "burstsize for per-flow cl-rl (0 means up to the driver)"); 7982 for (i = 0; i < sc->params.nsched_cls; i++) { 7983 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 7984 7985 snprintf(name, sizeof(name), "%d", i); 7986 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 7987 SYSCTL_CHILDREN(oid), OID_AUTO, name, 7988 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class")); 7989 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state", 7990 CTLFLAG_RD, &tc->state, 0, "current state"); 7991 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 7992 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags, 7993 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags"); 7994 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 7995 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 7996 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 7997 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7998 (pi->port_id << 16) | i, sysctl_tc_params, "A", 7999 "traffic class parameters"); 8000 } 8001 8002 /* 8003 * dev.cxgbe.X.stats. 8004 */ 8005 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 8006 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics"); 8007 children = SYSCTL_CHILDREN(oid); 8008 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 8009 &pi->tx_parse_error, 0, 8010 "# of tx packets with invalid length or # of segments"); 8011 8012 #define T4_REGSTAT(name, stat, desc) \ 8013 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \ 8014 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \ 8015 (is_t4(sc) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L) : \ 8016 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L)), \ 8017 sysctl_handle_t4_reg64, "QU", desc) 8018 8019 /* We get these from port_stats and they may be stale by up to 1s */ 8020 #define T4_PORTSTAT(name, desc) \ 8021 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 8022 &pi->stats.name, desc) 8023 8024 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames"); 8025 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames"); 8026 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames"); 8027 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames"); 8028 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames"); 8029 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames"); 8030 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range"); 8031 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range"); 8032 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range"); 8033 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range"); 8034 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range"); 8035 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range"); 8036 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range"); 8037 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames"); 8038 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted"); 8039 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted"); 8040 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted"); 8041 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted"); 8042 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted"); 8043 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted"); 8044 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted"); 8045 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted"); 8046 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted"); 8047 8048 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames"); 8049 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames"); 8050 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames"); 8051 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames"); 8052 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames"); 8053 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU"); 8054 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames"); 8055 if (is_t6(sc)) { 8056 T4_PORTSTAT(rx_fcs_err, 8057 "# of frames received with bad FCS since last link up"); 8058 } else { 8059 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR, 8060 "# of frames received with bad FCS"); 8061 } 8062 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error"); 8063 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors"); 8064 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received"); 8065 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range"); 8066 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range"); 8067 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range"); 8068 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range"); 8069 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range"); 8070 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range"); 8071 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range"); 8072 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received"); 8073 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received"); 8074 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received"); 8075 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received"); 8076 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received"); 8077 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received"); 8078 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received"); 8079 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received"); 8080 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received"); 8081 8082 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows"); 8083 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows"); 8084 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows"); 8085 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows"); 8086 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets"); 8087 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets"); 8088 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets"); 8089 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets"); 8090 8091 #undef T4_REGSTAT 8092 #undef T4_PORTSTAT 8093 } 8094 8095 static int 8096 sysctl_int_array(SYSCTL_HANDLER_ARGS) 8097 { 8098 int rc, *i, space = 0; 8099 struct sbuf sb; 8100 8101 sbuf_new_for_sysctl(&sb, NULL, 64, req); 8102 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 8103 if (space) 8104 sbuf_printf(&sb, " "); 8105 sbuf_printf(&sb, "%d", *i); 8106 space = 1; 8107 } 8108 rc = sbuf_finish(&sb); 8109 sbuf_delete(&sb); 8110 return (rc); 8111 } 8112 8113 static int 8114 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 8115 { 8116 int rc; 8117 struct sbuf *sb; 8118 8119 rc = sysctl_wire_old_buffer(req, 0); 8120 if (rc != 0) 8121 return(rc); 8122 8123 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8124 if (sb == NULL) 8125 return (ENOMEM); 8126 8127 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 8128 rc = sbuf_finish(sb); 8129 sbuf_delete(sb); 8130 8131 return (rc); 8132 } 8133 8134 static int 8135 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 8136 { 8137 int rc; 8138 struct sbuf *sb; 8139 8140 rc = sysctl_wire_old_buffer(req, 0); 8141 if (rc != 0) 8142 return(rc); 8143 8144 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8145 if (sb == NULL) 8146 return (ENOMEM); 8147 8148 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 8149 rc = sbuf_finish(sb); 8150 sbuf_delete(sb); 8151 8152 return (rc); 8153 } 8154 8155 static int 8156 sysctl_btphy(SYSCTL_HANDLER_ARGS) 8157 { 8158 struct port_info *pi = arg1; 8159 int op = arg2; 8160 struct adapter *sc = pi->adapter; 8161 u_int v; 8162 int rc; 8163 8164 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 8165 if (rc) 8166 return (rc); 8167 if (hw_off_limits(sc)) 8168 rc = ENXIO; 8169 else { 8170 /* XXX: magic numbers */ 8171 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, 8172 op ? 0x20 : 0xc820, &v); 8173 } 8174 end_synchronized_op(sc, 0); 8175 if (rc) 8176 return (rc); 8177 if (op == 0) 8178 v /= 256; 8179 8180 rc = sysctl_handle_int(oidp, &v, 0, req); 8181 return (rc); 8182 } 8183 8184 static int 8185 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 8186 { 8187 struct vi_info *vi = arg1; 8188 int rc, val; 8189 8190 val = vi->rsrv_noflowq; 8191 rc = sysctl_handle_int(oidp, &val, 0, req); 8192 if (rc != 0 || req->newptr == NULL) 8193 return (rc); 8194 8195 if ((val >= 1) && (vi->ntxq > 1)) 8196 vi->rsrv_noflowq = 1; 8197 else 8198 vi->rsrv_noflowq = 0; 8199 8200 return (rc); 8201 } 8202 8203 static int 8204 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS) 8205 { 8206 struct vi_info *vi = arg1; 8207 struct adapter *sc = vi->adapter; 8208 int rc, val, i; 8209 8210 MPASS(!(sc->flags & IS_VF)); 8211 8212 val = vi->flags & TX_USES_VM_WR ? 1 : 0; 8213 rc = sysctl_handle_int(oidp, &val, 0, req); 8214 if (rc != 0 || req->newptr == NULL) 8215 return (rc); 8216 8217 if (val != 0 && val != 1) 8218 return (EINVAL); 8219 8220 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8221 "t4txvm"); 8222 if (rc) 8223 return (rc); 8224 if (hw_off_limits(sc)) 8225 rc = ENXIO; 8226 else if (if_getdrvflags(vi->ifp) & IFF_DRV_RUNNING) { 8227 /* 8228 * We don't want parse_pkt to run with one setting (VF or PF) 8229 * and then eth_tx to see a different setting but still use 8230 * stale information calculated by parse_pkt. 8231 */ 8232 rc = EBUSY; 8233 } else { 8234 struct port_info *pi = vi->pi; 8235 struct sge_txq *txq; 8236 uint32_t ctrl0; 8237 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr; 8238 8239 if (val) { 8240 vi->flags |= TX_USES_VM_WR; 8241 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO); 8242 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8243 V_TXPKT_INTF(pi->tx_chan)); 8244 if (!(sc->flags & IS_VF)) 8245 npkt--; 8246 } else { 8247 vi->flags &= ~TX_USES_VM_WR; 8248 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO); 8249 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8250 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 8251 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 8252 } 8253 for_each_txq(vi, i, txq) { 8254 txq->cpl_ctrl0 = ctrl0; 8255 txq->txp.max_npkt = npkt; 8256 } 8257 } 8258 end_synchronized_op(sc, LOCK_HELD); 8259 return (rc); 8260 } 8261 8262 static int 8263 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 8264 { 8265 struct vi_info *vi = arg1; 8266 struct adapter *sc = vi->adapter; 8267 int idx, rc, i; 8268 struct sge_rxq *rxq; 8269 uint8_t v; 8270 8271 idx = vi->tmr_idx; 8272 8273 rc = sysctl_handle_int(oidp, &idx, 0, req); 8274 if (rc != 0 || req->newptr == NULL) 8275 return (rc); 8276 8277 if (idx < 0 || idx >= SGE_NTIMERS) 8278 return (EINVAL); 8279 8280 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8281 "t4tmr"); 8282 if (rc) 8283 return (rc); 8284 8285 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 8286 for_each_rxq(vi, i, rxq) { 8287 #ifdef atomic_store_rel_8 8288 atomic_store_rel_8(&rxq->iq.intr_params, v); 8289 #else 8290 rxq->iq.intr_params = v; 8291 #endif 8292 } 8293 vi->tmr_idx = idx; 8294 8295 end_synchronized_op(sc, LOCK_HELD); 8296 return (0); 8297 } 8298 8299 static int 8300 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 8301 { 8302 struct vi_info *vi = arg1; 8303 struct adapter *sc = vi->adapter; 8304 int idx, rc; 8305 8306 idx = vi->pktc_idx; 8307 8308 rc = sysctl_handle_int(oidp, &idx, 0, req); 8309 if (rc != 0 || req->newptr == NULL) 8310 return (rc); 8311 8312 if (idx < -1 || idx >= SGE_NCOUNTERS) 8313 return (EINVAL); 8314 8315 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8316 "t4pktc"); 8317 if (rc) 8318 return (rc); 8319 8320 if (vi->flags & VI_INIT_DONE) 8321 rc = EBUSY; /* cannot be changed once the queues are created */ 8322 else 8323 vi->pktc_idx = idx; 8324 8325 end_synchronized_op(sc, LOCK_HELD); 8326 return (rc); 8327 } 8328 8329 static int 8330 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 8331 { 8332 struct vi_info *vi = arg1; 8333 struct adapter *sc = vi->adapter; 8334 int qsize, rc; 8335 8336 qsize = vi->qsize_rxq; 8337 8338 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8339 if (rc != 0 || req->newptr == NULL) 8340 return (rc); 8341 8342 if (qsize < 128 || (qsize & 7)) 8343 return (EINVAL); 8344 8345 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8346 "t4rxqs"); 8347 if (rc) 8348 return (rc); 8349 8350 if (vi->flags & VI_INIT_DONE) 8351 rc = EBUSY; /* cannot be changed once the queues are created */ 8352 else 8353 vi->qsize_rxq = qsize; 8354 8355 end_synchronized_op(sc, LOCK_HELD); 8356 return (rc); 8357 } 8358 8359 static int 8360 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 8361 { 8362 struct vi_info *vi = arg1; 8363 struct adapter *sc = vi->adapter; 8364 int qsize, rc; 8365 8366 qsize = vi->qsize_txq; 8367 8368 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8369 if (rc != 0 || req->newptr == NULL) 8370 return (rc); 8371 8372 if (qsize < 128 || qsize > 65536) 8373 return (EINVAL); 8374 8375 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8376 "t4txqs"); 8377 if (rc) 8378 return (rc); 8379 8380 if (vi->flags & VI_INIT_DONE) 8381 rc = EBUSY; /* cannot be changed once the queues are created */ 8382 else 8383 vi->qsize_txq = qsize; 8384 8385 end_synchronized_op(sc, LOCK_HELD); 8386 return (rc); 8387 } 8388 8389 static int 8390 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 8391 { 8392 struct port_info *pi = arg1; 8393 struct adapter *sc = pi->adapter; 8394 struct link_config *lc = &pi->link_cfg; 8395 int rc; 8396 8397 if (req->newptr == NULL) { 8398 struct sbuf *sb; 8399 static char *bits = "\20\1RX\2TX\3AUTO"; 8400 8401 rc = sysctl_wire_old_buffer(req, 0); 8402 if (rc != 0) 8403 return(rc); 8404 8405 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8406 if (sb == NULL) 8407 return (ENOMEM); 8408 8409 if (lc->link_ok) { 8410 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 8411 (lc->requested_fc & PAUSE_AUTONEG), bits); 8412 } else { 8413 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 8414 PAUSE_RX | PAUSE_AUTONEG), bits); 8415 } 8416 rc = sbuf_finish(sb); 8417 sbuf_delete(sb); 8418 } else { 8419 char s[2]; 8420 int n; 8421 8422 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 8423 PAUSE_AUTONEG)); 8424 s[1] = 0; 8425 8426 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8427 if (rc != 0) 8428 return(rc); 8429 8430 if (s[1] != 0) 8431 return (EINVAL); 8432 if (s[0] < '0' || s[0] > '9') 8433 return (EINVAL); /* not a number */ 8434 n = s[0] - '0'; 8435 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 8436 return (EINVAL); /* some other bit is set too */ 8437 8438 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8439 "t4PAUSE"); 8440 if (rc) 8441 return (rc); 8442 if (!hw_off_limits(sc)) { 8443 PORT_LOCK(pi); 8444 lc->requested_fc = n; 8445 fixup_link_config(pi); 8446 if (pi->up_vis > 0) 8447 rc = apply_link_config(pi); 8448 set_current_media(pi); 8449 PORT_UNLOCK(pi); 8450 } 8451 end_synchronized_op(sc, 0); 8452 } 8453 8454 return (rc); 8455 } 8456 8457 static int 8458 sysctl_link_fec(SYSCTL_HANDLER_ARGS) 8459 { 8460 struct port_info *pi = arg1; 8461 struct link_config *lc = &pi->link_cfg; 8462 int rc; 8463 struct sbuf *sb; 8464 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2"; 8465 8466 rc = sysctl_wire_old_buffer(req, 0); 8467 if (rc != 0) 8468 return(rc); 8469 8470 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8471 if (sb == NULL) 8472 return (ENOMEM); 8473 if (lc->link_ok) 8474 sbuf_printf(sb, "%b", lc->fec, bits); 8475 else 8476 sbuf_printf(sb, "no link"); 8477 rc = sbuf_finish(sb); 8478 sbuf_delete(sb); 8479 8480 return (rc); 8481 } 8482 8483 static int 8484 sysctl_requested_fec(SYSCTL_HANDLER_ARGS) 8485 { 8486 struct port_info *pi = arg1; 8487 struct adapter *sc = pi->adapter; 8488 struct link_config *lc = &pi->link_cfg; 8489 int rc; 8490 int8_t old; 8491 8492 if (req->newptr == NULL) { 8493 struct sbuf *sb; 8494 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2" 8495 "\5RSVD3\6auto\7module"; 8496 8497 rc = sysctl_wire_old_buffer(req, 0); 8498 if (rc != 0) 8499 return(rc); 8500 8501 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8502 if (sb == NULL) 8503 return (ENOMEM); 8504 8505 sbuf_printf(sb, "%b", lc->requested_fec, bits); 8506 rc = sbuf_finish(sb); 8507 sbuf_delete(sb); 8508 } else { 8509 char s[8]; 8510 int n; 8511 8512 snprintf(s, sizeof(s), "%d", 8513 lc->requested_fec == FEC_AUTO ? -1 : 8514 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE)); 8515 8516 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8517 if (rc != 0) 8518 return(rc); 8519 8520 n = strtol(&s[0], NULL, 0); 8521 if (n < 0 || n & FEC_AUTO) 8522 n = FEC_AUTO; 8523 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE)) 8524 return (EINVAL);/* some other bit is set too */ 8525 8526 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8527 "t4reqf"); 8528 if (rc) 8529 return (rc); 8530 PORT_LOCK(pi); 8531 old = lc->requested_fec; 8532 if (n == FEC_AUTO) 8533 lc->requested_fec = FEC_AUTO; 8534 else if (n == 0 || n == FEC_NONE) 8535 lc->requested_fec = FEC_NONE; 8536 else { 8537 if ((lc->pcaps | 8538 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) != 8539 lc->pcaps) { 8540 rc = ENOTSUP; 8541 goto done; 8542 } 8543 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC | 8544 FEC_MODULE); 8545 } 8546 if (!hw_off_limits(sc)) { 8547 fixup_link_config(pi); 8548 if (pi->up_vis > 0) { 8549 rc = apply_link_config(pi); 8550 if (rc != 0) { 8551 lc->requested_fec = old; 8552 if (rc == FW_EPROTO) 8553 rc = ENOTSUP; 8554 } 8555 } 8556 } 8557 done: 8558 PORT_UNLOCK(pi); 8559 end_synchronized_op(sc, 0); 8560 } 8561 8562 return (rc); 8563 } 8564 8565 static int 8566 sysctl_module_fec(SYSCTL_HANDLER_ARGS) 8567 { 8568 struct port_info *pi = arg1; 8569 struct adapter *sc = pi->adapter; 8570 struct link_config *lc = &pi->link_cfg; 8571 int rc; 8572 int8_t fec; 8573 struct sbuf *sb; 8574 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3"; 8575 8576 rc = sysctl_wire_old_buffer(req, 0); 8577 if (rc != 0) 8578 return (rc); 8579 8580 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8581 if (sb == NULL) 8582 return (ENOMEM); 8583 8584 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) { 8585 rc = EBUSY; 8586 goto done; 8587 } 8588 if (hw_off_limits(sc)) { 8589 rc = ENXIO; 8590 goto done; 8591 } 8592 PORT_LOCK(pi); 8593 if (pi->up_vis == 0) { 8594 /* 8595 * If all the interfaces are administratively down the firmware 8596 * does not report transceiver changes. Refresh port info here. 8597 * This is the only reason we have a synchronized op in this 8598 * function. Just PORT_LOCK would have been enough otherwise. 8599 */ 8600 t4_update_port_info(pi); 8601 } 8602 8603 fec = lc->fec_hint; 8604 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE || 8605 !fec_supported(lc->pcaps)) { 8606 sbuf_printf(sb, "n/a"); 8607 } else { 8608 if (fec == 0) 8609 fec = FEC_NONE; 8610 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits); 8611 } 8612 rc = sbuf_finish(sb); 8613 PORT_UNLOCK(pi); 8614 done: 8615 sbuf_delete(sb); 8616 end_synchronized_op(sc, 0); 8617 8618 return (rc); 8619 } 8620 8621 static int 8622 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 8623 { 8624 struct port_info *pi = arg1; 8625 struct adapter *sc = pi->adapter; 8626 struct link_config *lc = &pi->link_cfg; 8627 int rc, val; 8628 8629 if (lc->pcaps & FW_PORT_CAP32_ANEG) 8630 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 8631 else 8632 val = -1; 8633 rc = sysctl_handle_int(oidp, &val, 0, req); 8634 if (rc != 0 || req->newptr == NULL) 8635 return (rc); 8636 if (val == 0) 8637 val = AUTONEG_DISABLE; 8638 else if (val == 1) 8639 val = AUTONEG_ENABLE; 8640 else 8641 val = AUTONEG_AUTO; 8642 8643 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8644 "t4aneg"); 8645 if (rc) 8646 return (rc); 8647 PORT_LOCK(pi); 8648 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 8649 rc = ENOTSUP; 8650 goto done; 8651 } 8652 lc->requested_aneg = val; 8653 if (!hw_off_limits(sc)) { 8654 fixup_link_config(pi); 8655 if (pi->up_vis > 0) 8656 rc = apply_link_config(pi); 8657 set_current_media(pi); 8658 } 8659 done: 8660 PORT_UNLOCK(pi); 8661 end_synchronized_op(sc, 0); 8662 return (rc); 8663 } 8664 8665 static int 8666 sysctl_force_fec(SYSCTL_HANDLER_ARGS) 8667 { 8668 struct port_info *pi = arg1; 8669 struct adapter *sc = pi->adapter; 8670 struct link_config *lc = &pi->link_cfg; 8671 int rc, val; 8672 8673 val = lc->force_fec; 8674 MPASS(val >= -1 && val <= 1); 8675 rc = sysctl_handle_int(oidp, &val, 0, req); 8676 if (rc != 0 || req->newptr == NULL) 8677 return (rc); 8678 if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC)) 8679 return (ENOTSUP); 8680 if (val < -1 || val > 1) 8681 return (EINVAL); 8682 8683 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff"); 8684 if (rc) 8685 return (rc); 8686 PORT_LOCK(pi); 8687 lc->force_fec = val; 8688 if (!hw_off_limits(sc)) { 8689 fixup_link_config(pi); 8690 if (pi->up_vis > 0) 8691 rc = apply_link_config(pi); 8692 } 8693 PORT_UNLOCK(pi); 8694 end_synchronized_op(sc, 0); 8695 return (rc); 8696 } 8697 8698 static int 8699 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 8700 { 8701 struct adapter *sc = arg1; 8702 int rc, reg = arg2; 8703 uint64_t val; 8704 8705 mtx_lock(&sc->reg_lock); 8706 if (hw_off_limits(sc)) 8707 rc = ENXIO; 8708 else { 8709 rc = 0; 8710 val = t4_read_reg64(sc, reg); 8711 } 8712 mtx_unlock(&sc->reg_lock); 8713 if (rc == 0) 8714 rc = sysctl_handle_64(oidp, &val, 0, req); 8715 return (rc); 8716 } 8717 8718 static int 8719 sysctl_temperature(SYSCTL_HANDLER_ARGS) 8720 { 8721 struct adapter *sc = arg1; 8722 int rc, t; 8723 uint32_t param, val; 8724 8725 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 8726 if (rc) 8727 return (rc); 8728 if (hw_off_limits(sc)) 8729 rc = ENXIO; 8730 else { 8731 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8732 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8733 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 8734 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8735 } 8736 end_synchronized_op(sc, 0); 8737 if (rc) 8738 return (rc); 8739 8740 /* unknown is returned as 0 but we display -1 in that case */ 8741 t = val == 0 ? -1 : val; 8742 8743 rc = sysctl_handle_int(oidp, &t, 0, req); 8744 return (rc); 8745 } 8746 8747 static int 8748 sysctl_vdd(SYSCTL_HANDLER_ARGS) 8749 { 8750 struct adapter *sc = arg1; 8751 int rc; 8752 uint32_t param, val; 8753 8754 if (sc->params.core_vdd == 0) { 8755 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8756 "t4vdd"); 8757 if (rc) 8758 return (rc); 8759 if (hw_off_limits(sc)) 8760 rc = ENXIO; 8761 else { 8762 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8763 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8764 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 8765 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, 8766 ¶m, &val); 8767 } 8768 end_synchronized_op(sc, 0); 8769 if (rc) 8770 return (rc); 8771 sc->params.core_vdd = val; 8772 } 8773 8774 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req)); 8775 } 8776 8777 static int 8778 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS) 8779 { 8780 struct adapter *sc = arg1; 8781 int rc, v; 8782 uint32_t param, val; 8783 8784 v = sc->sensor_resets; 8785 rc = sysctl_handle_int(oidp, &v, 0, req); 8786 if (rc != 0 || req->newptr == NULL || v <= 0) 8787 return (rc); 8788 8789 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) || 8790 chip_id(sc) < CHELSIO_T5) 8791 return (ENOTSUP); 8792 8793 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst"); 8794 if (rc) 8795 return (rc); 8796 if (hw_off_limits(sc)) 8797 rc = ENXIO; 8798 else { 8799 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8800 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8801 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR)); 8802 val = 1; 8803 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8804 } 8805 end_synchronized_op(sc, 0); 8806 if (rc == 0) 8807 sc->sensor_resets++; 8808 return (rc); 8809 } 8810 8811 static int 8812 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 8813 { 8814 struct adapter *sc = arg1; 8815 struct sbuf *sb; 8816 int rc; 8817 uint32_t param, val; 8818 8819 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 8820 if (rc) 8821 return (rc); 8822 if (hw_off_limits(sc)) 8823 rc = ENXIO; 8824 else { 8825 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8826 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 8827 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8828 } 8829 end_synchronized_op(sc, 0); 8830 if (rc) 8831 return (rc); 8832 8833 rc = sysctl_wire_old_buffer(req, 0); 8834 if (rc != 0) 8835 return (rc); 8836 8837 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8838 if (sb == NULL) 8839 return (ENOMEM); 8840 8841 if (val == 0xffffffff) { 8842 /* Only debug and custom firmwares report load averages. */ 8843 sbuf_printf(sb, "not available"); 8844 } else { 8845 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 8846 (val >> 16) & 0xff); 8847 } 8848 rc = sbuf_finish(sb); 8849 sbuf_delete(sb); 8850 8851 return (rc); 8852 } 8853 8854 static int 8855 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 8856 { 8857 struct adapter *sc = arg1; 8858 struct sbuf *sb; 8859 int rc, i; 8860 uint16_t incr[NMTUS][NCCTRL_WIN]; 8861 static const char *dec_fac[] = { 8862 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 8863 "0.9375" 8864 }; 8865 8866 rc = sysctl_wire_old_buffer(req, 0); 8867 if (rc != 0) 8868 return (rc); 8869 8870 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8871 if (sb == NULL) 8872 return (ENOMEM); 8873 8874 mtx_lock(&sc->reg_lock); 8875 if (hw_off_limits(sc)) 8876 rc = ENXIO; 8877 else 8878 t4_read_cong_tbl(sc, incr); 8879 mtx_unlock(&sc->reg_lock); 8880 if (rc) 8881 goto done; 8882 8883 for (i = 0; i < NCCTRL_WIN; ++i) { 8884 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 8885 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 8886 incr[5][i], incr[6][i], incr[7][i]); 8887 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 8888 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 8889 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 8890 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 8891 } 8892 8893 rc = sbuf_finish(sb); 8894 done: 8895 sbuf_delete(sb); 8896 return (rc); 8897 } 8898 8899 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 8900 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 8901 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 8902 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 8903 }; 8904 8905 static int 8906 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 8907 { 8908 struct adapter *sc = arg1; 8909 struct sbuf *sb; 8910 int rc, i, n, qid = arg2; 8911 uint32_t *buf, *p; 8912 char *qtype; 8913 u_int cim_num_obq = sc->chip_params->cim_num_obq; 8914 8915 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 8916 ("%s: bad qid %d\n", __func__, qid)); 8917 8918 if (qid < CIM_NUM_IBQ) { 8919 /* inbound queue */ 8920 qtype = "IBQ"; 8921 n = 4 * CIM_IBQ_SIZE; 8922 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 8923 mtx_lock(&sc->reg_lock); 8924 if (hw_off_limits(sc)) 8925 rc = -ENXIO; 8926 else 8927 rc = t4_read_cim_ibq(sc, qid, buf, n); 8928 mtx_unlock(&sc->reg_lock); 8929 } else { 8930 /* outbound queue */ 8931 qtype = "OBQ"; 8932 qid -= CIM_NUM_IBQ; 8933 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 8934 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 8935 mtx_lock(&sc->reg_lock); 8936 if (hw_off_limits(sc)) 8937 rc = -ENXIO; 8938 else 8939 rc = t4_read_cim_obq(sc, qid, buf, n); 8940 mtx_unlock(&sc->reg_lock); 8941 } 8942 8943 if (rc < 0) { 8944 rc = -rc; 8945 goto done; 8946 } 8947 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 8948 8949 rc = sysctl_wire_old_buffer(req, 0); 8950 if (rc != 0) 8951 goto done; 8952 8953 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 8954 if (sb == NULL) { 8955 rc = ENOMEM; 8956 goto done; 8957 } 8958 8959 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 8960 for (i = 0, p = buf; i < n; i += 16, p += 4) 8961 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 8962 p[2], p[3]); 8963 8964 rc = sbuf_finish(sb); 8965 sbuf_delete(sb); 8966 done: 8967 free(buf, M_CXGBE); 8968 return (rc); 8969 } 8970 8971 static void 8972 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 8973 { 8974 uint32_t *p; 8975 8976 sbuf_printf(sb, "Status Data PC%s", 8977 cfg & F_UPDBGLACAPTPCONLY ? "" : 8978 " LS0Stat LS0Addr LS0Data"); 8979 8980 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 8981 if (cfg & F_UPDBGLACAPTPCONLY) { 8982 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 8983 p[6], p[7]); 8984 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 8985 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 8986 p[4] & 0xff, p[5] >> 8); 8987 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 8988 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 8989 p[1] & 0xf, p[2] >> 4); 8990 } else { 8991 sbuf_printf(sb, 8992 "\n %02x %x%07x %x%07x %08x %08x " 8993 "%08x%08x%08x%08x", 8994 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 8995 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 8996 p[6], p[7]); 8997 } 8998 } 8999 } 9000 9001 static void 9002 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9003 { 9004 uint32_t *p; 9005 9006 sbuf_printf(sb, "Status Inst Data PC%s", 9007 cfg & F_UPDBGLACAPTPCONLY ? "" : 9008 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 9009 9010 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 9011 if (cfg & F_UPDBGLACAPTPCONLY) { 9012 sbuf_printf(sb, "\n %02x %08x %08x %08x", 9013 p[3] & 0xff, p[2], p[1], p[0]); 9014 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 9015 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 9016 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 9017 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 9018 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 9019 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 9020 p[6] >> 16); 9021 } else { 9022 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 9023 "%08x %08x %08x %08x %08x %08x", 9024 (p[9] >> 16) & 0xff, 9025 p[9] & 0xffff, p[8] >> 16, 9026 p[8] & 0xffff, p[7] >> 16, 9027 p[7] & 0xffff, p[6] >> 16, 9028 p[2], p[1], p[0], p[5], p[4], p[3]); 9029 } 9030 } 9031 } 9032 9033 static int 9034 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 9035 { 9036 uint32_t cfg, *buf; 9037 int rc; 9038 9039 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9040 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 9041 M_ZERO | flags); 9042 if (buf == NULL) 9043 return (ENOMEM); 9044 9045 mtx_lock(&sc->reg_lock); 9046 if (hw_off_limits(sc)) 9047 rc = ENXIO; 9048 else { 9049 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9050 if (rc == 0) 9051 rc = -t4_cim_read_la(sc, buf, NULL); 9052 } 9053 mtx_unlock(&sc->reg_lock); 9054 if (rc == 0) { 9055 if (chip_id(sc) < CHELSIO_T6) 9056 sbuf_cim_la4(sc, sb, buf, cfg); 9057 else 9058 sbuf_cim_la6(sc, sb, buf, cfg); 9059 } 9060 free(buf, M_CXGBE); 9061 return (rc); 9062 } 9063 9064 static int 9065 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 9066 { 9067 struct adapter *sc = arg1; 9068 struct sbuf *sb; 9069 int rc; 9070 9071 rc = sysctl_wire_old_buffer(req, 0); 9072 if (rc != 0) 9073 return (rc); 9074 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9075 if (sb == NULL) 9076 return (ENOMEM); 9077 9078 rc = sbuf_cim_la(sc, sb, M_WAITOK); 9079 if (rc == 0) 9080 rc = sbuf_finish(sb); 9081 sbuf_delete(sb); 9082 return (rc); 9083 } 9084 9085 static void 9086 dump_cim_regs(struct adapter *sc) 9087 { 9088 log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n", 9089 device_get_nameunit(sc->dev), 9090 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9091 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9092 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2), 9093 t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN), 9094 t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA)); 9095 log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n", 9096 device_get_nameunit(sc->dev), 9097 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9098 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9099 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800), 9100 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800), 9101 t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN)); 9102 } 9103 9104 static void 9105 dump_cimla(struct adapter *sc) 9106 { 9107 struct sbuf sb; 9108 int rc; 9109 9110 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9111 log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n", 9112 device_get_nameunit(sc->dev)); 9113 return; 9114 } 9115 rc = sbuf_cim_la(sc, &sb, M_WAITOK); 9116 if (rc == 0) { 9117 rc = sbuf_finish(&sb); 9118 if (rc == 0) { 9119 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n", 9120 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9121 } 9122 } 9123 sbuf_delete(&sb); 9124 } 9125 9126 void 9127 t4_os_cim_err(struct adapter *sc) 9128 { 9129 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 9130 } 9131 9132 static int 9133 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 9134 { 9135 struct adapter *sc = arg1; 9136 u_int i; 9137 struct sbuf *sb; 9138 uint32_t *buf, *p; 9139 int rc; 9140 9141 rc = sysctl_wire_old_buffer(req, 0); 9142 if (rc != 0) 9143 return (rc); 9144 9145 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9146 if (sb == NULL) 9147 return (ENOMEM); 9148 9149 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 9150 M_ZERO | M_WAITOK); 9151 9152 mtx_lock(&sc->reg_lock); 9153 if (hw_off_limits(sc)) 9154 rc = ENXIO; 9155 else 9156 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 9157 mtx_unlock(&sc->reg_lock); 9158 if (rc) 9159 goto done; 9160 9161 p = buf; 9162 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9163 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 9164 p[1], p[0]); 9165 } 9166 9167 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 9168 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9169 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 9170 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 9171 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 9172 (p[1] >> 2) | ((p[2] & 3) << 30), 9173 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 9174 p[0] & 1); 9175 } 9176 rc = sbuf_finish(sb); 9177 done: 9178 sbuf_delete(sb); 9179 free(buf, M_CXGBE); 9180 return (rc); 9181 } 9182 9183 static int 9184 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 9185 { 9186 struct adapter *sc = arg1; 9187 u_int i; 9188 struct sbuf *sb; 9189 uint32_t *buf, *p; 9190 int rc; 9191 9192 rc = sysctl_wire_old_buffer(req, 0); 9193 if (rc != 0) 9194 return (rc); 9195 9196 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9197 if (sb == NULL) 9198 return (ENOMEM); 9199 9200 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 9201 M_ZERO | M_WAITOK); 9202 9203 mtx_lock(&sc->reg_lock); 9204 if (hw_off_limits(sc)) 9205 rc = ENXIO; 9206 else 9207 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 9208 mtx_unlock(&sc->reg_lock); 9209 if (rc) 9210 goto done; 9211 9212 p = buf; 9213 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 9214 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9215 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 9216 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 9217 p[4], p[3], p[2], p[1], p[0]); 9218 } 9219 9220 sbuf_printf(sb, "\n\nCntl ID Data"); 9221 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9222 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 9223 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 9224 } 9225 9226 rc = sbuf_finish(sb); 9227 done: 9228 sbuf_delete(sb); 9229 free(buf, M_CXGBE); 9230 return (rc); 9231 } 9232 9233 static int 9234 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 9235 { 9236 struct adapter *sc = arg1; 9237 struct sbuf *sb; 9238 int rc, i; 9239 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9240 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9241 uint16_t thres[CIM_NUM_IBQ]; 9242 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 9243 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 9244 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 9245 9246 cim_num_obq = sc->chip_params->cim_num_obq; 9247 if (is_t4(sc)) { 9248 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 9249 obq_rdaddr = A_UP_OBQ_0_REALADDR; 9250 } else { 9251 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 9252 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 9253 } 9254 nq = CIM_NUM_IBQ + cim_num_obq; 9255 9256 mtx_lock(&sc->reg_lock); 9257 if (hw_off_limits(sc)) 9258 rc = ENXIO; 9259 else { 9260 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 9261 if (rc == 0) { 9262 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, 9263 obq_wr); 9264 if (rc == 0) 9265 t4_read_cimq_cfg(sc, base, size, thres); 9266 } 9267 } 9268 mtx_unlock(&sc->reg_lock); 9269 if (rc) 9270 return (rc); 9271 9272 rc = sysctl_wire_old_buffer(req, 0); 9273 if (rc != 0) 9274 return (rc); 9275 9276 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9277 if (sb == NULL) 9278 return (ENOMEM); 9279 9280 sbuf_printf(sb, 9281 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 9282 9283 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 9284 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 9285 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 9286 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9287 G_QUEREMFLITS(p[2]) * 16); 9288 for ( ; i < nq; i++, p += 4, wr += 2) 9289 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 9290 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 9291 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9292 G_QUEREMFLITS(p[2]) * 16); 9293 9294 rc = sbuf_finish(sb); 9295 sbuf_delete(sb); 9296 9297 return (rc); 9298 } 9299 9300 static int 9301 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 9302 { 9303 struct adapter *sc = arg1; 9304 struct sbuf *sb; 9305 int rc; 9306 struct tp_cpl_stats stats; 9307 9308 rc = sysctl_wire_old_buffer(req, 0); 9309 if (rc != 0) 9310 return (rc); 9311 9312 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9313 if (sb == NULL) 9314 return (ENOMEM); 9315 9316 mtx_lock(&sc->reg_lock); 9317 if (hw_off_limits(sc)) 9318 rc = ENXIO; 9319 else 9320 t4_tp_get_cpl_stats(sc, &stats, 0); 9321 mtx_unlock(&sc->reg_lock); 9322 if (rc) 9323 goto done; 9324 9325 if (sc->chip_params->nchan > 2) { 9326 sbuf_printf(sb, " channel 0 channel 1" 9327 " channel 2 channel 3"); 9328 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 9329 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 9330 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 9331 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 9332 } else { 9333 sbuf_printf(sb, " channel 0 channel 1"); 9334 sbuf_printf(sb, "\nCPL requests: %10u %10u", 9335 stats.req[0], stats.req[1]); 9336 sbuf_printf(sb, "\nCPL responses: %10u %10u", 9337 stats.rsp[0], stats.rsp[1]); 9338 } 9339 9340 rc = sbuf_finish(sb); 9341 done: 9342 sbuf_delete(sb); 9343 return (rc); 9344 } 9345 9346 static int 9347 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 9348 { 9349 struct adapter *sc = arg1; 9350 struct sbuf *sb; 9351 int rc; 9352 struct tp_usm_stats stats; 9353 9354 rc = sysctl_wire_old_buffer(req, 0); 9355 if (rc != 0) 9356 return(rc); 9357 9358 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9359 if (sb == NULL) 9360 return (ENOMEM); 9361 9362 mtx_lock(&sc->reg_lock); 9363 if (hw_off_limits(sc)) 9364 rc = ENXIO; 9365 else 9366 t4_get_usm_stats(sc, &stats, 1); 9367 mtx_unlock(&sc->reg_lock); 9368 if (rc == 0) { 9369 sbuf_printf(sb, "Frames: %u\n", stats.frames); 9370 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 9371 sbuf_printf(sb, "Drops: %u", stats.drops); 9372 rc = sbuf_finish(sb); 9373 } 9374 sbuf_delete(sb); 9375 9376 return (rc); 9377 } 9378 9379 static int 9380 sysctl_tid_stats(SYSCTL_HANDLER_ARGS) 9381 { 9382 struct adapter *sc = arg1; 9383 struct sbuf *sb; 9384 int rc; 9385 struct tp_tid_stats stats; 9386 9387 rc = sysctl_wire_old_buffer(req, 0); 9388 if (rc != 0) 9389 return(rc); 9390 9391 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9392 if (sb == NULL) 9393 return (ENOMEM); 9394 9395 mtx_lock(&sc->reg_lock); 9396 if (hw_off_limits(sc)) 9397 rc = ENXIO; 9398 else 9399 t4_tp_get_tid_stats(sc, &stats, 1); 9400 mtx_unlock(&sc->reg_lock); 9401 if (rc == 0) { 9402 sbuf_printf(sb, "Delete: %u\n", stats.del); 9403 sbuf_printf(sb, "Invalidate: %u\n", stats.inv); 9404 sbuf_printf(sb, "Active: %u\n", stats.act); 9405 sbuf_printf(sb, "Passive: %u", stats.pas); 9406 rc = sbuf_finish(sb); 9407 } 9408 sbuf_delete(sb); 9409 9410 return (rc); 9411 } 9412 9413 static const char * const devlog_level_strings[] = { 9414 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 9415 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 9416 [FW_DEVLOG_LEVEL_ERR] = "ERR", 9417 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 9418 [FW_DEVLOG_LEVEL_INFO] = "INFO", 9419 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 9420 }; 9421 9422 static const char * const devlog_facility_strings[] = { 9423 [FW_DEVLOG_FACILITY_CORE] = "CORE", 9424 [FW_DEVLOG_FACILITY_CF] = "CF", 9425 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 9426 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 9427 [FW_DEVLOG_FACILITY_RES] = "RES", 9428 [FW_DEVLOG_FACILITY_HW] = "HW", 9429 [FW_DEVLOG_FACILITY_FLR] = "FLR", 9430 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 9431 [FW_DEVLOG_FACILITY_PHY] = "PHY", 9432 [FW_DEVLOG_FACILITY_MAC] = "MAC", 9433 [FW_DEVLOG_FACILITY_PORT] = "PORT", 9434 [FW_DEVLOG_FACILITY_VI] = "VI", 9435 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 9436 [FW_DEVLOG_FACILITY_ACL] = "ACL", 9437 [FW_DEVLOG_FACILITY_TM] = "TM", 9438 [FW_DEVLOG_FACILITY_QFC] = "QFC", 9439 [FW_DEVLOG_FACILITY_DCB] = "DCB", 9440 [FW_DEVLOG_FACILITY_ETH] = "ETH", 9441 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 9442 [FW_DEVLOG_FACILITY_RI] = "RI", 9443 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 9444 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 9445 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 9446 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 9447 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 9448 }; 9449 9450 static int 9451 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 9452 { 9453 int i, j, rc, nentries, first = 0; 9454 struct devlog_params *dparams = &sc->params.devlog; 9455 struct fw_devlog_e *buf, *e; 9456 uint64_t ftstamp = UINT64_MAX; 9457 9458 if (dparams->addr == 0) 9459 return (ENXIO); 9460 9461 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9462 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 9463 if (buf == NULL) 9464 return (ENOMEM); 9465 9466 mtx_lock(&sc->reg_lock); 9467 if (hw_off_limits(sc)) 9468 rc = ENXIO; 9469 else 9470 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, 9471 dparams->size); 9472 mtx_unlock(&sc->reg_lock); 9473 if (rc != 0) 9474 goto done; 9475 9476 nentries = dparams->size / sizeof(struct fw_devlog_e); 9477 for (i = 0; i < nentries; i++) { 9478 e = &buf[i]; 9479 9480 if (e->timestamp == 0) 9481 break; /* end */ 9482 9483 e->timestamp = be64toh(e->timestamp); 9484 e->seqno = be32toh(e->seqno); 9485 for (j = 0; j < 8; j++) 9486 e->params[j] = be32toh(e->params[j]); 9487 9488 if (e->timestamp < ftstamp) { 9489 ftstamp = e->timestamp; 9490 first = i; 9491 } 9492 } 9493 9494 if (buf[first].timestamp == 0) 9495 goto done; /* nothing in the log */ 9496 9497 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 9498 "Seq#", "Tstamp", "Level", "Facility", "Message"); 9499 9500 i = first; 9501 do { 9502 e = &buf[i]; 9503 if (e->timestamp == 0) 9504 break; /* end */ 9505 9506 sbuf_printf(sb, "%10d %15ju %8s %8s ", 9507 e->seqno, e->timestamp, 9508 (e->level < nitems(devlog_level_strings) ? 9509 devlog_level_strings[e->level] : "UNKNOWN"), 9510 (e->facility < nitems(devlog_facility_strings) ? 9511 devlog_facility_strings[e->facility] : "UNKNOWN")); 9512 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 9513 e->params[2], e->params[3], e->params[4], 9514 e->params[5], e->params[6], e->params[7]); 9515 9516 if (++i == nentries) 9517 i = 0; 9518 } while (i != first); 9519 done: 9520 free(buf, M_CXGBE); 9521 return (rc); 9522 } 9523 9524 static int 9525 sysctl_devlog(SYSCTL_HANDLER_ARGS) 9526 { 9527 struct adapter *sc = arg1; 9528 int rc; 9529 struct sbuf *sb; 9530 9531 rc = sysctl_wire_old_buffer(req, 0); 9532 if (rc != 0) 9533 return (rc); 9534 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9535 if (sb == NULL) 9536 return (ENOMEM); 9537 9538 rc = sbuf_devlog(sc, sb, M_WAITOK); 9539 if (rc == 0) 9540 rc = sbuf_finish(sb); 9541 sbuf_delete(sb); 9542 return (rc); 9543 } 9544 9545 static void 9546 dump_devlog(struct adapter *sc) 9547 { 9548 int rc; 9549 struct sbuf sb; 9550 9551 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9552 log(LOG_DEBUG, "%s: failed to generate devlog dump.\n", 9553 device_get_nameunit(sc->dev)); 9554 return; 9555 } 9556 rc = sbuf_devlog(sc, &sb, M_WAITOK); 9557 if (rc == 0) { 9558 rc = sbuf_finish(&sb); 9559 if (rc == 0) { 9560 log(LOG_DEBUG, "%s: device log follows.\n%s", 9561 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9562 } 9563 } 9564 sbuf_delete(&sb); 9565 } 9566 9567 static int 9568 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 9569 { 9570 struct adapter *sc = arg1; 9571 struct sbuf *sb; 9572 int rc; 9573 struct tp_fcoe_stats stats[MAX_NCHAN]; 9574 int i, nchan = sc->chip_params->nchan; 9575 9576 rc = sysctl_wire_old_buffer(req, 0); 9577 if (rc != 0) 9578 return (rc); 9579 9580 mtx_lock(&sc->reg_lock); 9581 if (hw_off_limits(sc)) 9582 rc = ENXIO; 9583 else { 9584 for (i = 0; i < nchan; i++) 9585 t4_get_fcoe_stats(sc, i, &stats[i], 1); 9586 } 9587 mtx_unlock(&sc->reg_lock); 9588 if (rc != 0) 9589 return (rc); 9590 9591 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9592 if (sb == NULL) 9593 return (ENOMEM); 9594 9595 if (nchan > 2) { 9596 sbuf_printf(sb, " channel 0 channel 1" 9597 " channel 2 channel 3"); 9598 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 9599 stats[0].octets_ddp, stats[1].octets_ddp, 9600 stats[2].octets_ddp, stats[3].octets_ddp); 9601 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 9602 stats[0].frames_ddp, stats[1].frames_ddp, 9603 stats[2].frames_ddp, stats[3].frames_ddp); 9604 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 9605 stats[0].frames_drop, stats[1].frames_drop, 9606 stats[2].frames_drop, stats[3].frames_drop); 9607 } else { 9608 sbuf_printf(sb, " channel 0 channel 1"); 9609 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 9610 stats[0].octets_ddp, stats[1].octets_ddp); 9611 sbuf_printf(sb, "\nframesDDP: %16u %16u", 9612 stats[0].frames_ddp, stats[1].frames_ddp); 9613 sbuf_printf(sb, "\nframesDrop: %16u %16u", 9614 stats[0].frames_drop, stats[1].frames_drop); 9615 } 9616 9617 rc = sbuf_finish(sb); 9618 sbuf_delete(sb); 9619 9620 return (rc); 9621 } 9622 9623 static int 9624 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 9625 { 9626 struct adapter *sc = arg1; 9627 struct sbuf *sb; 9628 int rc, i; 9629 unsigned int map, kbps, ipg, mode; 9630 unsigned int pace_tab[NTX_SCHED]; 9631 9632 rc = sysctl_wire_old_buffer(req, 0); 9633 if (rc != 0) 9634 return (rc); 9635 9636 sb = sbuf_new_for_sysctl(NULL, NULL, 512, req); 9637 if (sb == NULL) 9638 return (ENOMEM); 9639 9640 mtx_lock(&sc->reg_lock); 9641 if (hw_off_limits(sc)) { 9642 rc = ENXIO; 9643 goto done; 9644 } 9645 9646 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 9647 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 9648 t4_read_pace_tbl(sc, pace_tab); 9649 9650 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 9651 "Class IPG (0.1 ns) Flow IPG (us)"); 9652 9653 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 9654 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 9655 sbuf_printf(sb, "\n %u %-5s %u ", i, 9656 (mode & (1 << i)) ? "flow" : "class", map & 3); 9657 if (kbps) 9658 sbuf_printf(sb, "%9u ", kbps); 9659 else 9660 sbuf_printf(sb, " disabled "); 9661 9662 if (ipg) 9663 sbuf_printf(sb, "%13u ", ipg); 9664 else 9665 sbuf_printf(sb, " disabled "); 9666 9667 if (pace_tab[i]) 9668 sbuf_printf(sb, "%10u", pace_tab[i]); 9669 else 9670 sbuf_printf(sb, " disabled"); 9671 } 9672 rc = sbuf_finish(sb); 9673 done: 9674 mtx_unlock(&sc->reg_lock); 9675 sbuf_delete(sb); 9676 return (rc); 9677 } 9678 9679 static int 9680 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 9681 { 9682 struct adapter *sc = arg1; 9683 struct sbuf *sb; 9684 int rc, i, j; 9685 uint64_t *p0, *p1; 9686 struct lb_port_stats s[2]; 9687 static const char *stat_name[] = { 9688 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 9689 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 9690 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 9691 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 9692 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 9693 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 9694 "BG2FramesTrunc:", "BG3FramesTrunc:" 9695 }; 9696 9697 rc = sysctl_wire_old_buffer(req, 0); 9698 if (rc != 0) 9699 return (rc); 9700 9701 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9702 if (sb == NULL) 9703 return (ENOMEM); 9704 9705 memset(s, 0, sizeof(s)); 9706 9707 for (i = 0; i < sc->chip_params->nchan; i += 2) { 9708 mtx_lock(&sc->reg_lock); 9709 if (hw_off_limits(sc)) 9710 rc = ENXIO; 9711 else { 9712 t4_get_lb_stats(sc, i, &s[0]); 9713 t4_get_lb_stats(sc, i + 1, &s[1]); 9714 } 9715 mtx_unlock(&sc->reg_lock); 9716 if (rc != 0) 9717 break; 9718 9719 p0 = &s[0].octets; 9720 p1 = &s[1].octets; 9721 sbuf_printf(sb, "%s Loopback %u" 9722 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 9723 9724 for (j = 0; j < nitems(stat_name); j++) 9725 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 9726 *p0++, *p1++); 9727 } 9728 9729 rc = sbuf_finish(sb); 9730 sbuf_delete(sb); 9731 9732 return (rc); 9733 } 9734 9735 static int 9736 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 9737 { 9738 int rc = 0; 9739 struct port_info *pi = arg1; 9740 struct link_config *lc = &pi->link_cfg; 9741 struct sbuf *sb; 9742 9743 rc = sysctl_wire_old_buffer(req, 0); 9744 if (rc != 0) 9745 return(rc); 9746 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 9747 if (sb == NULL) 9748 return (ENOMEM); 9749 9750 if (lc->link_ok || lc->link_down_rc == 255) 9751 sbuf_printf(sb, "n/a"); 9752 else 9753 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 9754 9755 rc = sbuf_finish(sb); 9756 sbuf_delete(sb); 9757 9758 return (rc); 9759 } 9760 9761 struct mem_desc { 9762 u_int base; 9763 u_int limit; 9764 u_int idx; 9765 }; 9766 9767 static int 9768 mem_desc_cmp(const void *a, const void *b) 9769 { 9770 const u_int v1 = ((const struct mem_desc *)a)->base; 9771 const u_int v2 = ((const struct mem_desc *)b)->base; 9772 9773 if (v1 < v2) 9774 return (-1); 9775 else if (v1 > v2) 9776 return (1); 9777 9778 return (0); 9779 } 9780 9781 static void 9782 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 9783 unsigned int to) 9784 { 9785 unsigned int size; 9786 9787 if (from == to) 9788 return; 9789 9790 size = to - from + 1; 9791 if (size == 0) 9792 return; 9793 9794 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 9795 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 9796 } 9797 9798 static int 9799 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 9800 { 9801 struct adapter *sc = arg1; 9802 struct sbuf *sb; 9803 int rc, i, n; 9804 uint32_t lo, hi, used, free, alloc; 9805 static const char *memory[] = { 9806 "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:" 9807 }; 9808 static const char *region[] = { 9809 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 9810 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 9811 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 9812 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 9813 "RQUDP region:", "PBL region:", "TXPBL region:", 9814 "TLSKey region:", "DBVFIFO region:", "ULPRX state:", 9815 "ULPTX state:", "On-chip queues:", 9816 }; 9817 struct mem_desc avail[4]; 9818 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 9819 struct mem_desc *md = mem; 9820 9821 rc = sysctl_wire_old_buffer(req, 0); 9822 if (rc != 0) 9823 return (rc); 9824 9825 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9826 if (sb == NULL) 9827 return (ENOMEM); 9828 9829 for (i = 0; i < nitems(mem); i++) { 9830 mem[i].limit = 0; 9831 mem[i].idx = i; 9832 } 9833 9834 mtx_lock(&sc->reg_lock); 9835 if (hw_off_limits(sc)) { 9836 rc = ENXIO; 9837 goto done; 9838 } 9839 9840 /* Find and sort the populated memory ranges */ 9841 i = 0; 9842 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 9843 if (lo & F_EDRAM0_ENABLE) { 9844 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 9845 avail[i].base = G_EDRAM0_BASE(hi) << 20; 9846 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 9847 avail[i].idx = 0; 9848 i++; 9849 } 9850 if (lo & F_EDRAM1_ENABLE) { 9851 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 9852 avail[i].base = G_EDRAM1_BASE(hi) << 20; 9853 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 9854 avail[i].idx = 1; 9855 i++; 9856 } 9857 if (lo & F_EXT_MEM_ENABLE) { 9858 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 9859 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 9860 avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20); 9861 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 9862 i++; 9863 } 9864 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 9865 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9866 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9867 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9868 avail[i].idx = 4; 9869 i++; 9870 } 9871 if (is_t6(sc) && lo & F_HMA_MUX) { 9872 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9873 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9874 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9875 avail[i].idx = 5; 9876 i++; 9877 } 9878 MPASS(i <= nitems(avail)); 9879 if (!i) /* no memory available */ 9880 goto done; 9881 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 9882 9883 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 9884 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 9885 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 9886 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9887 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 9888 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 9889 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 9890 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 9891 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 9892 9893 /* the next few have explicit upper bounds */ 9894 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 9895 md->limit = md->base - 1 + 9896 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 9897 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 9898 md++; 9899 9900 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 9901 md->limit = md->base - 1 + 9902 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 9903 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 9904 md++; 9905 9906 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 9907 if (chip_id(sc) <= CHELSIO_T5) 9908 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 9909 else 9910 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 9911 md->limit = 0; 9912 } else { 9913 md->base = 0; 9914 md->idx = nitems(region); /* hide it */ 9915 } 9916 md++; 9917 9918 #define ulp_region(reg) \ 9919 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 9920 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 9921 9922 ulp_region(RX_ISCSI); 9923 ulp_region(RX_TDDP); 9924 ulp_region(TX_TPT); 9925 ulp_region(RX_STAG); 9926 ulp_region(RX_RQ); 9927 ulp_region(RX_RQUDP); 9928 ulp_region(RX_PBL); 9929 ulp_region(TX_PBL); 9930 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 9931 ulp_region(RX_TLS_KEY); 9932 } 9933 #undef ulp_region 9934 9935 md->base = 0; 9936 if (is_t4(sc)) 9937 md->idx = nitems(region); 9938 else { 9939 uint32_t size = 0; 9940 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 9941 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 9942 9943 if (is_t5(sc)) { 9944 if (sge_ctrl & F_VFIFO_ENABLE) 9945 size = fifo_size << 2; 9946 } else 9947 size = G_T6_DBVFIFO_SIZE(fifo_size) << 6; 9948 9949 if (size) { 9950 md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR); 9951 md->limit = md->base + size - 1; 9952 } else 9953 md->idx = nitems(region); 9954 } 9955 md++; 9956 9957 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 9958 md->limit = 0; 9959 md++; 9960 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 9961 md->limit = 0; 9962 md++; 9963 9964 md->base = sc->vres.ocq.start; 9965 if (sc->vres.ocq.size) 9966 md->limit = md->base + sc->vres.ocq.size - 1; 9967 else 9968 md->idx = nitems(region); /* hide it */ 9969 md++; 9970 9971 /* add any address-space holes, there can be up to 3 */ 9972 for (n = 0; n < i - 1; n++) 9973 if (avail[n].limit < avail[n + 1].base) 9974 (md++)->base = avail[n].limit; 9975 if (avail[n].limit) 9976 (md++)->base = avail[n].limit; 9977 9978 n = md - mem; 9979 MPASS(n <= nitems(mem)); 9980 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 9981 9982 for (lo = 0; lo < i; lo++) 9983 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 9984 avail[lo].limit - 1); 9985 9986 sbuf_printf(sb, "\n"); 9987 for (i = 0; i < n; i++) { 9988 if (mem[i].idx >= nitems(region)) 9989 continue; /* skip holes */ 9990 if (!mem[i].limit) 9991 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 9992 mem_region_show(sb, region[mem[i].idx], mem[i].base, 9993 mem[i].limit); 9994 } 9995 9996 sbuf_printf(sb, "\n"); 9997 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 9998 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 9999 mem_region_show(sb, "uP RAM:", lo, hi); 10000 10001 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 10002 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 10003 mem_region_show(sb, "uP Extmem2:", lo, hi); 10004 10005 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 10006 for (i = 0, free = 0; i < 2; i++) 10007 free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT)); 10008 sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n", 10009 G_PMRXMAXPAGE(lo), free, 10010 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 10011 (lo & F_PMRXNUMCHN) ? 2 : 1); 10012 10013 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 10014 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 10015 for (i = 0, free = 0; i < 4; i++) 10016 free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT)); 10017 sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n", 10018 G_PMTXMAXPAGE(lo), free, 10019 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 10020 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 10021 sbuf_printf(sb, "%u p-structs (%u free)\n", 10022 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT), 10023 G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT))); 10024 10025 for (i = 0; i < 4; i++) { 10026 if (chip_id(sc) > CHELSIO_T5) 10027 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 10028 else 10029 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 10030 if (is_t5(sc)) { 10031 used = G_T5_USED(lo); 10032 alloc = G_T5_ALLOC(lo); 10033 } else { 10034 used = G_USED(lo); 10035 alloc = G_ALLOC(lo); 10036 } 10037 /* For T6 these are MAC buffer groups */ 10038 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 10039 i, used, alloc); 10040 } 10041 for (i = 0; i < sc->chip_params->nchan; i++) { 10042 if (chip_id(sc) > CHELSIO_T5) 10043 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 10044 else 10045 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 10046 if (is_t5(sc)) { 10047 used = G_T5_USED(lo); 10048 alloc = G_T5_ALLOC(lo); 10049 } else { 10050 used = G_USED(lo); 10051 alloc = G_ALLOC(lo); 10052 } 10053 /* For T6 these are MAC buffer groups */ 10054 sbuf_printf(sb, 10055 "\nLoopback %d using %u pages out of %u allocated", 10056 i, used, alloc); 10057 } 10058 done: 10059 mtx_unlock(&sc->reg_lock); 10060 if (rc == 0) 10061 rc = sbuf_finish(sb); 10062 sbuf_delete(sb); 10063 return (rc); 10064 } 10065 10066 static inline void 10067 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 10068 { 10069 *mask = x | y; 10070 y = htobe64(y); 10071 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 10072 } 10073 10074 static int 10075 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 10076 { 10077 struct adapter *sc = arg1; 10078 struct sbuf *sb; 10079 int rc, i; 10080 10081 MPASS(chip_id(sc) <= CHELSIO_T5); 10082 10083 rc = sysctl_wire_old_buffer(req, 0); 10084 if (rc != 0) 10085 return (rc); 10086 10087 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10088 if (sb == NULL) 10089 return (ENOMEM); 10090 10091 sbuf_printf(sb, 10092 "Idx Ethernet address Mask Vld Ports PF" 10093 " VF Replication P0 P1 P2 P3 ML"); 10094 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10095 uint64_t tcamx, tcamy, mask; 10096 uint32_t cls_lo, cls_hi; 10097 uint8_t addr[ETHER_ADDR_LEN]; 10098 10099 mtx_lock(&sc->reg_lock); 10100 if (hw_off_limits(sc)) 10101 rc = ENXIO; 10102 else { 10103 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 10104 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 10105 } 10106 mtx_unlock(&sc->reg_lock); 10107 if (rc != 0) 10108 break; 10109 if (tcamx & tcamy) 10110 continue; 10111 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10112 mtx_lock(&sc->reg_lock); 10113 if (hw_off_limits(sc)) 10114 rc = ENXIO; 10115 else { 10116 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10117 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10118 } 10119 mtx_unlock(&sc->reg_lock); 10120 if (rc != 0) 10121 break; 10122 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 10123 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 10124 addr[3], addr[4], addr[5], (uintmax_t)mask, 10125 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 10126 G_PORTMAP(cls_hi), G_PF(cls_lo), 10127 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 10128 10129 if (cls_lo & F_REPLICATE) { 10130 struct fw_ldst_cmd ldst_cmd; 10131 10132 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10133 ldst_cmd.op_to_addrspace = 10134 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10135 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10136 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10137 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10138 ldst_cmd.u.mps.rplc.fid_idx = 10139 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10140 V_FW_LDST_CMD_IDX(i)); 10141 10142 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10143 "t4mps"); 10144 if (rc) 10145 break; 10146 if (hw_off_limits(sc)) 10147 rc = ENXIO; 10148 else 10149 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10150 sizeof(ldst_cmd), &ldst_cmd); 10151 end_synchronized_op(sc, 0); 10152 if (rc != 0) 10153 break; 10154 else { 10155 sbuf_printf(sb, " %08x %08x %08x %08x", 10156 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10157 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10158 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10159 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10160 } 10161 } else 10162 sbuf_printf(sb, "%36s", ""); 10163 10164 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 10165 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 10166 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 10167 } 10168 10169 if (rc) 10170 (void) sbuf_finish(sb); 10171 else 10172 rc = sbuf_finish(sb); 10173 sbuf_delete(sb); 10174 10175 return (rc); 10176 } 10177 10178 static int 10179 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 10180 { 10181 struct adapter *sc = arg1; 10182 struct sbuf *sb; 10183 int rc, i; 10184 10185 MPASS(chip_id(sc) > CHELSIO_T5); 10186 10187 rc = sysctl_wire_old_buffer(req, 0); 10188 if (rc != 0) 10189 return (rc); 10190 10191 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10192 if (sb == NULL) 10193 return (ENOMEM); 10194 10195 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 10196 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 10197 " Replication" 10198 " P0 P1 P2 P3 ML\n"); 10199 10200 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10201 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 10202 uint16_t ivlan; 10203 uint64_t tcamx, tcamy, val, mask; 10204 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 10205 uint8_t addr[ETHER_ADDR_LEN]; 10206 10207 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 10208 if (i < 256) 10209 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 10210 else 10211 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 10212 mtx_lock(&sc->reg_lock); 10213 if (hw_off_limits(sc)) 10214 rc = ENXIO; 10215 else { 10216 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10217 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10218 tcamy = G_DMACH(val) << 32; 10219 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10220 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10221 } 10222 mtx_unlock(&sc->reg_lock); 10223 if (rc != 0) 10224 break; 10225 10226 lookup_type = G_DATALKPTYPE(data2); 10227 port_num = G_DATAPORTNUM(data2); 10228 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10229 /* Inner header VNI */ 10230 vniy = ((data2 & F_DATAVIDH2) << 23) | 10231 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10232 dip_hit = data2 & F_DATADIPHIT; 10233 vlan_vld = 0; 10234 } else { 10235 vniy = 0; 10236 dip_hit = 0; 10237 vlan_vld = data2 & F_DATAVIDH2; 10238 ivlan = G_VIDL(val); 10239 } 10240 10241 ctl |= V_CTLXYBITSEL(1); 10242 mtx_lock(&sc->reg_lock); 10243 if (hw_off_limits(sc)) 10244 rc = ENXIO; 10245 else { 10246 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10247 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10248 tcamx = G_DMACH(val) << 32; 10249 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10250 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10251 } 10252 mtx_unlock(&sc->reg_lock); 10253 if (rc != 0) 10254 break; 10255 10256 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10257 /* Inner header VNI mask */ 10258 vnix = ((data2 & F_DATAVIDH2) << 23) | 10259 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10260 } else 10261 vnix = 0; 10262 10263 if (tcamx & tcamy) 10264 continue; 10265 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10266 10267 mtx_lock(&sc->reg_lock); 10268 if (hw_off_limits(sc)) 10269 rc = ENXIO; 10270 else { 10271 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10272 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10273 } 10274 mtx_unlock(&sc->reg_lock); 10275 if (rc != 0) 10276 break; 10277 10278 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10279 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10280 "%012jx %06x %06x - - %3c" 10281 " I %4x %3c %#x%4u%4d", i, addr[0], 10282 addr[1], addr[2], addr[3], addr[4], addr[5], 10283 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 10284 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10285 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10286 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10287 } else { 10288 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10289 "%012jx - - ", i, addr[0], addr[1], 10290 addr[2], addr[3], addr[4], addr[5], 10291 (uintmax_t)mask); 10292 10293 if (vlan_vld) 10294 sbuf_printf(sb, "%4u Y ", ivlan); 10295 else 10296 sbuf_printf(sb, " - N "); 10297 10298 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 10299 lookup_type ? 'I' : 'O', port_num, 10300 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10301 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10302 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10303 } 10304 10305 10306 if (cls_lo & F_T6_REPLICATE) { 10307 struct fw_ldst_cmd ldst_cmd; 10308 10309 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10310 ldst_cmd.op_to_addrspace = 10311 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10312 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10313 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10314 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10315 ldst_cmd.u.mps.rplc.fid_idx = 10316 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10317 V_FW_LDST_CMD_IDX(i)); 10318 10319 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10320 "t6mps"); 10321 if (rc) 10322 break; 10323 if (hw_off_limits(sc)) 10324 rc = ENXIO; 10325 else 10326 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10327 sizeof(ldst_cmd), &ldst_cmd); 10328 end_synchronized_op(sc, 0); 10329 if (rc != 0) 10330 break; 10331 else { 10332 sbuf_printf(sb, " %08x %08x %08x %08x" 10333 " %08x %08x %08x %08x", 10334 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 10335 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 10336 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 10337 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 10338 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10339 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10340 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10341 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10342 } 10343 } else 10344 sbuf_printf(sb, "%72s", ""); 10345 10346 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 10347 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 10348 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 10349 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 10350 } 10351 10352 if (rc) 10353 (void) sbuf_finish(sb); 10354 else 10355 rc = sbuf_finish(sb); 10356 sbuf_delete(sb); 10357 10358 return (rc); 10359 } 10360 10361 static int 10362 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 10363 { 10364 struct adapter *sc = arg1; 10365 struct sbuf *sb; 10366 int rc; 10367 uint16_t mtus[NMTUS]; 10368 10369 rc = sysctl_wire_old_buffer(req, 0); 10370 if (rc != 0) 10371 return (rc); 10372 10373 mtx_lock(&sc->reg_lock); 10374 if (hw_off_limits(sc)) 10375 rc = ENXIO; 10376 else 10377 t4_read_mtu_tbl(sc, mtus, NULL); 10378 mtx_unlock(&sc->reg_lock); 10379 if (rc != 0) 10380 return (rc); 10381 10382 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10383 if (sb == NULL) 10384 return (ENOMEM); 10385 10386 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 10387 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 10388 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 10389 mtus[14], mtus[15]); 10390 10391 rc = sbuf_finish(sb); 10392 sbuf_delete(sb); 10393 10394 return (rc); 10395 } 10396 10397 static int 10398 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 10399 { 10400 struct adapter *sc = arg1; 10401 struct sbuf *sb; 10402 int rc, i; 10403 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 10404 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 10405 static const char *tx_stats[MAX_PM_NSTATS] = { 10406 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 10407 "Tx FIFO wait", NULL, "Tx latency" 10408 }; 10409 static const char *rx_stats[MAX_PM_NSTATS] = { 10410 "Read:", "Write bypass:", "Write mem:", "Flush:", 10411 "Rx FIFO wait", NULL, "Rx latency" 10412 }; 10413 10414 rc = sysctl_wire_old_buffer(req, 0); 10415 if (rc != 0) 10416 return (rc); 10417 10418 mtx_lock(&sc->reg_lock); 10419 if (hw_off_limits(sc)) 10420 rc = ENXIO; 10421 else { 10422 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 10423 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 10424 } 10425 mtx_unlock(&sc->reg_lock); 10426 if (rc != 0) 10427 return (rc); 10428 10429 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10430 if (sb == NULL) 10431 return (ENOMEM); 10432 10433 sbuf_printf(sb, " Tx pcmds Tx bytes"); 10434 for (i = 0; i < 4; i++) { 10435 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10436 tx_cyc[i]); 10437 } 10438 10439 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 10440 for (i = 0; i < 4; i++) { 10441 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10442 rx_cyc[i]); 10443 } 10444 10445 if (chip_id(sc) > CHELSIO_T5) { 10446 sbuf_printf(sb, 10447 "\n Total wait Total occupancy"); 10448 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10449 tx_cyc[i]); 10450 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10451 rx_cyc[i]); 10452 10453 i += 2; 10454 MPASS(i < nitems(tx_stats)); 10455 10456 sbuf_printf(sb, 10457 "\n Reads Total wait"); 10458 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10459 tx_cyc[i]); 10460 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10461 rx_cyc[i]); 10462 } 10463 10464 rc = sbuf_finish(sb); 10465 sbuf_delete(sb); 10466 10467 return (rc); 10468 } 10469 10470 static int 10471 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 10472 { 10473 struct adapter *sc = arg1; 10474 struct sbuf *sb; 10475 int rc; 10476 struct tp_rdma_stats stats; 10477 10478 rc = sysctl_wire_old_buffer(req, 0); 10479 if (rc != 0) 10480 return (rc); 10481 10482 mtx_lock(&sc->reg_lock); 10483 if (hw_off_limits(sc)) 10484 rc = ENXIO; 10485 else 10486 t4_tp_get_rdma_stats(sc, &stats, 0); 10487 mtx_unlock(&sc->reg_lock); 10488 if (rc != 0) 10489 return (rc); 10490 10491 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10492 if (sb == NULL) 10493 return (ENOMEM); 10494 10495 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 10496 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 10497 10498 rc = sbuf_finish(sb); 10499 sbuf_delete(sb); 10500 10501 return (rc); 10502 } 10503 10504 static int 10505 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 10506 { 10507 struct adapter *sc = arg1; 10508 struct sbuf *sb; 10509 int rc; 10510 struct tp_tcp_stats v4, v6; 10511 10512 rc = sysctl_wire_old_buffer(req, 0); 10513 if (rc != 0) 10514 return (rc); 10515 10516 mtx_lock(&sc->reg_lock); 10517 if (hw_off_limits(sc)) 10518 rc = ENXIO; 10519 else 10520 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 10521 mtx_unlock(&sc->reg_lock); 10522 if (rc != 0) 10523 return (rc); 10524 10525 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10526 if (sb == NULL) 10527 return (ENOMEM); 10528 10529 sbuf_printf(sb, 10530 " IP IPv6\n"); 10531 sbuf_printf(sb, "OutRsts: %20u %20u\n", 10532 v4.tcp_out_rsts, v6.tcp_out_rsts); 10533 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 10534 v4.tcp_in_segs, v6.tcp_in_segs); 10535 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 10536 v4.tcp_out_segs, v6.tcp_out_segs); 10537 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 10538 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 10539 10540 rc = sbuf_finish(sb); 10541 sbuf_delete(sb); 10542 10543 return (rc); 10544 } 10545 10546 static int 10547 sysctl_tids(SYSCTL_HANDLER_ARGS) 10548 { 10549 struct adapter *sc = arg1; 10550 struct sbuf *sb; 10551 int rc; 10552 uint32_t x, y; 10553 struct tid_info *t = &sc->tids; 10554 10555 rc = sysctl_wire_old_buffer(req, 0); 10556 if (rc != 0) 10557 return (rc); 10558 10559 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10560 if (sb == NULL) 10561 return (ENOMEM); 10562 10563 if (t->natids) { 10564 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 10565 t->atids_in_use); 10566 } 10567 10568 if (t->nhpftids) { 10569 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 10570 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 10571 } 10572 10573 if (t->ntids) { 10574 bool hashen = false; 10575 10576 mtx_lock(&sc->reg_lock); 10577 if (hw_off_limits(sc)) 10578 rc = ENXIO; 10579 else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 10580 hashen = true; 10581 if (chip_id(sc) <= CHELSIO_T5) { 10582 x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 10583 y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 10584 } else { 10585 x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 10586 y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 10587 } 10588 } 10589 mtx_unlock(&sc->reg_lock); 10590 if (rc != 0) 10591 goto done; 10592 10593 sbuf_printf(sb, "TID range: "); 10594 if (hashen) { 10595 if (x) 10596 sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1); 10597 sbuf_printf(sb, "%u-%u", y, t->ntids - 1); 10598 } else { 10599 sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base + 10600 t->ntids - 1); 10601 } 10602 sbuf_printf(sb, ", in use: %u\n", 10603 atomic_load_acq_int(&t->tids_in_use)); 10604 } 10605 10606 if (t->nstids) { 10607 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 10608 t->stid_base + t->nstids - 1, t->stids_in_use); 10609 } 10610 10611 if (t->nftids) { 10612 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 10613 t->ftid_end, t->ftids_in_use); 10614 } 10615 10616 if (t->netids) { 10617 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 10618 t->etid_base + t->netids - 1, t->etids_in_use); 10619 } 10620 10621 mtx_lock(&sc->reg_lock); 10622 if (hw_off_limits(sc)) 10623 rc = ENXIO; 10624 else { 10625 x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4); 10626 y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6); 10627 } 10628 mtx_unlock(&sc->reg_lock); 10629 if (rc != 0) 10630 goto done; 10631 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y); 10632 done: 10633 if (rc == 0) 10634 rc = sbuf_finish(sb); 10635 else 10636 (void)sbuf_finish(sb); 10637 sbuf_delete(sb); 10638 10639 return (rc); 10640 } 10641 10642 static int 10643 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 10644 { 10645 struct adapter *sc = arg1; 10646 struct sbuf *sb; 10647 int rc; 10648 struct tp_err_stats stats; 10649 10650 rc = sysctl_wire_old_buffer(req, 0); 10651 if (rc != 0) 10652 return (rc); 10653 10654 mtx_lock(&sc->reg_lock); 10655 if (hw_off_limits(sc)) 10656 rc = ENXIO; 10657 else 10658 t4_tp_get_err_stats(sc, &stats, 0); 10659 mtx_unlock(&sc->reg_lock); 10660 if (rc != 0) 10661 return (rc); 10662 10663 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10664 if (sb == NULL) 10665 return (ENOMEM); 10666 10667 if (sc->chip_params->nchan > 2) { 10668 sbuf_printf(sb, " channel 0 channel 1" 10669 " channel 2 channel 3\n"); 10670 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 10671 stats.mac_in_errs[0], stats.mac_in_errs[1], 10672 stats.mac_in_errs[2], stats.mac_in_errs[3]); 10673 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 10674 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 10675 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 10676 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 10677 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 10678 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 10679 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 10680 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 10681 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 10682 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 10683 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 10684 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 10685 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 10686 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 10687 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 10688 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 10689 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 10690 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 10691 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 10692 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 10693 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 10694 } else { 10695 sbuf_printf(sb, " channel 0 channel 1\n"); 10696 sbuf_printf(sb, "macInErrs: %10u %10u\n", 10697 stats.mac_in_errs[0], stats.mac_in_errs[1]); 10698 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 10699 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 10700 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 10701 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 10702 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 10703 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 10704 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 10705 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 10706 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 10707 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 10708 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 10709 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 10710 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 10711 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 10712 } 10713 10714 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 10715 stats.ofld_no_neigh, stats.ofld_cong_defer); 10716 10717 rc = sbuf_finish(sb); 10718 sbuf_delete(sb); 10719 10720 return (rc); 10721 } 10722 10723 static int 10724 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS) 10725 { 10726 struct adapter *sc = arg1; 10727 struct sbuf *sb; 10728 int rc; 10729 struct tp_tnl_stats stats; 10730 10731 rc = sysctl_wire_old_buffer(req, 0); 10732 if (rc != 0) 10733 return(rc); 10734 10735 mtx_lock(&sc->reg_lock); 10736 if (hw_off_limits(sc)) 10737 rc = ENXIO; 10738 else 10739 t4_tp_get_tnl_stats(sc, &stats, 1); 10740 mtx_unlock(&sc->reg_lock); 10741 if (rc != 0) 10742 return (rc); 10743 10744 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10745 if (sb == NULL) 10746 return (ENOMEM); 10747 10748 if (sc->chip_params->nchan > 2) { 10749 sbuf_printf(sb, " channel 0 channel 1" 10750 " channel 2 channel 3\n"); 10751 sbuf_printf(sb, "OutPkts: %10u %10u %10u %10u\n", 10752 stats.out_pkt[0], stats.out_pkt[1], 10753 stats.out_pkt[2], stats.out_pkt[3]); 10754 sbuf_printf(sb, "InPkts: %10u %10u %10u %10u", 10755 stats.in_pkt[0], stats.in_pkt[1], 10756 stats.in_pkt[2], stats.in_pkt[3]); 10757 } else { 10758 sbuf_printf(sb, " channel 0 channel 1\n"); 10759 sbuf_printf(sb, "OutPkts: %10u %10u\n", 10760 stats.out_pkt[0], stats.out_pkt[1]); 10761 sbuf_printf(sb, "InPkts: %10u %10u", 10762 stats.in_pkt[0], stats.in_pkt[1]); 10763 } 10764 10765 rc = sbuf_finish(sb); 10766 sbuf_delete(sb); 10767 10768 return (rc); 10769 } 10770 10771 static int 10772 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 10773 { 10774 struct adapter *sc = arg1; 10775 struct tp_params *tpp = &sc->params.tp; 10776 u_int mask; 10777 int rc; 10778 10779 mask = tpp->la_mask >> 16; 10780 rc = sysctl_handle_int(oidp, &mask, 0, req); 10781 if (rc != 0 || req->newptr == NULL) 10782 return (rc); 10783 if (mask > 0xffff) 10784 return (EINVAL); 10785 mtx_lock(&sc->reg_lock); 10786 if (hw_off_limits(sc)) 10787 rc = ENXIO; 10788 else { 10789 tpp->la_mask = mask << 16; 10790 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, 10791 tpp->la_mask); 10792 } 10793 mtx_unlock(&sc->reg_lock); 10794 10795 return (rc); 10796 } 10797 10798 struct field_desc { 10799 const char *name; 10800 u_int start; 10801 u_int width; 10802 }; 10803 10804 static void 10805 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 10806 { 10807 char buf[32]; 10808 int line_size = 0; 10809 10810 while (f->name) { 10811 uint64_t mask = (1ULL << f->width) - 1; 10812 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 10813 ((uintmax_t)v >> f->start) & mask); 10814 10815 if (line_size + len >= 79) { 10816 line_size = 8; 10817 sbuf_printf(sb, "\n "); 10818 } 10819 sbuf_printf(sb, "%s ", buf); 10820 line_size += len + 1; 10821 f++; 10822 } 10823 sbuf_printf(sb, "\n"); 10824 } 10825 10826 static const struct field_desc tp_la0[] = { 10827 { "RcfOpCodeOut", 60, 4 }, 10828 { "State", 56, 4 }, 10829 { "WcfState", 52, 4 }, 10830 { "RcfOpcSrcOut", 50, 2 }, 10831 { "CRxError", 49, 1 }, 10832 { "ERxError", 48, 1 }, 10833 { "SanityFailed", 47, 1 }, 10834 { "SpuriousMsg", 46, 1 }, 10835 { "FlushInputMsg", 45, 1 }, 10836 { "FlushInputCpl", 44, 1 }, 10837 { "RssUpBit", 43, 1 }, 10838 { "RssFilterHit", 42, 1 }, 10839 { "Tid", 32, 10 }, 10840 { "InitTcb", 31, 1 }, 10841 { "LineNumber", 24, 7 }, 10842 { "Emsg", 23, 1 }, 10843 { "EdataOut", 22, 1 }, 10844 { "Cmsg", 21, 1 }, 10845 { "CdataOut", 20, 1 }, 10846 { "EreadPdu", 19, 1 }, 10847 { "CreadPdu", 18, 1 }, 10848 { "TunnelPkt", 17, 1 }, 10849 { "RcfPeerFin", 16, 1 }, 10850 { "RcfReasonOut", 12, 4 }, 10851 { "TxCchannel", 10, 2 }, 10852 { "RcfTxChannel", 8, 2 }, 10853 { "RxEchannel", 6, 2 }, 10854 { "RcfRxChannel", 5, 1 }, 10855 { "RcfDataOutSrdy", 4, 1 }, 10856 { "RxDvld", 3, 1 }, 10857 { "RxOoDvld", 2, 1 }, 10858 { "RxCongestion", 1, 1 }, 10859 { "TxCongestion", 0, 1 }, 10860 { NULL } 10861 }; 10862 10863 static const struct field_desc tp_la1[] = { 10864 { "CplCmdIn", 56, 8 }, 10865 { "CplCmdOut", 48, 8 }, 10866 { "ESynOut", 47, 1 }, 10867 { "EAckOut", 46, 1 }, 10868 { "EFinOut", 45, 1 }, 10869 { "ERstOut", 44, 1 }, 10870 { "SynIn", 43, 1 }, 10871 { "AckIn", 42, 1 }, 10872 { "FinIn", 41, 1 }, 10873 { "RstIn", 40, 1 }, 10874 { "DataIn", 39, 1 }, 10875 { "DataInVld", 38, 1 }, 10876 { "PadIn", 37, 1 }, 10877 { "RxBufEmpty", 36, 1 }, 10878 { "RxDdp", 35, 1 }, 10879 { "RxFbCongestion", 34, 1 }, 10880 { "TxFbCongestion", 33, 1 }, 10881 { "TxPktSumSrdy", 32, 1 }, 10882 { "RcfUlpType", 28, 4 }, 10883 { "Eread", 27, 1 }, 10884 { "Ebypass", 26, 1 }, 10885 { "Esave", 25, 1 }, 10886 { "Static0", 24, 1 }, 10887 { "Cread", 23, 1 }, 10888 { "Cbypass", 22, 1 }, 10889 { "Csave", 21, 1 }, 10890 { "CPktOut", 20, 1 }, 10891 { "RxPagePoolFull", 18, 2 }, 10892 { "RxLpbkPkt", 17, 1 }, 10893 { "TxLpbkPkt", 16, 1 }, 10894 { "RxVfValid", 15, 1 }, 10895 { "SynLearned", 14, 1 }, 10896 { "SetDelEntry", 13, 1 }, 10897 { "SetInvEntry", 12, 1 }, 10898 { "CpcmdDvld", 11, 1 }, 10899 { "CpcmdSave", 10, 1 }, 10900 { "RxPstructsFull", 8, 2 }, 10901 { "EpcmdDvld", 7, 1 }, 10902 { "EpcmdFlush", 6, 1 }, 10903 { "EpcmdTrimPrefix", 5, 1 }, 10904 { "EpcmdTrimPostfix", 4, 1 }, 10905 { "ERssIp4Pkt", 3, 1 }, 10906 { "ERssIp6Pkt", 2, 1 }, 10907 { "ERssTcpUdpPkt", 1, 1 }, 10908 { "ERssFceFipPkt", 0, 1 }, 10909 { NULL } 10910 }; 10911 10912 static const struct field_desc tp_la2[] = { 10913 { "CplCmdIn", 56, 8 }, 10914 { "MpsVfVld", 55, 1 }, 10915 { "MpsPf", 52, 3 }, 10916 { "MpsVf", 44, 8 }, 10917 { "SynIn", 43, 1 }, 10918 { "AckIn", 42, 1 }, 10919 { "FinIn", 41, 1 }, 10920 { "RstIn", 40, 1 }, 10921 { "DataIn", 39, 1 }, 10922 { "DataInVld", 38, 1 }, 10923 { "PadIn", 37, 1 }, 10924 { "RxBufEmpty", 36, 1 }, 10925 { "RxDdp", 35, 1 }, 10926 { "RxFbCongestion", 34, 1 }, 10927 { "TxFbCongestion", 33, 1 }, 10928 { "TxPktSumSrdy", 32, 1 }, 10929 { "RcfUlpType", 28, 4 }, 10930 { "Eread", 27, 1 }, 10931 { "Ebypass", 26, 1 }, 10932 { "Esave", 25, 1 }, 10933 { "Static0", 24, 1 }, 10934 { "Cread", 23, 1 }, 10935 { "Cbypass", 22, 1 }, 10936 { "Csave", 21, 1 }, 10937 { "CPktOut", 20, 1 }, 10938 { "RxPagePoolFull", 18, 2 }, 10939 { "RxLpbkPkt", 17, 1 }, 10940 { "TxLpbkPkt", 16, 1 }, 10941 { "RxVfValid", 15, 1 }, 10942 { "SynLearned", 14, 1 }, 10943 { "SetDelEntry", 13, 1 }, 10944 { "SetInvEntry", 12, 1 }, 10945 { "CpcmdDvld", 11, 1 }, 10946 { "CpcmdSave", 10, 1 }, 10947 { "RxPstructsFull", 8, 2 }, 10948 { "EpcmdDvld", 7, 1 }, 10949 { "EpcmdFlush", 6, 1 }, 10950 { "EpcmdTrimPrefix", 5, 1 }, 10951 { "EpcmdTrimPostfix", 4, 1 }, 10952 { "ERssIp4Pkt", 3, 1 }, 10953 { "ERssIp6Pkt", 2, 1 }, 10954 { "ERssTcpUdpPkt", 1, 1 }, 10955 { "ERssFceFipPkt", 0, 1 }, 10956 { NULL } 10957 }; 10958 10959 static void 10960 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 10961 { 10962 10963 field_desc_show(sb, *p, tp_la0); 10964 } 10965 10966 static void 10967 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 10968 { 10969 10970 if (idx) 10971 sbuf_printf(sb, "\n"); 10972 field_desc_show(sb, p[0], tp_la0); 10973 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10974 field_desc_show(sb, p[1], tp_la0); 10975 } 10976 10977 static void 10978 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 10979 { 10980 10981 if (idx) 10982 sbuf_printf(sb, "\n"); 10983 field_desc_show(sb, p[0], tp_la0); 10984 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10985 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 10986 } 10987 10988 static int 10989 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 10990 { 10991 struct adapter *sc = arg1; 10992 struct sbuf *sb; 10993 uint64_t *buf, *p; 10994 int rc; 10995 u_int i, inc; 10996 void (*show_func)(struct sbuf *, uint64_t *, int); 10997 10998 rc = sysctl_wire_old_buffer(req, 0); 10999 if (rc != 0) 11000 return (rc); 11001 11002 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11003 if (sb == NULL) 11004 return (ENOMEM); 11005 11006 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 11007 11008 mtx_lock(&sc->reg_lock); 11009 if (hw_off_limits(sc)) 11010 rc = ENXIO; 11011 else { 11012 t4_tp_read_la(sc, buf, NULL); 11013 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 11014 case 2: 11015 inc = 2; 11016 show_func = tp_la_show2; 11017 break; 11018 case 3: 11019 inc = 2; 11020 show_func = tp_la_show3; 11021 break; 11022 default: 11023 inc = 1; 11024 show_func = tp_la_show; 11025 } 11026 } 11027 mtx_unlock(&sc->reg_lock); 11028 if (rc != 0) 11029 goto done; 11030 11031 p = buf; 11032 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 11033 (*show_func)(sb, p, i); 11034 rc = sbuf_finish(sb); 11035 done: 11036 sbuf_delete(sb); 11037 free(buf, M_CXGBE); 11038 return (rc); 11039 } 11040 11041 static int 11042 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 11043 { 11044 struct adapter *sc = arg1; 11045 struct sbuf *sb; 11046 int rc; 11047 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 11048 11049 rc = sysctl_wire_old_buffer(req, 0); 11050 if (rc != 0) 11051 return (rc); 11052 11053 mtx_lock(&sc->reg_lock); 11054 if (hw_off_limits(sc)) 11055 rc = ENXIO; 11056 else 11057 t4_get_chan_txrate(sc, nrate, orate); 11058 mtx_unlock(&sc->reg_lock); 11059 if (rc != 0) 11060 return (rc); 11061 11062 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 11063 if (sb == NULL) 11064 return (ENOMEM); 11065 11066 if (sc->chip_params->nchan > 2) { 11067 sbuf_printf(sb, " channel 0 channel 1" 11068 " channel 2 channel 3\n"); 11069 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 11070 nrate[0], nrate[1], nrate[2], nrate[3]); 11071 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 11072 orate[0], orate[1], orate[2], orate[3]); 11073 } else { 11074 sbuf_printf(sb, " channel 0 channel 1\n"); 11075 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 11076 nrate[0], nrate[1]); 11077 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 11078 orate[0], orate[1]); 11079 } 11080 11081 rc = sbuf_finish(sb); 11082 sbuf_delete(sb); 11083 11084 return (rc); 11085 } 11086 11087 static int 11088 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 11089 { 11090 struct adapter *sc = arg1; 11091 struct sbuf *sb; 11092 uint32_t *buf, *p; 11093 int rc, i; 11094 11095 rc = sysctl_wire_old_buffer(req, 0); 11096 if (rc != 0) 11097 return (rc); 11098 11099 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11100 if (sb == NULL) 11101 return (ENOMEM); 11102 11103 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 11104 M_ZERO | M_WAITOK); 11105 11106 mtx_lock(&sc->reg_lock); 11107 if (hw_off_limits(sc)) 11108 rc = ENXIO; 11109 else 11110 t4_ulprx_read_la(sc, buf); 11111 mtx_unlock(&sc->reg_lock); 11112 if (rc != 0) 11113 goto done; 11114 11115 p = buf; 11116 sbuf_printf(sb, " Pcmd Type Message" 11117 " Data"); 11118 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 11119 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 11120 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 11121 } 11122 rc = sbuf_finish(sb); 11123 done: 11124 sbuf_delete(sb); 11125 free(buf, M_CXGBE); 11126 return (rc); 11127 } 11128 11129 static int 11130 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 11131 { 11132 struct adapter *sc = arg1; 11133 struct sbuf *sb; 11134 int rc; 11135 uint32_t cfg, s1, s2; 11136 11137 MPASS(chip_id(sc) >= CHELSIO_T5); 11138 11139 rc = sysctl_wire_old_buffer(req, 0); 11140 if (rc != 0) 11141 return (rc); 11142 11143 mtx_lock(&sc->reg_lock); 11144 if (hw_off_limits(sc)) 11145 rc = ENXIO; 11146 else { 11147 cfg = t4_read_reg(sc, A_SGE_STAT_CFG); 11148 s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL); 11149 s2 = t4_read_reg(sc, A_SGE_STAT_MATCH); 11150 } 11151 mtx_unlock(&sc->reg_lock); 11152 if (rc != 0) 11153 return (rc); 11154 11155 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11156 if (sb == NULL) 11157 return (ENOMEM); 11158 11159 if (G_STATSOURCE_T5(cfg) == 7) { 11160 int mode; 11161 11162 mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg); 11163 if (mode == 0) 11164 sbuf_printf(sb, "total %d, incomplete %d", s1, s2); 11165 else if (mode == 1) 11166 sbuf_printf(sb, "total %d, data overflow %d", s1, s2); 11167 else 11168 sbuf_printf(sb, "unknown mode %d", mode); 11169 } 11170 rc = sbuf_finish(sb); 11171 sbuf_delete(sb); 11172 11173 return (rc); 11174 } 11175 11176 static int 11177 sysctl_cpus(SYSCTL_HANDLER_ARGS) 11178 { 11179 struct adapter *sc = arg1; 11180 enum cpu_sets op = arg2; 11181 cpuset_t cpuset; 11182 struct sbuf *sb; 11183 int i, rc; 11184 11185 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 11186 11187 CPU_ZERO(&cpuset); 11188 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 11189 if (rc != 0) 11190 return (rc); 11191 11192 rc = sysctl_wire_old_buffer(req, 0); 11193 if (rc != 0) 11194 return (rc); 11195 11196 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11197 if (sb == NULL) 11198 return (ENOMEM); 11199 11200 CPU_FOREACH(i) 11201 sbuf_printf(sb, "%d ", i); 11202 rc = sbuf_finish(sb); 11203 sbuf_delete(sb); 11204 11205 return (rc); 11206 } 11207 11208 static int 11209 sysctl_reset(SYSCTL_HANDLER_ARGS) 11210 { 11211 struct adapter *sc = arg1; 11212 u_int val; 11213 int rc; 11214 11215 val = atomic_load_int(&sc->num_resets); 11216 rc = sysctl_handle_int(oidp, &val, 0, req); 11217 if (rc != 0 || req->newptr == NULL) 11218 return (rc); 11219 11220 if (val == 0) { 11221 /* Zero out the counter that tracks reset. */ 11222 atomic_store_int(&sc->num_resets, 0); 11223 return (0); 11224 } 11225 11226 if (val != 1) 11227 return (EINVAL); /* 0 or 1 are the only legal values */ 11228 11229 if (hw_off_limits(sc)) /* harmless race */ 11230 return (EALREADY); 11231 11232 taskqueue_enqueue(reset_tq, &sc->reset_task); 11233 return (0); 11234 } 11235 11236 #ifdef TCP_OFFLOAD 11237 static int 11238 sysctl_tls(SYSCTL_HANDLER_ARGS) 11239 { 11240 struct adapter *sc = arg1; 11241 int i, j, v, rc; 11242 struct vi_info *vi; 11243 11244 v = sc->tt.tls; 11245 rc = sysctl_handle_int(oidp, &v, 0, req); 11246 if (rc != 0 || req->newptr == NULL) 11247 return (rc); 11248 11249 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 11250 return (ENOTSUP); 11251 11252 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls"); 11253 if (rc) 11254 return (rc); 11255 if (hw_off_limits(sc)) 11256 rc = ENXIO; 11257 else { 11258 sc->tt.tls = !!v; 11259 for_each_port(sc, i) { 11260 for_each_vi(sc->port[i], j, vi) { 11261 if (vi->flags & VI_INIT_DONE) 11262 t4_update_fl_bufsize(vi->ifp); 11263 } 11264 } 11265 } 11266 end_synchronized_op(sc, 0); 11267 11268 return (rc); 11269 11270 } 11271 11272 static void 11273 unit_conv(char *buf, size_t len, u_int val, u_int factor) 11274 { 11275 u_int rem = val % factor; 11276 11277 if (rem == 0) 11278 snprintf(buf, len, "%u", val / factor); 11279 else { 11280 while (rem % 10 == 0) 11281 rem /= 10; 11282 snprintf(buf, len, "%u.%u", val / factor, rem); 11283 } 11284 } 11285 11286 static int 11287 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 11288 { 11289 struct adapter *sc = arg1; 11290 char buf[16]; 11291 u_int res, re; 11292 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11293 11294 mtx_lock(&sc->reg_lock); 11295 if (hw_off_limits(sc)) 11296 res = (u_int)-1; 11297 else 11298 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 11299 mtx_unlock(&sc->reg_lock); 11300 if (res == (u_int)-1) 11301 return (ENXIO); 11302 11303 switch (arg2) { 11304 case 0: 11305 /* timer_tick */ 11306 re = G_TIMERRESOLUTION(res); 11307 break; 11308 case 1: 11309 /* TCP timestamp tick */ 11310 re = G_TIMESTAMPRESOLUTION(res); 11311 break; 11312 case 2: 11313 /* DACK tick */ 11314 re = G_DELAYEDACKRESOLUTION(res); 11315 break; 11316 default: 11317 return (EDOOFUS); 11318 } 11319 11320 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 11321 11322 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 11323 } 11324 11325 static int 11326 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 11327 { 11328 struct adapter *sc = arg1; 11329 int rc; 11330 u_int dack_tmr, dack_re, v; 11331 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11332 11333 mtx_lock(&sc->reg_lock); 11334 if (hw_off_limits(sc)) 11335 rc = ENXIO; 11336 else { 11337 rc = 0; 11338 dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc, 11339 A_TP_TIMER_RESOLUTION)); 11340 dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER); 11341 } 11342 mtx_unlock(&sc->reg_lock); 11343 if (rc != 0) 11344 return (rc); 11345 11346 v = ((cclk_ps << dack_re) / 1000000) * dack_tmr; 11347 11348 return (sysctl_handle_int(oidp, &v, 0, req)); 11349 } 11350 11351 static int 11352 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 11353 { 11354 struct adapter *sc = arg1; 11355 int rc, reg = arg2; 11356 u_int tre; 11357 u_long tp_tick_us, v; 11358 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11359 11360 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 11361 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 11362 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 11363 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 11364 11365 mtx_lock(&sc->reg_lock); 11366 if (hw_off_limits(sc)) 11367 rc = ENXIO; 11368 else { 11369 rc = 0; 11370 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 11371 tp_tick_us = (cclk_ps << tre) / 1000000; 11372 if (reg == A_TP_INIT_SRTT) 11373 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 11374 else 11375 v = tp_tick_us * t4_read_reg(sc, reg); 11376 } 11377 mtx_unlock(&sc->reg_lock); 11378 if (rc != 0) 11379 return (rc); 11380 else 11381 return (sysctl_handle_long(oidp, &v, 0, req)); 11382 } 11383 11384 /* 11385 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 11386 * passed to this function. 11387 */ 11388 static int 11389 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 11390 { 11391 struct adapter *sc = arg1; 11392 int rc, idx = arg2; 11393 u_int v; 11394 11395 MPASS(idx >= 0 && idx <= 24); 11396 11397 mtx_lock(&sc->reg_lock); 11398 if (hw_off_limits(sc)) 11399 rc = ENXIO; 11400 else { 11401 rc = 0; 11402 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 11403 } 11404 mtx_unlock(&sc->reg_lock); 11405 if (rc != 0) 11406 return (rc); 11407 else 11408 return (sysctl_handle_int(oidp, &v, 0, req)); 11409 } 11410 11411 static int 11412 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 11413 { 11414 struct adapter *sc = arg1; 11415 int rc, idx = arg2; 11416 u_int shift, v, r; 11417 11418 MPASS(idx >= 0 && idx < 16); 11419 11420 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 11421 shift = (idx & 3) << 3; 11422 mtx_lock(&sc->reg_lock); 11423 if (hw_off_limits(sc)) 11424 rc = ENXIO; 11425 else { 11426 rc = 0; 11427 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 11428 } 11429 mtx_unlock(&sc->reg_lock); 11430 if (rc != 0) 11431 return (rc); 11432 else 11433 return (sysctl_handle_int(oidp, &v, 0, req)); 11434 } 11435 11436 static int 11437 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 11438 { 11439 struct vi_info *vi = arg1; 11440 struct adapter *sc = vi->adapter; 11441 int idx, rc, i; 11442 struct sge_ofld_rxq *ofld_rxq; 11443 uint8_t v; 11444 11445 idx = vi->ofld_tmr_idx; 11446 11447 rc = sysctl_handle_int(oidp, &idx, 0, req); 11448 if (rc != 0 || req->newptr == NULL) 11449 return (rc); 11450 11451 if (idx < 0 || idx >= SGE_NTIMERS) 11452 return (EINVAL); 11453 11454 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11455 "t4otmr"); 11456 if (rc) 11457 return (rc); 11458 11459 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 11460 for_each_ofld_rxq(vi, i, ofld_rxq) { 11461 #ifdef atomic_store_rel_8 11462 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 11463 #else 11464 ofld_rxq->iq.intr_params = v; 11465 #endif 11466 } 11467 vi->ofld_tmr_idx = idx; 11468 11469 end_synchronized_op(sc, LOCK_HELD); 11470 return (0); 11471 } 11472 11473 static int 11474 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 11475 { 11476 struct vi_info *vi = arg1; 11477 struct adapter *sc = vi->adapter; 11478 int idx, rc; 11479 11480 idx = vi->ofld_pktc_idx; 11481 11482 rc = sysctl_handle_int(oidp, &idx, 0, req); 11483 if (rc != 0 || req->newptr == NULL) 11484 return (rc); 11485 11486 if (idx < -1 || idx >= SGE_NCOUNTERS) 11487 return (EINVAL); 11488 11489 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11490 "t4opktc"); 11491 if (rc) 11492 return (rc); 11493 11494 if (vi->flags & VI_INIT_DONE) 11495 rc = EBUSY; /* cannot be changed once the queues are created */ 11496 else 11497 vi->ofld_pktc_idx = idx; 11498 11499 end_synchronized_op(sc, LOCK_HELD); 11500 return (rc); 11501 } 11502 #endif 11503 11504 static int 11505 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 11506 { 11507 int rc; 11508 11509 if (cntxt->cid > M_CTXTQID) 11510 return (EINVAL); 11511 11512 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 11513 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 11514 return (EINVAL); 11515 11516 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 11517 if (rc) 11518 return (rc); 11519 11520 if (hw_off_limits(sc)) { 11521 rc = ENXIO; 11522 goto done; 11523 } 11524 11525 if (sc->flags & FW_OK) { 11526 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 11527 &cntxt->data[0]); 11528 if (rc == 0) 11529 goto done; 11530 } 11531 11532 /* 11533 * Read via firmware failed or wasn't even attempted. Read directly via 11534 * the backdoor. 11535 */ 11536 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 11537 done: 11538 end_synchronized_op(sc, 0); 11539 return (rc); 11540 } 11541 11542 static int 11543 load_fw(struct adapter *sc, struct t4_data *fw) 11544 { 11545 int rc; 11546 uint8_t *fw_data; 11547 11548 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 11549 if (rc) 11550 return (rc); 11551 11552 if (hw_off_limits(sc)) { 11553 rc = ENXIO; 11554 goto done; 11555 } 11556 11557 /* 11558 * The firmware, with the sole exception of the memory parity error 11559 * handler, runs from memory and not flash. It is almost always safe to 11560 * install a new firmware on a running system. Just set bit 1 in 11561 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 11562 */ 11563 if (sc->flags & FULL_INIT_DONE && 11564 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 11565 rc = EBUSY; 11566 goto done; 11567 } 11568 11569 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 11570 11571 rc = copyin(fw->data, fw_data, fw->len); 11572 if (rc == 0) 11573 rc = -t4_load_fw(sc, fw_data, fw->len); 11574 11575 free(fw_data, M_CXGBE); 11576 done: 11577 end_synchronized_op(sc, 0); 11578 return (rc); 11579 } 11580 11581 static int 11582 load_cfg(struct adapter *sc, struct t4_data *cfg) 11583 { 11584 int rc; 11585 uint8_t *cfg_data = NULL; 11586 11587 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11588 if (rc) 11589 return (rc); 11590 11591 if (hw_off_limits(sc)) { 11592 rc = ENXIO; 11593 goto done; 11594 } 11595 11596 if (cfg->len == 0) { 11597 /* clear */ 11598 rc = -t4_load_cfg(sc, NULL, 0); 11599 goto done; 11600 } 11601 11602 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 11603 11604 rc = copyin(cfg->data, cfg_data, cfg->len); 11605 if (rc == 0) 11606 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 11607 11608 free(cfg_data, M_CXGBE); 11609 done: 11610 end_synchronized_op(sc, 0); 11611 return (rc); 11612 } 11613 11614 static int 11615 load_boot(struct adapter *sc, struct t4_bootrom *br) 11616 { 11617 int rc; 11618 uint8_t *br_data = NULL; 11619 u_int offset; 11620 11621 if (br->len > 1024 * 1024) 11622 return (EFBIG); 11623 11624 if (br->pf_offset == 0) { 11625 /* pfidx */ 11626 if (br->pfidx_addr > 7) 11627 return (EINVAL); 11628 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 11629 A_PCIE_PF_EXPROM_OFST))); 11630 } else if (br->pf_offset == 1) { 11631 /* offset */ 11632 offset = G_OFFSET(br->pfidx_addr); 11633 } else { 11634 return (EINVAL); 11635 } 11636 11637 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 11638 if (rc) 11639 return (rc); 11640 11641 if (hw_off_limits(sc)) { 11642 rc = ENXIO; 11643 goto done; 11644 } 11645 11646 if (br->len == 0) { 11647 /* clear */ 11648 rc = -t4_load_boot(sc, NULL, offset, 0); 11649 goto done; 11650 } 11651 11652 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 11653 11654 rc = copyin(br->data, br_data, br->len); 11655 if (rc == 0) 11656 rc = -t4_load_boot(sc, br_data, offset, br->len); 11657 11658 free(br_data, M_CXGBE); 11659 done: 11660 end_synchronized_op(sc, 0); 11661 return (rc); 11662 } 11663 11664 static int 11665 load_bootcfg(struct adapter *sc, struct t4_data *bc) 11666 { 11667 int rc; 11668 uint8_t *bc_data = NULL; 11669 11670 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11671 if (rc) 11672 return (rc); 11673 11674 if (hw_off_limits(sc)) { 11675 rc = ENXIO; 11676 goto done; 11677 } 11678 11679 if (bc->len == 0) { 11680 /* clear */ 11681 rc = -t4_load_bootcfg(sc, NULL, 0); 11682 goto done; 11683 } 11684 11685 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 11686 11687 rc = copyin(bc->data, bc_data, bc->len); 11688 if (rc == 0) 11689 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 11690 11691 free(bc_data, M_CXGBE); 11692 done: 11693 end_synchronized_op(sc, 0); 11694 return (rc); 11695 } 11696 11697 static int 11698 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 11699 { 11700 int rc; 11701 struct cudbg_init *cudbg; 11702 void *handle, *buf; 11703 11704 /* buf is large, don't block if no memory is available */ 11705 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 11706 if (buf == NULL) 11707 return (ENOMEM); 11708 11709 handle = cudbg_alloc_handle(); 11710 if (handle == NULL) { 11711 rc = ENOMEM; 11712 goto done; 11713 } 11714 11715 cudbg = cudbg_get_init(handle); 11716 cudbg->adap = sc; 11717 cudbg->print = (cudbg_print_cb)printf; 11718 11719 #ifndef notyet 11720 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 11721 __func__, dump->wr_flash, dump->len, dump->data); 11722 #endif 11723 11724 if (dump->wr_flash) 11725 cudbg->use_flash = 1; 11726 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 11727 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 11728 11729 rc = cudbg_collect(handle, buf, &dump->len); 11730 if (rc != 0) 11731 goto done; 11732 11733 rc = copyout(buf, dump->data, dump->len); 11734 done: 11735 cudbg_free_handle(handle); 11736 free(buf, M_CXGBE); 11737 return (rc); 11738 } 11739 11740 static void 11741 free_offload_policy(struct t4_offload_policy *op) 11742 { 11743 struct offload_rule *r; 11744 int i; 11745 11746 if (op == NULL) 11747 return; 11748 11749 r = &op->rule[0]; 11750 for (i = 0; i < op->nrules; i++, r++) { 11751 free(r->bpf_prog.bf_insns, M_CXGBE); 11752 } 11753 free(op->rule, M_CXGBE); 11754 free(op, M_CXGBE); 11755 } 11756 11757 static int 11758 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 11759 { 11760 int i, rc, len; 11761 struct t4_offload_policy *op, *old; 11762 struct bpf_program *bf; 11763 const struct offload_settings *s; 11764 struct offload_rule *r; 11765 void *u; 11766 11767 if (!is_offload(sc)) 11768 return (ENODEV); 11769 11770 if (uop->nrules == 0) { 11771 /* Delete installed policies. */ 11772 op = NULL; 11773 goto set_policy; 11774 } else if (uop->nrules > 256) { /* arbitrary */ 11775 return (E2BIG); 11776 } 11777 11778 /* Copy userspace offload policy to kernel */ 11779 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 11780 op->nrules = uop->nrules; 11781 len = op->nrules * sizeof(struct offload_rule); 11782 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11783 rc = copyin(uop->rule, op->rule, len); 11784 if (rc) { 11785 free(op->rule, M_CXGBE); 11786 free(op, M_CXGBE); 11787 return (rc); 11788 } 11789 11790 r = &op->rule[0]; 11791 for (i = 0; i < op->nrules; i++, r++) { 11792 11793 /* Validate open_type */ 11794 if (r->open_type != OPEN_TYPE_LISTEN && 11795 r->open_type != OPEN_TYPE_ACTIVE && 11796 r->open_type != OPEN_TYPE_PASSIVE && 11797 r->open_type != OPEN_TYPE_DONTCARE) { 11798 error: 11799 /* 11800 * Rules 0 to i have malloc'd filters that need to be 11801 * freed. Rules i+1 to nrules have userspace pointers 11802 * and should be left alone. 11803 */ 11804 op->nrules = i; 11805 free_offload_policy(op); 11806 return (rc); 11807 } 11808 11809 /* Validate settings */ 11810 s = &r->settings; 11811 if ((s->offload != 0 && s->offload != 1) || 11812 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 11813 s->sched_class < -1 || 11814 s->sched_class >= sc->params.nsched_cls) { 11815 rc = EINVAL; 11816 goto error; 11817 } 11818 11819 bf = &r->bpf_prog; 11820 u = bf->bf_insns; /* userspace ptr */ 11821 bf->bf_insns = NULL; 11822 if (bf->bf_len == 0) { 11823 /* legal, matches everything */ 11824 continue; 11825 } 11826 len = bf->bf_len * sizeof(*bf->bf_insns); 11827 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11828 rc = copyin(u, bf->bf_insns, len); 11829 if (rc != 0) 11830 goto error; 11831 11832 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 11833 rc = EINVAL; 11834 goto error; 11835 } 11836 } 11837 set_policy: 11838 rw_wlock(&sc->policy_lock); 11839 old = sc->policy; 11840 sc->policy = op; 11841 rw_wunlock(&sc->policy_lock); 11842 free_offload_policy(old); 11843 11844 return (0); 11845 } 11846 11847 #define MAX_READ_BUF_SIZE (128 * 1024) 11848 static int 11849 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 11850 { 11851 uint32_t addr, remaining, n; 11852 uint32_t *buf; 11853 int rc; 11854 uint8_t *dst; 11855 11856 mtx_lock(&sc->reg_lock); 11857 if (hw_off_limits(sc)) 11858 rc = ENXIO; 11859 else 11860 rc = validate_mem_range(sc, mr->addr, mr->len); 11861 mtx_unlock(&sc->reg_lock); 11862 if (rc != 0) 11863 return (rc); 11864 11865 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 11866 addr = mr->addr; 11867 remaining = mr->len; 11868 dst = (void *)mr->data; 11869 11870 while (remaining) { 11871 n = min(remaining, MAX_READ_BUF_SIZE); 11872 mtx_lock(&sc->reg_lock); 11873 if (hw_off_limits(sc)) 11874 rc = ENXIO; 11875 else 11876 read_via_memwin(sc, 2, addr, buf, n); 11877 mtx_unlock(&sc->reg_lock); 11878 if (rc != 0) 11879 break; 11880 11881 rc = copyout(buf, dst, n); 11882 if (rc != 0) 11883 break; 11884 11885 dst += n; 11886 remaining -= n; 11887 addr += n; 11888 } 11889 11890 free(buf, M_CXGBE); 11891 return (rc); 11892 } 11893 #undef MAX_READ_BUF_SIZE 11894 11895 static int 11896 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 11897 { 11898 int rc; 11899 11900 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 11901 return (EINVAL); 11902 11903 if (i2cd->len > sizeof(i2cd->data)) 11904 return (EFBIG); 11905 11906 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 11907 if (rc) 11908 return (rc); 11909 if (hw_off_limits(sc)) 11910 rc = ENXIO; 11911 else 11912 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 11913 i2cd->offset, i2cd->len, &i2cd->data[0]); 11914 end_synchronized_op(sc, 0); 11915 11916 return (rc); 11917 } 11918 11919 static int 11920 clear_stats(struct adapter *sc, u_int port_id) 11921 { 11922 int i, v, chan_map; 11923 struct port_info *pi; 11924 struct vi_info *vi; 11925 struct sge_rxq *rxq; 11926 struct sge_txq *txq; 11927 struct sge_wrq *wrq; 11928 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 11929 struct sge_ofld_txq *ofld_txq; 11930 #endif 11931 #ifdef TCP_OFFLOAD 11932 struct sge_ofld_rxq *ofld_rxq; 11933 #endif 11934 11935 if (port_id >= sc->params.nports) 11936 return (EINVAL); 11937 pi = sc->port[port_id]; 11938 if (pi == NULL) 11939 return (EIO); 11940 11941 mtx_lock(&sc->reg_lock); 11942 if (!hw_off_limits(sc)) { 11943 /* MAC stats */ 11944 t4_clr_port_stats(sc, pi->tx_chan); 11945 if (is_t6(sc)) { 11946 if (pi->fcs_reg != -1) 11947 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 11948 else 11949 pi->stats.rx_fcs_err = 0; 11950 } 11951 for_each_vi(pi, v, vi) { 11952 if (vi->flags & VI_INIT_DONE) 11953 t4_clr_vi_stats(sc, vi->vin); 11954 } 11955 chan_map = pi->rx_e_chan_map; 11956 v = 0; /* reuse */ 11957 while (chan_map) { 11958 i = ffs(chan_map) - 1; 11959 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 11960 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 11961 chan_map &= ~(1 << i); 11962 } 11963 } 11964 mtx_unlock(&sc->reg_lock); 11965 pi->tx_parse_error = 0; 11966 pi->tnl_cong_drops = 0; 11967 11968 /* 11969 * Since this command accepts a port, clear stats for 11970 * all VIs on this port. 11971 */ 11972 for_each_vi(pi, v, vi) { 11973 if (vi->flags & VI_INIT_DONE) { 11974 11975 for_each_rxq(vi, i, rxq) { 11976 #if defined(INET) || defined(INET6) 11977 rxq->lro.lro_queued = 0; 11978 rxq->lro.lro_flushed = 0; 11979 #endif 11980 rxq->rxcsum = 0; 11981 rxq->vlan_extraction = 0; 11982 rxq->vxlan_rxcsum = 0; 11983 11984 rxq->fl.cl_allocated = 0; 11985 rxq->fl.cl_recycled = 0; 11986 rxq->fl.cl_fast_recycled = 0; 11987 } 11988 11989 for_each_txq(vi, i, txq) { 11990 txq->txcsum = 0; 11991 txq->tso_wrs = 0; 11992 txq->vlan_insertion = 0; 11993 txq->imm_wrs = 0; 11994 txq->sgl_wrs = 0; 11995 txq->txpkt_wrs = 0; 11996 txq->txpkts0_wrs = 0; 11997 txq->txpkts1_wrs = 0; 11998 txq->txpkts0_pkts = 0; 11999 txq->txpkts1_pkts = 0; 12000 txq->txpkts_flush = 0; 12001 txq->raw_wrs = 0; 12002 txq->vxlan_tso_wrs = 0; 12003 txq->vxlan_txcsum = 0; 12004 txq->kern_tls_records = 0; 12005 txq->kern_tls_short = 0; 12006 txq->kern_tls_partial = 0; 12007 txq->kern_tls_full = 0; 12008 txq->kern_tls_octets = 0; 12009 txq->kern_tls_waste = 0; 12010 txq->kern_tls_options = 0; 12011 txq->kern_tls_header = 0; 12012 txq->kern_tls_fin = 0; 12013 txq->kern_tls_fin_short = 0; 12014 txq->kern_tls_cbc = 0; 12015 txq->kern_tls_gcm = 0; 12016 mp_ring_reset_stats(txq->r); 12017 } 12018 12019 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12020 for_each_ofld_txq(vi, i, ofld_txq) { 12021 ofld_txq->wrq.tx_wrs_direct = 0; 12022 ofld_txq->wrq.tx_wrs_copied = 0; 12023 counter_u64_zero(ofld_txq->tx_iscsi_pdus); 12024 counter_u64_zero(ofld_txq->tx_iscsi_octets); 12025 counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs); 12026 counter_u64_zero(ofld_txq->tx_aio_jobs); 12027 counter_u64_zero(ofld_txq->tx_aio_octets); 12028 counter_u64_zero(ofld_txq->tx_toe_tls_records); 12029 counter_u64_zero(ofld_txq->tx_toe_tls_octets); 12030 } 12031 #endif 12032 #ifdef TCP_OFFLOAD 12033 for_each_ofld_rxq(vi, i, ofld_rxq) { 12034 ofld_rxq->fl.cl_allocated = 0; 12035 ofld_rxq->fl.cl_recycled = 0; 12036 ofld_rxq->fl.cl_fast_recycled = 0; 12037 counter_u64_zero( 12038 ofld_rxq->rx_iscsi_ddp_setup_ok); 12039 counter_u64_zero( 12040 ofld_rxq->rx_iscsi_ddp_setup_error); 12041 ofld_rxq->rx_iscsi_ddp_pdus = 0; 12042 ofld_rxq->rx_iscsi_ddp_octets = 0; 12043 ofld_rxq->rx_iscsi_fl_pdus = 0; 12044 ofld_rxq->rx_iscsi_fl_octets = 0; 12045 ofld_rxq->rx_aio_ddp_jobs = 0; 12046 ofld_rxq->rx_aio_ddp_octets = 0; 12047 ofld_rxq->rx_toe_tls_records = 0; 12048 ofld_rxq->rx_toe_tls_octets = 0; 12049 } 12050 #endif 12051 12052 if (IS_MAIN_VI(vi)) { 12053 wrq = &sc->sge.ctrlq[pi->port_id]; 12054 wrq->tx_wrs_direct = 0; 12055 wrq->tx_wrs_copied = 0; 12056 } 12057 } 12058 } 12059 12060 return (0); 12061 } 12062 12063 static int 12064 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12065 { 12066 #ifdef INET6 12067 struct in6_addr in6; 12068 12069 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12070 if (t4_get_clip_entry(sc, &in6, true) != NULL) 12071 return (0); 12072 else 12073 return (EIO); 12074 #else 12075 return (ENOTSUP); 12076 #endif 12077 } 12078 12079 static int 12080 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12081 { 12082 #ifdef INET6 12083 struct in6_addr in6; 12084 12085 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12086 return (t4_release_clip_addr(sc, &in6)); 12087 #else 12088 return (ENOTSUP); 12089 #endif 12090 } 12091 12092 int 12093 t4_os_find_pci_capability(struct adapter *sc, int cap) 12094 { 12095 int i; 12096 12097 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 12098 } 12099 12100 int 12101 t4_os_pci_save_state(struct adapter *sc) 12102 { 12103 device_t dev; 12104 struct pci_devinfo *dinfo; 12105 12106 dev = sc->dev; 12107 dinfo = device_get_ivars(dev); 12108 12109 pci_cfg_save(dev, dinfo, 0); 12110 return (0); 12111 } 12112 12113 int 12114 t4_os_pci_restore_state(struct adapter *sc) 12115 { 12116 device_t dev; 12117 struct pci_devinfo *dinfo; 12118 12119 dev = sc->dev; 12120 dinfo = device_get_ivars(dev); 12121 12122 pci_cfg_restore(dev, dinfo); 12123 return (0); 12124 } 12125 12126 void 12127 t4_os_portmod_changed(struct port_info *pi) 12128 { 12129 struct adapter *sc = pi->adapter; 12130 struct vi_info *vi; 12131 if_t ifp; 12132 static const char *mod_str[] = { 12133 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 12134 }; 12135 12136 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 12137 ("%s: port_type %u", __func__, pi->port_type)); 12138 12139 vi = &pi->vi[0]; 12140 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 12141 PORT_LOCK(pi); 12142 build_medialist(pi); 12143 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 12144 fixup_link_config(pi); 12145 apply_link_config(pi); 12146 } 12147 PORT_UNLOCK(pi); 12148 end_synchronized_op(sc, LOCK_HELD); 12149 } 12150 12151 ifp = vi->ifp; 12152 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 12153 if_printf(ifp, "transceiver unplugged.\n"); 12154 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 12155 if_printf(ifp, "unknown transceiver inserted.\n"); 12156 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 12157 if_printf(ifp, "unsupported transceiver inserted.\n"); 12158 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 12159 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 12160 port_top_speed(pi), mod_str[pi->mod_type]); 12161 } else { 12162 if_printf(ifp, "transceiver (type %d) inserted.\n", 12163 pi->mod_type); 12164 } 12165 } 12166 12167 void 12168 t4_os_link_changed(struct port_info *pi) 12169 { 12170 struct vi_info *vi; 12171 if_t ifp; 12172 struct link_config *lc = &pi->link_cfg; 12173 struct adapter *sc = pi->adapter; 12174 int v; 12175 12176 PORT_LOCK_ASSERT_OWNED(pi); 12177 12178 if (is_t6(sc)) { 12179 if (lc->link_ok) { 12180 if (lc->speed > 25000 || 12181 (lc->speed == 25000 && lc->fec == FEC_RS)) { 12182 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12183 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS); 12184 } else { 12185 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12186 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS); 12187 } 12188 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 12189 pi->stats.rx_fcs_err = 0; 12190 } else { 12191 pi->fcs_reg = -1; 12192 } 12193 } else { 12194 MPASS(pi->fcs_reg != -1); 12195 MPASS(pi->fcs_base == 0); 12196 } 12197 12198 for_each_vi(pi, v, vi) { 12199 ifp = vi->ifp; 12200 if (ifp == NULL) 12201 continue; 12202 12203 if (lc->link_ok) { 12204 if_setbaudrate(ifp, IF_Mbps(lc->speed)); 12205 if_link_state_change(ifp, LINK_STATE_UP); 12206 } else { 12207 if_link_state_change(ifp, LINK_STATE_DOWN); 12208 } 12209 } 12210 } 12211 12212 void 12213 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 12214 { 12215 struct adapter *sc; 12216 12217 sx_slock(&t4_list_lock); 12218 SLIST_FOREACH(sc, &t4_list, link) { 12219 /* 12220 * func should not make any assumptions about what state sc is 12221 * in - the only guarantee is that sc->sc_lock is a valid lock. 12222 */ 12223 func(sc, arg); 12224 } 12225 sx_sunlock(&t4_list_lock); 12226 } 12227 12228 static int 12229 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 12230 struct thread *td) 12231 { 12232 int rc; 12233 struct adapter *sc = dev->si_drv1; 12234 12235 rc = priv_check(td, PRIV_DRIVER); 12236 if (rc != 0) 12237 return (rc); 12238 12239 switch (cmd) { 12240 case CHELSIO_T4_GETREG: { 12241 struct t4_reg *edata = (struct t4_reg *)data; 12242 12243 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12244 return (EFAULT); 12245 12246 mtx_lock(&sc->reg_lock); 12247 if (hw_off_limits(sc)) 12248 rc = ENXIO; 12249 else if (edata->size == 4) 12250 edata->val = t4_read_reg(sc, edata->addr); 12251 else if (edata->size == 8) 12252 edata->val = t4_read_reg64(sc, edata->addr); 12253 else 12254 rc = EINVAL; 12255 mtx_unlock(&sc->reg_lock); 12256 12257 break; 12258 } 12259 case CHELSIO_T4_SETREG: { 12260 struct t4_reg *edata = (struct t4_reg *)data; 12261 12262 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12263 return (EFAULT); 12264 12265 mtx_lock(&sc->reg_lock); 12266 if (hw_off_limits(sc)) 12267 rc = ENXIO; 12268 else if (edata->size == 4) { 12269 if (edata->val & 0xffffffff00000000) 12270 rc = EINVAL; 12271 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 12272 } else if (edata->size == 8) 12273 t4_write_reg64(sc, edata->addr, edata->val); 12274 else 12275 rc = EINVAL; 12276 mtx_unlock(&sc->reg_lock); 12277 12278 break; 12279 } 12280 case CHELSIO_T4_REGDUMP: { 12281 struct t4_regdump *regs = (struct t4_regdump *)data; 12282 int reglen = t4_get_regs_len(sc); 12283 uint8_t *buf; 12284 12285 if (regs->len < reglen) { 12286 regs->len = reglen; /* hint to the caller */ 12287 return (ENOBUFS); 12288 } 12289 12290 regs->len = reglen; 12291 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 12292 mtx_lock(&sc->reg_lock); 12293 if (hw_off_limits(sc)) 12294 rc = ENXIO; 12295 else 12296 get_regs(sc, regs, buf); 12297 mtx_unlock(&sc->reg_lock); 12298 if (rc == 0) 12299 rc = copyout(buf, regs->data, reglen); 12300 free(buf, M_CXGBE); 12301 break; 12302 } 12303 case CHELSIO_T4_GET_FILTER_MODE: 12304 rc = get_filter_mode(sc, (uint32_t *)data); 12305 break; 12306 case CHELSIO_T4_SET_FILTER_MODE: 12307 rc = set_filter_mode(sc, *(uint32_t *)data); 12308 break; 12309 case CHELSIO_T4_SET_FILTER_MASK: 12310 rc = set_filter_mask(sc, *(uint32_t *)data); 12311 break; 12312 case CHELSIO_T4_GET_FILTER: 12313 rc = get_filter(sc, (struct t4_filter *)data); 12314 break; 12315 case CHELSIO_T4_SET_FILTER: 12316 rc = set_filter(sc, (struct t4_filter *)data); 12317 break; 12318 case CHELSIO_T4_DEL_FILTER: 12319 rc = del_filter(sc, (struct t4_filter *)data); 12320 break; 12321 case CHELSIO_T4_GET_SGE_CONTEXT: 12322 rc = get_sge_context(sc, (struct t4_sge_context *)data); 12323 break; 12324 case CHELSIO_T4_LOAD_FW: 12325 rc = load_fw(sc, (struct t4_data *)data); 12326 break; 12327 case CHELSIO_T4_GET_MEM: 12328 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 12329 break; 12330 case CHELSIO_T4_GET_I2C: 12331 rc = read_i2c(sc, (struct t4_i2c_data *)data); 12332 break; 12333 case CHELSIO_T4_CLEAR_STATS: 12334 rc = clear_stats(sc, *(uint32_t *)data); 12335 break; 12336 case CHELSIO_T4_SCHED_CLASS: 12337 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 12338 break; 12339 case CHELSIO_T4_SCHED_QUEUE: 12340 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 12341 break; 12342 case CHELSIO_T4_GET_TRACER: 12343 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 12344 break; 12345 case CHELSIO_T4_SET_TRACER: 12346 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 12347 break; 12348 case CHELSIO_T4_LOAD_CFG: 12349 rc = load_cfg(sc, (struct t4_data *)data); 12350 break; 12351 case CHELSIO_T4_LOAD_BOOT: 12352 rc = load_boot(sc, (struct t4_bootrom *)data); 12353 break; 12354 case CHELSIO_T4_LOAD_BOOTCFG: 12355 rc = load_bootcfg(sc, (struct t4_data *)data); 12356 break; 12357 case CHELSIO_T4_CUDBG_DUMP: 12358 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 12359 break; 12360 case CHELSIO_T4_SET_OFLD_POLICY: 12361 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 12362 break; 12363 case CHELSIO_T4_HOLD_CLIP_ADDR: 12364 rc = hold_clip_addr(sc, (struct t4_clip_addr *)data); 12365 break; 12366 case CHELSIO_T4_RELEASE_CLIP_ADDR: 12367 rc = release_clip_addr(sc, (struct t4_clip_addr *)data); 12368 break; 12369 default: 12370 rc = ENOTTY; 12371 } 12372 12373 return (rc); 12374 } 12375 12376 #ifdef TCP_OFFLOAD 12377 static int 12378 toe_capability(struct vi_info *vi, bool enable) 12379 { 12380 int rc; 12381 struct port_info *pi = vi->pi; 12382 struct adapter *sc = pi->adapter; 12383 12384 ASSERT_SYNCHRONIZED_OP(sc); 12385 12386 if (!is_offload(sc)) 12387 return (ENODEV); 12388 if (hw_off_limits(sc)) 12389 return (ENXIO); 12390 12391 if (enable) { 12392 #ifdef KERN_TLS 12393 if (sc->flags & KERN_TLS_ON && is_t6(sc)) { 12394 int i, j, n; 12395 struct port_info *p; 12396 struct vi_info *v; 12397 12398 /* 12399 * Reconfigure hardware for TOE if TXTLS is not enabled 12400 * on any ifnet. 12401 */ 12402 n = 0; 12403 for_each_port(sc, i) { 12404 p = sc->port[i]; 12405 for_each_vi(p, j, v) { 12406 if (if_getcapenable(v->ifp) & IFCAP_TXTLS) { 12407 CH_WARN(sc, 12408 "%s has NIC TLS enabled.\n", 12409 device_get_nameunit(v->dev)); 12410 n++; 12411 } 12412 } 12413 } 12414 if (n > 0) { 12415 CH_WARN(sc, "Disable NIC TLS on all interfaces " 12416 "associated with this adapter before " 12417 "trying to enable TOE.\n"); 12418 return (EAGAIN); 12419 } 12420 rc = t6_config_kern_tls(sc, false); 12421 if (rc) 12422 return (rc); 12423 } 12424 #endif 12425 if ((if_getcapenable(vi->ifp) & IFCAP_TOE) != 0) { 12426 /* TOE is already enabled. */ 12427 return (0); 12428 } 12429 12430 /* 12431 * We need the port's queues around so that we're able to send 12432 * and receive CPLs to/from the TOE even if the ifnet for this 12433 * port has never been UP'd administratively. 12434 */ 12435 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 12436 return (rc); 12437 if (!(pi->vi[0].flags & VI_INIT_DONE) && 12438 ((rc = vi_init(&pi->vi[0])) != 0)) 12439 return (rc); 12440 12441 if (isset(&sc->offload_map, pi->port_id)) { 12442 /* TOE is enabled on another VI of this port. */ 12443 pi->uld_vis++; 12444 return (0); 12445 } 12446 12447 if (!uld_active(sc, ULD_TOM)) { 12448 rc = t4_activate_uld(sc, ULD_TOM); 12449 if (rc == EAGAIN) { 12450 log(LOG_WARNING, 12451 "You must kldload t4_tom.ko before trying " 12452 "to enable TOE on a cxgbe interface.\n"); 12453 } 12454 if (rc != 0) 12455 return (rc); 12456 KASSERT(sc->tom_softc != NULL, 12457 ("%s: TOM activated but softc NULL", __func__)); 12458 KASSERT(uld_active(sc, ULD_TOM), 12459 ("%s: TOM activated but flag not set", __func__)); 12460 } 12461 12462 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 12463 if (!uld_active(sc, ULD_IWARP)) 12464 (void) t4_activate_uld(sc, ULD_IWARP); 12465 if (!uld_active(sc, ULD_ISCSI)) 12466 (void) t4_activate_uld(sc, ULD_ISCSI); 12467 12468 pi->uld_vis++; 12469 setbit(&sc->offload_map, pi->port_id); 12470 } else { 12471 pi->uld_vis--; 12472 12473 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 12474 return (0); 12475 12476 KASSERT(uld_active(sc, ULD_TOM), 12477 ("%s: TOM never initialized?", __func__)); 12478 clrbit(&sc->offload_map, pi->port_id); 12479 } 12480 12481 return (0); 12482 } 12483 12484 /* 12485 * Add an upper layer driver to the global list. 12486 */ 12487 int 12488 t4_register_uld(struct uld_info *ui) 12489 { 12490 int rc = 0; 12491 struct uld_info *u; 12492 12493 sx_xlock(&t4_uld_list_lock); 12494 SLIST_FOREACH(u, &t4_uld_list, link) { 12495 if (u->uld_id == ui->uld_id) { 12496 rc = EEXIST; 12497 goto done; 12498 } 12499 } 12500 12501 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 12502 ui->refcount = 0; 12503 done: 12504 sx_xunlock(&t4_uld_list_lock); 12505 return (rc); 12506 } 12507 12508 int 12509 t4_unregister_uld(struct uld_info *ui) 12510 { 12511 int rc = EINVAL; 12512 struct uld_info *u; 12513 12514 sx_xlock(&t4_uld_list_lock); 12515 12516 SLIST_FOREACH(u, &t4_uld_list, link) { 12517 if (u == ui) { 12518 if (ui->refcount > 0) { 12519 rc = EBUSY; 12520 goto done; 12521 } 12522 12523 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 12524 rc = 0; 12525 goto done; 12526 } 12527 } 12528 done: 12529 sx_xunlock(&t4_uld_list_lock); 12530 return (rc); 12531 } 12532 12533 int 12534 t4_activate_uld(struct adapter *sc, int id) 12535 { 12536 int rc; 12537 struct uld_info *ui; 12538 12539 ASSERT_SYNCHRONIZED_OP(sc); 12540 12541 if (id < 0 || id > ULD_MAX) 12542 return (EINVAL); 12543 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 12544 12545 sx_slock(&t4_uld_list_lock); 12546 12547 SLIST_FOREACH(ui, &t4_uld_list, link) { 12548 if (ui->uld_id == id) { 12549 if (!(sc->flags & FULL_INIT_DONE)) { 12550 rc = adapter_init(sc); 12551 if (rc != 0) 12552 break; 12553 } 12554 12555 rc = ui->activate(sc); 12556 if (rc == 0) { 12557 setbit(&sc->active_ulds, id); 12558 ui->refcount++; 12559 } 12560 break; 12561 } 12562 } 12563 12564 sx_sunlock(&t4_uld_list_lock); 12565 12566 return (rc); 12567 } 12568 12569 int 12570 t4_deactivate_uld(struct adapter *sc, int id) 12571 { 12572 int rc; 12573 struct uld_info *ui; 12574 12575 ASSERT_SYNCHRONIZED_OP(sc); 12576 12577 if (id < 0 || id > ULD_MAX) 12578 return (EINVAL); 12579 rc = ENXIO; 12580 12581 sx_slock(&t4_uld_list_lock); 12582 12583 SLIST_FOREACH(ui, &t4_uld_list, link) { 12584 if (ui->uld_id == id) { 12585 rc = ui->deactivate(sc); 12586 if (rc == 0) { 12587 clrbit(&sc->active_ulds, id); 12588 ui->refcount--; 12589 } 12590 break; 12591 } 12592 } 12593 12594 sx_sunlock(&t4_uld_list_lock); 12595 12596 return (rc); 12597 } 12598 12599 static int 12600 t4_deactivate_all_uld(struct adapter *sc) 12601 { 12602 int rc; 12603 struct uld_info *ui; 12604 12605 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld"); 12606 if (rc != 0) 12607 return (ENXIO); 12608 12609 sx_slock(&t4_uld_list_lock); 12610 12611 SLIST_FOREACH(ui, &t4_uld_list, link) { 12612 if (isset(&sc->active_ulds, ui->uld_id)) { 12613 rc = ui->deactivate(sc); 12614 if (rc != 0) 12615 break; 12616 clrbit(&sc->active_ulds, ui->uld_id); 12617 ui->refcount--; 12618 } 12619 } 12620 12621 sx_sunlock(&t4_uld_list_lock); 12622 end_synchronized_op(sc, 0); 12623 12624 return (rc); 12625 } 12626 12627 static void 12628 t4_async_event(struct adapter *sc) 12629 { 12630 struct uld_info *ui; 12631 12632 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4async") != 0) 12633 return; 12634 sx_slock(&t4_uld_list_lock); 12635 SLIST_FOREACH(ui, &t4_uld_list, link) { 12636 if (ui->uld_id == ULD_IWARP) { 12637 ui->async_event(sc); 12638 break; 12639 } 12640 } 12641 sx_sunlock(&t4_uld_list_lock); 12642 end_synchronized_op(sc, 0); 12643 } 12644 12645 int 12646 uld_active(struct adapter *sc, int uld_id) 12647 { 12648 12649 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 12650 12651 return (isset(&sc->active_ulds, uld_id)); 12652 } 12653 #endif 12654 12655 #ifdef KERN_TLS 12656 static int 12657 ktls_capability(struct adapter *sc, bool enable) 12658 { 12659 ASSERT_SYNCHRONIZED_OP(sc); 12660 12661 if (!is_ktls(sc)) 12662 return (ENODEV); 12663 if (!is_t6(sc)) 12664 return (0); 12665 if (hw_off_limits(sc)) 12666 return (ENXIO); 12667 12668 if (enable) { 12669 if (sc->flags & KERN_TLS_ON) 12670 return (0); /* already on */ 12671 if (sc->offload_map != 0) { 12672 CH_WARN(sc, 12673 "Disable TOE on all interfaces associated with " 12674 "this adapter before trying to enable NIC TLS.\n"); 12675 return (EAGAIN); 12676 } 12677 return (t6_config_kern_tls(sc, true)); 12678 } else { 12679 /* 12680 * Nothing to do for disable. If TOE is enabled sometime later 12681 * then toe_capability will reconfigure the hardware. 12682 */ 12683 return (0); 12684 } 12685 } 12686 #endif 12687 12688 /* 12689 * t = ptr to tunable. 12690 * nc = number of CPUs. 12691 * c = compiled in default for that tunable. 12692 */ 12693 static void 12694 calculate_nqueues(int *t, int nc, const int c) 12695 { 12696 int nq; 12697 12698 if (*t > 0) 12699 return; 12700 nq = *t < 0 ? -*t : c; 12701 *t = min(nc, nq); 12702 } 12703 12704 /* 12705 * Come up with reasonable defaults for some of the tunables, provided they're 12706 * not set by the user (in which case we'll use the values as is). 12707 */ 12708 static void 12709 tweak_tunables(void) 12710 { 12711 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 12712 12713 if (t4_ntxq < 1) { 12714 #ifdef RSS 12715 t4_ntxq = rss_getnumbuckets(); 12716 #else 12717 calculate_nqueues(&t4_ntxq, nc, NTXQ); 12718 #endif 12719 } 12720 12721 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 12722 12723 if (t4_nrxq < 1) { 12724 #ifdef RSS 12725 t4_nrxq = rss_getnumbuckets(); 12726 #else 12727 calculate_nqueues(&t4_nrxq, nc, NRXQ); 12728 #endif 12729 } 12730 12731 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 12732 12733 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12734 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 12735 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 12736 #endif 12737 #ifdef TCP_OFFLOAD 12738 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 12739 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 12740 #endif 12741 12742 #if defined(TCP_OFFLOAD) || defined(KERN_TLS) 12743 if (t4_toecaps_allowed == -1) 12744 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 12745 #else 12746 if (t4_toecaps_allowed == -1) 12747 t4_toecaps_allowed = 0; 12748 #endif 12749 12750 #ifdef TCP_OFFLOAD 12751 if (t4_rdmacaps_allowed == -1) { 12752 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 12753 FW_CAPS_CONFIG_RDMA_RDMAC; 12754 } 12755 12756 if (t4_iscsicaps_allowed == -1) { 12757 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 12758 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 12759 FW_CAPS_CONFIG_ISCSI_T10DIF; 12760 } 12761 12762 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 12763 t4_tmr_idx_ofld = TMR_IDX_OFLD; 12764 12765 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 12766 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 12767 #else 12768 if (t4_rdmacaps_allowed == -1) 12769 t4_rdmacaps_allowed = 0; 12770 12771 if (t4_iscsicaps_allowed == -1) 12772 t4_iscsicaps_allowed = 0; 12773 #endif 12774 12775 #ifdef DEV_NETMAP 12776 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ); 12777 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ); 12778 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 12779 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 12780 #endif 12781 12782 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 12783 t4_tmr_idx = TMR_IDX; 12784 12785 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 12786 t4_pktc_idx = PKTC_IDX; 12787 12788 if (t4_qsize_txq < 128) 12789 t4_qsize_txq = 128; 12790 12791 if (t4_qsize_rxq < 128) 12792 t4_qsize_rxq = 128; 12793 while (t4_qsize_rxq & 7) 12794 t4_qsize_rxq++; 12795 12796 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 12797 12798 /* 12799 * Number of VIs to create per-port. The first VI is the "main" regular 12800 * VI for the port. The rest are additional virtual interfaces on the 12801 * same physical port. Note that the main VI does not have native 12802 * netmap support but the extra VIs do. 12803 * 12804 * Limit the number of VIs per port to the number of available 12805 * MAC addresses per port. 12806 */ 12807 if (t4_num_vis < 1) 12808 t4_num_vis = 1; 12809 if (t4_num_vis > nitems(vi_mac_funcs)) { 12810 t4_num_vis = nitems(vi_mac_funcs); 12811 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 12812 } 12813 12814 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 12815 pcie_relaxed_ordering = 1; 12816 #if defined(__i386__) || defined(__amd64__) 12817 if (cpu_vendor_id == CPU_VENDOR_INTEL) 12818 pcie_relaxed_ordering = 0; 12819 #endif 12820 } 12821 } 12822 12823 #ifdef DDB 12824 static void 12825 t4_dump_tcb(struct adapter *sc, int tid) 12826 { 12827 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 12828 12829 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 12830 save = t4_read_reg(sc, reg); 12831 base = sc->memwin[2].mw_base; 12832 12833 /* Dump TCB for the tid */ 12834 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 12835 tcb_addr += tid * TCB_SIZE; 12836 12837 if (is_t4(sc)) { 12838 pf = 0; 12839 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 12840 } else { 12841 pf = V_PFNUM(sc->pf); 12842 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 12843 } 12844 t4_write_reg(sc, reg, win_pos | pf); 12845 t4_read_reg(sc, reg); 12846 12847 off = tcb_addr - win_pos; 12848 for (i = 0; i < 4; i++) { 12849 uint32_t buf[8]; 12850 for (j = 0; j < 8; j++, off += 4) 12851 buf[j] = htonl(t4_read_reg(sc, base + off)); 12852 12853 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 12854 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 12855 buf[7]); 12856 } 12857 12858 t4_write_reg(sc, reg, save); 12859 t4_read_reg(sc, reg); 12860 } 12861 12862 static void 12863 t4_dump_devlog(struct adapter *sc) 12864 { 12865 struct devlog_params *dparams = &sc->params.devlog; 12866 struct fw_devlog_e e; 12867 int i, first, j, m, nentries, rc; 12868 uint64_t ftstamp = UINT64_MAX; 12869 12870 if (dparams->start == 0) { 12871 db_printf("devlog params not valid\n"); 12872 return; 12873 } 12874 12875 nentries = dparams->size / sizeof(struct fw_devlog_e); 12876 m = fwmtype_to_hwmtype(dparams->memtype); 12877 12878 /* Find the first entry. */ 12879 first = -1; 12880 for (i = 0; i < nentries && !db_pager_quit; i++) { 12881 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12882 sizeof(e), (void *)&e); 12883 if (rc != 0) 12884 break; 12885 12886 if (e.timestamp == 0) 12887 break; 12888 12889 e.timestamp = be64toh(e.timestamp); 12890 if (e.timestamp < ftstamp) { 12891 ftstamp = e.timestamp; 12892 first = i; 12893 } 12894 } 12895 12896 if (first == -1) 12897 return; 12898 12899 i = first; 12900 do { 12901 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12902 sizeof(e), (void *)&e); 12903 if (rc != 0) 12904 return; 12905 12906 if (e.timestamp == 0) 12907 return; 12908 12909 e.timestamp = be64toh(e.timestamp); 12910 e.seqno = be32toh(e.seqno); 12911 for (j = 0; j < 8; j++) 12912 e.params[j] = be32toh(e.params[j]); 12913 12914 db_printf("%10d %15ju %8s %8s ", 12915 e.seqno, e.timestamp, 12916 (e.level < nitems(devlog_level_strings) ? 12917 devlog_level_strings[e.level] : "UNKNOWN"), 12918 (e.facility < nitems(devlog_facility_strings) ? 12919 devlog_facility_strings[e.facility] : "UNKNOWN")); 12920 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 12921 e.params[3], e.params[4], e.params[5], e.params[6], 12922 e.params[7]); 12923 12924 if (++i == nentries) 12925 i = 0; 12926 } while (i != first && !db_pager_quit); 12927 } 12928 12929 static DB_DEFINE_TABLE(show, t4, show_t4); 12930 12931 DB_TABLE_COMMAND_FLAGS(show_t4, devlog, db_show_devlog, CS_OWN) 12932 { 12933 device_t dev; 12934 int t; 12935 bool valid; 12936 12937 valid = false; 12938 t = db_read_token(); 12939 if (t == tIDENT) { 12940 dev = device_lookup_by_name(db_tok_string); 12941 valid = true; 12942 } 12943 db_skip_to_eol(); 12944 if (!valid) { 12945 db_printf("usage: show t4 devlog <nexus>\n"); 12946 return; 12947 } 12948 12949 if (dev == NULL) { 12950 db_printf("device not found\n"); 12951 return; 12952 } 12953 12954 t4_dump_devlog(device_get_softc(dev)); 12955 } 12956 12957 DB_TABLE_COMMAND_FLAGS(show_t4, tcb, db_show_t4tcb, CS_OWN) 12958 { 12959 device_t dev; 12960 int radix, tid, t; 12961 bool valid; 12962 12963 valid = false; 12964 radix = db_radix; 12965 db_radix = 10; 12966 t = db_read_token(); 12967 if (t == tIDENT) { 12968 dev = device_lookup_by_name(db_tok_string); 12969 t = db_read_token(); 12970 if (t == tNUMBER) { 12971 tid = db_tok_number; 12972 valid = true; 12973 } 12974 } 12975 db_radix = radix; 12976 db_skip_to_eol(); 12977 if (!valid) { 12978 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 12979 return; 12980 } 12981 12982 if (dev == NULL) { 12983 db_printf("device not found\n"); 12984 return; 12985 } 12986 if (tid < 0) { 12987 db_printf("invalid tid\n"); 12988 return; 12989 } 12990 12991 t4_dump_tcb(device_get_softc(dev), tid); 12992 } 12993 #endif 12994 12995 static eventhandler_tag vxlan_start_evtag; 12996 static eventhandler_tag vxlan_stop_evtag; 12997 12998 struct vxlan_evargs { 12999 if_t ifp; 13000 uint16_t port; 13001 }; 13002 13003 static void 13004 enable_vxlan_rx(struct adapter *sc) 13005 { 13006 int i, rc; 13007 struct port_info *pi; 13008 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 13009 13010 ASSERT_SYNCHRONIZED_OP(sc); 13011 13012 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) | 13013 F_VXLAN_EN); 13014 for_each_port(sc, i) { 13015 pi = sc->port[i]; 13016 if (pi->vxlan_tcam_entry == true) 13017 continue; 13018 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac, 13019 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 13020 true); 13021 if (rc < 0) { 13022 rc = -rc; 13023 CH_ERR(&pi->vi[0], 13024 "failed to add VXLAN TCAM entry: %d.\n", rc); 13025 } else { 13026 MPASS(rc == sc->rawf_base + pi->port_id); 13027 pi->vxlan_tcam_entry = true; 13028 } 13029 } 13030 } 13031 13032 static void 13033 t4_vxlan_start(struct adapter *sc, void *arg) 13034 { 13035 struct vxlan_evargs *v = arg; 13036 13037 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13038 return; 13039 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0) 13040 return; 13041 13042 if (sc->vxlan_refcount == 0) { 13043 sc->vxlan_port = v->port; 13044 sc->vxlan_refcount = 1; 13045 if (!hw_off_limits(sc)) 13046 enable_vxlan_rx(sc); 13047 } else if (sc->vxlan_port == v->port) { 13048 sc->vxlan_refcount++; 13049 } else { 13050 CH_ERR(sc, "VXLAN already configured on port %d; " 13051 "ignoring attempt to configure it on port %d\n", 13052 sc->vxlan_port, v->port); 13053 } 13054 end_synchronized_op(sc, 0); 13055 } 13056 13057 static void 13058 t4_vxlan_stop(struct adapter *sc, void *arg) 13059 { 13060 struct vxlan_evargs *v = arg; 13061 13062 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13063 return; 13064 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0) 13065 return; 13066 13067 /* 13068 * VXLANs may have been configured before the driver was loaded so we 13069 * may see more stops than starts. This is not handled cleanly but at 13070 * least we keep the refcount sane. 13071 */ 13072 if (sc->vxlan_port != v->port) 13073 goto done; 13074 if (sc->vxlan_refcount == 0) { 13075 CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; " 13076 "ignoring attempt to stop it again.\n", sc->vxlan_port); 13077 } else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc)) 13078 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0); 13079 done: 13080 end_synchronized_op(sc, 0); 13081 } 13082 13083 static void 13084 t4_vxlan_start_handler(void *arg __unused, if_t ifp, 13085 sa_family_t family, u_int port) 13086 { 13087 struct vxlan_evargs v; 13088 13089 MPASS(family == AF_INET || family == AF_INET6); 13090 v.ifp = ifp; 13091 v.port = port; 13092 13093 t4_iterate(t4_vxlan_start, &v); 13094 } 13095 13096 static void 13097 t4_vxlan_stop_handler(void *arg __unused, if_t ifp, sa_family_t family, 13098 u_int port) 13099 { 13100 struct vxlan_evargs v; 13101 13102 MPASS(family == AF_INET || family == AF_INET6); 13103 v.ifp = ifp; 13104 v.port = port; 13105 13106 t4_iterate(t4_vxlan_stop, &v); 13107 } 13108 13109 13110 static struct sx mlu; /* mod load unload */ 13111 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 13112 13113 static int 13114 mod_event(module_t mod, int cmd, void *arg) 13115 { 13116 int rc = 0; 13117 static int loaded = 0; 13118 13119 switch (cmd) { 13120 case MOD_LOAD: 13121 sx_xlock(&mlu); 13122 if (loaded++ == 0) { 13123 t4_sge_modload(); 13124 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13125 t4_filter_rpl, CPL_COOKIE_FILTER); 13126 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 13127 do_l2t_write_rpl, CPL_COOKIE_FILTER); 13128 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 13129 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 13130 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13131 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 13132 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 13133 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 13134 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 13135 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 13136 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 13137 do_smt_write_rpl); 13138 sx_init(&t4_list_lock, "T4/T5 adapters"); 13139 SLIST_INIT(&t4_list); 13140 callout_init(&fatal_callout, 1); 13141 #ifdef TCP_OFFLOAD 13142 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 13143 SLIST_INIT(&t4_uld_list); 13144 #endif 13145 #ifdef INET6 13146 t4_clip_modload(); 13147 #endif 13148 #ifdef KERN_TLS 13149 t6_ktls_modload(); 13150 #endif 13151 t4_tracer_modload(); 13152 tweak_tunables(); 13153 vxlan_start_evtag = 13154 EVENTHANDLER_REGISTER(vxlan_start, 13155 t4_vxlan_start_handler, NULL, 13156 EVENTHANDLER_PRI_ANY); 13157 vxlan_stop_evtag = 13158 EVENTHANDLER_REGISTER(vxlan_stop, 13159 t4_vxlan_stop_handler, NULL, 13160 EVENTHANDLER_PRI_ANY); 13161 reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK, 13162 taskqueue_thread_enqueue, &reset_tq); 13163 taskqueue_start_threads(&reset_tq, 1, PI_SOFT, 13164 "t4_rst_thr"); 13165 } 13166 sx_xunlock(&mlu); 13167 break; 13168 13169 case MOD_UNLOAD: 13170 sx_xlock(&mlu); 13171 if (--loaded == 0) { 13172 int tries; 13173 13174 taskqueue_free(reset_tq); 13175 sx_slock(&t4_list_lock); 13176 if (!SLIST_EMPTY(&t4_list)) { 13177 rc = EBUSY; 13178 sx_sunlock(&t4_list_lock); 13179 goto done_unload; 13180 } 13181 #ifdef TCP_OFFLOAD 13182 sx_slock(&t4_uld_list_lock); 13183 if (!SLIST_EMPTY(&t4_uld_list)) { 13184 rc = EBUSY; 13185 sx_sunlock(&t4_uld_list_lock); 13186 sx_sunlock(&t4_list_lock); 13187 goto done_unload; 13188 } 13189 #endif 13190 tries = 0; 13191 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 13192 uprintf("%ju clusters with custom free routine " 13193 "still is use.\n", t4_sge_extfree_refs()); 13194 pause("t4unload", 2 * hz); 13195 } 13196 #ifdef TCP_OFFLOAD 13197 sx_sunlock(&t4_uld_list_lock); 13198 #endif 13199 sx_sunlock(&t4_list_lock); 13200 13201 if (t4_sge_extfree_refs() == 0) { 13202 EVENTHANDLER_DEREGISTER(vxlan_start, 13203 vxlan_start_evtag); 13204 EVENTHANDLER_DEREGISTER(vxlan_stop, 13205 vxlan_stop_evtag); 13206 t4_tracer_modunload(); 13207 #ifdef KERN_TLS 13208 t6_ktls_modunload(); 13209 #endif 13210 #ifdef INET6 13211 t4_clip_modunload(); 13212 #endif 13213 #ifdef TCP_OFFLOAD 13214 sx_destroy(&t4_uld_list_lock); 13215 #endif 13216 sx_destroy(&t4_list_lock); 13217 t4_sge_modunload(); 13218 loaded = 0; 13219 } else { 13220 rc = EBUSY; 13221 loaded++; /* undo earlier decrement */ 13222 } 13223 } 13224 done_unload: 13225 sx_xunlock(&mlu); 13226 break; 13227 } 13228 13229 return (rc); 13230 } 13231 13232 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0); 13233 MODULE_VERSION(t4nex, 1); 13234 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 13235 #ifdef DEV_NETMAP 13236 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 13237 #endif /* DEV_NETMAP */ 13238 13239 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0); 13240 MODULE_VERSION(t5nex, 1); 13241 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 13242 #ifdef DEV_NETMAP 13243 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 13244 #endif /* DEV_NETMAP */ 13245 13246 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0); 13247 MODULE_VERSION(t6nex, 1); 13248 MODULE_DEPEND(t6nex, crypto, 1, 1, 1); 13249 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 13250 #ifdef DEV_NETMAP 13251 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 13252 #endif /* DEV_NETMAP */ 13253 13254 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0); 13255 MODULE_VERSION(cxgbe, 1); 13256 13257 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0); 13258 MODULE_VERSION(cxl, 1); 13259 13260 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0); 13261 MODULE_VERSION(cc, 1); 13262 13263 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0); 13264 MODULE_VERSION(vcxgbe, 1); 13265 13266 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0); 13267 MODULE_VERSION(vcxl, 1); 13268 13269 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0); 13270 MODULE_VERSION(vcc, 1); 13271