1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/param.h> 35 #include <sys/conf.h> 36 #include <sys/priv.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/queue.h> 42 #include <sys/taskqueue.h> 43 #include <sys/pciio.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pci_private.h> 47 #include <sys/firmware.h> 48 #include <sys/sbuf.h> 49 #include <sys/smp.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_types.h> 56 #include <net/if_dl.h> 57 #include <net/if_vlan_var.h> 58 #if defined(__i386__) || defined(__amd64__) 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 #endif 62 63 #include "common/common.h" 64 #include "common/t4_msg.h" 65 #include "common/t4_regs.h" 66 #include "common/t4_regs_values.h" 67 #include "t4_ioctl.h" 68 #include "t4_l2t.h" 69 70 /* T4 bus driver interface */ 71 static int t4_probe(device_t); 72 static int t4_attach(device_t); 73 static int t4_detach(device_t); 74 static device_method_t t4_methods[] = { 75 DEVMETHOD(device_probe, t4_probe), 76 DEVMETHOD(device_attach, t4_attach), 77 DEVMETHOD(device_detach, t4_detach), 78 79 DEVMETHOD_END 80 }; 81 static driver_t t4_driver = { 82 "t4nex", 83 t4_methods, 84 sizeof(struct adapter) 85 }; 86 87 88 /* T4 port (cxgbe) interface */ 89 static int cxgbe_probe(device_t); 90 static int cxgbe_attach(device_t); 91 static int cxgbe_detach(device_t); 92 static device_method_t cxgbe_methods[] = { 93 DEVMETHOD(device_probe, cxgbe_probe), 94 DEVMETHOD(device_attach, cxgbe_attach), 95 DEVMETHOD(device_detach, cxgbe_detach), 96 { 0, 0 } 97 }; 98 static driver_t cxgbe_driver = { 99 "cxgbe", 100 cxgbe_methods, 101 sizeof(struct port_info) 102 }; 103 104 static d_ioctl_t t4_ioctl; 105 static d_open_t t4_open; 106 static d_close_t t4_close; 107 108 static struct cdevsw t4_cdevsw = { 109 .d_version = D_VERSION, 110 .d_flags = 0, 111 .d_open = t4_open, 112 .d_close = t4_close, 113 .d_ioctl = t4_ioctl, 114 .d_name = "t4nex", 115 }; 116 117 /* T5 bus driver interface */ 118 static int t5_probe(device_t); 119 static device_method_t t5_methods[] = { 120 DEVMETHOD(device_probe, t5_probe), 121 DEVMETHOD(device_attach, t4_attach), 122 DEVMETHOD(device_detach, t4_detach), 123 124 DEVMETHOD_END 125 }; 126 static driver_t t5_driver = { 127 "t5nex", 128 t5_methods, 129 sizeof(struct adapter) 130 }; 131 132 133 /* T5 port (cxl) interface */ 134 static driver_t cxl_driver = { 135 "cxl", 136 cxgbe_methods, 137 sizeof(struct port_info) 138 }; 139 140 static struct cdevsw t5_cdevsw = { 141 .d_version = D_VERSION, 142 .d_flags = 0, 143 .d_open = t4_open, 144 .d_close = t4_close, 145 .d_ioctl = t4_ioctl, 146 .d_name = "t5nex", 147 }; 148 149 /* ifnet + media interface */ 150 static void cxgbe_init(void *); 151 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 152 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 153 static void cxgbe_qflush(struct ifnet *); 154 static int cxgbe_media_change(struct ifnet *); 155 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 156 157 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 158 159 /* 160 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 161 * then ADAPTER_LOCK, then t4_uld_list_lock. 162 */ 163 static struct sx t4_list_lock; 164 SLIST_HEAD(, adapter) t4_list; 165 #ifdef TCP_OFFLOAD 166 static struct sx t4_uld_list_lock; 167 SLIST_HEAD(, uld_info) t4_uld_list; 168 #endif 169 170 /* 171 * Tunables. See tweak_tunables() too. 172 * 173 * Each tunable is set to a default value here if it's known at compile-time. 174 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should 175 * provide a reasonable default when the driver is loaded. 176 * 177 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 178 * T5 are under hw.cxl. 179 */ 180 181 /* 182 * Number of queues for tx and rx, 10G and 1G, NIC and offload. 183 */ 184 #define NTXQ_10G 16 185 static int t4_ntxq10g = -1; 186 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g); 187 188 #define NRXQ_10G 8 189 static int t4_nrxq10g = -1; 190 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g); 191 192 #define NTXQ_1G 4 193 static int t4_ntxq1g = -1; 194 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g); 195 196 #define NRXQ_1G 2 197 static int t4_nrxq1g = -1; 198 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g); 199 200 #ifdef TCP_OFFLOAD 201 #define NOFLDTXQ_10G 8 202 static int t4_nofldtxq10g = -1; 203 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g); 204 205 #define NOFLDRXQ_10G 2 206 static int t4_nofldrxq10g = -1; 207 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g); 208 209 #define NOFLDTXQ_1G 2 210 static int t4_nofldtxq1g = -1; 211 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g); 212 213 #define NOFLDRXQ_1G 1 214 static int t4_nofldrxq1g = -1; 215 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g); 216 #endif 217 218 /* 219 * Holdoff parameters for 10G and 1G ports. 220 */ 221 #define TMR_IDX_10G 1 222 static int t4_tmr_idx_10g = TMR_IDX_10G; 223 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g); 224 225 #define PKTC_IDX_10G (-1) 226 static int t4_pktc_idx_10g = PKTC_IDX_10G; 227 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g); 228 229 #define TMR_IDX_1G 1 230 static int t4_tmr_idx_1g = TMR_IDX_1G; 231 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g); 232 233 #define PKTC_IDX_1G (-1) 234 static int t4_pktc_idx_1g = PKTC_IDX_1G; 235 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g); 236 237 /* 238 * Size (# of entries) of each tx and rx queue. 239 */ 240 static unsigned int t4_qsize_txq = TX_EQ_QSIZE; 241 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 242 243 static unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 244 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 245 246 /* 247 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 248 */ 249 static int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 250 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 251 252 /* 253 * Configuration file. 254 */ 255 #define DEFAULT_CF "default" 256 #define FLASH_CF "flash" 257 #define UWIRE_CF "uwire" 258 #define FPGA_CF "fpga" 259 static char t4_cfg_file[32] = DEFAULT_CF; 260 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 261 262 /* 263 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 264 * encouraged respectively). 265 */ 266 static unsigned int t4_fw_install = 1; 267 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 268 269 /* 270 * ASIC features that will be used. Disable the ones you don't want so that the 271 * chip resources aren't wasted on features that will not be used. 272 */ 273 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 274 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 275 276 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC; 277 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 278 279 static int t4_toecaps_allowed = -1; 280 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 281 282 static int t4_rdmacaps_allowed = 0; 283 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 284 285 static int t4_iscsicaps_allowed = 0; 286 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 287 288 static int t4_fcoecaps_allowed = 0; 289 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 290 291 static int t5_write_combine = 0; 292 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 293 294 struct intrs_and_queues { 295 int intr_type; /* INTx, MSI, or MSI-X */ 296 int nirq; /* Number of vectors */ 297 int intr_flags; 298 int ntxq10g; /* # of NIC txq's for each 10G port */ 299 int nrxq10g; /* # of NIC rxq's for each 10G port */ 300 int ntxq1g; /* # of NIC txq's for each 1G port */ 301 int nrxq1g; /* # of NIC rxq's for each 1G port */ 302 #ifdef TCP_OFFLOAD 303 int nofldtxq10g; /* # of TOE txq's for each 10G port */ 304 int nofldrxq10g; /* # of TOE rxq's for each 10G port */ 305 int nofldtxq1g; /* # of TOE txq's for each 1G port */ 306 int nofldrxq1g; /* # of TOE rxq's for each 1G port */ 307 #endif 308 }; 309 310 struct filter_entry { 311 uint32_t valid:1; /* filter allocated and valid */ 312 uint32_t locked:1; /* filter is administratively locked */ 313 uint32_t pending:1; /* filter action is pending firmware reply */ 314 uint32_t smtidx:8; /* Source MAC Table index for smac */ 315 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 316 317 struct t4_filter_specification fs; 318 }; 319 320 enum { 321 XGMAC_MTU = (1 << 0), 322 XGMAC_PROMISC = (1 << 1), 323 XGMAC_ALLMULTI = (1 << 2), 324 XGMAC_VLANEX = (1 << 3), 325 XGMAC_UCADDR = (1 << 4), 326 XGMAC_MCADDRS = (1 << 5), 327 328 XGMAC_ALL = 0xffff 329 }; 330 331 static int map_bars_0_and_4(struct adapter *); 332 static int map_bar_2(struct adapter *); 333 static void setup_memwin(struct adapter *); 334 static int validate_mem_range(struct adapter *, uint32_t, int); 335 static int fwmtype_to_hwmtype(int); 336 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 337 uint32_t *); 338 static void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); 339 static uint32_t position_memwin(struct adapter *, int, uint32_t); 340 static int cfg_itype_and_nqueues(struct adapter *, int, int, 341 struct intrs_and_queues *); 342 static int prep_firmware(struct adapter *); 343 static int partition_resources(struct adapter *, const struct firmware *, 344 const char *); 345 static int get_params__pre_init(struct adapter *); 346 static int get_params__post_init(struct adapter *); 347 static int set_params__post_init(struct adapter *); 348 static void t4_set_desc(struct adapter *); 349 static void build_medialist(struct port_info *); 350 static int update_mac_settings(struct port_info *, int); 351 static int cxgbe_init_synchronized(struct port_info *); 352 static int cxgbe_uninit_synchronized(struct port_info *); 353 static int setup_intr_handlers(struct adapter *); 354 static int adapter_full_init(struct adapter *); 355 static int adapter_full_uninit(struct adapter *); 356 static int port_full_init(struct port_info *); 357 static int port_full_uninit(struct port_info *); 358 static void quiesce_eq(struct adapter *, struct sge_eq *); 359 static void quiesce_iq(struct adapter *, struct sge_iq *); 360 static void quiesce_fl(struct adapter *, struct sge_fl *); 361 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 362 driver_intr_t *, void *, char *); 363 static int t4_free_irq(struct adapter *, struct irq *); 364 static void reg_block_dump(struct adapter *, uint8_t *, unsigned int, 365 unsigned int); 366 static void t4_get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 367 static void cxgbe_tick(void *); 368 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 369 static int cpl_not_handled(struct sge_iq *, const struct rss_header *, 370 struct mbuf *); 371 static int an_not_handled(struct sge_iq *, const struct rsp_ctrl *); 372 static int fw_msg_not_handled(struct adapter *, const __be64 *); 373 static int t4_sysctls(struct adapter *); 374 static int cxgbe_sysctls(struct port_info *); 375 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 376 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 377 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 378 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 379 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 380 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 381 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 382 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 383 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 384 #ifdef SBUF_DRAIN 385 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 386 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 387 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 388 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 389 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 390 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 391 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 392 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 393 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 394 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 395 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 396 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 397 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 398 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 399 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 400 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 401 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 402 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 403 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 404 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 405 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 406 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 407 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 408 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 409 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 410 #endif 411 static inline void txq_start(struct ifnet *, struct sge_txq *); 412 static uint32_t fconf_to_mode(uint32_t); 413 static uint32_t mode_to_fconf(uint32_t); 414 static uint32_t fspec_to_fconf(struct t4_filter_specification *); 415 static int get_filter_mode(struct adapter *, uint32_t *); 416 static int set_filter_mode(struct adapter *, uint32_t); 417 static inline uint64_t get_filter_hits(struct adapter *, uint32_t); 418 static int get_filter(struct adapter *, struct t4_filter *); 419 static int set_filter(struct adapter *, struct t4_filter *); 420 static int del_filter(struct adapter *, struct t4_filter *); 421 static void clear_filter(struct filter_entry *); 422 static int set_filter_wr(struct adapter *, int); 423 static int del_filter_wr(struct adapter *, int); 424 static int get_sge_context(struct adapter *, struct t4_sge_context *); 425 static int load_fw(struct adapter *, struct t4_data *); 426 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 427 static int read_i2c(struct adapter *, struct t4_i2c_data *); 428 static int set_sched_class(struct adapter *, struct t4_sched_params *); 429 static int set_sched_queue(struct adapter *, struct t4_sched_queue *); 430 #ifdef TCP_OFFLOAD 431 static int toe_capability(struct port_info *, int); 432 #endif 433 static int mod_event(module_t, int, void *); 434 435 struct { 436 uint16_t device; 437 char *desc; 438 } t4_pciids[] = { 439 {0xa000, "Chelsio Terminator 4 FPGA"}, 440 {0x4400, "Chelsio T440-dbg"}, 441 {0x4401, "Chelsio T420-CR"}, 442 {0x4402, "Chelsio T422-CR"}, 443 {0x4403, "Chelsio T440-CR"}, 444 {0x4404, "Chelsio T420-BCH"}, 445 {0x4405, "Chelsio T440-BCH"}, 446 {0x4406, "Chelsio T440-CH"}, 447 {0x4407, "Chelsio T420-SO"}, 448 {0x4408, "Chelsio T420-CX"}, 449 {0x4409, "Chelsio T420-BT"}, 450 {0x440a, "Chelsio T404-BT"}, 451 {0x440e, "Chelsio T440-LP-CR"}, 452 }, t5_pciids[] = { 453 {0xb000, "Chelsio Terminator 5 FPGA"}, 454 {0x5400, "Chelsio T580-dbg"}, 455 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 456 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 457 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 458 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 459 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 460 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 461 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 462 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 463 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 464 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 465 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 466 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 467 #ifdef notyet 468 {0x5404, "Chelsio T520-BCH"}, 469 {0x5405, "Chelsio T540-BCH"}, 470 {0x5406, "Chelsio T540-CH"}, 471 {0x5408, "Chelsio T520-CX"}, 472 {0x540b, "Chelsio B520-SR"}, 473 {0x540c, "Chelsio B504-BT"}, 474 {0x540f, "Chelsio Amsterdam"}, 475 {0x5413, "Chelsio T580-CHR"}, 476 #endif 477 }; 478 479 #ifdef TCP_OFFLOAD 480 /* 481 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 482 * exactly the same for both rxq and ofld_rxq. 483 */ 484 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 485 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 486 #endif 487 488 /* No easy way to include t4_msg.h before adapter.h so we check this way */ 489 CTASSERT(nitems(((struct adapter *)0)->cpl_handler) == NUM_CPL_CMDS); 490 CTASSERT(nitems(((struct adapter *)0)->fw_msg_handler) == NUM_FW6_TYPES); 491 492 static int 493 t4_probe(device_t dev) 494 { 495 int i; 496 uint16_t v = pci_get_vendor(dev); 497 uint16_t d = pci_get_device(dev); 498 uint8_t f = pci_get_function(dev); 499 500 if (v != PCI_VENDOR_ID_CHELSIO) 501 return (ENXIO); 502 503 /* Attach only to PF0 of the FPGA */ 504 if (d == 0xa000 && f != 0) 505 return (ENXIO); 506 507 for (i = 0; i < nitems(t4_pciids); i++) { 508 if (d == t4_pciids[i].device) { 509 device_set_desc(dev, t4_pciids[i].desc); 510 return (BUS_PROBE_DEFAULT); 511 } 512 } 513 514 return (ENXIO); 515 } 516 517 static int 518 t5_probe(device_t dev) 519 { 520 int i; 521 uint16_t v = pci_get_vendor(dev); 522 uint16_t d = pci_get_device(dev); 523 uint8_t f = pci_get_function(dev); 524 525 if (v != PCI_VENDOR_ID_CHELSIO) 526 return (ENXIO); 527 528 /* Attach only to PF0 of the FPGA */ 529 if (d == 0xb000 && f != 0) 530 return (ENXIO); 531 532 for (i = 0; i < nitems(t5_pciids); i++) { 533 if (d == t5_pciids[i].device) { 534 device_set_desc(dev, t5_pciids[i].desc); 535 return (BUS_PROBE_DEFAULT); 536 } 537 } 538 539 return (ENXIO); 540 } 541 542 static int 543 t4_attach(device_t dev) 544 { 545 struct adapter *sc; 546 int rc = 0, i, n10g, n1g, rqidx, tqidx; 547 struct intrs_and_queues iaq; 548 struct sge *s; 549 #ifdef TCP_OFFLOAD 550 int ofld_rqidx, ofld_tqidx; 551 #endif 552 const char *pcie_ts; 553 554 sc = device_get_softc(dev); 555 sc->dev = dev; 556 557 pci_enable_busmaster(dev); 558 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 559 uint32_t v; 560 561 pci_set_max_read_req(dev, 4096); 562 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 563 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 564 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 565 } 566 567 sc->traceq = -1; 568 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 569 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 570 device_get_nameunit(dev)); 571 572 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 573 device_get_nameunit(dev)); 574 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 575 sx_xlock(&t4_list_lock); 576 SLIST_INSERT_HEAD(&t4_list, sc, link); 577 sx_xunlock(&t4_list_lock); 578 579 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 580 TAILQ_INIT(&sc->sfl); 581 callout_init(&sc->sfl_callout, CALLOUT_MPSAFE); 582 583 rc = map_bars_0_and_4(sc); 584 if (rc != 0) 585 goto done; /* error message displayed already */ 586 587 /* 588 * This is the real PF# to which we're attaching. Works from within PCI 589 * passthrough environments too, where pci_get_function() could return a 590 * different PF# depending on the passthrough configuration. We need to 591 * use the real PF# in all our communication with the firmware. 592 */ 593 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI)); 594 sc->mbox = sc->pf; 595 596 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 597 sc->an_handler = an_not_handled; 598 for (i = 0; i < nitems(sc->cpl_handler); i++) 599 sc->cpl_handler[i] = cpl_not_handled; 600 for (i = 0; i < nitems(sc->fw_msg_handler); i++) 601 sc->fw_msg_handler[i] = fw_msg_not_handled; 602 t4_register_cpl_handler(sc, CPL_SET_TCB_RPL, t4_filter_rpl); 603 t4_register_cpl_handler(sc, CPL_TRACE_PKT, t4_trace_pkt); 604 t4_register_cpl_handler(sc, CPL_TRACE_PKT_T5, t5_trace_pkt); 605 t4_init_sge_cpl_handlers(sc); 606 607 /* Prepare the adapter for operation */ 608 rc = -t4_prep_adapter(sc); 609 if (rc != 0) { 610 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 611 goto done; 612 } 613 614 /* 615 * Do this really early, with the memory windows set up even before the 616 * character device. The userland tool's register i/o and mem read 617 * will work even in "recovery mode". 618 */ 619 setup_memwin(sc); 620 sc->cdev = make_dev(is_t4(sc) ? &t4_cdevsw : &t5_cdevsw, 621 device_get_unit(dev), UID_ROOT, GID_WHEEL, 0600, "%s", 622 device_get_nameunit(dev)); 623 if (sc->cdev == NULL) 624 device_printf(dev, "failed to create nexus char device.\n"); 625 else 626 sc->cdev->si_drv1 = sc; 627 628 /* Go no further if recovery mode has been requested. */ 629 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 630 device_printf(dev, "recovery mode.\n"); 631 goto done; 632 } 633 634 /* Prepare the firmware for operation */ 635 rc = prep_firmware(sc); 636 if (rc != 0) 637 goto done; /* error message displayed already */ 638 639 rc = get_params__post_init(sc); 640 if (rc != 0) 641 goto done; /* error message displayed already */ 642 643 rc = set_params__post_init(sc); 644 if (rc != 0) 645 goto done; /* error message displayed already */ 646 647 rc = map_bar_2(sc); 648 if (rc != 0) 649 goto done; /* error message displayed already */ 650 651 rc = t4_create_dma_tag(sc); 652 if (rc != 0) 653 goto done; /* error message displayed already */ 654 655 /* 656 * First pass over all the ports - allocate VIs and initialize some 657 * basic parameters like mac address, port type, etc. We also figure 658 * out whether a port is 10G or 1G and use that information when 659 * calculating how many interrupts to attempt to allocate. 660 */ 661 n10g = n1g = 0; 662 for_each_port(sc, i) { 663 struct port_info *pi; 664 665 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 666 sc->port[i] = pi; 667 668 /* These must be set before t4_port_init */ 669 pi->adapter = sc; 670 pi->port_id = i; 671 672 /* Allocate the vi and initialize parameters like mac addr */ 673 rc = -t4_port_init(pi, sc->mbox, sc->pf, 0); 674 if (rc != 0) { 675 device_printf(dev, "unable to initialize port %d: %d\n", 676 i, rc); 677 free(pi, M_CXGBE); 678 sc->port[i] = NULL; 679 goto done; 680 } 681 682 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 683 device_get_nameunit(dev), i); 684 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 685 sc->chan_map[pi->tx_chan] = i; 686 687 if (is_10G_port(pi) || is_40G_port(pi)) { 688 n10g++; 689 pi->tmr_idx = t4_tmr_idx_10g; 690 pi->pktc_idx = t4_pktc_idx_10g; 691 } else { 692 n1g++; 693 pi->tmr_idx = t4_tmr_idx_1g; 694 pi->pktc_idx = t4_pktc_idx_1g; 695 } 696 697 pi->xact_addr_filt = -1; 698 pi->linkdnrc = -1; 699 700 pi->qsize_rxq = t4_qsize_rxq; 701 pi->qsize_txq = t4_qsize_txq; 702 703 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1); 704 if (pi->dev == NULL) { 705 device_printf(dev, 706 "failed to add device for port %d.\n", i); 707 rc = ENXIO; 708 goto done; 709 } 710 device_set_softc(pi->dev, pi); 711 } 712 713 /* 714 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 715 */ 716 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq); 717 if (rc != 0) 718 goto done; /* error message displayed already */ 719 720 sc->intr_type = iaq.intr_type; 721 sc->intr_count = iaq.nirq; 722 sc->flags |= iaq.intr_flags; 723 724 s = &sc->sge; 725 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; 726 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; 727 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 728 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 729 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 730 731 #ifdef TCP_OFFLOAD 732 if (is_offload(sc)) { 733 734 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g; 735 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g; 736 s->neq += s->nofldtxq + s->nofldrxq; 737 s->niq += s->nofldrxq; 738 739 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 740 M_CXGBE, M_ZERO | M_WAITOK); 741 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 742 M_CXGBE, M_ZERO | M_WAITOK); 743 } 744 #endif 745 746 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE, 747 M_ZERO | M_WAITOK); 748 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 749 M_ZERO | M_WAITOK); 750 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 751 M_ZERO | M_WAITOK); 752 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 753 M_ZERO | M_WAITOK); 754 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 755 M_ZERO | M_WAITOK); 756 757 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 758 M_ZERO | M_WAITOK); 759 760 t4_init_l2t(sc, M_WAITOK); 761 762 /* 763 * Second pass over the ports. This time we know the number of rx and 764 * tx queues that each port should get. 765 */ 766 rqidx = tqidx = 0; 767 #ifdef TCP_OFFLOAD 768 ofld_rqidx = ofld_tqidx = 0; 769 #endif 770 for_each_port(sc, i) { 771 struct port_info *pi = sc->port[i]; 772 773 if (pi == NULL) 774 continue; 775 776 pi->first_rxq = rqidx; 777 pi->first_txq = tqidx; 778 if (is_10G_port(pi) || is_40G_port(pi)) { 779 pi->nrxq = iaq.nrxq10g; 780 pi->ntxq = iaq.ntxq10g; 781 } else { 782 pi->nrxq = iaq.nrxq1g; 783 pi->ntxq = iaq.ntxq1g; 784 } 785 786 rqidx += pi->nrxq; 787 tqidx += pi->ntxq; 788 789 #ifdef TCP_OFFLOAD 790 if (is_offload(sc)) { 791 pi->first_ofld_rxq = ofld_rqidx; 792 pi->first_ofld_txq = ofld_tqidx; 793 if (is_10G_port(pi) || is_40G_port(pi)) { 794 pi->nofldrxq = iaq.nofldrxq10g; 795 pi->nofldtxq = iaq.nofldtxq10g; 796 } else { 797 pi->nofldrxq = iaq.nofldrxq1g; 798 pi->nofldtxq = iaq.nofldtxq1g; 799 } 800 ofld_rqidx += pi->nofldrxq; 801 ofld_tqidx += pi->nofldtxq; 802 } 803 #endif 804 } 805 806 rc = setup_intr_handlers(sc); 807 if (rc != 0) { 808 device_printf(dev, 809 "failed to setup interrupt handlers: %d\n", rc); 810 goto done; 811 } 812 813 rc = bus_generic_attach(dev); 814 if (rc != 0) { 815 device_printf(dev, 816 "failed to attach all child ports: %d\n", rc); 817 goto done; 818 } 819 820 switch (sc->params.pci.speed) { 821 case 0x1: 822 pcie_ts = "2.5"; 823 break; 824 case 0x2: 825 pcie_ts = "5.0"; 826 break; 827 case 0x3: 828 pcie_ts = "8.0"; 829 break; 830 default: 831 pcie_ts = "??"; 832 break; 833 } 834 device_printf(dev, 835 "PCIe x%d (%s GTS/s) (%d), %d ports, %d %s interrupt%s, %d eq, %d iq\n", 836 sc->params.pci.width, pcie_ts, sc->params.pci.speed, 837 sc->params.nports, sc->intr_count, 838 sc->intr_type == INTR_MSIX ? "MSI-X" : 839 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 840 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 841 842 t4_set_desc(sc); 843 844 done: 845 if (rc != 0 && sc->cdev) { 846 /* cdev was created and so cxgbetool works; recover that way. */ 847 device_printf(dev, 848 "error during attach, adapter is now in recovery mode.\n"); 849 rc = 0; 850 } 851 852 if (rc != 0) 853 t4_detach(dev); 854 else 855 t4_sysctls(sc); 856 857 return (rc); 858 } 859 860 /* 861 * Idempotent 862 */ 863 static int 864 t4_detach(device_t dev) 865 { 866 struct adapter *sc; 867 struct port_info *pi; 868 int i, rc; 869 870 sc = device_get_softc(dev); 871 872 if (sc->flags & FULL_INIT_DONE) 873 t4_intr_disable(sc); 874 875 if (sc->cdev) { 876 destroy_dev(sc->cdev); 877 sc->cdev = NULL; 878 } 879 880 rc = bus_generic_detach(dev); 881 if (rc) { 882 device_printf(dev, 883 "failed to detach child devices: %d\n", rc); 884 return (rc); 885 } 886 887 for (i = 0; i < sc->intr_count; i++) 888 t4_free_irq(sc, &sc->irq[i]); 889 890 for (i = 0; i < MAX_NPORTS; i++) { 891 pi = sc->port[i]; 892 if (pi) { 893 t4_free_vi(pi->adapter, sc->mbox, sc->pf, 0, pi->viid); 894 if (pi->dev) 895 device_delete_child(dev, pi->dev); 896 897 mtx_destroy(&pi->pi_lock); 898 free(pi, M_CXGBE); 899 } 900 } 901 902 if (sc->flags & FULL_INIT_DONE) 903 adapter_full_uninit(sc); 904 905 if (sc->flags & FW_OK) 906 t4_fw_bye(sc, sc->mbox); 907 908 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 909 pci_release_msi(dev); 910 911 if (sc->regs_res) 912 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 913 sc->regs_res); 914 915 if (sc->udbs_res) 916 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 917 sc->udbs_res); 918 919 if (sc->msix_res) 920 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 921 sc->msix_res); 922 923 if (sc->l2t) 924 t4_free_l2t(sc->l2t); 925 926 #ifdef TCP_OFFLOAD 927 free(sc->sge.ofld_rxq, M_CXGBE); 928 free(sc->sge.ofld_txq, M_CXGBE); 929 #endif 930 free(sc->irq, M_CXGBE); 931 free(sc->sge.rxq, M_CXGBE); 932 free(sc->sge.txq, M_CXGBE); 933 free(sc->sge.ctrlq, M_CXGBE); 934 free(sc->sge.iqmap, M_CXGBE); 935 free(sc->sge.eqmap, M_CXGBE); 936 free(sc->tids.ftid_tab, M_CXGBE); 937 t4_destroy_dma_tag(sc); 938 if (mtx_initialized(&sc->sc_lock)) { 939 sx_xlock(&t4_list_lock); 940 SLIST_REMOVE(&t4_list, sc, adapter, link); 941 sx_xunlock(&t4_list_lock); 942 mtx_destroy(&sc->sc_lock); 943 } 944 945 if (mtx_initialized(&sc->tids.ftid_lock)) 946 mtx_destroy(&sc->tids.ftid_lock); 947 if (mtx_initialized(&sc->sfl_lock)) 948 mtx_destroy(&sc->sfl_lock); 949 if (mtx_initialized(&sc->ifp_lock)) 950 mtx_destroy(&sc->ifp_lock); 951 952 bzero(sc, sizeof(*sc)); 953 954 return (0); 955 } 956 957 958 static int 959 cxgbe_probe(device_t dev) 960 { 961 char buf[128]; 962 struct port_info *pi = device_get_softc(dev); 963 964 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 965 device_set_desc_copy(dev, buf); 966 967 return (BUS_PROBE_DEFAULT); 968 } 969 970 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 971 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 972 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 973 #define T4_CAP_ENABLE (T4_CAP) 974 975 static int 976 cxgbe_attach(device_t dev) 977 { 978 struct port_info *pi = device_get_softc(dev); 979 struct ifnet *ifp; 980 981 /* Allocate an ifnet and set it up */ 982 ifp = if_alloc(IFT_ETHER); 983 if (ifp == NULL) { 984 device_printf(dev, "Cannot allocate ifnet\n"); 985 return (ENOMEM); 986 } 987 pi->ifp = ifp; 988 ifp->if_softc = pi; 989 990 callout_init(&pi->tick, CALLOUT_MPSAFE); 991 992 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 993 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 994 995 ifp->if_init = cxgbe_init; 996 ifp->if_ioctl = cxgbe_ioctl; 997 ifp->if_transmit = cxgbe_transmit; 998 ifp->if_qflush = cxgbe_qflush; 999 1000 ifp->if_capabilities = T4_CAP; 1001 #ifdef TCP_OFFLOAD 1002 if (is_offload(pi->adapter)) 1003 ifp->if_capabilities |= IFCAP_TOE; 1004 #endif 1005 ifp->if_capenable = T4_CAP_ENABLE; 1006 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1007 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1008 1009 /* Initialize ifmedia for this port */ 1010 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1011 cxgbe_media_status); 1012 build_medialist(pi); 1013 1014 pi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1015 EVENTHANDLER_PRI_ANY); 1016 1017 ether_ifattach(ifp, pi->hw_addr); 1018 1019 #ifdef TCP_OFFLOAD 1020 if (is_offload(pi->adapter)) { 1021 device_printf(dev, 1022 "%d txq, %d rxq (NIC); %d txq, %d rxq (TOE)\n", 1023 pi->ntxq, pi->nrxq, pi->nofldtxq, pi->nofldrxq); 1024 } else 1025 #endif 1026 device_printf(dev, "%d txq, %d rxq\n", pi->ntxq, pi->nrxq); 1027 1028 cxgbe_sysctls(pi); 1029 1030 return (0); 1031 } 1032 1033 static int 1034 cxgbe_detach(device_t dev) 1035 { 1036 struct port_info *pi = device_get_softc(dev); 1037 struct adapter *sc = pi->adapter; 1038 struct ifnet *ifp = pi->ifp; 1039 1040 /* Tell if_ioctl and if_init that the port is going away */ 1041 ADAPTER_LOCK(sc); 1042 SET_DOOMED(pi); 1043 wakeup(&sc->flags); 1044 while (IS_BUSY(sc)) 1045 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 1046 SET_BUSY(sc); 1047 #ifdef INVARIANTS 1048 sc->last_op = "t4detach"; 1049 sc->last_op_thr = curthread; 1050 #endif 1051 ADAPTER_UNLOCK(sc); 1052 1053 if (pi->flags & HAS_TRACEQ) { 1054 sc->traceq = -1; /* cloner should not create ifnet */ 1055 t4_tracer_port_detach(sc); 1056 } 1057 1058 if (pi->vlan_c) 1059 EVENTHANDLER_DEREGISTER(vlan_config, pi->vlan_c); 1060 1061 PORT_LOCK(pi); 1062 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1063 callout_stop(&pi->tick); 1064 PORT_UNLOCK(pi); 1065 callout_drain(&pi->tick); 1066 1067 /* Let detach proceed even if these fail. */ 1068 cxgbe_uninit_synchronized(pi); 1069 port_full_uninit(pi); 1070 1071 ifmedia_removeall(&pi->media); 1072 ether_ifdetach(pi->ifp); 1073 if_free(pi->ifp); 1074 1075 ADAPTER_LOCK(sc); 1076 CLR_BUSY(sc); 1077 wakeup(&sc->flags); 1078 ADAPTER_UNLOCK(sc); 1079 1080 return (0); 1081 } 1082 1083 static void 1084 cxgbe_init(void *arg) 1085 { 1086 struct port_info *pi = arg; 1087 struct adapter *sc = pi->adapter; 1088 1089 if (begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4init") != 0) 1090 return; 1091 cxgbe_init_synchronized(pi); 1092 end_synchronized_op(sc, 0); 1093 } 1094 1095 static int 1096 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1097 { 1098 int rc = 0, mtu, flags; 1099 struct port_info *pi = ifp->if_softc; 1100 struct adapter *sc = pi->adapter; 1101 struct ifreq *ifr = (struct ifreq *)data; 1102 uint32_t mask; 1103 1104 switch (cmd) { 1105 case SIOCSIFMTU: 1106 mtu = ifr->ifr_mtu; 1107 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) 1108 return (EINVAL); 1109 1110 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4mtu"); 1111 if (rc) 1112 return (rc); 1113 ifp->if_mtu = mtu; 1114 if (pi->flags & PORT_INIT_DONE) { 1115 t4_update_fl_bufsize(ifp); 1116 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1117 rc = update_mac_settings(pi, XGMAC_MTU); 1118 } 1119 end_synchronized_op(sc, 0); 1120 break; 1121 1122 case SIOCSIFFLAGS: 1123 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4flg"); 1124 if (rc) 1125 return (rc); 1126 1127 if (ifp->if_flags & IFF_UP) { 1128 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1129 flags = pi->if_flags; 1130 if ((ifp->if_flags ^ flags) & 1131 (IFF_PROMISC | IFF_ALLMULTI)) { 1132 rc = update_mac_settings(pi, 1133 XGMAC_PROMISC | XGMAC_ALLMULTI); 1134 } 1135 } else 1136 rc = cxgbe_init_synchronized(pi); 1137 pi->if_flags = ifp->if_flags; 1138 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1139 rc = cxgbe_uninit_synchronized(pi); 1140 end_synchronized_op(sc, 0); 1141 break; 1142 1143 case SIOCADDMULTI: 1144 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1145 rc = begin_synchronized_op(sc, pi, HOLD_LOCK, "t4multi"); 1146 if (rc) 1147 return (rc); 1148 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1149 rc = update_mac_settings(pi, XGMAC_MCADDRS); 1150 end_synchronized_op(sc, LOCK_HELD); 1151 break; 1152 1153 case SIOCSIFCAP: 1154 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4cap"); 1155 if (rc) 1156 return (rc); 1157 1158 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1159 if (mask & IFCAP_TXCSUM) { 1160 ifp->if_capenable ^= IFCAP_TXCSUM; 1161 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1162 1163 if (IFCAP_TSO4 & ifp->if_capenable && 1164 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1165 ifp->if_capenable &= ~IFCAP_TSO4; 1166 if_printf(ifp, 1167 "tso4 disabled due to -txcsum.\n"); 1168 } 1169 } 1170 if (mask & IFCAP_TXCSUM_IPV6) { 1171 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1172 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1173 1174 if (IFCAP_TSO6 & ifp->if_capenable && 1175 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1176 ifp->if_capenable &= ~IFCAP_TSO6; 1177 if_printf(ifp, 1178 "tso6 disabled due to -txcsum6.\n"); 1179 } 1180 } 1181 if (mask & IFCAP_RXCSUM) 1182 ifp->if_capenable ^= IFCAP_RXCSUM; 1183 if (mask & IFCAP_RXCSUM_IPV6) 1184 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1185 1186 /* 1187 * Note that we leave CSUM_TSO alone (it is always set). The 1188 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1189 * sending a TSO request our way, so it's sufficient to toggle 1190 * IFCAP_TSOx only. 1191 */ 1192 if (mask & IFCAP_TSO4) { 1193 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1194 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1195 if_printf(ifp, "enable txcsum first.\n"); 1196 rc = EAGAIN; 1197 goto fail; 1198 } 1199 ifp->if_capenable ^= IFCAP_TSO4; 1200 } 1201 if (mask & IFCAP_TSO6) { 1202 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1203 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1204 if_printf(ifp, "enable txcsum6 first.\n"); 1205 rc = EAGAIN; 1206 goto fail; 1207 } 1208 ifp->if_capenable ^= IFCAP_TSO6; 1209 } 1210 if (mask & IFCAP_LRO) { 1211 #if defined(INET) || defined(INET6) 1212 int i; 1213 struct sge_rxq *rxq; 1214 1215 ifp->if_capenable ^= IFCAP_LRO; 1216 for_each_rxq(pi, i, rxq) { 1217 if (ifp->if_capenable & IFCAP_LRO) 1218 rxq->iq.flags |= IQ_LRO_ENABLED; 1219 else 1220 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1221 } 1222 #endif 1223 } 1224 #ifdef TCP_OFFLOAD 1225 if (mask & IFCAP_TOE) { 1226 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1227 1228 rc = toe_capability(pi, enable); 1229 if (rc != 0) 1230 goto fail; 1231 1232 ifp->if_capenable ^= mask; 1233 } 1234 #endif 1235 if (mask & IFCAP_VLAN_HWTAGGING) { 1236 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1237 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1238 rc = update_mac_settings(pi, XGMAC_VLANEX); 1239 } 1240 if (mask & IFCAP_VLAN_MTU) { 1241 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1242 1243 /* Need to find out how to disable auto-mtu-inflation */ 1244 } 1245 if (mask & IFCAP_VLAN_HWTSO) 1246 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1247 if (mask & IFCAP_VLAN_HWCSUM) 1248 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1249 1250 #ifdef VLAN_CAPABILITIES 1251 VLAN_CAPABILITIES(ifp); 1252 #endif 1253 fail: 1254 end_synchronized_op(sc, 0); 1255 break; 1256 1257 case SIOCSIFMEDIA: 1258 case SIOCGIFMEDIA: 1259 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 1260 break; 1261 1262 default: 1263 rc = ether_ioctl(ifp, cmd, data); 1264 } 1265 1266 return (rc); 1267 } 1268 1269 static int 1270 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1271 { 1272 struct port_info *pi = ifp->if_softc; 1273 struct adapter *sc = pi->adapter; 1274 struct sge_txq *txq = &sc->sge.txq[pi->first_txq]; 1275 struct buf_ring *br; 1276 int rc; 1277 1278 M_ASSERTPKTHDR(m); 1279 1280 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1281 m_freem(m); 1282 return (ENETDOWN); 1283 } 1284 1285 if (m->m_flags & M_FLOWID) 1286 txq += (m->m_pkthdr.flowid % pi->ntxq); 1287 br = txq->br; 1288 1289 if (TXQ_TRYLOCK(txq) == 0) { 1290 struct sge_eq *eq = &txq->eq; 1291 1292 /* 1293 * It is possible that t4_eth_tx finishes up and releases the 1294 * lock between the TRYLOCK above and the drbr_enqueue here. We 1295 * need to make sure that this mbuf doesn't just sit there in 1296 * the drbr. 1297 */ 1298 1299 rc = drbr_enqueue(ifp, br, m); 1300 if (rc == 0 && callout_pending(&eq->tx_callout) == 0 && 1301 !(eq->flags & EQ_DOOMED)) 1302 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1303 return (rc); 1304 } 1305 1306 /* 1307 * txq->m is the mbuf that is held up due to a temporary shortage of 1308 * resources and it should be put on the wire first. Then what's in 1309 * drbr and finally the mbuf that was just passed in to us. 1310 * 1311 * Return code should indicate the fate of the mbuf that was passed in 1312 * this time. 1313 */ 1314 1315 TXQ_LOCK_ASSERT_OWNED(txq); 1316 if (drbr_needs_enqueue(ifp, br) || txq->m) { 1317 1318 /* Queued for transmission. */ 1319 1320 rc = drbr_enqueue(ifp, br, m); 1321 m = txq->m ? txq->m : drbr_dequeue(ifp, br); 1322 (void) t4_eth_tx(ifp, txq, m); 1323 TXQ_UNLOCK(txq); 1324 return (rc); 1325 } 1326 1327 /* Direct transmission. */ 1328 rc = t4_eth_tx(ifp, txq, m); 1329 if (rc != 0 && txq->m) 1330 rc = 0; /* held, will be transmitted soon (hopefully) */ 1331 1332 TXQ_UNLOCK(txq); 1333 return (rc); 1334 } 1335 1336 static void 1337 cxgbe_qflush(struct ifnet *ifp) 1338 { 1339 struct port_info *pi = ifp->if_softc; 1340 struct sge_txq *txq; 1341 int i; 1342 struct mbuf *m; 1343 1344 /* queues do not exist if !PORT_INIT_DONE. */ 1345 if (pi->flags & PORT_INIT_DONE) { 1346 for_each_txq(pi, i, txq) { 1347 TXQ_LOCK(txq); 1348 m_freem(txq->m); 1349 txq->m = NULL; 1350 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) 1351 m_freem(m); 1352 TXQ_UNLOCK(txq); 1353 } 1354 } 1355 if_qflush(ifp); 1356 } 1357 1358 static int 1359 cxgbe_media_change(struct ifnet *ifp) 1360 { 1361 struct port_info *pi = ifp->if_softc; 1362 1363 device_printf(pi->dev, "%s unimplemented.\n", __func__); 1364 1365 return (EOPNOTSUPP); 1366 } 1367 1368 static void 1369 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1370 { 1371 struct port_info *pi = ifp->if_softc; 1372 struct ifmedia_entry *cur = pi->media.ifm_cur; 1373 int speed = pi->link_cfg.speed; 1374 int data = (pi->port_type << 8) | pi->mod_type; 1375 1376 if (cur->ifm_data != data) { 1377 build_medialist(pi); 1378 cur = pi->media.ifm_cur; 1379 } 1380 1381 ifmr->ifm_status = IFM_AVALID; 1382 if (!pi->link_cfg.link_ok) 1383 return; 1384 1385 ifmr->ifm_status |= IFM_ACTIVE; 1386 1387 /* active and current will differ iff current media is autoselect. */ 1388 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 1389 return; 1390 1391 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 1392 if (speed == SPEED_10000) 1393 ifmr->ifm_active |= IFM_10G_T; 1394 else if (speed == SPEED_1000) 1395 ifmr->ifm_active |= IFM_1000_T; 1396 else if (speed == SPEED_100) 1397 ifmr->ifm_active |= IFM_100_TX; 1398 else if (speed == SPEED_10) 1399 ifmr->ifm_active |= IFM_10_T; 1400 else 1401 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 1402 speed)); 1403 } 1404 1405 void 1406 t4_fatal_err(struct adapter *sc) 1407 { 1408 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 1409 t4_intr_disable(sc); 1410 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 1411 device_get_nameunit(sc->dev)); 1412 } 1413 1414 static int 1415 map_bars_0_and_4(struct adapter *sc) 1416 { 1417 sc->regs_rid = PCIR_BAR(0); 1418 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1419 &sc->regs_rid, RF_ACTIVE); 1420 if (sc->regs_res == NULL) { 1421 device_printf(sc->dev, "cannot map registers.\n"); 1422 return (ENXIO); 1423 } 1424 sc->bt = rman_get_bustag(sc->regs_res); 1425 sc->bh = rman_get_bushandle(sc->regs_res); 1426 sc->mmio_len = rman_get_size(sc->regs_res); 1427 setbit(&sc->doorbells, DOORBELL_KDB); 1428 1429 sc->msix_rid = PCIR_BAR(4); 1430 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1431 &sc->msix_rid, RF_ACTIVE); 1432 if (sc->msix_res == NULL) { 1433 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 1434 return (ENXIO); 1435 } 1436 1437 return (0); 1438 } 1439 1440 static int 1441 map_bar_2(struct adapter *sc) 1442 { 1443 1444 /* 1445 * T4: only iWARP driver uses the userspace doorbells. There is no need 1446 * to map it if RDMA is disabled. 1447 */ 1448 if (is_t4(sc) && sc->rdmacaps == 0) 1449 return (0); 1450 1451 sc->udbs_rid = PCIR_BAR(2); 1452 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1453 &sc->udbs_rid, RF_ACTIVE); 1454 if (sc->udbs_res == NULL) { 1455 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 1456 return (ENXIO); 1457 } 1458 sc->udbs_base = rman_get_virtual(sc->udbs_res); 1459 1460 if (is_t5(sc)) { 1461 setbit(&sc->doorbells, DOORBELL_UDB); 1462 #if defined(__i386__) || defined(__amd64__) 1463 if (t5_write_combine) { 1464 int rc; 1465 1466 /* 1467 * Enable write combining on BAR2. This is the 1468 * userspace doorbell BAR and is split into 128B 1469 * (UDBS_SEG_SIZE) doorbell regions, each associated 1470 * with an egress queue. The first 64B has the doorbell 1471 * and the second 64B can be used to submit a tx work 1472 * request with an implicit doorbell. 1473 */ 1474 1475 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 1476 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 1477 if (rc == 0) { 1478 clrbit(&sc->doorbells, DOORBELL_UDB); 1479 setbit(&sc->doorbells, DOORBELL_WCWR); 1480 setbit(&sc->doorbells, DOORBELL_UDBWC); 1481 } else { 1482 device_printf(sc->dev, 1483 "couldn't enable write combining: %d\n", 1484 rc); 1485 } 1486 1487 t4_write_reg(sc, A_SGE_STAT_CFG, 1488 V_STATSOURCE_T5(7) | V_STATMODE(0)); 1489 } 1490 #endif 1491 } 1492 1493 return (0); 1494 } 1495 1496 static const struct memwin t4_memwin[] = { 1497 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 1498 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 1499 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 1500 }; 1501 1502 static const struct memwin t5_memwin[] = { 1503 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 1504 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 1505 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 1506 }; 1507 1508 static void 1509 setup_memwin(struct adapter *sc) 1510 { 1511 const struct memwin *mw; 1512 int i, n; 1513 uint32_t bar0; 1514 1515 if (is_t4(sc)) { 1516 /* 1517 * Read low 32b of bar0 indirectly via the hardware backdoor 1518 * mechanism. Works from within PCI passthrough environments 1519 * too, where rman_get_start() can return a different value. We 1520 * need to program the T4 memory window decoders with the actual 1521 * addresses that will be coming across the PCIe link. 1522 */ 1523 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 1524 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 1525 1526 mw = &t4_memwin[0]; 1527 n = nitems(t4_memwin); 1528 } else { 1529 /* T5 uses the relative offset inside the PCIe BAR */ 1530 bar0 = 0; 1531 1532 mw = &t5_memwin[0]; 1533 n = nitems(t5_memwin); 1534 } 1535 1536 for (i = 0; i < n; i++, mw++) { 1537 t4_write_reg(sc, 1538 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 1539 (mw->base + bar0) | V_BIR(0) | 1540 V_WINDOW(ilog2(mw->aperture) - 10)); 1541 } 1542 1543 /* flush */ 1544 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 1545 } 1546 1547 /* 1548 * Verify that the memory range specified by the addr/len pair is valid and lies 1549 * entirely within a single region (EDCx or MCx). 1550 */ 1551 static int 1552 validate_mem_range(struct adapter *sc, uint32_t addr, int len) 1553 { 1554 uint32_t em, addr_len, maddr, mlen; 1555 1556 /* Memory can only be accessed in naturally aligned 4 byte units */ 1557 if (addr & 3 || len & 3 || len == 0) 1558 return (EINVAL); 1559 1560 /* Enabled memories */ 1561 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 1562 if (em & F_EDRAM0_ENABLE) { 1563 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 1564 maddr = G_EDRAM0_BASE(addr_len) << 20; 1565 mlen = G_EDRAM0_SIZE(addr_len) << 20; 1566 if (mlen > 0 && addr >= maddr && addr < maddr + mlen && 1567 addr + len <= maddr + mlen) 1568 return (0); 1569 } 1570 if (em & F_EDRAM1_ENABLE) { 1571 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 1572 maddr = G_EDRAM1_BASE(addr_len) << 20; 1573 mlen = G_EDRAM1_SIZE(addr_len) << 20; 1574 if (mlen > 0 && addr >= maddr && addr < maddr + mlen && 1575 addr + len <= maddr + mlen) 1576 return (0); 1577 } 1578 if (em & F_EXT_MEM_ENABLE) { 1579 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 1580 maddr = G_EXT_MEM_BASE(addr_len) << 20; 1581 mlen = G_EXT_MEM_SIZE(addr_len) << 20; 1582 if (mlen > 0 && addr >= maddr && addr < maddr + mlen && 1583 addr + len <= maddr + mlen) 1584 return (0); 1585 } 1586 if (!is_t4(sc) && em & F_EXT_MEM1_ENABLE) { 1587 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 1588 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 1589 mlen = G_EXT_MEM1_SIZE(addr_len) << 20; 1590 if (mlen > 0 && addr >= maddr && addr < maddr + mlen && 1591 addr + len <= maddr + mlen) 1592 return (0); 1593 } 1594 1595 return (EFAULT); 1596 } 1597 1598 static int 1599 fwmtype_to_hwmtype(int mtype) 1600 { 1601 1602 switch (mtype) { 1603 case FW_MEMTYPE_EDC0: 1604 return (MEM_EDC0); 1605 case FW_MEMTYPE_EDC1: 1606 return (MEM_EDC1); 1607 case FW_MEMTYPE_EXTMEM: 1608 return (MEM_MC0); 1609 case FW_MEMTYPE_EXTMEM1: 1610 return (MEM_MC1); 1611 default: 1612 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 1613 } 1614 } 1615 1616 /* 1617 * Verify that the memory range specified by the memtype/offset/len pair is 1618 * valid and lies entirely within the memtype specified. The global address of 1619 * the start of the range is returned in addr. 1620 */ 1621 static int 1622 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 1623 uint32_t *addr) 1624 { 1625 uint32_t em, addr_len, maddr, mlen; 1626 1627 /* Memory can only be accessed in naturally aligned 4 byte units */ 1628 if (off & 3 || len & 3 || len == 0) 1629 return (EINVAL); 1630 1631 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 1632 switch (fwmtype_to_hwmtype(mtype)) { 1633 case MEM_EDC0: 1634 if (!(em & F_EDRAM0_ENABLE)) 1635 return (EINVAL); 1636 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 1637 maddr = G_EDRAM0_BASE(addr_len) << 20; 1638 mlen = G_EDRAM0_SIZE(addr_len) << 20; 1639 break; 1640 case MEM_EDC1: 1641 if (!(em & F_EDRAM1_ENABLE)) 1642 return (EINVAL); 1643 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 1644 maddr = G_EDRAM1_BASE(addr_len) << 20; 1645 mlen = G_EDRAM1_SIZE(addr_len) << 20; 1646 break; 1647 case MEM_MC: 1648 if (!(em & F_EXT_MEM_ENABLE)) 1649 return (EINVAL); 1650 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 1651 maddr = G_EXT_MEM_BASE(addr_len) << 20; 1652 mlen = G_EXT_MEM_SIZE(addr_len) << 20; 1653 break; 1654 case MEM_MC1: 1655 if (is_t4(sc) || !(em & F_EXT_MEM1_ENABLE)) 1656 return (EINVAL); 1657 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 1658 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 1659 mlen = G_EXT_MEM1_SIZE(addr_len) << 20; 1660 break; 1661 default: 1662 return (EINVAL); 1663 } 1664 1665 if (mlen > 0 && off < mlen && off + len <= mlen) { 1666 *addr = maddr + off; /* global address */ 1667 return (0); 1668 } 1669 1670 return (EFAULT); 1671 } 1672 1673 static void 1674 memwin_info(struct adapter *sc, int win, uint32_t *base, uint32_t *aperture) 1675 { 1676 const struct memwin *mw; 1677 1678 if (is_t4(sc)) { 1679 KASSERT(win >= 0 && win < nitems(t4_memwin), 1680 ("%s: incorrect memwin# (%d)", __func__, win)); 1681 mw = &t4_memwin[win]; 1682 } else { 1683 KASSERT(win >= 0 && win < nitems(t5_memwin), 1684 ("%s: incorrect memwin# (%d)", __func__, win)); 1685 mw = &t5_memwin[win]; 1686 } 1687 1688 if (base != NULL) 1689 *base = mw->base; 1690 if (aperture != NULL) 1691 *aperture = mw->aperture; 1692 } 1693 1694 /* 1695 * Positions the memory window such that it can be used to access the specified 1696 * address in the chip's address space. The return value is the offset of addr 1697 * from the start of the window. 1698 */ 1699 static uint32_t 1700 position_memwin(struct adapter *sc, int n, uint32_t addr) 1701 { 1702 uint32_t start, pf; 1703 uint32_t reg; 1704 1705 KASSERT(n >= 0 && n <= 3, 1706 ("%s: invalid window %d.", __func__, n)); 1707 KASSERT((addr & 3) == 0, 1708 ("%s: addr (0x%x) is not at a 4B boundary.", __func__, addr)); 1709 1710 if (is_t4(sc)) { 1711 pf = 0; 1712 start = addr & ~0xf; /* start must be 16B aligned */ 1713 } else { 1714 pf = V_PFNUM(sc->pf); 1715 start = addr & ~0x7f; /* start must be 128B aligned */ 1716 } 1717 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, n); 1718 1719 t4_write_reg(sc, reg, start | pf); 1720 t4_read_reg(sc, reg); 1721 1722 return (addr - start); 1723 } 1724 1725 static int 1726 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 1727 struct intrs_and_queues *iaq) 1728 { 1729 int rc, itype, navail, nrxq10g, nrxq1g, n; 1730 int nofldrxq10g = 0, nofldrxq1g = 0; 1731 1732 bzero(iaq, sizeof(*iaq)); 1733 1734 iaq->ntxq10g = t4_ntxq10g; 1735 iaq->ntxq1g = t4_ntxq1g; 1736 iaq->nrxq10g = nrxq10g = t4_nrxq10g; 1737 iaq->nrxq1g = nrxq1g = t4_nrxq1g; 1738 #ifdef TCP_OFFLOAD 1739 if (is_offload(sc)) { 1740 iaq->nofldtxq10g = t4_nofldtxq10g; 1741 iaq->nofldtxq1g = t4_nofldtxq1g; 1742 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g; 1743 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g; 1744 } 1745 #endif 1746 1747 for (itype = INTR_MSIX; itype; itype >>= 1) { 1748 1749 if ((itype & t4_intr_types) == 0) 1750 continue; /* not allowed */ 1751 1752 if (itype == INTR_MSIX) 1753 navail = pci_msix_count(sc->dev); 1754 else if (itype == INTR_MSI) 1755 navail = pci_msi_count(sc->dev); 1756 else 1757 navail = 1; 1758 restart: 1759 if (navail == 0) 1760 continue; 1761 1762 iaq->intr_type = itype; 1763 iaq->intr_flags = 0; 1764 1765 /* 1766 * Best option: an interrupt vector for errors, one for the 1767 * firmware event queue, and one each for each rxq (NIC as well 1768 * as offload). 1769 */ 1770 iaq->nirq = T4_EXTRA_INTR; 1771 iaq->nirq += n10g * (nrxq10g + nofldrxq10g); 1772 iaq->nirq += n1g * (nrxq1g + nofldrxq1g); 1773 if (iaq->nirq <= navail && 1774 (itype != INTR_MSI || powerof2(iaq->nirq))) { 1775 iaq->intr_flags |= INTR_DIRECT; 1776 goto allocate; 1777 } 1778 1779 /* 1780 * Second best option: an interrupt vector for errors, one for 1781 * the firmware event queue, and one each for either NIC or 1782 * offload rxq's. 1783 */ 1784 iaq->nirq = T4_EXTRA_INTR; 1785 iaq->nirq += n10g * max(nrxq10g, nofldrxq10g); 1786 iaq->nirq += n1g * max(nrxq1g, nofldrxq1g); 1787 if (iaq->nirq <= navail && 1788 (itype != INTR_MSI || powerof2(iaq->nirq))) 1789 goto allocate; 1790 1791 /* 1792 * Next best option: an interrupt vector for errors, one for the 1793 * firmware event queue, and at least one per port. At this 1794 * point we know we'll have to downsize nrxq or nofldrxq to fit 1795 * what's available to us. 1796 */ 1797 iaq->nirq = T4_EXTRA_INTR; 1798 iaq->nirq += n10g + n1g; 1799 if (iaq->nirq <= navail) { 1800 int leftover = navail - iaq->nirq; 1801 1802 if (n10g > 0) { 1803 int target = max(nrxq10g, nofldrxq10g); 1804 1805 n = 1; 1806 while (n < target && leftover >= n10g) { 1807 leftover -= n10g; 1808 iaq->nirq += n10g; 1809 n++; 1810 } 1811 iaq->nrxq10g = min(n, nrxq10g); 1812 #ifdef TCP_OFFLOAD 1813 if (is_offload(sc)) 1814 iaq->nofldrxq10g = min(n, nofldrxq10g); 1815 #endif 1816 } 1817 1818 if (n1g > 0) { 1819 int target = max(nrxq1g, nofldrxq1g); 1820 1821 n = 1; 1822 while (n < target && leftover >= n1g) { 1823 leftover -= n1g; 1824 iaq->nirq += n1g; 1825 n++; 1826 } 1827 iaq->nrxq1g = min(n, nrxq1g); 1828 #ifdef TCP_OFFLOAD 1829 if (is_offload(sc)) 1830 iaq->nofldrxq1g = min(n, nofldrxq1g); 1831 #endif 1832 } 1833 1834 if (itype != INTR_MSI || powerof2(iaq->nirq)) 1835 goto allocate; 1836 } 1837 1838 /* 1839 * Least desirable option: one interrupt vector for everything. 1840 */ 1841 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1; 1842 #ifdef TCP_OFFLOAD 1843 if (is_offload(sc)) 1844 iaq->nofldrxq10g = iaq->nofldrxq1g = 1; 1845 #endif 1846 1847 allocate: 1848 navail = iaq->nirq; 1849 rc = 0; 1850 if (itype == INTR_MSIX) 1851 rc = pci_alloc_msix(sc->dev, &navail); 1852 else if (itype == INTR_MSI) 1853 rc = pci_alloc_msi(sc->dev, &navail); 1854 1855 if (rc == 0) { 1856 if (navail == iaq->nirq) 1857 return (0); 1858 1859 /* 1860 * Didn't get the number requested. Use whatever number 1861 * the kernel is willing to allocate (it's in navail). 1862 */ 1863 device_printf(sc->dev, "fewer vectors than requested, " 1864 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 1865 itype, iaq->nirq, navail); 1866 pci_release_msi(sc->dev); 1867 goto restart; 1868 } 1869 1870 device_printf(sc->dev, 1871 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 1872 itype, rc, iaq->nirq, navail); 1873 } 1874 1875 device_printf(sc->dev, 1876 "failed to find a usable interrupt type. " 1877 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 1878 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 1879 1880 return (ENXIO); 1881 } 1882 1883 #define FW_VERSION(chip) ( \ 1884 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 1885 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 1886 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 1887 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 1888 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 1889 1890 struct fw_info { 1891 uint8_t chip; 1892 char *kld_name; 1893 char *fw_mod_name; 1894 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 1895 } fw_info[] = { 1896 { 1897 .chip = CHELSIO_T4, 1898 .kld_name = "t4fw_cfg", 1899 .fw_mod_name = "t4fw", 1900 .fw_hdr = { 1901 .chip = FW_HDR_CHIP_T4, 1902 .fw_ver = htobe32_const(FW_VERSION(T4)), 1903 .intfver_nic = FW_INTFVER(T4, NIC), 1904 .intfver_vnic = FW_INTFVER(T4, VNIC), 1905 .intfver_ofld = FW_INTFVER(T4, OFLD), 1906 .intfver_ri = FW_INTFVER(T4, RI), 1907 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 1908 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 1909 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 1910 .intfver_fcoe = FW_INTFVER(T4, FCOE), 1911 }, 1912 }, { 1913 .chip = CHELSIO_T5, 1914 .kld_name = "t5fw_cfg", 1915 .fw_mod_name = "t5fw", 1916 .fw_hdr = { 1917 .chip = FW_HDR_CHIP_T5, 1918 .fw_ver = htobe32_const(FW_VERSION(T5)), 1919 .intfver_nic = FW_INTFVER(T5, NIC), 1920 .intfver_vnic = FW_INTFVER(T5, VNIC), 1921 .intfver_ofld = FW_INTFVER(T5, OFLD), 1922 .intfver_ri = FW_INTFVER(T5, RI), 1923 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 1924 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 1925 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 1926 .intfver_fcoe = FW_INTFVER(T5, FCOE), 1927 }, 1928 } 1929 }; 1930 1931 static struct fw_info * 1932 find_fw_info(int chip) 1933 { 1934 int i; 1935 1936 for (i = 0; i < nitems(fw_info); i++) { 1937 if (fw_info[i].chip == chip) 1938 return (&fw_info[i]); 1939 } 1940 return (NULL); 1941 } 1942 1943 /* 1944 * Is the given firmware API compatible with the one the driver was compiled 1945 * with? 1946 */ 1947 static int 1948 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 1949 { 1950 1951 /* short circuit if it's the exact same firmware version */ 1952 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 1953 return (1); 1954 1955 /* 1956 * XXX: Is this too conservative? Perhaps I should limit this to the 1957 * features that are supported in the driver. 1958 */ 1959 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 1960 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 1961 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 1962 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 1963 return (1); 1964 #undef SAME_INTF 1965 1966 return (0); 1967 } 1968 1969 /* 1970 * The firmware in the KLD is usable, but should it be installed? This routine 1971 * explains itself in detail if it indicates the KLD firmware should be 1972 * installed. 1973 */ 1974 static int 1975 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 1976 { 1977 const char *reason; 1978 1979 if (!card_fw_usable) { 1980 reason = "incompatible or unusable"; 1981 goto install; 1982 } 1983 1984 if (k > c) { 1985 reason = "older than the version bundled with this driver"; 1986 goto install; 1987 } 1988 1989 if (t4_fw_install == 2 && k != c) { 1990 reason = "different than the version bundled with this driver"; 1991 goto install; 1992 } 1993 1994 return (0); 1995 1996 install: 1997 if (t4_fw_install == 0) { 1998 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 1999 "but the driver is prohibited from installing a different " 2000 "firmware on the card.\n", 2001 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2002 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 2003 2004 return (0); 2005 } 2006 2007 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2008 "installing firmware %u.%u.%u.%u on card.\n", 2009 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2010 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 2011 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 2012 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 2013 2014 return (1); 2015 } 2016 /* 2017 * Establish contact with the firmware and determine if we are the master driver 2018 * or not, and whether we are responsible for chip initialization. 2019 */ 2020 static int 2021 prep_firmware(struct adapter *sc) 2022 { 2023 const struct firmware *fw = NULL, *default_cfg; 2024 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 2025 enum dev_state state; 2026 struct fw_info *fw_info; 2027 struct fw_hdr *card_fw; /* fw on the card */ 2028 const struct fw_hdr *kld_fw; /* fw in the KLD */ 2029 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 2030 against */ 2031 2032 /* Contact firmware. */ 2033 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 2034 if (rc < 0 || state == DEV_STATE_ERR) { 2035 rc = -rc; 2036 device_printf(sc->dev, 2037 "failed to connect to the firmware: %d, %d.\n", rc, state); 2038 return (rc); 2039 } 2040 pf = rc; 2041 if (pf == sc->mbox) 2042 sc->flags |= MASTER_PF; 2043 else if (state == DEV_STATE_UNINIT) { 2044 /* 2045 * We didn't get to be the master so we definitely won't be 2046 * configuring the chip. It's a bug if someone else hasn't 2047 * configured it already. 2048 */ 2049 device_printf(sc->dev, "couldn't be master(%d), " 2050 "device not already initialized either(%d).\n", rc, state); 2051 return (EDOOFUS); 2052 } 2053 2054 /* This is the firmware whose headers the driver was compiled against */ 2055 fw_info = find_fw_info(chip_id(sc)); 2056 if (fw_info == NULL) { 2057 device_printf(sc->dev, 2058 "unable to look up firmware information for chip %d.\n", 2059 chip_id(sc)); 2060 return (EINVAL); 2061 } 2062 drv_fw = &fw_info->fw_hdr; 2063 2064 /* 2065 * The firmware KLD contains many modules. The KLD name is also the 2066 * name of the module that contains the default config file. 2067 */ 2068 default_cfg = firmware_get(fw_info->kld_name); 2069 2070 /* Read the header of the firmware on the card */ 2071 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 2072 rc = -t4_read_flash(sc, FLASH_FW_START, 2073 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 2074 if (rc == 0) 2075 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 2076 else { 2077 device_printf(sc->dev, 2078 "Unable to read card's firmware header: %d\n", rc); 2079 card_fw_usable = 0; 2080 } 2081 2082 /* This is the firmware in the KLD */ 2083 fw = firmware_get(fw_info->fw_mod_name); 2084 if (fw != NULL) { 2085 kld_fw = (const void *)fw->data; 2086 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 2087 } else { 2088 kld_fw = NULL; 2089 kld_fw_usable = 0; 2090 } 2091 2092 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 2093 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 2094 /* 2095 * Common case: the firmware on the card is an exact match and 2096 * the KLD is an exact match too, or the KLD is 2097 * absent/incompatible. Note that t4_fw_install = 2 is ignored 2098 * here -- use cxgbetool loadfw if you want to reinstall the 2099 * same firmware as the one on the card. 2100 */ 2101 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 2102 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 2103 be32toh(card_fw->fw_ver))) { 2104 2105 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 2106 if (rc != 0) { 2107 device_printf(sc->dev, 2108 "failed to install firmware: %d\n", rc); 2109 goto done; 2110 } 2111 2112 /* Installed successfully, update the cached header too. */ 2113 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 2114 card_fw_usable = 1; 2115 need_fw_reset = 0; /* already reset as part of load_fw */ 2116 } 2117 2118 if (!card_fw_usable) { 2119 uint32_t d, c, k; 2120 2121 d = ntohl(drv_fw->fw_ver); 2122 c = ntohl(card_fw->fw_ver); 2123 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 2124 2125 device_printf(sc->dev, "Cannot find a usable firmware: " 2126 "fw_install %d, chip state %d, " 2127 "driver compiled with %d.%d.%d.%d, " 2128 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 2129 t4_fw_install, state, 2130 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 2131 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 2132 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2133 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 2134 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 2135 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 2136 rc = EINVAL; 2137 goto done; 2138 } 2139 2140 /* We're using whatever's on the card and it's known to be good. */ 2141 sc->params.fw_vers = ntohl(card_fw->fw_ver); 2142 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 2143 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 2144 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 2145 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 2146 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 2147 t4_get_tp_version(sc, &sc->params.tp_vers); 2148 2149 /* Reset device */ 2150 if (need_fw_reset && 2151 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 2152 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 2153 if (rc != ETIMEDOUT && rc != EIO) 2154 t4_fw_bye(sc, sc->mbox); 2155 goto done; 2156 } 2157 sc->flags |= FW_OK; 2158 2159 rc = get_params__pre_init(sc); 2160 if (rc != 0) 2161 goto done; /* error message displayed already */ 2162 2163 /* Partition adapter resources as specified in the config file. */ 2164 if (state == DEV_STATE_UNINIT) { 2165 2166 KASSERT(sc->flags & MASTER_PF, 2167 ("%s: trying to change chip settings when not master.", 2168 __func__)); 2169 2170 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 2171 if (rc != 0) 2172 goto done; /* error message displayed already */ 2173 2174 t4_tweak_chip_settings(sc); 2175 2176 /* get basic stuff going */ 2177 rc = -t4_fw_initialize(sc, sc->mbox); 2178 if (rc != 0) { 2179 device_printf(sc->dev, "fw init failed: %d.\n", rc); 2180 goto done; 2181 } 2182 } else { 2183 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 2184 sc->cfcsum = 0; 2185 } 2186 2187 done: 2188 free(card_fw, M_CXGBE); 2189 if (fw != NULL) 2190 firmware_put(fw, FIRMWARE_UNLOAD); 2191 if (default_cfg != NULL) 2192 firmware_put(default_cfg, FIRMWARE_UNLOAD); 2193 2194 return (rc); 2195 } 2196 2197 #define FW_PARAM_DEV(param) \ 2198 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 2199 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 2200 #define FW_PARAM_PFVF(param) \ 2201 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 2202 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 2203 2204 /* 2205 * Partition chip resources for use between various PFs, VFs, etc. 2206 */ 2207 static int 2208 partition_resources(struct adapter *sc, const struct firmware *default_cfg, 2209 const char *name_prefix) 2210 { 2211 const struct firmware *cfg = NULL; 2212 int rc = 0; 2213 struct fw_caps_config_cmd caps; 2214 uint32_t mtype, moff, finicsum, cfcsum; 2215 2216 /* 2217 * Figure out what configuration file to use. Pick the default config 2218 * file for the card if the user hasn't specified one explicitly. 2219 */ 2220 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 2221 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 2222 /* Card specific overrides go here. */ 2223 if (pci_get_device(sc->dev) == 0x440a) 2224 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 2225 if (is_fpga(sc)) 2226 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 2227 } 2228 2229 /* 2230 * We need to load another module if the profile is anything except 2231 * "default" or "flash". 2232 */ 2233 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 2234 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 2235 char s[32]; 2236 2237 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 2238 cfg = firmware_get(s); 2239 if (cfg == NULL) { 2240 if (default_cfg != NULL) { 2241 device_printf(sc->dev, 2242 "unable to load module \"%s\" for " 2243 "configuration profile \"%s\", will use " 2244 "the default config file instead.\n", 2245 s, sc->cfg_file); 2246 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 2247 "%s", DEFAULT_CF); 2248 } else { 2249 device_printf(sc->dev, 2250 "unable to load module \"%s\" for " 2251 "configuration profile \"%s\", will use " 2252 "the config file on the card's flash " 2253 "instead.\n", s, sc->cfg_file); 2254 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 2255 "%s", FLASH_CF); 2256 } 2257 } 2258 } 2259 2260 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 2261 default_cfg == NULL) { 2262 device_printf(sc->dev, 2263 "default config file not available, will use the config " 2264 "file on the card's flash instead.\n"); 2265 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 2266 } 2267 2268 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 2269 u_int cflen, i, n; 2270 const uint32_t *cfdata; 2271 uint32_t param, val, addr, off, mw_base, mw_aperture; 2272 2273 KASSERT(cfg != NULL || default_cfg != NULL, 2274 ("%s: no config to upload", __func__)); 2275 2276 /* 2277 * Ask the firmware where it wants us to upload the config file. 2278 */ 2279 param = FW_PARAM_DEV(CF); 2280 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2281 if (rc != 0) { 2282 /* No support for config file? Shouldn't happen. */ 2283 device_printf(sc->dev, 2284 "failed to query config file location: %d.\n", rc); 2285 goto done; 2286 } 2287 mtype = G_FW_PARAMS_PARAM_Y(val); 2288 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 2289 2290 /* 2291 * XXX: sheer laziness. We deliberately added 4 bytes of 2292 * useless stuffing/comments at the end of the config file so 2293 * it's ok to simply throw away the last remaining bytes when 2294 * the config file is not an exact multiple of 4. This also 2295 * helps with the validate_mt_off_len check. 2296 */ 2297 if (cfg != NULL) { 2298 cflen = cfg->datasize & ~3; 2299 cfdata = cfg->data; 2300 } else { 2301 cflen = default_cfg->datasize & ~3; 2302 cfdata = default_cfg->data; 2303 } 2304 2305 if (cflen > FLASH_CFG_MAX_SIZE) { 2306 device_printf(sc->dev, 2307 "config file too long (%d, max allowed is %d). " 2308 "Will try to use the config on the card, if any.\n", 2309 cflen, FLASH_CFG_MAX_SIZE); 2310 goto use_config_on_flash; 2311 } 2312 2313 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 2314 if (rc != 0) { 2315 device_printf(sc->dev, 2316 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 2317 "Will try to use the config on the card, if any.\n", 2318 __func__, mtype, moff, cflen, rc); 2319 goto use_config_on_flash; 2320 } 2321 2322 memwin_info(sc, 2, &mw_base, &mw_aperture); 2323 while (cflen) { 2324 off = position_memwin(sc, 2, addr); 2325 n = min(cflen, mw_aperture - off); 2326 for (i = 0; i < n; i += 4) 2327 t4_write_reg(sc, mw_base + off + i, *cfdata++); 2328 cflen -= n; 2329 addr += n; 2330 } 2331 } else { 2332 use_config_on_flash: 2333 mtype = FW_MEMTYPE_FLASH; 2334 moff = t4_flash_cfg_addr(sc); 2335 } 2336 2337 bzero(&caps, sizeof(caps)); 2338 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 2339 F_FW_CMD_REQUEST | F_FW_CMD_READ); 2340 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 2341 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 2342 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 2343 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 2344 if (rc != 0) { 2345 device_printf(sc->dev, 2346 "failed to pre-process config file: %d " 2347 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 2348 goto done; 2349 } 2350 2351 finicsum = be32toh(caps.finicsum); 2352 cfcsum = be32toh(caps.cfcsum); 2353 if (finicsum != cfcsum) { 2354 device_printf(sc->dev, 2355 "WARNING: config file checksum mismatch: %08x %08x\n", 2356 finicsum, cfcsum); 2357 } 2358 sc->cfcsum = cfcsum; 2359 2360 #define LIMIT_CAPS(x) do { \ 2361 caps.x &= htobe16(t4_##x##_allowed); \ 2362 } while (0) 2363 2364 /* 2365 * Let the firmware know what features will (not) be used so it can tune 2366 * things accordingly. 2367 */ 2368 LIMIT_CAPS(linkcaps); 2369 LIMIT_CAPS(niccaps); 2370 LIMIT_CAPS(toecaps); 2371 LIMIT_CAPS(rdmacaps); 2372 LIMIT_CAPS(iscsicaps); 2373 LIMIT_CAPS(fcoecaps); 2374 #undef LIMIT_CAPS 2375 2376 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 2377 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 2378 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 2379 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 2380 if (rc != 0) { 2381 device_printf(sc->dev, 2382 "failed to process config file: %d.\n", rc); 2383 } 2384 done: 2385 if (cfg != NULL) 2386 firmware_put(cfg, FIRMWARE_UNLOAD); 2387 return (rc); 2388 } 2389 2390 /* 2391 * Retrieve parameters that are needed (or nice to have) very early. 2392 */ 2393 static int 2394 get_params__pre_init(struct adapter *sc) 2395 { 2396 int rc; 2397 uint32_t param[2], val[2]; 2398 struct fw_devlog_cmd cmd; 2399 struct devlog_params *dlog = &sc->params.devlog; 2400 2401 param[0] = FW_PARAM_DEV(PORTVEC); 2402 param[1] = FW_PARAM_DEV(CCLK); 2403 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 2404 if (rc != 0) { 2405 device_printf(sc->dev, 2406 "failed to query parameters (pre_init): %d.\n", rc); 2407 return (rc); 2408 } 2409 2410 sc->params.portvec = val[0]; 2411 sc->params.nports = bitcount32(val[0]); 2412 sc->params.vpd.cclk = val[1]; 2413 2414 /* Read device log parameters. */ 2415 bzero(&cmd, sizeof(cmd)); 2416 cmd.op_to_write = htobe32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 2417 F_FW_CMD_REQUEST | F_FW_CMD_READ); 2418 cmd.retval_len16 = htobe32(FW_LEN16(cmd)); 2419 rc = -t4_wr_mbox(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 2420 if (rc != 0) { 2421 device_printf(sc->dev, 2422 "failed to get devlog parameters: %d.\n", rc); 2423 bzero(dlog, sizeof (*dlog)); 2424 rc = 0; /* devlog isn't critical for device operation */ 2425 } else { 2426 val[0] = be32toh(cmd.memtype_devlog_memaddr16_devlog); 2427 dlog->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(val[0]); 2428 dlog->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(val[0]) << 4; 2429 dlog->size = be32toh(cmd.memsize_devlog); 2430 } 2431 2432 return (rc); 2433 } 2434 2435 /* 2436 * Retrieve various parameters that are of interest to the driver. The device 2437 * has been initialized by the firmware at this point. 2438 */ 2439 static int 2440 get_params__post_init(struct adapter *sc) 2441 { 2442 int rc; 2443 uint32_t param[7], val[7]; 2444 struct fw_caps_config_cmd caps; 2445 2446 param[0] = FW_PARAM_PFVF(IQFLINT_START); 2447 param[1] = FW_PARAM_PFVF(EQ_START); 2448 param[2] = FW_PARAM_PFVF(FILTER_START); 2449 param[3] = FW_PARAM_PFVF(FILTER_END); 2450 param[4] = FW_PARAM_PFVF(L2T_START); 2451 param[5] = FW_PARAM_PFVF(L2T_END); 2452 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 2453 if (rc != 0) { 2454 device_printf(sc->dev, 2455 "failed to query parameters (post_init): %d.\n", rc); 2456 return (rc); 2457 } 2458 2459 sc->sge.iq_start = val[0]; 2460 sc->sge.eq_start = val[1]; 2461 sc->tids.ftid_base = val[2]; 2462 sc->tids.nftids = val[3] - val[2] + 1; 2463 sc->params.ftid_min = val[2]; 2464 sc->params.ftid_max = val[3]; 2465 sc->vres.l2t.start = val[4]; 2466 sc->vres.l2t.size = val[5] - val[4] + 1; 2467 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 2468 ("%s: L2 table size (%u) larger than expected (%u)", 2469 __func__, sc->vres.l2t.size, L2T_SIZE)); 2470 2471 /* get capabilites */ 2472 bzero(&caps, sizeof(caps)); 2473 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 2474 F_FW_CMD_REQUEST | F_FW_CMD_READ); 2475 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 2476 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 2477 if (rc != 0) { 2478 device_printf(sc->dev, 2479 "failed to get card capabilities: %d.\n", rc); 2480 return (rc); 2481 } 2482 2483 #define READ_CAPS(x) do { \ 2484 sc->x = htobe16(caps.x); \ 2485 } while (0) 2486 READ_CAPS(linkcaps); 2487 READ_CAPS(niccaps); 2488 READ_CAPS(toecaps); 2489 READ_CAPS(rdmacaps); 2490 READ_CAPS(iscsicaps); 2491 READ_CAPS(fcoecaps); 2492 2493 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 2494 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 2495 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 2496 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 2497 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 2498 if (rc != 0) { 2499 device_printf(sc->dev, 2500 "failed to query NIC parameters: %d.\n", rc); 2501 return (rc); 2502 } 2503 sc->tids.etid_base = val[0]; 2504 sc->params.etid_min = val[0]; 2505 sc->tids.netids = val[1] - val[0] + 1; 2506 sc->params.netids = sc->tids.netids; 2507 sc->params.eo_wr_cred = val[2]; 2508 sc->params.ethoffload = 1; 2509 } 2510 2511 if (sc->toecaps) { 2512 /* query offload-related parameters */ 2513 param[0] = FW_PARAM_DEV(NTID); 2514 param[1] = FW_PARAM_PFVF(SERVER_START); 2515 param[2] = FW_PARAM_PFVF(SERVER_END); 2516 param[3] = FW_PARAM_PFVF(TDDP_START); 2517 param[4] = FW_PARAM_PFVF(TDDP_END); 2518 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 2519 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 2520 if (rc != 0) { 2521 device_printf(sc->dev, 2522 "failed to query TOE parameters: %d.\n", rc); 2523 return (rc); 2524 } 2525 sc->tids.ntids = val[0]; 2526 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 2527 sc->tids.stid_base = val[1]; 2528 sc->tids.nstids = val[2] - val[1] + 1; 2529 sc->vres.ddp.start = val[3]; 2530 sc->vres.ddp.size = val[4] - val[3] + 1; 2531 sc->params.ofldq_wr_cred = val[5]; 2532 sc->params.offload = 1; 2533 } 2534 if (sc->rdmacaps) { 2535 param[0] = FW_PARAM_PFVF(STAG_START); 2536 param[1] = FW_PARAM_PFVF(STAG_END); 2537 param[2] = FW_PARAM_PFVF(RQ_START); 2538 param[3] = FW_PARAM_PFVF(RQ_END); 2539 param[4] = FW_PARAM_PFVF(PBL_START); 2540 param[5] = FW_PARAM_PFVF(PBL_END); 2541 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 2542 if (rc != 0) { 2543 device_printf(sc->dev, 2544 "failed to query RDMA parameters(1): %d.\n", rc); 2545 return (rc); 2546 } 2547 sc->vres.stag.start = val[0]; 2548 sc->vres.stag.size = val[1] - val[0] + 1; 2549 sc->vres.rq.start = val[2]; 2550 sc->vres.rq.size = val[3] - val[2] + 1; 2551 sc->vres.pbl.start = val[4]; 2552 sc->vres.pbl.size = val[5] - val[4] + 1; 2553 2554 param[0] = FW_PARAM_PFVF(SQRQ_START); 2555 param[1] = FW_PARAM_PFVF(SQRQ_END); 2556 param[2] = FW_PARAM_PFVF(CQ_START); 2557 param[3] = FW_PARAM_PFVF(CQ_END); 2558 param[4] = FW_PARAM_PFVF(OCQ_START); 2559 param[5] = FW_PARAM_PFVF(OCQ_END); 2560 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 2561 if (rc != 0) { 2562 device_printf(sc->dev, 2563 "failed to query RDMA parameters(2): %d.\n", rc); 2564 return (rc); 2565 } 2566 sc->vres.qp.start = val[0]; 2567 sc->vres.qp.size = val[1] - val[0] + 1; 2568 sc->vres.cq.start = val[2]; 2569 sc->vres.cq.size = val[3] - val[2] + 1; 2570 sc->vres.ocq.start = val[4]; 2571 sc->vres.ocq.size = val[5] - val[4] + 1; 2572 } 2573 if (sc->iscsicaps) { 2574 param[0] = FW_PARAM_PFVF(ISCSI_START); 2575 param[1] = FW_PARAM_PFVF(ISCSI_END); 2576 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 2577 if (rc != 0) { 2578 device_printf(sc->dev, 2579 "failed to query iSCSI parameters: %d.\n", rc); 2580 return (rc); 2581 } 2582 sc->vres.iscsi.start = val[0]; 2583 sc->vres.iscsi.size = val[1] - val[0] + 1; 2584 } 2585 2586 /* 2587 * We've got the params we wanted to query via the firmware. Now grab 2588 * some others directly from the chip. 2589 */ 2590 rc = t4_read_chip_settings(sc); 2591 2592 return (rc); 2593 } 2594 2595 static int 2596 set_params__post_init(struct adapter *sc) 2597 { 2598 uint32_t param, val; 2599 2600 /* ask for encapsulated CPLs */ 2601 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 2602 val = 1; 2603 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2604 2605 return (0); 2606 } 2607 2608 #undef FW_PARAM_PFVF 2609 #undef FW_PARAM_DEV 2610 2611 static void 2612 t4_set_desc(struct adapter *sc) 2613 { 2614 char buf[128]; 2615 struct adapter_params *p = &sc->params; 2616 2617 snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, " 2618 "P/N:%s, E/C:%s", p->vpd.id, is_offload(sc) ? "R" : "", 2619 chip_rev(sc), p->vpd.sn, p->vpd.pn, p->vpd.ec); 2620 2621 device_set_desc_copy(sc->dev, buf); 2622 } 2623 2624 static void 2625 build_medialist(struct port_info *pi) 2626 { 2627 struct ifmedia *media = &pi->media; 2628 int data, m; 2629 2630 PORT_LOCK(pi); 2631 2632 ifmedia_removeall(media); 2633 2634 m = IFM_ETHER | IFM_FDX; 2635 data = (pi->port_type << 8) | pi->mod_type; 2636 2637 switch(pi->port_type) { 2638 case FW_PORT_TYPE_BT_XFI: 2639 ifmedia_add(media, m | IFM_10G_T, data, NULL); 2640 break; 2641 2642 case FW_PORT_TYPE_BT_XAUI: 2643 ifmedia_add(media, m | IFM_10G_T, data, NULL); 2644 /* fall through */ 2645 2646 case FW_PORT_TYPE_BT_SGMII: 2647 ifmedia_add(media, m | IFM_1000_T, data, NULL); 2648 ifmedia_add(media, m | IFM_100_TX, data, NULL); 2649 ifmedia_add(media, IFM_ETHER | IFM_AUTO, data, NULL); 2650 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 2651 break; 2652 2653 case FW_PORT_TYPE_CX4: 2654 ifmedia_add(media, m | IFM_10G_CX4, data, NULL); 2655 ifmedia_set(media, m | IFM_10G_CX4); 2656 break; 2657 2658 case FW_PORT_TYPE_SFP: 2659 case FW_PORT_TYPE_FIBER_XFI: 2660 case FW_PORT_TYPE_FIBER_XAUI: 2661 switch (pi->mod_type) { 2662 2663 case FW_PORT_MOD_TYPE_LR: 2664 ifmedia_add(media, m | IFM_10G_LR, data, NULL); 2665 ifmedia_set(media, m | IFM_10G_LR); 2666 break; 2667 2668 case FW_PORT_MOD_TYPE_SR: 2669 ifmedia_add(media, m | IFM_10G_SR, data, NULL); 2670 ifmedia_set(media, m | IFM_10G_SR); 2671 break; 2672 2673 case FW_PORT_MOD_TYPE_LRM: 2674 ifmedia_add(media, m | IFM_10G_LRM, data, NULL); 2675 ifmedia_set(media, m | IFM_10G_LRM); 2676 break; 2677 2678 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2679 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2680 ifmedia_add(media, m | IFM_10G_TWINAX, data, NULL); 2681 ifmedia_set(media, m | IFM_10G_TWINAX); 2682 break; 2683 2684 case FW_PORT_MOD_TYPE_NONE: 2685 m &= ~IFM_FDX; 2686 ifmedia_add(media, m | IFM_NONE, data, NULL); 2687 ifmedia_set(media, m | IFM_NONE); 2688 break; 2689 2690 case FW_PORT_MOD_TYPE_NA: 2691 case FW_PORT_MOD_TYPE_ER: 2692 default: 2693 device_printf(pi->dev, 2694 "unknown port_type (%d), mod_type (%d)\n", 2695 pi->port_type, pi->mod_type); 2696 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL); 2697 ifmedia_set(media, m | IFM_UNKNOWN); 2698 break; 2699 } 2700 break; 2701 2702 case FW_PORT_TYPE_QSFP: 2703 switch (pi->mod_type) { 2704 2705 case FW_PORT_MOD_TYPE_LR: 2706 ifmedia_add(media, m | IFM_40G_LR4, data, NULL); 2707 ifmedia_set(media, m | IFM_40G_LR4); 2708 break; 2709 2710 case FW_PORT_MOD_TYPE_SR: 2711 ifmedia_add(media, m | IFM_40G_SR4, data, NULL); 2712 ifmedia_set(media, m | IFM_40G_SR4); 2713 break; 2714 2715 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2716 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2717 ifmedia_add(media, m | IFM_40G_CR4, data, NULL); 2718 ifmedia_set(media, m | IFM_40G_CR4); 2719 break; 2720 2721 case FW_PORT_MOD_TYPE_NONE: 2722 m &= ~IFM_FDX; 2723 ifmedia_add(media, m | IFM_NONE, data, NULL); 2724 ifmedia_set(media, m | IFM_NONE); 2725 break; 2726 2727 default: 2728 device_printf(pi->dev, 2729 "unknown port_type (%d), mod_type (%d)\n", 2730 pi->port_type, pi->mod_type); 2731 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL); 2732 ifmedia_set(media, m | IFM_UNKNOWN); 2733 break; 2734 } 2735 break; 2736 2737 default: 2738 device_printf(pi->dev, 2739 "unknown port_type (%d), mod_type (%d)\n", pi->port_type, 2740 pi->mod_type); 2741 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL); 2742 ifmedia_set(media, m | IFM_UNKNOWN); 2743 break; 2744 } 2745 2746 PORT_UNLOCK(pi); 2747 } 2748 2749 #define FW_MAC_EXACT_CHUNK 7 2750 2751 /* 2752 * Program the port's XGMAC based on parameters in ifnet. The caller also 2753 * indicates which parameters should be programmed (the rest are left alone). 2754 */ 2755 static int 2756 update_mac_settings(struct port_info *pi, int flags) 2757 { 2758 int rc; 2759 struct ifnet *ifp = pi->ifp; 2760 struct adapter *sc = pi->adapter; 2761 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 2762 2763 ASSERT_SYNCHRONIZED_OP(sc); 2764 KASSERT(flags, ("%s: not told what to update.", __func__)); 2765 2766 if (flags & XGMAC_MTU) 2767 mtu = ifp->if_mtu; 2768 2769 if (flags & XGMAC_PROMISC) 2770 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 2771 2772 if (flags & XGMAC_ALLMULTI) 2773 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 2774 2775 if (flags & XGMAC_VLANEX) 2776 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 2777 2778 rc = -t4_set_rxmode(sc, sc->mbox, pi->viid, mtu, promisc, allmulti, 1, 2779 vlanex, false); 2780 if (rc) { 2781 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, rc); 2782 return (rc); 2783 } 2784 2785 if (flags & XGMAC_UCADDR) { 2786 uint8_t ucaddr[ETHER_ADDR_LEN]; 2787 2788 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 2789 rc = t4_change_mac(sc, sc->mbox, pi->viid, pi->xact_addr_filt, 2790 ucaddr, true, true); 2791 if (rc < 0) { 2792 rc = -rc; 2793 if_printf(ifp, "change_mac failed: %d\n", rc); 2794 return (rc); 2795 } else { 2796 pi->xact_addr_filt = rc; 2797 rc = 0; 2798 } 2799 } 2800 2801 if (flags & XGMAC_MCADDRS) { 2802 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 2803 int del = 1; 2804 uint64_t hash = 0; 2805 struct ifmultiaddr *ifma; 2806 int i = 0, j; 2807 2808 if_maddr_rlock(ifp); 2809 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2810 if (ifma->ifma_addr->sa_family != AF_LINK) 2811 continue; 2812 mcaddr[i++] = 2813 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 2814 2815 if (i == FW_MAC_EXACT_CHUNK) { 2816 rc = t4_alloc_mac_filt(sc, sc->mbox, pi->viid, 2817 del, i, mcaddr, NULL, &hash, 0); 2818 if (rc < 0) { 2819 rc = -rc; 2820 for (j = 0; j < i; j++) { 2821 if_printf(ifp, 2822 "failed to add mc address" 2823 " %02x:%02x:%02x:" 2824 "%02x:%02x:%02x rc=%d\n", 2825 mcaddr[j][0], mcaddr[j][1], 2826 mcaddr[j][2], mcaddr[j][3], 2827 mcaddr[j][4], mcaddr[j][5], 2828 rc); 2829 } 2830 goto mcfail; 2831 } 2832 del = 0; 2833 i = 0; 2834 } 2835 } 2836 if (i > 0) { 2837 rc = t4_alloc_mac_filt(sc, sc->mbox, pi->viid, 2838 del, i, mcaddr, NULL, &hash, 0); 2839 if (rc < 0) { 2840 rc = -rc; 2841 for (j = 0; j < i; j++) { 2842 if_printf(ifp, 2843 "failed to add mc address" 2844 " %02x:%02x:%02x:" 2845 "%02x:%02x:%02x rc=%d\n", 2846 mcaddr[j][0], mcaddr[j][1], 2847 mcaddr[j][2], mcaddr[j][3], 2848 mcaddr[j][4], mcaddr[j][5], 2849 rc); 2850 } 2851 goto mcfail; 2852 } 2853 } 2854 2855 rc = -t4_set_addr_hash(sc, sc->mbox, pi->viid, 0, hash, 0); 2856 if (rc != 0) 2857 if_printf(ifp, "failed to set mc address hash: %d", rc); 2858 mcfail: 2859 if_maddr_runlock(ifp); 2860 } 2861 2862 return (rc); 2863 } 2864 2865 int 2866 begin_synchronized_op(struct adapter *sc, struct port_info *pi, int flags, 2867 char *wmesg) 2868 { 2869 int rc, pri; 2870 2871 #ifdef WITNESS 2872 /* the caller thinks it's ok to sleep, but is it really? */ 2873 if (flags & SLEEP_OK) 2874 pause("t4slptst", 1); 2875 #endif 2876 2877 if (INTR_OK) 2878 pri = PCATCH; 2879 else 2880 pri = 0; 2881 2882 ADAPTER_LOCK(sc); 2883 for (;;) { 2884 2885 if (pi && IS_DOOMED(pi)) { 2886 rc = ENXIO; 2887 goto done; 2888 } 2889 2890 if (!IS_BUSY(sc)) { 2891 rc = 0; 2892 break; 2893 } 2894 2895 if (!(flags & SLEEP_OK)) { 2896 rc = EBUSY; 2897 goto done; 2898 } 2899 2900 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 2901 rc = EINTR; 2902 goto done; 2903 } 2904 } 2905 2906 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 2907 SET_BUSY(sc); 2908 #ifdef INVARIANTS 2909 sc->last_op = wmesg; 2910 sc->last_op_thr = curthread; 2911 #endif 2912 2913 done: 2914 if (!(flags & HOLD_LOCK) || rc) 2915 ADAPTER_UNLOCK(sc); 2916 2917 return (rc); 2918 } 2919 2920 void 2921 end_synchronized_op(struct adapter *sc, int flags) 2922 { 2923 2924 if (flags & LOCK_HELD) 2925 ADAPTER_LOCK_ASSERT_OWNED(sc); 2926 else 2927 ADAPTER_LOCK(sc); 2928 2929 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 2930 CLR_BUSY(sc); 2931 wakeup(&sc->flags); 2932 ADAPTER_UNLOCK(sc); 2933 } 2934 2935 static int 2936 cxgbe_init_synchronized(struct port_info *pi) 2937 { 2938 struct adapter *sc = pi->adapter; 2939 struct ifnet *ifp = pi->ifp; 2940 int rc = 0; 2941 2942 ASSERT_SYNCHRONIZED_OP(sc); 2943 2944 if (isset(&sc->open_device_map, pi->port_id)) { 2945 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, 2946 ("mismatch between open_device_map and if_drv_flags")); 2947 return (0); /* already running */ 2948 } 2949 2950 if (!(sc->flags & FULL_INIT_DONE) && 2951 ((rc = adapter_full_init(sc)) != 0)) 2952 return (rc); /* error message displayed already */ 2953 2954 if (!(pi->flags & PORT_INIT_DONE) && 2955 ((rc = port_full_init(pi)) != 0)) 2956 return (rc); /* error message displayed already */ 2957 2958 rc = update_mac_settings(pi, XGMAC_ALL); 2959 if (rc) 2960 goto done; /* error message displayed already */ 2961 2962 rc = -t4_link_start(sc, sc->mbox, pi->tx_chan, &pi->link_cfg); 2963 if (rc != 0) { 2964 if_printf(ifp, "start_link failed: %d\n", rc); 2965 goto done; 2966 } 2967 2968 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, true, true); 2969 if (rc != 0) { 2970 if_printf(ifp, "enable_vi failed: %d\n", rc); 2971 goto done; 2972 } 2973 2974 /* 2975 * The first iq of the first port to come up is used for tracing. 2976 */ 2977 if (sc->traceq < 0) { 2978 sc->traceq = sc->sge.rxq[pi->first_rxq].iq.abs_id; 2979 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 2980 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 2981 V_QUEUENUMBER(sc->traceq)); 2982 pi->flags |= HAS_TRACEQ; 2983 } 2984 2985 /* all ok */ 2986 setbit(&sc->open_device_map, pi->port_id); 2987 PORT_LOCK(pi); 2988 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2989 PORT_UNLOCK(pi); 2990 2991 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 2992 done: 2993 if (rc != 0) 2994 cxgbe_uninit_synchronized(pi); 2995 2996 return (rc); 2997 } 2998 2999 /* 3000 * Idempotent. 3001 */ 3002 static int 3003 cxgbe_uninit_synchronized(struct port_info *pi) 3004 { 3005 struct adapter *sc = pi->adapter; 3006 struct ifnet *ifp = pi->ifp; 3007 int rc; 3008 3009 ASSERT_SYNCHRONIZED_OP(sc); 3010 3011 /* 3012 * Disable the VI so that all its data in either direction is discarded 3013 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 3014 * tick) intact as the TP can deliver negative advice or data that it's 3015 * holding in its RAM (for an offloaded connection) even after the VI is 3016 * disabled. 3017 */ 3018 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, false, false); 3019 if (rc) { 3020 if_printf(ifp, "disable_vi failed: %d\n", rc); 3021 return (rc); 3022 } 3023 3024 clrbit(&sc->open_device_map, pi->port_id); 3025 PORT_LOCK(pi); 3026 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3027 PORT_UNLOCK(pi); 3028 3029 pi->link_cfg.link_ok = 0; 3030 pi->link_cfg.speed = 0; 3031 pi->linkdnrc = -1; 3032 t4_os_link_changed(sc, pi->port_id, 0, -1); 3033 3034 return (0); 3035 } 3036 3037 /* 3038 * It is ok for this function to fail midway and return right away. t4_detach 3039 * will walk the entire sc->irq list and clean up whatever is valid. 3040 */ 3041 static int 3042 setup_intr_handlers(struct adapter *sc) 3043 { 3044 int rc, rid, p, q; 3045 char s[8]; 3046 struct irq *irq; 3047 struct port_info *pi; 3048 struct sge_rxq *rxq; 3049 #ifdef TCP_OFFLOAD 3050 struct sge_ofld_rxq *ofld_rxq; 3051 #endif 3052 3053 /* 3054 * Setup interrupts. 3055 */ 3056 irq = &sc->irq[0]; 3057 rid = sc->intr_type == INTR_INTX ? 0 : 1; 3058 if (sc->intr_count == 1) { 3059 KASSERT(!(sc->flags & INTR_DIRECT), 3060 ("%s: single interrupt && INTR_DIRECT?", __func__)); 3061 3062 rc = t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"); 3063 if (rc != 0) 3064 return (rc); 3065 } else { 3066 /* Multiple interrupts. */ 3067 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 3068 ("%s: too few intr.", __func__)); 3069 3070 /* The first one is always error intr */ 3071 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 3072 if (rc != 0) 3073 return (rc); 3074 irq++; 3075 rid++; 3076 3077 /* The second one is always the firmware event queue */ 3078 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sc->sge.fwq, 3079 "evt"); 3080 if (rc != 0) 3081 return (rc); 3082 irq++; 3083 rid++; 3084 3085 /* 3086 * Note that if INTR_DIRECT is not set then either the NIC rx 3087 * queues or (exclusive or) the TOE rx queueus will be taking 3088 * direct interrupts. 3089 * 3090 * There is no need to check for is_offload(sc) as nofldrxq 3091 * will be 0 if offload is disabled. 3092 */ 3093 for_each_port(sc, p) { 3094 pi = sc->port[p]; 3095 3096 #ifdef TCP_OFFLOAD 3097 /* 3098 * Skip over the NIC queues if they aren't taking direct 3099 * interrupts. 3100 */ 3101 if (!(sc->flags & INTR_DIRECT) && 3102 pi->nofldrxq > pi->nrxq) 3103 goto ofld_queues; 3104 #endif 3105 rxq = &sc->sge.rxq[pi->first_rxq]; 3106 for (q = 0; q < pi->nrxq; q++, rxq++) { 3107 snprintf(s, sizeof(s), "%d.%d", p, q); 3108 rc = t4_alloc_irq(sc, irq, rid, t4_intr, rxq, 3109 s); 3110 if (rc != 0) 3111 return (rc); 3112 irq++; 3113 rid++; 3114 } 3115 3116 #ifdef TCP_OFFLOAD 3117 /* 3118 * Skip over the offload queues if they aren't taking 3119 * direct interrupts. 3120 */ 3121 if (!(sc->flags & INTR_DIRECT)) 3122 continue; 3123 ofld_queues: 3124 ofld_rxq = &sc->sge.ofld_rxq[pi->first_ofld_rxq]; 3125 for (q = 0; q < pi->nofldrxq; q++, ofld_rxq++) { 3126 snprintf(s, sizeof(s), "%d,%d", p, q); 3127 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 3128 ofld_rxq, s); 3129 if (rc != 0) 3130 return (rc); 3131 irq++; 3132 rid++; 3133 } 3134 #endif 3135 } 3136 } 3137 3138 return (0); 3139 } 3140 3141 static int 3142 adapter_full_init(struct adapter *sc) 3143 { 3144 int rc, i; 3145 3146 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 3147 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 3148 ("%s: FULL_INIT_DONE already", __func__)); 3149 3150 /* 3151 * queues that belong to the adapter (not any particular port). 3152 */ 3153 rc = t4_setup_adapter_queues(sc); 3154 if (rc != 0) 3155 goto done; 3156 3157 for (i = 0; i < nitems(sc->tq); i++) { 3158 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 3159 taskqueue_thread_enqueue, &sc->tq[i]); 3160 if (sc->tq[i] == NULL) { 3161 device_printf(sc->dev, 3162 "failed to allocate task queue %d\n", i); 3163 rc = ENOMEM; 3164 goto done; 3165 } 3166 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 3167 device_get_nameunit(sc->dev), i); 3168 } 3169 3170 t4_intr_enable(sc); 3171 sc->flags |= FULL_INIT_DONE; 3172 done: 3173 if (rc != 0) 3174 adapter_full_uninit(sc); 3175 3176 return (rc); 3177 } 3178 3179 static int 3180 adapter_full_uninit(struct adapter *sc) 3181 { 3182 int i; 3183 3184 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 3185 3186 t4_teardown_adapter_queues(sc); 3187 3188 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 3189 taskqueue_free(sc->tq[i]); 3190 sc->tq[i] = NULL; 3191 } 3192 3193 sc->flags &= ~FULL_INIT_DONE; 3194 3195 return (0); 3196 } 3197 3198 static int 3199 port_full_init(struct port_info *pi) 3200 { 3201 struct adapter *sc = pi->adapter; 3202 struct ifnet *ifp = pi->ifp; 3203 uint16_t *rss; 3204 struct sge_rxq *rxq; 3205 int rc, i, j; 3206 3207 ASSERT_SYNCHRONIZED_OP(sc); 3208 KASSERT((pi->flags & PORT_INIT_DONE) == 0, 3209 ("%s: PORT_INIT_DONE already", __func__)); 3210 3211 sysctl_ctx_init(&pi->ctx); 3212 pi->flags |= PORT_SYSCTL_CTX; 3213 3214 /* 3215 * Allocate tx/rx/fl queues for this port. 3216 */ 3217 rc = t4_setup_port_queues(pi); 3218 if (rc != 0) 3219 goto done; /* error message displayed already */ 3220 3221 /* 3222 * Setup RSS for this port. Save a copy of the RSS table for later use. 3223 */ 3224 rss = malloc(pi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 3225 for (i = 0; i < pi->rss_size;) { 3226 for_each_rxq(pi, j, rxq) { 3227 rss[i++] = rxq->iq.abs_id; 3228 if (i == pi->rss_size) 3229 break; 3230 } 3231 } 3232 3233 rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0, pi->rss_size, rss, 3234 pi->rss_size); 3235 if (rc != 0) { 3236 if_printf(ifp, "rss_config failed: %d\n", rc); 3237 goto done; 3238 } 3239 3240 pi->rss = rss; 3241 pi->flags |= PORT_INIT_DONE; 3242 done: 3243 if (rc != 0) 3244 port_full_uninit(pi); 3245 3246 return (rc); 3247 } 3248 3249 /* 3250 * Idempotent. 3251 */ 3252 static int 3253 port_full_uninit(struct port_info *pi) 3254 { 3255 struct adapter *sc = pi->adapter; 3256 int i; 3257 struct sge_rxq *rxq; 3258 struct sge_txq *txq; 3259 #ifdef TCP_OFFLOAD 3260 struct sge_ofld_rxq *ofld_rxq; 3261 struct sge_wrq *ofld_txq; 3262 #endif 3263 3264 if (pi->flags & PORT_INIT_DONE) { 3265 3266 /* Need to quiesce queues. XXX: ctrl queues? */ 3267 3268 for_each_txq(pi, i, txq) { 3269 quiesce_eq(sc, &txq->eq); 3270 } 3271 3272 #ifdef TCP_OFFLOAD 3273 for_each_ofld_txq(pi, i, ofld_txq) { 3274 quiesce_eq(sc, &ofld_txq->eq); 3275 } 3276 #endif 3277 3278 for_each_rxq(pi, i, rxq) { 3279 quiesce_iq(sc, &rxq->iq); 3280 quiesce_fl(sc, &rxq->fl); 3281 } 3282 3283 #ifdef TCP_OFFLOAD 3284 for_each_ofld_rxq(pi, i, ofld_rxq) { 3285 quiesce_iq(sc, &ofld_rxq->iq); 3286 quiesce_fl(sc, &ofld_rxq->fl); 3287 } 3288 #endif 3289 free(pi->rss, M_CXGBE); 3290 } 3291 3292 t4_teardown_port_queues(pi); 3293 pi->flags &= ~PORT_INIT_DONE; 3294 3295 return (0); 3296 } 3297 3298 static void 3299 quiesce_eq(struct adapter *sc, struct sge_eq *eq) 3300 { 3301 EQ_LOCK(eq); 3302 eq->flags |= EQ_DOOMED; 3303 3304 /* 3305 * Wait for the response to a credit flush if one's 3306 * pending. 3307 */ 3308 while (eq->flags & EQ_CRFLUSHED) 3309 mtx_sleep(eq, &eq->eq_lock, 0, "crflush", 0); 3310 EQ_UNLOCK(eq); 3311 3312 callout_drain(&eq->tx_callout); /* XXX: iffy */ 3313 pause("callout", 10); /* Still iffy */ 3314 3315 taskqueue_drain(sc->tq[eq->tx_chan], &eq->tx_task); 3316 } 3317 3318 static void 3319 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 3320 { 3321 (void) sc; /* unused */ 3322 3323 /* Synchronize with the interrupt handler */ 3324 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 3325 pause("iqfree", 1); 3326 } 3327 3328 static void 3329 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 3330 { 3331 mtx_lock(&sc->sfl_lock); 3332 FL_LOCK(fl); 3333 fl->flags |= FL_DOOMED; 3334 FL_UNLOCK(fl); 3335 mtx_unlock(&sc->sfl_lock); 3336 3337 callout_drain(&sc->sfl_callout); 3338 KASSERT((fl->flags & FL_STARVING) == 0, 3339 ("%s: still starving", __func__)); 3340 } 3341 3342 static int 3343 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 3344 driver_intr_t *handler, void *arg, char *name) 3345 { 3346 int rc; 3347 3348 irq->rid = rid; 3349 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 3350 RF_SHAREABLE | RF_ACTIVE); 3351 if (irq->res == NULL) { 3352 device_printf(sc->dev, 3353 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 3354 return (ENOMEM); 3355 } 3356 3357 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 3358 NULL, handler, arg, &irq->tag); 3359 if (rc != 0) { 3360 device_printf(sc->dev, 3361 "failed to setup interrupt for rid %d, name %s: %d\n", 3362 rid, name, rc); 3363 } else if (name) 3364 bus_describe_intr(sc->dev, irq->res, irq->tag, name); 3365 3366 return (rc); 3367 } 3368 3369 static int 3370 t4_free_irq(struct adapter *sc, struct irq *irq) 3371 { 3372 if (irq->tag) 3373 bus_teardown_intr(sc->dev, irq->res, irq->tag); 3374 if (irq->res) 3375 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 3376 3377 bzero(irq, sizeof(*irq)); 3378 3379 return (0); 3380 } 3381 3382 static void 3383 reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start, 3384 unsigned int end) 3385 { 3386 uint32_t *p = (uint32_t *)(buf + start); 3387 3388 for ( ; start <= end; start += sizeof(uint32_t)) 3389 *p++ = t4_read_reg(sc, start); 3390 } 3391 3392 static void 3393 t4_get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 3394 { 3395 int i, n; 3396 const unsigned int *reg_ranges; 3397 static const unsigned int t4_reg_ranges[] = { 3398 0x1008, 0x1108, 3399 0x1180, 0x11b4, 3400 0x11fc, 0x123c, 3401 0x1300, 0x173c, 3402 0x1800, 0x18fc, 3403 0x3000, 0x30d8, 3404 0x30e0, 0x5924, 3405 0x5960, 0x59d4, 3406 0x5a00, 0x5af8, 3407 0x6000, 0x6098, 3408 0x6100, 0x6150, 3409 0x6200, 0x6208, 3410 0x6240, 0x6248, 3411 0x6280, 0x6338, 3412 0x6370, 0x638c, 3413 0x6400, 0x643c, 3414 0x6500, 0x6524, 3415 0x6a00, 0x6a38, 3416 0x6a60, 0x6a78, 3417 0x6b00, 0x6b84, 3418 0x6bf0, 0x6c84, 3419 0x6cf0, 0x6d84, 3420 0x6df0, 0x6e84, 3421 0x6ef0, 0x6f84, 3422 0x6ff0, 0x7084, 3423 0x70f0, 0x7184, 3424 0x71f0, 0x7284, 3425 0x72f0, 0x7384, 3426 0x73f0, 0x7450, 3427 0x7500, 0x7530, 3428 0x7600, 0x761c, 3429 0x7680, 0x76cc, 3430 0x7700, 0x7798, 3431 0x77c0, 0x77fc, 3432 0x7900, 0x79fc, 3433 0x7b00, 0x7c38, 3434 0x7d00, 0x7efc, 3435 0x8dc0, 0x8e1c, 3436 0x8e30, 0x8e78, 3437 0x8ea0, 0x8f6c, 3438 0x8fc0, 0x9074, 3439 0x90fc, 0x90fc, 3440 0x9400, 0x9458, 3441 0x9600, 0x96bc, 3442 0x9800, 0x9808, 3443 0x9820, 0x983c, 3444 0x9850, 0x9864, 3445 0x9c00, 0x9c6c, 3446 0x9c80, 0x9cec, 3447 0x9d00, 0x9d6c, 3448 0x9d80, 0x9dec, 3449 0x9e00, 0x9e6c, 3450 0x9e80, 0x9eec, 3451 0x9f00, 0x9f6c, 3452 0x9f80, 0x9fec, 3453 0xd004, 0xd03c, 3454 0xdfc0, 0xdfe0, 3455 0xe000, 0xea7c, 3456 0xf000, 0x11110, 3457 0x11118, 0x11190, 3458 0x19040, 0x1906c, 3459 0x19078, 0x19080, 3460 0x1908c, 0x19124, 3461 0x19150, 0x191b0, 3462 0x191d0, 0x191e8, 3463 0x19238, 0x1924c, 3464 0x193f8, 0x19474, 3465 0x19490, 0x194f8, 3466 0x19800, 0x19f30, 3467 0x1a000, 0x1a06c, 3468 0x1a0b0, 0x1a120, 3469 0x1a128, 0x1a138, 3470 0x1a190, 0x1a1c4, 3471 0x1a1fc, 0x1a1fc, 3472 0x1e040, 0x1e04c, 3473 0x1e284, 0x1e28c, 3474 0x1e2c0, 0x1e2c0, 3475 0x1e2e0, 0x1e2e0, 3476 0x1e300, 0x1e384, 3477 0x1e3c0, 0x1e3c8, 3478 0x1e440, 0x1e44c, 3479 0x1e684, 0x1e68c, 3480 0x1e6c0, 0x1e6c0, 3481 0x1e6e0, 0x1e6e0, 3482 0x1e700, 0x1e784, 3483 0x1e7c0, 0x1e7c8, 3484 0x1e840, 0x1e84c, 3485 0x1ea84, 0x1ea8c, 3486 0x1eac0, 0x1eac0, 3487 0x1eae0, 0x1eae0, 3488 0x1eb00, 0x1eb84, 3489 0x1ebc0, 0x1ebc8, 3490 0x1ec40, 0x1ec4c, 3491 0x1ee84, 0x1ee8c, 3492 0x1eec0, 0x1eec0, 3493 0x1eee0, 0x1eee0, 3494 0x1ef00, 0x1ef84, 3495 0x1efc0, 0x1efc8, 3496 0x1f040, 0x1f04c, 3497 0x1f284, 0x1f28c, 3498 0x1f2c0, 0x1f2c0, 3499 0x1f2e0, 0x1f2e0, 3500 0x1f300, 0x1f384, 3501 0x1f3c0, 0x1f3c8, 3502 0x1f440, 0x1f44c, 3503 0x1f684, 0x1f68c, 3504 0x1f6c0, 0x1f6c0, 3505 0x1f6e0, 0x1f6e0, 3506 0x1f700, 0x1f784, 3507 0x1f7c0, 0x1f7c8, 3508 0x1f840, 0x1f84c, 3509 0x1fa84, 0x1fa8c, 3510 0x1fac0, 0x1fac0, 3511 0x1fae0, 0x1fae0, 3512 0x1fb00, 0x1fb84, 3513 0x1fbc0, 0x1fbc8, 3514 0x1fc40, 0x1fc4c, 3515 0x1fe84, 0x1fe8c, 3516 0x1fec0, 0x1fec0, 3517 0x1fee0, 0x1fee0, 3518 0x1ff00, 0x1ff84, 3519 0x1ffc0, 0x1ffc8, 3520 0x20000, 0x2002c, 3521 0x20100, 0x2013c, 3522 0x20190, 0x201c8, 3523 0x20200, 0x20318, 3524 0x20400, 0x20528, 3525 0x20540, 0x20614, 3526 0x21000, 0x21040, 3527 0x2104c, 0x21060, 3528 0x210c0, 0x210ec, 3529 0x21200, 0x21268, 3530 0x21270, 0x21284, 3531 0x212fc, 0x21388, 3532 0x21400, 0x21404, 3533 0x21500, 0x21518, 3534 0x2152c, 0x2153c, 3535 0x21550, 0x21554, 3536 0x21600, 0x21600, 3537 0x21608, 0x21628, 3538 0x21630, 0x2163c, 3539 0x21700, 0x2171c, 3540 0x21780, 0x2178c, 3541 0x21800, 0x21c38, 3542 0x21c80, 0x21d7c, 3543 0x21e00, 0x21e04, 3544 0x22000, 0x2202c, 3545 0x22100, 0x2213c, 3546 0x22190, 0x221c8, 3547 0x22200, 0x22318, 3548 0x22400, 0x22528, 3549 0x22540, 0x22614, 3550 0x23000, 0x23040, 3551 0x2304c, 0x23060, 3552 0x230c0, 0x230ec, 3553 0x23200, 0x23268, 3554 0x23270, 0x23284, 3555 0x232fc, 0x23388, 3556 0x23400, 0x23404, 3557 0x23500, 0x23518, 3558 0x2352c, 0x2353c, 3559 0x23550, 0x23554, 3560 0x23600, 0x23600, 3561 0x23608, 0x23628, 3562 0x23630, 0x2363c, 3563 0x23700, 0x2371c, 3564 0x23780, 0x2378c, 3565 0x23800, 0x23c38, 3566 0x23c80, 0x23d7c, 3567 0x23e00, 0x23e04, 3568 0x24000, 0x2402c, 3569 0x24100, 0x2413c, 3570 0x24190, 0x241c8, 3571 0x24200, 0x24318, 3572 0x24400, 0x24528, 3573 0x24540, 0x24614, 3574 0x25000, 0x25040, 3575 0x2504c, 0x25060, 3576 0x250c0, 0x250ec, 3577 0x25200, 0x25268, 3578 0x25270, 0x25284, 3579 0x252fc, 0x25388, 3580 0x25400, 0x25404, 3581 0x25500, 0x25518, 3582 0x2552c, 0x2553c, 3583 0x25550, 0x25554, 3584 0x25600, 0x25600, 3585 0x25608, 0x25628, 3586 0x25630, 0x2563c, 3587 0x25700, 0x2571c, 3588 0x25780, 0x2578c, 3589 0x25800, 0x25c38, 3590 0x25c80, 0x25d7c, 3591 0x25e00, 0x25e04, 3592 0x26000, 0x2602c, 3593 0x26100, 0x2613c, 3594 0x26190, 0x261c8, 3595 0x26200, 0x26318, 3596 0x26400, 0x26528, 3597 0x26540, 0x26614, 3598 0x27000, 0x27040, 3599 0x2704c, 0x27060, 3600 0x270c0, 0x270ec, 3601 0x27200, 0x27268, 3602 0x27270, 0x27284, 3603 0x272fc, 0x27388, 3604 0x27400, 0x27404, 3605 0x27500, 0x27518, 3606 0x2752c, 0x2753c, 3607 0x27550, 0x27554, 3608 0x27600, 0x27600, 3609 0x27608, 0x27628, 3610 0x27630, 0x2763c, 3611 0x27700, 0x2771c, 3612 0x27780, 0x2778c, 3613 0x27800, 0x27c38, 3614 0x27c80, 0x27d7c, 3615 0x27e00, 0x27e04 3616 }; 3617 static const unsigned int t5_reg_ranges[] = { 3618 0x1008, 0x1148, 3619 0x1180, 0x11b4, 3620 0x11fc, 0x123c, 3621 0x1280, 0x173c, 3622 0x1800, 0x18fc, 3623 0x3000, 0x3028, 3624 0x3060, 0x30d8, 3625 0x30e0, 0x30fc, 3626 0x3140, 0x357c, 3627 0x35a8, 0x35cc, 3628 0x35ec, 0x35ec, 3629 0x3600, 0x5624, 3630 0x56cc, 0x575c, 3631 0x580c, 0x5814, 3632 0x5890, 0x58bc, 3633 0x5940, 0x59dc, 3634 0x59fc, 0x5a18, 3635 0x5a60, 0x5a9c, 3636 0x5b94, 0x5bfc, 3637 0x6000, 0x6040, 3638 0x6058, 0x614c, 3639 0x7700, 0x7798, 3640 0x77c0, 0x78fc, 3641 0x7b00, 0x7c54, 3642 0x7d00, 0x7efc, 3643 0x8dc0, 0x8de0, 3644 0x8df8, 0x8e84, 3645 0x8ea0, 0x8f84, 3646 0x8fc0, 0x90f8, 3647 0x9400, 0x9470, 3648 0x9600, 0x96f4, 3649 0x9800, 0x9808, 3650 0x9820, 0x983c, 3651 0x9850, 0x9864, 3652 0x9c00, 0x9c6c, 3653 0x9c80, 0x9cec, 3654 0x9d00, 0x9d6c, 3655 0x9d80, 0x9dec, 3656 0x9e00, 0x9e6c, 3657 0x9e80, 0x9eec, 3658 0x9f00, 0x9f6c, 3659 0x9f80, 0xa020, 3660 0xd004, 0xd03c, 3661 0xdfc0, 0xdfe0, 3662 0xe000, 0x11088, 3663 0x1109c, 0x11110, 3664 0x11118, 0x1117c, 3665 0x11190, 0x11204, 3666 0x19040, 0x1906c, 3667 0x19078, 0x19080, 3668 0x1908c, 0x19124, 3669 0x19150, 0x191b0, 3670 0x191d0, 0x191e8, 3671 0x19238, 0x19290, 3672 0x193f8, 0x19474, 3673 0x19490, 0x194cc, 3674 0x194f0, 0x194f8, 3675 0x19c00, 0x19c60, 3676 0x19c94, 0x19e10, 3677 0x19e50, 0x19f34, 3678 0x19f40, 0x19f50, 3679 0x19f90, 0x19fe4, 3680 0x1a000, 0x1a06c, 3681 0x1a0b0, 0x1a120, 3682 0x1a128, 0x1a138, 3683 0x1a190, 0x1a1c4, 3684 0x1a1fc, 0x1a1fc, 3685 0x1e008, 0x1e00c, 3686 0x1e040, 0x1e04c, 3687 0x1e284, 0x1e290, 3688 0x1e2c0, 0x1e2c0, 3689 0x1e2e0, 0x1e2e0, 3690 0x1e300, 0x1e384, 3691 0x1e3c0, 0x1e3c8, 3692 0x1e408, 0x1e40c, 3693 0x1e440, 0x1e44c, 3694 0x1e684, 0x1e690, 3695 0x1e6c0, 0x1e6c0, 3696 0x1e6e0, 0x1e6e0, 3697 0x1e700, 0x1e784, 3698 0x1e7c0, 0x1e7c8, 3699 0x1e808, 0x1e80c, 3700 0x1e840, 0x1e84c, 3701 0x1ea84, 0x1ea90, 3702 0x1eac0, 0x1eac0, 3703 0x1eae0, 0x1eae0, 3704 0x1eb00, 0x1eb84, 3705 0x1ebc0, 0x1ebc8, 3706 0x1ec08, 0x1ec0c, 3707 0x1ec40, 0x1ec4c, 3708 0x1ee84, 0x1ee90, 3709 0x1eec0, 0x1eec0, 3710 0x1eee0, 0x1eee0, 3711 0x1ef00, 0x1ef84, 3712 0x1efc0, 0x1efc8, 3713 0x1f008, 0x1f00c, 3714 0x1f040, 0x1f04c, 3715 0x1f284, 0x1f290, 3716 0x1f2c0, 0x1f2c0, 3717 0x1f2e0, 0x1f2e0, 3718 0x1f300, 0x1f384, 3719 0x1f3c0, 0x1f3c8, 3720 0x1f408, 0x1f40c, 3721 0x1f440, 0x1f44c, 3722 0x1f684, 0x1f690, 3723 0x1f6c0, 0x1f6c0, 3724 0x1f6e0, 0x1f6e0, 3725 0x1f700, 0x1f784, 3726 0x1f7c0, 0x1f7c8, 3727 0x1f808, 0x1f80c, 3728 0x1f840, 0x1f84c, 3729 0x1fa84, 0x1fa90, 3730 0x1fac0, 0x1fac0, 3731 0x1fae0, 0x1fae0, 3732 0x1fb00, 0x1fb84, 3733 0x1fbc0, 0x1fbc8, 3734 0x1fc08, 0x1fc0c, 3735 0x1fc40, 0x1fc4c, 3736 0x1fe84, 0x1fe90, 3737 0x1fec0, 0x1fec0, 3738 0x1fee0, 0x1fee0, 3739 0x1ff00, 0x1ff84, 3740 0x1ffc0, 0x1ffc8, 3741 0x30000, 0x30030, 3742 0x30100, 0x30144, 3743 0x30190, 0x301d0, 3744 0x30200, 0x30318, 3745 0x30400, 0x3052c, 3746 0x30540, 0x3061c, 3747 0x30800, 0x30834, 3748 0x308c0, 0x30908, 3749 0x30910, 0x309ac, 3750 0x30a00, 0x30a2c, 3751 0x30a44, 0x30a50, 3752 0x30a74, 0x30c24, 3753 0x30d00, 0x30d00, 3754 0x30d08, 0x30d14, 3755 0x30d1c, 0x30d20, 3756 0x30d3c, 0x30d50, 3757 0x31200, 0x3120c, 3758 0x31220, 0x31220, 3759 0x31240, 0x31240, 3760 0x31600, 0x3160c, 3761 0x31a00, 0x31a1c, 3762 0x31e00, 0x31e20, 3763 0x31e38, 0x31e3c, 3764 0x31e80, 0x31e80, 3765 0x31e88, 0x31ea8, 3766 0x31eb0, 0x31eb4, 3767 0x31ec8, 0x31ed4, 3768 0x31fb8, 0x32004, 3769 0x32200, 0x32200, 3770 0x32208, 0x32240, 3771 0x32248, 0x32280, 3772 0x32288, 0x322c0, 3773 0x322c8, 0x322fc, 3774 0x32600, 0x32630, 3775 0x32a00, 0x32abc, 3776 0x32b00, 0x32b70, 3777 0x33000, 0x33048, 3778 0x33060, 0x3309c, 3779 0x330f0, 0x33148, 3780 0x33160, 0x3319c, 3781 0x331f0, 0x332e4, 3782 0x332f8, 0x333e4, 3783 0x333f8, 0x33448, 3784 0x33460, 0x3349c, 3785 0x334f0, 0x33548, 3786 0x33560, 0x3359c, 3787 0x335f0, 0x336e4, 3788 0x336f8, 0x337e4, 3789 0x337f8, 0x337fc, 3790 0x33814, 0x33814, 3791 0x3382c, 0x3382c, 3792 0x33880, 0x3388c, 3793 0x338e8, 0x338ec, 3794 0x33900, 0x33948, 3795 0x33960, 0x3399c, 3796 0x339f0, 0x33ae4, 3797 0x33af8, 0x33b10, 3798 0x33b28, 0x33b28, 3799 0x33b3c, 0x33b50, 3800 0x33bf0, 0x33c10, 3801 0x33c28, 0x33c28, 3802 0x33c3c, 0x33c50, 3803 0x33cf0, 0x33cfc, 3804 0x34000, 0x34030, 3805 0x34100, 0x34144, 3806 0x34190, 0x341d0, 3807 0x34200, 0x34318, 3808 0x34400, 0x3452c, 3809 0x34540, 0x3461c, 3810 0x34800, 0x34834, 3811 0x348c0, 0x34908, 3812 0x34910, 0x349ac, 3813 0x34a00, 0x34a2c, 3814 0x34a44, 0x34a50, 3815 0x34a74, 0x34c24, 3816 0x34d00, 0x34d00, 3817 0x34d08, 0x34d14, 3818 0x34d1c, 0x34d20, 3819 0x34d3c, 0x34d50, 3820 0x35200, 0x3520c, 3821 0x35220, 0x35220, 3822 0x35240, 0x35240, 3823 0x35600, 0x3560c, 3824 0x35a00, 0x35a1c, 3825 0x35e00, 0x35e20, 3826 0x35e38, 0x35e3c, 3827 0x35e80, 0x35e80, 3828 0x35e88, 0x35ea8, 3829 0x35eb0, 0x35eb4, 3830 0x35ec8, 0x35ed4, 3831 0x35fb8, 0x36004, 3832 0x36200, 0x36200, 3833 0x36208, 0x36240, 3834 0x36248, 0x36280, 3835 0x36288, 0x362c0, 3836 0x362c8, 0x362fc, 3837 0x36600, 0x36630, 3838 0x36a00, 0x36abc, 3839 0x36b00, 0x36b70, 3840 0x37000, 0x37048, 3841 0x37060, 0x3709c, 3842 0x370f0, 0x37148, 3843 0x37160, 0x3719c, 3844 0x371f0, 0x372e4, 3845 0x372f8, 0x373e4, 3846 0x373f8, 0x37448, 3847 0x37460, 0x3749c, 3848 0x374f0, 0x37548, 3849 0x37560, 0x3759c, 3850 0x375f0, 0x376e4, 3851 0x376f8, 0x377e4, 3852 0x377f8, 0x377fc, 3853 0x37814, 0x37814, 3854 0x3782c, 0x3782c, 3855 0x37880, 0x3788c, 3856 0x378e8, 0x378ec, 3857 0x37900, 0x37948, 3858 0x37960, 0x3799c, 3859 0x379f0, 0x37ae4, 3860 0x37af8, 0x37b10, 3861 0x37b28, 0x37b28, 3862 0x37b3c, 0x37b50, 3863 0x37bf0, 0x37c10, 3864 0x37c28, 0x37c28, 3865 0x37c3c, 0x37c50, 3866 0x37cf0, 0x37cfc, 3867 0x38000, 0x38030, 3868 0x38100, 0x38144, 3869 0x38190, 0x381d0, 3870 0x38200, 0x38318, 3871 0x38400, 0x3852c, 3872 0x38540, 0x3861c, 3873 0x38800, 0x38834, 3874 0x388c0, 0x38908, 3875 0x38910, 0x389ac, 3876 0x38a00, 0x38a2c, 3877 0x38a44, 0x38a50, 3878 0x38a74, 0x38c24, 3879 0x38d00, 0x38d00, 3880 0x38d08, 0x38d14, 3881 0x38d1c, 0x38d20, 3882 0x38d3c, 0x38d50, 3883 0x39200, 0x3920c, 3884 0x39220, 0x39220, 3885 0x39240, 0x39240, 3886 0x39600, 0x3960c, 3887 0x39a00, 0x39a1c, 3888 0x39e00, 0x39e20, 3889 0x39e38, 0x39e3c, 3890 0x39e80, 0x39e80, 3891 0x39e88, 0x39ea8, 3892 0x39eb0, 0x39eb4, 3893 0x39ec8, 0x39ed4, 3894 0x39fb8, 0x3a004, 3895 0x3a200, 0x3a200, 3896 0x3a208, 0x3a240, 3897 0x3a248, 0x3a280, 3898 0x3a288, 0x3a2c0, 3899 0x3a2c8, 0x3a2fc, 3900 0x3a600, 0x3a630, 3901 0x3aa00, 0x3aabc, 3902 0x3ab00, 0x3ab70, 3903 0x3b000, 0x3b048, 3904 0x3b060, 0x3b09c, 3905 0x3b0f0, 0x3b148, 3906 0x3b160, 0x3b19c, 3907 0x3b1f0, 0x3b2e4, 3908 0x3b2f8, 0x3b3e4, 3909 0x3b3f8, 0x3b448, 3910 0x3b460, 0x3b49c, 3911 0x3b4f0, 0x3b548, 3912 0x3b560, 0x3b59c, 3913 0x3b5f0, 0x3b6e4, 3914 0x3b6f8, 0x3b7e4, 3915 0x3b7f8, 0x3b7fc, 3916 0x3b814, 0x3b814, 3917 0x3b82c, 0x3b82c, 3918 0x3b880, 0x3b88c, 3919 0x3b8e8, 0x3b8ec, 3920 0x3b900, 0x3b948, 3921 0x3b960, 0x3b99c, 3922 0x3b9f0, 0x3bae4, 3923 0x3baf8, 0x3bb10, 3924 0x3bb28, 0x3bb28, 3925 0x3bb3c, 0x3bb50, 3926 0x3bbf0, 0x3bc10, 3927 0x3bc28, 0x3bc28, 3928 0x3bc3c, 0x3bc50, 3929 0x3bcf0, 0x3bcfc, 3930 0x3c000, 0x3c030, 3931 0x3c100, 0x3c144, 3932 0x3c190, 0x3c1d0, 3933 0x3c200, 0x3c318, 3934 0x3c400, 0x3c52c, 3935 0x3c540, 0x3c61c, 3936 0x3c800, 0x3c834, 3937 0x3c8c0, 0x3c908, 3938 0x3c910, 0x3c9ac, 3939 0x3ca00, 0x3ca2c, 3940 0x3ca44, 0x3ca50, 3941 0x3ca74, 0x3cc24, 3942 0x3cd00, 0x3cd00, 3943 0x3cd08, 0x3cd14, 3944 0x3cd1c, 0x3cd20, 3945 0x3cd3c, 0x3cd50, 3946 0x3d200, 0x3d20c, 3947 0x3d220, 0x3d220, 3948 0x3d240, 0x3d240, 3949 0x3d600, 0x3d60c, 3950 0x3da00, 0x3da1c, 3951 0x3de00, 0x3de20, 3952 0x3de38, 0x3de3c, 3953 0x3de80, 0x3de80, 3954 0x3de88, 0x3dea8, 3955 0x3deb0, 0x3deb4, 3956 0x3dec8, 0x3ded4, 3957 0x3dfb8, 0x3e004, 3958 0x3e200, 0x3e200, 3959 0x3e208, 0x3e240, 3960 0x3e248, 0x3e280, 3961 0x3e288, 0x3e2c0, 3962 0x3e2c8, 0x3e2fc, 3963 0x3e600, 0x3e630, 3964 0x3ea00, 0x3eabc, 3965 0x3eb00, 0x3eb70, 3966 0x3f000, 0x3f048, 3967 0x3f060, 0x3f09c, 3968 0x3f0f0, 0x3f148, 3969 0x3f160, 0x3f19c, 3970 0x3f1f0, 0x3f2e4, 3971 0x3f2f8, 0x3f3e4, 3972 0x3f3f8, 0x3f448, 3973 0x3f460, 0x3f49c, 3974 0x3f4f0, 0x3f548, 3975 0x3f560, 0x3f59c, 3976 0x3f5f0, 0x3f6e4, 3977 0x3f6f8, 0x3f7e4, 3978 0x3f7f8, 0x3f7fc, 3979 0x3f814, 0x3f814, 3980 0x3f82c, 0x3f82c, 3981 0x3f880, 0x3f88c, 3982 0x3f8e8, 0x3f8ec, 3983 0x3f900, 0x3f948, 3984 0x3f960, 0x3f99c, 3985 0x3f9f0, 0x3fae4, 3986 0x3faf8, 0x3fb10, 3987 0x3fb28, 0x3fb28, 3988 0x3fb3c, 0x3fb50, 3989 0x3fbf0, 0x3fc10, 3990 0x3fc28, 0x3fc28, 3991 0x3fc3c, 0x3fc50, 3992 0x3fcf0, 0x3fcfc, 3993 0x40000, 0x4000c, 3994 0x40040, 0x40068, 3995 0x4007c, 0x40144, 3996 0x40180, 0x4018c, 3997 0x40200, 0x40298, 3998 0x402ac, 0x4033c, 3999 0x403f8, 0x403fc, 4000 0x41304, 0x413c4, 4001 0x41400, 0x4141c, 4002 0x41480, 0x414d0, 4003 0x44000, 0x44078, 4004 0x440c0, 0x44278, 4005 0x442c0, 0x44478, 4006 0x444c0, 0x44678, 4007 0x446c0, 0x44878, 4008 0x448c0, 0x449fc, 4009 0x45000, 0x45068, 4010 0x45080, 0x45084, 4011 0x450a0, 0x450b0, 4012 0x45200, 0x45268, 4013 0x45280, 0x45284, 4014 0x452a0, 0x452b0, 4015 0x460c0, 0x460e4, 4016 0x47000, 0x4708c, 4017 0x47200, 0x47250, 4018 0x47400, 0x47420, 4019 0x47600, 0x47618, 4020 0x47800, 0x47814, 4021 0x48000, 0x4800c, 4022 0x48040, 0x48068, 4023 0x4807c, 0x48144, 4024 0x48180, 0x4818c, 4025 0x48200, 0x48298, 4026 0x482ac, 0x4833c, 4027 0x483f8, 0x483fc, 4028 0x49304, 0x493c4, 4029 0x49400, 0x4941c, 4030 0x49480, 0x494d0, 4031 0x4c000, 0x4c078, 4032 0x4c0c0, 0x4c278, 4033 0x4c2c0, 0x4c478, 4034 0x4c4c0, 0x4c678, 4035 0x4c6c0, 0x4c878, 4036 0x4c8c0, 0x4c9fc, 4037 0x4d000, 0x4d068, 4038 0x4d080, 0x4d084, 4039 0x4d0a0, 0x4d0b0, 4040 0x4d200, 0x4d268, 4041 0x4d280, 0x4d284, 4042 0x4d2a0, 0x4d2b0, 4043 0x4e0c0, 0x4e0e4, 4044 0x4f000, 0x4f08c, 4045 0x4f200, 0x4f250, 4046 0x4f400, 0x4f420, 4047 0x4f600, 0x4f618, 4048 0x4f800, 0x4f814, 4049 0x50000, 0x500cc, 4050 0x50400, 0x50400, 4051 0x50800, 0x508cc, 4052 0x50c00, 0x50c00, 4053 0x51000, 0x5101c, 4054 0x51300, 0x51308, 4055 }; 4056 4057 if (is_t4(sc)) { 4058 reg_ranges = &t4_reg_ranges[0]; 4059 n = nitems(t4_reg_ranges); 4060 } else { 4061 reg_ranges = &t5_reg_ranges[0]; 4062 n = nitems(t5_reg_ranges); 4063 } 4064 4065 regs->version = chip_id(sc) | chip_rev(sc) << 10; 4066 for (i = 0; i < n; i += 2) 4067 reg_block_dump(sc, buf, reg_ranges[i], reg_ranges[i + 1]); 4068 } 4069 4070 static void 4071 cxgbe_tick(void *arg) 4072 { 4073 struct port_info *pi = arg; 4074 struct ifnet *ifp = pi->ifp; 4075 struct sge_txq *txq; 4076 int i, drops; 4077 struct port_stats *s = &pi->stats; 4078 4079 PORT_LOCK(pi); 4080 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4081 PORT_UNLOCK(pi); 4082 return; /* without scheduling another callout */ 4083 } 4084 4085 t4_get_port_stats(pi->adapter, pi->tx_chan, s); 4086 4087 ifp->if_opackets = s->tx_frames - s->tx_pause; 4088 ifp->if_ipackets = s->rx_frames - s->rx_pause; 4089 ifp->if_obytes = s->tx_octets - s->tx_pause * 64; 4090 ifp->if_ibytes = s->rx_octets - s->rx_pause * 64; 4091 ifp->if_omcasts = s->tx_mcast_frames - s->tx_pause; 4092 ifp->if_imcasts = s->rx_mcast_frames - s->rx_pause; 4093 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 4094 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 4095 s->rx_trunc3; 4096 4097 drops = s->tx_drop; 4098 for_each_txq(pi, i, txq) 4099 drops += txq->br->br_drops; 4100 ifp->if_snd.ifq_drops = drops; 4101 4102 ifp->if_oerrors = s->tx_error_frames; 4103 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long + 4104 s->rx_fcs_err + s->rx_len_err; 4105 4106 callout_schedule(&pi->tick, hz); 4107 PORT_UNLOCK(pi); 4108 } 4109 4110 static void 4111 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 4112 { 4113 struct ifnet *vlan; 4114 4115 if (arg != ifp || ifp->if_type != IFT_ETHER) 4116 return; 4117 4118 vlan = VLAN_DEVAT(ifp, vid); 4119 VLAN_SETCOOKIE(vlan, ifp); 4120 } 4121 4122 static int 4123 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 4124 { 4125 4126 #ifdef INVARIANTS 4127 panic("%s: opcode 0x%02x on iq %p with payload %p", 4128 __func__, rss->opcode, iq, m); 4129 #else 4130 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n", 4131 __func__, rss->opcode, iq, m); 4132 m_freem(m); 4133 #endif 4134 return (EDOOFUS); 4135 } 4136 4137 int 4138 t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h) 4139 { 4140 uintptr_t *loc, new; 4141 4142 if (opcode >= nitems(sc->cpl_handler)) 4143 return (EINVAL); 4144 4145 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled; 4146 loc = (uintptr_t *) &sc->cpl_handler[opcode]; 4147 atomic_store_rel_ptr(loc, new); 4148 4149 return (0); 4150 } 4151 4152 static int 4153 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl) 4154 { 4155 4156 #ifdef INVARIANTS 4157 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl); 4158 #else 4159 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n", 4160 __func__, iq, ctrl); 4161 #endif 4162 return (EDOOFUS); 4163 } 4164 4165 int 4166 t4_register_an_handler(struct adapter *sc, an_handler_t h) 4167 { 4168 uintptr_t *loc, new; 4169 4170 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled; 4171 loc = (uintptr_t *) &sc->an_handler; 4172 atomic_store_rel_ptr(loc, new); 4173 4174 return (0); 4175 } 4176 4177 static int 4178 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl) 4179 { 4180 const struct cpl_fw6_msg *cpl = 4181 __containerof(rpl, struct cpl_fw6_msg, data[0]); 4182 4183 #ifdef INVARIANTS 4184 panic("%s: fw_msg type %d", __func__, cpl->type); 4185 #else 4186 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type); 4187 #endif 4188 return (EDOOFUS); 4189 } 4190 4191 int 4192 t4_register_fw_msg_handler(struct adapter *sc, int type, fw_msg_handler_t h) 4193 { 4194 uintptr_t *loc, new; 4195 4196 if (type >= nitems(sc->fw_msg_handler)) 4197 return (EINVAL); 4198 4199 /* 4200 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 4201 * handler dispatch table. Reject any attempt to install a handler for 4202 * this subtype. 4203 */ 4204 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL) 4205 return (EINVAL); 4206 4207 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled; 4208 loc = (uintptr_t *) &sc->fw_msg_handler[type]; 4209 atomic_store_rel_ptr(loc, new); 4210 4211 return (0); 4212 } 4213 4214 static int 4215 t4_sysctls(struct adapter *sc) 4216 { 4217 struct sysctl_ctx_list *ctx; 4218 struct sysctl_oid *oid; 4219 struct sysctl_oid_list *children, *c0; 4220 static char *caps[] = { 4221 "\20\1PPP\2QFC\3DCBX", /* caps[0] linkcaps */ 4222 "\20\1NIC\2VM\3IDS\4UM\5UM_ISGL" /* caps[1] niccaps */ 4223 "\6HASHFILTER\7ETHOFLD", 4224 "\20\1TOE", /* caps[2] toecaps */ 4225 "\20\1RDDP\2RDMAC", /* caps[3] rdmacaps */ 4226 "\20\1INITIATOR_PDU\2TARGET_PDU" /* caps[4] iscsicaps */ 4227 "\3INITIATOR_CNXOFLD\4TARGET_CNXOFLD" 4228 "\5INITIATOR_SSNOFLD\6TARGET_SSNOFLD", 4229 "\20\1INITIATOR\2TARGET\3CTRL_OFLD" /* caps[5] fcoecaps */ 4230 "\4PO_INITIAOR\5PO_TARGET" 4231 }; 4232 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 4233 4234 ctx = device_get_sysctl_ctx(sc->dev); 4235 4236 /* 4237 * dev.t4nex.X. 4238 */ 4239 oid = device_get_sysctl_tree(sc->dev); 4240 c0 = children = SYSCTL_CHILDREN(oid); 4241 4242 sc->sc_do_rxcopy = 1; 4243 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 4244 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 4245 4246 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 4247 sc->params.nports, "# of ports"); 4248 4249 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 4250 NULL, chip_rev(sc), "chip hardware revision"); 4251 4252 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 4253 CTLFLAG_RD, &sc->fw_version, 0, "firmware version"); 4254 4255 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 4256 CTLFLAG_RD, &sc->cfg_file, 0, "configuration file"); 4257 4258 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 4259 sc->cfcsum, "config file checksum"); 4260 4261 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 4262 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 4263 sysctl_bitfield, "A", "available doorbells"); 4264 4265 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkcaps", 4266 CTLTYPE_STRING | CTLFLAG_RD, caps[0], sc->linkcaps, 4267 sysctl_bitfield, "A", "available link capabilities"); 4268 4269 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "niccaps", 4270 CTLTYPE_STRING | CTLFLAG_RD, caps[1], sc->niccaps, 4271 sysctl_bitfield, "A", "available NIC capabilities"); 4272 4273 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "toecaps", 4274 CTLTYPE_STRING | CTLFLAG_RD, caps[2], sc->toecaps, 4275 sysctl_bitfield, "A", "available TCP offload capabilities"); 4276 4277 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdmacaps", 4278 CTLTYPE_STRING | CTLFLAG_RD, caps[3], sc->rdmacaps, 4279 sysctl_bitfield, "A", "available RDMA capabilities"); 4280 4281 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "iscsicaps", 4282 CTLTYPE_STRING | CTLFLAG_RD, caps[4], sc->iscsicaps, 4283 sysctl_bitfield, "A", "available iSCSI capabilities"); 4284 4285 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoecaps", 4286 CTLTYPE_STRING | CTLFLAG_RD, caps[5], sc->fcoecaps, 4287 sysctl_bitfield, "A", "available FCoE capabilities"); 4288 4289 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 4290 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 4291 4292 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 4293 CTLTYPE_STRING | CTLFLAG_RD, sc->sge.timer_val, 4294 sizeof(sc->sge.timer_val), sysctl_int_array, "A", 4295 "interrupt holdoff timer values (us)"); 4296 4297 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 4298 CTLTYPE_STRING | CTLFLAG_RD, sc->sge.counter_val, 4299 sizeof(sc->sge.counter_val), sysctl_int_array, "A", 4300 "interrupt holdoff packet counter values"); 4301 4302 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 4303 NULL, sc->tids.nftids, "number of filters"); 4304 4305 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 4306 CTLFLAG_RD, sc, 0, sysctl_temperature, "A", 4307 "chip temperature (in Celsius)"); 4308 4309 t4_sge_sysctls(sc, ctx, children); 4310 4311 sc->lro_timeout = 100; 4312 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 4313 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 4314 4315 #ifdef SBUF_DRAIN 4316 /* 4317 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 4318 */ 4319 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 4320 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 4321 "logs and miscellaneous information"); 4322 children = SYSCTL_CHILDREN(oid); 4323 4324 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 4325 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4326 sysctl_cctrl, "A", "congestion control"); 4327 4328 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 4329 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4330 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 4331 4332 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 4333 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 4334 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 4335 4336 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 4337 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 4338 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 4339 4340 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 4341 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 4342 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 4343 4344 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 4345 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 4346 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 4347 4348 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 4349 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 4350 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 4351 4352 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 4353 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4354 sysctl_cim_la, "A", "CIM logic analyzer"); 4355 4356 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 4357 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4358 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 4359 4360 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 4361 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 4362 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 4363 4364 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 4365 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 4366 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 4367 4368 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 4369 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 4370 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 4371 4372 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 4373 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 4374 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 4375 4376 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 4377 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 4378 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 4379 4380 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 4381 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 4382 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 4383 4384 if (is_t5(sc)) { 4385 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 4386 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 4387 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 4388 4389 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 4390 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 4391 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 4392 } 4393 4394 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 4395 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4396 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 4397 4398 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 4399 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4400 sysctl_cim_qcfg, "A", "CIM queue configuration"); 4401 4402 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 4403 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4404 sysctl_cpl_stats, "A", "CPL statistics"); 4405 4406 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 4407 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4408 sysctl_ddp_stats, "A", "DDP statistics"); 4409 4410 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 4411 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4412 sysctl_devlog, "A", "firmware's device log"); 4413 4414 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 4415 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4416 sysctl_fcoe_stats, "A", "FCoE statistics"); 4417 4418 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 4419 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4420 sysctl_hw_sched, "A", "hardware scheduler "); 4421 4422 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 4423 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4424 sysctl_l2t, "A", "hardware L2 table"); 4425 4426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 4427 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4428 sysctl_lb_stats, "A", "loopback statistics"); 4429 4430 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 4431 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4432 sysctl_meminfo, "A", "memory regions"); 4433 4434 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 4435 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4436 sysctl_mps_tcam, "A", "MPS TCAM entries"); 4437 4438 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 4439 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4440 sysctl_path_mtus, "A", "path MTUs"); 4441 4442 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 4443 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4444 sysctl_pm_stats, "A", "PM statistics"); 4445 4446 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 4447 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4448 sysctl_rdma_stats, "A", "RDMA statistics"); 4449 4450 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 4451 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4452 sysctl_tcp_stats, "A", "TCP statistics"); 4453 4454 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 4455 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4456 sysctl_tids, "A", "TID information"); 4457 4458 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 4459 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4460 sysctl_tp_err_stats, "A", "TP error statistics"); 4461 4462 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 4463 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4464 sysctl_tp_la, "A", "TP logic analyzer"); 4465 4466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 4467 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4468 sysctl_tx_rate, "A", "Tx rate"); 4469 4470 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 4471 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4472 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 4473 4474 if (is_t5(sc)) { 4475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 4476 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4477 sysctl_wcwr_stats, "A", "write combined work requests"); 4478 } 4479 #endif 4480 4481 #ifdef TCP_OFFLOAD 4482 if (is_offload(sc)) { 4483 /* 4484 * dev.t4nex.X.toe. 4485 */ 4486 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 4487 NULL, "TOE parameters"); 4488 children = SYSCTL_CHILDREN(oid); 4489 4490 sc->tt.sndbuf = 256 * 1024; 4491 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 4492 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 4493 4494 sc->tt.ddp = 0; 4495 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 4496 &sc->tt.ddp, 0, "DDP allowed"); 4497 4498 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5)); 4499 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW, 4500 &sc->tt.indsz, 0, "DDP max indicate size allowed"); 4501 4502 sc->tt.ddp_thres = 4503 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)); 4504 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW, 4505 &sc->tt.ddp_thres, 0, "DDP threshold"); 4506 4507 sc->tt.rx_coalesce = 1; 4508 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 4509 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 4510 } 4511 #endif 4512 4513 4514 return (0); 4515 } 4516 4517 static int 4518 cxgbe_sysctls(struct port_info *pi) 4519 { 4520 struct sysctl_ctx_list *ctx; 4521 struct sysctl_oid *oid; 4522 struct sysctl_oid_list *children; 4523 struct adapter *sc = pi->adapter; 4524 4525 ctx = device_get_sysctl_ctx(pi->dev); 4526 4527 /* 4528 * dev.cxgbe.X. 4529 */ 4530 oid = device_get_sysctl_tree(pi->dev); 4531 children = SYSCTL_CHILDREN(oid); 4532 4533 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 4534 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 4535 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 4536 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 4537 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 4538 "PHY temperature (in Celsius)"); 4539 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 4540 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 4541 "PHY firmware version"); 4542 } 4543 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 4544 &pi->nrxq, 0, "# of rx queues"); 4545 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 4546 &pi->ntxq, 0, "# of tx queues"); 4547 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 4548 &pi->first_rxq, 0, "index of first rx queue"); 4549 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 4550 &pi->first_txq, 0, "index of first tx queue"); 4551 4552 #ifdef TCP_OFFLOAD 4553 if (is_offload(sc)) { 4554 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 4555 &pi->nofldrxq, 0, 4556 "# of rx queues for offloaded TCP connections"); 4557 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 4558 &pi->nofldtxq, 0, 4559 "# of tx queues for offloaded TCP connections"); 4560 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 4561 CTLFLAG_RD, &pi->first_ofld_rxq, 0, 4562 "index of first TOE rx queue"); 4563 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 4564 CTLFLAG_RD, &pi->first_ofld_txq, 0, 4565 "index of first TOE tx queue"); 4566 } 4567 #endif 4568 4569 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 4570 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_tmr_idx, "I", 4571 "holdoff timer index"); 4572 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 4573 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_pktc_idx, "I", 4574 "holdoff packet counter index"); 4575 4576 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 4577 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_rxq, "I", 4578 "rx queue size"); 4579 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 4580 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_txq, "I", 4581 "tx queue size"); 4582 4583 /* 4584 * dev.cxgbe.X.stats. 4585 */ 4586 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4587 NULL, "port statistics"); 4588 children = SYSCTL_CHILDREN(oid); 4589 4590 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 4591 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 4592 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 4593 sysctl_handle_t4_reg64, "QU", desc) 4594 4595 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 4596 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 4597 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 4598 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 4599 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 4600 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 4601 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 4602 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 4603 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 4604 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 4605 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 4606 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 4607 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 4608 "# of tx frames in this range", 4609 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 4610 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 4611 "# of tx frames in this range", 4612 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 4613 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 4614 "# of tx frames in this range", 4615 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 4616 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 4617 "# of tx frames in this range", 4618 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 4619 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 4620 "# of tx frames in this range", 4621 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 4622 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 4623 "# of tx frames in this range", 4624 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 4625 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 4626 "# of tx frames in this range", 4627 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 4628 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 4629 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 4630 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 4631 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 4632 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 4633 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 4634 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 4635 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 4636 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 4637 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 4638 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 4639 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 4640 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 4641 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 4642 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 4643 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 4644 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 4645 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 4646 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 4647 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 4648 4649 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 4650 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 4651 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 4652 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 4653 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 4654 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 4655 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 4656 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 4657 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 4658 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 4659 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 4660 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 4661 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 4662 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 4663 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 4664 "# of frames received with bad FCS", 4665 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 4666 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 4667 "# of frames received with length error", 4668 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 4669 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 4670 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 4671 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 4672 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 4673 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 4674 "# of rx frames in this range", 4675 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 4676 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 4677 "# of rx frames in this range", 4678 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 4679 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 4680 "# of rx frames in this range", 4681 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 4682 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 4683 "# of rx frames in this range", 4684 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 4685 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 4686 "# of rx frames in this range", 4687 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 4688 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 4689 "# of rx frames in this range", 4690 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 4691 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 4692 "# of rx frames in this range", 4693 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 4694 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 4695 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 4696 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 4697 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 4698 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 4699 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 4700 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 4701 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 4702 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 4703 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 4704 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 4705 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 4706 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 4707 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 4708 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 4709 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 4710 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 4711 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 4712 4713 #undef SYSCTL_ADD_T4_REG64 4714 4715 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 4716 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 4717 &pi->stats.name, desc) 4718 4719 /* We get these from port_stats and they may be stale by upto 1s */ 4720 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 4721 "# drops due to buffer-group 0 overflows"); 4722 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 4723 "# drops due to buffer-group 1 overflows"); 4724 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 4725 "# drops due to buffer-group 2 overflows"); 4726 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 4727 "# drops due to buffer-group 3 overflows"); 4728 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 4729 "# of buffer-group 0 truncated packets"); 4730 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 4731 "# of buffer-group 1 truncated packets"); 4732 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 4733 "# of buffer-group 2 truncated packets"); 4734 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 4735 "# of buffer-group 3 truncated packets"); 4736 4737 #undef SYSCTL_ADD_T4_PORTSTAT 4738 4739 return (0); 4740 } 4741 4742 static int 4743 sysctl_int_array(SYSCTL_HANDLER_ARGS) 4744 { 4745 int rc, *i; 4746 struct sbuf sb; 4747 4748 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 4749 for (i = arg1; arg2; arg2 -= sizeof(int), i++) 4750 sbuf_printf(&sb, "%d ", *i); 4751 sbuf_trim(&sb); 4752 sbuf_finish(&sb); 4753 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 4754 sbuf_delete(&sb); 4755 return (rc); 4756 } 4757 4758 static int 4759 sysctl_bitfield(SYSCTL_HANDLER_ARGS) 4760 { 4761 int rc; 4762 struct sbuf *sb; 4763 4764 rc = sysctl_wire_old_buffer(req, 0); 4765 if (rc != 0) 4766 return(rc); 4767 4768 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4769 if (sb == NULL) 4770 return (ENOMEM); 4771 4772 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 4773 rc = sbuf_finish(sb); 4774 sbuf_delete(sb); 4775 4776 return (rc); 4777 } 4778 4779 static int 4780 sysctl_btphy(SYSCTL_HANDLER_ARGS) 4781 { 4782 struct port_info *pi = arg1; 4783 int op = arg2; 4784 struct adapter *sc = pi->adapter; 4785 u_int v; 4786 int rc; 4787 4788 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4btt"); 4789 if (rc) 4790 return (rc); 4791 /* XXX: magic numbers */ 4792 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 4793 &v); 4794 end_synchronized_op(sc, 0); 4795 if (rc) 4796 return (rc); 4797 if (op == 0) 4798 v /= 256; 4799 4800 rc = sysctl_handle_int(oidp, &v, 0, req); 4801 return (rc); 4802 } 4803 4804 static int 4805 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 4806 { 4807 struct port_info *pi = arg1; 4808 struct adapter *sc = pi->adapter; 4809 int idx, rc, i; 4810 struct sge_rxq *rxq; 4811 #ifdef TCP_OFFLOAD 4812 struct sge_ofld_rxq *ofld_rxq; 4813 #endif 4814 uint8_t v; 4815 4816 idx = pi->tmr_idx; 4817 4818 rc = sysctl_handle_int(oidp, &idx, 0, req); 4819 if (rc != 0 || req->newptr == NULL) 4820 return (rc); 4821 4822 if (idx < 0 || idx >= SGE_NTIMERS) 4823 return (EINVAL); 4824 4825 rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK, 4826 "t4tmr"); 4827 if (rc) 4828 return (rc); 4829 4830 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(pi->pktc_idx != -1); 4831 for_each_rxq(pi, i, rxq) { 4832 #ifdef atomic_store_rel_8 4833 atomic_store_rel_8(&rxq->iq.intr_params, v); 4834 #else 4835 rxq->iq.intr_params = v; 4836 #endif 4837 } 4838 #ifdef TCP_OFFLOAD 4839 for_each_ofld_rxq(pi, i, ofld_rxq) { 4840 #ifdef atomic_store_rel_8 4841 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 4842 #else 4843 ofld_rxq->iq.intr_params = v; 4844 #endif 4845 } 4846 #endif 4847 pi->tmr_idx = idx; 4848 4849 end_synchronized_op(sc, LOCK_HELD); 4850 return (0); 4851 } 4852 4853 static int 4854 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 4855 { 4856 struct port_info *pi = arg1; 4857 struct adapter *sc = pi->adapter; 4858 int idx, rc; 4859 4860 idx = pi->pktc_idx; 4861 4862 rc = sysctl_handle_int(oidp, &idx, 0, req); 4863 if (rc != 0 || req->newptr == NULL) 4864 return (rc); 4865 4866 if (idx < -1 || idx >= SGE_NCOUNTERS) 4867 return (EINVAL); 4868 4869 rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK, 4870 "t4pktc"); 4871 if (rc) 4872 return (rc); 4873 4874 if (pi->flags & PORT_INIT_DONE) 4875 rc = EBUSY; /* cannot be changed once the queues are created */ 4876 else 4877 pi->pktc_idx = idx; 4878 4879 end_synchronized_op(sc, LOCK_HELD); 4880 return (rc); 4881 } 4882 4883 static int 4884 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 4885 { 4886 struct port_info *pi = arg1; 4887 struct adapter *sc = pi->adapter; 4888 int qsize, rc; 4889 4890 qsize = pi->qsize_rxq; 4891 4892 rc = sysctl_handle_int(oidp, &qsize, 0, req); 4893 if (rc != 0 || req->newptr == NULL) 4894 return (rc); 4895 4896 if (qsize < 128 || (qsize & 7)) 4897 return (EINVAL); 4898 4899 rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK, 4900 "t4rxqs"); 4901 if (rc) 4902 return (rc); 4903 4904 if (pi->flags & PORT_INIT_DONE) 4905 rc = EBUSY; /* cannot be changed once the queues are created */ 4906 else 4907 pi->qsize_rxq = qsize; 4908 4909 end_synchronized_op(sc, LOCK_HELD); 4910 return (rc); 4911 } 4912 4913 static int 4914 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 4915 { 4916 struct port_info *pi = arg1; 4917 struct adapter *sc = pi->adapter; 4918 int qsize, rc; 4919 4920 qsize = pi->qsize_txq; 4921 4922 rc = sysctl_handle_int(oidp, &qsize, 0, req); 4923 if (rc != 0 || req->newptr == NULL) 4924 return (rc); 4925 4926 /* bufring size must be powerof2 */ 4927 if (qsize < 128 || !powerof2(qsize)) 4928 return (EINVAL); 4929 4930 rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK, 4931 "t4txqs"); 4932 if (rc) 4933 return (rc); 4934 4935 if (pi->flags & PORT_INIT_DONE) 4936 rc = EBUSY; /* cannot be changed once the queues are created */ 4937 else 4938 pi->qsize_txq = qsize; 4939 4940 end_synchronized_op(sc, LOCK_HELD); 4941 return (rc); 4942 } 4943 4944 static int 4945 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 4946 { 4947 struct adapter *sc = arg1; 4948 int reg = arg2; 4949 uint64_t val; 4950 4951 val = t4_read_reg64(sc, reg); 4952 4953 return (sysctl_handle_64(oidp, &val, 0, req)); 4954 } 4955 4956 static int 4957 sysctl_temperature(SYSCTL_HANDLER_ARGS) 4958 { 4959 struct adapter *sc = arg1; 4960 int rc, t; 4961 uint32_t param, val; 4962 4963 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 4964 if (rc) 4965 return (rc); 4966 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 4967 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 4968 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 4969 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4970 end_synchronized_op(sc, 0); 4971 if (rc) 4972 return (rc); 4973 4974 /* unknown is returned as 0 but we display -1 in that case */ 4975 t = val == 0 ? -1 : val; 4976 4977 rc = sysctl_handle_int(oidp, &t, 0, req); 4978 return (rc); 4979 } 4980 4981 #ifdef SBUF_DRAIN 4982 static int 4983 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 4984 { 4985 struct adapter *sc = arg1; 4986 struct sbuf *sb; 4987 int rc, i; 4988 uint16_t incr[NMTUS][NCCTRL_WIN]; 4989 static const char *dec_fac[] = { 4990 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 4991 "0.9375" 4992 }; 4993 4994 rc = sysctl_wire_old_buffer(req, 0); 4995 if (rc != 0) 4996 return (rc); 4997 4998 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 4999 if (sb == NULL) 5000 return (ENOMEM); 5001 5002 t4_read_cong_tbl(sc, incr); 5003 5004 for (i = 0; i < NCCTRL_WIN; ++i) { 5005 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 5006 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 5007 incr[5][i], incr[6][i], incr[7][i]); 5008 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 5009 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 5010 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 5011 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 5012 } 5013 5014 rc = sbuf_finish(sb); 5015 sbuf_delete(sb); 5016 5017 return (rc); 5018 } 5019 5020 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 5021 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 5022 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 5023 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 5024 }; 5025 5026 static int 5027 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 5028 { 5029 struct adapter *sc = arg1; 5030 struct sbuf *sb; 5031 int rc, i, n, qid = arg2; 5032 uint32_t *buf, *p; 5033 char *qtype; 5034 u_int cim_num_obq = is_t4(sc) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 5035 5036 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 5037 ("%s: bad qid %d\n", __func__, qid)); 5038 5039 if (qid < CIM_NUM_IBQ) { 5040 /* inbound queue */ 5041 qtype = "IBQ"; 5042 n = 4 * CIM_IBQ_SIZE; 5043 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5044 rc = t4_read_cim_ibq(sc, qid, buf, n); 5045 } else { 5046 /* outbound queue */ 5047 qtype = "OBQ"; 5048 qid -= CIM_NUM_IBQ; 5049 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 5050 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5051 rc = t4_read_cim_obq(sc, qid, buf, n); 5052 } 5053 5054 if (rc < 0) { 5055 rc = -rc; 5056 goto done; 5057 } 5058 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 5059 5060 rc = sysctl_wire_old_buffer(req, 0); 5061 if (rc != 0) 5062 goto done; 5063 5064 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 5065 if (sb == NULL) { 5066 rc = ENOMEM; 5067 goto done; 5068 } 5069 5070 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 5071 for (i = 0, p = buf; i < n; i += 16, p += 4) 5072 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 5073 p[2], p[3]); 5074 5075 rc = sbuf_finish(sb); 5076 sbuf_delete(sb); 5077 done: 5078 free(buf, M_CXGBE); 5079 return (rc); 5080 } 5081 5082 static int 5083 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 5084 { 5085 struct adapter *sc = arg1; 5086 u_int cfg; 5087 struct sbuf *sb; 5088 uint32_t *buf, *p; 5089 int rc; 5090 5091 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 5092 if (rc != 0) 5093 return (rc); 5094 5095 rc = sysctl_wire_old_buffer(req, 0); 5096 if (rc != 0) 5097 return (rc); 5098 5099 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5100 if (sb == NULL) 5101 return (ENOMEM); 5102 5103 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 5104 M_ZERO | M_WAITOK); 5105 5106 rc = -t4_cim_read_la(sc, buf, NULL); 5107 if (rc != 0) 5108 goto done; 5109 5110 sbuf_printf(sb, "Status Data PC%s", 5111 cfg & F_UPDBGLACAPTPCONLY ? "" : 5112 " LS0Stat LS0Addr LS0Data"); 5113 5114 KASSERT((sc->params.cim_la_size & 7) == 0, 5115 ("%s: p will walk off the end of buf", __func__)); 5116 5117 for (p = buf; p < &buf[sc->params.cim_la_size]; p += 8) { 5118 if (cfg & F_UPDBGLACAPTPCONLY) { 5119 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 5120 p[6], p[7]); 5121 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 5122 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 5123 p[4] & 0xff, p[5] >> 8); 5124 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 5125 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 5126 p[1] & 0xf, p[2] >> 4); 5127 } else { 5128 sbuf_printf(sb, 5129 "\n %02x %x%07x %x%07x %08x %08x " 5130 "%08x%08x%08x%08x", 5131 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 5132 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 5133 p[6], p[7]); 5134 } 5135 } 5136 5137 rc = sbuf_finish(sb); 5138 sbuf_delete(sb); 5139 done: 5140 free(buf, M_CXGBE); 5141 return (rc); 5142 } 5143 5144 static int 5145 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 5146 { 5147 struct adapter *sc = arg1; 5148 u_int i; 5149 struct sbuf *sb; 5150 uint32_t *buf, *p; 5151 int rc; 5152 5153 rc = sysctl_wire_old_buffer(req, 0); 5154 if (rc != 0) 5155 return (rc); 5156 5157 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5158 if (sb == NULL) 5159 return (ENOMEM); 5160 5161 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 5162 M_ZERO | M_WAITOK); 5163 5164 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 5165 p = buf; 5166 5167 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 5168 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 5169 p[1], p[0]); 5170 } 5171 5172 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 5173 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 5174 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 5175 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 5176 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 5177 (p[1] >> 2) | ((p[2] & 3) << 30), 5178 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 5179 p[0] & 1); 5180 } 5181 5182 rc = sbuf_finish(sb); 5183 sbuf_delete(sb); 5184 free(buf, M_CXGBE); 5185 return (rc); 5186 } 5187 5188 static int 5189 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 5190 { 5191 struct adapter *sc = arg1; 5192 u_int i; 5193 struct sbuf *sb; 5194 uint32_t *buf, *p; 5195 int rc; 5196 5197 rc = sysctl_wire_old_buffer(req, 0); 5198 if (rc != 0) 5199 return (rc); 5200 5201 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5202 if (sb == NULL) 5203 return (ENOMEM); 5204 5205 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 5206 M_ZERO | M_WAITOK); 5207 5208 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 5209 p = buf; 5210 5211 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 5212 for (i = 0; i < CIM_MALA_SIZE; i++, p += 6) { 5213 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 5214 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 5215 p[4], p[3], p[2], p[1], p[0]); 5216 } 5217 5218 sbuf_printf(sb, "\n\nCntl ID Data"); 5219 for (i = 0; i < CIM_MALA_SIZE; i++, p += 6) { 5220 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 5221 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 5222 } 5223 5224 rc = sbuf_finish(sb); 5225 sbuf_delete(sb); 5226 free(buf, M_CXGBE); 5227 return (rc); 5228 } 5229 5230 static int 5231 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 5232 { 5233 struct adapter *sc = arg1; 5234 struct sbuf *sb; 5235 int rc, i; 5236 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 5237 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 5238 uint16_t thres[CIM_NUM_IBQ]; 5239 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 5240 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 5241 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 5242 5243 if (is_t4(sc)) { 5244 cim_num_obq = CIM_NUM_OBQ; 5245 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 5246 obq_rdaddr = A_UP_OBQ_0_REALADDR; 5247 } else { 5248 cim_num_obq = CIM_NUM_OBQ_T5; 5249 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 5250 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 5251 } 5252 nq = CIM_NUM_IBQ + cim_num_obq; 5253 5254 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 5255 if (rc == 0) 5256 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 5257 if (rc != 0) 5258 return (rc); 5259 5260 t4_read_cimq_cfg(sc, base, size, thres); 5261 5262 rc = sysctl_wire_old_buffer(req, 0); 5263 if (rc != 0) 5264 return (rc); 5265 5266 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 5267 if (sb == NULL) 5268 return (ENOMEM); 5269 5270 sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 5271 5272 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 5273 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 5274 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 5275 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 5276 G_QUEREMFLITS(p[2]) * 16); 5277 for ( ; i < nq; i++, p += 4, wr += 2) 5278 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 5279 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 5280 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 5281 G_QUEREMFLITS(p[2]) * 16); 5282 5283 rc = sbuf_finish(sb); 5284 sbuf_delete(sb); 5285 5286 return (rc); 5287 } 5288 5289 static int 5290 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 5291 { 5292 struct adapter *sc = arg1; 5293 struct sbuf *sb; 5294 int rc; 5295 struct tp_cpl_stats stats; 5296 5297 rc = sysctl_wire_old_buffer(req, 0); 5298 if (rc != 0) 5299 return (rc); 5300 5301 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 5302 if (sb == NULL) 5303 return (ENOMEM); 5304 5305 t4_tp_get_cpl_stats(sc, &stats); 5306 5307 sbuf_printf(sb, " channel 0 channel 1 channel 2 " 5308 "channel 3\n"); 5309 sbuf_printf(sb, "CPL requests: %10u %10u %10u %10u\n", 5310 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 5311 sbuf_printf(sb, "CPL responses: %10u %10u %10u %10u", 5312 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 5313 5314 rc = sbuf_finish(sb); 5315 sbuf_delete(sb); 5316 5317 return (rc); 5318 } 5319 5320 static int 5321 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 5322 { 5323 struct adapter *sc = arg1; 5324 struct sbuf *sb; 5325 int rc; 5326 struct tp_usm_stats stats; 5327 5328 rc = sysctl_wire_old_buffer(req, 0); 5329 if (rc != 0) 5330 return(rc); 5331 5332 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 5333 if (sb == NULL) 5334 return (ENOMEM); 5335 5336 t4_get_usm_stats(sc, &stats); 5337 5338 sbuf_printf(sb, "Frames: %u\n", stats.frames); 5339 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 5340 sbuf_printf(sb, "Drops: %u", stats.drops); 5341 5342 rc = sbuf_finish(sb); 5343 sbuf_delete(sb); 5344 5345 return (rc); 5346 } 5347 5348 const char *devlog_level_strings[] = { 5349 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 5350 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 5351 [FW_DEVLOG_LEVEL_ERR] = "ERR", 5352 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 5353 [FW_DEVLOG_LEVEL_INFO] = "INFO", 5354 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 5355 }; 5356 5357 const char *devlog_facility_strings[] = { 5358 [FW_DEVLOG_FACILITY_CORE] = "CORE", 5359 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 5360 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 5361 [FW_DEVLOG_FACILITY_RES] = "RES", 5362 [FW_DEVLOG_FACILITY_HW] = "HW", 5363 [FW_DEVLOG_FACILITY_FLR] = "FLR", 5364 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 5365 [FW_DEVLOG_FACILITY_PHY] = "PHY", 5366 [FW_DEVLOG_FACILITY_MAC] = "MAC", 5367 [FW_DEVLOG_FACILITY_PORT] = "PORT", 5368 [FW_DEVLOG_FACILITY_VI] = "VI", 5369 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 5370 [FW_DEVLOG_FACILITY_ACL] = "ACL", 5371 [FW_DEVLOG_FACILITY_TM] = "TM", 5372 [FW_DEVLOG_FACILITY_QFC] = "QFC", 5373 [FW_DEVLOG_FACILITY_DCB] = "DCB", 5374 [FW_DEVLOG_FACILITY_ETH] = "ETH", 5375 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 5376 [FW_DEVLOG_FACILITY_RI] = "RI", 5377 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 5378 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 5379 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 5380 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE" 5381 }; 5382 5383 static int 5384 sysctl_devlog(SYSCTL_HANDLER_ARGS) 5385 { 5386 struct adapter *sc = arg1; 5387 struct devlog_params *dparams = &sc->params.devlog; 5388 struct fw_devlog_e *buf, *e; 5389 int i, j, rc, nentries, first = 0, m; 5390 struct sbuf *sb; 5391 uint64_t ftstamp = UINT64_MAX; 5392 5393 if (dparams->start == 0) { 5394 dparams->memtype = FW_MEMTYPE_EDC0; 5395 dparams->start = 0x84000; 5396 dparams->size = 32768; 5397 } 5398 5399 nentries = dparams->size / sizeof(struct fw_devlog_e); 5400 5401 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 5402 if (buf == NULL) 5403 return (ENOMEM); 5404 5405 m = fwmtype_to_hwmtype(dparams->memtype); 5406 rc = -t4_mem_read(sc, m, dparams->start, dparams->size, (void *)buf); 5407 if (rc != 0) 5408 goto done; 5409 5410 for (i = 0; i < nentries; i++) { 5411 e = &buf[i]; 5412 5413 if (e->timestamp == 0) 5414 break; /* end */ 5415 5416 e->timestamp = be64toh(e->timestamp); 5417 e->seqno = be32toh(e->seqno); 5418 for (j = 0; j < 8; j++) 5419 e->params[j] = be32toh(e->params[j]); 5420 5421 if (e->timestamp < ftstamp) { 5422 ftstamp = e->timestamp; 5423 first = i; 5424 } 5425 } 5426 5427 if (buf[first].timestamp == 0) 5428 goto done; /* nothing in the log */ 5429 5430 rc = sysctl_wire_old_buffer(req, 0); 5431 if (rc != 0) 5432 goto done; 5433 5434 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5435 if (sb == NULL) { 5436 rc = ENOMEM; 5437 goto done; 5438 } 5439 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 5440 "Seq#", "Tstamp", "Level", "Facility", "Message"); 5441 5442 i = first; 5443 do { 5444 e = &buf[i]; 5445 if (e->timestamp == 0) 5446 break; /* end */ 5447 5448 sbuf_printf(sb, "%10d %15ju %8s %8s ", 5449 e->seqno, e->timestamp, 5450 (e->level < nitems(devlog_level_strings) ? 5451 devlog_level_strings[e->level] : "UNKNOWN"), 5452 (e->facility < nitems(devlog_facility_strings) ? 5453 devlog_facility_strings[e->facility] : "UNKNOWN")); 5454 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 5455 e->params[2], e->params[3], e->params[4], 5456 e->params[5], e->params[6], e->params[7]); 5457 5458 if (++i == nentries) 5459 i = 0; 5460 } while (i != first); 5461 5462 rc = sbuf_finish(sb); 5463 sbuf_delete(sb); 5464 done: 5465 free(buf, M_CXGBE); 5466 return (rc); 5467 } 5468 5469 static int 5470 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 5471 { 5472 struct adapter *sc = arg1; 5473 struct sbuf *sb; 5474 int rc; 5475 struct tp_fcoe_stats stats[4]; 5476 5477 rc = sysctl_wire_old_buffer(req, 0); 5478 if (rc != 0) 5479 return (rc); 5480 5481 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 5482 if (sb == NULL) 5483 return (ENOMEM); 5484 5485 t4_get_fcoe_stats(sc, 0, &stats[0]); 5486 t4_get_fcoe_stats(sc, 1, &stats[1]); 5487 t4_get_fcoe_stats(sc, 2, &stats[2]); 5488 t4_get_fcoe_stats(sc, 3, &stats[3]); 5489 5490 sbuf_printf(sb, " channel 0 channel 1 " 5491 "channel 2 channel 3\n"); 5492 sbuf_printf(sb, "octetsDDP: %16ju %16ju %16ju %16ju\n", 5493 stats[0].octetsDDP, stats[1].octetsDDP, stats[2].octetsDDP, 5494 stats[3].octetsDDP); 5495 sbuf_printf(sb, "framesDDP: %16u %16u %16u %16u\n", stats[0].framesDDP, 5496 stats[1].framesDDP, stats[2].framesDDP, stats[3].framesDDP); 5497 sbuf_printf(sb, "framesDrop: %16u %16u %16u %16u", 5498 stats[0].framesDrop, stats[1].framesDrop, stats[2].framesDrop, 5499 stats[3].framesDrop); 5500 5501 rc = sbuf_finish(sb); 5502 sbuf_delete(sb); 5503 5504 return (rc); 5505 } 5506 5507 static int 5508 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 5509 { 5510 struct adapter *sc = arg1; 5511 struct sbuf *sb; 5512 int rc, i; 5513 unsigned int map, kbps, ipg, mode; 5514 unsigned int pace_tab[NTX_SCHED]; 5515 5516 rc = sysctl_wire_old_buffer(req, 0); 5517 if (rc != 0) 5518 return (rc); 5519 5520 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 5521 if (sb == NULL) 5522 return (ENOMEM); 5523 5524 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 5525 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 5526 t4_read_pace_tbl(sc, pace_tab); 5527 5528 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 5529 "Class IPG (0.1 ns) Flow IPG (us)"); 5530 5531 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 5532 t4_get_tx_sched(sc, i, &kbps, &ipg); 5533 sbuf_printf(sb, "\n %u %-5s %u ", i, 5534 (mode & (1 << i)) ? "flow" : "class", map & 3); 5535 if (kbps) 5536 sbuf_printf(sb, "%9u ", kbps); 5537 else 5538 sbuf_printf(sb, " disabled "); 5539 5540 if (ipg) 5541 sbuf_printf(sb, "%13u ", ipg); 5542 else 5543 sbuf_printf(sb, " disabled "); 5544 5545 if (pace_tab[i]) 5546 sbuf_printf(sb, "%10u", pace_tab[i]); 5547 else 5548 sbuf_printf(sb, " disabled"); 5549 } 5550 5551 rc = sbuf_finish(sb); 5552 sbuf_delete(sb); 5553 5554 return (rc); 5555 } 5556 5557 static int 5558 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 5559 { 5560 struct adapter *sc = arg1; 5561 struct sbuf *sb; 5562 int rc, i, j; 5563 uint64_t *p0, *p1; 5564 struct lb_port_stats s[2]; 5565 static const char *stat_name[] = { 5566 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 5567 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 5568 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 5569 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 5570 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 5571 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 5572 "BG2FramesTrunc:", "BG3FramesTrunc:" 5573 }; 5574 5575 rc = sysctl_wire_old_buffer(req, 0); 5576 if (rc != 0) 5577 return (rc); 5578 5579 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5580 if (sb == NULL) 5581 return (ENOMEM); 5582 5583 memset(s, 0, sizeof(s)); 5584 5585 for (i = 0; i < 4; i += 2) { 5586 t4_get_lb_stats(sc, i, &s[0]); 5587 t4_get_lb_stats(sc, i + 1, &s[1]); 5588 5589 p0 = &s[0].octets; 5590 p1 = &s[1].octets; 5591 sbuf_printf(sb, "%s Loopback %u" 5592 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 5593 5594 for (j = 0; j < nitems(stat_name); j++) 5595 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 5596 *p0++, *p1++); 5597 } 5598 5599 rc = sbuf_finish(sb); 5600 sbuf_delete(sb); 5601 5602 return (rc); 5603 } 5604 5605 static int 5606 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 5607 { 5608 int rc = 0; 5609 struct port_info *pi = arg1; 5610 struct sbuf *sb; 5611 static const char *linkdnreasons[] = { 5612 "non-specific", "remote fault", "autoneg failed", "reserved3", 5613 "PHY overheated", "unknown", "rx los", "reserved7" 5614 }; 5615 5616 rc = sysctl_wire_old_buffer(req, 0); 5617 if (rc != 0) 5618 return(rc); 5619 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 5620 if (sb == NULL) 5621 return (ENOMEM); 5622 5623 if (pi->linkdnrc < 0) 5624 sbuf_printf(sb, "n/a"); 5625 else if (pi->linkdnrc < nitems(linkdnreasons)) 5626 sbuf_printf(sb, "%s", linkdnreasons[pi->linkdnrc]); 5627 else 5628 sbuf_printf(sb, "%d", pi->linkdnrc); 5629 5630 rc = sbuf_finish(sb); 5631 sbuf_delete(sb); 5632 5633 return (rc); 5634 } 5635 5636 struct mem_desc { 5637 unsigned int base; 5638 unsigned int limit; 5639 unsigned int idx; 5640 }; 5641 5642 static int 5643 mem_desc_cmp(const void *a, const void *b) 5644 { 5645 return ((const struct mem_desc *)a)->base - 5646 ((const struct mem_desc *)b)->base; 5647 } 5648 5649 static void 5650 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 5651 unsigned int to) 5652 { 5653 unsigned int size; 5654 5655 size = to - from + 1; 5656 if (size == 0) 5657 return; 5658 5659 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 5660 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 5661 } 5662 5663 static int 5664 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 5665 { 5666 struct adapter *sc = arg1; 5667 struct sbuf *sb; 5668 int rc, i, n; 5669 uint32_t lo, hi, used, alloc; 5670 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 5671 static const char *region[] = { 5672 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 5673 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 5674 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 5675 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 5676 "RQUDP region:", "PBL region:", "TXPBL region:", 5677 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 5678 "On-chip queues:" 5679 }; 5680 struct mem_desc avail[4]; 5681 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 5682 struct mem_desc *md = mem; 5683 5684 rc = sysctl_wire_old_buffer(req, 0); 5685 if (rc != 0) 5686 return (rc); 5687 5688 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5689 if (sb == NULL) 5690 return (ENOMEM); 5691 5692 for (i = 0; i < nitems(mem); i++) { 5693 mem[i].limit = 0; 5694 mem[i].idx = i; 5695 } 5696 5697 /* Find and sort the populated memory ranges */ 5698 i = 0; 5699 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 5700 if (lo & F_EDRAM0_ENABLE) { 5701 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 5702 avail[i].base = G_EDRAM0_BASE(hi) << 20; 5703 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 5704 avail[i].idx = 0; 5705 i++; 5706 } 5707 if (lo & F_EDRAM1_ENABLE) { 5708 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 5709 avail[i].base = G_EDRAM1_BASE(hi) << 20; 5710 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 5711 avail[i].idx = 1; 5712 i++; 5713 } 5714 if (lo & F_EXT_MEM_ENABLE) { 5715 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 5716 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 5717 avail[i].limit = avail[i].base + 5718 (G_EXT_MEM_SIZE(hi) << 20); 5719 avail[i].idx = is_t4(sc) ? 2 : 3; /* Call it MC for T4 */ 5720 i++; 5721 } 5722 if (!is_t4(sc) && lo & F_EXT_MEM1_ENABLE) { 5723 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 5724 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 5725 avail[i].limit = avail[i].base + 5726 (G_EXT_MEM1_SIZE(hi) << 20); 5727 avail[i].idx = 4; 5728 i++; 5729 } 5730 if (!i) /* no memory available */ 5731 return 0; 5732 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 5733 5734 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 5735 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 5736 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 5737 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 5738 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 5739 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 5740 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 5741 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 5742 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 5743 5744 /* the next few have explicit upper bounds */ 5745 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 5746 md->limit = md->base - 1 + 5747 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 5748 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 5749 md++; 5750 5751 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 5752 md->limit = md->base - 1 + 5753 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 5754 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 5755 md++; 5756 5757 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 5758 hi = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 5759 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 5760 md->limit = (sc->tids.ntids - hi) * 16 + md->base - 1; 5761 } else { 5762 md->base = 0; 5763 md->idx = nitems(region); /* hide it */ 5764 } 5765 md++; 5766 5767 #define ulp_region(reg) \ 5768 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 5769 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 5770 5771 ulp_region(RX_ISCSI); 5772 ulp_region(RX_TDDP); 5773 ulp_region(TX_TPT); 5774 ulp_region(RX_STAG); 5775 ulp_region(RX_RQ); 5776 ulp_region(RX_RQUDP); 5777 ulp_region(RX_PBL); 5778 ulp_region(TX_PBL); 5779 #undef ulp_region 5780 5781 md->base = 0; 5782 md->idx = nitems(region); 5783 if (!is_t4(sc) && t4_read_reg(sc, A_SGE_CONTROL2) & F_VFIFO_ENABLE) { 5784 md->base = G_BASEADDR(t4_read_reg(sc, A_SGE_DBVFIFO_BADDR)); 5785 md->limit = md->base + (G_DBVFIFO_SIZE((t4_read_reg(sc, 5786 A_SGE_DBVFIFO_SIZE))) << 2) - 1; 5787 } 5788 md++; 5789 5790 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 5791 md->limit = md->base + sc->tids.ntids - 1; 5792 md++; 5793 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 5794 md->limit = md->base + sc->tids.ntids - 1; 5795 md++; 5796 5797 md->base = sc->vres.ocq.start; 5798 if (sc->vres.ocq.size) 5799 md->limit = md->base + sc->vres.ocq.size - 1; 5800 else 5801 md->idx = nitems(region); /* hide it */ 5802 md++; 5803 5804 /* add any address-space holes, there can be up to 3 */ 5805 for (n = 0; n < i - 1; n++) 5806 if (avail[n].limit < avail[n + 1].base) 5807 (md++)->base = avail[n].limit; 5808 if (avail[n].limit) 5809 (md++)->base = avail[n].limit; 5810 5811 n = md - mem; 5812 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 5813 5814 for (lo = 0; lo < i; lo++) 5815 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 5816 avail[lo].limit - 1); 5817 5818 sbuf_printf(sb, "\n"); 5819 for (i = 0; i < n; i++) { 5820 if (mem[i].idx >= nitems(region)) 5821 continue; /* skip holes */ 5822 if (!mem[i].limit) 5823 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 5824 mem_region_show(sb, region[mem[i].idx], mem[i].base, 5825 mem[i].limit); 5826 } 5827 5828 sbuf_printf(sb, "\n"); 5829 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 5830 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 5831 mem_region_show(sb, "uP RAM:", lo, hi); 5832 5833 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 5834 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 5835 mem_region_show(sb, "uP Extmem2:", lo, hi); 5836 5837 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 5838 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 5839 G_PMRXMAXPAGE(lo), 5840 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 5841 (lo & F_PMRXNUMCHN) ? 2 : 1); 5842 5843 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 5844 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 5845 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 5846 G_PMTXMAXPAGE(lo), 5847 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 5848 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 5849 sbuf_printf(sb, "%u p-structs\n", 5850 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 5851 5852 for (i = 0; i < 4; i++) { 5853 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 5854 if (is_t4(sc)) { 5855 used = G_USED(lo); 5856 alloc = G_ALLOC(lo); 5857 } else { 5858 used = G_T5_USED(lo); 5859 alloc = G_T5_ALLOC(lo); 5860 } 5861 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 5862 i, used, alloc); 5863 } 5864 for (i = 0; i < 4; i++) { 5865 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 5866 if (is_t4(sc)) { 5867 used = G_USED(lo); 5868 alloc = G_ALLOC(lo); 5869 } else { 5870 used = G_T5_USED(lo); 5871 alloc = G_T5_ALLOC(lo); 5872 } 5873 sbuf_printf(sb, 5874 "\nLoopback %d using %u pages out of %u allocated", 5875 i, used, alloc); 5876 } 5877 5878 rc = sbuf_finish(sb); 5879 sbuf_delete(sb); 5880 5881 return (rc); 5882 } 5883 5884 static inline void 5885 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 5886 { 5887 *mask = x | y; 5888 y = htobe64(y); 5889 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 5890 } 5891 5892 static int 5893 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 5894 { 5895 struct adapter *sc = arg1; 5896 struct sbuf *sb; 5897 int rc, i, n; 5898 5899 rc = sysctl_wire_old_buffer(req, 0); 5900 if (rc != 0) 5901 return (rc); 5902 5903 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5904 if (sb == NULL) 5905 return (ENOMEM); 5906 5907 sbuf_printf(sb, 5908 "Idx Ethernet address Mask Vld Ports PF" 5909 " VF Replication P0 P1 P2 P3 ML"); 5910 n = is_t4(sc) ? NUM_MPS_CLS_SRAM_L_INSTANCES : 5911 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 5912 for (i = 0; i < n; i++) { 5913 uint64_t tcamx, tcamy, mask; 5914 uint32_t cls_lo, cls_hi; 5915 uint8_t addr[ETHER_ADDR_LEN]; 5916 5917 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 5918 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 5919 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 5920 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 5921 5922 if (tcamx & tcamy) 5923 continue; 5924 5925 tcamxy2valmask(tcamx, tcamy, addr, &mask); 5926 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 5927 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 5928 addr[3], addr[4], addr[5], (uintmax_t)mask, 5929 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 5930 G_PORTMAP(cls_hi), G_PF(cls_lo), 5931 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 5932 5933 if (cls_lo & F_REPLICATE) { 5934 struct fw_ldst_cmd ldst_cmd; 5935 5936 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 5937 ldst_cmd.op_to_addrspace = 5938 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 5939 F_FW_CMD_REQUEST | F_FW_CMD_READ | 5940 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 5941 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 5942 ldst_cmd.u.mps.fid_ctl = 5943 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 5944 V_FW_LDST_CMD_CTL(i)); 5945 5946 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 5947 "t4mps"); 5948 if (rc) 5949 break; 5950 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 5951 sizeof(ldst_cmd), &ldst_cmd); 5952 end_synchronized_op(sc, 0); 5953 5954 if (rc != 0) { 5955 sbuf_printf(sb, 5956 " ------------ error %3u ------------", rc); 5957 rc = 0; 5958 } else { 5959 sbuf_printf(sb, " %08x %08x %08x %08x", 5960 be32toh(ldst_cmd.u.mps.rplc127_96), 5961 be32toh(ldst_cmd.u.mps.rplc95_64), 5962 be32toh(ldst_cmd.u.mps.rplc63_32), 5963 be32toh(ldst_cmd.u.mps.rplc31_0)); 5964 } 5965 } else 5966 sbuf_printf(sb, "%36s", ""); 5967 5968 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 5969 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 5970 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 5971 } 5972 5973 if (rc) 5974 (void) sbuf_finish(sb); 5975 else 5976 rc = sbuf_finish(sb); 5977 sbuf_delete(sb); 5978 5979 return (rc); 5980 } 5981 5982 static int 5983 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 5984 { 5985 struct adapter *sc = arg1; 5986 struct sbuf *sb; 5987 int rc; 5988 uint16_t mtus[NMTUS]; 5989 5990 rc = sysctl_wire_old_buffer(req, 0); 5991 if (rc != 0) 5992 return (rc); 5993 5994 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 5995 if (sb == NULL) 5996 return (ENOMEM); 5997 5998 t4_read_mtu_tbl(sc, mtus, NULL); 5999 6000 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 6001 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 6002 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 6003 mtus[14], mtus[15]); 6004 6005 rc = sbuf_finish(sb); 6006 sbuf_delete(sb); 6007 6008 return (rc); 6009 } 6010 6011 static int 6012 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 6013 { 6014 struct adapter *sc = arg1; 6015 struct sbuf *sb; 6016 int rc, i; 6017 uint32_t cnt[PM_NSTATS]; 6018 uint64_t cyc[PM_NSTATS]; 6019 static const char *rx_stats[] = { 6020 "Read:", "Write bypass:", "Write mem:", "Flush:" 6021 }; 6022 static const char *tx_stats[] = { 6023 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:" 6024 }; 6025 6026 rc = sysctl_wire_old_buffer(req, 0); 6027 if (rc != 0) 6028 return (rc); 6029 6030 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6031 if (sb == NULL) 6032 return (ENOMEM); 6033 6034 t4_pmtx_get_stats(sc, cnt, cyc); 6035 sbuf_printf(sb, " Tx pcmds Tx bytes"); 6036 for (i = 0; i < ARRAY_SIZE(tx_stats); i++) 6037 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], cnt[i], 6038 cyc[i]); 6039 6040 t4_pmrx_get_stats(sc, cnt, cyc); 6041 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 6042 for (i = 0; i < ARRAY_SIZE(rx_stats); i++) 6043 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], cnt[i], 6044 cyc[i]); 6045 6046 rc = sbuf_finish(sb); 6047 sbuf_delete(sb); 6048 6049 return (rc); 6050 } 6051 6052 static int 6053 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 6054 { 6055 struct adapter *sc = arg1; 6056 struct sbuf *sb; 6057 int rc; 6058 struct tp_rdma_stats stats; 6059 6060 rc = sysctl_wire_old_buffer(req, 0); 6061 if (rc != 0) 6062 return (rc); 6063 6064 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6065 if (sb == NULL) 6066 return (ENOMEM); 6067 6068 t4_tp_get_rdma_stats(sc, &stats); 6069 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 6070 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 6071 6072 rc = sbuf_finish(sb); 6073 sbuf_delete(sb); 6074 6075 return (rc); 6076 } 6077 6078 static int 6079 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 6080 { 6081 struct adapter *sc = arg1; 6082 struct sbuf *sb; 6083 int rc; 6084 struct tp_tcp_stats v4, v6; 6085 6086 rc = sysctl_wire_old_buffer(req, 0); 6087 if (rc != 0) 6088 return (rc); 6089 6090 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6091 if (sb == NULL) 6092 return (ENOMEM); 6093 6094 t4_tp_get_tcp_stats(sc, &v4, &v6); 6095 sbuf_printf(sb, 6096 " IP IPv6\n"); 6097 sbuf_printf(sb, "OutRsts: %20u %20u\n", 6098 v4.tcpOutRsts, v6.tcpOutRsts); 6099 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 6100 v4.tcpInSegs, v6.tcpInSegs); 6101 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 6102 v4.tcpOutSegs, v6.tcpOutSegs); 6103 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 6104 v4.tcpRetransSegs, v6.tcpRetransSegs); 6105 6106 rc = sbuf_finish(sb); 6107 sbuf_delete(sb); 6108 6109 return (rc); 6110 } 6111 6112 static int 6113 sysctl_tids(SYSCTL_HANDLER_ARGS) 6114 { 6115 struct adapter *sc = arg1; 6116 struct sbuf *sb; 6117 int rc; 6118 struct tid_info *t = &sc->tids; 6119 6120 rc = sysctl_wire_old_buffer(req, 0); 6121 if (rc != 0) 6122 return (rc); 6123 6124 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6125 if (sb == NULL) 6126 return (ENOMEM); 6127 6128 if (t->natids) { 6129 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 6130 t->atids_in_use); 6131 } 6132 6133 if (t->ntids) { 6134 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 6135 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 6136 6137 if (b) { 6138 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1, 6139 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4, 6140 t->ntids - 1); 6141 } else { 6142 sbuf_printf(sb, "TID range: %u-%u", 6143 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4, 6144 t->ntids - 1); 6145 } 6146 } else 6147 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1); 6148 sbuf_printf(sb, ", in use: %u\n", 6149 atomic_load_acq_int(&t->tids_in_use)); 6150 } 6151 6152 if (t->nstids) { 6153 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 6154 t->stid_base + t->nstids - 1, t->stids_in_use); 6155 } 6156 6157 if (t->nftids) { 6158 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 6159 t->ftid_base + t->nftids - 1); 6160 } 6161 6162 if (t->netids) { 6163 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 6164 t->etid_base + t->netids - 1); 6165 } 6166 6167 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 6168 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 6169 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 6170 6171 rc = sbuf_finish(sb); 6172 sbuf_delete(sb); 6173 6174 return (rc); 6175 } 6176 6177 static int 6178 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 6179 { 6180 struct adapter *sc = arg1; 6181 struct sbuf *sb; 6182 int rc; 6183 struct tp_err_stats stats; 6184 6185 rc = sysctl_wire_old_buffer(req, 0); 6186 if (rc != 0) 6187 return (rc); 6188 6189 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6190 if (sb == NULL) 6191 return (ENOMEM); 6192 6193 t4_tp_get_err_stats(sc, &stats); 6194 6195 sbuf_printf(sb, " channel 0 channel 1 channel 2 " 6196 "channel 3\n"); 6197 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 6198 stats.macInErrs[0], stats.macInErrs[1], stats.macInErrs[2], 6199 stats.macInErrs[3]); 6200 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 6201 stats.hdrInErrs[0], stats.hdrInErrs[1], stats.hdrInErrs[2], 6202 stats.hdrInErrs[3]); 6203 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 6204 stats.tcpInErrs[0], stats.tcpInErrs[1], stats.tcpInErrs[2], 6205 stats.tcpInErrs[3]); 6206 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 6207 stats.tcp6InErrs[0], stats.tcp6InErrs[1], stats.tcp6InErrs[2], 6208 stats.tcp6InErrs[3]); 6209 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 6210 stats.tnlCongDrops[0], stats.tnlCongDrops[1], stats.tnlCongDrops[2], 6211 stats.tnlCongDrops[3]); 6212 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 6213 stats.tnlTxDrops[0], stats.tnlTxDrops[1], stats.tnlTxDrops[2], 6214 stats.tnlTxDrops[3]); 6215 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 6216 stats.ofldVlanDrops[0], stats.ofldVlanDrops[1], 6217 stats.ofldVlanDrops[2], stats.ofldVlanDrops[3]); 6218 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 6219 stats.ofldChanDrops[0], stats.ofldChanDrops[1], 6220 stats.ofldChanDrops[2], stats.ofldChanDrops[3]); 6221 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 6222 stats.ofldNoNeigh, stats.ofldCongDefer); 6223 6224 rc = sbuf_finish(sb); 6225 sbuf_delete(sb); 6226 6227 return (rc); 6228 } 6229 6230 struct field_desc { 6231 const char *name; 6232 u_int start; 6233 u_int width; 6234 }; 6235 6236 static void 6237 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 6238 { 6239 char buf[32]; 6240 int line_size = 0; 6241 6242 while (f->name) { 6243 uint64_t mask = (1ULL << f->width) - 1; 6244 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 6245 ((uintmax_t)v >> f->start) & mask); 6246 6247 if (line_size + len >= 79) { 6248 line_size = 8; 6249 sbuf_printf(sb, "\n "); 6250 } 6251 sbuf_printf(sb, "%s ", buf); 6252 line_size += len + 1; 6253 f++; 6254 } 6255 sbuf_printf(sb, "\n"); 6256 } 6257 6258 static struct field_desc tp_la0[] = { 6259 { "RcfOpCodeOut", 60, 4 }, 6260 { "State", 56, 4 }, 6261 { "WcfState", 52, 4 }, 6262 { "RcfOpcSrcOut", 50, 2 }, 6263 { "CRxError", 49, 1 }, 6264 { "ERxError", 48, 1 }, 6265 { "SanityFailed", 47, 1 }, 6266 { "SpuriousMsg", 46, 1 }, 6267 { "FlushInputMsg", 45, 1 }, 6268 { "FlushInputCpl", 44, 1 }, 6269 { "RssUpBit", 43, 1 }, 6270 { "RssFilterHit", 42, 1 }, 6271 { "Tid", 32, 10 }, 6272 { "InitTcb", 31, 1 }, 6273 { "LineNumber", 24, 7 }, 6274 { "Emsg", 23, 1 }, 6275 { "EdataOut", 22, 1 }, 6276 { "Cmsg", 21, 1 }, 6277 { "CdataOut", 20, 1 }, 6278 { "EreadPdu", 19, 1 }, 6279 { "CreadPdu", 18, 1 }, 6280 { "TunnelPkt", 17, 1 }, 6281 { "RcfPeerFin", 16, 1 }, 6282 { "RcfReasonOut", 12, 4 }, 6283 { "TxCchannel", 10, 2 }, 6284 { "RcfTxChannel", 8, 2 }, 6285 { "RxEchannel", 6, 2 }, 6286 { "RcfRxChannel", 5, 1 }, 6287 { "RcfDataOutSrdy", 4, 1 }, 6288 { "RxDvld", 3, 1 }, 6289 { "RxOoDvld", 2, 1 }, 6290 { "RxCongestion", 1, 1 }, 6291 { "TxCongestion", 0, 1 }, 6292 { NULL } 6293 }; 6294 6295 static struct field_desc tp_la1[] = { 6296 { "CplCmdIn", 56, 8 }, 6297 { "CplCmdOut", 48, 8 }, 6298 { "ESynOut", 47, 1 }, 6299 { "EAckOut", 46, 1 }, 6300 { "EFinOut", 45, 1 }, 6301 { "ERstOut", 44, 1 }, 6302 { "SynIn", 43, 1 }, 6303 { "AckIn", 42, 1 }, 6304 { "FinIn", 41, 1 }, 6305 { "RstIn", 40, 1 }, 6306 { "DataIn", 39, 1 }, 6307 { "DataInVld", 38, 1 }, 6308 { "PadIn", 37, 1 }, 6309 { "RxBufEmpty", 36, 1 }, 6310 { "RxDdp", 35, 1 }, 6311 { "RxFbCongestion", 34, 1 }, 6312 { "TxFbCongestion", 33, 1 }, 6313 { "TxPktSumSrdy", 32, 1 }, 6314 { "RcfUlpType", 28, 4 }, 6315 { "Eread", 27, 1 }, 6316 { "Ebypass", 26, 1 }, 6317 { "Esave", 25, 1 }, 6318 { "Static0", 24, 1 }, 6319 { "Cread", 23, 1 }, 6320 { "Cbypass", 22, 1 }, 6321 { "Csave", 21, 1 }, 6322 { "CPktOut", 20, 1 }, 6323 { "RxPagePoolFull", 18, 2 }, 6324 { "RxLpbkPkt", 17, 1 }, 6325 { "TxLpbkPkt", 16, 1 }, 6326 { "RxVfValid", 15, 1 }, 6327 { "SynLearned", 14, 1 }, 6328 { "SetDelEntry", 13, 1 }, 6329 { "SetInvEntry", 12, 1 }, 6330 { "CpcmdDvld", 11, 1 }, 6331 { "CpcmdSave", 10, 1 }, 6332 { "RxPstructsFull", 8, 2 }, 6333 { "EpcmdDvld", 7, 1 }, 6334 { "EpcmdFlush", 6, 1 }, 6335 { "EpcmdTrimPrefix", 5, 1 }, 6336 { "EpcmdTrimPostfix", 4, 1 }, 6337 { "ERssIp4Pkt", 3, 1 }, 6338 { "ERssIp6Pkt", 2, 1 }, 6339 { "ERssTcpUdpPkt", 1, 1 }, 6340 { "ERssFceFipPkt", 0, 1 }, 6341 { NULL } 6342 }; 6343 6344 static struct field_desc tp_la2[] = { 6345 { "CplCmdIn", 56, 8 }, 6346 { "MpsVfVld", 55, 1 }, 6347 { "MpsPf", 52, 3 }, 6348 { "MpsVf", 44, 8 }, 6349 { "SynIn", 43, 1 }, 6350 { "AckIn", 42, 1 }, 6351 { "FinIn", 41, 1 }, 6352 { "RstIn", 40, 1 }, 6353 { "DataIn", 39, 1 }, 6354 { "DataInVld", 38, 1 }, 6355 { "PadIn", 37, 1 }, 6356 { "RxBufEmpty", 36, 1 }, 6357 { "RxDdp", 35, 1 }, 6358 { "RxFbCongestion", 34, 1 }, 6359 { "TxFbCongestion", 33, 1 }, 6360 { "TxPktSumSrdy", 32, 1 }, 6361 { "RcfUlpType", 28, 4 }, 6362 { "Eread", 27, 1 }, 6363 { "Ebypass", 26, 1 }, 6364 { "Esave", 25, 1 }, 6365 { "Static0", 24, 1 }, 6366 { "Cread", 23, 1 }, 6367 { "Cbypass", 22, 1 }, 6368 { "Csave", 21, 1 }, 6369 { "CPktOut", 20, 1 }, 6370 { "RxPagePoolFull", 18, 2 }, 6371 { "RxLpbkPkt", 17, 1 }, 6372 { "TxLpbkPkt", 16, 1 }, 6373 { "RxVfValid", 15, 1 }, 6374 { "SynLearned", 14, 1 }, 6375 { "SetDelEntry", 13, 1 }, 6376 { "SetInvEntry", 12, 1 }, 6377 { "CpcmdDvld", 11, 1 }, 6378 { "CpcmdSave", 10, 1 }, 6379 { "RxPstructsFull", 8, 2 }, 6380 { "EpcmdDvld", 7, 1 }, 6381 { "EpcmdFlush", 6, 1 }, 6382 { "EpcmdTrimPrefix", 5, 1 }, 6383 { "EpcmdTrimPostfix", 4, 1 }, 6384 { "ERssIp4Pkt", 3, 1 }, 6385 { "ERssIp6Pkt", 2, 1 }, 6386 { "ERssTcpUdpPkt", 1, 1 }, 6387 { "ERssFceFipPkt", 0, 1 }, 6388 { NULL } 6389 }; 6390 6391 static void 6392 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 6393 { 6394 6395 field_desc_show(sb, *p, tp_la0); 6396 } 6397 6398 static void 6399 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 6400 { 6401 6402 if (idx) 6403 sbuf_printf(sb, "\n"); 6404 field_desc_show(sb, p[0], tp_la0); 6405 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 6406 field_desc_show(sb, p[1], tp_la0); 6407 } 6408 6409 static void 6410 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 6411 { 6412 6413 if (idx) 6414 sbuf_printf(sb, "\n"); 6415 field_desc_show(sb, p[0], tp_la0); 6416 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 6417 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 6418 } 6419 6420 static int 6421 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 6422 { 6423 struct adapter *sc = arg1; 6424 struct sbuf *sb; 6425 uint64_t *buf, *p; 6426 int rc; 6427 u_int i, inc; 6428 void (*show_func)(struct sbuf *, uint64_t *, int); 6429 6430 rc = sysctl_wire_old_buffer(req, 0); 6431 if (rc != 0) 6432 return (rc); 6433 6434 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6435 if (sb == NULL) 6436 return (ENOMEM); 6437 6438 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 6439 6440 t4_tp_read_la(sc, buf, NULL); 6441 p = buf; 6442 6443 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 6444 case 2: 6445 inc = 2; 6446 show_func = tp_la_show2; 6447 break; 6448 case 3: 6449 inc = 2; 6450 show_func = tp_la_show3; 6451 break; 6452 default: 6453 inc = 1; 6454 show_func = tp_la_show; 6455 } 6456 6457 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 6458 (*show_func)(sb, p, i); 6459 6460 rc = sbuf_finish(sb); 6461 sbuf_delete(sb); 6462 free(buf, M_CXGBE); 6463 return (rc); 6464 } 6465 6466 static int 6467 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 6468 { 6469 struct adapter *sc = arg1; 6470 struct sbuf *sb; 6471 int rc; 6472 u64 nrate[NCHAN], orate[NCHAN]; 6473 6474 rc = sysctl_wire_old_buffer(req, 0); 6475 if (rc != 0) 6476 return (rc); 6477 6478 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6479 if (sb == NULL) 6480 return (ENOMEM); 6481 6482 t4_get_chan_txrate(sc, nrate, orate); 6483 sbuf_printf(sb, " channel 0 channel 1 channel 2 " 6484 "channel 3\n"); 6485 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 6486 nrate[0], nrate[1], nrate[2], nrate[3]); 6487 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 6488 orate[0], orate[1], orate[2], orate[3]); 6489 6490 rc = sbuf_finish(sb); 6491 sbuf_delete(sb); 6492 6493 return (rc); 6494 } 6495 6496 static int 6497 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 6498 { 6499 struct adapter *sc = arg1; 6500 struct sbuf *sb; 6501 uint32_t *buf, *p; 6502 int rc, i; 6503 6504 rc = sysctl_wire_old_buffer(req, 0); 6505 if (rc != 0) 6506 return (rc); 6507 6508 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6509 if (sb == NULL) 6510 return (ENOMEM); 6511 6512 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 6513 M_ZERO | M_WAITOK); 6514 6515 t4_ulprx_read_la(sc, buf); 6516 p = buf; 6517 6518 sbuf_printf(sb, " Pcmd Type Message" 6519 " Data"); 6520 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 6521 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 6522 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 6523 } 6524 6525 rc = sbuf_finish(sb); 6526 sbuf_delete(sb); 6527 free(buf, M_CXGBE); 6528 return (rc); 6529 } 6530 6531 static int 6532 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 6533 { 6534 struct adapter *sc = arg1; 6535 struct sbuf *sb; 6536 int rc, v; 6537 6538 rc = sysctl_wire_old_buffer(req, 0); 6539 if (rc != 0) 6540 return (rc); 6541 6542 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6543 if (sb == NULL) 6544 return (ENOMEM); 6545 6546 v = t4_read_reg(sc, A_SGE_STAT_CFG); 6547 if (G_STATSOURCE_T5(v) == 7) { 6548 if (G_STATMODE(v) == 0) { 6549 sbuf_printf(sb, "total %d, incomplete %d", 6550 t4_read_reg(sc, A_SGE_STAT_TOTAL), 6551 t4_read_reg(sc, A_SGE_STAT_MATCH)); 6552 } else if (G_STATMODE(v) == 1) { 6553 sbuf_printf(sb, "total %d, data overflow %d", 6554 t4_read_reg(sc, A_SGE_STAT_TOTAL), 6555 t4_read_reg(sc, A_SGE_STAT_MATCH)); 6556 } 6557 } 6558 rc = sbuf_finish(sb); 6559 sbuf_delete(sb); 6560 6561 return (rc); 6562 } 6563 #endif 6564 6565 static inline void 6566 txq_start(struct ifnet *ifp, struct sge_txq *txq) 6567 { 6568 struct buf_ring *br; 6569 struct mbuf *m; 6570 6571 TXQ_LOCK_ASSERT_OWNED(txq); 6572 6573 br = txq->br; 6574 m = txq->m ? txq->m : drbr_dequeue(ifp, br); 6575 if (m) 6576 t4_eth_tx(ifp, txq, m); 6577 } 6578 6579 void 6580 t4_tx_callout(void *arg) 6581 { 6582 struct sge_eq *eq = arg; 6583 struct adapter *sc; 6584 6585 if (EQ_TRYLOCK(eq) == 0) 6586 goto reschedule; 6587 6588 if (eq->flags & EQ_STALLED && !can_resume_tx(eq)) { 6589 EQ_UNLOCK(eq); 6590 reschedule: 6591 if (__predict_true(!(eq->flags && EQ_DOOMED))) 6592 callout_schedule(&eq->tx_callout, 1); 6593 return; 6594 } 6595 6596 EQ_LOCK_ASSERT_OWNED(eq); 6597 6598 if (__predict_true((eq->flags & EQ_DOOMED) == 0)) { 6599 6600 if ((eq->flags & EQ_TYPEMASK) == EQ_ETH) { 6601 struct sge_txq *txq = arg; 6602 struct port_info *pi = txq->ifp->if_softc; 6603 6604 sc = pi->adapter; 6605 } else { 6606 struct sge_wrq *wrq = arg; 6607 6608 sc = wrq->adapter; 6609 } 6610 6611 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task); 6612 } 6613 6614 EQ_UNLOCK(eq); 6615 } 6616 6617 void 6618 t4_tx_task(void *arg, int count) 6619 { 6620 struct sge_eq *eq = arg; 6621 6622 EQ_LOCK(eq); 6623 if ((eq->flags & EQ_TYPEMASK) == EQ_ETH) { 6624 struct sge_txq *txq = arg; 6625 txq_start(txq->ifp, txq); 6626 } else { 6627 struct sge_wrq *wrq = arg; 6628 t4_wrq_tx_locked(wrq->adapter, wrq, NULL); 6629 } 6630 EQ_UNLOCK(eq); 6631 } 6632 6633 static uint32_t 6634 fconf_to_mode(uint32_t fconf) 6635 { 6636 uint32_t mode; 6637 6638 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR | 6639 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT; 6640 6641 if (fconf & F_FRAGMENTATION) 6642 mode |= T4_FILTER_IP_FRAGMENT; 6643 6644 if (fconf & F_MPSHITTYPE) 6645 mode |= T4_FILTER_MPS_HIT_TYPE; 6646 6647 if (fconf & F_MACMATCH) 6648 mode |= T4_FILTER_MAC_IDX; 6649 6650 if (fconf & F_ETHERTYPE) 6651 mode |= T4_FILTER_ETH_TYPE; 6652 6653 if (fconf & F_PROTOCOL) 6654 mode |= T4_FILTER_IP_PROTO; 6655 6656 if (fconf & F_TOS) 6657 mode |= T4_FILTER_IP_TOS; 6658 6659 if (fconf & F_VLAN) 6660 mode |= T4_FILTER_VLAN; 6661 6662 if (fconf & F_VNIC_ID) 6663 mode |= T4_FILTER_VNIC; 6664 6665 if (fconf & F_PORT) 6666 mode |= T4_FILTER_PORT; 6667 6668 if (fconf & F_FCOE) 6669 mode |= T4_FILTER_FCoE; 6670 6671 return (mode); 6672 } 6673 6674 static uint32_t 6675 mode_to_fconf(uint32_t mode) 6676 { 6677 uint32_t fconf = 0; 6678 6679 if (mode & T4_FILTER_IP_FRAGMENT) 6680 fconf |= F_FRAGMENTATION; 6681 6682 if (mode & T4_FILTER_MPS_HIT_TYPE) 6683 fconf |= F_MPSHITTYPE; 6684 6685 if (mode & T4_FILTER_MAC_IDX) 6686 fconf |= F_MACMATCH; 6687 6688 if (mode & T4_FILTER_ETH_TYPE) 6689 fconf |= F_ETHERTYPE; 6690 6691 if (mode & T4_FILTER_IP_PROTO) 6692 fconf |= F_PROTOCOL; 6693 6694 if (mode & T4_FILTER_IP_TOS) 6695 fconf |= F_TOS; 6696 6697 if (mode & T4_FILTER_VLAN) 6698 fconf |= F_VLAN; 6699 6700 if (mode & T4_FILTER_VNIC) 6701 fconf |= F_VNIC_ID; 6702 6703 if (mode & T4_FILTER_PORT) 6704 fconf |= F_PORT; 6705 6706 if (mode & T4_FILTER_FCoE) 6707 fconf |= F_FCOE; 6708 6709 return (fconf); 6710 } 6711 6712 static uint32_t 6713 fspec_to_fconf(struct t4_filter_specification *fs) 6714 { 6715 uint32_t fconf = 0; 6716 6717 if (fs->val.frag || fs->mask.frag) 6718 fconf |= F_FRAGMENTATION; 6719 6720 if (fs->val.matchtype || fs->mask.matchtype) 6721 fconf |= F_MPSHITTYPE; 6722 6723 if (fs->val.macidx || fs->mask.macidx) 6724 fconf |= F_MACMATCH; 6725 6726 if (fs->val.ethtype || fs->mask.ethtype) 6727 fconf |= F_ETHERTYPE; 6728 6729 if (fs->val.proto || fs->mask.proto) 6730 fconf |= F_PROTOCOL; 6731 6732 if (fs->val.tos || fs->mask.tos) 6733 fconf |= F_TOS; 6734 6735 if (fs->val.vlan_vld || fs->mask.vlan_vld) 6736 fconf |= F_VLAN; 6737 6738 if (fs->val.vnic_vld || fs->mask.vnic_vld) 6739 fconf |= F_VNIC_ID; 6740 6741 if (fs->val.iport || fs->mask.iport) 6742 fconf |= F_PORT; 6743 6744 if (fs->val.fcoe || fs->mask.fcoe) 6745 fconf |= F_FCOE; 6746 6747 return (fconf); 6748 } 6749 6750 static int 6751 get_filter_mode(struct adapter *sc, uint32_t *mode) 6752 { 6753 int rc; 6754 uint32_t fconf; 6755 6756 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 6757 "t4getfm"); 6758 if (rc) 6759 return (rc); 6760 6761 t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &fconf, 1, 6762 A_TP_VLAN_PRI_MAP); 6763 6764 if (sc->params.tp.vlan_pri_map != fconf) { 6765 log(LOG_WARNING, "%s: cached filter mode out of sync %x %x.\n", 6766 device_get_nameunit(sc->dev), sc->params.tp.vlan_pri_map, 6767 fconf); 6768 sc->params.tp.vlan_pri_map = fconf; 6769 } 6770 6771 *mode = fconf_to_mode(sc->params.tp.vlan_pri_map); 6772 6773 end_synchronized_op(sc, LOCK_HELD); 6774 return (0); 6775 } 6776 6777 static int 6778 set_filter_mode(struct adapter *sc, uint32_t mode) 6779 { 6780 uint32_t fconf; 6781 int rc; 6782 6783 fconf = mode_to_fconf(mode); 6784 6785 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 6786 "t4setfm"); 6787 if (rc) 6788 return (rc); 6789 6790 if (sc->tids.ftids_in_use > 0) { 6791 rc = EBUSY; 6792 goto done; 6793 } 6794 6795 #ifdef TCP_OFFLOAD 6796 if (sc->offload_map) { 6797 rc = EBUSY; 6798 goto done; 6799 } 6800 #endif 6801 6802 #ifdef notyet 6803 rc = -t4_set_filter_mode(sc, fconf); 6804 if (rc == 0) 6805 sc->filter_mode = fconf; 6806 #else 6807 rc = ENOTSUP; 6808 #endif 6809 6810 done: 6811 end_synchronized_op(sc, LOCK_HELD); 6812 return (rc); 6813 } 6814 6815 static inline uint64_t 6816 get_filter_hits(struct adapter *sc, uint32_t fid) 6817 { 6818 uint32_t mw_base, off, tcb_base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 6819 uint64_t hits; 6820 6821 memwin_info(sc, 0, &mw_base, NULL); 6822 off = position_memwin(sc, 0, 6823 tcb_base + (fid + sc->tids.ftid_base) * TCB_SIZE); 6824 if (is_t4(sc)) { 6825 hits = t4_read_reg64(sc, mw_base + off + 16); 6826 hits = be64toh(hits); 6827 } else { 6828 hits = t4_read_reg(sc, mw_base + off + 24); 6829 hits = be32toh(hits); 6830 } 6831 6832 return (hits); 6833 } 6834 6835 static int 6836 get_filter(struct adapter *sc, struct t4_filter *t) 6837 { 6838 int i, rc, nfilters = sc->tids.nftids; 6839 struct filter_entry *f; 6840 6841 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 6842 "t4getf"); 6843 if (rc) 6844 return (rc); 6845 6846 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL || 6847 t->idx >= nfilters) { 6848 t->idx = 0xffffffff; 6849 goto done; 6850 } 6851 6852 f = &sc->tids.ftid_tab[t->idx]; 6853 for (i = t->idx; i < nfilters; i++, f++) { 6854 if (f->valid) { 6855 t->idx = i; 6856 t->l2tidx = f->l2t ? f->l2t->idx : 0; 6857 t->smtidx = f->smtidx; 6858 if (f->fs.hitcnts) 6859 t->hits = get_filter_hits(sc, t->idx); 6860 else 6861 t->hits = UINT64_MAX; 6862 t->fs = f->fs; 6863 6864 goto done; 6865 } 6866 } 6867 6868 t->idx = 0xffffffff; 6869 done: 6870 end_synchronized_op(sc, LOCK_HELD); 6871 return (0); 6872 } 6873 6874 static int 6875 set_filter(struct adapter *sc, struct t4_filter *t) 6876 { 6877 unsigned int nfilters, nports; 6878 struct filter_entry *f; 6879 int i, rc; 6880 6881 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf"); 6882 if (rc) 6883 return (rc); 6884 6885 nfilters = sc->tids.nftids; 6886 nports = sc->params.nports; 6887 6888 if (nfilters == 0) { 6889 rc = ENOTSUP; 6890 goto done; 6891 } 6892 6893 if (!(sc->flags & FULL_INIT_DONE)) { 6894 rc = EAGAIN; 6895 goto done; 6896 } 6897 6898 if (t->idx >= nfilters) { 6899 rc = EINVAL; 6900 goto done; 6901 } 6902 6903 /* Validate against the global filter mode */ 6904 if ((sc->params.tp.vlan_pri_map | fspec_to_fconf(&t->fs)) != 6905 sc->params.tp.vlan_pri_map) { 6906 rc = E2BIG; 6907 goto done; 6908 } 6909 6910 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) { 6911 rc = EINVAL; 6912 goto done; 6913 } 6914 6915 if (t->fs.val.iport >= nports) { 6916 rc = EINVAL; 6917 goto done; 6918 } 6919 6920 /* Can't specify an iq if not steering to it */ 6921 if (!t->fs.dirsteer && t->fs.iq) { 6922 rc = EINVAL; 6923 goto done; 6924 } 6925 6926 /* IPv6 filter idx must be 4 aligned */ 6927 if (t->fs.type == 1 && 6928 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) { 6929 rc = EINVAL; 6930 goto done; 6931 } 6932 6933 if (sc->tids.ftid_tab == NULL) { 6934 KASSERT(sc->tids.ftids_in_use == 0, 6935 ("%s: no memory allocated but filters_in_use > 0", 6936 __func__)); 6937 6938 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) * 6939 nfilters, M_CXGBE, M_NOWAIT | M_ZERO); 6940 if (sc->tids.ftid_tab == NULL) { 6941 rc = ENOMEM; 6942 goto done; 6943 } 6944 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF); 6945 } 6946 6947 for (i = 0; i < 4; i++) { 6948 f = &sc->tids.ftid_tab[t->idx + i]; 6949 6950 if (f->pending || f->valid) { 6951 rc = EBUSY; 6952 goto done; 6953 } 6954 if (f->locked) { 6955 rc = EPERM; 6956 goto done; 6957 } 6958 6959 if (t->fs.type == 0) 6960 break; 6961 } 6962 6963 f = &sc->tids.ftid_tab[t->idx]; 6964 f->fs = t->fs; 6965 6966 rc = set_filter_wr(sc, t->idx); 6967 done: 6968 end_synchronized_op(sc, 0); 6969 6970 if (rc == 0) { 6971 mtx_lock(&sc->tids.ftid_lock); 6972 for (;;) { 6973 if (f->pending == 0) { 6974 rc = f->valid ? 0 : EIO; 6975 break; 6976 } 6977 6978 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 6979 PCATCH, "t4setfw", 0)) { 6980 rc = EINPROGRESS; 6981 break; 6982 } 6983 } 6984 mtx_unlock(&sc->tids.ftid_lock); 6985 } 6986 return (rc); 6987 } 6988 6989 static int 6990 del_filter(struct adapter *sc, struct t4_filter *t) 6991 { 6992 unsigned int nfilters; 6993 struct filter_entry *f; 6994 int rc; 6995 6996 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf"); 6997 if (rc) 6998 return (rc); 6999 7000 nfilters = sc->tids.nftids; 7001 7002 if (nfilters == 0) { 7003 rc = ENOTSUP; 7004 goto done; 7005 } 7006 7007 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 || 7008 t->idx >= nfilters) { 7009 rc = EINVAL; 7010 goto done; 7011 } 7012 7013 if (!(sc->flags & FULL_INIT_DONE)) { 7014 rc = EAGAIN; 7015 goto done; 7016 } 7017 7018 f = &sc->tids.ftid_tab[t->idx]; 7019 7020 if (f->pending) { 7021 rc = EBUSY; 7022 goto done; 7023 } 7024 if (f->locked) { 7025 rc = EPERM; 7026 goto done; 7027 } 7028 7029 if (f->valid) { 7030 t->fs = f->fs; /* extra info for the caller */ 7031 rc = del_filter_wr(sc, t->idx); 7032 } 7033 7034 done: 7035 end_synchronized_op(sc, 0); 7036 7037 if (rc == 0) { 7038 mtx_lock(&sc->tids.ftid_lock); 7039 for (;;) { 7040 if (f->pending == 0) { 7041 rc = f->valid ? EIO : 0; 7042 break; 7043 } 7044 7045 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 7046 PCATCH, "t4delfw", 0)) { 7047 rc = EINPROGRESS; 7048 break; 7049 } 7050 } 7051 mtx_unlock(&sc->tids.ftid_lock); 7052 } 7053 7054 return (rc); 7055 } 7056 7057 static void 7058 clear_filter(struct filter_entry *f) 7059 { 7060 if (f->l2t) 7061 t4_l2t_release(f->l2t); 7062 7063 bzero(f, sizeof (*f)); 7064 } 7065 7066 static int 7067 set_filter_wr(struct adapter *sc, int fidx) 7068 { 7069 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 7070 struct wrqe *wr; 7071 struct fw_filter_wr *fwr; 7072 unsigned int ftid; 7073 7074 ASSERT_SYNCHRONIZED_OP(sc); 7075 7076 if (f->fs.newdmac || f->fs.newvlan) { 7077 /* This filter needs an L2T entry; allocate one. */ 7078 f->l2t = t4_l2t_alloc_switching(sc->l2t); 7079 if (f->l2t == NULL) 7080 return (EAGAIN); 7081 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport, 7082 f->fs.dmac)) { 7083 t4_l2t_release(f->l2t); 7084 f->l2t = NULL; 7085 return (ENOMEM); 7086 } 7087 } 7088 7089 ftid = sc->tids.ftid_base + fidx; 7090 7091 wr = alloc_wrqe(sizeof(*fwr), &sc->sge.mgmtq); 7092 if (wr == NULL) 7093 return (ENOMEM); 7094 7095 fwr = wrtod(wr); 7096 bzero(fwr, sizeof (*fwr)); 7097 7098 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR)); 7099 fwr->len16_pkd = htobe32(FW_LEN16(*fwr)); 7100 fwr->tid_to_iq = 7101 htobe32(V_FW_FILTER_WR_TID(ftid) | 7102 V_FW_FILTER_WR_RQTYPE(f->fs.type) | 7103 V_FW_FILTER_WR_NOREPLY(0) | 7104 V_FW_FILTER_WR_IQ(f->fs.iq)); 7105 fwr->del_filter_to_l2tix = 7106 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) | 7107 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) | 7108 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) | 7109 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) | 7110 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) | 7111 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) | 7112 V_FW_FILTER_WR_DMAC(f->fs.newdmac) | 7113 V_FW_FILTER_WR_SMAC(f->fs.newsmac) | 7114 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT || 7115 f->fs.newvlan == VLAN_REWRITE) | 7116 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE || 7117 f->fs.newvlan == VLAN_REWRITE) | 7118 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) | 7119 V_FW_FILTER_WR_TXCHAN(f->fs.eport) | 7120 V_FW_FILTER_WR_PRIO(f->fs.prio) | 7121 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0)); 7122 fwr->ethtype = htobe16(f->fs.val.ethtype); 7123 fwr->ethtypem = htobe16(f->fs.mask.ethtype); 7124 fwr->frag_to_ovlan_vldm = 7125 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) | 7126 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) | 7127 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) | 7128 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.vnic_vld) | 7129 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) | 7130 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.vnic_vld)); 7131 fwr->smac_sel = 0; 7132 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) | 7133 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id)); 7134 fwr->maci_to_matchtypem = 7135 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) | 7136 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) | 7137 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) | 7138 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) | 7139 V_FW_FILTER_WR_PORT(f->fs.val.iport) | 7140 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) | 7141 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) | 7142 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype)); 7143 fwr->ptcl = f->fs.val.proto; 7144 fwr->ptclm = f->fs.mask.proto; 7145 fwr->ttyp = f->fs.val.tos; 7146 fwr->ttypm = f->fs.mask.tos; 7147 fwr->ivlan = htobe16(f->fs.val.vlan); 7148 fwr->ivlanm = htobe16(f->fs.mask.vlan); 7149 fwr->ovlan = htobe16(f->fs.val.vnic); 7150 fwr->ovlanm = htobe16(f->fs.mask.vnic); 7151 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip)); 7152 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm)); 7153 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip)); 7154 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm)); 7155 fwr->lp = htobe16(f->fs.val.dport); 7156 fwr->lpm = htobe16(f->fs.mask.dport); 7157 fwr->fp = htobe16(f->fs.val.sport); 7158 fwr->fpm = htobe16(f->fs.mask.sport); 7159 if (f->fs.newsmac) 7160 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma)); 7161 7162 f->pending = 1; 7163 sc->tids.ftids_in_use++; 7164 7165 t4_wrq_tx(sc, wr); 7166 return (0); 7167 } 7168 7169 static int 7170 del_filter_wr(struct adapter *sc, int fidx) 7171 { 7172 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 7173 struct wrqe *wr; 7174 struct fw_filter_wr *fwr; 7175 unsigned int ftid; 7176 7177 ftid = sc->tids.ftid_base + fidx; 7178 7179 wr = alloc_wrqe(sizeof(*fwr), &sc->sge.mgmtq); 7180 if (wr == NULL) 7181 return (ENOMEM); 7182 fwr = wrtod(wr); 7183 bzero(fwr, sizeof (*fwr)); 7184 7185 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id); 7186 7187 f->pending = 1; 7188 t4_wrq_tx(sc, wr); 7189 return (0); 7190 } 7191 7192 int 7193 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 7194 { 7195 struct adapter *sc = iq->adapter; 7196 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1); 7197 unsigned int idx = GET_TID(rpl); 7198 unsigned int rc; 7199 struct filter_entry *f; 7200 7201 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 7202 rss->opcode)); 7203 7204 if (is_ftid(sc, idx)) { 7205 7206 idx -= sc->tids.ftid_base; 7207 f = &sc->tids.ftid_tab[idx]; 7208 rc = G_COOKIE(rpl->cookie); 7209 7210 mtx_lock(&sc->tids.ftid_lock); 7211 if (rc == FW_FILTER_WR_FLT_ADDED) { 7212 KASSERT(f->pending, ("%s: filter[%u] isn't pending.", 7213 __func__, idx)); 7214 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; 7215 f->pending = 0; /* asynchronous setup completed */ 7216 f->valid = 1; 7217 } else { 7218 if (rc != FW_FILTER_WR_FLT_DELETED) { 7219 /* Add or delete failed, display an error */ 7220 log(LOG_ERR, 7221 "filter %u setup failed with error %u\n", 7222 idx, rc); 7223 } 7224 7225 clear_filter(f); 7226 sc->tids.ftids_in_use--; 7227 } 7228 wakeup(&sc->tids.ftid_tab); 7229 mtx_unlock(&sc->tids.ftid_lock); 7230 } 7231 7232 return (0); 7233 } 7234 7235 static int 7236 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 7237 { 7238 int rc; 7239 7240 if (cntxt->cid > M_CTXTQID) 7241 return (EINVAL); 7242 7243 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 7244 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 7245 return (EINVAL); 7246 7247 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 7248 if (rc) 7249 return (rc); 7250 7251 if (sc->flags & FW_OK) { 7252 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 7253 &cntxt->data[0]); 7254 if (rc == 0) 7255 goto done; 7256 } 7257 7258 /* 7259 * Read via firmware failed or wasn't even attempted. Read directly via 7260 * the backdoor. 7261 */ 7262 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 7263 done: 7264 end_synchronized_op(sc, 0); 7265 return (rc); 7266 } 7267 7268 static int 7269 load_fw(struct adapter *sc, struct t4_data *fw) 7270 { 7271 int rc; 7272 uint8_t *fw_data; 7273 7274 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 7275 if (rc) 7276 return (rc); 7277 7278 if (sc->flags & FULL_INIT_DONE) { 7279 rc = EBUSY; 7280 goto done; 7281 } 7282 7283 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 7284 if (fw_data == NULL) { 7285 rc = ENOMEM; 7286 goto done; 7287 } 7288 7289 rc = copyin(fw->data, fw_data, fw->len); 7290 if (rc == 0) 7291 rc = -t4_load_fw(sc, fw_data, fw->len); 7292 7293 free(fw_data, M_CXGBE); 7294 done: 7295 end_synchronized_op(sc, 0); 7296 return (rc); 7297 } 7298 7299 static int 7300 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 7301 { 7302 uint32_t addr, off, remaining, i, n; 7303 uint32_t *buf, *b; 7304 uint32_t mw_base, mw_aperture; 7305 int rc; 7306 uint8_t *dst; 7307 7308 rc = validate_mem_range(sc, mr->addr, mr->len); 7309 if (rc != 0) 7310 return (rc); 7311 7312 memwin_info(sc, win, &mw_base, &mw_aperture); 7313 buf = b = malloc(min(mr->len, mw_aperture), M_CXGBE, M_WAITOK); 7314 addr = mr->addr; 7315 remaining = mr->len; 7316 dst = (void *)mr->data; 7317 7318 while (remaining) { 7319 off = position_memwin(sc, win, addr); 7320 7321 /* number of bytes that we'll copy in the inner loop */ 7322 n = min(remaining, mw_aperture - off); 7323 for (i = 0; i < n; i += 4) 7324 *b++ = t4_read_reg(sc, mw_base + off + i); 7325 7326 rc = copyout(buf, dst, n); 7327 if (rc != 0) 7328 break; 7329 7330 b = buf; 7331 dst += n; 7332 remaining -= n; 7333 addr += n; 7334 } 7335 7336 free(buf, M_CXGBE); 7337 return (rc); 7338 } 7339 7340 static int 7341 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 7342 { 7343 int rc; 7344 7345 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 7346 return (EINVAL); 7347 7348 if (i2cd->len > 1) { 7349 /* XXX: need fw support for longer reads in one go */ 7350 return (ENOTSUP); 7351 } 7352 7353 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 7354 if (rc) 7355 return (rc); 7356 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 7357 i2cd->offset, &i2cd->data[0]); 7358 end_synchronized_op(sc, 0); 7359 7360 return (rc); 7361 } 7362 7363 static int 7364 in_range(int val, int lo, int hi) 7365 { 7366 7367 return (val < 0 || (val <= hi && val >= lo)); 7368 } 7369 7370 static int 7371 set_sched_class(struct adapter *sc, struct t4_sched_params *p) 7372 { 7373 int fw_subcmd, fw_type, rc; 7374 7375 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsc"); 7376 if (rc) 7377 return (rc); 7378 7379 if (!(sc->flags & FULL_INIT_DONE)) { 7380 rc = EAGAIN; 7381 goto done; 7382 } 7383 7384 /* 7385 * Translate the cxgbetool parameters into T4 firmware parameters. (The 7386 * sub-command and type are in common locations.) 7387 */ 7388 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG) 7389 fw_subcmd = FW_SCHED_SC_CONFIG; 7390 else if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS) 7391 fw_subcmd = FW_SCHED_SC_PARAMS; 7392 else { 7393 rc = EINVAL; 7394 goto done; 7395 } 7396 if (p->type == SCHED_CLASS_TYPE_PACKET) 7397 fw_type = FW_SCHED_TYPE_PKTSCHED; 7398 else { 7399 rc = EINVAL; 7400 goto done; 7401 } 7402 7403 if (fw_subcmd == FW_SCHED_SC_CONFIG) { 7404 /* Vet our parameters ..*/ 7405 if (p->u.config.minmax < 0) { 7406 rc = EINVAL; 7407 goto done; 7408 } 7409 7410 /* And pass the request to the firmware ...*/ 7411 rc = -t4_sched_config(sc, fw_type, p->u.config.minmax); 7412 goto done; 7413 } 7414 7415 if (fw_subcmd == FW_SCHED_SC_PARAMS) { 7416 int fw_level; 7417 int fw_mode; 7418 int fw_rateunit; 7419 int fw_ratemode; 7420 7421 if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL) 7422 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL; 7423 else if (p->u.params.level == SCHED_CLASS_LEVEL_CL_WRR) 7424 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 7425 else if (p->u.params.level == SCHED_CLASS_LEVEL_CH_RL) 7426 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL; 7427 else { 7428 rc = EINVAL; 7429 goto done; 7430 } 7431 7432 if (p->u.params.mode == SCHED_CLASS_MODE_CLASS) 7433 fw_mode = FW_SCHED_PARAMS_MODE_CLASS; 7434 else if (p->u.params.mode == SCHED_CLASS_MODE_FLOW) 7435 fw_mode = FW_SCHED_PARAMS_MODE_FLOW; 7436 else { 7437 rc = EINVAL; 7438 goto done; 7439 } 7440 7441 if (p->u.params.rateunit == SCHED_CLASS_RATEUNIT_BITS) 7442 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE; 7443 else if (p->u.params.rateunit == SCHED_CLASS_RATEUNIT_PKTS) 7444 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE; 7445 else { 7446 rc = EINVAL; 7447 goto done; 7448 } 7449 7450 if (p->u.params.ratemode == SCHED_CLASS_RATEMODE_REL) 7451 fw_ratemode = FW_SCHED_PARAMS_RATE_REL; 7452 else if (p->u.params.ratemode == SCHED_CLASS_RATEMODE_ABS) 7453 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS; 7454 else { 7455 rc = EINVAL; 7456 goto done; 7457 } 7458 7459 /* Vet our parameters ... */ 7460 if (!in_range(p->u.params.channel, 0, 3) || 7461 !in_range(p->u.params.cl, 0, is_t4(sc) ? 15 : 16) || 7462 !in_range(p->u.params.minrate, 0, 10000000) || 7463 !in_range(p->u.params.maxrate, 0, 10000000) || 7464 !in_range(p->u.params.weight, 0, 100)) { 7465 rc = ERANGE; 7466 goto done; 7467 } 7468 7469 /* 7470 * Translate any unset parameters into the firmware's 7471 * nomenclature and/or fail the call if the parameters 7472 * are required ... 7473 */ 7474 if (p->u.params.rateunit < 0 || p->u.params.ratemode < 0 || 7475 p->u.params.channel < 0 || p->u.params.cl < 0) { 7476 rc = EINVAL; 7477 goto done; 7478 } 7479 if (p->u.params.minrate < 0) 7480 p->u.params.minrate = 0; 7481 if (p->u.params.maxrate < 0) { 7482 if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL || 7483 p->u.params.level == SCHED_CLASS_LEVEL_CH_RL) { 7484 rc = EINVAL; 7485 goto done; 7486 } else 7487 p->u.params.maxrate = 0; 7488 } 7489 if (p->u.params.weight < 0) { 7490 if (p->u.params.level == SCHED_CLASS_LEVEL_CL_WRR) { 7491 rc = EINVAL; 7492 goto done; 7493 } else 7494 p->u.params.weight = 0; 7495 } 7496 if (p->u.params.pktsize < 0) { 7497 if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL || 7498 p->u.params.level == SCHED_CLASS_LEVEL_CH_RL) { 7499 rc = EINVAL; 7500 goto done; 7501 } else 7502 p->u.params.pktsize = 0; 7503 } 7504 7505 /* See what the firmware thinks of the request ... */ 7506 rc = -t4_sched_params(sc, fw_type, fw_level, fw_mode, 7507 fw_rateunit, fw_ratemode, p->u.params.channel, 7508 p->u.params.cl, p->u.params.minrate, p->u.params.maxrate, 7509 p->u.params.weight, p->u.params.pktsize); 7510 goto done; 7511 } 7512 7513 rc = EINVAL; 7514 done: 7515 end_synchronized_op(sc, 0); 7516 return (rc); 7517 } 7518 7519 static int 7520 set_sched_queue(struct adapter *sc, struct t4_sched_queue *p) 7521 { 7522 struct port_info *pi = NULL; 7523 struct sge_txq *txq; 7524 uint32_t fw_mnem, fw_queue, fw_class; 7525 int i, rc; 7526 7527 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq"); 7528 if (rc) 7529 return (rc); 7530 7531 if (!(sc->flags & FULL_INIT_DONE)) { 7532 rc = EAGAIN; 7533 goto done; 7534 } 7535 7536 if (p->port >= sc->params.nports) { 7537 rc = EINVAL; 7538 goto done; 7539 } 7540 7541 pi = sc->port[p->port]; 7542 if (!in_range(p->queue, 0, pi->ntxq - 1) || !in_range(p->cl, 0, 7)) { 7543 rc = EINVAL; 7544 goto done; 7545 } 7546 7547 /* 7548 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX 7549 * Scheduling Class in this case). 7550 */ 7551 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 7552 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH)); 7553 fw_class = p->cl < 0 ? 0xffffffff : p->cl; 7554 7555 /* 7556 * If op.queue is non-negative, then we're only changing the scheduling 7557 * on a single specified TX queue. 7558 */ 7559 if (p->queue >= 0) { 7560 txq = &sc->sge.txq[pi->first_txq + p->queue]; 7561 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 7562 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 7563 &fw_class); 7564 goto done; 7565 } 7566 7567 /* 7568 * Change the scheduling on all the TX queues for the 7569 * interface. 7570 */ 7571 for_each_txq(pi, i, txq) { 7572 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 7573 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 7574 &fw_class); 7575 if (rc) 7576 goto done; 7577 } 7578 7579 rc = 0; 7580 done: 7581 end_synchronized_op(sc, 0); 7582 return (rc); 7583 } 7584 7585 int 7586 t4_os_find_pci_capability(struct adapter *sc, int cap) 7587 { 7588 int i; 7589 7590 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 7591 } 7592 7593 int 7594 t4_os_pci_save_state(struct adapter *sc) 7595 { 7596 device_t dev; 7597 struct pci_devinfo *dinfo; 7598 7599 dev = sc->dev; 7600 dinfo = device_get_ivars(dev); 7601 7602 pci_cfg_save(dev, dinfo, 0); 7603 return (0); 7604 } 7605 7606 int 7607 t4_os_pci_restore_state(struct adapter *sc) 7608 { 7609 device_t dev; 7610 struct pci_devinfo *dinfo; 7611 7612 dev = sc->dev; 7613 dinfo = device_get_ivars(dev); 7614 7615 pci_cfg_restore(dev, dinfo); 7616 return (0); 7617 } 7618 7619 void 7620 t4_os_portmod_changed(const struct adapter *sc, int idx) 7621 { 7622 struct port_info *pi = sc->port[idx]; 7623 static const char *mod_str[] = { 7624 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 7625 }; 7626 7627 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 7628 if_printf(pi->ifp, "transceiver unplugged.\n"); 7629 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 7630 if_printf(pi->ifp, "unknown transceiver inserted.\n"); 7631 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 7632 if_printf(pi->ifp, "unsupported transceiver inserted.\n"); 7633 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 7634 if_printf(pi->ifp, "%s transceiver inserted.\n", 7635 mod_str[pi->mod_type]); 7636 } else { 7637 if_printf(pi->ifp, "transceiver (type %d) inserted.\n", 7638 pi->mod_type); 7639 } 7640 } 7641 7642 void 7643 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason) 7644 { 7645 struct port_info *pi = sc->port[idx]; 7646 struct ifnet *ifp = pi->ifp; 7647 7648 if (link_stat) { 7649 pi->linkdnrc = -1; 7650 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed); 7651 if_link_state_change(ifp, LINK_STATE_UP); 7652 } else { 7653 if (reason >= 0) 7654 pi->linkdnrc = reason; 7655 if_link_state_change(ifp, LINK_STATE_DOWN); 7656 } 7657 } 7658 7659 void 7660 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 7661 { 7662 struct adapter *sc; 7663 7664 sx_slock(&t4_list_lock); 7665 SLIST_FOREACH(sc, &t4_list, link) { 7666 /* 7667 * func should not make any assumptions about what state sc is 7668 * in - the only guarantee is that sc->sc_lock is a valid lock. 7669 */ 7670 func(sc, arg); 7671 } 7672 sx_sunlock(&t4_list_lock); 7673 } 7674 7675 static int 7676 t4_open(struct cdev *dev, int flags, int type, struct thread *td) 7677 { 7678 return (0); 7679 } 7680 7681 static int 7682 t4_close(struct cdev *dev, int flags, int type, struct thread *td) 7683 { 7684 return (0); 7685 } 7686 7687 static int 7688 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 7689 struct thread *td) 7690 { 7691 int rc; 7692 struct adapter *sc = dev->si_drv1; 7693 7694 rc = priv_check(td, PRIV_DRIVER); 7695 if (rc != 0) 7696 return (rc); 7697 7698 switch (cmd) { 7699 case CHELSIO_T4_GETREG: { 7700 struct t4_reg *edata = (struct t4_reg *)data; 7701 7702 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 7703 return (EFAULT); 7704 7705 if (edata->size == 4) 7706 edata->val = t4_read_reg(sc, edata->addr); 7707 else if (edata->size == 8) 7708 edata->val = t4_read_reg64(sc, edata->addr); 7709 else 7710 return (EINVAL); 7711 7712 break; 7713 } 7714 case CHELSIO_T4_SETREG: { 7715 struct t4_reg *edata = (struct t4_reg *)data; 7716 7717 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 7718 return (EFAULT); 7719 7720 if (edata->size == 4) { 7721 if (edata->val & 0xffffffff00000000) 7722 return (EINVAL); 7723 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 7724 } else if (edata->size == 8) 7725 t4_write_reg64(sc, edata->addr, edata->val); 7726 else 7727 return (EINVAL); 7728 break; 7729 } 7730 case CHELSIO_T4_REGDUMP: { 7731 struct t4_regdump *regs = (struct t4_regdump *)data; 7732 int reglen = is_t4(sc) ? T4_REGDUMP_SIZE : T5_REGDUMP_SIZE; 7733 uint8_t *buf; 7734 7735 if (regs->len < reglen) { 7736 regs->len = reglen; /* hint to the caller */ 7737 return (ENOBUFS); 7738 } 7739 7740 regs->len = reglen; 7741 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 7742 t4_get_regs(sc, regs, buf); 7743 rc = copyout(buf, regs->data, reglen); 7744 free(buf, M_CXGBE); 7745 break; 7746 } 7747 case CHELSIO_T4_GET_FILTER_MODE: 7748 rc = get_filter_mode(sc, (uint32_t *)data); 7749 break; 7750 case CHELSIO_T4_SET_FILTER_MODE: 7751 rc = set_filter_mode(sc, *(uint32_t *)data); 7752 break; 7753 case CHELSIO_T4_GET_FILTER: 7754 rc = get_filter(sc, (struct t4_filter *)data); 7755 break; 7756 case CHELSIO_T4_SET_FILTER: 7757 rc = set_filter(sc, (struct t4_filter *)data); 7758 break; 7759 case CHELSIO_T4_DEL_FILTER: 7760 rc = del_filter(sc, (struct t4_filter *)data); 7761 break; 7762 case CHELSIO_T4_GET_SGE_CONTEXT: 7763 rc = get_sge_context(sc, (struct t4_sge_context *)data); 7764 break; 7765 case CHELSIO_T4_LOAD_FW: 7766 rc = load_fw(sc, (struct t4_data *)data); 7767 break; 7768 case CHELSIO_T4_GET_MEM: 7769 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 7770 break; 7771 case CHELSIO_T4_GET_I2C: 7772 rc = read_i2c(sc, (struct t4_i2c_data *)data); 7773 break; 7774 case CHELSIO_T4_CLEAR_STATS: { 7775 int i; 7776 u_int port_id = *(uint32_t *)data; 7777 struct port_info *pi; 7778 7779 if (port_id >= sc->params.nports) 7780 return (EINVAL); 7781 7782 /* MAC stats */ 7783 t4_clr_port_stats(sc, port_id); 7784 7785 pi = sc->port[port_id]; 7786 if (pi->flags & PORT_INIT_DONE) { 7787 struct sge_rxq *rxq; 7788 struct sge_txq *txq; 7789 struct sge_wrq *wrq; 7790 7791 for_each_rxq(pi, i, rxq) { 7792 #if defined(INET) || defined(INET6) 7793 rxq->lro.lro_queued = 0; 7794 rxq->lro.lro_flushed = 0; 7795 #endif 7796 rxq->rxcsum = 0; 7797 rxq->vlan_extraction = 0; 7798 } 7799 7800 for_each_txq(pi, i, txq) { 7801 txq->txcsum = 0; 7802 txq->tso_wrs = 0; 7803 txq->vlan_insertion = 0; 7804 txq->imm_wrs = 0; 7805 txq->sgl_wrs = 0; 7806 txq->txpkt_wrs = 0; 7807 txq->txpkts_wrs = 0; 7808 txq->txpkts_pkts = 0; 7809 txq->br->br_drops = 0; 7810 txq->no_dmamap = 0; 7811 txq->no_desc = 0; 7812 } 7813 7814 #ifdef TCP_OFFLOAD 7815 /* nothing to clear for each ofld_rxq */ 7816 7817 for_each_ofld_txq(pi, i, wrq) { 7818 wrq->tx_wrs = 0; 7819 wrq->no_desc = 0; 7820 } 7821 #endif 7822 wrq = &sc->sge.ctrlq[pi->port_id]; 7823 wrq->tx_wrs = 0; 7824 wrq->no_desc = 0; 7825 } 7826 break; 7827 } 7828 case CHELSIO_T4_SCHED_CLASS: 7829 rc = set_sched_class(sc, (struct t4_sched_params *)data); 7830 break; 7831 case CHELSIO_T4_SCHED_QUEUE: 7832 rc = set_sched_queue(sc, (struct t4_sched_queue *)data); 7833 break; 7834 case CHELSIO_T4_GET_TRACER: 7835 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 7836 break; 7837 case CHELSIO_T4_SET_TRACER: 7838 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 7839 break; 7840 default: 7841 rc = EINVAL; 7842 } 7843 7844 return (rc); 7845 } 7846 7847 #ifdef TCP_OFFLOAD 7848 static int 7849 toe_capability(struct port_info *pi, int enable) 7850 { 7851 int rc; 7852 struct adapter *sc = pi->adapter; 7853 7854 ASSERT_SYNCHRONIZED_OP(sc); 7855 7856 if (!is_offload(sc)) 7857 return (ENODEV); 7858 7859 if (enable) { 7860 if (!(sc->flags & FULL_INIT_DONE)) { 7861 rc = cxgbe_init_synchronized(pi); 7862 if (rc) 7863 return (rc); 7864 } 7865 7866 if (isset(&sc->offload_map, pi->port_id)) 7867 return (0); 7868 7869 if (!(sc->flags & TOM_INIT_DONE)) { 7870 rc = t4_activate_uld(sc, ULD_TOM); 7871 if (rc == EAGAIN) { 7872 log(LOG_WARNING, 7873 "You must kldload t4_tom.ko before trying " 7874 "to enable TOE on a cxgbe interface.\n"); 7875 } 7876 if (rc != 0) 7877 return (rc); 7878 KASSERT(sc->tom_softc != NULL, 7879 ("%s: TOM activated but softc NULL", __func__)); 7880 KASSERT(sc->flags & TOM_INIT_DONE, 7881 ("%s: TOM activated but flag not set", __func__)); 7882 } 7883 7884 setbit(&sc->offload_map, pi->port_id); 7885 } else { 7886 if (!isset(&sc->offload_map, pi->port_id)) 7887 return (0); 7888 7889 KASSERT(sc->flags & TOM_INIT_DONE, 7890 ("%s: TOM never initialized?", __func__)); 7891 clrbit(&sc->offload_map, pi->port_id); 7892 } 7893 7894 return (0); 7895 } 7896 7897 /* 7898 * Add an upper layer driver to the global list. 7899 */ 7900 int 7901 t4_register_uld(struct uld_info *ui) 7902 { 7903 int rc = 0; 7904 struct uld_info *u; 7905 7906 sx_xlock(&t4_uld_list_lock); 7907 SLIST_FOREACH(u, &t4_uld_list, link) { 7908 if (u->uld_id == ui->uld_id) { 7909 rc = EEXIST; 7910 goto done; 7911 } 7912 } 7913 7914 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 7915 ui->refcount = 0; 7916 done: 7917 sx_xunlock(&t4_uld_list_lock); 7918 return (rc); 7919 } 7920 7921 int 7922 t4_unregister_uld(struct uld_info *ui) 7923 { 7924 int rc = EINVAL; 7925 struct uld_info *u; 7926 7927 sx_xlock(&t4_uld_list_lock); 7928 7929 SLIST_FOREACH(u, &t4_uld_list, link) { 7930 if (u == ui) { 7931 if (ui->refcount > 0) { 7932 rc = EBUSY; 7933 goto done; 7934 } 7935 7936 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 7937 rc = 0; 7938 goto done; 7939 } 7940 } 7941 done: 7942 sx_xunlock(&t4_uld_list_lock); 7943 return (rc); 7944 } 7945 7946 int 7947 t4_activate_uld(struct adapter *sc, int id) 7948 { 7949 int rc = EAGAIN; 7950 struct uld_info *ui; 7951 7952 ASSERT_SYNCHRONIZED_OP(sc); 7953 7954 sx_slock(&t4_uld_list_lock); 7955 7956 SLIST_FOREACH(ui, &t4_uld_list, link) { 7957 if (ui->uld_id == id) { 7958 rc = ui->activate(sc); 7959 if (rc == 0) 7960 ui->refcount++; 7961 goto done; 7962 } 7963 } 7964 done: 7965 sx_sunlock(&t4_uld_list_lock); 7966 7967 return (rc); 7968 } 7969 7970 int 7971 t4_deactivate_uld(struct adapter *sc, int id) 7972 { 7973 int rc = EINVAL; 7974 struct uld_info *ui; 7975 7976 ASSERT_SYNCHRONIZED_OP(sc); 7977 7978 sx_slock(&t4_uld_list_lock); 7979 7980 SLIST_FOREACH(ui, &t4_uld_list, link) { 7981 if (ui->uld_id == id) { 7982 rc = ui->deactivate(sc); 7983 if (rc == 0) 7984 ui->refcount--; 7985 goto done; 7986 } 7987 } 7988 done: 7989 sx_sunlock(&t4_uld_list_lock); 7990 7991 return (rc); 7992 } 7993 #endif 7994 7995 /* 7996 * Come up with reasonable defaults for some of the tunables, provided they're 7997 * not set by the user (in which case we'll use the values as is). 7998 */ 7999 static void 8000 tweak_tunables(void) 8001 { 8002 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 8003 8004 if (t4_ntxq10g < 1) 8005 t4_ntxq10g = min(nc, NTXQ_10G); 8006 8007 if (t4_ntxq1g < 1) 8008 t4_ntxq1g = min(nc, NTXQ_1G); 8009 8010 if (t4_nrxq10g < 1) 8011 t4_nrxq10g = min(nc, NRXQ_10G); 8012 8013 if (t4_nrxq1g < 1) 8014 t4_nrxq1g = min(nc, NRXQ_1G); 8015 8016 #ifdef TCP_OFFLOAD 8017 if (t4_nofldtxq10g < 1) 8018 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G); 8019 8020 if (t4_nofldtxq1g < 1) 8021 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G); 8022 8023 if (t4_nofldrxq10g < 1) 8024 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G); 8025 8026 if (t4_nofldrxq1g < 1) 8027 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G); 8028 8029 if (t4_toecaps_allowed == -1) 8030 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 8031 #else 8032 if (t4_toecaps_allowed == -1) 8033 t4_toecaps_allowed = 0; 8034 #endif 8035 8036 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS) 8037 t4_tmr_idx_10g = TMR_IDX_10G; 8038 8039 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS) 8040 t4_pktc_idx_10g = PKTC_IDX_10G; 8041 8042 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS) 8043 t4_tmr_idx_1g = TMR_IDX_1G; 8044 8045 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS) 8046 t4_pktc_idx_1g = PKTC_IDX_1G; 8047 8048 if (t4_qsize_txq < 128) 8049 t4_qsize_txq = 128; 8050 8051 if (t4_qsize_rxq < 128) 8052 t4_qsize_rxq = 128; 8053 while (t4_qsize_rxq & 7) 8054 t4_qsize_rxq++; 8055 8056 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 8057 } 8058 8059 static int 8060 mod_event(module_t mod, int cmd, void *arg) 8061 { 8062 int rc = 0; 8063 static int loaded = 0; 8064 8065 switch (cmd) { 8066 case MOD_LOAD: 8067 if (atomic_fetchadd_int(&loaded, 1)) 8068 break; 8069 t4_sge_modload(); 8070 sx_init(&t4_list_lock, "T4/T5 adapters"); 8071 SLIST_INIT(&t4_list); 8072 #ifdef TCP_OFFLOAD 8073 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 8074 SLIST_INIT(&t4_uld_list); 8075 #endif 8076 t4_tracer_modload(); 8077 tweak_tunables(); 8078 break; 8079 8080 case MOD_UNLOAD: 8081 if (atomic_fetchadd_int(&loaded, -1) > 1) 8082 break; 8083 t4_tracer_modunload(); 8084 #ifdef TCP_OFFLOAD 8085 sx_slock(&t4_uld_list_lock); 8086 if (!SLIST_EMPTY(&t4_uld_list)) { 8087 rc = EBUSY; 8088 sx_sunlock(&t4_uld_list_lock); 8089 break; 8090 } 8091 sx_sunlock(&t4_uld_list_lock); 8092 sx_destroy(&t4_uld_list_lock); 8093 #endif 8094 sx_slock(&t4_list_lock); 8095 if (!SLIST_EMPTY(&t4_list)) { 8096 rc = EBUSY; 8097 sx_sunlock(&t4_list_lock); 8098 break; 8099 } 8100 sx_sunlock(&t4_list_lock); 8101 sx_destroy(&t4_list_lock); 8102 break; 8103 } 8104 8105 return (rc); 8106 } 8107 8108 static devclass_t t4_devclass, t5_devclass; 8109 static devclass_t cxgbe_devclass, cxl_devclass; 8110 8111 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 8112 MODULE_VERSION(t4nex, 1); 8113 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 8114 8115 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 8116 MODULE_VERSION(t5nex, 1); 8117 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 8118 8119 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 8120 MODULE_VERSION(cxgbe, 1); 8121 8122 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 8123 MODULE_VERSION(cxl, 1); 8124