1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 33 #include <sys/param.h> 34 #include <sys/conf.h> 35 #include <sys/priv.h> 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/module.h> 39 #include <sys/pciio.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pci_private.h> 43 #include <sys/firmware.h> 44 #include <sys/smp.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <net/ethernet.h> 49 #include <net/if.h> 50 #include <net/if_types.h> 51 #include <net/if_dl.h> 52 53 #include "common/t4_hw.h" 54 #include "common/common.h" 55 #include "common/t4_regs.h" 56 #include "common/t4_regs_values.h" 57 #include "common/t4fw_interface.h" 58 #include "t4_ioctl.h" 59 60 /* T4 bus driver interface */ 61 static int t4_probe(device_t); 62 static int t4_attach(device_t); 63 static int t4_detach(device_t); 64 static device_method_t t4_methods[] = { 65 DEVMETHOD(device_probe, t4_probe), 66 DEVMETHOD(device_attach, t4_attach), 67 DEVMETHOD(device_detach, t4_detach), 68 69 /* bus interface */ 70 DEVMETHOD(bus_print_child, bus_generic_print_child), 71 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 72 73 { 0, 0 } 74 }; 75 static driver_t t4_driver = { 76 "t4nex", 77 t4_methods, 78 sizeof(struct adapter) 79 }; 80 81 82 /* T4 port (cxgbe) interface */ 83 static int cxgbe_probe(device_t); 84 static int cxgbe_attach(device_t); 85 static int cxgbe_detach(device_t); 86 static device_method_t cxgbe_methods[] = { 87 DEVMETHOD(device_probe, cxgbe_probe), 88 DEVMETHOD(device_attach, cxgbe_attach), 89 DEVMETHOD(device_detach, cxgbe_detach), 90 { 0, 0 } 91 }; 92 static driver_t cxgbe_driver = { 93 "cxgbe", 94 cxgbe_methods, 95 sizeof(struct port_info) 96 }; 97 98 static d_ioctl_t t4_ioctl; 99 static d_open_t t4_open; 100 static d_close_t t4_close; 101 102 static struct cdevsw t4_cdevsw = { 103 .d_version = D_VERSION, 104 .d_flags = 0, 105 .d_open = t4_open, 106 .d_close = t4_close, 107 .d_ioctl = t4_ioctl, 108 .d_name = "t4nex", 109 }; 110 111 /* ifnet + media interface */ 112 static void cxgbe_init(void *); 113 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 114 static void cxgbe_start(struct ifnet *); 115 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 116 static void cxgbe_qflush(struct ifnet *); 117 static int cxgbe_media_change(struct ifnet *); 118 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 119 120 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4 Ethernet driver and services"); 121 122 /* 123 * Tunables. 124 */ 125 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe driver parameters"); 126 127 static int force_firmware_install = 0; 128 TUNABLE_INT("hw.cxgbe.force_firmware_install", &force_firmware_install); 129 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, force_firmware_install, CTLFLAG_RDTUN, 130 &force_firmware_install, 0, "install firmware on every attach."); 131 132 /* 133 * Holdoff timer and packet counter values. 134 */ 135 static unsigned int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 136 static unsigned int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 137 138 /* 139 * Max # of tx and rx queues to use for each 10G and 1G port. 140 */ 141 static unsigned int max_ntxq_10g = 8; 142 TUNABLE_INT("hw.cxgbe.max_ntxq_10G_port", &max_ntxq_10g); 143 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_ntxq_10G_port, CTLFLAG_RDTUN, 144 &max_ntxq_10g, 0, "maximum number of tx queues per 10G port."); 145 146 static unsigned int max_nrxq_10g = 8; 147 TUNABLE_INT("hw.cxgbe.max_nrxq_10G_port", &max_nrxq_10g); 148 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_nrxq_10G_port, CTLFLAG_RDTUN, 149 &max_nrxq_10g, 0, "maximum number of rxq's (per 10G port)."); 150 151 static unsigned int max_ntxq_1g = 2; 152 TUNABLE_INT("hw.cxgbe.max_ntxq_1G_port", &max_ntxq_1g); 153 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_ntxq_1G_port, CTLFLAG_RDTUN, 154 &max_ntxq_1g, 0, "maximum number of tx queues per 1G port."); 155 156 static unsigned int max_nrxq_1g = 2; 157 TUNABLE_INT("hw.cxgbe.max_nrxq_1G_port", &max_nrxq_1g); 158 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_nrxq_1G_port, CTLFLAG_RDTUN, 159 &max_nrxq_1g, 0, "maximum number of rxq's (per 1G port)."); 160 161 /* 162 * Holdoff parameters for 10G and 1G ports. 163 */ 164 static unsigned int tmr_idx_10g = 1; 165 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &tmr_idx_10g); 166 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_10G, CTLFLAG_RDTUN, 167 &tmr_idx_10g, 0, 168 "default timer index for interrupt holdoff (10G ports)."); 169 170 static int pktc_idx_10g = 2; 171 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &pktc_idx_10g); 172 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_10G, CTLFLAG_RDTUN, 173 &pktc_idx_10g, 0, 174 "default pkt counter index for interrupt holdoff (10G ports)."); 175 176 static unsigned int tmr_idx_1g = 1; 177 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &tmr_idx_1g); 178 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_1G, CTLFLAG_RDTUN, 179 &tmr_idx_1g, 0, 180 "default timer index for interrupt holdoff (1G ports)."); 181 182 static int pktc_idx_1g = 2; 183 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &pktc_idx_1g); 184 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_1G, CTLFLAG_RDTUN, 185 &pktc_idx_1g, 0, 186 "default pkt counter index for interrupt holdoff (1G ports)."); 187 188 /* 189 * Size (# of entries) of each tx and rx queue. 190 */ 191 static unsigned int qsize_txq = TX_EQ_QSIZE; 192 TUNABLE_INT("hw.cxgbe.qsize_txq", &qsize_txq); 193 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, 194 &qsize_txq, 0, "default queue size of NIC tx queues."); 195 196 static unsigned int qsize_rxq = RX_IQ_QSIZE; 197 TUNABLE_INT("hw.cxgbe.qsize_rxq", &qsize_rxq); 198 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, 199 &qsize_rxq, 0, "default queue size of NIC rx queues."); 200 201 /* 202 * Interrupt types allowed. 203 */ 204 static int intr_types = 7; 205 TUNABLE_INT("hw.cxgbe.interrupt_types", &intr_types); 206 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &intr_types, 0, 207 "interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively)"); 208 209 /* 210 * Force the driver to use interrupt forwarding. 211 */ 212 static int intr_fwd = 0; 213 TUNABLE_INT("hw.cxgbe.interrupt_forwarding", &intr_fwd); 214 SYSCTL_UINT(_hw_cxgbe, OID_AUTO, interrupt_forwarding, CTLFLAG_RDTUN, 215 &intr_fwd, 0, "always use forwarded interrupts"); 216 217 struct intrs_and_queues { 218 int intr_type; /* 1, 2, or 4 for INTx, MSI, or MSI-X */ 219 int nirq; /* Number of vectors */ 220 int intr_fwd; /* Interrupts forwarded */ 221 int ntxq10g; /* # of NIC txq's for each 10G port */ 222 int nrxq10g; /* # of NIC rxq's for each 10G port */ 223 int ntxq1g; /* # of NIC txq's for each 1G port */ 224 int nrxq1g; /* # of NIC rxq's for each 1G port */ 225 }; 226 227 enum { 228 MEMWIN0_APERTURE = 2048, 229 MEMWIN0_BASE = 0x1b800, 230 MEMWIN1_APERTURE = 32768, 231 MEMWIN1_BASE = 0x28000, 232 MEMWIN2_APERTURE = 65536, 233 MEMWIN2_BASE = 0x30000, 234 }; 235 236 enum { 237 XGMAC_MTU = (1 << 0), 238 XGMAC_PROMISC = (1 << 1), 239 XGMAC_ALLMULTI = (1 << 2), 240 XGMAC_VLANEX = (1 << 3), 241 XGMAC_UCADDR = (1 << 4), 242 XGMAC_MCADDRS = (1 << 5), 243 244 XGMAC_ALL = 0xffff 245 }; 246 247 static int map_bars(struct adapter *); 248 static void setup_memwin(struct adapter *); 249 static int cfg_itype_and_nqueues(struct adapter *, int, int, 250 struct intrs_and_queues *); 251 static int prep_firmware(struct adapter *); 252 static int get_capabilities(struct adapter *, struct fw_caps_config_cmd *); 253 static int get_params(struct adapter *, struct fw_caps_config_cmd *); 254 static void t4_set_desc(struct adapter *); 255 static void build_medialist(struct port_info *); 256 static int update_mac_settings(struct port_info *, int); 257 static int cxgbe_init_locked(struct port_info *); 258 static int cxgbe_init_synchronized(struct port_info *); 259 static int cxgbe_uninit_locked(struct port_info *); 260 static int cxgbe_uninit_synchronized(struct port_info *); 261 static int first_port_up(struct adapter *); 262 static int last_port_down(struct adapter *); 263 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 264 iq_intr_handler_t *, void *, char *); 265 static int t4_free_irq(struct adapter *, struct irq *); 266 static void reg_block_dump(struct adapter *, uint8_t *, unsigned int, 267 unsigned int); 268 static void t4_get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 269 static void cxgbe_tick(void *); 270 static int t4_sysctls(struct adapter *); 271 static int cxgbe_sysctls(struct port_info *); 272 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 273 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 274 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 275 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 276 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 277 278 279 struct t4_pciids { 280 uint16_t device; 281 uint8_t mpf; 282 char *desc; 283 } t4_pciids[] = { 284 {0xa000, 0, "Chelsio Terminator 4 FPGA"}, 285 {0x4400, 4, "Chelsio T440-dbg"}, 286 {0x4401, 4, "Chelsio T420-CR"}, 287 {0x4402, 4, "Chelsio T422-CR"}, 288 {0x4403, 4, "Chelsio T440-CR"}, 289 {0x4404, 4, "Chelsio T420-BCH"}, 290 {0x4405, 4, "Chelsio T440-BCH"}, 291 {0x4406, 4, "Chelsio T440-CH"}, 292 {0x4407, 4, "Chelsio T420-SO"}, 293 {0x4408, 4, "Chelsio T420-CX"}, 294 {0x4409, 4, "Chelsio T420-BT"}, 295 {0x440a, 4, "Chelsio T404-BT"}, 296 }; 297 298 static int 299 t4_probe(device_t dev) 300 { 301 int i; 302 uint16_t v = pci_get_vendor(dev); 303 uint16_t d = pci_get_device(dev); 304 305 if (v != PCI_VENDOR_ID_CHELSIO) 306 return (ENXIO); 307 308 for (i = 0; i < ARRAY_SIZE(t4_pciids); i++) { 309 if (d == t4_pciids[i].device && 310 pci_get_function(dev) == t4_pciids[i].mpf) { 311 device_set_desc(dev, t4_pciids[i].desc); 312 return (BUS_PROBE_DEFAULT); 313 } 314 } 315 316 return (ENXIO); 317 } 318 319 static int 320 t4_attach(device_t dev) 321 { 322 struct adapter *sc; 323 int rc = 0, i, n10g, n1g, rqidx, tqidx; 324 struct fw_caps_config_cmd caps; 325 uint32_t p, v; 326 struct intrs_and_queues iaq; 327 struct sge *s; 328 329 sc = device_get_softc(dev); 330 sc->dev = dev; 331 sc->pf = pci_get_function(dev); 332 sc->mbox = sc->pf; 333 334 pci_enable_busmaster(dev); 335 pci_set_max_read_req(dev, 4096); 336 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 337 device_get_nameunit(dev)); 338 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 339 340 rc = map_bars(sc); 341 if (rc != 0) 342 goto done; /* error message displayed already */ 343 344 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 345 346 /* Prepare the adapter for operation */ 347 rc = -t4_prep_adapter(sc); 348 if (rc != 0) { 349 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 350 goto done; 351 } 352 353 /* Do this really early */ 354 sc->cdev = make_dev(&t4_cdevsw, device_get_unit(dev), UID_ROOT, 355 GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); 356 sc->cdev->si_drv1 = sc; 357 358 /* Prepare the firmware for operation */ 359 rc = prep_firmware(sc); 360 if (rc != 0) 361 goto done; /* error message displayed already */ 362 363 /* Get device capabilities and select which ones we'll use */ 364 rc = get_capabilities(sc, &caps); 365 if (rc != 0) { 366 device_printf(dev, 367 "failed to initialize adapter capabilities: %d.\n", rc); 368 goto done; 369 } 370 371 /* Choose the global RSS mode. */ 372 rc = -t4_config_glbl_rss(sc, sc->mbox, 373 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 374 F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN | 375 F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP); 376 if (rc != 0) { 377 device_printf(dev, 378 "failed to select global RSS mode: %d.\n", rc); 379 goto done; 380 } 381 382 /* These are total (sum of all ports) limits for a bus driver */ 383 rc = -t4_cfg_pfvf(sc, sc->mbox, sc->pf, 0, 384 64, /* max # of egress queues */ 385 64, /* max # of egress Ethernet or control queues */ 386 64, /* max # of ingress queues with fl/interrupt */ 387 0, /* max # of ingress queues without interrupt */ 388 0, /* PCIe traffic class */ 389 4, /* max # of virtual interfaces */ 390 M_FW_PFVF_CMD_CMASK, M_FW_PFVF_CMD_PMASK, 16, 391 FW_CMD_CAP_PF, FW_CMD_CAP_PF); 392 if (rc != 0) { 393 device_printf(dev, 394 "failed to configure pf/vf resources: %d.\n", rc); 395 goto done; 396 } 397 398 /* Need this before sge_init */ 399 for (i = 0; i < SGE_NTIMERS; i++) 400 sc->sge.timer_val[i] = min(intr_timer[i], 200U); 401 for (i = 0; i < SGE_NCOUNTERS; i++) 402 sc->sge.counter_val[i] = min(intr_pktcount[i], M_THRESHOLD_0); 403 404 /* Also need the cooked value of cclk before sge_init */ 405 p = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 406 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK)); 407 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &p, &v); 408 if (rc != 0) { 409 device_printf(sc->dev, 410 "failed to obtain core clock value: %d.\n", rc); 411 goto done; 412 } 413 sc->params.vpd.cclk = v; 414 415 t4_sge_init(sc); 416 417 /* 418 * XXX: This is the place to call t4_set_filter_mode() 419 */ 420 421 /* get basic stuff going */ 422 rc = -t4_early_init(sc, sc->mbox); 423 if (rc != 0) { 424 device_printf(dev, "early init failed: %d.\n", rc); 425 goto done; 426 } 427 428 rc = get_params(sc, &caps); 429 if (rc != 0) 430 goto done; /* error message displayed already */ 431 432 /* These are finalized by FW initialization, load their values now */ 433 v = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 434 sc->params.tp.tre = G_TIMERRESOLUTION(v); 435 sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v); 436 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 437 438 /* tweak some settings */ 439 t4_write_reg(sc, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | V_RXTSHIFTMAXR1(4) | 440 V_RXTSHIFTMAXR2(15) | V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) | 441 V_KEEPALIVEMAXR1(4) | V_KEEPALIVEMAXR2(9)); 442 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 443 444 setup_memwin(sc); 445 446 rc = t4_create_dma_tag(sc); 447 if (rc != 0) 448 goto done; /* error message displayed already */ 449 450 /* 451 * First pass over all the ports - allocate VIs and initialize some 452 * basic parameters like mac address, port type, etc. We also figure 453 * out whether a port is 10G or 1G and use that information when 454 * calculating how many interrupts to attempt to allocate. 455 */ 456 n10g = n1g = 0; 457 for_each_port(sc, i) { 458 struct port_info *pi; 459 460 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 461 sc->port[i] = pi; 462 463 /* These must be set before t4_port_init */ 464 pi->adapter = sc; 465 pi->port_id = i; 466 467 /* Allocate the vi and initialize parameters like mac addr */ 468 rc = -t4_port_init(pi, sc->mbox, sc->pf, 0); 469 if (rc != 0) { 470 device_printf(dev, "unable to initialize port %d: %d\n", 471 i, rc); 472 free(pi, M_CXGBE); 473 sc->port[i] = NULL; /* indicates init failed */ 474 continue; 475 } 476 477 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 478 device_get_nameunit(dev), i); 479 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 480 481 if (is_10G_port(pi)) { 482 n10g++; 483 pi->tmr_idx = tmr_idx_10g; 484 pi->pktc_idx = pktc_idx_10g; 485 } else { 486 n1g++; 487 pi->tmr_idx = tmr_idx_1g; 488 pi->pktc_idx = pktc_idx_1g; 489 } 490 491 pi->xact_addr_filt = -1; 492 493 pi->qsize_rxq = max(qsize_rxq, 128); 494 while (pi->qsize_rxq & 7) 495 pi->qsize_rxq++; 496 pi->qsize_txq = max(qsize_txq, 128); 497 498 if (pi->qsize_rxq != qsize_rxq) { 499 device_printf(dev, 500 "using %d instead of %d as the rx queue size.\n", 501 pi->qsize_rxq, qsize_rxq); 502 } 503 if (pi->qsize_txq != qsize_txq) { 504 device_printf(dev, 505 "using %d instead of %d as the tx queue size.\n", 506 pi->qsize_txq, qsize_txq); 507 } 508 509 pi->dev = device_add_child(dev, "cxgbe", -1); 510 if (pi->dev == NULL) { 511 device_printf(dev, 512 "failed to add device for port %d.\n", i); 513 rc = ENXIO; 514 goto done; 515 } 516 device_set_softc(pi->dev, pi); 517 518 setbit(&sc->registered_device_map, i); 519 } 520 521 if (sc->registered_device_map == 0) { 522 device_printf(dev, "no usable ports\n"); 523 rc = ENXIO; 524 goto done; 525 } 526 527 /* 528 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 529 */ 530 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq); 531 if (rc != 0) 532 goto done; /* error message displayed already */ 533 534 sc->intr_type = iaq.intr_type; 535 sc->intr_count = iaq.nirq; 536 537 s = &sc->sge; 538 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; 539 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; 540 s->neq = s->ntxq + s->nrxq; /* the fl in an rxq is an eq */ 541 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 542 if (iaq.intr_fwd) { 543 sc->flags |= INTR_FWD; 544 s->niq += NFIQ(sc); /* forwarded interrupt queues */ 545 s->fiq = malloc(NFIQ(sc) * sizeof(struct sge_iq), M_CXGBE, 546 M_ZERO | M_WAITOK); 547 } 548 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 549 M_ZERO | M_WAITOK); 550 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 551 M_ZERO | M_WAITOK); 552 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 553 M_ZERO | M_WAITOK); 554 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 555 M_ZERO | M_WAITOK); 556 557 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 558 M_ZERO | M_WAITOK); 559 560 t4_sysctls(sc); 561 562 /* 563 * Second pass over the ports. This time we know the number of rx and 564 * tx queues that each port should get. 565 */ 566 rqidx = tqidx = 0; 567 for_each_port(sc, i) { 568 struct port_info *pi = sc->port[i]; 569 570 if (pi == NULL) 571 continue; 572 573 pi->first_rxq = rqidx; 574 pi->nrxq = is_10G_port(pi) ? iaq.nrxq10g : iaq.nrxq1g; 575 576 pi->first_txq = tqidx; 577 pi->ntxq = is_10G_port(pi) ? iaq.ntxq10g : iaq.ntxq1g; 578 579 rqidx += pi->nrxq; 580 tqidx += pi->ntxq; 581 } 582 583 rc = bus_generic_attach(dev); 584 if (rc != 0) { 585 device_printf(dev, 586 "failed to attach all child ports: %d\n", rc); 587 goto done; 588 } 589 590 #ifdef INVARIANTS 591 device_printf(dev, 592 "%p, %d ports (0x%x), %d intr_type, %d intr_count\n", 593 sc, sc->params.nports, sc->params.portvec, 594 sc->intr_type, sc->intr_count); 595 #endif 596 t4_set_desc(sc); 597 598 done: 599 if (rc != 0) 600 t4_detach(dev); 601 602 return (rc); 603 } 604 605 /* 606 * Idempotent 607 */ 608 static int 609 t4_detach(device_t dev) 610 { 611 struct adapter *sc; 612 struct port_info *pi; 613 int i; 614 615 sc = device_get_softc(dev); 616 617 if (sc->cdev) 618 destroy_dev(sc->cdev); 619 620 bus_generic_detach(dev); 621 for (i = 0; i < MAX_NPORTS; i++) { 622 pi = sc->port[i]; 623 if (pi) { 624 t4_free_vi(pi->adapter, sc->mbox, sc->pf, 0, pi->viid); 625 if (pi->dev) 626 device_delete_child(dev, pi->dev); 627 628 mtx_destroy(&pi->pi_lock); 629 free(pi, M_CXGBE); 630 } 631 } 632 633 if (sc->flags & FW_OK) 634 t4_fw_bye(sc, sc->mbox); 635 636 if (sc->intr_type == 2 || sc->intr_type == 4) 637 pci_release_msi(dev); 638 639 if (sc->regs_res) 640 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 641 sc->regs_res); 642 643 if (sc->msix_res) 644 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 645 sc->msix_res); 646 647 free(sc->irq, M_CXGBE); 648 free(sc->sge.rxq, M_CXGBE); 649 free(sc->sge.txq, M_CXGBE); 650 free(sc->sge.fiq, M_CXGBE); 651 free(sc->sge.iqmap, M_CXGBE); 652 free(sc->sge.eqmap, M_CXGBE); 653 t4_destroy_dma_tag(sc); 654 mtx_destroy(&sc->sc_lock); 655 656 bzero(sc, sizeof(*sc)); 657 658 return (0); 659 } 660 661 662 static int 663 cxgbe_probe(device_t dev) 664 { 665 char buf[128]; 666 struct port_info *pi = device_get_softc(dev); 667 668 snprintf(buf, sizeof(buf), "Port %d", pi->port_id); 669 device_set_desc_copy(dev, buf); 670 671 return (BUS_PROBE_DEFAULT); 672 } 673 674 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 675 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 676 IFCAP_VLAN_HWTSO) 677 #define T4_CAP_ENABLE (T4_CAP & ~IFCAP_TSO6) 678 679 static int 680 cxgbe_attach(device_t dev) 681 { 682 struct port_info *pi = device_get_softc(dev); 683 struct ifnet *ifp; 684 685 /* Allocate an ifnet and set it up */ 686 ifp = if_alloc(IFT_ETHER); 687 if (ifp == NULL) { 688 device_printf(dev, "Cannot allocate ifnet\n"); 689 return (ENOMEM); 690 } 691 pi->ifp = ifp; 692 ifp->if_softc = pi; 693 694 callout_init(&pi->tick, CALLOUT_MPSAFE); 695 696 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 697 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 698 699 ifp->if_init = cxgbe_init; 700 ifp->if_ioctl = cxgbe_ioctl; 701 ifp->if_start = cxgbe_start; 702 ifp->if_transmit = cxgbe_transmit; 703 ifp->if_qflush = cxgbe_qflush; 704 705 ifp->if_snd.ifq_drv_maxlen = 1024; 706 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 707 IFQ_SET_READY(&ifp->if_snd); 708 709 ifp->if_capabilities = T4_CAP; 710 ifp->if_capenable = T4_CAP_ENABLE; 711 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO; 712 713 /* Initialize ifmedia for this port */ 714 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 715 cxgbe_media_status); 716 build_medialist(pi); 717 718 ether_ifattach(ifp, pi->hw_addr); 719 720 #ifdef INVARIANTS 721 device_printf(dev, "%p, %d txq, %d rxq\n", pi, pi->ntxq, pi->nrxq); 722 #endif 723 724 cxgbe_sysctls(pi); 725 726 return (0); 727 } 728 729 static int 730 cxgbe_detach(device_t dev) 731 { 732 struct port_info *pi = device_get_softc(dev); 733 struct adapter *sc = pi->adapter; 734 int rc; 735 736 /* Tell if_ioctl and if_init that the port is going away */ 737 ADAPTER_LOCK(sc); 738 SET_DOOMED(pi); 739 wakeup(&sc->flags); 740 while (IS_BUSY(sc)) 741 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 742 SET_BUSY(sc); 743 ADAPTER_UNLOCK(sc); 744 745 rc = cxgbe_uninit_synchronized(pi); 746 if (rc != 0) 747 device_printf(dev, "port uninit failed: %d.\n", rc); 748 749 ifmedia_removeall(&pi->media); 750 ether_ifdetach(pi->ifp); 751 if_free(pi->ifp); 752 753 ADAPTER_LOCK(sc); 754 CLR_BUSY(sc); 755 wakeup_one(&sc->flags); 756 ADAPTER_UNLOCK(sc); 757 758 return (0); 759 } 760 761 static void 762 cxgbe_init(void *arg) 763 { 764 struct port_info *pi = arg; 765 struct adapter *sc = pi->adapter; 766 767 ADAPTER_LOCK(sc); 768 cxgbe_init_locked(pi); /* releases adapter lock */ 769 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 770 } 771 772 static int 773 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 774 { 775 int rc = 0, mtu, flags; 776 struct port_info *pi = ifp->if_softc; 777 struct adapter *sc = pi->adapter; 778 struct ifreq *ifr = (struct ifreq *)data; 779 uint32_t mask; 780 781 switch (cmd) { 782 case SIOCSIFMTU: 783 ADAPTER_LOCK(sc); 784 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 785 if (rc) { 786 fail: 787 ADAPTER_UNLOCK(sc); 788 return (rc); 789 } 790 791 mtu = ifr->ifr_mtu; 792 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) { 793 rc = EINVAL; 794 } else { 795 ifp->if_mtu = mtu; 796 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 797 t4_update_fl_bufsize(ifp); 798 PORT_LOCK(pi); 799 rc = update_mac_settings(pi, XGMAC_MTU); 800 PORT_UNLOCK(pi); 801 } 802 } 803 ADAPTER_UNLOCK(sc); 804 break; 805 806 case SIOCSIFFLAGS: 807 ADAPTER_LOCK(sc); 808 if (IS_DOOMED(pi)) { 809 rc = ENXIO; 810 goto fail; 811 } 812 if (ifp->if_flags & IFF_UP) { 813 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 814 flags = pi->if_flags; 815 if ((ifp->if_flags ^ flags) & 816 (IFF_PROMISC | IFF_ALLMULTI)) { 817 if (IS_BUSY(sc)) { 818 rc = EBUSY; 819 goto fail; 820 } 821 PORT_LOCK(pi); 822 rc = update_mac_settings(pi, 823 XGMAC_PROMISC | XGMAC_ALLMULTI); 824 PORT_UNLOCK(pi); 825 } 826 ADAPTER_UNLOCK(sc); 827 } else 828 rc = cxgbe_init_locked(pi); 829 pi->if_flags = ifp->if_flags; 830 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 831 rc = cxgbe_uninit_locked(pi); 832 else 833 ADAPTER_UNLOCK(sc); 834 835 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 836 break; 837 838 case SIOCADDMULTI: 839 case SIOCDELMULTI: /* these two can be called with a mutex held :-( */ 840 ADAPTER_LOCK(sc); 841 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 842 if (rc) 843 goto fail; 844 845 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 846 PORT_LOCK(pi); 847 rc = update_mac_settings(pi, XGMAC_MCADDRS); 848 PORT_UNLOCK(pi); 849 } 850 ADAPTER_UNLOCK(sc); 851 break; 852 853 case SIOCSIFCAP: 854 ADAPTER_LOCK(sc); 855 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 856 if (rc) 857 goto fail; 858 859 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 860 if (mask & IFCAP_TXCSUM) { 861 ifp->if_capenable ^= IFCAP_TXCSUM; 862 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 863 864 if (IFCAP_TSO & ifp->if_capenable && 865 !(IFCAP_TXCSUM & ifp->if_capenable)) { 866 ifp->if_capenable &= ~IFCAP_TSO; 867 ifp->if_hwassist &= ~CSUM_TSO; 868 if_printf(ifp, 869 "tso disabled due to -txcsum.\n"); 870 } 871 } 872 if (mask & IFCAP_RXCSUM) 873 ifp->if_capenable ^= IFCAP_RXCSUM; 874 if (mask & IFCAP_TSO4) { 875 ifp->if_capenable ^= IFCAP_TSO4; 876 877 if (IFCAP_TSO & ifp->if_capenable) { 878 if (IFCAP_TXCSUM & ifp->if_capenable) 879 ifp->if_hwassist |= CSUM_TSO; 880 else { 881 ifp->if_capenable &= ~IFCAP_TSO; 882 ifp->if_hwassist &= ~CSUM_TSO; 883 if_printf(ifp, 884 "enable txcsum first.\n"); 885 rc = EAGAIN; 886 } 887 } else 888 ifp->if_hwassist &= ~CSUM_TSO; 889 } 890 if (mask & IFCAP_LRO) { 891 #ifdef INET 892 int i; 893 struct sge_rxq *rxq; 894 895 ifp->if_capenable ^= IFCAP_LRO; 896 for_each_rxq(pi, i, rxq) { 897 if (ifp->if_capenable & IFCAP_LRO) 898 rxq->flags |= RXQ_LRO_ENABLED; 899 else 900 rxq->flags &= ~RXQ_LRO_ENABLED; 901 } 902 #endif 903 } 904 #ifndef TCP_OFFLOAD_DISABLE 905 if (mask & IFCAP_TOE4) { 906 rc = EOPNOTSUPP; 907 } 908 #endif 909 if (mask & IFCAP_VLAN_HWTAGGING) { 910 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 911 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 912 PORT_LOCK(pi); 913 rc = update_mac_settings(pi, XGMAC_VLANEX); 914 PORT_UNLOCK(pi); 915 } 916 } 917 if (mask & IFCAP_VLAN_MTU) { 918 ifp->if_capenable ^= IFCAP_VLAN_MTU; 919 920 /* Need to find out how to disable auto-mtu-inflation */ 921 } 922 if (mask & IFCAP_VLAN_HWTSO) 923 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 924 if (mask & IFCAP_VLAN_HWCSUM) 925 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 926 927 #ifdef VLAN_CAPABILITIES 928 VLAN_CAPABILITIES(ifp); 929 #endif 930 ADAPTER_UNLOCK(sc); 931 break; 932 933 case SIOCSIFMEDIA: 934 case SIOCGIFMEDIA: 935 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 936 break; 937 938 default: 939 rc = ether_ioctl(ifp, cmd, data); 940 } 941 942 return (rc); 943 } 944 945 static void 946 cxgbe_start(struct ifnet *ifp) 947 { 948 struct port_info *pi = ifp->if_softc; 949 struct sge_txq *txq; 950 int i; 951 952 for_each_txq(pi, i, txq) { 953 if (TXQ_TRYLOCK(txq)) { 954 struct buf_ring *br = txq->eq.br; 955 struct mbuf *m; 956 957 m = txq->m ? txq->m : drbr_dequeue(ifp, br); 958 if (m) 959 t4_eth_tx(ifp, txq, m); 960 961 TXQ_UNLOCK(txq); 962 } 963 } 964 } 965 966 static int 967 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 968 { 969 struct port_info *pi = ifp->if_softc; 970 struct adapter *sc = pi->adapter; 971 struct sge_txq *txq = &sc->sge.txq[pi->first_txq]; 972 struct buf_ring *br; 973 int rc; 974 975 M_ASSERTPKTHDR(m); 976 977 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 978 m_freem(m); 979 return (0); 980 } 981 982 if (m->m_flags & M_FLOWID) 983 txq += (m->m_pkthdr.flowid % pi->ntxq); 984 br = txq->eq.br; 985 986 if (TXQ_TRYLOCK(txq) == 0) { 987 /* 988 * XXX: make sure that this packet really is sent out. There is 989 * a small race where t4_eth_tx may stop draining the drbr and 990 * goes away, just before we enqueued this mbuf. 991 */ 992 993 return (drbr_enqueue(ifp, br, m)); 994 } 995 996 /* 997 * txq->m is the mbuf that is held up due to a temporary shortage of 998 * resources and it should be put on the wire first. Then what's in 999 * drbr and finally the mbuf that was just passed in to us. 1000 * 1001 * Return code should indicate the fate of the mbuf that was passed in 1002 * this time. 1003 */ 1004 1005 TXQ_LOCK_ASSERT_OWNED(txq); 1006 if (drbr_needs_enqueue(ifp, br) || txq->m) { 1007 1008 /* Queued for transmission. */ 1009 1010 rc = drbr_enqueue(ifp, br, m); 1011 m = txq->m ? txq->m : drbr_dequeue(ifp, br); 1012 (void) t4_eth_tx(ifp, txq, m); 1013 TXQ_UNLOCK(txq); 1014 return (rc); 1015 } 1016 1017 /* Direct transmission. */ 1018 rc = t4_eth_tx(ifp, txq, m); 1019 if (rc != 0 && txq->m) 1020 rc = 0; /* held, will be transmitted soon (hopefully) */ 1021 1022 TXQ_UNLOCK(txq); 1023 return (rc); 1024 } 1025 1026 static void 1027 cxgbe_qflush(struct ifnet *ifp) 1028 { 1029 struct port_info *pi = ifp->if_softc; 1030 1031 device_printf(pi->dev, "%s unimplemented.\n", __func__); 1032 } 1033 1034 static int 1035 cxgbe_media_change(struct ifnet *ifp) 1036 { 1037 struct port_info *pi = ifp->if_softc; 1038 1039 device_printf(pi->dev, "%s unimplemented.\n", __func__); 1040 1041 return (EOPNOTSUPP); 1042 } 1043 1044 static void 1045 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1046 { 1047 struct port_info *pi = ifp->if_softc; 1048 struct ifmedia_entry *cur = pi->media.ifm_cur; 1049 int speed = pi->link_cfg.speed; 1050 int data = (pi->port_type << 8) | pi->mod_type; 1051 1052 if (cur->ifm_data != data) { 1053 build_medialist(pi); 1054 cur = pi->media.ifm_cur; 1055 } 1056 1057 ifmr->ifm_status = IFM_AVALID; 1058 if (!pi->link_cfg.link_ok) 1059 return; 1060 1061 ifmr->ifm_status |= IFM_ACTIVE; 1062 1063 /* active and current will differ iff current media is autoselect. */ 1064 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 1065 return; 1066 1067 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 1068 if (speed == SPEED_10000) 1069 ifmr->ifm_active |= IFM_10G_T; 1070 else if (speed == SPEED_1000) 1071 ifmr->ifm_active |= IFM_1000_T; 1072 else if (speed == SPEED_100) 1073 ifmr->ifm_active |= IFM_100_TX; 1074 else if (speed == SPEED_10) 1075 ifmr->ifm_active |= IFM_10_T; 1076 else 1077 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 1078 speed)); 1079 } 1080 1081 void 1082 t4_fatal_err(struct adapter *sc) 1083 { 1084 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 1085 t4_intr_disable(sc); 1086 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 1087 device_get_nameunit(sc->dev)); 1088 } 1089 1090 static int 1091 map_bars(struct adapter *sc) 1092 { 1093 sc->regs_rid = PCIR_BAR(0); 1094 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1095 &sc->regs_rid, RF_ACTIVE); 1096 if (sc->regs_res == NULL) { 1097 device_printf(sc->dev, "cannot map registers.\n"); 1098 return (ENXIO); 1099 } 1100 sc->bt = rman_get_bustag(sc->regs_res); 1101 sc->bh = rman_get_bushandle(sc->regs_res); 1102 sc->mmio_len = rman_get_size(sc->regs_res); 1103 1104 sc->msix_rid = PCIR_BAR(4); 1105 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1106 &sc->msix_rid, RF_ACTIVE); 1107 if (sc->msix_res == NULL) { 1108 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 1109 return (ENXIO); 1110 } 1111 1112 return (0); 1113 } 1114 1115 static void 1116 setup_memwin(struct adapter *sc) 1117 { 1118 u_long bar0; 1119 1120 bar0 = rman_get_start(sc->regs_res); 1121 1122 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0), 1123 (bar0 + MEMWIN0_BASE) | V_BIR(0) | 1124 V_WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); 1125 1126 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1), 1127 (bar0 + MEMWIN1_BASE) | V_BIR(0) | 1128 V_WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); 1129 1130 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2), 1131 (bar0 + MEMWIN2_BASE) | V_BIR(0) | 1132 V_WINDOW(ilog2(MEMWIN2_APERTURE) - 10)); 1133 } 1134 1135 static int 1136 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 1137 struct intrs_and_queues *iaq) 1138 { 1139 int rc, itype, navail, nc, nrxq10g, nrxq1g; 1140 1141 bzero(iaq, sizeof(*iaq)); 1142 nc = mp_ncpus; /* our snapshot of the number of CPUs */ 1143 1144 for (itype = 4; itype; itype >>= 1) { 1145 1146 if ((itype & intr_types) == 0) 1147 continue; /* not allowed */ 1148 1149 if (itype == 4) 1150 navail = pci_msix_count(sc->dev); 1151 else if (itype == 2) 1152 navail = pci_msi_count(sc->dev); 1153 else 1154 navail = 1; 1155 1156 if (navail == 0) 1157 continue; 1158 1159 iaq->intr_type = itype; 1160 1161 iaq->ntxq10g = min(nc, max_ntxq_10g); 1162 iaq->ntxq1g = min(nc, max_ntxq_1g); 1163 1164 nrxq10g = min(nc, max_nrxq_10g); 1165 nrxq1g = min(nc, max_nrxq_1g); 1166 1167 /* Extra 2 is for a) error interrupt b) firmware event */ 1168 iaq->nirq = n10g * nrxq10g + n1g * nrxq1g + 2; 1169 if (iaq->nirq <= navail && intr_fwd == 0) { 1170 1171 /* One for err, one for fwq, and one for each rxq */ 1172 1173 iaq->intr_fwd = 0; 1174 iaq->nrxq10g = nrxq10g; 1175 iaq->nrxq1g = nrxq1g; 1176 if (itype == 2) { 1177 /* # of vectors requested must be power of 2 */ 1178 while (!powerof2(iaq->nirq)) 1179 iaq->nirq++; 1180 KASSERT(iaq->nirq <= navail, 1181 ("%s: bad MSI calculation", __func__)); 1182 } 1183 } else { 1184 fwd: 1185 iaq->intr_fwd = 1; 1186 iaq->nirq = navail; 1187 1188 /* 1189 * If we have multiple vectors available reserve one 1190 * exclusively for errors. The rest will be shared by 1191 * the fwq and data. 1192 */ 1193 if (navail > 1) { 1194 navail--; 1195 1196 if (navail > nc && itype == 4) 1197 iaq->nirq = nc + 1; 1198 } 1199 1200 iaq->nrxq10g = min(nrxq10g, navail); 1201 iaq->nrxq1g = min(nrxq1g, navail); 1202 } 1203 1204 navail = iaq->nirq; 1205 rc = 0; 1206 if (itype == 4) 1207 rc = pci_alloc_msix(sc->dev, &navail); 1208 else if (itype == 2) 1209 rc = pci_alloc_msi(sc->dev, &navail); 1210 1211 if (rc == 0) { 1212 if (navail == iaq->nirq) 1213 return (0); 1214 1215 /* 1216 * Didn't get the number requested. Use whatever number 1217 * the kernel is willing to allocate (it's in navail). 1218 */ 1219 pci_release_msi(sc->dev); 1220 goto fwd; 1221 } 1222 1223 device_printf(sc->dev, 1224 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 1225 itype, rc, iaq->nirq, navail); 1226 } 1227 1228 device_printf(sc->dev, 1229 "failed to find a usable interrupt type. " 1230 "allowed=%d, msi-x=%d, msi=%d, intx=1", intr_types, 1231 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 1232 1233 return (ENXIO); 1234 } 1235 1236 /* 1237 * Install a compatible firmware (if required), establish contact with it, 1238 * become the master, and reset the device. 1239 */ 1240 static int 1241 prep_firmware(struct adapter *sc) 1242 { 1243 const struct firmware *fw; 1244 int rc; 1245 enum dev_state state; 1246 1247 /* Check firmware version and install a different one if necessary */ 1248 rc = t4_check_fw_version(sc); 1249 if (rc != 0 || force_firmware_install) { 1250 1251 fw = firmware_get(T4_FWNAME); 1252 if (fw == NULL) { 1253 device_printf(sc->dev, 1254 "Could not find firmware image %s\n", T4_FWNAME); 1255 return (ENOENT); 1256 } 1257 1258 device_printf(sc->dev, 1259 "installing firmware %d.%d.%d on card.\n", 1260 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 1261 rc = -t4_load_fw(sc, fw->data, fw->datasize); 1262 if (rc != 0) { 1263 device_printf(sc->dev, 1264 "failed to install firmware: %d\n", rc); 1265 return (rc); 1266 } else { 1267 t4_get_fw_version(sc, &sc->params.fw_vers); 1268 t4_get_tp_version(sc, &sc->params.tp_vers); 1269 } 1270 1271 firmware_put(fw, FIRMWARE_UNLOAD); 1272 } 1273 1274 /* Contact firmware, request master */ 1275 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MUST, &state); 1276 if (rc < 0) { 1277 rc = -rc; 1278 device_printf(sc->dev, 1279 "failed to connect to the firmware: %d.\n", rc); 1280 return (rc); 1281 } 1282 1283 /* Reset device */ 1284 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 1285 if (rc != 0) { 1286 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 1287 if (rc != ETIMEDOUT && rc != EIO) 1288 t4_fw_bye(sc, sc->mbox); 1289 return (rc); 1290 } 1291 1292 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 1293 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 1294 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 1295 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 1296 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 1297 sc->flags |= FW_OK; 1298 1299 return (0); 1300 } 1301 1302 static int 1303 get_capabilities(struct adapter *sc, struct fw_caps_config_cmd *caps) 1304 { 1305 int rc; 1306 1307 bzero(caps, sizeof(*caps)); 1308 caps->op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1309 F_FW_CMD_REQUEST | F_FW_CMD_READ); 1310 caps->retval_len16 = htobe32(FW_LEN16(*caps)); 1311 1312 rc = -t4_wr_mbox(sc, sc->mbox, caps, sizeof(*caps), caps); 1313 if (rc != 0) 1314 return (rc); 1315 1316 if (caps->niccaps & htobe16(FW_CAPS_CONFIG_NIC_VM)) 1317 caps->niccaps ^= htobe16(FW_CAPS_CONFIG_NIC_VM); 1318 1319 caps->op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1320 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 1321 rc = -t4_wr_mbox(sc, sc->mbox, caps, sizeof(*caps), NULL); 1322 1323 return (rc); 1324 } 1325 1326 static int 1327 get_params(struct adapter *sc, struct fw_caps_config_cmd *caps) 1328 { 1329 int rc; 1330 uint32_t params[7], val[7]; 1331 1332 #define FW_PARAM_DEV(param) \ 1333 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 1334 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 1335 #define FW_PARAM_PFVF(param) \ 1336 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 1337 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 1338 1339 params[0] = FW_PARAM_DEV(PORTVEC); 1340 params[1] = FW_PARAM_PFVF(IQFLINT_START); 1341 params[2] = FW_PARAM_PFVF(EQ_START); 1342 params[3] = FW_PARAM_PFVF(FILTER_START); 1343 params[4] = FW_PARAM_PFVF(FILTER_END); 1344 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 5, params, val); 1345 if (rc != 0) { 1346 device_printf(sc->dev, 1347 "failed to query parameters: %d.\n", rc); 1348 goto done; 1349 } 1350 1351 sc->params.portvec = val[0]; 1352 sc->params.nports = 0; 1353 while (val[0]) { 1354 sc->params.nports++; 1355 val[0] &= val[0] - 1; 1356 } 1357 1358 sc->sge.iq_start = val[1]; 1359 sc->sge.eq_start = val[2]; 1360 sc->tids.ftid_base = val[3]; 1361 sc->tids.nftids = val[4] - val[3] + 1; 1362 1363 if (caps->toecaps) { 1364 /* query offload-related parameters */ 1365 params[0] = FW_PARAM_DEV(NTID); 1366 params[1] = FW_PARAM_PFVF(SERVER_START); 1367 params[2] = FW_PARAM_PFVF(SERVER_END); 1368 params[3] = FW_PARAM_PFVF(TDDP_START); 1369 params[4] = FW_PARAM_PFVF(TDDP_END); 1370 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 1371 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, params, val); 1372 if (rc != 0) { 1373 device_printf(sc->dev, 1374 "failed to query TOE parameters: %d.\n", rc); 1375 goto done; 1376 } 1377 sc->tids.ntids = val[0]; 1378 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 1379 sc->tids.stid_base = val[1]; 1380 sc->tids.nstids = val[2] - val[1] + 1; 1381 sc->vres.ddp.start = val[3]; 1382 sc->vres.ddp.size = val[4] - val[3] + 1; 1383 sc->params.ofldq_wr_cred = val[5]; 1384 sc->params.offload = 1; 1385 } 1386 if (caps->rdmacaps) { 1387 params[0] = FW_PARAM_PFVF(STAG_START); 1388 params[1] = FW_PARAM_PFVF(STAG_END); 1389 params[2] = FW_PARAM_PFVF(RQ_START); 1390 params[3] = FW_PARAM_PFVF(RQ_END); 1391 params[4] = FW_PARAM_PFVF(PBL_START); 1392 params[5] = FW_PARAM_PFVF(PBL_END); 1393 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, params, val); 1394 if (rc != 0) { 1395 device_printf(sc->dev, 1396 "failed to query RDMA parameters: %d.\n", rc); 1397 goto done; 1398 } 1399 sc->vres.stag.start = val[0]; 1400 sc->vres.stag.size = val[1] - val[0] + 1; 1401 sc->vres.rq.start = val[2]; 1402 sc->vres.rq.size = val[3] - val[2] + 1; 1403 sc->vres.pbl.start = val[4]; 1404 sc->vres.pbl.size = val[5] - val[4] + 1; 1405 } 1406 if (caps->iscsicaps) { 1407 params[0] = FW_PARAM_PFVF(ISCSI_START); 1408 params[1] = FW_PARAM_PFVF(ISCSI_END); 1409 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, params, val); 1410 if (rc != 0) { 1411 device_printf(sc->dev, 1412 "failed to query iSCSI parameters: %d.\n", rc); 1413 goto done; 1414 } 1415 sc->vres.iscsi.start = val[0]; 1416 sc->vres.iscsi.size = val[1] - val[0] + 1; 1417 } 1418 #undef FW_PARAM_PFVF 1419 #undef FW_PARAM_DEV 1420 1421 done: 1422 return (rc); 1423 } 1424 1425 static void 1426 t4_set_desc(struct adapter *sc) 1427 { 1428 char buf[128]; 1429 struct adapter_params *p = &sc->params; 1430 1431 snprintf(buf, sizeof(buf), 1432 "Chelsio %s (rev %d) %d port %sNIC PCIe-x%d %s, S/N:%s, E/C:%s", 1433 p->vpd.id, p->rev, p->nports, is_offload(sc) ? "R" : "", 1434 p->pci.width, (sc->intr_type == 4 ) ? "MSI-X" : 1435 (sc->intr_type == 2) ? "MSI" : "INTx", p->vpd.sn, p->vpd.ec); 1436 1437 device_set_desc_copy(sc->dev, buf); 1438 } 1439 1440 static void 1441 build_medialist(struct port_info *pi) 1442 { 1443 struct ifmedia *media = &pi->media; 1444 int data, m; 1445 1446 PORT_LOCK(pi); 1447 1448 ifmedia_removeall(media); 1449 1450 m = IFM_ETHER | IFM_FDX; 1451 data = (pi->port_type << 8) | pi->mod_type; 1452 1453 switch(pi->port_type) { 1454 case FW_PORT_TYPE_BT_XFI: 1455 ifmedia_add(media, m | IFM_10G_T, data, NULL); 1456 break; 1457 1458 case FW_PORT_TYPE_BT_XAUI: 1459 ifmedia_add(media, m | IFM_10G_T, data, NULL); 1460 /* fall through */ 1461 1462 case FW_PORT_TYPE_BT_SGMII: 1463 ifmedia_add(media, m | IFM_1000_T, data, NULL); 1464 ifmedia_add(media, m | IFM_100_TX, data, NULL); 1465 ifmedia_add(media, IFM_ETHER | IFM_AUTO, data, NULL); 1466 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 1467 break; 1468 1469 case FW_PORT_TYPE_CX4: 1470 ifmedia_add(media, m | IFM_10G_CX4, data, NULL); 1471 ifmedia_set(media, m | IFM_10G_CX4); 1472 break; 1473 1474 case FW_PORT_TYPE_SFP: 1475 case FW_PORT_TYPE_FIBER_XFI: 1476 case FW_PORT_TYPE_FIBER_XAUI: 1477 switch (pi->mod_type) { 1478 1479 case FW_PORT_MOD_TYPE_LR: 1480 ifmedia_add(media, m | IFM_10G_LR, data, NULL); 1481 ifmedia_set(media, m | IFM_10G_LR); 1482 break; 1483 1484 case FW_PORT_MOD_TYPE_SR: 1485 ifmedia_add(media, m | IFM_10G_SR, data, NULL); 1486 ifmedia_set(media, m | IFM_10G_SR); 1487 break; 1488 1489 case FW_PORT_MOD_TYPE_LRM: 1490 ifmedia_add(media, m | IFM_10G_LRM, data, NULL); 1491 ifmedia_set(media, m | IFM_10G_LRM); 1492 break; 1493 1494 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 1495 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 1496 ifmedia_add(media, m | IFM_10G_TWINAX, data, NULL); 1497 ifmedia_set(media, m | IFM_10G_TWINAX); 1498 break; 1499 1500 case FW_PORT_MOD_TYPE_NONE: 1501 m &= ~IFM_FDX; 1502 ifmedia_add(media, m | IFM_NONE, data, NULL); 1503 ifmedia_set(media, m | IFM_NONE); 1504 break; 1505 1506 case FW_PORT_MOD_TYPE_NA: 1507 case FW_PORT_MOD_TYPE_ER: 1508 default: 1509 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL); 1510 ifmedia_set(media, m | IFM_UNKNOWN); 1511 break; 1512 } 1513 break; 1514 1515 case FW_PORT_TYPE_KX4: 1516 case FW_PORT_TYPE_KX: 1517 case FW_PORT_TYPE_KR: 1518 default: 1519 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL); 1520 ifmedia_set(media, m | IFM_UNKNOWN); 1521 break; 1522 } 1523 1524 PORT_UNLOCK(pi); 1525 } 1526 1527 /* 1528 * Program the port's XGMAC based on parameters in ifnet. The caller also 1529 * indicates which parameters should be programmed (the rest are left alone). 1530 */ 1531 static int 1532 update_mac_settings(struct port_info *pi, int flags) 1533 { 1534 int rc; 1535 struct ifnet *ifp = pi->ifp; 1536 struct adapter *sc = pi->adapter; 1537 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 1538 1539 PORT_LOCK_ASSERT_OWNED(pi); 1540 KASSERT(flags, ("%s: not told what to update.", __func__)); 1541 1542 if (flags & XGMAC_MTU) 1543 mtu = ifp->if_mtu; 1544 1545 if (flags & XGMAC_PROMISC) 1546 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 1547 1548 if (flags & XGMAC_ALLMULTI) 1549 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 1550 1551 if (flags & XGMAC_VLANEX) 1552 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 1553 1554 rc = -t4_set_rxmode(sc, sc->mbox, pi->viid, mtu, promisc, allmulti, 1, 1555 vlanex, false); 1556 if (rc) { 1557 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, rc); 1558 return (rc); 1559 } 1560 1561 if (flags & XGMAC_UCADDR) { 1562 uint8_t ucaddr[ETHER_ADDR_LEN]; 1563 1564 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 1565 rc = t4_change_mac(sc, sc->mbox, pi->viid, pi->xact_addr_filt, 1566 ucaddr, true, true); 1567 if (rc < 0) { 1568 rc = -rc; 1569 if_printf(ifp, "change_mac failed: %d\n", rc); 1570 return (rc); 1571 } else { 1572 pi->xact_addr_filt = rc; 1573 rc = 0; 1574 } 1575 } 1576 1577 if (flags & XGMAC_MCADDRS) { 1578 const uint8_t *mcaddr; 1579 int del = 1; 1580 uint64_t hash = 0; 1581 struct ifmultiaddr *ifma; 1582 1583 if_maddr_rlock(ifp); 1584 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1585 if (ifma->ifma_addr->sa_family != AF_LINK) 1586 continue; 1587 mcaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1588 1589 rc = t4_alloc_mac_filt(sc, sc->mbox, pi->viid, del, 1, 1590 &mcaddr, NULL, &hash, 0); 1591 if (rc < 0) { 1592 rc = -rc; 1593 if_printf(ifp, "failed to add mc address" 1594 " %02x:%02x:%02x:%02x:%02x:%02x rc=%d\n", 1595 mcaddr[0], mcaddr[1], mcaddr[2], mcaddr[3], 1596 mcaddr[4], mcaddr[5], rc); 1597 goto mcfail; 1598 } 1599 del = 0; 1600 } 1601 1602 rc = -t4_set_addr_hash(sc, sc->mbox, pi->viid, 0, hash, 0); 1603 if (rc != 0) 1604 if_printf(ifp, "failed to set mc address hash: %d", rc); 1605 mcfail: 1606 if_maddr_runlock(ifp); 1607 } 1608 1609 return (rc); 1610 } 1611 1612 static int 1613 cxgbe_init_locked(struct port_info *pi) 1614 { 1615 struct adapter *sc = pi->adapter; 1616 int rc = 0; 1617 1618 ADAPTER_LOCK_ASSERT_OWNED(sc); 1619 1620 while (!IS_DOOMED(pi) && IS_BUSY(sc)) { 1621 if (mtx_sleep(&sc->flags, &sc->sc_lock, PCATCH, "t4init", 0)) { 1622 rc = EINTR; 1623 goto done; 1624 } 1625 } 1626 if (IS_DOOMED(pi)) { 1627 rc = ENXIO; 1628 goto done; 1629 } 1630 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 1631 1632 /* Give up the adapter lock, port init code can sleep. */ 1633 SET_BUSY(sc); 1634 ADAPTER_UNLOCK(sc); 1635 1636 rc = cxgbe_init_synchronized(pi); 1637 1638 done: 1639 ADAPTER_LOCK(sc); 1640 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 1641 CLR_BUSY(sc); 1642 wakeup_one(&sc->flags); 1643 ADAPTER_UNLOCK(sc); 1644 return (rc); 1645 } 1646 1647 static int 1648 cxgbe_init_synchronized(struct port_info *pi) 1649 { 1650 struct adapter *sc = pi->adapter; 1651 struct ifnet *ifp = pi->ifp; 1652 int rc = 0, i; 1653 uint16_t *rss; 1654 struct sge_rxq *rxq; 1655 1656 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1657 1658 if (isset(&sc->open_device_map, pi->port_id)) { 1659 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, 1660 ("mismatch between open_device_map and if_drv_flags")); 1661 return (0); /* already running */ 1662 } 1663 1664 if (sc->open_device_map == 0 && ((rc = first_port_up(sc)) != 0)) 1665 return (rc); /* error message displayed already */ 1666 1667 /* 1668 * Allocate tx/rx/fl queues for this port. 1669 */ 1670 rc = t4_setup_eth_queues(pi); 1671 if (rc != 0) 1672 goto done; /* error message displayed already */ 1673 1674 /* 1675 * Setup RSS for this port. 1676 */ 1677 rss = malloc(pi->nrxq * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 1678 for_each_rxq(pi, i, rxq) { 1679 rss[i] = rxq->iq.abs_id; 1680 } 1681 rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0, pi->rss_size, rss, 1682 pi->nrxq); 1683 free(rss, M_CXGBE); 1684 if (rc != 0) { 1685 if_printf(ifp, "rss_config failed: %d\n", rc); 1686 goto done; 1687 } 1688 1689 PORT_LOCK(pi); 1690 rc = update_mac_settings(pi, XGMAC_ALL); 1691 PORT_UNLOCK(pi); 1692 if (rc) 1693 goto done; /* error message displayed already */ 1694 1695 rc = -t4_link_start(sc, sc->mbox, pi->tx_chan, &pi->link_cfg); 1696 if (rc != 0) { 1697 if_printf(ifp, "start_link failed: %d\n", rc); 1698 goto done; 1699 } 1700 1701 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, true, true); 1702 if (rc != 0) { 1703 if_printf(ifp, "enable_vi failed: %d\n", rc); 1704 goto done; 1705 } 1706 pi->flags |= VI_ENABLED; 1707 1708 /* all ok */ 1709 setbit(&sc->open_device_map, pi->port_id); 1710 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1711 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1712 1713 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 1714 done: 1715 if (rc != 0) 1716 cxgbe_uninit_synchronized(pi); 1717 1718 return (rc); 1719 } 1720 1721 static int 1722 cxgbe_uninit_locked(struct port_info *pi) 1723 { 1724 struct adapter *sc = pi->adapter; 1725 int rc; 1726 1727 ADAPTER_LOCK_ASSERT_OWNED(sc); 1728 1729 while (!IS_DOOMED(pi) && IS_BUSY(sc)) { 1730 if (mtx_sleep(&sc->flags, &sc->sc_lock, PCATCH, "t4uninit", 0)) { 1731 rc = EINTR; 1732 goto done; 1733 } 1734 } 1735 if (IS_DOOMED(pi)) { 1736 rc = ENXIO; 1737 goto done; 1738 } 1739 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 1740 SET_BUSY(sc); 1741 ADAPTER_UNLOCK(sc); 1742 1743 rc = cxgbe_uninit_synchronized(pi); 1744 1745 ADAPTER_LOCK(sc); 1746 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 1747 CLR_BUSY(sc); 1748 wakeup_one(&sc->flags); 1749 done: 1750 ADAPTER_UNLOCK(sc); 1751 return (rc); 1752 } 1753 1754 /* 1755 * Idempotent. 1756 */ 1757 static int 1758 cxgbe_uninit_synchronized(struct port_info *pi) 1759 { 1760 struct adapter *sc = pi->adapter; 1761 struct ifnet *ifp = pi->ifp; 1762 int rc; 1763 1764 /* 1765 * taskqueue_drain may cause a deadlock if the adapter lock is held. 1766 */ 1767 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1768 1769 /* 1770 * Clear this port's bit from the open device map, and then drain 1771 * tasks and callouts. 1772 */ 1773 clrbit(&sc->open_device_map, pi->port_id); 1774 1775 PORT_LOCK(pi); 1776 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1777 callout_stop(&pi->tick); 1778 PORT_UNLOCK(pi); 1779 callout_drain(&pi->tick); 1780 1781 /* 1782 * Stop and then free the queues' resources, including the queues 1783 * themselves. 1784 * 1785 * XXX: we could just stop the queues here (on ifconfig down) and free 1786 * them later (on port detach), but having up/down go through the entire 1787 * allocate/activate/deactivate/free sequence is a good way to find 1788 * leaks and bugs. 1789 */ 1790 rc = t4_teardown_eth_queues(pi); 1791 if (rc != 0) 1792 if_printf(ifp, "teardown failed: %d\n", rc); 1793 1794 if (pi->flags & VI_ENABLED) { 1795 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, false, false); 1796 if (rc) 1797 if_printf(ifp, "disable_vi failed: %d\n", rc); 1798 else 1799 pi->flags &= ~VI_ENABLED; 1800 } 1801 1802 pi->link_cfg.link_ok = 0; 1803 pi->link_cfg.speed = 0; 1804 t4_os_link_changed(sc, pi->port_id, 0); 1805 1806 if (sc->open_device_map == 0) 1807 last_port_down(sc); 1808 1809 return (0); 1810 } 1811 1812 #define T4_ALLOC_IRQ(sc, irqid, rid, handler, arg, name) do { \ 1813 rc = t4_alloc_irq(sc, &sc->irq[irqid], rid, handler, arg, name); \ 1814 if (rc != 0) \ 1815 goto done; \ 1816 } while (0) 1817 static int 1818 first_port_up(struct adapter *sc) 1819 { 1820 int rc, i; 1821 char name[8]; 1822 1823 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1824 1825 /* 1826 * The firmware event queue and the optional forwarded interrupt queues. 1827 */ 1828 rc = t4_setup_adapter_iqs(sc); 1829 if (rc != 0) 1830 goto done; 1831 1832 /* 1833 * Setup interrupts. 1834 */ 1835 if (sc->intr_count == 1) { 1836 KASSERT(sc->flags & INTR_FWD, 1837 ("%s: single interrupt but not forwarded?", __func__)); 1838 T4_ALLOC_IRQ(sc, 0, 0, t4_intr_all, sc, "all"); 1839 } else { 1840 /* Multiple interrupts. The first one is always error intr */ 1841 T4_ALLOC_IRQ(sc, 0, 1, t4_intr_err, sc, "err"); 1842 1843 if (sc->flags & INTR_FWD) { 1844 /* The rest are shared by the fwq and all data intr */ 1845 for (i = 1; i < sc->intr_count; i++) { 1846 snprintf(name, sizeof(name), "mux%d", i - 1); 1847 T4_ALLOC_IRQ(sc, i, i + 1, t4_intr_fwd, 1848 &sc->sge.fiq[i - 1], name); 1849 } 1850 } else { 1851 struct port_info *pi; 1852 int p, q; 1853 1854 T4_ALLOC_IRQ(sc, 1, 2, t4_intr_evt, &sc->sge.fwq, 1855 "evt"); 1856 1857 p = q = 0; 1858 pi = sc->port[p]; 1859 for (i = 2; i < sc->intr_count; i++) { 1860 snprintf(name, sizeof(name), "p%dq%d", p, q); 1861 if (++q >= pi->nrxq) { 1862 p++; 1863 q = 0; 1864 pi = sc->port[p]; 1865 } 1866 T4_ALLOC_IRQ(sc, i, i + 1, t4_intr_data, 1867 &sc->sge.rxq[i - 2], name); 1868 } 1869 } 1870 } 1871 1872 t4_intr_enable(sc); 1873 sc->flags |= FULL_INIT_DONE; 1874 1875 done: 1876 if (rc != 0) 1877 last_port_down(sc); 1878 1879 return (rc); 1880 } 1881 #undef T4_ALLOC_IRQ 1882 1883 /* 1884 * Idempotent. 1885 */ 1886 static int 1887 last_port_down(struct adapter *sc) 1888 { 1889 int i; 1890 1891 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1892 1893 t4_intr_disable(sc); 1894 1895 t4_teardown_adapter_iqs(sc); 1896 1897 for (i = 0; i < sc->intr_count; i++) 1898 t4_free_irq(sc, &sc->irq[i]); 1899 1900 sc->flags &= ~FULL_INIT_DONE; 1901 1902 return (0); 1903 } 1904 1905 static int 1906 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 1907 iq_intr_handler_t *handler, void *arg, char *name) 1908 { 1909 int rc; 1910 1911 irq->rid = rid; 1912 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 1913 RF_SHAREABLE | RF_ACTIVE); 1914 if (irq->res == NULL) { 1915 device_printf(sc->dev, 1916 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1917 return (ENOMEM); 1918 } 1919 1920 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 1921 NULL, handler, arg, &irq->tag); 1922 if (rc != 0) { 1923 device_printf(sc->dev, 1924 "failed to setup interrupt for rid %d, name %s: %d\n", 1925 rid, name, rc); 1926 } else if (name) 1927 bus_describe_intr(sc->dev, irq->res, irq->tag, name); 1928 1929 return (rc); 1930 } 1931 1932 static int 1933 t4_free_irq(struct adapter *sc, struct irq *irq) 1934 { 1935 if (irq->tag) 1936 bus_teardown_intr(sc->dev, irq->res, irq->tag); 1937 if (irq->res) 1938 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 1939 1940 bzero(irq, sizeof(*irq)); 1941 1942 return (0); 1943 } 1944 1945 static void 1946 reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start, 1947 unsigned int end) 1948 { 1949 uint32_t *p = (uint32_t *)(buf + start); 1950 1951 for ( ; start <= end; start += sizeof(uint32_t)) 1952 *p++ = t4_read_reg(sc, start); 1953 } 1954 1955 static void 1956 t4_get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 1957 { 1958 int i; 1959 static const unsigned int reg_ranges[] = { 1960 0x1008, 0x1108, 1961 0x1180, 0x11b4, 1962 0x11fc, 0x123c, 1963 0x1300, 0x173c, 1964 0x1800, 0x18fc, 1965 0x3000, 0x30d8, 1966 0x30e0, 0x5924, 1967 0x5960, 0x59d4, 1968 0x5a00, 0x5af8, 1969 0x6000, 0x6098, 1970 0x6100, 0x6150, 1971 0x6200, 0x6208, 1972 0x6240, 0x6248, 1973 0x6280, 0x6338, 1974 0x6370, 0x638c, 1975 0x6400, 0x643c, 1976 0x6500, 0x6524, 1977 0x6a00, 0x6a38, 1978 0x6a60, 0x6a78, 1979 0x6b00, 0x6b84, 1980 0x6bf0, 0x6c84, 1981 0x6cf0, 0x6d84, 1982 0x6df0, 0x6e84, 1983 0x6ef0, 0x6f84, 1984 0x6ff0, 0x7084, 1985 0x70f0, 0x7184, 1986 0x71f0, 0x7284, 1987 0x72f0, 0x7384, 1988 0x73f0, 0x7450, 1989 0x7500, 0x7530, 1990 0x7600, 0x761c, 1991 0x7680, 0x76cc, 1992 0x7700, 0x7798, 1993 0x77c0, 0x77fc, 1994 0x7900, 0x79fc, 1995 0x7b00, 0x7c38, 1996 0x7d00, 0x7efc, 1997 0x8dc0, 0x8e1c, 1998 0x8e30, 0x8e78, 1999 0x8ea0, 0x8f6c, 2000 0x8fc0, 0x9074, 2001 0x90fc, 0x90fc, 2002 0x9400, 0x9458, 2003 0x9600, 0x96bc, 2004 0x9800, 0x9808, 2005 0x9820, 0x983c, 2006 0x9850, 0x9864, 2007 0x9c00, 0x9c6c, 2008 0x9c80, 0x9cec, 2009 0x9d00, 0x9d6c, 2010 0x9d80, 0x9dec, 2011 0x9e00, 0x9e6c, 2012 0x9e80, 0x9eec, 2013 0x9f00, 0x9f6c, 2014 0x9f80, 0x9fec, 2015 0xd004, 0xd03c, 2016 0xdfc0, 0xdfe0, 2017 0xe000, 0xea7c, 2018 0xf000, 0x11190, 2019 0x19040, 0x19124, 2020 0x19150, 0x191b0, 2021 0x191d0, 0x191e8, 2022 0x19238, 0x1924c, 2023 0x193f8, 0x19474, 2024 0x19490, 0x194f8, 2025 0x19800, 0x19f30, 2026 0x1a000, 0x1a06c, 2027 0x1a0b0, 0x1a120, 2028 0x1a128, 0x1a138, 2029 0x1a190, 0x1a1c4, 2030 0x1a1fc, 0x1a1fc, 2031 0x1e040, 0x1e04c, 2032 0x1e240, 0x1e28c, 2033 0x1e2c0, 0x1e2c0, 2034 0x1e2e0, 0x1e2e0, 2035 0x1e300, 0x1e384, 2036 0x1e3c0, 0x1e3c8, 2037 0x1e440, 0x1e44c, 2038 0x1e640, 0x1e68c, 2039 0x1e6c0, 0x1e6c0, 2040 0x1e6e0, 0x1e6e0, 2041 0x1e700, 0x1e784, 2042 0x1e7c0, 0x1e7c8, 2043 0x1e840, 0x1e84c, 2044 0x1ea40, 0x1ea8c, 2045 0x1eac0, 0x1eac0, 2046 0x1eae0, 0x1eae0, 2047 0x1eb00, 0x1eb84, 2048 0x1ebc0, 0x1ebc8, 2049 0x1ec40, 0x1ec4c, 2050 0x1ee40, 0x1ee8c, 2051 0x1eec0, 0x1eec0, 2052 0x1eee0, 0x1eee0, 2053 0x1ef00, 0x1ef84, 2054 0x1efc0, 0x1efc8, 2055 0x1f040, 0x1f04c, 2056 0x1f240, 0x1f28c, 2057 0x1f2c0, 0x1f2c0, 2058 0x1f2e0, 0x1f2e0, 2059 0x1f300, 0x1f384, 2060 0x1f3c0, 0x1f3c8, 2061 0x1f440, 0x1f44c, 2062 0x1f640, 0x1f68c, 2063 0x1f6c0, 0x1f6c0, 2064 0x1f6e0, 0x1f6e0, 2065 0x1f700, 0x1f784, 2066 0x1f7c0, 0x1f7c8, 2067 0x1f840, 0x1f84c, 2068 0x1fa40, 0x1fa8c, 2069 0x1fac0, 0x1fac0, 2070 0x1fae0, 0x1fae0, 2071 0x1fb00, 0x1fb84, 2072 0x1fbc0, 0x1fbc8, 2073 0x1fc40, 0x1fc4c, 2074 0x1fe40, 0x1fe8c, 2075 0x1fec0, 0x1fec0, 2076 0x1fee0, 0x1fee0, 2077 0x1ff00, 0x1ff84, 2078 0x1ffc0, 0x1ffc8, 2079 0x20000, 0x2002c, 2080 0x20100, 0x2013c, 2081 0x20190, 0x201c8, 2082 0x20200, 0x20318, 2083 0x20400, 0x20528, 2084 0x20540, 0x20614, 2085 0x21000, 0x21040, 2086 0x2104c, 0x21060, 2087 0x210c0, 0x210ec, 2088 0x21200, 0x21268, 2089 0x21270, 0x21284, 2090 0x212fc, 0x21388, 2091 0x21400, 0x21404, 2092 0x21500, 0x21518, 2093 0x2152c, 0x2153c, 2094 0x21550, 0x21554, 2095 0x21600, 0x21600, 2096 0x21608, 0x21628, 2097 0x21630, 0x2163c, 2098 0x21700, 0x2171c, 2099 0x21780, 0x2178c, 2100 0x21800, 0x21c38, 2101 0x21c80, 0x21d7c, 2102 0x21e00, 0x21e04, 2103 0x22000, 0x2202c, 2104 0x22100, 0x2213c, 2105 0x22190, 0x221c8, 2106 0x22200, 0x22318, 2107 0x22400, 0x22528, 2108 0x22540, 0x22614, 2109 0x23000, 0x23040, 2110 0x2304c, 0x23060, 2111 0x230c0, 0x230ec, 2112 0x23200, 0x23268, 2113 0x23270, 0x23284, 2114 0x232fc, 0x23388, 2115 0x23400, 0x23404, 2116 0x23500, 0x23518, 2117 0x2352c, 0x2353c, 2118 0x23550, 0x23554, 2119 0x23600, 0x23600, 2120 0x23608, 0x23628, 2121 0x23630, 0x2363c, 2122 0x23700, 0x2371c, 2123 0x23780, 0x2378c, 2124 0x23800, 0x23c38, 2125 0x23c80, 0x23d7c, 2126 0x23e00, 0x23e04, 2127 0x24000, 0x2402c, 2128 0x24100, 0x2413c, 2129 0x24190, 0x241c8, 2130 0x24200, 0x24318, 2131 0x24400, 0x24528, 2132 0x24540, 0x24614, 2133 0x25000, 0x25040, 2134 0x2504c, 0x25060, 2135 0x250c0, 0x250ec, 2136 0x25200, 0x25268, 2137 0x25270, 0x25284, 2138 0x252fc, 0x25388, 2139 0x25400, 0x25404, 2140 0x25500, 0x25518, 2141 0x2552c, 0x2553c, 2142 0x25550, 0x25554, 2143 0x25600, 0x25600, 2144 0x25608, 0x25628, 2145 0x25630, 0x2563c, 2146 0x25700, 0x2571c, 2147 0x25780, 0x2578c, 2148 0x25800, 0x25c38, 2149 0x25c80, 0x25d7c, 2150 0x25e00, 0x25e04, 2151 0x26000, 0x2602c, 2152 0x26100, 0x2613c, 2153 0x26190, 0x261c8, 2154 0x26200, 0x26318, 2155 0x26400, 0x26528, 2156 0x26540, 0x26614, 2157 0x27000, 0x27040, 2158 0x2704c, 0x27060, 2159 0x270c0, 0x270ec, 2160 0x27200, 0x27268, 2161 0x27270, 0x27284, 2162 0x272fc, 0x27388, 2163 0x27400, 0x27404, 2164 0x27500, 0x27518, 2165 0x2752c, 0x2753c, 2166 0x27550, 0x27554, 2167 0x27600, 0x27600, 2168 0x27608, 0x27628, 2169 0x27630, 0x2763c, 2170 0x27700, 0x2771c, 2171 0x27780, 0x2778c, 2172 0x27800, 0x27c38, 2173 0x27c80, 0x27d7c, 2174 0x27e00, 0x27e04 2175 }; 2176 2177 regs->version = 4 | (sc->params.rev << 10); 2178 for (i = 0; i < ARRAY_SIZE(reg_ranges); i += 2) 2179 reg_block_dump(sc, buf, reg_ranges[i], reg_ranges[i + 1]); 2180 } 2181 2182 static void 2183 cxgbe_tick(void *arg) 2184 { 2185 struct port_info *pi = arg; 2186 struct ifnet *ifp = pi->ifp; 2187 struct sge_txq *txq; 2188 int i, drops; 2189 struct port_stats *s = &pi->stats; 2190 2191 PORT_LOCK(pi); 2192 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2193 PORT_UNLOCK(pi); 2194 return; /* without scheduling another callout */ 2195 } 2196 2197 t4_get_port_stats(pi->adapter, pi->tx_chan, s); 2198 2199 ifp->if_opackets = s->tx_frames; 2200 ifp->if_ipackets = s->rx_frames; 2201 ifp->if_obytes = s->tx_octets; 2202 ifp->if_ibytes = s->rx_octets; 2203 ifp->if_omcasts = s->tx_mcast_frames; 2204 ifp->if_imcasts = s->rx_mcast_frames; 2205 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2206 s->rx_ovflow3; 2207 2208 drops = s->tx_drop; 2209 for_each_txq(pi, i, txq) 2210 drops += txq->eq.br->br_drops; 2211 ifp->if_snd.ifq_drops = drops; 2212 2213 ifp->if_oerrors = s->tx_error_frames; 2214 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long + 2215 s->rx_fcs_err + s->rx_len_err; 2216 2217 callout_schedule(&pi->tick, hz); 2218 PORT_UNLOCK(pi); 2219 } 2220 2221 static int 2222 t4_sysctls(struct adapter *sc) 2223 { 2224 struct sysctl_ctx_list *ctx; 2225 struct sysctl_oid *oid; 2226 struct sysctl_oid_list *children; 2227 2228 ctx = device_get_sysctl_ctx(sc->dev); 2229 oid = device_get_sysctl_tree(sc->dev); 2230 children = SYSCTL_CHILDREN(oid); 2231 2232 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, 2233 &sc->params.nports, 0, "# of ports"); 2234 2235 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 2236 &sc->params.rev, 0, "chip hardware revision"); 2237 2238 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 2239 CTLFLAG_RD, &sc->fw_version, 0, "firmware version"); 2240 2241 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "TOE", CTLFLAG_RD, 2242 &sc->params.offload, 0, "hardware is capable of TCP offload"); 2243 2244 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, 2245 &sc->params.vpd.cclk, 0, "core clock frequency (in KHz)"); 2246 2247 /* XXX: this doesn't seem to show up */ 2248 SYSCTL_ADD_OPAQUE(ctx, children, OID_AUTO, "holdoff_tmr", 2249 CTLFLAG_RD, &intr_timer, sizeof(intr_timer), "IU", 2250 "interrupt holdoff timer values (us)"); 2251 2252 /* XXX: this doesn't seem to show up */ 2253 SYSCTL_ADD_OPAQUE(ctx, children, OID_AUTO, "holdoff_pktc", 2254 CTLFLAG_RD, &intr_pktcount, sizeof(intr_pktcount), "IU", 2255 "interrupt holdoff packet counter values"); 2256 2257 return (0); 2258 } 2259 2260 static int 2261 cxgbe_sysctls(struct port_info *pi) 2262 { 2263 struct sysctl_ctx_list *ctx; 2264 struct sysctl_oid *oid; 2265 struct sysctl_oid_list *children; 2266 2267 ctx = device_get_sysctl_ctx(pi->dev); 2268 2269 /* 2270 * dev.cxgbe.X. 2271 */ 2272 oid = device_get_sysctl_tree(pi->dev); 2273 children = SYSCTL_CHILDREN(oid); 2274 2275 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 2276 &pi->nrxq, 0, "# of rx queues"); 2277 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 2278 &pi->ntxq, 0, "# of tx queues"); 2279 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 2280 &pi->first_rxq, 0, "index of first rx queue"); 2281 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 2282 &pi->first_txq, 0, "index of first tx queue"); 2283 2284 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 2285 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_tmr_idx, "I", 2286 "holdoff timer index"); 2287 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 2288 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_pktc_idx, "I", 2289 "holdoff packet counter index"); 2290 2291 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 2292 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_rxq, "I", 2293 "rx queue size"); 2294 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 2295 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_txq, "I", 2296 "tx queue size"); 2297 2298 /* 2299 * dev.cxgbe.X.stats. 2300 */ 2301 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 2302 NULL, "port statistics"); 2303 children = SYSCTL_CHILDREN(oid); 2304 2305 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 2306 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 2307 CTLTYPE_U64 | CTLFLAG_RD, pi->adapter, reg, \ 2308 sysctl_handle_t4_reg64, "QU", desc) 2309 2310 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 2311 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 2312 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 2313 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 2314 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 2315 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 2316 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 2317 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 2318 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 2319 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 2320 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 2321 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 2322 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 2323 "# of tx frames in this range", 2324 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 2325 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 2326 "# of tx frames in this range", 2327 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 2328 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 2329 "# of tx frames in this range", 2330 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 2331 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 2332 "# of tx frames in this range", 2333 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 2334 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 2335 "# of tx frames in this range", 2336 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 2337 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 2338 "# of tx frames in this range", 2339 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 2340 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 2341 "# of tx frames in this range", 2342 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 2343 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 2344 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 2345 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 2346 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 2347 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 2348 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 2349 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 2350 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 2351 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 2352 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 2353 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 2354 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 2355 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 2356 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 2357 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 2358 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 2359 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 2360 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 2361 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 2362 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 2363 2364 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 2365 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 2366 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 2367 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 2368 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 2369 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 2370 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 2371 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 2372 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 2373 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 2374 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 2375 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 2376 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 2377 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 2378 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 2379 "# of frames received with bad FCS", 2380 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 2381 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 2382 "# of frames received with length error", 2383 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 2384 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 2385 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 2386 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 2387 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 2388 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 2389 "# of rx frames in this range", 2390 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 2391 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 2392 "# of rx frames in this range", 2393 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 2394 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 2395 "# of rx frames in this range", 2396 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 2397 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 2398 "# of rx frames in this range", 2399 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 2400 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 2401 "# of rx frames in this range", 2402 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 2403 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 2404 "# of rx frames in this range", 2405 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 2406 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 2407 "# of rx frames in this range", 2408 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 2409 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 2410 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 2411 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 2412 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 2413 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 2414 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 2415 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 2416 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 2417 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 2418 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 2419 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 2420 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 2421 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 2422 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 2423 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 2424 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 2425 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 2426 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 2427 2428 #undef SYSCTL_ADD_T4_REG64 2429 2430 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 2431 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 2432 &pi->stats.name, desc) 2433 2434 /* We get these from port_stats and they may be stale by upto 1s */ 2435 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 2436 "# drops due to buffer-group 0 overflows"); 2437 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 2438 "# drops due to buffer-group 1 overflows"); 2439 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 2440 "# drops due to buffer-group 2 overflows"); 2441 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 2442 "# drops due to buffer-group 3 overflows"); 2443 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 2444 "# of buffer-group 0 truncated packets"); 2445 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 2446 "# of buffer-group 1 truncated packets"); 2447 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 2448 "# of buffer-group 2 truncated packets"); 2449 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 2450 "# of buffer-group 3 truncated packets"); 2451 2452 #undef SYSCTL_ADD_T4_PORTSTAT 2453 2454 return (0); 2455 } 2456 2457 static int 2458 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 2459 { 2460 struct port_info *pi = arg1; 2461 struct adapter *sc = pi->adapter; 2462 struct sge_rxq *rxq; 2463 int idx, rc, i; 2464 2465 idx = pi->tmr_idx; 2466 2467 rc = sysctl_handle_int(oidp, &idx, 0, req); 2468 if (rc != 0 || req->newptr == NULL) 2469 return (rc); 2470 2471 if (idx < 0 || idx >= SGE_NTIMERS) 2472 return (EINVAL); 2473 2474 ADAPTER_LOCK(sc); 2475 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2476 if (rc == 0) { 2477 for_each_rxq(pi, i, rxq) { 2478 rxq->iq.intr_params = V_QINTR_TIMER_IDX(idx) | 2479 V_QINTR_CNT_EN(pi->pktc_idx != -1); 2480 } 2481 pi->tmr_idx = idx; 2482 } 2483 2484 ADAPTER_UNLOCK(sc); 2485 return (rc); 2486 } 2487 2488 static int 2489 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 2490 { 2491 struct port_info *pi = arg1; 2492 struct adapter *sc = pi->adapter; 2493 int idx, rc; 2494 2495 idx = pi->pktc_idx; 2496 2497 rc = sysctl_handle_int(oidp, &idx, 0, req); 2498 if (rc != 0 || req->newptr == NULL) 2499 return (rc); 2500 2501 if (idx < -1 || idx >= SGE_NCOUNTERS) 2502 return (EINVAL); 2503 2504 ADAPTER_LOCK(sc); 2505 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2506 if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING) 2507 rc = EBUSY; /* can be changed only when port is down */ 2508 2509 if (rc == 0) 2510 pi->pktc_idx = idx; 2511 2512 ADAPTER_UNLOCK(sc); 2513 return (rc); 2514 } 2515 2516 static int 2517 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 2518 { 2519 struct port_info *pi = arg1; 2520 struct adapter *sc = pi->adapter; 2521 int qsize, rc; 2522 2523 qsize = pi->qsize_rxq; 2524 2525 rc = sysctl_handle_int(oidp, &qsize, 0, req); 2526 if (rc != 0 || req->newptr == NULL) 2527 return (rc); 2528 2529 if (qsize < 128 || (qsize & 7)) 2530 return (EINVAL); 2531 2532 ADAPTER_LOCK(sc); 2533 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2534 if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING) 2535 rc = EBUSY; /* can be changed only when port is down */ 2536 2537 if (rc == 0) 2538 pi->qsize_rxq = qsize; 2539 2540 ADAPTER_UNLOCK(sc); 2541 return (rc); 2542 } 2543 2544 static int 2545 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 2546 { 2547 struct port_info *pi = arg1; 2548 struct adapter *sc = pi->adapter; 2549 int qsize, rc; 2550 2551 qsize = pi->qsize_txq; 2552 2553 rc = sysctl_handle_int(oidp, &qsize, 0, req); 2554 if (rc != 0 || req->newptr == NULL) 2555 return (rc); 2556 2557 if (qsize < 128) 2558 return (EINVAL); 2559 2560 ADAPTER_LOCK(sc); 2561 rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); 2562 if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING) 2563 rc = EBUSY; /* can be changed only when port is down */ 2564 2565 if (rc == 0) 2566 pi->qsize_txq = qsize; 2567 2568 ADAPTER_UNLOCK(sc); 2569 return (rc); 2570 } 2571 2572 static int 2573 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 2574 { 2575 struct adapter *sc = arg1; 2576 int reg = arg2; 2577 uint64_t val; 2578 2579 val = t4_read_reg64(sc, reg); 2580 2581 return (sysctl_handle_64(oidp, &val, 0, req)); 2582 } 2583 2584 int 2585 t4_os_find_pci_capability(struct adapter *sc, int cap) 2586 { 2587 device_t dev; 2588 struct pci_devinfo *dinfo; 2589 pcicfgregs *cfg; 2590 uint32_t status; 2591 uint8_t ptr; 2592 2593 dev = sc->dev; 2594 dinfo = device_get_ivars(dev); 2595 cfg = &dinfo->cfg; 2596 2597 status = pci_read_config(dev, PCIR_STATUS, 2); 2598 if (!(status & PCIM_STATUS_CAPPRESENT)) 2599 return (0); 2600 2601 switch (cfg->hdrtype & PCIM_HDRTYPE) { 2602 case 0: 2603 case 1: 2604 ptr = PCIR_CAP_PTR; 2605 break; 2606 case 2: 2607 ptr = PCIR_CAP_PTR_2; 2608 break; 2609 default: 2610 return (0); 2611 break; 2612 } 2613 ptr = pci_read_config(dev, ptr, 1); 2614 2615 while (ptr != 0) { 2616 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) 2617 return (ptr); 2618 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); 2619 } 2620 2621 return (0); 2622 } 2623 2624 int 2625 t4_os_pci_save_state(struct adapter *sc) 2626 { 2627 device_t dev; 2628 struct pci_devinfo *dinfo; 2629 2630 dev = sc->dev; 2631 dinfo = device_get_ivars(dev); 2632 2633 pci_cfg_save(dev, dinfo, 0); 2634 return (0); 2635 } 2636 2637 int 2638 t4_os_pci_restore_state(struct adapter *sc) 2639 { 2640 device_t dev; 2641 struct pci_devinfo *dinfo; 2642 2643 dev = sc->dev; 2644 dinfo = device_get_ivars(dev); 2645 2646 pci_cfg_restore(dev, dinfo); 2647 return (0); 2648 } 2649 void 2650 t4_os_portmod_changed(const struct adapter *sc, int idx) 2651 { 2652 struct port_info *pi = sc->port[idx]; 2653 static const char *mod_str[] = { 2654 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX" 2655 }; 2656 2657 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 2658 if_printf(pi->ifp, "transceiver unplugged.\n"); 2659 else 2660 if_printf(pi->ifp, "%s transceiver inserted.\n", 2661 mod_str[pi->mod_type]); 2662 2663 } 2664 2665 void 2666 t4_os_link_changed(struct adapter *sc, int idx, int link_stat) 2667 { 2668 struct port_info *pi = sc->port[idx]; 2669 struct ifnet *ifp = pi->ifp; 2670 2671 if (link_stat) { 2672 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed); 2673 if_link_state_change(ifp, LINK_STATE_UP); 2674 } else 2675 if_link_state_change(ifp, LINK_STATE_DOWN); 2676 } 2677 2678 static int 2679 t4_open(struct cdev *dev, int flags, int type, struct thread *td) 2680 { 2681 return (0); 2682 } 2683 2684 static int 2685 t4_close(struct cdev *dev, int flags, int type, struct thread *td) 2686 { 2687 return (0); 2688 } 2689 2690 static int 2691 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 2692 struct thread *td) 2693 { 2694 int rc; 2695 struct adapter *sc = dev->si_drv1; 2696 2697 rc = priv_check(td, PRIV_DRIVER); 2698 if (rc != 0) 2699 return (rc); 2700 2701 switch (cmd) { 2702 case CHELSIO_T4_GETREG32: { 2703 struct t4_reg32 *edata = (struct t4_reg32 *)data; 2704 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2705 return (EFAULT); 2706 edata->val = t4_read_reg(sc, edata->addr); 2707 break; 2708 } 2709 case CHELSIO_T4_SETREG32: { 2710 struct t4_reg32 *edata = (struct t4_reg32 *)data; 2711 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 2712 return (EFAULT); 2713 t4_write_reg(sc, edata->addr, edata->val); 2714 break; 2715 } 2716 case CHELSIO_T4_REGDUMP: { 2717 struct t4_regdump *regs = (struct t4_regdump *)data; 2718 int reglen = T4_REGDUMP_SIZE; 2719 uint8_t *buf; 2720 2721 if (regs->len < reglen) { 2722 regs->len = reglen; /* hint to the caller */ 2723 return (ENOBUFS); 2724 } 2725 2726 regs->len = reglen; 2727 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 2728 t4_get_regs(sc, regs, buf); 2729 rc = copyout(buf, regs->data, reglen); 2730 free(buf, M_CXGBE); 2731 break; 2732 } 2733 default: 2734 rc = EINVAL; 2735 } 2736 2737 return (rc); 2738 } 2739 2740 static devclass_t t4_devclass; 2741 static devclass_t cxgbe_devclass; 2742 2743 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, 0, 0); 2744 MODULE_VERSION(t4nex, 1); 2745 2746 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 2747 MODULE_VERSION(cxgbe, 1); 2748