1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_ratelimit.h" 37 #include "opt_rss.h" 38 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/priv.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #if defined(__i386__) || defined(__amd64__) 69 #include <machine/md_var.h> 70 #include <machine/cputypes.h> 71 #include <vm/vm.h> 72 #include <vm/pmap.h> 73 #endif 74 #include <crypto/rijndael/rijndael.h> 75 #ifdef DDB 76 #include <ddb/ddb.h> 77 #include <ddb/db_lex.h> 78 #endif 79 80 #include "common/common.h" 81 #include "common/t4_msg.h" 82 #include "common/t4_regs.h" 83 #include "common/t4_regs_values.h" 84 #include "cudbg/cudbg.h" 85 #include "t4_clip.h" 86 #include "t4_ioctl.h" 87 #include "t4_l2t.h" 88 #include "t4_mp_ring.h" 89 #include "t4_if.h" 90 #include "t4_smt.h" 91 92 /* T4 bus driver interface */ 93 static int t4_probe(device_t); 94 static int t4_attach(device_t); 95 static int t4_detach(device_t); 96 static int t4_child_location_str(device_t, device_t, char *, size_t); 97 static int t4_ready(device_t); 98 static int t4_read_port_device(device_t, int, device_t *); 99 static device_method_t t4_methods[] = { 100 DEVMETHOD(device_probe, t4_probe), 101 DEVMETHOD(device_attach, t4_attach), 102 DEVMETHOD(device_detach, t4_detach), 103 104 DEVMETHOD(bus_child_location_str, t4_child_location_str), 105 106 DEVMETHOD(t4_is_main_ready, t4_ready), 107 DEVMETHOD(t4_read_port_device, t4_read_port_device), 108 109 DEVMETHOD_END 110 }; 111 static driver_t t4_driver = { 112 "t4nex", 113 t4_methods, 114 sizeof(struct adapter) 115 }; 116 117 118 /* T4 port (cxgbe) interface */ 119 static int cxgbe_probe(device_t); 120 static int cxgbe_attach(device_t); 121 static int cxgbe_detach(device_t); 122 device_method_t cxgbe_methods[] = { 123 DEVMETHOD(device_probe, cxgbe_probe), 124 DEVMETHOD(device_attach, cxgbe_attach), 125 DEVMETHOD(device_detach, cxgbe_detach), 126 { 0, 0 } 127 }; 128 static driver_t cxgbe_driver = { 129 "cxgbe", 130 cxgbe_methods, 131 sizeof(struct port_info) 132 }; 133 134 /* T4 VI (vcxgbe) interface */ 135 static int vcxgbe_probe(device_t); 136 static int vcxgbe_attach(device_t); 137 static int vcxgbe_detach(device_t); 138 static device_method_t vcxgbe_methods[] = { 139 DEVMETHOD(device_probe, vcxgbe_probe), 140 DEVMETHOD(device_attach, vcxgbe_attach), 141 DEVMETHOD(device_detach, vcxgbe_detach), 142 { 0, 0 } 143 }; 144 static driver_t vcxgbe_driver = { 145 "vcxgbe", 146 vcxgbe_methods, 147 sizeof(struct vi_info) 148 }; 149 150 static d_ioctl_t t4_ioctl; 151 152 static struct cdevsw t4_cdevsw = { 153 .d_version = D_VERSION, 154 .d_ioctl = t4_ioctl, 155 .d_name = "t4nex", 156 }; 157 158 /* T5 bus driver interface */ 159 static int t5_probe(device_t); 160 static device_method_t t5_methods[] = { 161 DEVMETHOD(device_probe, t5_probe), 162 DEVMETHOD(device_attach, t4_attach), 163 DEVMETHOD(device_detach, t4_detach), 164 165 DEVMETHOD(bus_child_location_str, t4_child_location_str), 166 167 DEVMETHOD(t4_is_main_ready, t4_ready), 168 DEVMETHOD(t4_read_port_device, t4_read_port_device), 169 170 DEVMETHOD_END 171 }; 172 static driver_t t5_driver = { 173 "t5nex", 174 t5_methods, 175 sizeof(struct adapter) 176 }; 177 178 179 /* T5 port (cxl) interface */ 180 static driver_t cxl_driver = { 181 "cxl", 182 cxgbe_methods, 183 sizeof(struct port_info) 184 }; 185 186 /* T5 VI (vcxl) interface */ 187 static driver_t vcxl_driver = { 188 "vcxl", 189 vcxgbe_methods, 190 sizeof(struct vi_info) 191 }; 192 193 /* T6 bus driver interface */ 194 static int t6_probe(device_t); 195 static device_method_t t6_methods[] = { 196 DEVMETHOD(device_probe, t6_probe), 197 DEVMETHOD(device_attach, t4_attach), 198 DEVMETHOD(device_detach, t4_detach), 199 200 DEVMETHOD(bus_child_location_str, t4_child_location_str), 201 202 DEVMETHOD(t4_is_main_ready, t4_ready), 203 DEVMETHOD(t4_read_port_device, t4_read_port_device), 204 205 DEVMETHOD_END 206 }; 207 static driver_t t6_driver = { 208 "t6nex", 209 t6_methods, 210 sizeof(struct adapter) 211 }; 212 213 214 /* T6 port (cc) interface */ 215 static driver_t cc_driver = { 216 "cc", 217 cxgbe_methods, 218 sizeof(struct port_info) 219 }; 220 221 /* T6 VI (vcc) interface */ 222 static driver_t vcc_driver = { 223 "vcc", 224 vcxgbe_methods, 225 sizeof(struct vi_info) 226 }; 227 228 /* ifnet interface */ 229 static void cxgbe_init(void *); 230 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 231 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 232 static void cxgbe_qflush(struct ifnet *); 233 234 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 235 236 /* 237 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 238 * then ADAPTER_LOCK, then t4_uld_list_lock. 239 */ 240 static struct sx t4_list_lock; 241 SLIST_HEAD(, adapter) t4_list; 242 #ifdef TCP_OFFLOAD 243 static struct sx t4_uld_list_lock; 244 SLIST_HEAD(, uld_info) t4_uld_list; 245 #endif 246 247 /* 248 * Tunables. See tweak_tunables() too. 249 * 250 * Each tunable is set to a default value here if it's known at compile-time. 251 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 252 * provide a reasonable default (upto n) when the driver is loaded. 253 * 254 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 255 * T5 are under hw.cxl. 256 */ 257 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters"); 258 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters"); 259 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters"); 260 261 /* 262 * Number of queues for tx and rx, NIC and offload. 263 */ 264 #define NTXQ 16 265 int t4_ntxq = -NTXQ; 266 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 267 "Number of TX queues per port"); 268 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 269 270 #define NRXQ 8 271 int t4_nrxq = -NRXQ; 272 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 273 "Number of RX queues per port"); 274 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 275 276 #define NTXQ_VI 1 277 static int t4_ntxq_vi = -NTXQ_VI; 278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 279 "Number of TX queues per VI"); 280 281 #define NRXQ_VI 1 282 static int t4_nrxq_vi = -NRXQ_VI; 283 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 284 "Number of RX queues per VI"); 285 286 static int t4_rsrv_noflowq = 0; 287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 288 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 289 290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 291 #define NOFLDTXQ 8 292 static int t4_nofldtxq = -NOFLDTXQ; 293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 294 "Number of offload TX queues per port"); 295 296 #define NOFLDRXQ 2 297 static int t4_nofldrxq = -NOFLDRXQ; 298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 299 "Number of offload RX queues per port"); 300 301 #define NOFLDTXQ_VI 1 302 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 304 "Number of offload TX queues per VI"); 305 306 #define NOFLDRXQ_VI 1 307 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 309 "Number of offload RX queues per VI"); 310 311 #define TMR_IDX_OFLD 1 312 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 314 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 315 316 #define PKTC_IDX_OFLD (-1) 317 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 319 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 320 321 /* 0 means chip/fw default, non-zero number is value in microseconds */ 322 static u_long t4_toe_keepalive_idle = 0; 323 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 324 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 325 326 /* 0 means chip/fw default, non-zero number is value in microseconds */ 327 static u_long t4_toe_keepalive_interval = 0; 328 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 329 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 330 331 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 332 static int t4_toe_keepalive_count = 0; 333 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 334 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 335 336 /* 0 means chip/fw default, non-zero number is value in microseconds */ 337 static u_long t4_toe_rexmt_min = 0; 338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 339 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 340 341 /* 0 means chip/fw default, non-zero number is value in microseconds */ 342 static u_long t4_toe_rexmt_max = 0; 343 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 344 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 345 346 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 347 static int t4_toe_rexmt_count = 0; 348 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 349 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 350 351 /* -1 means chip/fw default, other values are raw backoff values to use */ 352 static int t4_toe_rexmt_backoff[16] = { 353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 354 }; 355 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0, 356 "cxgbe(4) TOE retransmit backoff values"); 357 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 358 &t4_toe_rexmt_backoff[0], 0, ""); 359 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 360 &t4_toe_rexmt_backoff[1], 0, ""); 361 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 362 &t4_toe_rexmt_backoff[2], 0, ""); 363 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_backoff[3], 0, ""); 365 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_backoff[4], 0, ""); 367 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 368 &t4_toe_rexmt_backoff[5], 0, ""); 369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 370 &t4_toe_rexmt_backoff[6], 0, ""); 371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 372 &t4_toe_rexmt_backoff[7], 0, ""); 373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_backoff[8], 0, ""); 375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_backoff[9], 0, ""); 377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 378 &t4_toe_rexmt_backoff[10], 0, ""); 379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 380 &t4_toe_rexmt_backoff[11], 0, ""); 381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 382 &t4_toe_rexmt_backoff[12], 0, ""); 383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[13], 0, ""); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[14], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[15], 0, ""); 389 #endif 390 391 #ifdef DEV_NETMAP 392 #define NNMTXQ_VI 2 393 static int t4_nnmtxq_vi = -NNMTXQ_VI; 394 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 395 "Number of netmap TX queues per VI"); 396 397 #define NNMRXQ_VI 2 398 static int t4_nnmrxq_vi = -NNMRXQ_VI; 399 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 400 "Number of netmap RX queues per VI"); 401 #endif 402 403 /* 404 * Holdoff parameters for ports. 405 */ 406 #define TMR_IDX 1 407 int t4_tmr_idx = TMR_IDX; 408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 409 0, "Holdoff timer index"); 410 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 411 412 #define PKTC_IDX (-1) 413 int t4_pktc_idx = PKTC_IDX; 414 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 415 0, "Holdoff packet counter index"); 416 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 417 418 /* 419 * Size (# of entries) of each tx and rx queue. 420 */ 421 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 423 "Number of descriptors in each TX queue"); 424 425 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 427 "Number of descriptors in each RX queue"); 428 429 /* 430 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 431 */ 432 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 434 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 435 436 /* 437 * Configuration file. All the _CF names here are special. 438 */ 439 #define DEFAULT_CF "default" 440 #define BUILTIN_CF "built-in" 441 #define FLASH_CF "flash" 442 #define UWIRE_CF "uwire" 443 #define FPGA_CF "fpga" 444 static char t4_cfg_file[32] = DEFAULT_CF; 445 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 446 sizeof(t4_cfg_file), "Firmware configuration file"); 447 448 /* 449 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 450 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 451 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 452 * mark or when signalled to do so, 0 to never emit PAUSE. 453 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 454 * negotiated settings will override rx_pause/tx_pause. 455 * Otherwise rx_pause/tx_pause are applied forcibly. 456 */ 457 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 459 &t4_pause_settings, 0, 460 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 461 462 /* 463 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 464 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 465 * 0 to disable FEC. 466 */ 467 static int t4_fec = -1; 468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 469 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 470 471 /* 472 * Link autonegotiation. 473 * -1 to run with the firmware default. 474 * 0 to disable. 475 * 1 to enable. 476 */ 477 static int t4_autoneg = -1; 478 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 479 "Link autonegotiation"); 480 481 /* 482 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 483 * encouraged respectively). '-n' is the same as 'n' except the firmware 484 * version used in the checks is read from the firmware bundled with the driver. 485 */ 486 static int t4_fw_install = 1; 487 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 488 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 489 490 /* 491 * ASIC features that will be used. Disable the ones you don't want so that the 492 * chip resources aren't wasted on features that will not be used. 493 */ 494 static int t4_nbmcaps_allowed = 0; 495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 496 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 497 498 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 499 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 500 &t4_linkcaps_allowed, 0, "Default link capabilities"); 501 502 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 503 FW_CAPS_CONFIG_SWITCH_EGRESS; 504 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 505 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 506 507 #ifdef RATELIMIT 508 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 509 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 510 #else 511 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 512 FW_CAPS_CONFIG_NIC_HASHFILTER; 513 #endif 514 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 515 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 516 517 static int t4_toecaps_allowed = -1; 518 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 519 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 520 521 static int t4_rdmacaps_allowed = -1; 522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 523 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 524 525 static int t4_cryptocaps_allowed = -1; 526 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 527 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 528 529 static int t4_iscsicaps_allowed = -1; 530 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 531 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 532 533 static int t4_fcoecaps_allowed = 0; 534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 535 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 536 537 static int t5_write_combine = 0; 538 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 539 0, "Use WC instead of UC for BAR2"); 540 541 static int t4_num_vis = 1; 542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 543 "Number of VIs per port"); 544 545 /* 546 * PCIe Relaxed Ordering. 547 * -1: driver should figure out a good value. 548 * 0: disable RO. 549 * 1: enable RO. 550 * 2: leave RO alone. 551 */ 552 static int pcie_relaxed_ordering = -1; 553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 554 &pcie_relaxed_ordering, 0, 555 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 556 557 static int t4_panic_on_fatal_err = 0; 558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN, 559 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 560 561 #ifdef TCP_OFFLOAD 562 /* 563 * TOE tunables. 564 */ 565 static int t4_cop_managed_offloading = 0; 566 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 567 &t4_cop_managed_offloading, 0, 568 "COP (Connection Offload Policy) controls all TOE offload"); 569 #endif 570 571 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 572 static int vi_mac_funcs[] = { 573 FW_VI_FUNC_ETH, 574 FW_VI_FUNC_OFLD, 575 FW_VI_FUNC_IWARP, 576 FW_VI_FUNC_OPENISCSI, 577 FW_VI_FUNC_OPENFCOE, 578 FW_VI_FUNC_FOISCSI, 579 FW_VI_FUNC_FOFCOE, 580 }; 581 582 struct intrs_and_queues { 583 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 584 uint16_t num_vis; /* number of VIs for each port */ 585 uint16_t nirq; /* Total # of vectors */ 586 uint16_t ntxq; /* # of NIC txq's for each port */ 587 uint16_t nrxq; /* # of NIC rxq's for each port */ 588 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 589 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 590 591 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 592 uint16_t ntxq_vi; /* # of NIC txq's */ 593 uint16_t nrxq_vi; /* # of NIC rxq's */ 594 uint16_t nofldtxq_vi; /* # of TOE txq's */ 595 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 596 uint16_t nnmtxq_vi; /* # of netmap txq's */ 597 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 598 }; 599 600 static void setup_memwin(struct adapter *); 601 static void position_memwin(struct adapter *, int, uint32_t); 602 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 603 static int fwmtype_to_hwmtype(int); 604 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 605 uint32_t *); 606 static int fixup_devlog_params(struct adapter *); 607 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 608 static int contact_firmware(struct adapter *); 609 static int partition_resources(struct adapter *); 610 static int get_params__pre_init(struct adapter *); 611 static int set_params__pre_init(struct adapter *); 612 static int get_params__post_init(struct adapter *); 613 static int set_params__post_init(struct adapter *); 614 static void t4_set_desc(struct adapter *); 615 static bool fixed_ifmedia(struct port_info *); 616 static void build_medialist(struct port_info *); 617 static void init_link_config(struct port_info *); 618 static int fixup_link_config(struct port_info *); 619 static int apply_link_config(struct port_info *); 620 static int cxgbe_init_synchronized(struct vi_info *); 621 static int cxgbe_uninit_synchronized(struct vi_info *); 622 static void quiesce_txq(struct adapter *, struct sge_txq *); 623 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 624 static void quiesce_iq(struct adapter *, struct sge_iq *); 625 static void quiesce_fl(struct adapter *, struct sge_fl *); 626 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 627 driver_intr_t *, void *, char *); 628 static int t4_free_irq(struct adapter *, struct irq *); 629 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 630 static void vi_refresh_stats(struct adapter *, struct vi_info *); 631 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 632 static void cxgbe_tick(void *); 633 static void cxgbe_sysctls(struct port_info *); 634 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 635 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 636 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 637 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 638 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 639 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 640 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 641 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 642 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 643 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 644 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 645 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 646 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 647 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 648 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 649 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 650 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 651 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 652 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 653 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 654 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 655 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 656 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 657 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 658 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 659 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 660 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 661 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 662 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 663 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 664 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 665 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 666 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 667 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 668 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 669 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 670 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 671 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 672 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 673 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 674 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 675 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 676 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 677 #ifdef TCP_OFFLOAD 678 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 679 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 680 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 681 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 682 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 683 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 684 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 685 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 686 #endif 687 static int get_sge_context(struct adapter *, struct t4_sge_context *); 688 static int load_fw(struct adapter *, struct t4_data *); 689 static int load_cfg(struct adapter *, struct t4_data *); 690 static int load_boot(struct adapter *, struct t4_bootrom *); 691 static int load_bootcfg(struct adapter *, struct t4_data *); 692 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 693 static void free_offload_policy(struct t4_offload_policy *); 694 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 695 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 696 static int read_i2c(struct adapter *, struct t4_i2c_data *); 697 #ifdef TCP_OFFLOAD 698 static int toe_capability(struct vi_info *, int); 699 #endif 700 static int mod_event(module_t, int, void *); 701 static int notify_siblings(device_t, int); 702 703 struct { 704 uint16_t device; 705 char *desc; 706 } t4_pciids[] = { 707 {0xa000, "Chelsio Terminator 4 FPGA"}, 708 {0x4400, "Chelsio T440-dbg"}, 709 {0x4401, "Chelsio T420-CR"}, 710 {0x4402, "Chelsio T422-CR"}, 711 {0x4403, "Chelsio T440-CR"}, 712 {0x4404, "Chelsio T420-BCH"}, 713 {0x4405, "Chelsio T440-BCH"}, 714 {0x4406, "Chelsio T440-CH"}, 715 {0x4407, "Chelsio T420-SO"}, 716 {0x4408, "Chelsio T420-CX"}, 717 {0x4409, "Chelsio T420-BT"}, 718 {0x440a, "Chelsio T404-BT"}, 719 {0x440e, "Chelsio T440-LP-CR"}, 720 }, t5_pciids[] = { 721 {0xb000, "Chelsio Terminator 5 FPGA"}, 722 {0x5400, "Chelsio T580-dbg"}, 723 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 724 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 725 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 726 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 727 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 728 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 729 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 730 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 731 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 732 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 733 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 734 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 735 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 736 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 737 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 738 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 739 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 740 741 /* Custom */ 742 {0x5483, "Custom T540-CR"}, 743 {0x5484, "Custom T540-BT"}, 744 }, t6_pciids[] = { 745 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 746 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 747 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 748 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 749 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 750 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 751 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 752 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 753 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 754 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 755 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 756 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 757 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 758 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 759 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 760 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 761 762 /* Custom */ 763 {0x6480, "Custom T6225-CR"}, 764 {0x6481, "Custom T62100-CR"}, 765 {0x6482, "Custom T6225-CR"}, 766 {0x6483, "Custom T62100-CR"}, 767 {0x6484, "Custom T64100-CR"}, 768 {0x6485, "Custom T6240-SO"}, 769 {0x6486, "Custom T6225-SO-CR"}, 770 {0x6487, "Custom T6225-CR"}, 771 }; 772 773 #ifdef TCP_OFFLOAD 774 /* 775 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 776 * be exactly the same for both rxq and ofld_rxq. 777 */ 778 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 779 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 780 #endif 781 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 782 783 static int 784 t4_probe(device_t dev) 785 { 786 int i; 787 uint16_t v = pci_get_vendor(dev); 788 uint16_t d = pci_get_device(dev); 789 uint8_t f = pci_get_function(dev); 790 791 if (v != PCI_VENDOR_ID_CHELSIO) 792 return (ENXIO); 793 794 /* Attach only to PF0 of the FPGA */ 795 if (d == 0xa000 && f != 0) 796 return (ENXIO); 797 798 for (i = 0; i < nitems(t4_pciids); i++) { 799 if (d == t4_pciids[i].device) { 800 device_set_desc(dev, t4_pciids[i].desc); 801 return (BUS_PROBE_DEFAULT); 802 } 803 } 804 805 return (ENXIO); 806 } 807 808 static int 809 t5_probe(device_t dev) 810 { 811 int i; 812 uint16_t v = pci_get_vendor(dev); 813 uint16_t d = pci_get_device(dev); 814 uint8_t f = pci_get_function(dev); 815 816 if (v != PCI_VENDOR_ID_CHELSIO) 817 return (ENXIO); 818 819 /* Attach only to PF0 of the FPGA */ 820 if (d == 0xb000 && f != 0) 821 return (ENXIO); 822 823 for (i = 0; i < nitems(t5_pciids); i++) { 824 if (d == t5_pciids[i].device) { 825 device_set_desc(dev, t5_pciids[i].desc); 826 return (BUS_PROBE_DEFAULT); 827 } 828 } 829 830 return (ENXIO); 831 } 832 833 static int 834 t6_probe(device_t dev) 835 { 836 int i; 837 uint16_t v = pci_get_vendor(dev); 838 uint16_t d = pci_get_device(dev); 839 840 if (v != PCI_VENDOR_ID_CHELSIO) 841 return (ENXIO); 842 843 for (i = 0; i < nitems(t6_pciids); i++) { 844 if (d == t6_pciids[i].device) { 845 device_set_desc(dev, t6_pciids[i].desc); 846 return (BUS_PROBE_DEFAULT); 847 } 848 } 849 850 return (ENXIO); 851 } 852 853 static void 854 t5_attribute_workaround(device_t dev) 855 { 856 device_t root_port; 857 uint32_t v; 858 859 /* 860 * The T5 chips do not properly echo the No Snoop and Relaxed 861 * Ordering attributes when replying to a TLP from a Root 862 * Port. As a workaround, find the parent Root Port and 863 * disable No Snoop and Relaxed Ordering. Note that this 864 * affects all devices under this root port. 865 */ 866 root_port = pci_find_pcie_root_port(dev); 867 if (root_port == NULL) { 868 device_printf(dev, "Unable to find parent root port\n"); 869 return; 870 } 871 872 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 873 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 874 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 875 0) 876 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 877 device_get_nameunit(root_port)); 878 } 879 880 static const struct devnames devnames[] = { 881 { 882 .nexus_name = "t4nex", 883 .ifnet_name = "cxgbe", 884 .vi_ifnet_name = "vcxgbe", 885 .pf03_drv_name = "t4iov", 886 .vf_nexus_name = "t4vf", 887 .vf_ifnet_name = "cxgbev" 888 }, { 889 .nexus_name = "t5nex", 890 .ifnet_name = "cxl", 891 .vi_ifnet_name = "vcxl", 892 .pf03_drv_name = "t5iov", 893 .vf_nexus_name = "t5vf", 894 .vf_ifnet_name = "cxlv" 895 }, { 896 .nexus_name = "t6nex", 897 .ifnet_name = "cc", 898 .vi_ifnet_name = "vcc", 899 .pf03_drv_name = "t6iov", 900 .vf_nexus_name = "t6vf", 901 .vf_ifnet_name = "ccv" 902 } 903 }; 904 905 void 906 t4_init_devnames(struct adapter *sc) 907 { 908 int id; 909 910 id = chip_id(sc); 911 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 912 sc->names = &devnames[id - CHELSIO_T4]; 913 else { 914 device_printf(sc->dev, "chip id %d is not supported.\n", id); 915 sc->names = NULL; 916 } 917 } 918 919 static int 920 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 921 { 922 const char *parent, *name; 923 long value; 924 int line, unit; 925 926 line = 0; 927 parent = device_get_nameunit(sc->dev); 928 name = sc->names->ifnet_name; 929 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 930 if (resource_long_value(name, unit, "port", &value) == 0 && 931 value == pi->port_id) 932 return (unit); 933 } 934 return (-1); 935 } 936 937 static int 938 t4_attach(device_t dev) 939 { 940 struct adapter *sc; 941 int rc = 0, i, j, rqidx, tqidx, nports; 942 struct make_dev_args mda; 943 struct intrs_and_queues iaq; 944 struct sge *s; 945 uint32_t *buf; 946 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 947 int ofld_tqidx; 948 #endif 949 #ifdef TCP_OFFLOAD 950 int ofld_rqidx; 951 #endif 952 #ifdef DEV_NETMAP 953 int nm_rqidx, nm_tqidx; 954 #endif 955 int num_vis; 956 957 sc = device_get_softc(dev); 958 sc->dev = dev; 959 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 960 961 if ((pci_get_device(dev) & 0xff00) == 0x5400) 962 t5_attribute_workaround(dev); 963 pci_enable_busmaster(dev); 964 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 965 uint32_t v; 966 967 pci_set_max_read_req(dev, 4096); 968 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 969 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 970 if (pcie_relaxed_ordering == 0 && 971 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 972 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 973 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 974 } else if (pcie_relaxed_ordering == 1 && 975 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 976 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 977 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 978 } 979 } 980 981 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 982 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 983 sc->traceq = -1; 984 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 985 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 986 device_get_nameunit(dev)); 987 988 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 989 device_get_nameunit(dev)); 990 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 991 t4_add_adapter(sc); 992 993 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 994 TAILQ_INIT(&sc->sfl); 995 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 996 997 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 998 999 sc->policy = NULL; 1000 rw_init(&sc->policy_lock, "connection offload policy"); 1001 1002 rc = t4_map_bars_0_and_4(sc); 1003 if (rc != 0) 1004 goto done; /* error message displayed already */ 1005 1006 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1007 1008 /* Prepare the adapter for operation. */ 1009 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1010 rc = -t4_prep_adapter(sc, buf); 1011 free(buf, M_CXGBE); 1012 if (rc != 0) { 1013 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1014 goto done; 1015 } 1016 1017 /* 1018 * This is the real PF# to which we're attaching. Works from within PCI 1019 * passthrough environments too, where pci_get_function() could return a 1020 * different PF# depending on the passthrough configuration. We need to 1021 * use the real PF# in all our communication with the firmware. 1022 */ 1023 j = t4_read_reg(sc, A_PL_WHOAMI); 1024 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1025 sc->mbox = sc->pf; 1026 1027 t4_init_devnames(sc); 1028 if (sc->names == NULL) { 1029 rc = ENOTSUP; 1030 goto done; /* error message displayed already */ 1031 } 1032 1033 /* 1034 * Do this really early, with the memory windows set up even before the 1035 * character device. The userland tool's register i/o and mem read 1036 * will work even in "recovery mode". 1037 */ 1038 setup_memwin(sc); 1039 if (t4_init_devlog_params(sc, 0) == 0) 1040 fixup_devlog_params(sc); 1041 make_dev_args_init(&mda); 1042 mda.mda_devsw = &t4_cdevsw; 1043 mda.mda_uid = UID_ROOT; 1044 mda.mda_gid = GID_WHEEL; 1045 mda.mda_mode = 0600; 1046 mda.mda_si_drv1 = sc; 1047 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1048 if (rc != 0) 1049 device_printf(dev, "failed to create nexus char device: %d.\n", 1050 rc); 1051 1052 /* Go no further if recovery mode has been requested. */ 1053 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1054 device_printf(dev, "recovery mode.\n"); 1055 goto done; 1056 } 1057 1058 #if defined(__i386__) 1059 if ((cpu_feature & CPUID_CX8) == 0) { 1060 device_printf(dev, "64 bit atomics not available.\n"); 1061 rc = ENOTSUP; 1062 goto done; 1063 } 1064 #endif 1065 1066 /* Contact the firmware and try to become the master driver. */ 1067 rc = contact_firmware(sc); 1068 if (rc != 0) 1069 goto done; /* error message displayed already */ 1070 MPASS(sc->flags & FW_OK); 1071 1072 rc = get_params__pre_init(sc); 1073 if (rc != 0) 1074 goto done; /* error message displayed already */ 1075 1076 if (sc->flags & MASTER_PF) { 1077 rc = partition_resources(sc); 1078 if (rc != 0) 1079 goto done; /* error message displayed already */ 1080 t4_intr_clear(sc); 1081 } 1082 1083 rc = get_params__post_init(sc); 1084 if (rc != 0) 1085 goto done; /* error message displayed already */ 1086 1087 rc = set_params__post_init(sc); 1088 if (rc != 0) 1089 goto done; /* error message displayed already */ 1090 1091 rc = t4_map_bar_2(sc); 1092 if (rc != 0) 1093 goto done; /* error message displayed already */ 1094 1095 rc = t4_create_dma_tag(sc); 1096 if (rc != 0) 1097 goto done; /* error message displayed already */ 1098 1099 /* 1100 * First pass over all the ports - allocate VIs and initialize some 1101 * basic parameters like mac address, port type, etc. 1102 */ 1103 for_each_port(sc, i) { 1104 struct port_info *pi; 1105 1106 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1107 sc->port[i] = pi; 1108 1109 /* These must be set before t4_port_init */ 1110 pi->adapter = sc; 1111 pi->port_id = i; 1112 /* 1113 * XXX: vi[0] is special so we can't delay this allocation until 1114 * pi->nvi's final value is known. 1115 */ 1116 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1117 M_ZERO | M_WAITOK); 1118 1119 /* 1120 * Allocate the "main" VI and initialize parameters 1121 * like mac addr. 1122 */ 1123 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1124 if (rc != 0) { 1125 device_printf(dev, "unable to initialize port %d: %d\n", 1126 i, rc); 1127 free(pi->vi, M_CXGBE); 1128 free(pi, M_CXGBE); 1129 sc->port[i] = NULL; 1130 goto done; 1131 } 1132 1133 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1134 device_get_nameunit(dev), i); 1135 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1136 sc->chan_map[pi->tx_chan] = i; 1137 1138 /* All VIs on this port share this media. */ 1139 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1140 cxgbe_media_status); 1141 1142 PORT_LOCK(pi); 1143 init_link_config(pi); 1144 fixup_link_config(pi); 1145 build_medialist(pi); 1146 if (fixed_ifmedia(pi)) 1147 pi->flags |= FIXED_IFMEDIA; 1148 PORT_UNLOCK(pi); 1149 1150 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1151 t4_ifnet_unit(sc, pi)); 1152 if (pi->dev == NULL) { 1153 device_printf(dev, 1154 "failed to add device for port %d.\n", i); 1155 rc = ENXIO; 1156 goto done; 1157 } 1158 pi->vi[0].dev = pi->dev; 1159 device_set_softc(pi->dev, pi); 1160 } 1161 1162 /* 1163 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1164 */ 1165 nports = sc->params.nports; 1166 rc = cfg_itype_and_nqueues(sc, &iaq); 1167 if (rc != 0) 1168 goto done; /* error message displayed already */ 1169 1170 num_vis = iaq.num_vis; 1171 sc->intr_type = iaq.intr_type; 1172 sc->intr_count = iaq.nirq; 1173 1174 s = &sc->sge; 1175 s->nrxq = nports * iaq.nrxq; 1176 s->ntxq = nports * iaq.ntxq; 1177 if (num_vis > 1) { 1178 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1179 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1180 } 1181 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1182 s->neq += nports; /* ctrl queues: 1 per port */ 1183 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1184 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1185 if (is_offload(sc) || is_ethoffload(sc)) { 1186 s->nofldtxq = nports * iaq.nofldtxq; 1187 if (num_vis > 1) 1188 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1189 s->neq += s->nofldtxq; 1190 1191 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1192 M_CXGBE, M_ZERO | M_WAITOK); 1193 } 1194 #endif 1195 #ifdef TCP_OFFLOAD 1196 if (is_offload(sc)) { 1197 s->nofldrxq = nports * iaq.nofldrxq; 1198 if (num_vis > 1) 1199 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1200 s->neq += s->nofldrxq; /* free list */ 1201 s->niq += s->nofldrxq; 1202 1203 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1204 M_CXGBE, M_ZERO | M_WAITOK); 1205 } 1206 #endif 1207 #ifdef DEV_NETMAP 1208 if (num_vis > 1) { 1209 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1210 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1211 } 1212 s->neq += s->nnmtxq + s->nnmrxq; 1213 s->niq += s->nnmrxq; 1214 1215 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1216 M_CXGBE, M_ZERO | M_WAITOK); 1217 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1218 M_CXGBE, M_ZERO | M_WAITOK); 1219 #endif 1220 1221 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1222 M_ZERO | M_WAITOK); 1223 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1224 M_ZERO | M_WAITOK); 1225 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1226 M_ZERO | M_WAITOK); 1227 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1228 M_ZERO | M_WAITOK); 1229 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1230 M_ZERO | M_WAITOK); 1231 1232 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1233 M_ZERO | M_WAITOK); 1234 1235 t4_init_l2t(sc, M_WAITOK); 1236 t4_init_smt(sc, M_WAITOK); 1237 t4_init_tx_sched(sc); 1238 #ifdef RATELIMIT 1239 t4_init_etid_table(sc); 1240 #endif 1241 #ifdef INET6 1242 t4_init_clip_table(sc); 1243 #endif 1244 if (sc->vres.key.size != 0) 1245 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1246 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1247 1248 /* 1249 * Second pass over the ports. This time we know the number of rx and 1250 * tx queues that each port should get. 1251 */ 1252 rqidx = tqidx = 0; 1253 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1254 ofld_tqidx = 0; 1255 #endif 1256 #ifdef TCP_OFFLOAD 1257 ofld_rqidx = 0; 1258 #endif 1259 #ifdef DEV_NETMAP 1260 nm_rqidx = nm_tqidx = 0; 1261 #endif 1262 for_each_port(sc, i) { 1263 struct port_info *pi = sc->port[i]; 1264 struct vi_info *vi; 1265 1266 if (pi == NULL) 1267 continue; 1268 1269 pi->nvi = num_vis; 1270 for_each_vi(pi, j, vi) { 1271 vi->pi = pi; 1272 vi->qsize_rxq = t4_qsize_rxq; 1273 vi->qsize_txq = t4_qsize_txq; 1274 1275 vi->first_rxq = rqidx; 1276 vi->first_txq = tqidx; 1277 vi->tmr_idx = t4_tmr_idx; 1278 vi->pktc_idx = t4_pktc_idx; 1279 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1280 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1281 1282 rqidx += vi->nrxq; 1283 tqidx += vi->ntxq; 1284 1285 if (j == 0 && vi->ntxq > 1) 1286 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1287 else 1288 vi->rsrv_noflowq = 0; 1289 1290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1291 vi->first_ofld_txq = ofld_tqidx; 1292 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1293 ofld_tqidx += vi->nofldtxq; 1294 #endif 1295 #ifdef TCP_OFFLOAD 1296 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1297 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1298 vi->first_ofld_rxq = ofld_rqidx; 1299 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1300 1301 ofld_rqidx += vi->nofldrxq; 1302 #endif 1303 #ifdef DEV_NETMAP 1304 if (j > 0) { 1305 vi->first_nm_rxq = nm_rqidx; 1306 vi->first_nm_txq = nm_tqidx; 1307 vi->nnmrxq = iaq.nnmrxq_vi; 1308 vi->nnmtxq = iaq.nnmtxq_vi; 1309 nm_rqidx += vi->nnmrxq; 1310 nm_tqidx += vi->nnmtxq; 1311 } 1312 #endif 1313 } 1314 } 1315 1316 rc = t4_setup_intr_handlers(sc); 1317 if (rc != 0) { 1318 device_printf(dev, 1319 "failed to setup interrupt handlers: %d\n", rc); 1320 goto done; 1321 } 1322 1323 rc = bus_generic_probe(dev); 1324 if (rc != 0) { 1325 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1326 goto done; 1327 } 1328 1329 /* 1330 * Ensure thread-safe mailbox access (in debug builds). 1331 * 1332 * So far this was the only thread accessing the mailbox but various 1333 * ifnets and sysctls are about to be created and their handlers/ioctls 1334 * will access the mailbox from different threads. 1335 */ 1336 sc->flags |= CHK_MBOX_ACCESS; 1337 1338 rc = bus_generic_attach(dev); 1339 if (rc != 0) { 1340 device_printf(dev, 1341 "failed to attach all child ports: %d\n", rc); 1342 goto done; 1343 } 1344 1345 device_printf(dev, 1346 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1347 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1348 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1349 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1350 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1351 1352 t4_set_desc(sc); 1353 1354 notify_siblings(dev, 0); 1355 1356 done: 1357 if (rc != 0 && sc->cdev) { 1358 /* cdev was created and so cxgbetool works; recover that way. */ 1359 device_printf(dev, 1360 "error during attach, adapter is now in recovery mode.\n"); 1361 rc = 0; 1362 } 1363 1364 if (rc != 0) 1365 t4_detach_common(dev); 1366 else 1367 t4_sysctls(sc); 1368 1369 return (rc); 1370 } 1371 1372 static int 1373 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen) 1374 { 1375 struct adapter *sc; 1376 struct port_info *pi; 1377 int i; 1378 1379 sc = device_get_softc(bus); 1380 buf[0] = '\0'; 1381 for_each_port(sc, i) { 1382 pi = sc->port[i]; 1383 if (pi != NULL && pi->dev == dev) { 1384 snprintf(buf, buflen, "port=%d", pi->port_id); 1385 break; 1386 } 1387 } 1388 return (0); 1389 } 1390 1391 static int 1392 t4_ready(device_t dev) 1393 { 1394 struct adapter *sc; 1395 1396 sc = device_get_softc(dev); 1397 if (sc->flags & FW_OK) 1398 return (0); 1399 return (ENXIO); 1400 } 1401 1402 static int 1403 t4_read_port_device(device_t dev, int port, device_t *child) 1404 { 1405 struct adapter *sc; 1406 struct port_info *pi; 1407 1408 sc = device_get_softc(dev); 1409 if (port < 0 || port >= MAX_NPORTS) 1410 return (EINVAL); 1411 pi = sc->port[port]; 1412 if (pi == NULL || pi->dev == NULL) 1413 return (ENXIO); 1414 *child = pi->dev; 1415 return (0); 1416 } 1417 1418 static int 1419 notify_siblings(device_t dev, int detaching) 1420 { 1421 device_t sibling; 1422 int error, i; 1423 1424 error = 0; 1425 for (i = 0; i < PCI_FUNCMAX; i++) { 1426 if (i == pci_get_function(dev)) 1427 continue; 1428 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1429 pci_get_slot(dev), i); 1430 if (sibling == NULL || !device_is_attached(sibling)) 1431 continue; 1432 if (detaching) 1433 error = T4_DETACH_CHILD(sibling); 1434 else 1435 (void)T4_ATTACH_CHILD(sibling); 1436 if (error) 1437 break; 1438 } 1439 return (error); 1440 } 1441 1442 /* 1443 * Idempotent 1444 */ 1445 static int 1446 t4_detach(device_t dev) 1447 { 1448 struct adapter *sc; 1449 int rc; 1450 1451 sc = device_get_softc(dev); 1452 1453 rc = notify_siblings(dev, 1); 1454 if (rc) { 1455 device_printf(dev, 1456 "failed to detach sibling devices: %d\n", rc); 1457 return (rc); 1458 } 1459 1460 return (t4_detach_common(dev)); 1461 } 1462 1463 int 1464 t4_detach_common(device_t dev) 1465 { 1466 struct adapter *sc; 1467 struct port_info *pi; 1468 int i, rc; 1469 1470 sc = device_get_softc(dev); 1471 1472 if (sc->cdev) { 1473 destroy_dev(sc->cdev); 1474 sc->cdev = NULL; 1475 } 1476 1477 sc->flags &= ~CHK_MBOX_ACCESS; 1478 if (sc->flags & FULL_INIT_DONE) { 1479 if (!(sc->flags & IS_VF)) 1480 t4_intr_disable(sc); 1481 } 1482 1483 if (device_is_attached(dev)) { 1484 rc = bus_generic_detach(dev); 1485 if (rc) { 1486 device_printf(dev, 1487 "failed to detach child devices: %d\n", rc); 1488 return (rc); 1489 } 1490 } 1491 1492 for (i = 0; i < sc->intr_count; i++) 1493 t4_free_irq(sc, &sc->irq[i]); 1494 1495 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1496 t4_free_tx_sched(sc); 1497 1498 for (i = 0; i < MAX_NPORTS; i++) { 1499 pi = sc->port[i]; 1500 if (pi) { 1501 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1502 if (pi->dev) 1503 device_delete_child(dev, pi->dev); 1504 1505 mtx_destroy(&pi->pi_lock); 1506 free(pi->vi, M_CXGBE); 1507 free(pi, M_CXGBE); 1508 } 1509 } 1510 1511 device_delete_children(dev); 1512 1513 if (sc->flags & FULL_INIT_DONE) 1514 adapter_full_uninit(sc); 1515 1516 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1517 t4_fw_bye(sc, sc->mbox); 1518 1519 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1520 pci_release_msi(dev); 1521 1522 if (sc->regs_res) 1523 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1524 sc->regs_res); 1525 1526 if (sc->udbs_res) 1527 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1528 sc->udbs_res); 1529 1530 if (sc->msix_res) 1531 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1532 sc->msix_res); 1533 1534 if (sc->l2t) 1535 t4_free_l2t(sc->l2t); 1536 if (sc->smt) 1537 t4_free_smt(sc->smt); 1538 #ifdef RATELIMIT 1539 t4_free_etid_table(sc); 1540 #endif 1541 if (sc->key_map) 1542 vmem_destroy(sc->key_map); 1543 #ifdef INET6 1544 t4_destroy_clip_table(sc); 1545 #endif 1546 1547 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1548 free(sc->sge.ofld_txq, M_CXGBE); 1549 #endif 1550 #ifdef TCP_OFFLOAD 1551 free(sc->sge.ofld_rxq, M_CXGBE); 1552 #endif 1553 #ifdef DEV_NETMAP 1554 free(sc->sge.nm_rxq, M_CXGBE); 1555 free(sc->sge.nm_txq, M_CXGBE); 1556 #endif 1557 free(sc->irq, M_CXGBE); 1558 free(sc->sge.rxq, M_CXGBE); 1559 free(sc->sge.txq, M_CXGBE); 1560 free(sc->sge.ctrlq, M_CXGBE); 1561 free(sc->sge.iqmap, M_CXGBE); 1562 free(sc->sge.eqmap, M_CXGBE); 1563 free(sc->tids.ftid_tab, M_CXGBE); 1564 free(sc->tids.hpftid_tab, M_CXGBE); 1565 free_hftid_hash(&sc->tids); 1566 free(sc->tids.atid_tab, M_CXGBE); 1567 free(sc->tids.tid_tab, M_CXGBE); 1568 free(sc->tt.tls_rx_ports, M_CXGBE); 1569 t4_destroy_dma_tag(sc); 1570 if (mtx_initialized(&sc->sc_lock)) { 1571 sx_xlock(&t4_list_lock); 1572 SLIST_REMOVE(&t4_list, sc, adapter, link); 1573 sx_xunlock(&t4_list_lock); 1574 mtx_destroy(&sc->sc_lock); 1575 } 1576 1577 callout_drain(&sc->sfl_callout); 1578 if (mtx_initialized(&sc->tids.ftid_lock)) { 1579 mtx_destroy(&sc->tids.ftid_lock); 1580 cv_destroy(&sc->tids.ftid_cv); 1581 } 1582 if (mtx_initialized(&sc->tids.atid_lock)) 1583 mtx_destroy(&sc->tids.atid_lock); 1584 if (mtx_initialized(&sc->sfl_lock)) 1585 mtx_destroy(&sc->sfl_lock); 1586 if (mtx_initialized(&sc->ifp_lock)) 1587 mtx_destroy(&sc->ifp_lock); 1588 if (mtx_initialized(&sc->reg_lock)) 1589 mtx_destroy(&sc->reg_lock); 1590 1591 if (rw_initialized(&sc->policy_lock)) { 1592 rw_destroy(&sc->policy_lock); 1593 #ifdef TCP_OFFLOAD 1594 if (sc->policy != NULL) 1595 free_offload_policy(sc->policy); 1596 #endif 1597 } 1598 1599 for (i = 0; i < NUM_MEMWIN; i++) { 1600 struct memwin *mw = &sc->memwin[i]; 1601 1602 if (rw_initialized(&mw->mw_lock)) 1603 rw_destroy(&mw->mw_lock); 1604 } 1605 1606 bzero(sc, sizeof(*sc)); 1607 1608 return (0); 1609 } 1610 1611 static int 1612 cxgbe_probe(device_t dev) 1613 { 1614 char buf[128]; 1615 struct port_info *pi = device_get_softc(dev); 1616 1617 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1618 device_set_desc_copy(dev, buf); 1619 1620 return (BUS_PROBE_DEFAULT); 1621 } 1622 1623 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1624 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1625 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 1626 IFCAP_HWRXTSTMP) 1627 #define T4_CAP_ENABLE (T4_CAP) 1628 1629 static int 1630 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1631 { 1632 struct ifnet *ifp; 1633 struct sbuf *sb; 1634 1635 vi->xact_addr_filt = -1; 1636 callout_init(&vi->tick, 1); 1637 1638 /* Allocate an ifnet and set it up */ 1639 ifp = if_alloc_dev(IFT_ETHER, dev); 1640 if (ifp == NULL) { 1641 device_printf(dev, "Cannot allocate ifnet\n"); 1642 return (ENOMEM); 1643 } 1644 vi->ifp = ifp; 1645 ifp->if_softc = vi; 1646 1647 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1648 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1649 1650 ifp->if_init = cxgbe_init; 1651 ifp->if_ioctl = cxgbe_ioctl; 1652 ifp->if_transmit = cxgbe_transmit; 1653 ifp->if_qflush = cxgbe_qflush; 1654 ifp->if_get_counter = cxgbe_get_counter; 1655 #ifdef RATELIMIT 1656 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 1657 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify; 1658 ifp->if_snd_tag_query = cxgbe_snd_tag_query; 1659 ifp->if_snd_tag_free = cxgbe_snd_tag_free; 1660 #endif 1661 1662 ifp->if_capabilities = T4_CAP; 1663 ifp->if_capenable = T4_CAP_ENABLE; 1664 #ifdef TCP_OFFLOAD 1665 if (vi->nofldrxq != 0) 1666 ifp->if_capabilities |= IFCAP_TOE; 1667 #endif 1668 #ifdef RATELIMIT 1669 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) { 1670 ifp->if_capabilities |= IFCAP_TXRTLMT; 1671 ifp->if_capenable |= IFCAP_TXRTLMT; 1672 } 1673 #endif 1674 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1675 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1676 1677 ifp->if_hw_tsomax = IP_MAXPACKET; 1678 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 1679 #ifdef RATELIMIT 1680 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) 1681 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO; 1682 #endif 1683 ifp->if_hw_tsomaxsegsize = 65536; 1684 1685 ether_ifattach(ifp, vi->hw_addr); 1686 #ifdef DEV_NETMAP 1687 if (vi->nnmrxq != 0) 1688 cxgbe_nm_attach(vi); 1689 #endif 1690 sb = sbuf_new_auto(); 1691 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1692 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1693 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 1694 case IFCAP_TOE: 1695 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 1696 break; 1697 case IFCAP_TOE | IFCAP_TXRTLMT: 1698 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 1699 break; 1700 case IFCAP_TXRTLMT: 1701 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 1702 break; 1703 } 1704 #endif 1705 #ifdef TCP_OFFLOAD 1706 if (ifp->if_capabilities & IFCAP_TOE) 1707 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 1708 #endif 1709 #ifdef DEV_NETMAP 1710 if (ifp->if_capabilities & IFCAP_NETMAP) 1711 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1712 vi->nnmtxq, vi->nnmrxq); 1713 #endif 1714 sbuf_finish(sb); 1715 device_printf(dev, "%s\n", sbuf_data(sb)); 1716 sbuf_delete(sb); 1717 1718 vi_sysctls(vi); 1719 1720 return (0); 1721 } 1722 1723 static int 1724 cxgbe_attach(device_t dev) 1725 { 1726 struct port_info *pi = device_get_softc(dev); 1727 struct adapter *sc = pi->adapter; 1728 struct vi_info *vi; 1729 int i, rc; 1730 1731 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1732 1733 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1734 if (rc) 1735 return (rc); 1736 1737 for_each_vi(pi, i, vi) { 1738 if (i == 0) 1739 continue; 1740 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1741 if (vi->dev == NULL) { 1742 device_printf(dev, "failed to add VI %d\n", i); 1743 continue; 1744 } 1745 device_set_softc(vi->dev, vi); 1746 } 1747 1748 cxgbe_sysctls(pi); 1749 1750 bus_generic_attach(dev); 1751 1752 return (0); 1753 } 1754 1755 static void 1756 cxgbe_vi_detach(struct vi_info *vi) 1757 { 1758 struct ifnet *ifp = vi->ifp; 1759 1760 ether_ifdetach(ifp); 1761 1762 /* Let detach proceed even if these fail. */ 1763 #ifdef DEV_NETMAP 1764 if (ifp->if_capabilities & IFCAP_NETMAP) 1765 cxgbe_nm_detach(vi); 1766 #endif 1767 cxgbe_uninit_synchronized(vi); 1768 callout_drain(&vi->tick); 1769 vi_full_uninit(vi); 1770 1771 if_free(vi->ifp); 1772 vi->ifp = NULL; 1773 } 1774 1775 static int 1776 cxgbe_detach(device_t dev) 1777 { 1778 struct port_info *pi = device_get_softc(dev); 1779 struct adapter *sc = pi->adapter; 1780 int rc; 1781 1782 /* Detach the extra VIs first. */ 1783 rc = bus_generic_detach(dev); 1784 if (rc) 1785 return (rc); 1786 device_delete_children(dev); 1787 1788 doom_vi(sc, &pi->vi[0]); 1789 1790 if (pi->flags & HAS_TRACEQ) { 1791 sc->traceq = -1; /* cloner should not create ifnet */ 1792 t4_tracer_port_detach(sc); 1793 } 1794 1795 cxgbe_vi_detach(&pi->vi[0]); 1796 callout_drain(&pi->tick); 1797 ifmedia_removeall(&pi->media); 1798 1799 end_synchronized_op(sc, 0); 1800 1801 return (0); 1802 } 1803 1804 static void 1805 cxgbe_init(void *arg) 1806 { 1807 struct vi_info *vi = arg; 1808 struct adapter *sc = vi->pi->adapter; 1809 1810 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1811 return; 1812 cxgbe_init_synchronized(vi); 1813 end_synchronized_op(sc, 0); 1814 } 1815 1816 static int 1817 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1818 { 1819 int rc = 0, mtu, flags; 1820 struct vi_info *vi = ifp->if_softc; 1821 struct port_info *pi = vi->pi; 1822 struct adapter *sc = pi->adapter; 1823 struct ifreq *ifr = (struct ifreq *)data; 1824 uint32_t mask; 1825 1826 switch (cmd) { 1827 case SIOCSIFMTU: 1828 mtu = ifr->ifr_mtu; 1829 if (mtu < ETHERMIN || mtu > MAX_MTU) 1830 return (EINVAL); 1831 1832 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1833 if (rc) 1834 return (rc); 1835 ifp->if_mtu = mtu; 1836 if (vi->flags & VI_INIT_DONE) { 1837 t4_update_fl_bufsize(ifp); 1838 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1839 rc = update_mac_settings(ifp, XGMAC_MTU); 1840 } 1841 end_synchronized_op(sc, 0); 1842 break; 1843 1844 case SIOCSIFFLAGS: 1845 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 1846 if (rc) 1847 return (rc); 1848 1849 if (ifp->if_flags & IFF_UP) { 1850 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1851 flags = vi->if_flags; 1852 if ((ifp->if_flags ^ flags) & 1853 (IFF_PROMISC | IFF_ALLMULTI)) { 1854 rc = update_mac_settings(ifp, 1855 XGMAC_PROMISC | XGMAC_ALLMULTI); 1856 } 1857 } else { 1858 rc = cxgbe_init_synchronized(vi); 1859 } 1860 vi->if_flags = ifp->if_flags; 1861 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1862 rc = cxgbe_uninit_synchronized(vi); 1863 } 1864 end_synchronized_op(sc, 0); 1865 break; 1866 1867 case SIOCADDMULTI: 1868 case SIOCDELMULTI: 1869 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 1870 if (rc) 1871 return (rc); 1872 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1873 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1874 end_synchronized_op(sc, 0); 1875 break; 1876 1877 case SIOCSIFCAP: 1878 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1879 if (rc) 1880 return (rc); 1881 1882 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1883 if (mask & IFCAP_TXCSUM) { 1884 ifp->if_capenable ^= IFCAP_TXCSUM; 1885 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1886 1887 if (IFCAP_TSO4 & ifp->if_capenable && 1888 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1889 ifp->if_capenable &= ~IFCAP_TSO4; 1890 if_printf(ifp, 1891 "tso4 disabled due to -txcsum.\n"); 1892 } 1893 } 1894 if (mask & IFCAP_TXCSUM_IPV6) { 1895 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1896 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1897 1898 if (IFCAP_TSO6 & ifp->if_capenable && 1899 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1900 ifp->if_capenable &= ~IFCAP_TSO6; 1901 if_printf(ifp, 1902 "tso6 disabled due to -txcsum6.\n"); 1903 } 1904 } 1905 if (mask & IFCAP_RXCSUM) 1906 ifp->if_capenable ^= IFCAP_RXCSUM; 1907 if (mask & IFCAP_RXCSUM_IPV6) 1908 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1909 1910 /* 1911 * Note that we leave CSUM_TSO alone (it is always set). The 1912 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1913 * sending a TSO request our way, so it's sufficient to toggle 1914 * IFCAP_TSOx only. 1915 */ 1916 if (mask & IFCAP_TSO4) { 1917 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1918 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1919 if_printf(ifp, "enable txcsum first.\n"); 1920 rc = EAGAIN; 1921 goto fail; 1922 } 1923 ifp->if_capenable ^= IFCAP_TSO4; 1924 } 1925 if (mask & IFCAP_TSO6) { 1926 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1927 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1928 if_printf(ifp, "enable txcsum6 first.\n"); 1929 rc = EAGAIN; 1930 goto fail; 1931 } 1932 ifp->if_capenable ^= IFCAP_TSO6; 1933 } 1934 if (mask & IFCAP_LRO) { 1935 #if defined(INET) || defined(INET6) 1936 int i; 1937 struct sge_rxq *rxq; 1938 1939 ifp->if_capenable ^= IFCAP_LRO; 1940 for_each_rxq(vi, i, rxq) { 1941 if (ifp->if_capenable & IFCAP_LRO) 1942 rxq->iq.flags |= IQ_LRO_ENABLED; 1943 else 1944 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1945 } 1946 #endif 1947 } 1948 #ifdef TCP_OFFLOAD 1949 if (mask & IFCAP_TOE) { 1950 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1951 1952 rc = toe_capability(vi, enable); 1953 if (rc != 0) 1954 goto fail; 1955 1956 ifp->if_capenable ^= mask; 1957 } 1958 #endif 1959 if (mask & IFCAP_VLAN_HWTAGGING) { 1960 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1961 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1962 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1963 } 1964 if (mask & IFCAP_VLAN_MTU) { 1965 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1966 1967 /* Need to find out how to disable auto-mtu-inflation */ 1968 } 1969 if (mask & IFCAP_VLAN_HWTSO) 1970 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1971 if (mask & IFCAP_VLAN_HWCSUM) 1972 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1973 #ifdef RATELIMIT 1974 if (mask & IFCAP_TXRTLMT) 1975 ifp->if_capenable ^= IFCAP_TXRTLMT; 1976 #endif 1977 if (mask & IFCAP_HWRXTSTMP) { 1978 int i; 1979 struct sge_rxq *rxq; 1980 1981 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 1982 for_each_rxq(vi, i, rxq) { 1983 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 1984 rxq->iq.flags |= IQ_RX_TIMESTAMP; 1985 else 1986 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 1987 } 1988 } 1989 1990 #ifdef VLAN_CAPABILITIES 1991 VLAN_CAPABILITIES(ifp); 1992 #endif 1993 fail: 1994 end_synchronized_op(sc, 0); 1995 break; 1996 1997 case SIOCSIFMEDIA: 1998 case SIOCGIFMEDIA: 1999 case SIOCGIFXMEDIA: 2000 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 2001 break; 2002 2003 case SIOCGI2C: { 2004 struct ifi2creq i2c; 2005 2006 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 2007 if (rc != 0) 2008 break; 2009 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 2010 rc = EPERM; 2011 break; 2012 } 2013 if (i2c.len > sizeof(i2c.data)) { 2014 rc = EINVAL; 2015 break; 2016 } 2017 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 2018 if (rc) 2019 return (rc); 2020 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 2021 i2c.offset, i2c.len, &i2c.data[0]); 2022 end_synchronized_op(sc, 0); 2023 if (rc == 0) 2024 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 2025 break; 2026 } 2027 2028 default: 2029 rc = ether_ioctl(ifp, cmd, data); 2030 } 2031 2032 return (rc); 2033 } 2034 2035 static int 2036 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 2037 { 2038 struct vi_info *vi = ifp->if_softc; 2039 struct port_info *pi = vi->pi; 2040 struct adapter *sc = pi->adapter; 2041 struct sge_txq *txq; 2042 void *items[1]; 2043 int rc; 2044 2045 M_ASSERTPKTHDR(m); 2046 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 2047 2048 if (__predict_false(pi->link_cfg.link_ok == false)) { 2049 m_freem(m); 2050 return (ENETDOWN); 2051 } 2052 2053 rc = parse_pkt(sc, &m); 2054 if (__predict_false(rc != 0)) { 2055 MPASS(m == NULL); /* was freed already */ 2056 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 2057 return (rc); 2058 } 2059 #ifdef RATELIMIT 2060 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) { 2061 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 2062 return (ethofld_transmit(ifp, m)); 2063 } 2064 #endif 2065 2066 /* Select a txq. */ 2067 txq = &sc->sge.txq[vi->first_txq]; 2068 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2069 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 2070 vi->rsrv_noflowq); 2071 2072 items[0] = m; 2073 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 2074 if (__predict_false(rc != 0)) 2075 m_freem(m); 2076 2077 return (rc); 2078 } 2079 2080 static void 2081 cxgbe_qflush(struct ifnet *ifp) 2082 { 2083 struct vi_info *vi = ifp->if_softc; 2084 struct sge_txq *txq; 2085 int i; 2086 2087 /* queues do not exist if !VI_INIT_DONE. */ 2088 if (vi->flags & VI_INIT_DONE) { 2089 for_each_txq(vi, i, txq) { 2090 TXQ_LOCK(txq); 2091 txq->eq.flags |= EQ_QFLUSH; 2092 TXQ_UNLOCK(txq); 2093 while (!mp_ring_is_idle(txq->r)) { 2094 mp_ring_check_drainage(txq->r, 0); 2095 pause("qflush", 1); 2096 } 2097 TXQ_LOCK(txq); 2098 txq->eq.flags &= ~EQ_QFLUSH; 2099 TXQ_UNLOCK(txq); 2100 } 2101 } 2102 if_qflush(ifp); 2103 } 2104 2105 static uint64_t 2106 vi_get_counter(struct ifnet *ifp, ift_counter c) 2107 { 2108 struct vi_info *vi = ifp->if_softc; 2109 struct fw_vi_stats_vf *s = &vi->stats; 2110 2111 vi_refresh_stats(vi->pi->adapter, vi); 2112 2113 switch (c) { 2114 case IFCOUNTER_IPACKETS: 2115 return (s->rx_bcast_frames + s->rx_mcast_frames + 2116 s->rx_ucast_frames); 2117 case IFCOUNTER_IERRORS: 2118 return (s->rx_err_frames); 2119 case IFCOUNTER_OPACKETS: 2120 return (s->tx_bcast_frames + s->tx_mcast_frames + 2121 s->tx_ucast_frames + s->tx_offload_frames); 2122 case IFCOUNTER_OERRORS: 2123 return (s->tx_drop_frames); 2124 case IFCOUNTER_IBYTES: 2125 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 2126 s->rx_ucast_bytes); 2127 case IFCOUNTER_OBYTES: 2128 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 2129 s->tx_ucast_bytes + s->tx_offload_bytes); 2130 case IFCOUNTER_IMCASTS: 2131 return (s->rx_mcast_frames); 2132 case IFCOUNTER_OMCASTS: 2133 return (s->tx_mcast_frames); 2134 case IFCOUNTER_OQDROPS: { 2135 uint64_t drops; 2136 2137 drops = 0; 2138 if (vi->flags & VI_INIT_DONE) { 2139 int i; 2140 struct sge_txq *txq; 2141 2142 for_each_txq(vi, i, txq) 2143 drops += counter_u64_fetch(txq->r->drops); 2144 } 2145 2146 return (drops); 2147 2148 } 2149 2150 default: 2151 return (if_get_counter_default(ifp, c)); 2152 } 2153 } 2154 2155 uint64_t 2156 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2157 { 2158 struct vi_info *vi = ifp->if_softc; 2159 struct port_info *pi = vi->pi; 2160 struct adapter *sc = pi->adapter; 2161 struct port_stats *s = &pi->stats; 2162 2163 if (pi->nvi > 1 || sc->flags & IS_VF) 2164 return (vi_get_counter(ifp, c)); 2165 2166 cxgbe_refresh_stats(sc, pi); 2167 2168 switch (c) { 2169 case IFCOUNTER_IPACKETS: 2170 return (s->rx_frames); 2171 2172 case IFCOUNTER_IERRORS: 2173 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2174 s->rx_fcs_err + s->rx_len_err); 2175 2176 case IFCOUNTER_OPACKETS: 2177 return (s->tx_frames); 2178 2179 case IFCOUNTER_OERRORS: 2180 return (s->tx_error_frames); 2181 2182 case IFCOUNTER_IBYTES: 2183 return (s->rx_octets); 2184 2185 case IFCOUNTER_OBYTES: 2186 return (s->tx_octets); 2187 2188 case IFCOUNTER_IMCASTS: 2189 return (s->rx_mcast_frames); 2190 2191 case IFCOUNTER_OMCASTS: 2192 return (s->tx_mcast_frames); 2193 2194 case IFCOUNTER_IQDROPS: 2195 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2196 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2197 s->rx_trunc3 + pi->tnl_cong_drops); 2198 2199 case IFCOUNTER_OQDROPS: { 2200 uint64_t drops; 2201 2202 drops = s->tx_drop; 2203 if (vi->flags & VI_INIT_DONE) { 2204 int i; 2205 struct sge_txq *txq; 2206 2207 for_each_txq(vi, i, txq) 2208 drops += counter_u64_fetch(txq->r->drops); 2209 } 2210 2211 return (drops); 2212 2213 } 2214 2215 default: 2216 return (if_get_counter_default(ifp, c)); 2217 } 2218 } 2219 2220 /* 2221 * The kernel picks a media from the list we had provided but we still validate 2222 * the requeste. 2223 */ 2224 int 2225 cxgbe_media_change(struct ifnet *ifp) 2226 { 2227 struct vi_info *vi = ifp->if_softc; 2228 struct port_info *pi = vi->pi; 2229 struct ifmedia *ifm = &pi->media; 2230 struct link_config *lc = &pi->link_cfg; 2231 struct adapter *sc = pi->adapter; 2232 int rc; 2233 2234 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2235 if (rc != 0) 2236 return (rc); 2237 PORT_LOCK(pi); 2238 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2239 /* ifconfig .. media autoselect */ 2240 if (!(lc->supported & FW_PORT_CAP32_ANEG)) { 2241 rc = ENOTSUP; /* AN not supported by transceiver */ 2242 goto done; 2243 } 2244 lc->requested_aneg = AUTONEG_ENABLE; 2245 lc->requested_speed = 0; 2246 lc->requested_fc |= PAUSE_AUTONEG; 2247 } else { 2248 lc->requested_aneg = AUTONEG_DISABLE; 2249 lc->requested_speed = 2250 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2251 lc->requested_fc = 0; 2252 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2253 lc->requested_fc |= PAUSE_RX; 2254 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2255 lc->requested_fc |= PAUSE_TX; 2256 } 2257 if (pi->up_vis > 0) { 2258 fixup_link_config(pi); 2259 rc = apply_link_config(pi); 2260 } 2261 done: 2262 PORT_UNLOCK(pi); 2263 end_synchronized_op(sc, 0); 2264 return (rc); 2265 } 2266 2267 /* 2268 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2269 * given speed. 2270 */ 2271 static int 2272 port_mword(struct port_info *pi, uint32_t speed) 2273 { 2274 2275 MPASS(speed & M_FW_PORT_CAP32_SPEED); 2276 MPASS(powerof2(speed)); 2277 2278 switch(pi->port_type) { 2279 case FW_PORT_TYPE_BT_SGMII: 2280 case FW_PORT_TYPE_BT_XFI: 2281 case FW_PORT_TYPE_BT_XAUI: 2282 /* BaseT */ 2283 switch (speed) { 2284 case FW_PORT_CAP32_SPEED_100M: 2285 return (IFM_100_T); 2286 case FW_PORT_CAP32_SPEED_1G: 2287 return (IFM_1000_T); 2288 case FW_PORT_CAP32_SPEED_10G: 2289 return (IFM_10G_T); 2290 } 2291 break; 2292 case FW_PORT_TYPE_KX4: 2293 if (speed == FW_PORT_CAP32_SPEED_10G) 2294 return (IFM_10G_KX4); 2295 break; 2296 case FW_PORT_TYPE_CX4: 2297 if (speed == FW_PORT_CAP32_SPEED_10G) 2298 return (IFM_10G_CX4); 2299 break; 2300 case FW_PORT_TYPE_KX: 2301 if (speed == FW_PORT_CAP32_SPEED_1G) 2302 return (IFM_1000_KX); 2303 break; 2304 case FW_PORT_TYPE_KR: 2305 case FW_PORT_TYPE_BP_AP: 2306 case FW_PORT_TYPE_BP4_AP: 2307 case FW_PORT_TYPE_BP40_BA: 2308 case FW_PORT_TYPE_KR4_100G: 2309 case FW_PORT_TYPE_KR_SFP28: 2310 case FW_PORT_TYPE_KR_XLAUI: 2311 switch (speed) { 2312 case FW_PORT_CAP32_SPEED_1G: 2313 return (IFM_1000_KX); 2314 case FW_PORT_CAP32_SPEED_10G: 2315 return (IFM_10G_KR); 2316 case FW_PORT_CAP32_SPEED_25G: 2317 return (IFM_25G_KR); 2318 case FW_PORT_CAP32_SPEED_40G: 2319 return (IFM_40G_KR4); 2320 case FW_PORT_CAP32_SPEED_50G: 2321 return (IFM_50G_KR2); 2322 case FW_PORT_CAP32_SPEED_100G: 2323 return (IFM_100G_KR4); 2324 } 2325 break; 2326 case FW_PORT_TYPE_FIBER_XFI: 2327 case FW_PORT_TYPE_FIBER_XAUI: 2328 case FW_PORT_TYPE_SFP: 2329 case FW_PORT_TYPE_QSFP_10G: 2330 case FW_PORT_TYPE_QSA: 2331 case FW_PORT_TYPE_QSFP: 2332 case FW_PORT_TYPE_CR4_QSFP: 2333 case FW_PORT_TYPE_CR_QSFP: 2334 case FW_PORT_TYPE_CR2_QSFP: 2335 case FW_PORT_TYPE_SFP28: 2336 /* Pluggable transceiver */ 2337 switch (pi->mod_type) { 2338 case FW_PORT_MOD_TYPE_LR: 2339 switch (speed) { 2340 case FW_PORT_CAP32_SPEED_1G: 2341 return (IFM_1000_LX); 2342 case FW_PORT_CAP32_SPEED_10G: 2343 return (IFM_10G_LR); 2344 case FW_PORT_CAP32_SPEED_25G: 2345 return (IFM_25G_LR); 2346 case FW_PORT_CAP32_SPEED_40G: 2347 return (IFM_40G_LR4); 2348 case FW_PORT_CAP32_SPEED_50G: 2349 return (IFM_50G_LR2); 2350 case FW_PORT_CAP32_SPEED_100G: 2351 return (IFM_100G_LR4); 2352 } 2353 break; 2354 case FW_PORT_MOD_TYPE_SR: 2355 switch (speed) { 2356 case FW_PORT_CAP32_SPEED_1G: 2357 return (IFM_1000_SX); 2358 case FW_PORT_CAP32_SPEED_10G: 2359 return (IFM_10G_SR); 2360 case FW_PORT_CAP32_SPEED_25G: 2361 return (IFM_25G_SR); 2362 case FW_PORT_CAP32_SPEED_40G: 2363 return (IFM_40G_SR4); 2364 case FW_PORT_CAP32_SPEED_50G: 2365 return (IFM_50G_SR2); 2366 case FW_PORT_CAP32_SPEED_100G: 2367 return (IFM_100G_SR4); 2368 } 2369 break; 2370 case FW_PORT_MOD_TYPE_ER: 2371 if (speed == FW_PORT_CAP32_SPEED_10G) 2372 return (IFM_10G_ER); 2373 break; 2374 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2375 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2376 switch (speed) { 2377 case FW_PORT_CAP32_SPEED_1G: 2378 return (IFM_1000_CX); 2379 case FW_PORT_CAP32_SPEED_10G: 2380 return (IFM_10G_TWINAX); 2381 case FW_PORT_CAP32_SPEED_25G: 2382 return (IFM_25G_CR); 2383 case FW_PORT_CAP32_SPEED_40G: 2384 return (IFM_40G_CR4); 2385 case FW_PORT_CAP32_SPEED_50G: 2386 return (IFM_50G_CR2); 2387 case FW_PORT_CAP32_SPEED_100G: 2388 return (IFM_100G_CR4); 2389 } 2390 break; 2391 case FW_PORT_MOD_TYPE_LRM: 2392 if (speed == FW_PORT_CAP32_SPEED_10G) 2393 return (IFM_10G_LRM); 2394 break; 2395 case FW_PORT_MOD_TYPE_NA: 2396 MPASS(0); /* Not pluggable? */ 2397 /* fall throough */ 2398 case FW_PORT_MOD_TYPE_ERROR: 2399 case FW_PORT_MOD_TYPE_UNKNOWN: 2400 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2401 break; 2402 case FW_PORT_MOD_TYPE_NONE: 2403 return (IFM_NONE); 2404 } 2405 break; 2406 case FW_PORT_TYPE_NONE: 2407 return (IFM_NONE); 2408 } 2409 2410 return (IFM_UNKNOWN); 2411 } 2412 2413 void 2414 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2415 { 2416 struct vi_info *vi = ifp->if_softc; 2417 struct port_info *pi = vi->pi; 2418 struct adapter *sc = pi->adapter; 2419 struct link_config *lc = &pi->link_cfg; 2420 2421 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2422 return; 2423 PORT_LOCK(pi); 2424 2425 if (pi->up_vis == 0) { 2426 /* 2427 * If all the interfaces are administratively down the firmware 2428 * does not report transceiver changes. Refresh port info here 2429 * so that ifconfig displays accurate ifmedia at all times. 2430 * This is the only reason we have a synchronized op in this 2431 * function. Just PORT_LOCK would have been enough otherwise. 2432 */ 2433 t4_update_port_info(pi); 2434 build_medialist(pi); 2435 } 2436 2437 /* ifm_status */ 2438 ifmr->ifm_status = IFM_AVALID; 2439 if (lc->link_ok == false) 2440 goto done; 2441 ifmr->ifm_status |= IFM_ACTIVE; 2442 2443 /* ifm_active */ 2444 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2445 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2446 if (lc->fc & PAUSE_RX) 2447 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2448 if (lc->fc & PAUSE_TX) 2449 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2450 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 2451 done: 2452 PORT_UNLOCK(pi); 2453 end_synchronized_op(sc, 0); 2454 } 2455 2456 static int 2457 vcxgbe_probe(device_t dev) 2458 { 2459 char buf[128]; 2460 struct vi_info *vi = device_get_softc(dev); 2461 2462 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2463 vi - vi->pi->vi); 2464 device_set_desc_copy(dev, buf); 2465 2466 return (BUS_PROBE_DEFAULT); 2467 } 2468 2469 static int 2470 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2471 { 2472 int func, index, rc; 2473 uint32_t param, val; 2474 2475 ASSERT_SYNCHRONIZED_OP(sc); 2476 2477 index = vi - pi->vi; 2478 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2479 KASSERT(index < nitems(vi_mac_funcs), 2480 ("%s: VI %s doesn't have a MAC func", __func__, 2481 device_get_nameunit(vi->dev))); 2482 func = vi_mac_funcs[index]; 2483 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2484 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 2485 if (rc < 0) { 2486 device_printf(vi->dev, "failed to allocate virtual interface %d" 2487 "for port %d: %d\n", index, pi->port_id, -rc); 2488 return (-rc); 2489 } 2490 vi->viid = rc; 2491 2492 if (vi->rss_size == 1) { 2493 /* 2494 * This VI didn't get a slice of the RSS table. Reduce the 2495 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2496 * configuration file (nvi, rssnvi for this PF) if this is a 2497 * problem. 2498 */ 2499 device_printf(vi->dev, "RSS table not available.\n"); 2500 vi->rss_base = 0xffff; 2501 2502 return (0); 2503 } 2504 2505 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2506 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2507 V_FW_PARAMS_PARAM_YZ(vi->viid); 2508 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2509 if (rc) 2510 vi->rss_base = 0xffff; 2511 else { 2512 MPASS((val >> 16) == vi->rss_size); 2513 vi->rss_base = val & 0xffff; 2514 } 2515 2516 return (0); 2517 } 2518 2519 static int 2520 vcxgbe_attach(device_t dev) 2521 { 2522 struct vi_info *vi; 2523 struct port_info *pi; 2524 struct adapter *sc; 2525 int rc; 2526 2527 vi = device_get_softc(dev); 2528 pi = vi->pi; 2529 sc = pi->adapter; 2530 2531 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2532 if (rc) 2533 return (rc); 2534 rc = alloc_extra_vi(sc, pi, vi); 2535 end_synchronized_op(sc, 0); 2536 if (rc) 2537 return (rc); 2538 2539 rc = cxgbe_vi_attach(dev, vi); 2540 if (rc) { 2541 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2542 return (rc); 2543 } 2544 return (0); 2545 } 2546 2547 static int 2548 vcxgbe_detach(device_t dev) 2549 { 2550 struct vi_info *vi; 2551 struct adapter *sc; 2552 2553 vi = device_get_softc(dev); 2554 sc = vi->pi->adapter; 2555 2556 doom_vi(sc, vi); 2557 2558 cxgbe_vi_detach(vi); 2559 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2560 2561 end_synchronized_op(sc, 0); 2562 2563 return (0); 2564 } 2565 2566 static struct callout fatal_callout; 2567 2568 static void 2569 delayed_panic(void *arg) 2570 { 2571 struct adapter *sc = arg; 2572 2573 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 2574 } 2575 2576 void 2577 t4_fatal_err(struct adapter *sc, bool fw_error) 2578 { 2579 2580 t4_shutdown_adapter(sc); 2581 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n", 2582 device_get_nameunit(sc->dev)); 2583 if (fw_error) { 2584 ASSERT_SYNCHRONIZED_OP(sc); 2585 sc->flags |= ADAP_ERR; 2586 } else { 2587 ADAPTER_LOCK(sc); 2588 sc->flags |= ADAP_ERR; 2589 ADAPTER_UNLOCK(sc); 2590 } 2591 2592 if (t4_panic_on_fatal_err) { 2593 log(LOG_ALERT, "%s: panic on fatal error after 30s", 2594 device_get_nameunit(sc->dev)); 2595 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 2596 } 2597 } 2598 2599 void 2600 t4_add_adapter(struct adapter *sc) 2601 { 2602 sx_xlock(&t4_list_lock); 2603 SLIST_INSERT_HEAD(&t4_list, sc, link); 2604 sx_xunlock(&t4_list_lock); 2605 } 2606 2607 int 2608 t4_map_bars_0_and_4(struct adapter *sc) 2609 { 2610 sc->regs_rid = PCIR_BAR(0); 2611 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2612 &sc->regs_rid, RF_ACTIVE); 2613 if (sc->regs_res == NULL) { 2614 device_printf(sc->dev, "cannot map registers.\n"); 2615 return (ENXIO); 2616 } 2617 sc->bt = rman_get_bustag(sc->regs_res); 2618 sc->bh = rman_get_bushandle(sc->regs_res); 2619 sc->mmio_len = rman_get_size(sc->regs_res); 2620 setbit(&sc->doorbells, DOORBELL_KDB); 2621 2622 sc->msix_rid = PCIR_BAR(4); 2623 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2624 &sc->msix_rid, RF_ACTIVE); 2625 if (sc->msix_res == NULL) { 2626 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2627 return (ENXIO); 2628 } 2629 2630 return (0); 2631 } 2632 2633 int 2634 t4_map_bar_2(struct adapter *sc) 2635 { 2636 2637 /* 2638 * T4: only iWARP driver uses the userspace doorbells. There is no need 2639 * to map it if RDMA is disabled. 2640 */ 2641 if (is_t4(sc) && sc->rdmacaps == 0) 2642 return (0); 2643 2644 sc->udbs_rid = PCIR_BAR(2); 2645 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2646 &sc->udbs_rid, RF_ACTIVE); 2647 if (sc->udbs_res == NULL) { 2648 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2649 return (ENXIO); 2650 } 2651 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2652 2653 if (chip_id(sc) >= CHELSIO_T5) { 2654 setbit(&sc->doorbells, DOORBELL_UDB); 2655 #if defined(__i386__) || defined(__amd64__) 2656 if (t5_write_combine) { 2657 int rc, mode; 2658 2659 /* 2660 * Enable write combining on BAR2. This is the 2661 * userspace doorbell BAR and is split into 128B 2662 * (UDBS_SEG_SIZE) doorbell regions, each associated 2663 * with an egress queue. The first 64B has the doorbell 2664 * and the second 64B can be used to submit a tx work 2665 * request with an implicit doorbell. 2666 */ 2667 2668 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2669 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2670 if (rc == 0) { 2671 clrbit(&sc->doorbells, DOORBELL_UDB); 2672 setbit(&sc->doorbells, DOORBELL_WCWR); 2673 setbit(&sc->doorbells, DOORBELL_UDBWC); 2674 } else { 2675 device_printf(sc->dev, 2676 "couldn't enable write combining: %d\n", 2677 rc); 2678 } 2679 2680 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2681 t4_write_reg(sc, A_SGE_STAT_CFG, 2682 V_STATSOURCE_T5(7) | mode); 2683 } 2684 #endif 2685 } 2686 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2687 2688 return (0); 2689 } 2690 2691 struct memwin_init { 2692 uint32_t base; 2693 uint32_t aperture; 2694 }; 2695 2696 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2697 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2698 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2699 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2700 }; 2701 2702 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2703 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2704 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2705 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2706 }; 2707 2708 static void 2709 setup_memwin(struct adapter *sc) 2710 { 2711 const struct memwin_init *mw_init; 2712 struct memwin *mw; 2713 int i; 2714 uint32_t bar0; 2715 2716 if (is_t4(sc)) { 2717 /* 2718 * Read low 32b of bar0 indirectly via the hardware backdoor 2719 * mechanism. Works from within PCI passthrough environments 2720 * too, where rman_get_start() can return a different value. We 2721 * need to program the T4 memory window decoders with the actual 2722 * addresses that will be coming across the PCIe link. 2723 */ 2724 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2725 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2726 2727 mw_init = &t4_memwin[0]; 2728 } else { 2729 /* T5+ use the relative offset inside the PCIe BAR */ 2730 bar0 = 0; 2731 2732 mw_init = &t5_memwin[0]; 2733 } 2734 2735 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2736 rw_init(&mw->mw_lock, "memory window access"); 2737 mw->mw_base = mw_init->base; 2738 mw->mw_aperture = mw_init->aperture; 2739 mw->mw_curpos = 0; 2740 t4_write_reg(sc, 2741 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2742 (mw->mw_base + bar0) | V_BIR(0) | 2743 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2744 rw_wlock(&mw->mw_lock); 2745 position_memwin(sc, i, 0); 2746 rw_wunlock(&mw->mw_lock); 2747 } 2748 2749 /* flush */ 2750 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2751 } 2752 2753 /* 2754 * Positions the memory window at the given address in the card's address space. 2755 * There are some alignment requirements and the actual position may be at an 2756 * address prior to the requested address. mw->mw_curpos always has the actual 2757 * position of the window. 2758 */ 2759 static void 2760 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2761 { 2762 struct memwin *mw; 2763 uint32_t pf; 2764 uint32_t reg; 2765 2766 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2767 mw = &sc->memwin[idx]; 2768 rw_assert(&mw->mw_lock, RA_WLOCKED); 2769 2770 if (is_t4(sc)) { 2771 pf = 0; 2772 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2773 } else { 2774 pf = V_PFNUM(sc->pf); 2775 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2776 } 2777 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2778 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2779 t4_read_reg(sc, reg); /* flush */ 2780 } 2781 2782 int 2783 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2784 int len, int rw) 2785 { 2786 struct memwin *mw; 2787 uint32_t mw_end, v; 2788 2789 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2790 2791 /* Memory can only be accessed in naturally aligned 4 byte units */ 2792 if (addr & 3 || len & 3 || len <= 0) 2793 return (EINVAL); 2794 2795 mw = &sc->memwin[idx]; 2796 while (len > 0) { 2797 rw_rlock(&mw->mw_lock); 2798 mw_end = mw->mw_curpos + mw->mw_aperture; 2799 if (addr >= mw_end || addr < mw->mw_curpos) { 2800 /* Will need to reposition the window */ 2801 if (!rw_try_upgrade(&mw->mw_lock)) { 2802 rw_runlock(&mw->mw_lock); 2803 rw_wlock(&mw->mw_lock); 2804 } 2805 rw_assert(&mw->mw_lock, RA_WLOCKED); 2806 position_memwin(sc, idx, addr); 2807 rw_downgrade(&mw->mw_lock); 2808 mw_end = mw->mw_curpos + mw->mw_aperture; 2809 } 2810 rw_assert(&mw->mw_lock, RA_RLOCKED); 2811 while (addr < mw_end && len > 0) { 2812 if (rw == 0) { 2813 v = t4_read_reg(sc, mw->mw_base + addr - 2814 mw->mw_curpos); 2815 *val++ = le32toh(v); 2816 } else { 2817 v = *val++; 2818 t4_write_reg(sc, mw->mw_base + addr - 2819 mw->mw_curpos, htole32(v)); 2820 } 2821 addr += 4; 2822 len -= 4; 2823 } 2824 rw_runlock(&mw->mw_lock); 2825 } 2826 2827 return (0); 2828 } 2829 2830 int 2831 alloc_atid_tab(struct tid_info *t, int flags) 2832 { 2833 int i; 2834 2835 MPASS(t->natids > 0); 2836 MPASS(t->atid_tab == NULL); 2837 2838 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2839 M_ZERO | flags); 2840 if (t->atid_tab == NULL) 2841 return (ENOMEM); 2842 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2843 t->afree = t->atid_tab; 2844 t->atids_in_use = 0; 2845 for (i = 1; i < t->natids; i++) 2846 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2847 t->atid_tab[t->natids - 1].next = NULL; 2848 2849 return (0); 2850 } 2851 2852 void 2853 free_atid_tab(struct tid_info *t) 2854 { 2855 2856 KASSERT(t->atids_in_use == 0, 2857 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2858 2859 if (mtx_initialized(&t->atid_lock)) 2860 mtx_destroy(&t->atid_lock); 2861 free(t->atid_tab, M_CXGBE); 2862 t->atid_tab = NULL; 2863 } 2864 2865 int 2866 alloc_atid(struct adapter *sc, void *ctx) 2867 { 2868 struct tid_info *t = &sc->tids; 2869 int atid = -1; 2870 2871 mtx_lock(&t->atid_lock); 2872 if (t->afree) { 2873 union aopen_entry *p = t->afree; 2874 2875 atid = p - t->atid_tab; 2876 MPASS(atid <= M_TID_TID); 2877 t->afree = p->next; 2878 p->data = ctx; 2879 t->atids_in_use++; 2880 } 2881 mtx_unlock(&t->atid_lock); 2882 return (atid); 2883 } 2884 2885 void * 2886 lookup_atid(struct adapter *sc, int atid) 2887 { 2888 struct tid_info *t = &sc->tids; 2889 2890 return (t->atid_tab[atid].data); 2891 } 2892 2893 void 2894 free_atid(struct adapter *sc, int atid) 2895 { 2896 struct tid_info *t = &sc->tids; 2897 union aopen_entry *p = &t->atid_tab[atid]; 2898 2899 mtx_lock(&t->atid_lock); 2900 p->next = t->afree; 2901 t->afree = p; 2902 t->atids_in_use--; 2903 mtx_unlock(&t->atid_lock); 2904 } 2905 2906 static void 2907 queue_tid_release(struct adapter *sc, int tid) 2908 { 2909 2910 CXGBE_UNIMPLEMENTED("deferred tid release"); 2911 } 2912 2913 void 2914 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2915 { 2916 struct wrqe *wr; 2917 struct cpl_tid_release *req; 2918 2919 wr = alloc_wrqe(sizeof(*req), ctrlq); 2920 if (wr == NULL) { 2921 queue_tid_release(sc, tid); /* defer */ 2922 return; 2923 } 2924 req = wrtod(wr); 2925 2926 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2927 2928 t4_wrq_tx(sc, wr); 2929 } 2930 2931 static int 2932 t4_range_cmp(const void *a, const void *b) 2933 { 2934 return ((const struct t4_range *)a)->start - 2935 ((const struct t4_range *)b)->start; 2936 } 2937 2938 /* 2939 * Verify that the memory range specified by the addr/len pair is valid within 2940 * the card's address space. 2941 */ 2942 static int 2943 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 2944 { 2945 struct t4_range mem_ranges[4], *r, *next; 2946 uint32_t em, addr_len; 2947 int i, n, remaining; 2948 2949 /* Memory can only be accessed in naturally aligned 4 byte units */ 2950 if (addr & 3 || len & 3 || len == 0) 2951 return (EINVAL); 2952 2953 /* Enabled memories */ 2954 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2955 2956 r = &mem_ranges[0]; 2957 n = 0; 2958 bzero(r, sizeof(mem_ranges)); 2959 if (em & F_EDRAM0_ENABLE) { 2960 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2961 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2962 if (r->size > 0) { 2963 r->start = G_EDRAM0_BASE(addr_len) << 20; 2964 if (addr >= r->start && 2965 addr + len <= r->start + r->size) 2966 return (0); 2967 r++; 2968 n++; 2969 } 2970 } 2971 if (em & F_EDRAM1_ENABLE) { 2972 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2973 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2974 if (r->size > 0) { 2975 r->start = G_EDRAM1_BASE(addr_len) << 20; 2976 if (addr >= r->start && 2977 addr + len <= r->start + r->size) 2978 return (0); 2979 r++; 2980 n++; 2981 } 2982 } 2983 if (em & F_EXT_MEM_ENABLE) { 2984 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2985 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2986 if (r->size > 0) { 2987 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2988 if (addr >= r->start && 2989 addr + len <= r->start + r->size) 2990 return (0); 2991 r++; 2992 n++; 2993 } 2994 } 2995 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2996 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2997 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2998 if (r->size > 0) { 2999 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 3000 if (addr >= r->start && 3001 addr + len <= r->start + r->size) 3002 return (0); 3003 r++; 3004 n++; 3005 } 3006 } 3007 MPASS(n <= nitems(mem_ranges)); 3008 3009 if (n > 1) { 3010 /* Sort and merge the ranges. */ 3011 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 3012 3013 /* Start from index 0 and examine the next n - 1 entries. */ 3014 r = &mem_ranges[0]; 3015 for (remaining = n - 1; remaining > 0; remaining--, r++) { 3016 3017 MPASS(r->size > 0); /* r is a valid entry. */ 3018 next = r + 1; 3019 MPASS(next->size > 0); /* and so is the next one. */ 3020 3021 while (r->start + r->size >= next->start) { 3022 /* Merge the next one into the current entry. */ 3023 r->size = max(r->start + r->size, 3024 next->start + next->size) - r->start; 3025 n--; /* One fewer entry in total. */ 3026 if (--remaining == 0) 3027 goto done; /* short circuit */ 3028 next++; 3029 } 3030 if (next != r + 1) { 3031 /* 3032 * Some entries were merged into r and next 3033 * points to the first valid entry that couldn't 3034 * be merged. 3035 */ 3036 MPASS(next->size > 0); /* must be valid */ 3037 memcpy(r + 1, next, remaining * sizeof(*r)); 3038 #ifdef INVARIANTS 3039 /* 3040 * This so that the foo->size assertion in the 3041 * next iteration of the loop do the right 3042 * thing for entries that were pulled up and are 3043 * no longer valid. 3044 */ 3045 MPASS(n < nitems(mem_ranges)); 3046 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 3047 sizeof(struct t4_range)); 3048 #endif 3049 } 3050 } 3051 done: 3052 /* Done merging the ranges. */ 3053 MPASS(n > 0); 3054 r = &mem_ranges[0]; 3055 for (i = 0; i < n; i++, r++) { 3056 if (addr >= r->start && 3057 addr + len <= r->start + r->size) 3058 return (0); 3059 } 3060 } 3061 3062 return (EFAULT); 3063 } 3064 3065 static int 3066 fwmtype_to_hwmtype(int mtype) 3067 { 3068 3069 switch (mtype) { 3070 case FW_MEMTYPE_EDC0: 3071 return (MEM_EDC0); 3072 case FW_MEMTYPE_EDC1: 3073 return (MEM_EDC1); 3074 case FW_MEMTYPE_EXTMEM: 3075 return (MEM_MC0); 3076 case FW_MEMTYPE_EXTMEM1: 3077 return (MEM_MC1); 3078 default: 3079 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 3080 } 3081 } 3082 3083 /* 3084 * Verify that the memory range specified by the memtype/offset/len pair is 3085 * valid and lies entirely within the memtype specified. The global address of 3086 * the start of the range is returned in addr. 3087 */ 3088 static int 3089 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 3090 uint32_t *addr) 3091 { 3092 uint32_t em, addr_len, maddr; 3093 3094 /* Memory can only be accessed in naturally aligned 4 byte units */ 3095 if (off & 3 || len & 3 || len == 0) 3096 return (EINVAL); 3097 3098 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3099 switch (fwmtype_to_hwmtype(mtype)) { 3100 case MEM_EDC0: 3101 if (!(em & F_EDRAM0_ENABLE)) 3102 return (EINVAL); 3103 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3104 maddr = G_EDRAM0_BASE(addr_len) << 20; 3105 break; 3106 case MEM_EDC1: 3107 if (!(em & F_EDRAM1_ENABLE)) 3108 return (EINVAL); 3109 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3110 maddr = G_EDRAM1_BASE(addr_len) << 20; 3111 break; 3112 case MEM_MC: 3113 if (!(em & F_EXT_MEM_ENABLE)) 3114 return (EINVAL); 3115 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3116 maddr = G_EXT_MEM_BASE(addr_len) << 20; 3117 break; 3118 case MEM_MC1: 3119 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 3120 return (EINVAL); 3121 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3122 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 3123 break; 3124 default: 3125 return (EINVAL); 3126 } 3127 3128 *addr = maddr + off; /* global address */ 3129 return (validate_mem_range(sc, *addr, len)); 3130 } 3131 3132 static int 3133 fixup_devlog_params(struct adapter *sc) 3134 { 3135 struct devlog_params *dparams = &sc->params.devlog; 3136 int rc; 3137 3138 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 3139 dparams->size, &dparams->addr); 3140 3141 return (rc); 3142 } 3143 3144 static void 3145 update_nirq(struct intrs_and_queues *iaq, int nports) 3146 { 3147 int extra = T4_EXTRA_INTR; 3148 3149 iaq->nirq = extra; 3150 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 3151 iaq->nirq += nports * (iaq->num_vis - 1) * 3152 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 3153 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 3154 } 3155 3156 /* 3157 * Adjust requirements to fit the number of interrupts available. 3158 */ 3159 static void 3160 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 3161 int navail) 3162 { 3163 int old_nirq; 3164 const int nports = sc->params.nports; 3165 3166 MPASS(nports > 0); 3167 MPASS(navail > 0); 3168 3169 bzero(iaq, sizeof(*iaq)); 3170 iaq->intr_type = itype; 3171 iaq->num_vis = t4_num_vis; 3172 iaq->ntxq = t4_ntxq; 3173 iaq->ntxq_vi = t4_ntxq_vi; 3174 iaq->nrxq = t4_nrxq; 3175 iaq->nrxq_vi = t4_nrxq_vi; 3176 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3177 if (is_offload(sc) || is_ethoffload(sc)) { 3178 iaq->nofldtxq = t4_nofldtxq; 3179 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3180 } 3181 #endif 3182 #ifdef TCP_OFFLOAD 3183 if (is_offload(sc)) { 3184 iaq->nofldrxq = t4_nofldrxq; 3185 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3186 } 3187 #endif 3188 #ifdef DEV_NETMAP 3189 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3190 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3191 #endif 3192 3193 update_nirq(iaq, nports); 3194 if (iaq->nirq <= navail && 3195 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3196 /* 3197 * This is the normal case -- there are enough interrupts for 3198 * everything. 3199 */ 3200 goto done; 3201 } 3202 3203 /* 3204 * If extra VIs have been configured try reducing their count and see if 3205 * that works. 3206 */ 3207 while (iaq->num_vis > 1) { 3208 iaq->num_vis--; 3209 update_nirq(iaq, nports); 3210 if (iaq->nirq <= navail && 3211 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3212 device_printf(sc->dev, "virtual interfaces per port " 3213 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3214 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3215 "itype %d, navail %u, nirq %d.\n", 3216 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3217 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3218 itype, navail, iaq->nirq); 3219 goto done; 3220 } 3221 } 3222 3223 /* 3224 * Extra VIs will not be created. Log a message if they were requested. 3225 */ 3226 MPASS(iaq->num_vis == 1); 3227 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3228 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3229 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3230 if (iaq->num_vis != t4_num_vis) { 3231 device_printf(sc->dev, "extra virtual interfaces disabled. " 3232 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3233 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3234 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3235 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3236 } 3237 3238 /* 3239 * Keep reducing the number of NIC rx queues to the next lower power of 3240 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3241 * if that works. 3242 */ 3243 do { 3244 if (iaq->nrxq > 1) { 3245 do { 3246 iaq->nrxq--; 3247 } while (!powerof2(iaq->nrxq)); 3248 } 3249 if (iaq->nofldrxq > 1) 3250 iaq->nofldrxq >>= 1; 3251 3252 old_nirq = iaq->nirq; 3253 update_nirq(iaq, nports); 3254 if (iaq->nirq <= navail && 3255 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3256 device_printf(sc->dev, "running with reduced number of " 3257 "rx queues because of shortage of interrupts. " 3258 "nrxq=%u, nofldrxq=%u. " 3259 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3260 iaq->nofldrxq, itype, navail, iaq->nirq); 3261 goto done; 3262 } 3263 } while (old_nirq != iaq->nirq); 3264 3265 /* One interrupt for everything. Ugh. */ 3266 device_printf(sc->dev, "running with minimal number of queues. " 3267 "itype %d, navail %u.\n", itype, navail); 3268 iaq->nirq = 1; 3269 MPASS(iaq->nrxq == 1); 3270 iaq->ntxq = 1; 3271 if (iaq->nofldrxq > 1) 3272 iaq->nofldtxq = 1; 3273 done: 3274 MPASS(iaq->num_vis > 0); 3275 if (iaq->num_vis > 1) { 3276 MPASS(iaq->nrxq_vi > 0); 3277 MPASS(iaq->ntxq_vi > 0); 3278 } 3279 MPASS(iaq->nirq > 0); 3280 MPASS(iaq->nrxq > 0); 3281 MPASS(iaq->ntxq > 0); 3282 if (itype == INTR_MSI) { 3283 MPASS(powerof2(iaq->nirq)); 3284 } 3285 } 3286 3287 static int 3288 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3289 { 3290 int rc, itype, navail, nalloc; 3291 3292 for (itype = INTR_MSIX; itype; itype >>= 1) { 3293 3294 if ((itype & t4_intr_types) == 0) 3295 continue; /* not allowed */ 3296 3297 if (itype == INTR_MSIX) 3298 navail = pci_msix_count(sc->dev); 3299 else if (itype == INTR_MSI) 3300 navail = pci_msi_count(sc->dev); 3301 else 3302 navail = 1; 3303 restart: 3304 if (navail == 0) 3305 continue; 3306 3307 calculate_iaq(sc, iaq, itype, navail); 3308 nalloc = iaq->nirq; 3309 rc = 0; 3310 if (itype == INTR_MSIX) 3311 rc = pci_alloc_msix(sc->dev, &nalloc); 3312 else if (itype == INTR_MSI) 3313 rc = pci_alloc_msi(sc->dev, &nalloc); 3314 3315 if (rc == 0 && nalloc > 0) { 3316 if (nalloc == iaq->nirq) 3317 return (0); 3318 3319 /* 3320 * Didn't get the number requested. Use whatever number 3321 * the kernel is willing to allocate. 3322 */ 3323 device_printf(sc->dev, "fewer vectors than requested, " 3324 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3325 itype, iaq->nirq, nalloc); 3326 pci_release_msi(sc->dev); 3327 navail = nalloc; 3328 goto restart; 3329 } 3330 3331 device_printf(sc->dev, 3332 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3333 itype, rc, iaq->nirq, nalloc); 3334 } 3335 3336 device_printf(sc->dev, 3337 "failed to find a usable interrupt type. " 3338 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3339 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3340 3341 return (ENXIO); 3342 } 3343 3344 #define FW_VERSION(chip) ( \ 3345 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3346 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3347 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3348 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3349 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3350 3351 /* Just enough of fw_hdr to cover all version info. */ 3352 struct fw_h { 3353 __u8 ver; 3354 __u8 chip; 3355 __be16 len512; 3356 __be32 fw_ver; 3357 __be32 tp_microcode_ver; 3358 __u8 intfver_nic; 3359 __u8 intfver_vnic; 3360 __u8 intfver_ofld; 3361 __u8 intfver_ri; 3362 __u8 intfver_iscsipdu; 3363 __u8 intfver_iscsi; 3364 __u8 intfver_fcoepdu; 3365 __u8 intfver_fcoe; 3366 }; 3367 /* Spot check a couple of fields. */ 3368 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 3369 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 3370 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 3371 3372 struct fw_info { 3373 uint8_t chip; 3374 char *kld_name; 3375 char *fw_mod_name; 3376 struct fw_h fw_h; 3377 } fw_info[] = { 3378 { 3379 .chip = CHELSIO_T4, 3380 .kld_name = "t4fw_cfg", 3381 .fw_mod_name = "t4fw", 3382 .fw_h = { 3383 .chip = FW_HDR_CHIP_T4, 3384 .fw_ver = htobe32(FW_VERSION(T4)), 3385 .intfver_nic = FW_INTFVER(T4, NIC), 3386 .intfver_vnic = FW_INTFVER(T4, VNIC), 3387 .intfver_ofld = FW_INTFVER(T4, OFLD), 3388 .intfver_ri = FW_INTFVER(T4, RI), 3389 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3390 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3391 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3392 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3393 }, 3394 }, { 3395 .chip = CHELSIO_T5, 3396 .kld_name = "t5fw_cfg", 3397 .fw_mod_name = "t5fw", 3398 .fw_h = { 3399 .chip = FW_HDR_CHIP_T5, 3400 .fw_ver = htobe32(FW_VERSION(T5)), 3401 .intfver_nic = FW_INTFVER(T5, NIC), 3402 .intfver_vnic = FW_INTFVER(T5, VNIC), 3403 .intfver_ofld = FW_INTFVER(T5, OFLD), 3404 .intfver_ri = FW_INTFVER(T5, RI), 3405 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3406 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3407 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3408 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3409 }, 3410 }, { 3411 .chip = CHELSIO_T6, 3412 .kld_name = "t6fw_cfg", 3413 .fw_mod_name = "t6fw", 3414 .fw_h = { 3415 .chip = FW_HDR_CHIP_T6, 3416 .fw_ver = htobe32(FW_VERSION(T6)), 3417 .intfver_nic = FW_INTFVER(T6, NIC), 3418 .intfver_vnic = FW_INTFVER(T6, VNIC), 3419 .intfver_ofld = FW_INTFVER(T6, OFLD), 3420 .intfver_ri = FW_INTFVER(T6, RI), 3421 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3422 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3423 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3424 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3425 }, 3426 } 3427 }; 3428 3429 static struct fw_info * 3430 find_fw_info(int chip) 3431 { 3432 int i; 3433 3434 for (i = 0; i < nitems(fw_info); i++) { 3435 if (fw_info[i].chip == chip) 3436 return (&fw_info[i]); 3437 } 3438 return (NULL); 3439 } 3440 3441 /* 3442 * Is the given firmware API compatible with the one the driver was compiled 3443 * with? 3444 */ 3445 static int 3446 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 3447 { 3448 3449 /* short circuit if it's the exact same firmware version */ 3450 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3451 return (1); 3452 3453 /* 3454 * XXX: Is this too conservative? Perhaps I should limit this to the 3455 * features that are supported in the driver. 3456 */ 3457 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3458 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3459 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3460 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3461 return (1); 3462 #undef SAME_INTF 3463 3464 return (0); 3465 } 3466 3467 static int 3468 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 3469 const struct firmware **fw) 3470 { 3471 struct fw_info *fw_info; 3472 3473 *dcfg = NULL; 3474 if (fw != NULL) 3475 *fw = NULL; 3476 3477 fw_info = find_fw_info(chip_id(sc)); 3478 if (fw_info == NULL) { 3479 device_printf(sc->dev, 3480 "unable to look up firmware information for chip %d.\n", 3481 chip_id(sc)); 3482 return (EINVAL); 3483 } 3484 3485 *dcfg = firmware_get(fw_info->kld_name); 3486 if (*dcfg != NULL) { 3487 if (fw != NULL) 3488 *fw = firmware_get(fw_info->fw_mod_name); 3489 return (0); 3490 } 3491 3492 return (ENOENT); 3493 } 3494 3495 static void 3496 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 3497 const struct firmware *fw) 3498 { 3499 3500 if (fw != NULL) 3501 firmware_put(fw, FIRMWARE_UNLOAD); 3502 if (dcfg != NULL) 3503 firmware_put(dcfg, FIRMWARE_UNLOAD); 3504 } 3505 3506 /* 3507 * Return values: 3508 * 0 means no firmware install attempted. 3509 * ERESTART means a firmware install was attempted and was successful. 3510 * +ve errno means a firmware install was attempted but failed. 3511 */ 3512 static int 3513 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 3514 const struct fw_h *drv_fw, const char *reason, int *already) 3515 { 3516 const struct firmware *cfg, *fw; 3517 const uint32_t c = be32toh(card_fw->fw_ver); 3518 uint32_t d, k; 3519 int rc, fw_install; 3520 struct fw_h bundled_fw; 3521 bool load_attempted; 3522 3523 cfg = fw = NULL; 3524 load_attempted = false; 3525 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 3526 3527 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 3528 if (t4_fw_install < 0) { 3529 rc = load_fw_module(sc, &cfg, &fw); 3530 if (rc != 0 || fw == NULL) { 3531 device_printf(sc->dev, 3532 "failed to load firmware module: %d. cfg %p, fw %p;" 3533 " will use compiled-in firmware version for" 3534 "hw.cxgbe.fw_install checks.\n", 3535 rc, cfg, fw); 3536 } else { 3537 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 3538 } 3539 load_attempted = true; 3540 } 3541 d = be32toh(bundled_fw.fw_ver); 3542 3543 if (reason != NULL) 3544 goto install; 3545 3546 if ((sc->flags & FW_OK) == 0) { 3547 3548 if (c == 0xffffffff) { 3549 reason = "missing"; 3550 goto install; 3551 } 3552 3553 rc = 0; 3554 goto done; 3555 } 3556 3557 if (!fw_compatible(card_fw, &bundled_fw)) { 3558 reason = "incompatible or unusable"; 3559 goto install; 3560 } 3561 3562 if (d > c) { 3563 reason = "older than the version bundled with this driver"; 3564 goto install; 3565 } 3566 3567 if (fw_install == 2 && d != c) { 3568 reason = "different than the version bundled with this driver"; 3569 goto install; 3570 } 3571 3572 /* No reason to do anything to the firmware already on the card. */ 3573 rc = 0; 3574 goto done; 3575 3576 install: 3577 rc = 0; 3578 if ((*already)++) 3579 goto done; 3580 3581 if (fw_install == 0) { 3582 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3583 "but the driver is prohibited from installing a firmware " 3584 "on the card.\n", 3585 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3586 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3587 3588 goto done; 3589 } 3590 3591 /* 3592 * We'll attempt to install a firmware. Load the module first (if it 3593 * hasn't been loaded already). 3594 */ 3595 if (!load_attempted) { 3596 rc = load_fw_module(sc, &cfg, &fw); 3597 if (rc != 0 || fw == NULL) { 3598 device_printf(sc->dev, 3599 "failed to load firmware module: %d. cfg %p, fw %p\n", 3600 rc, cfg, fw); 3601 /* carry on */ 3602 } 3603 } 3604 if (fw == NULL) { 3605 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3606 "but the driver cannot take corrective action because it " 3607 "is unable to load the firmware module.\n", 3608 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3609 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3610 rc = sc->flags & FW_OK ? 0 : ENOENT; 3611 goto done; 3612 } 3613 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 3614 if (k != d) { 3615 MPASS(t4_fw_install > 0); 3616 device_printf(sc->dev, 3617 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 3618 "expecting (%u.%u.%u.%u) and will not be used.\n", 3619 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3620 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 3621 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3622 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3623 rc = sc->flags & FW_OK ? 0 : EINVAL; 3624 goto done; 3625 } 3626 3627 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3628 "installing firmware %u.%u.%u.%u on card.\n", 3629 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3630 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3631 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3632 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3633 3634 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3635 if (rc != 0) { 3636 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 3637 } else { 3638 /* Installed successfully, update the cached header too. */ 3639 rc = ERESTART; 3640 memcpy(card_fw, fw->data, sizeof(*card_fw)); 3641 } 3642 done: 3643 unload_fw_module(sc, cfg, fw); 3644 3645 return (rc); 3646 } 3647 3648 /* 3649 * Establish contact with the firmware and attempt to become the master driver. 3650 * 3651 * A firmware will be installed to the card if needed (if the driver is allowed 3652 * to do so). 3653 */ 3654 static int 3655 contact_firmware(struct adapter *sc) 3656 { 3657 int rc, already = 0; 3658 enum dev_state state; 3659 struct fw_info *fw_info; 3660 struct fw_hdr *card_fw; /* fw on the card */ 3661 const struct fw_h *drv_fw; 3662 3663 fw_info = find_fw_info(chip_id(sc)); 3664 if (fw_info == NULL) { 3665 device_printf(sc->dev, 3666 "unable to look up firmware information for chip %d.\n", 3667 chip_id(sc)); 3668 return (EINVAL); 3669 } 3670 drv_fw = &fw_info->fw_h; 3671 3672 /* Read the header of the firmware on the card */ 3673 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3674 restart: 3675 rc = -t4_get_fw_hdr(sc, card_fw); 3676 if (rc != 0) { 3677 device_printf(sc->dev, 3678 "unable to read firmware header from card's flash: %d\n", 3679 rc); 3680 goto done; 3681 } 3682 3683 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 3684 &already); 3685 if (rc == ERESTART) 3686 goto restart; 3687 if (rc != 0) 3688 goto done; 3689 3690 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3691 if (rc < 0 || state == DEV_STATE_ERR) { 3692 rc = -rc; 3693 device_printf(sc->dev, 3694 "failed to connect to the firmware: %d, %d. " 3695 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3696 #if 0 3697 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3698 "not responding properly to HELLO", &already) == ERESTART) 3699 goto restart; 3700 #endif 3701 goto done; 3702 } 3703 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 3704 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 3705 3706 if (rc == sc->pf) { 3707 sc->flags |= MASTER_PF; 3708 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3709 NULL, &already); 3710 if (rc == ERESTART) 3711 rc = 0; 3712 else if (rc != 0) 3713 goto done; 3714 } else if (state == DEV_STATE_UNINIT) { 3715 /* 3716 * We didn't get to be the master so we definitely won't be 3717 * configuring the chip. It's a bug if someone else hasn't 3718 * configured it already. 3719 */ 3720 device_printf(sc->dev, "couldn't be master(%d), " 3721 "device not already initialized either(%d). " 3722 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3723 rc = EPROTO; 3724 goto done; 3725 } else { 3726 /* 3727 * Some other PF is the master and has configured the chip. 3728 * This is allowed but untested. 3729 */ 3730 device_printf(sc->dev, "PF%d is master, device state %d. " 3731 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3732 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 3733 sc->cfcsum = 0; 3734 rc = 0; 3735 } 3736 done: 3737 if (rc != 0 && sc->flags & FW_OK) { 3738 t4_fw_bye(sc, sc->mbox); 3739 sc->flags &= ~FW_OK; 3740 } 3741 free(card_fw, M_CXGBE); 3742 return (rc); 3743 } 3744 3745 static int 3746 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 3747 uint32_t mtype, uint32_t moff) 3748 { 3749 struct fw_info *fw_info; 3750 const struct firmware *dcfg, *rcfg = NULL; 3751 const uint32_t *cfdata; 3752 uint32_t cflen, addr; 3753 int rc; 3754 3755 load_fw_module(sc, &dcfg, NULL); 3756 3757 /* Card specific interpretation of "default". */ 3758 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3759 if (pci_get_device(sc->dev) == 0x440a) 3760 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 3761 if (is_fpga(sc)) 3762 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 3763 } 3764 3765 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3766 if (dcfg == NULL) { 3767 device_printf(sc->dev, 3768 "KLD with default config is not available.\n"); 3769 rc = ENOENT; 3770 goto done; 3771 } 3772 cfdata = dcfg->data; 3773 cflen = dcfg->datasize & ~3; 3774 } else { 3775 char s[32]; 3776 3777 fw_info = find_fw_info(chip_id(sc)); 3778 if (fw_info == NULL) { 3779 device_printf(sc->dev, 3780 "unable to look up firmware information for chip %d.\n", 3781 chip_id(sc)); 3782 rc = EINVAL; 3783 goto done; 3784 } 3785 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 3786 3787 rcfg = firmware_get(s); 3788 if (rcfg == NULL) { 3789 device_printf(sc->dev, 3790 "unable to load module \"%s\" for configuration " 3791 "profile \"%s\".\n", s, cfg_file); 3792 rc = ENOENT; 3793 goto done; 3794 } 3795 cfdata = rcfg->data; 3796 cflen = rcfg->datasize & ~3; 3797 } 3798 3799 if (cflen > FLASH_CFG_MAX_SIZE) { 3800 device_printf(sc->dev, 3801 "config file too long (%d, max allowed is %d).\n", 3802 cflen, FLASH_CFG_MAX_SIZE); 3803 rc = EINVAL; 3804 goto done; 3805 } 3806 3807 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3808 if (rc != 0) { 3809 device_printf(sc->dev, 3810 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 3811 __func__, mtype, moff, cflen, rc); 3812 rc = EINVAL; 3813 goto done; 3814 } 3815 write_via_memwin(sc, 2, addr, cfdata, cflen); 3816 done: 3817 if (rcfg != NULL) 3818 firmware_put(rcfg, FIRMWARE_UNLOAD); 3819 unload_fw_module(sc, dcfg, NULL); 3820 return (rc); 3821 } 3822 3823 struct caps_allowed { 3824 uint16_t nbmcaps; 3825 uint16_t linkcaps; 3826 uint16_t switchcaps; 3827 uint16_t niccaps; 3828 uint16_t toecaps; 3829 uint16_t rdmacaps; 3830 uint16_t cryptocaps; 3831 uint16_t iscsicaps; 3832 uint16_t fcoecaps; 3833 }; 3834 3835 #define FW_PARAM_DEV(param) \ 3836 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3837 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3838 #define FW_PARAM_PFVF(param) \ 3839 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3840 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3841 3842 /* 3843 * Provide a configuration profile to the firmware and have it initialize the 3844 * chip accordingly. This may involve uploading a configuration file to the 3845 * card. 3846 */ 3847 static int 3848 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 3849 const struct caps_allowed *caps_allowed) 3850 { 3851 int rc; 3852 struct fw_caps_config_cmd caps; 3853 uint32_t mtype, moff, finicsum, cfcsum, param, val; 3854 3855 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3856 if (rc != 0) { 3857 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3858 return (rc); 3859 } 3860 3861 bzero(&caps, sizeof(caps)); 3862 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3863 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3864 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 3865 mtype = 0; 3866 moff = 0; 3867 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3868 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 3869 mtype = FW_MEMTYPE_FLASH; 3870 moff = t4_flash_cfg_addr(sc); 3871 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3872 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3873 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3874 FW_LEN16(caps)); 3875 } else { 3876 /* 3877 * Ask the firmware where it wants us to upload the config file. 3878 */ 3879 param = FW_PARAM_DEV(CF); 3880 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3881 if (rc != 0) { 3882 /* No support for config file? Shouldn't happen. */ 3883 device_printf(sc->dev, 3884 "failed to query config file location: %d.\n", rc); 3885 goto done; 3886 } 3887 mtype = G_FW_PARAMS_PARAM_Y(val); 3888 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3889 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3890 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3891 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3892 FW_LEN16(caps)); 3893 3894 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 3895 if (rc != 0) { 3896 device_printf(sc->dev, 3897 "failed to upload config file to card: %d.\n", rc); 3898 goto done; 3899 } 3900 } 3901 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3902 if (rc != 0) { 3903 device_printf(sc->dev, "failed to pre-process config file: %d " 3904 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3905 goto done; 3906 } 3907 3908 finicsum = be32toh(caps.finicsum); 3909 cfcsum = be32toh(caps.cfcsum); /* actual */ 3910 if (finicsum != cfcsum) { 3911 device_printf(sc->dev, 3912 "WARNING: config file checksum mismatch: %08x %08x\n", 3913 finicsum, cfcsum); 3914 } 3915 sc->cfcsum = cfcsum; 3916 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 3917 3918 /* 3919 * Let the firmware know what features will (not) be used so it can tune 3920 * things accordingly. 3921 */ 3922 #define LIMIT_CAPS(x) do { \ 3923 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 3924 } while (0) 3925 LIMIT_CAPS(nbm); 3926 LIMIT_CAPS(link); 3927 LIMIT_CAPS(switch); 3928 LIMIT_CAPS(nic); 3929 LIMIT_CAPS(toe); 3930 LIMIT_CAPS(rdma); 3931 LIMIT_CAPS(crypto); 3932 LIMIT_CAPS(iscsi); 3933 LIMIT_CAPS(fcoe); 3934 #undef LIMIT_CAPS 3935 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3936 /* 3937 * TOE and hashfilters are mutually exclusive. It is a config 3938 * file or firmware bug if both are reported as available. Try 3939 * to cope with the situation in non-debug builds by disabling 3940 * TOE. 3941 */ 3942 MPASS(caps.toecaps == 0); 3943 3944 caps.toecaps = 0; 3945 caps.rdmacaps = 0; 3946 caps.iscsicaps = 0; 3947 } 3948 3949 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3950 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3951 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3952 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3953 if (rc != 0) { 3954 device_printf(sc->dev, 3955 "failed to process config file: %d.\n", rc); 3956 goto done; 3957 } 3958 3959 t4_tweak_chip_settings(sc); 3960 set_params__pre_init(sc); 3961 3962 /* get basic stuff going */ 3963 rc = -t4_fw_initialize(sc, sc->mbox); 3964 if (rc != 0) { 3965 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 3966 goto done; 3967 } 3968 done: 3969 return (rc); 3970 } 3971 3972 /* 3973 * Partition chip resources for use between various PFs, VFs, etc. 3974 */ 3975 static int 3976 partition_resources(struct adapter *sc) 3977 { 3978 char cfg_file[sizeof(t4_cfg_file)]; 3979 struct caps_allowed caps_allowed; 3980 int rc; 3981 bool fallback; 3982 3983 /* Only the master driver gets to configure the chip resources. */ 3984 MPASS(sc->flags & MASTER_PF); 3985 3986 #define COPY_CAPS(x) do { \ 3987 caps_allowed.x##caps = t4_##x##caps_allowed; \ 3988 } while (0) 3989 bzero(&caps_allowed, sizeof(caps_allowed)); 3990 COPY_CAPS(nbm); 3991 COPY_CAPS(link); 3992 COPY_CAPS(switch); 3993 COPY_CAPS(nic); 3994 COPY_CAPS(toe); 3995 COPY_CAPS(rdma); 3996 COPY_CAPS(crypto); 3997 COPY_CAPS(iscsi); 3998 COPY_CAPS(fcoe); 3999 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 4000 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 4001 retry: 4002 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 4003 if (rc != 0 && fallback) { 4004 device_printf(sc->dev, 4005 "failed (%d) to configure card with \"%s\" profile, " 4006 "will fall back to a basic configuration and retry.\n", 4007 rc, cfg_file); 4008 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 4009 bzero(&caps_allowed, sizeof(caps_allowed)); 4010 COPY_CAPS(nbm); 4011 COPY_CAPS(link); 4012 COPY_CAPS(switch); 4013 COPY_CAPS(nic); 4014 fallback = false; 4015 goto retry; 4016 } 4017 #undef COPY_CAPS 4018 return (rc); 4019 } 4020 4021 /* 4022 * Retrieve parameters that are needed (or nice to have) very early. 4023 */ 4024 static int 4025 get_params__pre_init(struct adapter *sc) 4026 { 4027 int rc; 4028 uint32_t param[2], val[2]; 4029 4030 t4_get_version_info(sc); 4031 4032 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 4033 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 4034 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 4035 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 4036 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 4037 4038 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 4039 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 4040 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 4041 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 4042 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 4043 4044 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 4045 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 4046 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 4047 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 4048 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 4049 4050 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 4051 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 4052 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 4053 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 4054 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 4055 4056 param[0] = FW_PARAM_DEV(PORTVEC); 4057 param[1] = FW_PARAM_DEV(CCLK); 4058 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4059 if (rc != 0) { 4060 device_printf(sc->dev, 4061 "failed to query parameters (pre_init): %d.\n", rc); 4062 return (rc); 4063 } 4064 4065 sc->params.portvec = val[0]; 4066 sc->params.nports = bitcount32(val[0]); 4067 sc->params.vpd.cclk = val[1]; 4068 4069 /* Read device log parameters. */ 4070 rc = -t4_init_devlog_params(sc, 1); 4071 if (rc == 0) 4072 fixup_devlog_params(sc); 4073 else { 4074 device_printf(sc->dev, 4075 "failed to get devlog parameters: %d.\n", rc); 4076 rc = 0; /* devlog isn't critical for device operation */ 4077 } 4078 4079 return (rc); 4080 } 4081 4082 /* 4083 * Any params that need to be set before FW_INITIALIZE. 4084 */ 4085 static int 4086 set_params__pre_init(struct adapter *sc) 4087 { 4088 int rc = 0; 4089 uint32_t param, val; 4090 4091 if (chip_id(sc) >= CHELSIO_T6) { 4092 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 4093 val = 1; 4094 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4095 /* firmwares < 1.20.1.0 do not have this param. */ 4096 if (rc == FW_EINVAL && sc->params.fw_vers < 4097 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4098 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) { 4099 rc = 0; 4100 } 4101 if (rc != 0) { 4102 device_printf(sc->dev, 4103 "failed to enable high priority filters :%d.\n", 4104 rc); 4105 } 4106 } 4107 4108 /* Enable opaque VIIDs with firmwares that support it. */ 4109 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 4110 val = 1; 4111 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4112 if (rc == 0 && val == 1) 4113 sc->params.viid_smt_extn_support = true; 4114 else 4115 sc->params.viid_smt_extn_support = false; 4116 4117 return (rc); 4118 } 4119 4120 /* 4121 * Retrieve various parameters that are of interest to the driver. The device 4122 * has been initialized by the firmware at this point. 4123 */ 4124 static int 4125 get_params__post_init(struct adapter *sc) 4126 { 4127 int rc; 4128 uint32_t param[7], val[7]; 4129 struct fw_caps_config_cmd caps; 4130 4131 param[0] = FW_PARAM_PFVF(IQFLINT_START); 4132 param[1] = FW_PARAM_PFVF(EQ_START); 4133 param[2] = FW_PARAM_PFVF(FILTER_START); 4134 param[3] = FW_PARAM_PFVF(FILTER_END); 4135 param[4] = FW_PARAM_PFVF(L2T_START); 4136 param[5] = FW_PARAM_PFVF(L2T_END); 4137 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 4138 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 4139 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 4140 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 4141 if (rc != 0) { 4142 device_printf(sc->dev, 4143 "failed to query parameters (post_init): %d.\n", rc); 4144 return (rc); 4145 } 4146 4147 sc->sge.iq_start = val[0]; 4148 sc->sge.eq_start = val[1]; 4149 if ((int)val[3] > (int)val[2]) { 4150 sc->tids.ftid_base = val[2]; 4151 sc->tids.ftid_end = val[3]; 4152 sc->tids.nftids = val[3] - val[2] + 1; 4153 } 4154 sc->vres.l2t.start = val[4]; 4155 sc->vres.l2t.size = val[5] - val[4] + 1; 4156 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 4157 ("%s: L2 table size (%u) larger than expected (%u)", 4158 __func__, sc->vres.l2t.size, L2T_SIZE)); 4159 sc->params.core_vdd = val[6]; 4160 4161 if (chip_id(sc) >= CHELSIO_T6) { 4162 4163 sc->tids.tid_base = t4_read_reg(sc, 4164 A_LE_DB_ACTIVE_TABLE_START_INDEX); 4165 4166 param[0] = FW_PARAM_PFVF(HPFILTER_START); 4167 param[1] = FW_PARAM_PFVF(HPFILTER_END); 4168 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4169 if (rc != 0) { 4170 device_printf(sc->dev, 4171 "failed to query hpfilter parameters: %d.\n", rc); 4172 return (rc); 4173 } 4174 if ((int)val[1] > (int)val[0]) { 4175 sc->tids.hpftid_base = val[0]; 4176 sc->tids.hpftid_end = val[1]; 4177 sc->tids.nhpftids = val[1] - val[0] + 1; 4178 4179 /* 4180 * These should go off if the layout changes and the 4181 * driver needs to catch up. 4182 */ 4183 MPASS(sc->tids.hpftid_base == 0); 4184 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 4185 } 4186 } 4187 4188 /* 4189 * MPSBGMAP is queried separately because only recent firmwares support 4190 * it as a parameter and we don't want the compound query above to fail 4191 * on older firmwares. 4192 */ 4193 param[0] = FW_PARAM_DEV(MPSBGMAP); 4194 val[0] = 0; 4195 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4196 if (rc == 0) 4197 sc->params.mps_bg_map = val[0]; 4198 else 4199 sc->params.mps_bg_map = 0; 4200 4201 /* 4202 * Determine whether the firmware supports the filter2 work request. 4203 * This is queried separately for the same reason as MPSBGMAP above. 4204 */ 4205 param[0] = FW_PARAM_DEV(FILTER2_WR); 4206 val[0] = 0; 4207 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4208 if (rc == 0) 4209 sc->params.filter2_wr_support = val[0] != 0; 4210 else 4211 sc->params.filter2_wr_support = 0; 4212 4213 /* 4214 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 4215 * This is queried separately for the same reason as other params above. 4216 */ 4217 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4218 val[0] = 0; 4219 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4220 if (rc == 0) 4221 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 4222 else 4223 sc->params.ulptx_memwrite_dsgl = false; 4224 4225 /* get capabilites */ 4226 bzero(&caps, sizeof(caps)); 4227 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4228 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4229 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4230 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4231 if (rc != 0) { 4232 device_printf(sc->dev, 4233 "failed to get card capabilities: %d.\n", rc); 4234 return (rc); 4235 } 4236 4237 #define READ_CAPS(x) do { \ 4238 sc->x = htobe16(caps.x); \ 4239 } while (0) 4240 READ_CAPS(nbmcaps); 4241 READ_CAPS(linkcaps); 4242 READ_CAPS(switchcaps); 4243 READ_CAPS(niccaps); 4244 READ_CAPS(toecaps); 4245 READ_CAPS(rdmacaps); 4246 READ_CAPS(cryptocaps); 4247 READ_CAPS(iscsicaps); 4248 READ_CAPS(fcoecaps); 4249 4250 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 4251 MPASS(chip_id(sc) > CHELSIO_T4); 4252 MPASS(sc->toecaps == 0); 4253 sc->toecaps = 0; 4254 4255 param[0] = FW_PARAM_DEV(NTID); 4256 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4257 if (rc != 0) { 4258 device_printf(sc->dev, 4259 "failed to query HASHFILTER parameters: %d.\n", rc); 4260 return (rc); 4261 } 4262 sc->tids.ntids = val[0]; 4263 if (sc->params.fw_vers < 4264 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4265 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4266 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4267 sc->tids.ntids -= sc->tids.nhpftids; 4268 } 4269 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4270 sc->params.hash_filter = 1; 4271 } 4272 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 4273 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 4274 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 4275 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4276 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 4277 if (rc != 0) { 4278 device_printf(sc->dev, 4279 "failed to query NIC parameters: %d.\n", rc); 4280 return (rc); 4281 } 4282 if ((int)val[1] > (int)val[0]) { 4283 sc->tids.etid_base = val[0]; 4284 sc->tids.etid_end = val[1]; 4285 sc->tids.netids = val[1] - val[0] + 1; 4286 sc->params.eo_wr_cred = val[2]; 4287 sc->params.ethoffload = 1; 4288 } 4289 } 4290 if (sc->toecaps) { 4291 /* query offload-related parameters */ 4292 param[0] = FW_PARAM_DEV(NTID); 4293 param[1] = FW_PARAM_PFVF(SERVER_START); 4294 param[2] = FW_PARAM_PFVF(SERVER_END); 4295 param[3] = FW_PARAM_PFVF(TDDP_START); 4296 param[4] = FW_PARAM_PFVF(TDDP_END); 4297 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4298 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4299 if (rc != 0) { 4300 device_printf(sc->dev, 4301 "failed to query TOE parameters: %d.\n", rc); 4302 return (rc); 4303 } 4304 sc->tids.ntids = val[0]; 4305 if (sc->params.fw_vers < 4306 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4307 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4308 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4309 sc->tids.ntids -= sc->tids.nhpftids; 4310 } 4311 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4312 if ((int)val[2] > (int)val[1]) { 4313 sc->tids.stid_base = val[1]; 4314 sc->tids.nstids = val[2] - val[1] + 1; 4315 } 4316 sc->vres.ddp.start = val[3]; 4317 sc->vres.ddp.size = val[4] - val[3] + 1; 4318 sc->params.ofldq_wr_cred = val[5]; 4319 sc->params.offload = 1; 4320 } else { 4321 /* 4322 * The firmware attempts memfree TOE configuration for -SO cards 4323 * and will report toecaps=0 if it runs out of resources (this 4324 * depends on the config file). It may not report 0 for other 4325 * capabilities dependent on the TOE in this case. Set them to 4326 * 0 here so that the driver doesn't bother tracking resources 4327 * that will never be used. 4328 */ 4329 sc->iscsicaps = 0; 4330 sc->rdmacaps = 0; 4331 } 4332 if (sc->rdmacaps) { 4333 param[0] = FW_PARAM_PFVF(STAG_START); 4334 param[1] = FW_PARAM_PFVF(STAG_END); 4335 param[2] = FW_PARAM_PFVF(RQ_START); 4336 param[3] = FW_PARAM_PFVF(RQ_END); 4337 param[4] = FW_PARAM_PFVF(PBL_START); 4338 param[5] = FW_PARAM_PFVF(PBL_END); 4339 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4340 if (rc != 0) { 4341 device_printf(sc->dev, 4342 "failed to query RDMA parameters(1): %d.\n", rc); 4343 return (rc); 4344 } 4345 sc->vres.stag.start = val[0]; 4346 sc->vres.stag.size = val[1] - val[0] + 1; 4347 sc->vres.rq.start = val[2]; 4348 sc->vres.rq.size = val[3] - val[2] + 1; 4349 sc->vres.pbl.start = val[4]; 4350 sc->vres.pbl.size = val[5] - val[4] + 1; 4351 4352 param[0] = FW_PARAM_PFVF(SQRQ_START); 4353 param[1] = FW_PARAM_PFVF(SQRQ_END); 4354 param[2] = FW_PARAM_PFVF(CQ_START); 4355 param[3] = FW_PARAM_PFVF(CQ_END); 4356 param[4] = FW_PARAM_PFVF(OCQ_START); 4357 param[5] = FW_PARAM_PFVF(OCQ_END); 4358 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4359 if (rc != 0) { 4360 device_printf(sc->dev, 4361 "failed to query RDMA parameters(2): %d.\n", rc); 4362 return (rc); 4363 } 4364 sc->vres.qp.start = val[0]; 4365 sc->vres.qp.size = val[1] - val[0] + 1; 4366 sc->vres.cq.start = val[2]; 4367 sc->vres.cq.size = val[3] - val[2] + 1; 4368 sc->vres.ocq.start = val[4]; 4369 sc->vres.ocq.size = val[5] - val[4] + 1; 4370 4371 param[0] = FW_PARAM_PFVF(SRQ_START); 4372 param[1] = FW_PARAM_PFVF(SRQ_END); 4373 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4374 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4375 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4376 if (rc != 0) { 4377 device_printf(sc->dev, 4378 "failed to query RDMA parameters(3): %d.\n", rc); 4379 return (rc); 4380 } 4381 sc->vres.srq.start = val[0]; 4382 sc->vres.srq.size = val[1] - val[0] + 1; 4383 sc->params.max_ordird_qp = val[2]; 4384 sc->params.max_ird_adapter = val[3]; 4385 } 4386 if (sc->iscsicaps) { 4387 param[0] = FW_PARAM_PFVF(ISCSI_START); 4388 param[1] = FW_PARAM_PFVF(ISCSI_END); 4389 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4390 if (rc != 0) { 4391 device_printf(sc->dev, 4392 "failed to query iSCSI parameters: %d.\n", rc); 4393 return (rc); 4394 } 4395 sc->vres.iscsi.start = val[0]; 4396 sc->vres.iscsi.size = val[1] - val[0] + 1; 4397 } 4398 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4399 param[0] = FW_PARAM_PFVF(TLS_START); 4400 param[1] = FW_PARAM_PFVF(TLS_END); 4401 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4402 if (rc != 0) { 4403 device_printf(sc->dev, 4404 "failed to query TLS parameters: %d.\n", rc); 4405 return (rc); 4406 } 4407 sc->vres.key.start = val[0]; 4408 sc->vres.key.size = val[1] - val[0] + 1; 4409 } 4410 4411 t4_init_sge_params(sc); 4412 4413 /* 4414 * We've got the params we wanted to query via the firmware. Now grab 4415 * some others directly from the chip. 4416 */ 4417 rc = t4_read_chip_settings(sc); 4418 4419 return (rc); 4420 } 4421 4422 static int 4423 set_params__post_init(struct adapter *sc) 4424 { 4425 uint32_t param, val; 4426 #ifdef TCP_OFFLOAD 4427 int i, v, shift; 4428 #endif 4429 4430 /* ask for encapsulated CPLs */ 4431 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4432 val = 1; 4433 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4434 4435 /* Enable 32b port caps if the firmware supports it. */ 4436 param = FW_PARAM_PFVF(PORT_CAPS32); 4437 val = 1; 4438 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 4439 sc->params.port_caps32 = 1; 4440 4441 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 4442 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 4443 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 4444 V_MASKFILTER(val - 1)); 4445 4446 #ifdef TCP_OFFLOAD 4447 /* 4448 * Override the TOE timers with user provided tunables. This is not the 4449 * recommended way to change the timers (the firmware config file is) so 4450 * these tunables are not documented. 4451 * 4452 * All the timer tunables are in microseconds. 4453 */ 4454 if (t4_toe_keepalive_idle != 0) { 4455 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4456 v &= M_KEEPALIVEIDLE; 4457 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4458 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4459 } 4460 if (t4_toe_keepalive_interval != 0) { 4461 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4462 v &= M_KEEPALIVEINTVL; 4463 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4464 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4465 } 4466 if (t4_toe_keepalive_count != 0) { 4467 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4468 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4469 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4470 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4471 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4472 } 4473 if (t4_toe_rexmt_min != 0) { 4474 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4475 v &= M_RXTMIN; 4476 t4_set_reg_field(sc, A_TP_RXT_MIN, 4477 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4478 } 4479 if (t4_toe_rexmt_max != 0) { 4480 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4481 v &= M_RXTMAX; 4482 t4_set_reg_field(sc, A_TP_RXT_MAX, 4483 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4484 } 4485 if (t4_toe_rexmt_count != 0) { 4486 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4487 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4488 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4489 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4490 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4491 } 4492 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4493 if (t4_toe_rexmt_backoff[i] != -1) { 4494 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4495 shift = (i & 3) << 3; 4496 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4497 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4498 } 4499 } 4500 #endif 4501 return (0); 4502 } 4503 4504 #undef FW_PARAM_PFVF 4505 #undef FW_PARAM_DEV 4506 4507 static void 4508 t4_set_desc(struct adapter *sc) 4509 { 4510 char buf[128]; 4511 struct adapter_params *p = &sc->params; 4512 4513 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4514 4515 device_set_desc_copy(sc->dev, buf); 4516 } 4517 4518 static inline void 4519 ifmedia_add4(struct ifmedia *ifm, int m) 4520 { 4521 4522 ifmedia_add(ifm, m, 0, NULL); 4523 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4524 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4525 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4526 } 4527 4528 /* 4529 * This is the selected media, which is not quite the same as the active media. 4530 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 4531 * and active are not the same, and "media: Ethernet selected" otherwise. 4532 */ 4533 static void 4534 set_current_media(struct port_info *pi) 4535 { 4536 struct link_config *lc; 4537 struct ifmedia *ifm; 4538 int mword; 4539 u_int speed; 4540 4541 PORT_LOCK_ASSERT_OWNED(pi); 4542 4543 /* Leave current media alone if it's already set to IFM_NONE. */ 4544 ifm = &pi->media; 4545 if (ifm->ifm_cur != NULL && 4546 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4547 return; 4548 4549 lc = &pi->link_cfg; 4550 if (lc->requested_aneg != AUTONEG_DISABLE && 4551 lc->supported & FW_PORT_CAP32_ANEG) { 4552 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4553 return; 4554 } 4555 mword = IFM_ETHER | IFM_FDX; 4556 if (lc->requested_fc & PAUSE_TX) 4557 mword |= IFM_ETH_TXPAUSE; 4558 if (lc->requested_fc & PAUSE_RX) 4559 mword |= IFM_ETH_RXPAUSE; 4560 if (lc->requested_speed == 0) 4561 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 4562 else 4563 speed = lc->requested_speed; 4564 mword |= port_mword(pi, speed_to_fwcap(speed)); 4565 ifmedia_set(ifm, mword); 4566 } 4567 4568 /* 4569 * Returns true if the ifmedia list for the port cannot change. 4570 */ 4571 static bool 4572 fixed_ifmedia(struct port_info *pi) 4573 { 4574 4575 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 4576 pi->port_type == FW_PORT_TYPE_BT_XFI || 4577 pi->port_type == FW_PORT_TYPE_BT_XAUI || 4578 pi->port_type == FW_PORT_TYPE_KX4 || 4579 pi->port_type == FW_PORT_TYPE_KX || 4580 pi->port_type == FW_PORT_TYPE_KR || 4581 pi->port_type == FW_PORT_TYPE_BP_AP || 4582 pi->port_type == FW_PORT_TYPE_BP4_AP || 4583 pi->port_type == FW_PORT_TYPE_BP40_BA || 4584 pi->port_type == FW_PORT_TYPE_KR4_100G || 4585 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 4586 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 4587 } 4588 4589 static void 4590 build_medialist(struct port_info *pi) 4591 { 4592 uint32_t ss, speed; 4593 int unknown, mword, bit; 4594 struct link_config *lc; 4595 struct ifmedia *ifm; 4596 4597 PORT_LOCK_ASSERT_OWNED(pi); 4598 4599 if (pi->flags & FIXED_IFMEDIA) 4600 return; 4601 4602 /* 4603 * Rebuild the ifmedia list. 4604 */ 4605 ifm = &pi->media; 4606 ifmedia_removeall(ifm); 4607 lc = &pi->link_cfg; 4608 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */ 4609 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 4610 MPASS(ss != 0); 4611 no_media: 4612 MPASS(LIST_EMPTY(&ifm->ifm_list)); 4613 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 4614 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 4615 return; 4616 } 4617 4618 unknown = 0; 4619 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 4620 speed = 1 << bit; 4621 MPASS(speed & M_FW_PORT_CAP32_SPEED); 4622 if (ss & speed) { 4623 mword = port_mword(pi, speed); 4624 if (mword == IFM_NONE) { 4625 goto no_media; 4626 } else if (mword == IFM_UNKNOWN) 4627 unknown++; 4628 else 4629 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 4630 } 4631 } 4632 if (unknown > 0) /* Add one unknown for all unknown media types. */ 4633 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 4634 if (lc->supported & FW_PORT_CAP32_ANEG) 4635 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 4636 4637 set_current_media(pi); 4638 } 4639 4640 /* 4641 * Initialize the requested fields in the link config based on driver tunables. 4642 */ 4643 static void 4644 init_link_config(struct port_info *pi) 4645 { 4646 struct link_config *lc = &pi->link_cfg; 4647 4648 PORT_LOCK_ASSERT_OWNED(pi); 4649 4650 lc->requested_speed = 0; 4651 4652 if (t4_autoneg == 0) 4653 lc->requested_aneg = AUTONEG_DISABLE; 4654 else if (t4_autoneg == 1) 4655 lc->requested_aneg = AUTONEG_ENABLE; 4656 else 4657 lc->requested_aneg = AUTONEG_AUTO; 4658 4659 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 4660 PAUSE_AUTONEG); 4661 4662 if (t4_fec == -1 || t4_fec & FEC_AUTO) 4663 lc->requested_fec = FEC_AUTO; 4664 else { 4665 lc->requested_fec = FEC_NONE; 4666 if (t4_fec & FEC_RS) 4667 lc->requested_fec |= FEC_RS; 4668 if (t4_fec & FEC_BASER_RS) 4669 lc->requested_fec |= FEC_BASER_RS; 4670 } 4671 } 4672 4673 /* 4674 * Makes sure that all requested settings comply with what's supported by the 4675 * port. Returns the number of settings that were invalid and had to be fixed. 4676 */ 4677 static int 4678 fixup_link_config(struct port_info *pi) 4679 { 4680 int n = 0; 4681 struct link_config *lc = &pi->link_cfg; 4682 uint32_t fwspeed; 4683 4684 PORT_LOCK_ASSERT_OWNED(pi); 4685 4686 /* Speed (when not autonegotiating) */ 4687 if (lc->requested_speed != 0) { 4688 fwspeed = speed_to_fwcap(lc->requested_speed); 4689 if ((fwspeed & lc->supported) == 0) { 4690 n++; 4691 lc->requested_speed = 0; 4692 } 4693 } 4694 4695 /* Link autonegotiation */ 4696 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 4697 lc->requested_aneg == AUTONEG_DISABLE || 4698 lc->requested_aneg == AUTONEG_AUTO); 4699 if (lc->requested_aneg == AUTONEG_ENABLE && 4700 !(lc->supported & FW_PORT_CAP32_ANEG)) { 4701 n++; 4702 lc->requested_aneg = AUTONEG_AUTO; 4703 } 4704 4705 /* Flow control */ 4706 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 4707 if (lc->requested_fc & PAUSE_TX && 4708 !(lc->supported & FW_PORT_CAP32_FC_TX)) { 4709 n++; 4710 lc->requested_fc &= ~PAUSE_TX; 4711 } 4712 if (lc->requested_fc & PAUSE_RX && 4713 !(lc->supported & FW_PORT_CAP32_FC_RX)) { 4714 n++; 4715 lc->requested_fc &= ~PAUSE_RX; 4716 } 4717 if (!(lc->requested_fc & PAUSE_AUTONEG) && 4718 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) { 4719 n++; 4720 lc->requested_fc |= PAUSE_AUTONEG; 4721 } 4722 4723 /* FEC */ 4724 if ((lc->requested_fec & FEC_RS && 4725 !(lc->supported & FW_PORT_CAP32_FEC_RS)) || 4726 (lc->requested_fec & FEC_BASER_RS && 4727 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) { 4728 n++; 4729 lc->requested_fec = FEC_AUTO; 4730 } 4731 4732 return (n); 4733 } 4734 4735 /* 4736 * Apply the requested L1 settings, which are expected to be valid, to the 4737 * hardware. 4738 */ 4739 static int 4740 apply_link_config(struct port_info *pi) 4741 { 4742 struct adapter *sc = pi->adapter; 4743 struct link_config *lc = &pi->link_cfg; 4744 int rc; 4745 4746 #ifdef INVARIANTS 4747 ASSERT_SYNCHRONIZED_OP(sc); 4748 PORT_LOCK_ASSERT_OWNED(pi); 4749 4750 if (lc->requested_aneg == AUTONEG_ENABLE) 4751 MPASS(lc->supported & FW_PORT_CAP32_ANEG); 4752 if (!(lc->requested_fc & PAUSE_AUTONEG)) 4753 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE); 4754 if (lc->requested_fc & PAUSE_TX) 4755 MPASS(lc->supported & FW_PORT_CAP32_FC_TX); 4756 if (lc->requested_fc & PAUSE_RX) 4757 MPASS(lc->supported & FW_PORT_CAP32_FC_RX); 4758 if (lc->requested_fec & FEC_RS) 4759 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS); 4760 if (lc->requested_fec & FEC_BASER_RS) 4761 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS); 4762 #endif 4763 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4764 if (rc != 0) { 4765 /* Don't complain if the VF driver gets back an EPERM. */ 4766 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 4767 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4768 } else { 4769 /* 4770 * An L1_CFG will almost always result in a link-change event if 4771 * the link is up, and the driver will refresh the actual 4772 * fec/fc/etc. when the notification is processed. If the link 4773 * is down then the actual settings are meaningless. 4774 * 4775 * This takes care of the case where a change in the L1 settings 4776 * may not result in a notification. 4777 */ 4778 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 4779 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 4780 } 4781 return (rc); 4782 } 4783 4784 #define FW_MAC_EXACT_CHUNK 7 4785 4786 /* 4787 * Program the port's XGMAC based on parameters in ifnet. The caller also 4788 * indicates which parameters should be programmed (the rest are left alone). 4789 */ 4790 int 4791 update_mac_settings(struct ifnet *ifp, int flags) 4792 { 4793 int rc = 0; 4794 struct vi_info *vi = ifp->if_softc; 4795 struct port_info *pi = vi->pi; 4796 struct adapter *sc = pi->adapter; 4797 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4798 4799 ASSERT_SYNCHRONIZED_OP(sc); 4800 KASSERT(flags, ("%s: not told what to update.", __func__)); 4801 4802 if (flags & XGMAC_MTU) 4803 mtu = ifp->if_mtu; 4804 4805 if (flags & XGMAC_PROMISC) 4806 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4807 4808 if (flags & XGMAC_ALLMULTI) 4809 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4810 4811 if (flags & XGMAC_VLANEX) 4812 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4813 4814 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4815 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4816 allmulti, 1, vlanex, false); 4817 if (rc) { 4818 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4819 rc); 4820 return (rc); 4821 } 4822 } 4823 4824 if (flags & XGMAC_UCADDR) { 4825 uint8_t ucaddr[ETHER_ADDR_LEN]; 4826 4827 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4828 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4829 ucaddr, true, &vi->smt_idx); 4830 if (rc < 0) { 4831 rc = -rc; 4832 if_printf(ifp, "change_mac failed: %d\n", rc); 4833 return (rc); 4834 } else { 4835 vi->xact_addr_filt = rc; 4836 rc = 0; 4837 } 4838 } 4839 4840 if (flags & XGMAC_MCADDRS) { 4841 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4842 int del = 1; 4843 uint64_t hash = 0; 4844 struct ifmultiaddr *ifma; 4845 int i = 0, j; 4846 4847 if_maddr_rlock(ifp); 4848 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4849 if (ifma->ifma_addr->sa_family != AF_LINK) 4850 continue; 4851 mcaddr[i] = 4852 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4853 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4854 i++; 4855 4856 if (i == FW_MAC_EXACT_CHUNK) { 4857 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4858 del, i, mcaddr, NULL, &hash, 0); 4859 if (rc < 0) { 4860 rc = -rc; 4861 for (j = 0; j < i; j++) { 4862 if_printf(ifp, 4863 "failed to add mc address" 4864 " %02x:%02x:%02x:" 4865 "%02x:%02x:%02x rc=%d\n", 4866 mcaddr[j][0], mcaddr[j][1], 4867 mcaddr[j][2], mcaddr[j][3], 4868 mcaddr[j][4], mcaddr[j][5], 4869 rc); 4870 } 4871 goto mcfail; 4872 } 4873 del = 0; 4874 i = 0; 4875 } 4876 } 4877 if (i > 0) { 4878 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4879 mcaddr, NULL, &hash, 0); 4880 if (rc < 0) { 4881 rc = -rc; 4882 for (j = 0; j < i; j++) { 4883 if_printf(ifp, 4884 "failed to add mc address" 4885 " %02x:%02x:%02x:" 4886 "%02x:%02x:%02x rc=%d\n", 4887 mcaddr[j][0], mcaddr[j][1], 4888 mcaddr[j][2], mcaddr[j][3], 4889 mcaddr[j][4], mcaddr[j][5], 4890 rc); 4891 } 4892 goto mcfail; 4893 } 4894 } 4895 4896 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4897 if (rc != 0) 4898 if_printf(ifp, "failed to set mc address hash: %d", rc); 4899 mcfail: 4900 if_maddr_runlock(ifp); 4901 } 4902 4903 return (rc); 4904 } 4905 4906 /* 4907 * {begin|end}_synchronized_op must be called from the same thread. 4908 */ 4909 int 4910 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4911 char *wmesg) 4912 { 4913 int rc, pri; 4914 4915 #ifdef WITNESS 4916 /* the caller thinks it's ok to sleep, but is it really? */ 4917 if (flags & SLEEP_OK) 4918 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4919 "begin_synchronized_op"); 4920 #endif 4921 4922 if (INTR_OK) 4923 pri = PCATCH; 4924 else 4925 pri = 0; 4926 4927 ADAPTER_LOCK(sc); 4928 for (;;) { 4929 4930 if (vi && IS_DOOMED(vi)) { 4931 rc = ENXIO; 4932 goto done; 4933 } 4934 4935 if (!IS_BUSY(sc)) { 4936 rc = 0; 4937 break; 4938 } 4939 4940 if (!(flags & SLEEP_OK)) { 4941 rc = EBUSY; 4942 goto done; 4943 } 4944 4945 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4946 rc = EINTR; 4947 goto done; 4948 } 4949 } 4950 4951 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4952 SET_BUSY(sc); 4953 #ifdef INVARIANTS 4954 sc->last_op = wmesg; 4955 sc->last_op_thr = curthread; 4956 sc->last_op_flags = flags; 4957 #endif 4958 4959 done: 4960 if (!(flags & HOLD_LOCK) || rc) 4961 ADAPTER_UNLOCK(sc); 4962 4963 return (rc); 4964 } 4965 4966 /* 4967 * Tell if_ioctl and if_init that the VI is going away. This is 4968 * special variant of begin_synchronized_op and must be paired with a 4969 * call to end_synchronized_op. 4970 */ 4971 void 4972 doom_vi(struct adapter *sc, struct vi_info *vi) 4973 { 4974 4975 ADAPTER_LOCK(sc); 4976 SET_DOOMED(vi); 4977 wakeup(&sc->flags); 4978 while (IS_BUSY(sc)) 4979 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4980 SET_BUSY(sc); 4981 #ifdef INVARIANTS 4982 sc->last_op = "t4detach"; 4983 sc->last_op_thr = curthread; 4984 sc->last_op_flags = 0; 4985 #endif 4986 ADAPTER_UNLOCK(sc); 4987 } 4988 4989 /* 4990 * {begin|end}_synchronized_op must be called from the same thread. 4991 */ 4992 void 4993 end_synchronized_op(struct adapter *sc, int flags) 4994 { 4995 4996 if (flags & LOCK_HELD) 4997 ADAPTER_LOCK_ASSERT_OWNED(sc); 4998 else 4999 ADAPTER_LOCK(sc); 5000 5001 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 5002 CLR_BUSY(sc); 5003 wakeup(&sc->flags); 5004 ADAPTER_UNLOCK(sc); 5005 } 5006 5007 static int 5008 cxgbe_init_synchronized(struct vi_info *vi) 5009 { 5010 struct port_info *pi = vi->pi; 5011 struct adapter *sc = pi->adapter; 5012 struct ifnet *ifp = vi->ifp; 5013 int rc = 0, i; 5014 struct sge_txq *txq; 5015 5016 ASSERT_SYNCHRONIZED_OP(sc); 5017 5018 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5019 return (0); /* already running */ 5020 5021 if (!(sc->flags & FULL_INIT_DONE) && 5022 ((rc = adapter_full_init(sc)) != 0)) 5023 return (rc); /* error message displayed already */ 5024 5025 if (!(vi->flags & VI_INIT_DONE) && 5026 ((rc = vi_full_init(vi)) != 0)) 5027 return (rc); /* error message displayed already */ 5028 5029 rc = update_mac_settings(ifp, XGMAC_ALL); 5030 if (rc) 5031 goto done; /* error message displayed already */ 5032 5033 PORT_LOCK(pi); 5034 if (pi->up_vis == 0) { 5035 t4_update_port_info(pi); 5036 fixup_link_config(pi); 5037 build_medialist(pi); 5038 apply_link_config(pi); 5039 } 5040 5041 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 5042 if (rc != 0) { 5043 if_printf(ifp, "enable_vi failed: %d\n", rc); 5044 PORT_UNLOCK(pi); 5045 goto done; 5046 } 5047 5048 /* 5049 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 5050 * if this changes. 5051 */ 5052 5053 for_each_txq(vi, i, txq) { 5054 TXQ_LOCK(txq); 5055 txq->eq.flags |= EQ_ENABLED; 5056 TXQ_UNLOCK(txq); 5057 } 5058 5059 /* 5060 * The first iq of the first port to come up is used for tracing. 5061 */ 5062 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 5063 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 5064 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 5065 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 5066 V_QUEUENUMBER(sc->traceq)); 5067 pi->flags |= HAS_TRACEQ; 5068 } 5069 5070 /* all ok */ 5071 pi->up_vis++; 5072 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5073 5074 if (pi->nvi > 1 || sc->flags & IS_VF) 5075 callout_reset(&vi->tick, hz, vi_tick, vi); 5076 else 5077 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 5078 if (pi->link_cfg.link_ok) 5079 t4_os_link_changed(pi); 5080 PORT_UNLOCK(pi); 5081 done: 5082 if (rc != 0) 5083 cxgbe_uninit_synchronized(vi); 5084 5085 return (rc); 5086 } 5087 5088 /* 5089 * Idempotent. 5090 */ 5091 static int 5092 cxgbe_uninit_synchronized(struct vi_info *vi) 5093 { 5094 struct port_info *pi = vi->pi; 5095 struct adapter *sc = pi->adapter; 5096 struct ifnet *ifp = vi->ifp; 5097 int rc, i; 5098 struct sge_txq *txq; 5099 5100 ASSERT_SYNCHRONIZED_OP(sc); 5101 5102 if (!(vi->flags & VI_INIT_DONE)) { 5103 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5104 KASSERT(0, ("uninited VI is running")); 5105 if_printf(ifp, "uninited VI with running ifnet. " 5106 "vi->flags 0x%016lx, if_flags 0x%08x, " 5107 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 5108 ifp->if_drv_flags); 5109 } 5110 return (0); 5111 } 5112 5113 /* 5114 * Disable the VI so that all its data in either direction is discarded 5115 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 5116 * tick) intact as the TP can deliver negative advice or data that it's 5117 * holding in its RAM (for an offloaded connection) even after the VI is 5118 * disabled. 5119 */ 5120 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 5121 if (rc) { 5122 if_printf(ifp, "disable_vi failed: %d\n", rc); 5123 return (rc); 5124 } 5125 5126 for_each_txq(vi, i, txq) { 5127 TXQ_LOCK(txq); 5128 txq->eq.flags &= ~EQ_ENABLED; 5129 TXQ_UNLOCK(txq); 5130 } 5131 5132 PORT_LOCK(pi); 5133 if (pi->nvi > 1 || sc->flags & IS_VF) 5134 callout_stop(&vi->tick); 5135 else 5136 callout_stop(&pi->tick); 5137 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5138 PORT_UNLOCK(pi); 5139 return (0); 5140 } 5141 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5142 pi->up_vis--; 5143 if (pi->up_vis > 0) { 5144 PORT_UNLOCK(pi); 5145 return (0); 5146 } 5147 5148 pi->link_cfg.link_ok = false; 5149 pi->link_cfg.speed = 0; 5150 pi->link_cfg.link_down_rc = 255; 5151 t4_os_link_changed(pi); 5152 PORT_UNLOCK(pi); 5153 5154 return (0); 5155 } 5156 5157 /* 5158 * It is ok for this function to fail midway and return right away. t4_detach 5159 * will walk the entire sc->irq list and clean up whatever is valid. 5160 */ 5161 int 5162 t4_setup_intr_handlers(struct adapter *sc) 5163 { 5164 int rc, rid, p, q, v; 5165 char s[8]; 5166 struct irq *irq; 5167 struct port_info *pi; 5168 struct vi_info *vi; 5169 struct sge *sge = &sc->sge; 5170 struct sge_rxq *rxq; 5171 #ifdef TCP_OFFLOAD 5172 struct sge_ofld_rxq *ofld_rxq; 5173 #endif 5174 #ifdef DEV_NETMAP 5175 struct sge_nm_rxq *nm_rxq; 5176 #endif 5177 #ifdef RSS 5178 int nbuckets = rss_getnumbuckets(); 5179 #endif 5180 5181 /* 5182 * Setup interrupts. 5183 */ 5184 irq = &sc->irq[0]; 5185 rid = sc->intr_type == INTR_INTX ? 0 : 1; 5186 if (forwarding_intr_to_fwq(sc)) 5187 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 5188 5189 /* Multiple interrupts. */ 5190 if (sc->flags & IS_VF) 5191 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 5192 ("%s: too few intr.", __func__)); 5193 else 5194 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 5195 ("%s: too few intr.", __func__)); 5196 5197 /* The first one is always error intr on PFs */ 5198 if (!(sc->flags & IS_VF)) { 5199 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 5200 if (rc != 0) 5201 return (rc); 5202 irq++; 5203 rid++; 5204 } 5205 5206 /* The second one is always the firmware event queue (first on VFs) */ 5207 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 5208 if (rc != 0) 5209 return (rc); 5210 irq++; 5211 rid++; 5212 5213 for_each_port(sc, p) { 5214 pi = sc->port[p]; 5215 for_each_vi(pi, v, vi) { 5216 vi->first_intr = rid - 1; 5217 5218 if (vi->nnmrxq > 0) { 5219 int n = max(vi->nrxq, vi->nnmrxq); 5220 5221 rxq = &sge->rxq[vi->first_rxq]; 5222 #ifdef DEV_NETMAP 5223 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 5224 #endif 5225 for (q = 0; q < n; q++) { 5226 snprintf(s, sizeof(s), "%x%c%x", p, 5227 'a' + v, q); 5228 if (q < vi->nrxq) 5229 irq->rxq = rxq++; 5230 #ifdef DEV_NETMAP 5231 if (q < vi->nnmrxq) 5232 irq->nm_rxq = nm_rxq++; 5233 5234 if (irq->nm_rxq != NULL && 5235 irq->rxq == NULL) { 5236 /* Netmap rx only */ 5237 rc = t4_alloc_irq(sc, irq, rid, 5238 t4_nm_intr, irq->nm_rxq, s); 5239 } 5240 if (irq->nm_rxq != NULL && 5241 irq->rxq != NULL) { 5242 /* NIC and Netmap rx */ 5243 rc = t4_alloc_irq(sc, irq, rid, 5244 t4_vi_intr, irq, s); 5245 } 5246 #endif 5247 if (irq->rxq != NULL && 5248 irq->nm_rxq == NULL) { 5249 /* NIC rx only */ 5250 rc = t4_alloc_irq(sc, irq, rid, 5251 t4_intr, irq->rxq, s); 5252 } 5253 if (rc != 0) 5254 return (rc); 5255 #ifdef RSS 5256 if (q < vi->nrxq) { 5257 bus_bind_intr(sc->dev, irq->res, 5258 rss_getcpu(q % nbuckets)); 5259 } 5260 #endif 5261 irq++; 5262 rid++; 5263 vi->nintr++; 5264 } 5265 } else { 5266 for_each_rxq(vi, q, rxq) { 5267 snprintf(s, sizeof(s), "%x%c%x", p, 5268 'a' + v, q); 5269 rc = t4_alloc_irq(sc, irq, rid, 5270 t4_intr, rxq, s); 5271 if (rc != 0) 5272 return (rc); 5273 #ifdef RSS 5274 bus_bind_intr(sc->dev, irq->res, 5275 rss_getcpu(q % nbuckets)); 5276 #endif 5277 irq++; 5278 rid++; 5279 vi->nintr++; 5280 } 5281 } 5282 #ifdef TCP_OFFLOAD 5283 for_each_ofld_rxq(vi, q, ofld_rxq) { 5284 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 5285 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 5286 ofld_rxq, s); 5287 if (rc != 0) 5288 return (rc); 5289 irq++; 5290 rid++; 5291 vi->nintr++; 5292 } 5293 #endif 5294 } 5295 } 5296 MPASS(irq == &sc->irq[sc->intr_count]); 5297 5298 return (0); 5299 } 5300 5301 int 5302 adapter_full_init(struct adapter *sc) 5303 { 5304 int rc, i; 5305 #ifdef RSS 5306 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5307 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5308 #endif 5309 5310 ASSERT_SYNCHRONIZED_OP(sc); 5311 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5312 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 5313 ("%s: FULL_INIT_DONE already", __func__)); 5314 5315 /* 5316 * queues that belong to the adapter (not any particular port). 5317 */ 5318 rc = t4_setup_adapter_queues(sc); 5319 if (rc != 0) 5320 goto done; 5321 5322 for (i = 0; i < nitems(sc->tq); i++) { 5323 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 5324 taskqueue_thread_enqueue, &sc->tq[i]); 5325 if (sc->tq[i] == NULL) { 5326 device_printf(sc->dev, 5327 "failed to allocate task queue %d\n", i); 5328 rc = ENOMEM; 5329 goto done; 5330 } 5331 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 5332 device_get_nameunit(sc->dev), i); 5333 } 5334 #ifdef RSS 5335 MPASS(RSS_KEYSIZE == 40); 5336 rss_getkey((void *)&raw_rss_key[0]); 5337 for (i = 0; i < nitems(rss_key); i++) { 5338 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 5339 } 5340 t4_write_rss_key(sc, &rss_key[0], -1, 1); 5341 #endif 5342 5343 if (!(sc->flags & IS_VF)) 5344 t4_intr_enable(sc); 5345 sc->flags |= FULL_INIT_DONE; 5346 done: 5347 if (rc != 0) 5348 adapter_full_uninit(sc); 5349 5350 return (rc); 5351 } 5352 5353 int 5354 adapter_full_uninit(struct adapter *sc) 5355 { 5356 int i; 5357 5358 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5359 5360 t4_teardown_adapter_queues(sc); 5361 5362 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 5363 taskqueue_free(sc->tq[i]); 5364 sc->tq[i] = NULL; 5365 } 5366 5367 sc->flags &= ~FULL_INIT_DONE; 5368 5369 return (0); 5370 } 5371 5372 #ifdef RSS 5373 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 5374 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 5375 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 5376 RSS_HASHTYPE_RSS_UDP_IPV6) 5377 5378 /* Translates kernel hash types to hardware. */ 5379 static int 5380 hashconfig_to_hashen(int hashconfig) 5381 { 5382 int hashen = 0; 5383 5384 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 5385 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 5386 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 5387 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 5388 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 5389 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5390 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5391 } 5392 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 5393 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5394 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5395 } 5396 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 5397 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5398 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 5399 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5400 5401 return (hashen); 5402 } 5403 5404 /* Translates hardware hash types to kernel. */ 5405 static int 5406 hashen_to_hashconfig(int hashen) 5407 { 5408 int hashconfig = 0; 5409 5410 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 5411 /* 5412 * If UDP hashing was enabled it must have been enabled for 5413 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 5414 * enabling any 4-tuple hash is nonsense configuration. 5415 */ 5416 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5417 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 5418 5419 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5420 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 5421 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5422 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 5423 } 5424 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5425 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 5426 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5427 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 5428 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 5429 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 5430 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 5431 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 5432 5433 return (hashconfig); 5434 } 5435 #endif 5436 5437 int 5438 vi_full_init(struct vi_info *vi) 5439 { 5440 struct adapter *sc = vi->pi->adapter; 5441 struct ifnet *ifp = vi->ifp; 5442 uint16_t *rss; 5443 struct sge_rxq *rxq; 5444 int rc, i, j; 5445 #ifdef RSS 5446 int nbuckets = rss_getnumbuckets(); 5447 int hashconfig = rss_gethashconfig(); 5448 int extra; 5449 #endif 5450 5451 ASSERT_SYNCHRONIZED_OP(sc); 5452 KASSERT((vi->flags & VI_INIT_DONE) == 0, 5453 ("%s: VI_INIT_DONE already", __func__)); 5454 5455 sysctl_ctx_init(&vi->ctx); 5456 vi->flags |= VI_SYSCTL_CTX; 5457 5458 /* 5459 * Allocate tx/rx/fl queues for this VI. 5460 */ 5461 rc = t4_setup_vi_queues(vi); 5462 if (rc != 0) 5463 goto done; /* error message displayed already */ 5464 5465 /* 5466 * Setup RSS for this VI. Save a copy of the RSS table for later use. 5467 */ 5468 if (vi->nrxq > vi->rss_size) { 5469 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 5470 "some queues will never receive traffic.\n", vi->nrxq, 5471 vi->rss_size); 5472 } else if (vi->rss_size % vi->nrxq) { 5473 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 5474 "expect uneven traffic distribution.\n", vi->nrxq, 5475 vi->rss_size); 5476 } 5477 #ifdef RSS 5478 if (vi->nrxq != nbuckets) { 5479 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5480 "performance will be impacted.\n", vi->nrxq, nbuckets); 5481 } 5482 #endif 5483 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5484 for (i = 0; i < vi->rss_size;) { 5485 #ifdef RSS 5486 j = rss_get_indirection_to_bucket(i); 5487 j %= vi->nrxq; 5488 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5489 rss[i++] = rxq->iq.abs_id; 5490 #else 5491 for_each_rxq(vi, j, rxq) { 5492 rss[i++] = rxq->iq.abs_id; 5493 if (i == vi->rss_size) 5494 break; 5495 } 5496 #endif 5497 } 5498 5499 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5500 vi->rss_size); 5501 if (rc != 0) { 5502 free(rss, M_CXGBE); 5503 if_printf(ifp, "rss_config failed: %d\n", rc); 5504 goto done; 5505 } 5506 5507 #ifdef RSS 5508 vi->hashen = hashconfig_to_hashen(hashconfig); 5509 5510 /* 5511 * We may have had to enable some hashes even though the global config 5512 * wants them disabled. This is a potential problem that must be 5513 * reported to the user. 5514 */ 5515 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 5516 5517 /* 5518 * If we consider only the supported hash types, then the enabled hashes 5519 * are a superset of the requested hashes. In other words, there cannot 5520 * be any supported hash that was requested but not enabled, but there 5521 * can be hashes that were not requested but had to be enabled. 5522 */ 5523 extra &= SUPPORTED_RSS_HASHTYPES; 5524 MPASS((extra & hashconfig) == 0); 5525 5526 if (extra) { 5527 if_printf(ifp, 5528 "global RSS config (0x%x) cannot be accommodated.\n", 5529 hashconfig); 5530 } 5531 if (extra & RSS_HASHTYPE_RSS_IPV4) 5532 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 5533 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 5534 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 5535 if (extra & RSS_HASHTYPE_RSS_IPV6) 5536 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 5537 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 5538 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 5539 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 5540 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 5541 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 5542 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 5543 #else 5544 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 5545 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 5546 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5547 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 5548 #endif 5549 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0); 5550 if (rc != 0) { 5551 free(rss, M_CXGBE); 5552 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 5553 goto done; 5554 } 5555 5556 vi->rss = rss; 5557 vi->flags |= VI_INIT_DONE; 5558 done: 5559 if (rc != 0) 5560 vi_full_uninit(vi); 5561 5562 return (rc); 5563 } 5564 5565 /* 5566 * Idempotent. 5567 */ 5568 int 5569 vi_full_uninit(struct vi_info *vi) 5570 { 5571 struct port_info *pi = vi->pi; 5572 struct adapter *sc = pi->adapter; 5573 int i; 5574 struct sge_rxq *rxq; 5575 struct sge_txq *txq; 5576 #ifdef TCP_OFFLOAD 5577 struct sge_ofld_rxq *ofld_rxq; 5578 #endif 5579 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5580 struct sge_wrq *ofld_txq; 5581 #endif 5582 5583 if (vi->flags & VI_INIT_DONE) { 5584 5585 /* Need to quiesce queues. */ 5586 5587 /* XXX: Only for the first VI? */ 5588 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5589 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5590 5591 for_each_txq(vi, i, txq) { 5592 quiesce_txq(sc, txq); 5593 } 5594 5595 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5596 for_each_ofld_txq(vi, i, ofld_txq) { 5597 quiesce_wrq(sc, ofld_txq); 5598 } 5599 #endif 5600 5601 for_each_rxq(vi, i, rxq) { 5602 quiesce_iq(sc, &rxq->iq); 5603 quiesce_fl(sc, &rxq->fl); 5604 } 5605 5606 #ifdef TCP_OFFLOAD 5607 for_each_ofld_rxq(vi, i, ofld_rxq) { 5608 quiesce_iq(sc, &ofld_rxq->iq); 5609 quiesce_fl(sc, &ofld_rxq->fl); 5610 } 5611 #endif 5612 free(vi->rss, M_CXGBE); 5613 free(vi->nm_rss, M_CXGBE); 5614 } 5615 5616 t4_teardown_vi_queues(vi); 5617 vi->flags &= ~VI_INIT_DONE; 5618 5619 return (0); 5620 } 5621 5622 static void 5623 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5624 { 5625 struct sge_eq *eq = &txq->eq; 5626 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5627 5628 (void) sc; /* unused */ 5629 5630 #ifdef INVARIANTS 5631 TXQ_LOCK(txq); 5632 MPASS((eq->flags & EQ_ENABLED) == 0); 5633 TXQ_UNLOCK(txq); 5634 #endif 5635 5636 /* Wait for the mp_ring to empty. */ 5637 while (!mp_ring_is_idle(txq->r)) { 5638 mp_ring_check_drainage(txq->r, 0); 5639 pause("rquiesce", 1); 5640 } 5641 5642 /* Then wait for the hardware to finish. */ 5643 while (spg->cidx != htobe16(eq->pidx)) 5644 pause("equiesce", 1); 5645 5646 /* Finally, wait for the driver to reclaim all descriptors. */ 5647 while (eq->cidx != eq->pidx) 5648 pause("dquiesce", 1); 5649 } 5650 5651 static void 5652 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5653 { 5654 5655 /* XXXTX */ 5656 } 5657 5658 static void 5659 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5660 { 5661 (void) sc; /* unused */ 5662 5663 /* Synchronize with the interrupt handler */ 5664 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5665 pause("iqfree", 1); 5666 } 5667 5668 static void 5669 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5670 { 5671 mtx_lock(&sc->sfl_lock); 5672 FL_LOCK(fl); 5673 fl->flags |= FL_DOOMED; 5674 FL_UNLOCK(fl); 5675 callout_stop(&sc->sfl_callout); 5676 mtx_unlock(&sc->sfl_lock); 5677 5678 KASSERT((fl->flags & FL_STARVING) == 0, 5679 ("%s: still starving", __func__)); 5680 } 5681 5682 static int 5683 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5684 driver_intr_t *handler, void *arg, char *name) 5685 { 5686 int rc; 5687 5688 irq->rid = rid; 5689 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5690 RF_SHAREABLE | RF_ACTIVE); 5691 if (irq->res == NULL) { 5692 device_printf(sc->dev, 5693 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5694 return (ENOMEM); 5695 } 5696 5697 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5698 NULL, handler, arg, &irq->tag); 5699 if (rc != 0) { 5700 device_printf(sc->dev, 5701 "failed to setup interrupt for rid %d, name %s: %d\n", 5702 rid, name, rc); 5703 } else if (name) 5704 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5705 5706 return (rc); 5707 } 5708 5709 static int 5710 t4_free_irq(struct adapter *sc, struct irq *irq) 5711 { 5712 if (irq->tag) 5713 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5714 if (irq->res) 5715 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5716 5717 bzero(irq, sizeof(*irq)); 5718 5719 return (0); 5720 } 5721 5722 static void 5723 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5724 { 5725 5726 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5727 t4_get_regs(sc, buf, regs->len); 5728 } 5729 5730 #define A_PL_INDIR_CMD 0x1f8 5731 5732 #define S_PL_AUTOINC 31 5733 #define M_PL_AUTOINC 0x1U 5734 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5735 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5736 5737 #define S_PL_VFID 20 5738 #define M_PL_VFID 0xffU 5739 #define V_PL_VFID(x) ((x) << S_PL_VFID) 5740 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5741 5742 #define S_PL_ADDR 0 5743 #define M_PL_ADDR 0xfffffU 5744 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5745 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5746 5747 #define A_PL_INDIR_DATA 0x1fc 5748 5749 static uint64_t 5750 read_vf_stat(struct adapter *sc, u_int vin, int reg) 5751 { 5752 u32 stats[2]; 5753 5754 mtx_assert(&sc->reg_lock, MA_OWNED); 5755 if (sc->flags & IS_VF) { 5756 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5757 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5758 } else { 5759 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5760 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 5761 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5762 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5763 } 5764 return (((uint64_t)stats[1]) << 32 | stats[0]); 5765 } 5766 5767 static void 5768 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 5769 { 5770 5771 #define GET_STAT(name) \ 5772 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 5773 5774 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5775 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5776 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5777 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5778 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5779 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5780 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5781 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5782 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5783 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5784 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5785 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5786 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5787 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5788 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5789 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5790 5791 #undef GET_STAT 5792 } 5793 5794 static void 5795 t4_clr_vi_stats(struct adapter *sc, u_int vin) 5796 { 5797 int reg; 5798 5799 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 5800 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5801 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5802 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5803 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5804 } 5805 5806 static void 5807 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5808 { 5809 struct timeval tv; 5810 const struct timeval interval = {0, 250000}; /* 250ms */ 5811 5812 if (!(vi->flags & VI_INIT_DONE)) 5813 return; 5814 5815 getmicrotime(&tv); 5816 timevalsub(&tv, &interval); 5817 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5818 return; 5819 5820 mtx_lock(&sc->reg_lock); 5821 t4_get_vi_stats(sc, vi->vin, &vi->stats); 5822 getmicrotime(&vi->last_refreshed); 5823 mtx_unlock(&sc->reg_lock); 5824 } 5825 5826 static void 5827 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5828 { 5829 u_int i, v, tnl_cong_drops, bg_map; 5830 struct timeval tv; 5831 const struct timeval interval = {0, 250000}; /* 250ms */ 5832 5833 getmicrotime(&tv); 5834 timevalsub(&tv, &interval); 5835 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5836 return; 5837 5838 tnl_cong_drops = 0; 5839 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5840 bg_map = pi->mps_bg_map; 5841 while (bg_map) { 5842 i = ffs(bg_map) - 1; 5843 mtx_lock(&sc->reg_lock); 5844 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5845 A_TP_MIB_TNL_CNG_DROP_0 + i); 5846 mtx_unlock(&sc->reg_lock); 5847 tnl_cong_drops += v; 5848 bg_map &= ~(1 << i); 5849 } 5850 pi->tnl_cong_drops = tnl_cong_drops; 5851 getmicrotime(&pi->last_refreshed); 5852 } 5853 5854 static void 5855 cxgbe_tick(void *arg) 5856 { 5857 struct port_info *pi = arg; 5858 struct adapter *sc = pi->adapter; 5859 5860 PORT_LOCK_ASSERT_OWNED(pi); 5861 cxgbe_refresh_stats(sc, pi); 5862 5863 callout_schedule(&pi->tick, hz); 5864 } 5865 5866 void 5867 vi_tick(void *arg) 5868 { 5869 struct vi_info *vi = arg; 5870 struct adapter *sc = vi->pi->adapter; 5871 5872 vi_refresh_stats(sc, vi); 5873 5874 callout_schedule(&vi->tick, hz); 5875 } 5876 5877 /* 5878 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5879 */ 5880 static char *caps_decoder[] = { 5881 "\20\001IPMI\002NCSI", /* 0: NBM */ 5882 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5883 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5884 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5885 "\006HASHFILTER\007ETHOFLD", 5886 "\20\001TOE", /* 4: TOE */ 5887 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5888 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5889 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5890 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5891 "\007T10DIF" 5892 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5893 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5894 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5895 "\004PO_INITIATOR\005PO_TARGET", 5896 }; 5897 5898 void 5899 t4_sysctls(struct adapter *sc) 5900 { 5901 struct sysctl_ctx_list *ctx; 5902 struct sysctl_oid *oid; 5903 struct sysctl_oid_list *children, *c0; 5904 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5905 5906 ctx = device_get_sysctl_ctx(sc->dev); 5907 5908 /* 5909 * dev.t4nex.X. 5910 */ 5911 oid = device_get_sysctl_tree(sc->dev); 5912 c0 = children = SYSCTL_CHILDREN(oid); 5913 5914 sc->sc_do_rxcopy = 1; 5915 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5916 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5917 5918 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5919 sc->params.nports, "# of ports"); 5920 5921 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5922 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells, 5923 sysctl_bitfield_8b, "A", "available doorbells"); 5924 5925 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5926 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5927 5928 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5929 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5930 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5931 "interrupt holdoff timer values (us)"); 5932 5933 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5934 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5935 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5936 "interrupt holdoff packet counter values"); 5937 5938 t4_sge_sysctls(sc, ctx, children); 5939 5940 sc->lro_timeout = 100; 5941 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5942 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5943 5944 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5945 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5946 5947 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5948 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5949 5950 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5951 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5952 5953 if (sc->flags & IS_VF) 5954 return; 5955 5956 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5957 NULL, chip_rev(sc), "chip hardware revision"); 5958 5959 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5960 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5961 5962 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5963 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5964 5965 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5966 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5967 5968 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5969 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5970 5971 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5972 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5973 5974 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5975 sc->er_version, 0, "expansion ROM version"); 5976 5977 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5978 sc->bs_version, 0, "bootstrap firmware version"); 5979 5980 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5981 NULL, sc->params.scfg_vers, "serial config version"); 5982 5983 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5984 NULL, sc->params.vpd_vers, "VPD version"); 5985 5986 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5987 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5988 5989 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5990 sc->cfcsum, "config file checksum"); 5991 5992 #define SYSCTL_CAP(name, n, text) \ 5993 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5994 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \ 5995 sysctl_bitfield_16b, "A", "available " text " capabilities") 5996 5997 SYSCTL_CAP(nbmcaps, 0, "NBM"); 5998 SYSCTL_CAP(linkcaps, 1, "link"); 5999 SYSCTL_CAP(switchcaps, 2, "switch"); 6000 SYSCTL_CAP(niccaps, 3, "NIC"); 6001 SYSCTL_CAP(toecaps, 4, "TCP offload"); 6002 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 6003 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 6004 SYSCTL_CAP(cryptocaps, 7, "crypto"); 6005 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 6006 #undef SYSCTL_CAP 6007 6008 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 6009 NULL, sc->tids.nftids, "number of filters"); 6010 6011 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 6012 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 6013 "chip temperature (in Celsius)"); 6014 6015 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING | 6016 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A", 6017 "microprocessor load averages (debug firmwares only)"); 6018 6019 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 6020 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 6021 6022 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 6023 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS, 6024 sysctl_cpus, "A", "local CPUs"); 6025 6026 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 6027 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS, 6028 sysctl_cpus, "A", "preferred CPUs for interrupts"); 6029 6030 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 6031 &sc->swintr, 0, "software triggered interrupts"); 6032 6033 /* 6034 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 6035 */ 6036 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 6037 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 6038 "logs and miscellaneous information"); 6039 children = SYSCTL_CHILDREN(oid); 6040 6041 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 6042 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6043 sysctl_cctrl, "A", "congestion control"); 6044 6045 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 6046 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6047 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 6048 6049 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 6050 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 6051 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 6052 6053 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 6054 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 6055 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 6056 6057 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 6058 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 6059 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 6060 6061 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 6062 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 6063 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 6064 6065 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 6066 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 6067 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 6068 6069 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 6070 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_la, 6071 "A", "CIM logic analyzer"); 6072 6073 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 6074 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6075 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 6076 6077 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 6078 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 6079 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 6080 6081 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 6082 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 6083 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 6084 6085 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 6086 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 6087 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 6088 6089 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 6090 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 6091 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 6092 6093 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 6094 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 6095 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 6096 6097 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 6098 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 6099 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 6100 6101 if (chip_id(sc) > CHELSIO_T4) { 6102 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 6103 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 6104 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 6105 6106 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 6107 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 6108 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 6109 } 6110 6111 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 6112 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6113 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 6114 6115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 6116 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6117 sysctl_cim_qcfg, "A", "CIM queue configuration"); 6118 6119 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 6120 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6121 sysctl_cpl_stats, "A", "CPL statistics"); 6122 6123 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 6124 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6125 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 6126 6127 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 6128 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6129 sysctl_devlog, "A", "firmware's device log"); 6130 6131 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 6132 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6133 sysctl_fcoe_stats, "A", "FCoE statistics"); 6134 6135 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 6136 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6137 sysctl_hw_sched, "A", "hardware scheduler "); 6138 6139 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 6140 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6141 sysctl_l2t, "A", "hardware L2 table"); 6142 6143 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 6144 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6145 sysctl_smt, "A", "hardware source MAC table"); 6146 6147 #ifdef INET6 6148 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 6149 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6150 sysctl_clip, "A", "active CLIP table entries"); 6151 #endif 6152 6153 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 6154 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6155 sysctl_lb_stats, "A", "loopback statistics"); 6156 6157 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 6158 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6159 sysctl_meminfo, "A", "memory regions"); 6160 6161 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 6162 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6163 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 6164 "A", "MPS TCAM entries"); 6165 6166 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 6167 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6168 sysctl_path_mtus, "A", "path MTUs"); 6169 6170 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 6171 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6172 sysctl_pm_stats, "A", "PM statistics"); 6173 6174 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 6175 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6176 sysctl_rdma_stats, "A", "RDMA statistics"); 6177 6178 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 6179 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6180 sysctl_tcp_stats, "A", "TCP statistics"); 6181 6182 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 6183 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6184 sysctl_tids, "A", "TID information"); 6185 6186 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 6187 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6188 sysctl_tp_err_stats, "A", "TP error statistics"); 6189 6190 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 6191 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 6192 "TP logic analyzer event capture mask"); 6193 6194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 6195 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6196 sysctl_tp_la, "A", "TP logic analyzer"); 6197 6198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 6199 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6200 sysctl_tx_rate, "A", "Tx rate"); 6201 6202 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 6203 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6204 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 6205 6206 if (chip_id(sc) >= CHELSIO_T5) { 6207 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 6208 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6209 sysctl_wcwr_stats, "A", "write combined work requests"); 6210 } 6211 6212 #ifdef TCP_OFFLOAD 6213 if (is_offload(sc)) { 6214 int i; 6215 char s[4]; 6216 6217 /* 6218 * dev.t4nex.X.toe. 6219 */ 6220 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 6221 NULL, "TOE parameters"); 6222 children = SYSCTL_CHILDREN(oid); 6223 6224 sc->tt.cong_algorithm = -1; 6225 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 6226 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 6227 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 6228 "3 = highspeed)"); 6229 6230 sc->tt.sndbuf = 256 * 1024; 6231 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 6232 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 6233 6234 sc->tt.ddp = 0; 6235 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 6236 &sc->tt.ddp, 0, "DDP allowed"); 6237 6238 sc->tt.rx_coalesce = 1; 6239 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 6240 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 6241 6242 sc->tt.tls = 0; 6243 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 6244 &sc->tt.tls, 0, "Inline TLS allowed"); 6245 6246 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 6247 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 6248 "I", "TCP ports that use inline TLS+TOE RX"); 6249 6250 sc->tt.tx_align = 1; 6251 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 6252 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 6253 6254 sc->tt.tx_zcopy = 0; 6255 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 6256 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 6257 "Enable zero-copy aio_write(2)"); 6258 6259 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 6260 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6261 "cop_managed_offloading", CTLFLAG_RW, 6262 &sc->tt.cop_managed_offloading, 0, 6263 "COP (Connection Offload Policy) controls all TOE offload"); 6264 6265 sc->tt.autorcvbuf_inc = 16 * 1024; 6266 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 6267 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 6268 "autorcvbuf increment"); 6269 6270 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 6271 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 6272 "TP timer tick (us)"); 6273 6274 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 6275 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 6276 "TCP timestamp tick (us)"); 6277 6278 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 6279 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 6280 "DACK tick (us)"); 6281 6282 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 6283 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 6284 "IU", "DACK timer (us)"); 6285 6286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 6287 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 6288 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 6289 6290 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 6291 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 6292 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 6293 6294 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 6295 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 6296 sysctl_tp_timer, "LU", "Persist timer min (us)"); 6297 6298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 6299 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 6300 sysctl_tp_timer, "LU", "Persist timer max (us)"); 6301 6302 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 6303 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 6304 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 6305 6306 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 6307 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 6308 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 6309 6310 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 6311 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 6312 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 6313 6314 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 6315 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 6316 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 6317 6318 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 6319 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 6320 sysctl_tp_shift_cnt, "IU", 6321 "Number of SYN retransmissions before abort"); 6322 6323 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 6324 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 6325 sysctl_tp_shift_cnt, "IU", 6326 "Number of retransmissions before abort"); 6327 6328 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 6329 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 6330 sysctl_tp_shift_cnt, "IU", 6331 "Number of keepalive probes before abort"); 6332 6333 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 6334 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 6335 children = SYSCTL_CHILDREN(oid); 6336 for (i = 0; i < 16; i++) { 6337 snprintf(s, sizeof(s), "%u", i); 6338 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 6339 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 6340 "IU", "TOE retransmit backoff"); 6341 } 6342 } 6343 #endif 6344 } 6345 6346 void 6347 vi_sysctls(struct vi_info *vi) 6348 { 6349 struct sysctl_ctx_list *ctx; 6350 struct sysctl_oid *oid; 6351 struct sysctl_oid_list *children; 6352 6353 ctx = device_get_sysctl_ctx(vi->dev); 6354 6355 /* 6356 * dev.v?(cxgbe|cxl).X. 6357 */ 6358 oid = device_get_sysctl_tree(vi->dev); 6359 children = SYSCTL_CHILDREN(oid); 6360 6361 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 6362 vi->viid, "VI identifer"); 6363 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 6364 &vi->nrxq, 0, "# of rx queues"); 6365 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 6366 &vi->ntxq, 0, "# of tx queues"); 6367 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 6368 &vi->first_rxq, 0, "index of first rx queue"); 6369 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 6370 &vi->first_txq, 0, "index of first tx queue"); 6371 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 6372 vi->rss_base, "start of RSS indirection table"); 6373 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 6374 vi->rss_size, "size of RSS indirection table"); 6375 6376 if (IS_MAIN_VI(vi)) { 6377 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 6378 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 6379 "Reserve queue 0 for non-flowid packets"); 6380 } 6381 6382 #ifdef TCP_OFFLOAD 6383 if (vi->nofldrxq != 0) { 6384 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 6385 &vi->nofldrxq, 0, 6386 "# of rx queues for offloaded TCP connections"); 6387 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 6388 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 6389 "index of first TOE rx queue"); 6390 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 6391 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6392 sysctl_holdoff_tmr_idx_ofld, "I", 6393 "holdoff timer index for TOE queues"); 6394 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 6395 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6396 sysctl_holdoff_pktc_idx_ofld, "I", 6397 "holdoff packet counter index for TOE queues"); 6398 } 6399 #endif 6400 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 6401 if (vi->nofldtxq != 0) { 6402 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 6403 &vi->nofldtxq, 0, 6404 "# of tx queues for TOE/ETHOFLD"); 6405 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 6406 CTLFLAG_RD, &vi->first_ofld_txq, 0, 6407 "index of first TOE/ETHOFLD tx queue"); 6408 } 6409 #endif 6410 #ifdef DEV_NETMAP 6411 if (vi->nnmrxq != 0) { 6412 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 6413 &vi->nnmrxq, 0, "# of netmap rx queues"); 6414 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 6415 &vi->nnmtxq, 0, "# of netmap tx queues"); 6416 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 6417 CTLFLAG_RD, &vi->first_nm_rxq, 0, 6418 "index of first netmap rx queue"); 6419 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 6420 CTLFLAG_RD, &vi->first_nm_txq, 0, 6421 "index of first netmap tx queue"); 6422 } 6423 #endif 6424 6425 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 6426 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 6427 "holdoff timer index"); 6428 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 6429 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 6430 "holdoff packet counter index"); 6431 6432 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 6433 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 6434 "rx queue size"); 6435 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 6436 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 6437 "tx queue size"); 6438 } 6439 6440 static void 6441 cxgbe_sysctls(struct port_info *pi) 6442 { 6443 struct sysctl_ctx_list *ctx; 6444 struct sysctl_oid *oid; 6445 struct sysctl_oid_list *children, *children2; 6446 struct adapter *sc = pi->adapter; 6447 int i; 6448 char name[16]; 6449 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"}; 6450 6451 ctx = device_get_sysctl_ctx(pi->dev); 6452 6453 /* 6454 * dev.cxgbe.X. 6455 */ 6456 oid = device_get_sysctl_tree(pi->dev); 6457 children = SYSCTL_CHILDREN(oid); 6458 6459 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 6460 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 6461 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 6462 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6463 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 6464 "PHY temperature (in Celsius)"); 6465 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 6466 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 6467 "PHY firmware version"); 6468 } 6469 6470 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 6471 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 6472 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 6473 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 6474 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 6475 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 6476 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 6477 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 6478 "autonegotiation (-1 = not supported)"); 6479 6480 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 6481 port_top_speed(pi), "max speed (in Gbps)"); 6482 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 6483 pi->mps_bg_map, "MPS buffer group map"); 6484 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 6485 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 6486 6487 if (sc->flags & IS_VF) 6488 return; 6489 6490 /* 6491 * dev.(cxgbe|cxl).X.tc. 6492 */ 6493 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 6494 "Tx scheduler traffic classes (cl_rl)"); 6495 children2 = SYSCTL_CHILDREN(oid); 6496 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 6497 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 6498 "pktsize for per-flow cl-rl (0 means up to the driver )"); 6499 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 6500 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 6501 "burstsize for per-flow cl-rl (0 means up to the driver)"); 6502 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 6503 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 6504 6505 snprintf(name, sizeof(name), "%d", i); 6506 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 6507 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 6508 "traffic class")); 6509 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 6510 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags, 6511 sysctl_bitfield_8b, "A", "flags"); 6512 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 6513 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 6514 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 6515 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 6516 sysctl_tc_params, "A", "traffic class parameters"); 6517 } 6518 6519 /* 6520 * dev.cxgbe.X.stats. 6521 */ 6522 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 6523 NULL, "port statistics"); 6524 children = SYSCTL_CHILDREN(oid); 6525 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 6526 &pi->tx_parse_error, 0, 6527 "# of tx packets with invalid length or # of segments"); 6528 6529 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 6530 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 6531 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 6532 sysctl_handle_t4_reg64, "QU", desc) 6533 6534 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 6535 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 6536 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 6537 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 6538 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 6539 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 6540 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 6541 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 6542 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 6543 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 6544 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 6545 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 6546 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 6547 "# of tx frames in this range", 6548 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 6549 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 6550 "# of tx frames in this range", 6551 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 6552 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 6553 "# of tx frames in this range", 6554 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 6555 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 6556 "# of tx frames in this range", 6557 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 6558 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 6559 "# of tx frames in this range", 6560 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 6561 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 6562 "# of tx frames in this range", 6563 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 6564 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 6565 "# of tx frames in this range", 6566 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 6567 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 6568 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 6569 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 6570 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 6571 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 6572 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 6573 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 6574 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 6575 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 6576 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 6577 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 6578 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 6579 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 6580 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 6581 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 6582 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 6583 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 6584 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 6585 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 6586 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 6587 6588 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 6589 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 6590 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 6591 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 6592 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 6593 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 6594 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 6595 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 6596 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 6597 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 6598 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 6599 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 6600 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 6601 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 6602 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 6603 "# of frames received with bad FCS", 6604 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 6605 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 6606 "# of frames received with length error", 6607 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 6608 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 6609 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 6610 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 6611 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 6612 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 6613 "# of rx frames in this range", 6614 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 6615 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 6616 "# of rx frames in this range", 6617 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 6618 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 6619 "# of rx frames in this range", 6620 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 6621 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 6622 "# of rx frames in this range", 6623 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 6624 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 6625 "# of rx frames in this range", 6626 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 6627 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 6628 "# of rx frames in this range", 6629 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 6630 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 6631 "# of rx frames in this range", 6632 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 6633 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 6634 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 6635 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 6636 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 6637 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 6638 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 6639 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 6640 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 6641 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6642 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6643 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6644 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6645 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6646 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6647 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6648 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6649 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6650 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6651 6652 #undef SYSCTL_ADD_T4_REG64 6653 6654 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6655 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6656 &pi->stats.name, desc) 6657 6658 /* We get these from port_stats and they may be stale by up to 1s */ 6659 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6660 "# drops due to buffer-group 0 overflows"); 6661 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6662 "# drops due to buffer-group 1 overflows"); 6663 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6664 "# drops due to buffer-group 2 overflows"); 6665 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6666 "# drops due to buffer-group 3 overflows"); 6667 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6668 "# of buffer-group 0 truncated packets"); 6669 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6670 "# of buffer-group 1 truncated packets"); 6671 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6672 "# of buffer-group 2 truncated packets"); 6673 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6674 "# of buffer-group 3 truncated packets"); 6675 6676 #undef SYSCTL_ADD_T4_PORTSTAT 6677 6678 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6679 CTLFLAG_RD, &pi->tx_tls_records, 6680 "# of TLS records transmitted"); 6681 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6682 CTLFLAG_RD, &pi->tx_tls_octets, 6683 "# of payload octets in transmitted TLS records"); 6684 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6685 CTLFLAG_RD, &pi->rx_tls_records, 6686 "# of TLS records received"); 6687 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6688 CTLFLAG_RD, &pi->rx_tls_octets, 6689 "# of payload octets in received TLS records"); 6690 } 6691 6692 static int 6693 sysctl_int_array(SYSCTL_HANDLER_ARGS) 6694 { 6695 int rc, *i, space = 0; 6696 struct sbuf sb; 6697 6698 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6699 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6700 if (space) 6701 sbuf_printf(&sb, " "); 6702 sbuf_printf(&sb, "%d", *i); 6703 space = 1; 6704 } 6705 rc = sbuf_finish(&sb); 6706 sbuf_delete(&sb); 6707 return (rc); 6708 } 6709 6710 static int 6711 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 6712 { 6713 int rc; 6714 struct sbuf *sb; 6715 6716 rc = sysctl_wire_old_buffer(req, 0); 6717 if (rc != 0) 6718 return(rc); 6719 6720 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6721 if (sb == NULL) 6722 return (ENOMEM); 6723 6724 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 6725 rc = sbuf_finish(sb); 6726 sbuf_delete(sb); 6727 6728 return (rc); 6729 } 6730 6731 static int 6732 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 6733 { 6734 int rc; 6735 struct sbuf *sb; 6736 6737 rc = sysctl_wire_old_buffer(req, 0); 6738 if (rc != 0) 6739 return(rc); 6740 6741 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6742 if (sb == NULL) 6743 return (ENOMEM); 6744 6745 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 6746 rc = sbuf_finish(sb); 6747 sbuf_delete(sb); 6748 6749 return (rc); 6750 } 6751 6752 static int 6753 sysctl_btphy(SYSCTL_HANDLER_ARGS) 6754 { 6755 struct port_info *pi = arg1; 6756 int op = arg2; 6757 struct adapter *sc = pi->adapter; 6758 u_int v; 6759 int rc; 6760 6761 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6762 if (rc) 6763 return (rc); 6764 /* XXX: magic numbers */ 6765 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6766 &v); 6767 end_synchronized_op(sc, 0); 6768 if (rc) 6769 return (rc); 6770 if (op == 0) 6771 v /= 256; 6772 6773 rc = sysctl_handle_int(oidp, &v, 0, req); 6774 return (rc); 6775 } 6776 6777 static int 6778 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6779 { 6780 struct vi_info *vi = arg1; 6781 int rc, val; 6782 6783 val = vi->rsrv_noflowq; 6784 rc = sysctl_handle_int(oidp, &val, 0, req); 6785 if (rc != 0 || req->newptr == NULL) 6786 return (rc); 6787 6788 if ((val >= 1) && (vi->ntxq > 1)) 6789 vi->rsrv_noflowq = 1; 6790 else 6791 vi->rsrv_noflowq = 0; 6792 6793 return (rc); 6794 } 6795 6796 static int 6797 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6798 { 6799 struct vi_info *vi = arg1; 6800 struct adapter *sc = vi->pi->adapter; 6801 int idx, rc, i; 6802 struct sge_rxq *rxq; 6803 uint8_t v; 6804 6805 idx = vi->tmr_idx; 6806 6807 rc = sysctl_handle_int(oidp, &idx, 0, req); 6808 if (rc != 0 || req->newptr == NULL) 6809 return (rc); 6810 6811 if (idx < 0 || idx >= SGE_NTIMERS) 6812 return (EINVAL); 6813 6814 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6815 "t4tmr"); 6816 if (rc) 6817 return (rc); 6818 6819 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6820 for_each_rxq(vi, i, rxq) { 6821 #ifdef atomic_store_rel_8 6822 atomic_store_rel_8(&rxq->iq.intr_params, v); 6823 #else 6824 rxq->iq.intr_params = v; 6825 #endif 6826 } 6827 vi->tmr_idx = idx; 6828 6829 end_synchronized_op(sc, LOCK_HELD); 6830 return (0); 6831 } 6832 6833 static int 6834 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6835 { 6836 struct vi_info *vi = arg1; 6837 struct adapter *sc = vi->pi->adapter; 6838 int idx, rc; 6839 6840 idx = vi->pktc_idx; 6841 6842 rc = sysctl_handle_int(oidp, &idx, 0, req); 6843 if (rc != 0 || req->newptr == NULL) 6844 return (rc); 6845 6846 if (idx < -1 || idx >= SGE_NCOUNTERS) 6847 return (EINVAL); 6848 6849 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6850 "t4pktc"); 6851 if (rc) 6852 return (rc); 6853 6854 if (vi->flags & VI_INIT_DONE) 6855 rc = EBUSY; /* cannot be changed once the queues are created */ 6856 else 6857 vi->pktc_idx = idx; 6858 6859 end_synchronized_op(sc, LOCK_HELD); 6860 return (rc); 6861 } 6862 6863 static int 6864 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6865 { 6866 struct vi_info *vi = arg1; 6867 struct adapter *sc = vi->pi->adapter; 6868 int qsize, rc; 6869 6870 qsize = vi->qsize_rxq; 6871 6872 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6873 if (rc != 0 || req->newptr == NULL) 6874 return (rc); 6875 6876 if (qsize < 128 || (qsize & 7)) 6877 return (EINVAL); 6878 6879 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6880 "t4rxqs"); 6881 if (rc) 6882 return (rc); 6883 6884 if (vi->flags & VI_INIT_DONE) 6885 rc = EBUSY; /* cannot be changed once the queues are created */ 6886 else 6887 vi->qsize_rxq = qsize; 6888 6889 end_synchronized_op(sc, LOCK_HELD); 6890 return (rc); 6891 } 6892 6893 static int 6894 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6895 { 6896 struct vi_info *vi = arg1; 6897 struct adapter *sc = vi->pi->adapter; 6898 int qsize, rc; 6899 6900 qsize = vi->qsize_txq; 6901 6902 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6903 if (rc != 0 || req->newptr == NULL) 6904 return (rc); 6905 6906 if (qsize < 128 || qsize > 65536) 6907 return (EINVAL); 6908 6909 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6910 "t4txqs"); 6911 if (rc) 6912 return (rc); 6913 6914 if (vi->flags & VI_INIT_DONE) 6915 rc = EBUSY; /* cannot be changed once the queues are created */ 6916 else 6917 vi->qsize_txq = qsize; 6918 6919 end_synchronized_op(sc, LOCK_HELD); 6920 return (rc); 6921 } 6922 6923 static int 6924 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6925 { 6926 struct port_info *pi = arg1; 6927 struct adapter *sc = pi->adapter; 6928 struct link_config *lc = &pi->link_cfg; 6929 int rc; 6930 6931 if (req->newptr == NULL) { 6932 struct sbuf *sb; 6933 static char *bits = "\20\1RX\2TX\3AUTO"; 6934 6935 rc = sysctl_wire_old_buffer(req, 0); 6936 if (rc != 0) 6937 return(rc); 6938 6939 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6940 if (sb == NULL) 6941 return (ENOMEM); 6942 6943 if (lc->link_ok) { 6944 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 6945 (lc->requested_fc & PAUSE_AUTONEG), bits); 6946 } else { 6947 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 6948 PAUSE_RX | PAUSE_AUTONEG), bits); 6949 } 6950 rc = sbuf_finish(sb); 6951 sbuf_delete(sb); 6952 } else { 6953 char s[2]; 6954 int n; 6955 6956 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 6957 PAUSE_AUTONEG)); 6958 s[1] = 0; 6959 6960 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6961 if (rc != 0) 6962 return(rc); 6963 6964 if (s[1] != 0) 6965 return (EINVAL); 6966 if (s[0] < '0' || s[0] > '9') 6967 return (EINVAL); /* not a number */ 6968 n = s[0] - '0'; 6969 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 6970 return (EINVAL); /* some other bit is set too */ 6971 6972 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6973 "t4PAUSE"); 6974 if (rc) 6975 return (rc); 6976 PORT_LOCK(pi); 6977 lc->requested_fc = n; 6978 fixup_link_config(pi); 6979 if (pi->up_vis > 0) 6980 rc = apply_link_config(pi); 6981 set_current_media(pi); 6982 PORT_UNLOCK(pi); 6983 end_synchronized_op(sc, 0); 6984 } 6985 6986 return (rc); 6987 } 6988 6989 static int 6990 sysctl_fec(SYSCTL_HANDLER_ARGS) 6991 { 6992 struct port_info *pi = arg1; 6993 struct adapter *sc = pi->adapter; 6994 struct link_config *lc = &pi->link_cfg; 6995 int rc; 6996 int8_t old; 6997 6998 if (req->newptr == NULL) { 6999 struct sbuf *sb; 7000 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO"; 7001 7002 rc = sysctl_wire_old_buffer(req, 0); 7003 if (rc != 0) 7004 return(rc); 7005 7006 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7007 if (sb == NULL) 7008 return (ENOMEM); 7009 7010 /* 7011 * Display the requested_fec when the link is down -- the actual 7012 * FEC makes sense only when the link is up. 7013 */ 7014 if (lc->link_ok) { 7015 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) | 7016 (lc->requested_fec & FEC_AUTO), bits); 7017 } else { 7018 sbuf_printf(sb, "%b", lc->requested_fec, bits); 7019 } 7020 rc = sbuf_finish(sb); 7021 sbuf_delete(sb); 7022 } else { 7023 char s[3]; 7024 int n; 7025 7026 snprintf(s, sizeof(s), "%d", 7027 lc->requested_fec == FEC_AUTO ? -1 : 7028 lc->requested_fec & M_FW_PORT_CAP32_FEC); 7029 7030 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 7031 if (rc != 0) 7032 return(rc); 7033 7034 n = strtol(&s[0], NULL, 0); 7035 if (n < 0 || n & FEC_AUTO) 7036 n = FEC_AUTO; 7037 else { 7038 if (n & ~M_FW_PORT_CAP32_FEC) 7039 return (EINVAL);/* some other bit is set too */ 7040 if (!powerof2(n)) 7041 return (EINVAL);/* one bit can be set at most */ 7042 } 7043 7044 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7045 "t4fec"); 7046 if (rc) 7047 return (rc); 7048 PORT_LOCK(pi); 7049 old = lc->requested_fec; 7050 if (n == FEC_AUTO) 7051 lc->requested_fec = FEC_AUTO; 7052 else if (n == 0) 7053 lc->requested_fec = FEC_NONE; 7054 else { 7055 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) != 7056 lc->supported) { 7057 rc = ENOTSUP; 7058 goto done; 7059 } 7060 lc->requested_fec = n; 7061 } 7062 fixup_link_config(pi); 7063 if (pi->up_vis > 0) { 7064 rc = apply_link_config(pi); 7065 if (rc != 0) { 7066 lc->requested_fec = old; 7067 if (rc == FW_EPROTO) 7068 rc = ENOTSUP; 7069 } 7070 } 7071 done: 7072 PORT_UNLOCK(pi); 7073 end_synchronized_op(sc, 0); 7074 } 7075 7076 return (rc); 7077 } 7078 7079 static int 7080 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 7081 { 7082 struct port_info *pi = arg1; 7083 struct adapter *sc = pi->adapter; 7084 struct link_config *lc = &pi->link_cfg; 7085 int rc, val; 7086 7087 if (lc->supported & FW_PORT_CAP32_ANEG) 7088 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 7089 else 7090 val = -1; 7091 rc = sysctl_handle_int(oidp, &val, 0, req); 7092 if (rc != 0 || req->newptr == NULL) 7093 return (rc); 7094 if (val == 0) 7095 val = AUTONEG_DISABLE; 7096 else if (val == 1) 7097 val = AUTONEG_ENABLE; 7098 else 7099 val = AUTONEG_AUTO; 7100 7101 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7102 "t4aneg"); 7103 if (rc) 7104 return (rc); 7105 PORT_LOCK(pi); 7106 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) { 7107 rc = ENOTSUP; 7108 goto done; 7109 } 7110 lc->requested_aneg = val; 7111 fixup_link_config(pi); 7112 if (pi->up_vis > 0) 7113 rc = apply_link_config(pi); 7114 set_current_media(pi); 7115 done: 7116 PORT_UNLOCK(pi); 7117 end_synchronized_op(sc, 0); 7118 return (rc); 7119 } 7120 7121 static int 7122 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 7123 { 7124 struct adapter *sc = arg1; 7125 int reg = arg2; 7126 uint64_t val; 7127 7128 val = t4_read_reg64(sc, reg); 7129 7130 return (sysctl_handle_64(oidp, &val, 0, req)); 7131 } 7132 7133 static int 7134 sysctl_temperature(SYSCTL_HANDLER_ARGS) 7135 { 7136 struct adapter *sc = arg1; 7137 int rc, t; 7138 uint32_t param, val; 7139 7140 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 7141 if (rc) 7142 return (rc); 7143 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7144 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7145 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 7146 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7147 end_synchronized_op(sc, 0); 7148 if (rc) 7149 return (rc); 7150 7151 /* unknown is returned as 0 but we display -1 in that case */ 7152 t = val == 0 ? -1 : val; 7153 7154 rc = sysctl_handle_int(oidp, &t, 0, req); 7155 return (rc); 7156 } 7157 7158 static int 7159 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 7160 { 7161 struct adapter *sc = arg1; 7162 struct sbuf *sb; 7163 int rc; 7164 uint32_t param, val; 7165 7166 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 7167 if (rc) 7168 return (rc); 7169 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7170 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 7171 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7172 end_synchronized_op(sc, 0); 7173 if (rc) 7174 return (rc); 7175 7176 rc = sysctl_wire_old_buffer(req, 0); 7177 if (rc != 0) 7178 return (rc); 7179 7180 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7181 if (sb == NULL) 7182 return (ENOMEM); 7183 7184 if (val == 0xffffffff) { 7185 /* Only debug and custom firmwares report load averages. */ 7186 sbuf_printf(sb, "not available"); 7187 } else { 7188 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 7189 (val >> 16) & 0xff); 7190 } 7191 rc = sbuf_finish(sb); 7192 sbuf_delete(sb); 7193 7194 return (rc); 7195 } 7196 7197 static int 7198 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 7199 { 7200 struct adapter *sc = arg1; 7201 struct sbuf *sb; 7202 int rc, i; 7203 uint16_t incr[NMTUS][NCCTRL_WIN]; 7204 static const char *dec_fac[] = { 7205 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 7206 "0.9375" 7207 }; 7208 7209 rc = sysctl_wire_old_buffer(req, 0); 7210 if (rc != 0) 7211 return (rc); 7212 7213 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7214 if (sb == NULL) 7215 return (ENOMEM); 7216 7217 t4_read_cong_tbl(sc, incr); 7218 7219 for (i = 0; i < NCCTRL_WIN; ++i) { 7220 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 7221 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 7222 incr[5][i], incr[6][i], incr[7][i]); 7223 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 7224 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 7225 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 7226 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 7227 } 7228 7229 rc = sbuf_finish(sb); 7230 sbuf_delete(sb); 7231 7232 return (rc); 7233 } 7234 7235 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 7236 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 7237 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 7238 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 7239 }; 7240 7241 static int 7242 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 7243 { 7244 struct adapter *sc = arg1; 7245 struct sbuf *sb; 7246 int rc, i, n, qid = arg2; 7247 uint32_t *buf, *p; 7248 char *qtype; 7249 u_int cim_num_obq = sc->chip_params->cim_num_obq; 7250 7251 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 7252 ("%s: bad qid %d\n", __func__, qid)); 7253 7254 if (qid < CIM_NUM_IBQ) { 7255 /* inbound queue */ 7256 qtype = "IBQ"; 7257 n = 4 * CIM_IBQ_SIZE; 7258 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7259 rc = t4_read_cim_ibq(sc, qid, buf, n); 7260 } else { 7261 /* outbound queue */ 7262 qtype = "OBQ"; 7263 qid -= CIM_NUM_IBQ; 7264 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 7265 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7266 rc = t4_read_cim_obq(sc, qid, buf, n); 7267 } 7268 7269 if (rc < 0) { 7270 rc = -rc; 7271 goto done; 7272 } 7273 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 7274 7275 rc = sysctl_wire_old_buffer(req, 0); 7276 if (rc != 0) 7277 goto done; 7278 7279 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7280 if (sb == NULL) { 7281 rc = ENOMEM; 7282 goto done; 7283 } 7284 7285 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 7286 for (i = 0, p = buf; i < n; i += 16, p += 4) 7287 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 7288 p[2], p[3]); 7289 7290 rc = sbuf_finish(sb); 7291 sbuf_delete(sb); 7292 done: 7293 free(buf, M_CXGBE); 7294 return (rc); 7295 } 7296 7297 static void 7298 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7299 { 7300 uint32_t *p; 7301 7302 sbuf_printf(sb, "Status Data PC%s", 7303 cfg & F_UPDBGLACAPTPCONLY ? "" : 7304 " LS0Stat LS0Addr LS0Data"); 7305 7306 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 7307 if (cfg & F_UPDBGLACAPTPCONLY) { 7308 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 7309 p[6], p[7]); 7310 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 7311 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 7312 p[4] & 0xff, p[5] >> 8); 7313 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 7314 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7315 p[1] & 0xf, p[2] >> 4); 7316 } else { 7317 sbuf_printf(sb, 7318 "\n %02x %x%07x %x%07x %08x %08x " 7319 "%08x%08x%08x%08x", 7320 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7321 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 7322 p[6], p[7]); 7323 } 7324 } 7325 } 7326 7327 static void 7328 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7329 { 7330 uint32_t *p; 7331 7332 sbuf_printf(sb, "Status Inst Data PC%s", 7333 cfg & F_UPDBGLACAPTPCONLY ? "" : 7334 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 7335 7336 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 7337 if (cfg & F_UPDBGLACAPTPCONLY) { 7338 sbuf_printf(sb, "\n %02x %08x %08x %08x", 7339 p[3] & 0xff, p[2], p[1], p[0]); 7340 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 7341 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 7342 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 7343 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 7344 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 7345 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 7346 p[6] >> 16); 7347 } else { 7348 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 7349 "%08x %08x %08x %08x %08x %08x", 7350 (p[9] >> 16) & 0xff, 7351 p[9] & 0xffff, p[8] >> 16, 7352 p[8] & 0xffff, p[7] >> 16, 7353 p[7] & 0xffff, p[6] >> 16, 7354 p[2], p[1], p[0], p[5], p[4], p[3]); 7355 } 7356 } 7357 } 7358 7359 static int 7360 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 7361 { 7362 uint32_t cfg, *buf; 7363 int rc; 7364 7365 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7366 if (rc != 0) 7367 return (rc); 7368 7369 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7370 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7371 M_ZERO | flags); 7372 if (buf == NULL) 7373 return (ENOMEM); 7374 7375 rc = -t4_cim_read_la(sc, buf, NULL); 7376 if (rc != 0) 7377 goto done; 7378 if (chip_id(sc) < CHELSIO_T6) 7379 sbuf_cim_la4(sc, sb, buf, cfg); 7380 else 7381 sbuf_cim_la6(sc, sb, buf, cfg); 7382 7383 done: 7384 free(buf, M_CXGBE); 7385 return (rc); 7386 } 7387 7388 static int 7389 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 7390 { 7391 struct adapter *sc = arg1; 7392 struct sbuf *sb; 7393 int rc; 7394 7395 rc = sysctl_wire_old_buffer(req, 0); 7396 if (rc != 0) 7397 return (rc); 7398 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7399 if (sb == NULL) 7400 return (ENOMEM); 7401 7402 rc = sbuf_cim_la(sc, sb, M_WAITOK); 7403 if (rc == 0) 7404 rc = sbuf_finish(sb); 7405 sbuf_delete(sb); 7406 return (rc); 7407 } 7408 7409 bool 7410 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose) 7411 { 7412 struct sbuf sb; 7413 int rc; 7414 7415 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7416 return (false); 7417 rc = sbuf_cim_la(sc, &sb, M_NOWAIT); 7418 if (rc == 0) { 7419 rc = sbuf_finish(&sb); 7420 if (rc == 0) { 7421 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s", 7422 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7423 } 7424 } 7425 sbuf_delete(&sb); 7426 return (false); 7427 } 7428 7429 static int 7430 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 7431 { 7432 struct adapter *sc = arg1; 7433 u_int i; 7434 struct sbuf *sb; 7435 uint32_t *buf, *p; 7436 int rc; 7437 7438 rc = sysctl_wire_old_buffer(req, 0); 7439 if (rc != 0) 7440 return (rc); 7441 7442 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7443 if (sb == NULL) 7444 return (ENOMEM); 7445 7446 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 7447 M_ZERO | M_WAITOK); 7448 7449 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 7450 p = buf; 7451 7452 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7453 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 7454 p[1], p[0]); 7455 } 7456 7457 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 7458 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7459 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 7460 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 7461 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 7462 (p[1] >> 2) | ((p[2] & 3) << 30), 7463 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 7464 p[0] & 1); 7465 } 7466 7467 rc = sbuf_finish(sb); 7468 sbuf_delete(sb); 7469 free(buf, M_CXGBE); 7470 return (rc); 7471 } 7472 7473 static int 7474 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 7475 { 7476 struct adapter *sc = arg1; 7477 u_int i; 7478 struct sbuf *sb; 7479 uint32_t *buf, *p; 7480 int rc; 7481 7482 rc = sysctl_wire_old_buffer(req, 0); 7483 if (rc != 0) 7484 return (rc); 7485 7486 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7487 if (sb == NULL) 7488 return (ENOMEM); 7489 7490 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 7491 M_ZERO | M_WAITOK); 7492 7493 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 7494 p = buf; 7495 7496 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 7497 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7498 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 7499 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 7500 p[4], p[3], p[2], p[1], p[0]); 7501 } 7502 7503 sbuf_printf(sb, "\n\nCntl ID Data"); 7504 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7505 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 7506 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 7507 } 7508 7509 rc = sbuf_finish(sb); 7510 sbuf_delete(sb); 7511 free(buf, M_CXGBE); 7512 return (rc); 7513 } 7514 7515 static int 7516 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 7517 { 7518 struct adapter *sc = arg1; 7519 struct sbuf *sb; 7520 int rc, i; 7521 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7522 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7523 uint16_t thres[CIM_NUM_IBQ]; 7524 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 7525 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 7526 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 7527 7528 cim_num_obq = sc->chip_params->cim_num_obq; 7529 if (is_t4(sc)) { 7530 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 7531 obq_rdaddr = A_UP_OBQ_0_REALADDR; 7532 } else { 7533 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 7534 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 7535 } 7536 nq = CIM_NUM_IBQ + cim_num_obq; 7537 7538 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 7539 if (rc == 0) 7540 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 7541 if (rc != 0) 7542 return (rc); 7543 7544 t4_read_cimq_cfg(sc, base, size, thres); 7545 7546 rc = sysctl_wire_old_buffer(req, 0); 7547 if (rc != 0) 7548 return (rc); 7549 7550 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7551 if (sb == NULL) 7552 return (ENOMEM); 7553 7554 sbuf_printf(sb, 7555 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 7556 7557 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 7558 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 7559 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 7560 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7561 G_QUEREMFLITS(p[2]) * 16); 7562 for ( ; i < nq; i++, p += 4, wr += 2) 7563 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 7564 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 7565 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7566 G_QUEREMFLITS(p[2]) * 16); 7567 7568 rc = sbuf_finish(sb); 7569 sbuf_delete(sb); 7570 7571 return (rc); 7572 } 7573 7574 static int 7575 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 7576 { 7577 struct adapter *sc = arg1; 7578 struct sbuf *sb; 7579 int rc; 7580 struct tp_cpl_stats stats; 7581 7582 rc = sysctl_wire_old_buffer(req, 0); 7583 if (rc != 0) 7584 return (rc); 7585 7586 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7587 if (sb == NULL) 7588 return (ENOMEM); 7589 7590 mtx_lock(&sc->reg_lock); 7591 t4_tp_get_cpl_stats(sc, &stats, 0); 7592 mtx_unlock(&sc->reg_lock); 7593 7594 if (sc->chip_params->nchan > 2) { 7595 sbuf_printf(sb, " channel 0 channel 1" 7596 " channel 2 channel 3"); 7597 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 7598 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 7599 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 7600 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 7601 } else { 7602 sbuf_printf(sb, " channel 0 channel 1"); 7603 sbuf_printf(sb, "\nCPL requests: %10u %10u", 7604 stats.req[0], stats.req[1]); 7605 sbuf_printf(sb, "\nCPL responses: %10u %10u", 7606 stats.rsp[0], stats.rsp[1]); 7607 } 7608 7609 rc = sbuf_finish(sb); 7610 sbuf_delete(sb); 7611 7612 return (rc); 7613 } 7614 7615 static int 7616 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 7617 { 7618 struct adapter *sc = arg1; 7619 struct sbuf *sb; 7620 int rc; 7621 struct tp_usm_stats stats; 7622 7623 rc = sysctl_wire_old_buffer(req, 0); 7624 if (rc != 0) 7625 return(rc); 7626 7627 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7628 if (sb == NULL) 7629 return (ENOMEM); 7630 7631 t4_get_usm_stats(sc, &stats, 1); 7632 7633 sbuf_printf(sb, "Frames: %u\n", stats.frames); 7634 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 7635 sbuf_printf(sb, "Drops: %u", stats.drops); 7636 7637 rc = sbuf_finish(sb); 7638 sbuf_delete(sb); 7639 7640 return (rc); 7641 } 7642 7643 static const char * const devlog_level_strings[] = { 7644 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 7645 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 7646 [FW_DEVLOG_LEVEL_ERR] = "ERR", 7647 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 7648 [FW_DEVLOG_LEVEL_INFO] = "INFO", 7649 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 7650 }; 7651 7652 static const char * const devlog_facility_strings[] = { 7653 [FW_DEVLOG_FACILITY_CORE] = "CORE", 7654 [FW_DEVLOG_FACILITY_CF] = "CF", 7655 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 7656 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 7657 [FW_DEVLOG_FACILITY_RES] = "RES", 7658 [FW_DEVLOG_FACILITY_HW] = "HW", 7659 [FW_DEVLOG_FACILITY_FLR] = "FLR", 7660 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 7661 [FW_DEVLOG_FACILITY_PHY] = "PHY", 7662 [FW_DEVLOG_FACILITY_MAC] = "MAC", 7663 [FW_DEVLOG_FACILITY_PORT] = "PORT", 7664 [FW_DEVLOG_FACILITY_VI] = "VI", 7665 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 7666 [FW_DEVLOG_FACILITY_ACL] = "ACL", 7667 [FW_DEVLOG_FACILITY_TM] = "TM", 7668 [FW_DEVLOG_FACILITY_QFC] = "QFC", 7669 [FW_DEVLOG_FACILITY_DCB] = "DCB", 7670 [FW_DEVLOG_FACILITY_ETH] = "ETH", 7671 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 7672 [FW_DEVLOG_FACILITY_RI] = "RI", 7673 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 7674 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 7675 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 7676 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 7677 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 7678 }; 7679 7680 static int 7681 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 7682 { 7683 int i, j, rc, nentries, first = 0; 7684 struct devlog_params *dparams = &sc->params.devlog; 7685 struct fw_devlog_e *buf, *e; 7686 uint64_t ftstamp = UINT64_MAX; 7687 7688 if (dparams->addr == 0) 7689 return (ENXIO); 7690 7691 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7692 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 7693 if (buf == NULL) 7694 return (ENOMEM); 7695 7696 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 7697 if (rc != 0) 7698 goto done; 7699 7700 nentries = dparams->size / sizeof(struct fw_devlog_e); 7701 for (i = 0; i < nentries; i++) { 7702 e = &buf[i]; 7703 7704 if (e->timestamp == 0) 7705 break; /* end */ 7706 7707 e->timestamp = be64toh(e->timestamp); 7708 e->seqno = be32toh(e->seqno); 7709 for (j = 0; j < 8; j++) 7710 e->params[j] = be32toh(e->params[j]); 7711 7712 if (e->timestamp < ftstamp) { 7713 ftstamp = e->timestamp; 7714 first = i; 7715 } 7716 } 7717 7718 if (buf[first].timestamp == 0) 7719 goto done; /* nothing in the log */ 7720 7721 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 7722 "Seq#", "Tstamp", "Level", "Facility", "Message"); 7723 7724 i = first; 7725 do { 7726 e = &buf[i]; 7727 if (e->timestamp == 0) 7728 break; /* end */ 7729 7730 sbuf_printf(sb, "%10d %15ju %8s %8s ", 7731 e->seqno, e->timestamp, 7732 (e->level < nitems(devlog_level_strings) ? 7733 devlog_level_strings[e->level] : "UNKNOWN"), 7734 (e->facility < nitems(devlog_facility_strings) ? 7735 devlog_facility_strings[e->facility] : "UNKNOWN")); 7736 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7737 e->params[2], e->params[3], e->params[4], 7738 e->params[5], e->params[6], e->params[7]); 7739 7740 if (++i == nentries) 7741 i = 0; 7742 } while (i != first); 7743 done: 7744 free(buf, M_CXGBE); 7745 return (rc); 7746 } 7747 7748 static int 7749 sysctl_devlog(SYSCTL_HANDLER_ARGS) 7750 { 7751 struct adapter *sc = arg1; 7752 int rc; 7753 struct sbuf *sb; 7754 7755 rc = sysctl_wire_old_buffer(req, 0); 7756 if (rc != 0) 7757 return (rc); 7758 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7759 if (sb == NULL) 7760 return (ENOMEM); 7761 7762 rc = sbuf_devlog(sc, sb, M_WAITOK); 7763 if (rc == 0) 7764 rc = sbuf_finish(sb); 7765 sbuf_delete(sb); 7766 return (rc); 7767 } 7768 7769 void 7770 t4_os_dump_devlog(struct adapter *sc) 7771 { 7772 int rc; 7773 struct sbuf sb; 7774 7775 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7776 return; 7777 rc = sbuf_devlog(sc, &sb, M_NOWAIT); 7778 if (rc == 0) { 7779 rc = sbuf_finish(&sb); 7780 if (rc == 0) { 7781 log(LOG_DEBUG, "%s: device log follows.\n%s", 7782 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7783 } 7784 } 7785 sbuf_delete(&sb); 7786 } 7787 7788 static int 7789 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7790 { 7791 struct adapter *sc = arg1; 7792 struct sbuf *sb; 7793 int rc; 7794 struct tp_fcoe_stats stats[MAX_NCHAN]; 7795 int i, nchan = sc->chip_params->nchan; 7796 7797 rc = sysctl_wire_old_buffer(req, 0); 7798 if (rc != 0) 7799 return (rc); 7800 7801 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7802 if (sb == NULL) 7803 return (ENOMEM); 7804 7805 for (i = 0; i < nchan; i++) 7806 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7807 7808 if (nchan > 2) { 7809 sbuf_printf(sb, " channel 0 channel 1" 7810 " channel 2 channel 3"); 7811 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7812 stats[0].octets_ddp, stats[1].octets_ddp, 7813 stats[2].octets_ddp, stats[3].octets_ddp); 7814 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7815 stats[0].frames_ddp, stats[1].frames_ddp, 7816 stats[2].frames_ddp, stats[3].frames_ddp); 7817 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7818 stats[0].frames_drop, stats[1].frames_drop, 7819 stats[2].frames_drop, stats[3].frames_drop); 7820 } else { 7821 sbuf_printf(sb, " channel 0 channel 1"); 7822 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7823 stats[0].octets_ddp, stats[1].octets_ddp); 7824 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7825 stats[0].frames_ddp, stats[1].frames_ddp); 7826 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7827 stats[0].frames_drop, stats[1].frames_drop); 7828 } 7829 7830 rc = sbuf_finish(sb); 7831 sbuf_delete(sb); 7832 7833 return (rc); 7834 } 7835 7836 static int 7837 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7838 { 7839 struct adapter *sc = arg1; 7840 struct sbuf *sb; 7841 int rc, i; 7842 unsigned int map, kbps, ipg, mode; 7843 unsigned int pace_tab[NTX_SCHED]; 7844 7845 rc = sysctl_wire_old_buffer(req, 0); 7846 if (rc != 0) 7847 return (rc); 7848 7849 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7850 if (sb == NULL) 7851 return (ENOMEM); 7852 7853 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7854 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7855 t4_read_pace_tbl(sc, pace_tab); 7856 7857 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7858 "Class IPG (0.1 ns) Flow IPG (us)"); 7859 7860 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7861 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7862 sbuf_printf(sb, "\n %u %-5s %u ", i, 7863 (mode & (1 << i)) ? "flow" : "class", map & 3); 7864 if (kbps) 7865 sbuf_printf(sb, "%9u ", kbps); 7866 else 7867 sbuf_printf(sb, " disabled "); 7868 7869 if (ipg) 7870 sbuf_printf(sb, "%13u ", ipg); 7871 else 7872 sbuf_printf(sb, " disabled "); 7873 7874 if (pace_tab[i]) 7875 sbuf_printf(sb, "%10u", pace_tab[i]); 7876 else 7877 sbuf_printf(sb, " disabled"); 7878 } 7879 7880 rc = sbuf_finish(sb); 7881 sbuf_delete(sb); 7882 7883 return (rc); 7884 } 7885 7886 static int 7887 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7888 { 7889 struct adapter *sc = arg1; 7890 struct sbuf *sb; 7891 int rc, i, j; 7892 uint64_t *p0, *p1; 7893 struct lb_port_stats s[2]; 7894 static const char *stat_name[] = { 7895 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7896 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7897 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7898 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7899 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7900 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7901 "BG2FramesTrunc:", "BG3FramesTrunc:" 7902 }; 7903 7904 rc = sysctl_wire_old_buffer(req, 0); 7905 if (rc != 0) 7906 return (rc); 7907 7908 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7909 if (sb == NULL) 7910 return (ENOMEM); 7911 7912 memset(s, 0, sizeof(s)); 7913 7914 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7915 t4_get_lb_stats(sc, i, &s[0]); 7916 t4_get_lb_stats(sc, i + 1, &s[1]); 7917 7918 p0 = &s[0].octets; 7919 p1 = &s[1].octets; 7920 sbuf_printf(sb, "%s Loopback %u" 7921 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7922 7923 for (j = 0; j < nitems(stat_name); j++) 7924 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7925 *p0++, *p1++); 7926 } 7927 7928 rc = sbuf_finish(sb); 7929 sbuf_delete(sb); 7930 7931 return (rc); 7932 } 7933 7934 static int 7935 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7936 { 7937 int rc = 0; 7938 struct port_info *pi = arg1; 7939 struct link_config *lc = &pi->link_cfg; 7940 struct sbuf *sb; 7941 7942 rc = sysctl_wire_old_buffer(req, 0); 7943 if (rc != 0) 7944 return(rc); 7945 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7946 if (sb == NULL) 7947 return (ENOMEM); 7948 7949 if (lc->link_ok || lc->link_down_rc == 255) 7950 sbuf_printf(sb, "n/a"); 7951 else 7952 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7953 7954 rc = sbuf_finish(sb); 7955 sbuf_delete(sb); 7956 7957 return (rc); 7958 } 7959 7960 struct mem_desc { 7961 unsigned int base; 7962 unsigned int limit; 7963 unsigned int idx; 7964 }; 7965 7966 static int 7967 mem_desc_cmp(const void *a, const void *b) 7968 { 7969 return ((const struct mem_desc *)a)->base - 7970 ((const struct mem_desc *)b)->base; 7971 } 7972 7973 static void 7974 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7975 unsigned int to) 7976 { 7977 unsigned int size; 7978 7979 if (from == to) 7980 return; 7981 7982 size = to - from + 1; 7983 if (size == 0) 7984 return; 7985 7986 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7987 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7988 } 7989 7990 static int 7991 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7992 { 7993 struct adapter *sc = arg1; 7994 struct sbuf *sb; 7995 int rc, i, n; 7996 uint32_t lo, hi, used, alloc; 7997 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 7998 static const char *region[] = { 7999 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 8000 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 8001 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 8002 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 8003 "RQUDP region:", "PBL region:", "TXPBL region:", 8004 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 8005 "On-chip queues:", "TLS keys:", 8006 }; 8007 struct mem_desc avail[4]; 8008 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 8009 struct mem_desc *md = mem; 8010 8011 rc = sysctl_wire_old_buffer(req, 0); 8012 if (rc != 0) 8013 return (rc); 8014 8015 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8016 if (sb == NULL) 8017 return (ENOMEM); 8018 8019 for (i = 0; i < nitems(mem); i++) { 8020 mem[i].limit = 0; 8021 mem[i].idx = i; 8022 } 8023 8024 /* Find and sort the populated memory ranges */ 8025 i = 0; 8026 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 8027 if (lo & F_EDRAM0_ENABLE) { 8028 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 8029 avail[i].base = G_EDRAM0_BASE(hi) << 20; 8030 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 8031 avail[i].idx = 0; 8032 i++; 8033 } 8034 if (lo & F_EDRAM1_ENABLE) { 8035 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 8036 avail[i].base = G_EDRAM1_BASE(hi) << 20; 8037 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 8038 avail[i].idx = 1; 8039 i++; 8040 } 8041 if (lo & F_EXT_MEM_ENABLE) { 8042 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 8043 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 8044 avail[i].limit = avail[i].base + 8045 (G_EXT_MEM_SIZE(hi) << 20); 8046 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 8047 i++; 8048 } 8049 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 8050 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 8051 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 8052 avail[i].limit = avail[i].base + 8053 (G_EXT_MEM1_SIZE(hi) << 20); 8054 avail[i].idx = 4; 8055 i++; 8056 } 8057 if (!i) /* no memory available */ 8058 return 0; 8059 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 8060 8061 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 8062 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 8063 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 8064 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 8065 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 8066 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 8067 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 8068 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 8069 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 8070 8071 /* the next few have explicit upper bounds */ 8072 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 8073 md->limit = md->base - 1 + 8074 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 8075 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 8076 md++; 8077 8078 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 8079 md->limit = md->base - 1 + 8080 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 8081 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 8082 md++; 8083 8084 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8085 if (chip_id(sc) <= CHELSIO_T5) 8086 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 8087 else 8088 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 8089 md->limit = 0; 8090 } else { 8091 md->base = 0; 8092 md->idx = nitems(region); /* hide it */ 8093 } 8094 md++; 8095 8096 #define ulp_region(reg) \ 8097 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 8098 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 8099 8100 ulp_region(RX_ISCSI); 8101 ulp_region(RX_TDDP); 8102 ulp_region(TX_TPT); 8103 ulp_region(RX_STAG); 8104 ulp_region(RX_RQ); 8105 ulp_region(RX_RQUDP); 8106 ulp_region(RX_PBL); 8107 ulp_region(TX_PBL); 8108 #undef ulp_region 8109 8110 md->base = 0; 8111 md->idx = nitems(region); 8112 if (!is_t4(sc)) { 8113 uint32_t size = 0; 8114 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 8115 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 8116 8117 if (is_t5(sc)) { 8118 if (sge_ctrl & F_VFIFO_ENABLE) 8119 size = G_DBVFIFO_SIZE(fifo_size); 8120 } else 8121 size = G_T6_DBVFIFO_SIZE(fifo_size); 8122 8123 if (size) { 8124 md->base = G_BASEADDR(t4_read_reg(sc, 8125 A_SGE_DBVFIFO_BADDR)); 8126 md->limit = md->base + (size << 2) - 1; 8127 } 8128 } 8129 md++; 8130 8131 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 8132 md->limit = 0; 8133 md++; 8134 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 8135 md->limit = 0; 8136 md++; 8137 8138 md->base = sc->vres.ocq.start; 8139 if (sc->vres.ocq.size) 8140 md->limit = md->base + sc->vres.ocq.size - 1; 8141 else 8142 md->idx = nitems(region); /* hide it */ 8143 md++; 8144 8145 md->base = sc->vres.key.start; 8146 if (sc->vres.key.size) 8147 md->limit = md->base + sc->vres.key.size - 1; 8148 else 8149 md->idx = nitems(region); /* hide it */ 8150 md++; 8151 8152 /* add any address-space holes, there can be up to 3 */ 8153 for (n = 0; n < i - 1; n++) 8154 if (avail[n].limit < avail[n + 1].base) 8155 (md++)->base = avail[n].limit; 8156 if (avail[n].limit) 8157 (md++)->base = avail[n].limit; 8158 8159 n = md - mem; 8160 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 8161 8162 for (lo = 0; lo < i; lo++) 8163 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 8164 avail[lo].limit - 1); 8165 8166 sbuf_printf(sb, "\n"); 8167 for (i = 0; i < n; i++) { 8168 if (mem[i].idx >= nitems(region)) 8169 continue; /* skip holes */ 8170 if (!mem[i].limit) 8171 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 8172 mem_region_show(sb, region[mem[i].idx], mem[i].base, 8173 mem[i].limit); 8174 } 8175 8176 sbuf_printf(sb, "\n"); 8177 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 8178 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 8179 mem_region_show(sb, "uP RAM:", lo, hi); 8180 8181 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 8182 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 8183 mem_region_show(sb, "uP Extmem2:", lo, hi); 8184 8185 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 8186 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 8187 G_PMRXMAXPAGE(lo), 8188 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 8189 (lo & F_PMRXNUMCHN) ? 2 : 1); 8190 8191 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 8192 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 8193 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 8194 G_PMTXMAXPAGE(lo), 8195 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 8196 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 8197 sbuf_printf(sb, "%u p-structs\n", 8198 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 8199 8200 for (i = 0; i < 4; i++) { 8201 if (chip_id(sc) > CHELSIO_T5) 8202 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 8203 else 8204 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 8205 if (is_t5(sc)) { 8206 used = G_T5_USED(lo); 8207 alloc = G_T5_ALLOC(lo); 8208 } else { 8209 used = G_USED(lo); 8210 alloc = G_ALLOC(lo); 8211 } 8212 /* For T6 these are MAC buffer groups */ 8213 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 8214 i, used, alloc); 8215 } 8216 for (i = 0; i < sc->chip_params->nchan; i++) { 8217 if (chip_id(sc) > CHELSIO_T5) 8218 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 8219 else 8220 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 8221 if (is_t5(sc)) { 8222 used = G_T5_USED(lo); 8223 alloc = G_T5_ALLOC(lo); 8224 } else { 8225 used = G_USED(lo); 8226 alloc = G_ALLOC(lo); 8227 } 8228 /* For T6 these are MAC buffer groups */ 8229 sbuf_printf(sb, 8230 "\nLoopback %d using %u pages out of %u allocated", 8231 i, used, alloc); 8232 } 8233 8234 rc = sbuf_finish(sb); 8235 sbuf_delete(sb); 8236 8237 return (rc); 8238 } 8239 8240 static inline void 8241 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 8242 { 8243 *mask = x | y; 8244 y = htobe64(y); 8245 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 8246 } 8247 8248 static int 8249 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 8250 { 8251 struct adapter *sc = arg1; 8252 struct sbuf *sb; 8253 int rc, i; 8254 8255 MPASS(chip_id(sc) <= CHELSIO_T5); 8256 8257 rc = sysctl_wire_old_buffer(req, 0); 8258 if (rc != 0) 8259 return (rc); 8260 8261 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8262 if (sb == NULL) 8263 return (ENOMEM); 8264 8265 sbuf_printf(sb, 8266 "Idx Ethernet address Mask Vld Ports PF" 8267 " VF Replication P0 P1 P2 P3 ML"); 8268 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8269 uint64_t tcamx, tcamy, mask; 8270 uint32_t cls_lo, cls_hi; 8271 uint8_t addr[ETHER_ADDR_LEN]; 8272 8273 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 8274 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 8275 if (tcamx & tcamy) 8276 continue; 8277 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8278 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8279 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8280 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 8281 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 8282 addr[3], addr[4], addr[5], (uintmax_t)mask, 8283 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 8284 G_PORTMAP(cls_hi), G_PF(cls_lo), 8285 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 8286 8287 if (cls_lo & F_REPLICATE) { 8288 struct fw_ldst_cmd ldst_cmd; 8289 8290 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8291 ldst_cmd.op_to_addrspace = 8292 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8293 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8294 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8295 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8296 ldst_cmd.u.mps.rplc.fid_idx = 8297 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8298 V_FW_LDST_CMD_IDX(i)); 8299 8300 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8301 "t4mps"); 8302 if (rc) 8303 break; 8304 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8305 sizeof(ldst_cmd), &ldst_cmd); 8306 end_synchronized_op(sc, 0); 8307 8308 if (rc != 0) { 8309 sbuf_printf(sb, "%36d", rc); 8310 rc = 0; 8311 } else { 8312 sbuf_printf(sb, " %08x %08x %08x %08x", 8313 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8314 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8315 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8316 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8317 } 8318 } else 8319 sbuf_printf(sb, "%36s", ""); 8320 8321 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 8322 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 8323 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 8324 } 8325 8326 if (rc) 8327 (void) sbuf_finish(sb); 8328 else 8329 rc = sbuf_finish(sb); 8330 sbuf_delete(sb); 8331 8332 return (rc); 8333 } 8334 8335 static int 8336 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 8337 { 8338 struct adapter *sc = arg1; 8339 struct sbuf *sb; 8340 int rc, i; 8341 8342 MPASS(chip_id(sc) > CHELSIO_T5); 8343 8344 rc = sysctl_wire_old_buffer(req, 0); 8345 if (rc != 0) 8346 return (rc); 8347 8348 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8349 if (sb == NULL) 8350 return (ENOMEM); 8351 8352 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 8353 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 8354 " Replication" 8355 " P0 P1 P2 P3 ML\n"); 8356 8357 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8358 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 8359 uint16_t ivlan; 8360 uint64_t tcamx, tcamy, val, mask; 8361 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 8362 uint8_t addr[ETHER_ADDR_LEN]; 8363 8364 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 8365 if (i < 256) 8366 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 8367 else 8368 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 8369 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8370 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8371 tcamy = G_DMACH(val) << 32; 8372 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8373 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8374 lookup_type = G_DATALKPTYPE(data2); 8375 port_num = G_DATAPORTNUM(data2); 8376 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8377 /* Inner header VNI */ 8378 vniy = ((data2 & F_DATAVIDH2) << 23) | 8379 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8380 dip_hit = data2 & F_DATADIPHIT; 8381 vlan_vld = 0; 8382 } else { 8383 vniy = 0; 8384 dip_hit = 0; 8385 vlan_vld = data2 & F_DATAVIDH2; 8386 ivlan = G_VIDL(val); 8387 } 8388 8389 ctl |= V_CTLXYBITSEL(1); 8390 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8391 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8392 tcamx = G_DMACH(val) << 32; 8393 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8394 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8395 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8396 /* Inner header VNI mask */ 8397 vnix = ((data2 & F_DATAVIDH2) << 23) | 8398 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8399 } else 8400 vnix = 0; 8401 8402 if (tcamx & tcamy) 8403 continue; 8404 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8405 8406 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8407 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8408 8409 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8410 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8411 "%012jx %06x %06x - - %3c" 8412 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 8413 addr[1], addr[2], addr[3], addr[4], addr[5], 8414 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 8415 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8416 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8417 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8418 } else { 8419 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8420 "%012jx - - ", i, addr[0], addr[1], 8421 addr[2], addr[3], addr[4], addr[5], 8422 (uintmax_t)mask); 8423 8424 if (vlan_vld) 8425 sbuf_printf(sb, "%4u Y ", ivlan); 8426 else 8427 sbuf_printf(sb, " - N "); 8428 8429 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 8430 lookup_type ? 'I' : 'O', port_num, 8431 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8432 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8433 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8434 } 8435 8436 8437 if (cls_lo & F_T6_REPLICATE) { 8438 struct fw_ldst_cmd ldst_cmd; 8439 8440 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8441 ldst_cmd.op_to_addrspace = 8442 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8443 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8444 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8445 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8446 ldst_cmd.u.mps.rplc.fid_idx = 8447 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8448 V_FW_LDST_CMD_IDX(i)); 8449 8450 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8451 "t6mps"); 8452 if (rc) 8453 break; 8454 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8455 sizeof(ldst_cmd), &ldst_cmd); 8456 end_synchronized_op(sc, 0); 8457 8458 if (rc != 0) { 8459 sbuf_printf(sb, "%72d", rc); 8460 rc = 0; 8461 } else { 8462 sbuf_printf(sb, " %08x %08x %08x %08x" 8463 " %08x %08x %08x %08x", 8464 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 8465 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 8466 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 8467 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 8468 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8469 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8470 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8471 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8472 } 8473 } else 8474 sbuf_printf(sb, "%72s", ""); 8475 8476 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 8477 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 8478 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 8479 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 8480 } 8481 8482 if (rc) 8483 (void) sbuf_finish(sb); 8484 else 8485 rc = sbuf_finish(sb); 8486 sbuf_delete(sb); 8487 8488 return (rc); 8489 } 8490 8491 static int 8492 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 8493 { 8494 struct adapter *sc = arg1; 8495 struct sbuf *sb; 8496 int rc; 8497 uint16_t mtus[NMTUS]; 8498 8499 rc = sysctl_wire_old_buffer(req, 0); 8500 if (rc != 0) 8501 return (rc); 8502 8503 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8504 if (sb == NULL) 8505 return (ENOMEM); 8506 8507 t4_read_mtu_tbl(sc, mtus, NULL); 8508 8509 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 8510 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 8511 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 8512 mtus[14], mtus[15]); 8513 8514 rc = sbuf_finish(sb); 8515 sbuf_delete(sb); 8516 8517 return (rc); 8518 } 8519 8520 static int 8521 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 8522 { 8523 struct adapter *sc = arg1; 8524 struct sbuf *sb; 8525 int rc, i; 8526 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 8527 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 8528 static const char *tx_stats[MAX_PM_NSTATS] = { 8529 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 8530 "Tx FIFO wait", NULL, "Tx latency" 8531 }; 8532 static const char *rx_stats[MAX_PM_NSTATS] = { 8533 "Read:", "Write bypass:", "Write mem:", "Flush:", 8534 "Rx FIFO wait", NULL, "Rx latency" 8535 }; 8536 8537 rc = sysctl_wire_old_buffer(req, 0); 8538 if (rc != 0) 8539 return (rc); 8540 8541 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8542 if (sb == NULL) 8543 return (ENOMEM); 8544 8545 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 8546 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 8547 8548 sbuf_printf(sb, " Tx pcmds Tx bytes"); 8549 for (i = 0; i < 4; i++) { 8550 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8551 tx_cyc[i]); 8552 } 8553 8554 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 8555 for (i = 0; i < 4; i++) { 8556 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8557 rx_cyc[i]); 8558 } 8559 8560 if (chip_id(sc) > CHELSIO_T5) { 8561 sbuf_printf(sb, 8562 "\n Total wait Total occupancy"); 8563 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8564 tx_cyc[i]); 8565 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8566 rx_cyc[i]); 8567 8568 i += 2; 8569 MPASS(i < nitems(tx_stats)); 8570 8571 sbuf_printf(sb, 8572 "\n Reads Total wait"); 8573 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8574 tx_cyc[i]); 8575 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8576 rx_cyc[i]); 8577 } 8578 8579 rc = sbuf_finish(sb); 8580 sbuf_delete(sb); 8581 8582 return (rc); 8583 } 8584 8585 static int 8586 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 8587 { 8588 struct adapter *sc = arg1; 8589 struct sbuf *sb; 8590 int rc; 8591 struct tp_rdma_stats stats; 8592 8593 rc = sysctl_wire_old_buffer(req, 0); 8594 if (rc != 0) 8595 return (rc); 8596 8597 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8598 if (sb == NULL) 8599 return (ENOMEM); 8600 8601 mtx_lock(&sc->reg_lock); 8602 t4_tp_get_rdma_stats(sc, &stats, 0); 8603 mtx_unlock(&sc->reg_lock); 8604 8605 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 8606 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 8607 8608 rc = sbuf_finish(sb); 8609 sbuf_delete(sb); 8610 8611 return (rc); 8612 } 8613 8614 static int 8615 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 8616 { 8617 struct adapter *sc = arg1; 8618 struct sbuf *sb; 8619 int rc; 8620 struct tp_tcp_stats v4, v6; 8621 8622 rc = sysctl_wire_old_buffer(req, 0); 8623 if (rc != 0) 8624 return (rc); 8625 8626 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8627 if (sb == NULL) 8628 return (ENOMEM); 8629 8630 mtx_lock(&sc->reg_lock); 8631 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 8632 mtx_unlock(&sc->reg_lock); 8633 8634 sbuf_printf(sb, 8635 " IP IPv6\n"); 8636 sbuf_printf(sb, "OutRsts: %20u %20u\n", 8637 v4.tcp_out_rsts, v6.tcp_out_rsts); 8638 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 8639 v4.tcp_in_segs, v6.tcp_in_segs); 8640 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 8641 v4.tcp_out_segs, v6.tcp_out_segs); 8642 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 8643 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 8644 8645 rc = sbuf_finish(sb); 8646 sbuf_delete(sb); 8647 8648 return (rc); 8649 } 8650 8651 static int 8652 sysctl_tids(SYSCTL_HANDLER_ARGS) 8653 { 8654 struct adapter *sc = arg1; 8655 struct sbuf *sb; 8656 int rc; 8657 struct tid_info *t = &sc->tids; 8658 8659 rc = sysctl_wire_old_buffer(req, 0); 8660 if (rc != 0) 8661 return (rc); 8662 8663 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8664 if (sb == NULL) 8665 return (ENOMEM); 8666 8667 if (t->natids) { 8668 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 8669 t->atids_in_use); 8670 } 8671 8672 if (t->nhpftids) { 8673 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 8674 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 8675 } 8676 8677 if (t->ntids) { 8678 sbuf_printf(sb, "TID range: "); 8679 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8680 uint32_t b, hb; 8681 8682 if (chip_id(sc) <= CHELSIO_T5) { 8683 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 8684 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 8685 } else { 8686 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 8687 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 8688 } 8689 8690 if (b) 8691 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1); 8692 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 8693 } else 8694 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1); 8695 sbuf_printf(sb, ", in use: %u\n", 8696 atomic_load_acq_int(&t->tids_in_use)); 8697 } 8698 8699 if (t->nstids) { 8700 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 8701 t->stid_base + t->nstids - 1, t->stids_in_use); 8702 } 8703 8704 if (t->nftids) { 8705 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 8706 t->ftid_end, t->ftids_in_use); 8707 } 8708 8709 if (t->netids) { 8710 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 8711 t->etid_base + t->netids - 1, t->etids_in_use); 8712 } 8713 8714 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 8715 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 8716 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 8717 8718 rc = sbuf_finish(sb); 8719 sbuf_delete(sb); 8720 8721 return (rc); 8722 } 8723 8724 static int 8725 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 8726 { 8727 struct adapter *sc = arg1; 8728 struct sbuf *sb; 8729 int rc; 8730 struct tp_err_stats stats; 8731 8732 rc = sysctl_wire_old_buffer(req, 0); 8733 if (rc != 0) 8734 return (rc); 8735 8736 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8737 if (sb == NULL) 8738 return (ENOMEM); 8739 8740 mtx_lock(&sc->reg_lock); 8741 t4_tp_get_err_stats(sc, &stats, 0); 8742 mtx_unlock(&sc->reg_lock); 8743 8744 if (sc->chip_params->nchan > 2) { 8745 sbuf_printf(sb, " channel 0 channel 1" 8746 " channel 2 channel 3\n"); 8747 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 8748 stats.mac_in_errs[0], stats.mac_in_errs[1], 8749 stats.mac_in_errs[2], stats.mac_in_errs[3]); 8750 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 8751 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 8752 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 8753 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 8754 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 8755 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 8756 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 8757 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 8758 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 8759 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 8760 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 8761 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 8762 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 8763 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 8764 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 8765 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 8766 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 8767 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 8768 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 8769 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 8770 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 8771 } else { 8772 sbuf_printf(sb, " channel 0 channel 1\n"); 8773 sbuf_printf(sb, "macInErrs: %10u %10u\n", 8774 stats.mac_in_errs[0], stats.mac_in_errs[1]); 8775 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 8776 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 8777 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 8778 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8779 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8780 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8781 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8782 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8783 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8784 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8785 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8786 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8787 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8788 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8789 } 8790 8791 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8792 stats.ofld_no_neigh, stats.ofld_cong_defer); 8793 8794 rc = sbuf_finish(sb); 8795 sbuf_delete(sb); 8796 8797 return (rc); 8798 } 8799 8800 static int 8801 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8802 { 8803 struct adapter *sc = arg1; 8804 struct tp_params *tpp = &sc->params.tp; 8805 u_int mask; 8806 int rc; 8807 8808 mask = tpp->la_mask >> 16; 8809 rc = sysctl_handle_int(oidp, &mask, 0, req); 8810 if (rc != 0 || req->newptr == NULL) 8811 return (rc); 8812 if (mask > 0xffff) 8813 return (EINVAL); 8814 tpp->la_mask = mask << 16; 8815 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8816 8817 return (0); 8818 } 8819 8820 struct field_desc { 8821 const char *name; 8822 u_int start; 8823 u_int width; 8824 }; 8825 8826 static void 8827 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8828 { 8829 char buf[32]; 8830 int line_size = 0; 8831 8832 while (f->name) { 8833 uint64_t mask = (1ULL << f->width) - 1; 8834 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8835 ((uintmax_t)v >> f->start) & mask); 8836 8837 if (line_size + len >= 79) { 8838 line_size = 8; 8839 sbuf_printf(sb, "\n "); 8840 } 8841 sbuf_printf(sb, "%s ", buf); 8842 line_size += len + 1; 8843 f++; 8844 } 8845 sbuf_printf(sb, "\n"); 8846 } 8847 8848 static const struct field_desc tp_la0[] = { 8849 { "RcfOpCodeOut", 60, 4 }, 8850 { "State", 56, 4 }, 8851 { "WcfState", 52, 4 }, 8852 { "RcfOpcSrcOut", 50, 2 }, 8853 { "CRxError", 49, 1 }, 8854 { "ERxError", 48, 1 }, 8855 { "SanityFailed", 47, 1 }, 8856 { "SpuriousMsg", 46, 1 }, 8857 { "FlushInputMsg", 45, 1 }, 8858 { "FlushInputCpl", 44, 1 }, 8859 { "RssUpBit", 43, 1 }, 8860 { "RssFilterHit", 42, 1 }, 8861 { "Tid", 32, 10 }, 8862 { "InitTcb", 31, 1 }, 8863 { "LineNumber", 24, 7 }, 8864 { "Emsg", 23, 1 }, 8865 { "EdataOut", 22, 1 }, 8866 { "Cmsg", 21, 1 }, 8867 { "CdataOut", 20, 1 }, 8868 { "EreadPdu", 19, 1 }, 8869 { "CreadPdu", 18, 1 }, 8870 { "TunnelPkt", 17, 1 }, 8871 { "RcfPeerFin", 16, 1 }, 8872 { "RcfReasonOut", 12, 4 }, 8873 { "TxCchannel", 10, 2 }, 8874 { "RcfTxChannel", 8, 2 }, 8875 { "RxEchannel", 6, 2 }, 8876 { "RcfRxChannel", 5, 1 }, 8877 { "RcfDataOutSrdy", 4, 1 }, 8878 { "RxDvld", 3, 1 }, 8879 { "RxOoDvld", 2, 1 }, 8880 { "RxCongestion", 1, 1 }, 8881 { "TxCongestion", 0, 1 }, 8882 { NULL } 8883 }; 8884 8885 static const struct field_desc tp_la1[] = { 8886 { "CplCmdIn", 56, 8 }, 8887 { "CplCmdOut", 48, 8 }, 8888 { "ESynOut", 47, 1 }, 8889 { "EAckOut", 46, 1 }, 8890 { "EFinOut", 45, 1 }, 8891 { "ERstOut", 44, 1 }, 8892 { "SynIn", 43, 1 }, 8893 { "AckIn", 42, 1 }, 8894 { "FinIn", 41, 1 }, 8895 { "RstIn", 40, 1 }, 8896 { "DataIn", 39, 1 }, 8897 { "DataInVld", 38, 1 }, 8898 { "PadIn", 37, 1 }, 8899 { "RxBufEmpty", 36, 1 }, 8900 { "RxDdp", 35, 1 }, 8901 { "RxFbCongestion", 34, 1 }, 8902 { "TxFbCongestion", 33, 1 }, 8903 { "TxPktSumSrdy", 32, 1 }, 8904 { "RcfUlpType", 28, 4 }, 8905 { "Eread", 27, 1 }, 8906 { "Ebypass", 26, 1 }, 8907 { "Esave", 25, 1 }, 8908 { "Static0", 24, 1 }, 8909 { "Cread", 23, 1 }, 8910 { "Cbypass", 22, 1 }, 8911 { "Csave", 21, 1 }, 8912 { "CPktOut", 20, 1 }, 8913 { "RxPagePoolFull", 18, 2 }, 8914 { "RxLpbkPkt", 17, 1 }, 8915 { "TxLpbkPkt", 16, 1 }, 8916 { "RxVfValid", 15, 1 }, 8917 { "SynLearned", 14, 1 }, 8918 { "SetDelEntry", 13, 1 }, 8919 { "SetInvEntry", 12, 1 }, 8920 { "CpcmdDvld", 11, 1 }, 8921 { "CpcmdSave", 10, 1 }, 8922 { "RxPstructsFull", 8, 2 }, 8923 { "EpcmdDvld", 7, 1 }, 8924 { "EpcmdFlush", 6, 1 }, 8925 { "EpcmdTrimPrefix", 5, 1 }, 8926 { "EpcmdTrimPostfix", 4, 1 }, 8927 { "ERssIp4Pkt", 3, 1 }, 8928 { "ERssIp6Pkt", 2, 1 }, 8929 { "ERssTcpUdpPkt", 1, 1 }, 8930 { "ERssFceFipPkt", 0, 1 }, 8931 { NULL } 8932 }; 8933 8934 static const struct field_desc tp_la2[] = { 8935 { "CplCmdIn", 56, 8 }, 8936 { "MpsVfVld", 55, 1 }, 8937 { "MpsPf", 52, 3 }, 8938 { "MpsVf", 44, 8 }, 8939 { "SynIn", 43, 1 }, 8940 { "AckIn", 42, 1 }, 8941 { "FinIn", 41, 1 }, 8942 { "RstIn", 40, 1 }, 8943 { "DataIn", 39, 1 }, 8944 { "DataInVld", 38, 1 }, 8945 { "PadIn", 37, 1 }, 8946 { "RxBufEmpty", 36, 1 }, 8947 { "RxDdp", 35, 1 }, 8948 { "RxFbCongestion", 34, 1 }, 8949 { "TxFbCongestion", 33, 1 }, 8950 { "TxPktSumSrdy", 32, 1 }, 8951 { "RcfUlpType", 28, 4 }, 8952 { "Eread", 27, 1 }, 8953 { "Ebypass", 26, 1 }, 8954 { "Esave", 25, 1 }, 8955 { "Static0", 24, 1 }, 8956 { "Cread", 23, 1 }, 8957 { "Cbypass", 22, 1 }, 8958 { "Csave", 21, 1 }, 8959 { "CPktOut", 20, 1 }, 8960 { "RxPagePoolFull", 18, 2 }, 8961 { "RxLpbkPkt", 17, 1 }, 8962 { "TxLpbkPkt", 16, 1 }, 8963 { "RxVfValid", 15, 1 }, 8964 { "SynLearned", 14, 1 }, 8965 { "SetDelEntry", 13, 1 }, 8966 { "SetInvEntry", 12, 1 }, 8967 { "CpcmdDvld", 11, 1 }, 8968 { "CpcmdSave", 10, 1 }, 8969 { "RxPstructsFull", 8, 2 }, 8970 { "EpcmdDvld", 7, 1 }, 8971 { "EpcmdFlush", 6, 1 }, 8972 { "EpcmdTrimPrefix", 5, 1 }, 8973 { "EpcmdTrimPostfix", 4, 1 }, 8974 { "ERssIp4Pkt", 3, 1 }, 8975 { "ERssIp6Pkt", 2, 1 }, 8976 { "ERssTcpUdpPkt", 1, 1 }, 8977 { "ERssFceFipPkt", 0, 1 }, 8978 { NULL } 8979 }; 8980 8981 static void 8982 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8983 { 8984 8985 field_desc_show(sb, *p, tp_la0); 8986 } 8987 8988 static void 8989 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8990 { 8991 8992 if (idx) 8993 sbuf_printf(sb, "\n"); 8994 field_desc_show(sb, p[0], tp_la0); 8995 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8996 field_desc_show(sb, p[1], tp_la0); 8997 } 8998 8999 static void 9000 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 9001 { 9002 9003 if (idx) 9004 sbuf_printf(sb, "\n"); 9005 field_desc_show(sb, p[0], tp_la0); 9006 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9007 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 9008 } 9009 9010 static int 9011 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 9012 { 9013 struct adapter *sc = arg1; 9014 struct sbuf *sb; 9015 uint64_t *buf, *p; 9016 int rc; 9017 u_int i, inc; 9018 void (*show_func)(struct sbuf *, uint64_t *, int); 9019 9020 rc = sysctl_wire_old_buffer(req, 0); 9021 if (rc != 0) 9022 return (rc); 9023 9024 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9025 if (sb == NULL) 9026 return (ENOMEM); 9027 9028 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 9029 9030 t4_tp_read_la(sc, buf, NULL); 9031 p = buf; 9032 9033 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 9034 case 2: 9035 inc = 2; 9036 show_func = tp_la_show2; 9037 break; 9038 case 3: 9039 inc = 2; 9040 show_func = tp_la_show3; 9041 break; 9042 default: 9043 inc = 1; 9044 show_func = tp_la_show; 9045 } 9046 9047 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 9048 (*show_func)(sb, p, i); 9049 9050 rc = sbuf_finish(sb); 9051 sbuf_delete(sb); 9052 free(buf, M_CXGBE); 9053 return (rc); 9054 } 9055 9056 static int 9057 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 9058 { 9059 struct adapter *sc = arg1; 9060 struct sbuf *sb; 9061 int rc; 9062 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 9063 9064 rc = sysctl_wire_old_buffer(req, 0); 9065 if (rc != 0) 9066 return (rc); 9067 9068 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9069 if (sb == NULL) 9070 return (ENOMEM); 9071 9072 t4_get_chan_txrate(sc, nrate, orate); 9073 9074 if (sc->chip_params->nchan > 2) { 9075 sbuf_printf(sb, " channel 0 channel 1" 9076 " channel 2 channel 3\n"); 9077 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 9078 nrate[0], nrate[1], nrate[2], nrate[3]); 9079 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 9080 orate[0], orate[1], orate[2], orate[3]); 9081 } else { 9082 sbuf_printf(sb, " channel 0 channel 1\n"); 9083 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 9084 nrate[0], nrate[1]); 9085 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 9086 orate[0], orate[1]); 9087 } 9088 9089 rc = sbuf_finish(sb); 9090 sbuf_delete(sb); 9091 9092 return (rc); 9093 } 9094 9095 static int 9096 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 9097 { 9098 struct adapter *sc = arg1; 9099 struct sbuf *sb; 9100 uint32_t *buf, *p; 9101 int rc, i; 9102 9103 rc = sysctl_wire_old_buffer(req, 0); 9104 if (rc != 0) 9105 return (rc); 9106 9107 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9108 if (sb == NULL) 9109 return (ENOMEM); 9110 9111 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 9112 M_ZERO | M_WAITOK); 9113 9114 t4_ulprx_read_la(sc, buf); 9115 p = buf; 9116 9117 sbuf_printf(sb, " Pcmd Type Message" 9118 " Data"); 9119 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 9120 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 9121 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 9122 } 9123 9124 rc = sbuf_finish(sb); 9125 sbuf_delete(sb); 9126 free(buf, M_CXGBE); 9127 return (rc); 9128 } 9129 9130 static int 9131 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 9132 { 9133 struct adapter *sc = arg1; 9134 struct sbuf *sb; 9135 int rc, v; 9136 9137 MPASS(chip_id(sc) >= CHELSIO_T5); 9138 9139 rc = sysctl_wire_old_buffer(req, 0); 9140 if (rc != 0) 9141 return (rc); 9142 9143 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9144 if (sb == NULL) 9145 return (ENOMEM); 9146 9147 v = t4_read_reg(sc, A_SGE_STAT_CFG); 9148 if (G_STATSOURCE_T5(v) == 7) { 9149 int mode; 9150 9151 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 9152 if (mode == 0) { 9153 sbuf_printf(sb, "total %d, incomplete %d", 9154 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9155 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9156 } else if (mode == 1) { 9157 sbuf_printf(sb, "total %d, data overflow %d", 9158 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9159 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9160 } else { 9161 sbuf_printf(sb, "unknown mode %d", mode); 9162 } 9163 } 9164 rc = sbuf_finish(sb); 9165 sbuf_delete(sb); 9166 9167 return (rc); 9168 } 9169 9170 static int 9171 sysctl_cpus(SYSCTL_HANDLER_ARGS) 9172 { 9173 struct adapter *sc = arg1; 9174 enum cpu_sets op = arg2; 9175 cpuset_t cpuset; 9176 struct sbuf *sb; 9177 int i, rc; 9178 9179 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 9180 9181 CPU_ZERO(&cpuset); 9182 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 9183 if (rc != 0) 9184 return (rc); 9185 9186 rc = sysctl_wire_old_buffer(req, 0); 9187 if (rc != 0) 9188 return (rc); 9189 9190 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9191 if (sb == NULL) 9192 return (ENOMEM); 9193 9194 CPU_FOREACH(i) 9195 sbuf_printf(sb, "%d ", i); 9196 rc = sbuf_finish(sb); 9197 sbuf_delete(sb); 9198 9199 return (rc); 9200 } 9201 9202 #ifdef TCP_OFFLOAD 9203 static int 9204 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 9205 { 9206 struct adapter *sc = arg1; 9207 int *old_ports, *new_ports; 9208 int i, new_count, rc; 9209 9210 if (req->newptr == NULL && req->oldptr == NULL) 9211 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 9212 sizeof(sc->tt.tls_rx_ports[0]))); 9213 9214 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 9215 if (rc) 9216 return (rc); 9217 9218 if (sc->tt.num_tls_rx_ports == 0) { 9219 i = -1; 9220 rc = SYSCTL_OUT(req, &i, sizeof(i)); 9221 } else 9222 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 9223 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 9224 if (rc == 0 && req->newptr != NULL) { 9225 new_count = req->newlen / sizeof(new_ports[0]); 9226 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 9227 M_WAITOK); 9228 rc = SYSCTL_IN(req, new_ports, new_count * 9229 sizeof(new_ports[0])); 9230 if (rc) 9231 goto err; 9232 9233 /* Allow setting to a single '-1' to clear the list. */ 9234 if (new_count == 1 && new_ports[0] == -1) { 9235 ADAPTER_LOCK(sc); 9236 old_ports = sc->tt.tls_rx_ports; 9237 sc->tt.tls_rx_ports = NULL; 9238 sc->tt.num_tls_rx_ports = 0; 9239 ADAPTER_UNLOCK(sc); 9240 free(old_ports, M_CXGBE); 9241 } else { 9242 for (i = 0; i < new_count; i++) { 9243 if (new_ports[i] < 1 || 9244 new_ports[i] > IPPORT_MAX) { 9245 rc = EINVAL; 9246 goto err; 9247 } 9248 } 9249 9250 ADAPTER_LOCK(sc); 9251 old_ports = sc->tt.tls_rx_ports; 9252 sc->tt.tls_rx_ports = new_ports; 9253 sc->tt.num_tls_rx_ports = new_count; 9254 ADAPTER_UNLOCK(sc); 9255 free(old_ports, M_CXGBE); 9256 new_ports = NULL; 9257 } 9258 err: 9259 free(new_ports, M_CXGBE); 9260 } 9261 end_synchronized_op(sc, 0); 9262 return (rc); 9263 } 9264 9265 static void 9266 unit_conv(char *buf, size_t len, u_int val, u_int factor) 9267 { 9268 u_int rem = val % factor; 9269 9270 if (rem == 0) 9271 snprintf(buf, len, "%u", val / factor); 9272 else { 9273 while (rem % 10 == 0) 9274 rem /= 10; 9275 snprintf(buf, len, "%u.%u", val / factor, rem); 9276 } 9277 } 9278 9279 static int 9280 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 9281 { 9282 struct adapter *sc = arg1; 9283 char buf[16]; 9284 u_int res, re; 9285 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9286 9287 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9288 switch (arg2) { 9289 case 0: 9290 /* timer_tick */ 9291 re = G_TIMERRESOLUTION(res); 9292 break; 9293 case 1: 9294 /* TCP timestamp tick */ 9295 re = G_TIMESTAMPRESOLUTION(res); 9296 break; 9297 case 2: 9298 /* DACK tick */ 9299 re = G_DELAYEDACKRESOLUTION(res); 9300 break; 9301 default: 9302 return (EDOOFUS); 9303 } 9304 9305 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 9306 9307 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 9308 } 9309 9310 static int 9311 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 9312 { 9313 struct adapter *sc = arg1; 9314 u_int res, dack_re, v; 9315 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9316 9317 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9318 dack_re = G_DELAYEDACKRESOLUTION(res); 9319 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 9320 9321 return (sysctl_handle_int(oidp, &v, 0, req)); 9322 } 9323 9324 static int 9325 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 9326 { 9327 struct adapter *sc = arg1; 9328 int reg = arg2; 9329 u_int tre; 9330 u_long tp_tick_us, v; 9331 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9332 9333 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 9334 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 9335 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 9336 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 9337 9338 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 9339 tp_tick_us = (cclk_ps << tre) / 1000000; 9340 9341 if (reg == A_TP_INIT_SRTT) 9342 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 9343 else 9344 v = tp_tick_us * t4_read_reg(sc, reg); 9345 9346 return (sysctl_handle_long(oidp, &v, 0, req)); 9347 } 9348 9349 /* 9350 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 9351 * passed to this function. 9352 */ 9353 static int 9354 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 9355 { 9356 struct adapter *sc = arg1; 9357 int idx = arg2; 9358 u_int v; 9359 9360 MPASS(idx >= 0 && idx <= 24); 9361 9362 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 9363 9364 return (sysctl_handle_int(oidp, &v, 0, req)); 9365 } 9366 9367 static int 9368 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 9369 { 9370 struct adapter *sc = arg1; 9371 int idx = arg2; 9372 u_int shift, v, r; 9373 9374 MPASS(idx >= 0 && idx < 16); 9375 9376 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 9377 shift = (idx & 3) << 3; 9378 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 9379 9380 return (sysctl_handle_int(oidp, &v, 0, req)); 9381 } 9382 9383 static int 9384 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 9385 { 9386 struct vi_info *vi = arg1; 9387 struct adapter *sc = vi->pi->adapter; 9388 int idx, rc, i; 9389 struct sge_ofld_rxq *ofld_rxq; 9390 uint8_t v; 9391 9392 idx = vi->ofld_tmr_idx; 9393 9394 rc = sysctl_handle_int(oidp, &idx, 0, req); 9395 if (rc != 0 || req->newptr == NULL) 9396 return (rc); 9397 9398 if (idx < 0 || idx >= SGE_NTIMERS) 9399 return (EINVAL); 9400 9401 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9402 "t4otmr"); 9403 if (rc) 9404 return (rc); 9405 9406 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 9407 for_each_ofld_rxq(vi, i, ofld_rxq) { 9408 #ifdef atomic_store_rel_8 9409 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 9410 #else 9411 ofld_rxq->iq.intr_params = v; 9412 #endif 9413 } 9414 vi->ofld_tmr_idx = idx; 9415 9416 end_synchronized_op(sc, LOCK_HELD); 9417 return (0); 9418 } 9419 9420 static int 9421 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 9422 { 9423 struct vi_info *vi = arg1; 9424 struct adapter *sc = vi->pi->adapter; 9425 int idx, rc; 9426 9427 idx = vi->ofld_pktc_idx; 9428 9429 rc = sysctl_handle_int(oidp, &idx, 0, req); 9430 if (rc != 0 || req->newptr == NULL) 9431 return (rc); 9432 9433 if (idx < -1 || idx >= SGE_NCOUNTERS) 9434 return (EINVAL); 9435 9436 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9437 "t4opktc"); 9438 if (rc) 9439 return (rc); 9440 9441 if (vi->flags & VI_INIT_DONE) 9442 rc = EBUSY; /* cannot be changed once the queues are created */ 9443 else 9444 vi->ofld_pktc_idx = idx; 9445 9446 end_synchronized_op(sc, LOCK_HELD); 9447 return (rc); 9448 } 9449 #endif 9450 9451 static int 9452 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 9453 { 9454 int rc; 9455 9456 if (cntxt->cid > M_CTXTQID) 9457 return (EINVAL); 9458 9459 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 9460 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 9461 return (EINVAL); 9462 9463 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 9464 if (rc) 9465 return (rc); 9466 9467 if (sc->flags & FW_OK) { 9468 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 9469 &cntxt->data[0]); 9470 if (rc == 0) 9471 goto done; 9472 } 9473 9474 /* 9475 * Read via firmware failed or wasn't even attempted. Read directly via 9476 * the backdoor. 9477 */ 9478 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 9479 done: 9480 end_synchronized_op(sc, 0); 9481 return (rc); 9482 } 9483 9484 static int 9485 load_fw(struct adapter *sc, struct t4_data *fw) 9486 { 9487 int rc; 9488 uint8_t *fw_data; 9489 9490 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 9491 if (rc) 9492 return (rc); 9493 9494 /* 9495 * The firmware, with the sole exception of the memory parity error 9496 * handler, runs from memory and not flash. It is almost always safe to 9497 * install a new firmware on a running system. Just set bit 1 in 9498 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 9499 */ 9500 if (sc->flags & FULL_INIT_DONE && 9501 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 9502 rc = EBUSY; 9503 goto done; 9504 } 9505 9506 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9507 if (fw_data == NULL) { 9508 rc = ENOMEM; 9509 goto done; 9510 } 9511 9512 rc = copyin(fw->data, fw_data, fw->len); 9513 if (rc == 0) 9514 rc = -t4_load_fw(sc, fw_data, fw->len); 9515 9516 free(fw_data, M_CXGBE); 9517 done: 9518 end_synchronized_op(sc, 0); 9519 return (rc); 9520 } 9521 9522 static int 9523 load_cfg(struct adapter *sc, struct t4_data *cfg) 9524 { 9525 int rc; 9526 uint8_t *cfg_data = NULL; 9527 9528 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9529 if (rc) 9530 return (rc); 9531 9532 if (cfg->len == 0) { 9533 /* clear */ 9534 rc = -t4_load_cfg(sc, NULL, 0); 9535 goto done; 9536 } 9537 9538 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9539 if (cfg_data == NULL) { 9540 rc = ENOMEM; 9541 goto done; 9542 } 9543 9544 rc = copyin(cfg->data, cfg_data, cfg->len); 9545 if (rc == 0) 9546 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9547 9548 free(cfg_data, M_CXGBE); 9549 done: 9550 end_synchronized_op(sc, 0); 9551 return (rc); 9552 } 9553 9554 static int 9555 load_boot(struct adapter *sc, struct t4_bootrom *br) 9556 { 9557 int rc; 9558 uint8_t *br_data = NULL; 9559 u_int offset; 9560 9561 if (br->len > 1024 * 1024) 9562 return (EFBIG); 9563 9564 if (br->pf_offset == 0) { 9565 /* pfidx */ 9566 if (br->pfidx_addr > 7) 9567 return (EINVAL); 9568 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9569 A_PCIE_PF_EXPROM_OFST))); 9570 } else if (br->pf_offset == 1) { 9571 /* offset */ 9572 offset = G_OFFSET(br->pfidx_addr); 9573 } else { 9574 return (EINVAL); 9575 } 9576 9577 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9578 if (rc) 9579 return (rc); 9580 9581 if (br->len == 0) { 9582 /* clear */ 9583 rc = -t4_load_boot(sc, NULL, offset, 0); 9584 goto done; 9585 } 9586 9587 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9588 if (br_data == NULL) { 9589 rc = ENOMEM; 9590 goto done; 9591 } 9592 9593 rc = copyin(br->data, br_data, br->len); 9594 if (rc == 0) 9595 rc = -t4_load_boot(sc, br_data, offset, br->len); 9596 9597 free(br_data, M_CXGBE); 9598 done: 9599 end_synchronized_op(sc, 0); 9600 return (rc); 9601 } 9602 9603 static int 9604 load_bootcfg(struct adapter *sc, struct t4_data *bc) 9605 { 9606 int rc; 9607 uint8_t *bc_data = NULL; 9608 9609 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9610 if (rc) 9611 return (rc); 9612 9613 if (bc->len == 0) { 9614 /* clear */ 9615 rc = -t4_load_bootcfg(sc, NULL, 0); 9616 goto done; 9617 } 9618 9619 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9620 if (bc_data == NULL) { 9621 rc = ENOMEM; 9622 goto done; 9623 } 9624 9625 rc = copyin(bc->data, bc_data, bc->len); 9626 if (rc == 0) 9627 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9628 9629 free(bc_data, M_CXGBE); 9630 done: 9631 end_synchronized_op(sc, 0); 9632 return (rc); 9633 } 9634 9635 static int 9636 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9637 { 9638 int rc; 9639 struct cudbg_init *cudbg; 9640 void *handle, *buf; 9641 9642 /* buf is large, don't block if no memory is available */ 9643 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9644 if (buf == NULL) 9645 return (ENOMEM); 9646 9647 handle = cudbg_alloc_handle(); 9648 if (handle == NULL) { 9649 rc = ENOMEM; 9650 goto done; 9651 } 9652 9653 cudbg = cudbg_get_init(handle); 9654 cudbg->adap = sc; 9655 cudbg->print = (cudbg_print_cb)printf; 9656 9657 #ifndef notyet 9658 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9659 __func__, dump->wr_flash, dump->len, dump->data); 9660 #endif 9661 9662 if (dump->wr_flash) 9663 cudbg->use_flash = 1; 9664 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9665 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9666 9667 rc = cudbg_collect(handle, buf, &dump->len); 9668 if (rc != 0) 9669 goto done; 9670 9671 rc = copyout(buf, dump->data, dump->len); 9672 done: 9673 cudbg_free_handle(handle); 9674 free(buf, M_CXGBE); 9675 return (rc); 9676 } 9677 9678 static void 9679 free_offload_policy(struct t4_offload_policy *op) 9680 { 9681 struct offload_rule *r; 9682 int i; 9683 9684 if (op == NULL) 9685 return; 9686 9687 r = &op->rule[0]; 9688 for (i = 0; i < op->nrules; i++, r++) { 9689 free(r->bpf_prog.bf_insns, M_CXGBE); 9690 } 9691 free(op->rule, M_CXGBE); 9692 free(op, M_CXGBE); 9693 } 9694 9695 static int 9696 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 9697 { 9698 int i, rc, len; 9699 struct t4_offload_policy *op, *old; 9700 struct bpf_program *bf; 9701 const struct offload_settings *s; 9702 struct offload_rule *r; 9703 void *u; 9704 9705 if (!is_offload(sc)) 9706 return (ENODEV); 9707 9708 if (uop->nrules == 0) { 9709 /* Delete installed policies. */ 9710 op = NULL; 9711 goto set_policy; 9712 } else if (uop->nrules > 256) { /* arbitrary */ 9713 return (E2BIG); 9714 } 9715 9716 /* Copy userspace offload policy to kernel */ 9717 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 9718 op->nrules = uop->nrules; 9719 len = op->nrules * sizeof(struct offload_rule); 9720 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9721 rc = copyin(uop->rule, op->rule, len); 9722 if (rc) { 9723 free(op->rule, M_CXGBE); 9724 free(op, M_CXGBE); 9725 return (rc); 9726 } 9727 9728 r = &op->rule[0]; 9729 for (i = 0; i < op->nrules; i++, r++) { 9730 9731 /* Validate open_type */ 9732 if (r->open_type != OPEN_TYPE_LISTEN && 9733 r->open_type != OPEN_TYPE_ACTIVE && 9734 r->open_type != OPEN_TYPE_PASSIVE && 9735 r->open_type != OPEN_TYPE_DONTCARE) { 9736 error: 9737 /* 9738 * Rules 0 to i have malloc'd filters that need to be 9739 * freed. Rules i+1 to nrules have userspace pointers 9740 * and should be left alone. 9741 */ 9742 op->nrules = i; 9743 free_offload_policy(op); 9744 return (rc); 9745 } 9746 9747 /* Validate settings */ 9748 s = &r->settings; 9749 if ((s->offload != 0 && s->offload != 1) || 9750 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9751 s->sched_class < -1 || 9752 s->sched_class >= sc->chip_params->nsched_cls) { 9753 rc = EINVAL; 9754 goto error; 9755 } 9756 9757 bf = &r->bpf_prog; 9758 u = bf->bf_insns; /* userspace ptr */ 9759 bf->bf_insns = NULL; 9760 if (bf->bf_len == 0) { 9761 /* legal, matches everything */ 9762 continue; 9763 } 9764 len = bf->bf_len * sizeof(*bf->bf_insns); 9765 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9766 rc = copyin(u, bf->bf_insns, len); 9767 if (rc != 0) 9768 goto error; 9769 9770 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9771 rc = EINVAL; 9772 goto error; 9773 } 9774 } 9775 set_policy: 9776 rw_wlock(&sc->policy_lock); 9777 old = sc->policy; 9778 sc->policy = op; 9779 rw_wunlock(&sc->policy_lock); 9780 free_offload_policy(old); 9781 9782 return (0); 9783 } 9784 9785 #define MAX_READ_BUF_SIZE (128 * 1024) 9786 static int 9787 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9788 { 9789 uint32_t addr, remaining, n; 9790 uint32_t *buf; 9791 int rc; 9792 uint8_t *dst; 9793 9794 rc = validate_mem_range(sc, mr->addr, mr->len); 9795 if (rc != 0) 9796 return (rc); 9797 9798 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9799 addr = mr->addr; 9800 remaining = mr->len; 9801 dst = (void *)mr->data; 9802 9803 while (remaining) { 9804 n = min(remaining, MAX_READ_BUF_SIZE); 9805 read_via_memwin(sc, 2, addr, buf, n); 9806 9807 rc = copyout(buf, dst, n); 9808 if (rc != 0) 9809 break; 9810 9811 dst += n; 9812 remaining -= n; 9813 addr += n; 9814 } 9815 9816 free(buf, M_CXGBE); 9817 return (rc); 9818 } 9819 #undef MAX_READ_BUF_SIZE 9820 9821 static int 9822 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9823 { 9824 int rc; 9825 9826 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9827 return (EINVAL); 9828 9829 if (i2cd->len > sizeof(i2cd->data)) 9830 return (EFBIG); 9831 9832 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9833 if (rc) 9834 return (rc); 9835 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9836 i2cd->offset, i2cd->len, &i2cd->data[0]); 9837 end_synchronized_op(sc, 0); 9838 9839 return (rc); 9840 } 9841 9842 int 9843 t4_os_find_pci_capability(struct adapter *sc, int cap) 9844 { 9845 int i; 9846 9847 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9848 } 9849 9850 int 9851 t4_os_pci_save_state(struct adapter *sc) 9852 { 9853 device_t dev; 9854 struct pci_devinfo *dinfo; 9855 9856 dev = sc->dev; 9857 dinfo = device_get_ivars(dev); 9858 9859 pci_cfg_save(dev, dinfo, 0); 9860 return (0); 9861 } 9862 9863 int 9864 t4_os_pci_restore_state(struct adapter *sc) 9865 { 9866 device_t dev; 9867 struct pci_devinfo *dinfo; 9868 9869 dev = sc->dev; 9870 dinfo = device_get_ivars(dev); 9871 9872 pci_cfg_restore(dev, dinfo); 9873 return (0); 9874 } 9875 9876 void 9877 t4_os_portmod_changed(struct port_info *pi) 9878 { 9879 struct adapter *sc = pi->adapter; 9880 struct vi_info *vi; 9881 struct ifnet *ifp; 9882 static const char *mod_str[] = { 9883 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9884 }; 9885 9886 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 9887 ("%s: port_type %u", __func__, pi->port_type)); 9888 9889 vi = &pi->vi[0]; 9890 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9891 PORT_LOCK(pi); 9892 build_medialist(pi); 9893 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 9894 fixup_link_config(pi); 9895 apply_link_config(pi); 9896 } 9897 PORT_UNLOCK(pi); 9898 end_synchronized_op(sc, LOCK_HELD); 9899 } 9900 9901 ifp = vi->ifp; 9902 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9903 if_printf(ifp, "transceiver unplugged.\n"); 9904 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9905 if_printf(ifp, "unknown transceiver inserted.\n"); 9906 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9907 if_printf(ifp, "unsupported transceiver inserted.\n"); 9908 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9909 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9910 port_top_speed(pi), mod_str[pi->mod_type]); 9911 } else { 9912 if_printf(ifp, "transceiver (type %d) inserted.\n", 9913 pi->mod_type); 9914 } 9915 } 9916 9917 void 9918 t4_os_link_changed(struct port_info *pi) 9919 { 9920 struct vi_info *vi; 9921 struct ifnet *ifp; 9922 struct link_config *lc; 9923 int v; 9924 9925 PORT_LOCK_ASSERT_OWNED(pi); 9926 9927 for_each_vi(pi, v, vi) { 9928 ifp = vi->ifp; 9929 if (ifp == NULL) 9930 continue; 9931 9932 lc = &pi->link_cfg; 9933 if (lc->link_ok) { 9934 ifp->if_baudrate = IF_Mbps(lc->speed); 9935 if_link_state_change(ifp, LINK_STATE_UP); 9936 } else { 9937 if_link_state_change(ifp, LINK_STATE_DOWN); 9938 } 9939 } 9940 } 9941 9942 void 9943 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9944 { 9945 struct adapter *sc; 9946 9947 sx_slock(&t4_list_lock); 9948 SLIST_FOREACH(sc, &t4_list, link) { 9949 /* 9950 * func should not make any assumptions about what state sc is 9951 * in - the only guarantee is that sc->sc_lock is a valid lock. 9952 */ 9953 func(sc, arg); 9954 } 9955 sx_sunlock(&t4_list_lock); 9956 } 9957 9958 static int 9959 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9960 struct thread *td) 9961 { 9962 int rc; 9963 struct adapter *sc = dev->si_drv1; 9964 9965 rc = priv_check(td, PRIV_DRIVER); 9966 if (rc != 0) 9967 return (rc); 9968 9969 switch (cmd) { 9970 case CHELSIO_T4_GETREG: { 9971 struct t4_reg *edata = (struct t4_reg *)data; 9972 9973 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9974 return (EFAULT); 9975 9976 if (edata->size == 4) 9977 edata->val = t4_read_reg(sc, edata->addr); 9978 else if (edata->size == 8) 9979 edata->val = t4_read_reg64(sc, edata->addr); 9980 else 9981 return (EINVAL); 9982 9983 break; 9984 } 9985 case CHELSIO_T4_SETREG: { 9986 struct t4_reg *edata = (struct t4_reg *)data; 9987 9988 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9989 return (EFAULT); 9990 9991 if (edata->size == 4) { 9992 if (edata->val & 0xffffffff00000000) 9993 return (EINVAL); 9994 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9995 } else if (edata->size == 8) 9996 t4_write_reg64(sc, edata->addr, edata->val); 9997 else 9998 return (EINVAL); 9999 break; 10000 } 10001 case CHELSIO_T4_REGDUMP: { 10002 struct t4_regdump *regs = (struct t4_regdump *)data; 10003 int reglen = t4_get_regs_len(sc); 10004 uint8_t *buf; 10005 10006 if (regs->len < reglen) { 10007 regs->len = reglen; /* hint to the caller */ 10008 return (ENOBUFS); 10009 } 10010 10011 regs->len = reglen; 10012 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 10013 get_regs(sc, regs, buf); 10014 rc = copyout(buf, regs->data, reglen); 10015 free(buf, M_CXGBE); 10016 break; 10017 } 10018 case CHELSIO_T4_GET_FILTER_MODE: 10019 rc = get_filter_mode(sc, (uint32_t *)data); 10020 break; 10021 case CHELSIO_T4_SET_FILTER_MODE: 10022 rc = set_filter_mode(sc, *(uint32_t *)data); 10023 break; 10024 case CHELSIO_T4_GET_FILTER: 10025 rc = get_filter(sc, (struct t4_filter *)data); 10026 break; 10027 case CHELSIO_T4_SET_FILTER: 10028 rc = set_filter(sc, (struct t4_filter *)data); 10029 break; 10030 case CHELSIO_T4_DEL_FILTER: 10031 rc = del_filter(sc, (struct t4_filter *)data); 10032 break; 10033 case CHELSIO_T4_GET_SGE_CONTEXT: 10034 rc = get_sge_context(sc, (struct t4_sge_context *)data); 10035 break; 10036 case CHELSIO_T4_LOAD_FW: 10037 rc = load_fw(sc, (struct t4_data *)data); 10038 break; 10039 case CHELSIO_T4_GET_MEM: 10040 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 10041 break; 10042 case CHELSIO_T4_GET_I2C: 10043 rc = read_i2c(sc, (struct t4_i2c_data *)data); 10044 break; 10045 case CHELSIO_T4_CLEAR_STATS: { 10046 int i, v, bg_map; 10047 u_int port_id = *(uint32_t *)data; 10048 struct port_info *pi; 10049 struct vi_info *vi; 10050 10051 if (port_id >= sc->params.nports) 10052 return (EINVAL); 10053 pi = sc->port[port_id]; 10054 if (pi == NULL) 10055 return (EIO); 10056 10057 /* MAC stats */ 10058 t4_clr_port_stats(sc, pi->tx_chan); 10059 pi->tx_parse_error = 0; 10060 pi->tnl_cong_drops = 0; 10061 mtx_lock(&sc->reg_lock); 10062 for_each_vi(pi, v, vi) { 10063 if (vi->flags & VI_INIT_DONE) 10064 t4_clr_vi_stats(sc, vi->vin); 10065 } 10066 bg_map = pi->mps_bg_map; 10067 v = 0; /* reuse */ 10068 while (bg_map) { 10069 i = ffs(bg_map) - 1; 10070 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 10071 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 10072 bg_map &= ~(1 << i); 10073 } 10074 mtx_unlock(&sc->reg_lock); 10075 10076 /* 10077 * Since this command accepts a port, clear stats for 10078 * all VIs on this port. 10079 */ 10080 for_each_vi(pi, v, vi) { 10081 if (vi->flags & VI_INIT_DONE) { 10082 struct sge_rxq *rxq; 10083 struct sge_txq *txq; 10084 struct sge_wrq *wrq; 10085 10086 for_each_rxq(vi, i, rxq) { 10087 #if defined(INET) || defined(INET6) 10088 rxq->lro.lro_queued = 0; 10089 rxq->lro.lro_flushed = 0; 10090 #endif 10091 rxq->rxcsum = 0; 10092 rxq->vlan_extraction = 0; 10093 } 10094 10095 for_each_txq(vi, i, txq) { 10096 txq->txcsum = 0; 10097 txq->tso_wrs = 0; 10098 txq->vlan_insertion = 0; 10099 txq->imm_wrs = 0; 10100 txq->sgl_wrs = 0; 10101 txq->txpkt_wrs = 0; 10102 txq->txpkts0_wrs = 0; 10103 txq->txpkts1_wrs = 0; 10104 txq->txpkts0_pkts = 0; 10105 txq->txpkts1_pkts = 0; 10106 txq->raw_wrs = 0; 10107 mp_ring_reset_stats(txq->r); 10108 } 10109 10110 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10111 /* nothing to clear for each ofld_rxq */ 10112 10113 for_each_ofld_txq(vi, i, wrq) { 10114 wrq->tx_wrs_direct = 0; 10115 wrq->tx_wrs_copied = 0; 10116 } 10117 #endif 10118 10119 if (IS_MAIN_VI(vi)) { 10120 wrq = &sc->sge.ctrlq[pi->port_id]; 10121 wrq->tx_wrs_direct = 0; 10122 wrq->tx_wrs_copied = 0; 10123 } 10124 } 10125 } 10126 break; 10127 } 10128 case CHELSIO_T4_SCHED_CLASS: 10129 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 10130 break; 10131 case CHELSIO_T4_SCHED_QUEUE: 10132 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 10133 break; 10134 case CHELSIO_T4_GET_TRACER: 10135 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 10136 break; 10137 case CHELSIO_T4_SET_TRACER: 10138 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 10139 break; 10140 case CHELSIO_T4_LOAD_CFG: 10141 rc = load_cfg(sc, (struct t4_data *)data); 10142 break; 10143 case CHELSIO_T4_LOAD_BOOT: 10144 rc = load_boot(sc, (struct t4_bootrom *)data); 10145 break; 10146 case CHELSIO_T4_LOAD_BOOTCFG: 10147 rc = load_bootcfg(sc, (struct t4_data *)data); 10148 break; 10149 case CHELSIO_T4_CUDBG_DUMP: 10150 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 10151 break; 10152 case CHELSIO_T4_SET_OFLD_POLICY: 10153 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 10154 break; 10155 default: 10156 rc = ENOTTY; 10157 } 10158 10159 return (rc); 10160 } 10161 10162 #ifdef TCP_OFFLOAD 10163 static int 10164 toe_capability(struct vi_info *vi, int enable) 10165 { 10166 int rc; 10167 struct port_info *pi = vi->pi; 10168 struct adapter *sc = pi->adapter; 10169 10170 ASSERT_SYNCHRONIZED_OP(sc); 10171 10172 if (!is_offload(sc)) 10173 return (ENODEV); 10174 10175 if (enable) { 10176 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 10177 /* TOE is already enabled. */ 10178 return (0); 10179 } 10180 10181 /* 10182 * We need the port's queues around so that we're able to send 10183 * and receive CPLs to/from the TOE even if the ifnet for this 10184 * port has never been UP'd administratively. 10185 */ 10186 if (!(vi->flags & VI_INIT_DONE)) { 10187 rc = vi_full_init(vi); 10188 if (rc) 10189 return (rc); 10190 } 10191 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 10192 rc = vi_full_init(&pi->vi[0]); 10193 if (rc) 10194 return (rc); 10195 } 10196 10197 if (isset(&sc->offload_map, pi->port_id)) { 10198 /* TOE is enabled on another VI of this port. */ 10199 pi->uld_vis++; 10200 return (0); 10201 } 10202 10203 if (!uld_active(sc, ULD_TOM)) { 10204 rc = t4_activate_uld(sc, ULD_TOM); 10205 if (rc == EAGAIN) { 10206 log(LOG_WARNING, 10207 "You must kldload t4_tom.ko before trying " 10208 "to enable TOE on a cxgbe interface.\n"); 10209 } 10210 if (rc != 0) 10211 return (rc); 10212 KASSERT(sc->tom_softc != NULL, 10213 ("%s: TOM activated but softc NULL", __func__)); 10214 KASSERT(uld_active(sc, ULD_TOM), 10215 ("%s: TOM activated but flag not set", __func__)); 10216 } 10217 10218 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 10219 if (!uld_active(sc, ULD_IWARP)) 10220 (void) t4_activate_uld(sc, ULD_IWARP); 10221 if (!uld_active(sc, ULD_ISCSI)) 10222 (void) t4_activate_uld(sc, ULD_ISCSI); 10223 10224 pi->uld_vis++; 10225 setbit(&sc->offload_map, pi->port_id); 10226 } else { 10227 pi->uld_vis--; 10228 10229 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 10230 return (0); 10231 10232 KASSERT(uld_active(sc, ULD_TOM), 10233 ("%s: TOM never initialized?", __func__)); 10234 clrbit(&sc->offload_map, pi->port_id); 10235 } 10236 10237 return (0); 10238 } 10239 10240 /* 10241 * Add an upper layer driver to the global list. 10242 */ 10243 int 10244 t4_register_uld(struct uld_info *ui) 10245 { 10246 int rc = 0; 10247 struct uld_info *u; 10248 10249 sx_xlock(&t4_uld_list_lock); 10250 SLIST_FOREACH(u, &t4_uld_list, link) { 10251 if (u->uld_id == ui->uld_id) { 10252 rc = EEXIST; 10253 goto done; 10254 } 10255 } 10256 10257 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 10258 ui->refcount = 0; 10259 done: 10260 sx_xunlock(&t4_uld_list_lock); 10261 return (rc); 10262 } 10263 10264 int 10265 t4_unregister_uld(struct uld_info *ui) 10266 { 10267 int rc = EINVAL; 10268 struct uld_info *u; 10269 10270 sx_xlock(&t4_uld_list_lock); 10271 10272 SLIST_FOREACH(u, &t4_uld_list, link) { 10273 if (u == ui) { 10274 if (ui->refcount > 0) { 10275 rc = EBUSY; 10276 goto done; 10277 } 10278 10279 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 10280 rc = 0; 10281 goto done; 10282 } 10283 } 10284 done: 10285 sx_xunlock(&t4_uld_list_lock); 10286 return (rc); 10287 } 10288 10289 int 10290 t4_activate_uld(struct adapter *sc, int id) 10291 { 10292 int rc; 10293 struct uld_info *ui; 10294 10295 ASSERT_SYNCHRONIZED_OP(sc); 10296 10297 if (id < 0 || id > ULD_MAX) 10298 return (EINVAL); 10299 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 10300 10301 sx_slock(&t4_uld_list_lock); 10302 10303 SLIST_FOREACH(ui, &t4_uld_list, link) { 10304 if (ui->uld_id == id) { 10305 if (!(sc->flags & FULL_INIT_DONE)) { 10306 rc = adapter_full_init(sc); 10307 if (rc != 0) 10308 break; 10309 } 10310 10311 rc = ui->activate(sc); 10312 if (rc == 0) { 10313 setbit(&sc->active_ulds, id); 10314 ui->refcount++; 10315 } 10316 break; 10317 } 10318 } 10319 10320 sx_sunlock(&t4_uld_list_lock); 10321 10322 return (rc); 10323 } 10324 10325 int 10326 t4_deactivate_uld(struct adapter *sc, int id) 10327 { 10328 int rc; 10329 struct uld_info *ui; 10330 10331 ASSERT_SYNCHRONIZED_OP(sc); 10332 10333 if (id < 0 || id > ULD_MAX) 10334 return (EINVAL); 10335 rc = ENXIO; 10336 10337 sx_slock(&t4_uld_list_lock); 10338 10339 SLIST_FOREACH(ui, &t4_uld_list, link) { 10340 if (ui->uld_id == id) { 10341 rc = ui->deactivate(sc); 10342 if (rc == 0) { 10343 clrbit(&sc->active_ulds, id); 10344 ui->refcount--; 10345 } 10346 break; 10347 } 10348 } 10349 10350 sx_sunlock(&t4_uld_list_lock); 10351 10352 return (rc); 10353 } 10354 10355 int 10356 uld_active(struct adapter *sc, int uld_id) 10357 { 10358 10359 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 10360 10361 return (isset(&sc->active_ulds, uld_id)); 10362 } 10363 #endif 10364 10365 /* 10366 * t = ptr to tunable. 10367 * nc = number of CPUs. 10368 * c = compiled in default for that tunable. 10369 */ 10370 static void 10371 calculate_nqueues(int *t, int nc, const int c) 10372 { 10373 int nq; 10374 10375 if (*t > 0) 10376 return; 10377 nq = *t < 0 ? -*t : c; 10378 *t = min(nc, nq); 10379 } 10380 10381 /* 10382 * Come up with reasonable defaults for some of the tunables, provided they're 10383 * not set by the user (in which case we'll use the values as is). 10384 */ 10385 static void 10386 tweak_tunables(void) 10387 { 10388 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 10389 10390 if (t4_ntxq < 1) { 10391 #ifdef RSS 10392 t4_ntxq = rss_getnumbuckets(); 10393 #else 10394 calculate_nqueues(&t4_ntxq, nc, NTXQ); 10395 #endif 10396 } 10397 10398 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 10399 10400 if (t4_nrxq < 1) { 10401 #ifdef RSS 10402 t4_nrxq = rss_getnumbuckets(); 10403 #else 10404 calculate_nqueues(&t4_nrxq, nc, NRXQ); 10405 #endif 10406 } 10407 10408 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 10409 10410 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10411 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 10412 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 10413 #endif 10414 #ifdef TCP_OFFLOAD 10415 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 10416 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 10417 10418 if (t4_toecaps_allowed == -1) 10419 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 10420 10421 if (t4_rdmacaps_allowed == -1) { 10422 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 10423 FW_CAPS_CONFIG_RDMA_RDMAC; 10424 } 10425 10426 if (t4_iscsicaps_allowed == -1) { 10427 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 10428 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 10429 FW_CAPS_CONFIG_ISCSI_T10DIF; 10430 } 10431 10432 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 10433 t4_tmr_idx_ofld = TMR_IDX_OFLD; 10434 10435 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 10436 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 10437 #else 10438 if (t4_toecaps_allowed == -1) 10439 t4_toecaps_allowed = 0; 10440 10441 if (t4_rdmacaps_allowed == -1) 10442 t4_rdmacaps_allowed = 0; 10443 10444 if (t4_iscsicaps_allowed == -1) 10445 t4_iscsicaps_allowed = 0; 10446 #endif 10447 10448 #ifdef DEV_NETMAP 10449 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 10450 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 10451 #endif 10452 10453 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 10454 t4_tmr_idx = TMR_IDX; 10455 10456 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 10457 t4_pktc_idx = PKTC_IDX; 10458 10459 if (t4_qsize_txq < 128) 10460 t4_qsize_txq = 128; 10461 10462 if (t4_qsize_rxq < 128) 10463 t4_qsize_rxq = 128; 10464 while (t4_qsize_rxq & 7) 10465 t4_qsize_rxq++; 10466 10467 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 10468 10469 /* 10470 * Number of VIs to create per-port. The first VI is the "main" regular 10471 * VI for the port. The rest are additional virtual interfaces on the 10472 * same physical port. Note that the main VI does not have native 10473 * netmap support but the extra VIs do. 10474 * 10475 * Limit the number of VIs per port to the number of available 10476 * MAC addresses per port. 10477 */ 10478 if (t4_num_vis < 1) 10479 t4_num_vis = 1; 10480 if (t4_num_vis > nitems(vi_mac_funcs)) { 10481 t4_num_vis = nitems(vi_mac_funcs); 10482 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 10483 } 10484 10485 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 10486 pcie_relaxed_ordering = 1; 10487 #if defined(__i386__) || defined(__amd64__) 10488 if (cpu_vendor_id == CPU_VENDOR_INTEL) 10489 pcie_relaxed_ordering = 0; 10490 #endif 10491 } 10492 } 10493 10494 #ifdef DDB 10495 static void 10496 t4_dump_tcb(struct adapter *sc, int tid) 10497 { 10498 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 10499 10500 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 10501 save = t4_read_reg(sc, reg); 10502 base = sc->memwin[2].mw_base; 10503 10504 /* Dump TCB for the tid */ 10505 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 10506 tcb_addr += tid * TCB_SIZE; 10507 10508 if (is_t4(sc)) { 10509 pf = 0; 10510 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 10511 } else { 10512 pf = V_PFNUM(sc->pf); 10513 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 10514 } 10515 t4_write_reg(sc, reg, win_pos | pf); 10516 t4_read_reg(sc, reg); 10517 10518 off = tcb_addr - win_pos; 10519 for (i = 0; i < 4; i++) { 10520 uint32_t buf[8]; 10521 for (j = 0; j < 8; j++, off += 4) 10522 buf[j] = htonl(t4_read_reg(sc, base + off)); 10523 10524 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 10525 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 10526 buf[7]); 10527 } 10528 10529 t4_write_reg(sc, reg, save); 10530 t4_read_reg(sc, reg); 10531 } 10532 10533 static void 10534 t4_dump_devlog(struct adapter *sc) 10535 { 10536 struct devlog_params *dparams = &sc->params.devlog; 10537 struct fw_devlog_e e; 10538 int i, first, j, m, nentries, rc; 10539 uint64_t ftstamp = UINT64_MAX; 10540 10541 if (dparams->start == 0) { 10542 db_printf("devlog params not valid\n"); 10543 return; 10544 } 10545 10546 nentries = dparams->size / sizeof(struct fw_devlog_e); 10547 m = fwmtype_to_hwmtype(dparams->memtype); 10548 10549 /* Find the first entry. */ 10550 first = -1; 10551 for (i = 0; i < nentries && !db_pager_quit; i++) { 10552 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10553 sizeof(e), (void *)&e); 10554 if (rc != 0) 10555 break; 10556 10557 if (e.timestamp == 0) 10558 break; 10559 10560 e.timestamp = be64toh(e.timestamp); 10561 if (e.timestamp < ftstamp) { 10562 ftstamp = e.timestamp; 10563 first = i; 10564 } 10565 } 10566 10567 if (first == -1) 10568 return; 10569 10570 i = first; 10571 do { 10572 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10573 sizeof(e), (void *)&e); 10574 if (rc != 0) 10575 return; 10576 10577 if (e.timestamp == 0) 10578 return; 10579 10580 e.timestamp = be64toh(e.timestamp); 10581 e.seqno = be32toh(e.seqno); 10582 for (j = 0; j < 8; j++) 10583 e.params[j] = be32toh(e.params[j]); 10584 10585 db_printf("%10d %15ju %8s %8s ", 10586 e.seqno, e.timestamp, 10587 (e.level < nitems(devlog_level_strings) ? 10588 devlog_level_strings[e.level] : "UNKNOWN"), 10589 (e.facility < nitems(devlog_facility_strings) ? 10590 devlog_facility_strings[e.facility] : "UNKNOWN")); 10591 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10592 e.params[3], e.params[4], e.params[5], e.params[6], 10593 e.params[7]); 10594 10595 if (++i == nentries) 10596 i = 0; 10597 } while (i != first && !db_pager_quit); 10598 } 10599 10600 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10601 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10602 10603 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10604 { 10605 device_t dev; 10606 int t; 10607 bool valid; 10608 10609 valid = false; 10610 t = db_read_token(); 10611 if (t == tIDENT) { 10612 dev = device_lookup_by_name(db_tok_string); 10613 valid = true; 10614 } 10615 db_skip_to_eol(); 10616 if (!valid) { 10617 db_printf("usage: show t4 devlog <nexus>\n"); 10618 return; 10619 } 10620 10621 if (dev == NULL) { 10622 db_printf("device not found\n"); 10623 return; 10624 } 10625 10626 t4_dump_devlog(device_get_softc(dev)); 10627 } 10628 10629 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10630 { 10631 device_t dev; 10632 int radix, tid, t; 10633 bool valid; 10634 10635 valid = false; 10636 radix = db_radix; 10637 db_radix = 10; 10638 t = db_read_token(); 10639 if (t == tIDENT) { 10640 dev = device_lookup_by_name(db_tok_string); 10641 t = db_read_token(); 10642 if (t == tNUMBER) { 10643 tid = db_tok_number; 10644 valid = true; 10645 } 10646 } 10647 db_radix = radix; 10648 db_skip_to_eol(); 10649 if (!valid) { 10650 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10651 return; 10652 } 10653 10654 if (dev == NULL) { 10655 db_printf("device not found\n"); 10656 return; 10657 } 10658 if (tid < 0) { 10659 db_printf("invalid tid\n"); 10660 return; 10661 } 10662 10663 t4_dump_tcb(device_get_softc(dev), tid); 10664 } 10665 #endif 10666 10667 /* 10668 * Borrowed from cesa_prep_aes_key(). 10669 * 10670 * NB: The crypto engine wants the words in the decryption key in reverse 10671 * order. 10672 */ 10673 void 10674 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 10675 { 10676 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 10677 uint32_t *dkey; 10678 int i; 10679 10680 rijndaelKeySetupEnc(ek, enc_key, kbits); 10681 dkey = dec_key; 10682 dkey += (kbits / 8) / 4; 10683 10684 switch (kbits) { 10685 case 128: 10686 for (i = 0; i < 4; i++) 10687 *--dkey = htobe32(ek[4 * 10 + i]); 10688 break; 10689 case 192: 10690 for (i = 0; i < 2; i++) 10691 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10692 for (i = 0; i < 4; i++) 10693 *--dkey = htobe32(ek[4 * 12 + i]); 10694 break; 10695 case 256: 10696 for (i = 0; i < 4; i++) 10697 *--dkey = htobe32(ek[4 * 13 + i]); 10698 for (i = 0; i < 4; i++) 10699 *--dkey = htobe32(ek[4 * 14 + i]); 10700 break; 10701 } 10702 MPASS(dkey == dec_key); 10703 } 10704 10705 static struct sx mlu; /* mod load unload */ 10706 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10707 10708 static int 10709 mod_event(module_t mod, int cmd, void *arg) 10710 { 10711 int rc = 0; 10712 static int loaded = 0; 10713 10714 switch (cmd) { 10715 case MOD_LOAD: 10716 sx_xlock(&mlu); 10717 if (loaded++ == 0) { 10718 t4_sge_modload(); 10719 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10720 t4_filter_rpl, CPL_COOKIE_FILTER); 10721 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 10722 do_l2t_write_rpl, CPL_COOKIE_FILTER); 10723 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 10724 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 10725 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10726 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 10727 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 10728 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10729 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10730 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10731 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 10732 do_smt_write_rpl); 10733 sx_init(&t4_list_lock, "T4/T5 adapters"); 10734 SLIST_INIT(&t4_list); 10735 callout_init(&fatal_callout, 1); 10736 #ifdef TCP_OFFLOAD 10737 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10738 SLIST_INIT(&t4_uld_list); 10739 #endif 10740 #ifdef INET6 10741 t4_clip_modload(); 10742 #endif 10743 t4_tracer_modload(); 10744 tweak_tunables(); 10745 } 10746 sx_xunlock(&mlu); 10747 break; 10748 10749 case MOD_UNLOAD: 10750 sx_xlock(&mlu); 10751 if (--loaded == 0) { 10752 int tries; 10753 10754 sx_slock(&t4_list_lock); 10755 if (!SLIST_EMPTY(&t4_list)) { 10756 rc = EBUSY; 10757 sx_sunlock(&t4_list_lock); 10758 goto done_unload; 10759 } 10760 #ifdef TCP_OFFLOAD 10761 sx_slock(&t4_uld_list_lock); 10762 if (!SLIST_EMPTY(&t4_uld_list)) { 10763 rc = EBUSY; 10764 sx_sunlock(&t4_uld_list_lock); 10765 sx_sunlock(&t4_list_lock); 10766 goto done_unload; 10767 } 10768 #endif 10769 tries = 0; 10770 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10771 uprintf("%ju clusters with custom free routine " 10772 "still is use.\n", t4_sge_extfree_refs()); 10773 pause("t4unload", 2 * hz); 10774 } 10775 #ifdef TCP_OFFLOAD 10776 sx_sunlock(&t4_uld_list_lock); 10777 #endif 10778 sx_sunlock(&t4_list_lock); 10779 10780 if (t4_sge_extfree_refs() == 0) { 10781 t4_tracer_modunload(); 10782 #ifdef INET6 10783 t4_clip_modunload(); 10784 #endif 10785 #ifdef TCP_OFFLOAD 10786 sx_destroy(&t4_uld_list_lock); 10787 #endif 10788 sx_destroy(&t4_list_lock); 10789 t4_sge_modunload(); 10790 loaded = 0; 10791 } else { 10792 rc = EBUSY; 10793 loaded++; /* undo earlier decrement */ 10794 } 10795 } 10796 done_unload: 10797 sx_xunlock(&mlu); 10798 break; 10799 } 10800 10801 return (rc); 10802 } 10803 10804 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10805 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10806 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10807 10808 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10809 MODULE_VERSION(t4nex, 1); 10810 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10811 #ifdef DEV_NETMAP 10812 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10813 #endif /* DEV_NETMAP */ 10814 10815 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10816 MODULE_VERSION(t5nex, 1); 10817 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10818 #ifdef DEV_NETMAP 10819 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10820 #endif /* DEV_NETMAP */ 10821 10822 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10823 MODULE_VERSION(t6nex, 1); 10824 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10825 #ifdef DEV_NETMAP 10826 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10827 #endif /* DEV_NETMAP */ 10828 10829 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10830 MODULE_VERSION(cxgbe, 1); 10831 10832 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10833 MODULE_VERSION(cxl, 1); 10834 10835 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10836 MODULE_VERSION(cc, 1); 10837 10838 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10839 MODULE_VERSION(vcxgbe, 1); 10840 10841 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10842 MODULE_VERSION(vcxl, 1); 10843 10844 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10845 MODULE_VERSION(vcc, 1); 10846