1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ddb.h" 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_rss.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/priv.h> 39 #include <sys/kernel.h> 40 #include <sys/bus.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pci_private.h> 49 #include <sys/firmware.h> 50 #include <sys/sbuf.h> 51 #include <sys/smp.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_types.h> 58 #include <net/if_dl.h> 59 #include <net/if_vlan_var.h> 60 #ifdef RSS 61 #include <net/rss_config.h> 62 #endif 63 #if defined(__i386__) || defined(__amd64__) 64 #include <vm/vm.h> 65 #include <vm/pmap.h> 66 #endif 67 #ifdef DDB 68 #include <ddb/ddb.h> 69 #include <ddb/db_lex.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_msg.h" 74 #include "common/t4_regs.h" 75 #include "common/t4_regs_values.h" 76 #include "cudbg/cudbg.h" 77 #include "t4_ioctl.h" 78 #include "t4_l2t.h" 79 #include "t4_mp_ring.h" 80 #include "t4_if.h" 81 82 /* T4 bus driver interface */ 83 static int t4_probe(device_t); 84 static int t4_attach(device_t); 85 static int t4_detach(device_t); 86 static int t4_ready(device_t); 87 static int t4_read_port_device(device_t, int, device_t *); 88 static device_method_t t4_methods[] = { 89 DEVMETHOD(device_probe, t4_probe), 90 DEVMETHOD(device_attach, t4_attach), 91 DEVMETHOD(device_detach, t4_detach), 92 93 DEVMETHOD(t4_is_main_ready, t4_ready), 94 DEVMETHOD(t4_read_port_device, t4_read_port_device), 95 96 DEVMETHOD_END 97 }; 98 static driver_t t4_driver = { 99 "t4nex", 100 t4_methods, 101 sizeof(struct adapter) 102 }; 103 104 105 /* T4 port (cxgbe) interface */ 106 static int cxgbe_probe(device_t); 107 static int cxgbe_attach(device_t); 108 static int cxgbe_detach(device_t); 109 device_method_t cxgbe_methods[] = { 110 DEVMETHOD(device_probe, cxgbe_probe), 111 DEVMETHOD(device_attach, cxgbe_attach), 112 DEVMETHOD(device_detach, cxgbe_detach), 113 { 0, 0 } 114 }; 115 static driver_t cxgbe_driver = { 116 "cxgbe", 117 cxgbe_methods, 118 sizeof(struct port_info) 119 }; 120 121 /* T4 VI (vcxgbe) interface */ 122 static int vcxgbe_probe(device_t); 123 static int vcxgbe_attach(device_t); 124 static int vcxgbe_detach(device_t); 125 static device_method_t vcxgbe_methods[] = { 126 DEVMETHOD(device_probe, vcxgbe_probe), 127 DEVMETHOD(device_attach, vcxgbe_attach), 128 DEVMETHOD(device_detach, vcxgbe_detach), 129 { 0, 0 } 130 }; 131 static driver_t vcxgbe_driver = { 132 "vcxgbe", 133 vcxgbe_methods, 134 sizeof(struct vi_info) 135 }; 136 137 static d_ioctl_t t4_ioctl; 138 139 static struct cdevsw t4_cdevsw = { 140 .d_version = D_VERSION, 141 .d_ioctl = t4_ioctl, 142 .d_name = "t4nex", 143 }; 144 145 /* T5 bus driver interface */ 146 static int t5_probe(device_t); 147 static device_method_t t5_methods[] = { 148 DEVMETHOD(device_probe, t5_probe), 149 DEVMETHOD(device_attach, t4_attach), 150 DEVMETHOD(device_detach, t4_detach), 151 152 DEVMETHOD(t4_is_main_ready, t4_ready), 153 DEVMETHOD(t4_read_port_device, t4_read_port_device), 154 155 DEVMETHOD_END 156 }; 157 static driver_t t5_driver = { 158 "t5nex", 159 t5_methods, 160 sizeof(struct adapter) 161 }; 162 163 164 /* T5 port (cxl) interface */ 165 static driver_t cxl_driver = { 166 "cxl", 167 cxgbe_methods, 168 sizeof(struct port_info) 169 }; 170 171 /* T5 VI (vcxl) interface */ 172 static driver_t vcxl_driver = { 173 "vcxl", 174 vcxgbe_methods, 175 sizeof(struct vi_info) 176 }; 177 178 /* T6 bus driver interface */ 179 static int t6_probe(device_t); 180 static device_method_t t6_methods[] = { 181 DEVMETHOD(device_probe, t6_probe), 182 DEVMETHOD(device_attach, t4_attach), 183 DEVMETHOD(device_detach, t4_detach), 184 185 DEVMETHOD(t4_is_main_ready, t4_ready), 186 DEVMETHOD(t4_read_port_device, t4_read_port_device), 187 188 DEVMETHOD_END 189 }; 190 static driver_t t6_driver = { 191 "t6nex", 192 t6_methods, 193 sizeof(struct adapter) 194 }; 195 196 197 /* T6 port (cc) interface */ 198 static driver_t cc_driver = { 199 "cc", 200 cxgbe_methods, 201 sizeof(struct port_info) 202 }; 203 204 /* T6 VI (vcc) interface */ 205 static driver_t vcc_driver = { 206 "vcc", 207 vcxgbe_methods, 208 sizeof(struct vi_info) 209 }; 210 211 /* ifnet + media interface */ 212 static void cxgbe_init(void *); 213 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 214 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 215 static void cxgbe_qflush(struct ifnet *); 216 static int cxgbe_media_change(struct ifnet *); 217 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 218 219 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 220 221 /* 222 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 223 * then ADAPTER_LOCK, then t4_uld_list_lock. 224 */ 225 static struct sx t4_list_lock; 226 SLIST_HEAD(, adapter) t4_list; 227 #ifdef TCP_OFFLOAD 228 static struct sx t4_uld_list_lock; 229 SLIST_HEAD(, uld_info) t4_uld_list; 230 #endif 231 232 /* 233 * Tunables. See tweak_tunables() too. 234 * 235 * Each tunable is set to a default value here if it's known at compile-time. 236 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 237 * provide a reasonable default (upto n) when the driver is loaded. 238 * 239 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 240 * T5 are under hw.cxl. 241 */ 242 243 /* 244 * Number of queues for tx and rx, NIC and offload. 245 */ 246 #define NTXQ 16 247 int t4_ntxq = -NTXQ; 248 TUNABLE_INT("hw.cxgbe.ntxq", &t4_ntxq); 249 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 250 251 #define NRXQ 8 252 int t4_nrxq = -NRXQ; 253 TUNABLE_INT("hw.cxgbe.nrxq", &t4_nrxq); 254 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 255 256 #define NTXQ_VI 1 257 static int t4_ntxq_vi = -NTXQ_VI; 258 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi); 259 260 #define NRXQ_VI 1 261 static int t4_nrxq_vi = -NRXQ_VI; 262 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi); 263 264 static int t4_rsrv_noflowq = 0; 265 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq); 266 267 #ifdef TCP_OFFLOAD 268 #define NOFLDTXQ 8 269 static int t4_nofldtxq = -NOFLDTXQ; 270 TUNABLE_INT("hw.cxgbe.nofldtxq", &t4_nofldtxq); 271 272 #define NOFLDRXQ 2 273 static int t4_nofldrxq = -NOFLDRXQ; 274 TUNABLE_INT("hw.cxgbe.nofldrxq", &t4_nofldrxq); 275 276 #define NOFLDTXQ_VI 1 277 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 278 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi); 279 280 #define NOFLDRXQ_VI 1 281 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 282 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi); 283 284 #define TMR_IDX_OFLD 1 285 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 286 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_ofld", &t4_tmr_idx_ofld); 287 288 #define PKTC_IDX_OFLD (-1) 289 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 290 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_ofld", &t4_pktc_idx_ofld); 291 292 /* 0 means chip/fw default, non-zero number is value in microseconds */ 293 static u_long t4_toe_keepalive_idle = 0; 294 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_idle", &t4_toe_keepalive_idle); 295 296 /* 0 means chip/fw default, non-zero number is value in microseconds */ 297 static u_long t4_toe_keepalive_interval = 0; 298 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_interval", &t4_toe_keepalive_interval); 299 300 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 301 static int t4_toe_keepalive_count = 0; 302 TUNABLE_INT("hw.cxgbe.toe.keepalive_count", &t4_toe_keepalive_count); 303 304 /* 0 means chip/fw default, non-zero number is value in microseconds */ 305 static u_long t4_toe_rexmt_min = 0; 306 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_min", &t4_toe_rexmt_min); 307 308 /* 0 means chip/fw default, non-zero number is value in microseconds */ 309 static u_long t4_toe_rexmt_max = 0; 310 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_max", &t4_toe_rexmt_max); 311 312 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 313 static int t4_toe_rexmt_count = 0; 314 TUNABLE_INT("hw.cxgbe.toe.rexmt_count", &t4_toe_rexmt_count); 315 316 /* -1 means chip/fw default, other values are raw backoff values to use */ 317 static int t4_toe_rexmt_backoff[16] = { 318 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 319 }; 320 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.0", &t4_toe_rexmt_backoff[0]); 321 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.1", &t4_toe_rexmt_backoff[1]); 322 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.2", &t4_toe_rexmt_backoff[2]); 323 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.3", &t4_toe_rexmt_backoff[3]); 324 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.4", &t4_toe_rexmt_backoff[4]); 325 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.5", &t4_toe_rexmt_backoff[5]); 326 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.6", &t4_toe_rexmt_backoff[6]); 327 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.7", &t4_toe_rexmt_backoff[7]); 328 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.8", &t4_toe_rexmt_backoff[8]); 329 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.9", &t4_toe_rexmt_backoff[9]); 330 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.10", &t4_toe_rexmt_backoff[10]); 331 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.11", &t4_toe_rexmt_backoff[11]); 332 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.12", &t4_toe_rexmt_backoff[12]); 333 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.13", &t4_toe_rexmt_backoff[13]); 334 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.14", &t4_toe_rexmt_backoff[14]); 335 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.15", &t4_toe_rexmt_backoff[15]); 336 #endif 337 338 #ifdef DEV_NETMAP 339 #define NNMTXQ_VI 2 340 static int t4_nnmtxq_vi = -NNMTXQ_VI; 341 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi); 342 343 #define NNMRXQ_VI 2 344 static int t4_nnmrxq_vi = -NNMRXQ_VI; 345 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi); 346 #endif 347 348 /* 349 * Holdoff parameters for ports. 350 */ 351 #define TMR_IDX 1 352 int t4_tmr_idx = TMR_IDX; 353 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx", &t4_tmr_idx); 354 355 #define PKTC_IDX (-1) 356 int t4_pktc_idx = PKTC_IDX; 357 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx", &t4_pktc_idx); 358 359 /* 360 * Size (# of entries) of each tx and rx queue. 361 */ 362 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 363 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 364 365 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 366 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 367 368 /* 369 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 370 */ 371 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 372 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 373 374 /* 375 * Configuration file. 376 */ 377 #define DEFAULT_CF "default" 378 #define FLASH_CF "flash" 379 #define UWIRE_CF "uwire" 380 #define FPGA_CF "fpga" 381 static char t4_cfg_file[32] = DEFAULT_CF; 382 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 383 384 /* 385 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively). 386 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 387 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 388 * mark or when signalled to do so, 0 to never emit PAUSE. 389 */ 390 static int t4_pause_settings = PAUSE_TX | PAUSE_RX; 391 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings); 392 393 /* 394 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS, 395 * FEC_RESERVED respectively). 396 * -1 to run with the firmware default. 397 * 0 to disable FEC. 398 */ 399 static int t4_fec = -1; 400 TUNABLE_INT("hw.cxgbe.fec", &t4_fec); 401 402 /* 403 * Link autonegotiation. 404 * -1 to run with the firmware default. 405 * 0 to disable. 406 * 1 to enable. 407 */ 408 static int t4_autoneg = -1; 409 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg); 410 411 /* 412 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 413 * encouraged respectively). 414 */ 415 static unsigned int t4_fw_install = 1; 416 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 417 418 /* 419 * ASIC features that will be used. Disable the ones you don't want so that the 420 * chip resources aren't wasted on features that will not be used. 421 */ 422 static int t4_nbmcaps_allowed = 0; 423 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed); 424 425 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 426 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 427 428 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 429 FW_CAPS_CONFIG_SWITCH_EGRESS; 430 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed); 431 432 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC; 433 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 434 435 static int t4_toecaps_allowed = -1; 436 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 437 438 static int t4_rdmacaps_allowed = -1; 439 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 440 441 static int t4_cryptocaps_allowed = -1; 442 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed); 443 444 static int t4_iscsicaps_allowed = -1; 445 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 446 447 static int t4_fcoecaps_allowed = 0; 448 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 449 450 static int t5_write_combine = 0; 451 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 452 453 static int t4_num_vis = 1; 454 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis); 455 456 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 457 static int vi_mac_funcs[] = { 458 FW_VI_FUNC_ETH, 459 FW_VI_FUNC_OFLD, 460 FW_VI_FUNC_IWARP, 461 FW_VI_FUNC_OPENISCSI, 462 FW_VI_FUNC_OPENFCOE, 463 FW_VI_FUNC_FOISCSI, 464 FW_VI_FUNC_FOFCOE, 465 }; 466 467 struct intrs_and_queues { 468 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 469 uint16_t num_vis; /* number of VIs for each port */ 470 uint16_t nirq; /* Total # of vectors */ 471 uint16_t intr_flags; /* Interrupt flags for each port */ 472 uint16_t ntxq; /* # of NIC txq's for each port */ 473 uint16_t nrxq; /* # of NIC rxq's for each port */ 474 uint16_t nofldtxq; /* # of TOE txq's for each port */ 475 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 476 477 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 478 uint16_t ntxq_vi; /* # of NIC txq's */ 479 uint16_t nrxq_vi; /* # of NIC rxq's */ 480 uint16_t nofldtxq_vi; /* # of TOE txq's */ 481 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 482 uint16_t nnmtxq_vi; /* # of netmap txq's */ 483 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 484 }; 485 486 struct filter_entry { 487 uint32_t valid:1; /* filter allocated and valid */ 488 uint32_t locked:1; /* filter is administratively locked */ 489 uint32_t pending:1; /* filter action is pending firmware reply */ 490 uint32_t smtidx:8; /* Source MAC Table index for smac */ 491 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 492 493 struct t4_filter_specification fs; 494 }; 495 496 static void setup_memwin(struct adapter *); 497 static void position_memwin(struct adapter *, int, uint32_t); 498 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 499 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *, 500 int); 501 static inline int write_via_memwin(struct adapter *, int, uint32_t, 502 const uint32_t *, int); 503 static int validate_mem_range(struct adapter *, uint32_t, int); 504 static int fwmtype_to_hwmtype(int); 505 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 506 uint32_t *); 507 static int fixup_devlog_params(struct adapter *); 508 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 509 static int prep_firmware(struct adapter *); 510 static int partition_resources(struct adapter *, const struct firmware *, 511 const char *); 512 static int get_params__pre_init(struct adapter *); 513 static int get_params__post_init(struct adapter *); 514 static int set_params__post_init(struct adapter *); 515 static void t4_set_desc(struct adapter *); 516 static void build_medialist(struct port_info *, struct ifmedia *); 517 static void init_l1cfg(struct port_info *); 518 static int cxgbe_init_synchronized(struct vi_info *); 519 static int cxgbe_uninit_synchronized(struct vi_info *); 520 static void quiesce_txq(struct adapter *, struct sge_txq *); 521 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 522 static void quiesce_iq(struct adapter *, struct sge_iq *); 523 static void quiesce_fl(struct adapter *, struct sge_fl *); 524 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 525 driver_intr_t *, void *, char *); 526 static int t4_free_irq(struct adapter *, struct irq *); 527 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 528 static void vi_refresh_stats(struct adapter *, struct vi_info *); 529 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 530 static void cxgbe_tick(void *); 531 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 532 static void cxgbe_sysctls(struct port_info *); 533 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 534 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 535 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 536 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 537 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 538 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 539 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 540 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 541 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 542 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 543 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 544 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 545 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 546 #ifdef SBUF_DRAIN 547 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 548 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 549 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 550 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 551 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 552 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 553 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 554 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 555 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 556 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 557 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 558 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 559 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 560 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 561 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 562 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 563 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 564 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 565 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 566 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 567 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 568 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 569 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 570 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 571 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 572 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 573 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 574 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 575 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 576 #endif 577 #ifdef TCP_OFFLOAD 578 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 579 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 580 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 581 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 582 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 583 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 584 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 585 #endif 586 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t); 587 static uint32_t mode_to_fconf(uint32_t); 588 static uint32_t mode_to_iconf(uint32_t); 589 static int check_fspec_against_fconf_iconf(struct adapter *, 590 struct t4_filter_specification *); 591 static int get_filter_mode(struct adapter *, uint32_t *); 592 static int set_filter_mode(struct adapter *, uint32_t); 593 static inline uint64_t get_filter_hits(struct adapter *, uint32_t); 594 static int get_filter(struct adapter *, struct t4_filter *); 595 static int set_filter(struct adapter *, struct t4_filter *); 596 static int del_filter(struct adapter *, struct t4_filter *); 597 static void clear_filter(struct filter_entry *); 598 static int set_filter_wr(struct adapter *, int); 599 static int del_filter_wr(struct adapter *, int); 600 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *, 601 struct mbuf *); 602 static int get_sge_context(struct adapter *, struct t4_sge_context *); 603 static int load_fw(struct adapter *, struct t4_data *); 604 static int load_cfg(struct adapter *, struct t4_data *); 605 static int load_boot(struct adapter *, struct t4_bootrom *); 606 static int load_bootcfg(struct adapter *, struct t4_data *); 607 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 608 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 609 static int read_i2c(struct adapter *, struct t4_i2c_data *); 610 #ifdef TCP_OFFLOAD 611 static int toe_capability(struct vi_info *, int); 612 #endif 613 static int mod_event(module_t, int, void *); 614 static int notify_siblings(device_t, int); 615 616 struct { 617 uint16_t device; 618 char *desc; 619 } t4_pciids[] = { 620 {0xa000, "Chelsio Terminator 4 FPGA"}, 621 {0x4400, "Chelsio T440-dbg"}, 622 {0x4401, "Chelsio T420-CR"}, 623 {0x4402, "Chelsio T422-CR"}, 624 {0x4403, "Chelsio T440-CR"}, 625 {0x4404, "Chelsio T420-BCH"}, 626 {0x4405, "Chelsio T440-BCH"}, 627 {0x4406, "Chelsio T440-CH"}, 628 {0x4407, "Chelsio T420-SO"}, 629 {0x4408, "Chelsio T420-CX"}, 630 {0x4409, "Chelsio T420-BT"}, 631 {0x440a, "Chelsio T404-BT"}, 632 {0x440e, "Chelsio T440-LP-CR"}, 633 }, t5_pciids[] = { 634 {0xb000, "Chelsio Terminator 5 FPGA"}, 635 {0x5400, "Chelsio T580-dbg"}, 636 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 637 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 638 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 639 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 640 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 641 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 642 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 643 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 644 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 645 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 646 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 647 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 648 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 649 #ifdef notyet 650 {0x5404, "Chelsio T520-BCH"}, 651 {0x5405, "Chelsio T540-BCH"}, 652 {0x5406, "Chelsio T540-CH"}, 653 {0x5408, "Chelsio T520-CX"}, 654 {0x540b, "Chelsio B520-SR"}, 655 {0x540c, "Chelsio B504-BT"}, 656 {0x540f, "Chelsio Amsterdam"}, 657 {0x5413, "Chelsio T580-CHR"}, 658 #endif 659 }, t6_pciids[] = { 660 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 661 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 662 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 663 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 664 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 665 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 666 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 667 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 668 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 669 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 670 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 671 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 672 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 673 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 674 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 675 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 676 677 /* Custom */ 678 {0x6480, "Chelsio T6225 80"}, 679 {0x6481, "Chelsio T62100 81"}, 680 {0x6484, "Chelsio T62100 84"}, 681 }; 682 683 #ifdef TCP_OFFLOAD 684 /* 685 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 686 * exactly the same for both rxq and ofld_rxq. 687 */ 688 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 689 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 690 #endif 691 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 692 693 static int 694 t4_probe(device_t dev) 695 { 696 int i; 697 uint16_t v = pci_get_vendor(dev); 698 uint16_t d = pci_get_device(dev); 699 uint8_t f = pci_get_function(dev); 700 701 if (v != PCI_VENDOR_ID_CHELSIO) 702 return (ENXIO); 703 704 /* Attach only to PF0 of the FPGA */ 705 if (d == 0xa000 && f != 0) 706 return (ENXIO); 707 708 for (i = 0; i < nitems(t4_pciids); i++) { 709 if (d == t4_pciids[i].device) { 710 device_set_desc(dev, t4_pciids[i].desc); 711 return (BUS_PROBE_DEFAULT); 712 } 713 } 714 715 return (ENXIO); 716 } 717 718 static int 719 t5_probe(device_t dev) 720 { 721 int i; 722 uint16_t v = pci_get_vendor(dev); 723 uint16_t d = pci_get_device(dev); 724 uint8_t f = pci_get_function(dev); 725 726 if (v != PCI_VENDOR_ID_CHELSIO) 727 return (ENXIO); 728 729 /* Attach only to PF0 of the FPGA */ 730 if (d == 0xb000 && f != 0) 731 return (ENXIO); 732 733 for (i = 0; i < nitems(t5_pciids); i++) { 734 if (d == t5_pciids[i].device) { 735 device_set_desc(dev, t5_pciids[i].desc); 736 return (BUS_PROBE_DEFAULT); 737 } 738 } 739 740 return (ENXIO); 741 } 742 743 static int 744 t6_probe(device_t dev) 745 { 746 int i; 747 uint16_t v = pci_get_vendor(dev); 748 uint16_t d = pci_get_device(dev); 749 750 if (v != PCI_VENDOR_ID_CHELSIO) 751 return (ENXIO); 752 753 for (i = 0; i < nitems(t6_pciids); i++) { 754 if (d == t6_pciids[i].device) { 755 device_set_desc(dev, t6_pciids[i].desc); 756 return (BUS_PROBE_DEFAULT); 757 } 758 } 759 760 return (ENXIO); 761 } 762 763 static void 764 t5_attribute_workaround(device_t dev) 765 { 766 device_t root_port; 767 uint32_t v; 768 769 /* 770 * The T5 chips do not properly echo the No Snoop and Relaxed 771 * Ordering attributes when replying to a TLP from a Root 772 * Port. As a workaround, find the parent Root Port and 773 * disable No Snoop and Relaxed Ordering. Note that this 774 * affects all devices under this root port. 775 */ 776 root_port = pci_find_pcie_root_port(dev); 777 if (root_port == NULL) { 778 device_printf(dev, "Unable to find parent root port\n"); 779 return; 780 } 781 782 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 783 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 784 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 785 0) 786 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 787 device_get_nameunit(root_port)); 788 } 789 790 static const struct devnames devnames[] = { 791 { 792 .nexus_name = "t4nex", 793 .ifnet_name = "cxgbe", 794 .vi_ifnet_name = "vcxgbe", 795 .pf03_drv_name = "t4iov", 796 .vf_nexus_name = "t4vf", 797 .vf_ifnet_name = "cxgbev" 798 }, { 799 .nexus_name = "t5nex", 800 .ifnet_name = "cxl", 801 .vi_ifnet_name = "vcxl", 802 .pf03_drv_name = "t5iov", 803 .vf_nexus_name = "t5vf", 804 .vf_ifnet_name = "cxlv" 805 }, { 806 .nexus_name = "t6nex", 807 .ifnet_name = "cc", 808 .vi_ifnet_name = "vcc", 809 .pf03_drv_name = "t6iov", 810 .vf_nexus_name = "t6vf", 811 .vf_ifnet_name = "ccv" 812 } 813 }; 814 815 void 816 t4_init_devnames(struct adapter *sc) 817 { 818 int id; 819 820 id = chip_id(sc); 821 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 822 sc->names = &devnames[id - CHELSIO_T4]; 823 else { 824 device_printf(sc->dev, "chip id %d is not supported.\n", id); 825 sc->names = NULL; 826 } 827 } 828 829 static int 830 t4_attach(device_t dev) 831 { 832 struct adapter *sc; 833 int rc = 0, i, j, rqidx, tqidx, nports; 834 struct make_dev_args mda; 835 struct intrs_and_queues iaq; 836 struct sge *s; 837 uint8_t *buf; 838 #ifdef TCP_OFFLOAD 839 int ofld_rqidx, ofld_tqidx; 840 #endif 841 #ifdef DEV_NETMAP 842 int nm_rqidx, nm_tqidx; 843 #endif 844 int num_vis; 845 846 sc = device_get_softc(dev); 847 sc->dev = dev; 848 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 849 850 if ((pci_get_device(dev) & 0xff00) == 0x5400) 851 t5_attribute_workaround(dev); 852 pci_enable_busmaster(dev); 853 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 854 uint32_t v; 855 856 pci_set_max_read_req(dev, 4096); 857 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 858 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 859 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 860 861 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 862 } 863 864 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 865 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 866 sc->traceq = -1; 867 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 868 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 869 device_get_nameunit(dev)); 870 871 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 872 device_get_nameunit(dev)); 873 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 874 t4_add_adapter(sc); 875 876 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 877 TAILQ_INIT(&sc->sfl); 878 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 879 880 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 881 882 rc = t4_map_bars_0_and_4(sc); 883 if (rc != 0) 884 goto done; /* error message displayed already */ 885 886 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 887 888 /* Prepare the adapter for operation. */ 889 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 890 rc = -t4_prep_adapter(sc, buf); 891 free(buf, M_CXGBE); 892 if (rc != 0) { 893 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 894 goto done; 895 } 896 897 /* 898 * This is the real PF# to which we're attaching. Works from within PCI 899 * passthrough environments too, where pci_get_function() could return a 900 * different PF# depending on the passthrough configuration. We need to 901 * use the real PF# in all our communication with the firmware. 902 */ 903 j = t4_read_reg(sc, A_PL_WHOAMI); 904 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 905 sc->mbox = sc->pf; 906 907 t4_init_devnames(sc); 908 if (sc->names == NULL) { 909 rc = ENOTSUP; 910 goto done; /* error message displayed already */ 911 } 912 913 /* 914 * Do this really early, with the memory windows set up even before the 915 * character device. The userland tool's register i/o and mem read 916 * will work even in "recovery mode". 917 */ 918 setup_memwin(sc); 919 if (t4_init_devlog_params(sc, 0) == 0) 920 fixup_devlog_params(sc); 921 make_dev_args_init(&mda); 922 mda.mda_devsw = &t4_cdevsw; 923 mda.mda_uid = UID_ROOT; 924 mda.mda_gid = GID_WHEEL; 925 mda.mda_mode = 0600; 926 mda.mda_si_drv1 = sc; 927 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 928 if (rc != 0) 929 device_printf(dev, "failed to create nexus char device: %d.\n", 930 rc); 931 932 /* Go no further if recovery mode has been requested. */ 933 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 934 device_printf(dev, "recovery mode.\n"); 935 goto done; 936 } 937 938 #if defined(__i386__) 939 if ((cpu_feature & CPUID_CX8) == 0) { 940 device_printf(dev, "64 bit atomics not available.\n"); 941 rc = ENOTSUP; 942 goto done; 943 } 944 #endif 945 946 /* Prepare the firmware for operation */ 947 rc = prep_firmware(sc); 948 if (rc != 0) 949 goto done; /* error message displayed already */ 950 951 rc = get_params__post_init(sc); 952 if (rc != 0) 953 goto done; /* error message displayed already */ 954 955 rc = set_params__post_init(sc); 956 if (rc != 0) 957 goto done; /* error message displayed already */ 958 959 rc = t4_map_bar_2(sc); 960 if (rc != 0) 961 goto done; /* error message displayed already */ 962 963 rc = t4_create_dma_tag(sc); 964 if (rc != 0) 965 goto done; /* error message displayed already */ 966 967 /* 968 * First pass over all the ports - allocate VIs and initialize some 969 * basic parameters like mac address, port type, etc. 970 */ 971 for_each_port(sc, i) { 972 struct port_info *pi; 973 974 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 975 sc->port[i] = pi; 976 977 /* These must be set before t4_port_init */ 978 pi->adapter = sc; 979 pi->port_id = i; 980 /* 981 * XXX: vi[0] is special so we can't delay this allocation until 982 * pi->nvi's final value is known. 983 */ 984 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 985 M_ZERO | M_WAITOK); 986 987 /* 988 * Allocate the "main" VI and initialize parameters 989 * like mac addr. 990 */ 991 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 992 if (rc != 0) { 993 device_printf(dev, "unable to initialize port %d: %d\n", 994 i, rc); 995 free(pi->vi, M_CXGBE); 996 free(pi, M_CXGBE); 997 sc->port[i] = NULL; 998 goto done; 999 } 1000 1001 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1002 device_get_nameunit(dev), i); 1003 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1004 sc->chan_map[pi->tx_chan] = i; 1005 1006 /* All VIs on this port share this media. */ 1007 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1008 cxgbe_media_status); 1009 1010 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1); 1011 if (pi->dev == NULL) { 1012 device_printf(dev, 1013 "failed to add device for port %d.\n", i); 1014 rc = ENXIO; 1015 goto done; 1016 } 1017 pi->vi[0].dev = pi->dev; 1018 device_set_softc(pi->dev, pi); 1019 } 1020 1021 /* 1022 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1023 */ 1024 nports = sc->params.nports; 1025 rc = cfg_itype_and_nqueues(sc, &iaq); 1026 if (rc != 0) 1027 goto done; /* error message displayed already */ 1028 1029 num_vis = iaq.num_vis; 1030 sc->intr_type = iaq.intr_type; 1031 sc->intr_count = iaq.nirq; 1032 1033 s = &sc->sge; 1034 s->nrxq = nports * iaq.nrxq; 1035 s->ntxq = nports * iaq.ntxq; 1036 if (num_vis > 1) { 1037 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1038 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1039 } 1040 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1041 s->neq += nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 1042 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1043 #ifdef TCP_OFFLOAD 1044 if (is_offload(sc)) { 1045 s->nofldrxq = nports * iaq.nofldrxq; 1046 s->nofldtxq = nports * iaq.nofldtxq; 1047 if (num_vis > 1) { 1048 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1049 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1050 } 1051 s->neq += s->nofldtxq + s->nofldrxq; 1052 s->niq += s->nofldrxq; 1053 1054 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1055 M_CXGBE, M_ZERO | M_WAITOK); 1056 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1057 M_CXGBE, M_ZERO | M_WAITOK); 1058 } 1059 #endif 1060 #ifdef DEV_NETMAP 1061 if (num_vis > 1) { 1062 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1063 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1064 } 1065 s->neq += s->nnmtxq + s->nnmrxq; 1066 s->niq += s->nnmrxq; 1067 1068 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1069 M_CXGBE, M_ZERO | M_WAITOK); 1070 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1071 M_CXGBE, M_ZERO | M_WAITOK); 1072 #endif 1073 1074 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1075 M_ZERO | M_WAITOK); 1076 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1077 M_ZERO | M_WAITOK); 1078 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1079 M_ZERO | M_WAITOK); 1080 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1081 M_ZERO | M_WAITOK); 1082 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1083 M_ZERO | M_WAITOK); 1084 1085 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1086 M_ZERO | M_WAITOK); 1087 1088 t4_init_l2t(sc, M_WAITOK); 1089 t4_init_tx_sched(sc); 1090 1091 /* 1092 * Second pass over the ports. This time we know the number of rx and 1093 * tx queues that each port should get. 1094 */ 1095 rqidx = tqidx = 0; 1096 #ifdef TCP_OFFLOAD 1097 ofld_rqidx = ofld_tqidx = 0; 1098 #endif 1099 #ifdef DEV_NETMAP 1100 nm_rqidx = nm_tqidx = 0; 1101 #endif 1102 for_each_port(sc, i) { 1103 struct port_info *pi = sc->port[i]; 1104 struct vi_info *vi; 1105 1106 if (pi == NULL) 1107 continue; 1108 1109 pi->nvi = num_vis; 1110 for_each_vi(pi, j, vi) { 1111 vi->pi = pi; 1112 vi->qsize_rxq = t4_qsize_rxq; 1113 vi->qsize_txq = t4_qsize_txq; 1114 1115 vi->first_rxq = rqidx; 1116 vi->first_txq = tqidx; 1117 vi->tmr_idx = t4_tmr_idx; 1118 vi->pktc_idx = t4_pktc_idx; 1119 vi->flags |= iaq.intr_flags & INTR_RXQ; 1120 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1121 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1122 1123 rqidx += vi->nrxq; 1124 tqidx += vi->ntxq; 1125 1126 if (j == 0 && vi->ntxq > 1) 1127 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1128 else 1129 vi->rsrv_noflowq = 0; 1130 1131 #ifdef TCP_OFFLOAD 1132 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1133 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1134 vi->first_ofld_rxq = ofld_rqidx; 1135 vi->first_ofld_txq = ofld_tqidx; 1136 vi->flags |= iaq.intr_flags & INTR_OFLD_RXQ; 1137 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1138 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1139 1140 ofld_rqidx += vi->nofldrxq; 1141 ofld_tqidx += vi->nofldtxq; 1142 #endif 1143 #ifdef DEV_NETMAP 1144 if (j > 0) { 1145 vi->first_nm_rxq = nm_rqidx; 1146 vi->first_nm_txq = nm_tqidx; 1147 vi->nnmrxq = iaq.nnmrxq_vi; 1148 vi->nnmtxq = iaq.nnmtxq_vi; 1149 nm_rqidx += vi->nnmrxq; 1150 nm_tqidx += vi->nnmtxq; 1151 } 1152 #endif 1153 } 1154 } 1155 1156 rc = t4_setup_intr_handlers(sc); 1157 if (rc != 0) { 1158 device_printf(dev, 1159 "failed to setup interrupt handlers: %d\n", rc); 1160 goto done; 1161 } 1162 1163 rc = bus_generic_probe(dev); 1164 if (rc != 0) { 1165 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1166 goto done; 1167 } 1168 1169 /* 1170 * Ensure thread-safe mailbox access (in debug builds). 1171 * 1172 * So far this was the only thread accessing the mailbox but various 1173 * ifnets and sysctls are about to be created and their handlers/ioctls 1174 * will access the mailbox from different threads. 1175 */ 1176 sc->flags |= CHK_MBOX_ACCESS; 1177 1178 rc = bus_generic_attach(dev); 1179 if (rc != 0) { 1180 device_printf(dev, 1181 "failed to attach all child ports: %d\n", rc); 1182 goto done; 1183 } 1184 1185 device_printf(dev, 1186 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1187 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1188 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1189 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1190 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1191 1192 t4_set_desc(sc); 1193 1194 notify_siblings(dev, 0); 1195 1196 done: 1197 if (rc != 0 && sc->cdev) { 1198 /* cdev was created and so cxgbetool works; recover that way. */ 1199 device_printf(dev, 1200 "error during attach, adapter is now in recovery mode.\n"); 1201 rc = 0; 1202 } 1203 1204 if (rc != 0) 1205 t4_detach_common(dev); 1206 else 1207 t4_sysctls(sc); 1208 1209 return (rc); 1210 } 1211 1212 static int 1213 t4_ready(device_t dev) 1214 { 1215 struct adapter *sc; 1216 1217 sc = device_get_softc(dev); 1218 if (sc->flags & FW_OK) 1219 return (0); 1220 return (ENXIO); 1221 } 1222 1223 static int 1224 t4_read_port_device(device_t dev, int port, device_t *child) 1225 { 1226 struct adapter *sc; 1227 struct port_info *pi; 1228 1229 sc = device_get_softc(dev); 1230 if (port < 0 || port >= MAX_NPORTS) 1231 return (EINVAL); 1232 pi = sc->port[port]; 1233 if (pi == NULL || pi->dev == NULL) 1234 return (ENXIO); 1235 *child = pi->dev; 1236 return (0); 1237 } 1238 1239 static int 1240 notify_siblings(device_t dev, int detaching) 1241 { 1242 device_t sibling; 1243 int error, i; 1244 1245 error = 0; 1246 for (i = 0; i < PCI_FUNCMAX; i++) { 1247 if (i == pci_get_function(dev)) 1248 continue; 1249 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1250 pci_get_slot(dev), i); 1251 if (sibling == NULL || !device_is_attached(sibling)) 1252 continue; 1253 if (detaching) 1254 error = T4_DETACH_CHILD(sibling); 1255 else 1256 (void)T4_ATTACH_CHILD(sibling); 1257 if (error) 1258 break; 1259 } 1260 return (error); 1261 } 1262 1263 /* 1264 * Idempotent 1265 */ 1266 static int 1267 t4_detach(device_t dev) 1268 { 1269 struct adapter *sc; 1270 int rc; 1271 1272 sc = device_get_softc(dev); 1273 1274 rc = notify_siblings(dev, 1); 1275 if (rc) { 1276 device_printf(dev, 1277 "failed to detach sibling devices: %d\n", rc); 1278 return (rc); 1279 } 1280 1281 return (t4_detach_common(dev)); 1282 } 1283 1284 int 1285 t4_detach_common(device_t dev) 1286 { 1287 struct adapter *sc; 1288 struct port_info *pi; 1289 int i, rc; 1290 1291 sc = device_get_softc(dev); 1292 1293 sc->flags &= ~CHK_MBOX_ACCESS; 1294 if (sc->flags & FULL_INIT_DONE) { 1295 if (!(sc->flags & IS_VF)) 1296 t4_intr_disable(sc); 1297 } 1298 1299 if (sc->cdev) { 1300 destroy_dev(sc->cdev); 1301 sc->cdev = NULL; 1302 } 1303 1304 if (device_is_attached(dev)) { 1305 rc = bus_generic_detach(dev); 1306 if (rc) { 1307 device_printf(dev, 1308 "failed to detach child devices: %d\n", rc); 1309 return (rc); 1310 } 1311 } 1312 1313 for (i = 0; i < sc->intr_count; i++) 1314 t4_free_irq(sc, &sc->irq[i]); 1315 1316 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1317 t4_free_tx_sched(sc); 1318 1319 for (i = 0; i < MAX_NPORTS; i++) { 1320 pi = sc->port[i]; 1321 if (pi) { 1322 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1323 if (pi->dev) 1324 device_delete_child(dev, pi->dev); 1325 1326 mtx_destroy(&pi->pi_lock); 1327 free(pi->vi, M_CXGBE); 1328 free(pi, M_CXGBE); 1329 } 1330 } 1331 1332 device_delete_children(dev); 1333 1334 if (sc->flags & FULL_INIT_DONE) 1335 adapter_full_uninit(sc); 1336 1337 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1338 t4_fw_bye(sc, sc->mbox); 1339 1340 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1341 pci_release_msi(dev); 1342 1343 if (sc->regs_res) 1344 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1345 sc->regs_res); 1346 1347 if (sc->udbs_res) 1348 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1349 sc->udbs_res); 1350 1351 if (sc->msix_res) 1352 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1353 sc->msix_res); 1354 1355 if (sc->l2t) 1356 t4_free_l2t(sc->l2t); 1357 1358 #ifdef TCP_OFFLOAD 1359 free(sc->sge.ofld_rxq, M_CXGBE); 1360 free(sc->sge.ofld_txq, M_CXGBE); 1361 #endif 1362 #ifdef DEV_NETMAP 1363 free(sc->sge.nm_rxq, M_CXGBE); 1364 free(sc->sge.nm_txq, M_CXGBE); 1365 #endif 1366 free(sc->irq, M_CXGBE); 1367 free(sc->sge.rxq, M_CXGBE); 1368 free(sc->sge.txq, M_CXGBE); 1369 free(sc->sge.ctrlq, M_CXGBE); 1370 free(sc->sge.iqmap, M_CXGBE); 1371 free(sc->sge.eqmap, M_CXGBE); 1372 free(sc->tids.ftid_tab, M_CXGBE); 1373 t4_destroy_dma_tag(sc); 1374 if (mtx_initialized(&sc->sc_lock)) { 1375 sx_xlock(&t4_list_lock); 1376 SLIST_REMOVE(&t4_list, sc, adapter, link); 1377 sx_xunlock(&t4_list_lock); 1378 mtx_destroy(&sc->sc_lock); 1379 } 1380 1381 callout_drain(&sc->sfl_callout); 1382 if (mtx_initialized(&sc->tids.ftid_lock)) 1383 mtx_destroy(&sc->tids.ftid_lock); 1384 if (mtx_initialized(&sc->sfl_lock)) 1385 mtx_destroy(&sc->sfl_lock); 1386 if (mtx_initialized(&sc->ifp_lock)) 1387 mtx_destroy(&sc->ifp_lock); 1388 if (mtx_initialized(&sc->reg_lock)) 1389 mtx_destroy(&sc->reg_lock); 1390 1391 for (i = 0; i < NUM_MEMWIN; i++) { 1392 struct memwin *mw = &sc->memwin[i]; 1393 1394 if (rw_initialized(&mw->mw_lock)) 1395 rw_destroy(&mw->mw_lock); 1396 } 1397 1398 bzero(sc, sizeof(*sc)); 1399 1400 return (0); 1401 } 1402 1403 static int 1404 cxgbe_probe(device_t dev) 1405 { 1406 char buf[128]; 1407 struct port_info *pi = device_get_softc(dev); 1408 1409 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1410 device_set_desc_copy(dev, buf); 1411 1412 return (BUS_PROBE_DEFAULT); 1413 } 1414 1415 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1416 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1417 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1418 #define T4_CAP_ENABLE (T4_CAP) 1419 1420 static int 1421 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1422 { 1423 struct ifnet *ifp; 1424 struct sbuf *sb; 1425 1426 vi->xact_addr_filt = -1; 1427 callout_init(&vi->tick, 1); 1428 1429 /* Allocate an ifnet and set it up */ 1430 ifp = if_alloc(IFT_ETHER); 1431 if (ifp == NULL) { 1432 device_printf(dev, "Cannot allocate ifnet\n"); 1433 return (ENOMEM); 1434 } 1435 vi->ifp = ifp; 1436 ifp->if_softc = vi; 1437 1438 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1439 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1440 1441 ifp->if_init = cxgbe_init; 1442 ifp->if_ioctl = cxgbe_ioctl; 1443 ifp->if_transmit = cxgbe_transmit; 1444 ifp->if_qflush = cxgbe_qflush; 1445 ifp->if_get_counter = cxgbe_get_counter; 1446 1447 ifp->if_capabilities = T4_CAP; 1448 #ifdef TCP_OFFLOAD 1449 if (vi->nofldrxq != 0) 1450 ifp->if_capabilities |= IFCAP_TOE; 1451 #endif 1452 #ifdef DEV_NETMAP 1453 if (vi->nnmrxq != 0) 1454 ifp->if_capabilities |= IFCAP_NETMAP; 1455 #endif 1456 ifp->if_capenable = T4_CAP_ENABLE; 1457 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1458 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1459 1460 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1461 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1462 ifp->if_hw_tsomaxsegsize = 65536; 1463 1464 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1465 EVENTHANDLER_PRI_ANY); 1466 1467 ether_ifattach(ifp, vi->hw_addr); 1468 #ifdef DEV_NETMAP 1469 if (ifp->if_capabilities & IFCAP_NETMAP) 1470 cxgbe_nm_attach(vi); 1471 #endif 1472 sb = sbuf_new_auto(); 1473 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1474 #ifdef TCP_OFFLOAD 1475 if (ifp->if_capabilities & IFCAP_TOE) 1476 sbuf_printf(sb, "; %d txq, %d rxq (TOE)", 1477 vi->nofldtxq, vi->nofldrxq); 1478 #endif 1479 #ifdef DEV_NETMAP 1480 if (ifp->if_capabilities & IFCAP_NETMAP) 1481 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1482 vi->nnmtxq, vi->nnmrxq); 1483 #endif 1484 sbuf_finish(sb); 1485 device_printf(dev, "%s\n", sbuf_data(sb)); 1486 sbuf_delete(sb); 1487 1488 vi_sysctls(vi); 1489 1490 return (0); 1491 } 1492 1493 static int 1494 cxgbe_attach(device_t dev) 1495 { 1496 struct port_info *pi = device_get_softc(dev); 1497 struct adapter *sc = pi->adapter; 1498 struct vi_info *vi; 1499 int i, rc; 1500 1501 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1502 1503 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1504 if (rc) 1505 return (rc); 1506 1507 for_each_vi(pi, i, vi) { 1508 if (i == 0) 1509 continue; 1510 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1511 if (vi->dev == NULL) { 1512 device_printf(dev, "failed to add VI %d\n", i); 1513 continue; 1514 } 1515 device_set_softc(vi->dev, vi); 1516 } 1517 1518 cxgbe_sysctls(pi); 1519 1520 bus_generic_attach(dev); 1521 1522 return (0); 1523 } 1524 1525 static void 1526 cxgbe_vi_detach(struct vi_info *vi) 1527 { 1528 struct ifnet *ifp = vi->ifp; 1529 1530 ether_ifdetach(ifp); 1531 1532 if (vi->vlan_c) 1533 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1534 1535 /* Let detach proceed even if these fail. */ 1536 #ifdef DEV_NETMAP 1537 if (ifp->if_capabilities & IFCAP_NETMAP) 1538 cxgbe_nm_detach(vi); 1539 #endif 1540 cxgbe_uninit_synchronized(vi); 1541 callout_drain(&vi->tick); 1542 vi_full_uninit(vi); 1543 1544 if_free(vi->ifp); 1545 vi->ifp = NULL; 1546 } 1547 1548 static int 1549 cxgbe_detach(device_t dev) 1550 { 1551 struct port_info *pi = device_get_softc(dev); 1552 struct adapter *sc = pi->adapter; 1553 int rc; 1554 1555 /* Detach the extra VIs first. */ 1556 rc = bus_generic_detach(dev); 1557 if (rc) 1558 return (rc); 1559 device_delete_children(dev); 1560 1561 doom_vi(sc, &pi->vi[0]); 1562 1563 if (pi->flags & HAS_TRACEQ) { 1564 sc->traceq = -1; /* cloner should not create ifnet */ 1565 t4_tracer_port_detach(sc); 1566 } 1567 1568 cxgbe_vi_detach(&pi->vi[0]); 1569 callout_drain(&pi->tick); 1570 ifmedia_removeall(&pi->media); 1571 1572 end_synchronized_op(sc, 0); 1573 1574 return (0); 1575 } 1576 1577 static void 1578 cxgbe_init(void *arg) 1579 { 1580 struct vi_info *vi = arg; 1581 struct adapter *sc = vi->pi->adapter; 1582 1583 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1584 return; 1585 cxgbe_init_synchronized(vi); 1586 end_synchronized_op(sc, 0); 1587 } 1588 1589 static int 1590 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1591 { 1592 int rc = 0, mtu, flags, can_sleep; 1593 struct vi_info *vi = ifp->if_softc; 1594 struct port_info *pi = vi->pi; 1595 struct adapter *sc = pi->adapter; 1596 struct ifreq *ifr = (struct ifreq *)data; 1597 uint32_t mask; 1598 1599 switch (cmd) { 1600 case SIOCSIFMTU: 1601 mtu = ifr->ifr_mtu; 1602 if (mtu < ETHERMIN || mtu > MAX_MTU) 1603 return (EINVAL); 1604 1605 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1606 if (rc) 1607 return (rc); 1608 ifp->if_mtu = mtu; 1609 if (vi->flags & VI_INIT_DONE) { 1610 t4_update_fl_bufsize(ifp); 1611 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1612 rc = update_mac_settings(ifp, XGMAC_MTU); 1613 } 1614 end_synchronized_op(sc, 0); 1615 break; 1616 1617 case SIOCSIFFLAGS: 1618 can_sleep = 0; 1619 redo_sifflags: 1620 rc = begin_synchronized_op(sc, vi, 1621 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1622 if (rc) 1623 return (rc); 1624 1625 if (ifp->if_flags & IFF_UP) { 1626 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1627 flags = vi->if_flags; 1628 if ((ifp->if_flags ^ flags) & 1629 (IFF_PROMISC | IFF_ALLMULTI)) { 1630 if (can_sleep == 1) { 1631 end_synchronized_op(sc, 0); 1632 can_sleep = 0; 1633 goto redo_sifflags; 1634 } 1635 rc = update_mac_settings(ifp, 1636 XGMAC_PROMISC | XGMAC_ALLMULTI); 1637 } 1638 } else { 1639 if (can_sleep == 0) { 1640 end_synchronized_op(sc, LOCK_HELD); 1641 can_sleep = 1; 1642 goto redo_sifflags; 1643 } 1644 rc = cxgbe_init_synchronized(vi); 1645 } 1646 vi->if_flags = ifp->if_flags; 1647 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1648 if (can_sleep == 0) { 1649 end_synchronized_op(sc, LOCK_HELD); 1650 can_sleep = 1; 1651 goto redo_sifflags; 1652 } 1653 rc = cxgbe_uninit_synchronized(vi); 1654 } 1655 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1656 break; 1657 1658 case SIOCADDMULTI: 1659 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1660 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1661 if (rc) 1662 return (rc); 1663 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1664 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1665 end_synchronized_op(sc, LOCK_HELD); 1666 break; 1667 1668 case SIOCSIFCAP: 1669 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1670 if (rc) 1671 return (rc); 1672 1673 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1674 if (mask & IFCAP_TXCSUM) { 1675 ifp->if_capenable ^= IFCAP_TXCSUM; 1676 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1677 1678 if (IFCAP_TSO4 & ifp->if_capenable && 1679 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1680 ifp->if_capenable &= ~IFCAP_TSO4; 1681 if_printf(ifp, 1682 "tso4 disabled due to -txcsum.\n"); 1683 } 1684 } 1685 if (mask & IFCAP_TXCSUM_IPV6) { 1686 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1687 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1688 1689 if (IFCAP_TSO6 & ifp->if_capenable && 1690 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1691 ifp->if_capenable &= ~IFCAP_TSO6; 1692 if_printf(ifp, 1693 "tso6 disabled due to -txcsum6.\n"); 1694 } 1695 } 1696 if (mask & IFCAP_RXCSUM) 1697 ifp->if_capenable ^= IFCAP_RXCSUM; 1698 if (mask & IFCAP_RXCSUM_IPV6) 1699 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1700 1701 /* 1702 * Note that we leave CSUM_TSO alone (it is always set). The 1703 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1704 * sending a TSO request our way, so it's sufficient to toggle 1705 * IFCAP_TSOx only. 1706 */ 1707 if (mask & IFCAP_TSO4) { 1708 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1709 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1710 if_printf(ifp, "enable txcsum first.\n"); 1711 rc = EAGAIN; 1712 goto fail; 1713 } 1714 ifp->if_capenable ^= IFCAP_TSO4; 1715 } 1716 if (mask & IFCAP_TSO6) { 1717 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1718 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1719 if_printf(ifp, "enable txcsum6 first.\n"); 1720 rc = EAGAIN; 1721 goto fail; 1722 } 1723 ifp->if_capenable ^= IFCAP_TSO6; 1724 } 1725 if (mask & IFCAP_LRO) { 1726 #if defined(INET) || defined(INET6) 1727 int i; 1728 struct sge_rxq *rxq; 1729 1730 ifp->if_capenable ^= IFCAP_LRO; 1731 for_each_rxq(vi, i, rxq) { 1732 if (ifp->if_capenable & IFCAP_LRO) 1733 rxq->iq.flags |= IQ_LRO_ENABLED; 1734 else 1735 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1736 } 1737 #endif 1738 } 1739 #ifdef TCP_OFFLOAD 1740 if (mask & IFCAP_TOE) { 1741 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1742 1743 rc = toe_capability(vi, enable); 1744 if (rc != 0) 1745 goto fail; 1746 1747 ifp->if_capenable ^= mask; 1748 } 1749 #endif 1750 if (mask & IFCAP_VLAN_HWTAGGING) { 1751 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1752 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1753 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1754 } 1755 if (mask & IFCAP_VLAN_MTU) { 1756 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1757 1758 /* Need to find out how to disable auto-mtu-inflation */ 1759 } 1760 if (mask & IFCAP_VLAN_HWTSO) 1761 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1762 if (mask & IFCAP_VLAN_HWCSUM) 1763 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1764 1765 #ifdef VLAN_CAPABILITIES 1766 VLAN_CAPABILITIES(ifp); 1767 #endif 1768 fail: 1769 end_synchronized_op(sc, 0); 1770 break; 1771 1772 case SIOCSIFMEDIA: 1773 case SIOCGIFMEDIA: 1774 case SIOCGIFXMEDIA: 1775 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 1776 break; 1777 1778 case SIOCGI2C: { 1779 struct ifi2creq i2c; 1780 1781 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 1782 if (rc != 0) 1783 break; 1784 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1785 rc = EPERM; 1786 break; 1787 } 1788 if (i2c.len > sizeof(i2c.data)) { 1789 rc = EINVAL; 1790 break; 1791 } 1792 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1793 if (rc) 1794 return (rc); 1795 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 1796 i2c.offset, i2c.len, &i2c.data[0]); 1797 end_synchronized_op(sc, 0); 1798 if (rc == 0) 1799 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 1800 break; 1801 } 1802 1803 default: 1804 rc = ether_ioctl(ifp, cmd, data); 1805 } 1806 1807 return (rc); 1808 } 1809 1810 static int 1811 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1812 { 1813 struct vi_info *vi = ifp->if_softc; 1814 struct port_info *pi = vi->pi; 1815 struct adapter *sc = pi->adapter; 1816 struct sge_txq *txq; 1817 void *items[1]; 1818 int rc; 1819 1820 M_ASSERTPKTHDR(m); 1821 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1822 1823 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1824 m_freem(m); 1825 return (ENETDOWN); 1826 } 1827 1828 rc = parse_pkt(sc, &m); 1829 if (__predict_false(rc != 0)) { 1830 MPASS(m == NULL); /* was freed already */ 1831 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1832 return (rc); 1833 } 1834 1835 /* Select a txq. */ 1836 txq = &sc->sge.txq[vi->first_txq]; 1837 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1838 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1839 vi->rsrv_noflowq); 1840 1841 items[0] = m; 1842 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 1843 if (__predict_false(rc != 0)) 1844 m_freem(m); 1845 1846 return (rc); 1847 } 1848 1849 static void 1850 cxgbe_qflush(struct ifnet *ifp) 1851 { 1852 struct vi_info *vi = ifp->if_softc; 1853 struct sge_txq *txq; 1854 int i; 1855 1856 /* queues do not exist if !VI_INIT_DONE. */ 1857 if (vi->flags & VI_INIT_DONE) { 1858 for_each_txq(vi, i, txq) { 1859 TXQ_LOCK(txq); 1860 txq->eq.flags |= EQ_QFLUSH; 1861 TXQ_UNLOCK(txq); 1862 while (!mp_ring_is_idle(txq->r)) { 1863 mp_ring_check_drainage(txq->r, 0); 1864 pause("qflush", 1); 1865 } 1866 TXQ_LOCK(txq); 1867 txq->eq.flags &= ~EQ_QFLUSH; 1868 TXQ_UNLOCK(txq); 1869 } 1870 } 1871 if_qflush(ifp); 1872 } 1873 1874 static uint64_t 1875 vi_get_counter(struct ifnet *ifp, ift_counter c) 1876 { 1877 struct vi_info *vi = ifp->if_softc; 1878 struct fw_vi_stats_vf *s = &vi->stats; 1879 1880 vi_refresh_stats(vi->pi->adapter, vi); 1881 1882 switch (c) { 1883 case IFCOUNTER_IPACKETS: 1884 return (s->rx_bcast_frames + s->rx_mcast_frames + 1885 s->rx_ucast_frames); 1886 case IFCOUNTER_IERRORS: 1887 return (s->rx_err_frames); 1888 case IFCOUNTER_OPACKETS: 1889 return (s->tx_bcast_frames + s->tx_mcast_frames + 1890 s->tx_ucast_frames + s->tx_offload_frames); 1891 case IFCOUNTER_OERRORS: 1892 return (s->tx_drop_frames); 1893 case IFCOUNTER_IBYTES: 1894 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 1895 s->rx_ucast_bytes); 1896 case IFCOUNTER_OBYTES: 1897 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 1898 s->tx_ucast_bytes + s->tx_offload_bytes); 1899 case IFCOUNTER_IMCASTS: 1900 return (s->rx_mcast_frames); 1901 case IFCOUNTER_OMCASTS: 1902 return (s->tx_mcast_frames); 1903 case IFCOUNTER_OQDROPS: { 1904 uint64_t drops; 1905 1906 drops = 0; 1907 if (vi->flags & VI_INIT_DONE) { 1908 int i; 1909 struct sge_txq *txq; 1910 1911 for_each_txq(vi, i, txq) 1912 drops += counter_u64_fetch(txq->r->drops); 1913 } 1914 1915 return (drops); 1916 1917 } 1918 1919 default: 1920 return (if_get_counter_default(ifp, c)); 1921 } 1922 } 1923 1924 uint64_t 1925 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 1926 { 1927 struct vi_info *vi = ifp->if_softc; 1928 struct port_info *pi = vi->pi; 1929 struct adapter *sc = pi->adapter; 1930 struct port_stats *s = &pi->stats; 1931 1932 if (pi->nvi > 1 || sc->flags & IS_VF) 1933 return (vi_get_counter(ifp, c)); 1934 1935 cxgbe_refresh_stats(sc, pi); 1936 1937 switch (c) { 1938 case IFCOUNTER_IPACKETS: 1939 return (s->rx_frames); 1940 1941 case IFCOUNTER_IERRORS: 1942 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 1943 s->rx_fcs_err + s->rx_len_err); 1944 1945 case IFCOUNTER_OPACKETS: 1946 return (s->tx_frames); 1947 1948 case IFCOUNTER_OERRORS: 1949 return (s->tx_error_frames); 1950 1951 case IFCOUNTER_IBYTES: 1952 return (s->rx_octets); 1953 1954 case IFCOUNTER_OBYTES: 1955 return (s->tx_octets); 1956 1957 case IFCOUNTER_IMCASTS: 1958 return (s->rx_mcast_frames); 1959 1960 case IFCOUNTER_OMCASTS: 1961 return (s->tx_mcast_frames); 1962 1963 case IFCOUNTER_IQDROPS: 1964 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 1965 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 1966 s->rx_trunc3 + pi->tnl_cong_drops); 1967 1968 case IFCOUNTER_OQDROPS: { 1969 uint64_t drops; 1970 1971 drops = s->tx_drop; 1972 if (vi->flags & VI_INIT_DONE) { 1973 int i; 1974 struct sge_txq *txq; 1975 1976 for_each_txq(vi, i, txq) 1977 drops += counter_u64_fetch(txq->r->drops); 1978 } 1979 1980 return (drops); 1981 1982 } 1983 1984 default: 1985 return (if_get_counter_default(ifp, c)); 1986 } 1987 } 1988 1989 static int 1990 cxgbe_media_change(struct ifnet *ifp) 1991 { 1992 struct vi_info *vi = ifp->if_softc; 1993 1994 device_printf(vi->dev, "%s unimplemented.\n", __func__); 1995 1996 return (EOPNOTSUPP); 1997 } 1998 1999 static void 2000 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2001 { 2002 struct vi_info *vi = ifp->if_softc; 2003 struct port_info *pi = vi->pi; 2004 struct ifmedia_entry *cur; 2005 struct link_config *lc = &pi->link_cfg; 2006 2007 /* 2008 * If all the interfaces are administratively down the firmware does not 2009 * report transceiver changes. Refresh port info here so that ifconfig 2010 * displays accurate information at all times. 2011 */ 2012 if (begin_synchronized_op(pi->adapter, NULL, SLEEP_OK | INTR_OK, 2013 "t4med") == 0) { 2014 PORT_LOCK(pi); 2015 if (pi->up_vis == 0) { 2016 t4_update_port_info(pi); 2017 build_medialist(pi, &pi->media); 2018 } 2019 PORT_UNLOCK(pi); 2020 end_synchronized_op(pi->adapter, 0); 2021 } 2022 2023 ifmr->ifm_status = IFM_AVALID; 2024 if (lc->link_ok == 0) 2025 return; 2026 2027 ifmr->ifm_status |= IFM_ACTIVE; 2028 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2029 if (lc->fc & PAUSE_RX) 2030 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2031 if (lc->fc & PAUSE_TX) 2032 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2033 2034 /* active and current will differ iff current media is autoselect. */ 2035 cur = pi->media.ifm_cur; 2036 if (cur != NULL && IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 2037 return; 2038 2039 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2040 if (lc->fc & PAUSE_RX) 2041 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2042 if (lc->fc & PAUSE_TX) 2043 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2044 switch (lc->speed) { 2045 case 10000: 2046 ifmr->ifm_active |= IFM_10G_T; 2047 break; 2048 case 1000: 2049 ifmr->ifm_active |= IFM_1000_T; 2050 break; 2051 case 100: 2052 ifmr->ifm_active |= IFM_100_TX; 2053 break; 2054 case 10: 2055 ifmr->ifm_active |= IFM_10_T; 2056 break; 2057 default: 2058 device_printf(vi->dev, "link up but speed unknown (%u)\n", 2059 lc->speed); 2060 } 2061 } 2062 2063 static int 2064 vcxgbe_probe(device_t dev) 2065 { 2066 char buf[128]; 2067 struct vi_info *vi = device_get_softc(dev); 2068 2069 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2070 vi - vi->pi->vi); 2071 device_set_desc_copy(dev, buf); 2072 2073 return (BUS_PROBE_DEFAULT); 2074 } 2075 2076 static int 2077 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2078 { 2079 int func, index, rc; 2080 uint32_t param, val; 2081 2082 ASSERT_SYNCHRONIZED_OP(sc); 2083 2084 index = vi - pi->vi; 2085 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2086 KASSERT(index < nitems(vi_mac_funcs), 2087 ("%s: VI %s doesn't have a MAC func", __func__, 2088 device_get_nameunit(vi->dev))); 2089 func = vi_mac_funcs[index]; 2090 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2091 vi->hw_addr, &vi->rss_size, func, 0); 2092 if (rc < 0) { 2093 device_printf(vi->dev, "failed to allocate virtual interface %d" 2094 "for port %d: %d\n", index, pi->port_id, -rc); 2095 return (-rc); 2096 } 2097 vi->viid = rc; 2098 if (chip_id(sc) <= CHELSIO_T5) 2099 vi->smt_idx = (rc & 0x7f) << 1; 2100 else 2101 vi->smt_idx = (rc & 0x7f); 2102 2103 if (vi->rss_size == 1) { 2104 /* 2105 * This VI didn't get a slice of the RSS table. Reduce the 2106 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2107 * configuration file (nvi, rssnvi for this PF) if this is a 2108 * problem. 2109 */ 2110 device_printf(vi->dev, "RSS table not available.\n"); 2111 vi->rss_base = 0xffff; 2112 2113 return (0); 2114 } 2115 2116 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2117 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2118 V_FW_PARAMS_PARAM_YZ(vi->viid); 2119 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2120 if (rc) 2121 vi->rss_base = 0xffff; 2122 else { 2123 MPASS((val >> 16) == vi->rss_size); 2124 vi->rss_base = val & 0xffff; 2125 } 2126 2127 return (0); 2128 } 2129 2130 static int 2131 vcxgbe_attach(device_t dev) 2132 { 2133 struct vi_info *vi; 2134 struct port_info *pi; 2135 struct adapter *sc; 2136 int rc; 2137 2138 vi = device_get_softc(dev); 2139 pi = vi->pi; 2140 sc = pi->adapter; 2141 2142 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2143 if (rc) 2144 return (rc); 2145 rc = alloc_extra_vi(sc, pi, vi); 2146 end_synchronized_op(sc, 0); 2147 if (rc) 2148 return (rc); 2149 2150 rc = cxgbe_vi_attach(dev, vi); 2151 if (rc) { 2152 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2153 return (rc); 2154 } 2155 return (0); 2156 } 2157 2158 static int 2159 vcxgbe_detach(device_t dev) 2160 { 2161 struct vi_info *vi; 2162 struct adapter *sc; 2163 2164 vi = device_get_softc(dev); 2165 sc = vi->pi->adapter; 2166 2167 doom_vi(sc, vi); 2168 2169 cxgbe_vi_detach(vi); 2170 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2171 2172 end_synchronized_op(sc, 0); 2173 2174 return (0); 2175 } 2176 2177 void 2178 t4_fatal_err(struct adapter *sc) 2179 { 2180 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2181 t4_intr_disable(sc); 2182 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2183 device_get_nameunit(sc->dev)); 2184 } 2185 2186 void 2187 t4_add_adapter(struct adapter *sc) 2188 { 2189 sx_xlock(&t4_list_lock); 2190 SLIST_INSERT_HEAD(&t4_list, sc, link); 2191 sx_xunlock(&t4_list_lock); 2192 } 2193 2194 int 2195 t4_map_bars_0_and_4(struct adapter *sc) 2196 { 2197 sc->regs_rid = PCIR_BAR(0); 2198 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2199 &sc->regs_rid, RF_ACTIVE); 2200 if (sc->regs_res == NULL) { 2201 device_printf(sc->dev, "cannot map registers.\n"); 2202 return (ENXIO); 2203 } 2204 sc->bt = rman_get_bustag(sc->regs_res); 2205 sc->bh = rman_get_bushandle(sc->regs_res); 2206 sc->mmio_len = rman_get_size(sc->regs_res); 2207 setbit(&sc->doorbells, DOORBELL_KDB); 2208 2209 sc->msix_rid = PCIR_BAR(4); 2210 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2211 &sc->msix_rid, RF_ACTIVE); 2212 if (sc->msix_res == NULL) { 2213 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2214 return (ENXIO); 2215 } 2216 2217 return (0); 2218 } 2219 2220 int 2221 t4_map_bar_2(struct adapter *sc) 2222 { 2223 2224 /* 2225 * T4: only iWARP driver uses the userspace doorbells. There is no need 2226 * to map it if RDMA is disabled. 2227 */ 2228 if (is_t4(sc) && sc->rdmacaps == 0) 2229 return (0); 2230 2231 sc->udbs_rid = PCIR_BAR(2); 2232 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2233 &sc->udbs_rid, RF_ACTIVE); 2234 if (sc->udbs_res == NULL) { 2235 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2236 return (ENXIO); 2237 } 2238 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2239 2240 if (chip_id(sc) >= CHELSIO_T5) { 2241 setbit(&sc->doorbells, DOORBELL_UDB); 2242 #if defined(__i386__) || defined(__amd64__) 2243 if (t5_write_combine) { 2244 int rc, mode; 2245 2246 /* 2247 * Enable write combining on BAR2. This is the 2248 * userspace doorbell BAR and is split into 128B 2249 * (UDBS_SEG_SIZE) doorbell regions, each associated 2250 * with an egress queue. The first 64B has the doorbell 2251 * and the second 64B can be used to submit a tx work 2252 * request with an implicit doorbell. 2253 */ 2254 2255 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2256 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2257 if (rc == 0) { 2258 clrbit(&sc->doorbells, DOORBELL_UDB); 2259 setbit(&sc->doorbells, DOORBELL_WCWR); 2260 setbit(&sc->doorbells, DOORBELL_UDBWC); 2261 } else { 2262 device_printf(sc->dev, 2263 "couldn't enable write combining: %d\n", 2264 rc); 2265 } 2266 2267 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2268 t4_write_reg(sc, A_SGE_STAT_CFG, 2269 V_STATSOURCE_T5(7) | mode); 2270 } 2271 #endif 2272 } 2273 2274 return (0); 2275 } 2276 2277 struct memwin_init { 2278 uint32_t base; 2279 uint32_t aperture; 2280 }; 2281 2282 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2283 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2284 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2285 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2286 }; 2287 2288 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2289 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2290 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2291 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2292 }; 2293 2294 static void 2295 setup_memwin(struct adapter *sc) 2296 { 2297 const struct memwin_init *mw_init; 2298 struct memwin *mw; 2299 int i; 2300 uint32_t bar0; 2301 2302 if (is_t4(sc)) { 2303 /* 2304 * Read low 32b of bar0 indirectly via the hardware backdoor 2305 * mechanism. Works from within PCI passthrough environments 2306 * too, where rman_get_start() can return a different value. We 2307 * need to program the T4 memory window decoders with the actual 2308 * addresses that will be coming across the PCIe link. 2309 */ 2310 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2311 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2312 2313 mw_init = &t4_memwin[0]; 2314 } else { 2315 /* T5+ use the relative offset inside the PCIe BAR */ 2316 bar0 = 0; 2317 2318 mw_init = &t5_memwin[0]; 2319 } 2320 2321 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2322 rw_init(&mw->mw_lock, "memory window access"); 2323 mw->mw_base = mw_init->base; 2324 mw->mw_aperture = mw_init->aperture; 2325 mw->mw_curpos = 0; 2326 t4_write_reg(sc, 2327 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2328 (mw->mw_base + bar0) | V_BIR(0) | 2329 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2330 rw_wlock(&mw->mw_lock); 2331 position_memwin(sc, i, 0); 2332 rw_wunlock(&mw->mw_lock); 2333 } 2334 2335 /* flush */ 2336 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2337 } 2338 2339 /* 2340 * Positions the memory window at the given address in the card's address space. 2341 * There are some alignment requirements and the actual position may be at an 2342 * address prior to the requested address. mw->mw_curpos always has the actual 2343 * position of the window. 2344 */ 2345 static void 2346 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2347 { 2348 struct memwin *mw; 2349 uint32_t pf; 2350 uint32_t reg; 2351 2352 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2353 mw = &sc->memwin[idx]; 2354 rw_assert(&mw->mw_lock, RA_WLOCKED); 2355 2356 if (is_t4(sc)) { 2357 pf = 0; 2358 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2359 } else { 2360 pf = V_PFNUM(sc->pf); 2361 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2362 } 2363 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2364 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2365 t4_read_reg(sc, reg); /* flush */ 2366 } 2367 2368 static int 2369 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2370 int len, int rw) 2371 { 2372 struct memwin *mw; 2373 uint32_t mw_end, v; 2374 2375 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2376 2377 /* Memory can only be accessed in naturally aligned 4 byte units */ 2378 if (addr & 3 || len & 3 || len <= 0) 2379 return (EINVAL); 2380 2381 mw = &sc->memwin[idx]; 2382 while (len > 0) { 2383 rw_rlock(&mw->mw_lock); 2384 mw_end = mw->mw_curpos + mw->mw_aperture; 2385 if (addr >= mw_end || addr < mw->mw_curpos) { 2386 /* Will need to reposition the window */ 2387 if (!rw_try_upgrade(&mw->mw_lock)) { 2388 rw_runlock(&mw->mw_lock); 2389 rw_wlock(&mw->mw_lock); 2390 } 2391 rw_assert(&mw->mw_lock, RA_WLOCKED); 2392 position_memwin(sc, idx, addr); 2393 rw_downgrade(&mw->mw_lock); 2394 mw_end = mw->mw_curpos + mw->mw_aperture; 2395 } 2396 rw_assert(&mw->mw_lock, RA_RLOCKED); 2397 while (addr < mw_end && len > 0) { 2398 if (rw == 0) { 2399 v = t4_read_reg(sc, mw->mw_base + addr - 2400 mw->mw_curpos); 2401 *val++ = le32toh(v); 2402 } else { 2403 v = *val++; 2404 t4_write_reg(sc, mw->mw_base + addr - 2405 mw->mw_curpos, htole32(v)); 2406 } 2407 addr += 4; 2408 len -= 4; 2409 } 2410 rw_runlock(&mw->mw_lock); 2411 } 2412 2413 return (0); 2414 } 2415 2416 static inline int 2417 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2418 int len) 2419 { 2420 2421 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 2422 } 2423 2424 static inline int 2425 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 2426 const uint32_t *val, int len) 2427 { 2428 2429 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 2430 } 2431 2432 static int 2433 t4_range_cmp(const void *a, const void *b) 2434 { 2435 return ((const struct t4_range *)a)->start - 2436 ((const struct t4_range *)b)->start; 2437 } 2438 2439 /* 2440 * Verify that the memory range specified by the addr/len pair is valid within 2441 * the card's address space. 2442 */ 2443 static int 2444 validate_mem_range(struct adapter *sc, uint32_t addr, int len) 2445 { 2446 struct t4_range mem_ranges[4], *r, *next; 2447 uint32_t em, addr_len; 2448 int i, n, remaining; 2449 2450 /* Memory can only be accessed in naturally aligned 4 byte units */ 2451 if (addr & 3 || len & 3 || len <= 0) 2452 return (EINVAL); 2453 2454 /* Enabled memories */ 2455 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2456 2457 r = &mem_ranges[0]; 2458 n = 0; 2459 bzero(r, sizeof(mem_ranges)); 2460 if (em & F_EDRAM0_ENABLE) { 2461 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2462 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2463 if (r->size > 0) { 2464 r->start = G_EDRAM0_BASE(addr_len) << 20; 2465 if (addr >= r->start && 2466 addr + len <= r->start + r->size) 2467 return (0); 2468 r++; 2469 n++; 2470 } 2471 } 2472 if (em & F_EDRAM1_ENABLE) { 2473 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2474 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2475 if (r->size > 0) { 2476 r->start = G_EDRAM1_BASE(addr_len) << 20; 2477 if (addr >= r->start && 2478 addr + len <= r->start + r->size) 2479 return (0); 2480 r++; 2481 n++; 2482 } 2483 } 2484 if (em & F_EXT_MEM_ENABLE) { 2485 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2486 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2487 if (r->size > 0) { 2488 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2489 if (addr >= r->start && 2490 addr + len <= r->start + r->size) 2491 return (0); 2492 r++; 2493 n++; 2494 } 2495 } 2496 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2497 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2498 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2499 if (r->size > 0) { 2500 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2501 if (addr >= r->start && 2502 addr + len <= r->start + r->size) 2503 return (0); 2504 r++; 2505 n++; 2506 } 2507 } 2508 MPASS(n <= nitems(mem_ranges)); 2509 2510 if (n > 1) { 2511 /* Sort and merge the ranges. */ 2512 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2513 2514 /* Start from index 0 and examine the next n - 1 entries. */ 2515 r = &mem_ranges[0]; 2516 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2517 2518 MPASS(r->size > 0); /* r is a valid entry. */ 2519 next = r + 1; 2520 MPASS(next->size > 0); /* and so is the next one. */ 2521 2522 while (r->start + r->size >= next->start) { 2523 /* Merge the next one into the current entry. */ 2524 r->size = max(r->start + r->size, 2525 next->start + next->size) - r->start; 2526 n--; /* One fewer entry in total. */ 2527 if (--remaining == 0) 2528 goto done; /* short circuit */ 2529 next++; 2530 } 2531 if (next != r + 1) { 2532 /* 2533 * Some entries were merged into r and next 2534 * points to the first valid entry that couldn't 2535 * be merged. 2536 */ 2537 MPASS(next->size > 0); /* must be valid */ 2538 memcpy(r + 1, next, remaining * sizeof(*r)); 2539 #ifdef INVARIANTS 2540 /* 2541 * This so that the foo->size assertion in the 2542 * next iteration of the loop do the right 2543 * thing for entries that were pulled up and are 2544 * no longer valid. 2545 */ 2546 MPASS(n < nitems(mem_ranges)); 2547 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2548 sizeof(struct t4_range)); 2549 #endif 2550 } 2551 } 2552 done: 2553 /* Done merging the ranges. */ 2554 MPASS(n > 0); 2555 r = &mem_ranges[0]; 2556 for (i = 0; i < n; i++, r++) { 2557 if (addr >= r->start && 2558 addr + len <= r->start + r->size) 2559 return (0); 2560 } 2561 } 2562 2563 return (EFAULT); 2564 } 2565 2566 static int 2567 fwmtype_to_hwmtype(int mtype) 2568 { 2569 2570 switch (mtype) { 2571 case FW_MEMTYPE_EDC0: 2572 return (MEM_EDC0); 2573 case FW_MEMTYPE_EDC1: 2574 return (MEM_EDC1); 2575 case FW_MEMTYPE_EXTMEM: 2576 return (MEM_MC0); 2577 case FW_MEMTYPE_EXTMEM1: 2578 return (MEM_MC1); 2579 default: 2580 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2581 } 2582 } 2583 2584 /* 2585 * Verify that the memory range specified by the memtype/offset/len pair is 2586 * valid and lies entirely within the memtype specified. The global address of 2587 * the start of the range is returned in addr. 2588 */ 2589 static int 2590 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 2591 uint32_t *addr) 2592 { 2593 uint32_t em, addr_len, maddr; 2594 2595 /* Memory can only be accessed in naturally aligned 4 byte units */ 2596 if (off & 3 || len & 3 || len == 0) 2597 return (EINVAL); 2598 2599 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2600 switch (fwmtype_to_hwmtype(mtype)) { 2601 case MEM_EDC0: 2602 if (!(em & F_EDRAM0_ENABLE)) 2603 return (EINVAL); 2604 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2605 maddr = G_EDRAM0_BASE(addr_len) << 20; 2606 break; 2607 case MEM_EDC1: 2608 if (!(em & F_EDRAM1_ENABLE)) 2609 return (EINVAL); 2610 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2611 maddr = G_EDRAM1_BASE(addr_len) << 20; 2612 break; 2613 case MEM_MC: 2614 if (!(em & F_EXT_MEM_ENABLE)) 2615 return (EINVAL); 2616 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2617 maddr = G_EXT_MEM_BASE(addr_len) << 20; 2618 break; 2619 case MEM_MC1: 2620 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 2621 return (EINVAL); 2622 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2623 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 2624 break; 2625 default: 2626 return (EINVAL); 2627 } 2628 2629 *addr = maddr + off; /* global address */ 2630 return (validate_mem_range(sc, *addr, len)); 2631 } 2632 2633 static int 2634 fixup_devlog_params(struct adapter *sc) 2635 { 2636 struct devlog_params *dparams = &sc->params.devlog; 2637 int rc; 2638 2639 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 2640 dparams->size, &dparams->addr); 2641 2642 return (rc); 2643 } 2644 2645 static int 2646 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 2647 { 2648 int rc, itype, navail, nrxq, nports, n; 2649 int nofldrxq = 0; 2650 2651 nports = sc->params.nports; 2652 MPASS(nports > 0); 2653 2654 bzero(iaq, sizeof(*iaq)); 2655 iaq->num_vis = t4_num_vis; 2656 iaq->ntxq = t4_ntxq; 2657 iaq->ntxq_vi = t4_ntxq_vi; 2658 iaq->nrxq = nrxq = t4_nrxq; 2659 iaq->nrxq_vi = t4_nrxq_vi; 2660 #ifdef TCP_OFFLOAD 2661 if (is_offload(sc)) { 2662 iaq->nofldtxq = t4_nofldtxq; 2663 iaq->nofldtxq_vi = t4_nofldtxq_vi; 2664 iaq->nofldrxq = nofldrxq = t4_nofldrxq; 2665 iaq->nofldrxq_vi = t4_nofldrxq_vi; 2666 } 2667 #endif 2668 #ifdef DEV_NETMAP 2669 iaq->nnmtxq_vi = t4_nnmtxq_vi; 2670 iaq->nnmrxq_vi = t4_nnmrxq_vi; 2671 #endif 2672 2673 for (itype = INTR_MSIX; itype; itype >>= 1) { 2674 2675 if ((itype & t4_intr_types) == 0) 2676 continue; /* not allowed */ 2677 2678 if (itype == INTR_MSIX) 2679 navail = pci_msix_count(sc->dev); 2680 else if (itype == INTR_MSI) 2681 navail = pci_msi_count(sc->dev); 2682 else 2683 navail = 1; 2684 restart: 2685 if (navail == 0) 2686 continue; 2687 2688 iaq->intr_type = itype; 2689 iaq->intr_flags = 0; 2690 2691 /* 2692 * Best option: an interrupt vector for errors, one for the 2693 * firmware event queue, and one for every rxq (NIC and TOE) of 2694 * every VI. The VIs that support netmap use the same 2695 * interrupts for the NIC rx queues and the netmap rx queues 2696 * because only one set of queues is active at a time. 2697 */ 2698 iaq->nirq = T4_EXTRA_INTR; 2699 iaq->nirq += nports * (nrxq + nofldrxq); 2700 iaq->nirq += nports * (iaq->num_vis - 1) * 2701 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */ 2702 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 2703 if (iaq->nirq <= navail && 2704 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2705 iaq->intr_flags = INTR_ALL; 2706 goto allocate; 2707 } 2708 2709 /* Disable the VIs (and netmap) if there aren't enough intrs */ 2710 if (iaq->num_vis > 1) { 2711 device_printf(sc->dev, "virtual interfaces disabled " 2712 "because num_vis=%u with current settings " 2713 "(nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 2714 "nnmrxq_vi=%u) would need %u interrupts but " 2715 "only %u are available.\n", iaq->num_vis, nrxq, 2716 nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 2717 iaq->nnmrxq_vi, iaq->nirq, navail); 2718 iaq->num_vis = 1; 2719 iaq->ntxq_vi = iaq->nrxq_vi = 0; 2720 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 2721 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 2722 goto restart; 2723 } 2724 2725 /* 2726 * Second best option: a vector for errors, one for the firmware 2727 * event queue, and vectors for either all the NIC rx queues or 2728 * all the TOE rx queues. The queues that don't get vectors 2729 * will forward their interrupts to those that do. 2730 */ 2731 iaq->nirq = T4_EXTRA_INTR; 2732 if (nrxq >= nofldrxq) { 2733 iaq->intr_flags = INTR_RXQ; 2734 iaq->nirq += nports * nrxq; 2735 } else { 2736 iaq->intr_flags = INTR_OFLD_RXQ; 2737 iaq->nirq += nports * nofldrxq; 2738 } 2739 if (iaq->nirq <= navail && 2740 (itype != INTR_MSI || powerof2(iaq->nirq))) 2741 goto allocate; 2742 2743 /* 2744 * Next best option: an interrupt vector for errors, one for the 2745 * firmware event queue, and at least one per main-VI. At this 2746 * point we know we'll have to downsize nrxq and/or nofldrxq to 2747 * fit what's available to us. 2748 */ 2749 iaq->nirq = T4_EXTRA_INTR; 2750 iaq->nirq += nports; 2751 if (iaq->nirq <= navail) { 2752 int leftover = navail - iaq->nirq; 2753 int target = max(nrxq, nofldrxq); 2754 2755 iaq->intr_flags = nrxq >= nofldrxq ? 2756 INTR_RXQ : INTR_OFLD_RXQ; 2757 2758 n = 1; 2759 while (n < target && leftover >= nports) { 2760 leftover -= nports; 2761 iaq->nirq += nports; 2762 n++; 2763 } 2764 iaq->nrxq = min(n, nrxq); 2765 #ifdef TCP_OFFLOAD 2766 iaq->nofldrxq = min(n, nofldrxq); 2767 #endif 2768 2769 if (itype != INTR_MSI || powerof2(iaq->nirq)) 2770 goto allocate; 2771 } 2772 2773 /* 2774 * Least desirable option: one interrupt vector for everything. 2775 */ 2776 iaq->nirq = iaq->nrxq = 1; 2777 iaq->intr_flags = 0; 2778 #ifdef TCP_OFFLOAD 2779 if (is_offload(sc)) 2780 iaq->nofldrxq = 1; 2781 #endif 2782 allocate: 2783 navail = iaq->nirq; 2784 rc = 0; 2785 if (itype == INTR_MSIX) 2786 rc = pci_alloc_msix(sc->dev, &navail); 2787 else if (itype == INTR_MSI) 2788 rc = pci_alloc_msi(sc->dev, &navail); 2789 2790 if (rc == 0) { 2791 if (navail == iaq->nirq) 2792 return (0); 2793 2794 /* 2795 * Didn't get the number requested. Use whatever number 2796 * the kernel is willing to allocate (it's in navail). 2797 */ 2798 device_printf(sc->dev, "fewer vectors than requested, " 2799 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 2800 itype, iaq->nirq, navail); 2801 pci_release_msi(sc->dev); 2802 goto restart; 2803 } 2804 2805 device_printf(sc->dev, 2806 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 2807 itype, rc, iaq->nirq, navail); 2808 } 2809 2810 device_printf(sc->dev, 2811 "failed to find a usable interrupt type. " 2812 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 2813 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 2814 2815 return (ENXIO); 2816 } 2817 2818 #define FW_VERSION(chip) ( \ 2819 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 2820 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 2821 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 2822 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 2823 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 2824 2825 struct fw_info { 2826 uint8_t chip; 2827 char *kld_name; 2828 char *fw_mod_name; 2829 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 2830 } fw_info[] = { 2831 { 2832 .chip = CHELSIO_T4, 2833 .kld_name = "t4fw_cfg", 2834 .fw_mod_name = "t4fw", 2835 .fw_hdr = { 2836 .chip = FW_HDR_CHIP_T4, 2837 .fw_ver = htobe32_const(FW_VERSION(T4)), 2838 .intfver_nic = FW_INTFVER(T4, NIC), 2839 .intfver_vnic = FW_INTFVER(T4, VNIC), 2840 .intfver_ofld = FW_INTFVER(T4, OFLD), 2841 .intfver_ri = FW_INTFVER(T4, RI), 2842 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 2843 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 2844 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 2845 .intfver_fcoe = FW_INTFVER(T4, FCOE), 2846 }, 2847 }, { 2848 .chip = CHELSIO_T5, 2849 .kld_name = "t5fw_cfg", 2850 .fw_mod_name = "t5fw", 2851 .fw_hdr = { 2852 .chip = FW_HDR_CHIP_T5, 2853 .fw_ver = htobe32_const(FW_VERSION(T5)), 2854 .intfver_nic = FW_INTFVER(T5, NIC), 2855 .intfver_vnic = FW_INTFVER(T5, VNIC), 2856 .intfver_ofld = FW_INTFVER(T5, OFLD), 2857 .intfver_ri = FW_INTFVER(T5, RI), 2858 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 2859 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 2860 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 2861 .intfver_fcoe = FW_INTFVER(T5, FCOE), 2862 }, 2863 }, { 2864 .chip = CHELSIO_T6, 2865 .kld_name = "t6fw_cfg", 2866 .fw_mod_name = "t6fw", 2867 .fw_hdr = { 2868 .chip = FW_HDR_CHIP_T6, 2869 .fw_ver = htobe32_const(FW_VERSION(T6)), 2870 .intfver_nic = FW_INTFVER(T6, NIC), 2871 .intfver_vnic = FW_INTFVER(T6, VNIC), 2872 .intfver_ofld = FW_INTFVER(T6, OFLD), 2873 .intfver_ri = FW_INTFVER(T6, RI), 2874 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 2875 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 2876 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 2877 .intfver_fcoe = FW_INTFVER(T6, FCOE), 2878 }, 2879 } 2880 }; 2881 2882 static struct fw_info * 2883 find_fw_info(int chip) 2884 { 2885 int i; 2886 2887 for (i = 0; i < nitems(fw_info); i++) { 2888 if (fw_info[i].chip == chip) 2889 return (&fw_info[i]); 2890 } 2891 return (NULL); 2892 } 2893 2894 /* 2895 * Is the given firmware API compatible with the one the driver was compiled 2896 * with? 2897 */ 2898 static int 2899 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 2900 { 2901 2902 /* short circuit if it's the exact same firmware version */ 2903 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 2904 return (1); 2905 2906 /* 2907 * XXX: Is this too conservative? Perhaps I should limit this to the 2908 * features that are supported in the driver. 2909 */ 2910 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 2911 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 2912 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 2913 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 2914 return (1); 2915 #undef SAME_INTF 2916 2917 return (0); 2918 } 2919 2920 /* 2921 * The firmware in the KLD is usable, but should it be installed? This routine 2922 * explains itself in detail if it indicates the KLD firmware should be 2923 * installed. 2924 */ 2925 static int 2926 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 2927 { 2928 const char *reason; 2929 2930 if (!card_fw_usable) { 2931 reason = "incompatible or unusable"; 2932 goto install; 2933 } 2934 2935 if (k > c) { 2936 reason = "older than the version bundled with this driver"; 2937 goto install; 2938 } 2939 2940 if (t4_fw_install == 2 && k != c) { 2941 reason = "different than the version bundled with this driver"; 2942 goto install; 2943 } 2944 2945 return (0); 2946 2947 install: 2948 if (t4_fw_install == 0) { 2949 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2950 "but the driver is prohibited from installing a different " 2951 "firmware on the card.\n", 2952 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2953 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 2954 2955 return (0); 2956 } 2957 2958 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2959 "installing firmware %u.%u.%u.%u on card.\n", 2960 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2961 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 2962 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 2963 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 2964 2965 return (1); 2966 } 2967 2968 /* 2969 * Establish contact with the firmware and determine if we are the master driver 2970 * or not, and whether we are responsible for chip initialization. 2971 */ 2972 static int 2973 prep_firmware(struct adapter *sc) 2974 { 2975 const struct firmware *fw = NULL, *default_cfg; 2976 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 2977 enum dev_state state; 2978 struct fw_info *fw_info; 2979 struct fw_hdr *card_fw; /* fw on the card */ 2980 const struct fw_hdr *kld_fw; /* fw in the KLD */ 2981 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 2982 against */ 2983 2984 /* This is the firmware whose headers the driver was compiled against */ 2985 fw_info = find_fw_info(chip_id(sc)); 2986 if (fw_info == NULL) { 2987 device_printf(sc->dev, 2988 "unable to look up firmware information for chip %d.\n", 2989 chip_id(sc)); 2990 return (EINVAL); 2991 } 2992 drv_fw = &fw_info->fw_hdr; 2993 2994 /* 2995 * The firmware KLD contains many modules. The KLD name is also the 2996 * name of the module that contains the default config file. 2997 */ 2998 default_cfg = firmware_get(fw_info->kld_name); 2999 3000 /* This is the firmware in the KLD */ 3001 fw = firmware_get(fw_info->fw_mod_name); 3002 if (fw != NULL) { 3003 kld_fw = (const void *)fw->data; 3004 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 3005 } else { 3006 kld_fw = NULL; 3007 kld_fw_usable = 0; 3008 } 3009 3010 /* Read the header of the firmware on the card */ 3011 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3012 rc = -t4_read_flash(sc, FLASH_FW_START, 3013 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 3014 if (rc == 0) { 3015 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 3016 if (card_fw->fw_ver == be32toh(0xffffffff)) { 3017 uint32_t d = be32toh(kld_fw->fw_ver); 3018 3019 if (!kld_fw_usable) { 3020 device_printf(sc->dev, 3021 "no firmware on the card and no usable " 3022 "firmware bundled with the driver.\n"); 3023 rc = EIO; 3024 goto done; 3025 } else if (t4_fw_install == 0) { 3026 device_printf(sc->dev, 3027 "no firmware on the card and the driver " 3028 "is prohibited from installing new " 3029 "firmware.\n"); 3030 rc = EIO; 3031 goto done; 3032 } 3033 3034 device_printf(sc->dev, "no firmware on the card, " 3035 "installing firmware %d.%d.%d.%d\n", 3036 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3037 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3038 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize); 3039 if (rc < 0) { 3040 rc = -rc; 3041 device_printf(sc->dev, 3042 "firmware install failed: %d.\n", rc); 3043 goto done; 3044 } 3045 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3046 card_fw_usable = 1; 3047 need_fw_reset = 0; 3048 } 3049 } else { 3050 device_printf(sc->dev, 3051 "Unable to read card's firmware header: %d\n", rc); 3052 card_fw_usable = 0; 3053 } 3054 3055 /* Contact firmware. */ 3056 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3057 if (rc < 0 || state == DEV_STATE_ERR) { 3058 rc = -rc; 3059 device_printf(sc->dev, 3060 "failed to connect to the firmware: %d, %d.\n", rc, state); 3061 goto done; 3062 } 3063 pf = rc; 3064 if (pf == sc->mbox) 3065 sc->flags |= MASTER_PF; 3066 else if (state == DEV_STATE_UNINIT) { 3067 /* 3068 * We didn't get to be the master so we definitely won't be 3069 * configuring the chip. It's a bug if someone else hasn't 3070 * configured it already. 3071 */ 3072 device_printf(sc->dev, "couldn't be master(%d), " 3073 "device not already initialized either(%d).\n", rc, state); 3074 rc = EPROTO; 3075 goto done; 3076 } 3077 3078 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 3079 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 3080 /* 3081 * Common case: the firmware on the card is an exact match and 3082 * the KLD is an exact match too, or the KLD is 3083 * absent/incompatible. Note that t4_fw_install = 2 is ignored 3084 * here -- use cxgbetool loadfw if you want to reinstall the 3085 * same firmware as the one on the card. 3086 */ 3087 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 3088 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 3089 be32toh(card_fw->fw_ver))) { 3090 3091 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3092 if (rc != 0) { 3093 device_printf(sc->dev, 3094 "failed to install firmware: %d\n", rc); 3095 goto done; 3096 } 3097 3098 /* Installed successfully, update the cached header too. */ 3099 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3100 card_fw_usable = 1; 3101 need_fw_reset = 0; /* already reset as part of load_fw */ 3102 } 3103 3104 if (!card_fw_usable) { 3105 uint32_t d, c, k; 3106 3107 d = ntohl(drv_fw->fw_ver); 3108 c = ntohl(card_fw->fw_ver); 3109 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3110 3111 device_printf(sc->dev, "Cannot find a usable firmware: " 3112 "fw_install %d, chip state %d, " 3113 "driver compiled with %d.%d.%d.%d, " 3114 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3115 t4_fw_install, state, 3116 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3117 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3118 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3119 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3120 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3121 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3122 rc = EINVAL; 3123 goto done; 3124 } 3125 3126 /* Reset device */ 3127 if (need_fw_reset && 3128 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3129 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3130 if (rc != ETIMEDOUT && rc != EIO) 3131 t4_fw_bye(sc, sc->mbox); 3132 goto done; 3133 } 3134 sc->flags |= FW_OK; 3135 3136 rc = get_params__pre_init(sc); 3137 if (rc != 0) 3138 goto done; /* error message displayed already */ 3139 3140 /* Partition adapter resources as specified in the config file. */ 3141 if (state == DEV_STATE_UNINIT) { 3142 3143 KASSERT(sc->flags & MASTER_PF, 3144 ("%s: trying to change chip settings when not master.", 3145 __func__)); 3146 3147 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3148 if (rc != 0) 3149 goto done; /* error message displayed already */ 3150 3151 t4_tweak_chip_settings(sc); 3152 3153 /* get basic stuff going */ 3154 rc = -t4_fw_initialize(sc, sc->mbox); 3155 if (rc != 0) { 3156 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3157 goto done; 3158 } 3159 } else { 3160 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3161 sc->cfcsum = 0; 3162 } 3163 3164 done: 3165 free(card_fw, M_CXGBE); 3166 if (fw != NULL) 3167 firmware_put(fw, FIRMWARE_UNLOAD); 3168 if (default_cfg != NULL) 3169 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3170 3171 return (rc); 3172 } 3173 3174 #define FW_PARAM_DEV(param) \ 3175 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3176 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3177 #define FW_PARAM_PFVF(param) \ 3178 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3179 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3180 3181 /* 3182 * Partition chip resources for use between various PFs, VFs, etc. 3183 */ 3184 static int 3185 partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3186 const char *name_prefix) 3187 { 3188 const struct firmware *cfg = NULL; 3189 int rc = 0; 3190 struct fw_caps_config_cmd caps; 3191 uint32_t mtype, moff, finicsum, cfcsum; 3192 3193 /* 3194 * Figure out what configuration file to use. Pick the default config 3195 * file for the card if the user hasn't specified one explicitly. 3196 */ 3197 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3198 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3199 /* Card specific overrides go here. */ 3200 if (pci_get_device(sc->dev) == 0x440a) 3201 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3202 if (is_fpga(sc)) 3203 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3204 } 3205 3206 /* 3207 * We need to load another module if the profile is anything except 3208 * "default" or "flash". 3209 */ 3210 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3211 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3212 char s[32]; 3213 3214 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3215 cfg = firmware_get(s); 3216 if (cfg == NULL) { 3217 if (default_cfg != NULL) { 3218 device_printf(sc->dev, 3219 "unable to load module \"%s\" for " 3220 "configuration profile \"%s\", will use " 3221 "the default config file instead.\n", 3222 s, sc->cfg_file); 3223 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3224 "%s", DEFAULT_CF); 3225 } else { 3226 device_printf(sc->dev, 3227 "unable to load module \"%s\" for " 3228 "configuration profile \"%s\", will use " 3229 "the config file on the card's flash " 3230 "instead.\n", s, sc->cfg_file); 3231 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3232 "%s", FLASH_CF); 3233 } 3234 } 3235 } 3236 3237 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3238 default_cfg == NULL) { 3239 device_printf(sc->dev, 3240 "default config file not available, will use the config " 3241 "file on the card's flash instead.\n"); 3242 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3243 } 3244 3245 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3246 u_int cflen; 3247 const uint32_t *cfdata; 3248 uint32_t param, val, addr; 3249 3250 KASSERT(cfg != NULL || default_cfg != NULL, 3251 ("%s: no config to upload", __func__)); 3252 3253 /* 3254 * Ask the firmware where it wants us to upload the config file. 3255 */ 3256 param = FW_PARAM_DEV(CF); 3257 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3258 if (rc != 0) { 3259 /* No support for config file? Shouldn't happen. */ 3260 device_printf(sc->dev, 3261 "failed to query config file location: %d.\n", rc); 3262 goto done; 3263 } 3264 mtype = G_FW_PARAMS_PARAM_Y(val); 3265 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3266 3267 /* 3268 * XXX: sheer laziness. We deliberately added 4 bytes of 3269 * useless stuffing/comments at the end of the config file so 3270 * it's ok to simply throw away the last remaining bytes when 3271 * the config file is not an exact multiple of 4. This also 3272 * helps with the validate_mt_off_len check. 3273 */ 3274 if (cfg != NULL) { 3275 cflen = cfg->datasize & ~3; 3276 cfdata = cfg->data; 3277 } else { 3278 cflen = default_cfg->datasize & ~3; 3279 cfdata = default_cfg->data; 3280 } 3281 3282 if (cflen > FLASH_CFG_MAX_SIZE) { 3283 device_printf(sc->dev, 3284 "config file too long (%d, max allowed is %d). " 3285 "Will try to use the config on the card, if any.\n", 3286 cflen, FLASH_CFG_MAX_SIZE); 3287 goto use_config_on_flash; 3288 } 3289 3290 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3291 if (rc != 0) { 3292 device_printf(sc->dev, 3293 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3294 "Will try to use the config on the card, if any.\n", 3295 __func__, mtype, moff, cflen, rc); 3296 goto use_config_on_flash; 3297 } 3298 write_via_memwin(sc, 2, addr, cfdata, cflen); 3299 } else { 3300 use_config_on_flash: 3301 mtype = FW_MEMTYPE_FLASH; 3302 moff = t4_flash_cfg_addr(sc); 3303 } 3304 3305 bzero(&caps, sizeof(caps)); 3306 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3307 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3308 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3309 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3310 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3311 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3312 if (rc != 0) { 3313 device_printf(sc->dev, 3314 "failed to pre-process config file: %d " 3315 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3316 goto done; 3317 } 3318 3319 finicsum = be32toh(caps.finicsum); 3320 cfcsum = be32toh(caps.cfcsum); 3321 if (finicsum != cfcsum) { 3322 device_printf(sc->dev, 3323 "WARNING: config file checksum mismatch: %08x %08x\n", 3324 finicsum, cfcsum); 3325 } 3326 sc->cfcsum = cfcsum; 3327 3328 #define LIMIT_CAPS(x) do { \ 3329 caps.x &= htobe16(t4_##x##_allowed); \ 3330 } while (0) 3331 3332 /* 3333 * Let the firmware know what features will (not) be used so it can tune 3334 * things accordingly. 3335 */ 3336 LIMIT_CAPS(nbmcaps); 3337 LIMIT_CAPS(linkcaps); 3338 LIMIT_CAPS(switchcaps); 3339 LIMIT_CAPS(niccaps); 3340 LIMIT_CAPS(toecaps); 3341 LIMIT_CAPS(rdmacaps); 3342 LIMIT_CAPS(cryptocaps); 3343 LIMIT_CAPS(iscsicaps); 3344 LIMIT_CAPS(fcoecaps); 3345 #undef LIMIT_CAPS 3346 3347 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3348 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3349 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3350 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3351 if (rc != 0) { 3352 device_printf(sc->dev, 3353 "failed to process config file: %d.\n", rc); 3354 } 3355 done: 3356 if (cfg != NULL) 3357 firmware_put(cfg, FIRMWARE_UNLOAD); 3358 return (rc); 3359 } 3360 3361 /* 3362 * Retrieve parameters that are needed (or nice to have) very early. 3363 */ 3364 static int 3365 get_params__pre_init(struct adapter *sc) 3366 { 3367 int rc; 3368 uint32_t param[2], val[2]; 3369 3370 t4_get_version_info(sc); 3371 3372 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3373 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3374 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3375 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3376 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3377 3378 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3379 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3380 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3381 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3382 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3383 3384 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3385 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3386 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3387 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3388 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3389 3390 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3391 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3392 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3393 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3394 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3395 3396 param[0] = FW_PARAM_DEV(PORTVEC); 3397 param[1] = FW_PARAM_DEV(CCLK); 3398 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3399 if (rc != 0) { 3400 device_printf(sc->dev, 3401 "failed to query parameters (pre_init): %d.\n", rc); 3402 return (rc); 3403 } 3404 3405 sc->params.portvec = val[0]; 3406 sc->params.nports = bitcount32(val[0]); 3407 sc->params.vpd.cclk = val[1]; 3408 3409 /* Read device log parameters. */ 3410 rc = -t4_init_devlog_params(sc, 1); 3411 if (rc == 0) 3412 fixup_devlog_params(sc); 3413 else { 3414 device_printf(sc->dev, 3415 "failed to get devlog parameters: %d.\n", rc); 3416 rc = 0; /* devlog isn't critical for device operation */ 3417 } 3418 3419 return (rc); 3420 } 3421 3422 /* 3423 * Retrieve various parameters that are of interest to the driver. The device 3424 * has been initialized by the firmware at this point. 3425 */ 3426 static int 3427 get_params__post_init(struct adapter *sc) 3428 { 3429 int rc; 3430 uint32_t param[7], val[7]; 3431 struct fw_caps_config_cmd caps; 3432 3433 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3434 param[1] = FW_PARAM_PFVF(EQ_START); 3435 param[2] = FW_PARAM_PFVF(FILTER_START); 3436 param[3] = FW_PARAM_PFVF(FILTER_END); 3437 param[4] = FW_PARAM_PFVF(L2T_START); 3438 param[5] = FW_PARAM_PFVF(L2T_END); 3439 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3440 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 3441 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 3442 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 3443 if (rc != 0) { 3444 device_printf(sc->dev, 3445 "failed to query parameters (post_init): %d.\n", rc); 3446 return (rc); 3447 } 3448 3449 sc->sge.iq_start = val[0]; 3450 sc->sge.eq_start = val[1]; 3451 sc->tids.ftid_base = val[2]; 3452 sc->tids.nftids = val[3] - val[2] + 1; 3453 sc->params.ftid_min = val[2]; 3454 sc->params.ftid_max = val[3]; 3455 sc->vres.l2t.start = val[4]; 3456 sc->vres.l2t.size = val[5] - val[4] + 1; 3457 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3458 ("%s: L2 table size (%u) larger than expected (%u)", 3459 __func__, sc->vres.l2t.size, L2T_SIZE)); 3460 sc->params.core_vdd = val[6]; 3461 3462 /* 3463 * MPSBGMAP is queried separately because only recent firmwares support 3464 * it as a parameter and we don't want the compound query above to fail 3465 * on older firmwares. 3466 */ 3467 param[0] = FW_PARAM_DEV(MPSBGMAP); 3468 val[0] = 0; 3469 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3470 if (rc == 0) 3471 sc->params.mps_bg_map = val[0]; 3472 else 3473 sc->params.mps_bg_map = 0; 3474 3475 /* get capabilites */ 3476 bzero(&caps, sizeof(caps)); 3477 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3478 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3479 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3480 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3481 if (rc != 0) { 3482 device_printf(sc->dev, 3483 "failed to get card capabilities: %d.\n", rc); 3484 return (rc); 3485 } 3486 3487 #define READ_CAPS(x) do { \ 3488 sc->x = htobe16(caps.x); \ 3489 } while (0) 3490 READ_CAPS(nbmcaps); 3491 READ_CAPS(linkcaps); 3492 READ_CAPS(switchcaps); 3493 READ_CAPS(niccaps); 3494 READ_CAPS(toecaps); 3495 READ_CAPS(rdmacaps); 3496 READ_CAPS(cryptocaps); 3497 READ_CAPS(iscsicaps); 3498 READ_CAPS(fcoecaps); 3499 3500 /* 3501 * The firmware attempts memfree TOE configuration for -SO cards and 3502 * will report toecaps=0 if it runs out of resources (this depends on 3503 * the config file). It may not report 0 for other capabilities 3504 * dependent on the TOE in this case. Set them to 0 here so that the 3505 * driver doesn't bother tracking resources that will never be used. 3506 */ 3507 if (sc->toecaps == 0) { 3508 sc->iscsicaps = 0; 3509 sc->rdmacaps = 0; 3510 } 3511 3512 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 3513 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 3514 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 3515 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3516 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 3517 if (rc != 0) { 3518 device_printf(sc->dev, 3519 "failed to query NIC parameters: %d.\n", rc); 3520 return (rc); 3521 } 3522 sc->tids.etid_base = val[0]; 3523 sc->params.etid_min = val[0]; 3524 sc->tids.netids = val[1] - val[0] + 1; 3525 sc->params.netids = sc->tids.netids; 3526 sc->params.eo_wr_cred = val[2]; 3527 sc->params.ethoffload = 1; 3528 } 3529 3530 if (sc->toecaps) { 3531 /* query offload-related parameters */ 3532 param[0] = FW_PARAM_DEV(NTID); 3533 param[1] = FW_PARAM_PFVF(SERVER_START); 3534 param[2] = FW_PARAM_PFVF(SERVER_END); 3535 param[3] = FW_PARAM_PFVF(TDDP_START); 3536 param[4] = FW_PARAM_PFVF(TDDP_END); 3537 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3538 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3539 if (rc != 0) { 3540 device_printf(sc->dev, 3541 "failed to query TOE parameters: %d.\n", rc); 3542 return (rc); 3543 } 3544 sc->tids.ntids = val[0]; 3545 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3546 sc->tids.stid_base = val[1]; 3547 sc->tids.nstids = val[2] - val[1] + 1; 3548 sc->vres.ddp.start = val[3]; 3549 sc->vres.ddp.size = val[4] - val[3] + 1; 3550 sc->params.ofldq_wr_cred = val[5]; 3551 sc->params.offload = 1; 3552 } 3553 if (sc->rdmacaps) { 3554 param[0] = FW_PARAM_PFVF(STAG_START); 3555 param[1] = FW_PARAM_PFVF(STAG_END); 3556 param[2] = FW_PARAM_PFVF(RQ_START); 3557 param[3] = FW_PARAM_PFVF(RQ_END); 3558 param[4] = FW_PARAM_PFVF(PBL_START); 3559 param[5] = FW_PARAM_PFVF(PBL_END); 3560 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3561 if (rc != 0) { 3562 device_printf(sc->dev, 3563 "failed to query RDMA parameters(1): %d.\n", rc); 3564 return (rc); 3565 } 3566 sc->vres.stag.start = val[0]; 3567 sc->vres.stag.size = val[1] - val[0] + 1; 3568 sc->vres.rq.start = val[2]; 3569 sc->vres.rq.size = val[3] - val[2] + 1; 3570 sc->vres.pbl.start = val[4]; 3571 sc->vres.pbl.size = val[5] - val[4] + 1; 3572 3573 param[0] = FW_PARAM_PFVF(SQRQ_START); 3574 param[1] = FW_PARAM_PFVF(SQRQ_END); 3575 param[2] = FW_PARAM_PFVF(CQ_START); 3576 param[3] = FW_PARAM_PFVF(CQ_END); 3577 param[4] = FW_PARAM_PFVF(OCQ_START); 3578 param[5] = FW_PARAM_PFVF(OCQ_END); 3579 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3580 if (rc != 0) { 3581 device_printf(sc->dev, 3582 "failed to query RDMA parameters(2): %d.\n", rc); 3583 return (rc); 3584 } 3585 sc->vres.qp.start = val[0]; 3586 sc->vres.qp.size = val[1] - val[0] + 1; 3587 sc->vres.cq.start = val[2]; 3588 sc->vres.cq.size = val[3] - val[2] + 1; 3589 sc->vres.ocq.start = val[4]; 3590 sc->vres.ocq.size = val[5] - val[4] + 1; 3591 3592 param[0] = FW_PARAM_PFVF(SRQ_START); 3593 param[1] = FW_PARAM_PFVF(SRQ_END); 3594 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 3595 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 3596 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 3597 if (rc != 0) { 3598 device_printf(sc->dev, 3599 "failed to query RDMA parameters(3): %d.\n", rc); 3600 return (rc); 3601 } 3602 sc->vres.srq.start = val[0]; 3603 sc->vres.srq.size = val[1] - val[0] + 1; 3604 sc->params.max_ordird_qp = val[2]; 3605 sc->params.max_ird_adapter = val[3]; 3606 } 3607 if (sc->iscsicaps) { 3608 param[0] = FW_PARAM_PFVF(ISCSI_START); 3609 param[1] = FW_PARAM_PFVF(ISCSI_END); 3610 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3611 if (rc != 0) { 3612 device_printf(sc->dev, 3613 "failed to query iSCSI parameters: %d.\n", rc); 3614 return (rc); 3615 } 3616 sc->vres.iscsi.start = val[0]; 3617 sc->vres.iscsi.size = val[1] - val[0] + 1; 3618 } 3619 3620 t4_init_sge_params(sc); 3621 3622 /* 3623 * We've got the params we wanted to query via the firmware. Now grab 3624 * some others directly from the chip. 3625 */ 3626 rc = t4_read_chip_settings(sc); 3627 3628 return (rc); 3629 } 3630 3631 static int 3632 set_params__post_init(struct adapter *sc) 3633 { 3634 uint32_t param, val; 3635 #ifdef TCP_OFFLOAD 3636 int i, v, shift; 3637 #endif 3638 3639 /* ask for encapsulated CPLs */ 3640 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3641 val = 1; 3642 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3643 3644 #ifdef TCP_OFFLOAD 3645 /* 3646 * Override the TOE timers with user provided tunables. This is not the 3647 * recommended way to change the timers (the firmware config file is) so 3648 * these tunables are not documented. 3649 * 3650 * All the timer tunables are in microseconds. 3651 */ 3652 if (t4_toe_keepalive_idle != 0) { 3653 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 3654 v &= M_KEEPALIVEIDLE; 3655 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 3656 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 3657 } 3658 if (t4_toe_keepalive_interval != 0) { 3659 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 3660 v &= M_KEEPALIVEINTVL; 3661 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 3662 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 3663 } 3664 if (t4_toe_keepalive_count != 0) { 3665 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 3666 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 3667 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 3668 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 3669 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 3670 } 3671 if (t4_toe_rexmt_min != 0) { 3672 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 3673 v &= M_RXTMIN; 3674 t4_set_reg_field(sc, A_TP_RXT_MIN, 3675 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 3676 } 3677 if (t4_toe_rexmt_max != 0) { 3678 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 3679 v &= M_RXTMAX; 3680 t4_set_reg_field(sc, A_TP_RXT_MAX, 3681 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 3682 } 3683 if (t4_toe_rexmt_count != 0) { 3684 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 3685 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 3686 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 3687 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 3688 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 3689 } 3690 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 3691 if (t4_toe_rexmt_backoff[i] != -1) { 3692 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 3693 shift = (i & 3) << 3; 3694 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 3695 M_TIMERBACKOFFINDEX0 << shift, v << shift); 3696 } 3697 } 3698 #endif 3699 return (0); 3700 } 3701 3702 #undef FW_PARAM_PFVF 3703 #undef FW_PARAM_DEV 3704 3705 static void 3706 t4_set_desc(struct adapter *sc) 3707 { 3708 char buf[128]; 3709 struct adapter_params *p = &sc->params; 3710 3711 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 3712 3713 device_set_desc_copy(sc->dev, buf); 3714 } 3715 3716 static void 3717 build_medialist(struct port_info *pi, struct ifmedia *media) 3718 { 3719 int m; 3720 3721 PORT_LOCK_ASSERT_OWNED(pi); 3722 3723 ifmedia_removeall(media); 3724 3725 /* 3726 * XXX: Would it be better to ifmedia_add all 4 combinations of pause 3727 * settings for every speed instead of just txpause|rxpause? ifconfig 3728 * media display looks much better if autoselect is the only case where 3729 * ifm_current is different from ifm_active. If the user picks anything 3730 * except txpause|rxpause the display is ugly. 3731 */ 3732 m = IFM_ETHER | IFM_FDX | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 3733 3734 switch(pi->port_type) { 3735 case FW_PORT_TYPE_BT_XFI: 3736 case FW_PORT_TYPE_BT_XAUI: 3737 ifmedia_add(media, m | IFM_10G_T, 0, NULL); 3738 /* fall through */ 3739 3740 case FW_PORT_TYPE_BT_SGMII: 3741 ifmedia_add(media, m | IFM_1000_T, 0, NULL); 3742 ifmedia_add(media, m | IFM_100_TX, 0, NULL); 3743 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL); 3744 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 3745 break; 3746 3747 case FW_PORT_TYPE_CX4: 3748 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL); 3749 ifmedia_set(media, m | IFM_10G_CX4); 3750 break; 3751 3752 case FW_PORT_TYPE_QSFP_10G: 3753 case FW_PORT_TYPE_SFP: 3754 case FW_PORT_TYPE_FIBER_XFI: 3755 case FW_PORT_TYPE_FIBER_XAUI: 3756 switch (pi->mod_type) { 3757 3758 case FW_PORT_MOD_TYPE_LR: 3759 ifmedia_add(media, m | IFM_10G_LR, 0, NULL); 3760 ifmedia_set(media, m | IFM_10G_LR); 3761 break; 3762 3763 case FW_PORT_MOD_TYPE_SR: 3764 ifmedia_add(media, m | IFM_10G_SR, 0, NULL); 3765 ifmedia_set(media, m | IFM_10G_SR); 3766 break; 3767 3768 case FW_PORT_MOD_TYPE_LRM: 3769 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL); 3770 ifmedia_set(media, m | IFM_10G_LRM); 3771 break; 3772 3773 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3774 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3775 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL); 3776 ifmedia_set(media, m | IFM_10G_TWINAX); 3777 break; 3778 3779 case FW_PORT_MOD_TYPE_NONE: 3780 m &= ~IFM_FDX; 3781 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3782 ifmedia_set(media, m | IFM_NONE); 3783 break; 3784 3785 case FW_PORT_MOD_TYPE_NA: 3786 case FW_PORT_MOD_TYPE_ER: 3787 default: 3788 device_printf(pi->dev, 3789 "unknown port_type (%d), mod_type (%d)\n", 3790 pi->port_type, pi->mod_type); 3791 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3792 ifmedia_set(media, m | IFM_UNKNOWN); 3793 break; 3794 } 3795 break; 3796 3797 case FW_PORT_TYPE_CR_QSFP: 3798 case FW_PORT_TYPE_SFP28: 3799 case FW_PORT_TYPE_KR_SFP28: 3800 switch (pi->mod_type) { 3801 3802 case FW_PORT_MOD_TYPE_SR: 3803 ifmedia_add(media, m | IFM_25G_SR, 0, NULL); 3804 ifmedia_set(media, m | IFM_25G_SR); 3805 break; 3806 3807 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3808 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3809 ifmedia_add(media, m | IFM_25G_CR, 0, NULL); 3810 ifmedia_set(media, m | IFM_25G_CR); 3811 break; 3812 3813 case FW_PORT_MOD_TYPE_NONE: 3814 m &= ~IFM_FDX; 3815 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3816 ifmedia_set(media, m | IFM_NONE); 3817 break; 3818 3819 default: 3820 device_printf(pi->dev, 3821 "unknown port_type (%d), mod_type (%d)\n", 3822 pi->port_type, pi->mod_type); 3823 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3824 ifmedia_set(media, m | IFM_UNKNOWN); 3825 break; 3826 } 3827 break; 3828 3829 case FW_PORT_TYPE_QSFP: 3830 switch (pi->mod_type) { 3831 3832 case FW_PORT_MOD_TYPE_LR: 3833 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL); 3834 ifmedia_set(media, m | IFM_40G_LR4); 3835 break; 3836 3837 case FW_PORT_MOD_TYPE_SR: 3838 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL); 3839 ifmedia_set(media, m | IFM_40G_SR4); 3840 break; 3841 3842 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3843 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3844 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL); 3845 ifmedia_set(media, m | IFM_40G_CR4); 3846 break; 3847 3848 case FW_PORT_MOD_TYPE_NONE: 3849 m &= ~IFM_FDX; 3850 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3851 ifmedia_set(media, m | IFM_NONE); 3852 break; 3853 3854 default: 3855 device_printf(pi->dev, 3856 "unknown port_type (%d), mod_type (%d)\n", 3857 pi->port_type, pi->mod_type); 3858 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3859 ifmedia_set(media, m | IFM_UNKNOWN); 3860 break; 3861 } 3862 break; 3863 3864 case FW_PORT_TYPE_KR4_100G: 3865 case FW_PORT_TYPE_CR4_QSFP: 3866 switch (pi->mod_type) { 3867 3868 case FW_PORT_MOD_TYPE_LR: 3869 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL); 3870 ifmedia_set(media, m | IFM_100G_LR4); 3871 break; 3872 3873 case FW_PORT_MOD_TYPE_SR: 3874 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL); 3875 ifmedia_set(media, m | IFM_100G_SR4); 3876 break; 3877 3878 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3879 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3880 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL); 3881 ifmedia_set(media, m | IFM_100G_CR4); 3882 break; 3883 3884 case FW_PORT_MOD_TYPE_NONE: 3885 m &= ~IFM_FDX; 3886 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3887 ifmedia_set(media, m | IFM_NONE); 3888 break; 3889 3890 default: 3891 device_printf(pi->dev, 3892 "unknown port_type (%d), mod_type (%d)\n", 3893 pi->port_type, pi->mod_type); 3894 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3895 ifmedia_set(media, m | IFM_UNKNOWN); 3896 break; 3897 } 3898 break; 3899 3900 default: 3901 device_printf(pi->dev, 3902 "unknown port_type (%d), mod_type (%d)\n", pi->port_type, 3903 pi->mod_type); 3904 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3905 ifmedia_set(media, m | IFM_UNKNOWN); 3906 break; 3907 } 3908 } 3909 3910 /* 3911 * Update all the requested_* fields in the link config and then send a mailbox 3912 * command to apply the settings. 3913 */ 3914 static void 3915 init_l1cfg(struct port_info *pi) 3916 { 3917 struct adapter *sc = pi->adapter; 3918 struct link_config *lc = &pi->link_cfg; 3919 int rc; 3920 3921 ASSERT_SYNCHRONIZED_OP(sc); 3922 3923 if (t4_autoneg != 0 && lc->supported & FW_PORT_CAP_ANEG) { 3924 lc->requested_aneg = AUTONEG_ENABLE; 3925 lc->requested_speed = 0; 3926 } else { 3927 lc->requested_aneg = AUTONEG_DISABLE; 3928 lc->requested_speed = port_top_speed(pi); /* in Gbps */ 3929 } 3930 3931 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX); 3932 3933 if (t4_fec != -1) { 3934 lc->requested_fec = t4_fec & (FEC_RS | FEC_BASER_RS | 3935 FEC_RESERVED); 3936 } else { 3937 /* Use the suggested value provided by the firmware in acaps */ 3938 if (lc->advertising & FW_PORT_CAP_FEC_RS) 3939 lc->requested_fec = FEC_RS; 3940 else if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS) 3941 lc->requested_fec = FEC_BASER_RS; 3942 else if (lc->advertising & FW_PORT_CAP_FEC_RESERVED) 3943 lc->requested_fec = FEC_RESERVED; 3944 else 3945 lc->requested_fec = 0; 3946 } 3947 3948 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 3949 if (rc != 0) { 3950 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 3951 } else { 3952 lc->fc = lc->requested_fc; 3953 lc->fec = lc->requested_fec; 3954 } 3955 } 3956 3957 #define FW_MAC_EXACT_CHUNK 7 3958 3959 /* 3960 * Program the port's XGMAC based on parameters in ifnet. The caller also 3961 * indicates which parameters should be programmed (the rest are left alone). 3962 */ 3963 int 3964 update_mac_settings(struct ifnet *ifp, int flags) 3965 { 3966 int rc = 0; 3967 struct vi_info *vi = ifp->if_softc; 3968 struct port_info *pi = vi->pi; 3969 struct adapter *sc = pi->adapter; 3970 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 3971 3972 ASSERT_SYNCHRONIZED_OP(sc); 3973 KASSERT(flags, ("%s: not told what to update.", __func__)); 3974 3975 if (flags & XGMAC_MTU) 3976 mtu = ifp->if_mtu; 3977 3978 if (flags & XGMAC_PROMISC) 3979 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 3980 3981 if (flags & XGMAC_ALLMULTI) 3982 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 3983 3984 if (flags & XGMAC_VLANEX) 3985 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 3986 3987 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 3988 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 3989 allmulti, 1, vlanex, false); 3990 if (rc) { 3991 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 3992 rc); 3993 return (rc); 3994 } 3995 } 3996 3997 if (flags & XGMAC_UCADDR) { 3998 uint8_t ucaddr[ETHER_ADDR_LEN]; 3999 4000 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4001 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4002 ucaddr, true, true); 4003 if (rc < 0) { 4004 rc = -rc; 4005 if_printf(ifp, "change_mac failed: %d\n", rc); 4006 return (rc); 4007 } else { 4008 vi->xact_addr_filt = rc; 4009 rc = 0; 4010 } 4011 } 4012 4013 if (flags & XGMAC_MCADDRS) { 4014 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4015 int del = 1; 4016 uint64_t hash = 0; 4017 struct ifmultiaddr *ifma; 4018 int i = 0, j; 4019 4020 if_maddr_rlock(ifp); 4021 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4022 if (ifma->ifma_addr->sa_family != AF_LINK) 4023 continue; 4024 mcaddr[i] = 4025 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4026 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4027 i++; 4028 4029 if (i == FW_MAC_EXACT_CHUNK) { 4030 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4031 del, i, mcaddr, NULL, &hash, 0); 4032 if (rc < 0) { 4033 rc = -rc; 4034 for (j = 0; j < i; j++) { 4035 if_printf(ifp, 4036 "failed to add mc address" 4037 " %02x:%02x:%02x:" 4038 "%02x:%02x:%02x rc=%d\n", 4039 mcaddr[j][0], mcaddr[j][1], 4040 mcaddr[j][2], mcaddr[j][3], 4041 mcaddr[j][4], mcaddr[j][5], 4042 rc); 4043 } 4044 goto mcfail; 4045 } 4046 del = 0; 4047 i = 0; 4048 } 4049 } 4050 if (i > 0) { 4051 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4052 mcaddr, NULL, &hash, 0); 4053 if (rc < 0) { 4054 rc = -rc; 4055 for (j = 0; j < i; j++) { 4056 if_printf(ifp, 4057 "failed to add mc address" 4058 " %02x:%02x:%02x:" 4059 "%02x:%02x:%02x rc=%d\n", 4060 mcaddr[j][0], mcaddr[j][1], 4061 mcaddr[j][2], mcaddr[j][3], 4062 mcaddr[j][4], mcaddr[j][5], 4063 rc); 4064 } 4065 goto mcfail; 4066 } 4067 } 4068 4069 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4070 if (rc != 0) 4071 if_printf(ifp, "failed to set mc address hash: %d", rc); 4072 mcfail: 4073 if_maddr_runlock(ifp); 4074 } 4075 4076 return (rc); 4077 } 4078 4079 /* 4080 * {begin|end}_synchronized_op must be called from the same thread. 4081 */ 4082 int 4083 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4084 char *wmesg) 4085 { 4086 int rc, pri; 4087 4088 #ifdef WITNESS 4089 /* the caller thinks it's ok to sleep, but is it really? */ 4090 if (flags & SLEEP_OK) 4091 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4092 "begin_synchronized_op"); 4093 #endif 4094 4095 if (INTR_OK) 4096 pri = PCATCH; 4097 else 4098 pri = 0; 4099 4100 ADAPTER_LOCK(sc); 4101 for (;;) { 4102 4103 if (vi && IS_DOOMED(vi)) { 4104 rc = ENXIO; 4105 goto done; 4106 } 4107 4108 if (!IS_BUSY(sc)) { 4109 rc = 0; 4110 break; 4111 } 4112 4113 if (!(flags & SLEEP_OK)) { 4114 rc = EBUSY; 4115 goto done; 4116 } 4117 4118 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4119 rc = EINTR; 4120 goto done; 4121 } 4122 } 4123 4124 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4125 SET_BUSY(sc); 4126 #ifdef INVARIANTS 4127 sc->last_op = wmesg; 4128 sc->last_op_thr = curthread; 4129 sc->last_op_flags = flags; 4130 #endif 4131 4132 done: 4133 if (!(flags & HOLD_LOCK) || rc) 4134 ADAPTER_UNLOCK(sc); 4135 4136 return (rc); 4137 } 4138 4139 /* 4140 * Tell if_ioctl and if_init that the VI is going away. This is 4141 * special variant of begin_synchronized_op and must be paired with a 4142 * call to end_synchronized_op. 4143 */ 4144 void 4145 doom_vi(struct adapter *sc, struct vi_info *vi) 4146 { 4147 4148 ADAPTER_LOCK(sc); 4149 SET_DOOMED(vi); 4150 wakeup(&sc->flags); 4151 while (IS_BUSY(sc)) 4152 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4153 SET_BUSY(sc); 4154 #ifdef INVARIANTS 4155 sc->last_op = "t4detach"; 4156 sc->last_op_thr = curthread; 4157 sc->last_op_flags = 0; 4158 #endif 4159 ADAPTER_UNLOCK(sc); 4160 } 4161 4162 /* 4163 * {begin|end}_synchronized_op must be called from the same thread. 4164 */ 4165 void 4166 end_synchronized_op(struct adapter *sc, int flags) 4167 { 4168 4169 if (flags & LOCK_HELD) 4170 ADAPTER_LOCK_ASSERT_OWNED(sc); 4171 else 4172 ADAPTER_LOCK(sc); 4173 4174 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 4175 CLR_BUSY(sc); 4176 wakeup(&sc->flags); 4177 ADAPTER_UNLOCK(sc); 4178 } 4179 4180 static int 4181 cxgbe_init_synchronized(struct vi_info *vi) 4182 { 4183 struct port_info *pi = vi->pi; 4184 struct adapter *sc = pi->adapter; 4185 struct ifnet *ifp = vi->ifp; 4186 int rc = 0, i; 4187 struct sge_txq *txq; 4188 4189 ASSERT_SYNCHRONIZED_OP(sc); 4190 4191 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4192 return (0); /* already running */ 4193 4194 if (!(sc->flags & FULL_INIT_DONE) && 4195 ((rc = adapter_full_init(sc)) != 0)) 4196 return (rc); /* error message displayed already */ 4197 4198 if (!(vi->flags & VI_INIT_DONE) && 4199 ((rc = vi_full_init(vi)) != 0)) 4200 return (rc); /* error message displayed already */ 4201 4202 rc = update_mac_settings(ifp, XGMAC_ALL); 4203 if (rc) 4204 goto done; /* error message displayed already */ 4205 4206 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 4207 if (rc != 0) { 4208 if_printf(ifp, "enable_vi failed: %d\n", rc); 4209 goto done; 4210 } 4211 4212 /* 4213 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 4214 * if this changes. 4215 */ 4216 4217 for_each_txq(vi, i, txq) { 4218 TXQ_LOCK(txq); 4219 txq->eq.flags |= EQ_ENABLED; 4220 TXQ_UNLOCK(txq); 4221 } 4222 4223 /* 4224 * The first iq of the first port to come up is used for tracing. 4225 */ 4226 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 4227 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 4228 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4229 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4230 V_QUEUENUMBER(sc->traceq)); 4231 pi->flags |= HAS_TRACEQ; 4232 } 4233 4234 /* all ok */ 4235 PORT_LOCK(pi); 4236 if (pi->up_vis++ == 0) { 4237 t4_update_port_info(pi); 4238 build_medialist(pi, &pi->media); 4239 init_l1cfg(pi); 4240 } 4241 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4242 4243 if (pi->nvi > 1 || sc->flags & IS_VF) 4244 callout_reset(&vi->tick, hz, vi_tick, vi); 4245 else 4246 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4247 PORT_UNLOCK(pi); 4248 done: 4249 if (rc != 0) 4250 cxgbe_uninit_synchronized(vi); 4251 4252 return (rc); 4253 } 4254 4255 /* 4256 * Idempotent. 4257 */ 4258 static int 4259 cxgbe_uninit_synchronized(struct vi_info *vi) 4260 { 4261 struct port_info *pi = vi->pi; 4262 struct adapter *sc = pi->adapter; 4263 struct ifnet *ifp = vi->ifp; 4264 int rc, i; 4265 struct sge_txq *txq; 4266 4267 ASSERT_SYNCHRONIZED_OP(sc); 4268 4269 if (!(vi->flags & VI_INIT_DONE)) { 4270 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING), 4271 ("uninited VI is running")); 4272 return (0); 4273 } 4274 4275 /* 4276 * Disable the VI so that all its data in either direction is discarded 4277 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4278 * tick) intact as the TP can deliver negative advice or data that it's 4279 * holding in its RAM (for an offloaded connection) even after the VI is 4280 * disabled. 4281 */ 4282 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4283 if (rc) { 4284 if_printf(ifp, "disable_vi failed: %d\n", rc); 4285 return (rc); 4286 } 4287 4288 for_each_txq(vi, i, txq) { 4289 TXQ_LOCK(txq); 4290 txq->eq.flags &= ~EQ_ENABLED; 4291 TXQ_UNLOCK(txq); 4292 } 4293 4294 PORT_LOCK(pi); 4295 if (pi->nvi > 1 || sc->flags & IS_VF) 4296 callout_stop(&vi->tick); 4297 else 4298 callout_stop(&pi->tick); 4299 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4300 PORT_UNLOCK(pi); 4301 return (0); 4302 } 4303 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4304 pi->up_vis--; 4305 if (pi->up_vis > 0) { 4306 PORT_UNLOCK(pi); 4307 return (0); 4308 } 4309 PORT_UNLOCK(pi); 4310 4311 pi->link_cfg.link_ok = 0; 4312 pi->link_cfg.speed = 0; 4313 pi->link_cfg.link_down_rc = 255; 4314 t4_os_link_changed(pi); 4315 pi->old_link_cfg = pi->link_cfg; 4316 4317 return (0); 4318 } 4319 4320 /* 4321 * It is ok for this function to fail midway and return right away. t4_detach 4322 * will walk the entire sc->irq list and clean up whatever is valid. 4323 */ 4324 int 4325 t4_setup_intr_handlers(struct adapter *sc) 4326 { 4327 int rc, rid, p, q, v; 4328 char s[8]; 4329 struct irq *irq; 4330 struct port_info *pi; 4331 struct vi_info *vi; 4332 struct sge *sge = &sc->sge; 4333 struct sge_rxq *rxq; 4334 #ifdef TCP_OFFLOAD 4335 struct sge_ofld_rxq *ofld_rxq; 4336 #endif 4337 #ifdef DEV_NETMAP 4338 struct sge_nm_rxq *nm_rxq; 4339 #endif 4340 #ifdef RSS 4341 int nbuckets = rss_getnumbuckets(); 4342 #endif 4343 4344 /* 4345 * Setup interrupts. 4346 */ 4347 irq = &sc->irq[0]; 4348 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4349 if (sc->intr_count == 1) 4350 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4351 4352 /* Multiple interrupts. */ 4353 if (sc->flags & IS_VF) 4354 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4355 ("%s: too few intr.", __func__)); 4356 else 4357 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4358 ("%s: too few intr.", __func__)); 4359 4360 /* The first one is always error intr on PFs */ 4361 if (!(sc->flags & IS_VF)) { 4362 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4363 if (rc != 0) 4364 return (rc); 4365 irq++; 4366 rid++; 4367 } 4368 4369 /* The second one is always the firmware event queue (first on VFs) */ 4370 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4371 if (rc != 0) 4372 return (rc); 4373 irq++; 4374 rid++; 4375 4376 for_each_port(sc, p) { 4377 pi = sc->port[p]; 4378 for_each_vi(pi, v, vi) { 4379 vi->first_intr = rid - 1; 4380 4381 if (vi->nnmrxq > 0) { 4382 int n = max(vi->nrxq, vi->nnmrxq); 4383 4384 MPASS(vi->flags & INTR_RXQ); 4385 4386 rxq = &sge->rxq[vi->first_rxq]; 4387 #ifdef DEV_NETMAP 4388 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4389 #endif 4390 for (q = 0; q < n; q++) { 4391 snprintf(s, sizeof(s), "%x%c%x", p, 4392 'a' + v, q); 4393 if (q < vi->nrxq) 4394 irq->rxq = rxq++; 4395 #ifdef DEV_NETMAP 4396 if (q < vi->nnmrxq) 4397 irq->nm_rxq = nm_rxq++; 4398 #endif 4399 rc = t4_alloc_irq(sc, irq, rid, 4400 t4_vi_intr, irq, s); 4401 if (rc != 0) 4402 return (rc); 4403 irq++; 4404 rid++; 4405 vi->nintr++; 4406 } 4407 } else if (vi->flags & INTR_RXQ) { 4408 for_each_rxq(vi, q, rxq) { 4409 snprintf(s, sizeof(s), "%x%c%x", p, 4410 'a' + v, q); 4411 rc = t4_alloc_irq(sc, irq, rid, 4412 t4_intr, rxq, s); 4413 if (rc != 0) 4414 return (rc); 4415 #ifdef RSS 4416 bus_bind_intr(sc->dev, irq->res, 4417 rss_getcpu(q % nbuckets)); 4418 #endif 4419 irq++; 4420 rid++; 4421 vi->nintr++; 4422 } 4423 } 4424 #ifdef TCP_OFFLOAD 4425 if (vi->flags & INTR_OFLD_RXQ) { 4426 for_each_ofld_rxq(vi, q, ofld_rxq) { 4427 snprintf(s, sizeof(s), "%x%c%x", p, 4428 'A' + v, q); 4429 rc = t4_alloc_irq(sc, irq, rid, 4430 t4_intr, ofld_rxq, s); 4431 if (rc != 0) 4432 return (rc); 4433 irq++; 4434 rid++; 4435 vi->nintr++; 4436 } 4437 } 4438 #endif 4439 } 4440 } 4441 MPASS(irq == &sc->irq[sc->intr_count]); 4442 4443 return (0); 4444 } 4445 4446 int 4447 adapter_full_init(struct adapter *sc) 4448 { 4449 int rc, i; 4450 #ifdef RSS 4451 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4452 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4453 #endif 4454 4455 ASSERT_SYNCHRONIZED_OP(sc); 4456 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4457 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 4458 ("%s: FULL_INIT_DONE already", __func__)); 4459 4460 /* 4461 * queues that belong to the adapter (not any particular port). 4462 */ 4463 rc = t4_setup_adapter_queues(sc); 4464 if (rc != 0) 4465 goto done; 4466 4467 for (i = 0; i < nitems(sc->tq); i++) { 4468 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 4469 taskqueue_thread_enqueue, &sc->tq[i]); 4470 if (sc->tq[i] == NULL) { 4471 device_printf(sc->dev, 4472 "failed to allocate task queue %d\n", i); 4473 rc = ENOMEM; 4474 goto done; 4475 } 4476 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 4477 device_get_nameunit(sc->dev), i); 4478 } 4479 #ifdef RSS 4480 MPASS(RSS_KEYSIZE == 40); 4481 rss_getkey((void *)&raw_rss_key[0]); 4482 for (i = 0; i < nitems(rss_key); i++) { 4483 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 4484 } 4485 t4_write_rss_key(sc, &rss_key[0], -1, 1); 4486 #endif 4487 4488 if (!(sc->flags & IS_VF)) 4489 t4_intr_enable(sc); 4490 sc->flags |= FULL_INIT_DONE; 4491 done: 4492 if (rc != 0) 4493 adapter_full_uninit(sc); 4494 4495 return (rc); 4496 } 4497 4498 int 4499 adapter_full_uninit(struct adapter *sc) 4500 { 4501 int i; 4502 4503 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4504 4505 t4_teardown_adapter_queues(sc); 4506 4507 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 4508 taskqueue_free(sc->tq[i]); 4509 sc->tq[i] = NULL; 4510 } 4511 4512 sc->flags &= ~FULL_INIT_DONE; 4513 4514 return (0); 4515 } 4516 4517 #ifdef RSS 4518 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 4519 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 4520 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 4521 RSS_HASHTYPE_RSS_UDP_IPV6) 4522 4523 /* Translates kernel hash types to hardware. */ 4524 static int 4525 hashconfig_to_hashen(int hashconfig) 4526 { 4527 int hashen = 0; 4528 4529 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 4530 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 4531 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 4532 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 4533 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 4534 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4535 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4536 } 4537 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 4538 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4539 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4540 } 4541 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 4542 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4543 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 4544 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4545 4546 return (hashen); 4547 } 4548 4549 /* Translates hardware hash types to kernel. */ 4550 static int 4551 hashen_to_hashconfig(int hashen) 4552 { 4553 int hashconfig = 0; 4554 4555 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 4556 /* 4557 * If UDP hashing was enabled it must have been enabled for 4558 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 4559 * enabling any 4-tuple hash is nonsense configuration. 4560 */ 4561 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4562 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 4563 4564 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4565 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 4566 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4567 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 4568 } 4569 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4570 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 4571 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4572 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 4573 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 4574 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 4575 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 4576 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 4577 4578 return (hashconfig); 4579 } 4580 #endif 4581 4582 int 4583 vi_full_init(struct vi_info *vi) 4584 { 4585 struct adapter *sc = vi->pi->adapter; 4586 struct ifnet *ifp = vi->ifp; 4587 uint16_t *rss; 4588 struct sge_rxq *rxq; 4589 int rc, i, j, hashen; 4590 #ifdef RSS 4591 int nbuckets = rss_getnumbuckets(); 4592 int hashconfig = rss_gethashconfig(); 4593 int extra; 4594 #endif 4595 4596 ASSERT_SYNCHRONIZED_OP(sc); 4597 KASSERT((vi->flags & VI_INIT_DONE) == 0, 4598 ("%s: VI_INIT_DONE already", __func__)); 4599 4600 sysctl_ctx_init(&vi->ctx); 4601 vi->flags |= VI_SYSCTL_CTX; 4602 4603 /* 4604 * Allocate tx/rx/fl queues for this VI. 4605 */ 4606 rc = t4_setup_vi_queues(vi); 4607 if (rc != 0) 4608 goto done; /* error message displayed already */ 4609 4610 /* 4611 * Setup RSS for this VI. Save a copy of the RSS table for later use. 4612 */ 4613 if (vi->nrxq > vi->rss_size) { 4614 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 4615 "some queues will never receive traffic.\n", vi->nrxq, 4616 vi->rss_size); 4617 } else if (vi->rss_size % vi->nrxq) { 4618 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 4619 "expect uneven traffic distribution.\n", vi->nrxq, 4620 vi->rss_size); 4621 } 4622 #ifdef RSS 4623 if (vi->nrxq != nbuckets) { 4624 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 4625 "performance will be impacted.\n", vi->nrxq, nbuckets); 4626 } 4627 #endif 4628 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 4629 for (i = 0; i < vi->rss_size;) { 4630 #ifdef RSS 4631 j = rss_get_indirection_to_bucket(i); 4632 j %= vi->nrxq; 4633 rxq = &sc->sge.rxq[vi->first_rxq + j]; 4634 rss[i++] = rxq->iq.abs_id; 4635 #else 4636 for_each_rxq(vi, j, rxq) { 4637 rss[i++] = rxq->iq.abs_id; 4638 if (i == vi->rss_size) 4639 break; 4640 } 4641 #endif 4642 } 4643 4644 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 4645 vi->rss_size); 4646 if (rc != 0) { 4647 if_printf(ifp, "rss_config failed: %d\n", rc); 4648 goto done; 4649 } 4650 4651 #ifdef RSS 4652 hashen = hashconfig_to_hashen(hashconfig); 4653 4654 /* 4655 * We may have had to enable some hashes even though the global config 4656 * wants them disabled. This is a potential problem that must be 4657 * reported to the user. 4658 */ 4659 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 4660 4661 /* 4662 * If we consider only the supported hash types, then the enabled hashes 4663 * are a superset of the requested hashes. In other words, there cannot 4664 * be any supported hash that was requested but not enabled, but there 4665 * can be hashes that were not requested but had to be enabled. 4666 */ 4667 extra &= SUPPORTED_RSS_HASHTYPES; 4668 MPASS((extra & hashconfig) == 0); 4669 4670 if (extra) { 4671 if_printf(ifp, 4672 "global RSS config (0x%x) cannot be accommodated.\n", 4673 hashconfig); 4674 } 4675 if (extra & RSS_HASHTYPE_RSS_IPV4) 4676 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 4677 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 4678 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 4679 if (extra & RSS_HASHTYPE_RSS_IPV6) 4680 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 4681 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 4682 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 4683 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 4684 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 4685 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 4686 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 4687 #else 4688 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 4689 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 4690 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4691 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 4692 #endif 4693 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0); 4694 if (rc != 0) { 4695 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 4696 goto done; 4697 } 4698 4699 vi->rss = rss; 4700 vi->flags |= VI_INIT_DONE; 4701 done: 4702 if (rc != 0) 4703 vi_full_uninit(vi); 4704 4705 return (rc); 4706 } 4707 4708 /* 4709 * Idempotent. 4710 */ 4711 int 4712 vi_full_uninit(struct vi_info *vi) 4713 { 4714 struct port_info *pi = vi->pi; 4715 struct adapter *sc = pi->adapter; 4716 int i; 4717 struct sge_rxq *rxq; 4718 struct sge_txq *txq; 4719 #ifdef TCP_OFFLOAD 4720 struct sge_ofld_rxq *ofld_rxq; 4721 struct sge_wrq *ofld_txq; 4722 #endif 4723 4724 if (vi->flags & VI_INIT_DONE) { 4725 4726 /* Need to quiesce queues. */ 4727 4728 /* XXX: Only for the first VI? */ 4729 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 4730 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 4731 4732 for_each_txq(vi, i, txq) { 4733 quiesce_txq(sc, txq); 4734 } 4735 4736 #ifdef TCP_OFFLOAD 4737 for_each_ofld_txq(vi, i, ofld_txq) { 4738 quiesce_wrq(sc, ofld_txq); 4739 } 4740 #endif 4741 4742 for_each_rxq(vi, i, rxq) { 4743 quiesce_iq(sc, &rxq->iq); 4744 quiesce_fl(sc, &rxq->fl); 4745 } 4746 4747 #ifdef TCP_OFFLOAD 4748 for_each_ofld_rxq(vi, i, ofld_rxq) { 4749 quiesce_iq(sc, &ofld_rxq->iq); 4750 quiesce_fl(sc, &ofld_rxq->fl); 4751 } 4752 #endif 4753 free(vi->rss, M_CXGBE); 4754 free(vi->nm_rss, M_CXGBE); 4755 } 4756 4757 t4_teardown_vi_queues(vi); 4758 vi->flags &= ~VI_INIT_DONE; 4759 4760 return (0); 4761 } 4762 4763 static void 4764 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 4765 { 4766 struct sge_eq *eq = &txq->eq; 4767 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4768 4769 (void) sc; /* unused */ 4770 4771 #ifdef INVARIANTS 4772 TXQ_LOCK(txq); 4773 MPASS((eq->flags & EQ_ENABLED) == 0); 4774 TXQ_UNLOCK(txq); 4775 #endif 4776 4777 /* Wait for the mp_ring to empty. */ 4778 while (!mp_ring_is_idle(txq->r)) { 4779 mp_ring_check_drainage(txq->r, 0); 4780 pause("rquiesce", 1); 4781 } 4782 4783 /* Then wait for the hardware to finish. */ 4784 while (spg->cidx != htobe16(eq->pidx)) 4785 pause("equiesce", 1); 4786 4787 /* Finally, wait for the driver to reclaim all descriptors. */ 4788 while (eq->cidx != eq->pidx) 4789 pause("dquiesce", 1); 4790 } 4791 4792 static void 4793 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 4794 { 4795 4796 /* XXXTX */ 4797 } 4798 4799 static void 4800 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 4801 { 4802 (void) sc; /* unused */ 4803 4804 /* Synchronize with the interrupt handler */ 4805 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 4806 pause("iqfree", 1); 4807 } 4808 4809 static void 4810 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 4811 { 4812 mtx_lock(&sc->sfl_lock); 4813 FL_LOCK(fl); 4814 fl->flags |= FL_DOOMED; 4815 FL_UNLOCK(fl); 4816 callout_stop(&sc->sfl_callout); 4817 mtx_unlock(&sc->sfl_lock); 4818 4819 KASSERT((fl->flags & FL_STARVING) == 0, 4820 ("%s: still starving", __func__)); 4821 } 4822 4823 static int 4824 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 4825 driver_intr_t *handler, void *arg, char *name) 4826 { 4827 int rc; 4828 4829 irq->rid = rid; 4830 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 4831 RF_SHAREABLE | RF_ACTIVE); 4832 if (irq->res == NULL) { 4833 device_printf(sc->dev, 4834 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 4835 return (ENOMEM); 4836 } 4837 4838 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 4839 NULL, handler, arg, &irq->tag); 4840 if (rc != 0) { 4841 device_printf(sc->dev, 4842 "failed to setup interrupt for rid %d, name %s: %d\n", 4843 rid, name, rc); 4844 } else if (name) 4845 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 4846 4847 return (rc); 4848 } 4849 4850 static int 4851 t4_free_irq(struct adapter *sc, struct irq *irq) 4852 { 4853 if (irq->tag) 4854 bus_teardown_intr(sc->dev, irq->res, irq->tag); 4855 if (irq->res) 4856 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 4857 4858 bzero(irq, sizeof(*irq)); 4859 4860 return (0); 4861 } 4862 4863 static void 4864 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 4865 { 4866 4867 regs->version = chip_id(sc) | chip_rev(sc) << 10; 4868 t4_get_regs(sc, buf, regs->len); 4869 } 4870 4871 #define A_PL_INDIR_CMD 0x1f8 4872 4873 #define S_PL_AUTOINC 31 4874 #define M_PL_AUTOINC 0x1U 4875 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 4876 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 4877 4878 #define S_PL_VFID 20 4879 #define M_PL_VFID 0xffU 4880 #define V_PL_VFID(x) ((x) << S_PL_VFID) 4881 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 4882 4883 #define S_PL_ADDR 0 4884 #define M_PL_ADDR 0xfffffU 4885 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 4886 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 4887 4888 #define A_PL_INDIR_DATA 0x1fc 4889 4890 static uint64_t 4891 read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 4892 { 4893 u32 stats[2]; 4894 4895 mtx_assert(&sc->reg_lock, MA_OWNED); 4896 if (sc->flags & IS_VF) { 4897 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 4898 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 4899 } else { 4900 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4901 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4902 V_PL_ADDR(VF_MPS_REG(reg))); 4903 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 4904 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 4905 } 4906 return (((uint64_t)stats[1]) << 32 | stats[0]); 4907 } 4908 4909 static void 4910 t4_get_vi_stats(struct adapter *sc, unsigned int viid, 4911 struct fw_vi_stats_vf *stats) 4912 { 4913 4914 #define GET_STAT(name) \ 4915 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 4916 4917 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 4918 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 4919 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 4920 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 4921 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 4922 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 4923 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 4924 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 4925 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 4926 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 4927 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 4928 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 4929 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 4930 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 4931 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 4932 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 4933 4934 #undef GET_STAT 4935 } 4936 4937 static void 4938 t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 4939 { 4940 int reg; 4941 4942 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4943 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4944 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 4945 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 4946 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 4947 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 4948 } 4949 4950 static void 4951 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 4952 { 4953 struct timeval tv; 4954 const struct timeval interval = {0, 250000}; /* 250ms */ 4955 4956 if (!(vi->flags & VI_INIT_DONE)) 4957 return; 4958 4959 getmicrotime(&tv); 4960 timevalsub(&tv, &interval); 4961 if (timevalcmp(&tv, &vi->last_refreshed, <)) 4962 return; 4963 4964 mtx_lock(&sc->reg_lock); 4965 t4_get_vi_stats(sc, vi->viid, &vi->stats); 4966 getmicrotime(&vi->last_refreshed); 4967 mtx_unlock(&sc->reg_lock); 4968 } 4969 4970 static void 4971 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 4972 { 4973 u_int i, v, tnl_cong_drops, bg_map; 4974 struct timeval tv; 4975 const struct timeval interval = {0, 250000}; /* 250ms */ 4976 4977 getmicrotime(&tv); 4978 timevalsub(&tv, &interval); 4979 if (timevalcmp(&tv, &pi->last_refreshed, <)) 4980 return; 4981 4982 tnl_cong_drops = 0; 4983 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 4984 bg_map = pi->mps_bg_map; 4985 while (bg_map) { 4986 i = ffs(bg_map) - 1; 4987 mtx_lock(&sc->reg_lock); 4988 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 4989 A_TP_MIB_TNL_CNG_DROP_0 + i); 4990 mtx_unlock(&sc->reg_lock); 4991 tnl_cong_drops += v; 4992 bg_map &= ~(1 << i); 4993 } 4994 pi->tnl_cong_drops = tnl_cong_drops; 4995 getmicrotime(&pi->last_refreshed); 4996 } 4997 4998 static void 4999 cxgbe_tick(void *arg) 5000 { 5001 struct port_info *pi = arg; 5002 struct adapter *sc = pi->adapter; 5003 5004 PORT_LOCK_ASSERT_OWNED(pi); 5005 cxgbe_refresh_stats(sc, pi); 5006 5007 callout_schedule(&pi->tick, hz); 5008 } 5009 5010 void 5011 vi_tick(void *arg) 5012 { 5013 struct vi_info *vi = arg; 5014 struct adapter *sc = vi->pi->adapter; 5015 5016 vi_refresh_stats(sc, vi); 5017 5018 callout_schedule(&vi->tick, hz); 5019 } 5020 5021 static void 5022 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 5023 { 5024 struct ifnet *vlan; 5025 5026 if (arg != ifp || ifp->if_type != IFT_ETHER) 5027 return; 5028 5029 vlan = VLAN_DEVAT(ifp, vid); 5030 VLAN_SETCOOKIE(vlan, ifp); 5031 } 5032 5033 /* 5034 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5035 */ 5036 static char *caps_decoder[] = { 5037 "\20\001IPMI\002NCSI", /* 0: NBM */ 5038 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5039 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5040 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5041 "\006HASHFILTER\007ETHOFLD", 5042 "\20\001TOE", /* 4: TOE */ 5043 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5044 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5045 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5046 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5047 "\007T10DIF" 5048 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5049 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5050 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5051 "\004PO_INITIATOR\005PO_TARGET", 5052 }; 5053 5054 void 5055 t4_sysctls(struct adapter *sc) 5056 { 5057 struct sysctl_ctx_list *ctx; 5058 struct sysctl_oid *oid; 5059 struct sysctl_oid_list *children, *c0; 5060 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5061 5062 ctx = device_get_sysctl_ctx(sc->dev); 5063 5064 /* 5065 * dev.t4nex.X. 5066 */ 5067 oid = device_get_sysctl_tree(sc->dev); 5068 c0 = children = SYSCTL_CHILDREN(oid); 5069 5070 sc->sc_do_rxcopy = 1; 5071 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5072 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5073 5074 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5075 sc->params.nports, "# of ports"); 5076 5077 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5078 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 5079 sysctl_bitfield, "A", "available doorbells"); 5080 5081 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5082 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5083 5084 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5085 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5086 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5087 "interrupt holdoff timer values (us)"); 5088 5089 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5090 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5091 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5092 "interrupt holdoff packet counter values"); 5093 5094 t4_sge_sysctls(sc, ctx, children); 5095 5096 sc->lro_timeout = 100; 5097 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5098 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5099 5100 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5101 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5102 5103 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5104 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5105 5106 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5107 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5108 5109 if (sc->flags & IS_VF) 5110 return; 5111 5112 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5113 NULL, chip_rev(sc), "chip hardware revision"); 5114 5115 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5116 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5117 5118 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5119 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5120 5121 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5122 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5123 5124 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5125 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5126 5127 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5128 sc->er_version, 0, "expansion ROM version"); 5129 5130 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5131 sc->bs_version, 0, "bootstrap firmware version"); 5132 5133 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5134 NULL, sc->params.scfg_vers, "serial config version"); 5135 5136 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5137 NULL, sc->params.vpd_vers, "VPD version"); 5138 5139 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5140 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5141 5142 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5143 sc->cfcsum, "config file checksum"); 5144 5145 #define SYSCTL_CAP(name, n, text) \ 5146 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5147 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \ 5148 sysctl_bitfield, "A", "available " text " capabilities") 5149 5150 SYSCTL_CAP(nbmcaps, 0, "NBM"); 5151 SYSCTL_CAP(linkcaps, 1, "link"); 5152 SYSCTL_CAP(switchcaps, 2, "switch"); 5153 SYSCTL_CAP(niccaps, 3, "NIC"); 5154 SYSCTL_CAP(toecaps, 4, "TCP offload"); 5155 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 5156 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 5157 SYSCTL_CAP(cryptocaps, 7, "crypto"); 5158 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 5159 #undef SYSCTL_CAP 5160 5161 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 5162 NULL, sc->tids.nftids, "number of filters"); 5163 5164 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 5165 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 5166 "chip temperature (in Celsius)"); 5167 5168 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 5169 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 5170 5171 #ifdef SBUF_DRAIN 5172 /* 5173 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 5174 */ 5175 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 5176 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 5177 "logs and miscellaneous information"); 5178 children = SYSCTL_CHILDREN(oid); 5179 5180 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 5181 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5182 sysctl_cctrl, "A", "congestion control"); 5183 5184 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 5185 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5186 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 5187 5188 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 5189 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 5190 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 5191 5192 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 5193 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 5194 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 5195 5196 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 5197 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 5198 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 5199 5200 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 5201 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 5202 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 5203 5204 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 5205 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 5206 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 5207 5208 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 5209 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5210 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 5211 "A", "CIM logic analyzer"); 5212 5213 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 5214 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5215 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 5216 5217 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 5218 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 5219 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 5220 5221 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 5222 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 5223 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 5224 5225 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 5226 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 5227 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 5228 5229 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 5230 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 5231 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 5232 5233 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 5234 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 5235 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 5236 5237 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 5238 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 5239 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5240 5241 if (chip_id(sc) > CHELSIO_T4) { 5242 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5243 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5244 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5245 5246 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5247 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5248 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5249 } 5250 5251 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5252 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5253 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5254 5255 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5256 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5257 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5258 5259 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5260 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5261 sysctl_cpl_stats, "A", "CPL statistics"); 5262 5263 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5264 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5265 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5266 5267 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5268 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5269 sysctl_devlog, "A", "firmware's device log"); 5270 5271 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5272 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5273 sysctl_fcoe_stats, "A", "FCoE statistics"); 5274 5275 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5276 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5277 sysctl_hw_sched, "A", "hardware scheduler "); 5278 5279 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5280 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5281 sysctl_l2t, "A", "hardware L2 table"); 5282 5283 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5284 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5285 sysctl_lb_stats, "A", "loopback statistics"); 5286 5287 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5288 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5289 sysctl_meminfo, "A", "memory regions"); 5290 5291 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5292 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5293 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5294 "A", "MPS TCAM entries"); 5295 5296 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5297 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5298 sysctl_path_mtus, "A", "path MTUs"); 5299 5300 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5301 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5302 sysctl_pm_stats, "A", "PM statistics"); 5303 5304 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5305 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5306 sysctl_rdma_stats, "A", "RDMA statistics"); 5307 5308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5309 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5310 sysctl_tcp_stats, "A", "TCP statistics"); 5311 5312 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5313 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5314 sysctl_tids, "A", "TID information"); 5315 5316 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5317 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5318 sysctl_tp_err_stats, "A", "TP error statistics"); 5319 5320 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5321 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5322 "TP logic analyzer event capture mask"); 5323 5324 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5325 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5326 sysctl_tp_la, "A", "TP logic analyzer"); 5327 5328 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5329 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5330 sysctl_tx_rate, "A", "Tx rate"); 5331 5332 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5333 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5334 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5335 5336 if (chip_id(sc) >= CHELSIO_T5) { 5337 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5338 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5339 sysctl_wcwr_stats, "A", "write combined work requests"); 5340 } 5341 #endif 5342 5343 #ifdef TCP_OFFLOAD 5344 if (is_offload(sc)) { 5345 int i; 5346 char s[4]; 5347 5348 /* 5349 * dev.t4nex.X.toe. 5350 */ 5351 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5352 NULL, "TOE parameters"); 5353 children = SYSCTL_CHILDREN(oid); 5354 5355 sc->tt.cong_algorithm = -1; 5356 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 5357 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 5358 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 5359 "3 = highspeed)"); 5360 5361 sc->tt.sndbuf = 256 * 1024; 5362 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 5363 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 5364 5365 sc->tt.ddp = 0; 5366 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 5367 &sc->tt.ddp, 0, "DDP allowed"); 5368 5369 sc->tt.rx_coalesce = 1; 5370 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 5371 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 5372 5373 sc->tt.tx_align = 1; 5374 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 5375 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 5376 5377 sc->tt.tx_zcopy = 0; 5378 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 5379 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 5380 "Enable zero-copy aio_write(2)"); 5381 5382 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 5383 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 5384 "TP timer tick (us)"); 5385 5386 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 5387 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 5388 "TCP timestamp tick (us)"); 5389 5390 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 5391 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 5392 "DACK tick (us)"); 5393 5394 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 5395 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 5396 "IU", "DACK timer (us)"); 5397 5398 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 5399 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 5400 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 5401 5402 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 5403 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 5404 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 5405 5406 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 5407 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 5408 sysctl_tp_timer, "LU", "Persist timer min (us)"); 5409 5410 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 5411 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 5412 sysctl_tp_timer, "LU", "Persist timer max (us)"); 5413 5414 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 5415 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 5416 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 5417 5418 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 5419 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 5420 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 5421 5422 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 5423 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 5424 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 5425 5426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 5427 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 5428 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 5429 5430 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 5431 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 5432 sysctl_tp_shift_cnt, "IU", 5433 "Number of SYN retransmissions before abort"); 5434 5435 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 5436 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 5437 sysctl_tp_shift_cnt, "IU", 5438 "Number of retransmissions before abort"); 5439 5440 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 5441 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 5442 sysctl_tp_shift_cnt, "IU", 5443 "Number of keepalive probes before abort"); 5444 5445 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 5446 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 5447 children = SYSCTL_CHILDREN(oid); 5448 for (i = 0; i < 16; i++) { 5449 snprintf(s, sizeof(s), "%u", i); 5450 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 5451 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 5452 "IU", "TOE retransmit backoff"); 5453 } 5454 } 5455 #endif 5456 } 5457 5458 void 5459 vi_sysctls(struct vi_info *vi) 5460 { 5461 struct sysctl_ctx_list *ctx; 5462 struct sysctl_oid *oid; 5463 struct sysctl_oid_list *children; 5464 5465 ctx = device_get_sysctl_ctx(vi->dev); 5466 5467 /* 5468 * dev.v?(cxgbe|cxl).X. 5469 */ 5470 oid = device_get_sysctl_tree(vi->dev); 5471 children = SYSCTL_CHILDREN(oid); 5472 5473 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 5474 vi->viid, "VI identifer"); 5475 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 5476 &vi->nrxq, 0, "# of rx queues"); 5477 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 5478 &vi->ntxq, 0, "# of tx queues"); 5479 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 5480 &vi->first_rxq, 0, "index of first rx queue"); 5481 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 5482 &vi->first_txq, 0, "index of first tx queue"); 5483 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 5484 vi->rss_size, "size of RSS indirection table"); 5485 5486 if (IS_MAIN_VI(vi)) { 5487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 5488 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 5489 "Reserve queue 0 for non-flowid packets"); 5490 } 5491 5492 #ifdef TCP_OFFLOAD 5493 if (vi->nofldrxq != 0) { 5494 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 5495 &vi->nofldrxq, 0, 5496 "# of rx queues for offloaded TCP connections"); 5497 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 5498 &vi->nofldtxq, 0, 5499 "# of tx queues for offloaded TCP connections"); 5500 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 5501 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 5502 "index of first TOE rx queue"); 5503 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 5504 CTLFLAG_RD, &vi->first_ofld_txq, 0, 5505 "index of first TOE tx queue"); 5506 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 5507 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5508 sysctl_holdoff_tmr_idx_ofld, "I", 5509 "holdoff timer index for TOE queues"); 5510 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 5511 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5512 sysctl_holdoff_pktc_idx_ofld, "I", 5513 "holdoff packet counter index for TOE queues"); 5514 } 5515 #endif 5516 #ifdef DEV_NETMAP 5517 if (vi->nnmrxq != 0) { 5518 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 5519 &vi->nnmrxq, 0, "# of netmap rx queues"); 5520 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 5521 &vi->nnmtxq, 0, "# of netmap tx queues"); 5522 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 5523 CTLFLAG_RD, &vi->first_nm_rxq, 0, 5524 "index of first netmap rx queue"); 5525 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 5526 CTLFLAG_RD, &vi->first_nm_txq, 0, 5527 "index of first netmap tx queue"); 5528 } 5529 #endif 5530 5531 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 5532 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 5533 "holdoff timer index"); 5534 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 5535 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 5536 "holdoff packet counter index"); 5537 5538 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 5539 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 5540 "rx queue size"); 5541 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 5542 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 5543 "tx queue size"); 5544 } 5545 5546 static void 5547 cxgbe_sysctls(struct port_info *pi) 5548 { 5549 struct sysctl_ctx_list *ctx; 5550 struct sysctl_oid *oid; 5551 struct sysctl_oid_list *children, *children2; 5552 struct adapter *sc = pi->adapter; 5553 int i; 5554 char name[16]; 5555 5556 ctx = device_get_sysctl_ctx(pi->dev); 5557 5558 /* 5559 * dev.cxgbe.X. 5560 */ 5561 oid = device_get_sysctl_tree(pi->dev); 5562 children = SYSCTL_CHILDREN(oid); 5563 5564 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 5565 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 5566 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 5567 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 5568 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 5569 "PHY temperature (in Celsius)"); 5570 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 5571 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 5572 "PHY firmware version"); 5573 } 5574 5575 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 5576 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 5577 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)"); 5578 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 5579 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 5580 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 5581 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 5582 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 5583 "autonegotiation (-1 = not supported)"); 5584 5585 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 5586 port_top_speed(pi), "max speed (in Gbps)"); 5587 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 5588 pi->mps_bg_map, "MPS buffer group map"); 5589 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 5590 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 5591 5592 if (sc->flags & IS_VF) 5593 return; 5594 5595 /* 5596 * dev.(cxgbe|cxl).X.tc. 5597 */ 5598 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 5599 "Tx scheduler traffic classes (cl_rl)"); 5600 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 5601 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 5602 5603 snprintf(name, sizeof(name), "%d", i); 5604 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 5605 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 5606 "traffic class")); 5607 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD, 5608 &tc->flags, 0, "flags"); 5609 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 5610 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 5611 #ifdef SBUF_DRAIN 5612 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 5613 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 5614 sysctl_tc_params, "A", "traffic class parameters"); 5615 #endif 5616 } 5617 5618 /* 5619 * dev.cxgbe.X.stats. 5620 */ 5621 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 5622 NULL, "port statistics"); 5623 children = SYSCTL_CHILDREN(oid); 5624 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 5625 &pi->tx_parse_error, 0, 5626 "# of tx packets with invalid length or # of segments"); 5627 5628 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 5629 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 5630 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 5631 sysctl_handle_t4_reg64, "QU", desc) 5632 5633 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 5634 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 5635 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 5636 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 5637 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 5638 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 5639 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 5640 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 5641 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 5642 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 5643 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 5644 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 5645 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 5646 "# of tx frames in this range", 5647 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 5648 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 5649 "# of tx frames in this range", 5650 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 5651 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 5652 "# of tx frames in this range", 5653 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 5654 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 5655 "# of tx frames in this range", 5656 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 5657 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 5658 "# of tx frames in this range", 5659 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 5660 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 5661 "# of tx frames in this range", 5662 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 5663 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 5664 "# of tx frames in this range", 5665 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 5666 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 5667 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 5668 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 5669 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 5670 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 5671 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 5672 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 5673 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 5674 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 5675 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 5676 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 5677 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 5678 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 5679 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 5680 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 5681 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 5682 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 5683 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 5684 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 5685 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 5686 5687 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 5688 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 5689 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 5690 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 5691 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 5692 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 5693 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 5694 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 5695 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 5696 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 5697 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 5698 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 5699 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 5700 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 5701 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 5702 "# of frames received with bad FCS", 5703 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 5704 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 5705 "# of frames received with length error", 5706 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 5707 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 5708 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 5709 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 5710 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 5711 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 5712 "# of rx frames in this range", 5713 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 5714 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 5715 "# of rx frames in this range", 5716 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 5717 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 5718 "# of rx frames in this range", 5719 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 5720 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 5721 "# of rx frames in this range", 5722 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 5723 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 5724 "# of rx frames in this range", 5725 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 5726 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 5727 "# of rx frames in this range", 5728 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 5729 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 5730 "# of rx frames in this range", 5731 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 5732 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 5733 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 5734 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 5735 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 5736 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 5737 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 5738 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 5739 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 5740 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 5741 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 5742 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 5743 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 5744 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 5745 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 5746 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 5747 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 5748 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 5749 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 5750 5751 #undef SYSCTL_ADD_T4_REG64 5752 5753 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 5754 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 5755 &pi->stats.name, desc) 5756 5757 /* We get these from port_stats and they may be stale by up to 1s */ 5758 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 5759 "# drops due to buffer-group 0 overflows"); 5760 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 5761 "# drops due to buffer-group 1 overflows"); 5762 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 5763 "# drops due to buffer-group 2 overflows"); 5764 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 5765 "# drops due to buffer-group 3 overflows"); 5766 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 5767 "# of buffer-group 0 truncated packets"); 5768 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 5769 "# of buffer-group 1 truncated packets"); 5770 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 5771 "# of buffer-group 2 truncated packets"); 5772 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 5773 "# of buffer-group 3 truncated packets"); 5774 5775 #undef SYSCTL_ADD_T4_PORTSTAT 5776 } 5777 5778 static int 5779 sysctl_int_array(SYSCTL_HANDLER_ARGS) 5780 { 5781 int rc, *i, space = 0; 5782 struct sbuf sb; 5783 5784 sbuf_new_for_sysctl(&sb, NULL, 64, req); 5785 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 5786 if (space) 5787 sbuf_printf(&sb, " "); 5788 sbuf_printf(&sb, "%d", *i); 5789 space = 1; 5790 } 5791 rc = sbuf_finish(&sb); 5792 sbuf_delete(&sb); 5793 return (rc); 5794 } 5795 5796 static int 5797 sysctl_bitfield(SYSCTL_HANDLER_ARGS) 5798 { 5799 int rc; 5800 struct sbuf *sb; 5801 5802 rc = sysctl_wire_old_buffer(req, 0); 5803 if (rc != 0) 5804 return(rc); 5805 5806 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5807 if (sb == NULL) 5808 return (ENOMEM); 5809 5810 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 5811 rc = sbuf_finish(sb); 5812 sbuf_delete(sb); 5813 5814 return (rc); 5815 } 5816 5817 static int 5818 sysctl_btphy(SYSCTL_HANDLER_ARGS) 5819 { 5820 struct port_info *pi = arg1; 5821 int op = arg2; 5822 struct adapter *sc = pi->adapter; 5823 u_int v; 5824 int rc; 5825 5826 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 5827 if (rc) 5828 return (rc); 5829 /* XXX: magic numbers */ 5830 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 5831 &v); 5832 end_synchronized_op(sc, 0); 5833 if (rc) 5834 return (rc); 5835 if (op == 0) 5836 v /= 256; 5837 5838 rc = sysctl_handle_int(oidp, &v, 0, req); 5839 return (rc); 5840 } 5841 5842 static int 5843 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 5844 { 5845 struct vi_info *vi = arg1; 5846 int rc, val; 5847 5848 val = vi->rsrv_noflowq; 5849 rc = sysctl_handle_int(oidp, &val, 0, req); 5850 if (rc != 0 || req->newptr == NULL) 5851 return (rc); 5852 5853 if ((val >= 1) && (vi->ntxq > 1)) 5854 vi->rsrv_noflowq = 1; 5855 else 5856 vi->rsrv_noflowq = 0; 5857 5858 return (rc); 5859 } 5860 5861 static int 5862 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 5863 { 5864 struct vi_info *vi = arg1; 5865 struct adapter *sc = vi->pi->adapter; 5866 int idx, rc, i; 5867 struct sge_rxq *rxq; 5868 uint8_t v; 5869 5870 idx = vi->tmr_idx; 5871 5872 rc = sysctl_handle_int(oidp, &idx, 0, req); 5873 if (rc != 0 || req->newptr == NULL) 5874 return (rc); 5875 5876 if (idx < 0 || idx >= SGE_NTIMERS) 5877 return (EINVAL); 5878 5879 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5880 "t4tmr"); 5881 if (rc) 5882 return (rc); 5883 5884 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 5885 for_each_rxq(vi, i, rxq) { 5886 #ifdef atomic_store_rel_8 5887 atomic_store_rel_8(&rxq->iq.intr_params, v); 5888 #else 5889 rxq->iq.intr_params = v; 5890 #endif 5891 } 5892 vi->tmr_idx = idx; 5893 5894 end_synchronized_op(sc, LOCK_HELD); 5895 return (0); 5896 } 5897 5898 static int 5899 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 5900 { 5901 struct vi_info *vi = arg1; 5902 struct adapter *sc = vi->pi->adapter; 5903 int idx, rc; 5904 5905 idx = vi->pktc_idx; 5906 5907 rc = sysctl_handle_int(oidp, &idx, 0, req); 5908 if (rc != 0 || req->newptr == NULL) 5909 return (rc); 5910 5911 if (idx < -1 || idx >= SGE_NCOUNTERS) 5912 return (EINVAL); 5913 5914 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5915 "t4pktc"); 5916 if (rc) 5917 return (rc); 5918 5919 if (vi->flags & VI_INIT_DONE) 5920 rc = EBUSY; /* cannot be changed once the queues are created */ 5921 else 5922 vi->pktc_idx = idx; 5923 5924 end_synchronized_op(sc, LOCK_HELD); 5925 return (rc); 5926 } 5927 5928 static int 5929 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 5930 { 5931 struct vi_info *vi = arg1; 5932 struct adapter *sc = vi->pi->adapter; 5933 int qsize, rc; 5934 5935 qsize = vi->qsize_rxq; 5936 5937 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5938 if (rc != 0 || req->newptr == NULL) 5939 return (rc); 5940 5941 if (qsize < 128 || (qsize & 7)) 5942 return (EINVAL); 5943 5944 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5945 "t4rxqs"); 5946 if (rc) 5947 return (rc); 5948 5949 if (vi->flags & VI_INIT_DONE) 5950 rc = EBUSY; /* cannot be changed once the queues are created */ 5951 else 5952 vi->qsize_rxq = qsize; 5953 5954 end_synchronized_op(sc, LOCK_HELD); 5955 return (rc); 5956 } 5957 5958 static int 5959 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 5960 { 5961 struct vi_info *vi = arg1; 5962 struct adapter *sc = vi->pi->adapter; 5963 int qsize, rc; 5964 5965 qsize = vi->qsize_txq; 5966 5967 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5968 if (rc != 0 || req->newptr == NULL) 5969 return (rc); 5970 5971 if (qsize < 128 || qsize > 65536) 5972 return (EINVAL); 5973 5974 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5975 "t4txqs"); 5976 if (rc) 5977 return (rc); 5978 5979 if (vi->flags & VI_INIT_DONE) 5980 rc = EBUSY; /* cannot be changed once the queues are created */ 5981 else 5982 vi->qsize_txq = qsize; 5983 5984 end_synchronized_op(sc, LOCK_HELD); 5985 return (rc); 5986 } 5987 5988 static int 5989 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 5990 { 5991 struct port_info *pi = arg1; 5992 struct adapter *sc = pi->adapter; 5993 struct link_config *lc = &pi->link_cfg; 5994 int rc; 5995 5996 if (req->newptr == NULL) { 5997 struct sbuf *sb; 5998 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX"; 5999 6000 rc = sysctl_wire_old_buffer(req, 0); 6001 if (rc != 0) 6002 return(rc); 6003 6004 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6005 if (sb == NULL) 6006 return (ENOMEM); 6007 6008 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits); 6009 rc = sbuf_finish(sb); 6010 sbuf_delete(sb); 6011 } else { 6012 char s[2]; 6013 int n; 6014 6015 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX)); 6016 s[1] = 0; 6017 6018 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6019 if (rc != 0) 6020 return(rc); 6021 6022 if (s[1] != 0) 6023 return (EINVAL); 6024 if (s[0] < '0' || s[0] > '9') 6025 return (EINVAL); /* not a number */ 6026 n = s[0] - '0'; 6027 if (n & ~(PAUSE_TX | PAUSE_RX)) 6028 return (EINVAL); /* some other bit is set too */ 6029 6030 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6031 "t4PAUSE"); 6032 if (rc) 6033 return (rc); 6034 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) { 6035 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 6036 lc->requested_fc |= n; 6037 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6038 if (rc == 0) { 6039 lc->fc = lc->requested_fc; 6040 } 6041 } 6042 end_synchronized_op(sc, 0); 6043 } 6044 6045 return (rc); 6046 } 6047 6048 static int 6049 sysctl_fec(SYSCTL_HANDLER_ARGS) 6050 { 6051 struct port_info *pi = arg1; 6052 struct adapter *sc = pi->adapter; 6053 struct link_config *lc = &pi->link_cfg; 6054 int rc; 6055 6056 if (req->newptr == NULL) { 6057 struct sbuf *sb; 6058 static char *bits = "\20\1RS\2BASER_RS\3RESERVED"; 6059 6060 rc = sysctl_wire_old_buffer(req, 0); 6061 if (rc != 0) 6062 return(rc); 6063 6064 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6065 if (sb == NULL) 6066 return (ENOMEM); 6067 6068 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits); 6069 rc = sbuf_finish(sb); 6070 sbuf_delete(sb); 6071 } else { 6072 char s[2]; 6073 int n; 6074 6075 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC); 6076 s[1] = 0; 6077 6078 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6079 if (rc != 0) 6080 return(rc); 6081 6082 if (s[1] != 0) 6083 return (EINVAL); 6084 if (s[0] < '0' || s[0] > '9') 6085 return (EINVAL); /* not a number */ 6086 n = s[0] - '0'; 6087 if (n & ~M_FW_PORT_CAP_FEC) 6088 return (EINVAL); /* some other bit is set too */ 6089 6090 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6091 "t4fec"); 6092 if (rc) 6093 return (rc); 6094 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) { 6095 lc->requested_fec = n & 6096 G_FW_PORT_CAP_FEC(lc->supported); 6097 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6098 if (rc == 0) { 6099 lc->fec = lc->requested_fec; 6100 } 6101 } 6102 end_synchronized_op(sc, 0); 6103 } 6104 6105 return (rc); 6106 } 6107 6108 static int 6109 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 6110 { 6111 struct port_info *pi = arg1; 6112 struct adapter *sc = pi->adapter; 6113 struct link_config *lc = &pi->link_cfg; 6114 int rc, val, old; 6115 6116 if (lc->supported & FW_PORT_CAP_ANEG) 6117 val = lc->requested_aneg == AUTONEG_ENABLE ? 1 : 0; 6118 else 6119 val = -1; 6120 rc = sysctl_handle_int(oidp, &val, 0, req); 6121 if (rc != 0 || req->newptr == NULL) 6122 return (rc); 6123 if ((lc->supported & FW_PORT_CAP_ANEG) == 0) 6124 return (ENOTSUP); 6125 6126 if (val == 0) 6127 val = AUTONEG_DISABLE; 6128 else if (val == 1) 6129 val = AUTONEG_ENABLE; 6130 else 6131 return (EINVAL); 6132 if (lc->requested_aneg == val) 6133 return (0); /* no change */ 6134 6135 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6136 "t4aneg"); 6137 if (rc) 6138 return (rc); 6139 old = lc->requested_aneg; 6140 lc->requested_aneg = val; 6141 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6142 if (rc != 0) 6143 lc->requested_aneg = old; 6144 end_synchronized_op(sc, 0); 6145 return (rc); 6146 } 6147 6148 static int 6149 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 6150 { 6151 struct adapter *sc = arg1; 6152 int reg = arg2; 6153 uint64_t val; 6154 6155 val = t4_read_reg64(sc, reg); 6156 6157 return (sysctl_handle_64(oidp, &val, 0, req)); 6158 } 6159 6160 static int 6161 sysctl_temperature(SYSCTL_HANDLER_ARGS) 6162 { 6163 struct adapter *sc = arg1; 6164 int rc, t; 6165 uint32_t param, val; 6166 6167 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 6168 if (rc) 6169 return (rc); 6170 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6171 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 6172 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 6173 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6174 end_synchronized_op(sc, 0); 6175 if (rc) 6176 return (rc); 6177 6178 /* unknown is returned as 0 but we display -1 in that case */ 6179 t = val == 0 ? -1 : val; 6180 6181 rc = sysctl_handle_int(oidp, &t, 0, req); 6182 return (rc); 6183 } 6184 6185 #ifdef SBUF_DRAIN 6186 static int 6187 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 6188 { 6189 struct adapter *sc = arg1; 6190 struct sbuf *sb; 6191 int rc, i; 6192 uint16_t incr[NMTUS][NCCTRL_WIN]; 6193 static const char *dec_fac[] = { 6194 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 6195 "0.9375" 6196 }; 6197 6198 rc = sysctl_wire_old_buffer(req, 0); 6199 if (rc != 0) 6200 return (rc); 6201 6202 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6203 if (sb == NULL) 6204 return (ENOMEM); 6205 6206 t4_read_cong_tbl(sc, incr); 6207 6208 for (i = 0; i < NCCTRL_WIN; ++i) { 6209 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 6210 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 6211 incr[5][i], incr[6][i], incr[7][i]); 6212 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 6213 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 6214 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 6215 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 6216 } 6217 6218 rc = sbuf_finish(sb); 6219 sbuf_delete(sb); 6220 6221 return (rc); 6222 } 6223 6224 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 6225 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 6226 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 6227 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 6228 }; 6229 6230 static int 6231 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 6232 { 6233 struct adapter *sc = arg1; 6234 struct sbuf *sb; 6235 int rc, i, n, qid = arg2; 6236 uint32_t *buf, *p; 6237 char *qtype; 6238 u_int cim_num_obq = sc->chip_params->cim_num_obq; 6239 6240 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 6241 ("%s: bad qid %d\n", __func__, qid)); 6242 6243 if (qid < CIM_NUM_IBQ) { 6244 /* inbound queue */ 6245 qtype = "IBQ"; 6246 n = 4 * CIM_IBQ_SIZE; 6247 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6248 rc = t4_read_cim_ibq(sc, qid, buf, n); 6249 } else { 6250 /* outbound queue */ 6251 qtype = "OBQ"; 6252 qid -= CIM_NUM_IBQ; 6253 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 6254 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6255 rc = t4_read_cim_obq(sc, qid, buf, n); 6256 } 6257 6258 if (rc < 0) { 6259 rc = -rc; 6260 goto done; 6261 } 6262 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 6263 6264 rc = sysctl_wire_old_buffer(req, 0); 6265 if (rc != 0) 6266 goto done; 6267 6268 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6269 if (sb == NULL) { 6270 rc = ENOMEM; 6271 goto done; 6272 } 6273 6274 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 6275 for (i = 0, p = buf; i < n; i += 16, p += 4) 6276 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 6277 p[2], p[3]); 6278 6279 rc = sbuf_finish(sb); 6280 sbuf_delete(sb); 6281 done: 6282 free(buf, M_CXGBE); 6283 return (rc); 6284 } 6285 6286 static int 6287 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 6288 { 6289 struct adapter *sc = arg1; 6290 u_int cfg; 6291 struct sbuf *sb; 6292 uint32_t *buf, *p; 6293 int rc; 6294 6295 MPASS(chip_id(sc) <= CHELSIO_T5); 6296 6297 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6298 if (rc != 0) 6299 return (rc); 6300 6301 rc = sysctl_wire_old_buffer(req, 0); 6302 if (rc != 0) 6303 return (rc); 6304 6305 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6306 if (sb == NULL) 6307 return (ENOMEM); 6308 6309 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6310 M_ZERO | M_WAITOK); 6311 6312 rc = -t4_cim_read_la(sc, buf, NULL); 6313 if (rc != 0) 6314 goto done; 6315 6316 sbuf_printf(sb, "Status Data PC%s", 6317 cfg & F_UPDBGLACAPTPCONLY ? "" : 6318 " LS0Stat LS0Addr LS0Data"); 6319 6320 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 6321 if (cfg & F_UPDBGLACAPTPCONLY) { 6322 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 6323 p[6], p[7]); 6324 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 6325 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 6326 p[4] & 0xff, p[5] >> 8); 6327 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 6328 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6329 p[1] & 0xf, p[2] >> 4); 6330 } else { 6331 sbuf_printf(sb, 6332 "\n %02x %x%07x %x%07x %08x %08x " 6333 "%08x%08x%08x%08x", 6334 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6335 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 6336 p[6], p[7]); 6337 } 6338 } 6339 6340 rc = sbuf_finish(sb); 6341 sbuf_delete(sb); 6342 done: 6343 free(buf, M_CXGBE); 6344 return (rc); 6345 } 6346 6347 static int 6348 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 6349 { 6350 struct adapter *sc = arg1; 6351 u_int cfg; 6352 struct sbuf *sb; 6353 uint32_t *buf, *p; 6354 int rc; 6355 6356 MPASS(chip_id(sc) > CHELSIO_T5); 6357 6358 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6359 if (rc != 0) 6360 return (rc); 6361 6362 rc = sysctl_wire_old_buffer(req, 0); 6363 if (rc != 0) 6364 return (rc); 6365 6366 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6367 if (sb == NULL) 6368 return (ENOMEM); 6369 6370 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6371 M_ZERO | M_WAITOK); 6372 6373 rc = -t4_cim_read_la(sc, buf, NULL); 6374 if (rc != 0) 6375 goto done; 6376 6377 sbuf_printf(sb, "Status Inst Data PC%s", 6378 cfg & F_UPDBGLACAPTPCONLY ? "" : 6379 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 6380 6381 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 6382 if (cfg & F_UPDBGLACAPTPCONLY) { 6383 sbuf_printf(sb, "\n %02x %08x %08x %08x", 6384 p[3] & 0xff, p[2], p[1], p[0]); 6385 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 6386 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 6387 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 6388 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 6389 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 6390 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 6391 p[6] >> 16); 6392 } else { 6393 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 6394 "%08x %08x %08x %08x %08x %08x", 6395 (p[9] >> 16) & 0xff, 6396 p[9] & 0xffff, p[8] >> 16, 6397 p[8] & 0xffff, p[7] >> 16, 6398 p[7] & 0xffff, p[6] >> 16, 6399 p[2], p[1], p[0], p[5], p[4], p[3]); 6400 } 6401 } 6402 6403 rc = sbuf_finish(sb); 6404 sbuf_delete(sb); 6405 done: 6406 free(buf, M_CXGBE); 6407 return (rc); 6408 } 6409 6410 static int 6411 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 6412 { 6413 struct adapter *sc = arg1; 6414 u_int i; 6415 struct sbuf *sb; 6416 uint32_t *buf, *p; 6417 int rc; 6418 6419 rc = sysctl_wire_old_buffer(req, 0); 6420 if (rc != 0) 6421 return (rc); 6422 6423 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6424 if (sb == NULL) 6425 return (ENOMEM); 6426 6427 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 6428 M_ZERO | M_WAITOK); 6429 6430 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 6431 p = buf; 6432 6433 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6434 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 6435 p[1], p[0]); 6436 } 6437 6438 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 6439 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6440 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 6441 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 6442 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 6443 (p[1] >> 2) | ((p[2] & 3) << 30), 6444 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 6445 p[0] & 1); 6446 } 6447 6448 rc = sbuf_finish(sb); 6449 sbuf_delete(sb); 6450 free(buf, M_CXGBE); 6451 return (rc); 6452 } 6453 6454 static int 6455 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 6456 { 6457 struct adapter *sc = arg1; 6458 u_int i; 6459 struct sbuf *sb; 6460 uint32_t *buf, *p; 6461 int rc; 6462 6463 rc = sysctl_wire_old_buffer(req, 0); 6464 if (rc != 0) 6465 return (rc); 6466 6467 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6468 if (sb == NULL) 6469 return (ENOMEM); 6470 6471 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 6472 M_ZERO | M_WAITOK); 6473 6474 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 6475 p = buf; 6476 6477 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 6478 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6479 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 6480 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 6481 p[4], p[3], p[2], p[1], p[0]); 6482 } 6483 6484 sbuf_printf(sb, "\n\nCntl ID Data"); 6485 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6486 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 6487 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 6488 } 6489 6490 rc = sbuf_finish(sb); 6491 sbuf_delete(sb); 6492 free(buf, M_CXGBE); 6493 return (rc); 6494 } 6495 6496 static int 6497 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 6498 { 6499 struct adapter *sc = arg1; 6500 struct sbuf *sb; 6501 int rc, i; 6502 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6503 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6504 uint16_t thres[CIM_NUM_IBQ]; 6505 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 6506 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 6507 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 6508 6509 cim_num_obq = sc->chip_params->cim_num_obq; 6510 if (is_t4(sc)) { 6511 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 6512 obq_rdaddr = A_UP_OBQ_0_REALADDR; 6513 } else { 6514 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 6515 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 6516 } 6517 nq = CIM_NUM_IBQ + cim_num_obq; 6518 6519 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 6520 if (rc == 0) 6521 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 6522 if (rc != 0) 6523 return (rc); 6524 6525 t4_read_cimq_cfg(sc, base, size, thres); 6526 6527 rc = sysctl_wire_old_buffer(req, 0); 6528 if (rc != 0) 6529 return (rc); 6530 6531 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6532 if (sb == NULL) 6533 return (ENOMEM); 6534 6535 sbuf_printf(sb, 6536 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 6537 6538 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 6539 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 6540 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 6541 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6542 G_QUEREMFLITS(p[2]) * 16); 6543 for ( ; i < nq; i++, p += 4, wr += 2) 6544 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 6545 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 6546 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6547 G_QUEREMFLITS(p[2]) * 16); 6548 6549 rc = sbuf_finish(sb); 6550 sbuf_delete(sb); 6551 6552 return (rc); 6553 } 6554 6555 static int 6556 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 6557 { 6558 struct adapter *sc = arg1; 6559 struct sbuf *sb; 6560 int rc; 6561 struct tp_cpl_stats stats; 6562 6563 rc = sysctl_wire_old_buffer(req, 0); 6564 if (rc != 0) 6565 return (rc); 6566 6567 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6568 if (sb == NULL) 6569 return (ENOMEM); 6570 6571 mtx_lock(&sc->reg_lock); 6572 t4_tp_get_cpl_stats(sc, &stats, 0); 6573 mtx_unlock(&sc->reg_lock); 6574 6575 if (sc->chip_params->nchan > 2) { 6576 sbuf_printf(sb, " channel 0 channel 1" 6577 " channel 2 channel 3"); 6578 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 6579 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 6580 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 6581 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 6582 } else { 6583 sbuf_printf(sb, " channel 0 channel 1"); 6584 sbuf_printf(sb, "\nCPL requests: %10u %10u", 6585 stats.req[0], stats.req[1]); 6586 sbuf_printf(sb, "\nCPL responses: %10u %10u", 6587 stats.rsp[0], stats.rsp[1]); 6588 } 6589 6590 rc = sbuf_finish(sb); 6591 sbuf_delete(sb); 6592 6593 return (rc); 6594 } 6595 6596 static int 6597 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 6598 { 6599 struct adapter *sc = arg1; 6600 struct sbuf *sb; 6601 int rc; 6602 struct tp_usm_stats stats; 6603 6604 rc = sysctl_wire_old_buffer(req, 0); 6605 if (rc != 0) 6606 return(rc); 6607 6608 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6609 if (sb == NULL) 6610 return (ENOMEM); 6611 6612 t4_get_usm_stats(sc, &stats, 1); 6613 6614 sbuf_printf(sb, "Frames: %u\n", stats.frames); 6615 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 6616 sbuf_printf(sb, "Drops: %u", stats.drops); 6617 6618 rc = sbuf_finish(sb); 6619 sbuf_delete(sb); 6620 6621 return (rc); 6622 } 6623 6624 static const char * const devlog_level_strings[] = { 6625 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 6626 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 6627 [FW_DEVLOG_LEVEL_ERR] = "ERR", 6628 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 6629 [FW_DEVLOG_LEVEL_INFO] = "INFO", 6630 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 6631 }; 6632 6633 static const char * const devlog_facility_strings[] = { 6634 [FW_DEVLOG_FACILITY_CORE] = "CORE", 6635 [FW_DEVLOG_FACILITY_CF] = "CF", 6636 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 6637 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 6638 [FW_DEVLOG_FACILITY_RES] = "RES", 6639 [FW_DEVLOG_FACILITY_HW] = "HW", 6640 [FW_DEVLOG_FACILITY_FLR] = "FLR", 6641 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 6642 [FW_DEVLOG_FACILITY_PHY] = "PHY", 6643 [FW_DEVLOG_FACILITY_MAC] = "MAC", 6644 [FW_DEVLOG_FACILITY_PORT] = "PORT", 6645 [FW_DEVLOG_FACILITY_VI] = "VI", 6646 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 6647 [FW_DEVLOG_FACILITY_ACL] = "ACL", 6648 [FW_DEVLOG_FACILITY_TM] = "TM", 6649 [FW_DEVLOG_FACILITY_QFC] = "QFC", 6650 [FW_DEVLOG_FACILITY_DCB] = "DCB", 6651 [FW_DEVLOG_FACILITY_ETH] = "ETH", 6652 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 6653 [FW_DEVLOG_FACILITY_RI] = "RI", 6654 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 6655 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 6656 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 6657 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 6658 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 6659 }; 6660 6661 static int 6662 sysctl_devlog(SYSCTL_HANDLER_ARGS) 6663 { 6664 struct adapter *sc = arg1; 6665 struct devlog_params *dparams = &sc->params.devlog; 6666 struct fw_devlog_e *buf, *e; 6667 int i, j, rc, nentries, first = 0; 6668 struct sbuf *sb; 6669 uint64_t ftstamp = UINT64_MAX; 6670 6671 if (dparams->addr == 0) 6672 return (ENXIO); 6673 6674 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 6675 if (buf == NULL) 6676 return (ENOMEM); 6677 6678 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 6679 if (rc != 0) 6680 goto done; 6681 6682 nentries = dparams->size / sizeof(struct fw_devlog_e); 6683 for (i = 0; i < nentries; i++) { 6684 e = &buf[i]; 6685 6686 if (e->timestamp == 0) 6687 break; /* end */ 6688 6689 e->timestamp = be64toh(e->timestamp); 6690 e->seqno = be32toh(e->seqno); 6691 for (j = 0; j < 8; j++) 6692 e->params[j] = be32toh(e->params[j]); 6693 6694 if (e->timestamp < ftstamp) { 6695 ftstamp = e->timestamp; 6696 first = i; 6697 } 6698 } 6699 6700 if (buf[first].timestamp == 0) 6701 goto done; /* nothing in the log */ 6702 6703 rc = sysctl_wire_old_buffer(req, 0); 6704 if (rc != 0) 6705 goto done; 6706 6707 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6708 if (sb == NULL) { 6709 rc = ENOMEM; 6710 goto done; 6711 } 6712 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 6713 "Seq#", "Tstamp", "Level", "Facility", "Message"); 6714 6715 i = first; 6716 do { 6717 e = &buf[i]; 6718 if (e->timestamp == 0) 6719 break; /* end */ 6720 6721 sbuf_printf(sb, "%10d %15ju %8s %8s ", 6722 e->seqno, e->timestamp, 6723 (e->level < nitems(devlog_level_strings) ? 6724 devlog_level_strings[e->level] : "UNKNOWN"), 6725 (e->facility < nitems(devlog_facility_strings) ? 6726 devlog_facility_strings[e->facility] : "UNKNOWN")); 6727 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 6728 e->params[2], e->params[3], e->params[4], 6729 e->params[5], e->params[6], e->params[7]); 6730 6731 if (++i == nentries) 6732 i = 0; 6733 } while (i != first); 6734 6735 rc = sbuf_finish(sb); 6736 sbuf_delete(sb); 6737 done: 6738 free(buf, M_CXGBE); 6739 return (rc); 6740 } 6741 6742 static int 6743 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 6744 { 6745 struct adapter *sc = arg1; 6746 struct sbuf *sb; 6747 int rc; 6748 struct tp_fcoe_stats stats[MAX_NCHAN]; 6749 int i, nchan = sc->chip_params->nchan; 6750 6751 rc = sysctl_wire_old_buffer(req, 0); 6752 if (rc != 0) 6753 return (rc); 6754 6755 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6756 if (sb == NULL) 6757 return (ENOMEM); 6758 6759 for (i = 0; i < nchan; i++) 6760 t4_get_fcoe_stats(sc, i, &stats[i], 1); 6761 6762 if (nchan > 2) { 6763 sbuf_printf(sb, " channel 0 channel 1" 6764 " channel 2 channel 3"); 6765 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 6766 stats[0].octets_ddp, stats[1].octets_ddp, 6767 stats[2].octets_ddp, stats[3].octets_ddp); 6768 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 6769 stats[0].frames_ddp, stats[1].frames_ddp, 6770 stats[2].frames_ddp, stats[3].frames_ddp); 6771 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 6772 stats[0].frames_drop, stats[1].frames_drop, 6773 stats[2].frames_drop, stats[3].frames_drop); 6774 } else { 6775 sbuf_printf(sb, " channel 0 channel 1"); 6776 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 6777 stats[0].octets_ddp, stats[1].octets_ddp); 6778 sbuf_printf(sb, "\nframesDDP: %16u %16u", 6779 stats[0].frames_ddp, stats[1].frames_ddp); 6780 sbuf_printf(sb, "\nframesDrop: %16u %16u", 6781 stats[0].frames_drop, stats[1].frames_drop); 6782 } 6783 6784 rc = sbuf_finish(sb); 6785 sbuf_delete(sb); 6786 6787 return (rc); 6788 } 6789 6790 static int 6791 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 6792 { 6793 struct adapter *sc = arg1; 6794 struct sbuf *sb; 6795 int rc, i; 6796 unsigned int map, kbps, ipg, mode; 6797 unsigned int pace_tab[NTX_SCHED]; 6798 6799 rc = sysctl_wire_old_buffer(req, 0); 6800 if (rc != 0) 6801 return (rc); 6802 6803 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6804 if (sb == NULL) 6805 return (ENOMEM); 6806 6807 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 6808 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 6809 t4_read_pace_tbl(sc, pace_tab); 6810 6811 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 6812 "Class IPG (0.1 ns) Flow IPG (us)"); 6813 6814 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 6815 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 6816 sbuf_printf(sb, "\n %u %-5s %u ", i, 6817 (mode & (1 << i)) ? "flow" : "class", map & 3); 6818 if (kbps) 6819 sbuf_printf(sb, "%9u ", kbps); 6820 else 6821 sbuf_printf(sb, " disabled "); 6822 6823 if (ipg) 6824 sbuf_printf(sb, "%13u ", ipg); 6825 else 6826 sbuf_printf(sb, " disabled "); 6827 6828 if (pace_tab[i]) 6829 sbuf_printf(sb, "%10u", pace_tab[i]); 6830 else 6831 sbuf_printf(sb, " disabled"); 6832 } 6833 6834 rc = sbuf_finish(sb); 6835 sbuf_delete(sb); 6836 6837 return (rc); 6838 } 6839 6840 static int 6841 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 6842 { 6843 struct adapter *sc = arg1; 6844 struct sbuf *sb; 6845 int rc, i, j; 6846 uint64_t *p0, *p1; 6847 struct lb_port_stats s[2]; 6848 static const char *stat_name[] = { 6849 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 6850 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 6851 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 6852 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 6853 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 6854 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 6855 "BG2FramesTrunc:", "BG3FramesTrunc:" 6856 }; 6857 6858 rc = sysctl_wire_old_buffer(req, 0); 6859 if (rc != 0) 6860 return (rc); 6861 6862 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6863 if (sb == NULL) 6864 return (ENOMEM); 6865 6866 memset(s, 0, sizeof(s)); 6867 6868 for (i = 0; i < sc->chip_params->nchan; i += 2) { 6869 t4_get_lb_stats(sc, i, &s[0]); 6870 t4_get_lb_stats(sc, i + 1, &s[1]); 6871 6872 p0 = &s[0].octets; 6873 p1 = &s[1].octets; 6874 sbuf_printf(sb, "%s Loopback %u" 6875 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 6876 6877 for (j = 0; j < nitems(stat_name); j++) 6878 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 6879 *p0++, *p1++); 6880 } 6881 6882 rc = sbuf_finish(sb); 6883 sbuf_delete(sb); 6884 6885 return (rc); 6886 } 6887 6888 static int 6889 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 6890 { 6891 int rc = 0; 6892 struct port_info *pi = arg1; 6893 struct link_config *lc = &pi->link_cfg; 6894 struct sbuf *sb; 6895 6896 rc = sysctl_wire_old_buffer(req, 0); 6897 if (rc != 0) 6898 return(rc); 6899 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 6900 if (sb == NULL) 6901 return (ENOMEM); 6902 6903 if (lc->link_ok || lc->link_down_rc == 255) 6904 sbuf_printf(sb, "n/a"); 6905 else 6906 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 6907 6908 rc = sbuf_finish(sb); 6909 sbuf_delete(sb); 6910 6911 return (rc); 6912 } 6913 6914 struct mem_desc { 6915 unsigned int base; 6916 unsigned int limit; 6917 unsigned int idx; 6918 }; 6919 6920 static int 6921 mem_desc_cmp(const void *a, const void *b) 6922 { 6923 return ((const struct mem_desc *)a)->base - 6924 ((const struct mem_desc *)b)->base; 6925 } 6926 6927 static void 6928 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 6929 unsigned int to) 6930 { 6931 unsigned int size; 6932 6933 if (from == to) 6934 return; 6935 6936 size = to - from + 1; 6937 if (size == 0) 6938 return; 6939 6940 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 6941 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 6942 } 6943 6944 static int 6945 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 6946 { 6947 struct adapter *sc = arg1; 6948 struct sbuf *sb; 6949 int rc, i, n; 6950 uint32_t lo, hi, used, alloc; 6951 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 6952 static const char *region[] = { 6953 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 6954 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 6955 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 6956 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 6957 "RQUDP region:", "PBL region:", "TXPBL region:", 6958 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 6959 "On-chip queues:" 6960 }; 6961 struct mem_desc avail[4]; 6962 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 6963 struct mem_desc *md = mem; 6964 6965 rc = sysctl_wire_old_buffer(req, 0); 6966 if (rc != 0) 6967 return (rc); 6968 6969 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6970 if (sb == NULL) 6971 return (ENOMEM); 6972 6973 for (i = 0; i < nitems(mem); i++) { 6974 mem[i].limit = 0; 6975 mem[i].idx = i; 6976 } 6977 6978 /* Find and sort the populated memory ranges */ 6979 i = 0; 6980 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 6981 if (lo & F_EDRAM0_ENABLE) { 6982 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 6983 avail[i].base = G_EDRAM0_BASE(hi) << 20; 6984 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 6985 avail[i].idx = 0; 6986 i++; 6987 } 6988 if (lo & F_EDRAM1_ENABLE) { 6989 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 6990 avail[i].base = G_EDRAM1_BASE(hi) << 20; 6991 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 6992 avail[i].idx = 1; 6993 i++; 6994 } 6995 if (lo & F_EXT_MEM_ENABLE) { 6996 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 6997 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 6998 avail[i].limit = avail[i].base + 6999 (G_EXT_MEM_SIZE(hi) << 20); 7000 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 7001 i++; 7002 } 7003 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 7004 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 7005 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 7006 avail[i].limit = avail[i].base + 7007 (G_EXT_MEM1_SIZE(hi) << 20); 7008 avail[i].idx = 4; 7009 i++; 7010 } 7011 if (!i) /* no memory available */ 7012 return 0; 7013 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 7014 7015 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 7016 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 7017 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 7018 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 7019 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 7020 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 7021 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 7022 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 7023 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 7024 7025 /* the next few have explicit upper bounds */ 7026 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 7027 md->limit = md->base - 1 + 7028 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 7029 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 7030 md++; 7031 7032 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 7033 md->limit = md->base - 1 + 7034 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 7035 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 7036 md++; 7037 7038 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7039 if (chip_id(sc) <= CHELSIO_T5) 7040 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 7041 else 7042 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 7043 md->limit = 0; 7044 } else { 7045 md->base = 0; 7046 md->idx = nitems(region); /* hide it */ 7047 } 7048 md++; 7049 7050 #define ulp_region(reg) \ 7051 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 7052 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 7053 7054 ulp_region(RX_ISCSI); 7055 ulp_region(RX_TDDP); 7056 ulp_region(TX_TPT); 7057 ulp_region(RX_STAG); 7058 ulp_region(RX_RQ); 7059 ulp_region(RX_RQUDP); 7060 ulp_region(RX_PBL); 7061 ulp_region(TX_PBL); 7062 #undef ulp_region 7063 7064 md->base = 0; 7065 md->idx = nitems(region); 7066 if (!is_t4(sc)) { 7067 uint32_t size = 0; 7068 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 7069 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 7070 7071 if (is_t5(sc)) { 7072 if (sge_ctrl & F_VFIFO_ENABLE) 7073 size = G_DBVFIFO_SIZE(fifo_size); 7074 } else 7075 size = G_T6_DBVFIFO_SIZE(fifo_size); 7076 7077 if (size) { 7078 md->base = G_BASEADDR(t4_read_reg(sc, 7079 A_SGE_DBVFIFO_BADDR)); 7080 md->limit = md->base + (size << 2) - 1; 7081 } 7082 } 7083 md++; 7084 7085 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 7086 md->limit = 0; 7087 md++; 7088 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 7089 md->limit = 0; 7090 md++; 7091 7092 md->base = sc->vres.ocq.start; 7093 if (sc->vres.ocq.size) 7094 md->limit = md->base + sc->vres.ocq.size - 1; 7095 else 7096 md->idx = nitems(region); /* hide it */ 7097 md++; 7098 7099 /* add any address-space holes, there can be up to 3 */ 7100 for (n = 0; n < i - 1; n++) 7101 if (avail[n].limit < avail[n + 1].base) 7102 (md++)->base = avail[n].limit; 7103 if (avail[n].limit) 7104 (md++)->base = avail[n].limit; 7105 7106 n = md - mem; 7107 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 7108 7109 for (lo = 0; lo < i; lo++) 7110 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 7111 avail[lo].limit - 1); 7112 7113 sbuf_printf(sb, "\n"); 7114 for (i = 0; i < n; i++) { 7115 if (mem[i].idx >= nitems(region)) 7116 continue; /* skip holes */ 7117 if (!mem[i].limit) 7118 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 7119 mem_region_show(sb, region[mem[i].idx], mem[i].base, 7120 mem[i].limit); 7121 } 7122 7123 sbuf_printf(sb, "\n"); 7124 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 7125 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 7126 mem_region_show(sb, "uP RAM:", lo, hi); 7127 7128 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 7129 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 7130 mem_region_show(sb, "uP Extmem2:", lo, hi); 7131 7132 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 7133 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 7134 G_PMRXMAXPAGE(lo), 7135 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 7136 (lo & F_PMRXNUMCHN) ? 2 : 1); 7137 7138 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 7139 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 7140 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 7141 G_PMTXMAXPAGE(lo), 7142 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 7143 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 7144 sbuf_printf(sb, "%u p-structs\n", 7145 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 7146 7147 for (i = 0; i < 4; i++) { 7148 if (chip_id(sc) > CHELSIO_T5) 7149 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 7150 else 7151 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 7152 if (is_t5(sc)) { 7153 used = G_T5_USED(lo); 7154 alloc = G_T5_ALLOC(lo); 7155 } else { 7156 used = G_USED(lo); 7157 alloc = G_ALLOC(lo); 7158 } 7159 /* For T6 these are MAC buffer groups */ 7160 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 7161 i, used, alloc); 7162 } 7163 for (i = 0; i < sc->chip_params->nchan; i++) { 7164 if (chip_id(sc) > CHELSIO_T5) 7165 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 7166 else 7167 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 7168 if (is_t5(sc)) { 7169 used = G_T5_USED(lo); 7170 alloc = G_T5_ALLOC(lo); 7171 } else { 7172 used = G_USED(lo); 7173 alloc = G_ALLOC(lo); 7174 } 7175 /* For T6 these are MAC buffer groups */ 7176 sbuf_printf(sb, 7177 "\nLoopback %d using %u pages out of %u allocated", 7178 i, used, alloc); 7179 } 7180 7181 rc = sbuf_finish(sb); 7182 sbuf_delete(sb); 7183 7184 return (rc); 7185 } 7186 7187 static inline void 7188 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 7189 { 7190 *mask = x | y; 7191 y = htobe64(y); 7192 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 7193 } 7194 7195 static int 7196 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 7197 { 7198 struct adapter *sc = arg1; 7199 struct sbuf *sb; 7200 int rc, i; 7201 7202 MPASS(chip_id(sc) <= CHELSIO_T5); 7203 7204 rc = sysctl_wire_old_buffer(req, 0); 7205 if (rc != 0) 7206 return (rc); 7207 7208 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7209 if (sb == NULL) 7210 return (ENOMEM); 7211 7212 sbuf_printf(sb, 7213 "Idx Ethernet address Mask Vld Ports PF" 7214 " VF Replication P0 P1 P2 P3 ML"); 7215 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7216 uint64_t tcamx, tcamy, mask; 7217 uint32_t cls_lo, cls_hi; 7218 uint8_t addr[ETHER_ADDR_LEN]; 7219 7220 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 7221 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 7222 if (tcamx & tcamy) 7223 continue; 7224 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7225 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7226 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7227 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 7228 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 7229 addr[3], addr[4], addr[5], (uintmax_t)mask, 7230 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 7231 G_PORTMAP(cls_hi), G_PF(cls_lo), 7232 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 7233 7234 if (cls_lo & F_REPLICATE) { 7235 struct fw_ldst_cmd ldst_cmd; 7236 7237 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7238 ldst_cmd.op_to_addrspace = 7239 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7240 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7241 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7242 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7243 ldst_cmd.u.mps.rplc.fid_idx = 7244 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7245 V_FW_LDST_CMD_IDX(i)); 7246 7247 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7248 "t4mps"); 7249 if (rc) 7250 break; 7251 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7252 sizeof(ldst_cmd), &ldst_cmd); 7253 end_synchronized_op(sc, 0); 7254 7255 if (rc != 0) { 7256 sbuf_printf(sb, "%36d", rc); 7257 rc = 0; 7258 } else { 7259 sbuf_printf(sb, " %08x %08x %08x %08x", 7260 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7261 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7262 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7263 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7264 } 7265 } else 7266 sbuf_printf(sb, "%36s", ""); 7267 7268 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 7269 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 7270 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 7271 } 7272 7273 if (rc) 7274 (void) sbuf_finish(sb); 7275 else 7276 rc = sbuf_finish(sb); 7277 sbuf_delete(sb); 7278 7279 return (rc); 7280 } 7281 7282 static int 7283 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 7284 { 7285 struct adapter *sc = arg1; 7286 struct sbuf *sb; 7287 int rc, i; 7288 7289 MPASS(chip_id(sc) > CHELSIO_T5); 7290 7291 rc = sysctl_wire_old_buffer(req, 0); 7292 if (rc != 0) 7293 return (rc); 7294 7295 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7296 if (sb == NULL) 7297 return (ENOMEM); 7298 7299 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 7300 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 7301 " Replication" 7302 " P0 P1 P2 P3 ML\n"); 7303 7304 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7305 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 7306 uint16_t ivlan; 7307 uint64_t tcamx, tcamy, val, mask; 7308 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 7309 uint8_t addr[ETHER_ADDR_LEN]; 7310 7311 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 7312 if (i < 256) 7313 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 7314 else 7315 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 7316 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7317 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7318 tcamy = G_DMACH(val) << 32; 7319 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7320 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7321 lookup_type = G_DATALKPTYPE(data2); 7322 port_num = G_DATAPORTNUM(data2); 7323 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7324 /* Inner header VNI */ 7325 vniy = ((data2 & F_DATAVIDH2) << 23) | 7326 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7327 dip_hit = data2 & F_DATADIPHIT; 7328 vlan_vld = 0; 7329 } else { 7330 vniy = 0; 7331 dip_hit = 0; 7332 vlan_vld = data2 & F_DATAVIDH2; 7333 ivlan = G_VIDL(val); 7334 } 7335 7336 ctl |= V_CTLXYBITSEL(1); 7337 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7338 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7339 tcamx = G_DMACH(val) << 32; 7340 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7341 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7342 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7343 /* Inner header VNI mask */ 7344 vnix = ((data2 & F_DATAVIDH2) << 23) | 7345 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7346 } else 7347 vnix = 0; 7348 7349 if (tcamx & tcamy) 7350 continue; 7351 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7352 7353 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7354 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7355 7356 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7357 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7358 "%012jx %06x %06x - - %3c" 7359 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 7360 addr[1], addr[2], addr[3], addr[4], addr[5], 7361 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 7362 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7363 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7364 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7365 } else { 7366 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7367 "%012jx - - ", i, addr[0], addr[1], 7368 addr[2], addr[3], addr[4], addr[5], 7369 (uintmax_t)mask); 7370 7371 if (vlan_vld) 7372 sbuf_printf(sb, "%4u Y ", ivlan); 7373 else 7374 sbuf_printf(sb, " - N "); 7375 7376 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 7377 lookup_type ? 'I' : 'O', port_num, 7378 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7379 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7380 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7381 } 7382 7383 7384 if (cls_lo & F_T6_REPLICATE) { 7385 struct fw_ldst_cmd ldst_cmd; 7386 7387 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7388 ldst_cmd.op_to_addrspace = 7389 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7390 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7391 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7392 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7393 ldst_cmd.u.mps.rplc.fid_idx = 7394 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7395 V_FW_LDST_CMD_IDX(i)); 7396 7397 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7398 "t6mps"); 7399 if (rc) 7400 break; 7401 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7402 sizeof(ldst_cmd), &ldst_cmd); 7403 end_synchronized_op(sc, 0); 7404 7405 if (rc != 0) { 7406 sbuf_printf(sb, "%72d", rc); 7407 rc = 0; 7408 } else { 7409 sbuf_printf(sb, " %08x %08x %08x %08x" 7410 " %08x %08x %08x %08x", 7411 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 7412 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 7413 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 7414 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 7415 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7416 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7417 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7418 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7419 } 7420 } else 7421 sbuf_printf(sb, "%72s", ""); 7422 7423 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 7424 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 7425 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 7426 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 7427 } 7428 7429 if (rc) 7430 (void) sbuf_finish(sb); 7431 else 7432 rc = sbuf_finish(sb); 7433 sbuf_delete(sb); 7434 7435 return (rc); 7436 } 7437 7438 static int 7439 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 7440 { 7441 struct adapter *sc = arg1; 7442 struct sbuf *sb; 7443 int rc; 7444 uint16_t mtus[NMTUS]; 7445 7446 rc = sysctl_wire_old_buffer(req, 0); 7447 if (rc != 0) 7448 return (rc); 7449 7450 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7451 if (sb == NULL) 7452 return (ENOMEM); 7453 7454 t4_read_mtu_tbl(sc, mtus, NULL); 7455 7456 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 7457 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 7458 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 7459 mtus[14], mtus[15]); 7460 7461 rc = sbuf_finish(sb); 7462 sbuf_delete(sb); 7463 7464 return (rc); 7465 } 7466 7467 static int 7468 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 7469 { 7470 struct adapter *sc = arg1; 7471 struct sbuf *sb; 7472 int rc, i; 7473 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 7474 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 7475 static const char *tx_stats[MAX_PM_NSTATS] = { 7476 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 7477 "Tx FIFO wait", NULL, "Tx latency" 7478 }; 7479 static const char *rx_stats[MAX_PM_NSTATS] = { 7480 "Read:", "Write bypass:", "Write mem:", "Flush:", 7481 "Rx FIFO wait", NULL, "Rx latency" 7482 }; 7483 7484 rc = sysctl_wire_old_buffer(req, 0); 7485 if (rc != 0) 7486 return (rc); 7487 7488 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7489 if (sb == NULL) 7490 return (ENOMEM); 7491 7492 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 7493 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 7494 7495 sbuf_printf(sb, " Tx pcmds Tx bytes"); 7496 for (i = 0; i < 4; i++) { 7497 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7498 tx_cyc[i]); 7499 } 7500 7501 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 7502 for (i = 0; i < 4; i++) { 7503 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7504 rx_cyc[i]); 7505 } 7506 7507 if (chip_id(sc) > CHELSIO_T5) { 7508 sbuf_printf(sb, 7509 "\n Total wait Total occupancy"); 7510 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7511 tx_cyc[i]); 7512 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7513 rx_cyc[i]); 7514 7515 i += 2; 7516 MPASS(i < nitems(tx_stats)); 7517 7518 sbuf_printf(sb, 7519 "\n Reads Total wait"); 7520 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7521 tx_cyc[i]); 7522 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7523 rx_cyc[i]); 7524 } 7525 7526 rc = sbuf_finish(sb); 7527 sbuf_delete(sb); 7528 7529 return (rc); 7530 } 7531 7532 static int 7533 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 7534 { 7535 struct adapter *sc = arg1; 7536 struct sbuf *sb; 7537 int rc; 7538 struct tp_rdma_stats stats; 7539 7540 rc = sysctl_wire_old_buffer(req, 0); 7541 if (rc != 0) 7542 return (rc); 7543 7544 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7545 if (sb == NULL) 7546 return (ENOMEM); 7547 7548 mtx_lock(&sc->reg_lock); 7549 t4_tp_get_rdma_stats(sc, &stats, 0); 7550 mtx_unlock(&sc->reg_lock); 7551 7552 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 7553 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 7554 7555 rc = sbuf_finish(sb); 7556 sbuf_delete(sb); 7557 7558 return (rc); 7559 } 7560 7561 static int 7562 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 7563 { 7564 struct adapter *sc = arg1; 7565 struct sbuf *sb; 7566 int rc; 7567 struct tp_tcp_stats v4, v6; 7568 7569 rc = sysctl_wire_old_buffer(req, 0); 7570 if (rc != 0) 7571 return (rc); 7572 7573 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7574 if (sb == NULL) 7575 return (ENOMEM); 7576 7577 mtx_lock(&sc->reg_lock); 7578 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 7579 mtx_unlock(&sc->reg_lock); 7580 7581 sbuf_printf(sb, 7582 " IP IPv6\n"); 7583 sbuf_printf(sb, "OutRsts: %20u %20u\n", 7584 v4.tcp_out_rsts, v6.tcp_out_rsts); 7585 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 7586 v4.tcp_in_segs, v6.tcp_in_segs); 7587 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 7588 v4.tcp_out_segs, v6.tcp_out_segs); 7589 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 7590 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 7591 7592 rc = sbuf_finish(sb); 7593 sbuf_delete(sb); 7594 7595 return (rc); 7596 } 7597 7598 static int 7599 sysctl_tids(SYSCTL_HANDLER_ARGS) 7600 { 7601 struct adapter *sc = arg1; 7602 struct sbuf *sb; 7603 int rc; 7604 struct tid_info *t = &sc->tids; 7605 7606 rc = sysctl_wire_old_buffer(req, 0); 7607 if (rc != 0) 7608 return (rc); 7609 7610 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7611 if (sb == NULL) 7612 return (ENOMEM); 7613 7614 if (t->natids) { 7615 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 7616 t->atids_in_use); 7617 } 7618 7619 if (t->ntids) { 7620 sbuf_printf(sb, "TID range: "); 7621 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7622 uint32_t b, hb; 7623 7624 if (chip_id(sc) <= CHELSIO_T5) { 7625 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 7626 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 7627 } else { 7628 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 7629 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 7630 } 7631 7632 if (b) 7633 sbuf_printf(sb, "0-%u, ", b - 1); 7634 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 7635 } else 7636 sbuf_printf(sb, "0-%u", t->ntids - 1); 7637 sbuf_printf(sb, ", in use: %u\n", 7638 atomic_load_acq_int(&t->tids_in_use)); 7639 } 7640 7641 if (t->nstids) { 7642 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 7643 t->stid_base + t->nstids - 1, t->stids_in_use); 7644 } 7645 7646 if (t->nftids) { 7647 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 7648 t->ftid_base + t->nftids - 1); 7649 } 7650 7651 if (t->netids) { 7652 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 7653 t->etid_base + t->netids - 1); 7654 } 7655 7656 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 7657 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 7658 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 7659 7660 rc = sbuf_finish(sb); 7661 sbuf_delete(sb); 7662 7663 return (rc); 7664 } 7665 7666 static int 7667 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 7668 { 7669 struct adapter *sc = arg1; 7670 struct sbuf *sb; 7671 int rc; 7672 struct tp_err_stats stats; 7673 7674 rc = sysctl_wire_old_buffer(req, 0); 7675 if (rc != 0) 7676 return (rc); 7677 7678 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7679 if (sb == NULL) 7680 return (ENOMEM); 7681 7682 mtx_lock(&sc->reg_lock); 7683 t4_tp_get_err_stats(sc, &stats, 0); 7684 mtx_unlock(&sc->reg_lock); 7685 7686 if (sc->chip_params->nchan > 2) { 7687 sbuf_printf(sb, " channel 0 channel 1" 7688 " channel 2 channel 3\n"); 7689 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 7690 stats.mac_in_errs[0], stats.mac_in_errs[1], 7691 stats.mac_in_errs[2], stats.mac_in_errs[3]); 7692 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 7693 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 7694 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 7695 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 7696 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 7697 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 7698 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 7699 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 7700 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 7701 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 7702 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 7703 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 7704 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 7705 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 7706 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 7707 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 7708 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 7709 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 7710 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 7711 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 7712 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 7713 } else { 7714 sbuf_printf(sb, " channel 0 channel 1\n"); 7715 sbuf_printf(sb, "macInErrs: %10u %10u\n", 7716 stats.mac_in_errs[0], stats.mac_in_errs[1]); 7717 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 7718 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 7719 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 7720 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 7721 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 7722 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 7723 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 7724 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 7725 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 7726 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 7727 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 7728 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 7729 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 7730 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 7731 } 7732 7733 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 7734 stats.ofld_no_neigh, stats.ofld_cong_defer); 7735 7736 rc = sbuf_finish(sb); 7737 sbuf_delete(sb); 7738 7739 return (rc); 7740 } 7741 7742 static int 7743 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 7744 { 7745 struct adapter *sc = arg1; 7746 struct tp_params *tpp = &sc->params.tp; 7747 u_int mask; 7748 int rc; 7749 7750 mask = tpp->la_mask >> 16; 7751 rc = sysctl_handle_int(oidp, &mask, 0, req); 7752 if (rc != 0 || req->newptr == NULL) 7753 return (rc); 7754 if (mask > 0xffff) 7755 return (EINVAL); 7756 tpp->la_mask = mask << 16; 7757 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 7758 7759 return (0); 7760 } 7761 7762 struct field_desc { 7763 const char *name; 7764 u_int start; 7765 u_int width; 7766 }; 7767 7768 static void 7769 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 7770 { 7771 char buf[32]; 7772 int line_size = 0; 7773 7774 while (f->name) { 7775 uint64_t mask = (1ULL << f->width) - 1; 7776 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 7777 ((uintmax_t)v >> f->start) & mask); 7778 7779 if (line_size + len >= 79) { 7780 line_size = 8; 7781 sbuf_printf(sb, "\n "); 7782 } 7783 sbuf_printf(sb, "%s ", buf); 7784 line_size += len + 1; 7785 f++; 7786 } 7787 sbuf_printf(sb, "\n"); 7788 } 7789 7790 static const struct field_desc tp_la0[] = { 7791 { "RcfOpCodeOut", 60, 4 }, 7792 { "State", 56, 4 }, 7793 { "WcfState", 52, 4 }, 7794 { "RcfOpcSrcOut", 50, 2 }, 7795 { "CRxError", 49, 1 }, 7796 { "ERxError", 48, 1 }, 7797 { "SanityFailed", 47, 1 }, 7798 { "SpuriousMsg", 46, 1 }, 7799 { "FlushInputMsg", 45, 1 }, 7800 { "FlushInputCpl", 44, 1 }, 7801 { "RssUpBit", 43, 1 }, 7802 { "RssFilterHit", 42, 1 }, 7803 { "Tid", 32, 10 }, 7804 { "InitTcb", 31, 1 }, 7805 { "LineNumber", 24, 7 }, 7806 { "Emsg", 23, 1 }, 7807 { "EdataOut", 22, 1 }, 7808 { "Cmsg", 21, 1 }, 7809 { "CdataOut", 20, 1 }, 7810 { "EreadPdu", 19, 1 }, 7811 { "CreadPdu", 18, 1 }, 7812 { "TunnelPkt", 17, 1 }, 7813 { "RcfPeerFin", 16, 1 }, 7814 { "RcfReasonOut", 12, 4 }, 7815 { "TxCchannel", 10, 2 }, 7816 { "RcfTxChannel", 8, 2 }, 7817 { "RxEchannel", 6, 2 }, 7818 { "RcfRxChannel", 5, 1 }, 7819 { "RcfDataOutSrdy", 4, 1 }, 7820 { "RxDvld", 3, 1 }, 7821 { "RxOoDvld", 2, 1 }, 7822 { "RxCongestion", 1, 1 }, 7823 { "TxCongestion", 0, 1 }, 7824 { NULL } 7825 }; 7826 7827 static const struct field_desc tp_la1[] = { 7828 { "CplCmdIn", 56, 8 }, 7829 { "CplCmdOut", 48, 8 }, 7830 { "ESynOut", 47, 1 }, 7831 { "EAckOut", 46, 1 }, 7832 { "EFinOut", 45, 1 }, 7833 { "ERstOut", 44, 1 }, 7834 { "SynIn", 43, 1 }, 7835 { "AckIn", 42, 1 }, 7836 { "FinIn", 41, 1 }, 7837 { "RstIn", 40, 1 }, 7838 { "DataIn", 39, 1 }, 7839 { "DataInVld", 38, 1 }, 7840 { "PadIn", 37, 1 }, 7841 { "RxBufEmpty", 36, 1 }, 7842 { "RxDdp", 35, 1 }, 7843 { "RxFbCongestion", 34, 1 }, 7844 { "TxFbCongestion", 33, 1 }, 7845 { "TxPktSumSrdy", 32, 1 }, 7846 { "RcfUlpType", 28, 4 }, 7847 { "Eread", 27, 1 }, 7848 { "Ebypass", 26, 1 }, 7849 { "Esave", 25, 1 }, 7850 { "Static0", 24, 1 }, 7851 { "Cread", 23, 1 }, 7852 { "Cbypass", 22, 1 }, 7853 { "Csave", 21, 1 }, 7854 { "CPktOut", 20, 1 }, 7855 { "RxPagePoolFull", 18, 2 }, 7856 { "RxLpbkPkt", 17, 1 }, 7857 { "TxLpbkPkt", 16, 1 }, 7858 { "RxVfValid", 15, 1 }, 7859 { "SynLearned", 14, 1 }, 7860 { "SetDelEntry", 13, 1 }, 7861 { "SetInvEntry", 12, 1 }, 7862 { "CpcmdDvld", 11, 1 }, 7863 { "CpcmdSave", 10, 1 }, 7864 { "RxPstructsFull", 8, 2 }, 7865 { "EpcmdDvld", 7, 1 }, 7866 { "EpcmdFlush", 6, 1 }, 7867 { "EpcmdTrimPrefix", 5, 1 }, 7868 { "EpcmdTrimPostfix", 4, 1 }, 7869 { "ERssIp4Pkt", 3, 1 }, 7870 { "ERssIp6Pkt", 2, 1 }, 7871 { "ERssTcpUdpPkt", 1, 1 }, 7872 { "ERssFceFipPkt", 0, 1 }, 7873 { NULL } 7874 }; 7875 7876 static const struct field_desc tp_la2[] = { 7877 { "CplCmdIn", 56, 8 }, 7878 { "MpsVfVld", 55, 1 }, 7879 { "MpsPf", 52, 3 }, 7880 { "MpsVf", 44, 8 }, 7881 { "SynIn", 43, 1 }, 7882 { "AckIn", 42, 1 }, 7883 { "FinIn", 41, 1 }, 7884 { "RstIn", 40, 1 }, 7885 { "DataIn", 39, 1 }, 7886 { "DataInVld", 38, 1 }, 7887 { "PadIn", 37, 1 }, 7888 { "RxBufEmpty", 36, 1 }, 7889 { "RxDdp", 35, 1 }, 7890 { "RxFbCongestion", 34, 1 }, 7891 { "TxFbCongestion", 33, 1 }, 7892 { "TxPktSumSrdy", 32, 1 }, 7893 { "RcfUlpType", 28, 4 }, 7894 { "Eread", 27, 1 }, 7895 { "Ebypass", 26, 1 }, 7896 { "Esave", 25, 1 }, 7897 { "Static0", 24, 1 }, 7898 { "Cread", 23, 1 }, 7899 { "Cbypass", 22, 1 }, 7900 { "Csave", 21, 1 }, 7901 { "CPktOut", 20, 1 }, 7902 { "RxPagePoolFull", 18, 2 }, 7903 { "RxLpbkPkt", 17, 1 }, 7904 { "TxLpbkPkt", 16, 1 }, 7905 { "RxVfValid", 15, 1 }, 7906 { "SynLearned", 14, 1 }, 7907 { "SetDelEntry", 13, 1 }, 7908 { "SetInvEntry", 12, 1 }, 7909 { "CpcmdDvld", 11, 1 }, 7910 { "CpcmdSave", 10, 1 }, 7911 { "RxPstructsFull", 8, 2 }, 7912 { "EpcmdDvld", 7, 1 }, 7913 { "EpcmdFlush", 6, 1 }, 7914 { "EpcmdTrimPrefix", 5, 1 }, 7915 { "EpcmdTrimPostfix", 4, 1 }, 7916 { "ERssIp4Pkt", 3, 1 }, 7917 { "ERssIp6Pkt", 2, 1 }, 7918 { "ERssTcpUdpPkt", 1, 1 }, 7919 { "ERssFceFipPkt", 0, 1 }, 7920 { NULL } 7921 }; 7922 7923 static void 7924 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 7925 { 7926 7927 field_desc_show(sb, *p, tp_la0); 7928 } 7929 7930 static void 7931 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 7932 { 7933 7934 if (idx) 7935 sbuf_printf(sb, "\n"); 7936 field_desc_show(sb, p[0], tp_la0); 7937 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7938 field_desc_show(sb, p[1], tp_la0); 7939 } 7940 7941 static void 7942 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 7943 { 7944 7945 if (idx) 7946 sbuf_printf(sb, "\n"); 7947 field_desc_show(sb, p[0], tp_la0); 7948 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7949 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 7950 } 7951 7952 static int 7953 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 7954 { 7955 struct adapter *sc = arg1; 7956 struct sbuf *sb; 7957 uint64_t *buf, *p; 7958 int rc; 7959 u_int i, inc; 7960 void (*show_func)(struct sbuf *, uint64_t *, int); 7961 7962 rc = sysctl_wire_old_buffer(req, 0); 7963 if (rc != 0) 7964 return (rc); 7965 7966 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7967 if (sb == NULL) 7968 return (ENOMEM); 7969 7970 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 7971 7972 t4_tp_read_la(sc, buf, NULL); 7973 p = buf; 7974 7975 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 7976 case 2: 7977 inc = 2; 7978 show_func = tp_la_show2; 7979 break; 7980 case 3: 7981 inc = 2; 7982 show_func = tp_la_show3; 7983 break; 7984 default: 7985 inc = 1; 7986 show_func = tp_la_show; 7987 } 7988 7989 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 7990 (*show_func)(sb, p, i); 7991 7992 rc = sbuf_finish(sb); 7993 sbuf_delete(sb); 7994 free(buf, M_CXGBE); 7995 return (rc); 7996 } 7997 7998 static int 7999 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 8000 { 8001 struct adapter *sc = arg1; 8002 struct sbuf *sb; 8003 int rc; 8004 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 8005 8006 rc = sysctl_wire_old_buffer(req, 0); 8007 if (rc != 0) 8008 return (rc); 8009 8010 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8011 if (sb == NULL) 8012 return (ENOMEM); 8013 8014 t4_get_chan_txrate(sc, nrate, orate); 8015 8016 if (sc->chip_params->nchan > 2) { 8017 sbuf_printf(sb, " channel 0 channel 1" 8018 " channel 2 channel 3\n"); 8019 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 8020 nrate[0], nrate[1], nrate[2], nrate[3]); 8021 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 8022 orate[0], orate[1], orate[2], orate[3]); 8023 } else { 8024 sbuf_printf(sb, " channel 0 channel 1\n"); 8025 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 8026 nrate[0], nrate[1]); 8027 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 8028 orate[0], orate[1]); 8029 } 8030 8031 rc = sbuf_finish(sb); 8032 sbuf_delete(sb); 8033 8034 return (rc); 8035 } 8036 8037 static int 8038 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 8039 { 8040 struct adapter *sc = arg1; 8041 struct sbuf *sb; 8042 uint32_t *buf, *p; 8043 int rc, i; 8044 8045 rc = sysctl_wire_old_buffer(req, 0); 8046 if (rc != 0) 8047 return (rc); 8048 8049 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8050 if (sb == NULL) 8051 return (ENOMEM); 8052 8053 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 8054 M_ZERO | M_WAITOK); 8055 8056 t4_ulprx_read_la(sc, buf); 8057 p = buf; 8058 8059 sbuf_printf(sb, " Pcmd Type Message" 8060 " Data"); 8061 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 8062 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 8063 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 8064 } 8065 8066 rc = sbuf_finish(sb); 8067 sbuf_delete(sb); 8068 free(buf, M_CXGBE); 8069 return (rc); 8070 } 8071 8072 static int 8073 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 8074 { 8075 struct adapter *sc = arg1; 8076 struct sbuf *sb; 8077 int rc, v; 8078 8079 MPASS(chip_id(sc) >= CHELSIO_T5); 8080 8081 rc = sysctl_wire_old_buffer(req, 0); 8082 if (rc != 0) 8083 return (rc); 8084 8085 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8086 if (sb == NULL) 8087 return (ENOMEM); 8088 8089 v = t4_read_reg(sc, A_SGE_STAT_CFG); 8090 if (G_STATSOURCE_T5(v) == 7) { 8091 int mode; 8092 8093 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 8094 if (mode == 0) { 8095 sbuf_printf(sb, "total %d, incomplete %d", 8096 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8097 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8098 } else if (mode == 1) { 8099 sbuf_printf(sb, "total %d, data overflow %d", 8100 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8101 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8102 } else { 8103 sbuf_printf(sb, "unknown mode %d", mode); 8104 } 8105 } 8106 rc = sbuf_finish(sb); 8107 sbuf_delete(sb); 8108 8109 return (rc); 8110 } 8111 8112 static int 8113 sysctl_tc_params(SYSCTL_HANDLER_ARGS) 8114 { 8115 struct adapter *sc = arg1; 8116 struct tx_cl_rl_params tc; 8117 struct sbuf *sb; 8118 int i, rc, port_id, mbps, gbps; 8119 8120 rc = sysctl_wire_old_buffer(req, 0); 8121 if (rc != 0) 8122 return (rc); 8123 8124 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8125 if (sb == NULL) 8126 return (ENOMEM); 8127 8128 port_id = arg2 >> 16; 8129 MPASS(port_id < sc->params.nports); 8130 MPASS(sc->port[port_id] != NULL); 8131 i = arg2 & 0xffff; 8132 MPASS(i < sc->chip_params->nsched_cls); 8133 8134 mtx_lock(&sc->tc_lock); 8135 tc = sc->port[port_id]->sched_params->cl_rl[i]; 8136 mtx_unlock(&sc->tc_lock); 8137 8138 if (tc.flags & TX_CLRL_ERROR) { 8139 sbuf_printf(sb, "error"); 8140 goto done; 8141 } 8142 8143 if (tc.ratemode == SCHED_CLASS_RATEMODE_REL) { 8144 /* XXX: top speed or actual link speed? */ 8145 gbps = port_top_speed(sc->port[port_id]); 8146 sbuf_printf(sb, " %u%% of %uGbps", tc.maxrate, gbps); 8147 } else if (tc.ratemode == SCHED_CLASS_RATEMODE_ABS) { 8148 switch (tc.rateunit) { 8149 case SCHED_CLASS_RATEUNIT_BITS: 8150 mbps = tc.maxrate / 1000; 8151 gbps = tc.maxrate / 1000000; 8152 if (tc.maxrate == gbps * 1000000) 8153 sbuf_printf(sb, " %uGbps", gbps); 8154 else if (tc.maxrate == mbps * 1000) 8155 sbuf_printf(sb, " %uMbps", mbps); 8156 else 8157 sbuf_printf(sb, " %uKbps", tc.maxrate); 8158 break; 8159 case SCHED_CLASS_RATEUNIT_PKTS: 8160 sbuf_printf(sb, " %upps", tc.maxrate); 8161 break; 8162 default: 8163 rc = ENXIO; 8164 goto done; 8165 } 8166 } 8167 8168 switch (tc.mode) { 8169 case SCHED_CLASS_MODE_CLASS: 8170 sbuf_printf(sb, " aggregate"); 8171 break; 8172 case SCHED_CLASS_MODE_FLOW: 8173 sbuf_printf(sb, " per-flow"); 8174 break; 8175 default: 8176 rc = ENXIO; 8177 goto done; 8178 } 8179 8180 done: 8181 if (rc == 0) 8182 rc = sbuf_finish(sb); 8183 sbuf_delete(sb); 8184 8185 return (rc); 8186 } 8187 #endif 8188 8189 #ifdef TCP_OFFLOAD 8190 static void 8191 unit_conv(char *buf, size_t len, u_int val, u_int factor) 8192 { 8193 u_int rem = val % factor; 8194 8195 if (rem == 0) 8196 snprintf(buf, len, "%u", val / factor); 8197 else { 8198 while (rem % 10 == 0) 8199 rem /= 10; 8200 snprintf(buf, len, "%u.%u", val / factor, rem); 8201 } 8202 } 8203 8204 static int 8205 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 8206 { 8207 struct adapter *sc = arg1; 8208 char buf[16]; 8209 u_int res, re; 8210 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8211 8212 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8213 switch (arg2) { 8214 case 0: 8215 /* timer_tick */ 8216 re = G_TIMERRESOLUTION(res); 8217 break; 8218 case 1: 8219 /* TCP timestamp tick */ 8220 re = G_TIMESTAMPRESOLUTION(res); 8221 break; 8222 case 2: 8223 /* DACK tick */ 8224 re = G_DELAYEDACKRESOLUTION(res); 8225 break; 8226 default: 8227 return (EDOOFUS); 8228 } 8229 8230 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 8231 8232 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 8233 } 8234 8235 static int 8236 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 8237 { 8238 struct adapter *sc = arg1; 8239 u_int res, dack_re, v; 8240 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8241 8242 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8243 dack_re = G_DELAYEDACKRESOLUTION(res); 8244 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 8245 8246 return (sysctl_handle_int(oidp, &v, 0, req)); 8247 } 8248 8249 static int 8250 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 8251 { 8252 struct adapter *sc = arg1; 8253 int reg = arg2; 8254 u_int tre; 8255 u_long tp_tick_us, v; 8256 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8257 8258 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 8259 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 8260 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 8261 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 8262 8263 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 8264 tp_tick_us = (cclk_ps << tre) / 1000000; 8265 8266 if (reg == A_TP_INIT_SRTT) 8267 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 8268 else 8269 v = tp_tick_us * t4_read_reg(sc, reg); 8270 8271 return (sysctl_handle_long(oidp, &v, 0, req)); 8272 } 8273 8274 /* 8275 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 8276 * passed to this function. 8277 */ 8278 static int 8279 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 8280 { 8281 struct adapter *sc = arg1; 8282 int idx = arg2; 8283 u_int v; 8284 8285 MPASS(idx >= 0 && idx <= 24); 8286 8287 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 8288 8289 return (sysctl_handle_int(oidp, &v, 0, req)); 8290 } 8291 8292 static int 8293 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 8294 { 8295 struct adapter *sc = arg1; 8296 int idx = arg2; 8297 u_int shift, v, r; 8298 8299 MPASS(idx >= 0 && idx < 16); 8300 8301 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 8302 shift = (idx & 3) << 3; 8303 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 8304 8305 return (sysctl_handle_int(oidp, &v, 0, req)); 8306 } 8307 8308 static int 8309 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 8310 { 8311 struct vi_info *vi = arg1; 8312 struct adapter *sc = vi->pi->adapter; 8313 int idx, rc, i; 8314 struct sge_ofld_rxq *ofld_rxq; 8315 uint8_t v; 8316 8317 idx = vi->ofld_tmr_idx; 8318 8319 rc = sysctl_handle_int(oidp, &idx, 0, req); 8320 if (rc != 0 || req->newptr == NULL) 8321 return (rc); 8322 8323 if (idx < 0 || idx >= SGE_NTIMERS) 8324 return (EINVAL); 8325 8326 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8327 "t4otmr"); 8328 if (rc) 8329 return (rc); 8330 8331 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 8332 for_each_ofld_rxq(vi, i, ofld_rxq) { 8333 #ifdef atomic_store_rel_8 8334 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 8335 #else 8336 ofld_rxq->iq.intr_params = v; 8337 #endif 8338 } 8339 vi->ofld_tmr_idx = idx; 8340 8341 end_synchronized_op(sc, LOCK_HELD); 8342 return (0); 8343 } 8344 8345 static int 8346 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 8347 { 8348 struct vi_info *vi = arg1; 8349 struct adapter *sc = vi->pi->adapter; 8350 int idx, rc; 8351 8352 idx = vi->ofld_pktc_idx; 8353 8354 rc = sysctl_handle_int(oidp, &idx, 0, req); 8355 if (rc != 0 || req->newptr == NULL) 8356 return (rc); 8357 8358 if (idx < -1 || idx >= SGE_NCOUNTERS) 8359 return (EINVAL); 8360 8361 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8362 "t4opktc"); 8363 if (rc) 8364 return (rc); 8365 8366 if (vi->flags & VI_INIT_DONE) 8367 rc = EBUSY; /* cannot be changed once the queues are created */ 8368 else 8369 vi->ofld_pktc_idx = idx; 8370 8371 end_synchronized_op(sc, LOCK_HELD); 8372 return (rc); 8373 } 8374 #endif 8375 8376 static uint32_t 8377 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf) 8378 { 8379 uint32_t mode; 8380 8381 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR | 8382 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT; 8383 8384 if (fconf & F_FRAGMENTATION) 8385 mode |= T4_FILTER_IP_FRAGMENT; 8386 8387 if (fconf & F_MPSHITTYPE) 8388 mode |= T4_FILTER_MPS_HIT_TYPE; 8389 8390 if (fconf & F_MACMATCH) 8391 mode |= T4_FILTER_MAC_IDX; 8392 8393 if (fconf & F_ETHERTYPE) 8394 mode |= T4_FILTER_ETH_TYPE; 8395 8396 if (fconf & F_PROTOCOL) 8397 mode |= T4_FILTER_IP_PROTO; 8398 8399 if (fconf & F_TOS) 8400 mode |= T4_FILTER_IP_TOS; 8401 8402 if (fconf & F_VLAN) 8403 mode |= T4_FILTER_VLAN; 8404 8405 if (fconf & F_VNIC_ID) { 8406 mode |= T4_FILTER_VNIC; 8407 if (iconf & F_VNIC) 8408 mode |= T4_FILTER_IC_VNIC; 8409 } 8410 8411 if (fconf & F_PORT) 8412 mode |= T4_FILTER_PORT; 8413 8414 if (fconf & F_FCOE) 8415 mode |= T4_FILTER_FCoE; 8416 8417 return (mode); 8418 } 8419 8420 static uint32_t 8421 mode_to_fconf(uint32_t mode) 8422 { 8423 uint32_t fconf = 0; 8424 8425 if (mode & T4_FILTER_IP_FRAGMENT) 8426 fconf |= F_FRAGMENTATION; 8427 8428 if (mode & T4_FILTER_MPS_HIT_TYPE) 8429 fconf |= F_MPSHITTYPE; 8430 8431 if (mode & T4_FILTER_MAC_IDX) 8432 fconf |= F_MACMATCH; 8433 8434 if (mode & T4_FILTER_ETH_TYPE) 8435 fconf |= F_ETHERTYPE; 8436 8437 if (mode & T4_FILTER_IP_PROTO) 8438 fconf |= F_PROTOCOL; 8439 8440 if (mode & T4_FILTER_IP_TOS) 8441 fconf |= F_TOS; 8442 8443 if (mode & T4_FILTER_VLAN) 8444 fconf |= F_VLAN; 8445 8446 if (mode & T4_FILTER_VNIC) 8447 fconf |= F_VNIC_ID; 8448 8449 if (mode & T4_FILTER_PORT) 8450 fconf |= F_PORT; 8451 8452 if (mode & T4_FILTER_FCoE) 8453 fconf |= F_FCOE; 8454 8455 return (fconf); 8456 } 8457 8458 static uint32_t 8459 mode_to_iconf(uint32_t mode) 8460 { 8461 8462 if (mode & T4_FILTER_IC_VNIC) 8463 return (F_VNIC); 8464 return (0); 8465 } 8466 8467 static int check_fspec_against_fconf_iconf(struct adapter *sc, 8468 struct t4_filter_specification *fs) 8469 { 8470 struct tp_params *tpp = &sc->params.tp; 8471 uint32_t fconf = 0; 8472 8473 if (fs->val.frag || fs->mask.frag) 8474 fconf |= F_FRAGMENTATION; 8475 8476 if (fs->val.matchtype || fs->mask.matchtype) 8477 fconf |= F_MPSHITTYPE; 8478 8479 if (fs->val.macidx || fs->mask.macidx) 8480 fconf |= F_MACMATCH; 8481 8482 if (fs->val.ethtype || fs->mask.ethtype) 8483 fconf |= F_ETHERTYPE; 8484 8485 if (fs->val.proto || fs->mask.proto) 8486 fconf |= F_PROTOCOL; 8487 8488 if (fs->val.tos || fs->mask.tos) 8489 fconf |= F_TOS; 8490 8491 if (fs->val.vlan_vld || fs->mask.vlan_vld) 8492 fconf |= F_VLAN; 8493 8494 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) { 8495 fconf |= F_VNIC_ID; 8496 if (tpp->ingress_config & F_VNIC) 8497 return (EINVAL); 8498 } 8499 8500 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) { 8501 fconf |= F_VNIC_ID; 8502 if ((tpp->ingress_config & F_VNIC) == 0) 8503 return (EINVAL); 8504 } 8505 8506 if (fs->val.iport || fs->mask.iport) 8507 fconf |= F_PORT; 8508 8509 if (fs->val.fcoe || fs->mask.fcoe) 8510 fconf |= F_FCOE; 8511 8512 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map) 8513 return (E2BIG); 8514 8515 return (0); 8516 } 8517 8518 static int 8519 get_filter_mode(struct adapter *sc, uint32_t *mode) 8520 { 8521 struct tp_params *tpp = &sc->params.tp; 8522 8523 /* 8524 * We trust the cached values of the relevant TP registers. This means 8525 * things work reliably only if writes to those registers are always via 8526 * t4_set_filter_mode. 8527 */ 8528 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config); 8529 8530 return (0); 8531 } 8532 8533 static int 8534 set_filter_mode(struct adapter *sc, uint32_t mode) 8535 { 8536 struct tp_params *tpp = &sc->params.tp; 8537 uint32_t fconf, iconf; 8538 int rc; 8539 8540 iconf = mode_to_iconf(mode); 8541 if ((iconf ^ tpp->ingress_config) & F_VNIC) { 8542 /* 8543 * For now we just complain if A_TP_INGRESS_CONFIG is not 8544 * already set to the correct value for the requested filter 8545 * mode. It's not clear if it's safe to write to this register 8546 * on the fly. (And we trust the cached value of the register). 8547 */ 8548 return (EBUSY); 8549 } 8550 8551 fconf = mode_to_fconf(mode); 8552 8553 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8554 "t4setfm"); 8555 if (rc) 8556 return (rc); 8557 8558 if (sc->tids.ftids_in_use > 0) { 8559 rc = EBUSY; 8560 goto done; 8561 } 8562 8563 #ifdef TCP_OFFLOAD 8564 if (uld_active(sc, ULD_TOM)) { 8565 rc = EBUSY; 8566 goto done; 8567 } 8568 #endif 8569 8570 rc = -t4_set_filter_mode(sc, fconf, true); 8571 done: 8572 end_synchronized_op(sc, LOCK_HELD); 8573 return (rc); 8574 } 8575 8576 static inline uint64_t 8577 get_filter_hits(struct adapter *sc, uint32_t fid) 8578 { 8579 uint32_t tcb_addr; 8580 8581 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) + 8582 (fid + sc->tids.ftid_base) * TCB_SIZE; 8583 8584 if (is_t4(sc)) { 8585 uint64_t hits; 8586 8587 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8); 8588 return (be64toh(hits)); 8589 } else { 8590 uint32_t hits; 8591 8592 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4); 8593 return (be32toh(hits)); 8594 } 8595 } 8596 8597 static int 8598 get_filter(struct adapter *sc, struct t4_filter *t) 8599 { 8600 int i, rc, nfilters = sc->tids.nftids; 8601 struct filter_entry *f; 8602 8603 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8604 "t4getf"); 8605 if (rc) 8606 return (rc); 8607 8608 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL || 8609 t->idx >= nfilters) { 8610 t->idx = 0xffffffff; 8611 goto done; 8612 } 8613 8614 f = &sc->tids.ftid_tab[t->idx]; 8615 for (i = t->idx; i < nfilters; i++, f++) { 8616 if (f->valid) { 8617 t->idx = i; 8618 t->l2tidx = f->l2t ? f->l2t->idx : 0; 8619 t->smtidx = f->smtidx; 8620 if (f->fs.hitcnts) 8621 t->hits = get_filter_hits(sc, t->idx); 8622 else 8623 t->hits = UINT64_MAX; 8624 t->fs = f->fs; 8625 8626 goto done; 8627 } 8628 } 8629 8630 t->idx = 0xffffffff; 8631 done: 8632 end_synchronized_op(sc, LOCK_HELD); 8633 return (0); 8634 } 8635 8636 static int 8637 set_filter(struct adapter *sc, struct t4_filter *t) 8638 { 8639 unsigned int nfilters, nports; 8640 struct filter_entry *f; 8641 int i, rc; 8642 8643 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf"); 8644 if (rc) 8645 return (rc); 8646 8647 nfilters = sc->tids.nftids; 8648 nports = sc->params.nports; 8649 8650 if (nfilters == 0) { 8651 rc = ENOTSUP; 8652 goto done; 8653 } 8654 8655 if (t->idx >= nfilters) { 8656 rc = EINVAL; 8657 goto done; 8658 } 8659 8660 /* Validate against the global filter mode and ingress config */ 8661 rc = check_fspec_against_fconf_iconf(sc, &t->fs); 8662 if (rc != 0) 8663 goto done; 8664 8665 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) { 8666 rc = EINVAL; 8667 goto done; 8668 } 8669 8670 if (t->fs.val.iport >= nports) { 8671 rc = EINVAL; 8672 goto done; 8673 } 8674 8675 /* Can't specify an iq if not steering to it */ 8676 if (!t->fs.dirsteer && t->fs.iq) { 8677 rc = EINVAL; 8678 goto done; 8679 } 8680 8681 /* IPv6 filter idx must be 4 aligned */ 8682 if (t->fs.type == 1 && 8683 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) { 8684 rc = EINVAL; 8685 goto done; 8686 } 8687 8688 if (!(sc->flags & FULL_INIT_DONE) && 8689 ((rc = adapter_full_init(sc)) != 0)) 8690 goto done; 8691 8692 if (sc->tids.ftid_tab == NULL) { 8693 KASSERT(sc->tids.ftids_in_use == 0, 8694 ("%s: no memory allocated but filters_in_use > 0", 8695 __func__)); 8696 8697 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) * 8698 nfilters, M_CXGBE, M_NOWAIT | M_ZERO); 8699 if (sc->tids.ftid_tab == NULL) { 8700 rc = ENOMEM; 8701 goto done; 8702 } 8703 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF); 8704 } 8705 8706 for (i = 0; i < 4; i++) { 8707 f = &sc->tids.ftid_tab[t->idx + i]; 8708 8709 if (f->pending || f->valid) { 8710 rc = EBUSY; 8711 goto done; 8712 } 8713 if (f->locked) { 8714 rc = EPERM; 8715 goto done; 8716 } 8717 8718 if (t->fs.type == 0) 8719 break; 8720 } 8721 8722 f = &sc->tids.ftid_tab[t->idx]; 8723 f->fs = t->fs; 8724 8725 rc = set_filter_wr(sc, t->idx); 8726 done: 8727 end_synchronized_op(sc, 0); 8728 8729 if (rc == 0) { 8730 mtx_lock(&sc->tids.ftid_lock); 8731 for (;;) { 8732 if (f->pending == 0) { 8733 rc = f->valid ? 0 : EIO; 8734 break; 8735 } 8736 8737 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8738 PCATCH, "t4setfw", 0)) { 8739 rc = EINPROGRESS; 8740 break; 8741 } 8742 } 8743 mtx_unlock(&sc->tids.ftid_lock); 8744 } 8745 return (rc); 8746 } 8747 8748 static int 8749 del_filter(struct adapter *sc, struct t4_filter *t) 8750 { 8751 unsigned int nfilters; 8752 struct filter_entry *f; 8753 int rc; 8754 8755 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf"); 8756 if (rc) 8757 return (rc); 8758 8759 nfilters = sc->tids.nftids; 8760 8761 if (nfilters == 0) { 8762 rc = ENOTSUP; 8763 goto done; 8764 } 8765 8766 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 || 8767 t->idx >= nfilters) { 8768 rc = EINVAL; 8769 goto done; 8770 } 8771 8772 if (!(sc->flags & FULL_INIT_DONE)) { 8773 rc = EAGAIN; 8774 goto done; 8775 } 8776 8777 f = &sc->tids.ftid_tab[t->idx]; 8778 8779 if (f->pending) { 8780 rc = EBUSY; 8781 goto done; 8782 } 8783 if (f->locked) { 8784 rc = EPERM; 8785 goto done; 8786 } 8787 8788 if (f->valid) { 8789 t->fs = f->fs; /* extra info for the caller */ 8790 rc = del_filter_wr(sc, t->idx); 8791 } 8792 8793 done: 8794 end_synchronized_op(sc, 0); 8795 8796 if (rc == 0) { 8797 mtx_lock(&sc->tids.ftid_lock); 8798 for (;;) { 8799 if (f->pending == 0) { 8800 rc = f->valid ? EIO : 0; 8801 break; 8802 } 8803 8804 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8805 PCATCH, "t4delfw", 0)) { 8806 rc = EINPROGRESS; 8807 break; 8808 } 8809 } 8810 mtx_unlock(&sc->tids.ftid_lock); 8811 } 8812 8813 return (rc); 8814 } 8815 8816 static void 8817 clear_filter(struct filter_entry *f) 8818 { 8819 if (f->l2t) 8820 t4_l2t_release(f->l2t); 8821 8822 bzero(f, sizeof (*f)); 8823 } 8824 8825 static int 8826 set_filter_wr(struct adapter *sc, int fidx) 8827 { 8828 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8829 struct fw_filter_wr *fwr; 8830 unsigned int ftid, vnic_vld, vnic_vld_mask; 8831 struct wrq_cookie cookie; 8832 8833 ASSERT_SYNCHRONIZED_OP(sc); 8834 8835 if (f->fs.newdmac || f->fs.newvlan) { 8836 /* This filter needs an L2T entry; allocate one. */ 8837 f->l2t = t4_l2t_alloc_switching(sc->l2t); 8838 if (f->l2t == NULL) 8839 return (EAGAIN); 8840 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport, 8841 f->fs.dmac)) { 8842 t4_l2t_release(f->l2t); 8843 f->l2t = NULL; 8844 return (ENOMEM); 8845 } 8846 } 8847 8848 /* Already validated against fconf, iconf */ 8849 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0); 8850 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0); 8851 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld) 8852 vnic_vld = 1; 8853 else 8854 vnic_vld = 0; 8855 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld) 8856 vnic_vld_mask = 1; 8857 else 8858 vnic_vld_mask = 0; 8859 8860 ftid = sc->tids.ftid_base + fidx; 8861 8862 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8863 if (fwr == NULL) 8864 return (ENOMEM); 8865 bzero(fwr, sizeof(*fwr)); 8866 8867 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR)); 8868 fwr->len16_pkd = htobe32(FW_LEN16(*fwr)); 8869 fwr->tid_to_iq = 8870 htobe32(V_FW_FILTER_WR_TID(ftid) | 8871 V_FW_FILTER_WR_RQTYPE(f->fs.type) | 8872 V_FW_FILTER_WR_NOREPLY(0) | 8873 V_FW_FILTER_WR_IQ(f->fs.iq)); 8874 fwr->del_filter_to_l2tix = 8875 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) | 8876 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) | 8877 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) | 8878 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) | 8879 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) | 8880 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) | 8881 V_FW_FILTER_WR_DMAC(f->fs.newdmac) | 8882 V_FW_FILTER_WR_SMAC(f->fs.newsmac) | 8883 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT || 8884 f->fs.newvlan == VLAN_REWRITE) | 8885 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE || 8886 f->fs.newvlan == VLAN_REWRITE) | 8887 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) | 8888 V_FW_FILTER_WR_TXCHAN(f->fs.eport) | 8889 V_FW_FILTER_WR_PRIO(f->fs.prio) | 8890 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0)); 8891 fwr->ethtype = htobe16(f->fs.val.ethtype); 8892 fwr->ethtypem = htobe16(f->fs.mask.ethtype); 8893 fwr->frag_to_ovlan_vldm = 8894 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) | 8895 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) | 8896 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) | 8897 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) | 8898 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) | 8899 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask)); 8900 fwr->smac_sel = 0; 8901 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) | 8902 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id)); 8903 fwr->maci_to_matchtypem = 8904 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) | 8905 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) | 8906 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) | 8907 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) | 8908 V_FW_FILTER_WR_PORT(f->fs.val.iport) | 8909 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) | 8910 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) | 8911 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype)); 8912 fwr->ptcl = f->fs.val.proto; 8913 fwr->ptclm = f->fs.mask.proto; 8914 fwr->ttyp = f->fs.val.tos; 8915 fwr->ttypm = f->fs.mask.tos; 8916 fwr->ivlan = htobe16(f->fs.val.vlan); 8917 fwr->ivlanm = htobe16(f->fs.mask.vlan); 8918 fwr->ovlan = htobe16(f->fs.val.vnic); 8919 fwr->ovlanm = htobe16(f->fs.mask.vnic); 8920 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip)); 8921 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm)); 8922 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip)); 8923 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm)); 8924 fwr->lp = htobe16(f->fs.val.dport); 8925 fwr->lpm = htobe16(f->fs.mask.dport); 8926 fwr->fp = htobe16(f->fs.val.sport); 8927 fwr->fpm = htobe16(f->fs.mask.sport); 8928 if (f->fs.newsmac) 8929 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma)); 8930 8931 f->pending = 1; 8932 sc->tids.ftids_in_use++; 8933 8934 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8935 return (0); 8936 } 8937 8938 static int 8939 del_filter_wr(struct adapter *sc, int fidx) 8940 { 8941 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8942 struct fw_filter_wr *fwr; 8943 unsigned int ftid; 8944 struct wrq_cookie cookie; 8945 8946 ftid = sc->tids.ftid_base + fidx; 8947 8948 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8949 if (fwr == NULL) 8950 return (ENOMEM); 8951 bzero(fwr, sizeof (*fwr)); 8952 8953 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id); 8954 8955 f->pending = 1; 8956 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8957 return (0); 8958 } 8959 8960 int 8961 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8962 { 8963 struct adapter *sc = iq->adapter; 8964 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1); 8965 unsigned int idx = GET_TID(rpl); 8966 unsigned int rc; 8967 struct filter_entry *f; 8968 8969 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 8970 rss->opcode)); 8971 MPASS(iq == &sc->sge.fwq); 8972 MPASS(is_ftid(sc, idx)); 8973 8974 idx -= sc->tids.ftid_base; 8975 f = &sc->tids.ftid_tab[idx]; 8976 rc = G_COOKIE(rpl->cookie); 8977 8978 mtx_lock(&sc->tids.ftid_lock); 8979 if (rc == FW_FILTER_WR_FLT_ADDED) { 8980 KASSERT(f->pending, ("%s: filter[%u] isn't pending.", 8981 __func__, idx)); 8982 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; 8983 f->pending = 0; /* asynchronous setup completed */ 8984 f->valid = 1; 8985 } else { 8986 if (rc != FW_FILTER_WR_FLT_DELETED) { 8987 /* Add or delete failed, display an error */ 8988 log(LOG_ERR, 8989 "filter %u setup failed with error %u\n", 8990 idx, rc); 8991 } 8992 8993 clear_filter(f); 8994 sc->tids.ftids_in_use--; 8995 } 8996 wakeup(&sc->tids.ftid_tab); 8997 mtx_unlock(&sc->tids.ftid_lock); 8998 8999 return (0); 9000 } 9001 9002 static int 9003 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 9004 { 9005 9006 MPASS(iq->set_tcb_rpl != NULL); 9007 return (iq->set_tcb_rpl(iq, rss, m)); 9008 } 9009 9010 static int 9011 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 9012 { 9013 9014 MPASS(iq->l2t_write_rpl != NULL); 9015 return (iq->l2t_write_rpl(iq, rss, m)); 9016 } 9017 9018 static int 9019 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 9020 { 9021 int rc; 9022 9023 if (cntxt->cid > M_CTXTQID) 9024 return (EINVAL); 9025 9026 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 9027 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 9028 return (EINVAL); 9029 9030 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 9031 if (rc) 9032 return (rc); 9033 9034 if (sc->flags & FW_OK) { 9035 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 9036 &cntxt->data[0]); 9037 if (rc == 0) 9038 goto done; 9039 } 9040 9041 /* 9042 * Read via firmware failed or wasn't even attempted. Read directly via 9043 * the backdoor. 9044 */ 9045 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 9046 done: 9047 end_synchronized_op(sc, 0); 9048 return (rc); 9049 } 9050 9051 static int 9052 load_fw(struct adapter *sc, struct t4_data *fw) 9053 { 9054 int rc; 9055 uint8_t *fw_data; 9056 9057 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 9058 if (rc) 9059 return (rc); 9060 9061 /* 9062 * The firmware, with the sole exception of the memory parity error 9063 * handler, runs from memory and not flash. It is almost always safe to 9064 * install a new firmware on a running system. Just set bit 1 in 9065 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 9066 */ 9067 if (sc->flags & FULL_INIT_DONE && 9068 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 9069 rc = EBUSY; 9070 goto done; 9071 } 9072 9073 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9074 if (fw_data == NULL) { 9075 rc = ENOMEM; 9076 goto done; 9077 } 9078 9079 rc = copyin(fw->data, fw_data, fw->len); 9080 if (rc == 0) 9081 rc = -t4_load_fw(sc, fw_data, fw->len); 9082 9083 free(fw_data, M_CXGBE); 9084 done: 9085 end_synchronized_op(sc, 0); 9086 return (rc); 9087 } 9088 9089 static int 9090 load_cfg(struct adapter *sc, struct t4_data *cfg) 9091 { 9092 int rc; 9093 uint8_t *cfg_data = NULL; 9094 9095 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9096 if (rc) 9097 return (rc); 9098 9099 if (cfg->len == 0) { 9100 /* clear */ 9101 rc = -t4_load_cfg(sc, NULL, 0); 9102 goto done; 9103 } 9104 9105 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9106 if (cfg_data == NULL) { 9107 rc = ENOMEM; 9108 goto done; 9109 } 9110 9111 rc = copyin(cfg->data, cfg_data, cfg->len); 9112 if (rc == 0) 9113 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9114 9115 free(cfg_data, M_CXGBE); 9116 done: 9117 end_synchronized_op(sc, 0); 9118 return (rc); 9119 } 9120 9121 static int 9122 load_boot(struct adapter *sc, struct t4_bootrom *br) 9123 { 9124 int rc; 9125 uint8_t *br_data = NULL; 9126 u_int offset; 9127 9128 if (br->len > 1024 * 1024) 9129 return (EFBIG); 9130 9131 if (br->pf_offset == 0) { 9132 /* pfidx */ 9133 if (br->pfidx_addr > 7) 9134 return (EINVAL); 9135 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9136 A_PCIE_PF_EXPROM_OFST))); 9137 } else if (br->pf_offset == 1) { 9138 /* offset */ 9139 offset = G_OFFSET(br->pfidx_addr); 9140 } else { 9141 return (EINVAL); 9142 } 9143 9144 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9145 if (rc) 9146 return (rc); 9147 9148 if (br->len == 0) { 9149 /* clear */ 9150 rc = -t4_load_boot(sc, NULL, offset, 0); 9151 goto done; 9152 } 9153 9154 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9155 if (br_data == NULL) { 9156 rc = ENOMEM; 9157 goto done; 9158 } 9159 9160 rc = copyin(br->data, br_data, br->len); 9161 if (rc == 0) 9162 rc = -t4_load_boot(sc, br_data, offset, br->len); 9163 9164 free(br_data, M_CXGBE); 9165 done: 9166 end_synchronized_op(sc, 0); 9167 return (rc); 9168 } 9169 9170 static int 9171 load_bootcfg(struct adapter *sc, struct t4_data *bc) 9172 { 9173 int rc; 9174 uint8_t *bc_data = NULL; 9175 9176 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9177 if (rc) 9178 return (rc); 9179 9180 if (bc->len == 0) { 9181 /* clear */ 9182 rc = -t4_load_bootcfg(sc, NULL, 0); 9183 goto done; 9184 } 9185 9186 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9187 if (bc_data == NULL) { 9188 rc = ENOMEM; 9189 goto done; 9190 } 9191 9192 rc = copyin(bc->data, bc_data, bc->len); 9193 if (rc == 0) 9194 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9195 9196 free(bc_data, M_CXGBE); 9197 done: 9198 end_synchronized_op(sc, 0); 9199 return (rc); 9200 } 9201 9202 static int 9203 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9204 { 9205 int rc; 9206 struct cudbg_init *cudbg; 9207 void *handle, *buf; 9208 9209 /* buf is large, don't block if no memory is available */ 9210 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9211 if (buf == NULL) 9212 return (ENOMEM); 9213 9214 handle = cudbg_alloc_handle(); 9215 if (handle == NULL) { 9216 rc = ENOMEM; 9217 goto done; 9218 } 9219 9220 cudbg = cudbg_get_init(handle); 9221 cudbg->adap = sc; 9222 cudbg->print = (cudbg_print_cb)printf; 9223 9224 #ifndef notyet 9225 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9226 __func__, dump->wr_flash, dump->len, dump->data); 9227 #endif 9228 9229 if (dump->wr_flash) 9230 cudbg->use_flash = 1; 9231 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9232 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9233 9234 rc = cudbg_collect(handle, buf, &dump->len); 9235 if (rc != 0) 9236 goto done; 9237 9238 rc = copyout(buf, dump->data, dump->len); 9239 done: 9240 cudbg_free_handle(handle); 9241 free(buf, M_CXGBE); 9242 return (rc); 9243 } 9244 9245 #define MAX_READ_BUF_SIZE (128 * 1024) 9246 static int 9247 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9248 { 9249 uint32_t addr, remaining, n; 9250 uint32_t *buf; 9251 int rc; 9252 uint8_t *dst; 9253 9254 rc = validate_mem_range(sc, mr->addr, mr->len); 9255 if (rc != 0) 9256 return (rc); 9257 9258 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9259 addr = mr->addr; 9260 remaining = mr->len; 9261 dst = (void *)mr->data; 9262 9263 while (remaining) { 9264 n = min(remaining, MAX_READ_BUF_SIZE); 9265 read_via_memwin(sc, 2, addr, buf, n); 9266 9267 rc = copyout(buf, dst, n); 9268 if (rc != 0) 9269 break; 9270 9271 dst += n; 9272 remaining -= n; 9273 addr += n; 9274 } 9275 9276 free(buf, M_CXGBE); 9277 return (rc); 9278 } 9279 #undef MAX_READ_BUF_SIZE 9280 9281 static int 9282 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9283 { 9284 int rc; 9285 9286 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9287 return (EINVAL); 9288 9289 if (i2cd->len > sizeof(i2cd->data)) 9290 return (EFBIG); 9291 9292 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9293 if (rc) 9294 return (rc); 9295 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9296 i2cd->offset, i2cd->len, &i2cd->data[0]); 9297 end_synchronized_op(sc, 0); 9298 9299 return (rc); 9300 } 9301 9302 int 9303 t4_os_find_pci_capability(struct adapter *sc, int cap) 9304 { 9305 int i; 9306 9307 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9308 } 9309 9310 int 9311 t4_os_pci_save_state(struct adapter *sc) 9312 { 9313 device_t dev; 9314 struct pci_devinfo *dinfo; 9315 9316 dev = sc->dev; 9317 dinfo = device_get_ivars(dev); 9318 9319 pci_cfg_save(dev, dinfo, 0); 9320 return (0); 9321 } 9322 9323 int 9324 t4_os_pci_restore_state(struct adapter *sc) 9325 { 9326 device_t dev; 9327 struct pci_devinfo *dinfo; 9328 9329 dev = sc->dev; 9330 dinfo = device_get_ivars(dev); 9331 9332 pci_cfg_restore(dev, dinfo); 9333 return (0); 9334 } 9335 9336 void 9337 t4_os_portmod_changed(struct port_info *pi) 9338 { 9339 struct adapter *sc = pi->adapter; 9340 struct vi_info *vi; 9341 struct ifnet *ifp; 9342 static const char *mod_str[] = { 9343 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9344 }; 9345 9346 PORT_LOCK(pi); 9347 build_medialist(pi, &pi->media); 9348 PORT_UNLOCK(pi); 9349 vi = &pi->vi[0]; 9350 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9351 init_l1cfg(pi); 9352 end_synchronized_op(sc, LOCK_HELD); 9353 } 9354 9355 ifp = vi->ifp; 9356 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9357 if_printf(ifp, "transceiver unplugged.\n"); 9358 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9359 if_printf(ifp, "unknown transceiver inserted.\n"); 9360 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9361 if_printf(ifp, "unsupported transceiver inserted.\n"); 9362 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9363 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9364 port_top_speed(pi), mod_str[pi->mod_type]); 9365 } else { 9366 if_printf(ifp, "transceiver (type %d) inserted.\n", 9367 pi->mod_type); 9368 } 9369 } 9370 9371 void 9372 t4_os_link_changed(struct port_info *pi) 9373 { 9374 struct vi_info *vi; 9375 struct ifnet *ifp; 9376 struct link_config *lc; 9377 int v; 9378 9379 for_each_vi(pi, v, vi) { 9380 ifp = vi->ifp; 9381 if (ifp == NULL) 9382 continue; 9383 9384 lc = &pi->link_cfg; 9385 if (lc->link_ok) { 9386 ifp->if_baudrate = IF_Mbps(lc->speed); 9387 if_link_state_change(ifp, LINK_STATE_UP); 9388 } else { 9389 if_link_state_change(ifp, LINK_STATE_DOWN); 9390 } 9391 } 9392 } 9393 9394 void 9395 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9396 { 9397 struct adapter *sc; 9398 9399 sx_slock(&t4_list_lock); 9400 SLIST_FOREACH(sc, &t4_list, link) { 9401 /* 9402 * func should not make any assumptions about what state sc is 9403 * in - the only guarantee is that sc->sc_lock is a valid lock. 9404 */ 9405 func(sc, arg); 9406 } 9407 sx_sunlock(&t4_list_lock); 9408 } 9409 9410 static int 9411 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9412 struct thread *td) 9413 { 9414 int rc; 9415 struct adapter *sc = dev->si_drv1; 9416 9417 rc = priv_check(td, PRIV_DRIVER); 9418 if (rc != 0) 9419 return (rc); 9420 9421 switch (cmd) { 9422 case CHELSIO_T4_GETREG: { 9423 struct t4_reg *edata = (struct t4_reg *)data; 9424 9425 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9426 return (EFAULT); 9427 9428 if (edata->size == 4) 9429 edata->val = t4_read_reg(sc, edata->addr); 9430 else if (edata->size == 8) 9431 edata->val = t4_read_reg64(sc, edata->addr); 9432 else 9433 return (EINVAL); 9434 9435 break; 9436 } 9437 case CHELSIO_T4_SETREG: { 9438 struct t4_reg *edata = (struct t4_reg *)data; 9439 9440 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9441 return (EFAULT); 9442 9443 if (edata->size == 4) { 9444 if (edata->val & 0xffffffff00000000) 9445 return (EINVAL); 9446 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9447 } else if (edata->size == 8) 9448 t4_write_reg64(sc, edata->addr, edata->val); 9449 else 9450 return (EINVAL); 9451 break; 9452 } 9453 case CHELSIO_T4_REGDUMP: { 9454 struct t4_regdump *regs = (struct t4_regdump *)data; 9455 int reglen = t4_get_regs_len(sc); 9456 uint8_t *buf; 9457 9458 if (regs->len < reglen) { 9459 regs->len = reglen; /* hint to the caller */ 9460 return (ENOBUFS); 9461 } 9462 9463 regs->len = reglen; 9464 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9465 get_regs(sc, regs, buf); 9466 rc = copyout(buf, regs->data, reglen); 9467 free(buf, M_CXGBE); 9468 break; 9469 } 9470 case CHELSIO_T4_GET_FILTER_MODE: 9471 rc = get_filter_mode(sc, (uint32_t *)data); 9472 break; 9473 case CHELSIO_T4_SET_FILTER_MODE: 9474 rc = set_filter_mode(sc, *(uint32_t *)data); 9475 break; 9476 case CHELSIO_T4_GET_FILTER: 9477 rc = get_filter(sc, (struct t4_filter *)data); 9478 break; 9479 case CHELSIO_T4_SET_FILTER: 9480 rc = set_filter(sc, (struct t4_filter *)data); 9481 break; 9482 case CHELSIO_T4_DEL_FILTER: 9483 rc = del_filter(sc, (struct t4_filter *)data); 9484 break; 9485 case CHELSIO_T4_GET_SGE_CONTEXT: 9486 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9487 break; 9488 case CHELSIO_T4_LOAD_FW: 9489 rc = load_fw(sc, (struct t4_data *)data); 9490 break; 9491 case CHELSIO_T4_GET_MEM: 9492 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9493 break; 9494 case CHELSIO_T4_GET_I2C: 9495 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9496 break; 9497 case CHELSIO_T4_CLEAR_STATS: { 9498 int i, v; 9499 u_int port_id = *(uint32_t *)data; 9500 struct port_info *pi; 9501 struct vi_info *vi; 9502 9503 if (port_id >= sc->params.nports) 9504 return (EINVAL); 9505 pi = sc->port[port_id]; 9506 if (pi == NULL) 9507 return (EIO); 9508 9509 /* MAC stats */ 9510 t4_clr_port_stats(sc, pi->tx_chan); 9511 pi->tx_parse_error = 0; 9512 mtx_lock(&sc->reg_lock); 9513 for_each_vi(pi, v, vi) { 9514 if (vi->flags & VI_INIT_DONE) 9515 t4_clr_vi_stats(sc, vi->viid); 9516 } 9517 mtx_unlock(&sc->reg_lock); 9518 9519 /* 9520 * Since this command accepts a port, clear stats for 9521 * all VIs on this port. 9522 */ 9523 for_each_vi(pi, v, vi) { 9524 if (vi->flags & VI_INIT_DONE) { 9525 struct sge_rxq *rxq; 9526 struct sge_txq *txq; 9527 struct sge_wrq *wrq; 9528 9529 for_each_rxq(vi, i, rxq) { 9530 #if defined(INET) || defined(INET6) 9531 rxq->lro.lro_queued = 0; 9532 rxq->lro.lro_flushed = 0; 9533 #endif 9534 rxq->rxcsum = 0; 9535 rxq->vlan_extraction = 0; 9536 } 9537 9538 for_each_txq(vi, i, txq) { 9539 txq->txcsum = 0; 9540 txq->tso_wrs = 0; 9541 txq->vlan_insertion = 0; 9542 txq->imm_wrs = 0; 9543 txq->sgl_wrs = 0; 9544 txq->txpkt_wrs = 0; 9545 txq->txpkts0_wrs = 0; 9546 txq->txpkts1_wrs = 0; 9547 txq->txpkts0_pkts = 0; 9548 txq->txpkts1_pkts = 0; 9549 mp_ring_reset_stats(txq->r); 9550 } 9551 9552 #ifdef TCP_OFFLOAD 9553 /* nothing to clear for each ofld_rxq */ 9554 9555 for_each_ofld_txq(vi, i, wrq) { 9556 wrq->tx_wrs_direct = 0; 9557 wrq->tx_wrs_copied = 0; 9558 } 9559 #endif 9560 9561 if (IS_MAIN_VI(vi)) { 9562 wrq = &sc->sge.ctrlq[pi->port_id]; 9563 wrq->tx_wrs_direct = 0; 9564 wrq->tx_wrs_copied = 0; 9565 } 9566 } 9567 } 9568 break; 9569 } 9570 case CHELSIO_T4_SCHED_CLASS: 9571 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9572 break; 9573 case CHELSIO_T4_SCHED_QUEUE: 9574 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9575 break; 9576 case CHELSIO_T4_GET_TRACER: 9577 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9578 break; 9579 case CHELSIO_T4_SET_TRACER: 9580 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9581 break; 9582 case CHELSIO_T4_LOAD_CFG: 9583 rc = load_cfg(sc, (struct t4_data *)data); 9584 break; 9585 case CHELSIO_T4_LOAD_BOOT: 9586 rc = load_boot(sc, (struct t4_bootrom *)data); 9587 break; 9588 case CHELSIO_T4_LOAD_BOOTCFG: 9589 rc = load_bootcfg(sc, (struct t4_data *)data); 9590 break; 9591 case CHELSIO_T4_CUDBG_DUMP: 9592 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 9593 break; 9594 default: 9595 rc = ENOTTY; 9596 } 9597 9598 return (rc); 9599 } 9600 9601 void 9602 t4_db_full(struct adapter *sc) 9603 { 9604 9605 CXGBE_UNIMPLEMENTED(__func__); 9606 } 9607 9608 void 9609 t4_db_dropped(struct adapter *sc) 9610 { 9611 9612 CXGBE_UNIMPLEMENTED(__func__); 9613 } 9614 9615 #ifdef TCP_OFFLOAD 9616 static int 9617 toe_capability(struct vi_info *vi, int enable) 9618 { 9619 int rc; 9620 struct port_info *pi = vi->pi; 9621 struct adapter *sc = pi->adapter; 9622 9623 ASSERT_SYNCHRONIZED_OP(sc); 9624 9625 if (!is_offload(sc)) 9626 return (ENODEV); 9627 9628 if (enable) { 9629 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9630 /* TOE is already enabled. */ 9631 return (0); 9632 } 9633 9634 /* 9635 * We need the port's queues around so that we're able to send 9636 * and receive CPLs to/from the TOE even if the ifnet for this 9637 * port has never been UP'd administratively. 9638 */ 9639 if (!(vi->flags & VI_INIT_DONE)) { 9640 rc = vi_full_init(vi); 9641 if (rc) 9642 return (rc); 9643 } 9644 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9645 rc = vi_full_init(&pi->vi[0]); 9646 if (rc) 9647 return (rc); 9648 } 9649 9650 if (isset(&sc->offload_map, pi->port_id)) { 9651 /* TOE is enabled on another VI of this port. */ 9652 pi->uld_vis++; 9653 return (0); 9654 } 9655 9656 if (!uld_active(sc, ULD_TOM)) { 9657 rc = t4_activate_uld(sc, ULD_TOM); 9658 if (rc == EAGAIN) { 9659 log(LOG_WARNING, 9660 "You must kldload t4_tom.ko before trying " 9661 "to enable TOE on a cxgbe interface.\n"); 9662 } 9663 if (rc != 0) 9664 return (rc); 9665 KASSERT(sc->tom_softc != NULL, 9666 ("%s: TOM activated but softc NULL", __func__)); 9667 KASSERT(uld_active(sc, ULD_TOM), 9668 ("%s: TOM activated but flag not set", __func__)); 9669 } 9670 9671 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9672 if (!uld_active(sc, ULD_IWARP)) 9673 (void) t4_activate_uld(sc, ULD_IWARP); 9674 if (!uld_active(sc, ULD_ISCSI)) 9675 (void) t4_activate_uld(sc, ULD_ISCSI); 9676 9677 pi->uld_vis++; 9678 setbit(&sc->offload_map, pi->port_id); 9679 } else { 9680 pi->uld_vis--; 9681 9682 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9683 return (0); 9684 9685 KASSERT(uld_active(sc, ULD_TOM), 9686 ("%s: TOM never initialized?", __func__)); 9687 clrbit(&sc->offload_map, pi->port_id); 9688 } 9689 9690 return (0); 9691 } 9692 9693 /* 9694 * Add an upper layer driver to the global list. 9695 */ 9696 int 9697 t4_register_uld(struct uld_info *ui) 9698 { 9699 int rc = 0; 9700 struct uld_info *u; 9701 9702 sx_xlock(&t4_uld_list_lock); 9703 SLIST_FOREACH(u, &t4_uld_list, link) { 9704 if (u->uld_id == ui->uld_id) { 9705 rc = EEXIST; 9706 goto done; 9707 } 9708 } 9709 9710 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9711 ui->refcount = 0; 9712 done: 9713 sx_xunlock(&t4_uld_list_lock); 9714 return (rc); 9715 } 9716 9717 int 9718 t4_unregister_uld(struct uld_info *ui) 9719 { 9720 int rc = EINVAL; 9721 struct uld_info *u; 9722 9723 sx_xlock(&t4_uld_list_lock); 9724 9725 SLIST_FOREACH(u, &t4_uld_list, link) { 9726 if (u == ui) { 9727 if (ui->refcount > 0) { 9728 rc = EBUSY; 9729 goto done; 9730 } 9731 9732 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 9733 rc = 0; 9734 goto done; 9735 } 9736 } 9737 done: 9738 sx_xunlock(&t4_uld_list_lock); 9739 return (rc); 9740 } 9741 9742 int 9743 t4_activate_uld(struct adapter *sc, int id) 9744 { 9745 int rc; 9746 struct uld_info *ui; 9747 9748 ASSERT_SYNCHRONIZED_OP(sc); 9749 9750 if (id < 0 || id > ULD_MAX) 9751 return (EINVAL); 9752 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 9753 9754 sx_slock(&t4_uld_list_lock); 9755 9756 SLIST_FOREACH(ui, &t4_uld_list, link) { 9757 if (ui->uld_id == id) { 9758 if (!(sc->flags & FULL_INIT_DONE)) { 9759 rc = adapter_full_init(sc); 9760 if (rc != 0) 9761 break; 9762 } 9763 9764 rc = ui->activate(sc); 9765 if (rc == 0) { 9766 setbit(&sc->active_ulds, id); 9767 ui->refcount++; 9768 } 9769 break; 9770 } 9771 } 9772 9773 sx_sunlock(&t4_uld_list_lock); 9774 9775 return (rc); 9776 } 9777 9778 int 9779 t4_deactivate_uld(struct adapter *sc, int id) 9780 { 9781 int rc; 9782 struct uld_info *ui; 9783 9784 ASSERT_SYNCHRONIZED_OP(sc); 9785 9786 if (id < 0 || id > ULD_MAX) 9787 return (EINVAL); 9788 rc = ENXIO; 9789 9790 sx_slock(&t4_uld_list_lock); 9791 9792 SLIST_FOREACH(ui, &t4_uld_list, link) { 9793 if (ui->uld_id == id) { 9794 rc = ui->deactivate(sc); 9795 if (rc == 0) { 9796 clrbit(&sc->active_ulds, id); 9797 ui->refcount--; 9798 } 9799 break; 9800 } 9801 } 9802 9803 sx_sunlock(&t4_uld_list_lock); 9804 9805 return (rc); 9806 } 9807 9808 int 9809 uld_active(struct adapter *sc, int uld_id) 9810 { 9811 9812 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 9813 9814 return (isset(&sc->active_ulds, uld_id)); 9815 } 9816 #endif 9817 9818 /* 9819 * t = ptr to tunable. 9820 * nc = number of CPUs. 9821 * c = compiled in default for that tunable. 9822 */ 9823 static void 9824 calculate_nqueues(int *t, int nc, const int c) 9825 { 9826 int nq; 9827 9828 if (*t > 0) 9829 return; 9830 nq = *t < 0 ? -*t : c; 9831 *t = min(nc, nq); 9832 } 9833 9834 /* 9835 * Come up with reasonable defaults for some of the tunables, provided they're 9836 * not set by the user (in which case we'll use the values as is). 9837 */ 9838 static void 9839 tweak_tunables(void) 9840 { 9841 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 9842 9843 if (t4_ntxq < 1) { 9844 #ifdef RSS 9845 t4_ntxq = rss_getnumbuckets(); 9846 #else 9847 calculate_nqueues(&t4_ntxq, nc, NTXQ); 9848 #endif 9849 } 9850 9851 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 9852 9853 if (t4_nrxq < 1) { 9854 #ifdef RSS 9855 t4_nrxq = rss_getnumbuckets(); 9856 #else 9857 calculate_nqueues(&t4_nrxq, nc, NRXQ); 9858 #endif 9859 } 9860 9861 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 9862 9863 #ifdef TCP_OFFLOAD 9864 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 9865 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 9866 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 9867 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 9868 9869 if (t4_toecaps_allowed == -1) 9870 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 9871 9872 if (t4_rdmacaps_allowed == -1) { 9873 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 9874 FW_CAPS_CONFIG_RDMA_RDMAC; 9875 } 9876 9877 if (t4_iscsicaps_allowed == -1) { 9878 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 9879 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 9880 FW_CAPS_CONFIG_ISCSI_T10DIF; 9881 } 9882 9883 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 9884 t4_tmr_idx_ofld = TMR_IDX_OFLD; 9885 9886 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 9887 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 9888 #else 9889 if (t4_toecaps_allowed == -1) 9890 t4_toecaps_allowed = 0; 9891 9892 if (t4_rdmacaps_allowed == -1) 9893 t4_rdmacaps_allowed = 0; 9894 9895 if (t4_iscsicaps_allowed == -1) 9896 t4_iscsicaps_allowed = 0; 9897 #endif 9898 9899 #ifdef DEV_NETMAP 9900 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 9901 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 9902 #endif 9903 9904 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 9905 t4_tmr_idx = TMR_IDX; 9906 9907 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 9908 t4_pktc_idx = PKTC_IDX; 9909 9910 if (t4_qsize_txq < 128) 9911 t4_qsize_txq = 128; 9912 9913 if (t4_qsize_rxq < 128) 9914 t4_qsize_rxq = 128; 9915 while (t4_qsize_rxq & 7) 9916 t4_qsize_rxq++; 9917 9918 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 9919 9920 /* 9921 * Number of VIs to create per-port. The first VI is the "main" regular 9922 * VI for the port. The rest are additional virtual interfaces on the 9923 * same physical port. Note that the main VI does not have native 9924 * netmap support but the extra VIs do. 9925 * 9926 * Limit the number of VIs per port to the number of available 9927 * MAC addresses per port. 9928 */ 9929 if (t4_num_vis < 1) 9930 t4_num_vis = 1; 9931 if (t4_num_vis > nitems(vi_mac_funcs)) { 9932 t4_num_vis = nitems(vi_mac_funcs); 9933 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 9934 } 9935 } 9936 9937 #ifdef DDB 9938 static void 9939 t4_dump_tcb(struct adapter *sc, int tid) 9940 { 9941 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 9942 9943 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 9944 save = t4_read_reg(sc, reg); 9945 base = sc->memwin[2].mw_base; 9946 9947 /* Dump TCB for the tid */ 9948 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9949 tcb_addr += tid * TCB_SIZE; 9950 9951 if (is_t4(sc)) { 9952 pf = 0; 9953 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 9954 } else { 9955 pf = V_PFNUM(sc->pf); 9956 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 9957 } 9958 t4_write_reg(sc, reg, win_pos | pf); 9959 t4_read_reg(sc, reg); 9960 9961 off = tcb_addr - win_pos; 9962 for (i = 0; i < 4; i++) { 9963 uint32_t buf[8]; 9964 for (j = 0; j < 8; j++, off += 4) 9965 buf[j] = htonl(t4_read_reg(sc, base + off)); 9966 9967 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 9968 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 9969 buf[7]); 9970 } 9971 9972 t4_write_reg(sc, reg, save); 9973 t4_read_reg(sc, reg); 9974 } 9975 9976 static void 9977 t4_dump_devlog(struct adapter *sc) 9978 { 9979 struct devlog_params *dparams = &sc->params.devlog; 9980 struct fw_devlog_e e; 9981 int i, first, j, m, nentries, rc; 9982 uint64_t ftstamp = UINT64_MAX; 9983 9984 if (dparams->start == 0) { 9985 db_printf("devlog params not valid\n"); 9986 return; 9987 } 9988 9989 nentries = dparams->size / sizeof(struct fw_devlog_e); 9990 m = fwmtype_to_hwmtype(dparams->memtype); 9991 9992 /* Find the first entry. */ 9993 first = -1; 9994 for (i = 0; i < nentries && !db_pager_quit; i++) { 9995 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9996 sizeof(e), (void *)&e); 9997 if (rc != 0) 9998 break; 9999 10000 if (e.timestamp == 0) 10001 break; 10002 10003 e.timestamp = be64toh(e.timestamp); 10004 if (e.timestamp < ftstamp) { 10005 ftstamp = e.timestamp; 10006 first = i; 10007 } 10008 } 10009 10010 if (first == -1) 10011 return; 10012 10013 i = first; 10014 do { 10015 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10016 sizeof(e), (void *)&e); 10017 if (rc != 0) 10018 return; 10019 10020 if (e.timestamp == 0) 10021 return; 10022 10023 e.timestamp = be64toh(e.timestamp); 10024 e.seqno = be32toh(e.seqno); 10025 for (j = 0; j < 8; j++) 10026 e.params[j] = be32toh(e.params[j]); 10027 10028 db_printf("%10d %15ju %8s %8s ", 10029 e.seqno, e.timestamp, 10030 (e.level < nitems(devlog_level_strings) ? 10031 devlog_level_strings[e.level] : "UNKNOWN"), 10032 (e.facility < nitems(devlog_facility_strings) ? 10033 devlog_facility_strings[e.facility] : "UNKNOWN")); 10034 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10035 e.params[3], e.params[4], e.params[5], e.params[6], 10036 e.params[7]); 10037 10038 if (++i == nentries) 10039 i = 0; 10040 } while (i != first && !db_pager_quit); 10041 } 10042 10043 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10044 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10045 10046 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10047 { 10048 device_t dev; 10049 int t; 10050 bool valid; 10051 10052 valid = false; 10053 t = db_read_token(); 10054 if (t == tIDENT) { 10055 dev = device_lookup_by_name(db_tok_string); 10056 valid = true; 10057 } 10058 db_skip_to_eol(); 10059 if (!valid) { 10060 db_printf("usage: show t4 devlog <nexus>\n"); 10061 return; 10062 } 10063 10064 if (dev == NULL) { 10065 db_printf("device not found\n"); 10066 return; 10067 } 10068 10069 t4_dump_devlog(device_get_softc(dev)); 10070 } 10071 10072 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10073 { 10074 device_t dev; 10075 int radix, tid, t; 10076 bool valid; 10077 10078 valid = false; 10079 radix = db_radix; 10080 db_radix = 10; 10081 t = db_read_token(); 10082 if (t == tIDENT) { 10083 dev = device_lookup_by_name(db_tok_string); 10084 t = db_read_token(); 10085 if (t == tNUMBER) { 10086 tid = db_tok_number; 10087 valid = true; 10088 } 10089 } 10090 db_radix = radix; 10091 db_skip_to_eol(); 10092 if (!valid) { 10093 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10094 return; 10095 } 10096 10097 if (dev == NULL) { 10098 db_printf("device not found\n"); 10099 return; 10100 } 10101 if (tid < 0) { 10102 db_printf("invalid tid\n"); 10103 return; 10104 } 10105 10106 t4_dump_tcb(device_get_softc(dev), tid); 10107 } 10108 #endif 10109 10110 static struct sx mlu; /* mod load unload */ 10111 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10112 10113 static int 10114 mod_event(module_t mod, int cmd, void *arg) 10115 { 10116 int rc = 0; 10117 static int loaded = 0; 10118 10119 switch (cmd) { 10120 case MOD_LOAD: 10121 sx_xlock(&mlu); 10122 if (loaded++ == 0) { 10123 t4_sge_modload(); 10124 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl); 10125 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl); 10126 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10127 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10128 sx_init(&t4_list_lock, "T4/T5 adapters"); 10129 SLIST_INIT(&t4_list); 10130 #ifdef TCP_OFFLOAD 10131 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10132 SLIST_INIT(&t4_uld_list); 10133 #endif 10134 t4_tracer_modload(); 10135 tweak_tunables(); 10136 } 10137 sx_xunlock(&mlu); 10138 break; 10139 10140 case MOD_UNLOAD: 10141 sx_xlock(&mlu); 10142 if (--loaded == 0) { 10143 int tries; 10144 10145 sx_slock(&t4_list_lock); 10146 if (!SLIST_EMPTY(&t4_list)) { 10147 rc = EBUSY; 10148 sx_sunlock(&t4_list_lock); 10149 goto done_unload; 10150 } 10151 #ifdef TCP_OFFLOAD 10152 sx_slock(&t4_uld_list_lock); 10153 if (!SLIST_EMPTY(&t4_uld_list)) { 10154 rc = EBUSY; 10155 sx_sunlock(&t4_uld_list_lock); 10156 sx_sunlock(&t4_list_lock); 10157 goto done_unload; 10158 } 10159 #endif 10160 tries = 0; 10161 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10162 uprintf("%ju clusters with custom free routine " 10163 "still is use.\n", t4_sge_extfree_refs()); 10164 pause("t4unload", 2 * hz); 10165 } 10166 #ifdef TCP_OFFLOAD 10167 sx_sunlock(&t4_uld_list_lock); 10168 #endif 10169 sx_sunlock(&t4_list_lock); 10170 10171 if (t4_sge_extfree_refs() == 0) { 10172 t4_tracer_modunload(); 10173 #ifdef TCP_OFFLOAD 10174 sx_destroy(&t4_uld_list_lock); 10175 #endif 10176 sx_destroy(&t4_list_lock); 10177 t4_sge_modunload(); 10178 loaded = 0; 10179 } else { 10180 rc = EBUSY; 10181 loaded++; /* undo earlier decrement */ 10182 } 10183 } 10184 done_unload: 10185 sx_xunlock(&mlu); 10186 break; 10187 } 10188 10189 return (rc); 10190 } 10191 10192 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10193 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10194 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10195 10196 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10197 MODULE_VERSION(t4nex, 1); 10198 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10199 #ifdef DEV_NETMAP 10200 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10201 #endif /* DEV_NETMAP */ 10202 10203 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10204 MODULE_VERSION(t5nex, 1); 10205 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10206 #ifdef DEV_NETMAP 10207 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10208 #endif /* DEV_NETMAP */ 10209 10210 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10211 MODULE_VERSION(t6nex, 1); 10212 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10213 #ifdef DEV_NETMAP 10214 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10215 #endif /* DEV_NETMAP */ 10216 10217 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10218 MODULE_VERSION(cxgbe, 1); 10219 10220 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10221 MODULE_VERSION(cxl, 1); 10222 10223 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10224 MODULE_VERSION(cc, 1); 10225 10226 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10227 MODULE_VERSION(vcxgbe, 1); 10228 10229 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10230 MODULE_VERSION(vcxl, 1); 10231 10232 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10233 MODULE_VERSION(vcc, 1); 10234