1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_ratelimit.h" 37 #include "opt_rss.h" 38 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/priv.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #if defined(__i386__) || defined(__amd64__) 67 #include <machine/md_var.h> 68 #include <machine/cputypes.h> 69 #include <vm/vm.h> 70 #include <vm/pmap.h> 71 #endif 72 #include <crypto/rijndael/rijndael.h> 73 #ifdef DDB 74 #include <ddb/ddb.h> 75 #include <ddb/db_lex.h> 76 #endif 77 78 #include "common/common.h" 79 #include "common/t4_msg.h" 80 #include "common/t4_regs.h" 81 #include "common/t4_regs_values.h" 82 #include "cudbg/cudbg.h" 83 #include "t4_ioctl.h" 84 #include "t4_l2t.h" 85 #include "t4_mp_ring.h" 86 #include "t4_if.h" 87 #include "t4_smt.h" 88 89 /* T4 bus driver interface */ 90 static int t4_probe(device_t); 91 static int t4_attach(device_t); 92 static int t4_detach(device_t); 93 static int t4_ready(device_t); 94 static int t4_read_port_device(device_t, int, device_t *); 95 static device_method_t t4_methods[] = { 96 DEVMETHOD(device_probe, t4_probe), 97 DEVMETHOD(device_attach, t4_attach), 98 DEVMETHOD(device_detach, t4_detach), 99 100 DEVMETHOD(t4_is_main_ready, t4_ready), 101 DEVMETHOD(t4_read_port_device, t4_read_port_device), 102 103 DEVMETHOD_END 104 }; 105 static driver_t t4_driver = { 106 "t4nex", 107 t4_methods, 108 sizeof(struct adapter) 109 }; 110 111 112 /* T4 port (cxgbe) interface */ 113 static int cxgbe_probe(device_t); 114 static int cxgbe_attach(device_t); 115 static int cxgbe_detach(device_t); 116 device_method_t cxgbe_methods[] = { 117 DEVMETHOD(device_probe, cxgbe_probe), 118 DEVMETHOD(device_attach, cxgbe_attach), 119 DEVMETHOD(device_detach, cxgbe_detach), 120 { 0, 0 } 121 }; 122 static driver_t cxgbe_driver = { 123 "cxgbe", 124 cxgbe_methods, 125 sizeof(struct port_info) 126 }; 127 128 /* T4 VI (vcxgbe) interface */ 129 static int vcxgbe_probe(device_t); 130 static int vcxgbe_attach(device_t); 131 static int vcxgbe_detach(device_t); 132 static device_method_t vcxgbe_methods[] = { 133 DEVMETHOD(device_probe, vcxgbe_probe), 134 DEVMETHOD(device_attach, vcxgbe_attach), 135 DEVMETHOD(device_detach, vcxgbe_detach), 136 { 0, 0 } 137 }; 138 static driver_t vcxgbe_driver = { 139 "vcxgbe", 140 vcxgbe_methods, 141 sizeof(struct vi_info) 142 }; 143 144 static d_ioctl_t t4_ioctl; 145 146 static struct cdevsw t4_cdevsw = { 147 .d_version = D_VERSION, 148 .d_ioctl = t4_ioctl, 149 .d_name = "t4nex", 150 }; 151 152 /* T5 bus driver interface */ 153 static int t5_probe(device_t); 154 static device_method_t t5_methods[] = { 155 DEVMETHOD(device_probe, t5_probe), 156 DEVMETHOD(device_attach, t4_attach), 157 DEVMETHOD(device_detach, t4_detach), 158 159 DEVMETHOD(t4_is_main_ready, t4_ready), 160 DEVMETHOD(t4_read_port_device, t4_read_port_device), 161 162 DEVMETHOD_END 163 }; 164 static driver_t t5_driver = { 165 "t5nex", 166 t5_methods, 167 sizeof(struct adapter) 168 }; 169 170 171 /* T5 port (cxl) interface */ 172 static driver_t cxl_driver = { 173 "cxl", 174 cxgbe_methods, 175 sizeof(struct port_info) 176 }; 177 178 /* T5 VI (vcxl) interface */ 179 static driver_t vcxl_driver = { 180 "vcxl", 181 vcxgbe_methods, 182 sizeof(struct vi_info) 183 }; 184 185 /* T6 bus driver interface */ 186 static int t6_probe(device_t); 187 static device_method_t t6_methods[] = { 188 DEVMETHOD(device_probe, t6_probe), 189 DEVMETHOD(device_attach, t4_attach), 190 DEVMETHOD(device_detach, t4_detach), 191 192 DEVMETHOD(t4_is_main_ready, t4_ready), 193 DEVMETHOD(t4_read_port_device, t4_read_port_device), 194 195 DEVMETHOD_END 196 }; 197 static driver_t t6_driver = { 198 "t6nex", 199 t6_methods, 200 sizeof(struct adapter) 201 }; 202 203 204 /* T6 port (cc) interface */ 205 static driver_t cc_driver = { 206 "cc", 207 cxgbe_methods, 208 sizeof(struct port_info) 209 }; 210 211 /* T6 VI (vcc) interface */ 212 static driver_t vcc_driver = { 213 "vcc", 214 vcxgbe_methods, 215 sizeof(struct vi_info) 216 }; 217 218 /* ifnet + media interface */ 219 static void cxgbe_init(void *); 220 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 221 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 222 static void cxgbe_qflush(struct ifnet *); 223 static int cxgbe_media_change(struct ifnet *); 224 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 225 226 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 227 228 /* 229 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 230 * then ADAPTER_LOCK, then t4_uld_list_lock. 231 */ 232 static struct sx t4_list_lock; 233 SLIST_HEAD(, adapter) t4_list; 234 #ifdef TCP_OFFLOAD 235 static struct sx t4_uld_list_lock; 236 SLIST_HEAD(, uld_info) t4_uld_list; 237 #endif 238 239 /* 240 * Tunables. See tweak_tunables() too. 241 * 242 * Each tunable is set to a default value here if it's known at compile-time. 243 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 244 * provide a reasonable default (upto n) when the driver is loaded. 245 * 246 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 247 * T5 are under hw.cxl. 248 */ 249 250 /* 251 * Number of queues for tx and rx, NIC and offload. 252 */ 253 #define NTXQ 16 254 int t4_ntxq = -NTXQ; 255 TUNABLE_INT("hw.cxgbe.ntxq", &t4_ntxq); 256 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 257 258 #define NRXQ 8 259 int t4_nrxq = -NRXQ; 260 TUNABLE_INT("hw.cxgbe.nrxq", &t4_nrxq); 261 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 262 263 #define NTXQ_VI 1 264 static int t4_ntxq_vi = -NTXQ_VI; 265 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi); 266 267 #define NRXQ_VI 1 268 static int t4_nrxq_vi = -NRXQ_VI; 269 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi); 270 271 static int t4_rsrv_noflowq = 0; 272 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq); 273 274 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 275 #define NOFLDTXQ 8 276 static int t4_nofldtxq = -NOFLDTXQ; 277 TUNABLE_INT("hw.cxgbe.nofldtxq", &t4_nofldtxq); 278 279 #define NOFLDRXQ 2 280 static int t4_nofldrxq = -NOFLDRXQ; 281 TUNABLE_INT("hw.cxgbe.nofldrxq", &t4_nofldrxq); 282 283 #define NOFLDTXQ_VI 1 284 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 285 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi); 286 287 #define NOFLDRXQ_VI 1 288 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 289 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi); 290 291 #define TMR_IDX_OFLD 1 292 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 293 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_ofld", &t4_tmr_idx_ofld); 294 295 #define PKTC_IDX_OFLD (-1) 296 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 297 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_ofld", &t4_pktc_idx_ofld); 298 299 /* 0 means chip/fw default, non-zero number is value in microseconds */ 300 static u_long t4_toe_keepalive_idle = 0; 301 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_idle", &t4_toe_keepalive_idle); 302 303 /* 0 means chip/fw default, non-zero number is value in microseconds */ 304 static u_long t4_toe_keepalive_interval = 0; 305 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_interval", &t4_toe_keepalive_interval); 306 307 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 308 static int t4_toe_keepalive_count = 0; 309 TUNABLE_INT("hw.cxgbe.toe.keepalive_count", &t4_toe_keepalive_count); 310 311 /* 0 means chip/fw default, non-zero number is value in microseconds */ 312 static u_long t4_toe_rexmt_min = 0; 313 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_min", &t4_toe_rexmt_min); 314 315 /* 0 means chip/fw default, non-zero number is value in microseconds */ 316 static u_long t4_toe_rexmt_max = 0; 317 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_max", &t4_toe_rexmt_max); 318 319 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 320 static int t4_toe_rexmt_count = 0; 321 TUNABLE_INT("hw.cxgbe.toe.rexmt_count", &t4_toe_rexmt_count); 322 323 /* -1 means chip/fw default, other values are raw backoff values to use */ 324 static int t4_toe_rexmt_backoff[16] = { 325 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 326 }; 327 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.0", &t4_toe_rexmt_backoff[0]); 328 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.1", &t4_toe_rexmt_backoff[1]); 329 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.2", &t4_toe_rexmt_backoff[2]); 330 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.3", &t4_toe_rexmt_backoff[3]); 331 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.4", &t4_toe_rexmt_backoff[4]); 332 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.5", &t4_toe_rexmt_backoff[5]); 333 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.6", &t4_toe_rexmt_backoff[6]); 334 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.7", &t4_toe_rexmt_backoff[7]); 335 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.8", &t4_toe_rexmt_backoff[8]); 336 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.9", &t4_toe_rexmt_backoff[9]); 337 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.10", &t4_toe_rexmt_backoff[10]); 338 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.11", &t4_toe_rexmt_backoff[11]); 339 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.12", &t4_toe_rexmt_backoff[12]); 340 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.13", &t4_toe_rexmt_backoff[13]); 341 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.14", &t4_toe_rexmt_backoff[14]); 342 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.15", &t4_toe_rexmt_backoff[15]); 343 #endif 344 345 #ifdef DEV_NETMAP 346 #define NNMTXQ_VI 2 347 static int t4_nnmtxq_vi = -NNMTXQ_VI; 348 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi); 349 350 #define NNMRXQ_VI 2 351 static int t4_nnmrxq_vi = -NNMRXQ_VI; 352 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi); 353 #endif 354 355 /* 356 * Holdoff parameters for ports. 357 */ 358 #define TMR_IDX 1 359 int t4_tmr_idx = TMR_IDX; 360 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx", &t4_tmr_idx); 361 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 362 363 #define PKTC_IDX (-1) 364 int t4_pktc_idx = PKTC_IDX; 365 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx", &t4_pktc_idx); 366 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 367 368 /* 369 * Size (# of entries) of each tx and rx queue. 370 */ 371 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 372 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 373 374 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 375 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 376 377 /* 378 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 379 */ 380 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 381 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 382 383 /* 384 * Configuration file. All the _CF names here are special. 385 */ 386 #define DEFAULT_CF "default" 387 #define BUILTIN_CF "built-in" 388 #define FLASH_CF "flash" 389 #define UWIRE_CF "uwire" 390 #define FPGA_CF "fpga" 391 static char t4_cfg_file[32] = DEFAULT_CF; 392 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 393 394 /* 395 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively). 396 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 397 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 398 * mark or when signalled to do so, 0 to never emit PAUSE. 399 */ 400 static int t4_pause_settings = PAUSE_TX | PAUSE_RX; 401 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings); 402 403 /* 404 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS, 405 * FEC_RESERVED respectively). 406 * -1 to run with the firmware default. 407 * 0 to disable FEC. 408 */ 409 static int t4_fec = -1; 410 TUNABLE_INT("hw.cxgbe.fec", &t4_fec); 411 412 /* 413 * Link autonegotiation. 414 * -1 to run with the firmware default. 415 * 0 to disable. 416 * 1 to enable. 417 */ 418 static int t4_autoneg = -1; 419 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg); 420 421 /* 422 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 423 * encouraged respectively). 424 */ 425 static unsigned int t4_fw_install = 1; 426 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 427 428 /* 429 * ASIC features that will be used. Disable the ones you don't want so that the 430 * chip resources aren't wasted on features that will not be used. 431 */ 432 static int t4_nbmcaps_allowed = 0; 433 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed); 434 435 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 436 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 437 438 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 439 FW_CAPS_CONFIG_SWITCH_EGRESS; 440 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed); 441 442 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 443 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 444 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 445 446 static int t4_toecaps_allowed = -1; 447 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 448 449 static int t4_rdmacaps_allowed = -1; 450 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 451 452 static int t4_cryptocaps_allowed = -1; 453 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed); 454 455 static int t4_iscsicaps_allowed = -1; 456 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 457 458 static int t4_fcoecaps_allowed = 0; 459 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 460 461 static int t5_write_combine = 0; 462 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 463 464 static int t4_num_vis = 1; 465 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis); 466 /* 467 * PCIe Relaxed Ordering. 468 * -1: driver should figure out a good value. 469 * 0: disable RO. 470 * 1: enable RO. 471 * 2: leave RO alone. 472 */ 473 static int pcie_relaxed_ordering = -1; 474 TUNABLE_INT("hw.cxgbe.pcie_relaxed_ordering", &pcie_relaxed_ordering); 475 476 static int t4_panic_on_fatal_err = 0; 477 TUNABLE_INT("hw.cxgbe.panic_on_fatal_err", &t4_panic_on_fatal_err); 478 479 #ifdef TCP_OFFLOAD 480 /* 481 * TOE tunables. 482 */ 483 static int t4_cop_managed_offloading = 0; 484 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading); 485 #endif 486 487 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 488 static int vi_mac_funcs[] = { 489 FW_VI_FUNC_ETH, 490 FW_VI_FUNC_OFLD, 491 FW_VI_FUNC_IWARP, 492 FW_VI_FUNC_OPENISCSI, 493 FW_VI_FUNC_OPENFCOE, 494 FW_VI_FUNC_FOISCSI, 495 FW_VI_FUNC_FOFCOE, 496 }; 497 498 struct intrs_and_queues { 499 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 500 uint16_t num_vis; /* number of VIs for each port */ 501 uint16_t nirq; /* Total # of vectors */ 502 uint16_t ntxq; /* # of NIC txq's for each port */ 503 uint16_t nrxq; /* # of NIC rxq's for each port */ 504 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 505 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 506 507 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 508 uint16_t ntxq_vi; /* # of NIC txq's */ 509 uint16_t nrxq_vi; /* # of NIC rxq's */ 510 uint16_t nofldtxq_vi; /* # of TOE txq's */ 511 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 512 uint16_t nnmtxq_vi; /* # of netmap txq's */ 513 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 514 }; 515 516 static void setup_memwin(struct adapter *); 517 static void position_memwin(struct adapter *, int, uint32_t); 518 static int validate_mem_range(struct adapter *, uint32_t, int); 519 static int fwmtype_to_hwmtype(int); 520 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 521 uint32_t *); 522 static int fixup_devlog_params(struct adapter *); 523 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 524 static int prep_firmware(struct adapter *); 525 static int partition_resources(struct adapter *, const struct firmware *, 526 const char *); 527 static int get_params__pre_init(struct adapter *); 528 static int get_params__post_init(struct adapter *); 529 static int set_params__post_init(struct adapter *); 530 static void t4_set_desc(struct adapter *); 531 static void build_medialist(struct port_info *, struct ifmedia *); 532 static void init_l1cfg(struct port_info *); 533 static int apply_l1cfg(struct port_info *); 534 static int cxgbe_init_synchronized(struct vi_info *); 535 static int cxgbe_uninit_synchronized(struct vi_info *); 536 static void quiesce_txq(struct adapter *, struct sge_txq *); 537 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 538 static void quiesce_iq(struct adapter *, struct sge_iq *); 539 static void quiesce_fl(struct adapter *, struct sge_fl *); 540 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 541 driver_intr_t *, void *, char *); 542 static int t4_free_irq(struct adapter *, struct irq *); 543 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 544 static void vi_refresh_stats(struct adapter *, struct vi_info *); 545 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 546 static void cxgbe_tick(void *); 547 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 548 static void cxgbe_sysctls(struct port_info *); 549 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 550 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 551 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 552 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 553 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 554 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 555 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 556 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 557 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 558 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 559 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 560 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 561 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 562 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 563 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 564 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 565 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 566 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 567 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 568 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 569 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 570 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 571 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 572 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 573 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 574 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 575 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 576 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 577 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 578 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 579 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 580 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 581 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 582 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 583 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 584 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 585 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 586 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 587 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 588 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 589 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 590 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 591 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 592 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 593 #ifdef TCP_OFFLOAD 594 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 595 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 596 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 597 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 598 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 599 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 600 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 601 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 602 #endif 603 static int get_sge_context(struct adapter *, struct t4_sge_context *); 604 static int load_fw(struct adapter *, struct t4_data *); 605 static int load_cfg(struct adapter *, struct t4_data *); 606 static int load_boot(struct adapter *, struct t4_bootrom *); 607 static int load_bootcfg(struct adapter *, struct t4_data *); 608 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 609 static void free_offload_policy(struct t4_offload_policy *); 610 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 611 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 612 static int read_i2c(struct adapter *, struct t4_i2c_data *); 613 #ifdef TCP_OFFLOAD 614 static int toe_capability(struct vi_info *, int); 615 #endif 616 static int mod_event(module_t, int, void *); 617 static int notify_siblings(device_t, int); 618 619 struct { 620 uint16_t device; 621 char *desc; 622 } t4_pciids[] = { 623 {0xa000, "Chelsio Terminator 4 FPGA"}, 624 {0x4400, "Chelsio T440-dbg"}, 625 {0x4401, "Chelsio T420-CR"}, 626 {0x4402, "Chelsio T422-CR"}, 627 {0x4403, "Chelsio T440-CR"}, 628 {0x4404, "Chelsio T420-BCH"}, 629 {0x4405, "Chelsio T440-BCH"}, 630 {0x4406, "Chelsio T440-CH"}, 631 {0x4407, "Chelsio T420-SO"}, 632 {0x4408, "Chelsio T420-CX"}, 633 {0x4409, "Chelsio T420-BT"}, 634 {0x440a, "Chelsio T404-BT"}, 635 {0x440e, "Chelsio T440-LP-CR"}, 636 }, t5_pciids[] = { 637 {0xb000, "Chelsio Terminator 5 FPGA"}, 638 {0x5400, "Chelsio T580-dbg"}, 639 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 640 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 641 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 642 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 643 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 644 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 645 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 646 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 647 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 648 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 649 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 650 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 651 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 652 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 653 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 654 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 655 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 656 }, t6_pciids[] = { 657 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 658 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 659 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 660 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 661 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 662 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 663 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 664 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 665 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 666 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 667 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 668 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 669 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 670 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 671 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 672 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 673 674 /* Custom */ 675 {0x6480, "Custom T6225-CR"}, 676 {0x6481, "Custom T62100-CR"}, 677 {0x6482, "Custom T6225-CR"}, 678 {0x6483, "Custom T62100-CR"}, 679 {0x6484, "Custom T64100-CR"}, 680 {0x6485, "Custom T6240-SO"}, 681 {0x6486, "Custom T6225-SO-CR"}, 682 {0x6487, "Custom T6225-CR"}, 683 }; 684 685 #ifdef TCP_OFFLOAD 686 /* 687 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 688 * exactly the same for both rxq and ofld_rxq. 689 */ 690 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 691 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 692 #endif 693 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 694 695 static int 696 t4_probe(device_t dev) 697 { 698 int i; 699 uint16_t v = pci_get_vendor(dev); 700 uint16_t d = pci_get_device(dev); 701 uint8_t f = pci_get_function(dev); 702 703 if (v != PCI_VENDOR_ID_CHELSIO) 704 return (ENXIO); 705 706 /* Attach only to PF0 of the FPGA */ 707 if (d == 0xa000 && f != 0) 708 return (ENXIO); 709 710 for (i = 0; i < nitems(t4_pciids); i++) { 711 if (d == t4_pciids[i].device) { 712 device_set_desc(dev, t4_pciids[i].desc); 713 return (BUS_PROBE_DEFAULT); 714 } 715 } 716 717 return (ENXIO); 718 } 719 720 static int 721 t5_probe(device_t dev) 722 { 723 int i; 724 uint16_t v = pci_get_vendor(dev); 725 uint16_t d = pci_get_device(dev); 726 uint8_t f = pci_get_function(dev); 727 728 if (v != PCI_VENDOR_ID_CHELSIO) 729 return (ENXIO); 730 731 /* Attach only to PF0 of the FPGA */ 732 if (d == 0xb000 && f != 0) 733 return (ENXIO); 734 735 for (i = 0; i < nitems(t5_pciids); i++) { 736 if (d == t5_pciids[i].device) { 737 device_set_desc(dev, t5_pciids[i].desc); 738 return (BUS_PROBE_DEFAULT); 739 } 740 } 741 742 return (ENXIO); 743 } 744 745 static int 746 t6_probe(device_t dev) 747 { 748 int i; 749 uint16_t v = pci_get_vendor(dev); 750 uint16_t d = pci_get_device(dev); 751 752 if (v != PCI_VENDOR_ID_CHELSIO) 753 return (ENXIO); 754 755 for (i = 0; i < nitems(t6_pciids); i++) { 756 if (d == t6_pciids[i].device) { 757 device_set_desc(dev, t6_pciids[i].desc); 758 return (BUS_PROBE_DEFAULT); 759 } 760 } 761 762 return (ENXIO); 763 } 764 765 static void 766 t5_attribute_workaround(device_t dev) 767 { 768 device_t root_port; 769 uint32_t v; 770 771 /* 772 * The T5 chips do not properly echo the No Snoop and Relaxed 773 * Ordering attributes when replying to a TLP from a Root 774 * Port. As a workaround, find the parent Root Port and 775 * disable No Snoop and Relaxed Ordering. Note that this 776 * affects all devices under this root port. 777 */ 778 root_port = pci_find_pcie_root_port(dev); 779 if (root_port == NULL) { 780 device_printf(dev, "Unable to find parent root port\n"); 781 return; 782 } 783 784 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 785 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 786 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 787 0) 788 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 789 device_get_nameunit(root_port)); 790 } 791 792 static const struct devnames devnames[] = { 793 { 794 .nexus_name = "t4nex", 795 .ifnet_name = "cxgbe", 796 .vi_ifnet_name = "vcxgbe", 797 .pf03_drv_name = "t4iov", 798 .vf_nexus_name = "t4vf", 799 .vf_ifnet_name = "cxgbev" 800 }, { 801 .nexus_name = "t5nex", 802 .ifnet_name = "cxl", 803 .vi_ifnet_name = "vcxl", 804 .pf03_drv_name = "t5iov", 805 .vf_nexus_name = "t5vf", 806 .vf_ifnet_name = "cxlv" 807 }, { 808 .nexus_name = "t6nex", 809 .ifnet_name = "cc", 810 .vi_ifnet_name = "vcc", 811 .pf03_drv_name = "t6iov", 812 .vf_nexus_name = "t6vf", 813 .vf_ifnet_name = "ccv" 814 } 815 }; 816 817 void 818 t4_init_devnames(struct adapter *sc) 819 { 820 int id; 821 822 id = chip_id(sc); 823 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 824 sc->names = &devnames[id - CHELSIO_T4]; 825 else { 826 device_printf(sc->dev, "chip id %d is not supported.\n", id); 827 sc->names = NULL; 828 } 829 } 830 831 static int 832 t4_attach(device_t dev) 833 { 834 struct adapter *sc; 835 int rc = 0, i, j, rqidx, tqidx, nports; 836 struct make_dev_args mda; 837 struct intrs_and_queues iaq; 838 struct sge *s; 839 uint32_t *buf; 840 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 841 int ofld_tqidx; 842 #endif 843 #ifdef TCP_OFFLOAD 844 int ofld_rqidx; 845 #endif 846 #ifdef DEV_NETMAP 847 int nm_rqidx, nm_tqidx; 848 #endif 849 int num_vis; 850 851 sc = device_get_softc(dev); 852 sc->dev = dev; 853 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 854 855 if ((pci_get_device(dev) & 0xff00) == 0x5400) 856 t5_attribute_workaround(dev); 857 pci_enable_busmaster(dev); 858 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 859 uint32_t v; 860 861 pci_set_max_read_req(dev, 4096); 862 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 863 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 864 if (pcie_relaxed_ordering == 0 && 865 (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 866 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 867 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 868 } else if (pcie_relaxed_ordering == 1 && 869 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 870 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 871 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 872 } 873 } 874 875 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 876 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 877 sc->traceq = -1; 878 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 879 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 880 device_get_nameunit(dev)); 881 882 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 883 device_get_nameunit(dev)); 884 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 885 t4_add_adapter(sc); 886 887 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 888 TAILQ_INIT(&sc->sfl); 889 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 890 891 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 892 893 sc->policy = NULL; 894 rw_init(&sc->policy_lock, "connection offload policy"); 895 896 rc = t4_map_bars_0_and_4(sc); 897 if (rc != 0) 898 goto done; /* error message displayed already */ 899 900 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 901 902 /* Prepare the adapter for operation. */ 903 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 904 rc = -t4_prep_adapter(sc, buf); 905 free(buf, M_CXGBE); 906 if (rc != 0) { 907 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 908 goto done; 909 } 910 911 /* 912 * This is the real PF# to which we're attaching. Works from within PCI 913 * passthrough environments too, where pci_get_function() could return a 914 * different PF# depending on the passthrough configuration. We need to 915 * use the real PF# in all our communication with the firmware. 916 */ 917 j = t4_read_reg(sc, A_PL_WHOAMI); 918 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 919 sc->mbox = sc->pf; 920 921 t4_init_devnames(sc); 922 if (sc->names == NULL) { 923 rc = ENOTSUP; 924 goto done; /* error message displayed already */ 925 } 926 927 /* 928 * Do this really early, with the memory windows set up even before the 929 * character device. The userland tool's register i/o and mem read 930 * will work even in "recovery mode". 931 */ 932 setup_memwin(sc); 933 if (t4_init_devlog_params(sc, 0) == 0) 934 fixup_devlog_params(sc); 935 make_dev_args_init(&mda); 936 mda.mda_devsw = &t4_cdevsw; 937 mda.mda_uid = UID_ROOT; 938 mda.mda_gid = GID_WHEEL; 939 mda.mda_mode = 0600; 940 mda.mda_si_drv1 = sc; 941 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 942 if (rc != 0) 943 device_printf(dev, "failed to create nexus char device: %d.\n", 944 rc); 945 946 /* Go no further if recovery mode has been requested. */ 947 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 948 device_printf(dev, "recovery mode.\n"); 949 goto done; 950 } 951 952 #if defined(__i386__) 953 if ((cpu_feature & CPUID_CX8) == 0) { 954 device_printf(dev, "64 bit atomics not available.\n"); 955 rc = ENOTSUP; 956 goto done; 957 } 958 #endif 959 960 /* Prepare the firmware for operation */ 961 rc = prep_firmware(sc); 962 if (rc != 0) 963 goto done; /* error message displayed already */ 964 965 rc = get_params__post_init(sc); 966 if (rc != 0) 967 goto done; /* error message displayed already */ 968 969 rc = set_params__post_init(sc); 970 if (rc != 0) 971 goto done; /* error message displayed already */ 972 973 rc = t4_map_bar_2(sc); 974 if (rc != 0) 975 goto done; /* error message displayed already */ 976 977 rc = t4_create_dma_tag(sc); 978 if (rc != 0) 979 goto done; /* error message displayed already */ 980 981 /* 982 * First pass over all the ports - allocate VIs and initialize some 983 * basic parameters like mac address, port type, etc. 984 */ 985 for_each_port(sc, i) { 986 struct port_info *pi; 987 988 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 989 sc->port[i] = pi; 990 991 /* These must be set before t4_port_init */ 992 pi->adapter = sc; 993 pi->port_id = i; 994 /* 995 * XXX: vi[0] is special so we can't delay this allocation until 996 * pi->nvi's final value is known. 997 */ 998 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 999 M_ZERO | M_WAITOK); 1000 1001 /* 1002 * Allocate the "main" VI and initialize parameters 1003 * like mac addr. 1004 */ 1005 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1006 if (rc != 0) { 1007 device_printf(dev, "unable to initialize port %d: %d\n", 1008 i, rc); 1009 free(pi->vi, M_CXGBE); 1010 free(pi, M_CXGBE); 1011 sc->port[i] = NULL; 1012 goto done; 1013 } 1014 1015 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1016 device_get_nameunit(dev), i); 1017 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1018 sc->chan_map[pi->tx_chan] = i; 1019 1020 /* All VIs on this port share this media. */ 1021 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1022 cxgbe_media_status); 1023 1024 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1); 1025 if (pi->dev == NULL) { 1026 device_printf(dev, 1027 "failed to add device for port %d.\n", i); 1028 rc = ENXIO; 1029 goto done; 1030 } 1031 pi->vi[0].dev = pi->dev; 1032 device_set_softc(pi->dev, pi); 1033 } 1034 1035 /* 1036 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1037 */ 1038 nports = sc->params.nports; 1039 rc = cfg_itype_and_nqueues(sc, &iaq); 1040 if (rc != 0) 1041 goto done; /* error message displayed already */ 1042 1043 num_vis = iaq.num_vis; 1044 sc->intr_type = iaq.intr_type; 1045 sc->intr_count = iaq.nirq; 1046 1047 s = &sc->sge; 1048 s->nrxq = nports * iaq.nrxq; 1049 s->ntxq = nports * iaq.ntxq; 1050 if (num_vis > 1) { 1051 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1052 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1053 } 1054 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1055 s->neq += nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 1056 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1057 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1058 if (is_offload(sc) || is_ethoffload(sc)) { 1059 s->nofldtxq = nports * iaq.nofldtxq; 1060 if (num_vis > 1) 1061 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1062 s->neq += s->nofldtxq; 1063 1064 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1065 M_CXGBE, M_ZERO | M_WAITOK); 1066 } 1067 #endif 1068 #ifdef TCP_OFFLOAD 1069 if (is_offload(sc)) { 1070 s->nofldrxq = nports * iaq.nofldrxq; 1071 if (num_vis > 1) 1072 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1073 s->neq += s->nofldrxq; /* free list */ 1074 s->niq += s->nofldrxq; 1075 1076 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1077 M_CXGBE, M_ZERO | M_WAITOK); 1078 } 1079 #endif 1080 #ifdef DEV_NETMAP 1081 if (num_vis > 1) { 1082 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1083 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1084 } 1085 s->neq += s->nnmtxq + s->nnmrxq; 1086 s->niq += s->nnmrxq; 1087 1088 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1089 M_CXGBE, M_ZERO | M_WAITOK); 1090 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1091 M_CXGBE, M_ZERO | M_WAITOK); 1092 #endif 1093 1094 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1095 M_ZERO | M_WAITOK); 1096 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1097 M_ZERO | M_WAITOK); 1098 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1099 M_ZERO | M_WAITOK); 1100 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1101 M_ZERO | M_WAITOK); 1102 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1103 M_ZERO | M_WAITOK); 1104 1105 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1106 M_ZERO | M_WAITOK); 1107 1108 t4_init_l2t(sc, M_WAITOK); 1109 t4_init_smt(sc, M_WAITOK); 1110 t4_init_tx_sched(sc); 1111 #ifdef RATELIMIT 1112 t4_init_etid_table(sc); 1113 #endif 1114 1115 /* 1116 * Second pass over the ports. This time we know the number of rx and 1117 * tx queues that each port should get. 1118 */ 1119 rqidx = tqidx = 0; 1120 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1121 ofld_tqidx = 0; 1122 #endif 1123 #ifdef TCP_OFFLOAD 1124 ofld_rqidx = 0; 1125 #endif 1126 #ifdef DEV_NETMAP 1127 nm_rqidx = nm_tqidx = 0; 1128 #endif 1129 for_each_port(sc, i) { 1130 struct port_info *pi = sc->port[i]; 1131 struct vi_info *vi; 1132 1133 if (pi == NULL) 1134 continue; 1135 1136 pi->nvi = num_vis; 1137 for_each_vi(pi, j, vi) { 1138 vi->pi = pi; 1139 vi->qsize_rxq = t4_qsize_rxq; 1140 vi->qsize_txq = t4_qsize_txq; 1141 1142 vi->first_rxq = rqidx; 1143 vi->first_txq = tqidx; 1144 vi->tmr_idx = t4_tmr_idx; 1145 vi->pktc_idx = t4_pktc_idx; 1146 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1147 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1148 1149 rqidx += vi->nrxq; 1150 tqidx += vi->ntxq; 1151 1152 if (j == 0 && vi->ntxq > 1) 1153 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1154 else 1155 vi->rsrv_noflowq = 0; 1156 1157 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1158 vi->first_ofld_txq = ofld_tqidx; 1159 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1160 ofld_tqidx += vi->nofldtxq; 1161 #endif 1162 #ifdef TCP_OFFLOAD 1163 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1164 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1165 vi->first_ofld_rxq = ofld_rqidx; 1166 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1167 1168 ofld_rqidx += vi->nofldrxq; 1169 #endif 1170 #ifdef DEV_NETMAP 1171 if (j > 0) { 1172 vi->first_nm_rxq = nm_rqidx; 1173 vi->first_nm_txq = nm_tqidx; 1174 vi->nnmrxq = iaq.nnmrxq_vi; 1175 vi->nnmtxq = iaq.nnmtxq_vi; 1176 nm_rqidx += vi->nnmrxq; 1177 nm_tqidx += vi->nnmtxq; 1178 } 1179 #endif 1180 } 1181 } 1182 1183 rc = t4_setup_intr_handlers(sc); 1184 if (rc != 0) { 1185 device_printf(dev, 1186 "failed to setup interrupt handlers: %d\n", rc); 1187 goto done; 1188 } 1189 1190 rc = bus_generic_probe(dev); 1191 if (rc != 0) { 1192 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1193 goto done; 1194 } 1195 1196 /* 1197 * Ensure thread-safe mailbox access (in debug builds). 1198 * 1199 * So far this was the only thread accessing the mailbox but various 1200 * ifnets and sysctls are about to be created and their handlers/ioctls 1201 * will access the mailbox from different threads. 1202 */ 1203 sc->flags |= CHK_MBOX_ACCESS; 1204 1205 rc = bus_generic_attach(dev); 1206 if (rc != 0) { 1207 device_printf(dev, 1208 "failed to attach all child ports: %d\n", rc); 1209 goto done; 1210 } 1211 1212 device_printf(dev, 1213 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1214 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1215 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1216 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1217 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1218 1219 t4_set_desc(sc); 1220 1221 notify_siblings(dev, 0); 1222 1223 done: 1224 if (rc != 0 && sc->cdev) { 1225 /* cdev was created and so cxgbetool works; recover that way. */ 1226 device_printf(dev, 1227 "error during attach, adapter is now in recovery mode.\n"); 1228 rc = 0; 1229 } 1230 1231 if (rc != 0) 1232 t4_detach_common(dev); 1233 else 1234 t4_sysctls(sc); 1235 1236 return (rc); 1237 } 1238 1239 static int 1240 t4_ready(device_t dev) 1241 { 1242 struct adapter *sc; 1243 1244 sc = device_get_softc(dev); 1245 if (sc->flags & FW_OK) 1246 return (0); 1247 return (ENXIO); 1248 } 1249 1250 static int 1251 t4_read_port_device(device_t dev, int port, device_t *child) 1252 { 1253 struct adapter *sc; 1254 struct port_info *pi; 1255 1256 sc = device_get_softc(dev); 1257 if (port < 0 || port >= MAX_NPORTS) 1258 return (EINVAL); 1259 pi = sc->port[port]; 1260 if (pi == NULL || pi->dev == NULL) 1261 return (ENXIO); 1262 *child = pi->dev; 1263 return (0); 1264 } 1265 1266 static int 1267 notify_siblings(device_t dev, int detaching) 1268 { 1269 device_t sibling; 1270 int error, i; 1271 1272 error = 0; 1273 for (i = 0; i < PCI_FUNCMAX; i++) { 1274 if (i == pci_get_function(dev)) 1275 continue; 1276 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1277 pci_get_slot(dev), i); 1278 if (sibling == NULL || !device_is_attached(sibling)) 1279 continue; 1280 if (detaching) 1281 error = T4_DETACH_CHILD(sibling); 1282 else 1283 (void)T4_ATTACH_CHILD(sibling); 1284 if (error) 1285 break; 1286 } 1287 return (error); 1288 } 1289 1290 /* 1291 * Idempotent 1292 */ 1293 static int 1294 t4_detach(device_t dev) 1295 { 1296 struct adapter *sc; 1297 int rc; 1298 1299 sc = device_get_softc(dev); 1300 1301 rc = notify_siblings(dev, 1); 1302 if (rc) { 1303 device_printf(dev, 1304 "failed to detach sibling devices: %d\n", rc); 1305 return (rc); 1306 } 1307 1308 return (t4_detach_common(dev)); 1309 } 1310 1311 int 1312 t4_detach_common(device_t dev) 1313 { 1314 struct adapter *sc; 1315 struct port_info *pi; 1316 int i, rc; 1317 1318 sc = device_get_softc(dev); 1319 1320 if (sc->cdev) { 1321 destroy_dev(sc->cdev); 1322 sc->cdev = NULL; 1323 } 1324 1325 sc->flags &= ~CHK_MBOX_ACCESS; 1326 if (sc->flags & FULL_INIT_DONE) { 1327 if (!(sc->flags & IS_VF)) 1328 t4_intr_disable(sc); 1329 } 1330 1331 if (device_is_attached(dev)) { 1332 rc = bus_generic_detach(dev); 1333 if (rc) { 1334 device_printf(dev, 1335 "failed to detach child devices: %d\n", rc); 1336 return (rc); 1337 } 1338 } 1339 1340 for (i = 0; i < sc->intr_count; i++) 1341 t4_free_irq(sc, &sc->irq[i]); 1342 1343 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1344 t4_free_tx_sched(sc); 1345 1346 for (i = 0; i < MAX_NPORTS; i++) { 1347 pi = sc->port[i]; 1348 if (pi) { 1349 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1350 if (pi->dev) 1351 device_delete_child(dev, pi->dev); 1352 1353 mtx_destroy(&pi->pi_lock); 1354 free(pi->vi, M_CXGBE); 1355 free(pi, M_CXGBE); 1356 } 1357 } 1358 1359 device_delete_children(dev); 1360 1361 if (sc->flags & FULL_INIT_DONE) 1362 adapter_full_uninit(sc); 1363 1364 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1365 t4_fw_bye(sc, sc->mbox); 1366 1367 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1368 pci_release_msi(dev); 1369 1370 if (sc->regs_res) 1371 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1372 sc->regs_res); 1373 1374 if (sc->udbs_res) 1375 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1376 sc->udbs_res); 1377 1378 if (sc->msix_res) 1379 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1380 sc->msix_res); 1381 1382 if (sc->l2t) 1383 t4_free_l2t(sc->l2t); 1384 if (sc->smt) 1385 t4_free_smt(sc->smt); 1386 #ifdef RATELIMIT 1387 t4_free_etid_table(sc); 1388 #endif 1389 1390 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1391 free(sc->sge.ofld_txq, M_CXGBE); 1392 #endif 1393 #ifdef TCP_OFFLOAD 1394 free(sc->sge.ofld_rxq, M_CXGBE); 1395 #endif 1396 #ifdef DEV_NETMAP 1397 free(sc->sge.nm_rxq, M_CXGBE); 1398 free(sc->sge.nm_txq, M_CXGBE); 1399 #endif 1400 free(sc->irq, M_CXGBE); 1401 free(sc->sge.rxq, M_CXGBE); 1402 free(sc->sge.txq, M_CXGBE); 1403 free(sc->sge.ctrlq, M_CXGBE); 1404 free(sc->sge.iqmap, M_CXGBE); 1405 free(sc->sge.eqmap, M_CXGBE); 1406 free(sc->tids.ftid_tab, M_CXGBE); 1407 if (sc->tids.hftid_tab) 1408 free_hftid_tab(&sc->tids); 1409 free(sc->tids.atid_tab, M_CXGBE); 1410 free(sc->tids.tid_tab, M_CXGBE); 1411 free(sc->tt.tls_rx_ports, M_CXGBE); 1412 t4_destroy_dma_tag(sc); 1413 if (mtx_initialized(&sc->sc_lock)) { 1414 sx_xlock(&t4_list_lock); 1415 SLIST_REMOVE(&t4_list, sc, adapter, link); 1416 sx_xunlock(&t4_list_lock); 1417 mtx_destroy(&sc->sc_lock); 1418 } 1419 1420 callout_drain(&sc->sfl_callout); 1421 if (mtx_initialized(&sc->tids.ftid_lock)) { 1422 mtx_destroy(&sc->tids.ftid_lock); 1423 cv_destroy(&sc->tids.ftid_cv); 1424 } 1425 if (mtx_initialized(&sc->tids.atid_lock)) 1426 mtx_destroy(&sc->tids.atid_lock); 1427 if (mtx_initialized(&sc->sfl_lock)) 1428 mtx_destroy(&sc->sfl_lock); 1429 if (mtx_initialized(&sc->ifp_lock)) 1430 mtx_destroy(&sc->ifp_lock); 1431 if (mtx_initialized(&sc->reg_lock)) 1432 mtx_destroy(&sc->reg_lock); 1433 1434 if (rw_initialized(&sc->policy_lock)) { 1435 rw_destroy(&sc->policy_lock); 1436 #ifdef TCP_OFFLOAD 1437 if (sc->policy != NULL) 1438 free_offload_policy(sc->policy); 1439 #endif 1440 } 1441 1442 for (i = 0; i < NUM_MEMWIN; i++) { 1443 struct memwin *mw = &sc->memwin[i]; 1444 1445 if (rw_initialized(&mw->mw_lock)) 1446 rw_destroy(&mw->mw_lock); 1447 } 1448 1449 bzero(sc, sizeof(*sc)); 1450 1451 return (0); 1452 } 1453 1454 static int 1455 cxgbe_probe(device_t dev) 1456 { 1457 char buf[128]; 1458 struct port_info *pi = device_get_softc(dev); 1459 1460 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1461 device_set_desc_copy(dev, buf); 1462 1463 return (BUS_PROBE_DEFAULT); 1464 } 1465 1466 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1467 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1468 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1469 #define T4_CAP_ENABLE (T4_CAP) 1470 1471 static int 1472 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1473 { 1474 struct ifnet *ifp; 1475 struct sbuf *sb; 1476 1477 vi->xact_addr_filt = -1; 1478 callout_init(&vi->tick, 1); 1479 1480 /* Allocate an ifnet and set it up */ 1481 ifp = if_alloc(IFT_ETHER); 1482 if (ifp == NULL) { 1483 device_printf(dev, "Cannot allocate ifnet\n"); 1484 return (ENOMEM); 1485 } 1486 vi->ifp = ifp; 1487 ifp->if_softc = vi; 1488 1489 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1490 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1491 1492 ifp->if_init = cxgbe_init; 1493 ifp->if_ioctl = cxgbe_ioctl; 1494 ifp->if_transmit = cxgbe_transmit; 1495 ifp->if_qflush = cxgbe_qflush; 1496 ifp->if_get_counter = cxgbe_get_counter; 1497 #ifdef RATELIMIT 1498 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 1499 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify; 1500 ifp->if_snd_tag_query = cxgbe_snd_tag_query; 1501 ifp->if_snd_tag_free = cxgbe_snd_tag_free; 1502 #endif 1503 1504 ifp->if_capabilities = T4_CAP; 1505 #ifdef TCP_OFFLOAD 1506 if (vi->nofldrxq != 0) 1507 ifp->if_capabilities |= IFCAP_TOE; 1508 #endif 1509 #ifdef DEV_NETMAP 1510 if (vi->nnmrxq != 0) 1511 ifp->if_capabilities |= IFCAP_NETMAP; 1512 #endif 1513 #ifdef RATELIMIT 1514 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) 1515 ifp->if_capabilities |= IFCAP_TXRTLMT; 1516 #endif 1517 ifp->if_capenable = T4_CAP_ENABLE; 1518 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1519 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1520 1521 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1522 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1523 ifp->if_hw_tsomaxsegsize = 65536; 1524 1525 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1526 EVENTHANDLER_PRI_ANY); 1527 1528 ether_ifattach(ifp, vi->hw_addr); 1529 #ifdef DEV_NETMAP 1530 if (ifp->if_capabilities & IFCAP_NETMAP) 1531 cxgbe_nm_attach(vi); 1532 #endif 1533 sb = sbuf_new_auto(); 1534 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1535 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1536 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 1537 case IFCAP_TOE: 1538 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 1539 break; 1540 case IFCAP_TOE | IFCAP_TXRTLMT: 1541 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 1542 break; 1543 case IFCAP_TXRTLMT: 1544 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 1545 break; 1546 } 1547 #endif 1548 #ifdef TCP_OFFLOAD 1549 if (ifp->if_capabilities & IFCAP_TOE) 1550 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 1551 #endif 1552 #ifdef DEV_NETMAP 1553 if (ifp->if_capabilities & IFCAP_NETMAP) 1554 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1555 vi->nnmtxq, vi->nnmrxq); 1556 #endif 1557 sbuf_finish(sb); 1558 device_printf(dev, "%s\n", sbuf_data(sb)); 1559 sbuf_delete(sb); 1560 1561 vi_sysctls(vi); 1562 1563 return (0); 1564 } 1565 1566 static int 1567 cxgbe_attach(device_t dev) 1568 { 1569 struct port_info *pi = device_get_softc(dev); 1570 struct adapter *sc = pi->adapter; 1571 struct vi_info *vi; 1572 int i, rc; 1573 1574 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1575 1576 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1577 if (rc) 1578 return (rc); 1579 1580 for_each_vi(pi, i, vi) { 1581 if (i == 0) 1582 continue; 1583 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1584 if (vi->dev == NULL) { 1585 device_printf(dev, "failed to add VI %d\n", i); 1586 continue; 1587 } 1588 device_set_softc(vi->dev, vi); 1589 } 1590 1591 cxgbe_sysctls(pi); 1592 1593 bus_generic_attach(dev); 1594 1595 return (0); 1596 } 1597 1598 static void 1599 cxgbe_vi_detach(struct vi_info *vi) 1600 { 1601 struct ifnet *ifp = vi->ifp; 1602 1603 ether_ifdetach(ifp); 1604 1605 if (vi->vlan_c) 1606 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1607 1608 /* Let detach proceed even if these fail. */ 1609 #ifdef DEV_NETMAP 1610 if (ifp->if_capabilities & IFCAP_NETMAP) 1611 cxgbe_nm_detach(vi); 1612 #endif 1613 cxgbe_uninit_synchronized(vi); 1614 callout_drain(&vi->tick); 1615 vi_full_uninit(vi); 1616 1617 if_free(vi->ifp); 1618 vi->ifp = NULL; 1619 } 1620 1621 static int 1622 cxgbe_detach(device_t dev) 1623 { 1624 struct port_info *pi = device_get_softc(dev); 1625 struct adapter *sc = pi->adapter; 1626 int rc; 1627 1628 /* Detach the extra VIs first. */ 1629 rc = bus_generic_detach(dev); 1630 if (rc) 1631 return (rc); 1632 device_delete_children(dev); 1633 1634 doom_vi(sc, &pi->vi[0]); 1635 1636 if (pi->flags & HAS_TRACEQ) { 1637 sc->traceq = -1; /* cloner should not create ifnet */ 1638 t4_tracer_port_detach(sc); 1639 } 1640 1641 cxgbe_vi_detach(&pi->vi[0]); 1642 callout_drain(&pi->tick); 1643 ifmedia_removeall(&pi->media); 1644 1645 end_synchronized_op(sc, 0); 1646 1647 return (0); 1648 } 1649 1650 static void 1651 cxgbe_init(void *arg) 1652 { 1653 struct vi_info *vi = arg; 1654 struct adapter *sc = vi->pi->adapter; 1655 1656 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1657 return; 1658 cxgbe_init_synchronized(vi); 1659 end_synchronized_op(sc, 0); 1660 } 1661 1662 static int 1663 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1664 { 1665 int rc = 0, mtu, flags; 1666 struct vi_info *vi = ifp->if_softc; 1667 struct port_info *pi = vi->pi; 1668 struct adapter *sc = pi->adapter; 1669 struct ifreq *ifr = (struct ifreq *)data; 1670 uint32_t mask; 1671 1672 switch (cmd) { 1673 case SIOCSIFMTU: 1674 mtu = ifr->ifr_mtu; 1675 if (mtu < ETHERMIN || mtu > MAX_MTU) 1676 return (EINVAL); 1677 1678 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1679 if (rc) 1680 return (rc); 1681 ifp->if_mtu = mtu; 1682 if (vi->flags & VI_INIT_DONE) { 1683 t4_update_fl_bufsize(ifp); 1684 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1685 rc = update_mac_settings(ifp, XGMAC_MTU); 1686 } 1687 end_synchronized_op(sc, 0); 1688 break; 1689 1690 case SIOCSIFFLAGS: 1691 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 1692 if (rc) 1693 return (rc); 1694 1695 if (ifp->if_flags & IFF_UP) { 1696 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1697 flags = vi->if_flags; 1698 if ((ifp->if_flags ^ flags) & 1699 (IFF_PROMISC | IFF_ALLMULTI)) { 1700 rc = update_mac_settings(ifp, 1701 XGMAC_PROMISC | XGMAC_ALLMULTI); 1702 } 1703 } else { 1704 rc = cxgbe_init_synchronized(vi); 1705 } 1706 vi->if_flags = ifp->if_flags; 1707 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1708 rc = cxgbe_uninit_synchronized(vi); 1709 } 1710 end_synchronized_op(sc, 0); 1711 break; 1712 1713 case SIOCADDMULTI: 1714 case SIOCDELMULTI: 1715 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 1716 if (rc) 1717 return (rc); 1718 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1719 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1720 end_synchronized_op(sc, 0); 1721 break; 1722 1723 case SIOCSIFCAP: 1724 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1725 if (rc) 1726 return (rc); 1727 1728 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1729 if (mask & IFCAP_TXCSUM) { 1730 ifp->if_capenable ^= IFCAP_TXCSUM; 1731 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1732 1733 if (IFCAP_TSO4 & ifp->if_capenable && 1734 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1735 ifp->if_capenable &= ~IFCAP_TSO4; 1736 if_printf(ifp, 1737 "tso4 disabled due to -txcsum.\n"); 1738 } 1739 } 1740 if (mask & IFCAP_TXCSUM_IPV6) { 1741 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1742 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1743 1744 if (IFCAP_TSO6 & ifp->if_capenable && 1745 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1746 ifp->if_capenable &= ~IFCAP_TSO6; 1747 if_printf(ifp, 1748 "tso6 disabled due to -txcsum6.\n"); 1749 } 1750 } 1751 if (mask & IFCAP_RXCSUM) 1752 ifp->if_capenable ^= IFCAP_RXCSUM; 1753 if (mask & IFCAP_RXCSUM_IPV6) 1754 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1755 1756 /* 1757 * Note that we leave CSUM_TSO alone (it is always set). The 1758 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1759 * sending a TSO request our way, so it's sufficient to toggle 1760 * IFCAP_TSOx only. 1761 */ 1762 if (mask & IFCAP_TSO4) { 1763 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1764 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1765 if_printf(ifp, "enable txcsum first.\n"); 1766 rc = EAGAIN; 1767 goto fail; 1768 } 1769 ifp->if_capenable ^= IFCAP_TSO4; 1770 } 1771 if (mask & IFCAP_TSO6) { 1772 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1773 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1774 if_printf(ifp, "enable txcsum6 first.\n"); 1775 rc = EAGAIN; 1776 goto fail; 1777 } 1778 ifp->if_capenable ^= IFCAP_TSO6; 1779 } 1780 if (mask & IFCAP_LRO) { 1781 #if defined(INET) || defined(INET6) 1782 int i; 1783 struct sge_rxq *rxq; 1784 1785 ifp->if_capenable ^= IFCAP_LRO; 1786 for_each_rxq(vi, i, rxq) { 1787 if (ifp->if_capenable & IFCAP_LRO) 1788 rxq->iq.flags |= IQ_LRO_ENABLED; 1789 else 1790 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1791 } 1792 #endif 1793 } 1794 #ifdef TCP_OFFLOAD 1795 if (mask & IFCAP_TOE) { 1796 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1797 1798 rc = toe_capability(vi, enable); 1799 if (rc != 0) 1800 goto fail; 1801 1802 ifp->if_capenable ^= mask; 1803 } 1804 #endif 1805 if (mask & IFCAP_VLAN_HWTAGGING) { 1806 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1807 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1808 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1809 } 1810 if (mask & IFCAP_VLAN_MTU) { 1811 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1812 1813 /* Need to find out how to disable auto-mtu-inflation */ 1814 } 1815 if (mask & IFCAP_VLAN_HWTSO) 1816 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1817 if (mask & IFCAP_VLAN_HWCSUM) 1818 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1819 #ifdef RATELIMIT 1820 if (mask & IFCAP_TXRTLMT) 1821 ifp->if_capenable ^= IFCAP_TXRTLMT; 1822 #endif 1823 1824 #ifdef VLAN_CAPABILITIES 1825 VLAN_CAPABILITIES(ifp); 1826 #endif 1827 fail: 1828 end_synchronized_op(sc, 0); 1829 break; 1830 1831 case SIOCSIFMEDIA: 1832 case SIOCGIFMEDIA: 1833 case SIOCGIFXMEDIA: 1834 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 1835 break; 1836 1837 case SIOCGI2C: { 1838 struct ifi2creq i2c; 1839 1840 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 1841 if (rc != 0) 1842 break; 1843 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1844 rc = EPERM; 1845 break; 1846 } 1847 if (i2c.len > sizeof(i2c.data)) { 1848 rc = EINVAL; 1849 break; 1850 } 1851 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1852 if (rc) 1853 return (rc); 1854 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 1855 i2c.offset, i2c.len, &i2c.data[0]); 1856 end_synchronized_op(sc, 0); 1857 if (rc == 0) 1858 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 1859 break; 1860 } 1861 1862 default: 1863 rc = ether_ioctl(ifp, cmd, data); 1864 } 1865 1866 return (rc); 1867 } 1868 1869 static int 1870 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1871 { 1872 struct vi_info *vi = ifp->if_softc; 1873 struct port_info *pi = vi->pi; 1874 struct adapter *sc = pi->adapter; 1875 struct sge_txq *txq; 1876 void *items[1]; 1877 int rc; 1878 1879 M_ASSERTPKTHDR(m); 1880 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1881 1882 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1883 m_freem(m); 1884 return (ENETDOWN); 1885 } 1886 1887 rc = parse_pkt(sc, &m); 1888 if (__predict_false(rc != 0)) { 1889 MPASS(m == NULL); /* was freed already */ 1890 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1891 return (rc); 1892 } 1893 #ifdef RATELIMIT 1894 if (m->m_pkthdr.snd_tag != NULL) { 1895 /* EAGAIN tells the stack we are not the correct interface. */ 1896 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) { 1897 m_freem(m); 1898 return (EAGAIN); 1899 } 1900 1901 return (ethofld_transmit(ifp, m)); 1902 } 1903 #endif 1904 1905 /* Select a txq. */ 1906 txq = &sc->sge.txq[vi->first_txq]; 1907 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1908 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1909 vi->rsrv_noflowq); 1910 1911 items[0] = m; 1912 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 1913 if (__predict_false(rc != 0)) 1914 m_freem(m); 1915 1916 return (rc); 1917 } 1918 1919 static void 1920 cxgbe_qflush(struct ifnet *ifp) 1921 { 1922 struct vi_info *vi = ifp->if_softc; 1923 struct sge_txq *txq; 1924 int i; 1925 1926 /* queues do not exist if !VI_INIT_DONE. */ 1927 if (vi->flags & VI_INIT_DONE) { 1928 for_each_txq(vi, i, txq) { 1929 TXQ_LOCK(txq); 1930 txq->eq.flags |= EQ_QFLUSH; 1931 TXQ_UNLOCK(txq); 1932 while (!mp_ring_is_idle(txq->r)) { 1933 mp_ring_check_drainage(txq->r, 0); 1934 pause("qflush", 1); 1935 } 1936 TXQ_LOCK(txq); 1937 txq->eq.flags &= ~EQ_QFLUSH; 1938 TXQ_UNLOCK(txq); 1939 } 1940 } 1941 if_qflush(ifp); 1942 } 1943 1944 static uint64_t 1945 vi_get_counter(struct ifnet *ifp, ift_counter c) 1946 { 1947 struct vi_info *vi = ifp->if_softc; 1948 struct fw_vi_stats_vf *s = &vi->stats; 1949 1950 vi_refresh_stats(vi->pi->adapter, vi); 1951 1952 switch (c) { 1953 case IFCOUNTER_IPACKETS: 1954 return (s->rx_bcast_frames + s->rx_mcast_frames + 1955 s->rx_ucast_frames); 1956 case IFCOUNTER_IERRORS: 1957 return (s->rx_err_frames); 1958 case IFCOUNTER_OPACKETS: 1959 return (s->tx_bcast_frames + s->tx_mcast_frames + 1960 s->tx_ucast_frames + s->tx_offload_frames); 1961 case IFCOUNTER_OERRORS: 1962 return (s->tx_drop_frames); 1963 case IFCOUNTER_IBYTES: 1964 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 1965 s->rx_ucast_bytes); 1966 case IFCOUNTER_OBYTES: 1967 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 1968 s->tx_ucast_bytes + s->tx_offload_bytes); 1969 case IFCOUNTER_IMCASTS: 1970 return (s->rx_mcast_frames); 1971 case IFCOUNTER_OMCASTS: 1972 return (s->tx_mcast_frames); 1973 case IFCOUNTER_OQDROPS: { 1974 uint64_t drops; 1975 1976 drops = 0; 1977 if (vi->flags & VI_INIT_DONE) { 1978 int i; 1979 struct sge_txq *txq; 1980 1981 for_each_txq(vi, i, txq) 1982 drops += counter_u64_fetch(txq->r->drops); 1983 } 1984 1985 return (drops); 1986 1987 } 1988 1989 default: 1990 return (if_get_counter_default(ifp, c)); 1991 } 1992 } 1993 1994 uint64_t 1995 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 1996 { 1997 struct vi_info *vi = ifp->if_softc; 1998 struct port_info *pi = vi->pi; 1999 struct adapter *sc = pi->adapter; 2000 struct port_stats *s = &pi->stats; 2001 2002 if (pi->nvi > 1 || sc->flags & IS_VF) 2003 return (vi_get_counter(ifp, c)); 2004 2005 cxgbe_refresh_stats(sc, pi); 2006 2007 switch (c) { 2008 case IFCOUNTER_IPACKETS: 2009 return (s->rx_frames); 2010 2011 case IFCOUNTER_IERRORS: 2012 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2013 s->rx_fcs_err + s->rx_len_err); 2014 2015 case IFCOUNTER_OPACKETS: 2016 return (s->tx_frames); 2017 2018 case IFCOUNTER_OERRORS: 2019 return (s->tx_error_frames); 2020 2021 case IFCOUNTER_IBYTES: 2022 return (s->rx_octets); 2023 2024 case IFCOUNTER_OBYTES: 2025 return (s->tx_octets); 2026 2027 case IFCOUNTER_IMCASTS: 2028 return (s->rx_mcast_frames); 2029 2030 case IFCOUNTER_OMCASTS: 2031 return (s->tx_mcast_frames); 2032 2033 case IFCOUNTER_IQDROPS: 2034 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2035 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2036 s->rx_trunc3 + pi->tnl_cong_drops); 2037 2038 case IFCOUNTER_OQDROPS: { 2039 uint64_t drops; 2040 2041 drops = s->tx_drop; 2042 if (vi->flags & VI_INIT_DONE) { 2043 int i; 2044 struct sge_txq *txq; 2045 2046 for_each_txq(vi, i, txq) 2047 drops += counter_u64_fetch(txq->r->drops); 2048 } 2049 2050 return (drops); 2051 2052 } 2053 2054 default: 2055 return (if_get_counter_default(ifp, c)); 2056 } 2057 } 2058 2059 /* 2060 * The kernel picks a media from the list we had provided so we do not have to 2061 * validate the request. 2062 */ 2063 static int 2064 cxgbe_media_change(struct ifnet *ifp) 2065 { 2066 struct vi_info *vi = ifp->if_softc; 2067 struct port_info *pi = vi->pi; 2068 struct ifmedia *ifm = &pi->media; 2069 struct link_config *lc = &pi->link_cfg; 2070 struct adapter *sc = pi->adapter; 2071 int rc; 2072 2073 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2074 if (rc != 0) 2075 return (rc); 2076 PORT_LOCK(pi); 2077 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2078 MPASS(lc->supported & FW_PORT_CAP_ANEG); 2079 lc->requested_aneg = AUTONEG_ENABLE; 2080 } else { 2081 lc->requested_aneg = AUTONEG_DISABLE; 2082 lc->requested_speed = 2083 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2084 lc->requested_fc = 0; 2085 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2086 lc->requested_fc |= PAUSE_RX; 2087 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2088 lc->requested_fc |= PAUSE_TX; 2089 } 2090 if (pi->up_vis > 0) 2091 rc = apply_l1cfg(pi); 2092 PORT_UNLOCK(pi); 2093 end_synchronized_op(sc, 0); 2094 return (rc); 2095 } 2096 2097 /* 2098 * Mbps to FW_PORT_CAP_SPEED_* bit. 2099 */ 2100 static uint16_t 2101 speed_to_fwspeed(int speed) 2102 { 2103 2104 switch (speed) { 2105 case 100000: 2106 return (FW_PORT_CAP_SPEED_100G); 2107 case 40000: 2108 return (FW_PORT_CAP_SPEED_40G); 2109 case 25000: 2110 return (FW_PORT_CAP_SPEED_25G); 2111 case 10000: 2112 return (FW_PORT_CAP_SPEED_10G); 2113 case 1000: 2114 return (FW_PORT_CAP_SPEED_1G); 2115 case 100: 2116 return (FW_PORT_CAP_SPEED_100M); 2117 } 2118 2119 return (0); 2120 } 2121 2122 /* 2123 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2124 * given speed. 2125 */ 2126 static int 2127 port_mword(struct port_info *pi, uint16_t speed) 2128 { 2129 2130 MPASS(speed & M_FW_PORT_CAP_SPEED); 2131 MPASS(powerof2(speed)); 2132 2133 switch(pi->port_type) { 2134 case FW_PORT_TYPE_BT_SGMII: 2135 case FW_PORT_TYPE_BT_XFI: 2136 case FW_PORT_TYPE_BT_XAUI: 2137 /* BaseT */ 2138 switch (speed) { 2139 case FW_PORT_CAP_SPEED_100M: 2140 return (IFM_100_T); 2141 case FW_PORT_CAP_SPEED_1G: 2142 return (IFM_1000_T); 2143 case FW_PORT_CAP_SPEED_10G: 2144 return (IFM_10G_T); 2145 } 2146 break; 2147 case FW_PORT_TYPE_KX4: 2148 if (speed == FW_PORT_CAP_SPEED_10G) 2149 return (IFM_10G_KX4); 2150 break; 2151 case FW_PORT_TYPE_CX4: 2152 if (speed == FW_PORT_CAP_SPEED_10G) 2153 return (IFM_10G_CX4); 2154 break; 2155 case FW_PORT_TYPE_KX: 2156 if (speed == FW_PORT_CAP_SPEED_1G) 2157 return (IFM_1000_KX); 2158 break; 2159 case FW_PORT_TYPE_KR: 2160 case FW_PORT_TYPE_BP_AP: 2161 case FW_PORT_TYPE_BP4_AP: 2162 case FW_PORT_TYPE_BP40_BA: 2163 case FW_PORT_TYPE_KR4_100G: 2164 case FW_PORT_TYPE_KR_SFP28: 2165 case FW_PORT_TYPE_KR_XLAUI: 2166 switch (speed) { 2167 case FW_PORT_CAP_SPEED_1G: 2168 return (IFM_1000_KX); 2169 case FW_PORT_CAP_SPEED_10G: 2170 return (IFM_10G_KR); 2171 case FW_PORT_CAP_SPEED_25G: 2172 return (IFM_25G_KR); 2173 case FW_PORT_CAP_SPEED_40G: 2174 return (IFM_40G_KR4); 2175 case FW_PORT_CAP_SPEED_100G: 2176 return (IFM_100G_KR4); 2177 } 2178 break; 2179 case FW_PORT_TYPE_FIBER_XFI: 2180 case FW_PORT_TYPE_FIBER_XAUI: 2181 case FW_PORT_TYPE_SFP: 2182 case FW_PORT_TYPE_QSFP_10G: 2183 case FW_PORT_TYPE_QSA: 2184 case FW_PORT_TYPE_QSFP: 2185 case FW_PORT_TYPE_CR4_QSFP: 2186 case FW_PORT_TYPE_CR_QSFP: 2187 case FW_PORT_TYPE_CR2_QSFP: 2188 case FW_PORT_TYPE_SFP28: 2189 /* Pluggable transceiver */ 2190 switch (pi->mod_type) { 2191 case FW_PORT_MOD_TYPE_LR: 2192 switch (speed) { 2193 case FW_PORT_CAP_SPEED_1G: 2194 return (IFM_1000_LX); 2195 case FW_PORT_CAP_SPEED_10G: 2196 return (IFM_10G_LR); 2197 case FW_PORT_CAP_SPEED_25G: 2198 return (IFM_25G_LR); 2199 case FW_PORT_CAP_SPEED_40G: 2200 return (IFM_40G_LR4); 2201 case FW_PORT_CAP_SPEED_100G: 2202 return (IFM_100G_LR4); 2203 } 2204 break; 2205 case FW_PORT_MOD_TYPE_SR: 2206 switch (speed) { 2207 case FW_PORT_CAP_SPEED_1G: 2208 return (IFM_1000_SX); 2209 case FW_PORT_CAP_SPEED_10G: 2210 return (IFM_10G_SR); 2211 case FW_PORT_CAP_SPEED_25G: 2212 return (IFM_25G_SR); 2213 case FW_PORT_CAP_SPEED_40G: 2214 return (IFM_40G_SR4); 2215 case FW_PORT_CAP_SPEED_100G: 2216 return (IFM_100G_SR4); 2217 } 2218 break; 2219 case FW_PORT_MOD_TYPE_ER: 2220 if (speed == FW_PORT_CAP_SPEED_10G) 2221 return (IFM_10G_ER); 2222 break; 2223 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2224 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2225 switch (speed) { 2226 case FW_PORT_CAP_SPEED_1G: 2227 return (IFM_1000_CX); 2228 case FW_PORT_CAP_SPEED_10G: 2229 return (IFM_10G_TWINAX); 2230 case FW_PORT_CAP_SPEED_25G: 2231 return (IFM_25G_CR); 2232 case FW_PORT_CAP_SPEED_40G: 2233 return (IFM_40G_CR4); 2234 case FW_PORT_CAP_SPEED_100G: 2235 return (IFM_100G_CR4); 2236 } 2237 break; 2238 case FW_PORT_MOD_TYPE_LRM: 2239 if (speed == FW_PORT_CAP_SPEED_10G) 2240 return (IFM_10G_LRM); 2241 break; 2242 case FW_PORT_MOD_TYPE_NA: 2243 MPASS(0); /* Not pluggable? */ 2244 /* fall throough */ 2245 case FW_PORT_MOD_TYPE_ERROR: 2246 case FW_PORT_MOD_TYPE_UNKNOWN: 2247 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2248 break; 2249 case FW_PORT_MOD_TYPE_NONE: 2250 return (IFM_NONE); 2251 } 2252 break; 2253 case FW_PORT_TYPE_NONE: 2254 return (IFM_NONE); 2255 } 2256 2257 return (IFM_UNKNOWN); 2258 } 2259 2260 static void 2261 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2262 { 2263 struct vi_info *vi = ifp->if_softc; 2264 struct port_info *pi = vi->pi; 2265 struct adapter *sc = pi->adapter; 2266 struct link_config *lc = &pi->link_cfg; 2267 2268 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2269 return; 2270 PORT_LOCK(pi); 2271 2272 if (pi->up_vis == 0) { 2273 /* 2274 * If all the interfaces are administratively down the firmware 2275 * does not report transceiver changes. Refresh port info here 2276 * so that ifconfig displays accurate ifmedia at all times. 2277 * This is the only reason we have a synchronized op in this 2278 * function. Just PORT_LOCK would have been enough otherwise. 2279 */ 2280 t4_update_port_info(pi); 2281 build_medialist(pi, &pi->media); 2282 } 2283 2284 /* ifm_status */ 2285 ifmr->ifm_status = IFM_AVALID; 2286 if (lc->link_ok == 0) 2287 goto done; 2288 ifmr->ifm_status |= IFM_ACTIVE; 2289 2290 /* ifm_active */ 2291 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2292 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2293 if (lc->fc & PAUSE_RX) 2294 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2295 if (lc->fc & PAUSE_TX) 2296 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2297 ifmr->ifm_active |= port_mword(pi, speed_to_fwspeed(lc->speed)); 2298 done: 2299 PORT_UNLOCK(pi); 2300 end_synchronized_op(sc, 0); 2301 } 2302 2303 static int 2304 vcxgbe_probe(device_t dev) 2305 { 2306 char buf[128]; 2307 struct vi_info *vi = device_get_softc(dev); 2308 2309 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2310 vi - vi->pi->vi); 2311 device_set_desc_copy(dev, buf); 2312 2313 return (BUS_PROBE_DEFAULT); 2314 } 2315 2316 static int 2317 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2318 { 2319 int func, index, rc; 2320 uint32_t param, val; 2321 2322 ASSERT_SYNCHRONIZED_OP(sc); 2323 2324 index = vi - pi->vi; 2325 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2326 KASSERT(index < nitems(vi_mac_funcs), 2327 ("%s: VI %s doesn't have a MAC func", __func__, 2328 device_get_nameunit(vi->dev))); 2329 func = vi_mac_funcs[index]; 2330 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2331 vi->hw_addr, &vi->rss_size, func, 0); 2332 if (rc < 0) { 2333 device_printf(vi->dev, "failed to allocate virtual interface %d" 2334 "for port %d: %d\n", index, pi->port_id, -rc); 2335 return (-rc); 2336 } 2337 vi->viid = rc; 2338 if (chip_id(sc) <= CHELSIO_T5) 2339 vi->smt_idx = (rc & 0x7f) << 1; 2340 else 2341 vi->smt_idx = (rc & 0x7f); 2342 2343 if (vi->rss_size == 1) { 2344 /* 2345 * This VI didn't get a slice of the RSS table. Reduce the 2346 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2347 * configuration file (nvi, rssnvi for this PF) if this is a 2348 * problem. 2349 */ 2350 device_printf(vi->dev, "RSS table not available.\n"); 2351 vi->rss_base = 0xffff; 2352 2353 return (0); 2354 } 2355 2356 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2357 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2358 V_FW_PARAMS_PARAM_YZ(vi->viid); 2359 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2360 if (rc) 2361 vi->rss_base = 0xffff; 2362 else { 2363 MPASS((val >> 16) == vi->rss_size); 2364 vi->rss_base = val & 0xffff; 2365 } 2366 2367 return (0); 2368 } 2369 2370 static int 2371 vcxgbe_attach(device_t dev) 2372 { 2373 struct vi_info *vi; 2374 struct port_info *pi; 2375 struct adapter *sc; 2376 int rc; 2377 2378 vi = device_get_softc(dev); 2379 pi = vi->pi; 2380 sc = pi->adapter; 2381 2382 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2383 if (rc) 2384 return (rc); 2385 rc = alloc_extra_vi(sc, pi, vi); 2386 end_synchronized_op(sc, 0); 2387 if (rc) 2388 return (rc); 2389 2390 rc = cxgbe_vi_attach(dev, vi); 2391 if (rc) { 2392 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2393 return (rc); 2394 } 2395 return (0); 2396 } 2397 2398 static int 2399 vcxgbe_detach(device_t dev) 2400 { 2401 struct vi_info *vi; 2402 struct adapter *sc; 2403 2404 vi = device_get_softc(dev); 2405 sc = vi->pi->adapter; 2406 2407 doom_vi(sc, vi); 2408 2409 cxgbe_vi_detach(vi); 2410 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2411 2412 end_synchronized_op(sc, 0); 2413 2414 return (0); 2415 } 2416 2417 void 2418 t4_fatal_err(struct adapter *sc) 2419 { 2420 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2421 t4_intr_disable(sc); 2422 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2423 device_get_nameunit(sc->dev)); 2424 if (t4_panic_on_fatal_err) 2425 panic("panic requested on fatal error"); 2426 } 2427 2428 void 2429 t4_add_adapter(struct adapter *sc) 2430 { 2431 sx_xlock(&t4_list_lock); 2432 SLIST_INSERT_HEAD(&t4_list, sc, link); 2433 sx_xunlock(&t4_list_lock); 2434 } 2435 2436 int 2437 t4_map_bars_0_and_4(struct adapter *sc) 2438 { 2439 sc->regs_rid = PCIR_BAR(0); 2440 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2441 &sc->regs_rid, RF_ACTIVE); 2442 if (sc->regs_res == NULL) { 2443 device_printf(sc->dev, "cannot map registers.\n"); 2444 return (ENXIO); 2445 } 2446 sc->bt = rman_get_bustag(sc->regs_res); 2447 sc->bh = rman_get_bushandle(sc->regs_res); 2448 sc->mmio_len = rman_get_size(sc->regs_res); 2449 setbit(&sc->doorbells, DOORBELL_KDB); 2450 2451 sc->msix_rid = PCIR_BAR(4); 2452 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2453 &sc->msix_rid, RF_ACTIVE); 2454 if (sc->msix_res == NULL) { 2455 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2456 return (ENXIO); 2457 } 2458 2459 return (0); 2460 } 2461 2462 int 2463 t4_map_bar_2(struct adapter *sc) 2464 { 2465 2466 /* 2467 * T4: only iWARP driver uses the userspace doorbells. There is no need 2468 * to map it if RDMA is disabled. 2469 */ 2470 if (is_t4(sc) && sc->rdmacaps == 0) 2471 return (0); 2472 2473 sc->udbs_rid = PCIR_BAR(2); 2474 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2475 &sc->udbs_rid, RF_ACTIVE); 2476 if (sc->udbs_res == NULL) { 2477 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2478 return (ENXIO); 2479 } 2480 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2481 2482 if (chip_id(sc) >= CHELSIO_T5) { 2483 setbit(&sc->doorbells, DOORBELL_UDB); 2484 #if defined(__i386__) || defined(__amd64__) 2485 if (t5_write_combine) { 2486 int rc, mode; 2487 2488 /* 2489 * Enable write combining on BAR2. This is the 2490 * userspace doorbell BAR and is split into 128B 2491 * (UDBS_SEG_SIZE) doorbell regions, each associated 2492 * with an egress queue. The first 64B has the doorbell 2493 * and the second 64B can be used to submit a tx work 2494 * request with an implicit doorbell. 2495 */ 2496 2497 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2498 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2499 if (rc == 0) { 2500 clrbit(&sc->doorbells, DOORBELL_UDB); 2501 setbit(&sc->doorbells, DOORBELL_WCWR); 2502 setbit(&sc->doorbells, DOORBELL_UDBWC); 2503 } else { 2504 device_printf(sc->dev, 2505 "couldn't enable write combining: %d\n", 2506 rc); 2507 } 2508 2509 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2510 t4_write_reg(sc, A_SGE_STAT_CFG, 2511 V_STATSOURCE_T5(7) | mode); 2512 } 2513 #endif 2514 } 2515 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2516 2517 return (0); 2518 } 2519 2520 struct memwin_init { 2521 uint32_t base; 2522 uint32_t aperture; 2523 }; 2524 2525 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2526 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2527 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2528 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2529 }; 2530 2531 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2532 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2533 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2534 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2535 }; 2536 2537 static void 2538 setup_memwin(struct adapter *sc) 2539 { 2540 const struct memwin_init *mw_init; 2541 struct memwin *mw; 2542 int i; 2543 uint32_t bar0; 2544 2545 if (is_t4(sc)) { 2546 /* 2547 * Read low 32b of bar0 indirectly via the hardware backdoor 2548 * mechanism. Works from within PCI passthrough environments 2549 * too, where rman_get_start() can return a different value. We 2550 * need to program the T4 memory window decoders with the actual 2551 * addresses that will be coming across the PCIe link. 2552 */ 2553 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2554 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2555 2556 mw_init = &t4_memwin[0]; 2557 } else { 2558 /* T5+ use the relative offset inside the PCIe BAR */ 2559 bar0 = 0; 2560 2561 mw_init = &t5_memwin[0]; 2562 } 2563 2564 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2565 rw_init(&mw->mw_lock, "memory window access"); 2566 mw->mw_base = mw_init->base; 2567 mw->mw_aperture = mw_init->aperture; 2568 mw->mw_curpos = 0; 2569 t4_write_reg(sc, 2570 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2571 (mw->mw_base + bar0) | V_BIR(0) | 2572 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2573 rw_wlock(&mw->mw_lock); 2574 position_memwin(sc, i, 0); 2575 rw_wunlock(&mw->mw_lock); 2576 } 2577 2578 /* flush */ 2579 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2580 } 2581 2582 /* 2583 * Positions the memory window at the given address in the card's address space. 2584 * There are some alignment requirements and the actual position may be at an 2585 * address prior to the requested address. mw->mw_curpos always has the actual 2586 * position of the window. 2587 */ 2588 static void 2589 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2590 { 2591 struct memwin *mw; 2592 uint32_t pf; 2593 uint32_t reg; 2594 2595 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2596 mw = &sc->memwin[idx]; 2597 rw_assert(&mw->mw_lock, RA_WLOCKED); 2598 2599 if (is_t4(sc)) { 2600 pf = 0; 2601 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2602 } else { 2603 pf = V_PFNUM(sc->pf); 2604 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2605 } 2606 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2607 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2608 t4_read_reg(sc, reg); /* flush */ 2609 } 2610 2611 int 2612 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2613 int len, int rw) 2614 { 2615 struct memwin *mw; 2616 uint32_t mw_end, v; 2617 2618 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2619 2620 /* Memory can only be accessed in naturally aligned 4 byte units */ 2621 if (addr & 3 || len & 3 || len <= 0) 2622 return (EINVAL); 2623 2624 mw = &sc->memwin[idx]; 2625 while (len > 0) { 2626 rw_rlock(&mw->mw_lock); 2627 mw_end = mw->mw_curpos + mw->mw_aperture; 2628 if (addr >= mw_end || addr < mw->mw_curpos) { 2629 /* Will need to reposition the window */ 2630 if (!rw_try_upgrade(&mw->mw_lock)) { 2631 rw_runlock(&mw->mw_lock); 2632 rw_wlock(&mw->mw_lock); 2633 } 2634 rw_assert(&mw->mw_lock, RA_WLOCKED); 2635 position_memwin(sc, idx, addr); 2636 rw_downgrade(&mw->mw_lock); 2637 mw_end = mw->mw_curpos + mw->mw_aperture; 2638 } 2639 rw_assert(&mw->mw_lock, RA_RLOCKED); 2640 while (addr < mw_end && len > 0) { 2641 if (rw == 0) { 2642 v = t4_read_reg(sc, mw->mw_base + addr - 2643 mw->mw_curpos); 2644 *val++ = le32toh(v); 2645 } else { 2646 v = *val++; 2647 t4_write_reg(sc, mw->mw_base + addr - 2648 mw->mw_curpos, htole32(v)); 2649 } 2650 addr += 4; 2651 len -= 4; 2652 } 2653 rw_runlock(&mw->mw_lock); 2654 } 2655 2656 return (0); 2657 } 2658 2659 int 2660 alloc_atid_tab(struct tid_info *t, int flags) 2661 { 2662 int i; 2663 2664 MPASS(t->natids > 0); 2665 MPASS(t->atid_tab == NULL); 2666 2667 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2668 M_ZERO | flags); 2669 if (t->atid_tab == NULL) 2670 return (ENOMEM); 2671 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2672 t->afree = t->atid_tab; 2673 t->atids_in_use = 0; 2674 for (i = 1; i < t->natids; i++) 2675 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2676 t->atid_tab[t->natids - 1].next = NULL; 2677 2678 return (0); 2679 } 2680 2681 void 2682 free_atid_tab(struct tid_info *t) 2683 { 2684 2685 KASSERT(t->atids_in_use == 0, 2686 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2687 2688 if (mtx_initialized(&t->atid_lock)) 2689 mtx_destroy(&t->atid_lock); 2690 free(t->atid_tab, M_CXGBE); 2691 t->atid_tab = NULL; 2692 } 2693 2694 int 2695 alloc_atid(struct adapter *sc, void *ctx) 2696 { 2697 struct tid_info *t = &sc->tids; 2698 int atid = -1; 2699 2700 mtx_lock(&t->atid_lock); 2701 if (t->afree) { 2702 union aopen_entry *p = t->afree; 2703 2704 atid = p - t->atid_tab; 2705 MPASS(atid <= M_TID_TID); 2706 t->afree = p->next; 2707 p->data = ctx; 2708 t->atids_in_use++; 2709 } 2710 mtx_unlock(&t->atid_lock); 2711 return (atid); 2712 } 2713 2714 void * 2715 lookup_atid(struct adapter *sc, int atid) 2716 { 2717 struct tid_info *t = &sc->tids; 2718 2719 return (t->atid_tab[atid].data); 2720 } 2721 2722 void 2723 free_atid(struct adapter *sc, int atid) 2724 { 2725 struct tid_info *t = &sc->tids; 2726 union aopen_entry *p = &t->atid_tab[atid]; 2727 2728 mtx_lock(&t->atid_lock); 2729 p->next = t->afree; 2730 t->afree = p; 2731 t->atids_in_use--; 2732 mtx_unlock(&t->atid_lock); 2733 } 2734 2735 static void 2736 queue_tid_release(struct adapter *sc, int tid) 2737 { 2738 2739 CXGBE_UNIMPLEMENTED("deferred tid release"); 2740 } 2741 2742 void 2743 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2744 { 2745 struct wrqe *wr; 2746 struct cpl_tid_release *req; 2747 2748 wr = alloc_wrqe(sizeof(*req), ctrlq); 2749 if (wr == NULL) { 2750 queue_tid_release(sc, tid); /* defer */ 2751 return; 2752 } 2753 req = wrtod(wr); 2754 2755 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2756 2757 t4_wrq_tx(sc, wr); 2758 } 2759 2760 static int 2761 t4_range_cmp(const void *a, const void *b) 2762 { 2763 return ((const struct t4_range *)a)->start - 2764 ((const struct t4_range *)b)->start; 2765 } 2766 2767 /* 2768 * Verify that the memory range specified by the addr/len pair is valid within 2769 * the card's address space. 2770 */ 2771 static int 2772 validate_mem_range(struct adapter *sc, uint32_t addr, int len) 2773 { 2774 struct t4_range mem_ranges[4], *r, *next; 2775 uint32_t em, addr_len; 2776 int i, n, remaining; 2777 2778 /* Memory can only be accessed in naturally aligned 4 byte units */ 2779 if (addr & 3 || len & 3 || len <= 0) 2780 return (EINVAL); 2781 2782 /* Enabled memories */ 2783 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2784 2785 r = &mem_ranges[0]; 2786 n = 0; 2787 bzero(r, sizeof(mem_ranges)); 2788 if (em & F_EDRAM0_ENABLE) { 2789 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2790 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2791 if (r->size > 0) { 2792 r->start = G_EDRAM0_BASE(addr_len) << 20; 2793 if (addr >= r->start && 2794 addr + len <= r->start + r->size) 2795 return (0); 2796 r++; 2797 n++; 2798 } 2799 } 2800 if (em & F_EDRAM1_ENABLE) { 2801 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2802 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2803 if (r->size > 0) { 2804 r->start = G_EDRAM1_BASE(addr_len) << 20; 2805 if (addr >= r->start && 2806 addr + len <= r->start + r->size) 2807 return (0); 2808 r++; 2809 n++; 2810 } 2811 } 2812 if (em & F_EXT_MEM_ENABLE) { 2813 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2814 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2815 if (r->size > 0) { 2816 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2817 if (addr >= r->start && 2818 addr + len <= r->start + r->size) 2819 return (0); 2820 r++; 2821 n++; 2822 } 2823 } 2824 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2825 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2826 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2827 if (r->size > 0) { 2828 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2829 if (addr >= r->start && 2830 addr + len <= r->start + r->size) 2831 return (0); 2832 r++; 2833 n++; 2834 } 2835 } 2836 MPASS(n <= nitems(mem_ranges)); 2837 2838 if (n > 1) { 2839 /* Sort and merge the ranges. */ 2840 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2841 2842 /* Start from index 0 and examine the next n - 1 entries. */ 2843 r = &mem_ranges[0]; 2844 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2845 2846 MPASS(r->size > 0); /* r is a valid entry. */ 2847 next = r + 1; 2848 MPASS(next->size > 0); /* and so is the next one. */ 2849 2850 while (r->start + r->size >= next->start) { 2851 /* Merge the next one into the current entry. */ 2852 r->size = max(r->start + r->size, 2853 next->start + next->size) - r->start; 2854 n--; /* One fewer entry in total. */ 2855 if (--remaining == 0) 2856 goto done; /* short circuit */ 2857 next++; 2858 } 2859 if (next != r + 1) { 2860 /* 2861 * Some entries were merged into r and next 2862 * points to the first valid entry that couldn't 2863 * be merged. 2864 */ 2865 MPASS(next->size > 0); /* must be valid */ 2866 memcpy(r + 1, next, remaining * sizeof(*r)); 2867 #ifdef INVARIANTS 2868 /* 2869 * This so that the foo->size assertion in the 2870 * next iteration of the loop do the right 2871 * thing for entries that were pulled up and are 2872 * no longer valid. 2873 */ 2874 MPASS(n < nitems(mem_ranges)); 2875 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2876 sizeof(struct t4_range)); 2877 #endif 2878 } 2879 } 2880 done: 2881 /* Done merging the ranges. */ 2882 MPASS(n > 0); 2883 r = &mem_ranges[0]; 2884 for (i = 0; i < n; i++, r++) { 2885 if (addr >= r->start && 2886 addr + len <= r->start + r->size) 2887 return (0); 2888 } 2889 } 2890 2891 return (EFAULT); 2892 } 2893 2894 static int 2895 fwmtype_to_hwmtype(int mtype) 2896 { 2897 2898 switch (mtype) { 2899 case FW_MEMTYPE_EDC0: 2900 return (MEM_EDC0); 2901 case FW_MEMTYPE_EDC1: 2902 return (MEM_EDC1); 2903 case FW_MEMTYPE_EXTMEM: 2904 return (MEM_MC0); 2905 case FW_MEMTYPE_EXTMEM1: 2906 return (MEM_MC1); 2907 default: 2908 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2909 } 2910 } 2911 2912 /* 2913 * Verify that the memory range specified by the memtype/offset/len pair is 2914 * valid and lies entirely within the memtype specified. The global address of 2915 * the start of the range is returned in addr. 2916 */ 2917 static int 2918 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 2919 uint32_t *addr) 2920 { 2921 uint32_t em, addr_len, maddr; 2922 2923 /* Memory can only be accessed in naturally aligned 4 byte units */ 2924 if (off & 3 || len & 3 || len == 0) 2925 return (EINVAL); 2926 2927 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2928 switch (fwmtype_to_hwmtype(mtype)) { 2929 case MEM_EDC0: 2930 if (!(em & F_EDRAM0_ENABLE)) 2931 return (EINVAL); 2932 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2933 maddr = G_EDRAM0_BASE(addr_len) << 20; 2934 break; 2935 case MEM_EDC1: 2936 if (!(em & F_EDRAM1_ENABLE)) 2937 return (EINVAL); 2938 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2939 maddr = G_EDRAM1_BASE(addr_len) << 20; 2940 break; 2941 case MEM_MC: 2942 if (!(em & F_EXT_MEM_ENABLE)) 2943 return (EINVAL); 2944 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2945 maddr = G_EXT_MEM_BASE(addr_len) << 20; 2946 break; 2947 case MEM_MC1: 2948 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 2949 return (EINVAL); 2950 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2951 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 2952 break; 2953 default: 2954 return (EINVAL); 2955 } 2956 2957 *addr = maddr + off; /* global address */ 2958 return (validate_mem_range(sc, *addr, len)); 2959 } 2960 2961 static int 2962 fixup_devlog_params(struct adapter *sc) 2963 { 2964 struct devlog_params *dparams = &sc->params.devlog; 2965 int rc; 2966 2967 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 2968 dparams->size, &dparams->addr); 2969 2970 return (rc); 2971 } 2972 2973 static void 2974 update_nirq(struct intrs_and_queues *iaq, int nports) 2975 { 2976 int extra = T4_EXTRA_INTR; 2977 2978 iaq->nirq = extra; 2979 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 2980 iaq->nirq += nports * (iaq->num_vis - 1) * 2981 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 2982 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 2983 } 2984 2985 /* 2986 * Adjust requirements to fit the number of interrupts available. 2987 */ 2988 static void 2989 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 2990 int navail) 2991 { 2992 int old_nirq; 2993 const int nports = sc->params.nports; 2994 2995 MPASS(nports > 0); 2996 MPASS(navail > 0); 2997 2998 bzero(iaq, sizeof(*iaq)); 2999 iaq->intr_type = itype; 3000 iaq->num_vis = t4_num_vis; 3001 iaq->ntxq = t4_ntxq; 3002 iaq->ntxq_vi = t4_ntxq_vi; 3003 iaq->nrxq = t4_nrxq; 3004 iaq->nrxq_vi = t4_nrxq_vi; 3005 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3006 if (is_offload(sc) || is_ethoffload(sc)) { 3007 iaq->nofldtxq = t4_nofldtxq; 3008 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3009 } 3010 #endif 3011 #ifdef TCP_OFFLOAD 3012 if (is_offload(sc)) { 3013 iaq->nofldrxq = t4_nofldrxq; 3014 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3015 } 3016 #endif 3017 #ifdef DEV_NETMAP 3018 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3019 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3020 #endif 3021 3022 update_nirq(iaq, nports); 3023 if (iaq->nirq <= navail && 3024 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3025 /* 3026 * This is the normal case -- there are enough interrupts for 3027 * everything. 3028 */ 3029 goto done; 3030 } 3031 3032 /* 3033 * If extra VIs have been configured try reducing their count and see if 3034 * that works. 3035 */ 3036 while (iaq->num_vis > 1) { 3037 iaq->num_vis--; 3038 update_nirq(iaq, nports); 3039 if (iaq->nirq <= navail && 3040 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3041 device_printf(sc->dev, "virtual interfaces per port " 3042 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3043 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3044 "itype %d, navail %u, nirq %d.\n", 3045 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3046 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3047 itype, navail, iaq->nirq); 3048 goto done; 3049 } 3050 } 3051 3052 /* 3053 * Extra VIs will not be created. Log a message if they were requested. 3054 */ 3055 MPASS(iaq->num_vis == 1); 3056 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3057 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3058 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3059 if (iaq->num_vis != t4_num_vis) { 3060 device_printf(sc->dev, "extra virtual interfaces disabled. " 3061 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3062 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3063 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3064 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3065 } 3066 3067 /* 3068 * Keep reducing the number of NIC rx queues to the next lower power of 3069 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3070 * if that works. 3071 */ 3072 do { 3073 if (iaq->nrxq > 1) { 3074 do { 3075 iaq->nrxq--; 3076 } while (!powerof2(iaq->nrxq)); 3077 } 3078 if (iaq->nofldrxq > 1) 3079 iaq->nofldrxq >>= 1; 3080 3081 old_nirq = iaq->nirq; 3082 update_nirq(iaq, nports); 3083 if (iaq->nirq <= navail && 3084 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3085 device_printf(sc->dev, "running with reduced number of " 3086 "rx queues because of shortage of interrupts. " 3087 "nrxq=%u, nofldrxq=%u. " 3088 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3089 iaq->nofldrxq, itype, navail, iaq->nirq); 3090 goto done; 3091 } 3092 } while (old_nirq != iaq->nirq); 3093 3094 /* One interrupt for everything. Ugh. */ 3095 device_printf(sc->dev, "running with minimal number of queues. " 3096 "itype %d, navail %u.\n", itype, navail); 3097 iaq->nirq = 1; 3098 MPASS(iaq->nrxq == 1); 3099 iaq->ntxq = 1; 3100 if (iaq->nofldrxq > 1) 3101 iaq->nofldtxq = 1; 3102 done: 3103 MPASS(iaq->num_vis > 0); 3104 if (iaq->num_vis > 1) { 3105 MPASS(iaq->nrxq_vi > 0); 3106 MPASS(iaq->ntxq_vi > 0); 3107 } 3108 MPASS(iaq->nirq > 0); 3109 MPASS(iaq->nrxq > 0); 3110 MPASS(iaq->ntxq > 0); 3111 if (itype == INTR_MSI) { 3112 MPASS(powerof2(iaq->nirq)); 3113 } 3114 } 3115 3116 static int 3117 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3118 { 3119 int rc, itype, navail, nalloc; 3120 3121 for (itype = INTR_MSIX; itype; itype >>= 1) { 3122 3123 if ((itype & t4_intr_types) == 0) 3124 continue; /* not allowed */ 3125 3126 if (itype == INTR_MSIX) 3127 navail = pci_msix_count(sc->dev); 3128 else if (itype == INTR_MSI) 3129 navail = pci_msi_count(sc->dev); 3130 else 3131 navail = 1; 3132 restart: 3133 if (navail == 0) 3134 continue; 3135 3136 calculate_iaq(sc, iaq, itype, navail); 3137 nalloc = iaq->nirq; 3138 rc = 0; 3139 if (itype == INTR_MSIX) 3140 rc = pci_alloc_msix(sc->dev, &nalloc); 3141 else if (itype == INTR_MSI) 3142 rc = pci_alloc_msi(sc->dev, &nalloc); 3143 3144 if (rc == 0 && nalloc > 0) { 3145 if (nalloc == iaq->nirq) 3146 return (0); 3147 3148 /* 3149 * Didn't get the number requested. Use whatever number 3150 * the kernel is willing to allocate. 3151 */ 3152 device_printf(sc->dev, "fewer vectors than requested, " 3153 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3154 itype, iaq->nirq, nalloc); 3155 pci_release_msi(sc->dev); 3156 navail = nalloc; 3157 goto restart; 3158 } 3159 3160 device_printf(sc->dev, 3161 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3162 itype, rc, iaq->nirq, nalloc); 3163 } 3164 3165 device_printf(sc->dev, 3166 "failed to find a usable interrupt type. " 3167 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3168 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3169 3170 return (ENXIO); 3171 } 3172 3173 #define FW_VERSION(chip) ( \ 3174 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3175 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3176 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3177 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3178 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3179 3180 struct fw_info { 3181 uint8_t chip; 3182 char *kld_name; 3183 char *fw_mod_name; 3184 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 3185 } fw_info[] = { 3186 { 3187 .chip = CHELSIO_T4, 3188 .kld_name = "t4fw_cfg", 3189 .fw_mod_name = "t4fw", 3190 .fw_hdr = { 3191 .chip = FW_HDR_CHIP_T4, 3192 .fw_ver = htobe32(FW_VERSION(T4)), 3193 .intfver_nic = FW_INTFVER(T4, NIC), 3194 .intfver_vnic = FW_INTFVER(T4, VNIC), 3195 .intfver_ofld = FW_INTFVER(T4, OFLD), 3196 .intfver_ri = FW_INTFVER(T4, RI), 3197 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3198 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3199 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3200 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3201 }, 3202 }, { 3203 .chip = CHELSIO_T5, 3204 .kld_name = "t5fw_cfg", 3205 .fw_mod_name = "t5fw", 3206 .fw_hdr = { 3207 .chip = FW_HDR_CHIP_T5, 3208 .fw_ver = htobe32(FW_VERSION(T5)), 3209 .intfver_nic = FW_INTFVER(T5, NIC), 3210 .intfver_vnic = FW_INTFVER(T5, VNIC), 3211 .intfver_ofld = FW_INTFVER(T5, OFLD), 3212 .intfver_ri = FW_INTFVER(T5, RI), 3213 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3214 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3215 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3216 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3217 }, 3218 }, { 3219 .chip = CHELSIO_T6, 3220 .kld_name = "t6fw_cfg", 3221 .fw_mod_name = "t6fw", 3222 .fw_hdr = { 3223 .chip = FW_HDR_CHIP_T6, 3224 .fw_ver = htobe32(FW_VERSION(T6)), 3225 .intfver_nic = FW_INTFVER(T6, NIC), 3226 .intfver_vnic = FW_INTFVER(T6, VNIC), 3227 .intfver_ofld = FW_INTFVER(T6, OFLD), 3228 .intfver_ri = FW_INTFVER(T6, RI), 3229 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3230 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3231 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3232 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3233 }, 3234 } 3235 }; 3236 3237 static struct fw_info * 3238 find_fw_info(int chip) 3239 { 3240 int i; 3241 3242 for (i = 0; i < nitems(fw_info); i++) { 3243 if (fw_info[i].chip == chip) 3244 return (&fw_info[i]); 3245 } 3246 return (NULL); 3247 } 3248 3249 /* 3250 * Is the given firmware API compatible with the one the driver was compiled 3251 * with? 3252 */ 3253 static int 3254 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 3255 { 3256 3257 /* short circuit if it's the exact same firmware version */ 3258 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3259 return (1); 3260 3261 /* 3262 * XXX: Is this too conservative? Perhaps I should limit this to the 3263 * features that are supported in the driver. 3264 */ 3265 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3266 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3267 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3268 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3269 return (1); 3270 #undef SAME_INTF 3271 3272 return (0); 3273 } 3274 3275 /* 3276 * The firmware in the KLD is usable, but should it be installed? This routine 3277 * explains itself in detail if it indicates the KLD firmware should be 3278 * installed. 3279 */ 3280 static int 3281 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 3282 { 3283 const char *reason; 3284 3285 if (!card_fw_usable) { 3286 reason = "incompatible or unusable"; 3287 goto install; 3288 } 3289 3290 if (k > c) { 3291 reason = "older than the version bundled with this driver"; 3292 goto install; 3293 } 3294 3295 if (t4_fw_install == 2 && k != c) { 3296 reason = "different than the version bundled with this driver"; 3297 goto install; 3298 } 3299 3300 return (0); 3301 3302 install: 3303 if (t4_fw_install == 0) { 3304 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3305 "but the driver is prohibited from installing a different " 3306 "firmware on the card.\n", 3307 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3308 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3309 3310 return (0); 3311 } 3312 3313 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3314 "installing firmware %u.%u.%u.%u on card.\n", 3315 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3316 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3317 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3318 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3319 3320 return (1); 3321 } 3322 3323 /* 3324 * Establish contact with the firmware and determine if we are the master driver 3325 * or not, and whether we are responsible for chip initialization. 3326 */ 3327 static int 3328 prep_firmware(struct adapter *sc) 3329 { 3330 const struct firmware *fw = NULL, *default_cfg; 3331 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 3332 enum dev_state state; 3333 struct fw_info *fw_info; 3334 struct fw_hdr *card_fw; /* fw on the card */ 3335 const struct fw_hdr *kld_fw; /* fw in the KLD */ 3336 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 3337 against */ 3338 3339 /* This is the firmware whose headers the driver was compiled against */ 3340 fw_info = find_fw_info(chip_id(sc)); 3341 if (fw_info == NULL) { 3342 device_printf(sc->dev, 3343 "unable to look up firmware information for chip %d.\n", 3344 chip_id(sc)); 3345 return (EINVAL); 3346 } 3347 drv_fw = &fw_info->fw_hdr; 3348 3349 /* 3350 * The firmware KLD contains many modules. The KLD name is also the 3351 * name of the module that contains the default config file. 3352 */ 3353 default_cfg = firmware_get(fw_info->kld_name); 3354 3355 /* This is the firmware in the KLD */ 3356 fw = firmware_get(fw_info->fw_mod_name); 3357 if (fw != NULL) { 3358 kld_fw = (const void *)fw->data; 3359 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 3360 } else { 3361 kld_fw = NULL; 3362 kld_fw_usable = 0; 3363 } 3364 3365 /* Read the header of the firmware on the card */ 3366 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3367 rc = -t4_read_flash(sc, FLASH_FW_START, 3368 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 3369 if (rc == 0) { 3370 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 3371 if (card_fw->fw_ver == be32toh(0xffffffff)) { 3372 uint32_t d = be32toh(kld_fw->fw_ver); 3373 3374 if (!kld_fw_usable) { 3375 device_printf(sc->dev, 3376 "no firmware on the card and no usable " 3377 "firmware bundled with the driver.\n"); 3378 rc = EIO; 3379 goto done; 3380 } else if (t4_fw_install == 0) { 3381 device_printf(sc->dev, 3382 "no firmware on the card and the driver " 3383 "is prohibited from installing new " 3384 "firmware.\n"); 3385 rc = EIO; 3386 goto done; 3387 } 3388 3389 device_printf(sc->dev, "no firmware on the card, " 3390 "installing firmware %d.%d.%d.%d\n", 3391 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3392 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3393 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize); 3394 if (rc < 0) { 3395 rc = -rc; 3396 device_printf(sc->dev, 3397 "firmware install failed: %d.\n", rc); 3398 goto done; 3399 } 3400 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3401 card_fw_usable = 1; 3402 need_fw_reset = 0; 3403 } 3404 } else { 3405 device_printf(sc->dev, 3406 "Unable to read card's firmware header: %d\n", rc); 3407 card_fw_usable = 0; 3408 } 3409 3410 /* Contact firmware. */ 3411 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3412 if (rc < 0 || state == DEV_STATE_ERR) { 3413 rc = -rc; 3414 device_printf(sc->dev, 3415 "failed to connect to the firmware: %d, %d.\n", rc, state); 3416 goto done; 3417 } 3418 pf = rc; 3419 if (pf == sc->mbox) 3420 sc->flags |= MASTER_PF; 3421 else if (state == DEV_STATE_UNINIT) { 3422 /* 3423 * We didn't get to be the master so we definitely won't be 3424 * configuring the chip. It's a bug if someone else hasn't 3425 * configured it already. 3426 */ 3427 device_printf(sc->dev, "couldn't be master(%d), " 3428 "device not already initialized either(%d).\n", rc, state); 3429 rc = EPROTO; 3430 goto done; 3431 } 3432 3433 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 3434 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 3435 /* 3436 * Common case: the firmware on the card is an exact match and 3437 * the KLD is an exact match too, or the KLD is 3438 * absent/incompatible. Note that t4_fw_install = 2 is ignored 3439 * here -- use cxgbetool loadfw if you want to reinstall the 3440 * same firmware as the one on the card. 3441 */ 3442 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 3443 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 3444 be32toh(card_fw->fw_ver))) { 3445 3446 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3447 if (rc != 0) { 3448 device_printf(sc->dev, 3449 "failed to install firmware: %d\n", rc); 3450 goto done; 3451 } 3452 3453 /* Installed successfully, update the cached header too. */ 3454 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3455 card_fw_usable = 1; 3456 need_fw_reset = 0; /* already reset as part of load_fw */ 3457 } 3458 3459 if (!card_fw_usable) { 3460 uint32_t d, c, k; 3461 3462 d = ntohl(drv_fw->fw_ver); 3463 c = ntohl(card_fw->fw_ver); 3464 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3465 3466 device_printf(sc->dev, "Cannot find a usable firmware: " 3467 "fw_install %d, chip state %d, " 3468 "driver compiled with %d.%d.%d.%d, " 3469 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3470 t4_fw_install, state, 3471 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3472 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3473 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3474 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3475 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3476 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3477 rc = EINVAL; 3478 goto done; 3479 } 3480 3481 /* Reset device */ 3482 if (need_fw_reset && 3483 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3484 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3485 if (rc != ETIMEDOUT && rc != EIO) 3486 t4_fw_bye(sc, sc->mbox); 3487 goto done; 3488 } 3489 sc->flags |= FW_OK; 3490 3491 rc = get_params__pre_init(sc); 3492 if (rc != 0) 3493 goto done; /* error message displayed already */ 3494 3495 /* Partition adapter resources as specified in the config file. */ 3496 if (state == DEV_STATE_UNINIT) { 3497 3498 KASSERT(sc->flags & MASTER_PF, 3499 ("%s: trying to change chip settings when not master.", 3500 __func__)); 3501 3502 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3503 if (rc != 0) 3504 goto done; /* error message displayed already */ 3505 3506 t4_tweak_chip_settings(sc); 3507 3508 /* get basic stuff going */ 3509 rc = -t4_fw_initialize(sc, sc->mbox); 3510 if (rc != 0) { 3511 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3512 goto done; 3513 } 3514 } else { 3515 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3516 sc->cfcsum = 0; 3517 } 3518 3519 done: 3520 free(card_fw, M_CXGBE); 3521 if (fw != NULL) 3522 firmware_put(fw, FIRMWARE_UNLOAD); 3523 if (default_cfg != NULL) 3524 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3525 3526 return (rc); 3527 } 3528 3529 #define FW_PARAM_DEV(param) \ 3530 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3531 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3532 #define FW_PARAM_PFVF(param) \ 3533 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3534 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3535 3536 /* 3537 * Partition chip resources for use between various PFs, VFs, etc. 3538 */ 3539 static int 3540 partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3541 const char *name_prefix) 3542 { 3543 const struct firmware *cfg = NULL; 3544 int rc = 0; 3545 struct fw_caps_config_cmd caps; 3546 uint32_t mtype, moff, finicsum, cfcsum; 3547 3548 /* 3549 * Figure out what configuration file to use. Pick the default config 3550 * file for the card if the user hasn't specified one explicitly. 3551 */ 3552 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3553 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3554 /* Card specific overrides go here. */ 3555 if (pci_get_device(sc->dev) == 0x440a) 3556 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3557 if (is_fpga(sc)) 3558 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3559 } else if (strncmp(t4_cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) 3560 goto use_built_in_config; /* go straight to config. */ 3561 3562 /* 3563 * We need to load another module if the profile is anything except 3564 * "default" or "flash". 3565 */ 3566 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3567 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3568 char s[32]; 3569 3570 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3571 cfg = firmware_get(s); 3572 if (cfg == NULL) { 3573 if (default_cfg != NULL) { 3574 device_printf(sc->dev, 3575 "unable to load module \"%s\" for " 3576 "configuration profile \"%s\", will use " 3577 "the default config file instead.\n", 3578 s, sc->cfg_file); 3579 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3580 "%s", DEFAULT_CF); 3581 } else { 3582 device_printf(sc->dev, 3583 "unable to load module \"%s\" for " 3584 "configuration profile \"%s\", will use " 3585 "the config file on the card's flash " 3586 "instead.\n", s, sc->cfg_file); 3587 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3588 "%s", FLASH_CF); 3589 } 3590 } 3591 } 3592 3593 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3594 default_cfg == NULL) { 3595 device_printf(sc->dev, 3596 "default config file not available, will use the config " 3597 "file on the card's flash instead.\n"); 3598 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3599 } 3600 3601 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3602 u_int cflen; 3603 const uint32_t *cfdata; 3604 uint32_t param, val, addr; 3605 3606 KASSERT(cfg != NULL || default_cfg != NULL, 3607 ("%s: no config to upload", __func__)); 3608 3609 /* 3610 * Ask the firmware where it wants us to upload the config file. 3611 */ 3612 param = FW_PARAM_DEV(CF); 3613 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3614 if (rc != 0) { 3615 /* No support for config file? Shouldn't happen. */ 3616 device_printf(sc->dev, 3617 "failed to query config file location: %d.\n", rc); 3618 goto done; 3619 } 3620 mtype = G_FW_PARAMS_PARAM_Y(val); 3621 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3622 3623 /* 3624 * XXX: sheer laziness. We deliberately added 4 bytes of 3625 * useless stuffing/comments at the end of the config file so 3626 * it's ok to simply throw away the last remaining bytes when 3627 * the config file is not an exact multiple of 4. This also 3628 * helps with the validate_mt_off_len check. 3629 */ 3630 if (cfg != NULL) { 3631 cflen = cfg->datasize & ~3; 3632 cfdata = cfg->data; 3633 } else { 3634 cflen = default_cfg->datasize & ~3; 3635 cfdata = default_cfg->data; 3636 } 3637 3638 if (cflen > FLASH_CFG_MAX_SIZE) { 3639 device_printf(sc->dev, 3640 "config file too long (%d, max allowed is %d). " 3641 "Will try to use the config on the card, if any.\n", 3642 cflen, FLASH_CFG_MAX_SIZE); 3643 goto use_config_on_flash; 3644 } 3645 3646 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3647 if (rc != 0) { 3648 device_printf(sc->dev, 3649 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3650 "Will try to use the config on the card, if any.\n", 3651 __func__, mtype, moff, cflen, rc); 3652 goto use_config_on_flash; 3653 } 3654 write_via_memwin(sc, 2, addr, cfdata, cflen); 3655 } else { 3656 use_config_on_flash: 3657 mtype = FW_MEMTYPE_FLASH; 3658 moff = t4_flash_cfg_addr(sc); 3659 } 3660 3661 bzero(&caps, sizeof(caps)); 3662 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3663 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3664 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3665 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3666 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3667 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3668 if (rc != 0) { 3669 device_printf(sc->dev, 3670 "failed to pre-process config file: %d " 3671 "(mtype %d, moff 0x%x). Will reset the firmware and retry " 3672 "with the built-in configuration.\n", rc, mtype, moff); 3673 3674 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3675 if (rc != 0) { 3676 device_printf(sc->dev, 3677 "firmware reset failed: %d.\n", rc); 3678 if (rc != ETIMEDOUT && rc != EIO) { 3679 t4_fw_bye(sc, sc->mbox); 3680 sc->flags &= ~FW_OK; 3681 } 3682 goto done; 3683 } 3684 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "built-in"); 3685 use_built_in_config: 3686 bzero(&caps, sizeof(caps)); 3687 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3688 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3689 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3690 rc = t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3691 if (rc != 0) { 3692 device_printf(sc->dev, 3693 "built-in configuration failed: %d.\n", rc); 3694 goto done; 3695 } 3696 } 3697 3698 finicsum = be32toh(caps.finicsum); 3699 cfcsum = be32toh(caps.cfcsum); 3700 if (finicsum != cfcsum) { 3701 device_printf(sc->dev, 3702 "WARNING: config file checksum mismatch: %08x %08x\n", 3703 finicsum, cfcsum); 3704 } 3705 sc->cfcsum = cfcsum; 3706 3707 #define LIMIT_CAPS(x) do { \ 3708 caps.x &= htobe16(t4_##x##_allowed); \ 3709 } while (0) 3710 3711 /* 3712 * Let the firmware know what features will (not) be used so it can tune 3713 * things accordingly. 3714 */ 3715 LIMIT_CAPS(nbmcaps); 3716 LIMIT_CAPS(linkcaps); 3717 LIMIT_CAPS(switchcaps); 3718 LIMIT_CAPS(niccaps); 3719 LIMIT_CAPS(toecaps); 3720 LIMIT_CAPS(rdmacaps); 3721 LIMIT_CAPS(cryptocaps); 3722 LIMIT_CAPS(iscsicaps); 3723 LIMIT_CAPS(fcoecaps); 3724 #undef LIMIT_CAPS 3725 3726 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3727 /* 3728 * TOE and hashfilters are mutually exclusive. It is a config 3729 * file or firmware bug if both are reported as available. Try 3730 * to cope with the situation in non-debug builds by disabling 3731 * TOE. 3732 */ 3733 MPASS(caps.toecaps == 0); 3734 3735 caps.toecaps = 0; 3736 caps.rdmacaps = 0; 3737 caps.iscsicaps = 0; 3738 } 3739 3740 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3741 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3742 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3743 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3744 if (rc != 0) { 3745 device_printf(sc->dev, 3746 "failed to process config file: %d.\n", rc); 3747 } 3748 done: 3749 if (cfg != NULL) 3750 firmware_put(cfg, FIRMWARE_UNLOAD); 3751 return (rc); 3752 } 3753 3754 /* 3755 * Retrieve parameters that are needed (or nice to have) very early. 3756 */ 3757 static int 3758 get_params__pre_init(struct adapter *sc) 3759 { 3760 int rc; 3761 uint32_t param[2], val[2]; 3762 3763 t4_get_version_info(sc); 3764 3765 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3766 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3767 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3768 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3769 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3770 3771 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3772 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3773 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3774 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3775 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3776 3777 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3778 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3779 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3780 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3781 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3782 3783 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3784 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3785 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3786 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3787 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3788 3789 param[0] = FW_PARAM_DEV(PORTVEC); 3790 param[1] = FW_PARAM_DEV(CCLK); 3791 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3792 if (rc != 0) { 3793 device_printf(sc->dev, 3794 "failed to query parameters (pre_init): %d.\n", rc); 3795 return (rc); 3796 } 3797 3798 sc->params.portvec = val[0]; 3799 sc->params.nports = bitcount32(val[0]); 3800 sc->params.vpd.cclk = val[1]; 3801 3802 /* Read device log parameters. */ 3803 rc = -t4_init_devlog_params(sc, 1); 3804 if (rc == 0) 3805 fixup_devlog_params(sc); 3806 else { 3807 device_printf(sc->dev, 3808 "failed to get devlog parameters: %d.\n", rc); 3809 rc = 0; /* devlog isn't critical for device operation */ 3810 } 3811 3812 return (rc); 3813 } 3814 3815 /* 3816 * Retrieve various parameters that are of interest to the driver. The device 3817 * has been initialized by the firmware at this point. 3818 */ 3819 static int 3820 get_params__post_init(struct adapter *sc) 3821 { 3822 int rc; 3823 uint32_t param[7], val[7]; 3824 struct fw_caps_config_cmd caps; 3825 3826 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3827 param[1] = FW_PARAM_PFVF(EQ_START); 3828 param[2] = FW_PARAM_PFVF(FILTER_START); 3829 param[3] = FW_PARAM_PFVF(FILTER_END); 3830 param[4] = FW_PARAM_PFVF(L2T_START); 3831 param[5] = FW_PARAM_PFVF(L2T_END); 3832 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3833 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 3834 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 3835 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 3836 if (rc != 0) { 3837 device_printf(sc->dev, 3838 "failed to query parameters (post_init): %d.\n", rc); 3839 return (rc); 3840 } 3841 3842 sc->sge.iq_start = val[0]; 3843 sc->sge.eq_start = val[1]; 3844 sc->tids.ftid_base = val[2]; 3845 sc->tids.nftids = val[3] - val[2] + 1; 3846 sc->params.ftid_min = val[2]; 3847 sc->params.ftid_max = val[3]; 3848 sc->vres.l2t.start = val[4]; 3849 sc->vres.l2t.size = val[5] - val[4] + 1; 3850 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3851 ("%s: L2 table size (%u) larger than expected (%u)", 3852 __func__, sc->vres.l2t.size, L2T_SIZE)); 3853 sc->params.core_vdd = val[6]; 3854 3855 /* 3856 * MPSBGMAP is queried separately because only recent firmwares support 3857 * it as a parameter and we don't want the compound query above to fail 3858 * on older firmwares. 3859 */ 3860 param[0] = FW_PARAM_DEV(MPSBGMAP); 3861 val[0] = 0; 3862 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3863 if (rc == 0) 3864 sc->params.mps_bg_map = val[0]; 3865 else 3866 sc->params.mps_bg_map = 0; 3867 3868 /* 3869 * Determine whether the firmware supports the filter2 work request. 3870 * This is queried separately for the same reason as MPSBGMAP above. 3871 */ 3872 param[0] = FW_PARAM_DEV(FILTER2_WR); 3873 val[0] = 0; 3874 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3875 if (rc == 0) 3876 sc->params.filter2_wr_support = val[0] != 0; 3877 else 3878 sc->params.filter2_wr_support = 0; 3879 3880 /* get capabilites */ 3881 bzero(&caps, sizeof(caps)); 3882 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3883 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3884 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3885 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3886 if (rc != 0) { 3887 device_printf(sc->dev, 3888 "failed to get card capabilities: %d.\n", rc); 3889 return (rc); 3890 } 3891 3892 #define READ_CAPS(x) do { \ 3893 sc->x = htobe16(caps.x); \ 3894 } while (0) 3895 READ_CAPS(nbmcaps); 3896 READ_CAPS(linkcaps); 3897 READ_CAPS(switchcaps); 3898 READ_CAPS(niccaps); 3899 READ_CAPS(toecaps); 3900 READ_CAPS(rdmacaps); 3901 READ_CAPS(cryptocaps); 3902 READ_CAPS(iscsicaps); 3903 READ_CAPS(fcoecaps); 3904 3905 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 3906 MPASS(chip_id(sc) > CHELSIO_T4); 3907 MPASS(sc->toecaps == 0); 3908 sc->toecaps = 0; 3909 3910 param[0] = FW_PARAM_DEV(NTID); 3911 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3912 if (rc != 0) { 3913 device_printf(sc->dev, 3914 "failed to query HASHFILTER parameters: %d.\n", rc); 3915 return (rc); 3916 } 3917 sc->tids.ntids = val[0]; 3918 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3919 sc->params.hash_filter = 1; 3920 } 3921 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 3922 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 3923 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 3924 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3925 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 3926 if (rc != 0) { 3927 device_printf(sc->dev, 3928 "failed to query NIC parameters: %d.\n", rc); 3929 return (rc); 3930 } 3931 sc->tids.etid_base = val[0]; 3932 sc->params.etid_min = val[0]; 3933 sc->params.etid_max = val[1]; 3934 sc->tids.netids = val[1] - val[0] + 1; 3935 sc->params.eo_wr_cred = val[2]; 3936 sc->params.ethoffload = 1; 3937 } 3938 if (sc->toecaps) { 3939 /* query offload-related parameters */ 3940 param[0] = FW_PARAM_DEV(NTID); 3941 param[1] = FW_PARAM_PFVF(SERVER_START); 3942 param[2] = FW_PARAM_PFVF(SERVER_END); 3943 param[3] = FW_PARAM_PFVF(TDDP_START); 3944 param[4] = FW_PARAM_PFVF(TDDP_END); 3945 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3946 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3947 if (rc != 0) { 3948 device_printf(sc->dev, 3949 "failed to query TOE parameters: %d.\n", rc); 3950 return (rc); 3951 } 3952 sc->tids.ntids = val[0]; 3953 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3954 sc->tids.stid_base = val[1]; 3955 sc->tids.nstids = val[2] - val[1] + 1; 3956 sc->vres.ddp.start = val[3]; 3957 sc->vres.ddp.size = val[4] - val[3] + 1; 3958 sc->params.ofldq_wr_cred = val[5]; 3959 sc->params.offload = 1; 3960 } else { 3961 /* 3962 * The firmware attempts memfree TOE configuration for -SO cards 3963 * and will report toecaps=0 if it runs out of resources (this 3964 * depends on the config file). It may not report 0 for other 3965 * capabilities dependent on the TOE in this case. Set them to 3966 * 0 here so that the driver doesn't bother tracking resources 3967 * that will never be used. 3968 */ 3969 sc->iscsicaps = 0; 3970 sc->rdmacaps = 0; 3971 } 3972 if (sc->rdmacaps) { 3973 param[0] = FW_PARAM_PFVF(STAG_START); 3974 param[1] = FW_PARAM_PFVF(STAG_END); 3975 param[2] = FW_PARAM_PFVF(RQ_START); 3976 param[3] = FW_PARAM_PFVF(RQ_END); 3977 param[4] = FW_PARAM_PFVF(PBL_START); 3978 param[5] = FW_PARAM_PFVF(PBL_END); 3979 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3980 if (rc != 0) { 3981 device_printf(sc->dev, 3982 "failed to query RDMA parameters(1): %d.\n", rc); 3983 return (rc); 3984 } 3985 sc->vres.stag.start = val[0]; 3986 sc->vres.stag.size = val[1] - val[0] + 1; 3987 sc->vres.rq.start = val[2]; 3988 sc->vres.rq.size = val[3] - val[2] + 1; 3989 sc->vres.pbl.start = val[4]; 3990 sc->vres.pbl.size = val[5] - val[4] + 1; 3991 3992 param[0] = FW_PARAM_PFVF(SQRQ_START); 3993 param[1] = FW_PARAM_PFVF(SQRQ_END); 3994 param[2] = FW_PARAM_PFVF(CQ_START); 3995 param[3] = FW_PARAM_PFVF(CQ_END); 3996 param[4] = FW_PARAM_PFVF(OCQ_START); 3997 param[5] = FW_PARAM_PFVF(OCQ_END); 3998 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3999 if (rc != 0) { 4000 device_printf(sc->dev, 4001 "failed to query RDMA parameters(2): %d.\n", rc); 4002 return (rc); 4003 } 4004 sc->vres.qp.start = val[0]; 4005 sc->vres.qp.size = val[1] - val[0] + 1; 4006 sc->vres.cq.start = val[2]; 4007 sc->vres.cq.size = val[3] - val[2] + 1; 4008 sc->vres.ocq.start = val[4]; 4009 sc->vres.ocq.size = val[5] - val[4] + 1; 4010 4011 param[0] = FW_PARAM_PFVF(SRQ_START); 4012 param[1] = FW_PARAM_PFVF(SRQ_END); 4013 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4014 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4015 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4016 if (rc != 0) { 4017 device_printf(sc->dev, 4018 "failed to query RDMA parameters(3): %d.\n", rc); 4019 return (rc); 4020 } 4021 sc->vres.srq.start = val[0]; 4022 sc->vres.srq.size = val[1] - val[0] + 1; 4023 sc->params.max_ordird_qp = val[2]; 4024 sc->params.max_ird_adapter = val[3]; 4025 } 4026 if (sc->iscsicaps) { 4027 param[0] = FW_PARAM_PFVF(ISCSI_START); 4028 param[1] = FW_PARAM_PFVF(ISCSI_END); 4029 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4030 if (rc != 0) { 4031 device_printf(sc->dev, 4032 "failed to query iSCSI parameters: %d.\n", rc); 4033 return (rc); 4034 } 4035 sc->vres.iscsi.start = val[0]; 4036 sc->vres.iscsi.size = val[1] - val[0] + 1; 4037 } 4038 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4039 param[0] = FW_PARAM_PFVF(TLS_START); 4040 param[1] = FW_PARAM_PFVF(TLS_END); 4041 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4042 if (rc != 0) { 4043 device_printf(sc->dev, 4044 "failed to query TLS parameters: %d.\n", rc); 4045 return (rc); 4046 } 4047 sc->vres.key.start = val[0]; 4048 sc->vres.key.size = val[1] - val[0] + 1; 4049 } 4050 4051 t4_init_sge_params(sc); 4052 4053 /* 4054 * We've got the params we wanted to query via the firmware. Now grab 4055 * some others directly from the chip. 4056 */ 4057 rc = t4_read_chip_settings(sc); 4058 4059 return (rc); 4060 } 4061 4062 static int 4063 set_params__post_init(struct adapter *sc) 4064 { 4065 uint32_t param, val; 4066 #ifdef TCP_OFFLOAD 4067 int i, v, shift; 4068 #endif 4069 4070 /* ask for encapsulated CPLs */ 4071 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4072 val = 1; 4073 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4074 4075 #ifdef TCP_OFFLOAD 4076 /* 4077 * Override the TOE timers with user provided tunables. This is not the 4078 * recommended way to change the timers (the firmware config file is) so 4079 * these tunables are not documented. 4080 * 4081 * All the timer tunables are in microseconds. 4082 */ 4083 if (t4_toe_keepalive_idle != 0) { 4084 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4085 v &= M_KEEPALIVEIDLE; 4086 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4087 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4088 } 4089 if (t4_toe_keepalive_interval != 0) { 4090 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4091 v &= M_KEEPALIVEINTVL; 4092 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4093 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4094 } 4095 if (t4_toe_keepalive_count != 0) { 4096 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4097 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4098 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4099 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4100 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4101 } 4102 if (t4_toe_rexmt_min != 0) { 4103 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4104 v &= M_RXTMIN; 4105 t4_set_reg_field(sc, A_TP_RXT_MIN, 4106 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4107 } 4108 if (t4_toe_rexmt_max != 0) { 4109 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4110 v &= M_RXTMAX; 4111 t4_set_reg_field(sc, A_TP_RXT_MAX, 4112 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4113 } 4114 if (t4_toe_rexmt_count != 0) { 4115 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4116 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4117 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4118 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4119 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4120 } 4121 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4122 if (t4_toe_rexmt_backoff[i] != -1) { 4123 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4124 shift = (i & 3) << 3; 4125 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4126 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4127 } 4128 } 4129 #endif 4130 return (0); 4131 } 4132 4133 #undef FW_PARAM_PFVF 4134 #undef FW_PARAM_DEV 4135 4136 static void 4137 t4_set_desc(struct adapter *sc) 4138 { 4139 char buf[128]; 4140 struct adapter_params *p = &sc->params; 4141 4142 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4143 4144 device_set_desc_copy(sc->dev, buf); 4145 } 4146 4147 static inline void 4148 ifmedia_add4(struct ifmedia *ifm, int m) 4149 { 4150 4151 ifmedia_add(ifm, m, 0, NULL); 4152 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4153 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4154 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4155 } 4156 4157 static void 4158 set_current_media(struct port_info *pi, struct ifmedia *ifm) 4159 { 4160 struct link_config *lc; 4161 int mword; 4162 4163 PORT_LOCK_ASSERT_OWNED(pi); 4164 4165 /* Leave current media alone if it's already set to IFM_NONE. */ 4166 if (ifm->ifm_cur != NULL && 4167 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4168 return; 4169 4170 lc = &pi->link_cfg; 4171 if (lc->requested_aneg == AUTONEG_ENABLE && 4172 lc->supported & FW_PORT_CAP_ANEG) { 4173 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4174 return; 4175 } 4176 mword = IFM_ETHER | IFM_FDX; 4177 if (lc->requested_fc & PAUSE_TX) 4178 mword |= IFM_ETH_TXPAUSE; 4179 if (lc->requested_fc & PAUSE_RX) 4180 mword |= IFM_ETH_RXPAUSE; 4181 mword |= port_mword(pi, speed_to_fwspeed(lc->requested_speed)); 4182 ifmedia_set(ifm, mword); 4183 } 4184 4185 static void 4186 build_medialist(struct port_info *pi, struct ifmedia *ifm) 4187 { 4188 uint16_t ss, speed; 4189 int unknown, mword, bit; 4190 struct link_config *lc; 4191 4192 PORT_LOCK_ASSERT_OWNED(pi); 4193 4194 if (pi->flags & FIXED_IFMEDIA) 4195 return; 4196 4197 /* 4198 * First setup all the requested_ fields so that they comply with what's 4199 * supported by the port + transceiver. Note that this clobbers any 4200 * user preferences set via sysctl_pause_settings or sysctl_autoneg. 4201 */ 4202 init_l1cfg(pi); 4203 4204 /* 4205 * Now (re)build the ifmedia list. 4206 */ 4207 ifmedia_removeall(ifm); 4208 lc = &pi->link_cfg; 4209 ss = G_FW_PORT_CAP_SPEED(lc->supported); /* Supported Speeds */ 4210 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 4211 MPASS(ss != 0); 4212 no_media: 4213 MPASS(LIST_EMPTY(&ifm->ifm_list)); 4214 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 4215 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 4216 return; 4217 } 4218 4219 unknown = 0; 4220 for (bit = 0; bit < fls(ss); bit++) { 4221 speed = 1 << bit; 4222 MPASS(speed & M_FW_PORT_CAP_SPEED); 4223 if (ss & speed) { 4224 mword = port_mword(pi, speed); 4225 if (mword == IFM_NONE) { 4226 goto no_media; 4227 } else if (mword == IFM_UNKNOWN) 4228 unknown++; 4229 else 4230 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 4231 } 4232 } 4233 if (unknown > 0) /* Add one unknown for all unknown media types. */ 4234 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 4235 if (lc->supported & FW_PORT_CAP_ANEG) 4236 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 4237 4238 set_current_media(pi, ifm); 4239 } 4240 4241 /* 4242 * Update all the requested_* fields in the link config to something valid (and 4243 * reasonable). 4244 */ 4245 static void 4246 init_l1cfg(struct port_info *pi) 4247 { 4248 struct link_config *lc = &pi->link_cfg; 4249 4250 PORT_LOCK_ASSERT_OWNED(pi); 4251 4252 /* Gbps -> Mbps */ 4253 lc->requested_speed = port_top_speed(pi) * 1000; 4254 4255 if (t4_autoneg != 0 && lc->supported & FW_PORT_CAP_ANEG) { 4256 lc->requested_aneg = AUTONEG_ENABLE; 4257 } else { 4258 lc->requested_aneg = AUTONEG_DISABLE; 4259 } 4260 4261 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX); 4262 4263 if (t4_fec != -1) { 4264 if (t4_fec & FEC_RS && lc->supported & FW_PORT_CAP_FEC_RS) { 4265 lc->requested_fec = FEC_RS; 4266 } else if (t4_fec & FEC_BASER_RS && 4267 lc->supported & FW_PORT_CAP_FEC_BASER_RS) { 4268 lc->requested_fec = FEC_BASER_RS; 4269 } else { 4270 lc->requested_fec = 0; 4271 } 4272 } else { 4273 /* Use the suggested value provided by the firmware in acaps */ 4274 if (lc->advertising & FW_PORT_CAP_FEC_RS && 4275 lc->supported & FW_PORT_CAP_FEC_RS) { 4276 lc->requested_fec = FEC_RS; 4277 } else if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS && 4278 lc->supported & FW_PORT_CAP_FEC_BASER_RS) { 4279 lc->requested_fec = FEC_BASER_RS; 4280 } else { 4281 lc->requested_fec = 0; 4282 } 4283 } 4284 } 4285 4286 /* 4287 * Apply the settings in requested_* to the hardware. The parameters are 4288 * expected to be sane. 4289 */ 4290 static int 4291 apply_l1cfg(struct port_info *pi) 4292 { 4293 struct adapter *sc = pi->adapter; 4294 struct link_config *lc = &pi->link_cfg; 4295 int rc; 4296 #ifdef INVARIANTS 4297 uint16_t fwspeed; 4298 4299 ASSERT_SYNCHRONIZED_OP(sc); 4300 PORT_LOCK_ASSERT_OWNED(pi); 4301 4302 if (lc->requested_aneg == AUTONEG_ENABLE) 4303 MPASS(lc->supported & FW_PORT_CAP_ANEG); 4304 if (lc->requested_fc & PAUSE_TX) 4305 MPASS(lc->supported & FW_PORT_CAP_FC_TX); 4306 if (lc->requested_fc & PAUSE_RX) 4307 MPASS(lc->supported & FW_PORT_CAP_FC_RX); 4308 if (lc->requested_fec == FEC_RS) 4309 MPASS(lc->supported & FW_PORT_CAP_FEC_RS); 4310 if (lc->requested_fec == FEC_BASER_RS) 4311 MPASS(lc->supported & FW_PORT_CAP_FEC_BASER_RS); 4312 fwspeed = speed_to_fwspeed(lc->requested_speed); 4313 MPASS(fwspeed != 0); 4314 MPASS(lc->supported & fwspeed); 4315 #endif 4316 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4317 if (rc != 0) { 4318 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4319 } else { 4320 lc->fc = lc->requested_fc; 4321 lc->fec = lc->requested_fec; 4322 } 4323 return (rc); 4324 } 4325 4326 #define FW_MAC_EXACT_CHUNK 7 4327 4328 /* 4329 * Program the port's XGMAC based on parameters in ifnet. The caller also 4330 * indicates which parameters should be programmed (the rest are left alone). 4331 */ 4332 int 4333 update_mac_settings(struct ifnet *ifp, int flags) 4334 { 4335 int rc = 0; 4336 struct vi_info *vi = ifp->if_softc; 4337 struct port_info *pi = vi->pi; 4338 struct adapter *sc = pi->adapter; 4339 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4340 4341 ASSERT_SYNCHRONIZED_OP(sc); 4342 KASSERT(flags, ("%s: not told what to update.", __func__)); 4343 4344 if (flags & XGMAC_MTU) 4345 mtu = ifp->if_mtu; 4346 4347 if (flags & XGMAC_PROMISC) 4348 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4349 4350 if (flags & XGMAC_ALLMULTI) 4351 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4352 4353 if (flags & XGMAC_VLANEX) 4354 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4355 4356 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4357 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4358 allmulti, 1, vlanex, false); 4359 if (rc) { 4360 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4361 rc); 4362 return (rc); 4363 } 4364 } 4365 4366 if (flags & XGMAC_UCADDR) { 4367 uint8_t ucaddr[ETHER_ADDR_LEN]; 4368 4369 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4370 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4371 ucaddr, true, true); 4372 if (rc < 0) { 4373 rc = -rc; 4374 if_printf(ifp, "change_mac failed: %d\n", rc); 4375 return (rc); 4376 } else { 4377 vi->xact_addr_filt = rc; 4378 rc = 0; 4379 } 4380 } 4381 4382 if (flags & XGMAC_MCADDRS) { 4383 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4384 int del = 1; 4385 uint64_t hash = 0; 4386 struct ifmultiaddr *ifma; 4387 int i = 0, j; 4388 4389 if_maddr_rlock(ifp); 4390 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4391 if (ifma->ifma_addr->sa_family != AF_LINK) 4392 continue; 4393 mcaddr[i] = 4394 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4395 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4396 i++; 4397 4398 if (i == FW_MAC_EXACT_CHUNK) { 4399 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4400 del, i, mcaddr, NULL, &hash, 0); 4401 if (rc < 0) { 4402 rc = -rc; 4403 for (j = 0; j < i; j++) { 4404 if_printf(ifp, 4405 "failed to add mc address" 4406 " %02x:%02x:%02x:" 4407 "%02x:%02x:%02x rc=%d\n", 4408 mcaddr[j][0], mcaddr[j][1], 4409 mcaddr[j][2], mcaddr[j][3], 4410 mcaddr[j][4], mcaddr[j][5], 4411 rc); 4412 } 4413 goto mcfail; 4414 } 4415 del = 0; 4416 i = 0; 4417 } 4418 } 4419 if (i > 0) { 4420 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4421 mcaddr, NULL, &hash, 0); 4422 if (rc < 0) { 4423 rc = -rc; 4424 for (j = 0; j < i; j++) { 4425 if_printf(ifp, 4426 "failed to add mc address" 4427 " %02x:%02x:%02x:" 4428 "%02x:%02x:%02x rc=%d\n", 4429 mcaddr[j][0], mcaddr[j][1], 4430 mcaddr[j][2], mcaddr[j][3], 4431 mcaddr[j][4], mcaddr[j][5], 4432 rc); 4433 } 4434 goto mcfail; 4435 } 4436 } 4437 4438 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4439 if (rc != 0) 4440 if_printf(ifp, "failed to set mc address hash: %d", rc); 4441 mcfail: 4442 if_maddr_runlock(ifp); 4443 } 4444 4445 return (rc); 4446 } 4447 4448 /* 4449 * {begin|end}_synchronized_op must be called from the same thread. 4450 */ 4451 int 4452 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4453 char *wmesg) 4454 { 4455 int rc, pri; 4456 4457 #ifdef WITNESS 4458 /* the caller thinks it's ok to sleep, but is it really? */ 4459 if (flags & SLEEP_OK) 4460 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4461 "begin_synchronized_op"); 4462 #endif 4463 4464 if (INTR_OK) 4465 pri = PCATCH; 4466 else 4467 pri = 0; 4468 4469 ADAPTER_LOCK(sc); 4470 for (;;) { 4471 4472 if (vi && IS_DOOMED(vi)) { 4473 rc = ENXIO; 4474 goto done; 4475 } 4476 4477 if (!IS_BUSY(sc)) { 4478 rc = 0; 4479 break; 4480 } 4481 4482 if (!(flags & SLEEP_OK)) { 4483 rc = EBUSY; 4484 goto done; 4485 } 4486 4487 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4488 rc = EINTR; 4489 goto done; 4490 } 4491 } 4492 4493 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4494 SET_BUSY(sc); 4495 #ifdef INVARIANTS 4496 sc->last_op = wmesg; 4497 sc->last_op_thr = curthread; 4498 sc->last_op_flags = flags; 4499 #endif 4500 4501 done: 4502 if (!(flags & HOLD_LOCK) || rc) 4503 ADAPTER_UNLOCK(sc); 4504 4505 return (rc); 4506 } 4507 4508 /* 4509 * Tell if_ioctl and if_init that the VI is going away. This is 4510 * special variant of begin_synchronized_op and must be paired with a 4511 * call to end_synchronized_op. 4512 */ 4513 void 4514 doom_vi(struct adapter *sc, struct vi_info *vi) 4515 { 4516 4517 ADAPTER_LOCK(sc); 4518 SET_DOOMED(vi); 4519 wakeup(&sc->flags); 4520 while (IS_BUSY(sc)) 4521 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4522 SET_BUSY(sc); 4523 #ifdef INVARIANTS 4524 sc->last_op = "t4detach"; 4525 sc->last_op_thr = curthread; 4526 sc->last_op_flags = 0; 4527 #endif 4528 ADAPTER_UNLOCK(sc); 4529 } 4530 4531 /* 4532 * {begin|end}_synchronized_op must be called from the same thread. 4533 */ 4534 void 4535 end_synchronized_op(struct adapter *sc, int flags) 4536 { 4537 4538 if (flags & LOCK_HELD) 4539 ADAPTER_LOCK_ASSERT_OWNED(sc); 4540 else 4541 ADAPTER_LOCK(sc); 4542 4543 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 4544 CLR_BUSY(sc); 4545 wakeup(&sc->flags); 4546 ADAPTER_UNLOCK(sc); 4547 } 4548 4549 static int 4550 cxgbe_init_synchronized(struct vi_info *vi) 4551 { 4552 struct port_info *pi = vi->pi; 4553 struct adapter *sc = pi->adapter; 4554 struct ifnet *ifp = vi->ifp; 4555 int rc = 0, i; 4556 struct sge_txq *txq; 4557 4558 ASSERT_SYNCHRONIZED_OP(sc); 4559 4560 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4561 return (0); /* already running */ 4562 4563 if (!(sc->flags & FULL_INIT_DONE) && 4564 ((rc = adapter_full_init(sc)) != 0)) 4565 return (rc); /* error message displayed already */ 4566 4567 if (!(vi->flags & VI_INIT_DONE) && 4568 ((rc = vi_full_init(vi)) != 0)) 4569 return (rc); /* error message displayed already */ 4570 4571 rc = update_mac_settings(ifp, XGMAC_ALL); 4572 if (rc) 4573 goto done; /* error message displayed already */ 4574 4575 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 4576 if (rc != 0) { 4577 if_printf(ifp, "enable_vi failed: %d\n", rc); 4578 goto done; 4579 } 4580 4581 /* 4582 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 4583 * if this changes. 4584 */ 4585 4586 for_each_txq(vi, i, txq) { 4587 TXQ_LOCK(txq); 4588 txq->eq.flags |= EQ_ENABLED; 4589 TXQ_UNLOCK(txq); 4590 } 4591 4592 /* 4593 * The first iq of the first port to come up is used for tracing. 4594 */ 4595 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 4596 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 4597 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4598 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4599 V_QUEUENUMBER(sc->traceq)); 4600 pi->flags |= HAS_TRACEQ; 4601 } 4602 4603 /* all ok */ 4604 PORT_LOCK(pi); 4605 if (pi->up_vis++ == 0) { 4606 t4_update_port_info(pi); 4607 build_medialist(pi, &pi->media); 4608 apply_l1cfg(pi); 4609 } 4610 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4611 4612 if (pi->nvi > 1 || sc->flags & IS_VF) 4613 callout_reset(&vi->tick, hz, vi_tick, vi); 4614 else 4615 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4616 PORT_UNLOCK(pi); 4617 done: 4618 if (rc != 0) 4619 cxgbe_uninit_synchronized(vi); 4620 4621 return (rc); 4622 } 4623 4624 /* 4625 * Idempotent. 4626 */ 4627 static int 4628 cxgbe_uninit_synchronized(struct vi_info *vi) 4629 { 4630 struct port_info *pi = vi->pi; 4631 struct adapter *sc = pi->adapter; 4632 struct ifnet *ifp = vi->ifp; 4633 int rc, i; 4634 struct sge_txq *txq; 4635 4636 ASSERT_SYNCHRONIZED_OP(sc); 4637 4638 if (!(vi->flags & VI_INIT_DONE)) { 4639 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4640 KASSERT(0, ("uninited VI is running")); 4641 if_printf(ifp, "uninited VI with running ifnet. " 4642 "vi->flags 0x%016lx, if_flags 0x%08x, " 4643 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 4644 ifp->if_drv_flags); 4645 } 4646 return (0); 4647 } 4648 4649 /* 4650 * Disable the VI so that all its data in either direction is discarded 4651 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4652 * tick) intact as the TP can deliver negative advice or data that it's 4653 * holding in its RAM (for an offloaded connection) even after the VI is 4654 * disabled. 4655 */ 4656 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4657 if (rc) { 4658 if_printf(ifp, "disable_vi failed: %d\n", rc); 4659 return (rc); 4660 } 4661 4662 for_each_txq(vi, i, txq) { 4663 TXQ_LOCK(txq); 4664 txq->eq.flags &= ~EQ_ENABLED; 4665 TXQ_UNLOCK(txq); 4666 } 4667 4668 PORT_LOCK(pi); 4669 if (pi->nvi > 1 || sc->flags & IS_VF) 4670 callout_stop(&vi->tick); 4671 else 4672 callout_stop(&pi->tick); 4673 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4674 PORT_UNLOCK(pi); 4675 return (0); 4676 } 4677 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4678 pi->up_vis--; 4679 if (pi->up_vis > 0) { 4680 PORT_UNLOCK(pi); 4681 return (0); 4682 } 4683 4684 pi->link_cfg.link_ok = 0; 4685 pi->link_cfg.speed = 0; 4686 pi->link_cfg.link_down_rc = 255; 4687 t4_os_link_changed(pi); 4688 pi->old_link_cfg = pi->link_cfg; 4689 PORT_UNLOCK(pi); 4690 4691 return (0); 4692 } 4693 4694 /* 4695 * It is ok for this function to fail midway and return right away. t4_detach 4696 * will walk the entire sc->irq list and clean up whatever is valid. 4697 */ 4698 int 4699 t4_setup_intr_handlers(struct adapter *sc) 4700 { 4701 int rc, rid, p, q, v; 4702 char s[8]; 4703 struct irq *irq; 4704 struct port_info *pi; 4705 struct vi_info *vi; 4706 struct sge *sge = &sc->sge; 4707 struct sge_rxq *rxq; 4708 #ifdef TCP_OFFLOAD 4709 struct sge_ofld_rxq *ofld_rxq; 4710 #endif 4711 #ifdef DEV_NETMAP 4712 struct sge_nm_rxq *nm_rxq; 4713 #endif 4714 #ifdef RSS 4715 int nbuckets = rss_getnumbuckets(); 4716 #endif 4717 4718 /* 4719 * Setup interrupts. 4720 */ 4721 irq = &sc->irq[0]; 4722 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4723 if (forwarding_intr_to_fwq(sc)) 4724 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4725 4726 /* Multiple interrupts. */ 4727 if (sc->flags & IS_VF) 4728 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4729 ("%s: too few intr.", __func__)); 4730 else 4731 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4732 ("%s: too few intr.", __func__)); 4733 4734 /* The first one is always error intr on PFs */ 4735 if (!(sc->flags & IS_VF)) { 4736 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4737 if (rc != 0) 4738 return (rc); 4739 irq++; 4740 rid++; 4741 } 4742 4743 /* The second one is always the firmware event queue (first on VFs) */ 4744 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4745 if (rc != 0) 4746 return (rc); 4747 irq++; 4748 rid++; 4749 4750 for_each_port(sc, p) { 4751 pi = sc->port[p]; 4752 for_each_vi(pi, v, vi) { 4753 vi->first_intr = rid - 1; 4754 4755 if (vi->nnmrxq > 0) { 4756 int n = max(vi->nrxq, vi->nnmrxq); 4757 4758 rxq = &sge->rxq[vi->first_rxq]; 4759 #ifdef DEV_NETMAP 4760 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4761 #endif 4762 for (q = 0; q < n; q++) { 4763 snprintf(s, sizeof(s), "%x%c%x", p, 4764 'a' + v, q); 4765 if (q < vi->nrxq) 4766 irq->rxq = rxq++; 4767 #ifdef DEV_NETMAP 4768 if (q < vi->nnmrxq) 4769 irq->nm_rxq = nm_rxq++; 4770 #endif 4771 rc = t4_alloc_irq(sc, irq, rid, 4772 t4_vi_intr, irq, s); 4773 if (rc != 0) 4774 return (rc); 4775 #ifdef RSS 4776 if (q < vi->nrxq) { 4777 bus_bind_intr(sc->dev, irq->res, 4778 rss_getcpu(q % nbuckets)); 4779 } 4780 #endif 4781 irq++; 4782 rid++; 4783 vi->nintr++; 4784 } 4785 } else { 4786 for_each_rxq(vi, q, rxq) { 4787 snprintf(s, sizeof(s), "%x%c%x", p, 4788 'a' + v, q); 4789 rc = t4_alloc_irq(sc, irq, rid, 4790 t4_intr, rxq, s); 4791 if (rc != 0) 4792 return (rc); 4793 #ifdef RSS 4794 bus_bind_intr(sc->dev, irq->res, 4795 rss_getcpu(q % nbuckets)); 4796 #endif 4797 irq++; 4798 rid++; 4799 vi->nintr++; 4800 } 4801 } 4802 #ifdef TCP_OFFLOAD 4803 for_each_ofld_rxq(vi, q, ofld_rxq) { 4804 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 4805 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 4806 ofld_rxq, s); 4807 if (rc != 0) 4808 return (rc); 4809 irq++; 4810 rid++; 4811 vi->nintr++; 4812 } 4813 #endif 4814 } 4815 } 4816 MPASS(irq == &sc->irq[sc->intr_count]); 4817 4818 return (0); 4819 } 4820 4821 int 4822 adapter_full_init(struct adapter *sc) 4823 { 4824 int rc, i; 4825 #ifdef RSS 4826 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4827 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4828 #endif 4829 4830 ASSERT_SYNCHRONIZED_OP(sc); 4831 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4832 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 4833 ("%s: FULL_INIT_DONE already", __func__)); 4834 4835 /* 4836 * queues that belong to the adapter (not any particular port). 4837 */ 4838 rc = t4_setup_adapter_queues(sc); 4839 if (rc != 0) 4840 goto done; 4841 4842 for (i = 0; i < nitems(sc->tq); i++) { 4843 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 4844 taskqueue_thread_enqueue, &sc->tq[i]); 4845 if (sc->tq[i] == NULL) { 4846 device_printf(sc->dev, 4847 "failed to allocate task queue %d\n", i); 4848 rc = ENOMEM; 4849 goto done; 4850 } 4851 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 4852 device_get_nameunit(sc->dev), i); 4853 } 4854 #ifdef RSS 4855 MPASS(RSS_KEYSIZE == 40); 4856 rss_getkey((void *)&raw_rss_key[0]); 4857 for (i = 0; i < nitems(rss_key); i++) { 4858 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 4859 } 4860 t4_write_rss_key(sc, &rss_key[0], -1, 1); 4861 #endif 4862 4863 if (!(sc->flags & IS_VF)) 4864 t4_intr_enable(sc); 4865 sc->flags |= FULL_INIT_DONE; 4866 done: 4867 if (rc != 0) 4868 adapter_full_uninit(sc); 4869 4870 return (rc); 4871 } 4872 4873 int 4874 adapter_full_uninit(struct adapter *sc) 4875 { 4876 int i; 4877 4878 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4879 4880 t4_teardown_adapter_queues(sc); 4881 4882 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 4883 taskqueue_free(sc->tq[i]); 4884 sc->tq[i] = NULL; 4885 } 4886 4887 sc->flags &= ~FULL_INIT_DONE; 4888 4889 return (0); 4890 } 4891 4892 #ifdef RSS 4893 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 4894 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 4895 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 4896 RSS_HASHTYPE_RSS_UDP_IPV6) 4897 4898 /* Translates kernel hash types to hardware. */ 4899 static int 4900 hashconfig_to_hashen(int hashconfig) 4901 { 4902 int hashen = 0; 4903 4904 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 4905 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 4906 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 4907 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 4908 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 4909 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4910 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4911 } 4912 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 4913 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4914 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4915 } 4916 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 4917 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4918 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 4919 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4920 4921 return (hashen); 4922 } 4923 4924 /* Translates hardware hash types to kernel. */ 4925 static int 4926 hashen_to_hashconfig(int hashen) 4927 { 4928 int hashconfig = 0; 4929 4930 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 4931 /* 4932 * If UDP hashing was enabled it must have been enabled for 4933 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 4934 * enabling any 4-tuple hash is nonsense configuration. 4935 */ 4936 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4937 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 4938 4939 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4940 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 4941 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4942 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 4943 } 4944 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4945 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 4946 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4947 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 4948 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 4949 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 4950 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 4951 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 4952 4953 return (hashconfig); 4954 } 4955 #endif 4956 4957 int 4958 vi_full_init(struct vi_info *vi) 4959 { 4960 struct adapter *sc = vi->pi->adapter; 4961 struct ifnet *ifp = vi->ifp; 4962 uint16_t *rss; 4963 struct sge_rxq *rxq; 4964 int rc, i, j, hashen; 4965 #ifdef RSS 4966 int nbuckets = rss_getnumbuckets(); 4967 int hashconfig = rss_gethashconfig(); 4968 int extra; 4969 #endif 4970 4971 ASSERT_SYNCHRONIZED_OP(sc); 4972 KASSERT((vi->flags & VI_INIT_DONE) == 0, 4973 ("%s: VI_INIT_DONE already", __func__)); 4974 4975 sysctl_ctx_init(&vi->ctx); 4976 vi->flags |= VI_SYSCTL_CTX; 4977 4978 /* 4979 * Allocate tx/rx/fl queues for this VI. 4980 */ 4981 rc = t4_setup_vi_queues(vi); 4982 if (rc != 0) 4983 goto done; /* error message displayed already */ 4984 4985 /* 4986 * Setup RSS for this VI. Save a copy of the RSS table for later use. 4987 */ 4988 if (vi->nrxq > vi->rss_size) { 4989 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 4990 "some queues will never receive traffic.\n", vi->nrxq, 4991 vi->rss_size); 4992 } else if (vi->rss_size % vi->nrxq) { 4993 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 4994 "expect uneven traffic distribution.\n", vi->nrxq, 4995 vi->rss_size); 4996 } 4997 #ifdef RSS 4998 if (vi->nrxq != nbuckets) { 4999 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5000 "performance will be impacted.\n", vi->nrxq, nbuckets); 5001 } 5002 #endif 5003 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5004 for (i = 0; i < vi->rss_size;) { 5005 #ifdef RSS 5006 j = rss_get_indirection_to_bucket(i); 5007 j %= vi->nrxq; 5008 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5009 rss[i++] = rxq->iq.abs_id; 5010 #else 5011 for_each_rxq(vi, j, rxq) { 5012 rss[i++] = rxq->iq.abs_id; 5013 if (i == vi->rss_size) 5014 break; 5015 } 5016 #endif 5017 } 5018 5019 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5020 vi->rss_size); 5021 if (rc != 0) { 5022 if_printf(ifp, "rss_config failed: %d\n", rc); 5023 goto done; 5024 } 5025 5026 #ifdef RSS 5027 hashen = hashconfig_to_hashen(hashconfig); 5028 5029 /* 5030 * We may have had to enable some hashes even though the global config 5031 * wants them disabled. This is a potential problem that must be 5032 * reported to the user. 5033 */ 5034 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 5035 5036 /* 5037 * If we consider only the supported hash types, then the enabled hashes 5038 * are a superset of the requested hashes. In other words, there cannot 5039 * be any supported hash that was requested but not enabled, but there 5040 * can be hashes that were not requested but had to be enabled. 5041 */ 5042 extra &= SUPPORTED_RSS_HASHTYPES; 5043 MPASS((extra & hashconfig) == 0); 5044 5045 if (extra) { 5046 if_printf(ifp, 5047 "global RSS config (0x%x) cannot be accommodated.\n", 5048 hashconfig); 5049 } 5050 if (extra & RSS_HASHTYPE_RSS_IPV4) 5051 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 5052 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 5053 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 5054 if (extra & RSS_HASHTYPE_RSS_IPV6) 5055 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 5056 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 5057 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 5058 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 5059 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 5060 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 5061 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 5062 #else 5063 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 5064 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 5065 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5066 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 5067 #endif 5068 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0); 5069 if (rc != 0) { 5070 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 5071 goto done; 5072 } 5073 5074 vi->rss = rss; 5075 vi->flags |= VI_INIT_DONE; 5076 done: 5077 if (rc != 0) 5078 vi_full_uninit(vi); 5079 5080 return (rc); 5081 } 5082 5083 /* 5084 * Idempotent. 5085 */ 5086 int 5087 vi_full_uninit(struct vi_info *vi) 5088 { 5089 struct port_info *pi = vi->pi; 5090 struct adapter *sc = pi->adapter; 5091 int i; 5092 struct sge_rxq *rxq; 5093 struct sge_txq *txq; 5094 #ifdef TCP_OFFLOAD 5095 struct sge_ofld_rxq *ofld_rxq; 5096 struct sge_wrq *ofld_txq; 5097 #endif 5098 5099 if (vi->flags & VI_INIT_DONE) { 5100 5101 /* Need to quiesce queues. */ 5102 5103 /* XXX: Only for the first VI? */ 5104 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5105 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5106 5107 for_each_txq(vi, i, txq) { 5108 quiesce_txq(sc, txq); 5109 } 5110 5111 #ifdef TCP_OFFLOAD 5112 for_each_ofld_txq(vi, i, ofld_txq) { 5113 quiesce_wrq(sc, ofld_txq); 5114 } 5115 #endif 5116 5117 for_each_rxq(vi, i, rxq) { 5118 quiesce_iq(sc, &rxq->iq); 5119 quiesce_fl(sc, &rxq->fl); 5120 } 5121 5122 #ifdef TCP_OFFLOAD 5123 for_each_ofld_rxq(vi, i, ofld_rxq) { 5124 quiesce_iq(sc, &ofld_rxq->iq); 5125 quiesce_fl(sc, &ofld_rxq->fl); 5126 } 5127 #endif 5128 free(vi->rss, M_CXGBE); 5129 free(vi->nm_rss, M_CXGBE); 5130 } 5131 5132 t4_teardown_vi_queues(vi); 5133 vi->flags &= ~VI_INIT_DONE; 5134 5135 return (0); 5136 } 5137 5138 static void 5139 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5140 { 5141 struct sge_eq *eq = &txq->eq; 5142 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5143 5144 (void) sc; /* unused */ 5145 5146 #ifdef INVARIANTS 5147 TXQ_LOCK(txq); 5148 MPASS((eq->flags & EQ_ENABLED) == 0); 5149 TXQ_UNLOCK(txq); 5150 #endif 5151 5152 /* Wait for the mp_ring to empty. */ 5153 while (!mp_ring_is_idle(txq->r)) { 5154 mp_ring_check_drainage(txq->r, 0); 5155 pause("rquiesce", 1); 5156 } 5157 5158 /* Then wait for the hardware to finish. */ 5159 while (spg->cidx != htobe16(eq->pidx)) 5160 pause("equiesce", 1); 5161 5162 /* Finally, wait for the driver to reclaim all descriptors. */ 5163 while (eq->cidx != eq->pidx) 5164 pause("dquiesce", 1); 5165 } 5166 5167 static void 5168 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5169 { 5170 5171 /* XXXTX */ 5172 } 5173 5174 static void 5175 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5176 { 5177 (void) sc; /* unused */ 5178 5179 /* Synchronize with the interrupt handler */ 5180 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5181 pause("iqfree", 1); 5182 } 5183 5184 static void 5185 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5186 { 5187 mtx_lock(&sc->sfl_lock); 5188 FL_LOCK(fl); 5189 fl->flags |= FL_DOOMED; 5190 FL_UNLOCK(fl); 5191 callout_stop(&sc->sfl_callout); 5192 mtx_unlock(&sc->sfl_lock); 5193 5194 KASSERT((fl->flags & FL_STARVING) == 0, 5195 ("%s: still starving", __func__)); 5196 } 5197 5198 static int 5199 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5200 driver_intr_t *handler, void *arg, char *name) 5201 { 5202 int rc; 5203 5204 irq->rid = rid; 5205 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5206 RF_SHAREABLE | RF_ACTIVE); 5207 if (irq->res == NULL) { 5208 device_printf(sc->dev, 5209 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5210 return (ENOMEM); 5211 } 5212 5213 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5214 NULL, handler, arg, &irq->tag); 5215 if (rc != 0) { 5216 device_printf(sc->dev, 5217 "failed to setup interrupt for rid %d, name %s: %d\n", 5218 rid, name, rc); 5219 } else if (name) 5220 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5221 5222 return (rc); 5223 } 5224 5225 static int 5226 t4_free_irq(struct adapter *sc, struct irq *irq) 5227 { 5228 if (irq->tag) 5229 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5230 if (irq->res) 5231 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5232 5233 bzero(irq, sizeof(*irq)); 5234 5235 return (0); 5236 } 5237 5238 static void 5239 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5240 { 5241 5242 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5243 t4_get_regs(sc, buf, regs->len); 5244 } 5245 5246 #define A_PL_INDIR_CMD 0x1f8 5247 5248 #define S_PL_AUTOINC 31 5249 #define M_PL_AUTOINC 0x1U 5250 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5251 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5252 5253 #define S_PL_VFID 20 5254 #define M_PL_VFID 0xffU 5255 #define V_PL_VFID(x) ((x) << S_PL_VFID) 5256 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5257 5258 #define S_PL_ADDR 0 5259 #define M_PL_ADDR 0xfffffU 5260 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5261 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5262 5263 #define A_PL_INDIR_DATA 0x1fc 5264 5265 static uint64_t 5266 read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 5267 { 5268 u32 stats[2]; 5269 5270 mtx_assert(&sc->reg_lock, MA_OWNED); 5271 if (sc->flags & IS_VF) { 5272 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5273 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5274 } else { 5275 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5276 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5277 V_PL_ADDR(VF_MPS_REG(reg))); 5278 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5279 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5280 } 5281 return (((uint64_t)stats[1]) << 32 | stats[0]); 5282 } 5283 5284 static void 5285 t4_get_vi_stats(struct adapter *sc, unsigned int viid, 5286 struct fw_vi_stats_vf *stats) 5287 { 5288 5289 #define GET_STAT(name) \ 5290 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 5291 5292 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5293 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5294 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5295 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5296 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5297 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5298 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5299 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5300 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5301 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5302 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5303 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5304 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5305 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5306 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5307 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5308 5309 #undef GET_STAT 5310 } 5311 5312 static void 5313 t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 5314 { 5315 int reg; 5316 5317 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5318 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5319 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5320 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5321 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5322 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5323 } 5324 5325 static void 5326 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5327 { 5328 struct timeval tv; 5329 const struct timeval interval = {0, 250000}; /* 250ms */ 5330 5331 if (!(vi->flags & VI_INIT_DONE)) 5332 return; 5333 5334 getmicrotime(&tv); 5335 timevalsub(&tv, &interval); 5336 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5337 return; 5338 5339 mtx_lock(&sc->reg_lock); 5340 t4_get_vi_stats(sc, vi->viid, &vi->stats); 5341 getmicrotime(&vi->last_refreshed); 5342 mtx_unlock(&sc->reg_lock); 5343 } 5344 5345 static void 5346 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5347 { 5348 u_int i, v, tnl_cong_drops, bg_map; 5349 struct timeval tv; 5350 const struct timeval interval = {0, 250000}; /* 250ms */ 5351 5352 getmicrotime(&tv); 5353 timevalsub(&tv, &interval); 5354 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5355 return; 5356 5357 tnl_cong_drops = 0; 5358 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5359 bg_map = pi->mps_bg_map; 5360 while (bg_map) { 5361 i = ffs(bg_map) - 1; 5362 mtx_lock(&sc->reg_lock); 5363 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5364 A_TP_MIB_TNL_CNG_DROP_0 + i); 5365 mtx_unlock(&sc->reg_lock); 5366 tnl_cong_drops += v; 5367 bg_map &= ~(1 << i); 5368 } 5369 pi->tnl_cong_drops = tnl_cong_drops; 5370 getmicrotime(&pi->last_refreshed); 5371 } 5372 5373 static void 5374 cxgbe_tick(void *arg) 5375 { 5376 struct port_info *pi = arg; 5377 struct adapter *sc = pi->adapter; 5378 5379 PORT_LOCK_ASSERT_OWNED(pi); 5380 cxgbe_refresh_stats(sc, pi); 5381 5382 callout_schedule(&pi->tick, hz); 5383 } 5384 5385 void 5386 vi_tick(void *arg) 5387 { 5388 struct vi_info *vi = arg; 5389 struct adapter *sc = vi->pi->adapter; 5390 5391 vi_refresh_stats(sc, vi); 5392 5393 callout_schedule(&vi->tick, hz); 5394 } 5395 5396 static void 5397 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 5398 { 5399 struct ifnet *vlan; 5400 5401 if (arg != ifp || ifp->if_type != IFT_ETHER) 5402 return; 5403 5404 vlan = VLAN_DEVAT(ifp, vid); 5405 VLAN_SETCOOKIE(vlan, ifp); 5406 } 5407 5408 /* 5409 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5410 */ 5411 static char *caps_decoder[] = { 5412 "\20\001IPMI\002NCSI", /* 0: NBM */ 5413 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5414 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5415 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5416 "\006HASHFILTER\007ETHOFLD", 5417 "\20\001TOE", /* 4: TOE */ 5418 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5419 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5420 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5421 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5422 "\007T10DIF" 5423 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5424 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5425 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5426 "\004PO_INITIATOR\005PO_TARGET", 5427 }; 5428 5429 void 5430 t4_sysctls(struct adapter *sc) 5431 { 5432 struct sysctl_ctx_list *ctx; 5433 struct sysctl_oid *oid; 5434 struct sysctl_oid_list *children, *c0; 5435 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5436 5437 ctx = device_get_sysctl_ctx(sc->dev); 5438 5439 /* 5440 * dev.t4nex.X. 5441 */ 5442 oid = device_get_sysctl_tree(sc->dev); 5443 c0 = children = SYSCTL_CHILDREN(oid); 5444 5445 sc->sc_do_rxcopy = 1; 5446 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5447 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5448 5449 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5450 sc->params.nports, "# of ports"); 5451 5452 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5453 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 5454 sysctl_bitfield, "A", "available doorbells"); 5455 5456 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5457 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5458 5459 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5460 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5461 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5462 "interrupt holdoff timer values (us)"); 5463 5464 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5465 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5466 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5467 "interrupt holdoff packet counter values"); 5468 5469 t4_sge_sysctls(sc, ctx, children); 5470 5471 sc->lro_timeout = 100; 5472 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5473 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5474 5475 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5476 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5477 5478 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5479 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5480 5481 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5482 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5483 5484 if (sc->flags & IS_VF) 5485 return; 5486 5487 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5488 NULL, chip_rev(sc), "chip hardware revision"); 5489 5490 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5491 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5492 5493 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5494 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5495 5496 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5497 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5498 5499 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5500 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5501 5502 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5503 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5504 5505 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5506 sc->er_version, 0, "expansion ROM version"); 5507 5508 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5509 sc->bs_version, 0, "bootstrap firmware version"); 5510 5511 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5512 NULL, sc->params.scfg_vers, "serial config version"); 5513 5514 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5515 NULL, sc->params.vpd_vers, "VPD version"); 5516 5517 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5518 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5519 5520 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5521 sc->cfcsum, "config file checksum"); 5522 5523 #define SYSCTL_CAP(name, n, text) \ 5524 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5525 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \ 5526 sysctl_bitfield, "A", "available " text " capabilities") 5527 5528 SYSCTL_CAP(nbmcaps, 0, "NBM"); 5529 SYSCTL_CAP(linkcaps, 1, "link"); 5530 SYSCTL_CAP(switchcaps, 2, "switch"); 5531 SYSCTL_CAP(niccaps, 3, "NIC"); 5532 SYSCTL_CAP(toecaps, 4, "TCP offload"); 5533 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 5534 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 5535 SYSCTL_CAP(cryptocaps, 7, "crypto"); 5536 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 5537 #undef SYSCTL_CAP 5538 5539 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 5540 NULL, sc->tids.nftids, "number of filters"); 5541 5542 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 5543 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 5544 "chip temperature (in Celsius)"); 5545 5546 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING | 5547 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A", 5548 "microprocessor load averages (debug firmwares only)"); 5549 5550 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 5551 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 5552 5553 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 5554 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS, 5555 sysctl_cpus, "A", "local CPUs"); 5556 5557 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 5558 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS, 5559 sysctl_cpus, "A", "preferred CPUs for interrupts"); 5560 5561 /* 5562 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 5563 */ 5564 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 5565 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 5566 "logs and miscellaneous information"); 5567 children = SYSCTL_CHILDREN(oid); 5568 5569 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 5570 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5571 sysctl_cctrl, "A", "congestion control"); 5572 5573 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 5574 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5575 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 5576 5577 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 5578 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 5579 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 5580 5581 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 5582 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 5583 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 5584 5585 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 5586 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 5587 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 5588 5589 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 5590 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 5591 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 5592 5593 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 5594 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 5595 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 5596 5597 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 5598 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5599 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 5600 "A", "CIM logic analyzer"); 5601 5602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 5603 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5604 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 5605 5606 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 5607 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 5608 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 5609 5610 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 5611 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 5612 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 5613 5614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 5615 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 5616 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 5617 5618 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 5619 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 5620 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 5621 5622 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 5623 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 5624 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 5625 5626 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 5627 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 5628 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5629 5630 if (chip_id(sc) > CHELSIO_T4) { 5631 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5632 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5633 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5634 5635 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5636 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5637 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5638 } 5639 5640 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5641 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5642 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5643 5644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5645 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5646 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5647 5648 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5649 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5650 sysctl_cpl_stats, "A", "CPL statistics"); 5651 5652 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5653 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5654 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5655 5656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5657 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5658 sysctl_devlog, "A", "firmware's device log"); 5659 5660 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5661 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5662 sysctl_fcoe_stats, "A", "FCoE statistics"); 5663 5664 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5665 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5666 sysctl_hw_sched, "A", "hardware scheduler "); 5667 5668 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5669 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5670 sysctl_l2t, "A", "hardware L2 table"); 5671 5672 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 5673 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5674 sysctl_smt, "A", "hardware source MAC table"); 5675 5676 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5677 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5678 sysctl_lb_stats, "A", "loopback statistics"); 5679 5680 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5681 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5682 sysctl_meminfo, "A", "memory regions"); 5683 5684 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5685 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5686 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5687 "A", "MPS TCAM entries"); 5688 5689 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5690 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5691 sysctl_path_mtus, "A", "path MTUs"); 5692 5693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5694 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5695 sysctl_pm_stats, "A", "PM statistics"); 5696 5697 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5698 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5699 sysctl_rdma_stats, "A", "RDMA statistics"); 5700 5701 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5702 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5703 sysctl_tcp_stats, "A", "TCP statistics"); 5704 5705 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5706 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5707 sysctl_tids, "A", "TID information"); 5708 5709 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5710 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5711 sysctl_tp_err_stats, "A", "TP error statistics"); 5712 5713 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5714 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5715 "TP logic analyzer event capture mask"); 5716 5717 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5718 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5719 sysctl_tp_la, "A", "TP logic analyzer"); 5720 5721 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5722 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5723 sysctl_tx_rate, "A", "Tx rate"); 5724 5725 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5726 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5727 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5728 5729 if (chip_id(sc) >= CHELSIO_T5) { 5730 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5731 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5732 sysctl_wcwr_stats, "A", "write combined work requests"); 5733 } 5734 5735 #ifdef TCP_OFFLOAD 5736 if (is_offload(sc)) { 5737 int i; 5738 char s[4]; 5739 5740 /* 5741 * dev.t4nex.X.toe. 5742 */ 5743 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5744 NULL, "TOE parameters"); 5745 children = SYSCTL_CHILDREN(oid); 5746 5747 sc->tt.cong_algorithm = -1; 5748 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 5749 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 5750 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 5751 "3 = highspeed)"); 5752 5753 sc->tt.sndbuf = 256 * 1024; 5754 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 5755 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 5756 5757 sc->tt.ddp = 0; 5758 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 5759 &sc->tt.ddp, 0, "DDP allowed"); 5760 5761 sc->tt.rx_coalesce = 1; 5762 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 5763 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 5764 5765 sc->tt.tls = 0; 5766 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 5767 &sc->tt.tls, 0, "Inline TLS allowed"); 5768 5769 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 5770 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 5771 "I", "TCP ports that use inline TLS+TOE RX"); 5772 5773 sc->tt.tx_align = 1; 5774 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 5775 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 5776 5777 sc->tt.tx_zcopy = 0; 5778 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 5779 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 5780 "Enable zero-copy aio_write(2)"); 5781 5782 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 5783 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5784 "cop_managed_offloading", CTLFLAG_RW, 5785 &sc->tt.cop_managed_offloading, 0, 5786 "COP (Connection Offload Policy) controls all TOE offload"); 5787 5788 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 5789 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 5790 "TP timer tick (us)"); 5791 5792 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 5793 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 5794 "TCP timestamp tick (us)"); 5795 5796 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 5797 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 5798 "DACK tick (us)"); 5799 5800 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 5801 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 5802 "IU", "DACK timer (us)"); 5803 5804 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 5805 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 5806 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 5807 5808 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 5809 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 5810 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 5811 5812 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 5813 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 5814 sysctl_tp_timer, "LU", "Persist timer min (us)"); 5815 5816 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 5817 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 5818 sysctl_tp_timer, "LU", "Persist timer max (us)"); 5819 5820 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 5821 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 5822 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 5823 5824 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 5825 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 5826 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 5827 5828 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 5829 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 5830 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 5831 5832 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 5833 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 5834 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 5835 5836 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 5837 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 5838 sysctl_tp_shift_cnt, "IU", 5839 "Number of SYN retransmissions before abort"); 5840 5841 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 5842 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 5843 sysctl_tp_shift_cnt, "IU", 5844 "Number of retransmissions before abort"); 5845 5846 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 5847 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 5848 sysctl_tp_shift_cnt, "IU", 5849 "Number of keepalive probes before abort"); 5850 5851 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 5852 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 5853 children = SYSCTL_CHILDREN(oid); 5854 for (i = 0; i < 16; i++) { 5855 snprintf(s, sizeof(s), "%u", i); 5856 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 5857 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 5858 "IU", "TOE retransmit backoff"); 5859 } 5860 } 5861 #endif 5862 } 5863 5864 void 5865 vi_sysctls(struct vi_info *vi) 5866 { 5867 struct sysctl_ctx_list *ctx; 5868 struct sysctl_oid *oid; 5869 struct sysctl_oid_list *children; 5870 5871 ctx = device_get_sysctl_ctx(vi->dev); 5872 5873 /* 5874 * dev.v?(cxgbe|cxl).X. 5875 */ 5876 oid = device_get_sysctl_tree(vi->dev); 5877 children = SYSCTL_CHILDREN(oid); 5878 5879 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 5880 vi->viid, "VI identifer"); 5881 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 5882 &vi->nrxq, 0, "# of rx queues"); 5883 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 5884 &vi->ntxq, 0, "# of tx queues"); 5885 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 5886 &vi->first_rxq, 0, "index of first rx queue"); 5887 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 5888 &vi->first_txq, 0, "index of first tx queue"); 5889 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 5890 vi->rss_size, "size of RSS indirection table"); 5891 5892 if (IS_MAIN_VI(vi)) { 5893 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 5894 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 5895 "Reserve queue 0 for non-flowid packets"); 5896 } 5897 5898 #ifdef TCP_OFFLOAD 5899 if (vi->nofldrxq != 0) { 5900 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 5901 &vi->nofldrxq, 0, 5902 "# of rx queues for offloaded TCP connections"); 5903 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 5904 &vi->nofldtxq, 0, 5905 "# of tx queues for offloaded TCP connections"); 5906 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 5907 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 5908 "index of first TOE rx queue"); 5909 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 5910 CTLFLAG_RD, &vi->first_ofld_txq, 0, 5911 "index of first TOE tx queue"); 5912 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 5913 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5914 sysctl_holdoff_tmr_idx_ofld, "I", 5915 "holdoff timer index for TOE queues"); 5916 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 5917 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5918 sysctl_holdoff_pktc_idx_ofld, "I", 5919 "holdoff packet counter index for TOE queues"); 5920 } 5921 #endif 5922 #ifdef DEV_NETMAP 5923 if (vi->nnmrxq != 0) { 5924 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 5925 &vi->nnmrxq, 0, "# of netmap rx queues"); 5926 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 5927 &vi->nnmtxq, 0, "# of netmap tx queues"); 5928 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 5929 CTLFLAG_RD, &vi->first_nm_rxq, 0, 5930 "index of first netmap rx queue"); 5931 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 5932 CTLFLAG_RD, &vi->first_nm_txq, 0, 5933 "index of first netmap tx queue"); 5934 } 5935 #endif 5936 5937 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 5938 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 5939 "holdoff timer index"); 5940 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 5941 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 5942 "holdoff packet counter index"); 5943 5944 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 5945 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 5946 "rx queue size"); 5947 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 5948 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 5949 "tx queue size"); 5950 } 5951 5952 static void 5953 cxgbe_sysctls(struct port_info *pi) 5954 { 5955 struct sysctl_ctx_list *ctx; 5956 struct sysctl_oid *oid; 5957 struct sysctl_oid_list *children, *children2; 5958 struct adapter *sc = pi->adapter; 5959 int i; 5960 char name[16]; 5961 5962 ctx = device_get_sysctl_ctx(pi->dev); 5963 5964 /* 5965 * dev.cxgbe.X. 5966 */ 5967 oid = device_get_sysctl_tree(pi->dev); 5968 children = SYSCTL_CHILDREN(oid); 5969 5970 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 5971 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 5972 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 5973 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 5974 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 5975 "PHY temperature (in Celsius)"); 5976 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 5977 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 5978 "PHY firmware version"); 5979 } 5980 5981 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 5982 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 5983 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)"); 5984 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 5985 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 5986 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 5987 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 5988 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 5989 "autonegotiation (-1 = not supported)"); 5990 5991 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 5992 port_top_speed(pi), "max speed (in Gbps)"); 5993 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 5994 pi->mps_bg_map, "MPS buffer group map"); 5995 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 5996 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 5997 5998 if (sc->flags & IS_VF) 5999 return; 6000 6001 /* 6002 * dev.(cxgbe|cxl).X.tc. 6003 */ 6004 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 6005 "Tx scheduler traffic classes (cl_rl)"); 6006 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 6007 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 6008 6009 snprintf(name, sizeof(name), "%d", i); 6010 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 6011 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 6012 "traffic class")); 6013 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD, 6014 &tc->flags, 0, "flags"); 6015 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 6016 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 6017 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 6018 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 6019 sysctl_tc_params, "A", "traffic class parameters"); 6020 } 6021 6022 /* 6023 * dev.cxgbe.X.stats. 6024 */ 6025 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 6026 NULL, "port statistics"); 6027 children = SYSCTL_CHILDREN(oid); 6028 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 6029 &pi->tx_parse_error, 0, 6030 "# of tx packets with invalid length or # of segments"); 6031 6032 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 6033 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 6034 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 6035 sysctl_handle_t4_reg64, "QU", desc) 6036 6037 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 6038 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 6039 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 6040 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 6041 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 6042 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 6043 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 6044 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 6045 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 6046 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 6047 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 6048 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 6049 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 6050 "# of tx frames in this range", 6051 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 6052 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 6053 "# of tx frames in this range", 6054 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 6055 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 6056 "# of tx frames in this range", 6057 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 6058 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 6059 "# of tx frames in this range", 6060 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 6061 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 6062 "# of tx frames in this range", 6063 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 6064 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 6065 "# of tx frames in this range", 6066 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 6067 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 6068 "# of tx frames in this range", 6069 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 6070 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 6071 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 6072 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 6073 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 6074 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 6075 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 6076 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 6077 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 6078 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 6079 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 6080 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 6081 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 6082 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 6083 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 6084 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 6085 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 6086 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 6087 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 6088 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 6089 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 6090 6091 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 6092 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 6093 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 6094 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 6095 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 6096 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 6097 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 6098 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 6099 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 6100 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 6101 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 6102 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 6103 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 6104 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 6105 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 6106 "# of frames received with bad FCS", 6107 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 6108 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 6109 "# of frames received with length error", 6110 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 6111 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 6112 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 6113 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 6114 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 6115 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 6116 "# of rx frames in this range", 6117 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 6118 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 6119 "# of rx frames in this range", 6120 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 6121 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 6122 "# of rx frames in this range", 6123 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 6124 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 6125 "# of rx frames in this range", 6126 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 6127 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 6128 "# of rx frames in this range", 6129 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 6130 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 6131 "# of rx frames in this range", 6132 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 6133 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 6134 "# of rx frames in this range", 6135 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 6136 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 6137 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 6138 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 6139 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 6140 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 6141 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 6142 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 6143 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 6144 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6145 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6146 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6147 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6148 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6149 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6150 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6151 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6152 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6153 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6154 6155 #undef SYSCTL_ADD_T4_REG64 6156 6157 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6158 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6159 &pi->stats.name, desc) 6160 6161 /* We get these from port_stats and they may be stale by up to 1s */ 6162 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6163 "# drops due to buffer-group 0 overflows"); 6164 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6165 "# drops due to buffer-group 1 overflows"); 6166 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6167 "# drops due to buffer-group 2 overflows"); 6168 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6169 "# drops due to buffer-group 3 overflows"); 6170 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6171 "# of buffer-group 0 truncated packets"); 6172 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6173 "# of buffer-group 1 truncated packets"); 6174 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6175 "# of buffer-group 2 truncated packets"); 6176 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6177 "# of buffer-group 3 truncated packets"); 6178 6179 #undef SYSCTL_ADD_T4_PORTSTAT 6180 6181 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6182 CTLFLAG_RD, &pi->tx_tls_records, 6183 "# of TLS records transmitted"); 6184 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6185 CTLFLAG_RD, &pi->tx_tls_octets, 6186 "# of payload octets in transmitted TLS records"); 6187 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6188 CTLFLAG_RD, &pi->rx_tls_records, 6189 "# of TLS records received"); 6190 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6191 CTLFLAG_RD, &pi->rx_tls_octets, 6192 "# of payload octets in received TLS records"); 6193 } 6194 6195 static int 6196 sysctl_int_array(SYSCTL_HANDLER_ARGS) 6197 { 6198 int rc, *i, space = 0; 6199 struct sbuf sb; 6200 6201 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6202 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6203 if (space) 6204 sbuf_printf(&sb, " "); 6205 sbuf_printf(&sb, "%d", *i); 6206 space = 1; 6207 } 6208 rc = sbuf_finish(&sb); 6209 sbuf_delete(&sb); 6210 return (rc); 6211 } 6212 6213 static int 6214 sysctl_bitfield(SYSCTL_HANDLER_ARGS) 6215 { 6216 int rc; 6217 struct sbuf *sb; 6218 6219 rc = sysctl_wire_old_buffer(req, 0); 6220 if (rc != 0) 6221 return(rc); 6222 6223 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6224 if (sb == NULL) 6225 return (ENOMEM); 6226 6227 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 6228 rc = sbuf_finish(sb); 6229 sbuf_delete(sb); 6230 6231 return (rc); 6232 } 6233 6234 static int 6235 sysctl_btphy(SYSCTL_HANDLER_ARGS) 6236 { 6237 struct port_info *pi = arg1; 6238 int op = arg2; 6239 struct adapter *sc = pi->adapter; 6240 u_int v; 6241 int rc; 6242 6243 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6244 if (rc) 6245 return (rc); 6246 /* XXX: magic numbers */ 6247 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6248 &v); 6249 end_synchronized_op(sc, 0); 6250 if (rc) 6251 return (rc); 6252 if (op == 0) 6253 v /= 256; 6254 6255 rc = sysctl_handle_int(oidp, &v, 0, req); 6256 return (rc); 6257 } 6258 6259 static int 6260 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6261 { 6262 struct vi_info *vi = arg1; 6263 int rc, val; 6264 6265 val = vi->rsrv_noflowq; 6266 rc = sysctl_handle_int(oidp, &val, 0, req); 6267 if (rc != 0 || req->newptr == NULL) 6268 return (rc); 6269 6270 if ((val >= 1) && (vi->ntxq > 1)) 6271 vi->rsrv_noflowq = 1; 6272 else 6273 vi->rsrv_noflowq = 0; 6274 6275 return (rc); 6276 } 6277 6278 static int 6279 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6280 { 6281 struct vi_info *vi = arg1; 6282 struct adapter *sc = vi->pi->adapter; 6283 int idx, rc, i; 6284 struct sge_rxq *rxq; 6285 uint8_t v; 6286 6287 idx = vi->tmr_idx; 6288 6289 rc = sysctl_handle_int(oidp, &idx, 0, req); 6290 if (rc != 0 || req->newptr == NULL) 6291 return (rc); 6292 6293 if (idx < 0 || idx >= SGE_NTIMERS) 6294 return (EINVAL); 6295 6296 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6297 "t4tmr"); 6298 if (rc) 6299 return (rc); 6300 6301 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6302 for_each_rxq(vi, i, rxq) { 6303 #ifdef atomic_store_rel_8 6304 atomic_store_rel_8(&rxq->iq.intr_params, v); 6305 #else 6306 rxq->iq.intr_params = v; 6307 #endif 6308 } 6309 vi->tmr_idx = idx; 6310 6311 end_synchronized_op(sc, LOCK_HELD); 6312 return (0); 6313 } 6314 6315 static int 6316 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6317 { 6318 struct vi_info *vi = arg1; 6319 struct adapter *sc = vi->pi->adapter; 6320 int idx, rc; 6321 6322 idx = vi->pktc_idx; 6323 6324 rc = sysctl_handle_int(oidp, &idx, 0, req); 6325 if (rc != 0 || req->newptr == NULL) 6326 return (rc); 6327 6328 if (idx < -1 || idx >= SGE_NCOUNTERS) 6329 return (EINVAL); 6330 6331 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6332 "t4pktc"); 6333 if (rc) 6334 return (rc); 6335 6336 if (vi->flags & VI_INIT_DONE) 6337 rc = EBUSY; /* cannot be changed once the queues are created */ 6338 else 6339 vi->pktc_idx = idx; 6340 6341 end_synchronized_op(sc, LOCK_HELD); 6342 return (rc); 6343 } 6344 6345 static int 6346 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6347 { 6348 struct vi_info *vi = arg1; 6349 struct adapter *sc = vi->pi->adapter; 6350 int qsize, rc; 6351 6352 qsize = vi->qsize_rxq; 6353 6354 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6355 if (rc != 0 || req->newptr == NULL) 6356 return (rc); 6357 6358 if (qsize < 128 || (qsize & 7)) 6359 return (EINVAL); 6360 6361 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6362 "t4rxqs"); 6363 if (rc) 6364 return (rc); 6365 6366 if (vi->flags & VI_INIT_DONE) 6367 rc = EBUSY; /* cannot be changed once the queues are created */ 6368 else 6369 vi->qsize_rxq = qsize; 6370 6371 end_synchronized_op(sc, LOCK_HELD); 6372 return (rc); 6373 } 6374 6375 static int 6376 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6377 { 6378 struct vi_info *vi = arg1; 6379 struct adapter *sc = vi->pi->adapter; 6380 int qsize, rc; 6381 6382 qsize = vi->qsize_txq; 6383 6384 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6385 if (rc != 0 || req->newptr == NULL) 6386 return (rc); 6387 6388 if (qsize < 128 || qsize > 65536) 6389 return (EINVAL); 6390 6391 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6392 "t4txqs"); 6393 if (rc) 6394 return (rc); 6395 6396 if (vi->flags & VI_INIT_DONE) 6397 rc = EBUSY; /* cannot be changed once the queues are created */ 6398 else 6399 vi->qsize_txq = qsize; 6400 6401 end_synchronized_op(sc, LOCK_HELD); 6402 return (rc); 6403 } 6404 6405 static int 6406 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6407 { 6408 struct port_info *pi = arg1; 6409 struct adapter *sc = pi->adapter; 6410 struct link_config *lc = &pi->link_cfg; 6411 int rc; 6412 6413 if (req->newptr == NULL) { 6414 struct sbuf *sb; 6415 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX"; 6416 6417 rc = sysctl_wire_old_buffer(req, 0); 6418 if (rc != 0) 6419 return(rc); 6420 6421 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6422 if (sb == NULL) 6423 return (ENOMEM); 6424 6425 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits); 6426 rc = sbuf_finish(sb); 6427 sbuf_delete(sb); 6428 } else { 6429 char s[2]; 6430 int n; 6431 6432 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX)); 6433 s[1] = 0; 6434 6435 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6436 if (rc != 0) 6437 return(rc); 6438 6439 if (s[1] != 0) 6440 return (EINVAL); 6441 if (s[0] < '0' || s[0] > '9') 6442 return (EINVAL); /* not a number */ 6443 n = s[0] - '0'; 6444 if (n & ~(PAUSE_TX | PAUSE_RX)) 6445 return (EINVAL); /* some other bit is set too */ 6446 6447 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6448 "t4PAUSE"); 6449 if (rc) 6450 return (rc); 6451 PORT_LOCK(pi); 6452 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) { 6453 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 6454 lc->requested_fc |= n; 6455 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6456 if (rc == 0) { 6457 lc->fc = lc->requested_fc; 6458 set_current_media(pi, &pi->media); 6459 } 6460 } 6461 PORT_UNLOCK(pi); 6462 end_synchronized_op(sc, 0); 6463 } 6464 6465 return (rc); 6466 } 6467 6468 static int 6469 sysctl_fec(SYSCTL_HANDLER_ARGS) 6470 { 6471 struct port_info *pi = arg1; 6472 struct adapter *sc = pi->adapter; 6473 struct link_config *lc = &pi->link_cfg; 6474 int rc; 6475 6476 if (req->newptr == NULL) { 6477 struct sbuf *sb; 6478 static char *bits = "\20\1RS\2BASER_RS\3RESERVED"; 6479 6480 rc = sysctl_wire_old_buffer(req, 0); 6481 if (rc != 0) 6482 return(rc); 6483 6484 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6485 if (sb == NULL) 6486 return (ENOMEM); 6487 6488 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits); 6489 rc = sbuf_finish(sb); 6490 sbuf_delete(sb); 6491 } else { 6492 char s[2]; 6493 int n; 6494 6495 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC); 6496 s[1] = 0; 6497 6498 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6499 if (rc != 0) 6500 return(rc); 6501 6502 if (s[1] != 0) 6503 return (EINVAL); 6504 if (s[0] < '0' || s[0] > '9') 6505 return (EINVAL); /* not a number */ 6506 n = s[0] - '0'; 6507 if (n & ~M_FW_PORT_CAP_FEC) 6508 return (EINVAL); /* some other bit is set too */ 6509 if (!powerof2(n)) 6510 return (EINVAL); /* one bit can be set at most */ 6511 6512 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6513 "t4fec"); 6514 if (rc) 6515 return (rc); 6516 PORT_LOCK(pi); 6517 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) { 6518 lc->requested_fec = n & 6519 G_FW_PORT_CAP_FEC(lc->supported); 6520 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6521 if (rc == 0) { 6522 lc->fec = lc->requested_fec; 6523 } 6524 } 6525 PORT_UNLOCK(pi); 6526 end_synchronized_op(sc, 0); 6527 } 6528 6529 return (rc); 6530 } 6531 6532 static int 6533 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 6534 { 6535 struct port_info *pi = arg1; 6536 struct adapter *sc = pi->adapter; 6537 struct link_config *lc = &pi->link_cfg; 6538 int rc, val, old; 6539 6540 if (lc->supported & FW_PORT_CAP_ANEG) 6541 val = lc->requested_aneg == AUTONEG_ENABLE ? 1 : 0; 6542 else 6543 val = -1; 6544 rc = sysctl_handle_int(oidp, &val, 0, req); 6545 if (rc != 0 || req->newptr == NULL) 6546 return (rc); 6547 if (val == 0) 6548 val = AUTONEG_DISABLE; 6549 else if (val == 1) 6550 val = AUTONEG_ENABLE; 6551 else 6552 return (EINVAL); 6553 6554 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6555 "t4aneg"); 6556 if (rc) 6557 return (rc); 6558 PORT_LOCK(pi); 6559 if ((lc->supported & FW_PORT_CAP_ANEG) == 0) { 6560 rc = ENOTSUP; 6561 goto done; 6562 } 6563 if (lc->requested_aneg == val) { 6564 rc = 0; /* no change, do nothing. */ 6565 goto done; 6566 } 6567 old = lc->requested_aneg; 6568 lc->requested_aneg = val; 6569 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6570 if (rc != 0) 6571 lc->requested_aneg = old; 6572 else 6573 set_current_media(pi, &pi->media); 6574 done: 6575 PORT_UNLOCK(pi); 6576 end_synchronized_op(sc, 0); 6577 return (rc); 6578 } 6579 6580 static int 6581 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 6582 { 6583 struct adapter *sc = arg1; 6584 int reg = arg2; 6585 uint64_t val; 6586 6587 val = t4_read_reg64(sc, reg); 6588 6589 return (sysctl_handle_64(oidp, &val, 0, req)); 6590 } 6591 6592 static int 6593 sysctl_temperature(SYSCTL_HANDLER_ARGS) 6594 { 6595 struct adapter *sc = arg1; 6596 int rc, t; 6597 uint32_t param, val; 6598 6599 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 6600 if (rc) 6601 return (rc); 6602 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6603 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 6604 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 6605 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6606 end_synchronized_op(sc, 0); 6607 if (rc) 6608 return (rc); 6609 6610 /* unknown is returned as 0 but we display -1 in that case */ 6611 t = val == 0 ? -1 : val; 6612 6613 rc = sysctl_handle_int(oidp, &t, 0, req); 6614 return (rc); 6615 } 6616 6617 static int 6618 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 6619 { 6620 struct adapter *sc = arg1; 6621 struct sbuf *sb; 6622 int rc; 6623 uint32_t param, val; 6624 6625 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 6626 if (rc) 6627 return (rc); 6628 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6629 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 6630 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6631 end_synchronized_op(sc, 0); 6632 if (rc) 6633 return (rc); 6634 6635 rc = sysctl_wire_old_buffer(req, 0); 6636 if (rc != 0) 6637 return (rc); 6638 6639 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6640 if (sb == NULL) 6641 return (ENOMEM); 6642 6643 if (val == 0xffffffff) { 6644 /* Only debug and custom firmwares report load averages. */ 6645 sbuf_printf(sb, "not available"); 6646 } else { 6647 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 6648 (val >> 16) & 0xff); 6649 } 6650 rc = sbuf_finish(sb); 6651 sbuf_delete(sb); 6652 6653 return (rc); 6654 } 6655 6656 static int 6657 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 6658 { 6659 struct adapter *sc = arg1; 6660 struct sbuf *sb; 6661 int rc, i; 6662 uint16_t incr[NMTUS][NCCTRL_WIN]; 6663 static const char *dec_fac[] = { 6664 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 6665 "0.9375" 6666 }; 6667 6668 rc = sysctl_wire_old_buffer(req, 0); 6669 if (rc != 0) 6670 return (rc); 6671 6672 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6673 if (sb == NULL) 6674 return (ENOMEM); 6675 6676 t4_read_cong_tbl(sc, incr); 6677 6678 for (i = 0; i < NCCTRL_WIN; ++i) { 6679 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 6680 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 6681 incr[5][i], incr[6][i], incr[7][i]); 6682 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 6683 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 6684 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 6685 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 6686 } 6687 6688 rc = sbuf_finish(sb); 6689 sbuf_delete(sb); 6690 6691 return (rc); 6692 } 6693 6694 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 6695 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 6696 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 6697 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 6698 }; 6699 6700 static int 6701 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 6702 { 6703 struct adapter *sc = arg1; 6704 struct sbuf *sb; 6705 int rc, i, n, qid = arg2; 6706 uint32_t *buf, *p; 6707 char *qtype; 6708 u_int cim_num_obq = sc->chip_params->cim_num_obq; 6709 6710 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 6711 ("%s: bad qid %d\n", __func__, qid)); 6712 6713 if (qid < CIM_NUM_IBQ) { 6714 /* inbound queue */ 6715 qtype = "IBQ"; 6716 n = 4 * CIM_IBQ_SIZE; 6717 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6718 rc = t4_read_cim_ibq(sc, qid, buf, n); 6719 } else { 6720 /* outbound queue */ 6721 qtype = "OBQ"; 6722 qid -= CIM_NUM_IBQ; 6723 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 6724 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6725 rc = t4_read_cim_obq(sc, qid, buf, n); 6726 } 6727 6728 if (rc < 0) { 6729 rc = -rc; 6730 goto done; 6731 } 6732 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 6733 6734 rc = sysctl_wire_old_buffer(req, 0); 6735 if (rc != 0) 6736 goto done; 6737 6738 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6739 if (sb == NULL) { 6740 rc = ENOMEM; 6741 goto done; 6742 } 6743 6744 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 6745 for (i = 0, p = buf; i < n; i += 16, p += 4) 6746 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 6747 p[2], p[3]); 6748 6749 rc = sbuf_finish(sb); 6750 sbuf_delete(sb); 6751 done: 6752 free(buf, M_CXGBE); 6753 return (rc); 6754 } 6755 6756 static int 6757 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 6758 { 6759 struct adapter *sc = arg1; 6760 u_int cfg; 6761 struct sbuf *sb; 6762 uint32_t *buf, *p; 6763 int rc; 6764 6765 MPASS(chip_id(sc) <= CHELSIO_T5); 6766 6767 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6768 if (rc != 0) 6769 return (rc); 6770 6771 rc = sysctl_wire_old_buffer(req, 0); 6772 if (rc != 0) 6773 return (rc); 6774 6775 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6776 if (sb == NULL) 6777 return (ENOMEM); 6778 6779 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6780 M_ZERO | M_WAITOK); 6781 6782 rc = -t4_cim_read_la(sc, buf, NULL); 6783 if (rc != 0) 6784 goto done; 6785 6786 sbuf_printf(sb, "Status Data PC%s", 6787 cfg & F_UPDBGLACAPTPCONLY ? "" : 6788 " LS0Stat LS0Addr LS0Data"); 6789 6790 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 6791 if (cfg & F_UPDBGLACAPTPCONLY) { 6792 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 6793 p[6], p[7]); 6794 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 6795 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 6796 p[4] & 0xff, p[5] >> 8); 6797 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 6798 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6799 p[1] & 0xf, p[2] >> 4); 6800 } else { 6801 sbuf_printf(sb, 6802 "\n %02x %x%07x %x%07x %08x %08x " 6803 "%08x%08x%08x%08x", 6804 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6805 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 6806 p[6], p[7]); 6807 } 6808 } 6809 6810 rc = sbuf_finish(sb); 6811 sbuf_delete(sb); 6812 done: 6813 free(buf, M_CXGBE); 6814 return (rc); 6815 } 6816 6817 static int 6818 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 6819 { 6820 struct adapter *sc = arg1; 6821 u_int cfg; 6822 struct sbuf *sb; 6823 uint32_t *buf, *p; 6824 int rc; 6825 6826 MPASS(chip_id(sc) > CHELSIO_T5); 6827 6828 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6829 if (rc != 0) 6830 return (rc); 6831 6832 rc = sysctl_wire_old_buffer(req, 0); 6833 if (rc != 0) 6834 return (rc); 6835 6836 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6837 if (sb == NULL) 6838 return (ENOMEM); 6839 6840 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6841 M_ZERO | M_WAITOK); 6842 6843 rc = -t4_cim_read_la(sc, buf, NULL); 6844 if (rc != 0) 6845 goto done; 6846 6847 sbuf_printf(sb, "Status Inst Data PC%s", 6848 cfg & F_UPDBGLACAPTPCONLY ? "" : 6849 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 6850 6851 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 6852 if (cfg & F_UPDBGLACAPTPCONLY) { 6853 sbuf_printf(sb, "\n %02x %08x %08x %08x", 6854 p[3] & 0xff, p[2], p[1], p[0]); 6855 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 6856 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 6857 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 6858 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 6859 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 6860 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 6861 p[6] >> 16); 6862 } else { 6863 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 6864 "%08x %08x %08x %08x %08x %08x", 6865 (p[9] >> 16) & 0xff, 6866 p[9] & 0xffff, p[8] >> 16, 6867 p[8] & 0xffff, p[7] >> 16, 6868 p[7] & 0xffff, p[6] >> 16, 6869 p[2], p[1], p[0], p[5], p[4], p[3]); 6870 } 6871 } 6872 6873 rc = sbuf_finish(sb); 6874 sbuf_delete(sb); 6875 done: 6876 free(buf, M_CXGBE); 6877 return (rc); 6878 } 6879 6880 static int 6881 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 6882 { 6883 struct adapter *sc = arg1; 6884 u_int i; 6885 struct sbuf *sb; 6886 uint32_t *buf, *p; 6887 int rc; 6888 6889 rc = sysctl_wire_old_buffer(req, 0); 6890 if (rc != 0) 6891 return (rc); 6892 6893 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6894 if (sb == NULL) 6895 return (ENOMEM); 6896 6897 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 6898 M_ZERO | M_WAITOK); 6899 6900 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 6901 p = buf; 6902 6903 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6904 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 6905 p[1], p[0]); 6906 } 6907 6908 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 6909 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6910 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 6911 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 6912 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 6913 (p[1] >> 2) | ((p[2] & 3) << 30), 6914 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 6915 p[0] & 1); 6916 } 6917 6918 rc = sbuf_finish(sb); 6919 sbuf_delete(sb); 6920 free(buf, M_CXGBE); 6921 return (rc); 6922 } 6923 6924 static int 6925 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 6926 { 6927 struct adapter *sc = arg1; 6928 u_int i; 6929 struct sbuf *sb; 6930 uint32_t *buf, *p; 6931 int rc; 6932 6933 rc = sysctl_wire_old_buffer(req, 0); 6934 if (rc != 0) 6935 return (rc); 6936 6937 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6938 if (sb == NULL) 6939 return (ENOMEM); 6940 6941 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 6942 M_ZERO | M_WAITOK); 6943 6944 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 6945 p = buf; 6946 6947 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 6948 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6949 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 6950 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 6951 p[4], p[3], p[2], p[1], p[0]); 6952 } 6953 6954 sbuf_printf(sb, "\n\nCntl ID Data"); 6955 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6956 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 6957 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 6958 } 6959 6960 rc = sbuf_finish(sb); 6961 sbuf_delete(sb); 6962 free(buf, M_CXGBE); 6963 return (rc); 6964 } 6965 6966 static int 6967 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 6968 { 6969 struct adapter *sc = arg1; 6970 struct sbuf *sb; 6971 int rc, i; 6972 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6973 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6974 uint16_t thres[CIM_NUM_IBQ]; 6975 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 6976 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 6977 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 6978 6979 cim_num_obq = sc->chip_params->cim_num_obq; 6980 if (is_t4(sc)) { 6981 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 6982 obq_rdaddr = A_UP_OBQ_0_REALADDR; 6983 } else { 6984 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 6985 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 6986 } 6987 nq = CIM_NUM_IBQ + cim_num_obq; 6988 6989 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 6990 if (rc == 0) 6991 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 6992 if (rc != 0) 6993 return (rc); 6994 6995 t4_read_cimq_cfg(sc, base, size, thres); 6996 6997 rc = sysctl_wire_old_buffer(req, 0); 6998 if (rc != 0) 6999 return (rc); 7000 7001 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7002 if (sb == NULL) 7003 return (ENOMEM); 7004 7005 sbuf_printf(sb, 7006 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 7007 7008 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 7009 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 7010 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 7011 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7012 G_QUEREMFLITS(p[2]) * 16); 7013 for ( ; i < nq; i++, p += 4, wr += 2) 7014 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 7015 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 7016 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7017 G_QUEREMFLITS(p[2]) * 16); 7018 7019 rc = sbuf_finish(sb); 7020 sbuf_delete(sb); 7021 7022 return (rc); 7023 } 7024 7025 static int 7026 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 7027 { 7028 struct adapter *sc = arg1; 7029 struct sbuf *sb; 7030 int rc; 7031 struct tp_cpl_stats stats; 7032 7033 rc = sysctl_wire_old_buffer(req, 0); 7034 if (rc != 0) 7035 return (rc); 7036 7037 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7038 if (sb == NULL) 7039 return (ENOMEM); 7040 7041 mtx_lock(&sc->reg_lock); 7042 t4_tp_get_cpl_stats(sc, &stats, 0); 7043 mtx_unlock(&sc->reg_lock); 7044 7045 if (sc->chip_params->nchan > 2) { 7046 sbuf_printf(sb, " channel 0 channel 1" 7047 " channel 2 channel 3"); 7048 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 7049 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 7050 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 7051 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 7052 } else { 7053 sbuf_printf(sb, " channel 0 channel 1"); 7054 sbuf_printf(sb, "\nCPL requests: %10u %10u", 7055 stats.req[0], stats.req[1]); 7056 sbuf_printf(sb, "\nCPL responses: %10u %10u", 7057 stats.rsp[0], stats.rsp[1]); 7058 } 7059 7060 rc = sbuf_finish(sb); 7061 sbuf_delete(sb); 7062 7063 return (rc); 7064 } 7065 7066 static int 7067 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 7068 { 7069 struct adapter *sc = arg1; 7070 struct sbuf *sb; 7071 int rc; 7072 struct tp_usm_stats stats; 7073 7074 rc = sysctl_wire_old_buffer(req, 0); 7075 if (rc != 0) 7076 return(rc); 7077 7078 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7079 if (sb == NULL) 7080 return (ENOMEM); 7081 7082 t4_get_usm_stats(sc, &stats, 1); 7083 7084 sbuf_printf(sb, "Frames: %u\n", stats.frames); 7085 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 7086 sbuf_printf(sb, "Drops: %u", stats.drops); 7087 7088 rc = sbuf_finish(sb); 7089 sbuf_delete(sb); 7090 7091 return (rc); 7092 } 7093 7094 static const char * const devlog_level_strings[] = { 7095 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 7096 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 7097 [FW_DEVLOG_LEVEL_ERR] = "ERR", 7098 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 7099 [FW_DEVLOG_LEVEL_INFO] = "INFO", 7100 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 7101 }; 7102 7103 static const char * const devlog_facility_strings[] = { 7104 [FW_DEVLOG_FACILITY_CORE] = "CORE", 7105 [FW_DEVLOG_FACILITY_CF] = "CF", 7106 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 7107 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 7108 [FW_DEVLOG_FACILITY_RES] = "RES", 7109 [FW_DEVLOG_FACILITY_HW] = "HW", 7110 [FW_DEVLOG_FACILITY_FLR] = "FLR", 7111 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 7112 [FW_DEVLOG_FACILITY_PHY] = "PHY", 7113 [FW_DEVLOG_FACILITY_MAC] = "MAC", 7114 [FW_DEVLOG_FACILITY_PORT] = "PORT", 7115 [FW_DEVLOG_FACILITY_VI] = "VI", 7116 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 7117 [FW_DEVLOG_FACILITY_ACL] = "ACL", 7118 [FW_DEVLOG_FACILITY_TM] = "TM", 7119 [FW_DEVLOG_FACILITY_QFC] = "QFC", 7120 [FW_DEVLOG_FACILITY_DCB] = "DCB", 7121 [FW_DEVLOG_FACILITY_ETH] = "ETH", 7122 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 7123 [FW_DEVLOG_FACILITY_RI] = "RI", 7124 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 7125 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 7126 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 7127 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 7128 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 7129 }; 7130 7131 static int 7132 sysctl_devlog(SYSCTL_HANDLER_ARGS) 7133 { 7134 struct adapter *sc = arg1; 7135 struct devlog_params *dparams = &sc->params.devlog; 7136 struct fw_devlog_e *buf, *e; 7137 int i, j, rc, nentries, first = 0; 7138 struct sbuf *sb; 7139 uint64_t ftstamp = UINT64_MAX; 7140 7141 if (dparams->addr == 0) 7142 return (ENXIO); 7143 7144 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 7145 if (buf == NULL) 7146 return (ENOMEM); 7147 7148 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 7149 if (rc != 0) 7150 goto done; 7151 7152 nentries = dparams->size / sizeof(struct fw_devlog_e); 7153 for (i = 0; i < nentries; i++) { 7154 e = &buf[i]; 7155 7156 if (e->timestamp == 0) 7157 break; /* end */ 7158 7159 e->timestamp = be64toh(e->timestamp); 7160 e->seqno = be32toh(e->seqno); 7161 for (j = 0; j < 8; j++) 7162 e->params[j] = be32toh(e->params[j]); 7163 7164 if (e->timestamp < ftstamp) { 7165 ftstamp = e->timestamp; 7166 first = i; 7167 } 7168 } 7169 7170 if (buf[first].timestamp == 0) 7171 goto done; /* nothing in the log */ 7172 7173 rc = sysctl_wire_old_buffer(req, 0); 7174 if (rc != 0) 7175 goto done; 7176 7177 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7178 if (sb == NULL) { 7179 rc = ENOMEM; 7180 goto done; 7181 } 7182 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 7183 "Seq#", "Tstamp", "Level", "Facility", "Message"); 7184 7185 i = first; 7186 do { 7187 e = &buf[i]; 7188 if (e->timestamp == 0) 7189 break; /* end */ 7190 7191 sbuf_printf(sb, "%10d %15ju %8s %8s ", 7192 e->seqno, e->timestamp, 7193 (e->level < nitems(devlog_level_strings) ? 7194 devlog_level_strings[e->level] : "UNKNOWN"), 7195 (e->facility < nitems(devlog_facility_strings) ? 7196 devlog_facility_strings[e->facility] : "UNKNOWN")); 7197 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7198 e->params[2], e->params[3], e->params[4], 7199 e->params[5], e->params[6], e->params[7]); 7200 7201 if (++i == nentries) 7202 i = 0; 7203 } while (i != first); 7204 7205 rc = sbuf_finish(sb); 7206 sbuf_delete(sb); 7207 done: 7208 free(buf, M_CXGBE); 7209 return (rc); 7210 } 7211 7212 static int 7213 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7214 { 7215 struct adapter *sc = arg1; 7216 struct sbuf *sb; 7217 int rc; 7218 struct tp_fcoe_stats stats[MAX_NCHAN]; 7219 int i, nchan = sc->chip_params->nchan; 7220 7221 rc = sysctl_wire_old_buffer(req, 0); 7222 if (rc != 0) 7223 return (rc); 7224 7225 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7226 if (sb == NULL) 7227 return (ENOMEM); 7228 7229 for (i = 0; i < nchan; i++) 7230 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7231 7232 if (nchan > 2) { 7233 sbuf_printf(sb, " channel 0 channel 1" 7234 " channel 2 channel 3"); 7235 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7236 stats[0].octets_ddp, stats[1].octets_ddp, 7237 stats[2].octets_ddp, stats[3].octets_ddp); 7238 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7239 stats[0].frames_ddp, stats[1].frames_ddp, 7240 stats[2].frames_ddp, stats[3].frames_ddp); 7241 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7242 stats[0].frames_drop, stats[1].frames_drop, 7243 stats[2].frames_drop, stats[3].frames_drop); 7244 } else { 7245 sbuf_printf(sb, " channel 0 channel 1"); 7246 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7247 stats[0].octets_ddp, stats[1].octets_ddp); 7248 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7249 stats[0].frames_ddp, stats[1].frames_ddp); 7250 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7251 stats[0].frames_drop, stats[1].frames_drop); 7252 } 7253 7254 rc = sbuf_finish(sb); 7255 sbuf_delete(sb); 7256 7257 return (rc); 7258 } 7259 7260 static int 7261 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7262 { 7263 struct adapter *sc = arg1; 7264 struct sbuf *sb; 7265 int rc, i; 7266 unsigned int map, kbps, ipg, mode; 7267 unsigned int pace_tab[NTX_SCHED]; 7268 7269 rc = sysctl_wire_old_buffer(req, 0); 7270 if (rc != 0) 7271 return (rc); 7272 7273 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7274 if (sb == NULL) 7275 return (ENOMEM); 7276 7277 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7278 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7279 t4_read_pace_tbl(sc, pace_tab); 7280 7281 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7282 "Class IPG (0.1 ns) Flow IPG (us)"); 7283 7284 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7285 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7286 sbuf_printf(sb, "\n %u %-5s %u ", i, 7287 (mode & (1 << i)) ? "flow" : "class", map & 3); 7288 if (kbps) 7289 sbuf_printf(sb, "%9u ", kbps); 7290 else 7291 sbuf_printf(sb, " disabled "); 7292 7293 if (ipg) 7294 sbuf_printf(sb, "%13u ", ipg); 7295 else 7296 sbuf_printf(sb, " disabled "); 7297 7298 if (pace_tab[i]) 7299 sbuf_printf(sb, "%10u", pace_tab[i]); 7300 else 7301 sbuf_printf(sb, " disabled"); 7302 } 7303 7304 rc = sbuf_finish(sb); 7305 sbuf_delete(sb); 7306 7307 return (rc); 7308 } 7309 7310 static int 7311 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7312 { 7313 struct adapter *sc = arg1; 7314 struct sbuf *sb; 7315 int rc, i, j; 7316 uint64_t *p0, *p1; 7317 struct lb_port_stats s[2]; 7318 static const char *stat_name[] = { 7319 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7320 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7321 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7322 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7323 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7324 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7325 "BG2FramesTrunc:", "BG3FramesTrunc:" 7326 }; 7327 7328 rc = sysctl_wire_old_buffer(req, 0); 7329 if (rc != 0) 7330 return (rc); 7331 7332 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7333 if (sb == NULL) 7334 return (ENOMEM); 7335 7336 memset(s, 0, sizeof(s)); 7337 7338 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7339 t4_get_lb_stats(sc, i, &s[0]); 7340 t4_get_lb_stats(sc, i + 1, &s[1]); 7341 7342 p0 = &s[0].octets; 7343 p1 = &s[1].octets; 7344 sbuf_printf(sb, "%s Loopback %u" 7345 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7346 7347 for (j = 0; j < nitems(stat_name); j++) 7348 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7349 *p0++, *p1++); 7350 } 7351 7352 rc = sbuf_finish(sb); 7353 sbuf_delete(sb); 7354 7355 return (rc); 7356 } 7357 7358 static int 7359 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7360 { 7361 int rc = 0; 7362 struct port_info *pi = arg1; 7363 struct link_config *lc = &pi->link_cfg; 7364 struct sbuf *sb; 7365 7366 rc = sysctl_wire_old_buffer(req, 0); 7367 if (rc != 0) 7368 return(rc); 7369 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7370 if (sb == NULL) 7371 return (ENOMEM); 7372 7373 if (lc->link_ok || lc->link_down_rc == 255) 7374 sbuf_printf(sb, "n/a"); 7375 else 7376 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7377 7378 rc = sbuf_finish(sb); 7379 sbuf_delete(sb); 7380 7381 return (rc); 7382 } 7383 7384 struct mem_desc { 7385 unsigned int base; 7386 unsigned int limit; 7387 unsigned int idx; 7388 }; 7389 7390 static int 7391 mem_desc_cmp(const void *a, const void *b) 7392 { 7393 return ((const struct mem_desc *)a)->base - 7394 ((const struct mem_desc *)b)->base; 7395 } 7396 7397 static void 7398 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7399 unsigned int to) 7400 { 7401 unsigned int size; 7402 7403 if (from == to) 7404 return; 7405 7406 size = to - from + 1; 7407 if (size == 0) 7408 return; 7409 7410 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7411 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7412 } 7413 7414 static int 7415 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7416 { 7417 struct adapter *sc = arg1; 7418 struct sbuf *sb; 7419 int rc, i, n; 7420 uint32_t lo, hi, used, alloc; 7421 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 7422 static const char *region[] = { 7423 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 7424 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 7425 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 7426 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 7427 "RQUDP region:", "PBL region:", "TXPBL region:", 7428 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 7429 "On-chip queues:", "TLS keys:", 7430 }; 7431 struct mem_desc avail[4]; 7432 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 7433 struct mem_desc *md = mem; 7434 7435 rc = sysctl_wire_old_buffer(req, 0); 7436 if (rc != 0) 7437 return (rc); 7438 7439 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7440 if (sb == NULL) 7441 return (ENOMEM); 7442 7443 for (i = 0; i < nitems(mem); i++) { 7444 mem[i].limit = 0; 7445 mem[i].idx = i; 7446 } 7447 7448 /* Find and sort the populated memory ranges */ 7449 i = 0; 7450 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 7451 if (lo & F_EDRAM0_ENABLE) { 7452 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 7453 avail[i].base = G_EDRAM0_BASE(hi) << 20; 7454 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 7455 avail[i].idx = 0; 7456 i++; 7457 } 7458 if (lo & F_EDRAM1_ENABLE) { 7459 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 7460 avail[i].base = G_EDRAM1_BASE(hi) << 20; 7461 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 7462 avail[i].idx = 1; 7463 i++; 7464 } 7465 if (lo & F_EXT_MEM_ENABLE) { 7466 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 7467 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 7468 avail[i].limit = avail[i].base + 7469 (G_EXT_MEM_SIZE(hi) << 20); 7470 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 7471 i++; 7472 } 7473 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 7474 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 7475 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 7476 avail[i].limit = avail[i].base + 7477 (G_EXT_MEM1_SIZE(hi) << 20); 7478 avail[i].idx = 4; 7479 i++; 7480 } 7481 if (!i) /* no memory available */ 7482 return 0; 7483 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 7484 7485 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 7486 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 7487 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 7488 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 7489 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 7490 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 7491 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 7492 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 7493 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 7494 7495 /* the next few have explicit upper bounds */ 7496 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 7497 md->limit = md->base - 1 + 7498 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 7499 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 7500 md++; 7501 7502 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 7503 md->limit = md->base - 1 + 7504 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 7505 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 7506 md++; 7507 7508 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7509 if (chip_id(sc) <= CHELSIO_T5) 7510 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 7511 else 7512 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 7513 md->limit = 0; 7514 } else { 7515 md->base = 0; 7516 md->idx = nitems(region); /* hide it */ 7517 } 7518 md++; 7519 7520 #define ulp_region(reg) \ 7521 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 7522 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 7523 7524 ulp_region(RX_ISCSI); 7525 ulp_region(RX_TDDP); 7526 ulp_region(TX_TPT); 7527 ulp_region(RX_STAG); 7528 ulp_region(RX_RQ); 7529 ulp_region(RX_RQUDP); 7530 ulp_region(RX_PBL); 7531 ulp_region(TX_PBL); 7532 #undef ulp_region 7533 7534 md->base = 0; 7535 md->idx = nitems(region); 7536 if (!is_t4(sc)) { 7537 uint32_t size = 0; 7538 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 7539 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 7540 7541 if (is_t5(sc)) { 7542 if (sge_ctrl & F_VFIFO_ENABLE) 7543 size = G_DBVFIFO_SIZE(fifo_size); 7544 } else 7545 size = G_T6_DBVFIFO_SIZE(fifo_size); 7546 7547 if (size) { 7548 md->base = G_BASEADDR(t4_read_reg(sc, 7549 A_SGE_DBVFIFO_BADDR)); 7550 md->limit = md->base + (size << 2) - 1; 7551 } 7552 } 7553 md++; 7554 7555 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 7556 md->limit = 0; 7557 md++; 7558 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 7559 md->limit = 0; 7560 md++; 7561 7562 md->base = sc->vres.ocq.start; 7563 if (sc->vres.ocq.size) 7564 md->limit = md->base + sc->vres.ocq.size - 1; 7565 else 7566 md->idx = nitems(region); /* hide it */ 7567 md++; 7568 7569 md->base = sc->vres.key.start; 7570 if (sc->vres.key.size) 7571 md->limit = md->base + sc->vres.key.size - 1; 7572 else 7573 md->idx = nitems(region); /* hide it */ 7574 md++; 7575 7576 /* add any address-space holes, there can be up to 3 */ 7577 for (n = 0; n < i - 1; n++) 7578 if (avail[n].limit < avail[n + 1].base) 7579 (md++)->base = avail[n].limit; 7580 if (avail[n].limit) 7581 (md++)->base = avail[n].limit; 7582 7583 n = md - mem; 7584 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 7585 7586 for (lo = 0; lo < i; lo++) 7587 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 7588 avail[lo].limit - 1); 7589 7590 sbuf_printf(sb, "\n"); 7591 for (i = 0; i < n; i++) { 7592 if (mem[i].idx >= nitems(region)) 7593 continue; /* skip holes */ 7594 if (!mem[i].limit) 7595 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 7596 mem_region_show(sb, region[mem[i].idx], mem[i].base, 7597 mem[i].limit); 7598 } 7599 7600 sbuf_printf(sb, "\n"); 7601 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 7602 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 7603 mem_region_show(sb, "uP RAM:", lo, hi); 7604 7605 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 7606 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 7607 mem_region_show(sb, "uP Extmem2:", lo, hi); 7608 7609 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 7610 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 7611 G_PMRXMAXPAGE(lo), 7612 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 7613 (lo & F_PMRXNUMCHN) ? 2 : 1); 7614 7615 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 7616 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 7617 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 7618 G_PMTXMAXPAGE(lo), 7619 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 7620 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 7621 sbuf_printf(sb, "%u p-structs\n", 7622 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 7623 7624 for (i = 0; i < 4; i++) { 7625 if (chip_id(sc) > CHELSIO_T5) 7626 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 7627 else 7628 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 7629 if (is_t5(sc)) { 7630 used = G_T5_USED(lo); 7631 alloc = G_T5_ALLOC(lo); 7632 } else { 7633 used = G_USED(lo); 7634 alloc = G_ALLOC(lo); 7635 } 7636 /* For T6 these are MAC buffer groups */ 7637 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 7638 i, used, alloc); 7639 } 7640 for (i = 0; i < sc->chip_params->nchan; i++) { 7641 if (chip_id(sc) > CHELSIO_T5) 7642 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 7643 else 7644 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 7645 if (is_t5(sc)) { 7646 used = G_T5_USED(lo); 7647 alloc = G_T5_ALLOC(lo); 7648 } else { 7649 used = G_USED(lo); 7650 alloc = G_ALLOC(lo); 7651 } 7652 /* For T6 these are MAC buffer groups */ 7653 sbuf_printf(sb, 7654 "\nLoopback %d using %u pages out of %u allocated", 7655 i, used, alloc); 7656 } 7657 7658 rc = sbuf_finish(sb); 7659 sbuf_delete(sb); 7660 7661 return (rc); 7662 } 7663 7664 static inline void 7665 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 7666 { 7667 *mask = x | y; 7668 y = htobe64(y); 7669 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 7670 } 7671 7672 static int 7673 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 7674 { 7675 struct adapter *sc = arg1; 7676 struct sbuf *sb; 7677 int rc, i; 7678 7679 MPASS(chip_id(sc) <= CHELSIO_T5); 7680 7681 rc = sysctl_wire_old_buffer(req, 0); 7682 if (rc != 0) 7683 return (rc); 7684 7685 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7686 if (sb == NULL) 7687 return (ENOMEM); 7688 7689 sbuf_printf(sb, 7690 "Idx Ethernet address Mask Vld Ports PF" 7691 " VF Replication P0 P1 P2 P3 ML"); 7692 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7693 uint64_t tcamx, tcamy, mask; 7694 uint32_t cls_lo, cls_hi; 7695 uint8_t addr[ETHER_ADDR_LEN]; 7696 7697 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 7698 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 7699 if (tcamx & tcamy) 7700 continue; 7701 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7702 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7703 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7704 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 7705 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 7706 addr[3], addr[4], addr[5], (uintmax_t)mask, 7707 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 7708 G_PORTMAP(cls_hi), G_PF(cls_lo), 7709 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 7710 7711 if (cls_lo & F_REPLICATE) { 7712 struct fw_ldst_cmd ldst_cmd; 7713 7714 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7715 ldst_cmd.op_to_addrspace = 7716 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7717 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7718 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7719 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7720 ldst_cmd.u.mps.rplc.fid_idx = 7721 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7722 V_FW_LDST_CMD_IDX(i)); 7723 7724 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7725 "t4mps"); 7726 if (rc) 7727 break; 7728 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7729 sizeof(ldst_cmd), &ldst_cmd); 7730 end_synchronized_op(sc, 0); 7731 7732 if (rc != 0) { 7733 sbuf_printf(sb, "%36d", rc); 7734 rc = 0; 7735 } else { 7736 sbuf_printf(sb, " %08x %08x %08x %08x", 7737 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7738 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7739 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7740 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7741 } 7742 } else 7743 sbuf_printf(sb, "%36s", ""); 7744 7745 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 7746 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 7747 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 7748 } 7749 7750 if (rc) 7751 (void) sbuf_finish(sb); 7752 else 7753 rc = sbuf_finish(sb); 7754 sbuf_delete(sb); 7755 7756 return (rc); 7757 } 7758 7759 static int 7760 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 7761 { 7762 struct adapter *sc = arg1; 7763 struct sbuf *sb; 7764 int rc, i; 7765 7766 MPASS(chip_id(sc) > CHELSIO_T5); 7767 7768 rc = sysctl_wire_old_buffer(req, 0); 7769 if (rc != 0) 7770 return (rc); 7771 7772 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7773 if (sb == NULL) 7774 return (ENOMEM); 7775 7776 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 7777 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 7778 " Replication" 7779 " P0 P1 P2 P3 ML\n"); 7780 7781 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7782 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 7783 uint16_t ivlan; 7784 uint64_t tcamx, tcamy, val, mask; 7785 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 7786 uint8_t addr[ETHER_ADDR_LEN]; 7787 7788 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 7789 if (i < 256) 7790 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 7791 else 7792 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 7793 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7794 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7795 tcamy = G_DMACH(val) << 32; 7796 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7797 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7798 lookup_type = G_DATALKPTYPE(data2); 7799 port_num = G_DATAPORTNUM(data2); 7800 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7801 /* Inner header VNI */ 7802 vniy = ((data2 & F_DATAVIDH2) << 23) | 7803 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7804 dip_hit = data2 & F_DATADIPHIT; 7805 vlan_vld = 0; 7806 } else { 7807 vniy = 0; 7808 dip_hit = 0; 7809 vlan_vld = data2 & F_DATAVIDH2; 7810 ivlan = G_VIDL(val); 7811 } 7812 7813 ctl |= V_CTLXYBITSEL(1); 7814 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7815 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7816 tcamx = G_DMACH(val) << 32; 7817 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7818 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7819 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7820 /* Inner header VNI mask */ 7821 vnix = ((data2 & F_DATAVIDH2) << 23) | 7822 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7823 } else 7824 vnix = 0; 7825 7826 if (tcamx & tcamy) 7827 continue; 7828 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7829 7830 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7831 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7832 7833 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7834 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7835 "%012jx %06x %06x - - %3c" 7836 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 7837 addr[1], addr[2], addr[3], addr[4], addr[5], 7838 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 7839 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7840 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7841 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7842 } else { 7843 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7844 "%012jx - - ", i, addr[0], addr[1], 7845 addr[2], addr[3], addr[4], addr[5], 7846 (uintmax_t)mask); 7847 7848 if (vlan_vld) 7849 sbuf_printf(sb, "%4u Y ", ivlan); 7850 else 7851 sbuf_printf(sb, " - N "); 7852 7853 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 7854 lookup_type ? 'I' : 'O', port_num, 7855 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7856 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7857 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7858 } 7859 7860 7861 if (cls_lo & F_T6_REPLICATE) { 7862 struct fw_ldst_cmd ldst_cmd; 7863 7864 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7865 ldst_cmd.op_to_addrspace = 7866 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7867 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7868 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7869 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7870 ldst_cmd.u.mps.rplc.fid_idx = 7871 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7872 V_FW_LDST_CMD_IDX(i)); 7873 7874 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7875 "t6mps"); 7876 if (rc) 7877 break; 7878 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7879 sizeof(ldst_cmd), &ldst_cmd); 7880 end_synchronized_op(sc, 0); 7881 7882 if (rc != 0) { 7883 sbuf_printf(sb, "%72d", rc); 7884 rc = 0; 7885 } else { 7886 sbuf_printf(sb, " %08x %08x %08x %08x" 7887 " %08x %08x %08x %08x", 7888 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 7889 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 7890 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 7891 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 7892 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7893 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7894 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7895 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7896 } 7897 } else 7898 sbuf_printf(sb, "%72s", ""); 7899 7900 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 7901 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 7902 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 7903 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 7904 } 7905 7906 if (rc) 7907 (void) sbuf_finish(sb); 7908 else 7909 rc = sbuf_finish(sb); 7910 sbuf_delete(sb); 7911 7912 return (rc); 7913 } 7914 7915 static int 7916 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 7917 { 7918 struct adapter *sc = arg1; 7919 struct sbuf *sb; 7920 int rc; 7921 uint16_t mtus[NMTUS]; 7922 7923 rc = sysctl_wire_old_buffer(req, 0); 7924 if (rc != 0) 7925 return (rc); 7926 7927 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7928 if (sb == NULL) 7929 return (ENOMEM); 7930 7931 t4_read_mtu_tbl(sc, mtus, NULL); 7932 7933 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 7934 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 7935 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 7936 mtus[14], mtus[15]); 7937 7938 rc = sbuf_finish(sb); 7939 sbuf_delete(sb); 7940 7941 return (rc); 7942 } 7943 7944 static int 7945 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 7946 { 7947 struct adapter *sc = arg1; 7948 struct sbuf *sb; 7949 int rc, i; 7950 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 7951 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 7952 static const char *tx_stats[MAX_PM_NSTATS] = { 7953 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 7954 "Tx FIFO wait", NULL, "Tx latency" 7955 }; 7956 static const char *rx_stats[MAX_PM_NSTATS] = { 7957 "Read:", "Write bypass:", "Write mem:", "Flush:", 7958 "Rx FIFO wait", NULL, "Rx latency" 7959 }; 7960 7961 rc = sysctl_wire_old_buffer(req, 0); 7962 if (rc != 0) 7963 return (rc); 7964 7965 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7966 if (sb == NULL) 7967 return (ENOMEM); 7968 7969 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 7970 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 7971 7972 sbuf_printf(sb, " Tx pcmds Tx bytes"); 7973 for (i = 0; i < 4; i++) { 7974 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7975 tx_cyc[i]); 7976 } 7977 7978 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 7979 for (i = 0; i < 4; i++) { 7980 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7981 rx_cyc[i]); 7982 } 7983 7984 if (chip_id(sc) > CHELSIO_T5) { 7985 sbuf_printf(sb, 7986 "\n Total wait Total occupancy"); 7987 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7988 tx_cyc[i]); 7989 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7990 rx_cyc[i]); 7991 7992 i += 2; 7993 MPASS(i < nitems(tx_stats)); 7994 7995 sbuf_printf(sb, 7996 "\n Reads Total wait"); 7997 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7998 tx_cyc[i]); 7999 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8000 rx_cyc[i]); 8001 } 8002 8003 rc = sbuf_finish(sb); 8004 sbuf_delete(sb); 8005 8006 return (rc); 8007 } 8008 8009 static int 8010 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 8011 { 8012 struct adapter *sc = arg1; 8013 struct sbuf *sb; 8014 int rc; 8015 struct tp_rdma_stats stats; 8016 8017 rc = sysctl_wire_old_buffer(req, 0); 8018 if (rc != 0) 8019 return (rc); 8020 8021 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8022 if (sb == NULL) 8023 return (ENOMEM); 8024 8025 mtx_lock(&sc->reg_lock); 8026 t4_tp_get_rdma_stats(sc, &stats, 0); 8027 mtx_unlock(&sc->reg_lock); 8028 8029 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 8030 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 8031 8032 rc = sbuf_finish(sb); 8033 sbuf_delete(sb); 8034 8035 return (rc); 8036 } 8037 8038 static int 8039 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 8040 { 8041 struct adapter *sc = arg1; 8042 struct sbuf *sb; 8043 int rc; 8044 struct tp_tcp_stats v4, v6; 8045 8046 rc = sysctl_wire_old_buffer(req, 0); 8047 if (rc != 0) 8048 return (rc); 8049 8050 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8051 if (sb == NULL) 8052 return (ENOMEM); 8053 8054 mtx_lock(&sc->reg_lock); 8055 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 8056 mtx_unlock(&sc->reg_lock); 8057 8058 sbuf_printf(sb, 8059 " IP IPv6\n"); 8060 sbuf_printf(sb, "OutRsts: %20u %20u\n", 8061 v4.tcp_out_rsts, v6.tcp_out_rsts); 8062 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 8063 v4.tcp_in_segs, v6.tcp_in_segs); 8064 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 8065 v4.tcp_out_segs, v6.tcp_out_segs); 8066 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 8067 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 8068 8069 rc = sbuf_finish(sb); 8070 sbuf_delete(sb); 8071 8072 return (rc); 8073 } 8074 8075 static int 8076 sysctl_tids(SYSCTL_HANDLER_ARGS) 8077 { 8078 struct adapter *sc = arg1; 8079 struct sbuf *sb; 8080 int rc; 8081 struct tid_info *t = &sc->tids; 8082 8083 rc = sysctl_wire_old_buffer(req, 0); 8084 if (rc != 0) 8085 return (rc); 8086 8087 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8088 if (sb == NULL) 8089 return (ENOMEM); 8090 8091 if (t->natids) { 8092 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 8093 t->atids_in_use); 8094 } 8095 8096 if (t->ntids) { 8097 sbuf_printf(sb, "TID range: "); 8098 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8099 uint32_t b, hb; 8100 8101 if (chip_id(sc) <= CHELSIO_T5) { 8102 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 8103 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 8104 } else { 8105 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 8106 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 8107 } 8108 8109 if (b) 8110 sbuf_printf(sb, "0-%u, ", b - 1); 8111 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 8112 } else 8113 sbuf_printf(sb, "0-%u", t->ntids - 1); 8114 sbuf_printf(sb, ", in use: %u\n", 8115 atomic_load_acq_int(&t->tids_in_use)); 8116 } 8117 8118 if (t->nstids) { 8119 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 8120 t->stid_base + t->nstids - 1, t->stids_in_use); 8121 } 8122 8123 if (t->nftids) { 8124 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 8125 t->ftid_base + t->nftids - 1); 8126 } 8127 8128 if (t->netids) { 8129 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 8130 t->etid_base + t->netids - 1, t->etids_in_use); 8131 } 8132 8133 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 8134 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 8135 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 8136 8137 rc = sbuf_finish(sb); 8138 sbuf_delete(sb); 8139 8140 return (rc); 8141 } 8142 8143 static int 8144 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 8145 { 8146 struct adapter *sc = arg1; 8147 struct sbuf *sb; 8148 int rc; 8149 struct tp_err_stats stats; 8150 8151 rc = sysctl_wire_old_buffer(req, 0); 8152 if (rc != 0) 8153 return (rc); 8154 8155 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8156 if (sb == NULL) 8157 return (ENOMEM); 8158 8159 mtx_lock(&sc->reg_lock); 8160 t4_tp_get_err_stats(sc, &stats, 0); 8161 mtx_unlock(&sc->reg_lock); 8162 8163 if (sc->chip_params->nchan > 2) { 8164 sbuf_printf(sb, " channel 0 channel 1" 8165 " channel 2 channel 3\n"); 8166 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 8167 stats.mac_in_errs[0], stats.mac_in_errs[1], 8168 stats.mac_in_errs[2], stats.mac_in_errs[3]); 8169 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 8170 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 8171 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 8172 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 8173 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 8174 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 8175 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 8176 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 8177 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 8178 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 8179 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 8180 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 8181 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 8182 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 8183 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 8184 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 8185 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 8186 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 8187 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 8188 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 8189 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 8190 } else { 8191 sbuf_printf(sb, " channel 0 channel 1\n"); 8192 sbuf_printf(sb, "macInErrs: %10u %10u\n", 8193 stats.mac_in_errs[0], stats.mac_in_errs[1]); 8194 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 8195 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 8196 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 8197 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8198 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8199 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8200 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8201 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8202 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8203 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8204 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8205 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8206 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8207 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8208 } 8209 8210 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8211 stats.ofld_no_neigh, stats.ofld_cong_defer); 8212 8213 rc = sbuf_finish(sb); 8214 sbuf_delete(sb); 8215 8216 return (rc); 8217 } 8218 8219 static int 8220 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8221 { 8222 struct adapter *sc = arg1; 8223 struct tp_params *tpp = &sc->params.tp; 8224 u_int mask; 8225 int rc; 8226 8227 mask = tpp->la_mask >> 16; 8228 rc = sysctl_handle_int(oidp, &mask, 0, req); 8229 if (rc != 0 || req->newptr == NULL) 8230 return (rc); 8231 if (mask > 0xffff) 8232 return (EINVAL); 8233 tpp->la_mask = mask << 16; 8234 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8235 8236 return (0); 8237 } 8238 8239 struct field_desc { 8240 const char *name; 8241 u_int start; 8242 u_int width; 8243 }; 8244 8245 static void 8246 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8247 { 8248 char buf[32]; 8249 int line_size = 0; 8250 8251 while (f->name) { 8252 uint64_t mask = (1ULL << f->width) - 1; 8253 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8254 ((uintmax_t)v >> f->start) & mask); 8255 8256 if (line_size + len >= 79) { 8257 line_size = 8; 8258 sbuf_printf(sb, "\n "); 8259 } 8260 sbuf_printf(sb, "%s ", buf); 8261 line_size += len + 1; 8262 f++; 8263 } 8264 sbuf_printf(sb, "\n"); 8265 } 8266 8267 static const struct field_desc tp_la0[] = { 8268 { "RcfOpCodeOut", 60, 4 }, 8269 { "State", 56, 4 }, 8270 { "WcfState", 52, 4 }, 8271 { "RcfOpcSrcOut", 50, 2 }, 8272 { "CRxError", 49, 1 }, 8273 { "ERxError", 48, 1 }, 8274 { "SanityFailed", 47, 1 }, 8275 { "SpuriousMsg", 46, 1 }, 8276 { "FlushInputMsg", 45, 1 }, 8277 { "FlushInputCpl", 44, 1 }, 8278 { "RssUpBit", 43, 1 }, 8279 { "RssFilterHit", 42, 1 }, 8280 { "Tid", 32, 10 }, 8281 { "InitTcb", 31, 1 }, 8282 { "LineNumber", 24, 7 }, 8283 { "Emsg", 23, 1 }, 8284 { "EdataOut", 22, 1 }, 8285 { "Cmsg", 21, 1 }, 8286 { "CdataOut", 20, 1 }, 8287 { "EreadPdu", 19, 1 }, 8288 { "CreadPdu", 18, 1 }, 8289 { "TunnelPkt", 17, 1 }, 8290 { "RcfPeerFin", 16, 1 }, 8291 { "RcfReasonOut", 12, 4 }, 8292 { "TxCchannel", 10, 2 }, 8293 { "RcfTxChannel", 8, 2 }, 8294 { "RxEchannel", 6, 2 }, 8295 { "RcfRxChannel", 5, 1 }, 8296 { "RcfDataOutSrdy", 4, 1 }, 8297 { "RxDvld", 3, 1 }, 8298 { "RxOoDvld", 2, 1 }, 8299 { "RxCongestion", 1, 1 }, 8300 { "TxCongestion", 0, 1 }, 8301 { NULL } 8302 }; 8303 8304 static const struct field_desc tp_la1[] = { 8305 { "CplCmdIn", 56, 8 }, 8306 { "CplCmdOut", 48, 8 }, 8307 { "ESynOut", 47, 1 }, 8308 { "EAckOut", 46, 1 }, 8309 { "EFinOut", 45, 1 }, 8310 { "ERstOut", 44, 1 }, 8311 { "SynIn", 43, 1 }, 8312 { "AckIn", 42, 1 }, 8313 { "FinIn", 41, 1 }, 8314 { "RstIn", 40, 1 }, 8315 { "DataIn", 39, 1 }, 8316 { "DataInVld", 38, 1 }, 8317 { "PadIn", 37, 1 }, 8318 { "RxBufEmpty", 36, 1 }, 8319 { "RxDdp", 35, 1 }, 8320 { "RxFbCongestion", 34, 1 }, 8321 { "TxFbCongestion", 33, 1 }, 8322 { "TxPktSumSrdy", 32, 1 }, 8323 { "RcfUlpType", 28, 4 }, 8324 { "Eread", 27, 1 }, 8325 { "Ebypass", 26, 1 }, 8326 { "Esave", 25, 1 }, 8327 { "Static0", 24, 1 }, 8328 { "Cread", 23, 1 }, 8329 { "Cbypass", 22, 1 }, 8330 { "Csave", 21, 1 }, 8331 { "CPktOut", 20, 1 }, 8332 { "RxPagePoolFull", 18, 2 }, 8333 { "RxLpbkPkt", 17, 1 }, 8334 { "TxLpbkPkt", 16, 1 }, 8335 { "RxVfValid", 15, 1 }, 8336 { "SynLearned", 14, 1 }, 8337 { "SetDelEntry", 13, 1 }, 8338 { "SetInvEntry", 12, 1 }, 8339 { "CpcmdDvld", 11, 1 }, 8340 { "CpcmdSave", 10, 1 }, 8341 { "RxPstructsFull", 8, 2 }, 8342 { "EpcmdDvld", 7, 1 }, 8343 { "EpcmdFlush", 6, 1 }, 8344 { "EpcmdTrimPrefix", 5, 1 }, 8345 { "EpcmdTrimPostfix", 4, 1 }, 8346 { "ERssIp4Pkt", 3, 1 }, 8347 { "ERssIp6Pkt", 2, 1 }, 8348 { "ERssTcpUdpPkt", 1, 1 }, 8349 { "ERssFceFipPkt", 0, 1 }, 8350 { NULL } 8351 }; 8352 8353 static const struct field_desc tp_la2[] = { 8354 { "CplCmdIn", 56, 8 }, 8355 { "MpsVfVld", 55, 1 }, 8356 { "MpsPf", 52, 3 }, 8357 { "MpsVf", 44, 8 }, 8358 { "SynIn", 43, 1 }, 8359 { "AckIn", 42, 1 }, 8360 { "FinIn", 41, 1 }, 8361 { "RstIn", 40, 1 }, 8362 { "DataIn", 39, 1 }, 8363 { "DataInVld", 38, 1 }, 8364 { "PadIn", 37, 1 }, 8365 { "RxBufEmpty", 36, 1 }, 8366 { "RxDdp", 35, 1 }, 8367 { "RxFbCongestion", 34, 1 }, 8368 { "TxFbCongestion", 33, 1 }, 8369 { "TxPktSumSrdy", 32, 1 }, 8370 { "RcfUlpType", 28, 4 }, 8371 { "Eread", 27, 1 }, 8372 { "Ebypass", 26, 1 }, 8373 { "Esave", 25, 1 }, 8374 { "Static0", 24, 1 }, 8375 { "Cread", 23, 1 }, 8376 { "Cbypass", 22, 1 }, 8377 { "Csave", 21, 1 }, 8378 { "CPktOut", 20, 1 }, 8379 { "RxPagePoolFull", 18, 2 }, 8380 { "RxLpbkPkt", 17, 1 }, 8381 { "TxLpbkPkt", 16, 1 }, 8382 { "RxVfValid", 15, 1 }, 8383 { "SynLearned", 14, 1 }, 8384 { "SetDelEntry", 13, 1 }, 8385 { "SetInvEntry", 12, 1 }, 8386 { "CpcmdDvld", 11, 1 }, 8387 { "CpcmdSave", 10, 1 }, 8388 { "RxPstructsFull", 8, 2 }, 8389 { "EpcmdDvld", 7, 1 }, 8390 { "EpcmdFlush", 6, 1 }, 8391 { "EpcmdTrimPrefix", 5, 1 }, 8392 { "EpcmdTrimPostfix", 4, 1 }, 8393 { "ERssIp4Pkt", 3, 1 }, 8394 { "ERssIp6Pkt", 2, 1 }, 8395 { "ERssTcpUdpPkt", 1, 1 }, 8396 { "ERssFceFipPkt", 0, 1 }, 8397 { NULL } 8398 }; 8399 8400 static void 8401 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8402 { 8403 8404 field_desc_show(sb, *p, tp_la0); 8405 } 8406 8407 static void 8408 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8409 { 8410 8411 if (idx) 8412 sbuf_printf(sb, "\n"); 8413 field_desc_show(sb, p[0], tp_la0); 8414 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8415 field_desc_show(sb, p[1], tp_la0); 8416 } 8417 8418 static void 8419 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 8420 { 8421 8422 if (idx) 8423 sbuf_printf(sb, "\n"); 8424 field_desc_show(sb, p[0], tp_la0); 8425 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8426 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 8427 } 8428 8429 static int 8430 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 8431 { 8432 struct adapter *sc = arg1; 8433 struct sbuf *sb; 8434 uint64_t *buf, *p; 8435 int rc; 8436 u_int i, inc; 8437 void (*show_func)(struct sbuf *, uint64_t *, int); 8438 8439 rc = sysctl_wire_old_buffer(req, 0); 8440 if (rc != 0) 8441 return (rc); 8442 8443 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8444 if (sb == NULL) 8445 return (ENOMEM); 8446 8447 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 8448 8449 t4_tp_read_la(sc, buf, NULL); 8450 p = buf; 8451 8452 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 8453 case 2: 8454 inc = 2; 8455 show_func = tp_la_show2; 8456 break; 8457 case 3: 8458 inc = 2; 8459 show_func = tp_la_show3; 8460 break; 8461 default: 8462 inc = 1; 8463 show_func = tp_la_show; 8464 } 8465 8466 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 8467 (*show_func)(sb, p, i); 8468 8469 rc = sbuf_finish(sb); 8470 sbuf_delete(sb); 8471 free(buf, M_CXGBE); 8472 return (rc); 8473 } 8474 8475 static int 8476 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 8477 { 8478 struct adapter *sc = arg1; 8479 struct sbuf *sb; 8480 int rc; 8481 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 8482 8483 rc = sysctl_wire_old_buffer(req, 0); 8484 if (rc != 0) 8485 return (rc); 8486 8487 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8488 if (sb == NULL) 8489 return (ENOMEM); 8490 8491 t4_get_chan_txrate(sc, nrate, orate); 8492 8493 if (sc->chip_params->nchan > 2) { 8494 sbuf_printf(sb, " channel 0 channel 1" 8495 " channel 2 channel 3\n"); 8496 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 8497 nrate[0], nrate[1], nrate[2], nrate[3]); 8498 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 8499 orate[0], orate[1], orate[2], orate[3]); 8500 } else { 8501 sbuf_printf(sb, " channel 0 channel 1\n"); 8502 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 8503 nrate[0], nrate[1]); 8504 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 8505 orate[0], orate[1]); 8506 } 8507 8508 rc = sbuf_finish(sb); 8509 sbuf_delete(sb); 8510 8511 return (rc); 8512 } 8513 8514 static int 8515 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 8516 { 8517 struct adapter *sc = arg1; 8518 struct sbuf *sb; 8519 uint32_t *buf, *p; 8520 int rc, i; 8521 8522 rc = sysctl_wire_old_buffer(req, 0); 8523 if (rc != 0) 8524 return (rc); 8525 8526 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8527 if (sb == NULL) 8528 return (ENOMEM); 8529 8530 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 8531 M_ZERO | M_WAITOK); 8532 8533 t4_ulprx_read_la(sc, buf); 8534 p = buf; 8535 8536 sbuf_printf(sb, " Pcmd Type Message" 8537 " Data"); 8538 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 8539 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 8540 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 8541 } 8542 8543 rc = sbuf_finish(sb); 8544 sbuf_delete(sb); 8545 free(buf, M_CXGBE); 8546 return (rc); 8547 } 8548 8549 static int 8550 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 8551 { 8552 struct adapter *sc = arg1; 8553 struct sbuf *sb; 8554 int rc, v; 8555 8556 MPASS(chip_id(sc) >= CHELSIO_T5); 8557 8558 rc = sysctl_wire_old_buffer(req, 0); 8559 if (rc != 0) 8560 return (rc); 8561 8562 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8563 if (sb == NULL) 8564 return (ENOMEM); 8565 8566 v = t4_read_reg(sc, A_SGE_STAT_CFG); 8567 if (G_STATSOURCE_T5(v) == 7) { 8568 int mode; 8569 8570 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 8571 if (mode == 0) { 8572 sbuf_printf(sb, "total %d, incomplete %d", 8573 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8574 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8575 } else if (mode == 1) { 8576 sbuf_printf(sb, "total %d, data overflow %d", 8577 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8578 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8579 } else { 8580 sbuf_printf(sb, "unknown mode %d", mode); 8581 } 8582 } 8583 rc = sbuf_finish(sb); 8584 sbuf_delete(sb); 8585 8586 return (rc); 8587 } 8588 8589 static int 8590 sysctl_tc_params(SYSCTL_HANDLER_ARGS) 8591 { 8592 struct adapter *sc = arg1; 8593 struct tx_cl_rl_params tc; 8594 struct sbuf *sb; 8595 int i, rc, port_id, mbps, gbps; 8596 8597 rc = sysctl_wire_old_buffer(req, 0); 8598 if (rc != 0) 8599 return (rc); 8600 8601 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8602 if (sb == NULL) 8603 return (ENOMEM); 8604 8605 port_id = arg2 >> 16; 8606 MPASS(port_id < sc->params.nports); 8607 MPASS(sc->port[port_id] != NULL); 8608 i = arg2 & 0xffff; 8609 MPASS(i < sc->chip_params->nsched_cls); 8610 8611 mtx_lock(&sc->tc_lock); 8612 tc = sc->port[port_id]->sched_params->cl_rl[i]; 8613 mtx_unlock(&sc->tc_lock); 8614 8615 if (tc.flags & TX_CLRL_ERROR) { 8616 sbuf_printf(sb, "error"); 8617 goto done; 8618 } 8619 8620 if (tc.ratemode == SCHED_CLASS_RATEMODE_REL) { 8621 /* XXX: top speed or actual link speed? */ 8622 gbps = port_top_speed(sc->port[port_id]); 8623 sbuf_printf(sb, " %u%% of %uGbps", tc.maxrate, gbps); 8624 } else if (tc.ratemode == SCHED_CLASS_RATEMODE_ABS) { 8625 switch (tc.rateunit) { 8626 case SCHED_CLASS_RATEUNIT_BITS: 8627 mbps = tc.maxrate / 1000; 8628 gbps = tc.maxrate / 1000000; 8629 if (tc.maxrate == gbps * 1000000) 8630 sbuf_printf(sb, " %uGbps", gbps); 8631 else if (tc.maxrate == mbps * 1000) 8632 sbuf_printf(sb, " %uMbps", mbps); 8633 else 8634 sbuf_printf(sb, " %uKbps", tc.maxrate); 8635 break; 8636 case SCHED_CLASS_RATEUNIT_PKTS: 8637 sbuf_printf(sb, " %upps", tc.maxrate); 8638 break; 8639 default: 8640 rc = ENXIO; 8641 goto done; 8642 } 8643 } 8644 8645 switch (tc.mode) { 8646 case SCHED_CLASS_MODE_CLASS: 8647 sbuf_printf(sb, " aggregate"); 8648 break; 8649 case SCHED_CLASS_MODE_FLOW: 8650 sbuf_printf(sb, " per-flow"); 8651 break; 8652 default: 8653 rc = ENXIO; 8654 goto done; 8655 } 8656 8657 done: 8658 if (rc == 0) 8659 rc = sbuf_finish(sb); 8660 sbuf_delete(sb); 8661 8662 return (rc); 8663 } 8664 8665 static int 8666 sysctl_cpus(SYSCTL_HANDLER_ARGS) 8667 { 8668 struct adapter *sc = arg1; 8669 enum cpu_sets op = arg2; 8670 cpuset_t cpuset; 8671 struct sbuf *sb; 8672 int i, rc; 8673 8674 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 8675 8676 CPU_ZERO(&cpuset); 8677 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 8678 if (rc != 0) 8679 return (rc); 8680 8681 rc = sysctl_wire_old_buffer(req, 0); 8682 if (rc != 0) 8683 return (rc); 8684 8685 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8686 if (sb == NULL) 8687 return (ENOMEM); 8688 8689 CPU_FOREACH(i) 8690 sbuf_printf(sb, "%d ", i); 8691 rc = sbuf_finish(sb); 8692 sbuf_delete(sb); 8693 8694 return (rc); 8695 } 8696 8697 #ifdef TCP_OFFLOAD 8698 static int 8699 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 8700 { 8701 struct adapter *sc = arg1; 8702 int *old_ports, *new_ports; 8703 int i, new_count, rc; 8704 8705 if (req->newptr == NULL && req->oldptr == NULL) 8706 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 8707 sizeof(sc->tt.tls_rx_ports[0]))); 8708 8709 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 8710 if (rc) 8711 return (rc); 8712 8713 if (sc->tt.num_tls_rx_ports == 0) { 8714 i = -1; 8715 rc = SYSCTL_OUT(req, &i, sizeof(i)); 8716 } else 8717 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 8718 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 8719 if (rc == 0 && req->newptr != NULL) { 8720 new_count = req->newlen / sizeof(new_ports[0]); 8721 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 8722 M_WAITOK); 8723 rc = SYSCTL_IN(req, new_ports, new_count * 8724 sizeof(new_ports[0])); 8725 if (rc) 8726 goto err; 8727 8728 /* Allow setting to a single '-1' to clear the list. */ 8729 if (new_count == 1 && new_ports[0] == -1) { 8730 ADAPTER_LOCK(sc); 8731 old_ports = sc->tt.tls_rx_ports; 8732 sc->tt.tls_rx_ports = NULL; 8733 sc->tt.num_tls_rx_ports = 0; 8734 ADAPTER_UNLOCK(sc); 8735 free(old_ports, M_CXGBE); 8736 } else { 8737 for (i = 0; i < new_count; i++) { 8738 if (new_ports[i] < 1 || 8739 new_ports[i] > IPPORT_MAX) { 8740 rc = EINVAL; 8741 goto err; 8742 } 8743 } 8744 8745 ADAPTER_LOCK(sc); 8746 old_ports = sc->tt.tls_rx_ports; 8747 sc->tt.tls_rx_ports = new_ports; 8748 sc->tt.num_tls_rx_ports = new_count; 8749 ADAPTER_UNLOCK(sc); 8750 free(old_ports, M_CXGBE); 8751 new_ports = NULL; 8752 } 8753 err: 8754 free(new_ports, M_CXGBE); 8755 } 8756 end_synchronized_op(sc, 0); 8757 return (rc); 8758 } 8759 8760 static void 8761 unit_conv(char *buf, size_t len, u_int val, u_int factor) 8762 { 8763 u_int rem = val % factor; 8764 8765 if (rem == 0) 8766 snprintf(buf, len, "%u", val / factor); 8767 else { 8768 while (rem % 10 == 0) 8769 rem /= 10; 8770 snprintf(buf, len, "%u.%u", val / factor, rem); 8771 } 8772 } 8773 8774 static int 8775 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 8776 { 8777 struct adapter *sc = arg1; 8778 char buf[16]; 8779 u_int res, re; 8780 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8781 8782 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8783 switch (arg2) { 8784 case 0: 8785 /* timer_tick */ 8786 re = G_TIMERRESOLUTION(res); 8787 break; 8788 case 1: 8789 /* TCP timestamp tick */ 8790 re = G_TIMESTAMPRESOLUTION(res); 8791 break; 8792 case 2: 8793 /* DACK tick */ 8794 re = G_DELAYEDACKRESOLUTION(res); 8795 break; 8796 default: 8797 return (EDOOFUS); 8798 } 8799 8800 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 8801 8802 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 8803 } 8804 8805 static int 8806 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 8807 { 8808 struct adapter *sc = arg1; 8809 u_int res, dack_re, v; 8810 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8811 8812 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8813 dack_re = G_DELAYEDACKRESOLUTION(res); 8814 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 8815 8816 return (sysctl_handle_int(oidp, &v, 0, req)); 8817 } 8818 8819 static int 8820 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 8821 { 8822 struct adapter *sc = arg1; 8823 int reg = arg2; 8824 u_int tre; 8825 u_long tp_tick_us, v; 8826 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8827 8828 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 8829 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 8830 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 8831 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 8832 8833 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 8834 tp_tick_us = (cclk_ps << tre) / 1000000; 8835 8836 if (reg == A_TP_INIT_SRTT) 8837 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 8838 else 8839 v = tp_tick_us * t4_read_reg(sc, reg); 8840 8841 return (sysctl_handle_long(oidp, &v, 0, req)); 8842 } 8843 8844 /* 8845 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 8846 * passed to this function. 8847 */ 8848 static int 8849 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 8850 { 8851 struct adapter *sc = arg1; 8852 int idx = arg2; 8853 u_int v; 8854 8855 MPASS(idx >= 0 && idx <= 24); 8856 8857 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 8858 8859 return (sysctl_handle_int(oidp, &v, 0, req)); 8860 } 8861 8862 static int 8863 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 8864 { 8865 struct adapter *sc = arg1; 8866 int idx = arg2; 8867 u_int shift, v, r; 8868 8869 MPASS(idx >= 0 && idx < 16); 8870 8871 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 8872 shift = (idx & 3) << 3; 8873 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 8874 8875 return (sysctl_handle_int(oidp, &v, 0, req)); 8876 } 8877 8878 static int 8879 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 8880 { 8881 struct vi_info *vi = arg1; 8882 struct adapter *sc = vi->pi->adapter; 8883 int idx, rc, i; 8884 struct sge_ofld_rxq *ofld_rxq; 8885 uint8_t v; 8886 8887 idx = vi->ofld_tmr_idx; 8888 8889 rc = sysctl_handle_int(oidp, &idx, 0, req); 8890 if (rc != 0 || req->newptr == NULL) 8891 return (rc); 8892 8893 if (idx < 0 || idx >= SGE_NTIMERS) 8894 return (EINVAL); 8895 8896 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8897 "t4otmr"); 8898 if (rc) 8899 return (rc); 8900 8901 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 8902 for_each_ofld_rxq(vi, i, ofld_rxq) { 8903 #ifdef atomic_store_rel_8 8904 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 8905 #else 8906 ofld_rxq->iq.intr_params = v; 8907 #endif 8908 } 8909 vi->ofld_tmr_idx = idx; 8910 8911 end_synchronized_op(sc, LOCK_HELD); 8912 return (0); 8913 } 8914 8915 static int 8916 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 8917 { 8918 struct vi_info *vi = arg1; 8919 struct adapter *sc = vi->pi->adapter; 8920 int idx, rc; 8921 8922 idx = vi->ofld_pktc_idx; 8923 8924 rc = sysctl_handle_int(oidp, &idx, 0, req); 8925 if (rc != 0 || req->newptr == NULL) 8926 return (rc); 8927 8928 if (idx < -1 || idx >= SGE_NCOUNTERS) 8929 return (EINVAL); 8930 8931 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8932 "t4opktc"); 8933 if (rc) 8934 return (rc); 8935 8936 if (vi->flags & VI_INIT_DONE) 8937 rc = EBUSY; /* cannot be changed once the queues are created */ 8938 else 8939 vi->ofld_pktc_idx = idx; 8940 8941 end_synchronized_op(sc, LOCK_HELD); 8942 return (rc); 8943 } 8944 #endif 8945 8946 static int 8947 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 8948 { 8949 int rc; 8950 8951 if (cntxt->cid > M_CTXTQID) 8952 return (EINVAL); 8953 8954 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 8955 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 8956 return (EINVAL); 8957 8958 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 8959 if (rc) 8960 return (rc); 8961 8962 if (sc->flags & FW_OK) { 8963 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 8964 &cntxt->data[0]); 8965 if (rc == 0) 8966 goto done; 8967 } 8968 8969 /* 8970 * Read via firmware failed or wasn't even attempted. Read directly via 8971 * the backdoor. 8972 */ 8973 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 8974 done: 8975 end_synchronized_op(sc, 0); 8976 return (rc); 8977 } 8978 8979 static int 8980 load_fw(struct adapter *sc, struct t4_data *fw) 8981 { 8982 int rc; 8983 uint8_t *fw_data; 8984 8985 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 8986 if (rc) 8987 return (rc); 8988 8989 /* 8990 * The firmware, with the sole exception of the memory parity error 8991 * handler, runs from memory and not flash. It is almost always safe to 8992 * install a new firmware on a running system. Just set bit 1 in 8993 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 8994 */ 8995 if (sc->flags & FULL_INIT_DONE && 8996 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 8997 rc = EBUSY; 8998 goto done; 8999 } 9000 9001 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9002 if (fw_data == NULL) { 9003 rc = ENOMEM; 9004 goto done; 9005 } 9006 9007 rc = copyin(fw->data, fw_data, fw->len); 9008 if (rc == 0) 9009 rc = -t4_load_fw(sc, fw_data, fw->len); 9010 9011 free(fw_data, M_CXGBE); 9012 done: 9013 end_synchronized_op(sc, 0); 9014 return (rc); 9015 } 9016 9017 static int 9018 load_cfg(struct adapter *sc, struct t4_data *cfg) 9019 { 9020 int rc; 9021 uint8_t *cfg_data = NULL; 9022 9023 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9024 if (rc) 9025 return (rc); 9026 9027 if (cfg->len == 0) { 9028 /* clear */ 9029 rc = -t4_load_cfg(sc, NULL, 0); 9030 goto done; 9031 } 9032 9033 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9034 if (cfg_data == NULL) { 9035 rc = ENOMEM; 9036 goto done; 9037 } 9038 9039 rc = copyin(cfg->data, cfg_data, cfg->len); 9040 if (rc == 0) 9041 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9042 9043 free(cfg_data, M_CXGBE); 9044 done: 9045 end_synchronized_op(sc, 0); 9046 return (rc); 9047 } 9048 9049 static int 9050 load_boot(struct adapter *sc, struct t4_bootrom *br) 9051 { 9052 int rc; 9053 uint8_t *br_data = NULL; 9054 u_int offset; 9055 9056 if (br->len > 1024 * 1024) 9057 return (EFBIG); 9058 9059 if (br->pf_offset == 0) { 9060 /* pfidx */ 9061 if (br->pfidx_addr > 7) 9062 return (EINVAL); 9063 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9064 A_PCIE_PF_EXPROM_OFST))); 9065 } else if (br->pf_offset == 1) { 9066 /* offset */ 9067 offset = G_OFFSET(br->pfidx_addr); 9068 } else { 9069 return (EINVAL); 9070 } 9071 9072 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9073 if (rc) 9074 return (rc); 9075 9076 if (br->len == 0) { 9077 /* clear */ 9078 rc = -t4_load_boot(sc, NULL, offset, 0); 9079 goto done; 9080 } 9081 9082 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9083 if (br_data == NULL) { 9084 rc = ENOMEM; 9085 goto done; 9086 } 9087 9088 rc = copyin(br->data, br_data, br->len); 9089 if (rc == 0) 9090 rc = -t4_load_boot(sc, br_data, offset, br->len); 9091 9092 free(br_data, M_CXGBE); 9093 done: 9094 end_synchronized_op(sc, 0); 9095 return (rc); 9096 } 9097 9098 static int 9099 load_bootcfg(struct adapter *sc, struct t4_data *bc) 9100 { 9101 int rc; 9102 uint8_t *bc_data = NULL; 9103 9104 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9105 if (rc) 9106 return (rc); 9107 9108 if (bc->len == 0) { 9109 /* clear */ 9110 rc = -t4_load_bootcfg(sc, NULL, 0); 9111 goto done; 9112 } 9113 9114 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9115 if (bc_data == NULL) { 9116 rc = ENOMEM; 9117 goto done; 9118 } 9119 9120 rc = copyin(bc->data, bc_data, bc->len); 9121 if (rc == 0) 9122 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9123 9124 free(bc_data, M_CXGBE); 9125 done: 9126 end_synchronized_op(sc, 0); 9127 return (rc); 9128 } 9129 9130 static int 9131 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9132 { 9133 int rc; 9134 struct cudbg_init *cudbg; 9135 void *handle, *buf; 9136 9137 /* buf is large, don't block if no memory is available */ 9138 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9139 if (buf == NULL) 9140 return (ENOMEM); 9141 9142 handle = cudbg_alloc_handle(); 9143 if (handle == NULL) { 9144 rc = ENOMEM; 9145 goto done; 9146 } 9147 9148 cudbg = cudbg_get_init(handle); 9149 cudbg->adap = sc; 9150 cudbg->print = (cudbg_print_cb)printf; 9151 9152 #ifndef notyet 9153 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9154 __func__, dump->wr_flash, dump->len, dump->data); 9155 #endif 9156 9157 if (dump->wr_flash) 9158 cudbg->use_flash = 1; 9159 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9160 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9161 9162 rc = cudbg_collect(handle, buf, &dump->len); 9163 if (rc != 0) 9164 goto done; 9165 9166 rc = copyout(buf, dump->data, dump->len); 9167 done: 9168 cudbg_free_handle(handle); 9169 free(buf, M_CXGBE); 9170 return (rc); 9171 } 9172 9173 static void 9174 free_offload_policy(struct t4_offload_policy *op) 9175 { 9176 struct offload_rule *r; 9177 int i; 9178 9179 if (op == NULL) 9180 return; 9181 9182 r = &op->rule[0]; 9183 for (i = 0; i < op->nrules; i++, r++) { 9184 free(r->bpf_prog.bf_insns, M_CXGBE); 9185 } 9186 free(op->rule, M_CXGBE); 9187 free(op, M_CXGBE); 9188 } 9189 9190 static int 9191 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 9192 { 9193 int i, rc, len; 9194 struct t4_offload_policy *op, *old; 9195 struct bpf_program *bf; 9196 const struct offload_settings *s; 9197 struct offload_rule *r; 9198 void *u; 9199 9200 if (!is_offload(sc)) 9201 return (ENODEV); 9202 9203 if (uop->nrules == 0) { 9204 /* Delete installed policies. */ 9205 op = NULL; 9206 goto set_policy; 9207 } if (uop->nrules > 256) { /* arbitrary */ 9208 return (E2BIG); 9209 } 9210 9211 /* Copy userspace offload policy to kernel */ 9212 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 9213 op->nrules = uop->nrules; 9214 len = op->nrules * sizeof(struct offload_rule); 9215 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9216 rc = copyin(uop->rule, op->rule, len); 9217 if (rc) { 9218 free(op->rule, M_CXGBE); 9219 free(op, M_CXGBE); 9220 return (rc); 9221 } 9222 9223 r = &op->rule[0]; 9224 for (i = 0; i < op->nrules; i++, r++) { 9225 9226 /* Validate open_type */ 9227 if (r->open_type != OPEN_TYPE_LISTEN && 9228 r->open_type != OPEN_TYPE_ACTIVE && 9229 r->open_type != OPEN_TYPE_PASSIVE && 9230 r->open_type != OPEN_TYPE_DONTCARE) { 9231 error: 9232 /* 9233 * Rules 0 to i have malloc'd filters that need to be 9234 * freed. Rules i+1 to nrules have userspace pointers 9235 * and should be left alone. 9236 */ 9237 op->nrules = i; 9238 free_offload_policy(op); 9239 return (rc); 9240 } 9241 9242 /* Validate settings */ 9243 s = &r->settings; 9244 if ((s->offload != 0 && s->offload != 1) || 9245 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9246 s->sched_class < -1 || 9247 s->sched_class >= sc->chip_params->nsched_cls) { 9248 rc = EINVAL; 9249 goto error; 9250 } 9251 9252 bf = &r->bpf_prog; 9253 u = bf->bf_insns; /* userspace ptr */ 9254 bf->bf_insns = NULL; 9255 if (bf->bf_len == 0) { 9256 /* legal, matches everything */ 9257 continue; 9258 } 9259 len = bf->bf_len * sizeof(*bf->bf_insns); 9260 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9261 rc = copyin(u, bf->bf_insns, len); 9262 if (rc != 0) 9263 goto error; 9264 9265 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9266 rc = EINVAL; 9267 goto error; 9268 } 9269 } 9270 set_policy: 9271 rw_wlock(&sc->policy_lock); 9272 old = sc->policy; 9273 sc->policy = op; 9274 rw_wunlock(&sc->policy_lock); 9275 free_offload_policy(old); 9276 9277 return (0); 9278 } 9279 9280 #define MAX_READ_BUF_SIZE (128 * 1024) 9281 static int 9282 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9283 { 9284 uint32_t addr, remaining, n; 9285 uint32_t *buf; 9286 int rc; 9287 uint8_t *dst; 9288 9289 rc = validate_mem_range(sc, mr->addr, mr->len); 9290 if (rc != 0) 9291 return (rc); 9292 9293 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9294 addr = mr->addr; 9295 remaining = mr->len; 9296 dst = (void *)mr->data; 9297 9298 while (remaining) { 9299 n = min(remaining, MAX_READ_BUF_SIZE); 9300 read_via_memwin(sc, 2, addr, buf, n); 9301 9302 rc = copyout(buf, dst, n); 9303 if (rc != 0) 9304 break; 9305 9306 dst += n; 9307 remaining -= n; 9308 addr += n; 9309 } 9310 9311 free(buf, M_CXGBE); 9312 return (rc); 9313 } 9314 #undef MAX_READ_BUF_SIZE 9315 9316 static int 9317 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9318 { 9319 int rc; 9320 9321 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9322 return (EINVAL); 9323 9324 if (i2cd->len > sizeof(i2cd->data)) 9325 return (EFBIG); 9326 9327 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9328 if (rc) 9329 return (rc); 9330 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9331 i2cd->offset, i2cd->len, &i2cd->data[0]); 9332 end_synchronized_op(sc, 0); 9333 9334 return (rc); 9335 } 9336 9337 int 9338 t4_os_find_pci_capability(struct adapter *sc, int cap) 9339 { 9340 int i; 9341 9342 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9343 } 9344 9345 int 9346 t4_os_pci_save_state(struct adapter *sc) 9347 { 9348 device_t dev; 9349 struct pci_devinfo *dinfo; 9350 9351 dev = sc->dev; 9352 dinfo = device_get_ivars(dev); 9353 9354 pci_cfg_save(dev, dinfo, 0); 9355 return (0); 9356 } 9357 9358 int 9359 t4_os_pci_restore_state(struct adapter *sc) 9360 { 9361 device_t dev; 9362 struct pci_devinfo *dinfo; 9363 9364 dev = sc->dev; 9365 dinfo = device_get_ivars(dev); 9366 9367 pci_cfg_restore(dev, dinfo); 9368 return (0); 9369 } 9370 9371 void 9372 t4_os_portmod_changed(struct port_info *pi) 9373 { 9374 struct adapter *sc = pi->adapter; 9375 struct vi_info *vi; 9376 struct ifnet *ifp; 9377 static const char *mod_str[] = { 9378 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9379 }; 9380 9381 MPASS((pi->flags & FIXED_IFMEDIA) == 0); 9382 9383 vi = &pi->vi[0]; 9384 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9385 PORT_LOCK(pi); 9386 build_medialist(pi, &pi->media); 9387 apply_l1cfg(pi); 9388 PORT_UNLOCK(pi); 9389 end_synchronized_op(sc, LOCK_HELD); 9390 } 9391 9392 ifp = vi->ifp; 9393 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9394 if_printf(ifp, "transceiver unplugged.\n"); 9395 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9396 if_printf(ifp, "unknown transceiver inserted.\n"); 9397 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9398 if_printf(ifp, "unsupported transceiver inserted.\n"); 9399 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9400 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9401 port_top_speed(pi), mod_str[pi->mod_type]); 9402 } else { 9403 if_printf(ifp, "transceiver (type %d) inserted.\n", 9404 pi->mod_type); 9405 } 9406 } 9407 9408 void 9409 t4_os_link_changed(struct port_info *pi) 9410 { 9411 struct vi_info *vi; 9412 struct ifnet *ifp; 9413 struct link_config *lc; 9414 int v; 9415 9416 PORT_LOCK_ASSERT_OWNED(pi); 9417 9418 for_each_vi(pi, v, vi) { 9419 ifp = vi->ifp; 9420 if (ifp == NULL) 9421 continue; 9422 9423 lc = &pi->link_cfg; 9424 if (lc->link_ok) { 9425 ifp->if_baudrate = IF_Mbps(lc->speed); 9426 if_link_state_change(ifp, LINK_STATE_UP); 9427 } else { 9428 if_link_state_change(ifp, LINK_STATE_DOWN); 9429 } 9430 } 9431 } 9432 9433 void 9434 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9435 { 9436 struct adapter *sc; 9437 9438 sx_slock(&t4_list_lock); 9439 SLIST_FOREACH(sc, &t4_list, link) { 9440 /* 9441 * func should not make any assumptions about what state sc is 9442 * in - the only guarantee is that sc->sc_lock is a valid lock. 9443 */ 9444 func(sc, arg); 9445 } 9446 sx_sunlock(&t4_list_lock); 9447 } 9448 9449 static int 9450 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9451 struct thread *td) 9452 { 9453 int rc; 9454 struct adapter *sc = dev->si_drv1; 9455 9456 rc = priv_check(td, PRIV_DRIVER); 9457 if (rc != 0) 9458 return (rc); 9459 9460 switch (cmd) { 9461 case CHELSIO_T4_GETREG: { 9462 struct t4_reg *edata = (struct t4_reg *)data; 9463 9464 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9465 return (EFAULT); 9466 9467 if (edata->size == 4) 9468 edata->val = t4_read_reg(sc, edata->addr); 9469 else if (edata->size == 8) 9470 edata->val = t4_read_reg64(sc, edata->addr); 9471 else 9472 return (EINVAL); 9473 9474 break; 9475 } 9476 case CHELSIO_T4_SETREG: { 9477 struct t4_reg *edata = (struct t4_reg *)data; 9478 9479 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9480 return (EFAULT); 9481 9482 if (edata->size == 4) { 9483 if (edata->val & 0xffffffff00000000) 9484 return (EINVAL); 9485 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9486 } else if (edata->size == 8) 9487 t4_write_reg64(sc, edata->addr, edata->val); 9488 else 9489 return (EINVAL); 9490 break; 9491 } 9492 case CHELSIO_T4_REGDUMP: { 9493 struct t4_regdump *regs = (struct t4_regdump *)data; 9494 int reglen = t4_get_regs_len(sc); 9495 uint8_t *buf; 9496 9497 if (regs->len < reglen) { 9498 regs->len = reglen; /* hint to the caller */ 9499 return (ENOBUFS); 9500 } 9501 9502 regs->len = reglen; 9503 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9504 get_regs(sc, regs, buf); 9505 rc = copyout(buf, regs->data, reglen); 9506 free(buf, M_CXGBE); 9507 break; 9508 } 9509 case CHELSIO_T4_GET_FILTER_MODE: 9510 rc = get_filter_mode(sc, (uint32_t *)data); 9511 break; 9512 case CHELSIO_T4_SET_FILTER_MODE: 9513 rc = set_filter_mode(sc, *(uint32_t *)data); 9514 break; 9515 case CHELSIO_T4_GET_FILTER: 9516 rc = get_filter(sc, (struct t4_filter *)data); 9517 break; 9518 case CHELSIO_T4_SET_FILTER: 9519 rc = set_filter(sc, (struct t4_filter *)data); 9520 break; 9521 case CHELSIO_T4_DEL_FILTER: 9522 rc = del_filter(sc, (struct t4_filter *)data); 9523 break; 9524 case CHELSIO_T4_GET_SGE_CONTEXT: 9525 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9526 break; 9527 case CHELSIO_T4_LOAD_FW: 9528 rc = load_fw(sc, (struct t4_data *)data); 9529 break; 9530 case CHELSIO_T4_GET_MEM: 9531 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9532 break; 9533 case CHELSIO_T4_GET_I2C: 9534 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9535 break; 9536 case CHELSIO_T4_CLEAR_STATS: { 9537 int i, v, bg_map; 9538 u_int port_id = *(uint32_t *)data; 9539 struct port_info *pi; 9540 struct vi_info *vi; 9541 9542 if (port_id >= sc->params.nports) 9543 return (EINVAL); 9544 pi = sc->port[port_id]; 9545 if (pi == NULL) 9546 return (EIO); 9547 9548 /* MAC stats */ 9549 t4_clr_port_stats(sc, pi->tx_chan); 9550 pi->tx_parse_error = 0; 9551 pi->tnl_cong_drops = 0; 9552 mtx_lock(&sc->reg_lock); 9553 for_each_vi(pi, v, vi) { 9554 if (vi->flags & VI_INIT_DONE) 9555 t4_clr_vi_stats(sc, vi->viid); 9556 } 9557 bg_map = pi->mps_bg_map; 9558 v = 0; /* reuse */ 9559 while (bg_map) { 9560 i = ffs(bg_map) - 1; 9561 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 9562 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 9563 bg_map &= ~(1 << i); 9564 } 9565 mtx_unlock(&sc->reg_lock); 9566 9567 /* 9568 * Since this command accepts a port, clear stats for 9569 * all VIs on this port. 9570 */ 9571 for_each_vi(pi, v, vi) { 9572 if (vi->flags & VI_INIT_DONE) { 9573 struct sge_rxq *rxq; 9574 struct sge_txq *txq; 9575 struct sge_wrq *wrq; 9576 9577 for_each_rxq(vi, i, rxq) { 9578 #if defined(INET) || defined(INET6) 9579 rxq->lro.lro_queued = 0; 9580 rxq->lro.lro_flushed = 0; 9581 #endif 9582 rxq->rxcsum = 0; 9583 rxq->vlan_extraction = 0; 9584 } 9585 9586 for_each_txq(vi, i, txq) { 9587 txq->txcsum = 0; 9588 txq->tso_wrs = 0; 9589 txq->vlan_insertion = 0; 9590 txq->imm_wrs = 0; 9591 txq->sgl_wrs = 0; 9592 txq->txpkt_wrs = 0; 9593 txq->txpkts0_wrs = 0; 9594 txq->txpkts1_wrs = 0; 9595 txq->txpkts0_pkts = 0; 9596 txq->txpkts1_pkts = 0; 9597 mp_ring_reset_stats(txq->r); 9598 } 9599 9600 #ifdef TCP_OFFLOAD 9601 /* nothing to clear for each ofld_rxq */ 9602 9603 for_each_ofld_txq(vi, i, wrq) { 9604 wrq->tx_wrs_direct = 0; 9605 wrq->tx_wrs_copied = 0; 9606 } 9607 #endif 9608 9609 if (IS_MAIN_VI(vi)) { 9610 wrq = &sc->sge.ctrlq[pi->port_id]; 9611 wrq->tx_wrs_direct = 0; 9612 wrq->tx_wrs_copied = 0; 9613 } 9614 } 9615 } 9616 break; 9617 } 9618 case CHELSIO_T4_SCHED_CLASS: 9619 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9620 break; 9621 case CHELSIO_T4_SCHED_QUEUE: 9622 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9623 break; 9624 case CHELSIO_T4_GET_TRACER: 9625 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9626 break; 9627 case CHELSIO_T4_SET_TRACER: 9628 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9629 break; 9630 case CHELSIO_T4_LOAD_CFG: 9631 rc = load_cfg(sc, (struct t4_data *)data); 9632 break; 9633 case CHELSIO_T4_LOAD_BOOT: 9634 rc = load_boot(sc, (struct t4_bootrom *)data); 9635 break; 9636 case CHELSIO_T4_LOAD_BOOTCFG: 9637 rc = load_bootcfg(sc, (struct t4_data *)data); 9638 break; 9639 case CHELSIO_T4_CUDBG_DUMP: 9640 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 9641 break; 9642 case CHELSIO_T4_SET_OFLD_POLICY: 9643 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 9644 break; 9645 default: 9646 rc = ENOTTY; 9647 } 9648 9649 return (rc); 9650 } 9651 9652 void 9653 t4_db_full(struct adapter *sc) 9654 { 9655 9656 CXGBE_UNIMPLEMENTED(__func__); 9657 } 9658 9659 void 9660 t4_db_dropped(struct adapter *sc) 9661 { 9662 9663 CXGBE_UNIMPLEMENTED(__func__); 9664 } 9665 9666 #ifdef TCP_OFFLOAD 9667 static int 9668 toe_capability(struct vi_info *vi, int enable) 9669 { 9670 int rc; 9671 struct port_info *pi = vi->pi; 9672 struct adapter *sc = pi->adapter; 9673 9674 ASSERT_SYNCHRONIZED_OP(sc); 9675 9676 if (!is_offload(sc)) 9677 return (ENODEV); 9678 9679 if (enable) { 9680 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9681 /* TOE is already enabled. */ 9682 return (0); 9683 } 9684 9685 /* 9686 * We need the port's queues around so that we're able to send 9687 * and receive CPLs to/from the TOE even if the ifnet for this 9688 * port has never been UP'd administratively. 9689 */ 9690 if (!(vi->flags & VI_INIT_DONE)) { 9691 rc = vi_full_init(vi); 9692 if (rc) 9693 return (rc); 9694 } 9695 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9696 rc = vi_full_init(&pi->vi[0]); 9697 if (rc) 9698 return (rc); 9699 } 9700 9701 if (isset(&sc->offload_map, pi->port_id)) { 9702 /* TOE is enabled on another VI of this port. */ 9703 pi->uld_vis++; 9704 return (0); 9705 } 9706 9707 if (!uld_active(sc, ULD_TOM)) { 9708 rc = t4_activate_uld(sc, ULD_TOM); 9709 if (rc == EAGAIN) { 9710 log(LOG_WARNING, 9711 "You must kldload t4_tom.ko before trying " 9712 "to enable TOE on a cxgbe interface.\n"); 9713 } 9714 if (rc != 0) 9715 return (rc); 9716 KASSERT(sc->tom_softc != NULL, 9717 ("%s: TOM activated but softc NULL", __func__)); 9718 KASSERT(uld_active(sc, ULD_TOM), 9719 ("%s: TOM activated but flag not set", __func__)); 9720 } 9721 9722 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9723 if (!uld_active(sc, ULD_IWARP)) 9724 (void) t4_activate_uld(sc, ULD_IWARP); 9725 if (!uld_active(sc, ULD_ISCSI)) 9726 (void) t4_activate_uld(sc, ULD_ISCSI); 9727 9728 pi->uld_vis++; 9729 setbit(&sc->offload_map, pi->port_id); 9730 } else { 9731 pi->uld_vis--; 9732 9733 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9734 return (0); 9735 9736 KASSERT(uld_active(sc, ULD_TOM), 9737 ("%s: TOM never initialized?", __func__)); 9738 clrbit(&sc->offload_map, pi->port_id); 9739 } 9740 9741 return (0); 9742 } 9743 9744 /* 9745 * Add an upper layer driver to the global list. 9746 */ 9747 int 9748 t4_register_uld(struct uld_info *ui) 9749 { 9750 int rc = 0; 9751 struct uld_info *u; 9752 9753 sx_xlock(&t4_uld_list_lock); 9754 SLIST_FOREACH(u, &t4_uld_list, link) { 9755 if (u->uld_id == ui->uld_id) { 9756 rc = EEXIST; 9757 goto done; 9758 } 9759 } 9760 9761 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9762 ui->refcount = 0; 9763 done: 9764 sx_xunlock(&t4_uld_list_lock); 9765 return (rc); 9766 } 9767 9768 int 9769 t4_unregister_uld(struct uld_info *ui) 9770 { 9771 int rc = EINVAL; 9772 struct uld_info *u; 9773 9774 sx_xlock(&t4_uld_list_lock); 9775 9776 SLIST_FOREACH(u, &t4_uld_list, link) { 9777 if (u == ui) { 9778 if (ui->refcount > 0) { 9779 rc = EBUSY; 9780 goto done; 9781 } 9782 9783 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 9784 rc = 0; 9785 goto done; 9786 } 9787 } 9788 done: 9789 sx_xunlock(&t4_uld_list_lock); 9790 return (rc); 9791 } 9792 9793 int 9794 t4_activate_uld(struct adapter *sc, int id) 9795 { 9796 int rc; 9797 struct uld_info *ui; 9798 9799 ASSERT_SYNCHRONIZED_OP(sc); 9800 9801 if (id < 0 || id > ULD_MAX) 9802 return (EINVAL); 9803 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 9804 9805 sx_slock(&t4_uld_list_lock); 9806 9807 SLIST_FOREACH(ui, &t4_uld_list, link) { 9808 if (ui->uld_id == id) { 9809 if (!(sc->flags & FULL_INIT_DONE)) { 9810 rc = adapter_full_init(sc); 9811 if (rc != 0) 9812 break; 9813 } 9814 9815 rc = ui->activate(sc); 9816 if (rc == 0) { 9817 setbit(&sc->active_ulds, id); 9818 ui->refcount++; 9819 } 9820 break; 9821 } 9822 } 9823 9824 sx_sunlock(&t4_uld_list_lock); 9825 9826 return (rc); 9827 } 9828 9829 int 9830 t4_deactivate_uld(struct adapter *sc, int id) 9831 { 9832 int rc; 9833 struct uld_info *ui; 9834 9835 ASSERT_SYNCHRONIZED_OP(sc); 9836 9837 if (id < 0 || id > ULD_MAX) 9838 return (EINVAL); 9839 rc = ENXIO; 9840 9841 sx_slock(&t4_uld_list_lock); 9842 9843 SLIST_FOREACH(ui, &t4_uld_list, link) { 9844 if (ui->uld_id == id) { 9845 rc = ui->deactivate(sc); 9846 if (rc == 0) { 9847 clrbit(&sc->active_ulds, id); 9848 ui->refcount--; 9849 } 9850 break; 9851 } 9852 } 9853 9854 sx_sunlock(&t4_uld_list_lock); 9855 9856 return (rc); 9857 } 9858 9859 int 9860 uld_active(struct adapter *sc, int uld_id) 9861 { 9862 9863 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 9864 9865 return (isset(&sc->active_ulds, uld_id)); 9866 } 9867 #endif 9868 9869 /* 9870 * t = ptr to tunable. 9871 * nc = number of CPUs. 9872 * c = compiled in default for that tunable. 9873 */ 9874 static void 9875 calculate_nqueues(int *t, int nc, const int c) 9876 { 9877 int nq; 9878 9879 if (*t > 0) 9880 return; 9881 nq = *t < 0 ? -*t : c; 9882 *t = min(nc, nq); 9883 } 9884 9885 /* 9886 * Come up with reasonable defaults for some of the tunables, provided they're 9887 * not set by the user (in which case we'll use the values as is). 9888 */ 9889 static void 9890 tweak_tunables(void) 9891 { 9892 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 9893 9894 if (t4_ntxq < 1) { 9895 #ifdef RSS 9896 t4_ntxq = rss_getnumbuckets(); 9897 #else 9898 calculate_nqueues(&t4_ntxq, nc, NTXQ); 9899 #endif 9900 } 9901 9902 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 9903 9904 if (t4_nrxq < 1) { 9905 #ifdef RSS 9906 t4_nrxq = rss_getnumbuckets(); 9907 #else 9908 calculate_nqueues(&t4_nrxq, nc, NRXQ); 9909 #endif 9910 } 9911 9912 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 9913 9914 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 9915 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 9916 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 9917 #endif 9918 #ifdef TCP_OFFLOAD 9919 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 9920 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 9921 9922 if (t4_toecaps_allowed == -1) 9923 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 9924 9925 if (t4_rdmacaps_allowed == -1) { 9926 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 9927 FW_CAPS_CONFIG_RDMA_RDMAC; 9928 } 9929 9930 if (t4_iscsicaps_allowed == -1) { 9931 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 9932 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 9933 FW_CAPS_CONFIG_ISCSI_T10DIF; 9934 } 9935 9936 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 9937 t4_tmr_idx_ofld = TMR_IDX_OFLD; 9938 9939 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 9940 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 9941 #else 9942 if (t4_toecaps_allowed == -1) 9943 t4_toecaps_allowed = 0; 9944 9945 if (t4_rdmacaps_allowed == -1) 9946 t4_rdmacaps_allowed = 0; 9947 9948 if (t4_iscsicaps_allowed == -1) 9949 t4_iscsicaps_allowed = 0; 9950 #endif 9951 9952 #ifdef DEV_NETMAP 9953 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 9954 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 9955 #endif 9956 9957 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 9958 t4_tmr_idx = TMR_IDX; 9959 9960 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 9961 t4_pktc_idx = PKTC_IDX; 9962 9963 if (t4_qsize_txq < 128) 9964 t4_qsize_txq = 128; 9965 9966 if (t4_qsize_rxq < 128) 9967 t4_qsize_rxq = 128; 9968 while (t4_qsize_rxq & 7) 9969 t4_qsize_rxq++; 9970 9971 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 9972 9973 /* 9974 * Number of VIs to create per-port. The first VI is the "main" regular 9975 * VI for the port. The rest are additional virtual interfaces on the 9976 * same physical port. Note that the main VI does not have native 9977 * netmap support but the extra VIs do. 9978 * 9979 * Limit the number of VIs per port to the number of available 9980 * MAC addresses per port. 9981 */ 9982 if (t4_num_vis < 1) 9983 t4_num_vis = 1; 9984 if (t4_num_vis > nitems(vi_mac_funcs)) { 9985 t4_num_vis = nitems(vi_mac_funcs); 9986 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 9987 } 9988 9989 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 9990 pcie_relaxed_ordering = 1; 9991 #if defined(__i386__) || defined(__amd64__) 9992 if (cpu_vendor_id == CPU_VENDOR_INTEL) 9993 pcie_relaxed_ordering = 0; 9994 #endif 9995 } 9996 } 9997 9998 #ifdef DDB 9999 static void 10000 t4_dump_tcb(struct adapter *sc, int tid) 10001 { 10002 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 10003 10004 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 10005 save = t4_read_reg(sc, reg); 10006 base = sc->memwin[2].mw_base; 10007 10008 /* Dump TCB for the tid */ 10009 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 10010 tcb_addr += tid * TCB_SIZE; 10011 10012 if (is_t4(sc)) { 10013 pf = 0; 10014 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 10015 } else { 10016 pf = V_PFNUM(sc->pf); 10017 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 10018 } 10019 t4_write_reg(sc, reg, win_pos | pf); 10020 t4_read_reg(sc, reg); 10021 10022 off = tcb_addr - win_pos; 10023 for (i = 0; i < 4; i++) { 10024 uint32_t buf[8]; 10025 for (j = 0; j < 8; j++, off += 4) 10026 buf[j] = htonl(t4_read_reg(sc, base + off)); 10027 10028 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 10029 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 10030 buf[7]); 10031 } 10032 10033 t4_write_reg(sc, reg, save); 10034 t4_read_reg(sc, reg); 10035 } 10036 10037 static void 10038 t4_dump_devlog(struct adapter *sc) 10039 { 10040 struct devlog_params *dparams = &sc->params.devlog; 10041 struct fw_devlog_e e; 10042 int i, first, j, m, nentries, rc; 10043 uint64_t ftstamp = UINT64_MAX; 10044 10045 if (dparams->start == 0) { 10046 db_printf("devlog params not valid\n"); 10047 return; 10048 } 10049 10050 nentries = dparams->size / sizeof(struct fw_devlog_e); 10051 m = fwmtype_to_hwmtype(dparams->memtype); 10052 10053 /* Find the first entry. */ 10054 first = -1; 10055 for (i = 0; i < nentries && !db_pager_quit; i++) { 10056 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10057 sizeof(e), (void *)&e); 10058 if (rc != 0) 10059 break; 10060 10061 if (e.timestamp == 0) 10062 break; 10063 10064 e.timestamp = be64toh(e.timestamp); 10065 if (e.timestamp < ftstamp) { 10066 ftstamp = e.timestamp; 10067 first = i; 10068 } 10069 } 10070 10071 if (first == -1) 10072 return; 10073 10074 i = first; 10075 do { 10076 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10077 sizeof(e), (void *)&e); 10078 if (rc != 0) 10079 return; 10080 10081 if (e.timestamp == 0) 10082 return; 10083 10084 e.timestamp = be64toh(e.timestamp); 10085 e.seqno = be32toh(e.seqno); 10086 for (j = 0; j < 8; j++) 10087 e.params[j] = be32toh(e.params[j]); 10088 10089 db_printf("%10d %15ju %8s %8s ", 10090 e.seqno, e.timestamp, 10091 (e.level < nitems(devlog_level_strings) ? 10092 devlog_level_strings[e.level] : "UNKNOWN"), 10093 (e.facility < nitems(devlog_facility_strings) ? 10094 devlog_facility_strings[e.facility] : "UNKNOWN")); 10095 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10096 e.params[3], e.params[4], e.params[5], e.params[6], 10097 e.params[7]); 10098 10099 if (++i == nentries) 10100 i = 0; 10101 } while (i != first && !db_pager_quit); 10102 } 10103 10104 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10105 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10106 10107 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10108 { 10109 device_t dev; 10110 int t; 10111 bool valid; 10112 10113 valid = false; 10114 t = db_read_token(); 10115 if (t == tIDENT) { 10116 dev = device_lookup_by_name(db_tok_string); 10117 valid = true; 10118 } 10119 db_skip_to_eol(); 10120 if (!valid) { 10121 db_printf("usage: show t4 devlog <nexus>\n"); 10122 return; 10123 } 10124 10125 if (dev == NULL) { 10126 db_printf("device not found\n"); 10127 return; 10128 } 10129 10130 t4_dump_devlog(device_get_softc(dev)); 10131 } 10132 10133 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10134 { 10135 device_t dev; 10136 int radix, tid, t; 10137 bool valid; 10138 10139 valid = false; 10140 radix = db_radix; 10141 db_radix = 10; 10142 t = db_read_token(); 10143 if (t == tIDENT) { 10144 dev = device_lookup_by_name(db_tok_string); 10145 t = db_read_token(); 10146 if (t == tNUMBER) { 10147 tid = db_tok_number; 10148 valid = true; 10149 } 10150 } 10151 db_radix = radix; 10152 db_skip_to_eol(); 10153 if (!valid) { 10154 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10155 return; 10156 } 10157 10158 if (dev == NULL) { 10159 db_printf("device not found\n"); 10160 return; 10161 } 10162 if (tid < 0) { 10163 db_printf("invalid tid\n"); 10164 return; 10165 } 10166 10167 t4_dump_tcb(device_get_softc(dev), tid); 10168 } 10169 #endif 10170 10171 /* 10172 * Borrowed from cesa_prep_aes_key(). 10173 * 10174 * NB: The crypto engine wants the words in the decryption key in reverse 10175 * order. 10176 */ 10177 void 10178 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 10179 { 10180 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 10181 uint32_t *dkey; 10182 int i; 10183 10184 rijndaelKeySetupEnc(ek, enc_key, kbits); 10185 dkey = dec_key; 10186 dkey += (kbits / 8) / 4; 10187 10188 switch (kbits) { 10189 case 128: 10190 for (i = 0; i < 4; i++) 10191 *--dkey = htobe32(ek[4 * 10 + i]); 10192 break; 10193 case 192: 10194 for (i = 0; i < 2; i++) 10195 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10196 for (i = 0; i < 4; i++) 10197 *--dkey = htobe32(ek[4 * 12 + i]); 10198 break; 10199 case 256: 10200 for (i = 0; i < 4; i++) 10201 *--dkey = htobe32(ek[4 * 13 + i]); 10202 for (i = 0; i < 4; i++) 10203 *--dkey = htobe32(ek[4 * 14 + i]); 10204 break; 10205 } 10206 MPASS(dkey == dec_key); 10207 } 10208 10209 static struct sx mlu; /* mod load unload */ 10210 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10211 10212 static int 10213 mod_event(module_t mod, int cmd, void *arg) 10214 { 10215 int rc = 0; 10216 static int loaded = 0; 10217 10218 switch (cmd) { 10219 case MOD_LOAD: 10220 sx_xlock(&mlu); 10221 if (loaded++ == 0) { 10222 t4_sge_modload(); 10223 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10224 t4_filter_rpl, CPL_COOKIE_FILTER); 10225 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 10226 do_l2t_write_rpl, CPL_COOKIE_FILTER); 10227 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 10228 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 10229 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10230 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 10231 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 10232 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10233 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10234 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10235 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 10236 do_smt_write_rpl); 10237 sx_init(&t4_list_lock, "T4/T5 adapters"); 10238 SLIST_INIT(&t4_list); 10239 #ifdef TCP_OFFLOAD 10240 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10241 SLIST_INIT(&t4_uld_list); 10242 #endif 10243 t4_tracer_modload(); 10244 tweak_tunables(); 10245 } 10246 sx_xunlock(&mlu); 10247 break; 10248 10249 case MOD_UNLOAD: 10250 sx_xlock(&mlu); 10251 if (--loaded == 0) { 10252 int tries; 10253 10254 sx_slock(&t4_list_lock); 10255 if (!SLIST_EMPTY(&t4_list)) { 10256 rc = EBUSY; 10257 sx_sunlock(&t4_list_lock); 10258 goto done_unload; 10259 } 10260 #ifdef TCP_OFFLOAD 10261 sx_slock(&t4_uld_list_lock); 10262 if (!SLIST_EMPTY(&t4_uld_list)) { 10263 rc = EBUSY; 10264 sx_sunlock(&t4_uld_list_lock); 10265 sx_sunlock(&t4_list_lock); 10266 goto done_unload; 10267 } 10268 #endif 10269 tries = 0; 10270 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10271 uprintf("%ju clusters with custom free routine " 10272 "still is use.\n", t4_sge_extfree_refs()); 10273 pause("t4unload", 2 * hz); 10274 } 10275 #ifdef TCP_OFFLOAD 10276 sx_sunlock(&t4_uld_list_lock); 10277 #endif 10278 sx_sunlock(&t4_list_lock); 10279 10280 if (t4_sge_extfree_refs() == 0) { 10281 t4_tracer_modunload(); 10282 #ifdef TCP_OFFLOAD 10283 sx_destroy(&t4_uld_list_lock); 10284 #endif 10285 sx_destroy(&t4_list_lock); 10286 t4_sge_modunload(); 10287 loaded = 0; 10288 } else { 10289 rc = EBUSY; 10290 loaded++; /* undo earlier decrement */ 10291 } 10292 } 10293 done_unload: 10294 sx_xunlock(&mlu); 10295 break; 10296 } 10297 10298 return (rc); 10299 } 10300 10301 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10302 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10303 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10304 10305 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10306 MODULE_VERSION(t4nex, 1); 10307 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10308 #ifdef DEV_NETMAP 10309 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10310 #endif /* DEV_NETMAP */ 10311 10312 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10313 MODULE_VERSION(t5nex, 1); 10314 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10315 #ifdef DEV_NETMAP 10316 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10317 #endif /* DEV_NETMAP */ 10318 10319 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10320 MODULE_VERSION(t6nex, 1); 10321 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10322 #ifdef DEV_NETMAP 10323 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10324 #endif /* DEV_NETMAP */ 10325 10326 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10327 MODULE_VERSION(cxgbe, 1); 10328 10329 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10330 MODULE_VERSION(cxl, 1); 10331 10332 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10333 MODULE_VERSION(cc, 1); 10334 10335 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10336 MODULE_VERSION(vcxgbe, 1); 10337 10338 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10339 MODULE_VERSION(vcxl, 1); 10340 10341 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10342 MODULE_VERSION(vcc, 1); 10343