1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_ratelimit.h" 37 #include "opt_rss.h" 38 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/priv.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #if defined(__i386__) || defined(__amd64__) 67 #include <machine/md_var.h> 68 #include <machine/cputypes.h> 69 #include <vm/vm.h> 70 #include <vm/pmap.h> 71 #endif 72 #include <crypto/rijndael/rijndael.h> 73 #ifdef DDB 74 #include <ddb/ddb.h> 75 #include <ddb/db_lex.h> 76 #endif 77 78 #include "common/common.h" 79 #include "common/t4_msg.h" 80 #include "common/t4_regs.h" 81 #include "common/t4_regs_values.h" 82 #include "cudbg/cudbg.h" 83 #include "t4_ioctl.h" 84 #include "t4_l2t.h" 85 #include "t4_mp_ring.h" 86 #include "t4_if.h" 87 88 /* T4 bus driver interface */ 89 static int t4_probe(device_t); 90 static int t4_attach(device_t); 91 static int t4_detach(device_t); 92 static int t4_ready(device_t); 93 static int t4_read_port_device(device_t, int, device_t *); 94 static device_method_t t4_methods[] = { 95 DEVMETHOD(device_probe, t4_probe), 96 DEVMETHOD(device_attach, t4_attach), 97 DEVMETHOD(device_detach, t4_detach), 98 99 DEVMETHOD(t4_is_main_ready, t4_ready), 100 DEVMETHOD(t4_read_port_device, t4_read_port_device), 101 102 DEVMETHOD_END 103 }; 104 static driver_t t4_driver = { 105 "t4nex", 106 t4_methods, 107 sizeof(struct adapter) 108 }; 109 110 111 /* T4 port (cxgbe) interface */ 112 static int cxgbe_probe(device_t); 113 static int cxgbe_attach(device_t); 114 static int cxgbe_detach(device_t); 115 device_method_t cxgbe_methods[] = { 116 DEVMETHOD(device_probe, cxgbe_probe), 117 DEVMETHOD(device_attach, cxgbe_attach), 118 DEVMETHOD(device_detach, cxgbe_detach), 119 { 0, 0 } 120 }; 121 static driver_t cxgbe_driver = { 122 "cxgbe", 123 cxgbe_methods, 124 sizeof(struct port_info) 125 }; 126 127 /* T4 VI (vcxgbe) interface */ 128 static int vcxgbe_probe(device_t); 129 static int vcxgbe_attach(device_t); 130 static int vcxgbe_detach(device_t); 131 static device_method_t vcxgbe_methods[] = { 132 DEVMETHOD(device_probe, vcxgbe_probe), 133 DEVMETHOD(device_attach, vcxgbe_attach), 134 DEVMETHOD(device_detach, vcxgbe_detach), 135 { 0, 0 } 136 }; 137 static driver_t vcxgbe_driver = { 138 "vcxgbe", 139 vcxgbe_methods, 140 sizeof(struct vi_info) 141 }; 142 143 static d_ioctl_t t4_ioctl; 144 145 static struct cdevsw t4_cdevsw = { 146 .d_version = D_VERSION, 147 .d_ioctl = t4_ioctl, 148 .d_name = "t4nex", 149 }; 150 151 /* T5 bus driver interface */ 152 static int t5_probe(device_t); 153 static device_method_t t5_methods[] = { 154 DEVMETHOD(device_probe, t5_probe), 155 DEVMETHOD(device_attach, t4_attach), 156 DEVMETHOD(device_detach, t4_detach), 157 158 DEVMETHOD(t4_is_main_ready, t4_ready), 159 DEVMETHOD(t4_read_port_device, t4_read_port_device), 160 161 DEVMETHOD_END 162 }; 163 static driver_t t5_driver = { 164 "t5nex", 165 t5_methods, 166 sizeof(struct adapter) 167 }; 168 169 170 /* T5 port (cxl) interface */ 171 static driver_t cxl_driver = { 172 "cxl", 173 cxgbe_methods, 174 sizeof(struct port_info) 175 }; 176 177 /* T5 VI (vcxl) interface */ 178 static driver_t vcxl_driver = { 179 "vcxl", 180 vcxgbe_methods, 181 sizeof(struct vi_info) 182 }; 183 184 /* T6 bus driver interface */ 185 static int t6_probe(device_t); 186 static device_method_t t6_methods[] = { 187 DEVMETHOD(device_probe, t6_probe), 188 DEVMETHOD(device_attach, t4_attach), 189 DEVMETHOD(device_detach, t4_detach), 190 191 DEVMETHOD(t4_is_main_ready, t4_ready), 192 DEVMETHOD(t4_read_port_device, t4_read_port_device), 193 194 DEVMETHOD_END 195 }; 196 static driver_t t6_driver = { 197 "t6nex", 198 t6_methods, 199 sizeof(struct adapter) 200 }; 201 202 203 /* T6 port (cc) interface */ 204 static driver_t cc_driver = { 205 "cc", 206 cxgbe_methods, 207 sizeof(struct port_info) 208 }; 209 210 /* T6 VI (vcc) interface */ 211 static driver_t vcc_driver = { 212 "vcc", 213 vcxgbe_methods, 214 sizeof(struct vi_info) 215 }; 216 217 /* ifnet + media interface */ 218 static void cxgbe_init(void *); 219 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 220 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 221 static void cxgbe_qflush(struct ifnet *); 222 static int cxgbe_media_change(struct ifnet *); 223 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 224 225 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 226 227 /* 228 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 229 * then ADAPTER_LOCK, then t4_uld_list_lock. 230 */ 231 static struct sx t4_list_lock; 232 SLIST_HEAD(, adapter) t4_list; 233 #ifdef TCP_OFFLOAD 234 static struct sx t4_uld_list_lock; 235 SLIST_HEAD(, uld_info) t4_uld_list; 236 #endif 237 238 /* 239 * Tunables. See tweak_tunables() too. 240 * 241 * Each tunable is set to a default value here if it's known at compile-time. 242 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 243 * provide a reasonable default (upto n) when the driver is loaded. 244 * 245 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 246 * T5 are under hw.cxl. 247 */ 248 249 /* 250 * Number of queues for tx and rx, NIC and offload. 251 */ 252 #define NTXQ 16 253 int t4_ntxq = -NTXQ; 254 TUNABLE_INT("hw.cxgbe.ntxq", &t4_ntxq); 255 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 256 257 #define NRXQ 8 258 int t4_nrxq = -NRXQ; 259 TUNABLE_INT("hw.cxgbe.nrxq", &t4_nrxq); 260 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 261 262 #define NTXQ_VI 1 263 static int t4_ntxq_vi = -NTXQ_VI; 264 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi); 265 266 #define NRXQ_VI 1 267 static int t4_nrxq_vi = -NRXQ_VI; 268 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi); 269 270 static int t4_rsrv_noflowq = 0; 271 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq); 272 273 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 274 #define NOFLDTXQ 8 275 static int t4_nofldtxq = -NOFLDTXQ; 276 TUNABLE_INT("hw.cxgbe.nofldtxq", &t4_nofldtxq); 277 278 #define NOFLDRXQ 2 279 static int t4_nofldrxq = -NOFLDRXQ; 280 TUNABLE_INT("hw.cxgbe.nofldrxq", &t4_nofldrxq); 281 282 #define NOFLDTXQ_VI 1 283 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 284 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi); 285 286 #define NOFLDRXQ_VI 1 287 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 288 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi); 289 290 #define TMR_IDX_OFLD 1 291 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 292 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_ofld", &t4_tmr_idx_ofld); 293 294 #define PKTC_IDX_OFLD (-1) 295 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 296 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_ofld", &t4_pktc_idx_ofld); 297 298 /* 0 means chip/fw default, non-zero number is value in microseconds */ 299 static u_long t4_toe_keepalive_idle = 0; 300 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_idle", &t4_toe_keepalive_idle); 301 302 /* 0 means chip/fw default, non-zero number is value in microseconds */ 303 static u_long t4_toe_keepalive_interval = 0; 304 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_interval", &t4_toe_keepalive_interval); 305 306 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 307 static int t4_toe_keepalive_count = 0; 308 TUNABLE_INT("hw.cxgbe.toe.keepalive_count", &t4_toe_keepalive_count); 309 310 /* 0 means chip/fw default, non-zero number is value in microseconds */ 311 static u_long t4_toe_rexmt_min = 0; 312 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_min", &t4_toe_rexmt_min); 313 314 /* 0 means chip/fw default, non-zero number is value in microseconds */ 315 static u_long t4_toe_rexmt_max = 0; 316 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_max", &t4_toe_rexmt_max); 317 318 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 319 static int t4_toe_rexmt_count = 0; 320 TUNABLE_INT("hw.cxgbe.toe.rexmt_count", &t4_toe_rexmt_count); 321 322 /* -1 means chip/fw default, other values are raw backoff values to use */ 323 static int t4_toe_rexmt_backoff[16] = { 324 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 325 }; 326 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.0", &t4_toe_rexmt_backoff[0]); 327 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.1", &t4_toe_rexmt_backoff[1]); 328 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.2", &t4_toe_rexmt_backoff[2]); 329 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.3", &t4_toe_rexmt_backoff[3]); 330 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.4", &t4_toe_rexmt_backoff[4]); 331 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.5", &t4_toe_rexmt_backoff[5]); 332 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.6", &t4_toe_rexmt_backoff[6]); 333 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.7", &t4_toe_rexmt_backoff[7]); 334 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.8", &t4_toe_rexmt_backoff[8]); 335 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.9", &t4_toe_rexmt_backoff[9]); 336 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.10", &t4_toe_rexmt_backoff[10]); 337 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.11", &t4_toe_rexmt_backoff[11]); 338 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.12", &t4_toe_rexmt_backoff[12]); 339 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.13", &t4_toe_rexmt_backoff[13]); 340 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.14", &t4_toe_rexmt_backoff[14]); 341 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.15", &t4_toe_rexmt_backoff[15]); 342 #endif 343 344 #ifdef DEV_NETMAP 345 #define NNMTXQ_VI 2 346 static int t4_nnmtxq_vi = -NNMTXQ_VI; 347 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi); 348 349 #define NNMRXQ_VI 2 350 static int t4_nnmrxq_vi = -NNMRXQ_VI; 351 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi); 352 #endif 353 354 /* 355 * Holdoff parameters for ports. 356 */ 357 #define TMR_IDX 1 358 int t4_tmr_idx = TMR_IDX; 359 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx", &t4_tmr_idx); 360 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 361 362 #define PKTC_IDX (-1) 363 int t4_pktc_idx = PKTC_IDX; 364 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx", &t4_pktc_idx); 365 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 366 367 /* 368 * Size (# of entries) of each tx and rx queue. 369 */ 370 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 371 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 372 373 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 374 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 375 376 /* 377 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 378 */ 379 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 380 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 381 382 /* 383 * Configuration file. All the _CF names here are special. 384 */ 385 #define DEFAULT_CF "default" 386 #define BUILTIN_CF "built-in" 387 #define FLASH_CF "flash" 388 #define UWIRE_CF "uwire" 389 #define FPGA_CF "fpga" 390 static char t4_cfg_file[32] = DEFAULT_CF; 391 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 392 393 /* 394 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively). 395 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 396 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 397 * mark or when signalled to do so, 0 to never emit PAUSE. 398 */ 399 static int t4_pause_settings = PAUSE_TX | PAUSE_RX; 400 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings); 401 402 /* 403 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS, 404 * FEC_RESERVED respectively). 405 * -1 to run with the firmware default. 406 * 0 to disable FEC. 407 */ 408 static int t4_fec = -1; 409 TUNABLE_INT("hw.cxgbe.fec", &t4_fec); 410 411 /* 412 * Link autonegotiation. 413 * -1 to run with the firmware default. 414 * 0 to disable. 415 * 1 to enable. 416 */ 417 static int t4_autoneg = -1; 418 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg); 419 420 /* 421 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 422 * encouraged respectively). 423 */ 424 static unsigned int t4_fw_install = 1; 425 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 426 427 /* 428 * ASIC features that will be used. Disable the ones you don't want so that the 429 * chip resources aren't wasted on features that will not be used. 430 */ 431 static int t4_nbmcaps_allowed = 0; 432 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed); 433 434 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 435 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 436 437 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 438 FW_CAPS_CONFIG_SWITCH_EGRESS; 439 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed); 440 441 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 442 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 443 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 444 445 static int t4_toecaps_allowed = -1; 446 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 447 448 static int t4_rdmacaps_allowed = -1; 449 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 450 451 static int t4_cryptocaps_allowed = -1; 452 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed); 453 454 static int t4_iscsicaps_allowed = -1; 455 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 456 457 static int t4_fcoecaps_allowed = 0; 458 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 459 460 static int t5_write_combine = 0; 461 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 462 463 static int t4_num_vis = 1; 464 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis); 465 /* 466 * PCIe Relaxed Ordering. 467 * -1: driver should figure out a good value. 468 * 0: disable RO. 469 * 1: enable RO. 470 * 2: leave RO alone. 471 */ 472 static int pcie_relaxed_ordering = -1; 473 TUNABLE_INT("hw.cxgbe.pcie_relaxed_ordering", &pcie_relaxed_ordering); 474 475 static int t4_panic_on_fatal_err = 0; 476 TUNABLE_INT("hw.cxgbe.panic_on_fatal_err", &t4_panic_on_fatal_err); 477 478 #ifdef TCP_OFFLOAD 479 /* 480 * TOE tunables. 481 */ 482 static int t4_cop_managed_offloading = 0; 483 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading); 484 #endif 485 486 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 487 static int vi_mac_funcs[] = { 488 FW_VI_FUNC_ETH, 489 FW_VI_FUNC_OFLD, 490 FW_VI_FUNC_IWARP, 491 FW_VI_FUNC_OPENISCSI, 492 FW_VI_FUNC_OPENFCOE, 493 FW_VI_FUNC_FOISCSI, 494 FW_VI_FUNC_FOFCOE, 495 }; 496 497 struct intrs_and_queues { 498 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 499 uint16_t num_vis; /* number of VIs for each port */ 500 uint16_t nirq; /* Total # of vectors */ 501 uint16_t ntxq; /* # of NIC txq's for each port */ 502 uint16_t nrxq; /* # of NIC rxq's for each port */ 503 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 504 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 505 506 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 507 uint16_t ntxq_vi; /* # of NIC txq's */ 508 uint16_t nrxq_vi; /* # of NIC rxq's */ 509 uint16_t nofldtxq_vi; /* # of TOE txq's */ 510 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 511 uint16_t nnmtxq_vi; /* # of netmap txq's */ 512 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 513 }; 514 515 static void setup_memwin(struct adapter *); 516 static void position_memwin(struct adapter *, int, uint32_t); 517 static int validate_mem_range(struct adapter *, uint32_t, int); 518 static int fwmtype_to_hwmtype(int); 519 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 520 uint32_t *); 521 static int fixup_devlog_params(struct adapter *); 522 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 523 static int prep_firmware(struct adapter *); 524 static int partition_resources(struct adapter *, const struct firmware *, 525 const char *); 526 static int get_params__pre_init(struct adapter *); 527 static int get_params__post_init(struct adapter *); 528 static int set_params__post_init(struct adapter *); 529 static void t4_set_desc(struct adapter *); 530 static void build_medialist(struct port_info *, struct ifmedia *); 531 static void init_l1cfg(struct port_info *); 532 static int cxgbe_init_synchronized(struct vi_info *); 533 static int cxgbe_uninit_synchronized(struct vi_info *); 534 static void quiesce_txq(struct adapter *, struct sge_txq *); 535 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 536 static void quiesce_iq(struct adapter *, struct sge_iq *); 537 static void quiesce_fl(struct adapter *, struct sge_fl *); 538 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 539 driver_intr_t *, void *, char *); 540 static int t4_free_irq(struct adapter *, struct irq *); 541 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 542 static void vi_refresh_stats(struct adapter *, struct vi_info *); 543 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 544 static void cxgbe_tick(void *); 545 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 546 static void cxgbe_sysctls(struct port_info *); 547 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 548 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 549 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 550 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 551 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 552 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 553 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 554 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 555 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 556 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 557 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 558 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 559 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 560 #ifdef SBUF_DRAIN 561 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 562 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 563 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 564 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 565 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 566 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 567 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 568 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 569 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 570 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 571 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 572 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 573 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 574 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 575 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 576 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 577 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 578 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 579 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 580 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 581 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 582 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 583 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 584 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 585 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 586 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 587 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 588 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 589 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 590 #endif 591 #ifdef TCP_OFFLOAD 592 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 593 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 594 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 595 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 596 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 597 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 598 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 599 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 600 #endif 601 static int get_sge_context(struct adapter *, struct t4_sge_context *); 602 static int load_fw(struct adapter *, struct t4_data *); 603 static int load_cfg(struct adapter *, struct t4_data *); 604 static int load_boot(struct adapter *, struct t4_bootrom *); 605 static int load_bootcfg(struct adapter *, struct t4_data *); 606 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 607 static void free_offload_policy(struct t4_offload_policy *); 608 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 609 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 610 static int read_i2c(struct adapter *, struct t4_i2c_data *); 611 #ifdef TCP_OFFLOAD 612 static int toe_capability(struct vi_info *, int); 613 #endif 614 static int mod_event(module_t, int, void *); 615 static int notify_siblings(device_t, int); 616 617 struct { 618 uint16_t device; 619 char *desc; 620 } t4_pciids[] = { 621 {0xa000, "Chelsio Terminator 4 FPGA"}, 622 {0x4400, "Chelsio T440-dbg"}, 623 {0x4401, "Chelsio T420-CR"}, 624 {0x4402, "Chelsio T422-CR"}, 625 {0x4403, "Chelsio T440-CR"}, 626 {0x4404, "Chelsio T420-BCH"}, 627 {0x4405, "Chelsio T440-BCH"}, 628 {0x4406, "Chelsio T440-CH"}, 629 {0x4407, "Chelsio T420-SO"}, 630 {0x4408, "Chelsio T420-CX"}, 631 {0x4409, "Chelsio T420-BT"}, 632 {0x440a, "Chelsio T404-BT"}, 633 {0x440e, "Chelsio T440-LP-CR"}, 634 }, t5_pciids[] = { 635 {0xb000, "Chelsio Terminator 5 FPGA"}, 636 {0x5400, "Chelsio T580-dbg"}, 637 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 638 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 639 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 640 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 641 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 642 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 643 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 644 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 645 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 646 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 647 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 648 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 649 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 650 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 651 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 652 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 653 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 654 }, t6_pciids[] = { 655 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 656 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 657 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 658 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 659 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 660 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 661 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 662 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 663 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 664 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 665 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 666 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 667 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 668 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 669 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 670 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 671 672 /* Custom */ 673 {0x6480, "Custom T6225-CR"}, 674 {0x6481, "Custom T62100-CR"}, 675 {0x6482, "Custom T6225-CR"}, 676 {0x6483, "Custom T62100-CR"}, 677 {0x6484, "Custom T64100-CR"}, 678 {0x6485, "Custom T6240-SO"}, 679 {0x6486, "Custom T6225-SO-CR"}, 680 {0x6487, "Custom T6225-CR"}, 681 }; 682 683 #ifdef TCP_OFFLOAD 684 /* 685 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 686 * exactly the same for both rxq and ofld_rxq. 687 */ 688 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 689 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 690 #endif 691 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 692 693 static int 694 t4_probe(device_t dev) 695 { 696 int i; 697 uint16_t v = pci_get_vendor(dev); 698 uint16_t d = pci_get_device(dev); 699 uint8_t f = pci_get_function(dev); 700 701 if (v != PCI_VENDOR_ID_CHELSIO) 702 return (ENXIO); 703 704 /* Attach only to PF0 of the FPGA */ 705 if (d == 0xa000 && f != 0) 706 return (ENXIO); 707 708 for (i = 0; i < nitems(t4_pciids); i++) { 709 if (d == t4_pciids[i].device) { 710 device_set_desc(dev, t4_pciids[i].desc); 711 return (BUS_PROBE_DEFAULT); 712 } 713 } 714 715 return (ENXIO); 716 } 717 718 static int 719 t5_probe(device_t dev) 720 { 721 int i; 722 uint16_t v = pci_get_vendor(dev); 723 uint16_t d = pci_get_device(dev); 724 uint8_t f = pci_get_function(dev); 725 726 if (v != PCI_VENDOR_ID_CHELSIO) 727 return (ENXIO); 728 729 /* Attach only to PF0 of the FPGA */ 730 if (d == 0xb000 && f != 0) 731 return (ENXIO); 732 733 for (i = 0; i < nitems(t5_pciids); i++) { 734 if (d == t5_pciids[i].device) { 735 device_set_desc(dev, t5_pciids[i].desc); 736 return (BUS_PROBE_DEFAULT); 737 } 738 } 739 740 return (ENXIO); 741 } 742 743 static int 744 t6_probe(device_t dev) 745 { 746 int i; 747 uint16_t v = pci_get_vendor(dev); 748 uint16_t d = pci_get_device(dev); 749 750 if (v != PCI_VENDOR_ID_CHELSIO) 751 return (ENXIO); 752 753 for (i = 0; i < nitems(t6_pciids); i++) { 754 if (d == t6_pciids[i].device) { 755 device_set_desc(dev, t6_pciids[i].desc); 756 return (BUS_PROBE_DEFAULT); 757 } 758 } 759 760 return (ENXIO); 761 } 762 763 static void 764 t5_attribute_workaround(device_t dev) 765 { 766 device_t root_port; 767 uint32_t v; 768 769 /* 770 * The T5 chips do not properly echo the No Snoop and Relaxed 771 * Ordering attributes when replying to a TLP from a Root 772 * Port. As a workaround, find the parent Root Port and 773 * disable No Snoop and Relaxed Ordering. Note that this 774 * affects all devices under this root port. 775 */ 776 root_port = pci_find_pcie_root_port(dev); 777 if (root_port == NULL) { 778 device_printf(dev, "Unable to find parent root port\n"); 779 return; 780 } 781 782 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 783 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 784 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 785 0) 786 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 787 device_get_nameunit(root_port)); 788 } 789 790 static const struct devnames devnames[] = { 791 { 792 .nexus_name = "t4nex", 793 .ifnet_name = "cxgbe", 794 .vi_ifnet_name = "vcxgbe", 795 .pf03_drv_name = "t4iov", 796 .vf_nexus_name = "t4vf", 797 .vf_ifnet_name = "cxgbev" 798 }, { 799 .nexus_name = "t5nex", 800 .ifnet_name = "cxl", 801 .vi_ifnet_name = "vcxl", 802 .pf03_drv_name = "t5iov", 803 .vf_nexus_name = "t5vf", 804 .vf_ifnet_name = "cxlv" 805 }, { 806 .nexus_name = "t6nex", 807 .ifnet_name = "cc", 808 .vi_ifnet_name = "vcc", 809 .pf03_drv_name = "t6iov", 810 .vf_nexus_name = "t6vf", 811 .vf_ifnet_name = "ccv" 812 } 813 }; 814 815 void 816 t4_init_devnames(struct adapter *sc) 817 { 818 int id; 819 820 id = chip_id(sc); 821 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 822 sc->names = &devnames[id - CHELSIO_T4]; 823 else { 824 device_printf(sc->dev, "chip id %d is not supported.\n", id); 825 sc->names = NULL; 826 } 827 } 828 829 static int 830 t4_attach(device_t dev) 831 { 832 struct adapter *sc; 833 int rc = 0, i, j, rqidx, tqidx, nports; 834 struct make_dev_args mda; 835 struct intrs_and_queues iaq; 836 struct sge *s; 837 uint32_t *buf; 838 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 839 int ofld_tqidx; 840 #endif 841 #ifdef TCP_OFFLOAD 842 int ofld_rqidx; 843 #endif 844 #ifdef DEV_NETMAP 845 int nm_rqidx, nm_tqidx; 846 #endif 847 int num_vis; 848 849 sc = device_get_softc(dev); 850 sc->dev = dev; 851 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 852 853 if ((pci_get_device(dev) & 0xff00) == 0x5400) 854 t5_attribute_workaround(dev); 855 pci_enable_busmaster(dev); 856 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 857 uint32_t v; 858 859 pci_set_max_read_req(dev, 4096); 860 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 861 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 862 if (pcie_relaxed_ordering == 0 && 863 (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 864 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 865 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 866 } else if (pcie_relaxed_ordering == 1 && 867 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 868 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 869 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 870 } 871 } 872 873 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 874 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 875 sc->traceq = -1; 876 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 877 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 878 device_get_nameunit(dev)); 879 880 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 881 device_get_nameunit(dev)); 882 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 883 t4_add_adapter(sc); 884 885 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 886 TAILQ_INIT(&sc->sfl); 887 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 888 889 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 890 891 sc->policy = NULL; 892 rw_init(&sc->policy_lock, "connection offload policy"); 893 894 rc = t4_map_bars_0_and_4(sc); 895 if (rc != 0) 896 goto done; /* error message displayed already */ 897 898 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 899 900 /* Prepare the adapter for operation. */ 901 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 902 rc = -t4_prep_adapter(sc, buf); 903 free(buf, M_CXGBE); 904 if (rc != 0) { 905 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 906 goto done; 907 } 908 909 /* 910 * This is the real PF# to which we're attaching. Works from within PCI 911 * passthrough environments too, where pci_get_function() could return a 912 * different PF# depending on the passthrough configuration. We need to 913 * use the real PF# in all our communication with the firmware. 914 */ 915 j = t4_read_reg(sc, A_PL_WHOAMI); 916 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 917 sc->mbox = sc->pf; 918 919 t4_init_devnames(sc); 920 if (sc->names == NULL) { 921 rc = ENOTSUP; 922 goto done; /* error message displayed already */ 923 } 924 925 /* 926 * Do this really early, with the memory windows set up even before the 927 * character device. The userland tool's register i/o and mem read 928 * will work even in "recovery mode". 929 */ 930 setup_memwin(sc); 931 if (t4_init_devlog_params(sc, 0) == 0) 932 fixup_devlog_params(sc); 933 make_dev_args_init(&mda); 934 mda.mda_devsw = &t4_cdevsw; 935 mda.mda_uid = UID_ROOT; 936 mda.mda_gid = GID_WHEEL; 937 mda.mda_mode = 0600; 938 mda.mda_si_drv1 = sc; 939 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 940 if (rc != 0) 941 device_printf(dev, "failed to create nexus char device: %d.\n", 942 rc); 943 944 /* Go no further if recovery mode has been requested. */ 945 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 946 device_printf(dev, "recovery mode.\n"); 947 goto done; 948 } 949 950 #if defined(__i386__) 951 if ((cpu_feature & CPUID_CX8) == 0) { 952 device_printf(dev, "64 bit atomics not available.\n"); 953 rc = ENOTSUP; 954 goto done; 955 } 956 #endif 957 958 /* Prepare the firmware for operation */ 959 rc = prep_firmware(sc); 960 if (rc != 0) 961 goto done; /* error message displayed already */ 962 963 rc = get_params__post_init(sc); 964 if (rc != 0) 965 goto done; /* error message displayed already */ 966 967 rc = set_params__post_init(sc); 968 if (rc != 0) 969 goto done; /* error message displayed already */ 970 971 rc = t4_map_bar_2(sc); 972 if (rc != 0) 973 goto done; /* error message displayed already */ 974 975 rc = t4_create_dma_tag(sc); 976 if (rc != 0) 977 goto done; /* error message displayed already */ 978 979 /* 980 * First pass over all the ports - allocate VIs and initialize some 981 * basic parameters like mac address, port type, etc. 982 */ 983 for_each_port(sc, i) { 984 struct port_info *pi; 985 986 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 987 sc->port[i] = pi; 988 989 /* These must be set before t4_port_init */ 990 pi->adapter = sc; 991 pi->port_id = i; 992 /* 993 * XXX: vi[0] is special so we can't delay this allocation until 994 * pi->nvi's final value is known. 995 */ 996 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 997 M_ZERO | M_WAITOK); 998 999 /* 1000 * Allocate the "main" VI and initialize parameters 1001 * like mac addr. 1002 */ 1003 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1004 if (rc != 0) { 1005 device_printf(dev, "unable to initialize port %d: %d\n", 1006 i, rc); 1007 free(pi->vi, M_CXGBE); 1008 free(pi, M_CXGBE); 1009 sc->port[i] = NULL; 1010 goto done; 1011 } 1012 1013 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1014 device_get_nameunit(dev), i); 1015 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1016 sc->chan_map[pi->tx_chan] = i; 1017 1018 /* All VIs on this port share this media. */ 1019 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1020 cxgbe_media_status); 1021 1022 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1); 1023 if (pi->dev == NULL) { 1024 device_printf(dev, 1025 "failed to add device for port %d.\n", i); 1026 rc = ENXIO; 1027 goto done; 1028 } 1029 pi->vi[0].dev = pi->dev; 1030 device_set_softc(pi->dev, pi); 1031 } 1032 1033 /* 1034 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1035 */ 1036 nports = sc->params.nports; 1037 rc = cfg_itype_and_nqueues(sc, &iaq); 1038 if (rc != 0) 1039 goto done; /* error message displayed already */ 1040 1041 num_vis = iaq.num_vis; 1042 sc->intr_type = iaq.intr_type; 1043 sc->intr_count = iaq.nirq; 1044 1045 s = &sc->sge; 1046 s->nrxq = nports * iaq.nrxq; 1047 s->ntxq = nports * iaq.ntxq; 1048 if (num_vis > 1) { 1049 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1050 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1051 } 1052 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1053 s->neq += nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 1054 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1055 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1056 if (is_offload(sc) || is_ethoffload(sc)) { 1057 s->nofldtxq = nports * iaq.nofldtxq; 1058 if (num_vis > 1) 1059 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1060 s->neq += s->nofldtxq; 1061 1062 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1063 M_CXGBE, M_ZERO | M_WAITOK); 1064 } 1065 #endif 1066 #ifdef TCP_OFFLOAD 1067 if (is_offload(sc)) { 1068 s->nofldrxq = nports * iaq.nofldrxq; 1069 if (num_vis > 1) 1070 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1071 s->neq += s->nofldrxq; /* free list */ 1072 s->niq += s->nofldrxq; 1073 1074 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1075 M_CXGBE, M_ZERO | M_WAITOK); 1076 } 1077 #endif 1078 #ifdef DEV_NETMAP 1079 if (num_vis > 1) { 1080 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1081 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1082 } 1083 s->neq += s->nnmtxq + s->nnmrxq; 1084 s->niq += s->nnmrxq; 1085 1086 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1087 M_CXGBE, M_ZERO | M_WAITOK); 1088 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1089 M_CXGBE, M_ZERO | M_WAITOK); 1090 #endif 1091 1092 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1093 M_ZERO | M_WAITOK); 1094 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1095 M_ZERO | M_WAITOK); 1096 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1097 M_ZERO | M_WAITOK); 1098 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1099 M_ZERO | M_WAITOK); 1100 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1101 M_ZERO | M_WAITOK); 1102 1103 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1104 M_ZERO | M_WAITOK); 1105 1106 t4_init_l2t(sc, M_WAITOK); 1107 t4_init_tx_sched(sc); 1108 1109 /* 1110 * Second pass over the ports. This time we know the number of rx and 1111 * tx queues that each port should get. 1112 */ 1113 rqidx = tqidx = 0; 1114 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1115 ofld_tqidx = 0; 1116 #endif 1117 #ifdef TCP_OFFLOAD 1118 ofld_rqidx = 0; 1119 #endif 1120 #ifdef DEV_NETMAP 1121 nm_rqidx = nm_tqidx = 0; 1122 #endif 1123 for_each_port(sc, i) { 1124 struct port_info *pi = sc->port[i]; 1125 struct vi_info *vi; 1126 1127 if (pi == NULL) 1128 continue; 1129 1130 pi->nvi = num_vis; 1131 for_each_vi(pi, j, vi) { 1132 vi->pi = pi; 1133 vi->qsize_rxq = t4_qsize_rxq; 1134 vi->qsize_txq = t4_qsize_txq; 1135 1136 vi->first_rxq = rqidx; 1137 vi->first_txq = tqidx; 1138 vi->tmr_idx = t4_tmr_idx; 1139 vi->pktc_idx = t4_pktc_idx; 1140 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1141 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1142 1143 rqidx += vi->nrxq; 1144 tqidx += vi->ntxq; 1145 1146 if (j == 0 && vi->ntxq > 1) 1147 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1148 else 1149 vi->rsrv_noflowq = 0; 1150 1151 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1152 vi->first_ofld_txq = ofld_tqidx; 1153 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1154 ofld_tqidx += vi->nofldtxq; 1155 #endif 1156 #ifdef TCP_OFFLOAD 1157 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1158 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1159 vi->first_ofld_rxq = ofld_rqidx; 1160 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1161 1162 ofld_rqidx += vi->nofldrxq; 1163 #endif 1164 #ifdef DEV_NETMAP 1165 if (j > 0) { 1166 vi->first_nm_rxq = nm_rqidx; 1167 vi->first_nm_txq = nm_tqidx; 1168 vi->nnmrxq = iaq.nnmrxq_vi; 1169 vi->nnmtxq = iaq.nnmtxq_vi; 1170 nm_rqidx += vi->nnmrxq; 1171 nm_tqidx += vi->nnmtxq; 1172 } 1173 #endif 1174 } 1175 } 1176 1177 rc = t4_setup_intr_handlers(sc); 1178 if (rc != 0) { 1179 device_printf(dev, 1180 "failed to setup interrupt handlers: %d\n", rc); 1181 goto done; 1182 } 1183 1184 rc = bus_generic_probe(dev); 1185 if (rc != 0) { 1186 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1187 goto done; 1188 } 1189 1190 /* 1191 * Ensure thread-safe mailbox access (in debug builds). 1192 * 1193 * So far this was the only thread accessing the mailbox but various 1194 * ifnets and sysctls are about to be created and their handlers/ioctls 1195 * will access the mailbox from different threads. 1196 */ 1197 sc->flags |= CHK_MBOX_ACCESS; 1198 1199 rc = bus_generic_attach(dev); 1200 if (rc != 0) { 1201 device_printf(dev, 1202 "failed to attach all child ports: %d\n", rc); 1203 goto done; 1204 } 1205 1206 device_printf(dev, 1207 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1208 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1209 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1210 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1211 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1212 1213 t4_set_desc(sc); 1214 1215 notify_siblings(dev, 0); 1216 1217 done: 1218 if (rc != 0 && sc->cdev) { 1219 /* cdev was created and so cxgbetool works; recover that way. */ 1220 device_printf(dev, 1221 "error during attach, adapter is now in recovery mode.\n"); 1222 rc = 0; 1223 } 1224 1225 if (rc != 0) 1226 t4_detach_common(dev); 1227 else 1228 t4_sysctls(sc); 1229 1230 return (rc); 1231 } 1232 1233 static int 1234 t4_ready(device_t dev) 1235 { 1236 struct adapter *sc; 1237 1238 sc = device_get_softc(dev); 1239 if (sc->flags & FW_OK) 1240 return (0); 1241 return (ENXIO); 1242 } 1243 1244 static int 1245 t4_read_port_device(device_t dev, int port, device_t *child) 1246 { 1247 struct adapter *sc; 1248 struct port_info *pi; 1249 1250 sc = device_get_softc(dev); 1251 if (port < 0 || port >= MAX_NPORTS) 1252 return (EINVAL); 1253 pi = sc->port[port]; 1254 if (pi == NULL || pi->dev == NULL) 1255 return (ENXIO); 1256 *child = pi->dev; 1257 return (0); 1258 } 1259 1260 static int 1261 notify_siblings(device_t dev, int detaching) 1262 { 1263 device_t sibling; 1264 int error, i; 1265 1266 error = 0; 1267 for (i = 0; i < PCI_FUNCMAX; i++) { 1268 if (i == pci_get_function(dev)) 1269 continue; 1270 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1271 pci_get_slot(dev), i); 1272 if (sibling == NULL || !device_is_attached(sibling)) 1273 continue; 1274 if (detaching) 1275 error = T4_DETACH_CHILD(sibling); 1276 else 1277 (void)T4_ATTACH_CHILD(sibling); 1278 if (error) 1279 break; 1280 } 1281 return (error); 1282 } 1283 1284 /* 1285 * Idempotent 1286 */ 1287 static int 1288 t4_detach(device_t dev) 1289 { 1290 struct adapter *sc; 1291 int rc; 1292 1293 sc = device_get_softc(dev); 1294 1295 rc = notify_siblings(dev, 1); 1296 if (rc) { 1297 device_printf(dev, 1298 "failed to detach sibling devices: %d\n", rc); 1299 return (rc); 1300 } 1301 1302 return (t4_detach_common(dev)); 1303 } 1304 1305 int 1306 t4_detach_common(device_t dev) 1307 { 1308 struct adapter *sc; 1309 struct port_info *pi; 1310 int i, rc; 1311 1312 sc = device_get_softc(dev); 1313 1314 if (sc->cdev) { 1315 destroy_dev(sc->cdev); 1316 sc->cdev = NULL; 1317 } 1318 1319 sc->flags &= ~CHK_MBOX_ACCESS; 1320 if (sc->flags & FULL_INIT_DONE) { 1321 if (!(sc->flags & IS_VF)) 1322 t4_intr_disable(sc); 1323 } 1324 1325 if (device_is_attached(dev)) { 1326 rc = bus_generic_detach(dev); 1327 if (rc) { 1328 device_printf(dev, 1329 "failed to detach child devices: %d\n", rc); 1330 return (rc); 1331 } 1332 } 1333 1334 for (i = 0; i < sc->intr_count; i++) 1335 t4_free_irq(sc, &sc->irq[i]); 1336 1337 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1338 t4_free_tx_sched(sc); 1339 1340 for (i = 0; i < MAX_NPORTS; i++) { 1341 pi = sc->port[i]; 1342 if (pi) { 1343 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1344 if (pi->dev) 1345 device_delete_child(dev, pi->dev); 1346 1347 mtx_destroy(&pi->pi_lock); 1348 free(pi->vi, M_CXGBE); 1349 free(pi, M_CXGBE); 1350 } 1351 } 1352 1353 device_delete_children(dev); 1354 1355 if (sc->flags & FULL_INIT_DONE) 1356 adapter_full_uninit(sc); 1357 1358 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1359 t4_fw_bye(sc, sc->mbox); 1360 1361 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1362 pci_release_msi(dev); 1363 1364 if (sc->regs_res) 1365 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1366 sc->regs_res); 1367 1368 if (sc->udbs_res) 1369 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1370 sc->udbs_res); 1371 1372 if (sc->msix_res) 1373 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1374 sc->msix_res); 1375 1376 if (sc->l2t) 1377 t4_free_l2t(sc->l2t); 1378 1379 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1380 free(sc->sge.ofld_txq, M_CXGBE); 1381 #endif 1382 #ifdef TCP_OFFLOAD 1383 free(sc->sge.ofld_rxq, M_CXGBE); 1384 #endif 1385 #ifdef DEV_NETMAP 1386 free(sc->sge.nm_rxq, M_CXGBE); 1387 free(sc->sge.nm_txq, M_CXGBE); 1388 #endif 1389 free(sc->irq, M_CXGBE); 1390 free(sc->sge.rxq, M_CXGBE); 1391 free(sc->sge.txq, M_CXGBE); 1392 free(sc->sge.ctrlq, M_CXGBE); 1393 free(sc->sge.iqmap, M_CXGBE); 1394 free(sc->sge.eqmap, M_CXGBE); 1395 free(sc->tids.ftid_tab, M_CXGBE); 1396 free(sc->tids.hftid_tab, M_CXGBE); 1397 free(sc->tids.atid_tab, M_CXGBE); 1398 free(sc->tids.tid_tab, M_CXGBE); 1399 free(sc->tt.tls_rx_ports, M_CXGBE); 1400 t4_destroy_dma_tag(sc); 1401 if (mtx_initialized(&sc->sc_lock)) { 1402 sx_xlock(&t4_list_lock); 1403 SLIST_REMOVE(&t4_list, sc, adapter, link); 1404 sx_xunlock(&t4_list_lock); 1405 mtx_destroy(&sc->sc_lock); 1406 } 1407 1408 callout_drain(&sc->sfl_callout); 1409 if (mtx_initialized(&sc->tids.ftid_lock)) { 1410 mtx_destroy(&sc->tids.ftid_lock); 1411 cv_destroy(&sc->tids.ftid_cv); 1412 } 1413 if (mtx_initialized(&sc->tids.hftid_lock)) { 1414 mtx_destroy(&sc->tids.hftid_lock); 1415 cv_destroy(&sc->tids.hftid_cv); 1416 } 1417 if (mtx_initialized(&sc->tids.atid_lock)) 1418 mtx_destroy(&sc->tids.atid_lock); 1419 if (mtx_initialized(&sc->sfl_lock)) 1420 mtx_destroy(&sc->sfl_lock); 1421 if (mtx_initialized(&sc->ifp_lock)) 1422 mtx_destroy(&sc->ifp_lock); 1423 if (mtx_initialized(&sc->reg_lock)) 1424 mtx_destroy(&sc->reg_lock); 1425 1426 if (rw_initialized(&sc->policy_lock)) { 1427 rw_destroy(&sc->policy_lock); 1428 #ifdef TCP_OFFLOAD 1429 if (sc->policy != NULL) 1430 free_offload_policy(sc->policy); 1431 #endif 1432 } 1433 1434 for (i = 0; i < NUM_MEMWIN; i++) { 1435 struct memwin *mw = &sc->memwin[i]; 1436 1437 if (rw_initialized(&mw->mw_lock)) 1438 rw_destroy(&mw->mw_lock); 1439 } 1440 1441 bzero(sc, sizeof(*sc)); 1442 1443 return (0); 1444 } 1445 1446 static int 1447 cxgbe_probe(device_t dev) 1448 { 1449 char buf[128]; 1450 struct port_info *pi = device_get_softc(dev); 1451 1452 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1453 device_set_desc_copy(dev, buf); 1454 1455 return (BUS_PROBE_DEFAULT); 1456 } 1457 1458 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1459 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1460 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1461 #define T4_CAP_ENABLE (T4_CAP) 1462 1463 static int 1464 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1465 { 1466 struct ifnet *ifp; 1467 struct sbuf *sb; 1468 1469 vi->xact_addr_filt = -1; 1470 callout_init(&vi->tick, 1); 1471 1472 /* Allocate an ifnet and set it up */ 1473 ifp = if_alloc(IFT_ETHER); 1474 if (ifp == NULL) { 1475 device_printf(dev, "Cannot allocate ifnet\n"); 1476 return (ENOMEM); 1477 } 1478 vi->ifp = ifp; 1479 ifp->if_softc = vi; 1480 1481 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1482 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1483 1484 ifp->if_init = cxgbe_init; 1485 ifp->if_ioctl = cxgbe_ioctl; 1486 ifp->if_transmit = cxgbe_transmit; 1487 ifp->if_qflush = cxgbe_qflush; 1488 ifp->if_get_counter = cxgbe_get_counter; 1489 1490 ifp->if_capabilities = T4_CAP; 1491 #ifdef TCP_OFFLOAD 1492 if (vi->nofldrxq != 0) 1493 ifp->if_capabilities |= IFCAP_TOE; 1494 #endif 1495 #ifdef DEV_NETMAP 1496 if (vi->nnmrxq != 0) 1497 ifp->if_capabilities |= IFCAP_NETMAP; 1498 #endif 1499 ifp->if_capenable = T4_CAP_ENABLE; 1500 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1501 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1502 1503 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1504 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1505 ifp->if_hw_tsomaxsegsize = 65536; 1506 1507 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1508 EVENTHANDLER_PRI_ANY); 1509 1510 ether_ifattach(ifp, vi->hw_addr); 1511 #ifdef DEV_NETMAP 1512 if (ifp->if_capabilities & IFCAP_NETMAP) 1513 cxgbe_nm_attach(vi); 1514 #endif 1515 sb = sbuf_new_auto(); 1516 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1517 #ifdef TCP_OFFLOAD 1518 if (ifp->if_capabilities & IFCAP_TOE) 1519 sbuf_printf(sb, "; %d txq, %d rxq (TOE)", 1520 vi->nofldtxq, vi->nofldrxq); 1521 #endif 1522 #ifdef DEV_NETMAP 1523 if (ifp->if_capabilities & IFCAP_NETMAP) 1524 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1525 vi->nnmtxq, vi->nnmrxq); 1526 #endif 1527 sbuf_finish(sb); 1528 device_printf(dev, "%s\n", sbuf_data(sb)); 1529 sbuf_delete(sb); 1530 1531 vi_sysctls(vi); 1532 1533 return (0); 1534 } 1535 1536 static int 1537 cxgbe_attach(device_t dev) 1538 { 1539 struct port_info *pi = device_get_softc(dev); 1540 struct adapter *sc = pi->adapter; 1541 struct vi_info *vi; 1542 int i, rc; 1543 1544 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1545 1546 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1547 if (rc) 1548 return (rc); 1549 1550 for_each_vi(pi, i, vi) { 1551 if (i == 0) 1552 continue; 1553 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1554 if (vi->dev == NULL) { 1555 device_printf(dev, "failed to add VI %d\n", i); 1556 continue; 1557 } 1558 device_set_softc(vi->dev, vi); 1559 } 1560 1561 cxgbe_sysctls(pi); 1562 1563 bus_generic_attach(dev); 1564 1565 return (0); 1566 } 1567 1568 static void 1569 cxgbe_vi_detach(struct vi_info *vi) 1570 { 1571 struct ifnet *ifp = vi->ifp; 1572 1573 ether_ifdetach(ifp); 1574 1575 if (vi->vlan_c) 1576 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1577 1578 /* Let detach proceed even if these fail. */ 1579 #ifdef DEV_NETMAP 1580 if (ifp->if_capabilities & IFCAP_NETMAP) 1581 cxgbe_nm_detach(vi); 1582 #endif 1583 cxgbe_uninit_synchronized(vi); 1584 callout_drain(&vi->tick); 1585 vi_full_uninit(vi); 1586 1587 if_free(vi->ifp); 1588 vi->ifp = NULL; 1589 } 1590 1591 static int 1592 cxgbe_detach(device_t dev) 1593 { 1594 struct port_info *pi = device_get_softc(dev); 1595 struct adapter *sc = pi->adapter; 1596 int rc; 1597 1598 /* Detach the extra VIs first. */ 1599 rc = bus_generic_detach(dev); 1600 if (rc) 1601 return (rc); 1602 device_delete_children(dev); 1603 1604 doom_vi(sc, &pi->vi[0]); 1605 1606 if (pi->flags & HAS_TRACEQ) { 1607 sc->traceq = -1; /* cloner should not create ifnet */ 1608 t4_tracer_port_detach(sc); 1609 } 1610 1611 cxgbe_vi_detach(&pi->vi[0]); 1612 callout_drain(&pi->tick); 1613 ifmedia_removeall(&pi->media); 1614 1615 end_synchronized_op(sc, 0); 1616 1617 return (0); 1618 } 1619 1620 static void 1621 cxgbe_init(void *arg) 1622 { 1623 struct vi_info *vi = arg; 1624 struct adapter *sc = vi->pi->adapter; 1625 1626 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1627 return; 1628 cxgbe_init_synchronized(vi); 1629 end_synchronized_op(sc, 0); 1630 } 1631 1632 static int 1633 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1634 { 1635 int rc = 0, mtu, flags, can_sleep; 1636 struct vi_info *vi = ifp->if_softc; 1637 struct port_info *pi = vi->pi; 1638 struct adapter *sc = pi->adapter; 1639 struct ifreq *ifr = (struct ifreq *)data; 1640 uint32_t mask; 1641 1642 switch (cmd) { 1643 case SIOCSIFMTU: 1644 mtu = ifr->ifr_mtu; 1645 if (mtu < ETHERMIN || mtu > MAX_MTU) 1646 return (EINVAL); 1647 1648 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1649 if (rc) 1650 return (rc); 1651 ifp->if_mtu = mtu; 1652 if (vi->flags & VI_INIT_DONE) { 1653 t4_update_fl_bufsize(ifp); 1654 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1655 rc = update_mac_settings(ifp, XGMAC_MTU); 1656 } 1657 end_synchronized_op(sc, 0); 1658 break; 1659 1660 case SIOCSIFFLAGS: 1661 can_sleep = 0; 1662 redo_sifflags: 1663 rc = begin_synchronized_op(sc, vi, 1664 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1665 if (rc) { 1666 if_printf(ifp, "%ssleepable synch operation failed: %d." 1667 " if_flags 0x%08x, if_drv_flags 0x%08x\n", 1668 can_sleep ? "" : "non-", rc, ifp->if_flags, 1669 ifp->if_drv_flags); 1670 return (rc); 1671 } 1672 1673 if (ifp->if_flags & IFF_UP) { 1674 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1675 flags = vi->if_flags; 1676 if ((ifp->if_flags ^ flags) & 1677 (IFF_PROMISC | IFF_ALLMULTI)) { 1678 if (can_sleep == 1) { 1679 end_synchronized_op(sc, 0); 1680 can_sleep = 0; 1681 goto redo_sifflags; 1682 } 1683 rc = update_mac_settings(ifp, 1684 XGMAC_PROMISC | XGMAC_ALLMULTI); 1685 } 1686 } else { 1687 if (can_sleep == 0) { 1688 end_synchronized_op(sc, LOCK_HELD); 1689 can_sleep = 1; 1690 goto redo_sifflags; 1691 } 1692 rc = cxgbe_init_synchronized(vi); 1693 } 1694 vi->if_flags = ifp->if_flags; 1695 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1696 if (can_sleep == 0) { 1697 end_synchronized_op(sc, LOCK_HELD); 1698 can_sleep = 1; 1699 goto redo_sifflags; 1700 } 1701 rc = cxgbe_uninit_synchronized(vi); 1702 } 1703 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1704 break; 1705 1706 case SIOCADDMULTI: 1707 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1708 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1709 if (rc) 1710 return (rc); 1711 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1712 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1713 end_synchronized_op(sc, LOCK_HELD); 1714 break; 1715 1716 case SIOCSIFCAP: 1717 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1718 if (rc) 1719 return (rc); 1720 1721 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1722 if (mask & IFCAP_TXCSUM) { 1723 ifp->if_capenable ^= IFCAP_TXCSUM; 1724 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1725 1726 if (IFCAP_TSO4 & ifp->if_capenable && 1727 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1728 ifp->if_capenable &= ~IFCAP_TSO4; 1729 if_printf(ifp, 1730 "tso4 disabled due to -txcsum.\n"); 1731 } 1732 } 1733 if (mask & IFCAP_TXCSUM_IPV6) { 1734 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1735 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1736 1737 if (IFCAP_TSO6 & ifp->if_capenable && 1738 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1739 ifp->if_capenable &= ~IFCAP_TSO6; 1740 if_printf(ifp, 1741 "tso6 disabled due to -txcsum6.\n"); 1742 } 1743 } 1744 if (mask & IFCAP_RXCSUM) 1745 ifp->if_capenable ^= IFCAP_RXCSUM; 1746 if (mask & IFCAP_RXCSUM_IPV6) 1747 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1748 1749 /* 1750 * Note that we leave CSUM_TSO alone (it is always set). The 1751 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1752 * sending a TSO request our way, so it's sufficient to toggle 1753 * IFCAP_TSOx only. 1754 */ 1755 if (mask & IFCAP_TSO4) { 1756 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1757 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1758 if_printf(ifp, "enable txcsum first.\n"); 1759 rc = EAGAIN; 1760 goto fail; 1761 } 1762 ifp->if_capenable ^= IFCAP_TSO4; 1763 } 1764 if (mask & IFCAP_TSO6) { 1765 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1766 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1767 if_printf(ifp, "enable txcsum6 first.\n"); 1768 rc = EAGAIN; 1769 goto fail; 1770 } 1771 ifp->if_capenable ^= IFCAP_TSO6; 1772 } 1773 if (mask & IFCAP_LRO) { 1774 #if defined(INET) || defined(INET6) 1775 int i; 1776 struct sge_rxq *rxq; 1777 1778 ifp->if_capenable ^= IFCAP_LRO; 1779 for_each_rxq(vi, i, rxq) { 1780 if (ifp->if_capenable & IFCAP_LRO) 1781 rxq->iq.flags |= IQ_LRO_ENABLED; 1782 else 1783 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1784 } 1785 #endif 1786 } 1787 #ifdef TCP_OFFLOAD 1788 if (mask & IFCAP_TOE) { 1789 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1790 1791 rc = toe_capability(vi, enable); 1792 if (rc != 0) 1793 goto fail; 1794 1795 ifp->if_capenable ^= mask; 1796 } 1797 #endif 1798 if (mask & IFCAP_VLAN_HWTAGGING) { 1799 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1800 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1801 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1802 } 1803 if (mask & IFCAP_VLAN_MTU) { 1804 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1805 1806 /* Need to find out how to disable auto-mtu-inflation */ 1807 } 1808 if (mask & IFCAP_VLAN_HWTSO) 1809 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1810 if (mask & IFCAP_VLAN_HWCSUM) 1811 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1812 1813 #ifdef VLAN_CAPABILITIES 1814 VLAN_CAPABILITIES(ifp); 1815 #endif 1816 fail: 1817 end_synchronized_op(sc, 0); 1818 break; 1819 1820 case SIOCSIFMEDIA: 1821 case SIOCGIFMEDIA: 1822 case SIOCGIFXMEDIA: 1823 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 1824 break; 1825 1826 case SIOCGI2C: { 1827 struct ifi2creq i2c; 1828 1829 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 1830 if (rc != 0) 1831 break; 1832 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1833 rc = EPERM; 1834 break; 1835 } 1836 if (i2c.len > sizeof(i2c.data)) { 1837 rc = EINVAL; 1838 break; 1839 } 1840 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1841 if (rc) 1842 return (rc); 1843 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 1844 i2c.offset, i2c.len, &i2c.data[0]); 1845 end_synchronized_op(sc, 0); 1846 if (rc == 0) 1847 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 1848 break; 1849 } 1850 1851 default: 1852 rc = ether_ioctl(ifp, cmd, data); 1853 } 1854 1855 return (rc); 1856 } 1857 1858 static int 1859 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1860 { 1861 struct vi_info *vi = ifp->if_softc; 1862 struct port_info *pi = vi->pi; 1863 struct adapter *sc = pi->adapter; 1864 struct sge_txq *txq; 1865 void *items[1]; 1866 int rc; 1867 1868 M_ASSERTPKTHDR(m); 1869 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1870 1871 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1872 m_freem(m); 1873 return (ENETDOWN); 1874 } 1875 1876 rc = parse_pkt(sc, &m); 1877 if (__predict_false(rc != 0)) { 1878 MPASS(m == NULL); /* was freed already */ 1879 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1880 return (rc); 1881 } 1882 1883 /* Select a txq. */ 1884 txq = &sc->sge.txq[vi->first_txq]; 1885 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1886 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1887 vi->rsrv_noflowq); 1888 1889 items[0] = m; 1890 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 1891 if (__predict_false(rc != 0)) 1892 m_freem(m); 1893 1894 return (rc); 1895 } 1896 1897 static void 1898 cxgbe_qflush(struct ifnet *ifp) 1899 { 1900 struct vi_info *vi = ifp->if_softc; 1901 struct sge_txq *txq; 1902 int i; 1903 1904 /* queues do not exist if !VI_INIT_DONE. */ 1905 if (vi->flags & VI_INIT_DONE) { 1906 for_each_txq(vi, i, txq) { 1907 TXQ_LOCK(txq); 1908 txq->eq.flags |= EQ_QFLUSH; 1909 TXQ_UNLOCK(txq); 1910 while (!mp_ring_is_idle(txq->r)) { 1911 mp_ring_check_drainage(txq->r, 0); 1912 pause("qflush", 1); 1913 } 1914 TXQ_LOCK(txq); 1915 txq->eq.flags &= ~EQ_QFLUSH; 1916 TXQ_UNLOCK(txq); 1917 } 1918 } 1919 if_qflush(ifp); 1920 } 1921 1922 static uint64_t 1923 vi_get_counter(struct ifnet *ifp, ift_counter c) 1924 { 1925 struct vi_info *vi = ifp->if_softc; 1926 struct fw_vi_stats_vf *s = &vi->stats; 1927 1928 vi_refresh_stats(vi->pi->adapter, vi); 1929 1930 switch (c) { 1931 case IFCOUNTER_IPACKETS: 1932 return (s->rx_bcast_frames + s->rx_mcast_frames + 1933 s->rx_ucast_frames); 1934 case IFCOUNTER_IERRORS: 1935 return (s->rx_err_frames); 1936 case IFCOUNTER_OPACKETS: 1937 return (s->tx_bcast_frames + s->tx_mcast_frames + 1938 s->tx_ucast_frames + s->tx_offload_frames); 1939 case IFCOUNTER_OERRORS: 1940 return (s->tx_drop_frames); 1941 case IFCOUNTER_IBYTES: 1942 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 1943 s->rx_ucast_bytes); 1944 case IFCOUNTER_OBYTES: 1945 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 1946 s->tx_ucast_bytes + s->tx_offload_bytes); 1947 case IFCOUNTER_IMCASTS: 1948 return (s->rx_mcast_frames); 1949 case IFCOUNTER_OMCASTS: 1950 return (s->tx_mcast_frames); 1951 case IFCOUNTER_OQDROPS: { 1952 uint64_t drops; 1953 1954 drops = 0; 1955 if (vi->flags & VI_INIT_DONE) { 1956 int i; 1957 struct sge_txq *txq; 1958 1959 for_each_txq(vi, i, txq) 1960 drops += counter_u64_fetch(txq->r->drops); 1961 } 1962 1963 return (drops); 1964 1965 } 1966 1967 default: 1968 return (if_get_counter_default(ifp, c)); 1969 } 1970 } 1971 1972 uint64_t 1973 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 1974 { 1975 struct vi_info *vi = ifp->if_softc; 1976 struct port_info *pi = vi->pi; 1977 struct adapter *sc = pi->adapter; 1978 struct port_stats *s = &pi->stats; 1979 1980 if (pi->nvi > 1 || sc->flags & IS_VF) 1981 return (vi_get_counter(ifp, c)); 1982 1983 cxgbe_refresh_stats(sc, pi); 1984 1985 switch (c) { 1986 case IFCOUNTER_IPACKETS: 1987 return (s->rx_frames); 1988 1989 case IFCOUNTER_IERRORS: 1990 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 1991 s->rx_fcs_err + s->rx_len_err); 1992 1993 case IFCOUNTER_OPACKETS: 1994 return (s->tx_frames); 1995 1996 case IFCOUNTER_OERRORS: 1997 return (s->tx_error_frames); 1998 1999 case IFCOUNTER_IBYTES: 2000 return (s->rx_octets); 2001 2002 case IFCOUNTER_OBYTES: 2003 return (s->tx_octets); 2004 2005 case IFCOUNTER_IMCASTS: 2006 return (s->rx_mcast_frames); 2007 2008 case IFCOUNTER_OMCASTS: 2009 return (s->tx_mcast_frames); 2010 2011 case IFCOUNTER_IQDROPS: 2012 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2013 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2014 s->rx_trunc3 + pi->tnl_cong_drops); 2015 2016 case IFCOUNTER_OQDROPS: { 2017 uint64_t drops; 2018 2019 drops = s->tx_drop; 2020 if (vi->flags & VI_INIT_DONE) { 2021 int i; 2022 struct sge_txq *txq; 2023 2024 for_each_txq(vi, i, txq) 2025 drops += counter_u64_fetch(txq->r->drops); 2026 } 2027 2028 return (drops); 2029 2030 } 2031 2032 default: 2033 return (if_get_counter_default(ifp, c)); 2034 } 2035 } 2036 2037 static int 2038 cxgbe_media_change(struct ifnet *ifp) 2039 { 2040 struct vi_info *vi = ifp->if_softc; 2041 2042 device_printf(vi->dev, "%s unimplemented.\n", __func__); 2043 2044 return (EOPNOTSUPP); 2045 } 2046 2047 static void 2048 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2049 { 2050 struct vi_info *vi = ifp->if_softc; 2051 struct port_info *pi = vi->pi; 2052 struct ifmedia_entry *cur; 2053 struct link_config *lc = &pi->link_cfg; 2054 2055 /* 2056 * If all the interfaces are administratively down the firmware does not 2057 * report transceiver changes. Refresh port info here so that ifconfig 2058 * displays accurate information at all times. 2059 */ 2060 if (begin_synchronized_op(pi->adapter, NULL, SLEEP_OK | INTR_OK, 2061 "t4med") == 0) { 2062 PORT_LOCK(pi); 2063 if (pi->up_vis == 0) { 2064 t4_update_port_info(pi); 2065 build_medialist(pi, &pi->media); 2066 } 2067 PORT_UNLOCK(pi); 2068 end_synchronized_op(pi->adapter, 0); 2069 } 2070 2071 ifmr->ifm_status = IFM_AVALID; 2072 if (lc->link_ok == 0) 2073 return; 2074 2075 ifmr->ifm_status |= IFM_ACTIVE; 2076 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2077 if (lc->fc & PAUSE_RX) 2078 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2079 if (lc->fc & PAUSE_TX) 2080 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2081 2082 /* active and current will differ iff current media is autoselect. */ 2083 cur = pi->media.ifm_cur; 2084 if (cur != NULL && IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 2085 return; 2086 2087 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2088 if (lc->fc & PAUSE_RX) 2089 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2090 if (lc->fc & PAUSE_TX) 2091 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2092 switch (lc->speed) { 2093 case 10000: 2094 ifmr->ifm_active |= IFM_10G_T; 2095 break; 2096 case 1000: 2097 ifmr->ifm_active |= IFM_1000_T; 2098 break; 2099 case 100: 2100 ifmr->ifm_active |= IFM_100_TX; 2101 break; 2102 case 10: 2103 ifmr->ifm_active |= IFM_10_T; 2104 break; 2105 default: 2106 device_printf(vi->dev, "link up but speed unknown (%u)\n", 2107 lc->speed); 2108 } 2109 } 2110 2111 static int 2112 vcxgbe_probe(device_t dev) 2113 { 2114 char buf[128]; 2115 struct vi_info *vi = device_get_softc(dev); 2116 2117 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2118 vi - vi->pi->vi); 2119 device_set_desc_copy(dev, buf); 2120 2121 return (BUS_PROBE_DEFAULT); 2122 } 2123 2124 static int 2125 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2126 { 2127 int func, index, rc; 2128 uint32_t param, val; 2129 2130 ASSERT_SYNCHRONIZED_OP(sc); 2131 2132 index = vi - pi->vi; 2133 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2134 KASSERT(index < nitems(vi_mac_funcs), 2135 ("%s: VI %s doesn't have a MAC func", __func__, 2136 device_get_nameunit(vi->dev))); 2137 func = vi_mac_funcs[index]; 2138 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2139 vi->hw_addr, &vi->rss_size, func, 0); 2140 if (rc < 0) { 2141 device_printf(vi->dev, "failed to allocate virtual interface %d" 2142 "for port %d: %d\n", index, pi->port_id, -rc); 2143 return (-rc); 2144 } 2145 vi->viid = rc; 2146 if (chip_id(sc) <= CHELSIO_T5) 2147 vi->smt_idx = (rc & 0x7f) << 1; 2148 else 2149 vi->smt_idx = (rc & 0x7f); 2150 2151 if (vi->rss_size == 1) { 2152 /* 2153 * This VI didn't get a slice of the RSS table. Reduce the 2154 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2155 * configuration file (nvi, rssnvi for this PF) if this is a 2156 * problem. 2157 */ 2158 device_printf(vi->dev, "RSS table not available.\n"); 2159 vi->rss_base = 0xffff; 2160 2161 return (0); 2162 } 2163 2164 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2165 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2166 V_FW_PARAMS_PARAM_YZ(vi->viid); 2167 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2168 if (rc) 2169 vi->rss_base = 0xffff; 2170 else { 2171 MPASS((val >> 16) == vi->rss_size); 2172 vi->rss_base = val & 0xffff; 2173 } 2174 2175 return (0); 2176 } 2177 2178 static int 2179 vcxgbe_attach(device_t dev) 2180 { 2181 struct vi_info *vi; 2182 struct port_info *pi; 2183 struct adapter *sc; 2184 int rc; 2185 2186 vi = device_get_softc(dev); 2187 pi = vi->pi; 2188 sc = pi->adapter; 2189 2190 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2191 if (rc) 2192 return (rc); 2193 rc = alloc_extra_vi(sc, pi, vi); 2194 end_synchronized_op(sc, 0); 2195 if (rc) 2196 return (rc); 2197 2198 rc = cxgbe_vi_attach(dev, vi); 2199 if (rc) { 2200 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2201 return (rc); 2202 } 2203 return (0); 2204 } 2205 2206 static int 2207 vcxgbe_detach(device_t dev) 2208 { 2209 struct vi_info *vi; 2210 struct adapter *sc; 2211 2212 vi = device_get_softc(dev); 2213 sc = vi->pi->adapter; 2214 2215 doom_vi(sc, vi); 2216 2217 cxgbe_vi_detach(vi); 2218 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2219 2220 end_synchronized_op(sc, 0); 2221 2222 return (0); 2223 } 2224 2225 void 2226 t4_fatal_err(struct adapter *sc) 2227 { 2228 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2229 t4_intr_disable(sc); 2230 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2231 device_get_nameunit(sc->dev)); 2232 if (t4_panic_on_fatal_err) 2233 panic("panic requested on fatal error"); 2234 } 2235 2236 void 2237 t4_add_adapter(struct adapter *sc) 2238 { 2239 sx_xlock(&t4_list_lock); 2240 SLIST_INSERT_HEAD(&t4_list, sc, link); 2241 sx_xunlock(&t4_list_lock); 2242 } 2243 2244 int 2245 t4_map_bars_0_and_4(struct adapter *sc) 2246 { 2247 sc->regs_rid = PCIR_BAR(0); 2248 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2249 &sc->regs_rid, RF_ACTIVE); 2250 if (sc->regs_res == NULL) { 2251 device_printf(sc->dev, "cannot map registers.\n"); 2252 return (ENXIO); 2253 } 2254 sc->bt = rman_get_bustag(sc->regs_res); 2255 sc->bh = rman_get_bushandle(sc->regs_res); 2256 sc->mmio_len = rman_get_size(sc->regs_res); 2257 setbit(&sc->doorbells, DOORBELL_KDB); 2258 2259 sc->msix_rid = PCIR_BAR(4); 2260 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2261 &sc->msix_rid, RF_ACTIVE); 2262 if (sc->msix_res == NULL) { 2263 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2264 return (ENXIO); 2265 } 2266 2267 return (0); 2268 } 2269 2270 int 2271 t4_map_bar_2(struct adapter *sc) 2272 { 2273 2274 /* 2275 * T4: only iWARP driver uses the userspace doorbells. There is no need 2276 * to map it if RDMA is disabled. 2277 */ 2278 if (is_t4(sc) && sc->rdmacaps == 0) 2279 return (0); 2280 2281 sc->udbs_rid = PCIR_BAR(2); 2282 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2283 &sc->udbs_rid, RF_ACTIVE); 2284 if (sc->udbs_res == NULL) { 2285 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2286 return (ENXIO); 2287 } 2288 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2289 2290 if (chip_id(sc) >= CHELSIO_T5) { 2291 setbit(&sc->doorbells, DOORBELL_UDB); 2292 #if defined(__i386__) || defined(__amd64__) 2293 if (t5_write_combine) { 2294 int rc, mode; 2295 2296 /* 2297 * Enable write combining on BAR2. This is the 2298 * userspace doorbell BAR and is split into 128B 2299 * (UDBS_SEG_SIZE) doorbell regions, each associated 2300 * with an egress queue. The first 64B has the doorbell 2301 * and the second 64B can be used to submit a tx work 2302 * request with an implicit doorbell. 2303 */ 2304 2305 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2306 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2307 if (rc == 0) { 2308 clrbit(&sc->doorbells, DOORBELL_UDB); 2309 setbit(&sc->doorbells, DOORBELL_WCWR); 2310 setbit(&sc->doorbells, DOORBELL_UDBWC); 2311 } else { 2312 device_printf(sc->dev, 2313 "couldn't enable write combining: %d\n", 2314 rc); 2315 } 2316 2317 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2318 t4_write_reg(sc, A_SGE_STAT_CFG, 2319 V_STATSOURCE_T5(7) | mode); 2320 } 2321 #endif 2322 } 2323 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2324 2325 return (0); 2326 } 2327 2328 struct memwin_init { 2329 uint32_t base; 2330 uint32_t aperture; 2331 }; 2332 2333 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2334 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2335 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2336 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2337 }; 2338 2339 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2340 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2341 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2342 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2343 }; 2344 2345 static void 2346 setup_memwin(struct adapter *sc) 2347 { 2348 const struct memwin_init *mw_init; 2349 struct memwin *mw; 2350 int i; 2351 uint32_t bar0; 2352 2353 if (is_t4(sc)) { 2354 /* 2355 * Read low 32b of bar0 indirectly via the hardware backdoor 2356 * mechanism. Works from within PCI passthrough environments 2357 * too, where rman_get_start() can return a different value. We 2358 * need to program the T4 memory window decoders with the actual 2359 * addresses that will be coming across the PCIe link. 2360 */ 2361 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2362 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2363 2364 mw_init = &t4_memwin[0]; 2365 } else { 2366 /* T5+ use the relative offset inside the PCIe BAR */ 2367 bar0 = 0; 2368 2369 mw_init = &t5_memwin[0]; 2370 } 2371 2372 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2373 rw_init(&mw->mw_lock, "memory window access"); 2374 mw->mw_base = mw_init->base; 2375 mw->mw_aperture = mw_init->aperture; 2376 mw->mw_curpos = 0; 2377 t4_write_reg(sc, 2378 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2379 (mw->mw_base + bar0) | V_BIR(0) | 2380 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2381 rw_wlock(&mw->mw_lock); 2382 position_memwin(sc, i, 0); 2383 rw_wunlock(&mw->mw_lock); 2384 } 2385 2386 /* flush */ 2387 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2388 } 2389 2390 /* 2391 * Positions the memory window at the given address in the card's address space. 2392 * There are some alignment requirements and the actual position may be at an 2393 * address prior to the requested address. mw->mw_curpos always has the actual 2394 * position of the window. 2395 */ 2396 static void 2397 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2398 { 2399 struct memwin *mw; 2400 uint32_t pf; 2401 uint32_t reg; 2402 2403 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2404 mw = &sc->memwin[idx]; 2405 rw_assert(&mw->mw_lock, RA_WLOCKED); 2406 2407 if (is_t4(sc)) { 2408 pf = 0; 2409 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2410 } else { 2411 pf = V_PFNUM(sc->pf); 2412 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2413 } 2414 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2415 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2416 t4_read_reg(sc, reg); /* flush */ 2417 } 2418 2419 int 2420 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2421 int len, int rw) 2422 { 2423 struct memwin *mw; 2424 uint32_t mw_end, v; 2425 2426 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2427 2428 /* Memory can only be accessed in naturally aligned 4 byte units */ 2429 if (addr & 3 || len & 3 || len <= 0) 2430 return (EINVAL); 2431 2432 mw = &sc->memwin[idx]; 2433 while (len > 0) { 2434 rw_rlock(&mw->mw_lock); 2435 mw_end = mw->mw_curpos + mw->mw_aperture; 2436 if (addr >= mw_end || addr < mw->mw_curpos) { 2437 /* Will need to reposition the window */ 2438 if (!rw_try_upgrade(&mw->mw_lock)) { 2439 rw_runlock(&mw->mw_lock); 2440 rw_wlock(&mw->mw_lock); 2441 } 2442 rw_assert(&mw->mw_lock, RA_WLOCKED); 2443 position_memwin(sc, idx, addr); 2444 rw_downgrade(&mw->mw_lock); 2445 mw_end = mw->mw_curpos + mw->mw_aperture; 2446 } 2447 rw_assert(&mw->mw_lock, RA_RLOCKED); 2448 while (addr < mw_end && len > 0) { 2449 if (rw == 0) { 2450 v = t4_read_reg(sc, mw->mw_base + addr - 2451 mw->mw_curpos); 2452 *val++ = le32toh(v); 2453 } else { 2454 v = *val++; 2455 t4_write_reg(sc, mw->mw_base + addr - 2456 mw->mw_curpos, htole32(v)); 2457 } 2458 addr += 4; 2459 len -= 4; 2460 } 2461 rw_runlock(&mw->mw_lock); 2462 } 2463 2464 return (0); 2465 } 2466 2467 int 2468 alloc_atid_tab(struct tid_info *t, int flags) 2469 { 2470 int i; 2471 2472 MPASS(t->natids > 0); 2473 MPASS(t->atid_tab == NULL); 2474 2475 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2476 M_ZERO | flags); 2477 if (t->atid_tab == NULL) 2478 return (ENOMEM); 2479 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2480 t->afree = t->atid_tab; 2481 t->atids_in_use = 0; 2482 for (i = 1; i < t->natids; i++) 2483 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2484 t->atid_tab[t->natids - 1].next = NULL; 2485 2486 return (0); 2487 } 2488 2489 void 2490 free_atid_tab(struct tid_info *t) 2491 { 2492 2493 KASSERT(t->atids_in_use == 0, 2494 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2495 2496 if (mtx_initialized(&t->atid_lock)) 2497 mtx_destroy(&t->atid_lock); 2498 free(t->atid_tab, M_CXGBE); 2499 t->atid_tab = NULL; 2500 } 2501 2502 int 2503 alloc_atid(struct adapter *sc, void *ctx) 2504 { 2505 struct tid_info *t = &sc->tids; 2506 int atid = -1; 2507 2508 mtx_lock(&t->atid_lock); 2509 if (t->afree) { 2510 union aopen_entry *p = t->afree; 2511 2512 atid = p - t->atid_tab; 2513 MPASS(atid <= M_TID_TID); 2514 t->afree = p->next; 2515 p->data = ctx; 2516 t->atids_in_use++; 2517 } 2518 mtx_unlock(&t->atid_lock); 2519 return (atid); 2520 } 2521 2522 void * 2523 lookup_atid(struct adapter *sc, int atid) 2524 { 2525 struct tid_info *t = &sc->tids; 2526 2527 return (t->atid_tab[atid].data); 2528 } 2529 2530 void 2531 free_atid(struct adapter *sc, int atid) 2532 { 2533 struct tid_info *t = &sc->tids; 2534 union aopen_entry *p = &t->atid_tab[atid]; 2535 2536 mtx_lock(&t->atid_lock); 2537 p->next = t->afree; 2538 t->afree = p; 2539 t->atids_in_use--; 2540 mtx_unlock(&t->atid_lock); 2541 } 2542 2543 static void 2544 queue_tid_release(struct adapter *sc, int tid) 2545 { 2546 2547 CXGBE_UNIMPLEMENTED("deferred tid release"); 2548 } 2549 2550 void 2551 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2552 { 2553 struct wrqe *wr; 2554 struct cpl_tid_release *req; 2555 2556 wr = alloc_wrqe(sizeof(*req), ctrlq); 2557 if (wr == NULL) { 2558 queue_tid_release(sc, tid); /* defer */ 2559 return; 2560 } 2561 req = wrtod(wr); 2562 2563 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2564 2565 t4_wrq_tx(sc, wr); 2566 } 2567 2568 static int 2569 t4_range_cmp(const void *a, const void *b) 2570 { 2571 return ((const struct t4_range *)a)->start - 2572 ((const struct t4_range *)b)->start; 2573 } 2574 2575 /* 2576 * Verify that the memory range specified by the addr/len pair is valid within 2577 * the card's address space. 2578 */ 2579 static int 2580 validate_mem_range(struct adapter *sc, uint32_t addr, int len) 2581 { 2582 struct t4_range mem_ranges[4], *r, *next; 2583 uint32_t em, addr_len; 2584 int i, n, remaining; 2585 2586 /* Memory can only be accessed in naturally aligned 4 byte units */ 2587 if (addr & 3 || len & 3 || len <= 0) 2588 return (EINVAL); 2589 2590 /* Enabled memories */ 2591 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2592 2593 r = &mem_ranges[0]; 2594 n = 0; 2595 bzero(r, sizeof(mem_ranges)); 2596 if (em & F_EDRAM0_ENABLE) { 2597 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2598 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2599 if (r->size > 0) { 2600 r->start = G_EDRAM0_BASE(addr_len) << 20; 2601 if (addr >= r->start && 2602 addr + len <= r->start + r->size) 2603 return (0); 2604 r++; 2605 n++; 2606 } 2607 } 2608 if (em & F_EDRAM1_ENABLE) { 2609 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2610 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2611 if (r->size > 0) { 2612 r->start = G_EDRAM1_BASE(addr_len) << 20; 2613 if (addr >= r->start && 2614 addr + len <= r->start + r->size) 2615 return (0); 2616 r++; 2617 n++; 2618 } 2619 } 2620 if (em & F_EXT_MEM_ENABLE) { 2621 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2622 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2623 if (r->size > 0) { 2624 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2625 if (addr >= r->start && 2626 addr + len <= r->start + r->size) 2627 return (0); 2628 r++; 2629 n++; 2630 } 2631 } 2632 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2633 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2634 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2635 if (r->size > 0) { 2636 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2637 if (addr >= r->start && 2638 addr + len <= r->start + r->size) 2639 return (0); 2640 r++; 2641 n++; 2642 } 2643 } 2644 MPASS(n <= nitems(mem_ranges)); 2645 2646 if (n > 1) { 2647 /* Sort and merge the ranges. */ 2648 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2649 2650 /* Start from index 0 and examine the next n - 1 entries. */ 2651 r = &mem_ranges[0]; 2652 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2653 2654 MPASS(r->size > 0); /* r is a valid entry. */ 2655 next = r + 1; 2656 MPASS(next->size > 0); /* and so is the next one. */ 2657 2658 while (r->start + r->size >= next->start) { 2659 /* Merge the next one into the current entry. */ 2660 r->size = max(r->start + r->size, 2661 next->start + next->size) - r->start; 2662 n--; /* One fewer entry in total. */ 2663 if (--remaining == 0) 2664 goto done; /* short circuit */ 2665 next++; 2666 } 2667 if (next != r + 1) { 2668 /* 2669 * Some entries were merged into r and next 2670 * points to the first valid entry that couldn't 2671 * be merged. 2672 */ 2673 MPASS(next->size > 0); /* must be valid */ 2674 memcpy(r + 1, next, remaining * sizeof(*r)); 2675 #ifdef INVARIANTS 2676 /* 2677 * This so that the foo->size assertion in the 2678 * next iteration of the loop do the right 2679 * thing for entries that were pulled up and are 2680 * no longer valid. 2681 */ 2682 MPASS(n < nitems(mem_ranges)); 2683 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2684 sizeof(struct t4_range)); 2685 #endif 2686 } 2687 } 2688 done: 2689 /* Done merging the ranges. */ 2690 MPASS(n > 0); 2691 r = &mem_ranges[0]; 2692 for (i = 0; i < n; i++, r++) { 2693 if (addr >= r->start && 2694 addr + len <= r->start + r->size) 2695 return (0); 2696 } 2697 } 2698 2699 return (EFAULT); 2700 } 2701 2702 static int 2703 fwmtype_to_hwmtype(int mtype) 2704 { 2705 2706 switch (mtype) { 2707 case FW_MEMTYPE_EDC0: 2708 return (MEM_EDC0); 2709 case FW_MEMTYPE_EDC1: 2710 return (MEM_EDC1); 2711 case FW_MEMTYPE_EXTMEM: 2712 return (MEM_MC0); 2713 case FW_MEMTYPE_EXTMEM1: 2714 return (MEM_MC1); 2715 default: 2716 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2717 } 2718 } 2719 2720 /* 2721 * Verify that the memory range specified by the memtype/offset/len pair is 2722 * valid and lies entirely within the memtype specified. The global address of 2723 * the start of the range is returned in addr. 2724 */ 2725 static int 2726 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 2727 uint32_t *addr) 2728 { 2729 uint32_t em, addr_len, maddr; 2730 2731 /* Memory can only be accessed in naturally aligned 4 byte units */ 2732 if (off & 3 || len & 3 || len == 0) 2733 return (EINVAL); 2734 2735 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2736 switch (fwmtype_to_hwmtype(mtype)) { 2737 case MEM_EDC0: 2738 if (!(em & F_EDRAM0_ENABLE)) 2739 return (EINVAL); 2740 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2741 maddr = G_EDRAM0_BASE(addr_len) << 20; 2742 break; 2743 case MEM_EDC1: 2744 if (!(em & F_EDRAM1_ENABLE)) 2745 return (EINVAL); 2746 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2747 maddr = G_EDRAM1_BASE(addr_len) << 20; 2748 break; 2749 case MEM_MC: 2750 if (!(em & F_EXT_MEM_ENABLE)) 2751 return (EINVAL); 2752 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2753 maddr = G_EXT_MEM_BASE(addr_len) << 20; 2754 break; 2755 case MEM_MC1: 2756 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 2757 return (EINVAL); 2758 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2759 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 2760 break; 2761 default: 2762 return (EINVAL); 2763 } 2764 2765 *addr = maddr + off; /* global address */ 2766 return (validate_mem_range(sc, *addr, len)); 2767 } 2768 2769 static int 2770 fixup_devlog_params(struct adapter *sc) 2771 { 2772 struct devlog_params *dparams = &sc->params.devlog; 2773 int rc; 2774 2775 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 2776 dparams->size, &dparams->addr); 2777 2778 return (rc); 2779 } 2780 2781 static void 2782 update_nirq(struct intrs_and_queues *iaq, int nports) 2783 { 2784 int extra = T4_EXTRA_INTR; 2785 2786 iaq->nirq = extra; 2787 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 2788 iaq->nirq += nports * (iaq->num_vis - 1) * 2789 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 2790 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 2791 } 2792 2793 /* 2794 * Adjust requirements to fit the number of interrupts available. 2795 */ 2796 static void 2797 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 2798 int navail) 2799 { 2800 int old_nirq; 2801 const int nports = sc->params.nports; 2802 2803 MPASS(nports > 0); 2804 MPASS(navail > 0); 2805 2806 bzero(iaq, sizeof(*iaq)); 2807 iaq->intr_type = itype; 2808 iaq->num_vis = t4_num_vis; 2809 iaq->ntxq = t4_ntxq; 2810 iaq->ntxq_vi = t4_ntxq_vi; 2811 iaq->nrxq = t4_nrxq; 2812 iaq->nrxq_vi = t4_nrxq_vi; 2813 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2814 if (is_offload(sc) || is_ethoffload(sc)) { 2815 iaq->nofldtxq = t4_nofldtxq; 2816 iaq->nofldtxq_vi = t4_nofldtxq_vi; 2817 } 2818 #endif 2819 #ifdef TCP_OFFLOAD 2820 if (is_offload(sc)) { 2821 iaq->nofldrxq = t4_nofldrxq; 2822 iaq->nofldrxq_vi = t4_nofldrxq_vi; 2823 } 2824 #endif 2825 #ifdef DEV_NETMAP 2826 iaq->nnmtxq_vi = t4_nnmtxq_vi; 2827 iaq->nnmrxq_vi = t4_nnmrxq_vi; 2828 #endif 2829 2830 update_nirq(iaq, nports); 2831 if (iaq->nirq <= navail && 2832 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2833 /* 2834 * This is the normal case -- there are enough interrupts for 2835 * everything. 2836 */ 2837 goto done; 2838 } 2839 2840 /* 2841 * If extra VIs have been configured try reducing their count and see if 2842 * that works. 2843 */ 2844 while (iaq->num_vis > 1) { 2845 iaq->num_vis--; 2846 update_nirq(iaq, nports); 2847 if (iaq->nirq <= navail && 2848 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2849 device_printf(sc->dev, "virtual interfaces per port " 2850 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 2851 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 2852 "itype %d, navail %u, nirq %d.\n", 2853 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 2854 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 2855 itype, navail, iaq->nirq); 2856 goto done; 2857 } 2858 } 2859 2860 /* 2861 * Extra VIs will not be created. Log a message if they were requested. 2862 */ 2863 MPASS(iaq->num_vis == 1); 2864 iaq->ntxq_vi = iaq->nrxq_vi = 0; 2865 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 2866 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 2867 if (iaq->num_vis != t4_num_vis) { 2868 device_printf(sc->dev, "extra virtual interfaces disabled. " 2869 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 2870 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 2871 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 2872 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 2873 } 2874 2875 /* 2876 * Keep reducing the number of NIC rx queues to the next lower power of 2877 * 2 (for even RSS distribution) and halving the TOE rx queues and see 2878 * if that works. 2879 */ 2880 do { 2881 if (iaq->nrxq > 1) { 2882 do { 2883 iaq->nrxq--; 2884 } while (!powerof2(iaq->nrxq)); 2885 } 2886 if (iaq->nofldrxq > 1) 2887 iaq->nofldrxq >>= 1; 2888 2889 old_nirq = iaq->nirq; 2890 update_nirq(iaq, nports); 2891 if (iaq->nirq <= navail && 2892 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2893 device_printf(sc->dev, "running with reduced number of " 2894 "rx queues because of shortage of interrupts. " 2895 "nrxq=%u, nofldrxq=%u. " 2896 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 2897 iaq->nofldrxq, itype, navail, iaq->nirq); 2898 goto done; 2899 } 2900 } while (old_nirq != iaq->nirq); 2901 2902 /* One interrupt for everything. Ugh. */ 2903 device_printf(sc->dev, "running with minimal number of queues. " 2904 "itype %d, navail %u.\n", itype, navail); 2905 iaq->nirq = 1; 2906 MPASS(iaq->nrxq == 1); 2907 iaq->ntxq = 1; 2908 if (iaq->nofldrxq > 1) 2909 iaq->nofldtxq = 1; 2910 done: 2911 MPASS(iaq->num_vis > 0); 2912 if (iaq->num_vis > 1) { 2913 MPASS(iaq->nrxq_vi > 0); 2914 MPASS(iaq->ntxq_vi > 0); 2915 } 2916 MPASS(iaq->nirq > 0); 2917 MPASS(iaq->nrxq > 0); 2918 MPASS(iaq->ntxq > 0); 2919 if (itype == INTR_MSI) { 2920 MPASS(powerof2(iaq->nirq)); 2921 } 2922 } 2923 2924 static int 2925 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 2926 { 2927 int rc, itype, navail, nalloc; 2928 2929 for (itype = INTR_MSIX; itype; itype >>= 1) { 2930 2931 if ((itype & t4_intr_types) == 0) 2932 continue; /* not allowed */ 2933 2934 if (itype == INTR_MSIX) 2935 navail = pci_msix_count(sc->dev); 2936 else if (itype == INTR_MSI) 2937 navail = pci_msi_count(sc->dev); 2938 else 2939 navail = 1; 2940 restart: 2941 if (navail == 0) 2942 continue; 2943 2944 calculate_iaq(sc, iaq, itype, navail); 2945 nalloc = iaq->nirq; 2946 rc = 0; 2947 if (itype == INTR_MSIX) 2948 rc = pci_alloc_msix(sc->dev, &nalloc); 2949 else if (itype == INTR_MSI) 2950 rc = pci_alloc_msi(sc->dev, &nalloc); 2951 2952 if (rc == 0 && nalloc > 0) { 2953 if (nalloc == iaq->nirq) 2954 return (0); 2955 2956 /* 2957 * Didn't get the number requested. Use whatever number 2958 * the kernel is willing to allocate. 2959 */ 2960 device_printf(sc->dev, "fewer vectors than requested, " 2961 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 2962 itype, iaq->nirq, nalloc); 2963 pci_release_msi(sc->dev); 2964 navail = nalloc; 2965 goto restart; 2966 } 2967 2968 device_printf(sc->dev, 2969 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 2970 itype, rc, iaq->nirq, nalloc); 2971 } 2972 2973 device_printf(sc->dev, 2974 "failed to find a usable interrupt type. " 2975 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 2976 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 2977 2978 return (ENXIO); 2979 } 2980 2981 #define FW_VERSION(chip) ( \ 2982 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 2983 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 2984 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 2985 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 2986 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 2987 2988 struct fw_info { 2989 uint8_t chip; 2990 char *kld_name; 2991 char *fw_mod_name; 2992 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 2993 } fw_info[] = { 2994 { 2995 .chip = CHELSIO_T4, 2996 .kld_name = "t4fw_cfg", 2997 .fw_mod_name = "t4fw", 2998 .fw_hdr = { 2999 .chip = FW_HDR_CHIP_T4, 3000 .fw_ver = htobe32_const(FW_VERSION(T4)), 3001 .intfver_nic = FW_INTFVER(T4, NIC), 3002 .intfver_vnic = FW_INTFVER(T4, VNIC), 3003 .intfver_ofld = FW_INTFVER(T4, OFLD), 3004 .intfver_ri = FW_INTFVER(T4, RI), 3005 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3006 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3007 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3008 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3009 }, 3010 }, { 3011 .chip = CHELSIO_T5, 3012 .kld_name = "t5fw_cfg", 3013 .fw_mod_name = "t5fw", 3014 .fw_hdr = { 3015 .chip = FW_HDR_CHIP_T5, 3016 .fw_ver = htobe32_const(FW_VERSION(T5)), 3017 .intfver_nic = FW_INTFVER(T5, NIC), 3018 .intfver_vnic = FW_INTFVER(T5, VNIC), 3019 .intfver_ofld = FW_INTFVER(T5, OFLD), 3020 .intfver_ri = FW_INTFVER(T5, RI), 3021 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3022 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3023 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3024 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3025 }, 3026 }, { 3027 .chip = CHELSIO_T6, 3028 .kld_name = "t6fw_cfg", 3029 .fw_mod_name = "t6fw", 3030 .fw_hdr = { 3031 .chip = FW_HDR_CHIP_T6, 3032 .fw_ver = htobe32_const(FW_VERSION(T6)), 3033 .intfver_nic = FW_INTFVER(T6, NIC), 3034 .intfver_vnic = FW_INTFVER(T6, VNIC), 3035 .intfver_ofld = FW_INTFVER(T6, OFLD), 3036 .intfver_ri = FW_INTFVER(T6, RI), 3037 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3038 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3039 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3040 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3041 }, 3042 } 3043 }; 3044 3045 static struct fw_info * 3046 find_fw_info(int chip) 3047 { 3048 int i; 3049 3050 for (i = 0; i < nitems(fw_info); i++) { 3051 if (fw_info[i].chip == chip) 3052 return (&fw_info[i]); 3053 } 3054 return (NULL); 3055 } 3056 3057 /* 3058 * Is the given firmware API compatible with the one the driver was compiled 3059 * with? 3060 */ 3061 static int 3062 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 3063 { 3064 3065 /* short circuit if it's the exact same firmware version */ 3066 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3067 return (1); 3068 3069 /* 3070 * XXX: Is this too conservative? Perhaps I should limit this to the 3071 * features that are supported in the driver. 3072 */ 3073 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3074 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3075 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3076 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3077 return (1); 3078 #undef SAME_INTF 3079 3080 return (0); 3081 } 3082 3083 /* 3084 * The firmware in the KLD is usable, but should it be installed? This routine 3085 * explains itself in detail if it indicates the KLD firmware should be 3086 * installed. 3087 */ 3088 static int 3089 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 3090 { 3091 const char *reason; 3092 3093 if (!card_fw_usable) { 3094 reason = "incompatible or unusable"; 3095 goto install; 3096 } 3097 3098 if (k > c) { 3099 reason = "older than the version bundled with this driver"; 3100 goto install; 3101 } 3102 3103 if (t4_fw_install == 2 && k != c) { 3104 reason = "different than the version bundled with this driver"; 3105 goto install; 3106 } 3107 3108 return (0); 3109 3110 install: 3111 if (t4_fw_install == 0) { 3112 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3113 "but the driver is prohibited from installing a different " 3114 "firmware on the card.\n", 3115 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3116 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3117 3118 return (0); 3119 } 3120 3121 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3122 "installing firmware %u.%u.%u.%u on card.\n", 3123 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3124 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3125 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3126 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3127 3128 return (1); 3129 } 3130 3131 /* 3132 * Establish contact with the firmware and determine if we are the master driver 3133 * or not, and whether we are responsible for chip initialization. 3134 */ 3135 static int 3136 prep_firmware(struct adapter *sc) 3137 { 3138 const struct firmware *fw = NULL, *default_cfg; 3139 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 3140 enum dev_state state; 3141 struct fw_info *fw_info; 3142 struct fw_hdr *card_fw; /* fw on the card */ 3143 const struct fw_hdr *kld_fw; /* fw in the KLD */ 3144 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 3145 against */ 3146 3147 /* This is the firmware whose headers the driver was compiled against */ 3148 fw_info = find_fw_info(chip_id(sc)); 3149 if (fw_info == NULL) { 3150 device_printf(sc->dev, 3151 "unable to look up firmware information for chip %d.\n", 3152 chip_id(sc)); 3153 return (EINVAL); 3154 } 3155 drv_fw = &fw_info->fw_hdr; 3156 3157 /* 3158 * The firmware KLD contains many modules. The KLD name is also the 3159 * name of the module that contains the default config file. 3160 */ 3161 default_cfg = firmware_get(fw_info->kld_name); 3162 3163 /* This is the firmware in the KLD */ 3164 fw = firmware_get(fw_info->fw_mod_name); 3165 if (fw != NULL) { 3166 kld_fw = (const void *)fw->data; 3167 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 3168 } else { 3169 kld_fw = NULL; 3170 kld_fw_usable = 0; 3171 } 3172 3173 /* Read the header of the firmware on the card */ 3174 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3175 rc = -t4_read_flash(sc, FLASH_FW_START, 3176 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 3177 if (rc == 0) { 3178 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 3179 if (card_fw->fw_ver == be32toh(0xffffffff)) { 3180 uint32_t d = be32toh(kld_fw->fw_ver); 3181 3182 if (!kld_fw_usable) { 3183 device_printf(sc->dev, 3184 "no firmware on the card and no usable " 3185 "firmware bundled with the driver.\n"); 3186 rc = EIO; 3187 goto done; 3188 } else if (t4_fw_install == 0) { 3189 device_printf(sc->dev, 3190 "no firmware on the card and the driver " 3191 "is prohibited from installing new " 3192 "firmware.\n"); 3193 rc = EIO; 3194 goto done; 3195 } 3196 3197 device_printf(sc->dev, "no firmware on the card, " 3198 "installing firmware %d.%d.%d.%d\n", 3199 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3200 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3201 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize); 3202 if (rc < 0) { 3203 rc = -rc; 3204 device_printf(sc->dev, 3205 "firmware install failed: %d.\n", rc); 3206 goto done; 3207 } 3208 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3209 card_fw_usable = 1; 3210 need_fw_reset = 0; 3211 } 3212 } else { 3213 device_printf(sc->dev, 3214 "Unable to read card's firmware header: %d\n", rc); 3215 card_fw_usable = 0; 3216 } 3217 3218 /* Contact firmware. */ 3219 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3220 if (rc < 0 || state == DEV_STATE_ERR) { 3221 rc = -rc; 3222 device_printf(sc->dev, 3223 "failed to connect to the firmware: %d, %d.\n", rc, state); 3224 goto done; 3225 } 3226 pf = rc; 3227 if (pf == sc->mbox) 3228 sc->flags |= MASTER_PF; 3229 else if (state == DEV_STATE_UNINIT) { 3230 /* 3231 * We didn't get to be the master so we definitely won't be 3232 * configuring the chip. It's a bug if someone else hasn't 3233 * configured it already. 3234 */ 3235 device_printf(sc->dev, "couldn't be master(%d), " 3236 "device not already initialized either(%d).\n", rc, state); 3237 rc = EPROTO; 3238 goto done; 3239 } 3240 3241 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 3242 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 3243 /* 3244 * Common case: the firmware on the card is an exact match and 3245 * the KLD is an exact match too, or the KLD is 3246 * absent/incompatible. Note that t4_fw_install = 2 is ignored 3247 * here -- use cxgbetool loadfw if you want to reinstall the 3248 * same firmware as the one on the card. 3249 */ 3250 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 3251 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 3252 be32toh(card_fw->fw_ver))) { 3253 3254 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3255 if (rc != 0) { 3256 device_printf(sc->dev, 3257 "failed to install firmware: %d\n", rc); 3258 goto done; 3259 } 3260 3261 /* Installed successfully, update the cached header too. */ 3262 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3263 card_fw_usable = 1; 3264 need_fw_reset = 0; /* already reset as part of load_fw */ 3265 } 3266 3267 if (!card_fw_usable) { 3268 uint32_t d, c, k; 3269 3270 d = ntohl(drv_fw->fw_ver); 3271 c = ntohl(card_fw->fw_ver); 3272 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3273 3274 device_printf(sc->dev, "Cannot find a usable firmware: " 3275 "fw_install %d, chip state %d, " 3276 "driver compiled with %d.%d.%d.%d, " 3277 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3278 t4_fw_install, state, 3279 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3280 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3281 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3282 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3283 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3284 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3285 rc = EINVAL; 3286 goto done; 3287 } 3288 3289 /* Reset device */ 3290 if (need_fw_reset && 3291 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3292 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3293 if (rc != ETIMEDOUT && rc != EIO) 3294 t4_fw_bye(sc, sc->mbox); 3295 goto done; 3296 } 3297 sc->flags |= FW_OK; 3298 3299 rc = get_params__pre_init(sc); 3300 if (rc != 0) 3301 goto done; /* error message displayed already */ 3302 3303 /* Partition adapter resources as specified in the config file. */ 3304 if (state == DEV_STATE_UNINIT) { 3305 3306 KASSERT(sc->flags & MASTER_PF, 3307 ("%s: trying to change chip settings when not master.", 3308 __func__)); 3309 3310 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3311 if (rc != 0) 3312 goto done; /* error message displayed already */ 3313 3314 t4_tweak_chip_settings(sc); 3315 3316 /* get basic stuff going */ 3317 rc = -t4_fw_initialize(sc, sc->mbox); 3318 if (rc != 0) { 3319 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3320 goto done; 3321 } 3322 } else { 3323 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3324 sc->cfcsum = 0; 3325 } 3326 3327 done: 3328 free(card_fw, M_CXGBE); 3329 if (fw != NULL) 3330 firmware_put(fw, FIRMWARE_UNLOAD); 3331 if (default_cfg != NULL) 3332 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3333 3334 return (rc); 3335 } 3336 3337 #define FW_PARAM_DEV(param) \ 3338 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3339 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3340 #define FW_PARAM_PFVF(param) \ 3341 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3342 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3343 3344 /* 3345 * Partition chip resources for use between various PFs, VFs, etc. 3346 */ 3347 static int 3348 partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3349 const char *name_prefix) 3350 { 3351 const struct firmware *cfg = NULL; 3352 int rc = 0; 3353 struct fw_caps_config_cmd caps; 3354 uint32_t mtype, moff, finicsum, cfcsum; 3355 3356 /* 3357 * Figure out what configuration file to use. Pick the default config 3358 * file for the card if the user hasn't specified one explicitly. 3359 */ 3360 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3361 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3362 /* Card specific overrides go here. */ 3363 if (pci_get_device(sc->dev) == 0x440a) 3364 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3365 if (is_fpga(sc)) 3366 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3367 } else if (strncmp(t4_cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) 3368 goto use_built_in_config; /* go straight to config. */ 3369 3370 /* 3371 * We need to load another module if the profile is anything except 3372 * "default" or "flash". 3373 */ 3374 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3375 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3376 char s[32]; 3377 3378 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3379 cfg = firmware_get(s); 3380 if (cfg == NULL) { 3381 if (default_cfg != NULL) { 3382 device_printf(sc->dev, 3383 "unable to load module \"%s\" for " 3384 "configuration profile \"%s\", will use " 3385 "the default config file instead.\n", 3386 s, sc->cfg_file); 3387 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3388 "%s", DEFAULT_CF); 3389 } else { 3390 device_printf(sc->dev, 3391 "unable to load module \"%s\" for " 3392 "configuration profile \"%s\", will use " 3393 "the config file on the card's flash " 3394 "instead.\n", s, sc->cfg_file); 3395 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3396 "%s", FLASH_CF); 3397 } 3398 } 3399 } 3400 3401 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3402 default_cfg == NULL) { 3403 device_printf(sc->dev, 3404 "default config file not available, will use the config " 3405 "file on the card's flash instead.\n"); 3406 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3407 } 3408 3409 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3410 u_int cflen; 3411 const uint32_t *cfdata; 3412 uint32_t param, val, addr; 3413 3414 KASSERT(cfg != NULL || default_cfg != NULL, 3415 ("%s: no config to upload", __func__)); 3416 3417 /* 3418 * Ask the firmware where it wants us to upload the config file. 3419 */ 3420 param = FW_PARAM_DEV(CF); 3421 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3422 if (rc != 0) { 3423 /* No support for config file? Shouldn't happen. */ 3424 device_printf(sc->dev, 3425 "failed to query config file location: %d.\n", rc); 3426 goto done; 3427 } 3428 mtype = G_FW_PARAMS_PARAM_Y(val); 3429 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3430 3431 /* 3432 * XXX: sheer laziness. We deliberately added 4 bytes of 3433 * useless stuffing/comments at the end of the config file so 3434 * it's ok to simply throw away the last remaining bytes when 3435 * the config file is not an exact multiple of 4. This also 3436 * helps with the validate_mt_off_len check. 3437 */ 3438 if (cfg != NULL) { 3439 cflen = cfg->datasize & ~3; 3440 cfdata = cfg->data; 3441 } else { 3442 cflen = default_cfg->datasize & ~3; 3443 cfdata = default_cfg->data; 3444 } 3445 3446 if (cflen > FLASH_CFG_MAX_SIZE) { 3447 device_printf(sc->dev, 3448 "config file too long (%d, max allowed is %d). " 3449 "Will try to use the config on the card, if any.\n", 3450 cflen, FLASH_CFG_MAX_SIZE); 3451 goto use_config_on_flash; 3452 } 3453 3454 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3455 if (rc != 0) { 3456 device_printf(sc->dev, 3457 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3458 "Will try to use the config on the card, if any.\n", 3459 __func__, mtype, moff, cflen, rc); 3460 goto use_config_on_flash; 3461 } 3462 write_via_memwin(sc, 2, addr, cfdata, cflen); 3463 } else { 3464 use_config_on_flash: 3465 mtype = FW_MEMTYPE_FLASH; 3466 moff = t4_flash_cfg_addr(sc); 3467 } 3468 3469 bzero(&caps, sizeof(caps)); 3470 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3471 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3472 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3473 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3474 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3475 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3476 if (rc != 0) { 3477 device_printf(sc->dev, 3478 "failed to pre-process config file: %d " 3479 "(mtype %d, moff 0x%x). Will reset the firmware and retry " 3480 "with the built-in configuration.\n", rc, mtype, moff); 3481 3482 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3483 if (rc != 0) { 3484 device_printf(sc->dev, 3485 "firmware reset failed: %d.\n", rc); 3486 if (rc != ETIMEDOUT && rc != EIO) { 3487 t4_fw_bye(sc, sc->mbox); 3488 sc->flags &= ~FW_OK; 3489 } 3490 goto done; 3491 } 3492 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "built-in"); 3493 use_built_in_config: 3494 bzero(&caps, sizeof(caps)); 3495 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3496 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3497 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3498 rc = t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3499 if (rc != 0) { 3500 device_printf(sc->dev, 3501 "built-in configuration failed: %d.\n", rc); 3502 goto done; 3503 } 3504 } 3505 3506 finicsum = be32toh(caps.finicsum); 3507 cfcsum = be32toh(caps.cfcsum); 3508 if (finicsum != cfcsum) { 3509 device_printf(sc->dev, 3510 "WARNING: config file checksum mismatch: %08x %08x\n", 3511 finicsum, cfcsum); 3512 } 3513 sc->cfcsum = cfcsum; 3514 3515 #define LIMIT_CAPS(x) do { \ 3516 caps.x &= htobe16(t4_##x##_allowed); \ 3517 } while (0) 3518 3519 /* 3520 * Let the firmware know what features will (not) be used so it can tune 3521 * things accordingly. 3522 */ 3523 LIMIT_CAPS(nbmcaps); 3524 LIMIT_CAPS(linkcaps); 3525 LIMIT_CAPS(switchcaps); 3526 LIMIT_CAPS(niccaps); 3527 LIMIT_CAPS(toecaps); 3528 LIMIT_CAPS(rdmacaps); 3529 LIMIT_CAPS(cryptocaps); 3530 LIMIT_CAPS(iscsicaps); 3531 LIMIT_CAPS(fcoecaps); 3532 #undef LIMIT_CAPS 3533 3534 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3535 /* 3536 * TOE and hashfilters are mutually exclusive. It is a config 3537 * file or firmware bug if both are reported as available. Try 3538 * to cope with the situation in non-debug builds by disabling 3539 * TOE. 3540 */ 3541 MPASS(caps.toecaps == 0); 3542 3543 caps.toecaps = 0; 3544 caps.rdmacaps = 0; 3545 caps.iscsicaps = 0; 3546 } 3547 3548 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3549 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3550 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3551 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3552 if (rc != 0) { 3553 device_printf(sc->dev, 3554 "failed to process config file: %d.\n", rc); 3555 } 3556 done: 3557 if (cfg != NULL) 3558 firmware_put(cfg, FIRMWARE_UNLOAD); 3559 return (rc); 3560 } 3561 3562 /* 3563 * Retrieve parameters that are needed (or nice to have) very early. 3564 */ 3565 static int 3566 get_params__pre_init(struct adapter *sc) 3567 { 3568 int rc; 3569 uint32_t param[2], val[2]; 3570 3571 t4_get_version_info(sc); 3572 3573 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3574 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3575 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3576 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3577 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3578 3579 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3580 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3581 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3582 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3583 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3584 3585 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3586 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3587 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3588 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3589 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3590 3591 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3592 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3593 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3594 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3595 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3596 3597 param[0] = FW_PARAM_DEV(PORTVEC); 3598 param[1] = FW_PARAM_DEV(CCLK); 3599 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3600 if (rc != 0) { 3601 device_printf(sc->dev, 3602 "failed to query parameters (pre_init): %d.\n", rc); 3603 return (rc); 3604 } 3605 3606 sc->params.portvec = val[0]; 3607 sc->params.nports = bitcount32(val[0]); 3608 sc->params.vpd.cclk = val[1]; 3609 3610 /* Read device log parameters. */ 3611 rc = -t4_init_devlog_params(sc, 1); 3612 if (rc == 0) 3613 fixup_devlog_params(sc); 3614 else { 3615 device_printf(sc->dev, 3616 "failed to get devlog parameters: %d.\n", rc); 3617 rc = 0; /* devlog isn't critical for device operation */ 3618 } 3619 3620 return (rc); 3621 } 3622 3623 /* 3624 * Retrieve various parameters that are of interest to the driver. The device 3625 * has been initialized by the firmware at this point. 3626 */ 3627 static int 3628 get_params__post_init(struct adapter *sc) 3629 { 3630 int rc; 3631 uint32_t param[7], val[7]; 3632 struct fw_caps_config_cmd caps; 3633 3634 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3635 param[1] = FW_PARAM_PFVF(EQ_START); 3636 param[2] = FW_PARAM_PFVF(FILTER_START); 3637 param[3] = FW_PARAM_PFVF(FILTER_END); 3638 param[4] = FW_PARAM_PFVF(L2T_START); 3639 param[5] = FW_PARAM_PFVF(L2T_END); 3640 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3641 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 3642 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 3643 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 3644 if (rc != 0) { 3645 device_printf(sc->dev, 3646 "failed to query parameters (post_init): %d.\n", rc); 3647 return (rc); 3648 } 3649 3650 sc->sge.iq_start = val[0]; 3651 sc->sge.eq_start = val[1]; 3652 sc->tids.ftid_base = val[2]; 3653 sc->tids.nftids = val[3] - val[2] + 1; 3654 sc->params.ftid_min = val[2]; 3655 sc->params.ftid_max = val[3]; 3656 sc->vres.l2t.start = val[4]; 3657 sc->vres.l2t.size = val[5] - val[4] + 1; 3658 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3659 ("%s: L2 table size (%u) larger than expected (%u)", 3660 __func__, sc->vres.l2t.size, L2T_SIZE)); 3661 sc->params.core_vdd = val[6]; 3662 3663 /* 3664 * MPSBGMAP is queried separately because only recent firmwares support 3665 * it as a parameter and we don't want the compound query above to fail 3666 * on older firmwares. 3667 */ 3668 param[0] = FW_PARAM_DEV(MPSBGMAP); 3669 val[0] = 0; 3670 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3671 if (rc == 0) 3672 sc->params.mps_bg_map = val[0]; 3673 else 3674 sc->params.mps_bg_map = 0; 3675 3676 /* 3677 * Determine whether the firmware supports the filter2 work request. 3678 * This is queried separately for the same reason as MPSBGMAP above. 3679 */ 3680 param[0] = FW_PARAM_DEV(FILTER2_WR); 3681 val[0] = 0; 3682 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3683 if (rc == 0) 3684 sc->params.filter2_wr_support = val[0] != 0; 3685 else 3686 sc->params.filter2_wr_support = 0; 3687 3688 /* get capabilites */ 3689 bzero(&caps, sizeof(caps)); 3690 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3691 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3692 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3693 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3694 if (rc != 0) { 3695 device_printf(sc->dev, 3696 "failed to get card capabilities: %d.\n", rc); 3697 return (rc); 3698 } 3699 3700 #define READ_CAPS(x) do { \ 3701 sc->x = htobe16(caps.x); \ 3702 } while (0) 3703 READ_CAPS(nbmcaps); 3704 READ_CAPS(linkcaps); 3705 READ_CAPS(switchcaps); 3706 READ_CAPS(niccaps); 3707 READ_CAPS(toecaps); 3708 READ_CAPS(rdmacaps); 3709 READ_CAPS(cryptocaps); 3710 READ_CAPS(iscsicaps); 3711 READ_CAPS(fcoecaps); 3712 3713 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 3714 MPASS(chip_id(sc) > CHELSIO_T4); 3715 MPASS(sc->toecaps == 0); 3716 sc->toecaps = 0; 3717 3718 param[0] = FW_PARAM_DEV(NTID); 3719 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3720 if (rc != 0) { 3721 device_printf(sc->dev, 3722 "failed to query HASHFILTER parameters: %d.\n", rc); 3723 return (rc); 3724 } 3725 sc->tids.ntids = val[0]; 3726 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3727 sc->params.hash_filter = 1; 3728 } 3729 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 3730 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 3731 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 3732 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3733 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 3734 if (rc != 0) { 3735 device_printf(sc->dev, 3736 "failed to query NIC parameters: %d.\n", rc); 3737 return (rc); 3738 } 3739 sc->tids.etid_base = val[0]; 3740 sc->params.etid_min = val[0]; 3741 sc->tids.netids = val[1] - val[0] + 1; 3742 sc->params.netids = sc->tids.netids; 3743 sc->params.eo_wr_cred = val[2]; 3744 sc->params.ethoffload = 1; 3745 } 3746 if (sc->toecaps) { 3747 /* query offload-related parameters */ 3748 param[0] = FW_PARAM_DEV(NTID); 3749 param[1] = FW_PARAM_PFVF(SERVER_START); 3750 param[2] = FW_PARAM_PFVF(SERVER_END); 3751 param[3] = FW_PARAM_PFVF(TDDP_START); 3752 param[4] = FW_PARAM_PFVF(TDDP_END); 3753 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3754 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3755 if (rc != 0) { 3756 device_printf(sc->dev, 3757 "failed to query TOE parameters: %d.\n", rc); 3758 return (rc); 3759 } 3760 sc->tids.ntids = val[0]; 3761 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3762 sc->tids.stid_base = val[1]; 3763 sc->tids.nstids = val[2] - val[1] + 1; 3764 sc->vres.ddp.start = val[3]; 3765 sc->vres.ddp.size = val[4] - val[3] + 1; 3766 sc->params.ofldq_wr_cred = val[5]; 3767 sc->params.offload = 1; 3768 } else { 3769 /* 3770 * The firmware attempts memfree TOE configuration for -SO cards 3771 * and will report toecaps=0 if it runs out of resources (this 3772 * depends on the config file). It may not report 0 for other 3773 * capabilities dependent on the TOE in this case. Set them to 3774 * 0 here so that the driver doesn't bother tracking resources 3775 * that will never be used. 3776 */ 3777 sc->iscsicaps = 0; 3778 sc->rdmacaps = 0; 3779 } 3780 if (sc->rdmacaps) { 3781 param[0] = FW_PARAM_PFVF(STAG_START); 3782 param[1] = FW_PARAM_PFVF(STAG_END); 3783 param[2] = FW_PARAM_PFVF(RQ_START); 3784 param[3] = FW_PARAM_PFVF(RQ_END); 3785 param[4] = FW_PARAM_PFVF(PBL_START); 3786 param[5] = FW_PARAM_PFVF(PBL_END); 3787 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3788 if (rc != 0) { 3789 device_printf(sc->dev, 3790 "failed to query RDMA parameters(1): %d.\n", rc); 3791 return (rc); 3792 } 3793 sc->vres.stag.start = val[0]; 3794 sc->vres.stag.size = val[1] - val[0] + 1; 3795 sc->vres.rq.start = val[2]; 3796 sc->vres.rq.size = val[3] - val[2] + 1; 3797 sc->vres.pbl.start = val[4]; 3798 sc->vres.pbl.size = val[5] - val[4] + 1; 3799 3800 param[0] = FW_PARAM_PFVF(SQRQ_START); 3801 param[1] = FW_PARAM_PFVF(SQRQ_END); 3802 param[2] = FW_PARAM_PFVF(CQ_START); 3803 param[3] = FW_PARAM_PFVF(CQ_END); 3804 param[4] = FW_PARAM_PFVF(OCQ_START); 3805 param[5] = FW_PARAM_PFVF(OCQ_END); 3806 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3807 if (rc != 0) { 3808 device_printf(sc->dev, 3809 "failed to query RDMA parameters(2): %d.\n", rc); 3810 return (rc); 3811 } 3812 sc->vres.qp.start = val[0]; 3813 sc->vres.qp.size = val[1] - val[0] + 1; 3814 sc->vres.cq.start = val[2]; 3815 sc->vres.cq.size = val[3] - val[2] + 1; 3816 sc->vres.ocq.start = val[4]; 3817 sc->vres.ocq.size = val[5] - val[4] + 1; 3818 3819 param[0] = FW_PARAM_PFVF(SRQ_START); 3820 param[1] = FW_PARAM_PFVF(SRQ_END); 3821 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 3822 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 3823 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 3824 if (rc != 0) { 3825 device_printf(sc->dev, 3826 "failed to query RDMA parameters(3): %d.\n", rc); 3827 return (rc); 3828 } 3829 sc->vres.srq.start = val[0]; 3830 sc->vres.srq.size = val[1] - val[0] + 1; 3831 sc->params.max_ordird_qp = val[2]; 3832 sc->params.max_ird_adapter = val[3]; 3833 } 3834 if (sc->iscsicaps) { 3835 param[0] = FW_PARAM_PFVF(ISCSI_START); 3836 param[1] = FW_PARAM_PFVF(ISCSI_END); 3837 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3838 if (rc != 0) { 3839 device_printf(sc->dev, 3840 "failed to query iSCSI parameters: %d.\n", rc); 3841 return (rc); 3842 } 3843 sc->vres.iscsi.start = val[0]; 3844 sc->vres.iscsi.size = val[1] - val[0] + 1; 3845 } 3846 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 3847 param[0] = FW_PARAM_PFVF(TLS_START); 3848 param[1] = FW_PARAM_PFVF(TLS_END); 3849 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3850 if (rc != 0) { 3851 device_printf(sc->dev, 3852 "failed to query TLS parameters: %d.\n", rc); 3853 return (rc); 3854 } 3855 sc->vres.key.start = val[0]; 3856 sc->vres.key.size = val[1] - val[0] + 1; 3857 } 3858 3859 t4_init_sge_params(sc); 3860 3861 /* 3862 * We've got the params we wanted to query via the firmware. Now grab 3863 * some others directly from the chip. 3864 */ 3865 rc = t4_read_chip_settings(sc); 3866 3867 return (rc); 3868 } 3869 3870 static int 3871 set_params__post_init(struct adapter *sc) 3872 { 3873 uint32_t param, val; 3874 #ifdef TCP_OFFLOAD 3875 int i, v, shift; 3876 #endif 3877 3878 /* ask for encapsulated CPLs */ 3879 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3880 val = 1; 3881 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3882 3883 #ifdef TCP_OFFLOAD 3884 /* 3885 * Override the TOE timers with user provided tunables. This is not the 3886 * recommended way to change the timers (the firmware config file is) so 3887 * these tunables are not documented. 3888 * 3889 * All the timer tunables are in microseconds. 3890 */ 3891 if (t4_toe_keepalive_idle != 0) { 3892 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 3893 v &= M_KEEPALIVEIDLE; 3894 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 3895 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 3896 } 3897 if (t4_toe_keepalive_interval != 0) { 3898 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 3899 v &= M_KEEPALIVEINTVL; 3900 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 3901 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 3902 } 3903 if (t4_toe_keepalive_count != 0) { 3904 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 3905 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 3906 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 3907 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 3908 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 3909 } 3910 if (t4_toe_rexmt_min != 0) { 3911 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 3912 v &= M_RXTMIN; 3913 t4_set_reg_field(sc, A_TP_RXT_MIN, 3914 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 3915 } 3916 if (t4_toe_rexmt_max != 0) { 3917 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 3918 v &= M_RXTMAX; 3919 t4_set_reg_field(sc, A_TP_RXT_MAX, 3920 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 3921 } 3922 if (t4_toe_rexmt_count != 0) { 3923 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 3924 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 3925 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 3926 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 3927 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 3928 } 3929 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 3930 if (t4_toe_rexmt_backoff[i] != -1) { 3931 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 3932 shift = (i & 3) << 3; 3933 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 3934 M_TIMERBACKOFFINDEX0 << shift, v << shift); 3935 } 3936 } 3937 #endif 3938 return (0); 3939 } 3940 3941 #undef FW_PARAM_PFVF 3942 #undef FW_PARAM_DEV 3943 3944 static void 3945 t4_set_desc(struct adapter *sc) 3946 { 3947 char buf[128]; 3948 struct adapter_params *p = &sc->params; 3949 3950 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 3951 3952 device_set_desc_copy(sc->dev, buf); 3953 } 3954 3955 static void 3956 build_medialist(struct port_info *pi, struct ifmedia *media) 3957 { 3958 int m; 3959 3960 PORT_LOCK_ASSERT_OWNED(pi); 3961 3962 ifmedia_removeall(media); 3963 3964 /* 3965 * XXX: Would it be better to ifmedia_add all 4 combinations of pause 3966 * settings for every speed instead of just txpause|rxpause? ifconfig 3967 * media display looks much better if autoselect is the only case where 3968 * ifm_current is different from ifm_active. If the user picks anything 3969 * except txpause|rxpause the display is ugly. 3970 */ 3971 m = IFM_ETHER | IFM_FDX | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 3972 3973 switch(pi->port_type) { 3974 case FW_PORT_TYPE_BT_XFI: 3975 case FW_PORT_TYPE_BT_XAUI: 3976 ifmedia_add(media, m | IFM_10G_T, 0, NULL); 3977 /* fall through */ 3978 3979 case FW_PORT_TYPE_BT_SGMII: 3980 ifmedia_add(media, m | IFM_1000_T, 0, NULL); 3981 ifmedia_add(media, m | IFM_100_TX, 0, NULL); 3982 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL); 3983 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 3984 break; 3985 3986 case FW_PORT_TYPE_CX4: 3987 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL); 3988 ifmedia_set(media, m | IFM_10G_CX4); 3989 break; 3990 3991 case FW_PORT_TYPE_QSFP_10G: 3992 case FW_PORT_TYPE_SFP: 3993 case FW_PORT_TYPE_FIBER_XFI: 3994 case FW_PORT_TYPE_FIBER_XAUI: 3995 switch (pi->mod_type) { 3996 3997 case FW_PORT_MOD_TYPE_LR: 3998 ifmedia_add(media, m | IFM_10G_LR, 0, NULL); 3999 ifmedia_set(media, m | IFM_10G_LR); 4000 break; 4001 4002 case FW_PORT_MOD_TYPE_SR: 4003 ifmedia_add(media, m | IFM_10G_SR, 0, NULL); 4004 ifmedia_set(media, m | IFM_10G_SR); 4005 break; 4006 4007 case FW_PORT_MOD_TYPE_LRM: 4008 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL); 4009 ifmedia_set(media, m | IFM_10G_LRM); 4010 break; 4011 4012 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 4013 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 4014 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL); 4015 ifmedia_set(media, m | IFM_10G_TWINAX); 4016 break; 4017 4018 case FW_PORT_MOD_TYPE_NONE: 4019 m &= ~IFM_FDX; 4020 ifmedia_add(media, m | IFM_NONE, 0, NULL); 4021 ifmedia_set(media, m | IFM_NONE); 4022 break; 4023 4024 case FW_PORT_MOD_TYPE_NA: 4025 case FW_PORT_MOD_TYPE_ER: 4026 default: 4027 device_printf(pi->dev, 4028 "unknown port_type (%d), mod_type (%d)\n", 4029 pi->port_type, pi->mod_type); 4030 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4031 ifmedia_set(media, m | IFM_UNKNOWN); 4032 break; 4033 } 4034 break; 4035 4036 case FW_PORT_TYPE_CR_QSFP: 4037 case FW_PORT_TYPE_SFP28: 4038 case FW_PORT_TYPE_KR_SFP28: 4039 switch (pi->mod_type) { 4040 4041 case FW_PORT_MOD_TYPE_SR: 4042 ifmedia_add(media, m | IFM_25G_SR, 0, NULL); 4043 ifmedia_set(media, m | IFM_25G_SR); 4044 break; 4045 4046 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 4047 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 4048 ifmedia_add(media, m | IFM_25G_CR, 0, NULL); 4049 ifmedia_set(media, m | IFM_25G_CR); 4050 break; 4051 4052 case FW_PORT_MOD_TYPE_NONE: 4053 m &= ~IFM_FDX; 4054 ifmedia_add(media, m | IFM_NONE, 0, NULL); 4055 ifmedia_set(media, m | IFM_NONE); 4056 break; 4057 4058 default: 4059 device_printf(pi->dev, 4060 "unknown port_type (%d), mod_type (%d)\n", 4061 pi->port_type, pi->mod_type); 4062 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4063 ifmedia_set(media, m | IFM_UNKNOWN); 4064 break; 4065 } 4066 break; 4067 4068 case FW_PORT_TYPE_QSFP: 4069 switch (pi->mod_type) { 4070 4071 case FW_PORT_MOD_TYPE_LR: 4072 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL); 4073 ifmedia_set(media, m | IFM_40G_LR4); 4074 break; 4075 4076 case FW_PORT_MOD_TYPE_SR: 4077 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL); 4078 ifmedia_set(media, m | IFM_40G_SR4); 4079 break; 4080 4081 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 4082 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 4083 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL); 4084 ifmedia_set(media, m | IFM_40G_CR4); 4085 break; 4086 4087 case FW_PORT_MOD_TYPE_NONE: 4088 m &= ~IFM_FDX; 4089 ifmedia_add(media, m | IFM_NONE, 0, NULL); 4090 ifmedia_set(media, m | IFM_NONE); 4091 break; 4092 4093 default: 4094 device_printf(pi->dev, 4095 "unknown port_type (%d), mod_type (%d)\n", 4096 pi->port_type, pi->mod_type); 4097 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4098 ifmedia_set(media, m | IFM_UNKNOWN); 4099 break; 4100 } 4101 break; 4102 4103 case FW_PORT_TYPE_KR4_100G: 4104 case FW_PORT_TYPE_CR4_QSFP: 4105 switch (pi->mod_type) { 4106 4107 case FW_PORT_MOD_TYPE_LR: 4108 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL); 4109 ifmedia_set(media, m | IFM_100G_LR4); 4110 break; 4111 4112 case FW_PORT_MOD_TYPE_SR: 4113 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL); 4114 ifmedia_set(media, m | IFM_100G_SR4); 4115 break; 4116 4117 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 4118 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 4119 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL); 4120 ifmedia_set(media, m | IFM_100G_CR4); 4121 break; 4122 4123 case FW_PORT_MOD_TYPE_NONE: 4124 m &= ~IFM_FDX; 4125 ifmedia_add(media, m | IFM_NONE, 0, NULL); 4126 ifmedia_set(media, m | IFM_NONE); 4127 break; 4128 4129 default: 4130 device_printf(pi->dev, 4131 "unknown port_type (%d), mod_type (%d)\n", 4132 pi->port_type, pi->mod_type); 4133 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4134 ifmedia_set(media, m | IFM_UNKNOWN); 4135 break; 4136 } 4137 break; 4138 4139 default: 4140 device_printf(pi->dev, 4141 "unknown port_type (%d), mod_type (%d)\n", pi->port_type, 4142 pi->mod_type); 4143 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 4144 ifmedia_set(media, m | IFM_UNKNOWN); 4145 break; 4146 } 4147 } 4148 4149 /* 4150 * Update all the requested_* fields in the link config and then send a mailbox 4151 * command to apply the settings. 4152 */ 4153 static void 4154 init_l1cfg(struct port_info *pi) 4155 { 4156 struct adapter *sc = pi->adapter; 4157 struct link_config *lc = &pi->link_cfg; 4158 int rc; 4159 4160 ASSERT_SYNCHRONIZED_OP(sc); 4161 4162 lc->requested_speed = port_top_speed(pi); /* in Gbps */ 4163 if (t4_autoneg != 0 && lc->supported & FW_PORT_CAP_ANEG) { 4164 lc->requested_aneg = AUTONEG_ENABLE; 4165 } else { 4166 lc->requested_aneg = AUTONEG_DISABLE; 4167 } 4168 4169 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX); 4170 4171 if (t4_fec != -1) { 4172 lc->requested_fec = t4_fec & (FEC_RS | FEC_BASER_RS | 4173 FEC_RESERVED); 4174 } else { 4175 /* Use the suggested value provided by the firmware in acaps */ 4176 if (lc->advertising & FW_PORT_CAP_FEC_RS) 4177 lc->requested_fec = FEC_RS; 4178 else if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS) 4179 lc->requested_fec = FEC_BASER_RS; 4180 else 4181 lc->requested_fec = 0; 4182 } 4183 4184 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4185 if (rc != 0) { 4186 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4187 } else { 4188 lc->fc = lc->requested_fc; 4189 lc->fec = lc->requested_fec; 4190 } 4191 } 4192 4193 #define FW_MAC_EXACT_CHUNK 7 4194 4195 /* 4196 * Program the port's XGMAC based on parameters in ifnet. The caller also 4197 * indicates which parameters should be programmed (the rest are left alone). 4198 */ 4199 int 4200 update_mac_settings(struct ifnet *ifp, int flags) 4201 { 4202 int rc = 0; 4203 struct vi_info *vi = ifp->if_softc; 4204 struct port_info *pi = vi->pi; 4205 struct adapter *sc = pi->adapter; 4206 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4207 4208 ASSERT_SYNCHRONIZED_OP(sc); 4209 KASSERT(flags, ("%s: not told what to update.", __func__)); 4210 4211 if (flags & XGMAC_MTU) 4212 mtu = ifp->if_mtu; 4213 4214 if (flags & XGMAC_PROMISC) 4215 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4216 4217 if (flags & XGMAC_ALLMULTI) 4218 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4219 4220 if (flags & XGMAC_VLANEX) 4221 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4222 4223 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4224 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4225 allmulti, 1, vlanex, false); 4226 if (rc) { 4227 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4228 rc); 4229 return (rc); 4230 } 4231 } 4232 4233 if (flags & XGMAC_UCADDR) { 4234 uint8_t ucaddr[ETHER_ADDR_LEN]; 4235 4236 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4237 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4238 ucaddr, true, true); 4239 if (rc < 0) { 4240 rc = -rc; 4241 if_printf(ifp, "change_mac failed: %d\n", rc); 4242 return (rc); 4243 } else { 4244 vi->xact_addr_filt = rc; 4245 rc = 0; 4246 } 4247 } 4248 4249 if (flags & XGMAC_MCADDRS) { 4250 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4251 int del = 1; 4252 uint64_t hash = 0; 4253 struct ifmultiaddr *ifma; 4254 int i = 0, j; 4255 4256 if_maddr_rlock(ifp); 4257 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4258 if (ifma->ifma_addr->sa_family != AF_LINK) 4259 continue; 4260 mcaddr[i] = 4261 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4262 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4263 i++; 4264 4265 if (i == FW_MAC_EXACT_CHUNK) { 4266 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4267 del, i, mcaddr, NULL, &hash, 0); 4268 if (rc < 0) { 4269 rc = -rc; 4270 for (j = 0; j < i; j++) { 4271 if_printf(ifp, 4272 "failed to add mc address" 4273 " %02x:%02x:%02x:" 4274 "%02x:%02x:%02x rc=%d\n", 4275 mcaddr[j][0], mcaddr[j][1], 4276 mcaddr[j][2], mcaddr[j][3], 4277 mcaddr[j][4], mcaddr[j][5], 4278 rc); 4279 } 4280 goto mcfail; 4281 } 4282 del = 0; 4283 i = 0; 4284 } 4285 } 4286 if (i > 0) { 4287 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4288 mcaddr, NULL, &hash, 0); 4289 if (rc < 0) { 4290 rc = -rc; 4291 for (j = 0; j < i; j++) { 4292 if_printf(ifp, 4293 "failed to add mc address" 4294 " %02x:%02x:%02x:" 4295 "%02x:%02x:%02x rc=%d\n", 4296 mcaddr[j][0], mcaddr[j][1], 4297 mcaddr[j][2], mcaddr[j][3], 4298 mcaddr[j][4], mcaddr[j][5], 4299 rc); 4300 } 4301 goto mcfail; 4302 } 4303 } 4304 4305 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4306 if (rc != 0) 4307 if_printf(ifp, "failed to set mc address hash: %d", rc); 4308 mcfail: 4309 if_maddr_runlock(ifp); 4310 } 4311 4312 return (rc); 4313 } 4314 4315 /* 4316 * {begin|end}_synchronized_op must be called from the same thread. 4317 */ 4318 int 4319 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4320 char *wmesg) 4321 { 4322 int rc, pri; 4323 4324 #ifdef WITNESS 4325 /* the caller thinks it's ok to sleep, but is it really? */ 4326 if (flags & SLEEP_OK) 4327 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4328 "begin_synchronized_op"); 4329 #endif 4330 4331 if (INTR_OK) 4332 pri = PCATCH; 4333 else 4334 pri = 0; 4335 4336 ADAPTER_LOCK(sc); 4337 for (;;) { 4338 4339 if (vi && IS_DOOMED(vi)) { 4340 rc = ENXIO; 4341 goto done; 4342 } 4343 4344 if (!IS_BUSY(sc)) { 4345 rc = 0; 4346 break; 4347 } 4348 4349 if (!(flags & SLEEP_OK)) { 4350 rc = EBUSY; 4351 goto done; 4352 } 4353 4354 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4355 rc = EINTR; 4356 goto done; 4357 } 4358 } 4359 4360 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4361 SET_BUSY(sc); 4362 #ifdef INVARIANTS 4363 sc->last_op = wmesg; 4364 sc->last_op_thr = curthread; 4365 sc->last_op_flags = flags; 4366 #endif 4367 4368 done: 4369 if (!(flags & HOLD_LOCK) || rc) 4370 ADAPTER_UNLOCK(sc); 4371 4372 return (rc); 4373 } 4374 4375 /* 4376 * Tell if_ioctl and if_init that the VI is going away. This is 4377 * special variant of begin_synchronized_op and must be paired with a 4378 * call to end_synchronized_op. 4379 */ 4380 void 4381 doom_vi(struct adapter *sc, struct vi_info *vi) 4382 { 4383 4384 ADAPTER_LOCK(sc); 4385 SET_DOOMED(vi); 4386 wakeup(&sc->flags); 4387 while (IS_BUSY(sc)) 4388 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4389 SET_BUSY(sc); 4390 #ifdef INVARIANTS 4391 sc->last_op = "t4detach"; 4392 sc->last_op_thr = curthread; 4393 sc->last_op_flags = 0; 4394 #endif 4395 ADAPTER_UNLOCK(sc); 4396 } 4397 4398 /* 4399 * {begin|end}_synchronized_op must be called from the same thread. 4400 */ 4401 void 4402 end_synchronized_op(struct adapter *sc, int flags) 4403 { 4404 4405 if (flags & LOCK_HELD) 4406 ADAPTER_LOCK_ASSERT_OWNED(sc); 4407 else 4408 ADAPTER_LOCK(sc); 4409 4410 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 4411 CLR_BUSY(sc); 4412 wakeup(&sc->flags); 4413 ADAPTER_UNLOCK(sc); 4414 } 4415 4416 static int 4417 cxgbe_init_synchronized(struct vi_info *vi) 4418 { 4419 struct port_info *pi = vi->pi; 4420 struct adapter *sc = pi->adapter; 4421 struct ifnet *ifp = vi->ifp; 4422 int rc = 0, i; 4423 struct sge_txq *txq; 4424 4425 ASSERT_SYNCHRONIZED_OP(sc); 4426 4427 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4428 return (0); /* already running */ 4429 4430 if (!(sc->flags & FULL_INIT_DONE) && 4431 ((rc = adapter_full_init(sc)) != 0)) 4432 return (rc); /* error message displayed already */ 4433 4434 if (!(vi->flags & VI_INIT_DONE) && 4435 ((rc = vi_full_init(vi)) != 0)) 4436 return (rc); /* error message displayed already */ 4437 4438 rc = update_mac_settings(ifp, XGMAC_ALL); 4439 if (rc) 4440 goto done; /* error message displayed already */ 4441 4442 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 4443 if (rc != 0) { 4444 if_printf(ifp, "enable_vi failed: %d\n", rc); 4445 goto done; 4446 } 4447 4448 /* 4449 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 4450 * if this changes. 4451 */ 4452 4453 for_each_txq(vi, i, txq) { 4454 TXQ_LOCK(txq); 4455 txq->eq.flags |= EQ_ENABLED; 4456 TXQ_UNLOCK(txq); 4457 } 4458 4459 /* 4460 * The first iq of the first port to come up is used for tracing. 4461 */ 4462 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 4463 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 4464 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4465 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4466 V_QUEUENUMBER(sc->traceq)); 4467 pi->flags |= HAS_TRACEQ; 4468 } 4469 4470 /* all ok */ 4471 PORT_LOCK(pi); 4472 if (pi->up_vis++ == 0) { 4473 t4_update_port_info(pi); 4474 build_medialist(pi, &pi->media); 4475 init_l1cfg(pi); 4476 } 4477 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4478 4479 if (pi->nvi > 1 || sc->flags & IS_VF) 4480 callout_reset(&vi->tick, hz, vi_tick, vi); 4481 else 4482 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4483 PORT_UNLOCK(pi); 4484 done: 4485 if (rc != 0) 4486 cxgbe_uninit_synchronized(vi); 4487 4488 return (rc); 4489 } 4490 4491 /* 4492 * Idempotent. 4493 */ 4494 static int 4495 cxgbe_uninit_synchronized(struct vi_info *vi) 4496 { 4497 struct port_info *pi = vi->pi; 4498 struct adapter *sc = pi->adapter; 4499 struct ifnet *ifp = vi->ifp; 4500 int rc, i; 4501 struct sge_txq *txq; 4502 4503 ASSERT_SYNCHRONIZED_OP(sc); 4504 4505 if (!(vi->flags & VI_INIT_DONE)) { 4506 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4507 KASSERT(0, ("uninited VI is running")); 4508 if_printf(ifp, "uninited VI with running ifnet. " 4509 "vi->flags 0x%016lx, if_flags 0x%08x, " 4510 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 4511 ifp->if_drv_flags); 4512 } 4513 return (0); 4514 } 4515 4516 /* 4517 * Disable the VI so that all its data in either direction is discarded 4518 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4519 * tick) intact as the TP can deliver negative advice or data that it's 4520 * holding in its RAM (for an offloaded connection) even after the VI is 4521 * disabled. 4522 */ 4523 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4524 if (rc) { 4525 if_printf(ifp, "disable_vi failed: %d\n", rc); 4526 return (rc); 4527 } 4528 4529 for_each_txq(vi, i, txq) { 4530 TXQ_LOCK(txq); 4531 txq->eq.flags &= ~EQ_ENABLED; 4532 TXQ_UNLOCK(txq); 4533 } 4534 4535 PORT_LOCK(pi); 4536 if (pi->nvi > 1 || sc->flags & IS_VF) 4537 callout_stop(&vi->tick); 4538 else 4539 callout_stop(&pi->tick); 4540 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4541 PORT_UNLOCK(pi); 4542 return (0); 4543 } 4544 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4545 pi->up_vis--; 4546 if (pi->up_vis > 0) { 4547 PORT_UNLOCK(pi); 4548 return (0); 4549 } 4550 PORT_UNLOCK(pi); 4551 4552 pi->link_cfg.link_ok = 0; 4553 pi->link_cfg.speed = 0; 4554 pi->link_cfg.link_down_rc = 255; 4555 t4_os_link_changed(pi); 4556 pi->old_link_cfg = pi->link_cfg; 4557 4558 return (0); 4559 } 4560 4561 /* 4562 * It is ok for this function to fail midway and return right away. t4_detach 4563 * will walk the entire sc->irq list and clean up whatever is valid. 4564 */ 4565 int 4566 t4_setup_intr_handlers(struct adapter *sc) 4567 { 4568 int rc, rid, p, q, v; 4569 char s[8]; 4570 struct irq *irq; 4571 struct port_info *pi; 4572 struct vi_info *vi; 4573 struct sge *sge = &sc->sge; 4574 struct sge_rxq *rxq; 4575 #ifdef TCP_OFFLOAD 4576 struct sge_ofld_rxq *ofld_rxq; 4577 #endif 4578 #ifdef DEV_NETMAP 4579 struct sge_nm_rxq *nm_rxq; 4580 #endif 4581 #ifdef RSS 4582 int nbuckets = rss_getnumbuckets(); 4583 #endif 4584 4585 /* 4586 * Setup interrupts. 4587 */ 4588 irq = &sc->irq[0]; 4589 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4590 if (forwarding_intr_to_fwq(sc)) 4591 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4592 4593 /* Multiple interrupts. */ 4594 if (sc->flags & IS_VF) 4595 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4596 ("%s: too few intr.", __func__)); 4597 else 4598 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4599 ("%s: too few intr.", __func__)); 4600 4601 /* The first one is always error intr on PFs */ 4602 if (!(sc->flags & IS_VF)) { 4603 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4604 if (rc != 0) 4605 return (rc); 4606 irq++; 4607 rid++; 4608 } 4609 4610 /* The second one is always the firmware event queue (first on VFs) */ 4611 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4612 if (rc != 0) 4613 return (rc); 4614 irq++; 4615 rid++; 4616 4617 for_each_port(sc, p) { 4618 pi = sc->port[p]; 4619 for_each_vi(pi, v, vi) { 4620 vi->first_intr = rid - 1; 4621 4622 if (vi->nnmrxq > 0) { 4623 int n = max(vi->nrxq, vi->nnmrxq); 4624 4625 rxq = &sge->rxq[vi->first_rxq]; 4626 #ifdef DEV_NETMAP 4627 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4628 #endif 4629 for (q = 0; q < n; q++) { 4630 snprintf(s, sizeof(s), "%x%c%x", p, 4631 'a' + v, q); 4632 if (q < vi->nrxq) 4633 irq->rxq = rxq++; 4634 #ifdef DEV_NETMAP 4635 if (q < vi->nnmrxq) 4636 irq->nm_rxq = nm_rxq++; 4637 #endif 4638 rc = t4_alloc_irq(sc, irq, rid, 4639 t4_vi_intr, irq, s); 4640 if (rc != 0) 4641 return (rc); 4642 #ifdef RSS 4643 if (q < vi->nrxq) { 4644 bus_bind_intr(sc->dev, irq->res, 4645 rss_getcpu(q % nbuckets)); 4646 } 4647 #endif 4648 irq++; 4649 rid++; 4650 vi->nintr++; 4651 } 4652 } else { 4653 for_each_rxq(vi, q, rxq) { 4654 snprintf(s, sizeof(s), "%x%c%x", p, 4655 'a' + v, q); 4656 rc = t4_alloc_irq(sc, irq, rid, 4657 t4_intr, rxq, s); 4658 if (rc != 0) 4659 return (rc); 4660 #ifdef RSS 4661 bus_bind_intr(sc->dev, irq->res, 4662 rss_getcpu(q % nbuckets)); 4663 #endif 4664 irq++; 4665 rid++; 4666 vi->nintr++; 4667 } 4668 } 4669 #ifdef TCP_OFFLOAD 4670 for_each_ofld_rxq(vi, q, ofld_rxq) { 4671 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 4672 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 4673 ofld_rxq, s); 4674 if (rc != 0) 4675 return (rc); 4676 irq++; 4677 rid++; 4678 vi->nintr++; 4679 } 4680 #endif 4681 } 4682 } 4683 MPASS(irq == &sc->irq[sc->intr_count]); 4684 4685 return (0); 4686 } 4687 4688 int 4689 adapter_full_init(struct adapter *sc) 4690 { 4691 int rc, i; 4692 #ifdef RSS 4693 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4694 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4695 #endif 4696 4697 ASSERT_SYNCHRONIZED_OP(sc); 4698 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4699 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 4700 ("%s: FULL_INIT_DONE already", __func__)); 4701 4702 /* 4703 * queues that belong to the adapter (not any particular port). 4704 */ 4705 rc = t4_setup_adapter_queues(sc); 4706 if (rc != 0) 4707 goto done; 4708 4709 for (i = 0; i < nitems(sc->tq); i++) { 4710 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 4711 taskqueue_thread_enqueue, &sc->tq[i]); 4712 if (sc->tq[i] == NULL) { 4713 device_printf(sc->dev, 4714 "failed to allocate task queue %d\n", i); 4715 rc = ENOMEM; 4716 goto done; 4717 } 4718 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 4719 device_get_nameunit(sc->dev), i); 4720 } 4721 #ifdef RSS 4722 MPASS(RSS_KEYSIZE == 40); 4723 rss_getkey((void *)&raw_rss_key[0]); 4724 for (i = 0; i < nitems(rss_key); i++) { 4725 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 4726 } 4727 t4_write_rss_key(sc, &rss_key[0], -1, 1); 4728 #endif 4729 4730 if (!(sc->flags & IS_VF)) 4731 t4_intr_enable(sc); 4732 sc->flags |= FULL_INIT_DONE; 4733 done: 4734 if (rc != 0) 4735 adapter_full_uninit(sc); 4736 4737 return (rc); 4738 } 4739 4740 int 4741 adapter_full_uninit(struct adapter *sc) 4742 { 4743 int i; 4744 4745 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4746 4747 t4_teardown_adapter_queues(sc); 4748 4749 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 4750 taskqueue_free(sc->tq[i]); 4751 sc->tq[i] = NULL; 4752 } 4753 4754 sc->flags &= ~FULL_INIT_DONE; 4755 4756 return (0); 4757 } 4758 4759 #ifdef RSS 4760 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 4761 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 4762 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 4763 RSS_HASHTYPE_RSS_UDP_IPV6) 4764 4765 /* Translates kernel hash types to hardware. */ 4766 static int 4767 hashconfig_to_hashen(int hashconfig) 4768 { 4769 int hashen = 0; 4770 4771 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 4772 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 4773 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 4774 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 4775 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 4776 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4777 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4778 } 4779 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 4780 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4781 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4782 } 4783 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 4784 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4785 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 4786 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4787 4788 return (hashen); 4789 } 4790 4791 /* Translates hardware hash types to kernel. */ 4792 static int 4793 hashen_to_hashconfig(int hashen) 4794 { 4795 int hashconfig = 0; 4796 4797 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 4798 /* 4799 * If UDP hashing was enabled it must have been enabled for 4800 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 4801 * enabling any 4-tuple hash is nonsense configuration. 4802 */ 4803 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4804 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 4805 4806 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4807 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 4808 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4809 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 4810 } 4811 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4812 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 4813 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4814 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 4815 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 4816 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 4817 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 4818 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 4819 4820 return (hashconfig); 4821 } 4822 #endif 4823 4824 int 4825 vi_full_init(struct vi_info *vi) 4826 { 4827 struct adapter *sc = vi->pi->adapter; 4828 struct ifnet *ifp = vi->ifp; 4829 uint16_t *rss; 4830 struct sge_rxq *rxq; 4831 int rc, i, j, hashen; 4832 #ifdef RSS 4833 int nbuckets = rss_getnumbuckets(); 4834 int hashconfig = rss_gethashconfig(); 4835 int extra; 4836 #endif 4837 4838 ASSERT_SYNCHRONIZED_OP(sc); 4839 KASSERT((vi->flags & VI_INIT_DONE) == 0, 4840 ("%s: VI_INIT_DONE already", __func__)); 4841 4842 sysctl_ctx_init(&vi->ctx); 4843 vi->flags |= VI_SYSCTL_CTX; 4844 4845 /* 4846 * Allocate tx/rx/fl queues for this VI. 4847 */ 4848 rc = t4_setup_vi_queues(vi); 4849 if (rc != 0) 4850 goto done; /* error message displayed already */ 4851 4852 /* 4853 * Setup RSS for this VI. Save a copy of the RSS table for later use. 4854 */ 4855 if (vi->nrxq > vi->rss_size) { 4856 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 4857 "some queues will never receive traffic.\n", vi->nrxq, 4858 vi->rss_size); 4859 } else if (vi->rss_size % vi->nrxq) { 4860 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 4861 "expect uneven traffic distribution.\n", vi->nrxq, 4862 vi->rss_size); 4863 } 4864 #ifdef RSS 4865 if (vi->nrxq != nbuckets) { 4866 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 4867 "performance will be impacted.\n", vi->nrxq, nbuckets); 4868 } 4869 #endif 4870 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 4871 for (i = 0; i < vi->rss_size;) { 4872 #ifdef RSS 4873 j = rss_get_indirection_to_bucket(i); 4874 j %= vi->nrxq; 4875 rxq = &sc->sge.rxq[vi->first_rxq + j]; 4876 rss[i++] = rxq->iq.abs_id; 4877 #else 4878 for_each_rxq(vi, j, rxq) { 4879 rss[i++] = rxq->iq.abs_id; 4880 if (i == vi->rss_size) 4881 break; 4882 } 4883 #endif 4884 } 4885 4886 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 4887 vi->rss_size); 4888 if (rc != 0) { 4889 if_printf(ifp, "rss_config failed: %d\n", rc); 4890 goto done; 4891 } 4892 4893 #ifdef RSS 4894 hashen = hashconfig_to_hashen(hashconfig); 4895 4896 /* 4897 * We may have had to enable some hashes even though the global config 4898 * wants them disabled. This is a potential problem that must be 4899 * reported to the user. 4900 */ 4901 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 4902 4903 /* 4904 * If we consider only the supported hash types, then the enabled hashes 4905 * are a superset of the requested hashes. In other words, there cannot 4906 * be any supported hash that was requested but not enabled, but there 4907 * can be hashes that were not requested but had to be enabled. 4908 */ 4909 extra &= SUPPORTED_RSS_HASHTYPES; 4910 MPASS((extra & hashconfig) == 0); 4911 4912 if (extra) { 4913 if_printf(ifp, 4914 "global RSS config (0x%x) cannot be accommodated.\n", 4915 hashconfig); 4916 } 4917 if (extra & RSS_HASHTYPE_RSS_IPV4) 4918 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 4919 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 4920 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 4921 if (extra & RSS_HASHTYPE_RSS_IPV6) 4922 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 4923 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 4924 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 4925 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 4926 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 4927 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 4928 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 4929 #else 4930 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 4931 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 4932 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4933 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 4934 #endif 4935 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0); 4936 if (rc != 0) { 4937 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 4938 goto done; 4939 } 4940 4941 vi->rss = rss; 4942 vi->flags |= VI_INIT_DONE; 4943 done: 4944 if (rc != 0) 4945 vi_full_uninit(vi); 4946 4947 return (rc); 4948 } 4949 4950 /* 4951 * Idempotent. 4952 */ 4953 int 4954 vi_full_uninit(struct vi_info *vi) 4955 { 4956 struct port_info *pi = vi->pi; 4957 struct adapter *sc = pi->adapter; 4958 int i; 4959 struct sge_rxq *rxq; 4960 struct sge_txq *txq; 4961 #ifdef TCP_OFFLOAD 4962 struct sge_ofld_rxq *ofld_rxq; 4963 struct sge_wrq *ofld_txq; 4964 #endif 4965 4966 if (vi->flags & VI_INIT_DONE) { 4967 4968 /* Need to quiesce queues. */ 4969 4970 /* XXX: Only for the first VI? */ 4971 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 4972 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 4973 4974 for_each_txq(vi, i, txq) { 4975 quiesce_txq(sc, txq); 4976 } 4977 4978 #ifdef TCP_OFFLOAD 4979 for_each_ofld_txq(vi, i, ofld_txq) { 4980 quiesce_wrq(sc, ofld_txq); 4981 } 4982 #endif 4983 4984 for_each_rxq(vi, i, rxq) { 4985 quiesce_iq(sc, &rxq->iq); 4986 quiesce_fl(sc, &rxq->fl); 4987 } 4988 4989 #ifdef TCP_OFFLOAD 4990 for_each_ofld_rxq(vi, i, ofld_rxq) { 4991 quiesce_iq(sc, &ofld_rxq->iq); 4992 quiesce_fl(sc, &ofld_rxq->fl); 4993 } 4994 #endif 4995 free(vi->rss, M_CXGBE); 4996 free(vi->nm_rss, M_CXGBE); 4997 } 4998 4999 t4_teardown_vi_queues(vi); 5000 vi->flags &= ~VI_INIT_DONE; 5001 5002 return (0); 5003 } 5004 5005 static void 5006 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5007 { 5008 struct sge_eq *eq = &txq->eq; 5009 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5010 5011 (void) sc; /* unused */ 5012 5013 #ifdef INVARIANTS 5014 TXQ_LOCK(txq); 5015 MPASS((eq->flags & EQ_ENABLED) == 0); 5016 TXQ_UNLOCK(txq); 5017 #endif 5018 5019 /* Wait for the mp_ring to empty. */ 5020 while (!mp_ring_is_idle(txq->r)) { 5021 mp_ring_check_drainage(txq->r, 0); 5022 pause("rquiesce", 1); 5023 } 5024 5025 /* Then wait for the hardware to finish. */ 5026 while (spg->cidx != htobe16(eq->pidx)) 5027 pause("equiesce", 1); 5028 5029 /* Finally, wait for the driver to reclaim all descriptors. */ 5030 while (eq->cidx != eq->pidx) 5031 pause("dquiesce", 1); 5032 } 5033 5034 static void 5035 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5036 { 5037 5038 /* XXXTX */ 5039 } 5040 5041 static void 5042 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5043 { 5044 (void) sc; /* unused */ 5045 5046 /* Synchronize with the interrupt handler */ 5047 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5048 pause("iqfree", 1); 5049 } 5050 5051 static void 5052 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5053 { 5054 mtx_lock(&sc->sfl_lock); 5055 FL_LOCK(fl); 5056 fl->flags |= FL_DOOMED; 5057 FL_UNLOCK(fl); 5058 callout_stop(&sc->sfl_callout); 5059 mtx_unlock(&sc->sfl_lock); 5060 5061 KASSERT((fl->flags & FL_STARVING) == 0, 5062 ("%s: still starving", __func__)); 5063 } 5064 5065 static int 5066 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5067 driver_intr_t *handler, void *arg, char *name) 5068 { 5069 int rc; 5070 5071 irq->rid = rid; 5072 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5073 RF_SHAREABLE | RF_ACTIVE); 5074 if (irq->res == NULL) { 5075 device_printf(sc->dev, 5076 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5077 return (ENOMEM); 5078 } 5079 5080 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5081 NULL, handler, arg, &irq->tag); 5082 if (rc != 0) { 5083 device_printf(sc->dev, 5084 "failed to setup interrupt for rid %d, name %s: %d\n", 5085 rid, name, rc); 5086 } else if (name) 5087 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5088 5089 return (rc); 5090 } 5091 5092 static int 5093 t4_free_irq(struct adapter *sc, struct irq *irq) 5094 { 5095 if (irq->tag) 5096 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5097 if (irq->res) 5098 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5099 5100 bzero(irq, sizeof(*irq)); 5101 5102 return (0); 5103 } 5104 5105 static void 5106 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5107 { 5108 5109 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5110 t4_get_regs(sc, buf, regs->len); 5111 } 5112 5113 #define A_PL_INDIR_CMD 0x1f8 5114 5115 #define S_PL_AUTOINC 31 5116 #define M_PL_AUTOINC 0x1U 5117 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5118 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5119 5120 #define S_PL_VFID 20 5121 #define M_PL_VFID 0xffU 5122 #define V_PL_VFID(x) ((x) << S_PL_VFID) 5123 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5124 5125 #define S_PL_ADDR 0 5126 #define M_PL_ADDR 0xfffffU 5127 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5128 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5129 5130 #define A_PL_INDIR_DATA 0x1fc 5131 5132 static uint64_t 5133 read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 5134 { 5135 u32 stats[2]; 5136 5137 mtx_assert(&sc->reg_lock, MA_OWNED); 5138 if (sc->flags & IS_VF) { 5139 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5140 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5141 } else { 5142 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5143 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5144 V_PL_ADDR(VF_MPS_REG(reg))); 5145 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5146 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5147 } 5148 return (((uint64_t)stats[1]) << 32 | stats[0]); 5149 } 5150 5151 static void 5152 t4_get_vi_stats(struct adapter *sc, unsigned int viid, 5153 struct fw_vi_stats_vf *stats) 5154 { 5155 5156 #define GET_STAT(name) \ 5157 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 5158 5159 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5160 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5161 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5162 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5163 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5164 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5165 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5166 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5167 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5168 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5169 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5170 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5171 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5172 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5173 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5174 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5175 5176 #undef GET_STAT 5177 } 5178 5179 static void 5180 t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 5181 { 5182 int reg; 5183 5184 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5185 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5186 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5187 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5188 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5189 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5190 } 5191 5192 static void 5193 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5194 { 5195 struct timeval tv; 5196 const struct timeval interval = {0, 250000}; /* 250ms */ 5197 5198 if (!(vi->flags & VI_INIT_DONE)) 5199 return; 5200 5201 getmicrotime(&tv); 5202 timevalsub(&tv, &interval); 5203 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5204 return; 5205 5206 mtx_lock(&sc->reg_lock); 5207 t4_get_vi_stats(sc, vi->viid, &vi->stats); 5208 getmicrotime(&vi->last_refreshed); 5209 mtx_unlock(&sc->reg_lock); 5210 } 5211 5212 static void 5213 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5214 { 5215 u_int i, v, tnl_cong_drops, bg_map; 5216 struct timeval tv; 5217 const struct timeval interval = {0, 250000}; /* 250ms */ 5218 5219 getmicrotime(&tv); 5220 timevalsub(&tv, &interval); 5221 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5222 return; 5223 5224 tnl_cong_drops = 0; 5225 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5226 bg_map = pi->mps_bg_map; 5227 while (bg_map) { 5228 i = ffs(bg_map) - 1; 5229 mtx_lock(&sc->reg_lock); 5230 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5231 A_TP_MIB_TNL_CNG_DROP_0 + i); 5232 mtx_unlock(&sc->reg_lock); 5233 tnl_cong_drops += v; 5234 bg_map &= ~(1 << i); 5235 } 5236 pi->tnl_cong_drops = tnl_cong_drops; 5237 getmicrotime(&pi->last_refreshed); 5238 } 5239 5240 static void 5241 cxgbe_tick(void *arg) 5242 { 5243 struct port_info *pi = arg; 5244 struct adapter *sc = pi->adapter; 5245 5246 PORT_LOCK_ASSERT_OWNED(pi); 5247 cxgbe_refresh_stats(sc, pi); 5248 5249 callout_schedule(&pi->tick, hz); 5250 } 5251 5252 void 5253 vi_tick(void *arg) 5254 { 5255 struct vi_info *vi = arg; 5256 struct adapter *sc = vi->pi->adapter; 5257 5258 vi_refresh_stats(sc, vi); 5259 5260 callout_schedule(&vi->tick, hz); 5261 } 5262 5263 static void 5264 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 5265 { 5266 struct ifnet *vlan; 5267 5268 if (arg != ifp || ifp->if_type != IFT_ETHER) 5269 return; 5270 5271 vlan = VLAN_DEVAT(ifp, vid); 5272 VLAN_SETCOOKIE(vlan, ifp); 5273 } 5274 5275 /* 5276 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5277 */ 5278 static char *caps_decoder[] = { 5279 "\20\001IPMI\002NCSI", /* 0: NBM */ 5280 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5281 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5282 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5283 "\006HASHFILTER\007ETHOFLD", 5284 "\20\001TOE", /* 4: TOE */ 5285 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5286 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5287 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5288 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5289 "\007T10DIF" 5290 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5291 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5292 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5293 "\004PO_INITIATOR\005PO_TARGET", 5294 }; 5295 5296 void 5297 t4_sysctls(struct adapter *sc) 5298 { 5299 struct sysctl_ctx_list *ctx; 5300 struct sysctl_oid *oid; 5301 struct sysctl_oid_list *children, *c0; 5302 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5303 5304 ctx = device_get_sysctl_ctx(sc->dev); 5305 5306 /* 5307 * dev.t4nex.X. 5308 */ 5309 oid = device_get_sysctl_tree(sc->dev); 5310 c0 = children = SYSCTL_CHILDREN(oid); 5311 5312 sc->sc_do_rxcopy = 1; 5313 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5314 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5315 5316 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5317 sc->params.nports, "# of ports"); 5318 5319 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5320 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 5321 sysctl_bitfield, "A", "available doorbells"); 5322 5323 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5324 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5325 5326 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5327 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5328 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5329 "interrupt holdoff timer values (us)"); 5330 5331 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5332 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5333 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5334 "interrupt holdoff packet counter values"); 5335 5336 t4_sge_sysctls(sc, ctx, children); 5337 5338 sc->lro_timeout = 100; 5339 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5340 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5341 5342 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5343 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5344 5345 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5346 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5347 5348 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5349 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5350 5351 if (sc->flags & IS_VF) 5352 return; 5353 5354 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5355 NULL, chip_rev(sc), "chip hardware revision"); 5356 5357 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5358 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5359 5360 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5361 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5362 5363 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5364 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5365 5366 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5367 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5368 5369 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5370 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5371 5372 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5373 sc->er_version, 0, "expansion ROM version"); 5374 5375 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5376 sc->bs_version, 0, "bootstrap firmware version"); 5377 5378 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5379 NULL, sc->params.scfg_vers, "serial config version"); 5380 5381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5382 NULL, sc->params.vpd_vers, "VPD version"); 5383 5384 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5385 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5386 5387 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5388 sc->cfcsum, "config file checksum"); 5389 5390 #define SYSCTL_CAP(name, n, text) \ 5391 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5392 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \ 5393 sysctl_bitfield, "A", "available " text " capabilities") 5394 5395 SYSCTL_CAP(nbmcaps, 0, "NBM"); 5396 SYSCTL_CAP(linkcaps, 1, "link"); 5397 SYSCTL_CAP(switchcaps, 2, "switch"); 5398 SYSCTL_CAP(niccaps, 3, "NIC"); 5399 SYSCTL_CAP(toecaps, 4, "TCP offload"); 5400 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 5401 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 5402 SYSCTL_CAP(cryptocaps, 7, "crypto"); 5403 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 5404 #undef SYSCTL_CAP 5405 5406 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 5407 NULL, sc->tids.nftids, "number of filters"); 5408 5409 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 5410 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 5411 "chip temperature (in Celsius)"); 5412 5413 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 5414 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 5415 5416 #ifdef SBUF_DRAIN 5417 /* 5418 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 5419 */ 5420 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 5421 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 5422 "logs and miscellaneous information"); 5423 children = SYSCTL_CHILDREN(oid); 5424 5425 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 5426 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5427 sysctl_cctrl, "A", "congestion control"); 5428 5429 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 5430 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5431 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 5432 5433 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 5434 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 5435 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 5436 5437 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 5438 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 5439 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 5440 5441 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 5442 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 5443 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 5444 5445 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 5446 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 5447 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 5448 5449 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 5450 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 5451 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 5452 5453 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 5454 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5455 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 5456 "A", "CIM logic analyzer"); 5457 5458 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 5459 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5460 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 5461 5462 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 5463 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 5464 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 5465 5466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 5467 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 5468 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 5469 5470 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 5471 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 5472 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 5473 5474 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 5475 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 5476 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 5477 5478 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 5479 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 5480 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 5481 5482 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 5483 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 5484 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5485 5486 if (chip_id(sc) > CHELSIO_T4) { 5487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5488 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5489 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5490 5491 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5492 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5493 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5494 } 5495 5496 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5497 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5498 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5499 5500 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5501 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5502 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5503 5504 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5505 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5506 sysctl_cpl_stats, "A", "CPL statistics"); 5507 5508 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5509 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5510 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5511 5512 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5513 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5514 sysctl_devlog, "A", "firmware's device log"); 5515 5516 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5517 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5518 sysctl_fcoe_stats, "A", "FCoE statistics"); 5519 5520 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5521 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5522 sysctl_hw_sched, "A", "hardware scheduler "); 5523 5524 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5525 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5526 sysctl_l2t, "A", "hardware L2 table"); 5527 5528 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5529 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5530 sysctl_lb_stats, "A", "loopback statistics"); 5531 5532 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5533 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5534 sysctl_meminfo, "A", "memory regions"); 5535 5536 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5537 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5538 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5539 "A", "MPS TCAM entries"); 5540 5541 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5542 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5543 sysctl_path_mtus, "A", "path MTUs"); 5544 5545 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5546 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5547 sysctl_pm_stats, "A", "PM statistics"); 5548 5549 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5550 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5551 sysctl_rdma_stats, "A", "RDMA statistics"); 5552 5553 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5554 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5555 sysctl_tcp_stats, "A", "TCP statistics"); 5556 5557 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5558 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5559 sysctl_tids, "A", "TID information"); 5560 5561 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5562 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5563 sysctl_tp_err_stats, "A", "TP error statistics"); 5564 5565 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5566 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5567 "TP logic analyzer event capture mask"); 5568 5569 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5570 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5571 sysctl_tp_la, "A", "TP logic analyzer"); 5572 5573 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5574 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5575 sysctl_tx_rate, "A", "Tx rate"); 5576 5577 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5578 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5579 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5580 5581 if (chip_id(sc) >= CHELSIO_T5) { 5582 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5583 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5584 sysctl_wcwr_stats, "A", "write combined work requests"); 5585 } 5586 #endif 5587 5588 #ifdef TCP_OFFLOAD 5589 if (is_offload(sc)) { 5590 int i; 5591 char s[4]; 5592 5593 /* 5594 * dev.t4nex.X.toe. 5595 */ 5596 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5597 NULL, "TOE parameters"); 5598 children = SYSCTL_CHILDREN(oid); 5599 5600 sc->tt.cong_algorithm = -1; 5601 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 5602 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 5603 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 5604 "3 = highspeed)"); 5605 5606 sc->tt.sndbuf = 256 * 1024; 5607 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 5608 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 5609 5610 sc->tt.ddp = 0; 5611 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 5612 &sc->tt.ddp, 0, "DDP allowed"); 5613 5614 sc->tt.rx_coalesce = 1; 5615 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 5616 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 5617 5618 sc->tt.tls = 0; 5619 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 5620 &sc->tt.tls, 0, "Inline TLS allowed"); 5621 5622 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 5623 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 5624 "I", "TCP ports that use inline TLS+TOE RX"); 5625 5626 sc->tt.tx_align = 1; 5627 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 5628 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 5629 5630 sc->tt.tx_zcopy = 0; 5631 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 5632 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 5633 "Enable zero-copy aio_write(2)"); 5634 5635 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 5636 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5637 "cop_managed_offloading", CTLFLAG_RW, 5638 &sc->tt.cop_managed_offloading, 0, 5639 "COP (Connection Offload Policy) controls all TOE offload"); 5640 5641 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 5642 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 5643 "TP timer tick (us)"); 5644 5645 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 5646 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 5647 "TCP timestamp tick (us)"); 5648 5649 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 5650 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 5651 "DACK tick (us)"); 5652 5653 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 5654 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 5655 "IU", "DACK timer (us)"); 5656 5657 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 5658 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 5659 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 5660 5661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 5662 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 5663 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 5664 5665 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 5666 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 5667 sysctl_tp_timer, "LU", "Persist timer min (us)"); 5668 5669 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 5670 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 5671 sysctl_tp_timer, "LU", "Persist timer max (us)"); 5672 5673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 5674 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 5675 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 5676 5677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 5678 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 5679 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 5680 5681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 5682 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 5683 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 5684 5685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 5686 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 5687 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 5688 5689 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 5690 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 5691 sysctl_tp_shift_cnt, "IU", 5692 "Number of SYN retransmissions before abort"); 5693 5694 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 5695 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 5696 sysctl_tp_shift_cnt, "IU", 5697 "Number of retransmissions before abort"); 5698 5699 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 5700 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 5701 sysctl_tp_shift_cnt, "IU", 5702 "Number of keepalive probes before abort"); 5703 5704 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 5705 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 5706 children = SYSCTL_CHILDREN(oid); 5707 for (i = 0; i < 16; i++) { 5708 snprintf(s, sizeof(s), "%u", i); 5709 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 5710 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 5711 "IU", "TOE retransmit backoff"); 5712 } 5713 } 5714 #endif 5715 } 5716 5717 void 5718 vi_sysctls(struct vi_info *vi) 5719 { 5720 struct sysctl_ctx_list *ctx; 5721 struct sysctl_oid *oid; 5722 struct sysctl_oid_list *children; 5723 5724 ctx = device_get_sysctl_ctx(vi->dev); 5725 5726 /* 5727 * dev.v?(cxgbe|cxl).X. 5728 */ 5729 oid = device_get_sysctl_tree(vi->dev); 5730 children = SYSCTL_CHILDREN(oid); 5731 5732 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 5733 vi->viid, "VI identifer"); 5734 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 5735 &vi->nrxq, 0, "# of rx queues"); 5736 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 5737 &vi->ntxq, 0, "# of tx queues"); 5738 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 5739 &vi->first_rxq, 0, "index of first rx queue"); 5740 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 5741 &vi->first_txq, 0, "index of first tx queue"); 5742 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 5743 vi->rss_size, "size of RSS indirection table"); 5744 5745 if (IS_MAIN_VI(vi)) { 5746 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 5747 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 5748 "Reserve queue 0 for non-flowid packets"); 5749 } 5750 5751 #ifdef TCP_OFFLOAD 5752 if (vi->nofldrxq != 0) { 5753 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 5754 &vi->nofldrxq, 0, 5755 "# of rx queues for offloaded TCP connections"); 5756 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 5757 &vi->nofldtxq, 0, 5758 "# of tx queues for offloaded TCP connections"); 5759 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 5760 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 5761 "index of first TOE rx queue"); 5762 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 5763 CTLFLAG_RD, &vi->first_ofld_txq, 0, 5764 "index of first TOE tx queue"); 5765 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 5766 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5767 sysctl_holdoff_tmr_idx_ofld, "I", 5768 "holdoff timer index for TOE queues"); 5769 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 5770 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 5771 sysctl_holdoff_pktc_idx_ofld, "I", 5772 "holdoff packet counter index for TOE queues"); 5773 } 5774 #endif 5775 #ifdef DEV_NETMAP 5776 if (vi->nnmrxq != 0) { 5777 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 5778 &vi->nnmrxq, 0, "# of netmap rx queues"); 5779 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 5780 &vi->nnmtxq, 0, "# of netmap tx queues"); 5781 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 5782 CTLFLAG_RD, &vi->first_nm_rxq, 0, 5783 "index of first netmap rx queue"); 5784 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 5785 CTLFLAG_RD, &vi->first_nm_txq, 0, 5786 "index of first netmap tx queue"); 5787 } 5788 #endif 5789 5790 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 5791 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 5792 "holdoff timer index"); 5793 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 5794 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 5795 "holdoff packet counter index"); 5796 5797 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 5798 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 5799 "rx queue size"); 5800 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 5801 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 5802 "tx queue size"); 5803 } 5804 5805 static void 5806 cxgbe_sysctls(struct port_info *pi) 5807 { 5808 struct sysctl_ctx_list *ctx; 5809 struct sysctl_oid *oid; 5810 struct sysctl_oid_list *children, *children2; 5811 struct adapter *sc = pi->adapter; 5812 int i; 5813 char name[16]; 5814 5815 ctx = device_get_sysctl_ctx(pi->dev); 5816 5817 /* 5818 * dev.cxgbe.X. 5819 */ 5820 oid = device_get_sysctl_tree(pi->dev); 5821 children = SYSCTL_CHILDREN(oid); 5822 5823 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 5824 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 5825 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 5826 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 5827 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 5828 "PHY temperature (in Celsius)"); 5829 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 5830 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 5831 "PHY firmware version"); 5832 } 5833 5834 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 5835 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 5836 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)"); 5837 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 5838 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 5839 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 5840 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 5841 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 5842 "autonegotiation (-1 = not supported)"); 5843 5844 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 5845 port_top_speed(pi), "max speed (in Gbps)"); 5846 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 5847 pi->mps_bg_map, "MPS buffer group map"); 5848 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 5849 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 5850 5851 if (sc->flags & IS_VF) 5852 return; 5853 5854 /* 5855 * dev.(cxgbe|cxl).X.tc. 5856 */ 5857 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 5858 "Tx scheduler traffic classes (cl_rl)"); 5859 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 5860 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 5861 5862 snprintf(name, sizeof(name), "%d", i); 5863 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 5864 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 5865 "traffic class")); 5866 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD, 5867 &tc->flags, 0, "flags"); 5868 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 5869 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 5870 #ifdef SBUF_DRAIN 5871 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 5872 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 5873 sysctl_tc_params, "A", "traffic class parameters"); 5874 #endif 5875 } 5876 5877 /* 5878 * dev.cxgbe.X.stats. 5879 */ 5880 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 5881 NULL, "port statistics"); 5882 children = SYSCTL_CHILDREN(oid); 5883 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 5884 &pi->tx_parse_error, 0, 5885 "# of tx packets with invalid length or # of segments"); 5886 5887 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 5888 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 5889 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 5890 sysctl_handle_t4_reg64, "QU", desc) 5891 5892 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 5893 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 5894 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 5895 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 5896 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 5897 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 5898 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 5899 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 5900 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 5901 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 5902 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 5903 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 5904 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 5905 "# of tx frames in this range", 5906 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 5907 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 5908 "# of tx frames in this range", 5909 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 5910 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 5911 "# of tx frames in this range", 5912 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 5913 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 5914 "# of tx frames in this range", 5915 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 5916 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 5917 "# of tx frames in this range", 5918 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 5919 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 5920 "# of tx frames in this range", 5921 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 5922 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 5923 "# of tx frames in this range", 5924 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 5925 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 5926 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 5927 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 5928 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 5929 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 5930 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 5931 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 5932 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 5933 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 5934 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 5935 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 5936 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 5937 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 5938 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 5939 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 5940 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 5941 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 5942 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 5943 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 5944 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 5945 5946 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 5947 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 5948 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 5949 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 5950 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 5951 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 5952 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 5953 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 5954 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 5955 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 5956 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 5957 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 5958 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 5959 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 5960 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 5961 "# of frames received with bad FCS", 5962 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 5963 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 5964 "# of frames received with length error", 5965 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 5966 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 5967 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 5968 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 5969 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 5970 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 5971 "# of rx frames in this range", 5972 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 5973 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 5974 "# of rx frames in this range", 5975 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 5976 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 5977 "# of rx frames in this range", 5978 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 5979 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 5980 "# of rx frames in this range", 5981 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 5982 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 5983 "# of rx frames in this range", 5984 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 5985 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 5986 "# of rx frames in this range", 5987 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 5988 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 5989 "# of rx frames in this range", 5990 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 5991 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 5992 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 5993 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 5994 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 5995 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 5996 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 5997 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 5998 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 5999 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6000 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6001 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6002 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6003 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6004 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6005 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6006 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6007 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6008 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6009 6010 #undef SYSCTL_ADD_T4_REG64 6011 6012 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6013 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6014 &pi->stats.name, desc) 6015 6016 /* We get these from port_stats and they may be stale by up to 1s */ 6017 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6018 "# drops due to buffer-group 0 overflows"); 6019 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6020 "# drops due to buffer-group 1 overflows"); 6021 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6022 "# drops due to buffer-group 2 overflows"); 6023 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6024 "# drops due to buffer-group 3 overflows"); 6025 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6026 "# of buffer-group 0 truncated packets"); 6027 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6028 "# of buffer-group 1 truncated packets"); 6029 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6030 "# of buffer-group 2 truncated packets"); 6031 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6032 "# of buffer-group 3 truncated packets"); 6033 6034 #undef SYSCTL_ADD_T4_PORTSTAT 6035 6036 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6037 CTLFLAG_RD, &pi->tx_tls_records, 6038 "# of TLS records transmitted"); 6039 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6040 CTLFLAG_RD, &pi->tx_tls_octets, 6041 "# of payload octets in transmitted TLS records"); 6042 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6043 CTLFLAG_RD, &pi->rx_tls_records, 6044 "# of TLS records received"); 6045 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6046 CTLFLAG_RD, &pi->rx_tls_octets, 6047 "# of payload octets in received TLS records"); 6048 } 6049 6050 static int 6051 sysctl_int_array(SYSCTL_HANDLER_ARGS) 6052 { 6053 int rc, *i, space = 0; 6054 struct sbuf sb; 6055 6056 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6057 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6058 if (space) 6059 sbuf_printf(&sb, " "); 6060 sbuf_printf(&sb, "%d", *i); 6061 space = 1; 6062 } 6063 rc = sbuf_finish(&sb); 6064 sbuf_delete(&sb); 6065 return (rc); 6066 } 6067 6068 static int 6069 sysctl_bitfield(SYSCTL_HANDLER_ARGS) 6070 { 6071 int rc; 6072 struct sbuf *sb; 6073 6074 rc = sysctl_wire_old_buffer(req, 0); 6075 if (rc != 0) 6076 return(rc); 6077 6078 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6079 if (sb == NULL) 6080 return (ENOMEM); 6081 6082 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 6083 rc = sbuf_finish(sb); 6084 sbuf_delete(sb); 6085 6086 return (rc); 6087 } 6088 6089 static int 6090 sysctl_btphy(SYSCTL_HANDLER_ARGS) 6091 { 6092 struct port_info *pi = arg1; 6093 int op = arg2; 6094 struct adapter *sc = pi->adapter; 6095 u_int v; 6096 int rc; 6097 6098 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6099 if (rc) 6100 return (rc); 6101 /* XXX: magic numbers */ 6102 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6103 &v); 6104 end_synchronized_op(sc, 0); 6105 if (rc) 6106 return (rc); 6107 if (op == 0) 6108 v /= 256; 6109 6110 rc = sysctl_handle_int(oidp, &v, 0, req); 6111 return (rc); 6112 } 6113 6114 static int 6115 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6116 { 6117 struct vi_info *vi = arg1; 6118 int rc, val; 6119 6120 val = vi->rsrv_noflowq; 6121 rc = sysctl_handle_int(oidp, &val, 0, req); 6122 if (rc != 0 || req->newptr == NULL) 6123 return (rc); 6124 6125 if ((val >= 1) && (vi->ntxq > 1)) 6126 vi->rsrv_noflowq = 1; 6127 else 6128 vi->rsrv_noflowq = 0; 6129 6130 return (rc); 6131 } 6132 6133 static int 6134 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6135 { 6136 struct vi_info *vi = arg1; 6137 struct adapter *sc = vi->pi->adapter; 6138 int idx, rc, i; 6139 struct sge_rxq *rxq; 6140 uint8_t v; 6141 6142 idx = vi->tmr_idx; 6143 6144 rc = sysctl_handle_int(oidp, &idx, 0, req); 6145 if (rc != 0 || req->newptr == NULL) 6146 return (rc); 6147 6148 if (idx < 0 || idx >= SGE_NTIMERS) 6149 return (EINVAL); 6150 6151 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6152 "t4tmr"); 6153 if (rc) 6154 return (rc); 6155 6156 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6157 for_each_rxq(vi, i, rxq) { 6158 #ifdef atomic_store_rel_8 6159 atomic_store_rel_8(&rxq->iq.intr_params, v); 6160 #else 6161 rxq->iq.intr_params = v; 6162 #endif 6163 } 6164 vi->tmr_idx = idx; 6165 6166 end_synchronized_op(sc, LOCK_HELD); 6167 return (0); 6168 } 6169 6170 static int 6171 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6172 { 6173 struct vi_info *vi = arg1; 6174 struct adapter *sc = vi->pi->adapter; 6175 int idx, rc; 6176 6177 idx = vi->pktc_idx; 6178 6179 rc = sysctl_handle_int(oidp, &idx, 0, req); 6180 if (rc != 0 || req->newptr == NULL) 6181 return (rc); 6182 6183 if (idx < -1 || idx >= SGE_NCOUNTERS) 6184 return (EINVAL); 6185 6186 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6187 "t4pktc"); 6188 if (rc) 6189 return (rc); 6190 6191 if (vi->flags & VI_INIT_DONE) 6192 rc = EBUSY; /* cannot be changed once the queues are created */ 6193 else 6194 vi->pktc_idx = idx; 6195 6196 end_synchronized_op(sc, LOCK_HELD); 6197 return (rc); 6198 } 6199 6200 static int 6201 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6202 { 6203 struct vi_info *vi = arg1; 6204 struct adapter *sc = vi->pi->adapter; 6205 int qsize, rc; 6206 6207 qsize = vi->qsize_rxq; 6208 6209 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6210 if (rc != 0 || req->newptr == NULL) 6211 return (rc); 6212 6213 if (qsize < 128 || (qsize & 7)) 6214 return (EINVAL); 6215 6216 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6217 "t4rxqs"); 6218 if (rc) 6219 return (rc); 6220 6221 if (vi->flags & VI_INIT_DONE) 6222 rc = EBUSY; /* cannot be changed once the queues are created */ 6223 else 6224 vi->qsize_rxq = qsize; 6225 6226 end_synchronized_op(sc, LOCK_HELD); 6227 return (rc); 6228 } 6229 6230 static int 6231 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6232 { 6233 struct vi_info *vi = arg1; 6234 struct adapter *sc = vi->pi->adapter; 6235 int qsize, rc; 6236 6237 qsize = vi->qsize_txq; 6238 6239 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6240 if (rc != 0 || req->newptr == NULL) 6241 return (rc); 6242 6243 if (qsize < 128 || qsize > 65536) 6244 return (EINVAL); 6245 6246 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6247 "t4txqs"); 6248 if (rc) 6249 return (rc); 6250 6251 if (vi->flags & VI_INIT_DONE) 6252 rc = EBUSY; /* cannot be changed once the queues are created */ 6253 else 6254 vi->qsize_txq = qsize; 6255 6256 end_synchronized_op(sc, LOCK_HELD); 6257 return (rc); 6258 } 6259 6260 static int 6261 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6262 { 6263 struct port_info *pi = arg1; 6264 struct adapter *sc = pi->adapter; 6265 struct link_config *lc = &pi->link_cfg; 6266 int rc; 6267 6268 if (req->newptr == NULL) { 6269 struct sbuf *sb; 6270 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX"; 6271 6272 rc = sysctl_wire_old_buffer(req, 0); 6273 if (rc != 0) 6274 return(rc); 6275 6276 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6277 if (sb == NULL) 6278 return (ENOMEM); 6279 6280 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits); 6281 rc = sbuf_finish(sb); 6282 sbuf_delete(sb); 6283 } else { 6284 char s[2]; 6285 int n; 6286 6287 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX)); 6288 s[1] = 0; 6289 6290 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6291 if (rc != 0) 6292 return(rc); 6293 6294 if (s[1] != 0) 6295 return (EINVAL); 6296 if (s[0] < '0' || s[0] > '9') 6297 return (EINVAL); /* not a number */ 6298 n = s[0] - '0'; 6299 if (n & ~(PAUSE_TX | PAUSE_RX)) 6300 return (EINVAL); /* some other bit is set too */ 6301 6302 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6303 "t4PAUSE"); 6304 if (rc) 6305 return (rc); 6306 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) { 6307 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 6308 lc->requested_fc |= n; 6309 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6310 if (rc == 0) { 6311 lc->fc = lc->requested_fc; 6312 } 6313 } 6314 end_synchronized_op(sc, 0); 6315 } 6316 6317 return (rc); 6318 } 6319 6320 static int 6321 sysctl_fec(SYSCTL_HANDLER_ARGS) 6322 { 6323 struct port_info *pi = arg1; 6324 struct adapter *sc = pi->adapter; 6325 struct link_config *lc = &pi->link_cfg; 6326 int rc; 6327 6328 if (req->newptr == NULL) { 6329 struct sbuf *sb; 6330 static char *bits = "\20\1RS\2BASER_RS\3RESERVED"; 6331 6332 rc = sysctl_wire_old_buffer(req, 0); 6333 if (rc != 0) 6334 return(rc); 6335 6336 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6337 if (sb == NULL) 6338 return (ENOMEM); 6339 6340 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits); 6341 rc = sbuf_finish(sb); 6342 sbuf_delete(sb); 6343 } else { 6344 char s[2]; 6345 int n; 6346 6347 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC); 6348 s[1] = 0; 6349 6350 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6351 if (rc != 0) 6352 return(rc); 6353 6354 if (s[1] != 0) 6355 return (EINVAL); 6356 if (s[0] < '0' || s[0] > '9') 6357 return (EINVAL); /* not a number */ 6358 n = s[0] - '0'; 6359 if (n & ~M_FW_PORT_CAP_FEC) 6360 return (EINVAL); /* some other bit is set too */ 6361 6362 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6363 "t4fec"); 6364 if (rc) 6365 return (rc); 6366 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) { 6367 lc->requested_fec = n & 6368 G_FW_PORT_CAP_FEC(lc->supported); 6369 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6370 if (rc == 0) { 6371 lc->fec = lc->requested_fec; 6372 } 6373 } 6374 end_synchronized_op(sc, 0); 6375 } 6376 6377 return (rc); 6378 } 6379 6380 static int 6381 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 6382 { 6383 struct port_info *pi = arg1; 6384 struct adapter *sc = pi->adapter; 6385 struct link_config *lc = &pi->link_cfg; 6386 int rc, val, old; 6387 6388 if (lc->supported & FW_PORT_CAP_ANEG) 6389 val = lc->requested_aneg == AUTONEG_ENABLE ? 1 : 0; 6390 else 6391 val = -1; 6392 rc = sysctl_handle_int(oidp, &val, 0, req); 6393 if (rc != 0 || req->newptr == NULL) 6394 return (rc); 6395 if ((lc->supported & FW_PORT_CAP_ANEG) == 0) 6396 return (ENOTSUP); 6397 6398 if (val == 0) 6399 val = AUTONEG_DISABLE; 6400 else if (val == 1) 6401 val = AUTONEG_ENABLE; 6402 else 6403 return (EINVAL); 6404 if (lc->requested_aneg == val) 6405 return (0); /* no change */ 6406 6407 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6408 "t4aneg"); 6409 if (rc) 6410 return (rc); 6411 old = lc->requested_aneg; 6412 lc->requested_aneg = val; 6413 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6414 if (rc != 0) 6415 lc->requested_aneg = old; 6416 end_synchronized_op(sc, 0); 6417 return (rc); 6418 } 6419 6420 static int 6421 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 6422 { 6423 struct adapter *sc = arg1; 6424 int reg = arg2; 6425 uint64_t val; 6426 6427 val = t4_read_reg64(sc, reg); 6428 6429 return (sysctl_handle_64(oidp, &val, 0, req)); 6430 } 6431 6432 static int 6433 sysctl_temperature(SYSCTL_HANDLER_ARGS) 6434 { 6435 struct adapter *sc = arg1; 6436 int rc, t; 6437 uint32_t param, val; 6438 6439 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 6440 if (rc) 6441 return (rc); 6442 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6443 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 6444 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 6445 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6446 end_synchronized_op(sc, 0); 6447 if (rc) 6448 return (rc); 6449 6450 /* unknown is returned as 0 but we display -1 in that case */ 6451 t = val == 0 ? -1 : val; 6452 6453 rc = sysctl_handle_int(oidp, &t, 0, req); 6454 return (rc); 6455 } 6456 6457 #ifdef SBUF_DRAIN 6458 static int 6459 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 6460 { 6461 struct adapter *sc = arg1; 6462 struct sbuf *sb; 6463 int rc, i; 6464 uint16_t incr[NMTUS][NCCTRL_WIN]; 6465 static const char *dec_fac[] = { 6466 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 6467 "0.9375" 6468 }; 6469 6470 rc = sysctl_wire_old_buffer(req, 0); 6471 if (rc != 0) 6472 return (rc); 6473 6474 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6475 if (sb == NULL) 6476 return (ENOMEM); 6477 6478 t4_read_cong_tbl(sc, incr); 6479 6480 for (i = 0; i < NCCTRL_WIN; ++i) { 6481 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 6482 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 6483 incr[5][i], incr[6][i], incr[7][i]); 6484 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 6485 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 6486 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 6487 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 6488 } 6489 6490 rc = sbuf_finish(sb); 6491 sbuf_delete(sb); 6492 6493 return (rc); 6494 } 6495 6496 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 6497 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 6498 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 6499 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 6500 }; 6501 6502 static int 6503 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 6504 { 6505 struct adapter *sc = arg1; 6506 struct sbuf *sb; 6507 int rc, i, n, qid = arg2; 6508 uint32_t *buf, *p; 6509 char *qtype; 6510 u_int cim_num_obq = sc->chip_params->cim_num_obq; 6511 6512 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 6513 ("%s: bad qid %d\n", __func__, qid)); 6514 6515 if (qid < CIM_NUM_IBQ) { 6516 /* inbound queue */ 6517 qtype = "IBQ"; 6518 n = 4 * CIM_IBQ_SIZE; 6519 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6520 rc = t4_read_cim_ibq(sc, qid, buf, n); 6521 } else { 6522 /* outbound queue */ 6523 qtype = "OBQ"; 6524 qid -= CIM_NUM_IBQ; 6525 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 6526 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 6527 rc = t4_read_cim_obq(sc, qid, buf, n); 6528 } 6529 6530 if (rc < 0) { 6531 rc = -rc; 6532 goto done; 6533 } 6534 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 6535 6536 rc = sysctl_wire_old_buffer(req, 0); 6537 if (rc != 0) 6538 goto done; 6539 6540 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6541 if (sb == NULL) { 6542 rc = ENOMEM; 6543 goto done; 6544 } 6545 6546 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 6547 for (i = 0, p = buf; i < n; i += 16, p += 4) 6548 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 6549 p[2], p[3]); 6550 6551 rc = sbuf_finish(sb); 6552 sbuf_delete(sb); 6553 done: 6554 free(buf, M_CXGBE); 6555 return (rc); 6556 } 6557 6558 static int 6559 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 6560 { 6561 struct adapter *sc = arg1; 6562 u_int cfg; 6563 struct sbuf *sb; 6564 uint32_t *buf, *p; 6565 int rc; 6566 6567 MPASS(chip_id(sc) <= CHELSIO_T5); 6568 6569 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6570 if (rc != 0) 6571 return (rc); 6572 6573 rc = sysctl_wire_old_buffer(req, 0); 6574 if (rc != 0) 6575 return (rc); 6576 6577 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6578 if (sb == NULL) 6579 return (ENOMEM); 6580 6581 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6582 M_ZERO | M_WAITOK); 6583 6584 rc = -t4_cim_read_la(sc, buf, NULL); 6585 if (rc != 0) 6586 goto done; 6587 6588 sbuf_printf(sb, "Status Data PC%s", 6589 cfg & F_UPDBGLACAPTPCONLY ? "" : 6590 " LS0Stat LS0Addr LS0Data"); 6591 6592 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 6593 if (cfg & F_UPDBGLACAPTPCONLY) { 6594 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 6595 p[6], p[7]); 6596 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 6597 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 6598 p[4] & 0xff, p[5] >> 8); 6599 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 6600 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6601 p[1] & 0xf, p[2] >> 4); 6602 } else { 6603 sbuf_printf(sb, 6604 "\n %02x %x%07x %x%07x %08x %08x " 6605 "%08x%08x%08x%08x", 6606 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6607 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 6608 p[6], p[7]); 6609 } 6610 } 6611 6612 rc = sbuf_finish(sb); 6613 sbuf_delete(sb); 6614 done: 6615 free(buf, M_CXGBE); 6616 return (rc); 6617 } 6618 6619 static int 6620 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 6621 { 6622 struct adapter *sc = arg1; 6623 u_int cfg; 6624 struct sbuf *sb; 6625 uint32_t *buf, *p; 6626 int rc; 6627 6628 MPASS(chip_id(sc) > CHELSIO_T5); 6629 6630 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6631 if (rc != 0) 6632 return (rc); 6633 6634 rc = sysctl_wire_old_buffer(req, 0); 6635 if (rc != 0) 6636 return (rc); 6637 6638 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6639 if (sb == NULL) 6640 return (ENOMEM); 6641 6642 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6643 M_ZERO | M_WAITOK); 6644 6645 rc = -t4_cim_read_la(sc, buf, NULL); 6646 if (rc != 0) 6647 goto done; 6648 6649 sbuf_printf(sb, "Status Inst Data PC%s", 6650 cfg & F_UPDBGLACAPTPCONLY ? "" : 6651 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 6652 6653 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 6654 if (cfg & F_UPDBGLACAPTPCONLY) { 6655 sbuf_printf(sb, "\n %02x %08x %08x %08x", 6656 p[3] & 0xff, p[2], p[1], p[0]); 6657 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 6658 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 6659 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 6660 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 6661 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 6662 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 6663 p[6] >> 16); 6664 } else { 6665 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 6666 "%08x %08x %08x %08x %08x %08x", 6667 (p[9] >> 16) & 0xff, 6668 p[9] & 0xffff, p[8] >> 16, 6669 p[8] & 0xffff, p[7] >> 16, 6670 p[7] & 0xffff, p[6] >> 16, 6671 p[2], p[1], p[0], p[5], p[4], p[3]); 6672 } 6673 } 6674 6675 rc = sbuf_finish(sb); 6676 sbuf_delete(sb); 6677 done: 6678 free(buf, M_CXGBE); 6679 return (rc); 6680 } 6681 6682 static int 6683 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 6684 { 6685 struct adapter *sc = arg1; 6686 u_int i; 6687 struct sbuf *sb; 6688 uint32_t *buf, *p; 6689 int rc; 6690 6691 rc = sysctl_wire_old_buffer(req, 0); 6692 if (rc != 0) 6693 return (rc); 6694 6695 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6696 if (sb == NULL) 6697 return (ENOMEM); 6698 6699 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 6700 M_ZERO | M_WAITOK); 6701 6702 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 6703 p = buf; 6704 6705 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6706 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 6707 p[1], p[0]); 6708 } 6709 6710 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 6711 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6712 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 6713 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 6714 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 6715 (p[1] >> 2) | ((p[2] & 3) << 30), 6716 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 6717 p[0] & 1); 6718 } 6719 6720 rc = sbuf_finish(sb); 6721 sbuf_delete(sb); 6722 free(buf, M_CXGBE); 6723 return (rc); 6724 } 6725 6726 static int 6727 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 6728 { 6729 struct adapter *sc = arg1; 6730 u_int i; 6731 struct sbuf *sb; 6732 uint32_t *buf, *p; 6733 int rc; 6734 6735 rc = sysctl_wire_old_buffer(req, 0); 6736 if (rc != 0) 6737 return (rc); 6738 6739 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6740 if (sb == NULL) 6741 return (ENOMEM); 6742 6743 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 6744 M_ZERO | M_WAITOK); 6745 6746 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 6747 p = buf; 6748 6749 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 6750 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6751 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 6752 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 6753 p[4], p[3], p[2], p[1], p[0]); 6754 } 6755 6756 sbuf_printf(sb, "\n\nCntl ID Data"); 6757 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6758 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 6759 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 6760 } 6761 6762 rc = sbuf_finish(sb); 6763 sbuf_delete(sb); 6764 free(buf, M_CXGBE); 6765 return (rc); 6766 } 6767 6768 static int 6769 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 6770 { 6771 struct adapter *sc = arg1; 6772 struct sbuf *sb; 6773 int rc, i; 6774 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6775 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6776 uint16_t thres[CIM_NUM_IBQ]; 6777 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 6778 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 6779 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 6780 6781 cim_num_obq = sc->chip_params->cim_num_obq; 6782 if (is_t4(sc)) { 6783 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 6784 obq_rdaddr = A_UP_OBQ_0_REALADDR; 6785 } else { 6786 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 6787 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 6788 } 6789 nq = CIM_NUM_IBQ + cim_num_obq; 6790 6791 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 6792 if (rc == 0) 6793 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 6794 if (rc != 0) 6795 return (rc); 6796 6797 t4_read_cimq_cfg(sc, base, size, thres); 6798 6799 rc = sysctl_wire_old_buffer(req, 0); 6800 if (rc != 0) 6801 return (rc); 6802 6803 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6804 if (sb == NULL) 6805 return (ENOMEM); 6806 6807 sbuf_printf(sb, 6808 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 6809 6810 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 6811 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 6812 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 6813 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6814 G_QUEREMFLITS(p[2]) * 16); 6815 for ( ; i < nq; i++, p += 4, wr += 2) 6816 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 6817 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 6818 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6819 G_QUEREMFLITS(p[2]) * 16); 6820 6821 rc = sbuf_finish(sb); 6822 sbuf_delete(sb); 6823 6824 return (rc); 6825 } 6826 6827 static int 6828 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 6829 { 6830 struct adapter *sc = arg1; 6831 struct sbuf *sb; 6832 int rc; 6833 struct tp_cpl_stats stats; 6834 6835 rc = sysctl_wire_old_buffer(req, 0); 6836 if (rc != 0) 6837 return (rc); 6838 6839 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6840 if (sb == NULL) 6841 return (ENOMEM); 6842 6843 mtx_lock(&sc->reg_lock); 6844 t4_tp_get_cpl_stats(sc, &stats, 0); 6845 mtx_unlock(&sc->reg_lock); 6846 6847 if (sc->chip_params->nchan > 2) { 6848 sbuf_printf(sb, " channel 0 channel 1" 6849 " channel 2 channel 3"); 6850 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 6851 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 6852 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 6853 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 6854 } else { 6855 sbuf_printf(sb, " channel 0 channel 1"); 6856 sbuf_printf(sb, "\nCPL requests: %10u %10u", 6857 stats.req[0], stats.req[1]); 6858 sbuf_printf(sb, "\nCPL responses: %10u %10u", 6859 stats.rsp[0], stats.rsp[1]); 6860 } 6861 6862 rc = sbuf_finish(sb); 6863 sbuf_delete(sb); 6864 6865 return (rc); 6866 } 6867 6868 static int 6869 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 6870 { 6871 struct adapter *sc = arg1; 6872 struct sbuf *sb; 6873 int rc; 6874 struct tp_usm_stats stats; 6875 6876 rc = sysctl_wire_old_buffer(req, 0); 6877 if (rc != 0) 6878 return(rc); 6879 6880 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6881 if (sb == NULL) 6882 return (ENOMEM); 6883 6884 t4_get_usm_stats(sc, &stats, 1); 6885 6886 sbuf_printf(sb, "Frames: %u\n", stats.frames); 6887 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 6888 sbuf_printf(sb, "Drops: %u", stats.drops); 6889 6890 rc = sbuf_finish(sb); 6891 sbuf_delete(sb); 6892 6893 return (rc); 6894 } 6895 6896 static const char * const devlog_level_strings[] = { 6897 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 6898 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 6899 [FW_DEVLOG_LEVEL_ERR] = "ERR", 6900 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 6901 [FW_DEVLOG_LEVEL_INFO] = "INFO", 6902 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 6903 }; 6904 6905 static const char * const devlog_facility_strings[] = { 6906 [FW_DEVLOG_FACILITY_CORE] = "CORE", 6907 [FW_DEVLOG_FACILITY_CF] = "CF", 6908 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 6909 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 6910 [FW_DEVLOG_FACILITY_RES] = "RES", 6911 [FW_DEVLOG_FACILITY_HW] = "HW", 6912 [FW_DEVLOG_FACILITY_FLR] = "FLR", 6913 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 6914 [FW_DEVLOG_FACILITY_PHY] = "PHY", 6915 [FW_DEVLOG_FACILITY_MAC] = "MAC", 6916 [FW_DEVLOG_FACILITY_PORT] = "PORT", 6917 [FW_DEVLOG_FACILITY_VI] = "VI", 6918 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 6919 [FW_DEVLOG_FACILITY_ACL] = "ACL", 6920 [FW_DEVLOG_FACILITY_TM] = "TM", 6921 [FW_DEVLOG_FACILITY_QFC] = "QFC", 6922 [FW_DEVLOG_FACILITY_DCB] = "DCB", 6923 [FW_DEVLOG_FACILITY_ETH] = "ETH", 6924 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 6925 [FW_DEVLOG_FACILITY_RI] = "RI", 6926 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 6927 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 6928 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 6929 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 6930 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 6931 }; 6932 6933 static int 6934 sysctl_devlog(SYSCTL_HANDLER_ARGS) 6935 { 6936 struct adapter *sc = arg1; 6937 struct devlog_params *dparams = &sc->params.devlog; 6938 struct fw_devlog_e *buf, *e; 6939 int i, j, rc, nentries, first = 0; 6940 struct sbuf *sb; 6941 uint64_t ftstamp = UINT64_MAX; 6942 6943 if (dparams->addr == 0) 6944 return (ENXIO); 6945 6946 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 6947 if (buf == NULL) 6948 return (ENOMEM); 6949 6950 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 6951 if (rc != 0) 6952 goto done; 6953 6954 nentries = dparams->size / sizeof(struct fw_devlog_e); 6955 for (i = 0; i < nentries; i++) { 6956 e = &buf[i]; 6957 6958 if (e->timestamp == 0) 6959 break; /* end */ 6960 6961 e->timestamp = be64toh(e->timestamp); 6962 e->seqno = be32toh(e->seqno); 6963 for (j = 0; j < 8; j++) 6964 e->params[j] = be32toh(e->params[j]); 6965 6966 if (e->timestamp < ftstamp) { 6967 ftstamp = e->timestamp; 6968 first = i; 6969 } 6970 } 6971 6972 if (buf[first].timestamp == 0) 6973 goto done; /* nothing in the log */ 6974 6975 rc = sysctl_wire_old_buffer(req, 0); 6976 if (rc != 0) 6977 goto done; 6978 6979 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6980 if (sb == NULL) { 6981 rc = ENOMEM; 6982 goto done; 6983 } 6984 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 6985 "Seq#", "Tstamp", "Level", "Facility", "Message"); 6986 6987 i = first; 6988 do { 6989 e = &buf[i]; 6990 if (e->timestamp == 0) 6991 break; /* end */ 6992 6993 sbuf_printf(sb, "%10d %15ju %8s %8s ", 6994 e->seqno, e->timestamp, 6995 (e->level < nitems(devlog_level_strings) ? 6996 devlog_level_strings[e->level] : "UNKNOWN"), 6997 (e->facility < nitems(devlog_facility_strings) ? 6998 devlog_facility_strings[e->facility] : "UNKNOWN")); 6999 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7000 e->params[2], e->params[3], e->params[4], 7001 e->params[5], e->params[6], e->params[7]); 7002 7003 if (++i == nentries) 7004 i = 0; 7005 } while (i != first); 7006 7007 rc = sbuf_finish(sb); 7008 sbuf_delete(sb); 7009 done: 7010 free(buf, M_CXGBE); 7011 return (rc); 7012 } 7013 7014 static int 7015 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7016 { 7017 struct adapter *sc = arg1; 7018 struct sbuf *sb; 7019 int rc; 7020 struct tp_fcoe_stats stats[MAX_NCHAN]; 7021 int i, nchan = sc->chip_params->nchan; 7022 7023 rc = sysctl_wire_old_buffer(req, 0); 7024 if (rc != 0) 7025 return (rc); 7026 7027 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7028 if (sb == NULL) 7029 return (ENOMEM); 7030 7031 for (i = 0; i < nchan; i++) 7032 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7033 7034 if (nchan > 2) { 7035 sbuf_printf(sb, " channel 0 channel 1" 7036 " channel 2 channel 3"); 7037 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7038 stats[0].octets_ddp, stats[1].octets_ddp, 7039 stats[2].octets_ddp, stats[3].octets_ddp); 7040 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7041 stats[0].frames_ddp, stats[1].frames_ddp, 7042 stats[2].frames_ddp, stats[3].frames_ddp); 7043 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7044 stats[0].frames_drop, stats[1].frames_drop, 7045 stats[2].frames_drop, stats[3].frames_drop); 7046 } else { 7047 sbuf_printf(sb, " channel 0 channel 1"); 7048 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7049 stats[0].octets_ddp, stats[1].octets_ddp); 7050 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7051 stats[0].frames_ddp, stats[1].frames_ddp); 7052 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7053 stats[0].frames_drop, stats[1].frames_drop); 7054 } 7055 7056 rc = sbuf_finish(sb); 7057 sbuf_delete(sb); 7058 7059 return (rc); 7060 } 7061 7062 static int 7063 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7064 { 7065 struct adapter *sc = arg1; 7066 struct sbuf *sb; 7067 int rc, i; 7068 unsigned int map, kbps, ipg, mode; 7069 unsigned int pace_tab[NTX_SCHED]; 7070 7071 rc = sysctl_wire_old_buffer(req, 0); 7072 if (rc != 0) 7073 return (rc); 7074 7075 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7076 if (sb == NULL) 7077 return (ENOMEM); 7078 7079 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7080 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7081 t4_read_pace_tbl(sc, pace_tab); 7082 7083 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7084 "Class IPG (0.1 ns) Flow IPG (us)"); 7085 7086 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7087 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7088 sbuf_printf(sb, "\n %u %-5s %u ", i, 7089 (mode & (1 << i)) ? "flow" : "class", map & 3); 7090 if (kbps) 7091 sbuf_printf(sb, "%9u ", kbps); 7092 else 7093 sbuf_printf(sb, " disabled "); 7094 7095 if (ipg) 7096 sbuf_printf(sb, "%13u ", ipg); 7097 else 7098 sbuf_printf(sb, " disabled "); 7099 7100 if (pace_tab[i]) 7101 sbuf_printf(sb, "%10u", pace_tab[i]); 7102 else 7103 sbuf_printf(sb, " disabled"); 7104 } 7105 7106 rc = sbuf_finish(sb); 7107 sbuf_delete(sb); 7108 7109 return (rc); 7110 } 7111 7112 static int 7113 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7114 { 7115 struct adapter *sc = arg1; 7116 struct sbuf *sb; 7117 int rc, i, j; 7118 uint64_t *p0, *p1; 7119 struct lb_port_stats s[2]; 7120 static const char *stat_name[] = { 7121 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7122 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7123 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7124 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7125 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7126 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7127 "BG2FramesTrunc:", "BG3FramesTrunc:" 7128 }; 7129 7130 rc = sysctl_wire_old_buffer(req, 0); 7131 if (rc != 0) 7132 return (rc); 7133 7134 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7135 if (sb == NULL) 7136 return (ENOMEM); 7137 7138 memset(s, 0, sizeof(s)); 7139 7140 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7141 t4_get_lb_stats(sc, i, &s[0]); 7142 t4_get_lb_stats(sc, i + 1, &s[1]); 7143 7144 p0 = &s[0].octets; 7145 p1 = &s[1].octets; 7146 sbuf_printf(sb, "%s Loopback %u" 7147 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7148 7149 for (j = 0; j < nitems(stat_name); j++) 7150 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7151 *p0++, *p1++); 7152 } 7153 7154 rc = sbuf_finish(sb); 7155 sbuf_delete(sb); 7156 7157 return (rc); 7158 } 7159 7160 static int 7161 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7162 { 7163 int rc = 0; 7164 struct port_info *pi = arg1; 7165 struct link_config *lc = &pi->link_cfg; 7166 struct sbuf *sb; 7167 7168 rc = sysctl_wire_old_buffer(req, 0); 7169 if (rc != 0) 7170 return(rc); 7171 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7172 if (sb == NULL) 7173 return (ENOMEM); 7174 7175 if (lc->link_ok || lc->link_down_rc == 255) 7176 sbuf_printf(sb, "n/a"); 7177 else 7178 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7179 7180 rc = sbuf_finish(sb); 7181 sbuf_delete(sb); 7182 7183 return (rc); 7184 } 7185 7186 struct mem_desc { 7187 unsigned int base; 7188 unsigned int limit; 7189 unsigned int idx; 7190 }; 7191 7192 static int 7193 mem_desc_cmp(const void *a, const void *b) 7194 { 7195 return ((const struct mem_desc *)a)->base - 7196 ((const struct mem_desc *)b)->base; 7197 } 7198 7199 static void 7200 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7201 unsigned int to) 7202 { 7203 unsigned int size; 7204 7205 if (from == to) 7206 return; 7207 7208 size = to - from + 1; 7209 if (size == 0) 7210 return; 7211 7212 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7213 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7214 } 7215 7216 static int 7217 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7218 { 7219 struct adapter *sc = arg1; 7220 struct sbuf *sb; 7221 int rc, i, n; 7222 uint32_t lo, hi, used, alloc; 7223 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 7224 static const char *region[] = { 7225 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 7226 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 7227 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 7228 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 7229 "RQUDP region:", "PBL region:", "TXPBL region:", 7230 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 7231 "On-chip queues:", "TLS keys:", 7232 }; 7233 struct mem_desc avail[4]; 7234 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 7235 struct mem_desc *md = mem; 7236 7237 rc = sysctl_wire_old_buffer(req, 0); 7238 if (rc != 0) 7239 return (rc); 7240 7241 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7242 if (sb == NULL) 7243 return (ENOMEM); 7244 7245 for (i = 0; i < nitems(mem); i++) { 7246 mem[i].limit = 0; 7247 mem[i].idx = i; 7248 } 7249 7250 /* Find and sort the populated memory ranges */ 7251 i = 0; 7252 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 7253 if (lo & F_EDRAM0_ENABLE) { 7254 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 7255 avail[i].base = G_EDRAM0_BASE(hi) << 20; 7256 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 7257 avail[i].idx = 0; 7258 i++; 7259 } 7260 if (lo & F_EDRAM1_ENABLE) { 7261 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 7262 avail[i].base = G_EDRAM1_BASE(hi) << 20; 7263 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 7264 avail[i].idx = 1; 7265 i++; 7266 } 7267 if (lo & F_EXT_MEM_ENABLE) { 7268 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 7269 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 7270 avail[i].limit = avail[i].base + 7271 (G_EXT_MEM_SIZE(hi) << 20); 7272 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 7273 i++; 7274 } 7275 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 7276 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 7277 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 7278 avail[i].limit = avail[i].base + 7279 (G_EXT_MEM1_SIZE(hi) << 20); 7280 avail[i].idx = 4; 7281 i++; 7282 } 7283 if (!i) /* no memory available */ 7284 return 0; 7285 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 7286 7287 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 7288 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 7289 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 7290 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 7291 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 7292 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 7293 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 7294 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 7295 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 7296 7297 /* the next few have explicit upper bounds */ 7298 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 7299 md->limit = md->base - 1 + 7300 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 7301 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 7302 md++; 7303 7304 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 7305 md->limit = md->base - 1 + 7306 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 7307 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 7308 md++; 7309 7310 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7311 if (chip_id(sc) <= CHELSIO_T5) 7312 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 7313 else 7314 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 7315 md->limit = 0; 7316 } else { 7317 md->base = 0; 7318 md->idx = nitems(region); /* hide it */ 7319 } 7320 md++; 7321 7322 #define ulp_region(reg) \ 7323 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 7324 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 7325 7326 ulp_region(RX_ISCSI); 7327 ulp_region(RX_TDDP); 7328 ulp_region(TX_TPT); 7329 ulp_region(RX_STAG); 7330 ulp_region(RX_RQ); 7331 ulp_region(RX_RQUDP); 7332 ulp_region(RX_PBL); 7333 ulp_region(TX_PBL); 7334 #undef ulp_region 7335 7336 md->base = 0; 7337 md->idx = nitems(region); 7338 if (!is_t4(sc)) { 7339 uint32_t size = 0; 7340 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 7341 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 7342 7343 if (is_t5(sc)) { 7344 if (sge_ctrl & F_VFIFO_ENABLE) 7345 size = G_DBVFIFO_SIZE(fifo_size); 7346 } else 7347 size = G_T6_DBVFIFO_SIZE(fifo_size); 7348 7349 if (size) { 7350 md->base = G_BASEADDR(t4_read_reg(sc, 7351 A_SGE_DBVFIFO_BADDR)); 7352 md->limit = md->base + (size << 2) - 1; 7353 } 7354 } 7355 md++; 7356 7357 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 7358 md->limit = 0; 7359 md++; 7360 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 7361 md->limit = 0; 7362 md++; 7363 7364 md->base = sc->vres.ocq.start; 7365 if (sc->vres.ocq.size) 7366 md->limit = md->base + sc->vres.ocq.size - 1; 7367 else 7368 md->idx = nitems(region); /* hide it */ 7369 md++; 7370 7371 md->base = sc->vres.key.start; 7372 if (sc->vres.key.size) 7373 md->limit = md->base + sc->vres.key.size - 1; 7374 else 7375 md->idx = nitems(region); /* hide it */ 7376 md++; 7377 7378 /* add any address-space holes, there can be up to 3 */ 7379 for (n = 0; n < i - 1; n++) 7380 if (avail[n].limit < avail[n + 1].base) 7381 (md++)->base = avail[n].limit; 7382 if (avail[n].limit) 7383 (md++)->base = avail[n].limit; 7384 7385 n = md - mem; 7386 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 7387 7388 for (lo = 0; lo < i; lo++) 7389 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 7390 avail[lo].limit - 1); 7391 7392 sbuf_printf(sb, "\n"); 7393 for (i = 0; i < n; i++) { 7394 if (mem[i].idx >= nitems(region)) 7395 continue; /* skip holes */ 7396 if (!mem[i].limit) 7397 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 7398 mem_region_show(sb, region[mem[i].idx], mem[i].base, 7399 mem[i].limit); 7400 } 7401 7402 sbuf_printf(sb, "\n"); 7403 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 7404 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 7405 mem_region_show(sb, "uP RAM:", lo, hi); 7406 7407 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 7408 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 7409 mem_region_show(sb, "uP Extmem2:", lo, hi); 7410 7411 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 7412 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 7413 G_PMRXMAXPAGE(lo), 7414 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 7415 (lo & F_PMRXNUMCHN) ? 2 : 1); 7416 7417 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 7418 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 7419 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 7420 G_PMTXMAXPAGE(lo), 7421 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 7422 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 7423 sbuf_printf(sb, "%u p-structs\n", 7424 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 7425 7426 for (i = 0; i < 4; i++) { 7427 if (chip_id(sc) > CHELSIO_T5) 7428 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 7429 else 7430 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 7431 if (is_t5(sc)) { 7432 used = G_T5_USED(lo); 7433 alloc = G_T5_ALLOC(lo); 7434 } else { 7435 used = G_USED(lo); 7436 alloc = G_ALLOC(lo); 7437 } 7438 /* For T6 these are MAC buffer groups */ 7439 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 7440 i, used, alloc); 7441 } 7442 for (i = 0; i < sc->chip_params->nchan; i++) { 7443 if (chip_id(sc) > CHELSIO_T5) 7444 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 7445 else 7446 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 7447 if (is_t5(sc)) { 7448 used = G_T5_USED(lo); 7449 alloc = G_T5_ALLOC(lo); 7450 } else { 7451 used = G_USED(lo); 7452 alloc = G_ALLOC(lo); 7453 } 7454 /* For T6 these are MAC buffer groups */ 7455 sbuf_printf(sb, 7456 "\nLoopback %d using %u pages out of %u allocated", 7457 i, used, alloc); 7458 } 7459 7460 rc = sbuf_finish(sb); 7461 sbuf_delete(sb); 7462 7463 return (rc); 7464 } 7465 7466 static inline void 7467 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 7468 { 7469 *mask = x | y; 7470 y = htobe64(y); 7471 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 7472 } 7473 7474 static int 7475 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 7476 { 7477 struct adapter *sc = arg1; 7478 struct sbuf *sb; 7479 int rc, i; 7480 7481 MPASS(chip_id(sc) <= CHELSIO_T5); 7482 7483 rc = sysctl_wire_old_buffer(req, 0); 7484 if (rc != 0) 7485 return (rc); 7486 7487 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7488 if (sb == NULL) 7489 return (ENOMEM); 7490 7491 sbuf_printf(sb, 7492 "Idx Ethernet address Mask Vld Ports PF" 7493 " VF Replication P0 P1 P2 P3 ML"); 7494 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7495 uint64_t tcamx, tcamy, mask; 7496 uint32_t cls_lo, cls_hi; 7497 uint8_t addr[ETHER_ADDR_LEN]; 7498 7499 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 7500 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 7501 if (tcamx & tcamy) 7502 continue; 7503 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7504 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7505 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7506 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 7507 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 7508 addr[3], addr[4], addr[5], (uintmax_t)mask, 7509 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 7510 G_PORTMAP(cls_hi), G_PF(cls_lo), 7511 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 7512 7513 if (cls_lo & F_REPLICATE) { 7514 struct fw_ldst_cmd ldst_cmd; 7515 7516 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7517 ldst_cmd.op_to_addrspace = 7518 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7519 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7520 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7521 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7522 ldst_cmd.u.mps.rplc.fid_idx = 7523 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7524 V_FW_LDST_CMD_IDX(i)); 7525 7526 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7527 "t4mps"); 7528 if (rc) 7529 break; 7530 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7531 sizeof(ldst_cmd), &ldst_cmd); 7532 end_synchronized_op(sc, 0); 7533 7534 if (rc != 0) { 7535 sbuf_printf(sb, "%36d", rc); 7536 rc = 0; 7537 } else { 7538 sbuf_printf(sb, " %08x %08x %08x %08x", 7539 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7540 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7541 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7542 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7543 } 7544 } else 7545 sbuf_printf(sb, "%36s", ""); 7546 7547 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 7548 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 7549 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 7550 } 7551 7552 if (rc) 7553 (void) sbuf_finish(sb); 7554 else 7555 rc = sbuf_finish(sb); 7556 sbuf_delete(sb); 7557 7558 return (rc); 7559 } 7560 7561 static int 7562 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 7563 { 7564 struct adapter *sc = arg1; 7565 struct sbuf *sb; 7566 int rc, i; 7567 7568 MPASS(chip_id(sc) > CHELSIO_T5); 7569 7570 rc = sysctl_wire_old_buffer(req, 0); 7571 if (rc != 0) 7572 return (rc); 7573 7574 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7575 if (sb == NULL) 7576 return (ENOMEM); 7577 7578 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 7579 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 7580 " Replication" 7581 " P0 P1 P2 P3 ML\n"); 7582 7583 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7584 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 7585 uint16_t ivlan; 7586 uint64_t tcamx, tcamy, val, mask; 7587 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 7588 uint8_t addr[ETHER_ADDR_LEN]; 7589 7590 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 7591 if (i < 256) 7592 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 7593 else 7594 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 7595 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7596 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7597 tcamy = G_DMACH(val) << 32; 7598 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7599 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7600 lookup_type = G_DATALKPTYPE(data2); 7601 port_num = G_DATAPORTNUM(data2); 7602 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7603 /* Inner header VNI */ 7604 vniy = ((data2 & F_DATAVIDH2) << 23) | 7605 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7606 dip_hit = data2 & F_DATADIPHIT; 7607 vlan_vld = 0; 7608 } else { 7609 vniy = 0; 7610 dip_hit = 0; 7611 vlan_vld = data2 & F_DATAVIDH2; 7612 ivlan = G_VIDL(val); 7613 } 7614 7615 ctl |= V_CTLXYBITSEL(1); 7616 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7617 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7618 tcamx = G_DMACH(val) << 32; 7619 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7620 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7621 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7622 /* Inner header VNI mask */ 7623 vnix = ((data2 & F_DATAVIDH2) << 23) | 7624 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7625 } else 7626 vnix = 0; 7627 7628 if (tcamx & tcamy) 7629 continue; 7630 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7631 7632 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7633 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7634 7635 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7636 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7637 "%012jx %06x %06x - - %3c" 7638 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 7639 addr[1], addr[2], addr[3], addr[4], addr[5], 7640 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 7641 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7642 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7643 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7644 } else { 7645 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7646 "%012jx - - ", i, addr[0], addr[1], 7647 addr[2], addr[3], addr[4], addr[5], 7648 (uintmax_t)mask); 7649 7650 if (vlan_vld) 7651 sbuf_printf(sb, "%4u Y ", ivlan); 7652 else 7653 sbuf_printf(sb, " - N "); 7654 7655 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 7656 lookup_type ? 'I' : 'O', port_num, 7657 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7658 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7659 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7660 } 7661 7662 7663 if (cls_lo & F_T6_REPLICATE) { 7664 struct fw_ldst_cmd ldst_cmd; 7665 7666 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7667 ldst_cmd.op_to_addrspace = 7668 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7669 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7670 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7671 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7672 ldst_cmd.u.mps.rplc.fid_idx = 7673 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7674 V_FW_LDST_CMD_IDX(i)); 7675 7676 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7677 "t6mps"); 7678 if (rc) 7679 break; 7680 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7681 sizeof(ldst_cmd), &ldst_cmd); 7682 end_synchronized_op(sc, 0); 7683 7684 if (rc != 0) { 7685 sbuf_printf(sb, "%72d", rc); 7686 rc = 0; 7687 } else { 7688 sbuf_printf(sb, " %08x %08x %08x %08x" 7689 " %08x %08x %08x %08x", 7690 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 7691 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 7692 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 7693 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 7694 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7695 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7696 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7697 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7698 } 7699 } else 7700 sbuf_printf(sb, "%72s", ""); 7701 7702 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 7703 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 7704 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 7705 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 7706 } 7707 7708 if (rc) 7709 (void) sbuf_finish(sb); 7710 else 7711 rc = sbuf_finish(sb); 7712 sbuf_delete(sb); 7713 7714 return (rc); 7715 } 7716 7717 static int 7718 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 7719 { 7720 struct adapter *sc = arg1; 7721 struct sbuf *sb; 7722 int rc; 7723 uint16_t mtus[NMTUS]; 7724 7725 rc = sysctl_wire_old_buffer(req, 0); 7726 if (rc != 0) 7727 return (rc); 7728 7729 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7730 if (sb == NULL) 7731 return (ENOMEM); 7732 7733 t4_read_mtu_tbl(sc, mtus, NULL); 7734 7735 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 7736 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 7737 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 7738 mtus[14], mtus[15]); 7739 7740 rc = sbuf_finish(sb); 7741 sbuf_delete(sb); 7742 7743 return (rc); 7744 } 7745 7746 static int 7747 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 7748 { 7749 struct adapter *sc = arg1; 7750 struct sbuf *sb; 7751 int rc, i; 7752 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 7753 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 7754 static const char *tx_stats[MAX_PM_NSTATS] = { 7755 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 7756 "Tx FIFO wait", NULL, "Tx latency" 7757 }; 7758 static const char *rx_stats[MAX_PM_NSTATS] = { 7759 "Read:", "Write bypass:", "Write mem:", "Flush:", 7760 "Rx FIFO wait", NULL, "Rx latency" 7761 }; 7762 7763 rc = sysctl_wire_old_buffer(req, 0); 7764 if (rc != 0) 7765 return (rc); 7766 7767 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7768 if (sb == NULL) 7769 return (ENOMEM); 7770 7771 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 7772 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 7773 7774 sbuf_printf(sb, " Tx pcmds Tx bytes"); 7775 for (i = 0; i < 4; i++) { 7776 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7777 tx_cyc[i]); 7778 } 7779 7780 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 7781 for (i = 0; i < 4; i++) { 7782 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7783 rx_cyc[i]); 7784 } 7785 7786 if (chip_id(sc) > CHELSIO_T5) { 7787 sbuf_printf(sb, 7788 "\n Total wait Total occupancy"); 7789 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7790 tx_cyc[i]); 7791 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7792 rx_cyc[i]); 7793 7794 i += 2; 7795 MPASS(i < nitems(tx_stats)); 7796 7797 sbuf_printf(sb, 7798 "\n Reads Total wait"); 7799 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7800 tx_cyc[i]); 7801 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7802 rx_cyc[i]); 7803 } 7804 7805 rc = sbuf_finish(sb); 7806 sbuf_delete(sb); 7807 7808 return (rc); 7809 } 7810 7811 static int 7812 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 7813 { 7814 struct adapter *sc = arg1; 7815 struct sbuf *sb; 7816 int rc; 7817 struct tp_rdma_stats stats; 7818 7819 rc = sysctl_wire_old_buffer(req, 0); 7820 if (rc != 0) 7821 return (rc); 7822 7823 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7824 if (sb == NULL) 7825 return (ENOMEM); 7826 7827 mtx_lock(&sc->reg_lock); 7828 t4_tp_get_rdma_stats(sc, &stats, 0); 7829 mtx_unlock(&sc->reg_lock); 7830 7831 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 7832 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 7833 7834 rc = sbuf_finish(sb); 7835 sbuf_delete(sb); 7836 7837 return (rc); 7838 } 7839 7840 static int 7841 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 7842 { 7843 struct adapter *sc = arg1; 7844 struct sbuf *sb; 7845 int rc; 7846 struct tp_tcp_stats v4, v6; 7847 7848 rc = sysctl_wire_old_buffer(req, 0); 7849 if (rc != 0) 7850 return (rc); 7851 7852 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7853 if (sb == NULL) 7854 return (ENOMEM); 7855 7856 mtx_lock(&sc->reg_lock); 7857 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 7858 mtx_unlock(&sc->reg_lock); 7859 7860 sbuf_printf(sb, 7861 " IP IPv6\n"); 7862 sbuf_printf(sb, "OutRsts: %20u %20u\n", 7863 v4.tcp_out_rsts, v6.tcp_out_rsts); 7864 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 7865 v4.tcp_in_segs, v6.tcp_in_segs); 7866 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 7867 v4.tcp_out_segs, v6.tcp_out_segs); 7868 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 7869 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 7870 7871 rc = sbuf_finish(sb); 7872 sbuf_delete(sb); 7873 7874 return (rc); 7875 } 7876 7877 static int 7878 sysctl_tids(SYSCTL_HANDLER_ARGS) 7879 { 7880 struct adapter *sc = arg1; 7881 struct sbuf *sb; 7882 int rc; 7883 struct tid_info *t = &sc->tids; 7884 7885 rc = sysctl_wire_old_buffer(req, 0); 7886 if (rc != 0) 7887 return (rc); 7888 7889 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7890 if (sb == NULL) 7891 return (ENOMEM); 7892 7893 if (t->natids) { 7894 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 7895 t->atids_in_use); 7896 } 7897 7898 if (t->ntids) { 7899 sbuf_printf(sb, "TID range: "); 7900 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7901 uint32_t b, hb; 7902 7903 if (chip_id(sc) <= CHELSIO_T5) { 7904 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 7905 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 7906 } else { 7907 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 7908 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 7909 } 7910 7911 if (b) 7912 sbuf_printf(sb, "0-%u, ", b - 1); 7913 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 7914 } else 7915 sbuf_printf(sb, "0-%u", t->ntids - 1); 7916 sbuf_printf(sb, ", in use: %u\n", 7917 atomic_load_acq_int(&t->tids_in_use)); 7918 } 7919 7920 if (t->nstids) { 7921 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 7922 t->stid_base + t->nstids - 1, t->stids_in_use); 7923 } 7924 7925 if (t->nftids) { 7926 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 7927 t->ftid_base + t->nftids - 1); 7928 } 7929 7930 if (t->netids) { 7931 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 7932 t->etid_base + t->netids - 1); 7933 } 7934 7935 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 7936 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 7937 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 7938 7939 rc = sbuf_finish(sb); 7940 sbuf_delete(sb); 7941 7942 return (rc); 7943 } 7944 7945 static int 7946 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 7947 { 7948 struct adapter *sc = arg1; 7949 struct sbuf *sb; 7950 int rc; 7951 struct tp_err_stats stats; 7952 7953 rc = sysctl_wire_old_buffer(req, 0); 7954 if (rc != 0) 7955 return (rc); 7956 7957 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7958 if (sb == NULL) 7959 return (ENOMEM); 7960 7961 mtx_lock(&sc->reg_lock); 7962 t4_tp_get_err_stats(sc, &stats, 0); 7963 mtx_unlock(&sc->reg_lock); 7964 7965 if (sc->chip_params->nchan > 2) { 7966 sbuf_printf(sb, " channel 0 channel 1" 7967 " channel 2 channel 3\n"); 7968 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 7969 stats.mac_in_errs[0], stats.mac_in_errs[1], 7970 stats.mac_in_errs[2], stats.mac_in_errs[3]); 7971 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 7972 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 7973 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 7974 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 7975 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 7976 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 7977 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 7978 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 7979 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 7980 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 7981 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 7982 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 7983 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 7984 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 7985 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 7986 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 7987 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 7988 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 7989 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 7990 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 7991 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 7992 } else { 7993 sbuf_printf(sb, " channel 0 channel 1\n"); 7994 sbuf_printf(sb, "macInErrs: %10u %10u\n", 7995 stats.mac_in_errs[0], stats.mac_in_errs[1]); 7996 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 7997 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 7998 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 7999 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8000 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8001 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8002 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8003 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8004 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8005 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8006 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8007 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8008 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8009 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8010 } 8011 8012 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8013 stats.ofld_no_neigh, stats.ofld_cong_defer); 8014 8015 rc = sbuf_finish(sb); 8016 sbuf_delete(sb); 8017 8018 return (rc); 8019 } 8020 8021 static int 8022 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8023 { 8024 struct adapter *sc = arg1; 8025 struct tp_params *tpp = &sc->params.tp; 8026 u_int mask; 8027 int rc; 8028 8029 mask = tpp->la_mask >> 16; 8030 rc = sysctl_handle_int(oidp, &mask, 0, req); 8031 if (rc != 0 || req->newptr == NULL) 8032 return (rc); 8033 if (mask > 0xffff) 8034 return (EINVAL); 8035 tpp->la_mask = mask << 16; 8036 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8037 8038 return (0); 8039 } 8040 8041 struct field_desc { 8042 const char *name; 8043 u_int start; 8044 u_int width; 8045 }; 8046 8047 static void 8048 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8049 { 8050 char buf[32]; 8051 int line_size = 0; 8052 8053 while (f->name) { 8054 uint64_t mask = (1ULL << f->width) - 1; 8055 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8056 ((uintmax_t)v >> f->start) & mask); 8057 8058 if (line_size + len >= 79) { 8059 line_size = 8; 8060 sbuf_printf(sb, "\n "); 8061 } 8062 sbuf_printf(sb, "%s ", buf); 8063 line_size += len + 1; 8064 f++; 8065 } 8066 sbuf_printf(sb, "\n"); 8067 } 8068 8069 static const struct field_desc tp_la0[] = { 8070 { "RcfOpCodeOut", 60, 4 }, 8071 { "State", 56, 4 }, 8072 { "WcfState", 52, 4 }, 8073 { "RcfOpcSrcOut", 50, 2 }, 8074 { "CRxError", 49, 1 }, 8075 { "ERxError", 48, 1 }, 8076 { "SanityFailed", 47, 1 }, 8077 { "SpuriousMsg", 46, 1 }, 8078 { "FlushInputMsg", 45, 1 }, 8079 { "FlushInputCpl", 44, 1 }, 8080 { "RssUpBit", 43, 1 }, 8081 { "RssFilterHit", 42, 1 }, 8082 { "Tid", 32, 10 }, 8083 { "InitTcb", 31, 1 }, 8084 { "LineNumber", 24, 7 }, 8085 { "Emsg", 23, 1 }, 8086 { "EdataOut", 22, 1 }, 8087 { "Cmsg", 21, 1 }, 8088 { "CdataOut", 20, 1 }, 8089 { "EreadPdu", 19, 1 }, 8090 { "CreadPdu", 18, 1 }, 8091 { "TunnelPkt", 17, 1 }, 8092 { "RcfPeerFin", 16, 1 }, 8093 { "RcfReasonOut", 12, 4 }, 8094 { "TxCchannel", 10, 2 }, 8095 { "RcfTxChannel", 8, 2 }, 8096 { "RxEchannel", 6, 2 }, 8097 { "RcfRxChannel", 5, 1 }, 8098 { "RcfDataOutSrdy", 4, 1 }, 8099 { "RxDvld", 3, 1 }, 8100 { "RxOoDvld", 2, 1 }, 8101 { "RxCongestion", 1, 1 }, 8102 { "TxCongestion", 0, 1 }, 8103 { NULL } 8104 }; 8105 8106 static const struct field_desc tp_la1[] = { 8107 { "CplCmdIn", 56, 8 }, 8108 { "CplCmdOut", 48, 8 }, 8109 { "ESynOut", 47, 1 }, 8110 { "EAckOut", 46, 1 }, 8111 { "EFinOut", 45, 1 }, 8112 { "ERstOut", 44, 1 }, 8113 { "SynIn", 43, 1 }, 8114 { "AckIn", 42, 1 }, 8115 { "FinIn", 41, 1 }, 8116 { "RstIn", 40, 1 }, 8117 { "DataIn", 39, 1 }, 8118 { "DataInVld", 38, 1 }, 8119 { "PadIn", 37, 1 }, 8120 { "RxBufEmpty", 36, 1 }, 8121 { "RxDdp", 35, 1 }, 8122 { "RxFbCongestion", 34, 1 }, 8123 { "TxFbCongestion", 33, 1 }, 8124 { "TxPktSumSrdy", 32, 1 }, 8125 { "RcfUlpType", 28, 4 }, 8126 { "Eread", 27, 1 }, 8127 { "Ebypass", 26, 1 }, 8128 { "Esave", 25, 1 }, 8129 { "Static0", 24, 1 }, 8130 { "Cread", 23, 1 }, 8131 { "Cbypass", 22, 1 }, 8132 { "Csave", 21, 1 }, 8133 { "CPktOut", 20, 1 }, 8134 { "RxPagePoolFull", 18, 2 }, 8135 { "RxLpbkPkt", 17, 1 }, 8136 { "TxLpbkPkt", 16, 1 }, 8137 { "RxVfValid", 15, 1 }, 8138 { "SynLearned", 14, 1 }, 8139 { "SetDelEntry", 13, 1 }, 8140 { "SetInvEntry", 12, 1 }, 8141 { "CpcmdDvld", 11, 1 }, 8142 { "CpcmdSave", 10, 1 }, 8143 { "RxPstructsFull", 8, 2 }, 8144 { "EpcmdDvld", 7, 1 }, 8145 { "EpcmdFlush", 6, 1 }, 8146 { "EpcmdTrimPrefix", 5, 1 }, 8147 { "EpcmdTrimPostfix", 4, 1 }, 8148 { "ERssIp4Pkt", 3, 1 }, 8149 { "ERssIp6Pkt", 2, 1 }, 8150 { "ERssTcpUdpPkt", 1, 1 }, 8151 { "ERssFceFipPkt", 0, 1 }, 8152 { NULL } 8153 }; 8154 8155 static const struct field_desc tp_la2[] = { 8156 { "CplCmdIn", 56, 8 }, 8157 { "MpsVfVld", 55, 1 }, 8158 { "MpsPf", 52, 3 }, 8159 { "MpsVf", 44, 8 }, 8160 { "SynIn", 43, 1 }, 8161 { "AckIn", 42, 1 }, 8162 { "FinIn", 41, 1 }, 8163 { "RstIn", 40, 1 }, 8164 { "DataIn", 39, 1 }, 8165 { "DataInVld", 38, 1 }, 8166 { "PadIn", 37, 1 }, 8167 { "RxBufEmpty", 36, 1 }, 8168 { "RxDdp", 35, 1 }, 8169 { "RxFbCongestion", 34, 1 }, 8170 { "TxFbCongestion", 33, 1 }, 8171 { "TxPktSumSrdy", 32, 1 }, 8172 { "RcfUlpType", 28, 4 }, 8173 { "Eread", 27, 1 }, 8174 { "Ebypass", 26, 1 }, 8175 { "Esave", 25, 1 }, 8176 { "Static0", 24, 1 }, 8177 { "Cread", 23, 1 }, 8178 { "Cbypass", 22, 1 }, 8179 { "Csave", 21, 1 }, 8180 { "CPktOut", 20, 1 }, 8181 { "RxPagePoolFull", 18, 2 }, 8182 { "RxLpbkPkt", 17, 1 }, 8183 { "TxLpbkPkt", 16, 1 }, 8184 { "RxVfValid", 15, 1 }, 8185 { "SynLearned", 14, 1 }, 8186 { "SetDelEntry", 13, 1 }, 8187 { "SetInvEntry", 12, 1 }, 8188 { "CpcmdDvld", 11, 1 }, 8189 { "CpcmdSave", 10, 1 }, 8190 { "RxPstructsFull", 8, 2 }, 8191 { "EpcmdDvld", 7, 1 }, 8192 { "EpcmdFlush", 6, 1 }, 8193 { "EpcmdTrimPrefix", 5, 1 }, 8194 { "EpcmdTrimPostfix", 4, 1 }, 8195 { "ERssIp4Pkt", 3, 1 }, 8196 { "ERssIp6Pkt", 2, 1 }, 8197 { "ERssTcpUdpPkt", 1, 1 }, 8198 { "ERssFceFipPkt", 0, 1 }, 8199 { NULL } 8200 }; 8201 8202 static void 8203 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8204 { 8205 8206 field_desc_show(sb, *p, tp_la0); 8207 } 8208 8209 static void 8210 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8211 { 8212 8213 if (idx) 8214 sbuf_printf(sb, "\n"); 8215 field_desc_show(sb, p[0], tp_la0); 8216 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8217 field_desc_show(sb, p[1], tp_la0); 8218 } 8219 8220 static void 8221 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 8222 { 8223 8224 if (idx) 8225 sbuf_printf(sb, "\n"); 8226 field_desc_show(sb, p[0], tp_la0); 8227 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8228 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 8229 } 8230 8231 static int 8232 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 8233 { 8234 struct adapter *sc = arg1; 8235 struct sbuf *sb; 8236 uint64_t *buf, *p; 8237 int rc; 8238 u_int i, inc; 8239 void (*show_func)(struct sbuf *, uint64_t *, int); 8240 8241 rc = sysctl_wire_old_buffer(req, 0); 8242 if (rc != 0) 8243 return (rc); 8244 8245 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8246 if (sb == NULL) 8247 return (ENOMEM); 8248 8249 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 8250 8251 t4_tp_read_la(sc, buf, NULL); 8252 p = buf; 8253 8254 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 8255 case 2: 8256 inc = 2; 8257 show_func = tp_la_show2; 8258 break; 8259 case 3: 8260 inc = 2; 8261 show_func = tp_la_show3; 8262 break; 8263 default: 8264 inc = 1; 8265 show_func = tp_la_show; 8266 } 8267 8268 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 8269 (*show_func)(sb, p, i); 8270 8271 rc = sbuf_finish(sb); 8272 sbuf_delete(sb); 8273 free(buf, M_CXGBE); 8274 return (rc); 8275 } 8276 8277 static int 8278 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 8279 { 8280 struct adapter *sc = arg1; 8281 struct sbuf *sb; 8282 int rc; 8283 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 8284 8285 rc = sysctl_wire_old_buffer(req, 0); 8286 if (rc != 0) 8287 return (rc); 8288 8289 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8290 if (sb == NULL) 8291 return (ENOMEM); 8292 8293 t4_get_chan_txrate(sc, nrate, orate); 8294 8295 if (sc->chip_params->nchan > 2) { 8296 sbuf_printf(sb, " channel 0 channel 1" 8297 " channel 2 channel 3\n"); 8298 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 8299 nrate[0], nrate[1], nrate[2], nrate[3]); 8300 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 8301 orate[0], orate[1], orate[2], orate[3]); 8302 } else { 8303 sbuf_printf(sb, " channel 0 channel 1\n"); 8304 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 8305 nrate[0], nrate[1]); 8306 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 8307 orate[0], orate[1]); 8308 } 8309 8310 rc = sbuf_finish(sb); 8311 sbuf_delete(sb); 8312 8313 return (rc); 8314 } 8315 8316 static int 8317 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 8318 { 8319 struct adapter *sc = arg1; 8320 struct sbuf *sb; 8321 uint32_t *buf, *p; 8322 int rc, i; 8323 8324 rc = sysctl_wire_old_buffer(req, 0); 8325 if (rc != 0) 8326 return (rc); 8327 8328 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8329 if (sb == NULL) 8330 return (ENOMEM); 8331 8332 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 8333 M_ZERO | M_WAITOK); 8334 8335 t4_ulprx_read_la(sc, buf); 8336 p = buf; 8337 8338 sbuf_printf(sb, " Pcmd Type Message" 8339 " Data"); 8340 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 8341 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 8342 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 8343 } 8344 8345 rc = sbuf_finish(sb); 8346 sbuf_delete(sb); 8347 free(buf, M_CXGBE); 8348 return (rc); 8349 } 8350 8351 static int 8352 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 8353 { 8354 struct adapter *sc = arg1; 8355 struct sbuf *sb; 8356 int rc, v; 8357 8358 MPASS(chip_id(sc) >= CHELSIO_T5); 8359 8360 rc = sysctl_wire_old_buffer(req, 0); 8361 if (rc != 0) 8362 return (rc); 8363 8364 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8365 if (sb == NULL) 8366 return (ENOMEM); 8367 8368 v = t4_read_reg(sc, A_SGE_STAT_CFG); 8369 if (G_STATSOURCE_T5(v) == 7) { 8370 int mode; 8371 8372 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 8373 if (mode == 0) { 8374 sbuf_printf(sb, "total %d, incomplete %d", 8375 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8376 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8377 } else if (mode == 1) { 8378 sbuf_printf(sb, "total %d, data overflow %d", 8379 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8380 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8381 } else { 8382 sbuf_printf(sb, "unknown mode %d", mode); 8383 } 8384 } 8385 rc = sbuf_finish(sb); 8386 sbuf_delete(sb); 8387 8388 return (rc); 8389 } 8390 8391 static int 8392 sysctl_tc_params(SYSCTL_HANDLER_ARGS) 8393 { 8394 struct adapter *sc = arg1; 8395 struct tx_cl_rl_params tc; 8396 struct sbuf *sb; 8397 int i, rc, port_id, mbps, gbps; 8398 8399 rc = sysctl_wire_old_buffer(req, 0); 8400 if (rc != 0) 8401 return (rc); 8402 8403 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8404 if (sb == NULL) 8405 return (ENOMEM); 8406 8407 port_id = arg2 >> 16; 8408 MPASS(port_id < sc->params.nports); 8409 MPASS(sc->port[port_id] != NULL); 8410 i = arg2 & 0xffff; 8411 MPASS(i < sc->chip_params->nsched_cls); 8412 8413 mtx_lock(&sc->tc_lock); 8414 tc = sc->port[port_id]->sched_params->cl_rl[i]; 8415 mtx_unlock(&sc->tc_lock); 8416 8417 if (tc.flags & TX_CLRL_ERROR) { 8418 sbuf_printf(sb, "error"); 8419 goto done; 8420 } 8421 8422 if (tc.ratemode == SCHED_CLASS_RATEMODE_REL) { 8423 /* XXX: top speed or actual link speed? */ 8424 gbps = port_top_speed(sc->port[port_id]); 8425 sbuf_printf(sb, " %u%% of %uGbps", tc.maxrate, gbps); 8426 } else if (tc.ratemode == SCHED_CLASS_RATEMODE_ABS) { 8427 switch (tc.rateunit) { 8428 case SCHED_CLASS_RATEUNIT_BITS: 8429 mbps = tc.maxrate / 1000; 8430 gbps = tc.maxrate / 1000000; 8431 if (tc.maxrate == gbps * 1000000) 8432 sbuf_printf(sb, " %uGbps", gbps); 8433 else if (tc.maxrate == mbps * 1000) 8434 sbuf_printf(sb, " %uMbps", mbps); 8435 else 8436 sbuf_printf(sb, " %uKbps", tc.maxrate); 8437 break; 8438 case SCHED_CLASS_RATEUNIT_PKTS: 8439 sbuf_printf(sb, " %upps", tc.maxrate); 8440 break; 8441 default: 8442 rc = ENXIO; 8443 goto done; 8444 } 8445 } 8446 8447 switch (tc.mode) { 8448 case SCHED_CLASS_MODE_CLASS: 8449 sbuf_printf(sb, " aggregate"); 8450 break; 8451 case SCHED_CLASS_MODE_FLOW: 8452 sbuf_printf(sb, " per-flow"); 8453 break; 8454 default: 8455 rc = ENXIO; 8456 goto done; 8457 } 8458 8459 done: 8460 if (rc == 0) 8461 rc = sbuf_finish(sb); 8462 sbuf_delete(sb); 8463 8464 return (rc); 8465 } 8466 #endif 8467 8468 #ifdef TCP_OFFLOAD 8469 static int 8470 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 8471 { 8472 struct adapter *sc = arg1; 8473 int *old_ports, *new_ports; 8474 int i, new_count, rc; 8475 8476 if (req->newptr == NULL && req->oldptr == NULL) 8477 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 8478 sizeof(sc->tt.tls_rx_ports[0]))); 8479 8480 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 8481 if (rc) 8482 return (rc); 8483 8484 if (sc->tt.num_tls_rx_ports == 0) { 8485 i = -1; 8486 rc = SYSCTL_OUT(req, &i, sizeof(i)); 8487 } else 8488 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 8489 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 8490 if (rc == 0 && req->newptr != NULL) { 8491 new_count = req->newlen / sizeof(new_ports[0]); 8492 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 8493 M_WAITOK); 8494 rc = SYSCTL_IN(req, new_ports, new_count * 8495 sizeof(new_ports[0])); 8496 if (rc) 8497 goto err; 8498 8499 /* Allow setting to a single '-1' to clear the list. */ 8500 if (new_count == 1 && new_ports[0] == -1) { 8501 ADAPTER_LOCK(sc); 8502 old_ports = sc->tt.tls_rx_ports; 8503 sc->tt.tls_rx_ports = NULL; 8504 sc->tt.num_tls_rx_ports = 0; 8505 ADAPTER_UNLOCK(sc); 8506 free(old_ports, M_CXGBE); 8507 } else { 8508 for (i = 0; i < new_count; i++) { 8509 if (new_ports[i] < 1 || 8510 new_ports[i] > IPPORT_MAX) { 8511 rc = EINVAL; 8512 goto err; 8513 } 8514 } 8515 8516 ADAPTER_LOCK(sc); 8517 old_ports = sc->tt.tls_rx_ports; 8518 sc->tt.tls_rx_ports = new_ports; 8519 sc->tt.num_tls_rx_ports = new_count; 8520 ADAPTER_UNLOCK(sc); 8521 free(old_ports, M_CXGBE); 8522 new_ports = NULL; 8523 } 8524 err: 8525 free(new_ports, M_CXGBE); 8526 } 8527 end_synchronized_op(sc, 0); 8528 return (rc); 8529 } 8530 8531 static void 8532 unit_conv(char *buf, size_t len, u_int val, u_int factor) 8533 { 8534 u_int rem = val % factor; 8535 8536 if (rem == 0) 8537 snprintf(buf, len, "%u", val / factor); 8538 else { 8539 while (rem % 10 == 0) 8540 rem /= 10; 8541 snprintf(buf, len, "%u.%u", val / factor, rem); 8542 } 8543 } 8544 8545 static int 8546 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 8547 { 8548 struct adapter *sc = arg1; 8549 char buf[16]; 8550 u_int res, re; 8551 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8552 8553 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8554 switch (arg2) { 8555 case 0: 8556 /* timer_tick */ 8557 re = G_TIMERRESOLUTION(res); 8558 break; 8559 case 1: 8560 /* TCP timestamp tick */ 8561 re = G_TIMESTAMPRESOLUTION(res); 8562 break; 8563 case 2: 8564 /* DACK tick */ 8565 re = G_DELAYEDACKRESOLUTION(res); 8566 break; 8567 default: 8568 return (EDOOFUS); 8569 } 8570 8571 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 8572 8573 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 8574 } 8575 8576 static int 8577 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 8578 { 8579 struct adapter *sc = arg1; 8580 u_int res, dack_re, v; 8581 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8582 8583 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 8584 dack_re = G_DELAYEDACKRESOLUTION(res); 8585 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 8586 8587 return (sysctl_handle_int(oidp, &v, 0, req)); 8588 } 8589 8590 static int 8591 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 8592 { 8593 struct adapter *sc = arg1; 8594 int reg = arg2; 8595 u_int tre; 8596 u_long tp_tick_us, v; 8597 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8598 8599 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 8600 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 8601 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 8602 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 8603 8604 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 8605 tp_tick_us = (cclk_ps << tre) / 1000000; 8606 8607 if (reg == A_TP_INIT_SRTT) 8608 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 8609 else 8610 v = tp_tick_us * t4_read_reg(sc, reg); 8611 8612 return (sysctl_handle_long(oidp, &v, 0, req)); 8613 } 8614 8615 /* 8616 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 8617 * passed to this function. 8618 */ 8619 static int 8620 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 8621 { 8622 struct adapter *sc = arg1; 8623 int idx = arg2; 8624 u_int v; 8625 8626 MPASS(idx >= 0 && idx <= 24); 8627 8628 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 8629 8630 return (sysctl_handle_int(oidp, &v, 0, req)); 8631 } 8632 8633 static int 8634 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 8635 { 8636 struct adapter *sc = arg1; 8637 int idx = arg2; 8638 u_int shift, v, r; 8639 8640 MPASS(idx >= 0 && idx < 16); 8641 8642 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 8643 shift = (idx & 3) << 3; 8644 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 8645 8646 return (sysctl_handle_int(oidp, &v, 0, req)); 8647 } 8648 8649 static int 8650 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 8651 { 8652 struct vi_info *vi = arg1; 8653 struct adapter *sc = vi->pi->adapter; 8654 int idx, rc, i; 8655 struct sge_ofld_rxq *ofld_rxq; 8656 uint8_t v; 8657 8658 idx = vi->ofld_tmr_idx; 8659 8660 rc = sysctl_handle_int(oidp, &idx, 0, req); 8661 if (rc != 0 || req->newptr == NULL) 8662 return (rc); 8663 8664 if (idx < 0 || idx >= SGE_NTIMERS) 8665 return (EINVAL); 8666 8667 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8668 "t4otmr"); 8669 if (rc) 8670 return (rc); 8671 8672 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 8673 for_each_ofld_rxq(vi, i, ofld_rxq) { 8674 #ifdef atomic_store_rel_8 8675 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 8676 #else 8677 ofld_rxq->iq.intr_params = v; 8678 #endif 8679 } 8680 vi->ofld_tmr_idx = idx; 8681 8682 end_synchronized_op(sc, LOCK_HELD); 8683 return (0); 8684 } 8685 8686 static int 8687 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 8688 { 8689 struct vi_info *vi = arg1; 8690 struct adapter *sc = vi->pi->adapter; 8691 int idx, rc; 8692 8693 idx = vi->ofld_pktc_idx; 8694 8695 rc = sysctl_handle_int(oidp, &idx, 0, req); 8696 if (rc != 0 || req->newptr == NULL) 8697 return (rc); 8698 8699 if (idx < -1 || idx >= SGE_NCOUNTERS) 8700 return (EINVAL); 8701 8702 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8703 "t4opktc"); 8704 if (rc) 8705 return (rc); 8706 8707 if (vi->flags & VI_INIT_DONE) 8708 rc = EBUSY; /* cannot be changed once the queues are created */ 8709 else 8710 vi->ofld_pktc_idx = idx; 8711 8712 end_synchronized_op(sc, LOCK_HELD); 8713 return (rc); 8714 } 8715 #endif 8716 8717 static int 8718 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 8719 { 8720 int rc; 8721 8722 if (cntxt->cid > M_CTXTQID) 8723 return (EINVAL); 8724 8725 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 8726 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 8727 return (EINVAL); 8728 8729 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 8730 if (rc) 8731 return (rc); 8732 8733 if (sc->flags & FW_OK) { 8734 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 8735 &cntxt->data[0]); 8736 if (rc == 0) 8737 goto done; 8738 } 8739 8740 /* 8741 * Read via firmware failed or wasn't even attempted. Read directly via 8742 * the backdoor. 8743 */ 8744 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 8745 done: 8746 end_synchronized_op(sc, 0); 8747 return (rc); 8748 } 8749 8750 static int 8751 load_fw(struct adapter *sc, struct t4_data *fw) 8752 { 8753 int rc; 8754 uint8_t *fw_data; 8755 8756 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 8757 if (rc) 8758 return (rc); 8759 8760 /* 8761 * The firmware, with the sole exception of the memory parity error 8762 * handler, runs from memory and not flash. It is almost always safe to 8763 * install a new firmware on a running system. Just set bit 1 in 8764 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 8765 */ 8766 if (sc->flags & FULL_INIT_DONE && 8767 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 8768 rc = EBUSY; 8769 goto done; 8770 } 8771 8772 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 8773 if (fw_data == NULL) { 8774 rc = ENOMEM; 8775 goto done; 8776 } 8777 8778 rc = copyin(fw->data, fw_data, fw->len); 8779 if (rc == 0) 8780 rc = -t4_load_fw(sc, fw_data, fw->len); 8781 8782 free(fw_data, M_CXGBE); 8783 done: 8784 end_synchronized_op(sc, 0); 8785 return (rc); 8786 } 8787 8788 static int 8789 load_cfg(struct adapter *sc, struct t4_data *cfg) 8790 { 8791 int rc; 8792 uint8_t *cfg_data = NULL; 8793 8794 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 8795 if (rc) 8796 return (rc); 8797 8798 if (cfg->len == 0) { 8799 /* clear */ 8800 rc = -t4_load_cfg(sc, NULL, 0); 8801 goto done; 8802 } 8803 8804 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 8805 if (cfg_data == NULL) { 8806 rc = ENOMEM; 8807 goto done; 8808 } 8809 8810 rc = copyin(cfg->data, cfg_data, cfg->len); 8811 if (rc == 0) 8812 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 8813 8814 free(cfg_data, M_CXGBE); 8815 done: 8816 end_synchronized_op(sc, 0); 8817 return (rc); 8818 } 8819 8820 static int 8821 load_boot(struct adapter *sc, struct t4_bootrom *br) 8822 { 8823 int rc; 8824 uint8_t *br_data = NULL; 8825 u_int offset; 8826 8827 if (br->len > 1024 * 1024) 8828 return (EFBIG); 8829 8830 if (br->pf_offset == 0) { 8831 /* pfidx */ 8832 if (br->pfidx_addr > 7) 8833 return (EINVAL); 8834 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 8835 A_PCIE_PF_EXPROM_OFST))); 8836 } else if (br->pf_offset == 1) { 8837 /* offset */ 8838 offset = G_OFFSET(br->pfidx_addr); 8839 } else { 8840 return (EINVAL); 8841 } 8842 8843 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 8844 if (rc) 8845 return (rc); 8846 8847 if (br->len == 0) { 8848 /* clear */ 8849 rc = -t4_load_boot(sc, NULL, offset, 0); 8850 goto done; 8851 } 8852 8853 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 8854 if (br_data == NULL) { 8855 rc = ENOMEM; 8856 goto done; 8857 } 8858 8859 rc = copyin(br->data, br_data, br->len); 8860 if (rc == 0) 8861 rc = -t4_load_boot(sc, br_data, offset, br->len); 8862 8863 free(br_data, M_CXGBE); 8864 done: 8865 end_synchronized_op(sc, 0); 8866 return (rc); 8867 } 8868 8869 static int 8870 load_bootcfg(struct adapter *sc, struct t4_data *bc) 8871 { 8872 int rc; 8873 uint8_t *bc_data = NULL; 8874 8875 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 8876 if (rc) 8877 return (rc); 8878 8879 if (bc->len == 0) { 8880 /* clear */ 8881 rc = -t4_load_bootcfg(sc, NULL, 0); 8882 goto done; 8883 } 8884 8885 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 8886 if (bc_data == NULL) { 8887 rc = ENOMEM; 8888 goto done; 8889 } 8890 8891 rc = copyin(bc->data, bc_data, bc->len); 8892 if (rc == 0) 8893 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 8894 8895 free(bc_data, M_CXGBE); 8896 done: 8897 end_synchronized_op(sc, 0); 8898 return (rc); 8899 } 8900 8901 static int 8902 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 8903 { 8904 int rc; 8905 struct cudbg_init *cudbg; 8906 void *handle, *buf; 8907 8908 /* buf is large, don't block if no memory is available */ 8909 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 8910 if (buf == NULL) 8911 return (ENOMEM); 8912 8913 handle = cudbg_alloc_handle(); 8914 if (handle == NULL) { 8915 rc = ENOMEM; 8916 goto done; 8917 } 8918 8919 cudbg = cudbg_get_init(handle); 8920 cudbg->adap = sc; 8921 cudbg->print = (cudbg_print_cb)printf; 8922 8923 #ifndef notyet 8924 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 8925 __func__, dump->wr_flash, dump->len, dump->data); 8926 #endif 8927 8928 if (dump->wr_flash) 8929 cudbg->use_flash = 1; 8930 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 8931 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 8932 8933 rc = cudbg_collect(handle, buf, &dump->len); 8934 if (rc != 0) 8935 goto done; 8936 8937 rc = copyout(buf, dump->data, dump->len); 8938 done: 8939 cudbg_free_handle(handle); 8940 free(buf, M_CXGBE); 8941 return (rc); 8942 } 8943 8944 static void 8945 free_offload_policy(struct t4_offload_policy *op) 8946 { 8947 struct offload_rule *r; 8948 int i; 8949 8950 if (op == NULL) 8951 return; 8952 8953 r = &op->rule[0]; 8954 for (i = 0; i < op->nrules; i++, r++) { 8955 free(r->bpf_prog.bf_insns, M_CXGBE); 8956 } 8957 free(op->rule, M_CXGBE); 8958 free(op, M_CXGBE); 8959 } 8960 8961 static int 8962 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 8963 { 8964 int i, rc, len; 8965 struct t4_offload_policy *op, *old; 8966 struct bpf_program *bf; 8967 const struct offload_settings *s; 8968 struct offload_rule *r; 8969 void *u; 8970 8971 if (!is_offload(sc)) 8972 return (ENODEV); 8973 8974 if (uop->nrules == 0) { 8975 /* Delete installed policies. */ 8976 op = NULL; 8977 goto set_policy; 8978 } if (uop->nrules > 256) { /* arbitrary */ 8979 return (E2BIG); 8980 } 8981 8982 /* Copy userspace offload policy to kernel */ 8983 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 8984 op->nrules = uop->nrules; 8985 len = op->nrules * sizeof(struct offload_rule); 8986 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 8987 rc = copyin(uop->rule, op->rule, len); 8988 if (rc) { 8989 free(op->rule, M_CXGBE); 8990 free(op, M_CXGBE); 8991 return (rc); 8992 } 8993 8994 r = &op->rule[0]; 8995 for (i = 0; i < op->nrules; i++, r++) { 8996 8997 /* Validate open_type */ 8998 if (r->open_type != OPEN_TYPE_LISTEN && 8999 r->open_type != OPEN_TYPE_ACTIVE && 9000 r->open_type != OPEN_TYPE_PASSIVE && 9001 r->open_type != OPEN_TYPE_DONTCARE) { 9002 error: 9003 /* 9004 * Rules 0 to i have malloc'd filters that need to be 9005 * freed. Rules i+1 to nrules have userspace pointers 9006 * and should be left alone. 9007 */ 9008 op->nrules = i; 9009 free_offload_policy(op); 9010 return (rc); 9011 } 9012 9013 /* Validate settings */ 9014 s = &r->settings; 9015 if ((s->offload != 0 && s->offload != 1) || 9016 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9017 s->sched_class < -1 || 9018 s->sched_class >= sc->chip_params->nsched_cls) { 9019 rc = EINVAL; 9020 goto error; 9021 } 9022 9023 bf = &r->bpf_prog; 9024 u = bf->bf_insns; /* userspace ptr */ 9025 bf->bf_insns = NULL; 9026 if (bf->bf_len == 0) { 9027 /* legal, matches everything */ 9028 continue; 9029 } 9030 len = bf->bf_len * sizeof(*bf->bf_insns); 9031 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9032 rc = copyin(u, bf->bf_insns, len); 9033 if (rc != 0) 9034 goto error; 9035 9036 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9037 rc = EINVAL; 9038 goto error; 9039 } 9040 } 9041 set_policy: 9042 rw_wlock(&sc->policy_lock); 9043 old = sc->policy; 9044 sc->policy = op; 9045 rw_wunlock(&sc->policy_lock); 9046 free_offload_policy(old); 9047 9048 return (0); 9049 } 9050 9051 #define MAX_READ_BUF_SIZE (128 * 1024) 9052 static int 9053 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9054 { 9055 uint32_t addr, remaining, n; 9056 uint32_t *buf; 9057 int rc; 9058 uint8_t *dst; 9059 9060 rc = validate_mem_range(sc, mr->addr, mr->len); 9061 if (rc != 0) 9062 return (rc); 9063 9064 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9065 addr = mr->addr; 9066 remaining = mr->len; 9067 dst = (void *)mr->data; 9068 9069 while (remaining) { 9070 n = min(remaining, MAX_READ_BUF_SIZE); 9071 read_via_memwin(sc, 2, addr, buf, n); 9072 9073 rc = copyout(buf, dst, n); 9074 if (rc != 0) 9075 break; 9076 9077 dst += n; 9078 remaining -= n; 9079 addr += n; 9080 } 9081 9082 free(buf, M_CXGBE); 9083 return (rc); 9084 } 9085 #undef MAX_READ_BUF_SIZE 9086 9087 static int 9088 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9089 { 9090 int rc; 9091 9092 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9093 return (EINVAL); 9094 9095 if (i2cd->len > sizeof(i2cd->data)) 9096 return (EFBIG); 9097 9098 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9099 if (rc) 9100 return (rc); 9101 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9102 i2cd->offset, i2cd->len, &i2cd->data[0]); 9103 end_synchronized_op(sc, 0); 9104 9105 return (rc); 9106 } 9107 9108 int 9109 t4_os_find_pci_capability(struct adapter *sc, int cap) 9110 { 9111 int i; 9112 9113 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9114 } 9115 9116 int 9117 t4_os_pci_save_state(struct adapter *sc) 9118 { 9119 device_t dev; 9120 struct pci_devinfo *dinfo; 9121 9122 dev = sc->dev; 9123 dinfo = device_get_ivars(dev); 9124 9125 pci_cfg_save(dev, dinfo, 0); 9126 return (0); 9127 } 9128 9129 int 9130 t4_os_pci_restore_state(struct adapter *sc) 9131 { 9132 device_t dev; 9133 struct pci_devinfo *dinfo; 9134 9135 dev = sc->dev; 9136 dinfo = device_get_ivars(dev); 9137 9138 pci_cfg_restore(dev, dinfo); 9139 return (0); 9140 } 9141 9142 void 9143 t4_os_portmod_changed(struct port_info *pi) 9144 { 9145 struct adapter *sc = pi->adapter; 9146 struct vi_info *vi; 9147 struct ifnet *ifp; 9148 static const char *mod_str[] = { 9149 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9150 }; 9151 9152 PORT_LOCK(pi); 9153 build_medialist(pi, &pi->media); 9154 PORT_UNLOCK(pi); 9155 vi = &pi->vi[0]; 9156 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9157 init_l1cfg(pi); 9158 end_synchronized_op(sc, LOCK_HELD); 9159 } 9160 9161 ifp = vi->ifp; 9162 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9163 if_printf(ifp, "transceiver unplugged.\n"); 9164 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9165 if_printf(ifp, "unknown transceiver inserted.\n"); 9166 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9167 if_printf(ifp, "unsupported transceiver inserted.\n"); 9168 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9169 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9170 port_top_speed(pi), mod_str[pi->mod_type]); 9171 } else { 9172 if_printf(ifp, "transceiver (type %d) inserted.\n", 9173 pi->mod_type); 9174 } 9175 } 9176 9177 void 9178 t4_os_link_changed(struct port_info *pi) 9179 { 9180 struct vi_info *vi; 9181 struct ifnet *ifp; 9182 struct link_config *lc; 9183 int v; 9184 9185 for_each_vi(pi, v, vi) { 9186 ifp = vi->ifp; 9187 if (ifp == NULL) 9188 continue; 9189 9190 lc = &pi->link_cfg; 9191 if (lc->link_ok) { 9192 ifp->if_baudrate = IF_Mbps(lc->speed); 9193 if_link_state_change(ifp, LINK_STATE_UP); 9194 } else { 9195 if_link_state_change(ifp, LINK_STATE_DOWN); 9196 } 9197 } 9198 } 9199 9200 void 9201 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9202 { 9203 struct adapter *sc; 9204 9205 sx_slock(&t4_list_lock); 9206 SLIST_FOREACH(sc, &t4_list, link) { 9207 /* 9208 * func should not make any assumptions about what state sc is 9209 * in - the only guarantee is that sc->sc_lock is a valid lock. 9210 */ 9211 func(sc, arg); 9212 } 9213 sx_sunlock(&t4_list_lock); 9214 } 9215 9216 static int 9217 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9218 struct thread *td) 9219 { 9220 int rc; 9221 struct adapter *sc = dev->si_drv1; 9222 9223 rc = priv_check(td, PRIV_DRIVER); 9224 if (rc != 0) 9225 return (rc); 9226 9227 switch (cmd) { 9228 case CHELSIO_T4_GETREG: { 9229 struct t4_reg *edata = (struct t4_reg *)data; 9230 9231 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9232 return (EFAULT); 9233 9234 if (edata->size == 4) 9235 edata->val = t4_read_reg(sc, edata->addr); 9236 else if (edata->size == 8) 9237 edata->val = t4_read_reg64(sc, edata->addr); 9238 else 9239 return (EINVAL); 9240 9241 break; 9242 } 9243 case CHELSIO_T4_SETREG: { 9244 struct t4_reg *edata = (struct t4_reg *)data; 9245 9246 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9247 return (EFAULT); 9248 9249 if (edata->size == 4) { 9250 if (edata->val & 0xffffffff00000000) 9251 return (EINVAL); 9252 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9253 } else if (edata->size == 8) 9254 t4_write_reg64(sc, edata->addr, edata->val); 9255 else 9256 return (EINVAL); 9257 break; 9258 } 9259 case CHELSIO_T4_REGDUMP: { 9260 struct t4_regdump *regs = (struct t4_regdump *)data; 9261 int reglen = t4_get_regs_len(sc); 9262 uint8_t *buf; 9263 9264 if (regs->len < reglen) { 9265 regs->len = reglen; /* hint to the caller */ 9266 return (ENOBUFS); 9267 } 9268 9269 regs->len = reglen; 9270 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9271 get_regs(sc, regs, buf); 9272 rc = copyout(buf, regs->data, reglen); 9273 free(buf, M_CXGBE); 9274 break; 9275 } 9276 case CHELSIO_T4_GET_FILTER_MODE: 9277 rc = get_filter_mode(sc, (uint32_t *)data); 9278 break; 9279 case CHELSIO_T4_SET_FILTER_MODE: 9280 rc = set_filter_mode(sc, *(uint32_t *)data); 9281 break; 9282 case CHELSIO_T4_GET_FILTER: 9283 rc = get_filter(sc, (struct t4_filter *)data); 9284 break; 9285 case CHELSIO_T4_SET_FILTER: 9286 rc = set_filter(sc, (struct t4_filter *)data); 9287 break; 9288 case CHELSIO_T4_DEL_FILTER: 9289 rc = del_filter(sc, (struct t4_filter *)data); 9290 break; 9291 case CHELSIO_T4_GET_SGE_CONTEXT: 9292 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9293 break; 9294 case CHELSIO_T4_LOAD_FW: 9295 rc = load_fw(sc, (struct t4_data *)data); 9296 break; 9297 case CHELSIO_T4_GET_MEM: 9298 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9299 break; 9300 case CHELSIO_T4_GET_I2C: 9301 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9302 break; 9303 case CHELSIO_T4_CLEAR_STATS: { 9304 int i, v, bg_map; 9305 u_int port_id = *(uint32_t *)data; 9306 struct port_info *pi; 9307 struct vi_info *vi; 9308 9309 if (port_id >= sc->params.nports) 9310 return (EINVAL); 9311 pi = sc->port[port_id]; 9312 if (pi == NULL) 9313 return (EIO); 9314 9315 /* MAC stats */ 9316 t4_clr_port_stats(sc, pi->tx_chan); 9317 pi->tx_parse_error = 0; 9318 pi->tnl_cong_drops = 0; 9319 mtx_lock(&sc->reg_lock); 9320 for_each_vi(pi, v, vi) { 9321 if (vi->flags & VI_INIT_DONE) 9322 t4_clr_vi_stats(sc, vi->viid); 9323 } 9324 bg_map = pi->mps_bg_map; 9325 v = 0; /* reuse */ 9326 while (bg_map) { 9327 i = ffs(bg_map) - 1; 9328 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 9329 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 9330 bg_map &= ~(1 << i); 9331 } 9332 mtx_unlock(&sc->reg_lock); 9333 9334 /* 9335 * Since this command accepts a port, clear stats for 9336 * all VIs on this port. 9337 */ 9338 for_each_vi(pi, v, vi) { 9339 if (vi->flags & VI_INIT_DONE) { 9340 struct sge_rxq *rxq; 9341 struct sge_txq *txq; 9342 struct sge_wrq *wrq; 9343 9344 for_each_rxq(vi, i, rxq) { 9345 #if defined(INET) || defined(INET6) 9346 rxq->lro.lro_queued = 0; 9347 rxq->lro.lro_flushed = 0; 9348 #endif 9349 rxq->rxcsum = 0; 9350 rxq->vlan_extraction = 0; 9351 } 9352 9353 for_each_txq(vi, i, txq) { 9354 txq->txcsum = 0; 9355 txq->tso_wrs = 0; 9356 txq->vlan_insertion = 0; 9357 txq->imm_wrs = 0; 9358 txq->sgl_wrs = 0; 9359 txq->txpkt_wrs = 0; 9360 txq->txpkts0_wrs = 0; 9361 txq->txpkts1_wrs = 0; 9362 txq->txpkts0_pkts = 0; 9363 txq->txpkts1_pkts = 0; 9364 mp_ring_reset_stats(txq->r); 9365 } 9366 9367 #ifdef TCP_OFFLOAD 9368 /* nothing to clear for each ofld_rxq */ 9369 9370 for_each_ofld_txq(vi, i, wrq) { 9371 wrq->tx_wrs_direct = 0; 9372 wrq->tx_wrs_copied = 0; 9373 } 9374 #endif 9375 9376 if (IS_MAIN_VI(vi)) { 9377 wrq = &sc->sge.ctrlq[pi->port_id]; 9378 wrq->tx_wrs_direct = 0; 9379 wrq->tx_wrs_copied = 0; 9380 } 9381 } 9382 } 9383 break; 9384 } 9385 case CHELSIO_T4_SCHED_CLASS: 9386 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9387 break; 9388 case CHELSIO_T4_SCHED_QUEUE: 9389 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9390 break; 9391 case CHELSIO_T4_GET_TRACER: 9392 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9393 break; 9394 case CHELSIO_T4_SET_TRACER: 9395 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9396 break; 9397 case CHELSIO_T4_LOAD_CFG: 9398 rc = load_cfg(sc, (struct t4_data *)data); 9399 break; 9400 case CHELSIO_T4_LOAD_BOOT: 9401 rc = load_boot(sc, (struct t4_bootrom *)data); 9402 break; 9403 case CHELSIO_T4_LOAD_BOOTCFG: 9404 rc = load_bootcfg(sc, (struct t4_data *)data); 9405 break; 9406 case CHELSIO_T4_CUDBG_DUMP: 9407 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 9408 break; 9409 case CHELSIO_T4_SET_OFLD_POLICY: 9410 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 9411 break; 9412 default: 9413 rc = ENOTTY; 9414 } 9415 9416 return (rc); 9417 } 9418 9419 void 9420 t4_db_full(struct adapter *sc) 9421 { 9422 9423 CXGBE_UNIMPLEMENTED(__func__); 9424 } 9425 9426 void 9427 t4_db_dropped(struct adapter *sc) 9428 { 9429 9430 CXGBE_UNIMPLEMENTED(__func__); 9431 } 9432 9433 #ifdef TCP_OFFLOAD 9434 static int 9435 toe_capability(struct vi_info *vi, int enable) 9436 { 9437 int rc; 9438 struct port_info *pi = vi->pi; 9439 struct adapter *sc = pi->adapter; 9440 9441 ASSERT_SYNCHRONIZED_OP(sc); 9442 9443 if (!is_offload(sc)) 9444 return (ENODEV); 9445 9446 if (enable) { 9447 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9448 /* TOE is already enabled. */ 9449 return (0); 9450 } 9451 9452 /* 9453 * We need the port's queues around so that we're able to send 9454 * and receive CPLs to/from the TOE even if the ifnet for this 9455 * port has never been UP'd administratively. 9456 */ 9457 if (!(vi->flags & VI_INIT_DONE)) { 9458 rc = vi_full_init(vi); 9459 if (rc) 9460 return (rc); 9461 } 9462 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9463 rc = vi_full_init(&pi->vi[0]); 9464 if (rc) 9465 return (rc); 9466 } 9467 9468 if (isset(&sc->offload_map, pi->port_id)) { 9469 /* TOE is enabled on another VI of this port. */ 9470 pi->uld_vis++; 9471 return (0); 9472 } 9473 9474 if (!uld_active(sc, ULD_TOM)) { 9475 rc = t4_activate_uld(sc, ULD_TOM); 9476 if (rc == EAGAIN) { 9477 log(LOG_WARNING, 9478 "You must kldload t4_tom.ko before trying " 9479 "to enable TOE on a cxgbe interface.\n"); 9480 } 9481 if (rc != 0) 9482 return (rc); 9483 KASSERT(sc->tom_softc != NULL, 9484 ("%s: TOM activated but softc NULL", __func__)); 9485 KASSERT(uld_active(sc, ULD_TOM), 9486 ("%s: TOM activated but flag not set", __func__)); 9487 } 9488 9489 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9490 if (!uld_active(sc, ULD_IWARP)) 9491 (void) t4_activate_uld(sc, ULD_IWARP); 9492 if (!uld_active(sc, ULD_ISCSI)) 9493 (void) t4_activate_uld(sc, ULD_ISCSI); 9494 9495 pi->uld_vis++; 9496 setbit(&sc->offload_map, pi->port_id); 9497 } else { 9498 pi->uld_vis--; 9499 9500 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9501 return (0); 9502 9503 KASSERT(uld_active(sc, ULD_TOM), 9504 ("%s: TOM never initialized?", __func__)); 9505 clrbit(&sc->offload_map, pi->port_id); 9506 } 9507 9508 return (0); 9509 } 9510 9511 /* 9512 * Add an upper layer driver to the global list. 9513 */ 9514 int 9515 t4_register_uld(struct uld_info *ui) 9516 { 9517 int rc = 0; 9518 struct uld_info *u; 9519 9520 sx_xlock(&t4_uld_list_lock); 9521 SLIST_FOREACH(u, &t4_uld_list, link) { 9522 if (u->uld_id == ui->uld_id) { 9523 rc = EEXIST; 9524 goto done; 9525 } 9526 } 9527 9528 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9529 ui->refcount = 0; 9530 done: 9531 sx_xunlock(&t4_uld_list_lock); 9532 return (rc); 9533 } 9534 9535 int 9536 t4_unregister_uld(struct uld_info *ui) 9537 { 9538 int rc = EINVAL; 9539 struct uld_info *u; 9540 9541 sx_xlock(&t4_uld_list_lock); 9542 9543 SLIST_FOREACH(u, &t4_uld_list, link) { 9544 if (u == ui) { 9545 if (ui->refcount > 0) { 9546 rc = EBUSY; 9547 goto done; 9548 } 9549 9550 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 9551 rc = 0; 9552 goto done; 9553 } 9554 } 9555 done: 9556 sx_xunlock(&t4_uld_list_lock); 9557 return (rc); 9558 } 9559 9560 int 9561 t4_activate_uld(struct adapter *sc, int id) 9562 { 9563 int rc; 9564 struct uld_info *ui; 9565 9566 ASSERT_SYNCHRONIZED_OP(sc); 9567 9568 if (id < 0 || id > ULD_MAX) 9569 return (EINVAL); 9570 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 9571 9572 sx_slock(&t4_uld_list_lock); 9573 9574 SLIST_FOREACH(ui, &t4_uld_list, link) { 9575 if (ui->uld_id == id) { 9576 if (!(sc->flags & FULL_INIT_DONE)) { 9577 rc = adapter_full_init(sc); 9578 if (rc != 0) 9579 break; 9580 } 9581 9582 rc = ui->activate(sc); 9583 if (rc == 0) { 9584 setbit(&sc->active_ulds, id); 9585 ui->refcount++; 9586 } 9587 break; 9588 } 9589 } 9590 9591 sx_sunlock(&t4_uld_list_lock); 9592 9593 return (rc); 9594 } 9595 9596 int 9597 t4_deactivate_uld(struct adapter *sc, int id) 9598 { 9599 int rc; 9600 struct uld_info *ui; 9601 9602 ASSERT_SYNCHRONIZED_OP(sc); 9603 9604 if (id < 0 || id > ULD_MAX) 9605 return (EINVAL); 9606 rc = ENXIO; 9607 9608 sx_slock(&t4_uld_list_lock); 9609 9610 SLIST_FOREACH(ui, &t4_uld_list, link) { 9611 if (ui->uld_id == id) { 9612 rc = ui->deactivate(sc); 9613 if (rc == 0) { 9614 clrbit(&sc->active_ulds, id); 9615 ui->refcount--; 9616 } 9617 break; 9618 } 9619 } 9620 9621 sx_sunlock(&t4_uld_list_lock); 9622 9623 return (rc); 9624 } 9625 9626 int 9627 uld_active(struct adapter *sc, int uld_id) 9628 { 9629 9630 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 9631 9632 return (isset(&sc->active_ulds, uld_id)); 9633 } 9634 #endif 9635 9636 /* 9637 * t = ptr to tunable. 9638 * nc = number of CPUs. 9639 * c = compiled in default for that tunable. 9640 */ 9641 static void 9642 calculate_nqueues(int *t, int nc, const int c) 9643 { 9644 int nq; 9645 9646 if (*t > 0) 9647 return; 9648 nq = *t < 0 ? -*t : c; 9649 *t = min(nc, nq); 9650 } 9651 9652 /* 9653 * Come up with reasonable defaults for some of the tunables, provided they're 9654 * not set by the user (in which case we'll use the values as is). 9655 */ 9656 static void 9657 tweak_tunables(void) 9658 { 9659 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 9660 9661 if (t4_ntxq < 1) { 9662 #ifdef RSS 9663 t4_ntxq = rss_getnumbuckets(); 9664 #else 9665 calculate_nqueues(&t4_ntxq, nc, NTXQ); 9666 #endif 9667 } 9668 9669 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 9670 9671 if (t4_nrxq < 1) { 9672 #ifdef RSS 9673 t4_nrxq = rss_getnumbuckets(); 9674 #else 9675 calculate_nqueues(&t4_nrxq, nc, NRXQ); 9676 #endif 9677 } 9678 9679 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 9680 9681 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 9682 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 9683 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 9684 #endif 9685 #ifdef TCP_OFFLOAD 9686 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 9687 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 9688 9689 if (t4_toecaps_allowed == -1) 9690 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 9691 9692 if (t4_rdmacaps_allowed == -1) { 9693 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 9694 FW_CAPS_CONFIG_RDMA_RDMAC; 9695 } 9696 9697 if (t4_iscsicaps_allowed == -1) { 9698 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 9699 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 9700 FW_CAPS_CONFIG_ISCSI_T10DIF; 9701 } 9702 9703 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 9704 t4_tmr_idx_ofld = TMR_IDX_OFLD; 9705 9706 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 9707 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 9708 #else 9709 if (t4_toecaps_allowed == -1) 9710 t4_toecaps_allowed = 0; 9711 9712 if (t4_rdmacaps_allowed == -1) 9713 t4_rdmacaps_allowed = 0; 9714 9715 if (t4_iscsicaps_allowed == -1) 9716 t4_iscsicaps_allowed = 0; 9717 #endif 9718 9719 #ifdef DEV_NETMAP 9720 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 9721 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 9722 #endif 9723 9724 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 9725 t4_tmr_idx = TMR_IDX; 9726 9727 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 9728 t4_pktc_idx = PKTC_IDX; 9729 9730 if (t4_qsize_txq < 128) 9731 t4_qsize_txq = 128; 9732 9733 if (t4_qsize_rxq < 128) 9734 t4_qsize_rxq = 128; 9735 while (t4_qsize_rxq & 7) 9736 t4_qsize_rxq++; 9737 9738 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 9739 9740 /* 9741 * Number of VIs to create per-port. The first VI is the "main" regular 9742 * VI for the port. The rest are additional virtual interfaces on the 9743 * same physical port. Note that the main VI does not have native 9744 * netmap support but the extra VIs do. 9745 * 9746 * Limit the number of VIs per port to the number of available 9747 * MAC addresses per port. 9748 */ 9749 if (t4_num_vis < 1) 9750 t4_num_vis = 1; 9751 if (t4_num_vis > nitems(vi_mac_funcs)) { 9752 t4_num_vis = nitems(vi_mac_funcs); 9753 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 9754 } 9755 9756 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 9757 pcie_relaxed_ordering = 1; 9758 #if defined(__i386__) || defined(__amd64__) 9759 if (cpu_vendor_id == CPU_VENDOR_INTEL) 9760 pcie_relaxed_ordering = 0; 9761 #endif 9762 } 9763 } 9764 9765 #ifdef DDB 9766 static void 9767 t4_dump_tcb(struct adapter *sc, int tid) 9768 { 9769 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 9770 9771 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 9772 save = t4_read_reg(sc, reg); 9773 base = sc->memwin[2].mw_base; 9774 9775 /* Dump TCB for the tid */ 9776 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9777 tcb_addr += tid * TCB_SIZE; 9778 9779 if (is_t4(sc)) { 9780 pf = 0; 9781 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 9782 } else { 9783 pf = V_PFNUM(sc->pf); 9784 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 9785 } 9786 t4_write_reg(sc, reg, win_pos | pf); 9787 t4_read_reg(sc, reg); 9788 9789 off = tcb_addr - win_pos; 9790 for (i = 0; i < 4; i++) { 9791 uint32_t buf[8]; 9792 for (j = 0; j < 8; j++, off += 4) 9793 buf[j] = htonl(t4_read_reg(sc, base + off)); 9794 9795 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 9796 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 9797 buf[7]); 9798 } 9799 9800 t4_write_reg(sc, reg, save); 9801 t4_read_reg(sc, reg); 9802 } 9803 9804 static void 9805 t4_dump_devlog(struct adapter *sc) 9806 { 9807 struct devlog_params *dparams = &sc->params.devlog; 9808 struct fw_devlog_e e; 9809 int i, first, j, m, nentries, rc; 9810 uint64_t ftstamp = UINT64_MAX; 9811 9812 if (dparams->start == 0) { 9813 db_printf("devlog params not valid\n"); 9814 return; 9815 } 9816 9817 nentries = dparams->size / sizeof(struct fw_devlog_e); 9818 m = fwmtype_to_hwmtype(dparams->memtype); 9819 9820 /* Find the first entry. */ 9821 first = -1; 9822 for (i = 0; i < nentries && !db_pager_quit; i++) { 9823 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9824 sizeof(e), (void *)&e); 9825 if (rc != 0) 9826 break; 9827 9828 if (e.timestamp == 0) 9829 break; 9830 9831 e.timestamp = be64toh(e.timestamp); 9832 if (e.timestamp < ftstamp) { 9833 ftstamp = e.timestamp; 9834 first = i; 9835 } 9836 } 9837 9838 if (first == -1) 9839 return; 9840 9841 i = first; 9842 do { 9843 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9844 sizeof(e), (void *)&e); 9845 if (rc != 0) 9846 return; 9847 9848 if (e.timestamp == 0) 9849 return; 9850 9851 e.timestamp = be64toh(e.timestamp); 9852 e.seqno = be32toh(e.seqno); 9853 for (j = 0; j < 8; j++) 9854 e.params[j] = be32toh(e.params[j]); 9855 9856 db_printf("%10d %15ju %8s %8s ", 9857 e.seqno, e.timestamp, 9858 (e.level < nitems(devlog_level_strings) ? 9859 devlog_level_strings[e.level] : "UNKNOWN"), 9860 (e.facility < nitems(devlog_facility_strings) ? 9861 devlog_facility_strings[e.facility] : "UNKNOWN")); 9862 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 9863 e.params[3], e.params[4], e.params[5], e.params[6], 9864 e.params[7]); 9865 9866 if (++i == nentries) 9867 i = 0; 9868 } while (i != first && !db_pager_quit); 9869 } 9870 9871 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 9872 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 9873 9874 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 9875 { 9876 device_t dev; 9877 int t; 9878 bool valid; 9879 9880 valid = false; 9881 t = db_read_token(); 9882 if (t == tIDENT) { 9883 dev = device_lookup_by_name(db_tok_string); 9884 valid = true; 9885 } 9886 db_skip_to_eol(); 9887 if (!valid) { 9888 db_printf("usage: show t4 devlog <nexus>\n"); 9889 return; 9890 } 9891 9892 if (dev == NULL) { 9893 db_printf("device not found\n"); 9894 return; 9895 } 9896 9897 t4_dump_devlog(device_get_softc(dev)); 9898 } 9899 9900 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 9901 { 9902 device_t dev; 9903 int radix, tid, t; 9904 bool valid; 9905 9906 valid = false; 9907 radix = db_radix; 9908 db_radix = 10; 9909 t = db_read_token(); 9910 if (t == tIDENT) { 9911 dev = device_lookup_by_name(db_tok_string); 9912 t = db_read_token(); 9913 if (t == tNUMBER) { 9914 tid = db_tok_number; 9915 valid = true; 9916 } 9917 } 9918 db_radix = radix; 9919 db_skip_to_eol(); 9920 if (!valid) { 9921 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 9922 return; 9923 } 9924 9925 if (dev == NULL) { 9926 db_printf("device not found\n"); 9927 return; 9928 } 9929 if (tid < 0) { 9930 db_printf("invalid tid\n"); 9931 return; 9932 } 9933 9934 t4_dump_tcb(device_get_softc(dev), tid); 9935 } 9936 #endif 9937 9938 /* 9939 * Borrowed from cesa_prep_aes_key(). 9940 * 9941 * NB: The crypto engine wants the words in the decryption key in reverse 9942 * order. 9943 */ 9944 void 9945 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 9946 { 9947 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 9948 uint32_t *dkey; 9949 int i; 9950 9951 rijndaelKeySetupEnc(ek, enc_key, kbits); 9952 dkey = dec_key; 9953 dkey += (kbits / 8) / 4; 9954 9955 switch (kbits) { 9956 case 128: 9957 for (i = 0; i < 4; i++) 9958 *--dkey = htobe32(ek[4 * 10 + i]); 9959 break; 9960 case 192: 9961 for (i = 0; i < 2; i++) 9962 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 9963 for (i = 0; i < 4; i++) 9964 *--dkey = htobe32(ek[4 * 12 + i]); 9965 break; 9966 case 256: 9967 for (i = 0; i < 4; i++) 9968 *--dkey = htobe32(ek[4 * 13 + i]); 9969 for (i = 0; i < 4; i++) 9970 *--dkey = htobe32(ek[4 * 14 + i]); 9971 break; 9972 } 9973 MPASS(dkey == dec_key); 9974 } 9975 9976 static struct sx mlu; /* mod load unload */ 9977 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 9978 9979 static int 9980 mod_event(module_t mod, int cmd, void *arg) 9981 { 9982 int rc = 0; 9983 static int loaded = 0; 9984 9985 switch (cmd) { 9986 case MOD_LOAD: 9987 sx_xlock(&mlu); 9988 if (loaded++ == 0) { 9989 t4_sge_modload(); 9990 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 9991 t4_filter_rpl, CPL_COOKIE_FILTER); 9992 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 9993 do_l2t_write_rpl, CPL_COOKIE_FILTER); 9994 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 9995 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 9996 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 9997 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 9998 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 9999 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10000 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10001 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10002 sx_init(&t4_list_lock, "T4/T5 adapters"); 10003 SLIST_INIT(&t4_list); 10004 #ifdef TCP_OFFLOAD 10005 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10006 SLIST_INIT(&t4_uld_list); 10007 #endif 10008 t4_tracer_modload(); 10009 tweak_tunables(); 10010 } 10011 sx_xunlock(&mlu); 10012 break; 10013 10014 case MOD_UNLOAD: 10015 sx_xlock(&mlu); 10016 if (--loaded == 0) { 10017 int tries; 10018 10019 sx_slock(&t4_list_lock); 10020 if (!SLIST_EMPTY(&t4_list)) { 10021 rc = EBUSY; 10022 sx_sunlock(&t4_list_lock); 10023 goto done_unload; 10024 } 10025 #ifdef TCP_OFFLOAD 10026 sx_slock(&t4_uld_list_lock); 10027 if (!SLIST_EMPTY(&t4_uld_list)) { 10028 rc = EBUSY; 10029 sx_sunlock(&t4_uld_list_lock); 10030 sx_sunlock(&t4_list_lock); 10031 goto done_unload; 10032 } 10033 #endif 10034 tries = 0; 10035 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10036 uprintf("%ju clusters with custom free routine " 10037 "still is use.\n", t4_sge_extfree_refs()); 10038 pause("t4unload", 2 * hz); 10039 } 10040 #ifdef TCP_OFFLOAD 10041 sx_sunlock(&t4_uld_list_lock); 10042 #endif 10043 sx_sunlock(&t4_list_lock); 10044 10045 if (t4_sge_extfree_refs() == 0) { 10046 t4_tracer_modunload(); 10047 #ifdef TCP_OFFLOAD 10048 sx_destroy(&t4_uld_list_lock); 10049 #endif 10050 sx_destroy(&t4_list_lock); 10051 t4_sge_modunload(); 10052 loaded = 0; 10053 } else { 10054 rc = EBUSY; 10055 loaded++; /* undo earlier decrement */ 10056 } 10057 } 10058 done_unload: 10059 sx_xunlock(&mlu); 10060 break; 10061 } 10062 10063 return (rc); 10064 } 10065 10066 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10067 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10068 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10069 10070 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10071 MODULE_VERSION(t4nex, 1); 10072 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10073 #ifdef DEV_NETMAP 10074 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10075 #endif /* DEV_NETMAP */ 10076 10077 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10078 MODULE_VERSION(t5nex, 1); 10079 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10080 #ifdef DEV_NETMAP 10081 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10082 #endif /* DEV_NETMAP */ 10083 10084 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10085 MODULE_VERSION(t6nex, 1); 10086 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10087 #ifdef DEV_NETMAP 10088 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10089 #endif /* DEV_NETMAP */ 10090 10091 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10092 MODULE_VERSION(cxgbe, 1); 10093 10094 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10095 MODULE_VERSION(cxl, 1); 10096 10097 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10098 MODULE_VERSION(cc, 1); 10099 10100 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10101 MODULE_VERSION(vcxgbe, 1); 10102 10103 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10104 MODULE_VERSION(vcxl, 1); 10105 10106 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10107 MODULE_VERSION(vcc, 1); 10108