1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "opt_ddb.h" 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_kern_tls.h" 35 #include "opt_ratelimit.h" 36 #include "opt_rss.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/priv.h> 41 #include <sys/kernel.h> 42 #include <sys/bus.h> 43 #include <sys/eventhandler.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #ifdef KERN_TLS 69 #include <netinet/tcp_seq.h> 70 #endif 71 #if defined(__i386__) || defined(__amd64__) 72 #include <machine/md_var.h> 73 #include <machine/cputypes.h> 74 #include <vm/vm.h> 75 #include <vm/pmap.h> 76 #endif 77 #ifdef DDB 78 #include <ddb/ddb.h> 79 #include <ddb/db_lex.h> 80 #endif 81 82 #include "common/common.h" 83 #include "common/t4_msg.h" 84 #include "common/t4_regs.h" 85 #include "common/t4_regs_values.h" 86 #include "cudbg/cudbg.h" 87 #include "t4_clip.h" 88 #include "t4_ioctl.h" 89 #include "t4_l2t.h" 90 #include "t4_mp_ring.h" 91 #include "t4_if.h" 92 #include "t4_smt.h" 93 94 /* T4 bus driver interface */ 95 static int t4_probe(device_t); 96 static int t4_attach(device_t); 97 static int t4_detach(device_t); 98 static int t4_child_location(device_t, device_t, struct sbuf *); 99 static int t4_ready(device_t); 100 static int t4_read_port_device(device_t, int, device_t *); 101 static int t4_suspend(device_t); 102 static int t4_resume(device_t); 103 static int t4_reset_prepare(device_t, device_t); 104 static int t4_reset_post(device_t, device_t); 105 static device_method_t t4_methods[] = { 106 DEVMETHOD(device_probe, t4_probe), 107 DEVMETHOD(device_attach, t4_attach), 108 DEVMETHOD(device_detach, t4_detach), 109 DEVMETHOD(device_suspend, t4_suspend), 110 DEVMETHOD(device_resume, t4_resume), 111 112 DEVMETHOD(bus_child_location, t4_child_location), 113 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 114 DEVMETHOD(bus_reset_post, t4_reset_post), 115 116 DEVMETHOD(t4_is_main_ready, t4_ready), 117 DEVMETHOD(t4_read_port_device, t4_read_port_device), 118 119 DEVMETHOD_END 120 }; 121 static driver_t t4_driver = { 122 "t4nex", 123 t4_methods, 124 sizeof(struct adapter) 125 }; 126 127 128 /* T4 port (cxgbe) interface */ 129 static int cxgbe_probe(device_t); 130 static int cxgbe_attach(device_t); 131 static int cxgbe_detach(device_t); 132 device_method_t cxgbe_methods[] = { 133 DEVMETHOD(device_probe, cxgbe_probe), 134 DEVMETHOD(device_attach, cxgbe_attach), 135 DEVMETHOD(device_detach, cxgbe_detach), 136 { 0, 0 } 137 }; 138 static driver_t cxgbe_driver = { 139 "cxgbe", 140 cxgbe_methods, 141 sizeof(struct port_info) 142 }; 143 144 /* T4 VI (vcxgbe) interface */ 145 static int vcxgbe_probe(device_t); 146 static int vcxgbe_attach(device_t); 147 static int vcxgbe_detach(device_t); 148 static device_method_t vcxgbe_methods[] = { 149 DEVMETHOD(device_probe, vcxgbe_probe), 150 DEVMETHOD(device_attach, vcxgbe_attach), 151 DEVMETHOD(device_detach, vcxgbe_detach), 152 { 0, 0 } 153 }; 154 static driver_t vcxgbe_driver = { 155 "vcxgbe", 156 vcxgbe_methods, 157 sizeof(struct vi_info) 158 }; 159 160 static d_ioctl_t t4_ioctl; 161 162 static struct cdevsw t4_cdevsw = { 163 .d_version = D_VERSION, 164 .d_ioctl = t4_ioctl, 165 .d_name = "t4nex", 166 }; 167 168 /* T5 bus driver interface */ 169 static int t5_probe(device_t); 170 static device_method_t t5_methods[] = { 171 DEVMETHOD(device_probe, t5_probe), 172 DEVMETHOD(device_attach, t4_attach), 173 DEVMETHOD(device_detach, t4_detach), 174 DEVMETHOD(device_suspend, t4_suspend), 175 DEVMETHOD(device_resume, t4_resume), 176 177 DEVMETHOD(bus_child_location, t4_child_location), 178 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 179 DEVMETHOD(bus_reset_post, t4_reset_post), 180 181 DEVMETHOD(t4_is_main_ready, t4_ready), 182 DEVMETHOD(t4_read_port_device, t4_read_port_device), 183 184 DEVMETHOD_END 185 }; 186 static driver_t t5_driver = { 187 "t5nex", 188 t5_methods, 189 sizeof(struct adapter) 190 }; 191 192 193 /* T5 port (cxl) interface */ 194 static driver_t cxl_driver = { 195 "cxl", 196 cxgbe_methods, 197 sizeof(struct port_info) 198 }; 199 200 /* T5 VI (vcxl) interface */ 201 static driver_t vcxl_driver = { 202 "vcxl", 203 vcxgbe_methods, 204 sizeof(struct vi_info) 205 }; 206 207 /* T6 bus driver interface */ 208 static int t6_probe(device_t); 209 static device_method_t t6_methods[] = { 210 DEVMETHOD(device_probe, t6_probe), 211 DEVMETHOD(device_attach, t4_attach), 212 DEVMETHOD(device_detach, t4_detach), 213 DEVMETHOD(device_suspend, t4_suspend), 214 DEVMETHOD(device_resume, t4_resume), 215 216 DEVMETHOD(bus_child_location, t4_child_location), 217 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 218 DEVMETHOD(bus_reset_post, t4_reset_post), 219 220 DEVMETHOD(t4_is_main_ready, t4_ready), 221 DEVMETHOD(t4_read_port_device, t4_read_port_device), 222 223 DEVMETHOD_END 224 }; 225 static driver_t t6_driver = { 226 "t6nex", 227 t6_methods, 228 sizeof(struct adapter) 229 }; 230 231 232 /* T6 port (cc) interface */ 233 static driver_t cc_driver = { 234 "cc", 235 cxgbe_methods, 236 sizeof(struct port_info) 237 }; 238 239 /* T6 VI (vcc) interface */ 240 static driver_t vcc_driver = { 241 "vcc", 242 vcxgbe_methods, 243 sizeof(struct vi_info) 244 }; 245 246 /* ifnet interface */ 247 static void cxgbe_init(void *); 248 static int cxgbe_ioctl(if_t, unsigned long, caddr_t); 249 static int cxgbe_transmit(if_t, struct mbuf *); 250 static void cxgbe_qflush(if_t); 251 #if defined(KERN_TLS) || defined(RATELIMIT) 252 static int cxgbe_snd_tag_alloc(if_t, union if_snd_tag_alloc_params *, 253 struct m_snd_tag **); 254 #endif 255 256 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 257 258 /* 259 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 260 * then ADAPTER_LOCK, then t4_uld_list_lock. 261 */ 262 static struct sx t4_list_lock; 263 SLIST_HEAD(, adapter) t4_list; 264 #ifdef TCP_OFFLOAD 265 static struct sx t4_uld_list_lock; 266 struct uld_info *t4_uld_list[ULD_MAX + 1]; 267 #endif 268 269 /* 270 * Tunables. See tweak_tunables() too. 271 * 272 * Each tunable is set to a default value here if it's known at compile-time. 273 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 274 * provide a reasonable default (upto n) when the driver is loaded. 275 * 276 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 277 * T5 are under hw.cxl. 278 */ 279 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 280 "cxgbe(4) parameters"); 281 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 282 "cxgbe(4) T5+ parameters"); 283 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 284 "cxgbe(4) TOE parameters"); 285 286 /* 287 * Number of queues for tx and rx, NIC and offload. 288 */ 289 #define NTXQ 16 290 int t4_ntxq = -NTXQ; 291 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 292 "Number of TX queues per port"); 293 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 294 295 #define NRXQ 8 296 int t4_nrxq = -NRXQ; 297 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 298 "Number of RX queues per port"); 299 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 300 301 #define NTXQ_VI 1 302 static int t4_ntxq_vi = -NTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 304 "Number of TX queues per VI"); 305 306 #define NRXQ_VI 1 307 static int t4_nrxq_vi = -NRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 309 "Number of RX queues per VI"); 310 311 static int t4_rsrv_noflowq = 0; 312 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 313 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 314 315 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 316 #define NOFLDTXQ 8 317 static int t4_nofldtxq = -NOFLDTXQ; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 319 "Number of offload TX queues per port"); 320 321 #define NOFLDTXQ_VI 1 322 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 323 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 324 "Number of offload TX queues per VI"); 325 #endif 326 327 #if defined(TCP_OFFLOAD) 328 #define NOFLDRXQ 2 329 static int t4_nofldrxq = -NOFLDRXQ; 330 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 331 "Number of offload RX queues per port"); 332 333 #define NOFLDRXQ_VI 1 334 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 335 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 336 "Number of offload RX queues per VI"); 337 338 #define TMR_IDX_OFLD 1 339 static int t4_tmr_idx_ofld = TMR_IDX_OFLD; 340 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 341 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 342 343 #define PKTC_IDX_OFLD (-1) 344 static int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 345 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 346 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 347 348 /* 0 means chip/fw default, non-zero number is value in microseconds */ 349 static u_long t4_toe_keepalive_idle = 0; 350 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 351 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 352 353 /* 0 means chip/fw default, non-zero number is value in microseconds */ 354 static u_long t4_toe_keepalive_interval = 0; 355 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 356 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 357 358 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 359 static int t4_toe_keepalive_count = 0; 360 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 361 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 362 363 /* 0 means chip/fw default, non-zero number is value in microseconds */ 364 static u_long t4_toe_rexmt_min = 0; 365 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 367 368 /* 0 means chip/fw default, non-zero number is value in microseconds */ 369 static u_long t4_toe_rexmt_max = 0; 370 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 371 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 372 373 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 374 static int t4_toe_rexmt_count = 0; 375 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 377 378 /* -1 means chip/fw default, other values are raw backoff values to use */ 379 static int t4_toe_rexmt_backoff[16] = { 380 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 381 }; 382 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, 383 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 384 "cxgbe(4) TOE retransmit backoff values"); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[0], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[1], 0, ""); 389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 390 &t4_toe_rexmt_backoff[2], 0, ""); 391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 392 &t4_toe_rexmt_backoff[3], 0, ""); 393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 394 &t4_toe_rexmt_backoff[4], 0, ""); 395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 396 &t4_toe_rexmt_backoff[5], 0, ""); 397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 398 &t4_toe_rexmt_backoff[6], 0, ""); 399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 400 &t4_toe_rexmt_backoff[7], 0, ""); 401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 402 &t4_toe_rexmt_backoff[8], 0, ""); 403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 404 &t4_toe_rexmt_backoff[9], 0, ""); 405 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 406 &t4_toe_rexmt_backoff[10], 0, ""); 407 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 408 &t4_toe_rexmt_backoff[11], 0, ""); 409 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 410 &t4_toe_rexmt_backoff[12], 0, ""); 411 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 412 &t4_toe_rexmt_backoff[13], 0, ""); 413 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 414 &t4_toe_rexmt_backoff[14], 0, ""); 415 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 416 &t4_toe_rexmt_backoff[15], 0, ""); 417 418 int t4_ddp_rcvbuf_len = 256 * 1024; 419 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_len, CTLFLAG_RWTUN, 420 &t4_ddp_rcvbuf_len, 0, "length of each DDP RX buffer"); 421 422 unsigned int t4_ddp_rcvbuf_cache = 4; 423 SYSCTL_UINT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_cache, CTLFLAG_RWTUN, 424 &t4_ddp_rcvbuf_cache, 0, 425 "maximum number of free DDP RX buffers to cache per connection"); 426 #endif 427 428 #ifdef DEV_NETMAP 429 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */ 430 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */ 431 static int t4_native_netmap = NN_EXTRA_VI; 432 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap, 433 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs"); 434 435 #define NNMTXQ 8 436 static int t4_nnmtxq = -NNMTXQ; 437 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0, 438 "Number of netmap TX queues"); 439 440 #define NNMRXQ 8 441 static int t4_nnmrxq = -NNMRXQ; 442 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0, 443 "Number of netmap RX queues"); 444 445 #define NNMTXQ_VI 2 446 static int t4_nnmtxq_vi = -NNMTXQ_VI; 447 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 448 "Number of netmap TX queues per VI"); 449 450 #define NNMRXQ_VI 2 451 static int t4_nnmrxq_vi = -NNMRXQ_VI; 452 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 453 "Number of netmap RX queues per VI"); 454 #endif 455 456 /* 457 * Holdoff parameters for ports. 458 */ 459 #define TMR_IDX 1 460 int t4_tmr_idx = TMR_IDX; 461 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 462 0, "Holdoff timer index"); 463 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 464 465 #define PKTC_IDX (-1) 466 int t4_pktc_idx = PKTC_IDX; 467 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 468 0, "Holdoff packet counter index"); 469 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 470 471 /* 472 * Size (# of entries) of each tx and rx queue. 473 */ 474 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 475 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 476 "Number of descriptors in each TX queue"); 477 478 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 479 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 480 "Number of descriptors in each RX queue"); 481 482 /* 483 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 484 */ 485 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 486 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 487 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 488 489 /* 490 * Configuration file. All the _CF names here are special. 491 */ 492 #define DEFAULT_CF "default" 493 #define BUILTIN_CF "built-in" 494 #define FLASH_CF "flash" 495 #define UWIRE_CF "uwire" 496 #define FPGA_CF "fpga" 497 static char t4_cfg_file[32] = DEFAULT_CF; 498 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 499 sizeof(t4_cfg_file), "Firmware configuration file"); 500 501 /* 502 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 503 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 504 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 505 * mark or when signalled to do so, 0 to never emit PAUSE. 506 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 507 * negotiated settings will override rx_pause/tx_pause. 508 * Otherwise rx_pause/tx_pause are applied forcibly. 509 */ 510 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 511 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 512 &t4_pause_settings, 0, 513 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 514 515 /* 516 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 517 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 518 * 0 to disable FEC. 519 */ 520 static int t4_fec = -1; 521 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 522 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 523 524 /* 525 * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it 526 * issues to the firmware. If the firmware doesn't support FORCE_FEC then the 527 * driver runs as if this is set to 0. 528 * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay. 529 * 0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the 530 * transceiver. Multiple FEC bits may not be okay but will be passed on to 531 * the firmware anyway (may result in l1cfg errors with old firmwares). 532 * 1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO 533 * means set all FEC bits that are valid for the speed. 534 */ 535 static int t4_force_fec = -1; 536 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0, 537 "Controls the use of FORCE_FEC bit in L1 configuration."); 538 539 /* 540 * Link autonegotiation. 541 * -1 to run with the firmware default. 542 * 0 to disable. 543 * 1 to enable. 544 */ 545 static int t4_autoneg = -1; 546 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 547 "Link autonegotiation"); 548 549 /* 550 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 551 * encouraged respectively). '-n' is the same as 'n' except the firmware 552 * version used in the checks is read from the firmware bundled with the driver. 553 */ 554 static int t4_fw_install = 1; 555 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 556 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 557 558 /* 559 * ASIC features that will be used. Disable the ones you don't want so that the 560 * chip resources aren't wasted on features that will not be used. 561 */ 562 static int t4_nbmcaps_allowed = 0; 563 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 564 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 565 566 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 567 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 568 &t4_linkcaps_allowed, 0, "Default link capabilities"); 569 570 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 571 FW_CAPS_CONFIG_SWITCH_EGRESS; 572 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 573 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 574 575 #ifdef RATELIMIT 576 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 577 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 578 #else 579 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 580 FW_CAPS_CONFIG_NIC_HASHFILTER; 581 #endif 582 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 583 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 584 585 static int t4_toecaps_allowed = -1; 586 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 587 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 588 589 static int t4_rdmacaps_allowed = -1; 590 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 591 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 592 593 static int t4_cryptocaps_allowed = -1; 594 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 595 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 596 597 static int t4_iscsicaps_allowed = -1; 598 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 599 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 600 601 static int t4_fcoecaps_allowed = 0; 602 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 603 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 604 605 static int t5_write_combine = 0; 606 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 607 0, "Use WC instead of UC for BAR2"); 608 609 /* From t4_sysctls: doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"} */ 610 static int t4_doorbells_allowed = 0xf; 611 SYSCTL_INT(_hw_cxgbe, OID_AUTO, doorbells_allowed, CTLFLAG_RDTUN, 612 &t4_doorbells_allowed, 0, "Limit tx queues to these doorbells"); 613 614 static int t4_num_vis = 1; 615 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 616 "Number of VIs per port"); 617 618 /* 619 * PCIe Relaxed Ordering. 620 * -1: driver should figure out a good value. 621 * 0: disable RO. 622 * 1: enable RO. 623 * 2: leave RO alone. 624 */ 625 static int pcie_relaxed_ordering = -1; 626 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 627 &pcie_relaxed_ordering, 0, 628 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 629 630 static int t4_panic_on_fatal_err = 0; 631 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN, 632 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 633 634 static int t4_reset_on_fatal_err = 0; 635 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN, 636 &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors"); 637 638 static int t4_clock_gate_on_suspend = 0; 639 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN, 640 &t4_clock_gate_on_suspend, 0, "gate the clock on suspend"); 641 642 static int t4_tx_vm_wr = 0; 643 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0, 644 "Use VM work requests to transmit packets."); 645 646 /* 647 * Set to non-zero to enable the attack filter. A packet that matches any of 648 * these conditions will get dropped on ingress: 649 * 1) IP && source address == destination address. 650 * 2) TCP/IP && source address is not a unicast address. 651 * 3) TCP/IP && destination address is not a unicast address. 652 * 4) IP && source address is loopback (127.x.y.z). 653 * 5) IP && destination address is loopback (127.x.y.z). 654 * 6) IPv6 && source address == destination address. 655 * 7) IPv6 && source address is not a unicast address. 656 * 8) IPv6 && source address is loopback (::1/128). 657 * 9) IPv6 && destination address is loopback (::1/128). 658 * 10) IPv6 && source address is unspecified (::/128). 659 * 11) IPv6 && destination address is unspecified (::/128). 660 * 12) TCP/IPv6 && source address is multicast (ff00::/8). 661 * 13) TCP/IPv6 && destination address is multicast (ff00::/8). 662 */ 663 static int t4_attack_filter = 0; 664 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN, 665 &t4_attack_filter, 0, "Drop suspicious traffic"); 666 667 static int t4_drop_ip_fragments = 0; 668 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN, 669 &t4_drop_ip_fragments, 0, "Drop IP fragments"); 670 671 static int t4_drop_pkts_with_l2_errors = 1; 672 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN, 673 &t4_drop_pkts_with_l2_errors, 0, 674 "Drop all frames with Layer 2 length or checksum errors"); 675 676 static int t4_drop_pkts_with_l3_errors = 0; 677 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN, 678 &t4_drop_pkts_with_l3_errors, 0, 679 "Drop all frames with IP version, length, or checksum errors"); 680 681 static int t4_drop_pkts_with_l4_errors = 0; 682 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN, 683 &t4_drop_pkts_with_l4_errors, 0, 684 "Drop all frames with Layer 4 length, checksum, or other errors"); 685 686 #ifdef TCP_OFFLOAD 687 /* 688 * TOE tunables. 689 */ 690 static int t4_cop_managed_offloading = 0; 691 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 692 &t4_cop_managed_offloading, 0, 693 "COP (Connection Offload Policy) controls all TOE offload"); 694 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading); 695 #endif 696 697 #ifdef KERN_TLS 698 /* 699 * This enables KERN_TLS for all adapters if set. 700 */ 701 static int t4_kern_tls = 0; 702 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0, 703 "Enable KERN_TLS mode for T6 adapters"); 704 705 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 706 "cxgbe(4) KERN_TLS parameters"); 707 708 static int t4_tls_inline_keys = 0; 709 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN, 710 &t4_tls_inline_keys, 0, 711 "Always pass TLS keys in work requests (1) or attempt to store TLS keys " 712 "in card memory."); 713 714 static int t4_tls_combo_wrs = 0; 715 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs, 716 0, "Attempt to combine TCB field updates with TLS record work requests."); 717 #endif 718 719 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 720 static int vi_mac_funcs[] = { 721 FW_VI_FUNC_ETH, 722 FW_VI_FUNC_OFLD, 723 FW_VI_FUNC_IWARP, 724 FW_VI_FUNC_OPENISCSI, 725 FW_VI_FUNC_OPENFCOE, 726 FW_VI_FUNC_FOISCSI, 727 FW_VI_FUNC_FOFCOE, 728 }; 729 730 struct intrs_and_queues { 731 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 732 uint16_t num_vis; /* number of VIs for each port */ 733 uint16_t nirq; /* Total # of vectors */ 734 uint16_t ntxq; /* # of NIC txq's for each port */ 735 uint16_t nrxq; /* # of NIC rxq's for each port */ 736 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 737 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 738 uint16_t nnmtxq; /* # of netmap txq's */ 739 uint16_t nnmrxq; /* # of netmap rxq's */ 740 741 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 742 uint16_t ntxq_vi; /* # of NIC txq's */ 743 uint16_t nrxq_vi; /* # of NIC rxq's */ 744 uint16_t nofldtxq_vi; /* # of TOE txq's */ 745 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 746 uint16_t nnmtxq_vi; /* # of netmap txq's */ 747 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 748 }; 749 750 static void setup_memwin(struct adapter *); 751 static void position_memwin(struct adapter *, int, uint32_t); 752 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 753 static int fwmtype_to_hwmtype(int); 754 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 755 uint32_t *); 756 static int fixup_devlog_params(struct adapter *); 757 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 758 static int contact_firmware(struct adapter *); 759 static int partition_resources(struct adapter *); 760 static int get_params__pre_init(struct adapter *); 761 static int set_params__pre_init(struct adapter *); 762 static int get_params__post_init(struct adapter *); 763 static int set_params__post_init(struct adapter *); 764 static void t4_set_desc(struct adapter *); 765 static bool fixed_ifmedia(struct port_info *); 766 static void build_medialist(struct port_info *); 767 static void init_link_config(struct port_info *); 768 static int fixup_link_config(struct port_info *); 769 static int apply_link_config(struct port_info *); 770 static int cxgbe_init_synchronized(struct vi_info *); 771 static int cxgbe_uninit_synchronized(struct vi_info *); 772 static int adapter_full_init(struct adapter *); 773 static void adapter_full_uninit(struct adapter *); 774 static int vi_full_init(struct vi_info *); 775 static void vi_full_uninit(struct vi_info *); 776 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *); 777 static void quiesce_txq(struct sge_txq *); 778 static void quiesce_wrq(struct sge_wrq *); 779 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 780 static void quiesce_vi(struct vi_info *); 781 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 782 driver_intr_t *, void *, char *); 783 static int t4_free_irq(struct adapter *, struct irq *); 784 static void t4_init_atid_table(struct adapter *); 785 static void t4_free_atid_table(struct adapter *); 786 static void stop_atid_allocator(struct adapter *); 787 static void restart_atid_allocator(struct adapter *); 788 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 789 static void vi_refresh_stats(struct vi_info *); 790 static void cxgbe_refresh_stats(struct vi_info *); 791 static void cxgbe_tick(void *); 792 static void vi_tick(void *); 793 static void cxgbe_sysctls(struct port_info *); 794 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 795 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 796 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 797 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 798 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 799 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS); 800 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 801 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 802 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 803 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 804 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 805 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS); 806 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS); 807 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS); 808 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 809 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS); 810 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 811 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 812 static int sysctl_vdd(SYSCTL_HANDLER_ARGS); 813 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS); 814 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 815 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 816 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 817 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 818 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 819 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 820 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 821 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 822 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 823 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS); 824 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 825 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 826 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 827 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 828 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 829 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 830 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 831 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 832 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 833 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 834 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 835 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 836 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 837 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 838 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS); 839 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 840 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 841 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 842 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 843 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 844 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 845 static int sysctl_reset(SYSCTL_HANDLER_ARGS); 846 #ifdef TCP_OFFLOAD 847 static int sysctl_tls(SYSCTL_HANDLER_ARGS); 848 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 849 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 850 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 851 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 852 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 853 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 854 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 855 #endif 856 static int get_sge_context(struct adapter *, struct t4_sge_context *); 857 static int load_fw(struct adapter *, struct t4_data *); 858 static int load_cfg(struct adapter *, struct t4_data *); 859 static int load_boot(struct adapter *, struct t4_bootrom *); 860 static int load_bootcfg(struct adapter *, struct t4_data *); 861 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 862 static void free_offload_policy(struct t4_offload_policy *); 863 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 864 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 865 static int read_i2c(struct adapter *, struct t4_i2c_data *); 866 static int clear_stats(struct adapter *, u_int); 867 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *); 868 static int release_clip_addr(struct adapter *, struct t4_clip_addr *); 869 static inline int stop_adapter(struct adapter *); 870 static inline void set_adapter_hwstatus(struct adapter *, const bool); 871 static int stop_lld(struct adapter *); 872 static inline int restart_adapter(struct adapter *); 873 static int restart_lld(struct adapter *); 874 #ifdef TCP_OFFLOAD 875 static int deactivate_all_uld(struct adapter *); 876 static void stop_all_uld(struct adapter *); 877 static void restart_all_uld(struct adapter *); 878 #endif 879 #ifdef KERN_TLS 880 static int ktls_capability(struct adapter *, bool); 881 #endif 882 static int mod_event(module_t, int, void *); 883 static int notify_siblings(device_t, int); 884 static uint64_t vi_get_counter(if_t, ift_counter); 885 static uint64_t cxgbe_get_counter(if_t, ift_counter); 886 static void enable_vxlan_rx(struct adapter *); 887 static void reset_adapter_task(void *, int); 888 static void fatal_error_task(void *, int); 889 static void dump_devlog(struct adapter *); 890 static void dump_cim_regs(struct adapter *); 891 static void dump_cimla(struct adapter *); 892 893 struct { 894 uint16_t device; 895 char *desc; 896 } t4_pciids[] = { 897 {0xa000, "Chelsio Terminator 4 FPGA"}, 898 {0x4400, "Chelsio T440-dbg"}, 899 {0x4401, "Chelsio T420-CR"}, 900 {0x4402, "Chelsio T422-CR"}, 901 {0x4403, "Chelsio T440-CR"}, 902 {0x4404, "Chelsio T420-BCH"}, 903 {0x4405, "Chelsio T440-BCH"}, 904 {0x4406, "Chelsio T440-CH"}, 905 {0x4407, "Chelsio T420-SO"}, 906 {0x4408, "Chelsio T420-CX"}, 907 {0x4409, "Chelsio T420-BT"}, 908 {0x440a, "Chelsio T404-BT"}, 909 {0x440e, "Chelsio T440-LP-CR"}, 910 }, t5_pciids[] = { 911 {0xb000, "Chelsio Terminator 5 FPGA"}, 912 {0x5400, "Chelsio T580-dbg"}, 913 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 914 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 915 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 916 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 917 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 918 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 919 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 920 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 921 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 922 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 923 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 924 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 925 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 926 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 927 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 928 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 929 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 930 931 /* Custom */ 932 {0x5483, "Custom T540-CR"}, 933 {0x5484, "Custom T540-BT"}, 934 }, t6_pciids[] = { 935 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 936 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 937 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 938 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 939 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 940 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 941 {0x6405, "Chelsio T6225-SO-OCP3"}, /* 2 x 10/25G, nomem */ 942 {0x6406, "Chelsio T6225-OCP3"}, /* 2 x 10/25G */ 943 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 944 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 945 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 946 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 947 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 948 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 949 {0x6414, "Chelsio T62100-SO-OCP3"}, /* 2 x 40/50/100G, nomem */ 950 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 951 952 /* Custom */ 953 {0x6480, "Custom T6225-CR"}, 954 {0x6481, "Custom T62100-CR"}, 955 {0x6482, "Custom T6225-CR"}, 956 {0x6483, "Custom T62100-CR"}, 957 {0x6484, "Custom T64100-CR"}, 958 {0x6485, "Custom T6240-SO"}, 959 {0x6486, "Custom T6225-SO-CR"}, 960 {0x6487, "Custom T6225-CR"}, 961 }; 962 963 #ifdef TCP_OFFLOAD 964 /* 965 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 966 * be exactly the same for both rxq and ofld_rxq. 967 */ 968 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 969 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 970 #endif 971 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 972 973 static int 974 t4_probe(device_t dev) 975 { 976 int i; 977 uint16_t v = pci_get_vendor(dev); 978 uint16_t d = pci_get_device(dev); 979 uint8_t f = pci_get_function(dev); 980 981 if (v != PCI_VENDOR_ID_CHELSIO) 982 return (ENXIO); 983 984 /* Attach only to PF0 of the FPGA */ 985 if (d == 0xa000 && f != 0) 986 return (ENXIO); 987 988 for (i = 0; i < nitems(t4_pciids); i++) { 989 if (d == t4_pciids[i].device) { 990 device_set_desc(dev, t4_pciids[i].desc); 991 return (BUS_PROBE_DEFAULT); 992 } 993 } 994 995 return (ENXIO); 996 } 997 998 static int 999 t5_probe(device_t dev) 1000 { 1001 int i; 1002 uint16_t v = pci_get_vendor(dev); 1003 uint16_t d = pci_get_device(dev); 1004 uint8_t f = pci_get_function(dev); 1005 1006 if (v != PCI_VENDOR_ID_CHELSIO) 1007 return (ENXIO); 1008 1009 /* Attach only to PF0 of the FPGA */ 1010 if (d == 0xb000 && f != 0) 1011 return (ENXIO); 1012 1013 for (i = 0; i < nitems(t5_pciids); i++) { 1014 if (d == t5_pciids[i].device) { 1015 device_set_desc(dev, t5_pciids[i].desc); 1016 return (BUS_PROBE_DEFAULT); 1017 } 1018 } 1019 1020 return (ENXIO); 1021 } 1022 1023 static int 1024 t6_probe(device_t dev) 1025 { 1026 int i; 1027 uint16_t v = pci_get_vendor(dev); 1028 uint16_t d = pci_get_device(dev); 1029 1030 if (v != PCI_VENDOR_ID_CHELSIO) 1031 return (ENXIO); 1032 1033 for (i = 0; i < nitems(t6_pciids); i++) { 1034 if (d == t6_pciids[i].device) { 1035 device_set_desc(dev, t6_pciids[i].desc); 1036 return (BUS_PROBE_DEFAULT); 1037 } 1038 } 1039 1040 return (ENXIO); 1041 } 1042 1043 static void 1044 t5_attribute_workaround(device_t dev) 1045 { 1046 device_t root_port; 1047 uint32_t v; 1048 1049 /* 1050 * The T5 chips do not properly echo the No Snoop and Relaxed 1051 * Ordering attributes when replying to a TLP from a Root 1052 * Port. As a workaround, find the parent Root Port and 1053 * disable No Snoop and Relaxed Ordering. Note that this 1054 * affects all devices under this root port. 1055 */ 1056 root_port = pci_find_pcie_root_port(dev); 1057 if (root_port == NULL) { 1058 device_printf(dev, "Unable to find parent root port\n"); 1059 return; 1060 } 1061 1062 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 1063 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 1064 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 1065 0) 1066 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 1067 device_get_nameunit(root_port)); 1068 } 1069 1070 static const struct devnames devnames[] = { 1071 { 1072 .nexus_name = "t4nex", 1073 .ifnet_name = "cxgbe", 1074 .vi_ifnet_name = "vcxgbe", 1075 .pf03_drv_name = "t4iov", 1076 .vf_nexus_name = "t4vf", 1077 .vf_ifnet_name = "cxgbev" 1078 }, { 1079 .nexus_name = "t5nex", 1080 .ifnet_name = "cxl", 1081 .vi_ifnet_name = "vcxl", 1082 .pf03_drv_name = "t5iov", 1083 .vf_nexus_name = "t5vf", 1084 .vf_ifnet_name = "cxlv" 1085 }, { 1086 .nexus_name = "t6nex", 1087 .ifnet_name = "cc", 1088 .vi_ifnet_name = "vcc", 1089 .pf03_drv_name = "t6iov", 1090 .vf_nexus_name = "t6vf", 1091 .vf_ifnet_name = "ccv" 1092 } 1093 }; 1094 1095 void 1096 t4_init_devnames(struct adapter *sc) 1097 { 1098 int id; 1099 1100 id = chip_id(sc); 1101 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 1102 sc->names = &devnames[id - CHELSIO_T4]; 1103 else { 1104 device_printf(sc->dev, "chip id %d is not supported.\n", id); 1105 sc->names = NULL; 1106 } 1107 } 1108 1109 static int 1110 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 1111 { 1112 const char *parent, *name; 1113 long value; 1114 int line, unit; 1115 1116 line = 0; 1117 parent = device_get_nameunit(sc->dev); 1118 name = sc->names->ifnet_name; 1119 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 1120 if (resource_long_value(name, unit, "port", &value) == 0 && 1121 value == pi->port_id) 1122 return (unit); 1123 } 1124 return (-1); 1125 } 1126 1127 static void 1128 t4_calibration(void *arg) 1129 { 1130 struct adapter *sc; 1131 struct clock_sync *cur, *nex; 1132 uint64_t hw; 1133 sbintime_t sbt; 1134 int next_up; 1135 1136 sc = (struct adapter *)arg; 1137 1138 KASSERT((hw_off_limits(sc) == 0), ("hw_off_limits at t4_calibration")); 1139 hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO); 1140 sbt = sbinuptime(); 1141 1142 cur = &sc->cal_info[sc->cal_current]; 1143 next_up = (sc->cal_current + 1) % CNT_CAL_INFO; 1144 nex = &sc->cal_info[next_up]; 1145 if (__predict_false(sc->cal_count == 0)) { 1146 /* First time in, just get the values in */ 1147 cur->hw_cur = hw; 1148 cur->sbt_cur = sbt; 1149 sc->cal_count++; 1150 goto done; 1151 } 1152 1153 if (cur->hw_cur == hw) { 1154 /* The clock is not advancing? */ 1155 sc->cal_count = 0; 1156 atomic_store_rel_int(&cur->gen, 0); 1157 goto done; 1158 } 1159 1160 seqc_write_begin(&nex->gen); 1161 nex->hw_prev = cur->hw_cur; 1162 nex->sbt_prev = cur->sbt_cur; 1163 nex->hw_cur = hw; 1164 nex->sbt_cur = sbt; 1165 seqc_write_end(&nex->gen); 1166 sc->cal_current = next_up; 1167 done: 1168 callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration, 1169 sc, C_DIRECT_EXEC); 1170 } 1171 1172 static void 1173 t4_calibration_start(struct adapter *sc) 1174 { 1175 /* 1176 * Here if we have not done a calibration 1177 * then do so otherwise start the appropriate 1178 * timer. 1179 */ 1180 int i; 1181 1182 for (i = 0; i < CNT_CAL_INFO; i++) { 1183 sc->cal_info[i].gen = 0; 1184 } 1185 sc->cal_current = 0; 1186 sc->cal_count = 0; 1187 sc->cal_gen = 0; 1188 t4_calibration(sc); 1189 } 1190 1191 static int 1192 t4_attach(device_t dev) 1193 { 1194 struct adapter *sc; 1195 int rc = 0, i, j, rqidx, tqidx, nports; 1196 struct make_dev_args mda; 1197 struct intrs_and_queues iaq; 1198 struct sge *s; 1199 uint32_t *buf; 1200 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1201 int ofld_tqidx; 1202 #endif 1203 #ifdef TCP_OFFLOAD 1204 int ofld_rqidx; 1205 #endif 1206 #ifdef DEV_NETMAP 1207 int nm_rqidx, nm_tqidx; 1208 #endif 1209 int num_vis; 1210 1211 sc = device_get_softc(dev); 1212 sc->dev = dev; 1213 sysctl_ctx_init(&sc->ctx); 1214 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 1215 1216 if ((pci_get_device(dev) & 0xff00) == 0x5400) 1217 t5_attribute_workaround(dev); 1218 pci_enable_busmaster(dev); 1219 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 1220 uint32_t v; 1221 1222 pci_set_max_read_req(dev, 4096); 1223 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 1224 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 1225 if (pcie_relaxed_ordering == 0 && 1226 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 1227 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 1228 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1229 } else if (pcie_relaxed_ordering == 1 && 1230 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 1231 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 1232 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1233 } 1234 } 1235 1236 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 1237 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 1238 sc->traceq = -1; 1239 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 1240 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 1241 device_get_nameunit(dev)); 1242 1243 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 1244 device_get_nameunit(dev)); 1245 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 1246 t4_add_adapter(sc); 1247 1248 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 1249 TAILQ_INIT(&sc->sfl); 1250 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 1251 1252 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 1253 1254 sc->policy = NULL; 1255 rw_init(&sc->policy_lock, "connection offload policy"); 1256 1257 callout_init(&sc->ktls_tick, 1); 1258 1259 callout_init(&sc->cal_callout, 1); 1260 1261 refcount_init(&sc->vxlan_refcount, 0); 1262 1263 TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc); 1264 TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc); 1265 1266 sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1267 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq", 1268 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 1269 sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1270 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq", 1271 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 1272 1273 rc = t4_map_bars_0_and_4(sc); 1274 if (rc != 0) 1275 goto done; /* error message displayed already */ 1276 1277 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1278 1279 /* Prepare the adapter for operation. */ 1280 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1281 rc = -t4_prep_adapter(sc, buf); 1282 free(buf, M_CXGBE); 1283 if (rc != 0) { 1284 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1285 goto done; 1286 } 1287 1288 /* 1289 * This is the real PF# to which we're attaching. Works from within PCI 1290 * passthrough environments too, where pci_get_function() could return a 1291 * different PF# depending on the passthrough configuration. We need to 1292 * use the real PF# in all our communication with the firmware. 1293 */ 1294 j = t4_read_reg(sc, A_PL_WHOAMI); 1295 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1296 sc->mbox = sc->pf; 1297 1298 t4_init_devnames(sc); 1299 if (sc->names == NULL) { 1300 rc = ENOTSUP; 1301 goto done; /* error message displayed already */ 1302 } 1303 1304 /* 1305 * Do this really early, with the memory windows set up even before the 1306 * character device. The userland tool's register i/o and mem read 1307 * will work even in "recovery mode". 1308 */ 1309 setup_memwin(sc); 1310 if (t4_init_devlog_params(sc, 0) == 0) 1311 fixup_devlog_params(sc); 1312 make_dev_args_init(&mda); 1313 mda.mda_devsw = &t4_cdevsw; 1314 mda.mda_uid = UID_ROOT; 1315 mda.mda_gid = GID_WHEEL; 1316 mda.mda_mode = 0600; 1317 mda.mda_si_drv1 = sc; 1318 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1319 if (rc != 0) 1320 device_printf(dev, "failed to create nexus char device: %d.\n", 1321 rc); 1322 1323 /* Go no further if recovery mode has been requested. */ 1324 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1325 device_printf(dev, "recovery mode.\n"); 1326 goto done; 1327 } 1328 1329 #if defined(__i386__) 1330 if ((cpu_feature & CPUID_CX8) == 0) { 1331 device_printf(dev, "64 bit atomics not available.\n"); 1332 rc = ENOTSUP; 1333 goto done; 1334 } 1335 #endif 1336 1337 /* Contact the firmware and try to become the master driver. */ 1338 rc = contact_firmware(sc); 1339 if (rc != 0) 1340 goto done; /* error message displayed already */ 1341 MPASS(sc->flags & FW_OK); 1342 1343 rc = get_params__pre_init(sc); 1344 if (rc != 0) 1345 goto done; /* error message displayed already */ 1346 1347 if (sc->flags & MASTER_PF) { 1348 rc = partition_resources(sc); 1349 if (rc != 0) 1350 goto done; /* error message displayed already */ 1351 } 1352 1353 rc = get_params__post_init(sc); 1354 if (rc != 0) 1355 goto done; /* error message displayed already */ 1356 1357 rc = set_params__post_init(sc); 1358 if (rc != 0) 1359 goto done; /* error message displayed already */ 1360 1361 rc = t4_map_bar_2(sc); 1362 if (rc != 0) 1363 goto done; /* error message displayed already */ 1364 1365 rc = t4_adj_doorbells(sc); 1366 if (rc != 0) 1367 goto done; /* error message displayed already */ 1368 1369 rc = t4_create_dma_tag(sc); 1370 if (rc != 0) 1371 goto done; /* error message displayed already */ 1372 1373 /* 1374 * First pass over all the ports - allocate VIs and initialize some 1375 * basic parameters like mac address, port type, etc. 1376 */ 1377 for_each_port(sc, i) { 1378 struct port_info *pi; 1379 1380 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1381 sc->port[i] = pi; 1382 1383 /* These must be set before t4_port_init */ 1384 pi->adapter = sc; 1385 pi->port_id = i; 1386 /* 1387 * XXX: vi[0] is special so we can't delay this allocation until 1388 * pi->nvi's final value is known. 1389 */ 1390 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1391 M_ZERO | M_WAITOK); 1392 1393 /* 1394 * Allocate the "main" VI and initialize parameters 1395 * like mac addr. 1396 */ 1397 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1398 if (rc != 0) { 1399 device_printf(dev, "unable to initialize port %d: %d\n", 1400 i, rc); 1401 free(pi->vi, M_CXGBE); 1402 free(pi, M_CXGBE); 1403 sc->port[i] = NULL; 1404 goto done; 1405 } 1406 1407 if (is_bt(pi->port_type)) 1408 setbit(&sc->bt_map, pi->tx_chan); 1409 else 1410 MPASS(!isset(&sc->bt_map, pi->tx_chan)); 1411 1412 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1413 device_get_nameunit(dev), i); 1414 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1415 sc->chan_map[pi->tx_chan] = i; 1416 1417 /* 1418 * The MPS counter for FCS errors doesn't work correctly on the 1419 * T6 so we use the MAC counter here. Which MAC is in use 1420 * depends on the link settings which will be known when the 1421 * link comes up. 1422 */ 1423 if (is_t6(sc)) 1424 pi->fcs_reg = -1; 1425 else { 1426 pi->fcs_reg = t4_port_reg(sc, pi->tx_chan, 1427 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1428 } 1429 pi->fcs_base = 0; 1430 1431 /* All VIs on this port share this media. */ 1432 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1433 cxgbe_media_status); 1434 1435 PORT_LOCK(pi); 1436 init_link_config(pi); 1437 fixup_link_config(pi); 1438 build_medialist(pi); 1439 if (fixed_ifmedia(pi)) 1440 pi->flags |= FIXED_IFMEDIA; 1441 PORT_UNLOCK(pi); 1442 1443 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1444 t4_ifnet_unit(sc, pi)); 1445 if (pi->dev == NULL) { 1446 device_printf(dev, 1447 "failed to add device for port %d.\n", i); 1448 rc = ENXIO; 1449 goto done; 1450 } 1451 pi->vi[0].dev = pi->dev; 1452 device_set_softc(pi->dev, pi); 1453 } 1454 1455 /* 1456 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1457 */ 1458 nports = sc->params.nports; 1459 rc = cfg_itype_and_nqueues(sc, &iaq); 1460 if (rc != 0) 1461 goto done; /* error message displayed already */ 1462 1463 num_vis = iaq.num_vis; 1464 sc->intr_type = iaq.intr_type; 1465 sc->intr_count = iaq.nirq; 1466 1467 s = &sc->sge; 1468 s->nrxq = nports * iaq.nrxq; 1469 s->ntxq = nports * iaq.ntxq; 1470 if (num_vis > 1) { 1471 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1472 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1473 } 1474 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1475 s->neq += nports; /* ctrl queues: 1 per port */ 1476 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1477 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1478 if (is_offload(sc) || is_ethoffload(sc)) { 1479 s->nofldtxq = nports * iaq.nofldtxq; 1480 if (num_vis > 1) 1481 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1482 s->neq += s->nofldtxq; 1483 1484 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq), 1485 M_CXGBE, M_ZERO | M_WAITOK); 1486 } 1487 #endif 1488 #ifdef TCP_OFFLOAD 1489 if (is_offload(sc)) { 1490 s->nofldrxq = nports * iaq.nofldrxq; 1491 if (num_vis > 1) 1492 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1493 s->neq += s->nofldrxq; /* free list */ 1494 s->niq += s->nofldrxq; 1495 1496 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1497 M_CXGBE, M_ZERO | M_WAITOK); 1498 } 1499 #endif 1500 #ifdef DEV_NETMAP 1501 s->nnmrxq = 0; 1502 s->nnmtxq = 0; 1503 if (t4_native_netmap & NN_MAIN_VI) { 1504 s->nnmrxq += nports * iaq.nnmrxq; 1505 s->nnmtxq += nports * iaq.nnmtxq; 1506 } 1507 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) { 1508 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi; 1509 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi; 1510 } 1511 s->neq += s->nnmtxq + s->nnmrxq; 1512 s->niq += s->nnmrxq; 1513 1514 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1515 M_CXGBE, M_ZERO | M_WAITOK); 1516 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1517 M_CXGBE, M_ZERO | M_WAITOK); 1518 #endif 1519 MPASS(s->niq <= s->iqmap_sz); 1520 MPASS(s->neq <= s->eqmap_sz); 1521 1522 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1523 M_ZERO | M_WAITOK); 1524 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1525 M_ZERO | M_WAITOK); 1526 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1527 M_ZERO | M_WAITOK); 1528 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE, 1529 M_ZERO | M_WAITOK); 1530 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE, 1531 M_ZERO | M_WAITOK); 1532 1533 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1534 M_ZERO | M_WAITOK); 1535 1536 t4_init_l2t(sc, M_WAITOK); 1537 t4_init_smt(sc, M_WAITOK); 1538 t4_init_tx_sched(sc); 1539 t4_init_atid_table(sc); 1540 #ifdef RATELIMIT 1541 t4_init_etid_table(sc); 1542 #endif 1543 #ifdef INET6 1544 t4_init_clip_table(sc); 1545 #endif 1546 if (sc->vres.key.size != 0) 1547 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1548 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1549 1550 /* 1551 * Second pass over the ports. This time we know the number of rx and 1552 * tx queues that each port should get. 1553 */ 1554 rqidx = tqidx = 0; 1555 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1556 ofld_tqidx = 0; 1557 #endif 1558 #ifdef TCP_OFFLOAD 1559 ofld_rqidx = 0; 1560 #endif 1561 #ifdef DEV_NETMAP 1562 nm_rqidx = nm_tqidx = 0; 1563 #endif 1564 for_each_port(sc, i) { 1565 struct port_info *pi = sc->port[i]; 1566 struct vi_info *vi; 1567 1568 if (pi == NULL) 1569 continue; 1570 1571 pi->nvi = num_vis; 1572 for_each_vi(pi, j, vi) { 1573 vi->pi = pi; 1574 vi->adapter = sc; 1575 vi->first_intr = -1; 1576 vi->qsize_rxq = t4_qsize_rxq; 1577 vi->qsize_txq = t4_qsize_txq; 1578 1579 vi->first_rxq = rqidx; 1580 vi->first_txq = tqidx; 1581 vi->tmr_idx = t4_tmr_idx; 1582 vi->pktc_idx = t4_pktc_idx; 1583 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1584 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1585 1586 rqidx += vi->nrxq; 1587 tqidx += vi->ntxq; 1588 1589 if (j == 0 && vi->ntxq > 1) 1590 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1591 else 1592 vi->rsrv_noflowq = 0; 1593 1594 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1595 vi->first_ofld_txq = ofld_tqidx; 1596 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1597 ofld_tqidx += vi->nofldtxq; 1598 #endif 1599 #ifdef TCP_OFFLOAD 1600 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1601 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1602 vi->first_ofld_rxq = ofld_rqidx; 1603 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1604 1605 ofld_rqidx += vi->nofldrxq; 1606 #endif 1607 #ifdef DEV_NETMAP 1608 vi->first_nm_rxq = nm_rqidx; 1609 vi->first_nm_txq = nm_tqidx; 1610 if (j == 0) { 1611 vi->nnmrxq = iaq.nnmrxq; 1612 vi->nnmtxq = iaq.nnmtxq; 1613 } else { 1614 vi->nnmrxq = iaq.nnmrxq_vi; 1615 vi->nnmtxq = iaq.nnmtxq_vi; 1616 } 1617 nm_rqidx += vi->nnmrxq; 1618 nm_tqidx += vi->nnmtxq; 1619 #endif 1620 } 1621 } 1622 1623 rc = t4_setup_intr_handlers(sc); 1624 if (rc != 0) { 1625 device_printf(dev, 1626 "failed to setup interrupt handlers: %d\n", rc); 1627 goto done; 1628 } 1629 1630 bus_identify_children(dev); 1631 1632 /* 1633 * Ensure thread-safe mailbox access (in debug builds). 1634 * 1635 * So far this was the only thread accessing the mailbox but various 1636 * ifnets and sysctls are about to be created and their handlers/ioctls 1637 * will access the mailbox from different threads. 1638 */ 1639 sc->flags |= CHK_MBOX_ACCESS; 1640 1641 bus_attach_children(dev); 1642 t4_calibration_start(sc); 1643 1644 device_printf(dev, 1645 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1646 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1647 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1648 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1649 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1650 1651 t4_set_desc(sc); 1652 1653 notify_siblings(dev, 0); 1654 1655 done: 1656 if (rc != 0 && sc->cdev) { 1657 /* cdev was created and so cxgbetool works; recover that way. */ 1658 device_printf(dev, 1659 "error during attach, adapter is now in recovery mode.\n"); 1660 rc = 0; 1661 } 1662 1663 if (rc != 0) 1664 t4_detach_common(dev); 1665 else 1666 t4_sysctls(sc); 1667 1668 return (rc); 1669 } 1670 1671 static int 1672 t4_child_location(device_t bus, device_t dev, struct sbuf *sb) 1673 { 1674 struct adapter *sc; 1675 struct port_info *pi; 1676 int i; 1677 1678 sc = device_get_softc(bus); 1679 for_each_port(sc, i) { 1680 pi = sc->port[i]; 1681 if (pi != NULL && pi->dev == dev) { 1682 sbuf_printf(sb, "port=%d", pi->port_id); 1683 break; 1684 } 1685 } 1686 return (0); 1687 } 1688 1689 static int 1690 t4_ready(device_t dev) 1691 { 1692 struct adapter *sc; 1693 1694 sc = device_get_softc(dev); 1695 if (sc->flags & FW_OK) 1696 return (0); 1697 return (ENXIO); 1698 } 1699 1700 static int 1701 t4_read_port_device(device_t dev, int port, device_t *child) 1702 { 1703 struct adapter *sc; 1704 struct port_info *pi; 1705 1706 sc = device_get_softc(dev); 1707 if (port < 0 || port >= MAX_NPORTS) 1708 return (EINVAL); 1709 pi = sc->port[port]; 1710 if (pi == NULL || pi->dev == NULL) 1711 return (ENXIO); 1712 *child = pi->dev; 1713 return (0); 1714 } 1715 1716 static int 1717 notify_siblings(device_t dev, int detaching) 1718 { 1719 device_t sibling; 1720 int error, i; 1721 1722 error = 0; 1723 for (i = 0; i < PCI_FUNCMAX; i++) { 1724 if (i == pci_get_function(dev)) 1725 continue; 1726 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1727 pci_get_slot(dev), i); 1728 if (sibling == NULL || !device_is_attached(sibling)) 1729 continue; 1730 if (detaching) 1731 error = T4_DETACH_CHILD(sibling); 1732 else 1733 (void)T4_ATTACH_CHILD(sibling); 1734 if (error) 1735 break; 1736 } 1737 return (error); 1738 } 1739 1740 /* 1741 * Idempotent 1742 */ 1743 static int 1744 t4_detach(device_t dev) 1745 { 1746 int rc; 1747 1748 rc = notify_siblings(dev, 1); 1749 if (rc) { 1750 device_printf(dev, 1751 "failed to detach sibling devices: %d\n", rc); 1752 return (rc); 1753 } 1754 1755 return (t4_detach_common(dev)); 1756 } 1757 1758 int 1759 t4_detach_common(device_t dev) 1760 { 1761 struct adapter *sc; 1762 struct port_info *pi; 1763 int i, rc; 1764 1765 sc = device_get_softc(dev); 1766 1767 #ifdef TCP_OFFLOAD 1768 rc = deactivate_all_uld(sc); 1769 if (rc) { 1770 device_printf(dev, 1771 "failed to detach upper layer drivers: %d\n", rc); 1772 return (rc); 1773 } 1774 #endif 1775 1776 if (sc->cdev) { 1777 destroy_dev(sc->cdev); 1778 sc->cdev = NULL; 1779 } 1780 1781 sx_xlock(&t4_list_lock); 1782 SLIST_REMOVE(&t4_list, sc, adapter, link); 1783 sx_xunlock(&t4_list_lock); 1784 1785 sc->flags &= ~CHK_MBOX_ACCESS; 1786 if (sc->flags & FULL_INIT_DONE) { 1787 if (!(sc->flags & IS_VF)) 1788 t4_intr_disable(sc); 1789 } 1790 1791 if (device_is_attached(dev)) { 1792 rc = bus_detach_children(dev); 1793 if (rc) { 1794 device_printf(dev, 1795 "failed to detach child devices: %d\n", rc); 1796 return (rc); 1797 } 1798 } 1799 1800 for (i = 0; i < sc->intr_count; i++) 1801 t4_free_irq(sc, &sc->irq[i]); 1802 1803 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1804 t4_free_tx_sched(sc); 1805 1806 for (i = 0; i < MAX_NPORTS; i++) { 1807 pi = sc->port[i]; 1808 if (pi) { 1809 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1810 1811 mtx_destroy(&pi->pi_lock); 1812 free(pi->vi, M_CXGBE); 1813 free(pi, M_CXGBE); 1814 } 1815 } 1816 callout_stop(&sc->cal_callout); 1817 callout_drain(&sc->cal_callout); 1818 device_delete_children(dev); 1819 sysctl_ctx_free(&sc->ctx); 1820 adapter_full_uninit(sc); 1821 1822 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1823 t4_fw_bye(sc, sc->mbox); 1824 1825 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1826 pci_release_msi(dev); 1827 1828 if (sc->regs_res) 1829 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1830 sc->regs_res); 1831 1832 if (sc->udbs_res) 1833 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1834 sc->udbs_res); 1835 1836 if (sc->msix_res) 1837 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1838 sc->msix_res); 1839 1840 if (sc->l2t) 1841 t4_free_l2t(sc); 1842 if (sc->smt) 1843 t4_free_smt(sc->smt); 1844 t4_free_atid_table(sc); 1845 #ifdef RATELIMIT 1846 t4_free_etid_table(sc); 1847 #endif 1848 if (sc->key_map) 1849 vmem_destroy(sc->key_map); 1850 #ifdef INET6 1851 t4_destroy_clip_table(sc); 1852 #endif 1853 1854 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1855 free(sc->sge.ofld_txq, M_CXGBE); 1856 #endif 1857 #ifdef TCP_OFFLOAD 1858 free(sc->sge.ofld_rxq, M_CXGBE); 1859 #endif 1860 #ifdef DEV_NETMAP 1861 free(sc->sge.nm_rxq, M_CXGBE); 1862 free(sc->sge.nm_txq, M_CXGBE); 1863 #endif 1864 free(sc->irq, M_CXGBE); 1865 free(sc->sge.rxq, M_CXGBE); 1866 free(sc->sge.txq, M_CXGBE); 1867 free(sc->sge.ctrlq, M_CXGBE); 1868 free(sc->sge.iqmap, M_CXGBE); 1869 free(sc->sge.eqmap, M_CXGBE); 1870 free(sc->tids.ftid_tab, M_CXGBE); 1871 free(sc->tids.hpftid_tab, M_CXGBE); 1872 free_hftid_hash(&sc->tids); 1873 free(sc->tids.tid_tab, M_CXGBE); 1874 t4_destroy_dma_tag(sc); 1875 1876 callout_drain(&sc->ktls_tick); 1877 callout_drain(&sc->sfl_callout); 1878 if (mtx_initialized(&sc->tids.ftid_lock)) { 1879 mtx_destroy(&sc->tids.ftid_lock); 1880 cv_destroy(&sc->tids.ftid_cv); 1881 } 1882 if (mtx_initialized(&sc->tids.atid_lock)) 1883 mtx_destroy(&sc->tids.atid_lock); 1884 if (mtx_initialized(&sc->ifp_lock)) 1885 mtx_destroy(&sc->ifp_lock); 1886 1887 if (rw_initialized(&sc->policy_lock)) { 1888 rw_destroy(&sc->policy_lock); 1889 #ifdef TCP_OFFLOAD 1890 if (sc->policy != NULL) 1891 free_offload_policy(sc->policy); 1892 #endif 1893 } 1894 1895 for (i = 0; i < NUM_MEMWIN; i++) { 1896 struct memwin *mw = &sc->memwin[i]; 1897 1898 if (rw_initialized(&mw->mw_lock)) 1899 rw_destroy(&mw->mw_lock); 1900 } 1901 1902 mtx_destroy(&sc->sfl_lock); 1903 mtx_destroy(&sc->reg_lock); 1904 mtx_destroy(&sc->sc_lock); 1905 1906 bzero(sc, sizeof(*sc)); 1907 1908 return (0); 1909 } 1910 1911 static inline int 1912 stop_adapter(struct adapter *sc) 1913 { 1914 struct port_info *pi; 1915 int i; 1916 1917 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) { 1918 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n", 1919 __func__, curthread, sc->flags, sc->error_flags); 1920 return (EALREADY); 1921 } 1922 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread, 1923 sc->flags, sc->error_flags); 1924 t4_shutdown_adapter(sc); 1925 for_each_port(sc, i) { 1926 pi = sc->port[i]; 1927 PORT_LOCK(pi); 1928 if (pi->up_vis > 0 && pi->link_cfg.link_ok) { 1929 /* 1930 * t4_shutdown_adapter has already shut down all the 1931 * PHYs but it also disables interrupts and DMA so there 1932 * won't be a link interrupt. Update the state manually 1933 * if the link was up previously and inform the kernel. 1934 */ 1935 pi->link_cfg.link_ok = false; 1936 t4_os_link_changed(pi); 1937 } 1938 PORT_UNLOCK(pi); 1939 } 1940 1941 return (0); 1942 } 1943 1944 static inline int 1945 restart_adapter(struct adapter *sc) 1946 { 1947 uint32_t val; 1948 1949 if (!atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_STOPPED))) { 1950 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n", 1951 __func__, curthread, sc->flags, sc->error_flags); 1952 return (EALREADY); 1953 } 1954 CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread, 1955 sc->flags, sc->error_flags); 1956 1957 MPASS(hw_off_limits(sc)); 1958 MPASS((sc->flags & FW_OK) == 0); 1959 MPASS((sc->flags & MASTER_PF) == 0); 1960 MPASS(sc->reset_thread == NULL); 1961 1962 /* 1963 * The adapter is supposed to be back on PCIE with its config space and 1964 * BARs restored to their state before reset. Register access via 1965 * t4_read_reg BAR0 should just work. 1966 */ 1967 sc->reset_thread = curthread; 1968 val = t4_read_reg(sc, A_PL_WHOAMI); 1969 if (val == 0xffffffff || val == 0xeeeeeeee) { 1970 CH_ERR(sc, "%s: device registers not readable.\n", __func__); 1971 sc->reset_thread = NULL; 1972 atomic_set_int(&sc->error_flags, ADAP_STOPPED); 1973 return (ENXIO); 1974 } 1975 atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR); 1976 atomic_add_int(&sc->incarnation, 1); 1977 atomic_add_int(&sc->num_resets, 1); 1978 1979 return (0); 1980 } 1981 1982 static inline void 1983 set_adapter_hwstatus(struct adapter *sc, const bool usable) 1984 { 1985 if (usable) { 1986 /* Must be marked reusable by the designated thread. */ 1987 ASSERT_SYNCHRONIZED_OP(sc); 1988 MPASS(sc->reset_thread == curthread); 1989 mtx_lock(&sc->reg_lock); 1990 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 1991 mtx_unlock(&sc->reg_lock); 1992 } else { 1993 /* Mark the adapter totally off limits. */ 1994 begin_synchronized_op(sc, NULL, SLEEP_OK, "t4hwsts"); 1995 mtx_lock(&sc->reg_lock); 1996 atomic_set_int(&sc->error_flags, HW_OFF_LIMITS); 1997 mtx_unlock(&sc->reg_lock); 1998 sc->flags &= ~(FW_OK | MASTER_PF); 1999 sc->reset_thread = NULL; 2000 end_synchronized_op(sc, 0); 2001 } 2002 } 2003 2004 static int 2005 stop_lld(struct adapter *sc) 2006 { 2007 struct port_info *pi; 2008 struct vi_info *vi; 2009 if_t ifp; 2010 struct sge_rxq *rxq; 2011 struct sge_txq *txq; 2012 struct sge_wrq *wrq; 2013 #ifdef TCP_OFFLOAD 2014 struct sge_ofld_rxq *ofld_rxq; 2015 #endif 2016 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2017 struct sge_ofld_txq *ofld_txq; 2018 #endif 2019 int rc, i, j, k; 2020 2021 /* 2022 * XXX: Can there be a synch_op in progress that will hang because 2023 * hardware has been stopped? We'll hang too and the solution will be 2024 * to use a version of begin_synch_op that wakes up existing synch_op 2025 * with errors. Maybe stop_adapter should do this wakeup? 2026 * 2027 * I don't think any synch_op could get stranded waiting for DMA or 2028 * interrupt so I think we're okay here. Remove this comment block 2029 * after testing. 2030 */ 2031 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4slld"); 2032 if (rc != 0) 2033 return (ENXIO); 2034 2035 /* Quiesce all activity. */ 2036 for_each_port(sc, i) { 2037 pi = sc->port[i]; 2038 pi->vxlan_tcam_entry = false; 2039 for_each_vi(pi, j, vi) { 2040 vi->xact_addr_filt = -1; 2041 mtx_lock(&vi->tick_mtx); 2042 vi->flags |= VI_SKIP_STATS; 2043 mtx_unlock(&vi->tick_mtx); 2044 if (!(vi->flags & VI_INIT_DONE)) 2045 continue; 2046 2047 ifp = vi->ifp; 2048 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2049 mtx_lock(&vi->tick_mtx); 2050 callout_stop(&vi->tick); 2051 mtx_unlock(&vi->tick_mtx); 2052 callout_drain(&vi->tick); 2053 } 2054 2055 /* 2056 * Note that the HW is not available. 2057 */ 2058 for_each_txq(vi, k, txq) { 2059 TXQ_LOCK(txq); 2060 txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED); 2061 TXQ_UNLOCK(txq); 2062 } 2063 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2064 for_each_ofld_txq(vi, k, ofld_txq) { 2065 TXQ_LOCK(&ofld_txq->wrq); 2066 ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED; 2067 TXQ_UNLOCK(&ofld_txq->wrq); 2068 } 2069 #endif 2070 for_each_rxq(vi, k, rxq) { 2071 rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2072 } 2073 #if defined(TCP_OFFLOAD) 2074 for_each_ofld_rxq(vi, k, ofld_rxq) { 2075 ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2076 } 2077 #endif 2078 2079 quiesce_vi(vi); 2080 } 2081 2082 if (sc->flags & FULL_INIT_DONE) { 2083 /* Control queue */ 2084 wrq = &sc->sge.ctrlq[i]; 2085 TXQ_LOCK(wrq); 2086 wrq->eq.flags &= ~EQ_HW_ALLOCATED; 2087 TXQ_UNLOCK(wrq); 2088 quiesce_wrq(wrq); 2089 } 2090 2091 if (pi->flags & HAS_TRACEQ) { 2092 pi->flags &= ~HAS_TRACEQ; 2093 sc->traceq = -1; 2094 sc->tracer_valid = 0; 2095 sc->tracer_enabled = 0; 2096 } 2097 } 2098 if (sc->flags & FULL_INIT_DONE) { 2099 /* Firmware event queue */ 2100 sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED; 2101 quiesce_iq_fl(sc, &sc->sge.fwq, NULL); 2102 } 2103 2104 /* Stop calibration */ 2105 callout_stop(&sc->cal_callout); 2106 callout_drain(&sc->cal_callout); 2107 2108 if (t4_clock_gate_on_suspend) { 2109 t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN | 2110 F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN | 2111 F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0); 2112 } 2113 2114 end_synchronized_op(sc, 0); 2115 2116 stop_atid_allocator(sc); 2117 t4_stop_l2t(sc); 2118 2119 return (rc); 2120 } 2121 2122 int 2123 suspend_adapter(struct adapter *sc) 2124 { 2125 stop_adapter(sc); 2126 stop_lld(sc); 2127 #ifdef TCP_OFFLOAD 2128 stop_all_uld(sc); 2129 #endif 2130 set_adapter_hwstatus(sc, false); 2131 2132 return (0); 2133 } 2134 2135 static int 2136 t4_suspend(device_t dev) 2137 { 2138 struct adapter *sc = device_get_softc(dev); 2139 int rc; 2140 2141 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2142 rc = suspend_adapter(sc); 2143 CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread); 2144 2145 return (rc); 2146 } 2147 2148 struct adapter_pre_reset_state { 2149 u_int flags; 2150 uint16_t nbmcaps; 2151 uint16_t linkcaps; 2152 uint16_t switchcaps; 2153 uint16_t niccaps; 2154 uint16_t toecaps; 2155 uint16_t rdmacaps; 2156 uint16_t cryptocaps; 2157 uint16_t iscsicaps; 2158 uint16_t fcoecaps; 2159 2160 u_int cfcsum; 2161 char cfg_file[32]; 2162 2163 struct adapter_params params; 2164 struct t4_virt_res vres; 2165 struct tid_info tids; 2166 struct sge sge; 2167 2168 int rawf_base; 2169 int nrawf; 2170 2171 }; 2172 2173 static void 2174 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2175 { 2176 2177 ASSERT_SYNCHRONIZED_OP(sc); 2178 2179 o->flags = sc->flags; 2180 2181 o->nbmcaps = sc->nbmcaps; 2182 o->linkcaps = sc->linkcaps; 2183 o->switchcaps = sc->switchcaps; 2184 o->niccaps = sc->niccaps; 2185 o->toecaps = sc->toecaps; 2186 o->rdmacaps = sc->rdmacaps; 2187 o->cryptocaps = sc->cryptocaps; 2188 o->iscsicaps = sc->iscsicaps; 2189 o->fcoecaps = sc->fcoecaps; 2190 2191 o->cfcsum = sc->cfcsum; 2192 MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file)); 2193 memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file)); 2194 2195 o->params = sc->params; 2196 o->vres = sc->vres; 2197 o->tids = sc->tids; 2198 o->sge = sc->sge; 2199 2200 o->rawf_base = sc->rawf_base; 2201 o->nrawf = sc->nrawf; 2202 } 2203 2204 static int 2205 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2206 { 2207 int rc = 0; 2208 2209 ASSERT_SYNCHRONIZED_OP(sc); 2210 2211 /* Capabilities */ 2212 #define COMPARE_CAPS(c) do { \ 2213 if (o->c##caps != sc->c##caps) { \ 2214 CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \ 2215 sc->c##caps); \ 2216 rc = EINVAL; \ 2217 } \ 2218 } while (0) 2219 COMPARE_CAPS(nbm); 2220 COMPARE_CAPS(link); 2221 COMPARE_CAPS(switch); 2222 COMPARE_CAPS(nic); 2223 COMPARE_CAPS(toe); 2224 COMPARE_CAPS(rdma); 2225 COMPARE_CAPS(crypto); 2226 COMPARE_CAPS(iscsi); 2227 COMPARE_CAPS(fcoe); 2228 #undef COMPARE_CAPS 2229 2230 /* Firmware config file */ 2231 if (o->cfcsum != sc->cfcsum) { 2232 CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file, 2233 o->cfcsum, sc->cfg_file, sc->cfcsum); 2234 rc = EINVAL; 2235 } 2236 2237 #define COMPARE_PARAM(p, name) do { \ 2238 if (o->p != sc->p) { \ 2239 CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \ 2240 rc = EINVAL; \ 2241 } \ 2242 } while (0) 2243 COMPARE_PARAM(sge.iq_start, iq_start); 2244 COMPARE_PARAM(sge.eq_start, eq_start); 2245 COMPARE_PARAM(tids.ftid_base, ftid_base); 2246 COMPARE_PARAM(tids.ftid_end, ftid_end); 2247 COMPARE_PARAM(tids.nftids, nftids); 2248 COMPARE_PARAM(vres.l2t.start, l2t_start); 2249 COMPARE_PARAM(vres.l2t.size, l2t_size); 2250 COMPARE_PARAM(sge.iqmap_sz, iqmap_sz); 2251 COMPARE_PARAM(sge.eqmap_sz, eqmap_sz); 2252 COMPARE_PARAM(tids.tid_base, tid_base); 2253 COMPARE_PARAM(tids.hpftid_base, hpftid_base); 2254 COMPARE_PARAM(tids.hpftid_end, hpftid_end); 2255 COMPARE_PARAM(tids.nhpftids, nhpftids); 2256 COMPARE_PARAM(rawf_base, rawf_base); 2257 COMPARE_PARAM(nrawf, nrawf); 2258 COMPARE_PARAM(params.mps_bg_map, mps_bg_map); 2259 COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support); 2260 COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl); 2261 COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support); 2262 COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr); 2263 COMPARE_PARAM(tids.ntids, ntids); 2264 COMPARE_PARAM(tids.etid_base, etid_base); 2265 COMPARE_PARAM(tids.etid_end, etid_end); 2266 COMPARE_PARAM(tids.netids, netids); 2267 COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred); 2268 COMPARE_PARAM(params.ethoffload, ethoffload); 2269 COMPARE_PARAM(tids.natids, natids); 2270 COMPARE_PARAM(tids.stid_base, stid_base); 2271 COMPARE_PARAM(vres.ddp.start, ddp_start); 2272 COMPARE_PARAM(vres.ddp.size, ddp_size); 2273 COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred); 2274 COMPARE_PARAM(vres.stag.start, stag_start); 2275 COMPARE_PARAM(vres.stag.size, stag_size); 2276 COMPARE_PARAM(vres.rq.start, rq_start); 2277 COMPARE_PARAM(vres.rq.size, rq_size); 2278 COMPARE_PARAM(vres.pbl.start, pbl_start); 2279 COMPARE_PARAM(vres.pbl.size, pbl_size); 2280 COMPARE_PARAM(vres.qp.start, qp_start); 2281 COMPARE_PARAM(vres.qp.size, qp_size); 2282 COMPARE_PARAM(vres.cq.start, cq_start); 2283 COMPARE_PARAM(vres.cq.size, cq_size); 2284 COMPARE_PARAM(vres.ocq.start, ocq_start); 2285 COMPARE_PARAM(vres.ocq.size, ocq_size); 2286 COMPARE_PARAM(vres.srq.start, srq_start); 2287 COMPARE_PARAM(vres.srq.size, srq_size); 2288 COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp); 2289 COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter); 2290 COMPARE_PARAM(vres.iscsi.start, iscsi_start); 2291 COMPARE_PARAM(vres.iscsi.size, iscsi_size); 2292 COMPARE_PARAM(vres.key.start, key_start); 2293 COMPARE_PARAM(vres.key.size, key_size); 2294 #undef COMPARE_PARAM 2295 2296 return (rc); 2297 } 2298 2299 static int 2300 restart_lld(struct adapter *sc) 2301 { 2302 struct adapter_pre_reset_state *old_state = NULL; 2303 struct port_info *pi; 2304 struct vi_info *vi; 2305 if_t ifp; 2306 struct sge_txq *txq; 2307 int rc, i, j, k; 2308 2309 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rlld"); 2310 if (rc != 0) 2311 return (ENXIO); 2312 2313 /* Restore memory window. */ 2314 setup_memwin(sc); 2315 2316 /* Go no further if recovery mode has been requested. */ 2317 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 2318 CH_ALERT(sc, "%s: recovery mode during restart.\n", __func__); 2319 rc = 0; 2320 set_adapter_hwstatus(sc, true); 2321 goto done; 2322 } 2323 2324 old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK); 2325 save_caps_and_params(sc, old_state); 2326 2327 /* Reestablish contact with firmware and become the primary PF. */ 2328 rc = contact_firmware(sc); 2329 if (rc != 0) 2330 goto done; /* error message displayed already */ 2331 MPASS(sc->flags & FW_OK); 2332 2333 if (sc->flags & MASTER_PF) { 2334 rc = partition_resources(sc); 2335 if (rc != 0) 2336 goto done; /* error message displayed already */ 2337 } 2338 2339 rc = get_params__post_init(sc); 2340 if (rc != 0) 2341 goto done; /* error message displayed already */ 2342 2343 rc = set_params__post_init(sc); 2344 if (rc != 0) 2345 goto done; /* error message displayed already */ 2346 2347 rc = compare_caps_and_params(sc, old_state); 2348 if (rc != 0) 2349 goto done; /* error message displayed already */ 2350 2351 for_each_port(sc, i) { 2352 pi = sc->port[i]; 2353 MPASS(pi != NULL); 2354 MPASS(pi->vi != NULL); 2355 MPASS(pi->vi[0].dev == pi->dev); 2356 2357 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 2358 if (rc != 0) { 2359 CH_ERR(sc, 2360 "failed to re-initialize port %d: %d\n", i, rc); 2361 goto done; 2362 } 2363 MPASS(sc->chan_map[pi->tx_chan] == i); 2364 2365 PORT_LOCK(pi); 2366 fixup_link_config(pi); 2367 build_medialist(pi); 2368 PORT_UNLOCK(pi); 2369 for_each_vi(pi, j, vi) { 2370 if (IS_MAIN_VI(vi)) 2371 continue; 2372 rc = alloc_extra_vi(sc, pi, vi); 2373 if (rc != 0) { 2374 CH_ERR(vi, 2375 "failed to re-allocate extra VI: %d\n", rc); 2376 goto done; 2377 } 2378 } 2379 } 2380 2381 /* 2382 * Interrupts and queues are about to be enabled and other threads will 2383 * want to access the hardware too. It is safe to do so. Note that 2384 * this thread is still in the middle of a synchronized_op. 2385 */ 2386 set_adapter_hwstatus(sc, true); 2387 2388 if (sc->flags & FULL_INIT_DONE) { 2389 rc = adapter_full_init(sc); 2390 if (rc != 0) { 2391 CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc); 2392 goto done; 2393 } 2394 2395 if (sc->vxlan_refcount > 0) 2396 enable_vxlan_rx(sc); 2397 2398 for_each_port(sc, i) { 2399 pi = sc->port[i]; 2400 for_each_vi(pi, j, vi) { 2401 mtx_lock(&vi->tick_mtx); 2402 vi->flags &= ~VI_SKIP_STATS; 2403 mtx_unlock(&vi->tick_mtx); 2404 if (!(vi->flags & VI_INIT_DONE)) 2405 continue; 2406 rc = vi_full_init(vi); 2407 if (rc != 0) { 2408 CH_ERR(vi, "failed to re-initialize " 2409 "interface: %d\n", rc); 2410 goto done; 2411 } 2412 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 2413 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 2414 t4_write_reg(sc, is_t4(sc) ? 2415 A_MPS_TRC_RSS_CONTROL : 2416 A_MPS_T5_TRC_RSS_CONTROL, 2417 V_RSSCONTROL(pi->tx_chan) | 2418 V_QUEUENUMBER(sc->traceq)); 2419 pi->flags |= HAS_TRACEQ; 2420 } 2421 2422 ifp = vi->ifp; 2423 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2424 continue; 2425 /* 2426 * Note that we do not setup multicast addresses 2427 * in the first pass. This ensures that the 2428 * unicast DMACs for all VIs on all ports get an 2429 * MPS TCAM entry. 2430 */ 2431 rc = update_mac_settings(ifp, XGMAC_ALL & 2432 ~XGMAC_MCADDRS); 2433 if (rc != 0) { 2434 CH_ERR(vi, "failed to re-configure MAC: %d\n", rc); 2435 goto done; 2436 } 2437 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, 2438 true); 2439 if (rc != 0) { 2440 CH_ERR(vi, "failed to re-enable VI: %d\n", rc); 2441 goto done; 2442 } 2443 for_each_txq(vi, k, txq) { 2444 TXQ_LOCK(txq); 2445 txq->eq.flags |= EQ_ENABLED; 2446 TXQ_UNLOCK(txq); 2447 } 2448 mtx_lock(&vi->tick_mtx); 2449 callout_schedule(&vi->tick, hz); 2450 mtx_unlock(&vi->tick_mtx); 2451 } 2452 PORT_LOCK(pi); 2453 if (pi->up_vis > 0) { 2454 t4_update_port_info(pi); 2455 fixup_link_config(pi); 2456 build_medialist(pi); 2457 apply_link_config(pi); 2458 if (pi->link_cfg.link_ok) 2459 t4_os_link_changed(pi); 2460 } 2461 PORT_UNLOCK(pi); 2462 } 2463 2464 /* Now reprogram the L2 multicast addresses. */ 2465 for_each_port(sc, i) { 2466 pi = sc->port[i]; 2467 for_each_vi(pi, j, vi) { 2468 if (!(vi->flags & VI_INIT_DONE)) 2469 continue; 2470 ifp = vi->ifp; 2471 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 2472 continue; 2473 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2474 if (rc != 0) { 2475 CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc); 2476 rc = 0; /* carry on */ 2477 } 2478 } 2479 } 2480 } 2481 2482 /* Reset all calibration */ 2483 t4_calibration_start(sc); 2484 done: 2485 end_synchronized_op(sc, 0); 2486 free(old_state, M_CXGBE); 2487 2488 restart_atid_allocator(sc); 2489 t4_restart_l2t(sc); 2490 2491 return (rc); 2492 } 2493 2494 int 2495 resume_adapter(struct adapter *sc) 2496 { 2497 restart_adapter(sc); 2498 restart_lld(sc); 2499 #ifdef TCP_OFFLOAD 2500 restart_all_uld(sc); 2501 #endif 2502 return (0); 2503 } 2504 2505 static int 2506 t4_resume(device_t dev) 2507 { 2508 struct adapter *sc = device_get_softc(dev); 2509 int rc; 2510 2511 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2512 rc = resume_adapter(sc); 2513 CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread); 2514 2515 return (rc); 2516 } 2517 2518 static int 2519 t4_reset_prepare(device_t dev, device_t child) 2520 { 2521 struct adapter *sc = device_get_softc(dev); 2522 2523 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2524 return (0); 2525 } 2526 2527 static int 2528 t4_reset_post(device_t dev, device_t child) 2529 { 2530 struct adapter *sc = device_get_softc(dev); 2531 2532 CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread); 2533 return (0); 2534 } 2535 2536 static int 2537 reset_adapter_with_pci_bus_reset(struct adapter *sc) 2538 { 2539 int rc; 2540 2541 mtx_lock(&Giant); 2542 rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0); 2543 mtx_unlock(&Giant); 2544 return (rc); 2545 } 2546 2547 static int 2548 reset_adapter_with_pl_rst(struct adapter *sc) 2549 { 2550 suspend_adapter(sc); 2551 2552 /* This is a t4_write_reg without the hw_off_limits check. */ 2553 MPASS(sc->error_flags & HW_OFF_LIMITS); 2554 bus_space_write_4(sc->bt, sc->bh, A_PL_RST, 2555 F_PIORSTMODE | F_PIORST | F_AUTOPCIEPAUSE); 2556 pause("pl_rst", 1 * hz); /* Wait 1s for reset */ 2557 2558 resume_adapter(sc); 2559 2560 return (0); 2561 } 2562 2563 static inline int 2564 reset_adapter(struct adapter *sc) 2565 { 2566 if (vm_guest == 0) 2567 return (reset_adapter_with_pci_bus_reset(sc)); 2568 else 2569 return (reset_adapter_with_pl_rst(sc)); 2570 } 2571 2572 static void 2573 reset_adapter_task(void *arg, int pending) 2574 { 2575 struct adapter *sc = arg; 2576 const int flags = sc->flags; 2577 const int eflags = sc->error_flags; 2578 int rc; 2579 2580 if (pending > 1) 2581 CH_ALERT(sc, "%s: pending %d\n", __func__, pending); 2582 rc = reset_adapter(sc); 2583 if (rc != 0) { 2584 CH_ERR(sc, "adapter did not reset properly, rc = %d, " 2585 "flags 0x%08x -> 0x%08x, err_flags 0x%08x -> 0x%08x.\n", 2586 rc, flags, sc->flags, eflags, sc->error_flags); 2587 } 2588 } 2589 2590 static int 2591 cxgbe_probe(device_t dev) 2592 { 2593 struct port_info *pi = device_get_softc(dev); 2594 2595 device_set_descf(dev, "port %d", pi->port_id); 2596 2597 return (BUS_PROBE_DEFAULT); 2598 } 2599 2600 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 2601 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 2602 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 2603 IFCAP_HWRXTSTMP | IFCAP_MEXTPG) 2604 #define T4_CAP_ENABLE (T4_CAP) 2605 2606 static void 2607 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 2608 { 2609 if_t ifp; 2610 struct sbuf *sb; 2611 struct sysctl_ctx_list *ctx = &vi->ctx; 2612 struct sysctl_oid_list *children; 2613 struct pfil_head_args pa; 2614 struct adapter *sc = vi->adapter; 2615 2616 sysctl_ctx_init(ctx); 2617 children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev)); 2618 vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq", 2619 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues"); 2620 vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq", 2621 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues"); 2622 #ifdef DEV_NETMAP 2623 vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq", 2624 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues"); 2625 vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq", 2626 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues"); 2627 #endif 2628 #ifdef TCP_OFFLOAD 2629 vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq", 2630 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues"); 2631 #endif 2632 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2633 vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq", 2634 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues"); 2635 #endif 2636 2637 vi->xact_addr_filt = -1; 2638 mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF); 2639 callout_init_mtx(&vi->tick, &vi->tick_mtx, 0); 2640 if (sc->flags & IS_VF || t4_tx_vm_wr != 0) 2641 vi->flags |= TX_USES_VM_WR; 2642 2643 /* Allocate an ifnet and set it up */ 2644 ifp = if_alloc_dev(IFT_ETHER, dev); 2645 vi->ifp = ifp; 2646 if_setsoftc(ifp, vi); 2647 2648 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2649 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2650 2651 if_setinitfn(ifp, cxgbe_init); 2652 if_setioctlfn(ifp, cxgbe_ioctl); 2653 if_settransmitfn(ifp, cxgbe_transmit); 2654 if_setqflushfn(ifp, cxgbe_qflush); 2655 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 2656 if_setgetcounterfn(ifp, vi_get_counter); 2657 else 2658 if_setgetcounterfn(ifp, cxgbe_get_counter); 2659 #if defined(KERN_TLS) || defined(RATELIMIT) 2660 if_setsndtagallocfn(ifp, cxgbe_snd_tag_alloc); 2661 #endif 2662 #ifdef RATELIMIT 2663 if_setratelimitqueryfn(ifp, cxgbe_ratelimit_query); 2664 #endif 2665 2666 if_setcapabilities(ifp, T4_CAP); 2667 if_setcapenable(ifp, T4_CAP_ENABLE); 2668 if_sethwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 2669 CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2670 if (chip_id(sc) >= CHELSIO_T6) { 2671 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2672 if_setcapenablebit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 2673 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 2674 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2675 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN, 0); 2676 } 2677 2678 #ifdef TCP_OFFLOAD 2679 if (vi->nofldrxq != 0) 2680 if_setcapabilitiesbit(ifp, IFCAP_TOE, 0); 2681 #endif 2682 #ifdef RATELIMIT 2683 if (is_ethoffload(sc) && vi->nofldtxq != 0) { 2684 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0); 2685 if_setcapenablebit(ifp, IFCAP_TXRTLMT, 0); 2686 } 2687 #endif 2688 2689 if_sethwtsomax(ifp, IP_MAXPACKET); 2690 if (vi->flags & TX_USES_VM_WR) 2691 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_VM_TSO); 2692 else 2693 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_TSO); 2694 #ifdef RATELIMIT 2695 if (is_ethoffload(sc) && vi->nofldtxq != 0) 2696 if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_EO_TSO); 2697 #endif 2698 if_sethwtsomaxsegsize(ifp, 65536); 2699 #ifdef KERN_TLS 2700 if (is_ktls(sc)) { 2701 if_setcapabilitiesbit(ifp, IFCAP_TXTLS, 0); 2702 if (sc->flags & KERN_TLS_ON || !is_t6(sc)) 2703 if_setcapenablebit(ifp, IFCAP_TXTLS, 0); 2704 } 2705 #endif 2706 2707 ether_ifattach(ifp, vi->hw_addr); 2708 #ifdef DEV_NETMAP 2709 if (vi->nnmrxq != 0) 2710 cxgbe_nm_attach(vi); 2711 #endif 2712 sb = sbuf_new_auto(); 2713 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 2714 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2715 switch (if_getcapabilities(ifp) & (IFCAP_TOE | IFCAP_TXRTLMT)) { 2716 case IFCAP_TOE: 2717 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 2718 break; 2719 case IFCAP_TOE | IFCAP_TXRTLMT: 2720 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 2721 break; 2722 case IFCAP_TXRTLMT: 2723 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 2724 break; 2725 } 2726 #endif 2727 #ifdef TCP_OFFLOAD 2728 if (if_getcapabilities(ifp) & IFCAP_TOE) 2729 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 2730 #endif 2731 #ifdef DEV_NETMAP 2732 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2733 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 2734 vi->nnmtxq, vi->nnmrxq); 2735 #endif 2736 sbuf_finish(sb); 2737 device_printf(dev, "%s\n", sbuf_data(sb)); 2738 sbuf_delete(sb); 2739 2740 vi_sysctls(vi); 2741 2742 pa.pa_version = PFIL_VERSION; 2743 pa.pa_flags = PFIL_IN; 2744 pa.pa_type = PFIL_TYPE_ETHERNET; 2745 pa.pa_headname = if_name(ifp); 2746 vi->pfil = pfil_head_register(&pa); 2747 } 2748 2749 static int 2750 cxgbe_attach(device_t dev) 2751 { 2752 struct port_info *pi = device_get_softc(dev); 2753 struct adapter *sc = pi->adapter; 2754 struct vi_info *vi; 2755 int i; 2756 2757 sysctl_ctx_init(&pi->ctx); 2758 2759 cxgbe_vi_attach(dev, &pi->vi[0]); 2760 2761 for_each_vi(pi, i, vi) { 2762 if (i == 0) 2763 continue; 2764 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, DEVICE_UNIT_ANY); 2765 if (vi->dev == NULL) { 2766 device_printf(dev, "failed to add VI %d\n", i); 2767 continue; 2768 } 2769 device_set_softc(vi->dev, vi); 2770 } 2771 2772 cxgbe_sysctls(pi); 2773 2774 bus_attach_children(dev); 2775 2776 return (0); 2777 } 2778 2779 static void 2780 cxgbe_vi_detach(struct vi_info *vi) 2781 { 2782 if_t ifp = vi->ifp; 2783 2784 if (vi->pfil != NULL) { 2785 pfil_head_unregister(vi->pfil); 2786 vi->pfil = NULL; 2787 } 2788 2789 ether_ifdetach(ifp); 2790 2791 /* Let detach proceed even if these fail. */ 2792 #ifdef DEV_NETMAP 2793 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 2794 cxgbe_nm_detach(vi); 2795 #endif 2796 cxgbe_uninit_synchronized(vi); 2797 callout_drain(&vi->tick); 2798 mtx_destroy(&vi->tick_mtx); 2799 sysctl_ctx_free(&vi->ctx); 2800 vi_full_uninit(vi); 2801 2802 if_free(vi->ifp); 2803 vi->ifp = NULL; 2804 } 2805 2806 static int 2807 cxgbe_detach(device_t dev) 2808 { 2809 struct port_info *pi = device_get_softc(dev); 2810 struct adapter *sc = pi->adapter; 2811 int rc; 2812 2813 /* Detach the extra VIs first. */ 2814 rc = bus_generic_detach(dev); 2815 if (rc) 2816 return (rc); 2817 2818 sysctl_ctx_free(&pi->ctx); 2819 begin_vi_detach(sc, &pi->vi[0]); 2820 if (pi->flags & HAS_TRACEQ) { 2821 sc->traceq = -1; /* cloner should not create ifnet */ 2822 t4_tracer_port_detach(sc); 2823 } 2824 cxgbe_vi_detach(&pi->vi[0]); 2825 ifmedia_removeall(&pi->media); 2826 end_vi_detach(sc, &pi->vi[0]); 2827 2828 return (0); 2829 } 2830 2831 static void 2832 cxgbe_init(void *arg) 2833 { 2834 struct vi_info *vi = arg; 2835 struct adapter *sc = vi->adapter; 2836 2837 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 2838 return; 2839 cxgbe_init_synchronized(vi); 2840 end_synchronized_op(sc, 0); 2841 } 2842 2843 static int 2844 cxgbe_ioctl(if_t ifp, unsigned long cmd, caddr_t data) 2845 { 2846 int rc = 0, mtu, flags; 2847 struct vi_info *vi = if_getsoftc(ifp); 2848 struct port_info *pi = vi->pi; 2849 struct adapter *sc = pi->adapter; 2850 struct ifreq *ifr = (struct ifreq *)data; 2851 uint32_t mask; 2852 2853 switch (cmd) { 2854 case SIOCSIFMTU: 2855 mtu = ifr->ifr_mtu; 2856 if (mtu < ETHERMIN || mtu > MAX_MTU) 2857 return (EINVAL); 2858 2859 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 2860 if (rc) 2861 return (rc); 2862 if_setmtu(ifp, mtu); 2863 if (vi->flags & VI_INIT_DONE) { 2864 t4_update_fl_bufsize(ifp); 2865 if (!hw_off_limits(sc) && 2866 if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2867 rc = update_mac_settings(ifp, XGMAC_MTU); 2868 } 2869 end_synchronized_op(sc, 0); 2870 break; 2871 2872 case SIOCSIFFLAGS: 2873 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 2874 if (rc) 2875 return (rc); 2876 2877 if (hw_off_limits(sc)) { 2878 rc = ENXIO; 2879 goto fail; 2880 } 2881 2882 if (if_getflags(ifp) & IFF_UP) { 2883 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2884 flags = vi->if_flags; 2885 if ((if_getflags(ifp) ^ flags) & 2886 (IFF_PROMISC | IFF_ALLMULTI)) { 2887 rc = update_mac_settings(ifp, 2888 XGMAC_PROMISC | XGMAC_ALLMULTI); 2889 } 2890 } else { 2891 rc = cxgbe_init_synchronized(vi); 2892 } 2893 vi->if_flags = if_getflags(ifp); 2894 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2895 rc = cxgbe_uninit_synchronized(vi); 2896 } 2897 end_synchronized_op(sc, 0); 2898 break; 2899 2900 case SIOCADDMULTI: 2901 case SIOCDELMULTI: 2902 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 2903 if (rc) 2904 return (rc); 2905 if (!hw_off_limits(sc) && if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2906 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2907 end_synchronized_op(sc, 0); 2908 break; 2909 2910 case SIOCSIFCAP: 2911 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 2912 if (rc) 2913 return (rc); 2914 2915 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2916 if (mask & IFCAP_TXCSUM) { 2917 if_togglecapenable(ifp, IFCAP_TXCSUM); 2918 if_togglehwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP); 2919 2920 if (IFCAP_TSO4 & if_getcapenable(ifp) && 2921 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2922 mask &= ~IFCAP_TSO4; 2923 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 2924 if_printf(ifp, 2925 "tso4 disabled due to -txcsum.\n"); 2926 } 2927 } 2928 if (mask & IFCAP_TXCSUM_IPV6) { 2929 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 2930 if_togglehwassist(ifp, CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2931 2932 if (IFCAP_TSO6 & if_getcapenable(ifp) && 2933 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2934 mask &= ~IFCAP_TSO6; 2935 if_setcapenablebit(ifp, 0, IFCAP_TSO6); 2936 if_printf(ifp, 2937 "tso6 disabled due to -txcsum6.\n"); 2938 } 2939 } 2940 if (mask & IFCAP_RXCSUM) 2941 if_togglecapenable(ifp, IFCAP_RXCSUM); 2942 if (mask & IFCAP_RXCSUM_IPV6) 2943 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 2944 2945 /* 2946 * Note that we leave CSUM_TSO alone (it is always set). The 2947 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 2948 * sending a TSO request our way, so it's sufficient to toggle 2949 * IFCAP_TSOx only. 2950 */ 2951 if (mask & IFCAP_TSO4) { 2952 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) && 2953 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 2954 if_printf(ifp, "enable txcsum first.\n"); 2955 rc = EAGAIN; 2956 goto fail; 2957 } 2958 if_togglecapenable(ifp, IFCAP_TSO4); 2959 } 2960 if (mask & IFCAP_TSO6) { 2961 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) && 2962 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 2963 if_printf(ifp, "enable txcsum6 first.\n"); 2964 rc = EAGAIN; 2965 goto fail; 2966 } 2967 if_togglecapenable(ifp, IFCAP_TSO6); 2968 } 2969 if (mask & IFCAP_LRO) { 2970 #if defined(INET) || defined(INET6) 2971 int i; 2972 struct sge_rxq *rxq; 2973 2974 if_togglecapenable(ifp, IFCAP_LRO); 2975 for_each_rxq(vi, i, rxq) { 2976 if (if_getcapenable(ifp) & IFCAP_LRO) 2977 rxq->iq.flags |= IQ_LRO_ENABLED; 2978 else 2979 rxq->iq.flags &= ~IQ_LRO_ENABLED; 2980 } 2981 #endif 2982 } 2983 #ifdef TCP_OFFLOAD 2984 if (mask & IFCAP_TOE) { 2985 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TOE; 2986 2987 rc = toe_capability(vi, enable); 2988 if (rc != 0) 2989 goto fail; 2990 2991 if_togglecapenable(ifp, mask); 2992 } 2993 #endif 2994 if (mask & IFCAP_VLAN_HWTAGGING) { 2995 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2996 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2997 rc = update_mac_settings(ifp, XGMAC_VLANEX); 2998 } 2999 if (mask & IFCAP_VLAN_MTU) { 3000 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 3001 3002 /* Need to find out how to disable auto-mtu-inflation */ 3003 } 3004 if (mask & IFCAP_VLAN_HWTSO) 3005 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3006 if (mask & IFCAP_VLAN_HWCSUM) 3007 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3008 #ifdef RATELIMIT 3009 if (mask & IFCAP_TXRTLMT) 3010 if_togglecapenable(ifp, IFCAP_TXRTLMT); 3011 #endif 3012 if (mask & IFCAP_HWRXTSTMP) { 3013 int i; 3014 struct sge_rxq *rxq; 3015 3016 if_togglecapenable(ifp, IFCAP_HWRXTSTMP); 3017 for_each_rxq(vi, i, rxq) { 3018 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) 3019 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3020 else 3021 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 3022 } 3023 } 3024 if (mask & IFCAP_MEXTPG) 3025 if_togglecapenable(ifp, IFCAP_MEXTPG); 3026 3027 #ifdef KERN_TLS 3028 if (mask & IFCAP_TXTLS) { 3029 int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TXTLS; 3030 3031 rc = ktls_capability(sc, enable); 3032 if (rc != 0) 3033 goto fail; 3034 3035 if_togglecapenable(ifp, mask & IFCAP_TXTLS); 3036 } 3037 #endif 3038 if (mask & IFCAP_VXLAN_HWCSUM) { 3039 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM); 3040 if_togglehwassist(ifp, CSUM_INNER_IP6_UDP | 3041 CSUM_INNER_IP6_TCP | CSUM_INNER_IP | 3042 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP); 3043 } 3044 if (mask & IFCAP_VXLAN_HWTSO) { 3045 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO); 3046 if_togglehwassist(ifp, CSUM_INNER_IP6_TSO | 3047 CSUM_INNER_IP_TSO); 3048 } 3049 3050 #ifdef VLAN_CAPABILITIES 3051 VLAN_CAPABILITIES(ifp); 3052 #endif 3053 fail: 3054 end_synchronized_op(sc, 0); 3055 break; 3056 3057 case SIOCSIFMEDIA: 3058 case SIOCGIFMEDIA: 3059 case SIOCGIFXMEDIA: 3060 rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 3061 break; 3062 3063 case SIOCGI2C: { 3064 struct ifi2creq i2c; 3065 3066 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3067 if (rc != 0) 3068 break; 3069 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3070 rc = EPERM; 3071 break; 3072 } 3073 if (i2c.len > sizeof(i2c.data)) { 3074 rc = EINVAL; 3075 break; 3076 } 3077 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 3078 if (rc) 3079 return (rc); 3080 if (hw_off_limits(sc)) 3081 rc = ENXIO; 3082 else 3083 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 3084 i2c.offset, i2c.len, &i2c.data[0]); 3085 end_synchronized_op(sc, 0); 3086 if (rc == 0) 3087 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3088 break; 3089 } 3090 3091 default: 3092 rc = ether_ioctl(ifp, cmd, data); 3093 } 3094 3095 return (rc); 3096 } 3097 3098 static int 3099 cxgbe_transmit(if_t ifp, struct mbuf *m) 3100 { 3101 struct vi_info *vi = if_getsoftc(ifp); 3102 struct port_info *pi = vi->pi; 3103 struct adapter *sc; 3104 struct sge_txq *txq; 3105 void *items[1]; 3106 int rc; 3107 3108 M_ASSERTPKTHDR(m); 3109 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 3110 #if defined(KERN_TLS) || defined(RATELIMIT) 3111 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) 3112 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 3113 #endif 3114 3115 if (__predict_false(pi->link_cfg.link_ok == false)) { 3116 m_freem(m); 3117 return (ENETDOWN); 3118 } 3119 3120 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR); 3121 if (__predict_false(rc != 0)) { 3122 if (__predict_true(rc == EINPROGRESS)) { 3123 /* queued by parse_pkt */ 3124 MPASS(m != NULL); 3125 return (0); 3126 } 3127 3128 MPASS(m == NULL); /* was freed already */ 3129 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 3130 return (rc); 3131 } 3132 3133 /* Select a txq. */ 3134 sc = vi->adapter; 3135 txq = &sc->sge.txq[vi->first_txq]; 3136 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 3137 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 3138 vi->rsrv_noflowq); 3139 3140 items[0] = m; 3141 rc = mp_ring_enqueue(txq->r, items, 1, 256); 3142 if (__predict_false(rc != 0)) 3143 m_freem(m); 3144 3145 return (rc); 3146 } 3147 3148 static void 3149 cxgbe_qflush(if_t ifp) 3150 { 3151 struct vi_info *vi = if_getsoftc(ifp); 3152 struct sge_txq *txq; 3153 int i; 3154 3155 /* queues do not exist if !VI_INIT_DONE. */ 3156 if (vi->flags & VI_INIT_DONE) { 3157 for_each_txq(vi, i, txq) { 3158 TXQ_LOCK(txq); 3159 txq->eq.flags |= EQ_QFLUSH; 3160 TXQ_UNLOCK(txq); 3161 while (!mp_ring_is_idle(txq->r)) { 3162 mp_ring_check_drainage(txq->r, 4096); 3163 pause("qflush", 1); 3164 } 3165 TXQ_LOCK(txq); 3166 txq->eq.flags &= ~EQ_QFLUSH; 3167 TXQ_UNLOCK(txq); 3168 } 3169 } 3170 if_qflush(ifp); 3171 } 3172 3173 static uint64_t 3174 vi_get_counter(if_t ifp, ift_counter c) 3175 { 3176 struct vi_info *vi = if_getsoftc(ifp); 3177 struct fw_vi_stats_vf *s = &vi->stats; 3178 3179 mtx_lock(&vi->tick_mtx); 3180 vi_refresh_stats(vi); 3181 mtx_unlock(&vi->tick_mtx); 3182 3183 switch (c) { 3184 case IFCOUNTER_IPACKETS: 3185 return (s->rx_bcast_frames + s->rx_mcast_frames + 3186 s->rx_ucast_frames); 3187 case IFCOUNTER_IERRORS: 3188 return (s->rx_err_frames); 3189 case IFCOUNTER_OPACKETS: 3190 return (s->tx_bcast_frames + s->tx_mcast_frames + 3191 s->tx_ucast_frames + s->tx_offload_frames); 3192 case IFCOUNTER_OERRORS: 3193 return (s->tx_drop_frames); 3194 case IFCOUNTER_IBYTES: 3195 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 3196 s->rx_ucast_bytes); 3197 case IFCOUNTER_OBYTES: 3198 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 3199 s->tx_ucast_bytes + s->tx_offload_bytes); 3200 case IFCOUNTER_IMCASTS: 3201 return (s->rx_mcast_frames); 3202 case IFCOUNTER_OMCASTS: 3203 return (s->tx_mcast_frames); 3204 case IFCOUNTER_OQDROPS: { 3205 uint64_t drops; 3206 3207 drops = 0; 3208 if (vi->flags & VI_INIT_DONE) { 3209 int i; 3210 struct sge_txq *txq; 3211 3212 for_each_txq(vi, i, txq) 3213 drops += counter_u64_fetch(txq->r->dropped); 3214 } 3215 3216 return (drops); 3217 3218 } 3219 3220 default: 3221 return (if_get_counter_default(ifp, c)); 3222 } 3223 } 3224 3225 static uint64_t 3226 cxgbe_get_counter(if_t ifp, ift_counter c) 3227 { 3228 struct vi_info *vi = if_getsoftc(ifp); 3229 struct port_info *pi = vi->pi; 3230 struct port_stats *s = &pi->stats; 3231 3232 mtx_lock(&vi->tick_mtx); 3233 cxgbe_refresh_stats(vi); 3234 mtx_unlock(&vi->tick_mtx); 3235 3236 switch (c) { 3237 case IFCOUNTER_IPACKETS: 3238 return (s->rx_frames); 3239 3240 case IFCOUNTER_IERRORS: 3241 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 3242 s->rx_fcs_err + s->rx_len_err); 3243 3244 case IFCOUNTER_OPACKETS: 3245 return (s->tx_frames); 3246 3247 case IFCOUNTER_OERRORS: 3248 return (s->tx_error_frames); 3249 3250 case IFCOUNTER_IBYTES: 3251 return (s->rx_octets); 3252 3253 case IFCOUNTER_OBYTES: 3254 return (s->tx_octets); 3255 3256 case IFCOUNTER_IMCASTS: 3257 return (s->rx_mcast_frames); 3258 3259 case IFCOUNTER_OMCASTS: 3260 return (s->tx_mcast_frames); 3261 3262 case IFCOUNTER_IQDROPS: 3263 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 3264 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 3265 s->rx_trunc3 + pi->tnl_cong_drops); 3266 3267 case IFCOUNTER_OQDROPS: { 3268 uint64_t drops; 3269 3270 drops = s->tx_drop; 3271 if (vi->flags & VI_INIT_DONE) { 3272 int i; 3273 struct sge_txq *txq; 3274 3275 for_each_txq(vi, i, txq) 3276 drops += counter_u64_fetch(txq->r->dropped); 3277 } 3278 3279 return (drops); 3280 3281 } 3282 3283 default: 3284 return (if_get_counter_default(ifp, c)); 3285 } 3286 } 3287 3288 #if defined(KERN_TLS) || defined(RATELIMIT) 3289 static int 3290 cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params, 3291 struct m_snd_tag **pt) 3292 { 3293 int error; 3294 3295 switch (params->hdr.type) { 3296 #ifdef RATELIMIT 3297 case IF_SND_TAG_TYPE_RATE_LIMIT: 3298 error = cxgbe_rate_tag_alloc(ifp, params, pt); 3299 break; 3300 #endif 3301 #ifdef KERN_TLS 3302 case IF_SND_TAG_TYPE_TLS: 3303 { 3304 struct vi_info *vi = if_getsoftc(ifp); 3305 3306 if (is_t6(vi->pi->adapter)) 3307 error = t6_tls_tag_alloc(ifp, params, pt); 3308 else 3309 error = EOPNOTSUPP; 3310 break; 3311 } 3312 #endif 3313 default: 3314 error = EOPNOTSUPP; 3315 } 3316 return (error); 3317 } 3318 #endif 3319 3320 /* 3321 * The kernel picks a media from the list we had provided but we still validate 3322 * the requeste. 3323 */ 3324 int 3325 cxgbe_media_change(if_t ifp) 3326 { 3327 struct vi_info *vi = if_getsoftc(ifp); 3328 struct port_info *pi = vi->pi; 3329 struct ifmedia *ifm = &pi->media; 3330 struct link_config *lc = &pi->link_cfg; 3331 struct adapter *sc = pi->adapter; 3332 int rc; 3333 3334 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 3335 if (rc != 0) 3336 return (rc); 3337 PORT_LOCK(pi); 3338 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 3339 /* ifconfig .. media autoselect */ 3340 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { 3341 rc = ENOTSUP; /* AN not supported by transceiver */ 3342 goto done; 3343 } 3344 lc->requested_aneg = AUTONEG_ENABLE; 3345 lc->requested_speed = 0; 3346 lc->requested_fc |= PAUSE_AUTONEG; 3347 } else { 3348 lc->requested_aneg = AUTONEG_DISABLE; 3349 lc->requested_speed = 3350 ifmedia_baudrate(ifm->ifm_media) / 1000000; 3351 lc->requested_fc = 0; 3352 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 3353 lc->requested_fc |= PAUSE_RX; 3354 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 3355 lc->requested_fc |= PAUSE_TX; 3356 } 3357 if (pi->up_vis > 0 && !hw_off_limits(sc)) { 3358 fixup_link_config(pi); 3359 rc = apply_link_config(pi); 3360 } 3361 done: 3362 PORT_UNLOCK(pi); 3363 end_synchronized_op(sc, 0); 3364 return (rc); 3365 } 3366 3367 /* 3368 * Base media word (without ETHER, pause, link active, etc.) for the port at the 3369 * given speed. 3370 */ 3371 static int 3372 port_mword(struct port_info *pi, uint32_t speed) 3373 { 3374 3375 MPASS(speed & M_FW_PORT_CAP32_SPEED); 3376 MPASS(powerof2(speed)); 3377 3378 switch(pi->port_type) { 3379 case FW_PORT_TYPE_BT_SGMII: 3380 case FW_PORT_TYPE_BT_XFI: 3381 case FW_PORT_TYPE_BT_XAUI: 3382 /* BaseT */ 3383 switch (speed) { 3384 case FW_PORT_CAP32_SPEED_100M: 3385 return (IFM_100_T); 3386 case FW_PORT_CAP32_SPEED_1G: 3387 return (IFM_1000_T); 3388 case FW_PORT_CAP32_SPEED_10G: 3389 return (IFM_10G_T); 3390 } 3391 break; 3392 case FW_PORT_TYPE_KX4: 3393 if (speed == FW_PORT_CAP32_SPEED_10G) 3394 return (IFM_10G_KX4); 3395 break; 3396 case FW_PORT_TYPE_CX4: 3397 if (speed == FW_PORT_CAP32_SPEED_10G) 3398 return (IFM_10G_CX4); 3399 break; 3400 case FW_PORT_TYPE_KX: 3401 if (speed == FW_PORT_CAP32_SPEED_1G) 3402 return (IFM_1000_KX); 3403 break; 3404 case FW_PORT_TYPE_KR: 3405 case FW_PORT_TYPE_BP_AP: 3406 case FW_PORT_TYPE_BP4_AP: 3407 case FW_PORT_TYPE_BP40_BA: 3408 case FW_PORT_TYPE_KR4_100G: 3409 case FW_PORT_TYPE_KR_SFP28: 3410 case FW_PORT_TYPE_KR_XLAUI: 3411 switch (speed) { 3412 case FW_PORT_CAP32_SPEED_1G: 3413 return (IFM_1000_KX); 3414 case FW_PORT_CAP32_SPEED_10G: 3415 return (IFM_10G_KR); 3416 case FW_PORT_CAP32_SPEED_25G: 3417 return (IFM_25G_KR); 3418 case FW_PORT_CAP32_SPEED_40G: 3419 return (IFM_40G_KR4); 3420 case FW_PORT_CAP32_SPEED_50G: 3421 return (IFM_50G_KR2); 3422 case FW_PORT_CAP32_SPEED_100G: 3423 return (IFM_100G_KR4); 3424 } 3425 break; 3426 case FW_PORT_TYPE_FIBER_XFI: 3427 case FW_PORT_TYPE_FIBER_XAUI: 3428 case FW_PORT_TYPE_SFP: 3429 case FW_PORT_TYPE_QSFP_10G: 3430 case FW_PORT_TYPE_QSA: 3431 case FW_PORT_TYPE_QSFP: 3432 case FW_PORT_TYPE_CR4_QSFP: 3433 case FW_PORT_TYPE_CR_QSFP: 3434 case FW_PORT_TYPE_CR2_QSFP: 3435 case FW_PORT_TYPE_SFP28: 3436 /* Pluggable transceiver */ 3437 switch (pi->mod_type) { 3438 case FW_PORT_MOD_TYPE_LR: 3439 switch (speed) { 3440 case FW_PORT_CAP32_SPEED_1G: 3441 return (IFM_1000_LX); 3442 case FW_PORT_CAP32_SPEED_10G: 3443 return (IFM_10G_LR); 3444 case FW_PORT_CAP32_SPEED_25G: 3445 return (IFM_25G_LR); 3446 case FW_PORT_CAP32_SPEED_40G: 3447 return (IFM_40G_LR4); 3448 case FW_PORT_CAP32_SPEED_50G: 3449 return (IFM_50G_LR2); 3450 case FW_PORT_CAP32_SPEED_100G: 3451 return (IFM_100G_LR4); 3452 } 3453 break; 3454 case FW_PORT_MOD_TYPE_SR: 3455 switch (speed) { 3456 case FW_PORT_CAP32_SPEED_1G: 3457 return (IFM_1000_SX); 3458 case FW_PORT_CAP32_SPEED_10G: 3459 return (IFM_10G_SR); 3460 case FW_PORT_CAP32_SPEED_25G: 3461 return (IFM_25G_SR); 3462 case FW_PORT_CAP32_SPEED_40G: 3463 return (IFM_40G_SR4); 3464 case FW_PORT_CAP32_SPEED_50G: 3465 return (IFM_50G_SR2); 3466 case FW_PORT_CAP32_SPEED_100G: 3467 return (IFM_100G_SR4); 3468 } 3469 break; 3470 case FW_PORT_MOD_TYPE_ER: 3471 if (speed == FW_PORT_CAP32_SPEED_10G) 3472 return (IFM_10G_ER); 3473 break; 3474 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3475 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3476 switch (speed) { 3477 case FW_PORT_CAP32_SPEED_1G: 3478 return (IFM_1000_CX); 3479 case FW_PORT_CAP32_SPEED_10G: 3480 return (IFM_10G_TWINAX); 3481 case FW_PORT_CAP32_SPEED_25G: 3482 return (IFM_25G_CR); 3483 case FW_PORT_CAP32_SPEED_40G: 3484 return (IFM_40G_CR4); 3485 case FW_PORT_CAP32_SPEED_50G: 3486 return (IFM_50G_CR2); 3487 case FW_PORT_CAP32_SPEED_100G: 3488 return (IFM_100G_CR4); 3489 } 3490 break; 3491 case FW_PORT_MOD_TYPE_LRM: 3492 if (speed == FW_PORT_CAP32_SPEED_10G) 3493 return (IFM_10G_LRM); 3494 break; 3495 case FW_PORT_MOD_TYPE_NA: 3496 MPASS(0); /* Not pluggable? */ 3497 /* fall throough */ 3498 case FW_PORT_MOD_TYPE_ERROR: 3499 case FW_PORT_MOD_TYPE_UNKNOWN: 3500 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 3501 break; 3502 case FW_PORT_MOD_TYPE_NONE: 3503 return (IFM_NONE); 3504 } 3505 break; 3506 case FW_PORT_TYPE_NONE: 3507 return (IFM_NONE); 3508 } 3509 3510 return (IFM_UNKNOWN); 3511 } 3512 3513 void 3514 cxgbe_media_status(if_t ifp, struct ifmediareq *ifmr) 3515 { 3516 struct vi_info *vi = if_getsoftc(ifp); 3517 struct port_info *pi = vi->pi; 3518 struct adapter *sc = pi->adapter; 3519 struct link_config *lc = &pi->link_cfg; 3520 3521 if (begin_synchronized_op(sc, vi , SLEEP_OK | INTR_OK, "t4med") != 0) 3522 return; 3523 PORT_LOCK(pi); 3524 3525 if (pi->up_vis == 0 && !hw_off_limits(sc)) { 3526 /* 3527 * If all the interfaces are administratively down the firmware 3528 * does not report transceiver changes. Refresh port info here 3529 * so that ifconfig displays accurate ifmedia at all times. 3530 * This is the only reason we have a synchronized op in this 3531 * function. Just PORT_LOCK would have been enough otherwise. 3532 */ 3533 t4_update_port_info(pi); 3534 build_medialist(pi); 3535 } 3536 3537 /* ifm_status */ 3538 ifmr->ifm_status = IFM_AVALID; 3539 if (lc->link_ok == false) 3540 goto done; 3541 ifmr->ifm_status |= IFM_ACTIVE; 3542 3543 /* ifm_active */ 3544 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 3545 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 3546 if (lc->fc & PAUSE_RX) 3547 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3548 if (lc->fc & PAUSE_TX) 3549 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3550 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 3551 done: 3552 PORT_UNLOCK(pi); 3553 end_synchronized_op(sc, 0); 3554 } 3555 3556 static int 3557 vcxgbe_probe(device_t dev) 3558 { 3559 struct vi_info *vi = device_get_softc(dev); 3560 3561 device_set_descf(dev, "port %d vi %td", vi->pi->port_id, 3562 vi - vi->pi->vi); 3563 3564 return (BUS_PROBE_DEFAULT); 3565 } 3566 3567 static int 3568 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 3569 { 3570 int func, index, rc; 3571 uint32_t param, val; 3572 3573 ASSERT_SYNCHRONIZED_OP(sc); 3574 3575 index = vi - pi->vi; 3576 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 3577 KASSERT(index < nitems(vi_mac_funcs), 3578 ("%s: VI %s doesn't have a MAC func", __func__, 3579 device_get_nameunit(vi->dev))); 3580 func = vi_mac_funcs[index]; 3581 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 3582 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 3583 if (rc < 0) { 3584 CH_ERR(vi, "failed to allocate virtual interface %d" 3585 "for port %d: %d\n", index, pi->port_id, -rc); 3586 return (-rc); 3587 } 3588 vi->viid = rc; 3589 3590 if (vi->rss_size == 1) { 3591 /* 3592 * This VI didn't get a slice of the RSS table. Reduce the 3593 * number of VIs being created (hw.cxgbe.num_vis) or modify the 3594 * configuration file (nvi, rssnvi for this PF) if this is a 3595 * problem. 3596 */ 3597 device_printf(vi->dev, "RSS table not available.\n"); 3598 vi->rss_base = 0xffff; 3599 3600 return (0); 3601 } 3602 3603 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3604 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 3605 V_FW_PARAMS_PARAM_YZ(vi->viid); 3606 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3607 if (rc) 3608 vi->rss_base = 0xffff; 3609 else { 3610 MPASS((val >> 16) == vi->rss_size); 3611 vi->rss_base = val & 0xffff; 3612 } 3613 3614 return (0); 3615 } 3616 3617 static int 3618 vcxgbe_attach(device_t dev) 3619 { 3620 struct vi_info *vi; 3621 struct port_info *pi; 3622 struct adapter *sc; 3623 int rc; 3624 3625 vi = device_get_softc(dev); 3626 pi = vi->pi; 3627 sc = pi->adapter; 3628 3629 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 3630 if (rc) 3631 return (rc); 3632 rc = alloc_extra_vi(sc, pi, vi); 3633 end_synchronized_op(sc, 0); 3634 if (rc) 3635 return (rc); 3636 3637 cxgbe_vi_attach(dev, vi); 3638 3639 return (0); 3640 } 3641 3642 static int 3643 vcxgbe_detach(device_t dev) 3644 { 3645 struct vi_info *vi; 3646 struct adapter *sc; 3647 3648 vi = device_get_softc(dev); 3649 sc = vi->adapter; 3650 3651 begin_vi_detach(sc, vi); 3652 cxgbe_vi_detach(vi); 3653 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3654 end_vi_detach(sc, vi); 3655 3656 return (0); 3657 } 3658 3659 static struct callout fatal_callout; 3660 static struct taskqueue *reset_tq; 3661 3662 static void 3663 delayed_panic(void *arg) 3664 { 3665 struct adapter *sc = arg; 3666 3667 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 3668 } 3669 3670 static void 3671 fatal_error_task(void *arg, int pending) 3672 { 3673 struct adapter *sc = arg; 3674 int rc; 3675 3676 if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) { 3677 dump_cim_regs(sc); 3678 dump_cimla(sc); 3679 dump_devlog(sc); 3680 } 3681 3682 if (t4_reset_on_fatal_err) { 3683 CH_ALERT(sc, "resetting adapter after fatal error.\n"); 3684 rc = reset_adapter(sc); 3685 if (rc == 0 && t4_panic_on_fatal_err) { 3686 CH_ALERT(sc, "reset was successful, " 3687 "system will NOT panic.\n"); 3688 return; 3689 } 3690 } 3691 3692 if (t4_panic_on_fatal_err) { 3693 CH_ALERT(sc, "panicking on fatal error (after 30s).\n"); 3694 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 3695 } 3696 } 3697 3698 void 3699 t4_fatal_err(struct adapter *sc, bool fw_error) 3700 { 3701 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 3702 3703 stop_adapter(sc); 3704 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR))) 3705 return; 3706 if (fw_error) { 3707 /* 3708 * We are here because of a firmware error/timeout and not 3709 * because of a hardware interrupt. It is possible (although 3710 * not very likely) that an error interrupt was also raised but 3711 * this thread ran first and inhibited t4_intr_err. We walk the 3712 * main INT_CAUSE registers here to make sure we haven't missed 3713 * anything interesting. 3714 */ 3715 t4_slow_intr_handler(sc, verbose); 3716 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 3717 } 3718 t4_report_fw_error(sc); 3719 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n", 3720 device_get_nameunit(sc->dev), fw_error); 3721 taskqueue_enqueue(reset_tq, &sc->fatal_error_task); 3722 } 3723 3724 void 3725 t4_add_adapter(struct adapter *sc) 3726 { 3727 sx_xlock(&t4_list_lock); 3728 SLIST_INSERT_HEAD(&t4_list, sc, link); 3729 sx_xunlock(&t4_list_lock); 3730 } 3731 3732 int 3733 t4_map_bars_0_and_4(struct adapter *sc) 3734 { 3735 sc->regs_rid = PCIR_BAR(0); 3736 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3737 &sc->regs_rid, RF_ACTIVE); 3738 if (sc->regs_res == NULL) { 3739 device_printf(sc->dev, "cannot map registers.\n"); 3740 return (ENXIO); 3741 } 3742 sc->bt = rman_get_bustag(sc->regs_res); 3743 sc->bh = rman_get_bushandle(sc->regs_res); 3744 sc->mmio_len = rman_get_size(sc->regs_res); 3745 setbit(&sc->doorbells, DOORBELL_KDB); 3746 3747 sc->msix_rid = PCIR_BAR(4); 3748 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3749 &sc->msix_rid, RF_ACTIVE); 3750 if (sc->msix_res == NULL) { 3751 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 3752 return (ENXIO); 3753 } 3754 3755 return (0); 3756 } 3757 3758 int 3759 t4_map_bar_2(struct adapter *sc) 3760 { 3761 3762 /* 3763 * T4: only iWARP driver uses the userspace doorbells. There is no need 3764 * to map it if RDMA is disabled. 3765 */ 3766 if (is_t4(sc) && sc->rdmacaps == 0) 3767 return (0); 3768 3769 sc->udbs_rid = PCIR_BAR(2); 3770 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3771 &sc->udbs_rid, RF_ACTIVE); 3772 if (sc->udbs_res == NULL) { 3773 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 3774 return (ENXIO); 3775 } 3776 sc->udbs_base = rman_get_virtual(sc->udbs_res); 3777 3778 if (chip_id(sc) >= CHELSIO_T5) { 3779 setbit(&sc->doorbells, DOORBELL_UDB); 3780 #if defined(__i386__) || defined(__amd64__) 3781 if (t5_write_combine) { 3782 int rc, mode; 3783 3784 /* 3785 * Enable write combining on BAR2. This is the 3786 * userspace doorbell BAR and is split into 128B 3787 * (UDBS_SEG_SIZE) doorbell regions, each associated 3788 * with an egress queue. The first 64B has the doorbell 3789 * and the second 64B can be used to submit a tx work 3790 * request with an implicit doorbell. 3791 */ 3792 3793 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 3794 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 3795 if (rc == 0) { 3796 clrbit(&sc->doorbells, DOORBELL_UDB); 3797 setbit(&sc->doorbells, DOORBELL_WCWR); 3798 setbit(&sc->doorbells, DOORBELL_UDBWC); 3799 } else { 3800 device_printf(sc->dev, 3801 "couldn't enable write combining: %d\n", 3802 rc); 3803 } 3804 3805 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 3806 t4_write_reg(sc, A_SGE_STAT_CFG, 3807 V_STATSOURCE_T5(7) | mode); 3808 } 3809 #endif 3810 } 3811 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 3812 3813 return (0); 3814 } 3815 3816 int 3817 t4_adj_doorbells(struct adapter *sc) 3818 { 3819 if ((sc->doorbells & t4_doorbells_allowed) != 0) { 3820 sc->doorbells &= t4_doorbells_allowed; 3821 return (0); 3822 } 3823 CH_ERR(sc, "No usable doorbell (available = 0x%x, allowed = 0x%x).\n", 3824 sc->doorbells, t4_doorbells_allowed); 3825 return (EINVAL); 3826 } 3827 3828 struct memwin_init { 3829 uint32_t base; 3830 uint32_t aperture; 3831 }; 3832 3833 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 3834 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3835 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3836 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 3837 }; 3838 3839 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 3840 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3841 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3842 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 3843 }; 3844 3845 static void 3846 setup_memwin(struct adapter *sc) 3847 { 3848 const struct memwin_init *mw_init; 3849 struct memwin *mw; 3850 int i; 3851 uint32_t bar0; 3852 3853 if (is_t4(sc)) { 3854 /* 3855 * Read low 32b of bar0 indirectly via the hardware backdoor 3856 * mechanism. Works from within PCI passthrough environments 3857 * too, where rman_get_start() can return a different value. We 3858 * need to program the T4 memory window decoders with the actual 3859 * addresses that will be coming across the PCIe link. 3860 */ 3861 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 3862 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 3863 3864 mw_init = &t4_memwin[0]; 3865 } else { 3866 /* T5+ use the relative offset inside the PCIe BAR */ 3867 bar0 = 0; 3868 3869 mw_init = &t5_memwin[0]; 3870 } 3871 3872 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 3873 if (!rw_initialized(&mw->mw_lock)) { 3874 rw_init(&mw->mw_lock, "memory window access"); 3875 mw->mw_base = mw_init->base; 3876 mw->mw_aperture = mw_init->aperture; 3877 mw->mw_curpos = 0; 3878 } 3879 t4_write_reg(sc, 3880 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 3881 (mw->mw_base + bar0) | V_BIR(0) | 3882 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 3883 rw_wlock(&mw->mw_lock); 3884 position_memwin(sc, i, mw->mw_curpos); 3885 rw_wunlock(&mw->mw_lock); 3886 } 3887 3888 /* flush */ 3889 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 3890 } 3891 3892 /* 3893 * Positions the memory window at the given address in the card's address space. 3894 * There are some alignment requirements and the actual position may be at an 3895 * address prior to the requested address. mw->mw_curpos always has the actual 3896 * position of the window. 3897 */ 3898 static void 3899 position_memwin(struct adapter *sc, int idx, uint32_t addr) 3900 { 3901 struct memwin *mw; 3902 uint32_t pf; 3903 uint32_t reg; 3904 3905 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3906 mw = &sc->memwin[idx]; 3907 rw_assert(&mw->mw_lock, RA_WLOCKED); 3908 3909 if (is_t4(sc)) { 3910 pf = 0; 3911 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 3912 } else { 3913 pf = V_PFNUM(sc->pf); 3914 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 3915 } 3916 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 3917 t4_write_reg(sc, reg, mw->mw_curpos | pf); 3918 t4_read_reg(sc, reg); /* flush */ 3919 } 3920 3921 int 3922 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 3923 int len, int rw) 3924 { 3925 struct memwin *mw; 3926 uint32_t mw_end, v; 3927 3928 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3929 3930 /* Memory can only be accessed in naturally aligned 4 byte units */ 3931 if (addr & 3 || len & 3 || len <= 0) 3932 return (EINVAL); 3933 3934 mw = &sc->memwin[idx]; 3935 while (len > 0) { 3936 rw_rlock(&mw->mw_lock); 3937 mw_end = mw->mw_curpos + mw->mw_aperture; 3938 if (addr >= mw_end || addr < mw->mw_curpos) { 3939 /* Will need to reposition the window */ 3940 if (!rw_try_upgrade(&mw->mw_lock)) { 3941 rw_runlock(&mw->mw_lock); 3942 rw_wlock(&mw->mw_lock); 3943 } 3944 rw_assert(&mw->mw_lock, RA_WLOCKED); 3945 position_memwin(sc, idx, addr); 3946 rw_downgrade(&mw->mw_lock); 3947 mw_end = mw->mw_curpos + mw->mw_aperture; 3948 } 3949 rw_assert(&mw->mw_lock, RA_RLOCKED); 3950 while (addr < mw_end && len > 0) { 3951 if (rw == 0) { 3952 v = t4_read_reg(sc, mw->mw_base + addr - 3953 mw->mw_curpos); 3954 *val++ = le32toh(v); 3955 } else { 3956 v = *val++; 3957 t4_write_reg(sc, mw->mw_base + addr - 3958 mw->mw_curpos, htole32(v)); 3959 } 3960 addr += 4; 3961 len -= 4; 3962 } 3963 rw_runlock(&mw->mw_lock); 3964 } 3965 3966 return (0); 3967 } 3968 3969 CTASSERT(M_TID_COOKIE == M_COOKIE); 3970 CTASSERT(MAX_ATIDS <= (M_TID_TID + 1)); 3971 3972 static void 3973 t4_init_atid_table(struct adapter *sc) 3974 { 3975 struct tid_info *t; 3976 int i; 3977 3978 t = &sc->tids; 3979 if (t->natids == 0) 3980 return; 3981 3982 MPASS(t->atid_tab == NULL); 3983 3984 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 3985 M_ZERO | M_WAITOK); 3986 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 3987 t->afree = t->atid_tab; 3988 t->atids_in_use = 0; 3989 t->atid_alloc_stopped = false; 3990 for (i = 1; i < t->natids; i++) 3991 t->atid_tab[i - 1].next = &t->atid_tab[i]; 3992 t->atid_tab[t->natids - 1].next = NULL; 3993 } 3994 3995 static void 3996 t4_free_atid_table(struct adapter *sc) 3997 { 3998 struct tid_info *t; 3999 4000 t = &sc->tids; 4001 4002 KASSERT(t->atids_in_use == 0, 4003 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 4004 4005 if (mtx_initialized(&t->atid_lock)) 4006 mtx_destroy(&t->atid_lock); 4007 free(t->atid_tab, M_CXGBE); 4008 t->atid_tab = NULL; 4009 } 4010 4011 static void 4012 stop_atid_allocator(struct adapter *sc) 4013 { 4014 struct tid_info *t = &sc->tids; 4015 4016 mtx_lock(&t->atid_lock); 4017 t->atid_alloc_stopped = true; 4018 mtx_unlock(&t->atid_lock); 4019 } 4020 4021 static void 4022 restart_atid_allocator(struct adapter *sc) 4023 { 4024 struct tid_info *t = &sc->tids; 4025 4026 mtx_lock(&t->atid_lock); 4027 KASSERT(t->atids_in_use == 0, 4028 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 4029 t->atid_alloc_stopped = false; 4030 mtx_unlock(&t->atid_lock); 4031 } 4032 4033 int 4034 alloc_atid(struct adapter *sc, void *ctx) 4035 { 4036 struct tid_info *t = &sc->tids; 4037 int atid = -1; 4038 4039 mtx_lock(&t->atid_lock); 4040 if (t->afree && !t->atid_alloc_stopped) { 4041 union aopen_entry *p = t->afree; 4042 4043 atid = p - t->atid_tab; 4044 MPASS(atid <= M_TID_TID); 4045 t->afree = p->next; 4046 p->data = ctx; 4047 t->atids_in_use++; 4048 } 4049 mtx_unlock(&t->atid_lock); 4050 return (atid); 4051 } 4052 4053 void * 4054 lookup_atid(struct adapter *sc, int atid) 4055 { 4056 struct tid_info *t = &sc->tids; 4057 4058 return (t->atid_tab[atid].data); 4059 } 4060 4061 void 4062 free_atid(struct adapter *sc, int atid) 4063 { 4064 struct tid_info *t = &sc->tids; 4065 union aopen_entry *p = &t->atid_tab[atid]; 4066 4067 mtx_lock(&t->atid_lock); 4068 p->next = t->afree; 4069 t->afree = p; 4070 t->atids_in_use--; 4071 mtx_unlock(&t->atid_lock); 4072 } 4073 4074 static void 4075 queue_tid_release(struct adapter *sc, int tid) 4076 { 4077 4078 CXGBE_UNIMPLEMENTED("deferred tid release"); 4079 } 4080 4081 void 4082 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 4083 { 4084 struct wrqe *wr; 4085 struct cpl_tid_release *req; 4086 4087 wr = alloc_wrqe(sizeof(*req), ctrlq); 4088 if (wr == NULL) { 4089 queue_tid_release(sc, tid); /* defer */ 4090 return; 4091 } 4092 req = wrtod(wr); 4093 4094 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 4095 4096 t4_wrq_tx(sc, wr); 4097 } 4098 4099 static int 4100 t4_range_cmp(const void *a, const void *b) 4101 { 4102 return ((const struct t4_range *)a)->start - 4103 ((const struct t4_range *)b)->start; 4104 } 4105 4106 /* 4107 * Verify that the memory range specified by the addr/len pair is valid within 4108 * the card's address space. 4109 */ 4110 static int 4111 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 4112 { 4113 struct t4_range mem_ranges[4], *r, *next; 4114 uint32_t em, addr_len; 4115 int i, n, remaining; 4116 4117 /* Memory can only be accessed in naturally aligned 4 byte units */ 4118 if (addr & 3 || len & 3 || len == 0) 4119 return (EINVAL); 4120 4121 /* Enabled memories */ 4122 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4123 4124 r = &mem_ranges[0]; 4125 n = 0; 4126 bzero(r, sizeof(mem_ranges)); 4127 if (em & F_EDRAM0_ENABLE) { 4128 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4129 r->size = G_EDRAM0_SIZE(addr_len) << 20; 4130 if (r->size > 0) { 4131 r->start = G_EDRAM0_BASE(addr_len) << 20; 4132 if (addr >= r->start && 4133 addr + len <= r->start + r->size) 4134 return (0); 4135 r++; 4136 n++; 4137 } 4138 } 4139 if (em & F_EDRAM1_ENABLE) { 4140 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4141 r->size = G_EDRAM1_SIZE(addr_len) << 20; 4142 if (r->size > 0) { 4143 r->start = G_EDRAM1_BASE(addr_len) << 20; 4144 if (addr >= r->start && 4145 addr + len <= r->start + r->size) 4146 return (0); 4147 r++; 4148 n++; 4149 } 4150 } 4151 if (em & F_EXT_MEM_ENABLE) { 4152 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4153 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 4154 if (r->size > 0) { 4155 r->start = G_EXT_MEM_BASE(addr_len) << 20; 4156 if (addr >= r->start && 4157 addr + len <= r->start + r->size) 4158 return (0); 4159 r++; 4160 n++; 4161 } 4162 } 4163 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 4164 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4165 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 4166 if (r->size > 0) { 4167 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 4168 if (addr >= r->start && 4169 addr + len <= r->start + r->size) 4170 return (0); 4171 r++; 4172 n++; 4173 } 4174 } 4175 MPASS(n <= nitems(mem_ranges)); 4176 4177 if (n > 1) { 4178 /* Sort and merge the ranges. */ 4179 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 4180 4181 /* Start from index 0 and examine the next n - 1 entries. */ 4182 r = &mem_ranges[0]; 4183 for (remaining = n - 1; remaining > 0; remaining--, r++) { 4184 4185 MPASS(r->size > 0); /* r is a valid entry. */ 4186 next = r + 1; 4187 MPASS(next->size > 0); /* and so is the next one. */ 4188 4189 while (r->start + r->size >= next->start) { 4190 /* Merge the next one into the current entry. */ 4191 r->size = max(r->start + r->size, 4192 next->start + next->size) - r->start; 4193 n--; /* One fewer entry in total. */ 4194 if (--remaining == 0) 4195 goto done; /* short circuit */ 4196 next++; 4197 } 4198 if (next != r + 1) { 4199 /* 4200 * Some entries were merged into r and next 4201 * points to the first valid entry that couldn't 4202 * be merged. 4203 */ 4204 MPASS(next->size > 0); /* must be valid */ 4205 memcpy(r + 1, next, remaining * sizeof(*r)); 4206 #ifdef INVARIANTS 4207 /* 4208 * This so that the foo->size assertion in the 4209 * next iteration of the loop do the right 4210 * thing for entries that were pulled up and are 4211 * no longer valid. 4212 */ 4213 MPASS(n < nitems(mem_ranges)); 4214 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 4215 sizeof(struct t4_range)); 4216 #endif 4217 } 4218 } 4219 done: 4220 /* Done merging the ranges. */ 4221 MPASS(n > 0); 4222 r = &mem_ranges[0]; 4223 for (i = 0; i < n; i++, r++) { 4224 if (addr >= r->start && 4225 addr + len <= r->start + r->size) 4226 return (0); 4227 } 4228 } 4229 4230 return (EFAULT); 4231 } 4232 4233 static int 4234 fwmtype_to_hwmtype(int mtype) 4235 { 4236 4237 switch (mtype) { 4238 case FW_MEMTYPE_EDC0: 4239 return (MEM_EDC0); 4240 case FW_MEMTYPE_EDC1: 4241 return (MEM_EDC1); 4242 case FW_MEMTYPE_EXTMEM: 4243 return (MEM_MC0); 4244 case FW_MEMTYPE_EXTMEM1: 4245 return (MEM_MC1); 4246 default: 4247 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 4248 } 4249 } 4250 4251 /* 4252 * Verify that the memory range specified by the memtype/offset/len pair is 4253 * valid and lies entirely within the memtype specified. The global address of 4254 * the start of the range is returned in addr. 4255 */ 4256 static int 4257 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 4258 uint32_t *addr) 4259 { 4260 uint32_t em, addr_len, maddr; 4261 4262 /* Memory can only be accessed in naturally aligned 4 byte units */ 4263 if (off & 3 || len & 3 || len == 0) 4264 return (EINVAL); 4265 4266 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4267 switch (fwmtype_to_hwmtype(mtype)) { 4268 case MEM_EDC0: 4269 if (!(em & F_EDRAM0_ENABLE)) 4270 return (EINVAL); 4271 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4272 maddr = G_EDRAM0_BASE(addr_len) << 20; 4273 break; 4274 case MEM_EDC1: 4275 if (!(em & F_EDRAM1_ENABLE)) 4276 return (EINVAL); 4277 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4278 maddr = G_EDRAM1_BASE(addr_len) << 20; 4279 break; 4280 case MEM_MC: 4281 if (!(em & F_EXT_MEM_ENABLE)) 4282 return (EINVAL); 4283 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4284 maddr = G_EXT_MEM_BASE(addr_len) << 20; 4285 break; 4286 case MEM_MC1: 4287 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 4288 return (EINVAL); 4289 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4290 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 4291 break; 4292 default: 4293 return (EINVAL); 4294 } 4295 4296 *addr = maddr + off; /* global address */ 4297 return (validate_mem_range(sc, *addr, len)); 4298 } 4299 4300 static int 4301 fixup_devlog_params(struct adapter *sc) 4302 { 4303 struct devlog_params *dparams = &sc->params.devlog; 4304 int rc; 4305 4306 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 4307 dparams->size, &dparams->addr); 4308 4309 return (rc); 4310 } 4311 4312 static void 4313 update_nirq(struct intrs_and_queues *iaq, int nports) 4314 { 4315 4316 iaq->nirq = T4_EXTRA_INTR; 4317 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq); 4318 iaq->nirq += nports * iaq->nofldrxq; 4319 iaq->nirq += nports * (iaq->num_vis - 1) * 4320 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 4321 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 4322 } 4323 4324 /* 4325 * Adjust requirements to fit the number of interrupts available. 4326 */ 4327 static void 4328 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 4329 int navail) 4330 { 4331 int old_nirq; 4332 const int nports = sc->params.nports; 4333 4334 MPASS(nports > 0); 4335 MPASS(navail > 0); 4336 4337 bzero(iaq, sizeof(*iaq)); 4338 iaq->intr_type = itype; 4339 iaq->num_vis = t4_num_vis; 4340 iaq->ntxq = t4_ntxq; 4341 iaq->ntxq_vi = t4_ntxq_vi; 4342 iaq->nrxq = t4_nrxq; 4343 iaq->nrxq_vi = t4_nrxq_vi; 4344 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4345 if (is_offload(sc) || is_ethoffload(sc)) { 4346 iaq->nofldtxq = t4_nofldtxq; 4347 iaq->nofldtxq_vi = t4_nofldtxq_vi; 4348 } 4349 #endif 4350 #ifdef TCP_OFFLOAD 4351 if (is_offload(sc)) { 4352 iaq->nofldrxq = t4_nofldrxq; 4353 iaq->nofldrxq_vi = t4_nofldrxq_vi; 4354 } 4355 #endif 4356 #ifdef DEV_NETMAP 4357 if (t4_native_netmap & NN_MAIN_VI) { 4358 iaq->nnmtxq = t4_nnmtxq; 4359 iaq->nnmrxq = t4_nnmrxq; 4360 } 4361 if (t4_native_netmap & NN_EXTRA_VI) { 4362 iaq->nnmtxq_vi = t4_nnmtxq_vi; 4363 iaq->nnmrxq_vi = t4_nnmrxq_vi; 4364 } 4365 #endif 4366 4367 update_nirq(iaq, nports); 4368 if (iaq->nirq <= navail && 4369 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4370 /* 4371 * This is the normal case -- there are enough interrupts for 4372 * everything. 4373 */ 4374 goto done; 4375 } 4376 4377 /* 4378 * If extra VIs have been configured try reducing their count and see if 4379 * that works. 4380 */ 4381 while (iaq->num_vis > 1) { 4382 iaq->num_vis--; 4383 update_nirq(iaq, nports); 4384 if (iaq->nirq <= navail && 4385 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4386 device_printf(sc->dev, "virtual interfaces per port " 4387 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 4388 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 4389 "itype %d, navail %u, nirq %d.\n", 4390 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 4391 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 4392 itype, navail, iaq->nirq); 4393 goto done; 4394 } 4395 } 4396 4397 /* 4398 * Extra VIs will not be created. Log a message if they were requested. 4399 */ 4400 MPASS(iaq->num_vis == 1); 4401 iaq->ntxq_vi = iaq->nrxq_vi = 0; 4402 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 4403 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 4404 if (iaq->num_vis != t4_num_vis) { 4405 device_printf(sc->dev, "extra virtual interfaces disabled. " 4406 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 4407 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 4408 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 4409 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 4410 } 4411 4412 /* 4413 * Keep reducing the number of NIC rx queues to the next lower power of 4414 * 2 (for even RSS distribution) and halving the TOE rx queues and see 4415 * if that works. 4416 */ 4417 do { 4418 if (iaq->nrxq > 1) { 4419 iaq->nrxq = rounddown_pow_of_two(iaq->nrxq - 1); 4420 if (iaq->nnmrxq > iaq->nrxq) 4421 iaq->nnmrxq = iaq->nrxq; 4422 } 4423 if (iaq->nofldrxq > 1) 4424 iaq->nofldrxq >>= 1; 4425 4426 old_nirq = iaq->nirq; 4427 update_nirq(iaq, nports); 4428 if (iaq->nirq <= navail && 4429 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4430 device_printf(sc->dev, "running with reduced number of " 4431 "rx queues because of shortage of interrupts. " 4432 "nrxq=%u, nofldrxq=%u. " 4433 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 4434 iaq->nofldrxq, itype, navail, iaq->nirq); 4435 goto done; 4436 } 4437 } while (old_nirq != iaq->nirq); 4438 4439 /* One interrupt for everything. Ugh. */ 4440 device_printf(sc->dev, "running with minimal number of queues. " 4441 "itype %d, navail %u.\n", itype, navail); 4442 iaq->nirq = 1; 4443 iaq->nrxq = 1; 4444 iaq->ntxq = 1; 4445 if (iaq->nofldrxq > 0) { 4446 iaq->nofldrxq = 1; 4447 iaq->nofldtxq = 1; 4448 } 4449 iaq->nnmtxq = 0; 4450 iaq->nnmrxq = 0; 4451 done: 4452 MPASS(iaq->num_vis > 0); 4453 if (iaq->num_vis > 1) { 4454 MPASS(iaq->nrxq_vi > 0); 4455 MPASS(iaq->ntxq_vi > 0); 4456 } 4457 MPASS(iaq->nirq > 0); 4458 MPASS(iaq->nrxq > 0); 4459 MPASS(iaq->ntxq > 0); 4460 if (itype == INTR_MSI) { 4461 MPASS(powerof2(iaq->nirq)); 4462 } 4463 } 4464 4465 static int 4466 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 4467 { 4468 int rc, itype, navail, nalloc; 4469 4470 for (itype = INTR_MSIX; itype; itype >>= 1) { 4471 4472 if ((itype & t4_intr_types) == 0) 4473 continue; /* not allowed */ 4474 4475 if (itype == INTR_MSIX) 4476 navail = pci_msix_count(sc->dev); 4477 else if (itype == INTR_MSI) 4478 navail = pci_msi_count(sc->dev); 4479 else 4480 navail = 1; 4481 restart: 4482 if (navail == 0) 4483 continue; 4484 4485 calculate_iaq(sc, iaq, itype, navail); 4486 nalloc = iaq->nirq; 4487 rc = 0; 4488 if (itype == INTR_MSIX) 4489 rc = pci_alloc_msix(sc->dev, &nalloc); 4490 else if (itype == INTR_MSI) 4491 rc = pci_alloc_msi(sc->dev, &nalloc); 4492 4493 if (rc == 0 && nalloc > 0) { 4494 if (nalloc == iaq->nirq) 4495 return (0); 4496 4497 /* 4498 * Didn't get the number requested. Use whatever number 4499 * the kernel is willing to allocate. 4500 */ 4501 device_printf(sc->dev, "fewer vectors than requested, " 4502 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 4503 itype, iaq->nirq, nalloc); 4504 pci_release_msi(sc->dev); 4505 navail = nalloc; 4506 goto restart; 4507 } 4508 4509 device_printf(sc->dev, 4510 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 4511 itype, rc, iaq->nirq, nalloc); 4512 } 4513 4514 device_printf(sc->dev, 4515 "failed to find a usable interrupt type. " 4516 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 4517 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 4518 4519 return (ENXIO); 4520 } 4521 4522 #define FW_VERSION(chip) ( \ 4523 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 4524 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 4525 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 4526 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 4527 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 4528 4529 /* Just enough of fw_hdr to cover all version info. */ 4530 struct fw_h { 4531 __u8 ver; 4532 __u8 chip; 4533 __be16 len512; 4534 __be32 fw_ver; 4535 __be32 tp_microcode_ver; 4536 __u8 intfver_nic; 4537 __u8 intfver_vnic; 4538 __u8 intfver_ofld; 4539 __u8 intfver_ri; 4540 __u8 intfver_iscsipdu; 4541 __u8 intfver_iscsi; 4542 __u8 intfver_fcoepdu; 4543 __u8 intfver_fcoe; 4544 }; 4545 /* Spot check a couple of fields. */ 4546 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 4547 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 4548 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 4549 4550 struct fw_info { 4551 uint8_t chip; 4552 char *kld_name; 4553 char *fw_mod_name; 4554 struct fw_h fw_h; 4555 } fw_info[] = { 4556 { 4557 .chip = CHELSIO_T4, 4558 .kld_name = "t4fw_cfg", 4559 .fw_mod_name = "t4fw", 4560 .fw_h = { 4561 .chip = FW_HDR_CHIP_T4, 4562 .fw_ver = htobe32(FW_VERSION(T4)), 4563 .intfver_nic = FW_INTFVER(T4, NIC), 4564 .intfver_vnic = FW_INTFVER(T4, VNIC), 4565 .intfver_ofld = FW_INTFVER(T4, OFLD), 4566 .intfver_ri = FW_INTFVER(T4, RI), 4567 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 4568 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4569 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 4570 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4571 }, 4572 }, { 4573 .chip = CHELSIO_T5, 4574 .kld_name = "t5fw_cfg", 4575 .fw_mod_name = "t5fw", 4576 .fw_h = { 4577 .chip = FW_HDR_CHIP_T5, 4578 .fw_ver = htobe32(FW_VERSION(T5)), 4579 .intfver_nic = FW_INTFVER(T5, NIC), 4580 .intfver_vnic = FW_INTFVER(T5, VNIC), 4581 .intfver_ofld = FW_INTFVER(T5, OFLD), 4582 .intfver_ri = FW_INTFVER(T5, RI), 4583 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 4584 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4585 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 4586 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4587 }, 4588 }, { 4589 .chip = CHELSIO_T6, 4590 .kld_name = "t6fw_cfg", 4591 .fw_mod_name = "t6fw", 4592 .fw_h = { 4593 .chip = FW_HDR_CHIP_T6, 4594 .fw_ver = htobe32(FW_VERSION(T6)), 4595 .intfver_nic = FW_INTFVER(T6, NIC), 4596 .intfver_vnic = FW_INTFVER(T6, VNIC), 4597 .intfver_ofld = FW_INTFVER(T6, OFLD), 4598 .intfver_ri = FW_INTFVER(T6, RI), 4599 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4600 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4601 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4602 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4603 }, 4604 } 4605 }; 4606 4607 static struct fw_info * 4608 find_fw_info(int chip) 4609 { 4610 int i; 4611 4612 for (i = 0; i < nitems(fw_info); i++) { 4613 if (fw_info[i].chip == chip) 4614 return (&fw_info[i]); 4615 } 4616 return (NULL); 4617 } 4618 4619 /* 4620 * Is the given firmware API compatible with the one the driver was compiled 4621 * with? 4622 */ 4623 static int 4624 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 4625 { 4626 4627 /* short circuit if it's the exact same firmware version */ 4628 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 4629 return (1); 4630 4631 /* 4632 * XXX: Is this too conservative? Perhaps I should limit this to the 4633 * features that are supported in the driver. 4634 */ 4635 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 4636 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 4637 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 4638 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 4639 return (1); 4640 #undef SAME_INTF 4641 4642 return (0); 4643 } 4644 4645 static int 4646 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 4647 const struct firmware **fw) 4648 { 4649 struct fw_info *fw_info; 4650 4651 *dcfg = NULL; 4652 if (fw != NULL) 4653 *fw = NULL; 4654 4655 fw_info = find_fw_info(chip_id(sc)); 4656 if (fw_info == NULL) { 4657 device_printf(sc->dev, 4658 "unable to look up firmware information for chip %d.\n", 4659 chip_id(sc)); 4660 return (EINVAL); 4661 } 4662 4663 *dcfg = firmware_get(fw_info->kld_name); 4664 if (*dcfg != NULL) { 4665 if (fw != NULL) 4666 *fw = firmware_get(fw_info->fw_mod_name); 4667 return (0); 4668 } 4669 4670 return (ENOENT); 4671 } 4672 4673 static void 4674 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 4675 const struct firmware *fw) 4676 { 4677 4678 if (fw != NULL) 4679 firmware_put(fw, FIRMWARE_UNLOAD); 4680 if (dcfg != NULL) 4681 firmware_put(dcfg, FIRMWARE_UNLOAD); 4682 } 4683 4684 /* 4685 * Return values: 4686 * 0 means no firmware install attempted. 4687 * ERESTART means a firmware install was attempted and was successful. 4688 * +ve errno means a firmware install was attempted but failed. 4689 */ 4690 static int 4691 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 4692 const struct fw_h *drv_fw, const char *reason, int *already) 4693 { 4694 const struct firmware *cfg, *fw; 4695 const uint32_t c = be32toh(card_fw->fw_ver); 4696 uint32_t d, k; 4697 int rc, fw_install; 4698 struct fw_h bundled_fw; 4699 bool load_attempted; 4700 4701 cfg = fw = NULL; 4702 load_attempted = false; 4703 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 4704 4705 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 4706 if (t4_fw_install < 0) { 4707 rc = load_fw_module(sc, &cfg, &fw); 4708 if (rc != 0 || fw == NULL) { 4709 device_printf(sc->dev, 4710 "failed to load firmware module: %d. cfg %p, fw %p;" 4711 " will use compiled-in firmware version for" 4712 "hw.cxgbe.fw_install checks.\n", 4713 rc, cfg, fw); 4714 } else { 4715 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 4716 } 4717 load_attempted = true; 4718 } 4719 d = be32toh(bundled_fw.fw_ver); 4720 4721 if (reason != NULL) 4722 goto install; 4723 4724 if ((sc->flags & FW_OK) == 0) { 4725 4726 if (c == 0xffffffff) { 4727 reason = "missing"; 4728 goto install; 4729 } 4730 4731 rc = 0; 4732 goto done; 4733 } 4734 4735 if (!fw_compatible(card_fw, &bundled_fw)) { 4736 reason = "incompatible or unusable"; 4737 goto install; 4738 } 4739 4740 if (d > c) { 4741 reason = "older than the version bundled with this driver"; 4742 goto install; 4743 } 4744 4745 if (fw_install == 2 && d != c) { 4746 reason = "different than the version bundled with this driver"; 4747 goto install; 4748 } 4749 4750 /* No reason to do anything to the firmware already on the card. */ 4751 rc = 0; 4752 goto done; 4753 4754 install: 4755 rc = 0; 4756 if ((*already)++) 4757 goto done; 4758 4759 if (fw_install == 0) { 4760 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4761 "but the driver is prohibited from installing a firmware " 4762 "on the card.\n", 4763 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4764 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4765 4766 goto done; 4767 } 4768 4769 /* 4770 * We'll attempt to install a firmware. Load the module first (if it 4771 * hasn't been loaded already). 4772 */ 4773 if (!load_attempted) { 4774 rc = load_fw_module(sc, &cfg, &fw); 4775 if (rc != 0 || fw == NULL) { 4776 device_printf(sc->dev, 4777 "failed to load firmware module: %d. cfg %p, fw %p\n", 4778 rc, cfg, fw); 4779 /* carry on */ 4780 } 4781 } 4782 if (fw == NULL) { 4783 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4784 "but the driver cannot take corrective action because it " 4785 "is unable to load the firmware module.\n", 4786 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4787 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4788 rc = sc->flags & FW_OK ? 0 : ENOENT; 4789 goto done; 4790 } 4791 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 4792 if (k != d) { 4793 MPASS(t4_fw_install > 0); 4794 device_printf(sc->dev, 4795 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 4796 "expecting (%u.%u.%u.%u) and will not be used.\n", 4797 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 4798 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 4799 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4800 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4801 rc = sc->flags & FW_OK ? 0 : EINVAL; 4802 goto done; 4803 } 4804 4805 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4806 "installing firmware %u.%u.%u.%u on card.\n", 4807 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4808 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 4809 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4810 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4811 4812 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 4813 if (rc != 0) { 4814 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 4815 } else { 4816 /* Installed successfully, update the cached header too. */ 4817 rc = ERESTART; 4818 memcpy(card_fw, fw->data, sizeof(*card_fw)); 4819 } 4820 done: 4821 unload_fw_module(sc, cfg, fw); 4822 4823 return (rc); 4824 } 4825 4826 /* 4827 * Establish contact with the firmware and attempt to become the master driver. 4828 * 4829 * A firmware will be installed to the card if needed (if the driver is allowed 4830 * to do so). 4831 */ 4832 static int 4833 contact_firmware(struct adapter *sc) 4834 { 4835 int rc, already = 0; 4836 enum dev_state state; 4837 struct fw_info *fw_info; 4838 struct fw_hdr *card_fw; /* fw on the card */ 4839 const struct fw_h *drv_fw; 4840 4841 fw_info = find_fw_info(chip_id(sc)); 4842 if (fw_info == NULL) { 4843 device_printf(sc->dev, 4844 "unable to look up firmware information for chip %d.\n", 4845 chip_id(sc)); 4846 return (EINVAL); 4847 } 4848 drv_fw = &fw_info->fw_h; 4849 4850 /* Read the header of the firmware on the card */ 4851 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 4852 restart: 4853 rc = -t4_get_fw_hdr(sc, card_fw); 4854 if (rc != 0) { 4855 device_printf(sc->dev, 4856 "unable to read firmware header from card's flash: %d\n", 4857 rc); 4858 goto done; 4859 } 4860 4861 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 4862 &already); 4863 if (rc == ERESTART) 4864 goto restart; 4865 if (rc != 0) 4866 goto done; 4867 4868 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 4869 if (rc < 0 || state == DEV_STATE_ERR) { 4870 rc = -rc; 4871 device_printf(sc->dev, 4872 "failed to connect to the firmware: %d, %d. " 4873 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4874 #if 0 4875 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4876 "not responding properly to HELLO", &already) == ERESTART) 4877 goto restart; 4878 #endif 4879 goto done; 4880 } 4881 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 4882 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 4883 4884 if (rc == sc->pf) { 4885 sc->flags |= MASTER_PF; 4886 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4887 NULL, &already); 4888 if (rc == ERESTART) 4889 rc = 0; 4890 else if (rc != 0) 4891 goto done; 4892 } else if (state == DEV_STATE_UNINIT) { 4893 /* 4894 * We didn't get to be the master so we definitely won't be 4895 * configuring the chip. It's a bug if someone else hasn't 4896 * configured it already. 4897 */ 4898 device_printf(sc->dev, "couldn't be master(%d), " 4899 "device not already initialized either(%d). " 4900 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4901 rc = EPROTO; 4902 goto done; 4903 } else { 4904 /* 4905 * Some other PF is the master and has configured the chip. 4906 * This is allowed but untested. 4907 */ 4908 device_printf(sc->dev, "PF%d is master, device state %d. " 4909 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4910 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 4911 sc->cfcsum = 0; 4912 rc = 0; 4913 } 4914 done: 4915 if (rc != 0 && sc->flags & FW_OK) { 4916 t4_fw_bye(sc, sc->mbox); 4917 sc->flags &= ~FW_OK; 4918 } 4919 free(card_fw, M_CXGBE); 4920 return (rc); 4921 } 4922 4923 static int 4924 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 4925 uint32_t mtype, uint32_t moff) 4926 { 4927 struct fw_info *fw_info; 4928 const struct firmware *dcfg, *rcfg = NULL; 4929 const uint32_t *cfdata; 4930 uint32_t cflen, addr; 4931 int rc; 4932 4933 load_fw_module(sc, &dcfg, NULL); 4934 4935 /* Card specific interpretation of "default". */ 4936 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4937 if (pci_get_device(sc->dev) == 0x440a) 4938 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 4939 if (is_fpga(sc)) 4940 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 4941 } 4942 4943 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4944 if (dcfg == NULL) { 4945 device_printf(sc->dev, 4946 "KLD with default config is not available.\n"); 4947 rc = ENOENT; 4948 goto done; 4949 } 4950 cfdata = dcfg->data; 4951 cflen = dcfg->datasize & ~3; 4952 } else { 4953 char s[32]; 4954 4955 fw_info = find_fw_info(chip_id(sc)); 4956 if (fw_info == NULL) { 4957 device_printf(sc->dev, 4958 "unable to look up firmware information for chip %d.\n", 4959 chip_id(sc)); 4960 rc = EINVAL; 4961 goto done; 4962 } 4963 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 4964 4965 rcfg = firmware_get(s); 4966 if (rcfg == NULL) { 4967 device_printf(sc->dev, 4968 "unable to load module \"%s\" for configuration " 4969 "profile \"%s\".\n", s, cfg_file); 4970 rc = ENOENT; 4971 goto done; 4972 } 4973 cfdata = rcfg->data; 4974 cflen = rcfg->datasize & ~3; 4975 } 4976 4977 if (cflen > FLASH_CFG_MAX_SIZE) { 4978 device_printf(sc->dev, 4979 "config file too long (%d, max allowed is %d).\n", 4980 cflen, FLASH_CFG_MAX_SIZE); 4981 rc = EINVAL; 4982 goto done; 4983 } 4984 4985 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 4986 if (rc != 0) { 4987 device_printf(sc->dev, 4988 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 4989 __func__, mtype, moff, cflen, rc); 4990 rc = EINVAL; 4991 goto done; 4992 } 4993 write_via_memwin(sc, 2, addr, cfdata, cflen); 4994 done: 4995 if (rcfg != NULL) 4996 firmware_put(rcfg, FIRMWARE_UNLOAD); 4997 unload_fw_module(sc, dcfg, NULL); 4998 return (rc); 4999 } 5000 5001 struct caps_allowed { 5002 uint16_t nbmcaps; 5003 uint16_t linkcaps; 5004 uint16_t switchcaps; 5005 uint16_t niccaps; 5006 uint16_t toecaps; 5007 uint16_t rdmacaps; 5008 uint16_t cryptocaps; 5009 uint16_t iscsicaps; 5010 uint16_t fcoecaps; 5011 }; 5012 5013 #define FW_PARAM_DEV(param) \ 5014 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 5015 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 5016 #define FW_PARAM_PFVF(param) \ 5017 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 5018 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 5019 5020 /* 5021 * Provide a configuration profile to the firmware and have it initialize the 5022 * chip accordingly. This may involve uploading a configuration file to the 5023 * card. 5024 */ 5025 static int 5026 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 5027 const struct caps_allowed *caps_allowed) 5028 { 5029 int rc; 5030 struct fw_caps_config_cmd caps; 5031 uint32_t mtype, moff, finicsum, cfcsum, param, val; 5032 5033 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 5034 if (rc != 0) { 5035 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 5036 return (rc); 5037 } 5038 5039 bzero(&caps, sizeof(caps)); 5040 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5041 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5042 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 5043 mtype = 0; 5044 moff = 0; 5045 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5046 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 5047 mtype = FW_MEMTYPE_FLASH; 5048 moff = t4_flash_cfg_addr(sc); 5049 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 5050 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 5051 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 5052 FW_LEN16(caps)); 5053 } else { 5054 /* 5055 * Ask the firmware where it wants us to upload the config file. 5056 */ 5057 param = FW_PARAM_DEV(CF); 5058 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5059 if (rc != 0) { 5060 /* No support for config file? Shouldn't happen. */ 5061 device_printf(sc->dev, 5062 "failed to query config file location: %d.\n", rc); 5063 goto done; 5064 } 5065 mtype = G_FW_PARAMS_PARAM_Y(val); 5066 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 5067 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 5068 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 5069 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 5070 FW_LEN16(caps)); 5071 5072 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 5073 if (rc != 0) { 5074 device_printf(sc->dev, 5075 "failed to upload config file to card: %d.\n", rc); 5076 goto done; 5077 } 5078 } 5079 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5080 if (rc != 0) { 5081 device_printf(sc->dev, "failed to pre-process config file: %d " 5082 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 5083 goto done; 5084 } 5085 5086 finicsum = be32toh(caps.finicsum); 5087 cfcsum = be32toh(caps.cfcsum); /* actual */ 5088 if (finicsum != cfcsum) { 5089 device_printf(sc->dev, 5090 "WARNING: config file checksum mismatch: %08x %08x\n", 5091 finicsum, cfcsum); 5092 } 5093 sc->cfcsum = cfcsum; 5094 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 5095 5096 /* 5097 * Let the firmware know what features will (not) be used so it can tune 5098 * things accordingly. 5099 */ 5100 #define LIMIT_CAPS(x) do { \ 5101 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 5102 } while (0) 5103 LIMIT_CAPS(nbm); 5104 LIMIT_CAPS(link); 5105 LIMIT_CAPS(switch); 5106 LIMIT_CAPS(nic); 5107 LIMIT_CAPS(toe); 5108 LIMIT_CAPS(rdma); 5109 LIMIT_CAPS(crypto); 5110 LIMIT_CAPS(iscsi); 5111 LIMIT_CAPS(fcoe); 5112 #undef LIMIT_CAPS 5113 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 5114 /* 5115 * TOE and hashfilters are mutually exclusive. It is a config 5116 * file or firmware bug if both are reported as available. Try 5117 * to cope with the situation in non-debug builds by disabling 5118 * TOE. 5119 */ 5120 MPASS(caps.toecaps == 0); 5121 5122 caps.toecaps = 0; 5123 caps.rdmacaps = 0; 5124 caps.iscsicaps = 0; 5125 } 5126 5127 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5128 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5129 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5130 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 5131 if (rc != 0) { 5132 device_printf(sc->dev, 5133 "failed to process config file: %d.\n", rc); 5134 goto done; 5135 } 5136 5137 t4_tweak_chip_settings(sc); 5138 set_params__pre_init(sc); 5139 5140 /* get basic stuff going */ 5141 rc = -t4_fw_initialize(sc, sc->mbox); 5142 if (rc != 0) { 5143 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 5144 goto done; 5145 } 5146 done: 5147 return (rc); 5148 } 5149 5150 /* 5151 * Partition chip resources for use between various PFs, VFs, etc. 5152 */ 5153 static int 5154 partition_resources(struct adapter *sc) 5155 { 5156 char cfg_file[sizeof(t4_cfg_file)]; 5157 struct caps_allowed caps_allowed; 5158 int rc; 5159 bool fallback; 5160 5161 /* Only the master driver gets to configure the chip resources. */ 5162 MPASS(sc->flags & MASTER_PF); 5163 5164 #define COPY_CAPS(x) do { \ 5165 caps_allowed.x##caps = t4_##x##caps_allowed; \ 5166 } while (0) 5167 bzero(&caps_allowed, sizeof(caps_allowed)); 5168 COPY_CAPS(nbm); 5169 COPY_CAPS(link); 5170 COPY_CAPS(switch); 5171 COPY_CAPS(nic); 5172 COPY_CAPS(toe); 5173 COPY_CAPS(rdma); 5174 COPY_CAPS(crypto); 5175 COPY_CAPS(iscsi); 5176 COPY_CAPS(fcoe); 5177 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 5178 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 5179 retry: 5180 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 5181 if (rc != 0 && fallback) { 5182 dump_devlog(sc); 5183 device_printf(sc->dev, 5184 "failed (%d) to configure card with \"%s\" profile, " 5185 "will fall back to a basic configuration and retry.\n", 5186 rc, cfg_file); 5187 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 5188 bzero(&caps_allowed, sizeof(caps_allowed)); 5189 COPY_CAPS(switch); 5190 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 5191 fallback = false; 5192 goto retry; 5193 } 5194 #undef COPY_CAPS 5195 return (rc); 5196 } 5197 5198 /* 5199 * Retrieve parameters that are needed (or nice to have) very early. 5200 */ 5201 static int 5202 get_params__pre_init(struct adapter *sc) 5203 { 5204 int rc; 5205 uint32_t param[2], val[2]; 5206 5207 t4_get_version_info(sc); 5208 5209 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 5210 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 5211 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 5212 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 5213 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 5214 5215 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 5216 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 5217 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 5218 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 5219 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 5220 5221 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 5222 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 5223 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 5224 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 5225 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 5226 5227 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 5228 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 5229 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 5230 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 5231 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 5232 5233 param[0] = FW_PARAM_DEV(PORTVEC); 5234 param[1] = FW_PARAM_DEV(CCLK); 5235 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5236 if (rc != 0) { 5237 device_printf(sc->dev, 5238 "failed to query parameters (pre_init): %d.\n", rc); 5239 return (rc); 5240 } 5241 5242 sc->params.portvec = val[0]; 5243 sc->params.nports = bitcount32(val[0]); 5244 sc->params.vpd.cclk = val[1]; 5245 5246 /* Read device log parameters. */ 5247 rc = -t4_init_devlog_params(sc, 1); 5248 if (rc == 0) 5249 fixup_devlog_params(sc); 5250 else { 5251 device_printf(sc->dev, 5252 "failed to get devlog parameters: %d.\n", rc); 5253 rc = 0; /* devlog isn't critical for device operation */ 5254 } 5255 5256 return (rc); 5257 } 5258 5259 /* 5260 * Any params that need to be set before FW_INITIALIZE. 5261 */ 5262 static int 5263 set_params__pre_init(struct adapter *sc) 5264 { 5265 int rc = 0; 5266 uint32_t param, val; 5267 5268 if (chip_id(sc) >= CHELSIO_T6) { 5269 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 5270 val = 1; 5271 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5272 /* firmwares < 1.20.1.0 do not have this param. */ 5273 if (rc == FW_EINVAL && 5274 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) { 5275 rc = 0; 5276 } 5277 if (rc != 0) { 5278 device_printf(sc->dev, 5279 "failed to enable high priority filters :%d.\n", 5280 rc); 5281 } 5282 5283 param = FW_PARAM_DEV(PPOD_EDRAM); 5284 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5285 if (rc == 0 && val == 1) { 5286 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, 5287 &val); 5288 if (rc != 0) { 5289 device_printf(sc->dev, 5290 "failed to set PPOD_EDRAM: %d.\n", rc); 5291 } 5292 } 5293 } 5294 5295 /* Enable opaque VIIDs with firmwares that support it. */ 5296 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 5297 val = 1; 5298 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5299 if (rc == 0 && val == 1) 5300 sc->params.viid_smt_extn_support = true; 5301 else 5302 sc->params.viid_smt_extn_support = false; 5303 5304 return (rc); 5305 } 5306 5307 /* 5308 * Retrieve various parameters that are of interest to the driver. The device 5309 * has been initialized by the firmware at this point. 5310 */ 5311 static int 5312 get_params__post_init(struct adapter *sc) 5313 { 5314 int rc; 5315 uint32_t param[7], val[7]; 5316 struct fw_caps_config_cmd caps; 5317 5318 param[0] = FW_PARAM_PFVF(IQFLINT_START); 5319 param[1] = FW_PARAM_PFVF(EQ_START); 5320 param[2] = FW_PARAM_PFVF(FILTER_START); 5321 param[3] = FW_PARAM_PFVF(FILTER_END); 5322 param[4] = FW_PARAM_PFVF(L2T_START); 5323 param[5] = FW_PARAM_PFVF(L2T_END); 5324 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5325 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5326 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 5327 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 5328 if (rc != 0) { 5329 device_printf(sc->dev, 5330 "failed to query parameters (post_init): %d.\n", rc); 5331 return (rc); 5332 } 5333 5334 sc->sge.iq_start = val[0]; 5335 sc->sge.eq_start = val[1]; 5336 if ((int)val[3] > (int)val[2]) { 5337 sc->tids.ftid_base = val[2]; 5338 sc->tids.ftid_end = val[3]; 5339 sc->tids.nftids = val[3] - val[2] + 1; 5340 } 5341 sc->vres.l2t.start = val[4]; 5342 sc->vres.l2t.size = val[5] - val[4] + 1; 5343 /* val[5] is the last hwidx and it must not collide with F_SYNC_WR */ 5344 if (sc->vres.l2t.size > 0) 5345 MPASS(fls(val[5]) <= S_SYNC_WR); 5346 sc->params.core_vdd = val[6]; 5347 5348 param[0] = FW_PARAM_PFVF(IQFLINT_END); 5349 param[1] = FW_PARAM_PFVF(EQ_END); 5350 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5351 if (rc != 0) { 5352 device_printf(sc->dev, 5353 "failed to query parameters (post_init2): %d.\n", rc); 5354 return (rc); 5355 } 5356 MPASS((int)val[0] >= sc->sge.iq_start); 5357 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1; 5358 MPASS((int)val[1] >= sc->sge.eq_start); 5359 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1; 5360 5361 if (chip_id(sc) >= CHELSIO_T6) { 5362 5363 sc->tids.tid_base = t4_read_reg(sc, 5364 A_LE_DB_ACTIVE_TABLE_START_INDEX); 5365 5366 param[0] = FW_PARAM_PFVF(HPFILTER_START); 5367 param[1] = FW_PARAM_PFVF(HPFILTER_END); 5368 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5369 if (rc != 0) { 5370 device_printf(sc->dev, 5371 "failed to query hpfilter parameters: %d.\n", rc); 5372 return (rc); 5373 } 5374 if ((int)val[1] > (int)val[0]) { 5375 sc->tids.hpftid_base = val[0]; 5376 sc->tids.hpftid_end = val[1]; 5377 sc->tids.nhpftids = val[1] - val[0] + 1; 5378 5379 /* 5380 * These should go off if the layout changes and the 5381 * driver needs to catch up. 5382 */ 5383 MPASS(sc->tids.hpftid_base == 0); 5384 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 5385 } 5386 5387 param[0] = FW_PARAM_PFVF(RAWF_START); 5388 param[1] = FW_PARAM_PFVF(RAWF_END); 5389 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5390 if (rc != 0) { 5391 device_printf(sc->dev, 5392 "failed to query rawf parameters: %d.\n", rc); 5393 return (rc); 5394 } 5395 if ((int)val[1] > (int)val[0]) { 5396 sc->rawf_base = val[0]; 5397 sc->nrawf = val[1] - val[0] + 1; 5398 } 5399 } 5400 5401 /* 5402 * The parameters that follow may not be available on all firmwares. We 5403 * query them individually rather than in a compound query because old 5404 * firmwares fail the entire query if an unknown parameter is queried. 5405 */ 5406 5407 /* 5408 * MPS buffer group configuration. 5409 */ 5410 param[0] = FW_PARAM_DEV(MPSBGMAP); 5411 val[0] = 0; 5412 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5413 if (rc == 0) 5414 sc->params.mps_bg_map = val[0]; 5415 else 5416 sc->params.mps_bg_map = UINT32_MAX; /* Not a legal value. */ 5417 5418 param[0] = FW_PARAM_DEV(TPCHMAP); 5419 val[0] = 0; 5420 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5421 if (rc == 0) 5422 sc->params.tp_ch_map = val[0]; 5423 else 5424 sc->params.tp_ch_map = UINT32_MAX; /* Not a legal value. */ 5425 5426 /* 5427 * Determine whether the firmware supports the filter2 work request. 5428 */ 5429 param[0] = FW_PARAM_DEV(FILTER2_WR); 5430 val[0] = 0; 5431 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5432 if (rc == 0) 5433 sc->params.filter2_wr_support = val[0] != 0; 5434 else 5435 sc->params.filter2_wr_support = 0; 5436 5437 /* 5438 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 5439 */ 5440 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 5441 val[0] = 0; 5442 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5443 if (rc == 0) 5444 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 5445 else 5446 sc->params.ulptx_memwrite_dsgl = false; 5447 5448 /* FW_RI_FR_NSMR_TPTE_WR support */ 5449 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 5450 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5451 if (rc == 0) 5452 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0; 5453 else 5454 sc->params.fr_nsmr_tpte_wr_support = false; 5455 5456 /* Support for 512 SGL entries per FR MR. */ 5457 param[0] = FW_PARAM_DEV(DEV_512SGL_MR); 5458 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5459 if (rc == 0) 5460 sc->params.dev_512sgl_mr = val[0] != 0; 5461 else 5462 sc->params.dev_512sgl_mr = false; 5463 5464 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 5465 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5466 if (rc == 0) 5467 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0]; 5468 else 5469 sc->params.max_pkts_per_eth_tx_pkts_wr = 15; 5470 5471 param[0] = FW_PARAM_DEV(NUM_TM_CLASS); 5472 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5473 if (rc == 0) { 5474 MPASS(val[0] > 0 && val[0] < 256); /* nsched_cls is 8b */ 5475 sc->params.nsched_cls = val[0]; 5476 } else 5477 sc->params.nsched_cls = sc->chip_params->nsched_cls; 5478 5479 /* get capabilites */ 5480 bzero(&caps, sizeof(caps)); 5481 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5482 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5483 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5484 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5485 if (rc != 0) { 5486 device_printf(sc->dev, 5487 "failed to get card capabilities: %d.\n", rc); 5488 return (rc); 5489 } 5490 5491 #define READ_CAPS(x) do { \ 5492 sc->x = htobe16(caps.x); \ 5493 } while (0) 5494 READ_CAPS(nbmcaps); 5495 READ_CAPS(linkcaps); 5496 READ_CAPS(switchcaps); 5497 READ_CAPS(niccaps); 5498 READ_CAPS(toecaps); 5499 READ_CAPS(rdmacaps); 5500 READ_CAPS(cryptocaps); 5501 READ_CAPS(iscsicaps); 5502 READ_CAPS(fcoecaps); 5503 5504 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 5505 MPASS(chip_id(sc) > CHELSIO_T4); 5506 MPASS(sc->toecaps == 0); 5507 sc->toecaps = 0; 5508 5509 param[0] = FW_PARAM_DEV(NTID); 5510 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5511 if (rc != 0) { 5512 device_printf(sc->dev, 5513 "failed to query HASHFILTER parameters: %d.\n", rc); 5514 return (rc); 5515 } 5516 sc->tids.ntids = val[0]; 5517 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5518 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5519 sc->tids.ntids -= sc->tids.nhpftids; 5520 } 5521 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5522 sc->params.hash_filter = 1; 5523 } 5524 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 5525 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 5526 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 5527 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5528 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 5529 if (rc != 0) { 5530 device_printf(sc->dev, 5531 "failed to query NIC parameters: %d.\n", rc); 5532 return (rc); 5533 } 5534 if ((int)val[1] > (int)val[0]) { 5535 sc->tids.etid_base = val[0]; 5536 sc->tids.etid_end = val[1]; 5537 sc->tids.netids = val[1] - val[0] + 1; 5538 sc->params.eo_wr_cred = val[2]; 5539 sc->params.ethoffload = 1; 5540 } 5541 } 5542 if (sc->toecaps) { 5543 /* query offload-related parameters */ 5544 param[0] = FW_PARAM_DEV(NTID); 5545 param[1] = FW_PARAM_PFVF(SERVER_START); 5546 param[2] = FW_PARAM_PFVF(SERVER_END); 5547 param[3] = FW_PARAM_PFVF(TDDP_START); 5548 param[4] = FW_PARAM_PFVF(TDDP_END); 5549 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5550 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5551 if (rc != 0) { 5552 device_printf(sc->dev, 5553 "failed to query TOE parameters: %d.\n", rc); 5554 return (rc); 5555 } 5556 sc->tids.ntids = val[0]; 5557 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5558 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5559 sc->tids.ntids -= sc->tids.nhpftids; 5560 } 5561 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5562 if ((int)val[2] > (int)val[1]) { 5563 sc->tids.stid_base = val[1]; 5564 sc->tids.nstids = val[2] - val[1] + 1; 5565 } 5566 sc->vres.ddp.start = val[3]; 5567 sc->vres.ddp.size = val[4] - val[3] + 1; 5568 sc->params.ofldq_wr_cred = val[5]; 5569 sc->params.offload = 1; 5570 } else { 5571 /* 5572 * The firmware attempts memfree TOE configuration for -SO cards 5573 * and will report toecaps=0 if it runs out of resources (this 5574 * depends on the config file). It may not report 0 for other 5575 * capabilities dependent on the TOE in this case. Set them to 5576 * 0 here so that the driver doesn't bother tracking resources 5577 * that will never be used. 5578 */ 5579 sc->iscsicaps = 0; 5580 sc->rdmacaps = 0; 5581 } 5582 if (sc->rdmacaps) { 5583 param[0] = FW_PARAM_PFVF(STAG_START); 5584 param[1] = FW_PARAM_PFVF(STAG_END); 5585 param[2] = FW_PARAM_PFVF(RQ_START); 5586 param[3] = FW_PARAM_PFVF(RQ_END); 5587 param[4] = FW_PARAM_PFVF(PBL_START); 5588 param[5] = FW_PARAM_PFVF(PBL_END); 5589 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5590 if (rc != 0) { 5591 device_printf(sc->dev, 5592 "failed to query RDMA parameters(1): %d.\n", rc); 5593 return (rc); 5594 } 5595 sc->vres.stag.start = val[0]; 5596 sc->vres.stag.size = val[1] - val[0] + 1; 5597 sc->vres.rq.start = val[2]; 5598 sc->vres.rq.size = val[3] - val[2] + 1; 5599 sc->vres.pbl.start = val[4]; 5600 sc->vres.pbl.size = val[5] - val[4] + 1; 5601 5602 param[0] = FW_PARAM_PFVF(SQRQ_START); 5603 param[1] = FW_PARAM_PFVF(SQRQ_END); 5604 param[2] = FW_PARAM_PFVF(CQ_START); 5605 param[3] = FW_PARAM_PFVF(CQ_END); 5606 param[4] = FW_PARAM_PFVF(OCQ_START); 5607 param[5] = FW_PARAM_PFVF(OCQ_END); 5608 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5609 if (rc != 0) { 5610 device_printf(sc->dev, 5611 "failed to query RDMA parameters(2): %d.\n", rc); 5612 return (rc); 5613 } 5614 sc->vres.qp.start = val[0]; 5615 sc->vres.qp.size = val[1] - val[0] + 1; 5616 sc->vres.cq.start = val[2]; 5617 sc->vres.cq.size = val[3] - val[2] + 1; 5618 sc->vres.ocq.start = val[4]; 5619 sc->vres.ocq.size = val[5] - val[4] + 1; 5620 5621 param[0] = FW_PARAM_PFVF(SRQ_START); 5622 param[1] = FW_PARAM_PFVF(SRQ_END); 5623 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 5624 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 5625 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 5626 if (rc != 0) { 5627 device_printf(sc->dev, 5628 "failed to query RDMA parameters(3): %d.\n", rc); 5629 return (rc); 5630 } 5631 sc->vres.srq.start = val[0]; 5632 sc->vres.srq.size = val[1] - val[0] + 1; 5633 sc->params.max_ordird_qp = val[2]; 5634 sc->params.max_ird_adapter = val[3]; 5635 } 5636 if (sc->iscsicaps) { 5637 param[0] = FW_PARAM_PFVF(ISCSI_START); 5638 param[1] = FW_PARAM_PFVF(ISCSI_END); 5639 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5640 if (rc != 0) { 5641 device_printf(sc->dev, 5642 "failed to query iSCSI parameters: %d.\n", rc); 5643 return (rc); 5644 } 5645 sc->vres.iscsi.start = val[0]; 5646 sc->vres.iscsi.size = val[1] - val[0] + 1; 5647 } 5648 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 5649 param[0] = FW_PARAM_PFVF(TLS_START); 5650 param[1] = FW_PARAM_PFVF(TLS_END); 5651 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5652 if (rc != 0) { 5653 device_printf(sc->dev, 5654 "failed to query TLS parameters: %d.\n", rc); 5655 return (rc); 5656 } 5657 sc->vres.key.start = val[0]; 5658 sc->vres.key.size = val[1] - val[0] + 1; 5659 } 5660 5661 /* 5662 * We've got the params we wanted to query directly from the firmware. 5663 * Grab some others via other means. 5664 */ 5665 t4_init_sge_params(sc); 5666 t4_init_tp_params(sc); 5667 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 5668 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 5669 5670 rc = t4_verify_chip_settings(sc); 5671 if (rc != 0) 5672 return (rc); 5673 t4_init_rx_buf_info(sc); 5674 5675 return (rc); 5676 } 5677 5678 #ifdef KERN_TLS 5679 static void 5680 ktls_tick(void *arg) 5681 { 5682 struct adapter *sc; 5683 uint32_t tstamp; 5684 5685 sc = arg; 5686 tstamp = tcp_ts_getticks(); 5687 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1); 5688 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31); 5689 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK); 5690 } 5691 5692 static int 5693 t6_config_kern_tls(struct adapter *sc, bool enable) 5694 { 5695 int rc; 5696 uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5697 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) | 5698 V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) | 5699 V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE); 5700 5701 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, ¶m); 5702 if (rc != 0) { 5703 CH_ERR(sc, "failed to %s NIC TLS: %d\n", 5704 enable ? "enable" : "disable", rc); 5705 return (rc); 5706 } 5707 5708 if (enable) { 5709 sc->flags |= KERN_TLS_ON; 5710 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc, 5711 C_HARDCLOCK); 5712 } else { 5713 sc->flags &= ~KERN_TLS_ON; 5714 callout_stop(&sc->ktls_tick); 5715 } 5716 5717 return (rc); 5718 } 5719 #endif 5720 5721 static int 5722 set_params__post_init(struct adapter *sc) 5723 { 5724 uint32_t mask, param, val; 5725 #ifdef TCP_OFFLOAD 5726 int i, v, shift; 5727 #endif 5728 5729 /* ask for encapsulated CPLs */ 5730 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 5731 val = 1; 5732 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5733 5734 /* Enable 32b port caps if the firmware supports it. */ 5735 param = FW_PARAM_PFVF(PORT_CAPS32); 5736 val = 1; 5737 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 5738 sc->params.port_caps32 = 1; 5739 5740 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 5741 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 5742 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 5743 V_MASKFILTER(val - 1)); 5744 5745 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER | 5746 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN | 5747 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5748 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM; 5749 val = 0; 5750 if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) { 5751 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE, 5752 F_ATTACKFILTERENABLE); 5753 val |= F_DROPERRORATTACK; 5754 } 5755 if (t4_drop_ip_fragments != 0) { 5756 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP, 5757 F_FRAGMENTDROP); 5758 val |= F_DROPERRORFRAG; 5759 } 5760 if (t4_drop_pkts_with_l2_errors != 0) 5761 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN; 5762 if (t4_drop_pkts_with_l3_errors != 0) { 5763 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN | 5764 F_DROPERRORCSUMIP; 5765 } 5766 if (t4_drop_pkts_with_l4_errors != 0) { 5767 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5768 F_DROPERRORTCPOPT | F_DROPERRORCSUM; 5769 } 5770 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val); 5771 5772 #ifdef TCP_OFFLOAD 5773 /* 5774 * Override the TOE timers with user provided tunables. This is not the 5775 * recommended way to change the timers (the firmware config file is) so 5776 * these tunables are not documented. 5777 * 5778 * All the timer tunables are in microseconds. 5779 */ 5780 if (t4_toe_keepalive_idle != 0) { 5781 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 5782 v &= M_KEEPALIVEIDLE; 5783 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 5784 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 5785 } 5786 if (t4_toe_keepalive_interval != 0) { 5787 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 5788 v &= M_KEEPALIVEINTVL; 5789 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 5790 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 5791 } 5792 if (t4_toe_keepalive_count != 0) { 5793 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 5794 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5795 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 5796 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 5797 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 5798 } 5799 if (t4_toe_rexmt_min != 0) { 5800 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 5801 v &= M_RXTMIN; 5802 t4_set_reg_field(sc, A_TP_RXT_MIN, 5803 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 5804 } 5805 if (t4_toe_rexmt_max != 0) { 5806 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 5807 v &= M_RXTMAX; 5808 t4_set_reg_field(sc, A_TP_RXT_MAX, 5809 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 5810 } 5811 if (t4_toe_rexmt_count != 0) { 5812 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 5813 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5814 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 5815 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 5816 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 5817 } 5818 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 5819 if (t4_toe_rexmt_backoff[i] != -1) { 5820 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 5821 shift = (i & 3) << 3; 5822 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 5823 M_TIMERBACKOFFINDEX0 << shift, v << shift); 5824 } 5825 } 5826 #endif 5827 5828 /* 5829 * Limit TOE connections to 2 reassembly "islands". This is 5830 * required to permit migrating TOE connections to either 5831 * ULP_MODE_TCPDDP or UPL_MODE_TLS. 5832 */ 5833 t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, V_PASSMODE(M_PASSMODE), 5834 V_PASSMODE(2)); 5835 5836 #ifdef KERN_TLS 5837 if (is_ktls(sc)) { 5838 sc->tlst.inline_keys = t4_tls_inline_keys; 5839 sc->tlst.combo_wrs = t4_tls_combo_wrs; 5840 if (t4_kern_tls != 0 && is_t6(sc)) 5841 t6_config_kern_tls(sc, true); 5842 } 5843 #endif 5844 return (0); 5845 } 5846 5847 #undef FW_PARAM_PFVF 5848 #undef FW_PARAM_DEV 5849 5850 static void 5851 t4_set_desc(struct adapter *sc) 5852 { 5853 struct adapter_params *p = &sc->params; 5854 5855 device_set_descf(sc->dev, "Chelsio %s", p->vpd.id); 5856 } 5857 5858 static inline void 5859 ifmedia_add4(struct ifmedia *ifm, int m) 5860 { 5861 5862 ifmedia_add(ifm, m, 0, NULL); 5863 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 5864 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 5865 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 5866 } 5867 5868 /* 5869 * This is the selected media, which is not quite the same as the active media. 5870 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 5871 * and active are not the same, and "media: Ethernet selected" otherwise. 5872 */ 5873 static void 5874 set_current_media(struct port_info *pi) 5875 { 5876 struct link_config *lc; 5877 struct ifmedia *ifm; 5878 int mword; 5879 u_int speed; 5880 5881 PORT_LOCK_ASSERT_OWNED(pi); 5882 5883 /* Leave current media alone if it's already set to IFM_NONE. */ 5884 ifm = &pi->media; 5885 if (ifm->ifm_cur != NULL && 5886 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 5887 return; 5888 5889 lc = &pi->link_cfg; 5890 if (lc->requested_aneg != AUTONEG_DISABLE && 5891 lc->pcaps & FW_PORT_CAP32_ANEG) { 5892 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 5893 return; 5894 } 5895 mword = IFM_ETHER | IFM_FDX; 5896 if (lc->requested_fc & PAUSE_TX) 5897 mword |= IFM_ETH_TXPAUSE; 5898 if (lc->requested_fc & PAUSE_RX) 5899 mword |= IFM_ETH_RXPAUSE; 5900 if (lc->requested_speed == 0) 5901 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 5902 else 5903 speed = lc->requested_speed; 5904 mword |= port_mword(pi, speed_to_fwcap(speed)); 5905 ifmedia_set(ifm, mword); 5906 } 5907 5908 /* 5909 * Returns true if the ifmedia list for the port cannot change. 5910 */ 5911 static bool 5912 fixed_ifmedia(struct port_info *pi) 5913 { 5914 5915 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 5916 pi->port_type == FW_PORT_TYPE_BT_XFI || 5917 pi->port_type == FW_PORT_TYPE_BT_XAUI || 5918 pi->port_type == FW_PORT_TYPE_KX4 || 5919 pi->port_type == FW_PORT_TYPE_KX || 5920 pi->port_type == FW_PORT_TYPE_KR || 5921 pi->port_type == FW_PORT_TYPE_BP_AP || 5922 pi->port_type == FW_PORT_TYPE_BP4_AP || 5923 pi->port_type == FW_PORT_TYPE_BP40_BA || 5924 pi->port_type == FW_PORT_TYPE_KR4_100G || 5925 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 5926 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 5927 } 5928 5929 static void 5930 build_medialist(struct port_info *pi) 5931 { 5932 uint32_t ss, speed; 5933 int unknown, mword, bit; 5934 struct link_config *lc; 5935 struct ifmedia *ifm; 5936 5937 PORT_LOCK_ASSERT_OWNED(pi); 5938 5939 if (pi->flags & FIXED_IFMEDIA) 5940 return; 5941 5942 /* 5943 * Rebuild the ifmedia list. 5944 */ 5945 ifm = &pi->media; 5946 ifmedia_removeall(ifm); 5947 lc = &pi->link_cfg; 5948 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */ 5949 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 5950 MPASS(ss != 0); 5951 no_media: 5952 MPASS(LIST_EMPTY(&ifm->ifm_list)); 5953 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 5954 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 5955 return; 5956 } 5957 5958 unknown = 0; 5959 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 5960 speed = 1 << bit; 5961 MPASS(speed & M_FW_PORT_CAP32_SPEED); 5962 if (ss & speed) { 5963 mword = port_mword(pi, speed); 5964 if (mword == IFM_NONE) { 5965 goto no_media; 5966 } else if (mword == IFM_UNKNOWN) 5967 unknown++; 5968 else 5969 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 5970 } 5971 } 5972 if (unknown > 0) /* Add one unknown for all unknown media types. */ 5973 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 5974 if (lc->pcaps & FW_PORT_CAP32_ANEG) 5975 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 5976 5977 set_current_media(pi); 5978 } 5979 5980 /* 5981 * Initialize the requested fields in the link config based on driver tunables. 5982 */ 5983 static void 5984 init_link_config(struct port_info *pi) 5985 { 5986 struct link_config *lc = &pi->link_cfg; 5987 5988 PORT_LOCK_ASSERT_OWNED(pi); 5989 5990 lc->requested_caps = 0; 5991 lc->requested_speed = 0; 5992 5993 if (t4_autoneg == 0) 5994 lc->requested_aneg = AUTONEG_DISABLE; 5995 else if (t4_autoneg == 1) 5996 lc->requested_aneg = AUTONEG_ENABLE; 5997 else 5998 lc->requested_aneg = AUTONEG_AUTO; 5999 6000 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 6001 PAUSE_AUTONEG); 6002 6003 if (t4_fec & FEC_AUTO) 6004 lc->requested_fec = FEC_AUTO; 6005 else if (t4_fec == 0) 6006 lc->requested_fec = FEC_NONE; 6007 else { 6008 /* -1 is handled by the FEC_AUTO block above and not here. */ 6009 lc->requested_fec = t4_fec & 6010 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE); 6011 if (lc->requested_fec == 0) 6012 lc->requested_fec = FEC_AUTO; 6013 } 6014 if (t4_force_fec < 0) 6015 lc->force_fec = -1; 6016 else if (t4_force_fec > 0) 6017 lc->force_fec = 1; 6018 else 6019 lc->force_fec = 0; 6020 } 6021 6022 /* 6023 * Makes sure that all requested settings comply with what's supported by the 6024 * port. Returns the number of settings that were invalid and had to be fixed. 6025 */ 6026 static int 6027 fixup_link_config(struct port_info *pi) 6028 { 6029 int n = 0; 6030 struct link_config *lc = &pi->link_cfg; 6031 uint32_t fwspeed; 6032 6033 PORT_LOCK_ASSERT_OWNED(pi); 6034 6035 /* Speed (when not autonegotiating) */ 6036 if (lc->requested_speed != 0) { 6037 fwspeed = speed_to_fwcap(lc->requested_speed); 6038 if ((fwspeed & lc->pcaps) == 0) { 6039 n++; 6040 lc->requested_speed = 0; 6041 } 6042 } 6043 6044 /* Link autonegotiation */ 6045 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 6046 lc->requested_aneg == AUTONEG_DISABLE || 6047 lc->requested_aneg == AUTONEG_AUTO); 6048 if (lc->requested_aneg == AUTONEG_ENABLE && 6049 !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 6050 n++; 6051 lc->requested_aneg = AUTONEG_AUTO; 6052 } 6053 6054 /* Flow control */ 6055 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 6056 if (lc->requested_fc & PAUSE_TX && 6057 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) { 6058 n++; 6059 lc->requested_fc &= ~PAUSE_TX; 6060 } 6061 if (lc->requested_fc & PAUSE_RX && 6062 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) { 6063 n++; 6064 lc->requested_fc &= ~PAUSE_RX; 6065 } 6066 if (!(lc->requested_fc & PAUSE_AUTONEG) && 6067 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) { 6068 n++; 6069 lc->requested_fc |= PAUSE_AUTONEG; 6070 } 6071 6072 /* FEC */ 6073 if ((lc->requested_fec & FEC_RS && 6074 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) || 6075 (lc->requested_fec & FEC_BASER_RS && 6076 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) { 6077 n++; 6078 lc->requested_fec = FEC_AUTO; 6079 } 6080 6081 return (n); 6082 } 6083 6084 /* 6085 * Apply the requested L1 settings, which are expected to be valid, to the 6086 * hardware. 6087 */ 6088 static int 6089 apply_link_config(struct port_info *pi) 6090 { 6091 struct adapter *sc = pi->adapter; 6092 struct link_config *lc = &pi->link_cfg; 6093 int rc; 6094 6095 #ifdef INVARIANTS 6096 ASSERT_SYNCHRONIZED_OP(sc); 6097 PORT_LOCK_ASSERT_OWNED(pi); 6098 6099 if (lc->requested_aneg == AUTONEG_ENABLE) 6100 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG); 6101 if (!(lc->requested_fc & PAUSE_AUTONEG)) 6102 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE); 6103 if (lc->requested_fc & PAUSE_TX) 6104 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX); 6105 if (lc->requested_fc & PAUSE_RX) 6106 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX); 6107 if (lc->requested_fec & FEC_RS) 6108 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS); 6109 if (lc->requested_fec & FEC_BASER_RS) 6110 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS); 6111 #endif 6112 if (!(sc->flags & IS_VF)) { 6113 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6114 if (rc != 0) { 6115 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 6116 return (rc); 6117 } 6118 } 6119 6120 /* 6121 * An L1_CFG will almost always result in a link-change event if the 6122 * link is up, and the driver will refresh the actual fec/fc/etc. when 6123 * the notification is processed. If the link is down then the actual 6124 * settings are meaningless. 6125 * 6126 * This takes care of the case where a change in the L1 settings may not 6127 * result in a notification. 6128 */ 6129 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 6130 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 6131 6132 return (0); 6133 } 6134 6135 #define FW_MAC_EXACT_CHUNK 7 6136 struct mcaddr_ctx { 6137 if_t ifp; 6138 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 6139 uint64_t hash; 6140 int i; 6141 int del; 6142 int rc; 6143 }; 6144 6145 static u_int 6146 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 6147 { 6148 struct mcaddr_ctx *ctx = arg; 6149 struct vi_info *vi = if_getsoftc(ctx->ifp); 6150 struct port_info *pi = vi->pi; 6151 struct adapter *sc = pi->adapter; 6152 6153 if (ctx->rc < 0) 6154 return (0); 6155 6156 ctx->mcaddr[ctx->i] = LLADDR(sdl); 6157 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i])); 6158 ctx->i++; 6159 6160 if (ctx->i == FW_MAC_EXACT_CHUNK) { 6161 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del, 6162 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0); 6163 if (ctx->rc < 0) { 6164 int j; 6165 6166 for (j = 0; j < ctx->i; j++) { 6167 if_printf(ctx->ifp, 6168 "failed to add mc address" 6169 " %02x:%02x:%02x:" 6170 "%02x:%02x:%02x rc=%d\n", 6171 ctx->mcaddr[j][0], ctx->mcaddr[j][1], 6172 ctx->mcaddr[j][2], ctx->mcaddr[j][3], 6173 ctx->mcaddr[j][4], ctx->mcaddr[j][5], 6174 -ctx->rc); 6175 } 6176 return (0); 6177 } 6178 ctx->del = 0; 6179 ctx->i = 0; 6180 } 6181 6182 return (1); 6183 } 6184 6185 /* 6186 * Program the port's XGMAC based on parameters in ifnet. The caller also 6187 * indicates which parameters should be programmed (the rest are left alone). 6188 */ 6189 int 6190 update_mac_settings(if_t ifp, int flags) 6191 { 6192 int rc = 0; 6193 struct vi_info *vi = if_getsoftc(ifp); 6194 struct port_info *pi = vi->pi; 6195 struct adapter *sc = pi->adapter; 6196 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 6197 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 6198 6199 ASSERT_SYNCHRONIZED_OP(sc); 6200 KASSERT(flags, ("%s: not told what to update.", __func__)); 6201 6202 if (flags & XGMAC_MTU) 6203 mtu = if_getmtu(ifp); 6204 6205 if (flags & XGMAC_PROMISC) 6206 promisc = if_getflags(ifp) & IFF_PROMISC ? 1 : 0; 6207 6208 if (flags & XGMAC_ALLMULTI) 6209 allmulti = if_getflags(ifp) & IFF_ALLMULTI ? 1 : 0; 6210 6211 if (flags & XGMAC_VLANEX) 6212 vlanex = if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING ? 1 : 0; 6213 6214 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 6215 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 6216 allmulti, 1, vlanex, false); 6217 if (rc) { 6218 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 6219 rc); 6220 return (rc); 6221 } 6222 } 6223 6224 if (flags & XGMAC_UCADDR) { 6225 uint8_t ucaddr[ETHER_ADDR_LEN]; 6226 6227 bcopy(if_getlladdr(ifp), ucaddr, sizeof(ucaddr)); 6228 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 6229 ucaddr, true, &vi->smt_idx); 6230 if (rc < 0) { 6231 rc = -rc; 6232 if_printf(ifp, "change_mac failed: %d\n", rc); 6233 return (rc); 6234 } else { 6235 vi->xact_addr_filt = rc; 6236 rc = 0; 6237 } 6238 } 6239 6240 if (flags & XGMAC_MCADDRS) { 6241 struct epoch_tracker et; 6242 struct mcaddr_ctx ctx; 6243 int j; 6244 6245 ctx.ifp = ifp; 6246 ctx.hash = 0; 6247 ctx.i = 0; 6248 ctx.del = 1; 6249 ctx.rc = 0; 6250 /* 6251 * Unlike other drivers, we accumulate list of pointers into 6252 * interface address lists and we need to keep it safe even 6253 * after if_foreach_llmaddr() returns, thus we must enter the 6254 * network epoch. 6255 */ 6256 NET_EPOCH_ENTER(et); 6257 if_foreach_llmaddr(ifp, add_maddr, &ctx); 6258 if (ctx.rc < 0) { 6259 NET_EPOCH_EXIT(et); 6260 rc = -ctx.rc; 6261 return (rc); 6262 } 6263 if (ctx.i > 0) { 6264 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 6265 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0); 6266 NET_EPOCH_EXIT(et); 6267 if (rc < 0) { 6268 rc = -rc; 6269 for (j = 0; j < ctx.i; j++) { 6270 if_printf(ifp, 6271 "failed to add mcast address" 6272 " %02x:%02x:%02x:" 6273 "%02x:%02x:%02x rc=%d\n", 6274 ctx.mcaddr[j][0], ctx.mcaddr[j][1], 6275 ctx.mcaddr[j][2], ctx.mcaddr[j][3], 6276 ctx.mcaddr[j][4], ctx.mcaddr[j][5], 6277 rc); 6278 } 6279 return (rc); 6280 } 6281 ctx.del = 0; 6282 } else 6283 NET_EPOCH_EXIT(et); 6284 6285 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0); 6286 if (rc != 0) 6287 if_printf(ifp, "failed to set mcast address hash: %d\n", 6288 rc); 6289 if (ctx.del == 0) { 6290 /* We clobbered the VXLAN entry if there was one. */ 6291 pi->vxlan_tcam_entry = false; 6292 } 6293 } 6294 6295 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 && 6296 pi->vxlan_tcam_entry == false) { 6297 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac, 6298 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 6299 true); 6300 if (rc < 0) { 6301 rc = -rc; 6302 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n", 6303 rc); 6304 } else { 6305 MPASS(rc == sc->rawf_base + pi->port_id); 6306 rc = 0; 6307 pi->vxlan_tcam_entry = true; 6308 } 6309 } 6310 6311 return (rc); 6312 } 6313 6314 /* 6315 * {begin|end}_synchronized_op must be called from the same thread. 6316 */ 6317 int 6318 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 6319 char *wmesg) 6320 { 6321 int rc, pri; 6322 6323 #ifdef WITNESS 6324 /* the caller thinks it's ok to sleep, but is it really? */ 6325 if (flags & SLEEP_OK) 6326 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 6327 "begin_synchronized_op"); 6328 #endif 6329 6330 if (INTR_OK) 6331 pri = PCATCH; 6332 else 6333 pri = 0; 6334 6335 ADAPTER_LOCK(sc); 6336 for (;;) { 6337 6338 if (vi && IS_DETACHING(vi)) { 6339 rc = ENXIO; 6340 goto done; 6341 } 6342 6343 if (!IS_BUSY(sc)) { 6344 rc = 0; 6345 break; 6346 } 6347 6348 if (!(flags & SLEEP_OK)) { 6349 rc = EBUSY; 6350 goto done; 6351 } 6352 6353 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 6354 rc = EINTR; 6355 goto done; 6356 } 6357 } 6358 6359 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 6360 SET_BUSY(sc); 6361 #ifdef INVARIANTS 6362 sc->last_op = wmesg; 6363 sc->last_op_thr = curthread; 6364 sc->last_op_flags = flags; 6365 #endif 6366 6367 done: 6368 if (!(flags & HOLD_LOCK) || rc) 6369 ADAPTER_UNLOCK(sc); 6370 6371 return (rc); 6372 } 6373 6374 /* 6375 * Tell if_ioctl and if_init that the VI is going away. This is 6376 * special variant of begin_synchronized_op and must be paired with a 6377 * call to end_vi_detach. 6378 */ 6379 void 6380 begin_vi_detach(struct adapter *sc, struct vi_info *vi) 6381 { 6382 ADAPTER_LOCK(sc); 6383 SET_DETACHING(vi); 6384 wakeup(&sc->flags); 6385 while (IS_BUSY(sc)) 6386 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 6387 SET_BUSY(sc); 6388 #ifdef INVARIANTS 6389 sc->last_op = "t4detach"; 6390 sc->last_op_thr = curthread; 6391 sc->last_op_flags = 0; 6392 #endif 6393 ADAPTER_UNLOCK(sc); 6394 } 6395 6396 void 6397 end_vi_detach(struct adapter *sc, struct vi_info *vi) 6398 { 6399 ADAPTER_LOCK(sc); 6400 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6401 CLR_BUSY(sc); 6402 CLR_DETACHING(vi); 6403 wakeup(&sc->flags); 6404 ADAPTER_UNLOCK(sc); 6405 } 6406 6407 /* 6408 * {begin|end}_synchronized_op must be called from the same thread. 6409 */ 6410 void 6411 end_synchronized_op(struct adapter *sc, int flags) 6412 { 6413 6414 if (flags & LOCK_HELD) 6415 ADAPTER_LOCK_ASSERT_OWNED(sc); 6416 else 6417 ADAPTER_LOCK(sc); 6418 6419 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6420 CLR_BUSY(sc); 6421 wakeup(&sc->flags); 6422 ADAPTER_UNLOCK(sc); 6423 } 6424 6425 static int 6426 cxgbe_init_synchronized(struct vi_info *vi) 6427 { 6428 struct port_info *pi = vi->pi; 6429 struct adapter *sc = pi->adapter; 6430 if_t ifp = vi->ifp; 6431 int rc = 0, i; 6432 struct sge_txq *txq; 6433 6434 ASSERT_SYNCHRONIZED_OP(sc); 6435 6436 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6437 return (0); /* already running */ 6438 6439 if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0)) 6440 return (rc); /* error message displayed already */ 6441 6442 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 6443 return (rc); /* error message displayed already */ 6444 6445 rc = update_mac_settings(ifp, XGMAC_ALL); 6446 if (rc) 6447 goto done; /* error message displayed already */ 6448 6449 PORT_LOCK(pi); 6450 if (pi->up_vis == 0) { 6451 t4_update_port_info(pi); 6452 fixup_link_config(pi); 6453 build_medialist(pi); 6454 apply_link_config(pi); 6455 } 6456 6457 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 6458 if (rc != 0) { 6459 if_printf(ifp, "enable_vi failed: %d\n", rc); 6460 PORT_UNLOCK(pi); 6461 goto done; 6462 } 6463 6464 /* 6465 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 6466 * if this changes. 6467 */ 6468 6469 for_each_txq(vi, i, txq) { 6470 TXQ_LOCK(txq); 6471 txq->eq.flags |= EQ_ENABLED; 6472 TXQ_UNLOCK(txq); 6473 } 6474 6475 /* 6476 * The first iq of the first port to come up is used for tracing. 6477 */ 6478 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 6479 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 6480 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 6481 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 6482 V_QUEUENUMBER(sc->traceq)); 6483 pi->flags |= HAS_TRACEQ; 6484 } 6485 6486 /* all ok */ 6487 pi->up_vis++; 6488 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 6489 if (pi->link_cfg.link_ok) 6490 t4_os_link_changed(pi); 6491 PORT_UNLOCK(pi); 6492 6493 mtx_lock(&vi->tick_mtx); 6494 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 6495 callout_reset(&vi->tick, hz, vi_tick, vi); 6496 else 6497 callout_reset(&vi->tick, hz, cxgbe_tick, vi); 6498 mtx_unlock(&vi->tick_mtx); 6499 done: 6500 if (rc != 0) 6501 cxgbe_uninit_synchronized(vi); 6502 6503 return (rc); 6504 } 6505 6506 /* 6507 * Idempotent. 6508 */ 6509 static int 6510 cxgbe_uninit_synchronized(struct vi_info *vi) 6511 { 6512 struct port_info *pi = vi->pi; 6513 struct adapter *sc = pi->adapter; 6514 if_t ifp = vi->ifp; 6515 int rc, i; 6516 struct sge_txq *txq; 6517 6518 ASSERT_SYNCHRONIZED_OP(sc); 6519 6520 if (!(vi->flags & VI_INIT_DONE)) { 6521 if (__predict_false(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6522 KASSERT(0, ("uninited VI is running")); 6523 if_printf(ifp, "uninited VI with running ifnet. " 6524 "vi->flags 0x%016lx, if_flags 0x%08x, " 6525 "if_drv_flags 0x%08x\n", vi->flags, if_getflags(ifp), 6526 if_getdrvflags(ifp)); 6527 } 6528 return (0); 6529 } 6530 6531 /* 6532 * Disable the VI so that all its data in either direction is discarded 6533 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 6534 * tick) intact as the TP can deliver negative advice or data that it's 6535 * holding in its RAM (for an offloaded connection) even after the VI is 6536 * disabled. 6537 */ 6538 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 6539 if (rc) { 6540 if_printf(ifp, "disable_vi failed: %d\n", rc); 6541 return (rc); 6542 } 6543 6544 for_each_txq(vi, i, txq) { 6545 TXQ_LOCK(txq); 6546 txq->eq.flags &= ~EQ_ENABLED; 6547 TXQ_UNLOCK(txq); 6548 } 6549 6550 mtx_lock(&vi->tick_mtx); 6551 callout_stop(&vi->tick); 6552 mtx_unlock(&vi->tick_mtx); 6553 6554 PORT_LOCK(pi); 6555 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 6556 PORT_UNLOCK(pi); 6557 return (0); 6558 } 6559 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 6560 pi->up_vis--; 6561 if (pi->up_vis > 0) { 6562 PORT_UNLOCK(pi); 6563 return (0); 6564 } 6565 6566 pi->link_cfg.link_ok = false; 6567 pi->link_cfg.speed = 0; 6568 pi->link_cfg.link_down_rc = 255; 6569 t4_os_link_changed(pi); 6570 PORT_UNLOCK(pi); 6571 6572 return (0); 6573 } 6574 6575 /* 6576 * It is ok for this function to fail midway and return right away. t4_detach 6577 * will walk the entire sc->irq list and clean up whatever is valid. 6578 */ 6579 int 6580 t4_setup_intr_handlers(struct adapter *sc) 6581 { 6582 int rc, rid, p, q, v; 6583 char s[8]; 6584 struct irq *irq; 6585 struct port_info *pi; 6586 struct vi_info *vi; 6587 struct sge *sge = &sc->sge; 6588 struct sge_rxq *rxq; 6589 #ifdef TCP_OFFLOAD 6590 struct sge_ofld_rxq *ofld_rxq; 6591 #endif 6592 #ifdef DEV_NETMAP 6593 struct sge_nm_rxq *nm_rxq; 6594 #endif 6595 #ifdef RSS 6596 int nbuckets = rss_getnumbuckets(); 6597 #endif 6598 6599 /* 6600 * Setup interrupts. 6601 */ 6602 irq = &sc->irq[0]; 6603 rid = sc->intr_type == INTR_INTX ? 0 : 1; 6604 if (forwarding_intr_to_fwq(sc)) 6605 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 6606 6607 /* Multiple interrupts. */ 6608 if (sc->flags & IS_VF) 6609 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 6610 ("%s: too few intr.", __func__)); 6611 else 6612 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 6613 ("%s: too few intr.", __func__)); 6614 6615 /* The first one is always error intr on PFs */ 6616 if (!(sc->flags & IS_VF)) { 6617 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 6618 if (rc != 0) 6619 return (rc); 6620 irq++; 6621 rid++; 6622 } 6623 6624 /* The second one is always the firmware event queue (first on VFs) */ 6625 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 6626 if (rc != 0) 6627 return (rc); 6628 irq++; 6629 rid++; 6630 6631 for_each_port(sc, p) { 6632 pi = sc->port[p]; 6633 for_each_vi(pi, v, vi) { 6634 vi->first_intr = rid - 1; 6635 6636 if (vi->nnmrxq > 0) { 6637 int n = max(vi->nrxq, vi->nnmrxq); 6638 6639 rxq = &sge->rxq[vi->first_rxq]; 6640 #ifdef DEV_NETMAP 6641 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 6642 #endif 6643 for (q = 0; q < n; q++) { 6644 snprintf(s, sizeof(s), "%x%c%x", p, 6645 'a' + v, q); 6646 if (q < vi->nrxq) 6647 irq->rxq = rxq++; 6648 #ifdef DEV_NETMAP 6649 if (q < vi->nnmrxq) 6650 irq->nm_rxq = nm_rxq++; 6651 6652 if (irq->nm_rxq != NULL && 6653 irq->rxq == NULL) { 6654 /* Netmap rx only */ 6655 rc = t4_alloc_irq(sc, irq, rid, 6656 t4_nm_intr, irq->nm_rxq, s); 6657 } 6658 if (irq->nm_rxq != NULL && 6659 irq->rxq != NULL) { 6660 /* NIC and Netmap rx */ 6661 rc = t4_alloc_irq(sc, irq, rid, 6662 t4_vi_intr, irq, s); 6663 } 6664 #endif 6665 if (irq->rxq != NULL && 6666 irq->nm_rxq == NULL) { 6667 /* NIC rx only */ 6668 rc = t4_alloc_irq(sc, irq, rid, 6669 t4_intr, irq->rxq, s); 6670 } 6671 if (rc != 0) 6672 return (rc); 6673 #ifdef RSS 6674 if (q < vi->nrxq) { 6675 bus_bind_intr(sc->dev, irq->res, 6676 rss_getcpu(q % nbuckets)); 6677 } 6678 #endif 6679 irq++; 6680 rid++; 6681 vi->nintr++; 6682 } 6683 } else { 6684 for_each_rxq(vi, q, rxq) { 6685 snprintf(s, sizeof(s), "%x%c%x", p, 6686 'a' + v, q); 6687 rc = t4_alloc_irq(sc, irq, rid, 6688 t4_intr, rxq, s); 6689 if (rc != 0) 6690 return (rc); 6691 #ifdef RSS 6692 bus_bind_intr(sc->dev, irq->res, 6693 rss_getcpu(q % nbuckets)); 6694 #endif 6695 irq++; 6696 rid++; 6697 vi->nintr++; 6698 } 6699 } 6700 #ifdef TCP_OFFLOAD 6701 for_each_ofld_rxq(vi, q, ofld_rxq) { 6702 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 6703 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 6704 ofld_rxq, s); 6705 if (rc != 0) 6706 return (rc); 6707 irq++; 6708 rid++; 6709 vi->nintr++; 6710 } 6711 #endif 6712 } 6713 } 6714 MPASS(irq == &sc->irq[sc->intr_count]); 6715 6716 return (0); 6717 } 6718 6719 static void 6720 write_global_rss_key(struct adapter *sc) 6721 { 6722 #ifdef RSS 6723 int i; 6724 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6725 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6726 6727 CTASSERT(RSS_KEYSIZE == 40); 6728 6729 rss_getkey((void *)&raw_rss_key[0]); 6730 for (i = 0; i < nitems(rss_key); i++) { 6731 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 6732 } 6733 t4_write_rss_key(sc, &rss_key[0], -1, 1); 6734 #endif 6735 } 6736 6737 /* 6738 * Idempotent. 6739 */ 6740 static int 6741 adapter_full_init(struct adapter *sc) 6742 { 6743 int rc, i; 6744 6745 ASSERT_SYNCHRONIZED_OP(sc); 6746 6747 /* 6748 * queues that belong to the adapter (not any particular port). 6749 */ 6750 rc = t4_setup_adapter_queues(sc); 6751 if (rc != 0) 6752 return (rc); 6753 6754 MPASS(sc->params.nports <= nitems(sc->tq)); 6755 for (i = 0; i < sc->params.nports; i++) { 6756 if (sc->tq[i] != NULL) 6757 continue; 6758 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 6759 taskqueue_thread_enqueue, &sc->tq[i]); 6760 if (sc->tq[i] == NULL) { 6761 CH_ERR(sc, "failed to allocate task queue %d\n", i); 6762 return (ENOMEM); 6763 } 6764 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 6765 device_get_nameunit(sc->dev), i); 6766 } 6767 6768 if (!(sc->flags & IS_VF)) { 6769 write_global_rss_key(sc); 6770 t4_intr_enable(sc); 6771 } 6772 return (0); 6773 } 6774 6775 int 6776 adapter_init(struct adapter *sc) 6777 { 6778 int rc; 6779 6780 ASSERT_SYNCHRONIZED_OP(sc); 6781 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 6782 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 6783 ("%s: FULL_INIT_DONE already", __func__)); 6784 6785 rc = adapter_full_init(sc); 6786 if (rc != 0) 6787 adapter_full_uninit(sc); 6788 else 6789 sc->flags |= FULL_INIT_DONE; 6790 6791 return (rc); 6792 } 6793 6794 /* 6795 * Idempotent. 6796 */ 6797 static void 6798 adapter_full_uninit(struct adapter *sc) 6799 { 6800 int i; 6801 6802 t4_teardown_adapter_queues(sc); 6803 6804 for (i = 0; i < nitems(sc->tq); i++) { 6805 if (sc->tq[i] == NULL) 6806 continue; 6807 taskqueue_free(sc->tq[i]); 6808 sc->tq[i] = NULL; 6809 } 6810 6811 sc->flags &= ~FULL_INIT_DONE; 6812 } 6813 6814 #ifdef RSS 6815 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 6816 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 6817 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 6818 RSS_HASHTYPE_RSS_UDP_IPV6) 6819 6820 /* Translates kernel hash types to hardware. */ 6821 static int 6822 hashconfig_to_hashen(int hashconfig) 6823 { 6824 int hashen = 0; 6825 6826 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 6827 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 6828 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 6829 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 6830 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 6831 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6832 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6833 } 6834 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 6835 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6836 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6837 } 6838 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 6839 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6840 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 6841 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6842 6843 return (hashen); 6844 } 6845 6846 /* Translates hardware hash types to kernel. */ 6847 static int 6848 hashen_to_hashconfig(int hashen) 6849 { 6850 int hashconfig = 0; 6851 6852 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 6853 /* 6854 * If UDP hashing was enabled it must have been enabled for 6855 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 6856 * enabling any 4-tuple hash is nonsense configuration. 6857 */ 6858 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6859 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 6860 6861 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6862 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 6863 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6864 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 6865 } 6866 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6867 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 6868 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6869 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 6870 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6871 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 6872 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6873 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 6874 6875 return (hashconfig); 6876 } 6877 #endif 6878 6879 /* 6880 * Idempotent. 6881 */ 6882 static int 6883 vi_full_init(struct vi_info *vi) 6884 { 6885 struct adapter *sc = vi->adapter; 6886 struct sge_rxq *rxq; 6887 int rc, i, j; 6888 #ifdef RSS 6889 int nbuckets = rss_getnumbuckets(); 6890 int hashconfig = rss_gethashconfig(); 6891 int extra; 6892 #endif 6893 6894 ASSERT_SYNCHRONIZED_OP(sc); 6895 6896 /* 6897 * Allocate tx/rx/fl queues for this VI. 6898 */ 6899 rc = t4_setup_vi_queues(vi); 6900 if (rc != 0) 6901 return (rc); 6902 6903 /* 6904 * Setup RSS for this VI. Save a copy of the RSS table for later use. 6905 */ 6906 if (vi->nrxq > vi->rss_size) { 6907 CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); " 6908 "some queues will never receive traffic.\n", vi->nrxq, 6909 vi->rss_size); 6910 } else if (vi->rss_size % vi->nrxq) { 6911 CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); " 6912 "expect uneven traffic distribution.\n", vi->nrxq, 6913 vi->rss_size); 6914 } 6915 #ifdef RSS 6916 if (vi->nrxq != nbuckets) { 6917 CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);" 6918 "performance will be impacted.\n", vi->nrxq, nbuckets); 6919 } 6920 #endif 6921 if (vi->rss == NULL) 6922 vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE, 6923 M_ZERO | M_WAITOK); 6924 for (i = 0; i < vi->rss_size;) { 6925 #ifdef RSS 6926 j = rss_get_indirection_to_bucket(i); 6927 j %= vi->nrxq; 6928 rxq = &sc->sge.rxq[vi->first_rxq + j]; 6929 vi->rss[i++] = rxq->iq.abs_id; 6930 #else 6931 for_each_rxq(vi, j, rxq) { 6932 vi->rss[i++] = rxq->iq.abs_id; 6933 if (i == vi->rss_size) 6934 break; 6935 } 6936 #endif 6937 } 6938 6939 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 6940 vi->rss, vi->rss_size); 6941 if (rc != 0) { 6942 CH_ERR(vi, "rss_config failed: %d\n", rc); 6943 return (rc); 6944 } 6945 6946 #ifdef RSS 6947 vi->hashen = hashconfig_to_hashen(hashconfig); 6948 6949 /* 6950 * We may have had to enable some hashes even though the global config 6951 * wants them disabled. This is a potential problem that must be 6952 * reported to the user. 6953 */ 6954 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 6955 6956 /* 6957 * If we consider only the supported hash types, then the enabled hashes 6958 * are a superset of the requested hashes. In other words, there cannot 6959 * be any supported hash that was requested but not enabled, but there 6960 * can be hashes that were not requested but had to be enabled. 6961 */ 6962 extra &= SUPPORTED_RSS_HASHTYPES; 6963 MPASS((extra & hashconfig) == 0); 6964 6965 if (extra) { 6966 CH_ALERT(vi, 6967 "global RSS config (0x%x) cannot be accommodated.\n", 6968 hashconfig); 6969 } 6970 if (extra & RSS_HASHTYPE_RSS_IPV4) 6971 CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n"); 6972 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 6973 CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n"); 6974 if (extra & RSS_HASHTYPE_RSS_IPV6) 6975 CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n"); 6976 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 6977 CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n"); 6978 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 6979 CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n"); 6980 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 6981 CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n"); 6982 #else 6983 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 6984 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 6985 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6986 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 6987 #endif 6988 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 6989 0, 0); 6990 if (rc != 0) { 6991 CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc); 6992 return (rc); 6993 } 6994 6995 return (0); 6996 } 6997 6998 int 6999 vi_init(struct vi_info *vi) 7000 { 7001 int rc; 7002 7003 ASSERT_SYNCHRONIZED_OP(vi->adapter); 7004 KASSERT((vi->flags & VI_INIT_DONE) == 0, 7005 ("%s: VI_INIT_DONE already", __func__)); 7006 7007 rc = vi_full_init(vi); 7008 if (rc != 0) 7009 vi_full_uninit(vi); 7010 else 7011 vi->flags |= VI_INIT_DONE; 7012 7013 return (rc); 7014 } 7015 7016 /* 7017 * Idempotent. 7018 */ 7019 static void 7020 vi_full_uninit(struct vi_info *vi) 7021 { 7022 7023 if (vi->flags & VI_INIT_DONE) { 7024 quiesce_vi(vi); 7025 free(vi->rss, M_CXGBE); 7026 free(vi->nm_rss, M_CXGBE); 7027 } 7028 7029 t4_teardown_vi_queues(vi); 7030 vi->flags &= ~VI_INIT_DONE; 7031 } 7032 7033 static void 7034 quiesce_txq(struct sge_txq *txq) 7035 { 7036 struct sge_eq *eq = &txq->eq; 7037 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 7038 7039 MPASS(eq->flags & EQ_SW_ALLOCATED); 7040 MPASS(!(eq->flags & EQ_ENABLED)); 7041 7042 /* Wait for the mp_ring to empty. */ 7043 while (!mp_ring_is_idle(txq->r)) { 7044 mp_ring_check_drainage(txq->r, 4096); 7045 pause("rquiesce", 1); 7046 } 7047 MPASS(txq->txp.npkt == 0); 7048 7049 if (eq->flags & EQ_HW_ALLOCATED) { 7050 /* 7051 * Hardware is alive and working normally. Wait for it to 7052 * finish and then wait for the driver to catch up and reclaim 7053 * all descriptors. 7054 */ 7055 while (spg->cidx != htobe16(eq->pidx)) 7056 pause("equiesce", 1); 7057 while (eq->cidx != eq->pidx) 7058 pause("dquiesce", 1); 7059 } else { 7060 /* 7061 * Hardware is unavailable. Discard all pending tx and reclaim 7062 * descriptors directly. 7063 */ 7064 TXQ_LOCK(txq); 7065 while (eq->cidx != eq->pidx) { 7066 struct mbuf *m, *nextpkt; 7067 struct tx_sdesc *txsd; 7068 7069 txsd = &txq->sdesc[eq->cidx]; 7070 for (m = txsd->m; m != NULL; m = nextpkt) { 7071 nextpkt = m->m_nextpkt; 7072 m->m_nextpkt = NULL; 7073 m_freem(m); 7074 } 7075 IDXINCR(eq->cidx, txsd->desc_used, eq->sidx); 7076 } 7077 spg->pidx = spg->cidx = htobe16(eq->cidx); 7078 TXQ_UNLOCK(txq); 7079 } 7080 } 7081 7082 static void 7083 quiesce_wrq(struct sge_wrq *wrq) 7084 { 7085 struct wrqe *wr; 7086 7087 TXQ_LOCK(wrq); 7088 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 7089 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 7090 #ifdef INVARIANTS 7091 wrq->nwr_pending--; 7092 wrq->ndesc_needed -= howmany(wr->wr_len, EQ_ESIZE); 7093 #endif 7094 free(wr, M_CXGBE); 7095 } 7096 MPASS(wrq->nwr_pending == 0); 7097 MPASS(wrq->ndesc_needed == 0); 7098 wrq->nwr_pending = 0; 7099 wrq->ndesc_needed = 0; 7100 TXQ_UNLOCK(wrq); 7101 } 7102 7103 static void 7104 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 7105 { 7106 /* Synchronize with the interrupt handler */ 7107 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 7108 pause("iqfree", 1); 7109 7110 if (fl != NULL) { 7111 MPASS(iq->flags & IQ_HAS_FL); 7112 7113 mtx_lock(&sc->sfl_lock); 7114 FL_LOCK(fl); 7115 fl->flags |= FL_DOOMED; 7116 FL_UNLOCK(fl); 7117 callout_stop(&sc->sfl_callout); 7118 mtx_unlock(&sc->sfl_lock); 7119 7120 KASSERT((fl->flags & FL_STARVING) == 0, 7121 ("%s: still starving", __func__)); 7122 7123 /* Release all buffers if hardware is no longer available. */ 7124 if (!(iq->flags & IQ_HW_ALLOCATED)) 7125 free_fl_buffers(sc, fl); 7126 } 7127 } 7128 7129 /* 7130 * Wait for all activity on all the queues of the VI to complete. It is assumed 7131 * that no new work is being enqueued by the hardware or the driver. That part 7132 * should be arranged before calling this function. 7133 */ 7134 static void 7135 quiesce_vi(struct vi_info *vi) 7136 { 7137 int i; 7138 struct adapter *sc = vi->adapter; 7139 struct sge_rxq *rxq; 7140 struct sge_txq *txq; 7141 #ifdef TCP_OFFLOAD 7142 struct sge_ofld_rxq *ofld_rxq; 7143 #endif 7144 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7145 struct sge_ofld_txq *ofld_txq; 7146 #endif 7147 7148 if (!(vi->flags & VI_INIT_DONE)) 7149 return; 7150 7151 for_each_txq(vi, i, txq) { 7152 quiesce_txq(txq); 7153 } 7154 7155 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7156 for_each_ofld_txq(vi, i, ofld_txq) { 7157 quiesce_wrq(&ofld_txq->wrq); 7158 } 7159 #endif 7160 7161 for_each_rxq(vi, i, rxq) { 7162 quiesce_iq_fl(sc, &rxq->iq, &rxq->fl); 7163 } 7164 7165 #ifdef TCP_OFFLOAD 7166 for_each_ofld_rxq(vi, i, ofld_rxq) { 7167 quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl); 7168 } 7169 #endif 7170 } 7171 7172 static int 7173 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 7174 driver_intr_t *handler, void *arg, char *name) 7175 { 7176 int rc; 7177 7178 irq->rid = rid; 7179 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 7180 RF_SHAREABLE | RF_ACTIVE); 7181 if (irq->res == NULL) { 7182 device_printf(sc->dev, 7183 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 7184 return (ENOMEM); 7185 } 7186 7187 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 7188 NULL, handler, arg, &irq->tag); 7189 if (rc != 0) { 7190 device_printf(sc->dev, 7191 "failed to setup interrupt for rid %d, name %s: %d\n", 7192 rid, name, rc); 7193 } else if (name) 7194 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 7195 7196 return (rc); 7197 } 7198 7199 static int 7200 t4_free_irq(struct adapter *sc, struct irq *irq) 7201 { 7202 if (irq->tag) 7203 bus_teardown_intr(sc->dev, irq->res, irq->tag); 7204 if (irq->res) 7205 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 7206 7207 bzero(irq, sizeof(*irq)); 7208 7209 return (0); 7210 } 7211 7212 static void 7213 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 7214 { 7215 7216 regs->version = chip_id(sc) | chip_rev(sc) << 10; 7217 t4_get_regs(sc, buf, regs->len); 7218 } 7219 7220 #define A_PL_INDIR_CMD 0x1f8 7221 7222 #define S_PL_AUTOINC 31 7223 #define M_PL_AUTOINC 0x1U 7224 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 7225 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 7226 7227 #define S_PL_VFID 20 7228 #define M_PL_VFID 0xffU 7229 #define V_PL_VFID(x) ((x) << S_PL_VFID) 7230 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 7231 7232 #define S_PL_ADDR 0 7233 #define M_PL_ADDR 0xfffffU 7234 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 7235 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 7236 7237 #define A_PL_INDIR_DATA 0x1fc 7238 7239 static uint64_t 7240 read_vf_stat(struct adapter *sc, u_int vin, int reg) 7241 { 7242 u32 stats[2]; 7243 7244 if (sc->flags & IS_VF) { 7245 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 7246 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 7247 } else { 7248 mtx_assert(&sc->reg_lock, MA_OWNED); 7249 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 7250 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 7251 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 7252 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 7253 } 7254 return (((uint64_t)stats[1]) << 32 | stats[0]); 7255 } 7256 7257 static void 7258 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 7259 { 7260 7261 #define GET_STAT(name) \ 7262 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 7263 7264 if (!(sc->flags & IS_VF)) 7265 mtx_lock(&sc->reg_lock); 7266 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 7267 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 7268 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 7269 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 7270 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 7271 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 7272 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 7273 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 7274 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 7275 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 7276 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 7277 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 7278 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 7279 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 7280 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 7281 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 7282 if (!(sc->flags & IS_VF)) 7283 mtx_unlock(&sc->reg_lock); 7284 7285 #undef GET_STAT 7286 } 7287 7288 static void 7289 t4_clr_vi_stats(struct adapter *sc, u_int vin) 7290 { 7291 int reg; 7292 7293 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 7294 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 7295 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 7296 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 7297 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 7298 } 7299 7300 static void 7301 vi_refresh_stats(struct vi_info *vi) 7302 { 7303 struct timeval tv; 7304 const struct timeval interval = {0, 250000}; /* 250ms */ 7305 7306 mtx_assert(&vi->tick_mtx, MA_OWNED); 7307 7308 if (vi->flags & VI_SKIP_STATS) 7309 return; 7310 7311 getmicrotime(&tv); 7312 timevalsub(&tv, &interval); 7313 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7314 return; 7315 7316 t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats); 7317 getmicrotime(&vi->last_refreshed); 7318 } 7319 7320 static void 7321 cxgbe_refresh_stats(struct vi_info *vi) 7322 { 7323 u_int i, v, tnl_cong_drops, chan_map; 7324 struct timeval tv; 7325 const struct timeval interval = {0, 250000}; /* 250ms */ 7326 struct port_info *pi; 7327 struct adapter *sc; 7328 7329 mtx_assert(&vi->tick_mtx, MA_OWNED); 7330 7331 if (vi->flags & VI_SKIP_STATS) 7332 return; 7333 7334 getmicrotime(&tv); 7335 timevalsub(&tv, &interval); 7336 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7337 return; 7338 7339 pi = vi->pi; 7340 sc = vi->adapter; 7341 tnl_cong_drops = 0; 7342 t4_get_port_stats(sc, pi->port_id, &pi->stats); 7343 chan_map = pi->rx_e_chan_map; 7344 while (chan_map) { 7345 i = ffs(chan_map) - 1; 7346 mtx_lock(&sc->reg_lock); 7347 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 7348 A_TP_MIB_TNL_CNG_DROP_0 + i); 7349 mtx_unlock(&sc->reg_lock); 7350 tnl_cong_drops += v; 7351 chan_map &= ~(1 << i); 7352 } 7353 pi->tnl_cong_drops = tnl_cong_drops; 7354 getmicrotime(&vi->last_refreshed); 7355 } 7356 7357 static void 7358 cxgbe_tick(void *arg) 7359 { 7360 struct vi_info *vi = arg; 7361 7362 MPASS(IS_MAIN_VI(vi)); 7363 mtx_assert(&vi->tick_mtx, MA_OWNED); 7364 7365 cxgbe_refresh_stats(vi); 7366 callout_schedule(&vi->tick, hz); 7367 } 7368 7369 static void 7370 vi_tick(void *arg) 7371 { 7372 struct vi_info *vi = arg; 7373 7374 mtx_assert(&vi->tick_mtx, MA_OWNED); 7375 7376 vi_refresh_stats(vi); 7377 callout_schedule(&vi->tick, hz); 7378 } 7379 7380 /* 7381 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 7382 */ 7383 static char *caps_decoder[] = { 7384 "\20\001IPMI\002NCSI", /* 0: NBM */ 7385 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 7386 "\20\001INGRESS\002EGRESS", /* 2: switch */ 7387 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 7388 "\006HASHFILTER\007ETHOFLD", 7389 "\20\001TOE", /* 4: TOE */ 7390 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 7391 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 7392 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 7393 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 7394 "\007T10DIF" 7395 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 7396 "\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE" /* 7: Crypto */ 7397 "\004TLS_HW", 7398 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 7399 "\004PO_INITIATOR\005PO_TARGET", 7400 }; 7401 7402 void 7403 t4_sysctls(struct adapter *sc) 7404 { 7405 struct sysctl_ctx_list *ctx = &sc->ctx; 7406 struct sysctl_oid *oid; 7407 struct sysctl_oid_list *children, *c0; 7408 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 7409 7410 /* 7411 * dev.t4nex.X. 7412 */ 7413 oid = device_get_sysctl_tree(sc->dev); 7414 c0 = children = SYSCTL_CHILDREN(oid); 7415 7416 sc->sc_do_rxcopy = 1; 7417 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 7418 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 7419 7420 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 7421 sc->params.nports, "# of ports"); 7422 7423 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 7424 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells, 7425 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A", 7426 "available doorbells"); 7427 7428 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 7429 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 7430 7431 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 7432 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7433 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val), 7434 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 7435 7436 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 7437 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7438 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val), 7439 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 7440 7441 t4_sge_sysctls(sc, ctx, children); 7442 7443 sc->lro_timeout = 100; 7444 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 7445 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 7446 7447 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 7448 &sc->debug_flags, 0, "flags to enable runtime debugging"); 7449 7450 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 7451 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 7452 7453 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 7454 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 7455 7456 if (sc->flags & IS_VF) 7457 return; 7458 7459 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 7460 NULL, chip_rev(sc), "chip hardware revision"); 7461 7462 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 7463 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 7464 7465 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 7466 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 7467 7468 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 7469 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 7470 7471 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 7472 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 7473 7474 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 7475 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 7476 7477 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 7478 sc->er_version, 0, "expansion ROM version"); 7479 7480 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 7481 sc->bs_version, 0, "bootstrap firmware version"); 7482 7483 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 7484 NULL, sc->params.scfg_vers, "serial config version"); 7485 7486 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 7487 NULL, sc->params.vpd_vers, "VPD version"); 7488 7489 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 7490 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 7491 7492 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 7493 sc->cfcsum, "config file checksum"); 7494 7495 #define SYSCTL_CAP(name, n, text) \ 7496 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 7497 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \ 7498 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \ 7499 "available " text " capabilities") 7500 7501 SYSCTL_CAP(nbmcaps, 0, "NBM"); 7502 SYSCTL_CAP(linkcaps, 1, "link"); 7503 SYSCTL_CAP(switchcaps, 2, "switch"); 7504 SYSCTL_CAP(niccaps, 3, "NIC"); 7505 SYSCTL_CAP(toecaps, 4, "TCP offload"); 7506 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 7507 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 7508 SYSCTL_CAP(cryptocaps, 7, "crypto"); 7509 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 7510 #undef SYSCTL_CAP 7511 7512 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 7513 NULL, sc->tids.nftids, "number of filters"); 7514 7515 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7516 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7517 sysctl_temperature, "I", "chip temperature (in Celsius)"); 7518 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", 7519 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7520 sysctl_reset_sensor, "I", "reset the chip's temperature sensor."); 7521 7522 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", 7523 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7524 sysctl_loadavg, "A", 7525 "microprocessor load averages (debug firmwares only)"); 7526 7527 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", 7528 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd, 7529 "I", "core Vdd (in mV)"); 7530 7531 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 7532 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS, 7533 sysctl_cpus, "A", "local CPUs"); 7534 7535 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 7536 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS, 7537 sysctl_cpus, "A", "preferred CPUs for interrupts"); 7538 7539 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 7540 &sc->swintr, 0, "software triggered interrupts"); 7541 7542 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset", 7543 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I", 7544 "1 = reset adapter, 0 = zero reset counter"); 7545 7546 /* 7547 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 7548 */ 7549 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 7550 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL, 7551 "logs and miscellaneous information"); 7552 children = SYSCTL_CHILDREN(oid); 7553 7554 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 7555 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7556 sysctl_cctrl, "A", "congestion control"); 7557 7558 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 7559 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7560 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 7561 7562 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 7563 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7564 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 7565 7566 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 7567 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7568 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 7569 7570 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 7571 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3, 7572 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 7573 7574 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 7575 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4, 7576 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 7577 7578 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 7579 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5, 7580 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 7581 7582 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 7583 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7584 sysctl_cim_la, "A", "CIM logic analyzer"); 7585 7586 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 7587 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7588 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 7589 7590 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 7591 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7592 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 7593 7594 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 7595 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7596 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 7597 7598 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 7599 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7600 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 7601 7602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 7603 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7604 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 7605 7606 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 7607 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7608 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 7609 7610 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 7611 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7612 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 7613 7614 if (chip_id(sc) > CHELSIO_T4) { 7615 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 7616 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7617 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7618 "CIM OBQ 6 (SGE0-RX)"); 7619 7620 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 7621 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7622 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7623 "CIM OBQ 7 (SGE1-RX)"); 7624 } 7625 7626 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 7627 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7628 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 7629 7630 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 7631 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7632 sysctl_cim_qcfg, "A", "CIM queue configuration"); 7633 7634 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 7635 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7636 sysctl_cpl_stats, "A", "CPL statistics"); 7637 7638 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 7639 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7640 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 7641 7642 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats", 7643 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7644 sysctl_tid_stats, "A", "tid stats"); 7645 7646 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 7647 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7648 sysctl_devlog, "A", "firmware's device log"); 7649 7650 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 7651 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7652 sysctl_fcoe_stats, "A", "FCoE statistics"); 7653 7654 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 7655 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7656 sysctl_hw_sched, "A", "hardware scheduler "); 7657 7658 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 7659 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7660 sysctl_l2t, "A", "hardware L2 table"); 7661 7662 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 7663 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7664 sysctl_smt, "A", "hardware source MAC table"); 7665 7666 #ifdef INET6 7667 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 7668 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7669 sysctl_clip, "A", "active CLIP table entries"); 7670 #endif 7671 7672 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 7673 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7674 sysctl_lb_stats, "A", "loopback statistics"); 7675 7676 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 7677 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7678 sysctl_meminfo, "A", "memory regions"); 7679 7680 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 7681 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7682 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 7683 "A", "MPS TCAM entries"); 7684 7685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 7686 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7687 sysctl_path_mtus, "A", "path MTUs"); 7688 7689 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 7690 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7691 sysctl_pm_stats, "A", "PM statistics"); 7692 7693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 7694 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7695 sysctl_rdma_stats, "A", "RDMA statistics"); 7696 7697 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 7698 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7699 sysctl_tcp_stats, "A", "TCP statistics"); 7700 7701 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 7702 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7703 sysctl_tids, "A", "TID information"); 7704 7705 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 7706 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7707 sysctl_tp_err_stats, "A", "TP error statistics"); 7708 7709 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats", 7710 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7711 sysctl_tnl_stats, "A", "TP tunnel statistics"); 7712 7713 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 7714 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7715 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask"); 7716 7717 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 7718 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7719 sysctl_tp_la, "A", "TP logic analyzer"); 7720 7721 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 7722 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7723 sysctl_tx_rate, "A", "Tx rate"); 7724 7725 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 7726 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7727 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 7728 7729 if (chip_id(sc) >= CHELSIO_T5) { 7730 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 7731 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7732 sysctl_wcwr_stats, "A", "write combined work requests"); 7733 } 7734 7735 #ifdef KERN_TLS 7736 if (is_ktls(sc)) { 7737 /* 7738 * dev.t4nex.0.tls. 7739 */ 7740 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", 7741 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters"); 7742 children = SYSCTL_CHILDREN(oid); 7743 7744 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys", 7745 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS " 7746 "keys in work requests (1) or attempt to store TLS keys " 7747 "in card memory."); 7748 7749 if (is_t6(sc)) 7750 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs", 7751 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to " 7752 "combine TCB field updates with TLS record work " 7753 "requests."); 7754 } 7755 #endif 7756 7757 #ifdef TCP_OFFLOAD 7758 if (is_offload(sc)) { 7759 int i; 7760 char s[4]; 7761 7762 /* 7763 * dev.t4nex.X.toe. 7764 */ 7765 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", 7766 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters"); 7767 children = SYSCTL_CHILDREN(oid); 7768 7769 sc->tt.cong_algorithm = -1; 7770 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 7771 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 7772 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 7773 "3 = highspeed)"); 7774 7775 sc->tt.sndbuf = -1; 7776 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 7777 &sc->tt.sndbuf, 0, "hardware send buffer"); 7778 7779 sc->tt.ddp = 0; 7780 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", 7781 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, ""); 7782 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW, 7783 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)"); 7784 7785 sc->tt.rx_coalesce = -1; 7786 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 7787 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 7788 7789 sc->tt.tls = 1; 7790 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT | 7791 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I", 7792 "Inline TLS allowed"); 7793 7794 sc->tt.tx_align = -1; 7795 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 7796 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 7797 7798 sc->tt.tx_zcopy = 0; 7799 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 7800 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 7801 "Enable zero-copy aio_write(2)"); 7802 7803 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 7804 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7805 "cop_managed_offloading", CTLFLAG_RW, 7806 &sc->tt.cop_managed_offloading, 0, 7807 "COP (Connection Offload Policy) controls all TOE offload"); 7808 7809 sc->tt.autorcvbuf_inc = 16 * 1024; 7810 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 7811 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 7812 "autorcvbuf increment"); 7813 7814 sc->tt.update_hc_on_pmtu_change = 1; 7815 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7816 "update_hc_on_pmtu_change", CTLFLAG_RW, 7817 &sc->tt.update_hc_on_pmtu_change, 0, 7818 "Update hostcache entry if the PMTU changes"); 7819 7820 sc->tt.iso = 1; 7821 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW, 7822 &sc->tt.iso, 0, "Enable iSCSI segmentation offload"); 7823 7824 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 7825 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7826 sysctl_tp_tick, "A", "TP timer tick (us)"); 7827 7828 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 7829 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7830 sysctl_tp_tick, "A", "TCP timestamp tick (us)"); 7831 7832 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 7833 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7834 sysctl_tp_tick, "A", "DACK tick (us)"); 7835 7836 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 7837 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7838 sysctl_tp_dack_timer, "IU", "DACK timer (us)"); 7839 7840 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 7841 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7842 A_TP_RXT_MIN, sysctl_tp_timer, "LU", 7843 "Minimum retransmit interval (us)"); 7844 7845 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 7846 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7847 A_TP_RXT_MAX, sysctl_tp_timer, "LU", 7848 "Maximum retransmit interval (us)"); 7849 7850 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 7851 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7852 A_TP_PERS_MIN, sysctl_tp_timer, "LU", 7853 "Persist timer min (us)"); 7854 7855 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 7856 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7857 A_TP_PERS_MAX, sysctl_tp_timer, "LU", 7858 "Persist timer max (us)"); 7859 7860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 7861 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7862 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU", 7863 "Keepalive idle timer (us)"); 7864 7865 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 7866 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7867 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU", 7868 "Keepalive interval timer (us)"); 7869 7870 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 7871 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7872 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)"); 7873 7874 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 7875 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7876 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU", 7877 "FINWAIT2 timer (us)"); 7878 7879 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 7880 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7881 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU", 7882 "Number of SYN retransmissions before abort"); 7883 7884 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 7885 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7886 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU", 7887 "Number of retransmissions before abort"); 7888 7889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 7890 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7891 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU", 7892 "Number of keepalive probes before abort"); 7893 7894 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 7895 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7896 "TOE retransmit backoffs"); 7897 children = SYSCTL_CHILDREN(oid); 7898 for (i = 0; i < 16; i++) { 7899 snprintf(s, sizeof(s), "%u", i); 7900 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 7901 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7902 i, sysctl_tp_backoff, "IU", 7903 "TOE retransmit backoff"); 7904 } 7905 } 7906 #endif 7907 } 7908 7909 void 7910 vi_sysctls(struct vi_info *vi) 7911 { 7912 struct sysctl_ctx_list *ctx = &vi->ctx; 7913 struct sysctl_oid *oid; 7914 struct sysctl_oid_list *children; 7915 7916 /* 7917 * dev.v?(cxgbe|cxl).X. 7918 */ 7919 oid = device_get_sysctl_tree(vi->dev); 7920 children = SYSCTL_CHILDREN(oid); 7921 7922 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 7923 vi->viid, "VI identifer"); 7924 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 7925 &vi->nrxq, 0, "# of rx queues"); 7926 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 7927 &vi->ntxq, 0, "# of tx queues"); 7928 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 7929 &vi->first_rxq, 0, "index of first rx queue"); 7930 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 7931 &vi->first_txq, 0, "index of first tx queue"); 7932 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 7933 vi->rss_base, "start of RSS indirection table"); 7934 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 7935 vi->rss_size, "size of RSS indirection table"); 7936 7937 if (IS_MAIN_VI(vi)) { 7938 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 7939 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7940 sysctl_noflowq, "IU", 7941 "Reserve queue 0 for non-flowid packets"); 7942 } 7943 7944 if (vi->adapter->flags & IS_VF) { 7945 MPASS(vi->flags & TX_USES_VM_WR); 7946 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD, 7947 NULL, 1, "use VM work requests for transmit"); 7948 } else { 7949 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr", 7950 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7951 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit"); 7952 } 7953 7954 #ifdef TCP_OFFLOAD 7955 if (vi->nofldrxq != 0) { 7956 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 7957 &vi->nofldrxq, 0, 7958 "# of rx queues for offloaded TCP connections"); 7959 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 7960 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 7961 "index of first TOE rx queue"); 7962 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 7963 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7964 sysctl_holdoff_tmr_idx_ofld, "I", 7965 "holdoff timer index for TOE queues"); 7966 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 7967 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7968 sysctl_holdoff_pktc_idx_ofld, "I", 7969 "holdoff packet counter index for TOE queues"); 7970 } 7971 #endif 7972 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7973 if (vi->nofldtxq != 0) { 7974 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 7975 &vi->nofldtxq, 0, 7976 "# of tx queues for TOE/ETHOFLD"); 7977 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 7978 CTLFLAG_RD, &vi->first_ofld_txq, 0, 7979 "index of first TOE/ETHOFLD tx queue"); 7980 } 7981 #endif 7982 #ifdef DEV_NETMAP 7983 if (vi->nnmrxq != 0) { 7984 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 7985 &vi->nnmrxq, 0, "# of netmap rx queues"); 7986 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 7987 &vi->nnmtxq, 0, "# of netmap tx queues"); 7988 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 7989 CTLFLAG_RD, &vi->first_nm_rxq, 0, 7990 "index of first netmap rx queue"); 7991 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 7992 CTLFLAG_RD, &vi->first_nm_txq, 0, 7993 "index of first netmap tx queue"); 7994 } 7995 #endif 7996 7997 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 7998 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7999 sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); 8000 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 8001 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 8002 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); 8003 8004 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 8005 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 8006 sysctl_qsize_rxq, "I", "rx queue size"); 8007 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 8008 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 8009 sysctl_qsize_txq, "I", "tx queue size"); 8010 } 8011 8012 static void 8013 cxgbe_sysctls(struct port_info *pi) 8014 { 8015 struct sysctl_ctx_list *ctx = &pi->ctx; 8016 struct sysctl_oid *oid; 8017 struct sysctl_oid_list *children, *children2; 8018 struct adapter *sc = pi->adapter; 8019 int i; 8020 char name[16]; 8021 static char *tc_flags = {"\20\1USER"}; 8022 8023 /* 8024 * dev.cxgbe.X. 8025 */ 8026 oid = device_get_sysctl_tree(pi->dev); 8027 children = SYSCTL_CHILDREN(oid); 8028 8029 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", 8030 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 8031 sysctl_linkdnrc, "A", "reason why link is down"); 8032 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 8033 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 8034 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 8035 sysctl_btphy, "I", "PHY temperature (in Celsius)"); 8036 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 8037 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1, 8038 sysctl_btphy, "I", "PHY firmware version"); 8039 } 8040 8041 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 8042 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8043 sysctl_pause_settings, "A", 8044 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 8045 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec", 8046 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A", 8047 "FEC in use on the link"); 8048 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec", 8049 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8050 sysctl_requested_fec, "A", 8051 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)"); 8052 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec", 8053 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A", 8054 "FEC recommended by the cable/transceiver"); 8055 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 8056 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8057 sysctl_autoneg, "I", 8058 "autonegotiation (-1 = not supported)"); 8059 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec", 8060 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 8061 sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config"); 8062 8063 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD, 8064 &pi->link_cfg.requested_caps, 0, "L1 config requested by driver"); 8065 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD, 8066 &pi->link_cfg.pcaps, 0, "port capabilities"); 8067 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD, 8068 &pi->link_cfg.acaps, 0, "advertised capabilities"); 8069 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD, 8070 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities"); 8071 8072 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 8073 port_top_speed(pi), "max speed (in Gbps)"); 8074 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 8075 pi->mps_bg_map, "MPS buffer group map"); 8076 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 8077 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 8078 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_chan", CTLFLAG_RD, NULL, 8079 pi->tx_chan, "TP tx c-channel"); 8080 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_chan", CTLFLAG_RD, NULL, 8081 pi->rx_chan, "TP rx c-channel"); 8082 8083 if (sc->flags & IS_VF) 8084 return; 8085 8086 /* 8087 * dev.(cxgbe|cxl).X.tc. 8088 */ 8089 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", 8090 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 8091 "Tx scheduler traffic classes (cl_rl)"); 8092 children2 = SYSCTL_CHILDREN(oid); 8093 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 8094 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 8095 "pktsize for per-flow cl-rl (0 means up to the driver )"); 8096 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 8097 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 8098 "burstsize for per-flow cl-rl (0 means up to the driver)"); 8099 for (i = 0; i < sc->params.nsched_cls; i++) { 8100 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 8101 8102 snprintf(name, sizeof(name), "%d", i); 8103 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 8104 SYSCTL_CHILDREN(oid), OID_AUTO, name, 8105 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class")); 8106 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state", 8107 CTLFLAG_RD, &tc->state, 0, "current state"); 8108 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 8109 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags, 8110 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags"); 8111 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 8112 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 8113 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 8114 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 8115 (pi->port_id << 16) | i, sysctl_tc_params, "A", 8116 "traffic class parameters"); 8117 } 8118 8119 /* 8120 * dev.cxgbe.X.stats. 8121 */ 8122 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 8123 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics"); 8124 children = SYSCTL_CHILDREN(oid); 8125 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 8126 &pi->tx_parse_error, 0, 8127 "# of tx packets with invalid length or # of segments"); 8128 8129 #define T4_REGSTAT(name, stat, desc) \ 8130 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \ 8131 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \ 8132 t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \ 8133 sysctl_handle_t4_reg64, "QU", desc) 8134 8135 /* We get these from port_stats and they may be stale by up to 1s */ 8136 #define T4_PORTSTAT(name, desc) \ 8137 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 8138 &pi->stats.name, desc) 8139 8140 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames"); 8141 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames"); 8142 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames"); 8143 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames"); 8144 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames"); 8145 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames"); 8146 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range"); 8147 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range"); 8148 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range"); 8149 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range"); 8150 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range"); 8151 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range"); 8152 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range"); 8153 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames"); 8154 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted"); 8155 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted"); 8156 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted"); 8157 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted"); 8158 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted"); 8159 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted"); 8160 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted"); 8161 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted"); 8162 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted"); 8163 8164 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames"); 8165 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames"); 8166 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames"); 8167 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames"); 8168 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames"); 8169 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU"); 8170 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames"); 8171 if (is_t6(sc)) { 8172 T4_PORTSTAT(rx_fcs_err, 8173 "# of frames received with bad FCS since last link up"); 8174 } else { 8175 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR, 8176 "# of frames received with bad FCS"); 8177 } 8178 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error"); 8179 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors"); 8180 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received"); 8181 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range"); 8182 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range"); 8183 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range"); 8184 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range"); 8185 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range"); 8186 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range"); 8187 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range"); 8188 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received"); 8189 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received"); 8190 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received"); 8191 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received"); 8192 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received"); 8193 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received"); 8194 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received"); 8195 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received"); 8196 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received"); 8197 8198 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows"); 8199 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows"); 8200 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows"); 8201 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows"); 8202 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets"); 8203 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets"); 8204 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets"); 8205 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets"); 8206 8207 #undef T4_REGSTAT 8208 #undef T4_PORTSTAT 8209 } 8210 8211 static int 8212 sysctl_int_array(SYSCTL_HANDLER_ARGS) 8213 { 8214 int rc, *i, space = 0; 8215 struct sbuf sb; 8216 8217 sbuf_new_for_sysctl(&sb, NULL, 64, req); 8218 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 8219 if (space) 8220 sbuf_printf(&sb, " "); 8221 sbuf_printf(&sb, "%d", *i); 8222 space = 1; 8223 } 8224 rc = sbuf_finish(&sb); 8225 sbuf_delete(&sb); 8226 return (rc); 8227 } 8228 8229 static int 8230 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 8231 { 8232 int rc; 8233 struct sbuf *sb; 8234 8235 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8236 if (sb == NULL) 8237 return (ENOMEM); 8238 8239 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 8240 rc = sbuf_finish(sb); 8241 sbuf_delete(sb); 8242 8243 return (rc); 8244 } 8245 8246 static int 8247 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 8248 { 8249 int rc; 8250 struct sbuf *sb; 8251 8252 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8253 if (sb == NULL) 8254 return (ENOMEM); 8255 8256 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 8257 rc = sbuf_finish(sb); 8258 sbuf_delete(sb); 8259 8260 return (rc); 8261 } 8262 8263 static int 8264 sysctl_btphy(SYSCTL_HANDLER_ARGS) 8265 { 8266 struct port_info *pi = arg1; 8267 int op = arg2; 8268 struct adapter *sc = pi->adapter; 8269 u_int v; 8270 int rc; 8271 8272 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 8273 if (rc) 8274 return (rc); 8275 if (hw_off_limits(sc)) 8276 rc = ENXIO; 8277 else { 8278 /* XXX: magic numbers */ 8279 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, 8280 op ? 0x20 : 0xc820, &v); 8281 } 8282 end_synchronized_op(sc, 0); 8283 if (rc) 8284 return (rc); 8285 if (op == 0) 8286 v /= 256; 8287 8288 rc = sysctl_handle_int(oidp, &v, 0, req); 8289 return (rc); 8290 } 8291 8292 static int 8293 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 8294 { 8295 struct vi_info *vi = arg1; 8296 int rc, val; 8297 8298 val = vi->rsrv_noflowq; 8299 rc = sysctl_handle_int(oidp, &val, 0, req); 8300 if (rc != 0 || req->newptr == NULL) 8301 return (rc); 8302 8303 if ((val >= 1) && (vi->ntxq > 1)) 8304 vi->rsrv_noflowq = 1; 8305 else 8306 vi->rsrv_noflowq = 0; 8307 8308 return (rc); 8309 } 8310 8311 static int 8312 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS) 8313 { 8314 struct vi_info *vi = arg1; 8315 struct adapter *sc = vi->adapter; 8316 int rc, val, i; 8317 8318 MPASS(!(sc->flags & IS_VF)); 8319 8320 val = vi->flags & TX_USES_VM_WR ? 1 : 0; 8321 rc = sysctl_handle_int(oidp, &val, 0, req); 8322 if (rc != 0 || req->newptr == NULL) 8323 return (rc); 8324 8325 if (val != 0 && val != 1) 8326 return (EINVAL); 8327 8328 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8329 "t4txvm"); 8330 if (rc) 8331 return (rc); 8332 if (hw_off_limits(sc)) 8333 rc = ENXIO; 8334 else if (if_getdrvflags(vi->ifp) & IFF_DRV_RUNNING) { 8335 /* 8336 * We don't want parse_pkt to run with one setting (VF or PF) 8337 * and then eth_tx to see a different setting but still use 8338 * stale information calculated by parse_pkt. 8339 */ 8340 rc = EBUSY; 8341 } else { 8342 struct port_info *pi = vi->pi; 8343 struct sge_txq *txq; 8344 uint32_t ctrl0; 8345 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr; 8346 8347 if (val) { 8348 vi->flags |= TX_USES_VM_WR; 8349 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO); 8350 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8351 V_TXPKT_INTF(pi->tx_chan)); 8352 if (!(sc->flags & IS_VF)) 8353 npkt--; 8354 } else { 8355 vi->flags &= ~TX_USES_VM_WR; 8356 if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO); 8357 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8358 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 8359 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 8360 } 8361 for_each_txq(vi, i, txq) { 8362 txq->cpl_ctrl0 = ctrl0; 8363 txq->txp.max_npkt = npkt; 8364 } 8365 } 8366 end_synchronized_op(sc, LOCK_HELD); 8367 return (rc); 8368 } 8369 8370 static int 8371 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 8372 { 8373 struct vi_info *vi = arg1; 8374 struct adapter *sc = vi->adapter; 8375 int idx, rc, i; 8376 struct sge_rxq *rxq; 8377 uint8_t v; 8378 8379 idx = vi->tmr_idx; 8380 8381 rc = sysctl_handle_int(oidp, &idx, 0, req); 8382 if (rc != 0 || req->newptr == NULL) 8383 return (rc); 8384 8385 if (idx < 0 || idx >= SGE_NTIMERS) 8386 return (EINVAL); 8387 8388 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8389 "t4tmr"); 8390 if (rc) 8391 return (rc); 8392 8393 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 8394 for_each_rxq(vi, i, rxq) { 8395 #ifdef atomic_store_rel_8 8396 atomic_store_rel_8(&rxq->iq.intr_params, v); 8397 #else 8398 rxq->iq.intr_params = v; 8399 #endif 8400 } 8401 vi->tmr_idx = idx; 8402 8403 end_synchronized_op(sc, LOCK_HELD); 8404 return (0); 8405 } 8406 8407 static int 8408 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 8409 { 8410 struct vi_info *vi = arg1; 8411 struct adapter *sc = vi->adapter; 8412 int idx, rc; 8413 8414 idx = vi->pktc_idx; 8415 8416 rc = sysctl_handle_int(oidp, &idx, 0, req); 8417 if (rc != 0 || req->newptr == NULL) 8418 return (rc); 8419 8420 if (idx < -1 || idx >= SGE_NCOUNTERS) 8421 return (EINVAL); 8422 8423 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8424 "t4pktc"); 8425 if (rc) 8426 return (rc); 8427 8428 if (vi->flags & VI_INIT_DONE) 8429 rc = EBUSY; /* cannot be changed once the queues are created */ 8430 else 8431 vi->pktc_idx = idx; 8432 8433 end_synchronized_op(sc, LOCK_HELD); 8434 return (rc); 8435 } 8436 8437 static int 8438 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 8439 { 8440 struct vi_info *vi = arg1; 8441 struct adapter *sc = vi->adapter; 8442 int qsize, rc; 8443 8444 qsize = vi->qsize_rxq; 8445 8446 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8447 if (rc != 0 || req->newptr == NULL) 8448 return (rc); 8449 8450 if (qsize < 128 || (qsize & 7)) 8451 return (EINVAL); 8452 8453 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8454 "t4rxqs"); 8455 if (rc) 8456 return (rc); 8457 8458 if (vi->flags & VI_INIT_DONE) 8459 rc = EBUSY; /* cannot be changed once the queues are created */ 8460 else 8461 vi->qsize_rxq = qsize; 8462 8463 end_synchronized_op(sc, LOCK_HELD); 8464 return (rc); 8465 } 8466 8467 static int 8468 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 8469 { 8470 struct vi_info *vi = arg1; 8471 struct adapter *sc = vi->adapter; 8472 int qsize, rc; 8473 8474 qsize = vi->qsize_txq; 8475 8476 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8477 if (rc != 0 || req->newptr == NULL) 8478 return (rc); 8479 8480 if (qsize < 128 || qsize > 65536) 8481 return (EINVAL); 8482 8483 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8484 "t4txqs"); 8485 if (rc) 8486 return (rc); 8487 8488 if (vi->flags & VI_INIT_DONE) 8489 rc = EBUSY; /* cannot be changed once the queues are created */ 8490 else 8491 vi->qsize_txq = qsize; 8492 8493 end_synchronized_op(sc, LOCK_HELD); 8494 return (rc); 8495 } 8496 8497 static int 8498 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 8499 { 8500 struct port_info *pi = arg1; 8501 struct adapter *sc = pi->adapter; 8502 struct link_config *lc = &pi->link_cfg; 8503 int rc; 8504 8505 if (req->newptr == NULL) { 8506 struct sbuf *sb; 8507 static char *bits = "\20\1RX\2TX\3AUTO"; 8508 8509 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8510 if (sb == NULL) 8511 return (ENOMEM); 8512 8513 if (lc->link_ok) { 8514 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 8515 (lc->requested_fc & PAUSE_AUTONEG), bits); 8516 } else { 8517 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 8518 PAUSE_RX | PAUSE_AUTONEG), bits); 8519 } 8520 rc = sbuf_finish(sb); 8521 sbuf_delete(sb); 8522 } else { 8523 char s[2]; 8524 int n; 8525 8526 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 8527 PAUSE_AUTONEG)); 8528 s[1] = 0; 8529 8530 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8531 if (rc != 0) 8532 return(rc); 8533 8534 if (s[1] != 0) 8535 return (EINVAL); 8536 if (s[0] < '0' || s[0] > '9') 8537 return (EINVAL); /* not a number */ 8538 n = s[0] - '0'; 8539 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 8540 return (EINVAL); /* some other bit is set too */ 8541 8542 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8543 "t4PAUSE"); 8544 if (rc) 8545 return (rc); 8546 if (!hw_off_limits(sc)) { 8547 PORT_LOCK(pi); 8548 lc->requested_fc = n; 8549 fixup_link_config(pi); 8550 if (pi->up_vis > 0) 8551 rc = apply_link_config(pi); 8552 set_current_media(pi); 8553 PORT_UNLOCK(pi); 8554 } 8555 end_synchronized_op(sc, 0); 8556 } 8557 8558 return (rc); 8559 } 8560 8561 static int 8562 sysctl_link_fec(SYSCTL_HANDLER_ARGS) 8563 { 8564 struct port_info *pi = arg1; 8565 struct link_config *lc = &pi->link_cfg; 8566 int rc; 8567 struct sbuf *sb; 8568 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2"; 8569 8570 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8571 if (sb == NULL) 8572 return (ENOMEM); 8573 if (lc->link_ok) 8574 sbuf_printf(sb, "%b", lc->fec, bits); 8575 else 8576 sbuf_printf(sb, "no link"); 8577 rc = sbuf_finish(sb); 8578 sbuf_delete(sb); 8579 8580 return (rc); 8581 } 8582 8583 static int 8584 sysctl_requested_fec(SYSCTL_HANDLER_ARGS) 8585 { 8586 struct port_info *pi = arg1; 8587 struct adapter *sc = pi->adapter; 8588 struct link_config *lc = &pi->link_cfg; 8589 int rc; 8590 int8_t old; 8591 8592 if (req->newptr == NULL) { 8593 struct sbuf *sb; 8594 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2" 8595 "\5RSVD3\6auto\7module"; 8596 8597 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8598 if (sb == NULL) 8599 return (ENOMEM); 8600 8601 sbuf_printf(sb, "%b", lc->requested_fec, bits); 8602 rc = sbuf_finish(sb); 8603 sbuf_delete(sb); 8604 } else { 8605 char s[8]; 8606 int n; 8607 8608 snprintf(s, sizeof(s), "%d", 8609 lc->requested_fec == FEC_AUTO ? -1 : 8610 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE)); 8611 8612 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8613 if (rc != 0) 8614 return(rc); 8615 8616 n = strtol(&s[0], NULL, 0); 8617 if (n < 0 || n & FEC_AUTO) 8618 n = FEC_AUTO; 8619 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE)) 8620 return (EINVAL);/* some other bit is set too */ 8621 8622 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8623 "t4reqf"); 8624 if (rc) 8625 return (rc); 8626 PORT_LOCK(pi); 8627 old = lc->requested_fec; 8628 if (n == FEC_AUTO) 8629 lc->requested_fec = FEC_AUTO; 8630 else if (n == 0 || n == FEC_NONE) 8631 lc->requested_fec = FEC_NONE; 8632 else { 8633 if ((lc->pcaps | 8634 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) != 8635 lc->pcaps) { 8636 rc = ENOTSUP; 8637 goto done; 8638 } 8639 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC | 8640 FEC_MODULE); 8641 } 8642 if (!hw_off_limits(sc)) { 8643 fixup_link_config(pi); 8644 if (pi->up_vis > 0) { 8645 rc = apply_link_config(pi); 8646 if (rc != 0) { 8647 lc->requested_fec = old; 8648 if (rc == FW_EPROTO) 8649 rc = ENOTSUP; 8650 } 8651 } 8652 } 8653 done: 8654 PORT_UNLOCK(pi); 8655 end_synchronized_op(sc, 0); 8656 } 8657 8658 return (rc); 8659 } 8660 8661 static int 8662 sysctl_module_fec(SYSCTL_HANDLER_ARGS) 8663 { 8664 struct port_info *pi = arg1; 8665 struct adapter *sc = pi->adapter; 8666 struct link_config *lc = &pi->link_cfg; 8667 int rc; 8668 int8_t fec; 8669 struct sbuf *sb; 8670 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3"; 8671 8672 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8673 if (sb == NULL) 8674 return (ENOMEM); 8675 8676 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) { 8677 rc = EBUSY; 8678 goto done; 8679 } 8680 if (hw_off_limits(sc)) { 8681 rc = ENXIO; 8682 goto done; 8683 } 8684 PORT_LOCK(pi); 8685 if (pi->up_vis == 0) { 8686 /* 8687 * If all the interfaces are administratively down the firmware 8688 * does not report transceiver changes. Refresh port info here. 8689 * This is the only reason we have a synchronized op in this 8690 * function. Just PORT_LOCK would have been enough otherwise. 8691 */ 8692 t4_update_port_info(pi); 8693 } 8694 8695 fec = lc->fec_hint; 8696 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE || 8697 !fec_supported(lc->pcaps)) { 8698 PORT_UNLOCK(pi); 8699 sbuf_printf(sb, "n/a"); 8700 } else { 8701 if (fec == 0) 8702 fec = FEC_NONE; 8703 PORT_UNLOCK(pi); 8704 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits); 8705 } 8706 rc = sbuf_finish(sb); 8707 done: 8708 sbuf_delete(sb); 8709 end_synchronized_op(sc, 0); 8710 8711 return (rc); 8712 } 8713 8714 static int 8715 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 8716 { 8717 struct port_info *pi = arg1; 8718 struct adapter *sc = pi->adapter; 8719 struct link_config *lc = &pi->link_cfg; 8720 int rc, val; 8721 8722 if (lc->pcaps & FW_PORT_CAP32_ANEG) 8723 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 8724 else 8725 val = -1; 8726 rc = sysctl_handle_int(oidp, &val, 0, req); 8727 if (rc != 0 || req->newptr == NULL) 8728 return (rc); 8729 if (val == 0) 8730 val = AUTONEG_DISABLE; 8731 else if (val == 1) 8732 val = AUTONEG_ENABLE; 8733 else 8734 val = AUTONEG_AUTO; 8735 8736 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8737 "t4aneg"); 8738 if (rc) 8739 return (rc); 8740 PORT_LOCK(pi); 8741 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 8742 rc = ENOTSUP; 8743 goto done; 8744 } 8745 lc->requested_aneg = val; 8746 if (!hw_off_limits(sc)) { 8747 fixup_link_config(pi); 8748 if (pi->up_vis > 0) 8749 rc = apply_link_config(pi); 8750 set_current_media(pi); 8751 } 8752 done: 8753 PORT_UNLOCK(pi); 8754 end_synchronized_op(sc, 0); 8755 return (rc); 8756 } 8757 8758 static int 8759 sysctl_force_fec(SYSCTL_HANDLER_ARGS) 8760 { 8761 struct port_info *pi = arg1; 8762 struct adapter *sc = pi->adapter; 8763 struct link_config *lc = &pi->link_cfg; 8764 int rc, val; 8765 8766 val = lc->force_fec; 8767 MPASS(val >= -1 && val <= 1); 8768 rc = sysctl_handle_int(oidp, &val, 0, req); 8769 if (rc != 0 || req->newptr == NULL) 8770 return (rc); 8771 if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC)) 8772 return (ENOTSUP); 8773 if (val < -1 || val > 1) 8774 return (EINVAL); 8775 8776 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff"); 8777 if (rc) 8778 return (rc); 8779 PORT_LOCK(pi); 8780 lc->force_fec = val; 8781 if (!hw_off_limits(sc)) { 8782 fixup_link_config(pi); 8783 if (pi->up_vis > 0) 8784 rc = apply_link_config(pi); 8785 } 8786 PORT_UNLOCK(pi); 8787 end_synchronized_op(sc, 0); 8788 return (rc); 8789 } 8790 8791 static int 8792 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 8793 { 8794 struct adapter *sc = arg1; 8795 int rc, reg = arg2; 8796 uint64_t val; 8797 8798 mtx_lock(&sc->reg_lock); 8799 if (hw_off_limits(sc)) 8800 rc = ENXIO; 8801 else { 8802 rc = 0; 8803 val = t4_read_reg64(sc, reg); 8804 } 8805 mtx_unlock(&sc->reg_lock); 8806 if (rc == 0) 8807 rc = sysctl_handle_64(oidp, &val, 0, req); 8808 return (rc); 8809 } 8810 8811 static int 8812 sysctl_temperature(SYSCTL_HANDLER_ARGS) 8813 { 8814 struct adapter *sc = arg1; 8815 int rc, t; 8816 uint32_t param, val; 8817 8818 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 8819 if (rc) 8820 return (rc); 8821 if (hw_off_limits(sc)) 8822 rc = ENXIO; 8823 else { 8824 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8825 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8826 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 8827 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8828 } 8829 end_synchronized_op(sc, 0); 8830 if (rc) 8831 return (rc); 8832 8833 /* unknown is returned as 0 but we display -1 in that case */ 8834 t = val == 0 ? -1 : val; 8835 8836 rc = sysctl_handle_int(oidp, &t, 0, req); 8837 return (rc); 8838 } 8839 8840 static int 8841 sysctl_vdd(SYSCTL_HANDLER_ARGS) 8842 { 8843 struct adapter *sc = arg1; 8844 int rc; 8845 uint32_t param, val; 8846 8847 if (sc->params.core_vdd == 0) { 8848 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8849 "t4vdd"); 8850 if (rc) 8851 return (rc); 8852 if (hw_off_limits(sc)) 8853 rc = ENXIO; 8854 else { 8855 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8856 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8857 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 8858 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, 8859 ¶m, &val); 8860 } 8861 end_synchronized_op(sc, 0); 8862 if (rc) 8863 return (rc); 8864 sc->params.core_vdd = val; 8865 } 8866 8867 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req)); 8868 } 8869 8870 static int 8871 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS) 8872 { 8873 struct adapter *sc = arg1; 8874 int rc, v; 8875 uint32_t param, val; 8876 8877 v = sc->sensor_resets; 8878 rc = sysctl_handle_int(oidp, &v, 0, req); 8879 if (rc != 0 || req->newptr == NULL || v <= 0) 8880 return (rc); 8881 8882 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) || 8883 chip_id(sc) < CHELSIO_T5) 8884 return (ENOTSUP); 8885 8886 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst"); 8887 if (rc) 8888 return (rc); 8889 if (hw_off_limits(sc)) 8890 rc = ENXIO; 8891 else { 8892 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8893 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8894 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR)); 8895 val = 1; 8896 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8897 } 8898 end_synchronized_op(sc, 0); 8899 if (rc == 0) 8900 sc->sensor_resets++; 8901 return (rc); 8902 } 8903 8904 static int 8905 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 8906 { 8907 struct adapter *sc = arg1; 8908 struct sbuf *sb; 8909 int rc; 8910 uint32_t param, val; 8911 8912 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 8913 if (rc) 8914 return (rc); 8915 if (hw_off_limits(sc)) 8916 rc = ENXIO; 8917 else { 8918 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8919 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 8920 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8921 } 8922 end_synchronized_op(sc, 0); 8923 if (rc) 8924 return (rc); 8925 8926 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8927 if (sb == NULL) 8928 return (ENOMEM); 8929 8930 if (val == 0xffffffff) { 8931 /* Only debug and custom firmwares report load averages. */ 8932 sbuf_printf(sb, "not available"); 8933 } else { 8934 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 8935 (val >> 16) & 0xff); 8936 } 8937 rc = sbuf_finish(sb); 8938 sbuf_delete(sb); 8939 8940 return (rc); 8941 } 8942 8943 static int 8944 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 8945 { 8946 struct adapter *sc = arg1; 8947 struct sbuf *sb; 8948 int rc, i; 8949 uint16_t incr[NMTUS][NCCTRL_WIN]; 8950 static const char *dec_fac[] = { 8951 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 8952 "0.9375" 8953 }; 8954 8955 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8956 if (sb == NULL) 8957 return (ENOMEM); 8958 8959 rc = 0; 8960 mtx_lock(&sc->reg_lock); 8961 if (hw_off_limits(sc)) 8962 rc = ENXIO; 8963 else 8964 t4_read_cong_tbl(sc, incr); 8965 mtx_unlock(&sc->reg_lock); 8966 if (rc) 8967 goto done; 8968 8969 for (i = 0; i < NCCTRL_WIN; ++i) { 8970 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 8971 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 8972 incr[5][i], incr[6][i], incr[7][i]); 8973 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 8974 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 8975 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 8976 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 8977 } 8978 8979 rc = sbuf_finish(sb); 8980 done: 8981 sbuf_delete(sb); 8982 return (rc); 8983 } 8984 8985 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 8986 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 8987 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 8988 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 8989 }; 8990 8991 static int 8992 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 8993 { 8994 struct adapter *sc = arg1; 8995 struct sbuf *sb; 8996 int rc, i, n, qid = arg2; 8997 uint32_t *buf, *p; 8998 char *qtype; 8999 u_int cim_num_obq = sc->chip_params->cim_num_obq; 9000 9001 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 9002 ("%s: bad qid %d\n", __func__, qid)); 9003 9004 if (qid < CIM_NUM_IBQ) { 9005 /* inbound queue */ 9006 qtype = "IBQ"; 9007 n = 4 * CIM_IBQ_SIZE; 9008 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 9009 mtx_lock(&sc->reg_lock); 9010 if (hw_off_limits(sc)) 9011 rc = -ENXIO; 9012 else 9013 rc = t4_read_cim_ibq(sc, qid, buf, n); 9014 mtx_unlock(&sc->reg_lock); 9015 } else { 9016 /* outbound queue */ 9017 qtype = "OBQ"; 9018 qid -= CIM_NUM_IBQ; 9019 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 9020 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 9021 mtx_lock(&sc->reg_lock); 9022 if (hw_off_limits(sc)) 9023 rc = -ENXIO; 9024 else 9025 rc = t4_read_cim_obq(sc, qid, buf, n); 9026 mtx_unlock(&sc->reg_lock); 9027 } 9028 9029 if (rc < 0) { 9030 rc = -rc; 9031 goto done; 9032 } 9033 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 9034 9035 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9036 if (sb == NULL) { 9037 rc = ENOMEM; 9038 goto done; 9039 } 9040 9041 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 9042 for (i = 0, p = buf; i < n; i += 16, p += 4) 9043 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 9044 p[2], p[3]); 9045 9046 rc = sbuf_finish(sb); 9047 sbuf_delete(sb); 9048 done: 9049 free(buf, M_CXGBE); 9050 return (rc); 9051 } 9052 9053 static void 9054 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9055 { 9056 uint32_t *p; 9057 9058 sbuf_printf(sb, "Status Data PC%s", 9059 cfg & F_UPDBGLACAPTPCONLY ? "" : 9060 " LS0Stat LS0Addr LS0Data"); 9061 9062 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 9063 if (cfg & F_UPDBGLACAPTPCONLY) { 9064 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 9065 p[6], p[7]); 9066 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 9067 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 9068 p[4] & 0xff, p[5] >> 8); 9069 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 9070 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9071 p[1] & 0xf, p[2] >> 4); 9072 } else { 9073 sbuf_printf(sb, 9074 "\n %02x %x%07x %x%07x %08x %08x " 9075 "%08x%08x%08x%08x", 9076 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 9077 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 9078 p[6], p[7]); 9079 } 9080 } 9081 } 9082 9083 static void 9084 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9085 { 9086 uint32_t *p; 9087 9088 sbuf_printf(sb, "Status Inst Data PC%s", 9089 cfg & F_UPDBGLACAPTPCONLY ? "" : 9090 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 9091 9092 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 9093 if (cfg & F_UPDBGLACAPTPCONLY) { 9094 sbuf_printf(sb, "\n %02x %08x %08x %08x", 9095 p[3] & 0xff, p[2], p[1], p[0]); 9096 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 9097 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 9098 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 9099 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 9100 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 9101 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 9102 p[6] >> 16); 9103 } else { 9104 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 9105 "%08x %08x %08x %08x %08x %08x", 9106 (p[9] >> 16) & 0xff, 9107 p[9] & 0xffff, p[8] >> 16, 9108 p[8] & 0xffff, p[7] >> 16, 9109 p[7] & 0xffff, p[6] >> 16, 9110 p[2], p[1], p[0], p[5], p[4], p[3]); 9111 } 9112 } 9113 } 9114 9115 static int 9116 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 9117 { 9118 uint32_t cfg, *buf; 9119 int rc; 9120 9121 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9122 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 9123 M_ZERO | flags); 9124 if (buf == NULL) 9125 return (ENOMEM); 9126 9127 mtx_lock(&sc->reg_lock); 9128 if (hw_off_limits(sc)) 9129 rc = ENXIO; 9130 else { 9131 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9132 if (rc == 0) 9133 rc = -t4_cim_read_la(sc, buf, NULL); 9134 } 9135 mtx_unlock(&sc->reg_lock); 9136 if (rc == 0) { 9137 if (chip_id(sc) < CHELSIO_T6) 9138 sbuf_cim_la4(sc, sb, buf, cfg); 9139 else 9140 sbuf_cim_la6(sc, sb, buf, cfg); 9141 } 9142 free(buf, M_CXGBE); 9143 return (rc); 9144 } 9145 9146 static int 9147 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 9148 { 9149 struct adapter *sc = arg1; 9150 struct sbuf *sb; 9151 int rc; 9152 9153 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9154 if (sb == NULL) 9155 return (ENOMEM); 9156 9157 rc = sbuf_cim_la(sc, sb, M_WAITOK); 9158 if (rc == 0) 9159 rc = sbuf_finish(sb); 9160 sbuf_delete(sb); 9161 return (rc); 9162 } 9163 9164 static void 9165 dump_cim_regs(struct adapter *sc) 9166 { 9167 log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n", 9168 device_get_nameunit(sc->dev), 9169 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9170 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9171 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2), 9172 t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN), 9173 t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA)); 9174 log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n", 9175 device_get_nameunit(sc->dev), 9176 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9177 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9178 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800), 9179 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800), 9180 t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN)); 9181 } 9182 9183 static void 9184 dump_cimla(struct adapter *sc) 9185 { 9186 struct sbuf sb; 9187 int rc; 9188 9189 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9190 log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n", 9191 device_get_nameunit(sc->dev)); 9192 return; 9193 } 9194 rc = sbuf_cim_la(sc, &sb, M_WAITOK); 9195 if (rc == 0) { 9196 rc = sbuf_finish(&sb); 9197 if (rc == 0) { 9198 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n", 9199 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9200 } 9201 } 9202 sbuf_delete(&sb); 9203 } 9204 9205 void 9206 t4_os_cim_err(struct adapter *sc) 9207 { 9208 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 9209 } 9210 9211 static int 9212 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 9213 { 9214 struct adapter *sc = arg1; 9215 u_int i; 9216 struct sbuf *sb; 9217 uint32_t *buf, *p; 9218 int rc; 9219 9220 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9221 if (sb == NULL) 9222 return (ENOMEM); 9223 9224 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 9225 M_ZERO | M_WAITOK); 9226 9227 rc = 0; 9228 mtx_lock(&sc->reg_lock); 9229 if (hw_off_limits(sc)) 9230 rc = ENXIO; 9231 else 9232 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 9233 mtx_unlock(&sc->reg_lock); 9234 if (rc) 9235 goto done; 9236 9237 p = buf; 9238 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9239 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 9240 p[1], p[0]); 9241 } 9242 9243 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 9244 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9245 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 9246 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 9247 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 9248 (p[1] >> 2) | ((p[2] & 3) << 30), 9249 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 9250 p[0] & 1); 9251 } 9252 rc = sbuf_finish(sb); 9253 done: 9254 sbuf_delete(sb); 9255 free(buf, M_CXGBE); 9256 return (rc); 9257 } 9258 9259 static int 9260 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 9261 { 9262 struct adapter *sc = arg1; 9263 u_int i; 9264 struct sbuf *sb; 9265 uint32_t *buf, *p; 9266 int rc; 9267 9268 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9269 if (sb == NULL) 9270 return (ENOMEM); 9271 9272 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 9273 M_ZERO | M_WAITOK); 9274 9275 rc = 0; 9276 mtx_lock(&sc->reg_lock); 9277 if (hw_off_limits(sc)) 9278 rc = ENXIO; 9279 else 9280 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 9281 mtx_unlock(&sc->reg_lock); 9282 if (rc) 9283 goto done; 9284 9285 p = buf; 9286 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 9287 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9288 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 9289 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 9290 p[4], p[3], p[2], p[1], p[0]); 9291 } 9292 9293 sbuf_printf(sb, "\n\nCntl ID Data"); 9294 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9295 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 9296 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 9297 } 9298 9299 rc = sbuf_finish(sb); 9300 done: 9301 sbuf_delete(sb); 9302 free(buf, M_CXGBE); 9303 return (rc); 9304 } 9305 9306 static int 9307 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 9308 { 9309 struct adapter *sc = arg1; 9310 struct sbuf *sb; 9311 int rc, i; 9312 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9313 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9314 uint16_t thres[CIM_NUM_IBQ]; 9315 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 9316 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 9317 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 9318 9319 cim_num_obq = sc->chip_params->cim_num_obq; 9320 if (is_t4(sc)) { 9321 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 9322 obq_rdaddr = A_UP_OBQ_0_REALADDR; 9323 } else { 9324 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 9325 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 9326 } 9327 nq = CIM_NUM_IBQ + cim_num_obq; 9328 9329 mtx_lock(&sc->reg_lock); 9330 if (hw_off_limits(sc)) 9331 rc = ENXIO; 9332 else { 9333 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 9334 if (rc == 0) { 9335 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, 9336 obq_wr); 9337 if (rc == 0) 9338 t4_read_cimq_cfg(sc, base, size, thres); 9339 } 9340 } 9341 mtx_unlock(&sc->reg_lock); 9342 if (rc) 9343 return (rc); 9344 9345 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9346 if (sb == NULL) 9347 return (ENOMEM); 9348 9349 sbuf_printf(sb, 9350 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 9351 9352 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 9353 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 9354 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 9355 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9356 G_QUEREMFLITS(p[2]) * 16); 9357 for ( ; i < nq; i++, p += 4, wr += 2) 9358 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 9359 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 9360 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9361 G_QUEREMFLITS(p[2]) * 16); 9362 9363 rc = sbuf_finish(sb); 9364 sbuf_delete(sb); 9365 9366 return (rc); 9367 } 9368 9369 static int 9370 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 9371 { 9372 struct adapter *sc = arg1; 9373 struct sbuf *sb; 9374 int rc; 9375 struct tp_cpl_stats stats; 9376 9377 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9378 if (sb == NULL) 9379 return (ENOMEM); 9380 9381 rc = 0; 9382 mtx_lock(&sc->reg_lock); 9383 if (hw_off_limits(sc)) 9384 rc = ENXIO; 9385 else 9386 t4_tp_get_cpl_stats(sc, &stats, 0); 9387 mtx_unlock(&sc->reg_lock); 9388 if (rc) 9389 goto done; 9390 9391 if (sc->chip_params->nchan > 2) { 9392 sbuf_printf(sb, " channel 0 channel 1" 9393 " channel 2 channel 3"); 9394 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 9395 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 9396 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 9397 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 9398 } else { 9399 sbuf_printf(sb, " channel 0 channel 1"); 9400 sbuf_printf(sb, "\nCPL requests: %10u %10u", 9401 stats.req[0], stats.req[1]); 9402 sbuf_printf(sb, "\nCPL responses: %10u %10u", 9403 stats.rsp[0], stats.rsp[1]); 9404 } 9405 9406 rc = sbuf_finish(sb); 9407 done: 9408 sbuf_delete(sb); 9409 return (rc); 9410 } 9411 9412 static int 9413 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 9414 { 9415 struct adapter *sc = arg1; 9416 struct sbuf *sb; 9417 int rc; 9418 struct tp_usm_stats stats; 9419 9420 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9421 if (sb == NULL) 9422 return (ENOMEM); 9423 9424 rc = 0; 9425 mtx_lock(&sc->reg_lock); 9426 if (hw_off_limits(sc)) 9427 rc = ENXIO; 9428 else 9429 t4_get_usm_stats(sc, &stats, 1); 9430 mtx_unlock(&sc->reg_lock); 9431 if (rc == 0) { 9432 sbuf_printf(sb, "Frames: %u\n", stats.frames); 9433 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 9434 sbuf_printf(sb, "Drops: %u", stats.drops); 9435 rc = sbuf_finish(sb); 9436 } 9437 sbuf_delete(sb); 9438 9439 return (rc); 9440 } 9441 9442 static int 9443 sysctl_tid_stats(SYSCTL_HANDLER_ARGS) 9444 { 9445 struct adapter *sc = arg1; 9446 struct sbuf *sb; 9447 int rc; 9448 struct tp_tid_stats stats; 9449 9450 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9451 if (sb == NULL) 9452 return (ENOMEM); 9453 9454 rc = 0; 9455 mtx_lock(&sc->reg_lock); 9456 if (hw_off_limits(sc)) 9457 rc = ENXIO; 9458 else 9459 t4_tp_get_tid_stats(sc, &stats, 1); 9460 mtx_unlock(&sc->reg_lock); 9461 if (rc == 0) { 9462 sbuf_printf(sb, "Delete: %u\n", stats.del); 9463 sbuf_printf(sb, "Invalidate: %u\n", stats.inv); 9464 sbuf_printf(sb, "Active: %u\n", stats.act); 9465 sbuf_printf(sb, "Passive: %u", stats.pas); 9466 rc = sbuf_finish(sb); 9467 } 9468 sbuf_delete(sb); 9469 9470 return (rc); 9471 } 9472 9473 static const char * const devlog_level_strings[] = { 9474 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 9475 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 9476 [FW_DEVLOG_LEVEL_ERR] = "ERR", 9477 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 9478 [FW_DEVLOG_LEVEL_INFO] = "INFO", 9479 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 9480 }; 9481 9482 static const char * const devlog_facility_strings[] = { 9483 [FW_DEVLOG_FACILITY_CORE] = "CORE", 9484 [FW_DEVLOG_FACILITY_CF] = "CF", 9485 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 9486 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 9487 [FW_DEVLOG_FACILITY_RES] = "RES", 9488 [FW_DEVLOG_FACILITY_HW] = "HW", 9489 [FW_DEVLOG_FACILITY_FLR] = "FLR", 9490 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 9491 [FW_DEVLOG_FACILITY_PHY] = "PHY", 9492 [FW_DEVLOG_FACILITY_MAC] = "MAC", 9493 [FW_DEVLOG_FACILITY_PORT] = "PORT", 9494 [FW_DEVLOG_FACILITY_VI] = "VI", 9495 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 9496 [FW_DEVLOG_FACILITY_ACL] = "ACL", 9497 [FW_DEVLOG_FACILITY_TM] = "TM", 9498 [FW_DEVLOG_FACILITY_QFC] = "QFC", 9499 [FW_DEVLOG_FACILITY_DCB] = "DCB", 9500 [FW_DEVLOG_FACILITY_ETH] = "ETH", 9501 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 9502 [FW_DEVLOG_FACILITY_RI] = "RI", 9503 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 9504 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 9505 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 9506 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 9507 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 9508 }; 9509 9510 static int 9511 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 9512 { 9513 int i, j, rc, nentries, first = 0; 9514 struct devlog_params *dparams = &sc->params.devlog; 9515 struct fw_devlog_e *buf, *e; 9516 uint64_t ftstamp = UINT64_MAX; 9517 9518 if (dparams->addr == 0) 9519 return (ENXIO); 9520 9521 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9522 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 9523 if (buf == NULL) 9524 return (ENOMEM); 9525 9526 mtx_lock(&sc->reg_lock); 9527 if (hw_off_limits(sc)) 9528 rc = ENXIO; 9529 else 9530 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, 9531 dparams->size); 9532 mtx_unlock(&sc->reg_lock); 9533 if (rc != 0) 9534 goto done; 9535 9536 nentries = dparams->size / sizeof(struct fw_devlog_e); 9537 for (i = 0; i < nentries; i++) { 9538 e = &buf[i]; 9539 9540 if (e->timestamp == 0) 9541 break; /* end */ 9542 9543 e->timestamp = be64toh(e->timestamp); 9544 e->seqno = be32toh(e->seqno); 9545 for (j = 0; j < 8; j++) 9546 e->params[j] = be32toh(e->params[j]); 9547 9548 if (e->timestamp < ftstamp) { 9549 ftstamp = e->timestamp; 9550 first = i; 9551 } 9552 } 9553 9554 if (buf[first].timestamp == 0) 9555 goto done; /* nothing in the log */ 9556 9557 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 9558 "Seq#", "Tstamp", "Level", "Facility", "Message"); 9559 9560 i = first; 9561 do { 9562 e = &buf[i]; 9563 if (e->timestamp == 0) 9564 break; /* end */ 9565 9566 sbuf_printf(sb, "%10d %15ju %8s %8s ", 9567 e->seqno, e->timestamp, 9568 (e->level < nitems(devlog_level_strings) ? 9569 devlog_level_strings[e->level] : "UNKNOWN"), 9570 (e->facility < nitems(devlog_facility_strings) ? 9571 devlog_facility_strings[e->facility] : "UNKNOWN")); 9572 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 9573 e->params[2], e->params[3], e->params[4], 9574 e->params[5], e->params[6], e->params[7]); 9575 9576 if (++i == nentries) 9577 i = 0; 9578 } while (i != first); 9579 done: 9580 free(buf, M_CXGBE); 9581 return (rc); 9582 } 9583 9584 static int 9585 sysctl_devlog(SYSCTL_HANDLER_ARGS) 9586 { 9587 struct adapter *sc = arg1; 9588 int rc; 9589 struct sbuf *sb; 9590 9591 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9592 if (sb == NULL) 9593 return (ENOMEM); 9594 9595 rc = sbuf_devlog(sc, sb, M_WAITOK); 9596 if (rc == 0) 9597 rc = sbuf_finish(sb); 9598 sbuf_delete(sb); 9599 return (rc); 9600 } 9601 9602 static void 9603 dump_devlog(struct adapter *sc) 9604 { 9605 int rc; 9606 struct sbuf sb; 9607 9608 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9609 log(LOG_DEBUG, "%s: failed to generate devlog dump.\n", 9610 device_get_nameunit(sc->dev)); 9611 return; 9612 } 9613 rc = sbuf_devlog(sc, &sb, M_WAITOK); 9614 if (rc == 0) { 9615 rc = sbuf_finish(&sb); 9616 if (rc == 0) { 9617 log(LOG_DEBUG, "%s: device log follows.\n%s", 9618 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9619 } 9620 } 9621 sbuf_delete(&sb); 9622 } 9623 9624 static int 9625 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 9626 { 9627 struct adapter *sc = arg1; 9628 struct sbuf *sb; 9629 int rc; 9630 struct tp_fcoe_stats stats[MAX_NCHAN]; 9631 int i, nchan = sc->chip_params->nchan; 9632 9633 rc = 0; 9634 mtx_lock(&sc->reg_lock); 9635 if (hw_off_limits(sc)) 9636 rc = ENXIO; 9637 else { 9638 for (i = 0; i < nchan; i++) 9639 t4_get_fcoe_stats(sc, i, &stats[i], 1); 9640 } 9641 mtx_unlock(&sc->reg_lock); 9642 if (rc != 0) 9643 return (rc); 9644 9645 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9646 if (sb == NULL) 9647 return (ENOMEM); 9648 9649 if (nchan > 2) { 9650 sbuf_printf(sb, " channel 0 channel 1" 9651 " channel 2 channel 3"); 9652 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 9653 stats[0].octets_ddp, stats[1].octets_ddp, 9654 stats[2].octets_ddp, stats[3].octets_ddp); 9655 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 9656 stats[0].frames_ddp, stats[1].frames_ddp, 9657 stats[2].frames_ddp, stats[3].frames_ddp); 9658 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 9659 stats[0].frames_drop, stats[1].frames_drop, 9660 stats[2].frames_drop, stats[3].frames_drop); 9661 } else { 9662 sbuf_printf(sb, " channel 0 channel 1"); 9663 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 9664 stats[0].octets_ddp, stats[1].octets_ddp); 9665 sbuf_printf(sb, "\nframesDDP: %16u %16u", 9666 stats[0].frames_ddp, stats[1].frames_ddp); 9667 sbuf_printf(sb, "\nframesDrop: %16u %16u", 9668 stats[0].frames_drop, stats[1].frames_drop); 9669 } 9670 9671 rc = sbuf_finish(sb); 9672 sbuf_delete(sb); 9673 9674 return (rc); 9675 } 9676 9677 static int 9678 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 9679 { 9680 struct adapter *sc = arg1; 9681 struct sbuf *sb; 9682 int rc, i; 9683 unsigned int map, kbps, ipg, mode; 9684 unsigned int pace_tab[NTX_SCHED]; 9685 9686 sb = sbuf_new_for_sysctl(NULL, NULL, 512, req); 9687 if (sb == NULL) 9688 return (ENOMEM); 9689 9690 mtx_lock(&sc->reg_lock); 9691 if (hw_off_limits(sc)) { 9692 mtx_unlock(&sc->reg_lock); 9693 rc = ENXIO; 9694 goto done; 9695 } 9696 9697 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 9698 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 9699 t4_read_pace_tbl(sc, pace_tab); 9700 mtx_unlock(&sc->reg_lock); 9701 9702 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 9703 "Class IPG (0.1 ns) Flow IPG (us)"); 9704 9705 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 9706 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 9707 sbuf_printf(sb, "\n %u %-5s %u ", i, 9708 (mode & (1 << i)) ? "flow" : "class", map & 3); 9709 if (kbps) 9710 sbuf_printf(sb, "%9u ", kbps); 9711 else 9712 sbuf_printf(sb, " disabled "); 9713 9714 if (ipg) 9715 sbuf_printf(sb, "%13u ", ipg); 9716 else 9717 sbuf_printf(sb, " disabled "); 9718 9719 if (pace_tab[i]) 9720 sbuf_printf(sb, "%10u", pace_tab[i]); 9721 else 9722 sbuf_printf(sb, " disabled"); 9723 } 9724 rc = sbuf_finish(sb); 9725 done: 9726 sbuf_delete(sb); 9727 return (rc); 9728 } 9729 9730 static int 9731 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 9732 { 9733 struct adapter *sc = arg1; 9734 struct sbuf *sb; 9735 int rc, i, j; 9736 uint64_t *p0, *p1; 9737 struct lb_port_stats s[2]; 9738 static const char *stat_name[] = { 9739 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 9740 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 9741 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 9742 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 9743 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 9744 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 9745 "BG2FramesTrunc:", "BG3FramesTrunc:" 9746 }; 9747 9748 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9749 if (sb == NULL) 9750 return (ENOMEM); 9751 9752 memset(s, 0, sizeof(s)); 9753 9754 rc = 0; 9755 for (i = 0; i < sc->chip_params->nchan; i += 2) { 9756 mtx_lock(&sc->reg_lock); 9757 if (hw_off_limits(sc)) 9758 rc = ENXIO; 9759 else { 9760 t4_get_lb_stats(sc, i, &s[0]); 9761 t4_get_lb_stats(sc, i + 1, &s[1]); 9762 } 9763 mtx_unlock(&sc->reg_lock); 9764 if (rc != 0) 9765 break; 9766 9767 p0 = &s[0].octets; 9768 p1 = &s[1].octets; 9769 sbuf_printf(sb, "%s Loopback %u" 9770 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 9771 9772 for (j = 0; j < nitems(stat_name); j++) 9773 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 9774 *p0++, *p1++); 9775 } 9776 9777 if (rc == 0) 9778 rc = sbuf_finish(sb); 9779 sbuf_delete(sb); 9780 9781 return (rc); 9782 } 9783 9784 static int 9785 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 9786 { 9787 int rc = 0; 9788 struct port_info *pi = arg1; 9789 struct link_config *lc = &pi->link_cfg; 9790 struct sbuf *sb; 9791 9792 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 9793 if (sb == NULL) 9794 return (ENOMEM); 9795 9796 if (lc->link_ok || lc->link_down_rc == 255) 9797 sbuf_printf(sb, "n/a"); 9798 else 9799 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 9800 9801 rc = sbuf_finish(sb); 9802 sbuf_delete(sb); 9803 9804 return (rc); 9805 } 9806 9807 struct mem_desc { 9808 u_int base; 9809 u_int limit; 9810 u_int idx; 9811 }; 9812 9813 static int 9814 mem_desc_cmp(const void *a, const void *b) 9815 { 9816 const u_int v1 = ((const struct mem_desc *)a)->base; 9817 const u_int v2 = ((const struct mem_desc *)b)->base; 9818 9819 if (v1 < v2) 9820 return (-1); 9821 else if (v1 > v2) 9822 return (1); 9823 9824 return (0); 9825 } 9826 9827 static void 9828 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 9829 unsigned int to) 9830 { 9831 unsigned int size; 9832 9833 if (from == to) 9834 return; 9835 9836 size = to - from + 1; 9837 if (size == 0) 9838 return; 9839 9840 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 9841 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 9842 } 9843 9844 static int 9845 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 9846 { 9847 struct adapter *sc = arg1; 9848 struct sbuf *sb; 9849 int rc, i, n; 9850 uint32_t lo, hi, used, free, alloc; 9851 static const char *memory[] = { 9852 "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:" 9853 }; 9854 static const char *region[] = { 9855 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 9856 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 9857 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 9858 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 9859 "RQUDP region:", "PBL region:", "TXPBL region:", 9860 "TLSKey region:", "DBVFIFO region:", "ULPRX state:", 9861 "ULPTX state:", "On-chip queues:", 9862 }; 9863 struct mem_desc avail[4]; 9864 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 9865 struct mem_desc *md = mem; 9866 9867 rc = sysctl_wire_old_buffer(req, 0); 9868 if (rc != 0) 9869 return (rc); 9870 9871 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9872 if (sb == NULL) 9873 return (ENOMEM); 9874 9875 for (i = 0; i < nitems(mem); i++) { 9876 mem[i].limit = 0; 9877 mem[i].idx = i; 9878 } 9879 9880 mtx_lock(&sc->reg_lock); 9881 if (hw_off_limits(sc)) { 9882 rc = ENXIO; 9883 goto done; 9884 } 9885 9886 /* Find and sort the populated memory ranges */ 9887 i = 0; 9888 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 9889 if (lo & F_EDRAM0_ENABLE) { 9890 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 9891 avail[i].base = G_EDRAM0_BASE(hi) << 20; 9892 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 9893 avail[i].idx = 0; 9894 i++; 9895 } 9896 if (lo & F_EDRAM1_ENABLE) { 9897 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 9898 avail[i].base = G_EDRAM1_BASE(hi) << 20; 9899 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 9900 avail[i].idx = 1; 9901 i++; 9902 } 9903 if (lo & F_EXT_MEM_ENABLE) { 9904 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 9905 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 9906 avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20); 9907 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 9908 i++; 9909 } 9910 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 9911 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9912 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9913 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9914 avail[i].idx = 4; 9915 i++; 9916 } 9917 if (is_t6(sc) && lo & F_HMA_MUX) { 9918 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9919 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9920 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9921 avail[i].idx = 5; 9922 i++; 9923 } 9924 MPASS(i <= nitems(avail)); 9925 if (!i) /* no memory available */ 9926 goto done; 9927 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 9928 9929 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 9930 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 9931 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 9932 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9933 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 9934 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 9935 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 9936 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 9937 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 9938 9939 /* the next few have explicit upper bounds */ 9940 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 9941 md->limit = md->base - 1 + 9942 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 9943 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 9944 md++; 9945 9946 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 9947 md->limit = md->base - 1 + 9948 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 9949 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 9950 md++; 9951 9952 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 9953 if (chip_id(sc) <= CHELSIO_T5) 9954 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 9955 else 9956 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 9957 md->limit = 0; 9958 } else { 9959 md->base = 0; 9960 md->idx = nitems(region); /* hide it */ 9961 } 9962 md++; 9963 9964 #define ulp_region(reg) \ 9965 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 9966 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 9967 9968 ulp_region(RX_ISCSI); 9969 ulp_region(RX_TDDP); 9970 ulp_region(TX_TPT); 9971 ulp_region(RX_STAG); 9972 ulp_region(RX_RQ); 9973 ulp_region(RX_RQUDP); 9974 ulp_region(RX_PBL); 9975 ulp_region(TX_PBL); 9976 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 9977 ulp_region(RX_TLS_KEY); 9978 } 9979 #undef ulp_region 9980 9981 md->base = 0; 9982 if (is_t4(sc)) 9983 md->idx = nitems(region); 9984 else { 9985 uint32_t size = 0; 9986 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 9987 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 9988 9989 if (is_t5(sc)) { 9990 if (sge_ctrl & F_VFIFO_ENABLE) 9991 size = fifo_size << 2; 9992 } else 9993 size = G_T6_DBVFIFO_SIZE(fifo_size) << 6; 9994 9995 if (size) { 9996 md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR); 9997 md->limit = md->base + size - 1; 9998 } else 9999 md->idx = nitems(region); 10000 } 10001 md++; 10002 10003 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 10004 md->limit = 0; 10005 md++; 10006 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 10007 md->limit = 0; 10008 md++; 10009 10010 md->base = sc->vres.ocq.start; 10011 if (sc->vres.ocq.size) 10012 md->limit = md->base + sc->vres.ocq.size - 1; 10013 else 10014 md->idx = nitems(region); /* hide it */ 10015 md++; 10016 10017 /* add any address-space holes, there can be up to 3 */ 10018 for (n = 0; n < i - 1; n++) 10019 if (avail[n].limit < avail[n + 1].base) 10020 (md++)->base = avail[n].limit; 10021 if (avail[n].limit) 10022 (md++)->base = avail[n].limit; 10023 10024 n = md - mem; 10025 MPASS(n <= nitems(mem)); 10026 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 10027 10028 for (lo = 0; lo < i; lo++) 10029 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 10030 avail[lo].limit - 1); 10031 10032 sbuf_printf(sb, "\n"); 10033 for (i = 0; i < n; i++) { 10034 if (mem[i].idx >= nitems(region)) 10035 continue; /* skip holes */ 10036 if (!mem[i].limit) 10037 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 10038 mem_region_show(sb, region[mem[i].idx], mem[i].base, 10039 mem[i].limit); 10040 } 10041 10042 sbuf_printf(sb, "\n"); 10043 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 10044 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 10045 mem_region_show(sb, "uP RAM:", lo, hi); 10046 10047 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 10048 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 10049 mem_region_show(sb, "uP Extmem2:", lo, hi); 10050 10051 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 10052 for (i = 0, free = 0; i < 2; i++) 10053 free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT)); 10054 sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n", 10055 G_PMRXMAXPAGE(lo), free, 10056 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 10057 (lo & F_PMRXNUMCHN) ? 2 : 1); 10058 10059 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 10060 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 10061 for (i = 0, free = 0; i < 4; i++) 10062 free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT)); 10063 sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n", 10064 G_PMTXMAXPAGE(lo), free, 10065 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 10066 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 10067 sbuf_printf(sb, "%u p-structs (%u free)\n", 10068 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT), 10069 G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT))); 10070 10071 for (i = 0; i < 4; i++) { 10072 if (chip_id(sc) > CHELSIO_T5) 10073 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 10074 else 10075 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 10076 if (is_t5(sc)) { 10077 used = G_T5_USED(lo); 10078 alloc = G_T5_ALLOC(lo); 10079 } else { 10080 used = G_USED(lo); 10081 alloc = G_ALLOC(lo); 10082 } 10083 /* For T6 these are MAC buffer groups */ 10084 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 10085 i, used, alloc); 10086 } 10087 for (i = 0; i < sc->chip_params->nchan; i++) { 10088 if (chip_id(sc) > CHELSIO_T5) 10089 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 10090 else 10091 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 10092 if (is_t5(sc)) { 10093 used = G_T5_USED(lo); 10094 alloc = G_T5_ALLOC(lo); 10095 } else { 10096 used = G_USED(lo); 10097 alloc = G_ALLOC(lo); 10098 } 10099 /* For T6 these are MAC buffer groups */ 10100 sbuf_printf(sb, 10101 "\nLoopback %d using %u pages out of %u allocated", 10102 i, used, alloc); 10103 } 10104 done: 10105 mtx_unlock(&sc->reg_lock); 10106 if (rc == 0) 10107 rc = sbuf_finish(sb); 10108 sbuf_delete(sb); 10109 return (rc); 10110 } 10111 10112 static inline void 10113 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 10114 { 10115 *mask = x | y; 10116 y = htobe64(y); 10117 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 10118 } 10119 10120 static int 10121 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 10122 { 10123 struct adapter *sc = arg1; 10124 struct sbuf *sb; 10125 int rc, i; 10126 10127 MPASS(chip_id(sc) <= CHELSIO_T5); 10128 10129 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10130 if (sb == NULL) 10131 return (ENOMEM); 10132 10133 sbuf_printf(sb, 10134 "Idx Ethernet address Mask Vld Ports PF" 10135 " VF Replication P0 P1 P2 P3 ML"); 10136 rc = 0; 10137 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10138 uint64_t tcamx, tcamy, mask; 10139 uint32_t cls_lo, cls_hi; 10140 uint8_t addr[ETHER_ADDR_LEN]; 10141 10142 mtx_lock(&sc->reg_lock); 10143 if (hw_off_limits(sc)) 10144 rc = ENXIO; 10145 else { 10146 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 10147 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 10148 } 10149 mtx_unlock(&sc->reg_lock); 10150 if (rc != 0) 10151 break; 10152 if (tcamx & tcamy) 10153 continue; 10154 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10155 mtx_lock(&sc->reg_lock); 10156 if (hw_off_limits(sc)) 10157 rc = ENXIO; 10158 else { 10159 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10160 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10161 } 10162 mtx_unlock(&sc->reg_lock); 10163 if (rc != 0) 10164 break; 10165 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 10166 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 10167 addr[3], addr[4], addr[5], (uintmax_t)mask, 10168 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 10169 G_PORTMAP(cls_hi), G_PF(cls_lo), 10170 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 10171 10172 if (cls_lo & F_REPLICATE) { 10173 struct fw_ldst_cmd ldst_cmd; 10174 10175 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10176 ldst_cmd.op_to_addrspace = 10177 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10178 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10179 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10180 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10181 ldst_cmd.u.mps.rplc.fid_idx = 10182 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10183 V_FW_LDST_CMD_IDX(i)); 10184 10185 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10186 "t4mps"); 10187 if (rc) 10188 break; 10189 if (hw_off_limits(sc)) 10190 rc = ENXIO; 10191 else 10192 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10193 sizeof(ldst_cmd), &ldst_cmd); 10194 end_synchronized_op(sc, 0); 10195 if (rc != 0) 10196 break; 10197 else { 10198 sbuf_printf(sb, " %08x %08x %08x %08x", 10199 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10200 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10201 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10202 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10203 } 10204 } else 10205 sbuf_printf(sb, "%36s", ""); 10206 10207 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 10208 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 10209 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 10210 } 10211 10212 if (rc) 10213 (void) sbuf_finish(sb); 10214 else 10215 rc = sbuf_finish(sb); 10216 sbuf_delete(sb); 10217 10218 return (rc); 10219 } 10220 10221 static int 10222 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 10223 { 10224 struct adapter *sc = arg1; 10225 struct sbuf *sb; 10226 int rc, i; 10227 10228 MPASS(chip_id(sc) > CHELSIO_T5); 10229 10230 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10231 if (sb == NULL) 10232 return (ENOMEM); 10233 10234 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 10235 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 10236 " Replication" 10237 " P0 P1 P2 P3 ML\n"); 10238 10239 rc = 0; 10240 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10241 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 10242 uint16_t ivlan; 10243 uint64_t tcamx, tcamy, val, mask; 10244 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 10245 uint8_t addr[ETHER_ADDR_LEN]; 10246 10247 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 10248 if (i < 256) 10249 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 10250 else 10251 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 10252 mtx_lock(&sc->reg_lock); 10253 if (hw_off_limits(sc)) 10254 rc = ENXIO; 10255 else { 10256 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10257 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10258 tcamy = G_DMACH(val) << 32; 10259 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10260 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10261 } 10262 mtx_unlock(&sc->reg_lock); 10263 if (rc != 0) 10264 break; 10265 10266 lookup_type = G_DATALKPTYPE(data2); 10267 port_num = G_DATAPORTNUM(data2); 10268 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10269 /* Inner header VNI */ 10270 vniy = ((data2 & F_DATAVIDH2) << 23) | 10271 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10272 dip_hit = data2 & F_DATADIPHIT; 10273 vlan_vld = 0; 10274 } else { 10275 vniy = 0; 10276 dip_hit = 0; 10277 vlan_vld = data2 & F_DATAVIDH2; 10278 ivlan = G_VIDL(val); 10279 } 10280 10281 ctl |= V_CTLXYBITSEL(1); 10282 mtx_lock(&sc->reg_lock); 10283 if (hw_off_limits(sc)) 10284 rc = ENXIO; 10285 else { 10286 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10287 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10288 tcamx = G_DMACH(val) << 32; 10289 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10290 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10291 } 10292 mtx_unlock(&sc->reg_lock); 10293 if (rc != 0) 10294 break; 10295 10296 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10297 /* Inner header VNI mask */ 10298 vnix = ((data2 & F_DATAVIDH2) << 23) | 10299 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10300 } else 10301 vnix = 0; 10302 10303 if (tcamx & tcamy) 10304 continue; 10305 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10306 10307 mtx_lock(&sc->reg_lock); 10308 if (hw_off_limits(sc)) 10309 rc = ENXIO; 10310 else { 10311 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10312 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10313 } 10314 mtx_unlock(&sc->reg_lock); 10315 if (rc != 0) 10316 break; 10317 10318 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10319 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10320 "%012jx %06x %06x - - %3c" 10321 " I %4x %3c %#x%4u%4d", i, addr[0], 10322 addr[1], addr[2], addr[3], addr[4], addr[5], 10323 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 10324 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10325 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10326 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10327 } else { 10328 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10329 "%012jx - - ", i, addr[0], addr[1], 10330 addr[2], addr[3], addr[4], addr[5], 10331 (uintmax_t)mask); 10332 10333 if (vlan_vld) 10334 sbuf_printf(sb, "%4u Y ", ivlan); 10335 else 10336 sbuf_printf(sb, " - N "); 10337 10338 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 10339 lookup_type ? 'I' : 'O', port_num, 10340 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10341 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10342 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10343 } 10344 10345 10346 if (cls_lo & F_T6_REPLICATE) { 10347 struct fw_ldst_cmd ldst_cmd; 10348 10349 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10350 ldst_cmd.op_to_addrspace = 10351 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10352 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10353 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10354 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10355 ldst_cmd.u.mps.rplc.fid_idx = 10356 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10357 V_FW_LDST_CMD_IDX(i)); 10358 10359 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10360 "t6mps"); 10361 if (rc) 10362 break; 10363 if (hw_off_limits(sc)) 10364 rc = ENXIO; 10365 else 10366 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10367 sizeof(ldst_cmd), &ldst_cmd); 10368 end_synchronized_op(sc, 0); 10369 if (rc != 0) 10370 break; 10371 else { 10372 sbuf_printf(sb, " %08x %08x %08x %08x" 10373 " %08x %08x %08x %08x", 10374 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 10375 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 10376 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 10377 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 10378 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10379 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10380 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10381 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10382 } 10383 } else 10384 sbuf_printf(sb, "%72s", ""); 10385 10386 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 10387 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 10388 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 10389 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 10390 } 10391 10392 if (rc) 10393 (void) sbuf_finish(sb); 10394 else 10395 rc = sbuf_finish(sb); 10396 sbuf_delete(sb); 10397 10398 return (rc); 10399 } 10400 10401 static int 10402 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 10403 { 10404 struct adapter *sc = arg1; 10405 struct sbuf *sb; 10406 int rc; 10407 uint16_t mtus[NMTUS]; 10408 10409 rc = 0; 10410 mtx_lock(&sc->reg_lock); 10411 if (hw_off_limits(sc)) 10412 rc = ENXIO; 10413 else 10414 t4_read_mtu_tbl(sc, mtus, NULL); 10415 mtx_unlock(&sc->reg_lock); 10416 if (rc != 0) 10417 return (rc); 10418 10419 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10420 if (sb == NULL) 10421 return (ENOMEM); 10422 10423 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 10424 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 10425 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 10426 mtus[14], mtus[15]); 10427 10428 rc = sbuf_finish(sb); 10429 sbuf_delete(sb); 10430 10431 return (rc); 10432 } 10433 10434 static int 10435 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 10436 { 10437 struct adapter *sc = arg1; 10438 struct sbuf *sb; 10439 int rc, i; 10440 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 10441 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 10442 static const char *tx_stats[MAX_PM_NSTATS] = { 10443 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 10444 "Tx FIFO wait", NULL, "Tx latency" 10445 }; 10446 static const char *rx_stats[MAX_PM_NSTATS] = { 10447 "Read:", "Write bypass:", "Write mem:", "Flush:", 10448 "Rx FIFO wait", NULL, "Rx latency" 10449 }; 10450 10451 rc = 0; 10452 mtx_lock(&sc->reg_lock); 10453 if (hw_off_limits(sc)) 10454 rc = ENXIO; 10455 else { 10456 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 10457 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 10458 } 10459 mtx_unlock(&sc->reg_lock); 10460 if (rc != 0) 10461 return (rc); 10462 10463 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10464 if (sb == NULL) 10465 return (ENOMEM); 10466 10467 sbuf_printf(sb, " Tx pcmds Tx bytes"); 10468 for (i = 0; i < 4; i++) { 10469 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10470 tx_cyc[i]); 10471 } 10472 10473 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 10474 for (i = 0; i < 4; i++) { 10475 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10476 rx_cyc[i]); 10477 } 10478 10479 if (chip_id(sc) > CHELSIO_T5) { 10480 sbuf_printf(sb, 10481 "\n Total wait Total occupancy"); 10482 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10483 tx_cyc[i]); 10484 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10485 rx_cyc[i]); 10486 10487 i += 2; 10488 MPASS(i < nitems(tx_stats)); 10489 10490 sbuf_printf(sb, 10491 "\n Reads Total wait"); 10492 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10493 tx_cyc[i]); 10494 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10495 rx_cyc[i]); 10496 } 10497 10498 rc = sbuf_finish(sb); 10499 sbuf_delete(sb); 10500 10501 return (rc); 10502 } 10503 10504 static int 10505 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 10506 { 10507 struct adapter *sc = arg1; 10508 struct sbuf *sb; 10509 int rc; 10510 struct tp_rdma_stats stats; 10511 10512 rc = 0; 10513 mtx_lock(&sc->reg_lock); 10514 if (hw_off_limits(sc)) 10515 rc = ENXIO; 10516 else 10517 t4_tp_get_rdma_stats(sc, &stats, 0); 10518 mtx_unlock(&sc->reg_lock); 10519 if (rc != 0) 10520 return (rc); 10521 10522 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10523 if (sb == NULL) 10524 return (ENOMEM); 10525 10526 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 10527 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 10528 10529 rc = sbuf_finish(sb); 10530 sbuf_delete(sb); 10531 10532 return (rc); 10533 } 10534 10535 static int 10536 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 10537 { 10538 struct adapter *sc = arg1; 10539 struct sbuf *sb; 10540 int rc; 10541 struct tp_tcp_stats v4, v6; 10542 10543 rc = 0; 10544 mtx_lock(&sc->reg_lock); 10545 if (hw_off_limits(sc)) 10546 rc = ENXIO; 10547 else 10548 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 10549 mtx_unlock(&sc->reg_lock); 10550 if (rc != 0) 10551 return (rc); 10552 10553 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10554 if (sb == NULL) 10555 return (ENOMEM); 10556 10557 sbuf_printf(sb, 10558 " IP IPv6\n"); 10559 sbuf_printf(sb, "OutRsts: %20u %20u\n", 10560 v4.tcp_out_rsts, v6.tcp_out_rsts); 10561 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 10562 v4.tcp_in_segs, v6.tcp_in_segs); 10563 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 10564 v4.tcp_out_segs, v6.tcp_out_segs); 10565 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 10566 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 10567 10568 rc = sbuf_finish(sb); 10569 sbuf_delete(sb); 10570 10571 return (rc); 10572 } 10573 10574 static int 10575 sysctl_tids(SYSCTL_HANDLER_ARGS) 10576 { 10577 struct adapter *sc = arg1; 10578 struct sbuf *sb; 10579 int rc; 10580 uint32_t x, y; 10581 struct tid_info *t = &sc->tids; 10582 10583 rc = 0; 10584 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10585 if (sb == NULL) 10586 return (ENOMEM); 10587 10588 if (t->natids) { 10589 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 10590 t->atids_in_use); 10591 } 10592 10593 if (t->nhpftids) { 10594 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 10595 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 10596 } 10597 10598 if (t->ntids) { 10599 bool hashen = false; 10600 10601 mtx_lock(&sc->reg_lock); 10602 if (hw_off_limits(sc)) 10603 rc = ENXIO; 10604 else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 10605 hashen = true; 10606 if (chip_id(sc) <= CHELSIO_T5) { 10607 x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 10608 y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 10609 } else { 10610 x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 10611 y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 10612 } 10613 } 10614 mtx_unlock(&sc->reg_lock); 10615 if (rc != 0) 10616 goto done; 10617 10618 sbuf_printf(sb, "TID range: "); 10619 if (hashen) { 10620 if (x) 10621 sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1); 10622 sbuf_printf(sb, "%u-%u", y, t->ntids - 1); 10623 } else { 10624 sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base + 10625 t->ntids - 1); 10626 } 10627 sbuf_printf(sb, ", in use: %u\n", 10628 atomic_load_acq_int(&t->tids_in_use)); 10629 } 10630 10631 if (t->nstids) { 10632 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 10633 t->stid_base + t->nstids - 1, t->stids_in_use); 10634 } 10635 10636 if (t->nftids) { 10637 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 10638 t->ftid_end, t->ftids_in_use); 10639 } 10640 10641 if (t->netids) { 10642 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 10643 t->etid_base + t->netids - 1, t->etids_in_use); 10644 } 10645 10646 mtx_lock(&sc->reg_lock); 10647 if (hw_off_limits(sc)) 10648 rc = ENXIO; 10649 else { 10650 x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4); 10651 y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6); 10652 } 10653 mtx_unlock(&sc->reg_lock); 10654 if (rc != 0) 10655 goto done; 10656 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y); 10657 done: 10658 if (rc == 0) 10659 rc = sbuf_finish(sb); 10660 else 10661 (void)sbuf_finish(sb); 10662 sbuf_delete(sb); 10663 10664 return (rc); 10665 } 10666 10667 static int 10668 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 10669 { 10670 struct adapter *sc = arg1; 10671 struct sbuf *sb; 10672 int rc; 10673 struct tp_err_stats stats; 10674 10675 rc = 0; 10676 mtx_lock(&sc->reg_lock); 10677 if (hw_off_limits(sc)) 10678 rc = ENXIO; 10679 else 10680 t4_tp_get_err_stats(sc, &stats, 0); 10681 mtx_unlock(&sc->reg_lock); 10682 if (rc != 0) 10683 return (rc); 10684 10685 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10686 if (sb == NULL) 10687 return (ENOMEM); 10688 10689 if (sc->chip_params->nchan > 2) { 10690 sbuf_printf(sb, " channel 0 channel 1" 10691 " channel 2 channel 3\n"); 10692 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 10693 stats.mac_in_errs[0], stats.mac_in_errs[1], 10694 stats.mac_in_errs[2], stats.mac_in_errs[3]); 10695 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 10696 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 10697 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 10698 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 10699 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 10700 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 10701 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 10702 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 10703 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 10704 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 10705 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 10706 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 10707 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 10708 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 10709 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 10710 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 10711 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 10712 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 10713 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 10714 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 10715 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 10716 } else { 10717 sbuf_printf(sb, " channel 0 channel 1\n"); 10718 sbuf_printf(sb, "macInErrs: %10u %10u\n", 10719 stats.mac_in_errs[0], stats.mac_in_errs[1]); 10720 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 10721 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 10722 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 10723 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 10724 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 10725 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 10726 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 10727 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 10728 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 10729 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 10730 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 10731 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 10732 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 10733 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 10734 } 10735 10736 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 10737 stats.ofld_no_neigh, stats.ofld_cong_defer); 10738 10739 rc = sbuf_finish(sb); 10740 sbuf_delete(sb); 10741 10742 return (rc); 10743 } 10744 10745 static int 10746 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS) 10747 { 10748 struct adapter *sc = arg1; 10749 struct sbuf *sb; 10750 int rc; 10751 struct tp_tnl_stats stats; 10752 10753 rc = 0; 10754 mtx_lock(&sc->reg_lock); 10755 if (hw_off_limits(sc)) 10756 rc = ENXIO; 10757 else 10758 t4_tp_get_tnl_stats(sc, &stats, 1); 10759 mtx_unlock(&sc->reg_lock); 10760 if (rc != 0) 10761 return (rc); 10762 10763 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10764 if (sb == NULL) 10765 return (ENOMEM); 10766 10767 if (sc->chip_params->nchan > 2) { 10768 sbuf_printf(sb, " channel 0 channel 1" 10769 " channel 2 channel 3\n"); 10770 sbuf_printf(sb, "OutPkts: %10u %10u %10u %10u\n", 10771 stats.out_pkt[0], stats.out_pkt[1], 10772 stats.out_pkt[2], stats.out_pkt[3]); 10773 sbuf_printf(sb, "InPkts: %10u %10u %10u %10u", 10774 stats.in_pkt[0], stats.in_pkt[1], 10775 stats.in_pkt[2], stats.in_pkt[3]); 10776 } else { 10777 sbuf_printf(sb, " channel 0 channel 1\n"); 10778 sbuf_printf(sb, "OutPkts: %10u %10u\n", 10779 stats.out_pkt[0], stats.out_pkt[1]); 10780 sbuf_printf(sb, "InPkts: %10u %10u", 10781 stats.in_pkt[0], stats.in_pkt[1]); 10782 } 10783 10784 rc = sbuf_finish(sb); 10785 sbuf_delete(sb); 10786 10787 return (rc); 10788 } 10789 10790 static int 10791 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 10792 { 10793 struct adapter *sc = arg1; 10794 struct tp_params *tpp = &sc->params.tp; 10795 u_int mask; 10796 int rc; 10797 10798 mask = tpp->la_mask >> 16; 10799 rc = sysctl_handle_int(oidp, &mask, 0, req); 10800 if (rc != 0 || req->newptr == NULL) 10801 return (rc); 10802 if (mask > 0xffff) 10803 return (EINVAL); 10804 mtx_lock(&sc->reg_lock); 10805 if (hw_off_limits(sc)) 10806 rc = ENXIO; 10807 else { 10808 tpp->la_mask = mask << 16; 10809 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, 10810 tpp->la_mask); 10811 } 10812 mtx_unlock(&sc->reg_lock); 10813 10814 return (rc); 10815 } 10816 10817 struct field_desc { 10818 const char *name; 10819 u_int start; 10820 u_int width; 10821 }; 10822 10823 static void 10824 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 10825 { 10826 char buf[32]; 10827 int line_size = 0; 10828 10829 while (f->name) { 10830 uint64_t mask = (1ULL << f->width) - 1; 10831 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 10832 ((uintmax_t)v >> f->start) & mask); 10833 10834 if (line_size + len >= 79) { 10835 line_size = 8; 10836 sbuf_printf(sb, "\n "); 10837 } 10838 sbuf_printf(sb, "%s ", buf); 10839 line_size += len + 1; 10840 f++; 10841 } 10842 sbuf_printf(sb, "\n"); 10843 } 10844 10845 static const struct field_desc tp_la0[] = { 10846 { "RcfOpCodeOut", 60, 4 }, 10847 { "State", 56, 4 }, 10848 { "WcfState", 52, 4 }, 10849 { "RcfOpcSrcOut", 50, 2 }, 10850 { "CRxError", 49, 1 }, 10851 { "ERxError", 48, 1 }, 10852 { "SanityFailed", 47, 1 }, 10853 { "SpuriousMsg", 46, 1 }, 10854 { "FlushInputMsg", 45, 1 }, 10855 { "FlushInputCpl", 44, 1 }, 10856 { "RssUpBit", 43, 1 }, 10857 { "RssFilterHit", 42, 1 }, 10858 { "Tid", 32, 10 }, 10859 { "InitTcb", 31, 1 }, 10860 { "LineNumber", 24, 7 }, 10861 { "Emsg", 23, 1 }, 10862 { "EdataOut", 22, 1 }, 10863 { "Cmsg", 21, 1 }, 10864 { "CdataOut", 20, 1 }, 10865 { "EreadPdu", 19, 1 }, 10866 { "CreadPdu", 18, 1 }, 10867 { "TunnelPkt", 17, 1 }, 10868 { "RcfPeerFin", 16, 1 }, 10869 { "RcfReasonOut", 12, 4 }, 10870 { "TxCchannel", 10, 2 }, 10871 { "RcfTxChannel", 8, 2 }, 10872 { "RxEchannel", 6, 2 }, 10873 { "RcfRxChannel", 5, 1 }, 10874 { "RcfDataOutSrdy", 4, 1 }, 10875 { "RxDvld", 3, 1 }, 10876 { "RxOoDvld", 2, 1 }, 10877 { "RxCongestion", 1, 1 }, 10878 { "TxCongestion", 0, 1 }, 10879 { NULL } 10880 }; 10881 10882 static const struct field_desc tp_la1[] = { 10883 { "CplCmdIn", 56, 8 }, 10884 { "CplCmdOut", 48, 8 }, 10885 { "ESynOut", 47, 1 }, 10886 { "EAckOut", 46, 1 }, 10887 { "EFinOut", 45, 1 }, 10888 { "ERstOut", 44, 1 }, 10889 { "SynIn", 43, 1 }, 10890 { "AckIn", 42, 1 }, 10891 { "FinIn", 41, 1 }, 10892 { "RstIn", 40, 1 }, 10893 { "DataIn", 39, 1 }, 10894 { "DataInVld", 38, 1 }, 10895 { "PadIn", 37, 1 }, 10896 { "RxBufEmpty", 36, 1 }, 10897 { "RxDdp", 35, 1 }, 10898 { "RxFbCongestion", 34, 1 }, 10899 { "TxFbCongestion", 33, 1 }, 10900 { "TxPktSumSrdy", 32, 1 }, 10901 { "RcfUlpType", 28, 4 }, 10902 { "Eread", 27, 1 }, 10903 { "Ebypass", 26, 1 }, 10904 { "Esave", 25, 1 }, 10905 { "Static0", 24, 1 }, 10906 { "Cread", 23, 1 }, 10907 { "Cbypass", 22, 1 }, 10908 { "Csave", 21, 1 }, 10909 { "CPktOut", 20, 1 }, 10910 { "RxPagePoolFull", 18, 2 }, 10911 { "RxLpbkPkt", 17, 1 }, 10912 { "TxLpbkPkt", 16, 1 }, 10913 { "RxVfValid", 15, 1 }, 10914 { "SynLearned", 14, 1 }, 10915 { "SetDelEntry", 13, 1 }, 10916 { "SetInvEntry", 12, 1 }, 10917 { "CpcmdDvld", 11, 1 }, 10918 { "CpcmdSave", 10, 1 }, 10919 { "RxPstructsFull", 8, 2 }, 10920 { "EpcmdDvld", 7, 1 }, 10921 { "EpcmdFlush", 6, 1 }, 10922 { "EpcmdTrimPrefix", 5, 1 }, 10923 { "EpcmdTrimPostfix", 4, 1 }, 10924 { "ERssIp4Pkt", 3, 1 }, 10925 { "ERssIp6Pkt", 2, 1 }, 10926 { "ERssTcpUdpPkt", 1, 1 }, 10927 { "ERssFceFipPkt", 0, 1 }, 10928 { NULL } 10929 }; 10930 10931 static const struct field_desc tp_la2[] = { 10932 { "CplCmdIn", 56, 8 }, 10933 { "MpsVfVld", 55, 1 }, 10934 { "MpsPf", 52, 3 }, 10935 { "MpsVf", 44, 8 }, 10936 { "SynIn", 43, 1 }, 10937 { "AckIn", 42, 1 }, 10938 { "FinIn", 41, 1 }, 10939 { "RstIn", 40, 1 }, 10940 { "DataIn", 39, 1 }, 10941 { "DataInVld", 38, 1 }, 10942 { "PadIn", 37, 1 }, 10943 { "RxBufEmpty", 36, 1 }, 10944 { "RxDdp", 35, 1 }, 10945 { "RxFbCongestion", 34, 1 }, 10946 { "TxFbCongestion", 33, 1 }, 10947 { "TxPktSumSrdy", 32, 1 }, 10948 { "RcfUlpType", 28, 4 }, 10949 { "Eread", 27, 1 }, 10950 { "Ebypass", 26, 1 }, 10951 { "Esave", 25, 1 }, 10952 { "Static0", 24, 1 }, 10953 { "Cread", 23, 1 }, 10954 { "Cbypass", 22, 1 }, 10955 { "Csave", 21, 1 }, 10956 { "CPktOut", 20, 1 }, 10957 { "RxPagePoolFull", 18, 2 }, 10958 { "RxLpbkPkt", 17, 1 }, 10959 { "TxLpbkPkt", 16, 1 }, 10960 { "RxVfValid", 15, 1 }, 10961 { "SynLearned", 14, 1 }, 10962 { "SetDelEntry", 13, 1 }, 10963 { "SetInvEntry", 12, 1 }, 10964 { "CpcmdDvld", 11, 1 }, 10965 { "CpcmdSave", 10, 1 }, 10966 { "RxPstructsFull", 8, 2 }, 10967 { "EpcmdDvld", 7, 1 }, 10968 { "EpcmdFlush", 6, 1 }, 10969 { "EpcmdTrimPrefix", 5, 1 }, 10970 { "EpcmdTrimPostfix", 4, 1 }, 10971 { "ERssIp4Pkt", 3, 1 }, 10972 { "ERssIp6Pkt", 2, 1 }, 10973 { "ERssTcpUdpPkt", 1, 1 }, 10974 { "ERssFceFipPkt", 0, 1 }, 10975 { NULL } 10976 }; 10977 10978 static void 10979 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 10980 { 10981 10982 field_desc_show(sb, *p, tp_la0); 10983 } 10984 10985 static void 10986 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 10987 { 10988 10989 if (idx) 10990 sbuf_printf(sb, "\n"); 10991 field_desc_show(sb, p[0], tp_la0); 10992 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10993 field_desc_show(sb, p[1], tp_la0); 10994 } 10995 10996 static void 10997 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 10998 { 10999 11000 if (idx) 11001 sbuf_printf(sb, "\n"); 11002 field_desc_show(sb, p[0], tp_la0); 11003 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 11004 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 11005 } 11006 11007 static int 11008 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 11009 { 11010 struct adapter *sc = arg1; 11011 struct sbuf *sb; 11012 uint64_t *buf, *p; 11013 int rc; 11014 u_int i, inc; 11015 void (*show_func)(struct sbuf *, uint64_t *, int); 11016 11017 rc = 0; 11018 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11019 if (sb == NULL) 11020 return (ENOMEM); 11021 11022 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 11023 11024 mtx_lock(&sc->reg_lock); 11025 if (hw_off_limits(sc)) 11026 rc = ENXIO; 11027 else { 11028 t4_tp_read_la(sc, buf, NULL); 11029 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 11030 case 2: 11031 inc = 2; 11032 show_func = tp_la_show2; 11033 break; 11034 case 3: 11035 inc = 2; 11036 show_func = tp_la_show3; 11037 break; 11038 default: 11039 inc = 1; 11040 show_func = tp_la_show; 11041 } 11042 } 11043 mtx_unlock(&sc->reg_lock); 11044 if (rc != 0) 11045 goto done; 11046 11047 p = buf; 11048 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 11049 (*show_func)(sb, p, i); 11050 rc = sbuf_finish(sb); 11051 done: 11052 sbuf_delete(sb); 11053 free(buf, M_CXGBE); 11054 return (rc); 11055 } 11056 11057 static int 11058 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 11059 { 11060 struct adapter *sc = arg1; 11061 struct sbuf *sb; 11062 int rc; 11063 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 11064 11065 rc = 0; 11066 mtx_lock(&sc->reg_lock); 11067 if (hw_off_limits(sc)) 11068 rc = ENXIO; 11069 else 11070 t4_get_chan_txrate(sc, nrate, orate); 11071 mtx_unlock(&sc->reg_lock); 11072 if (rc != 0) 11073 return (rc); 11074 11075 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 11076 if (sb == NULL) 11077 return (ENOMEM); 11078 11079 if (sc->chip_params->nchan > 2) { 11080 sbuf_printf(sb, " channel 0 channel 1" 11081 " channel 2 channel 3\n"); 11082 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 11083 nrate[0], nrate[1], nrate[2], nrate[3]); 11084 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 11085 orate[0], orate[1], orate[2], orate[3]); 11086 } else { 11087 sbuf_printf(sb, " channel 0 channel 1\n"); 11088 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 11089 nrate[0], nrate[1]); 11090 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 11091 orate[0], orate[1]); 11092 } 11093 11094 rc = sbuf_finish(sb); 11095 sbuf_delete(sb); 11096 11097 return (rc); 11098 } 11099 11100 static int 11101 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 11102 { 11103 struct adapter *sc = arg1; 11104 struct sbuf *sb; 11105 uint32_t *buf, *p; 11106 int rc, i; 11107 11108 rc = 0; 11109 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11110 if (sb == NULL) 11111 return (ENOMEM); 11112 11113 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 11114 M_ZERO | M_WAITOK); 11115 11116 mtx_lock(&sc->reg_lock); 11117 if (hw_off_limits(sc)) 11118 rc = ENXIO; 11119 else 11120 t4_ulprx_read_la(sc, buf); 11121 mtx_unlock(&sc->reg_lock); 11122 if (rc != 0) 11123 goto done; 11124 11125 p = buf; 11126 sbuf_printf(sb, " Pcmd Type Message" 11127 " Data"); 11128 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 11129 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 11130 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 11131 } 11132 rc = sbuf_finish(sb); 11133 done: 11134 sbuf_delete(sb); 11135 free(buf, M_CXGBE); 11136 return (rc); 11137 } 11138 11139 static int 11140 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 11141 { 11142 struct adapter *sc = arg1; 11143 struct sbuf *sb; 11144 int rc; 11145 uint32_t cfg, s1, s2; 11146 11147 MPASS(chip_id(sc) >= CHELSIO_T5); 11148 11149 rc = 0; 11150 mtx_lock(&sc->reg_lock); 11151 if (hw_off_limits(sc)) 11152 rc = ENXIO; 11153 else { 11154 cfg = t4_read_reg(sc, A_SGE_STAT_CFG); 11155 s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL); 11156 s2 = t4_read_reg(sc, A_SGE_STAT_MATCH); 11157 } 11158 mtx_unlock(&sc->reg_lock); 11159 if (rc != 0) 11160 return (rc); 11161 11162 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11163 if (sb == NULL) 11164 return (ENOMEM); 11165 11166 if (G_STATSOURCE_T5(cfg) == 7) { 11167 int mode; 11168 11169 mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg); 11170 if (mode == 0) 11171 sbuf_printf(sb, "total %d, incomplete %d", s1, s2); 11172 else if (mode == 1) 11173 sbuf_printf(sb, "total %d, data overflow %d", s1, s2); 11174 else 11175 sbuf_printf(sb, "unknown mode %d", mode); 11176 } 11177 rc = sbuf_finish(sb); 11178 sbuf_delete(sb); 11179 11180 return (rc); 11181 } 11182 11183 static int 11184 sysctl_cpus(SYSCTL_HANDLER_ARGS) 11185 { 11186 struct adapter *sc = arg1; 11187 enum cpu_sets op = arg2; 11188 cpuset_t cpuset; 11189 struct sbuf *sb; 11190 int i, rc; 11191 11192 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 11193 11194 CPU_ZERO(&cpuset); 11195 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 11196 if (rc != 0) 11197 return (rc); 11198 11199 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11200 if (sb == NULL) 11201 return (ENOMEM); 11202 11203 CPU_FOREACH(i) 11204 sbuf_printf(sb, "%d ", i); 11205 rc = sbuf_finish(sb); 11206 sbuf_delete(sb); 11207 11208 return (rc); 11209 } 11210 11211 static int 11212 sysctl_reset(SYSCTL_HANDLER_ARGS) 11213 { 11214 struct adapter *sc = arg1; 11215 u_int val; 11216 int rc; 11217 11218 val = atomic_load_int(&sc->num_resets); 11219 rc = sysctl_handle_int(oidp, &val, 0, req); 11220 if (rc != 0 || req->newptr == NULL) 11221 return (rc); 11222 11223 if (val == 0) { 11224 /* Zero out the counter that tracks reset. */ 11225 atomic_store_int(&sc->num_resets, 0); 11226 return (0); 11227 } 11228 11229 if (val != 1) 11230 return (EINVAL); /* 0 or 1 are the only legal values */ 11231 11232 if (hw_off_limits(sc)) /* harmless race */ 11233 return (EALREADY); 11234 11235 taskqueue_enqueue(reset_tq, &sc->reset_task); 11236 return (0); 11237 } 11238 11239 #ifdef TCP_OFFLOAD 11240 static int 11241 sysctl_tls(SYSCTL_HANDLER_ARGS) 11242 { 11243 struct adapter *sc = arg1; 11244 int i, j, v, rc; 11245 struct vi_info *vi; 11246 11247 v = sc->tt.tls; 11248 rc = sysctl_handle_int(oidp, &v, 0, req); 11249 if (rc != 0 || req->newptr == NULL) 11250 return (rc); 11251 11252 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 11253 return (ENOTSUP); 11254 11255 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls"); 11256 if (rc) 11257 return (rc); 11258 if (hw_off_limits(sc)) 11259 rc = ENXIO; 11260 else { 11261 sc->tt.tls = !!v; 11262 for_each_port(sc, i) { 11263 for_each_vi(sc->port[i], j, vi) { 11264 if (vi->flags & VI_INIT_DONE) 11265 t4_update_fl_bufsize(vi->ifp); 11266 } 11267 } 11268 } 11269 end_synchronized_op(sc, 0); 11270 11271 return (rc); 11272 11273 } 11274 11275 static void 11276 unit_conv(char *buf, size_t len, u_int val, u_int factor) 11277 { 11278 u_int rem = val % factor; 11279 11280 if (rem == 0) 11281 snprintf(buf, len, "%u", val / factor); 11282 else { 11283 while (rem % 10 == 0) 11284 rem /= 10; 11285 snprintf(buf, len, "%u.%u", val / factor, rem); 11286 } 11287 } 11288 11289 static int 11290 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 11291 { 11292 struct adapter *sc = arg1; 11293 char buf[16]; 11294 u_int res, re; 11295 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11296 11297 mtx_lock(&sc->reg_lock); 11298 if (hw_off_limits(sc)) 11299 res = (u_int)-1; 11300 else 11301 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 11302 mtx_unlock(&sc->reg_lock); 11303 if (res == (u_int)-1) 11304 return (ENXIO); 11305 11306 switch (arg2) { 11307 case 0: 11308 /* timer_tick */ 11309 re = G_TIMERRESOLUTION(res); 11310 break; 11311 case 1: 11312 /* TCP timestamp tick */ 11313 re = G_TIMESTAMPRESOLUTION(res); 11314 break; 11315 case 2: 11316 /* DACK tick */ 11317 re = G_DELAYEDACKRESOLUTION(res); 11318 break; 11319 default: 11320 return (EDOOFUS); 11321 } 11322 11323 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 11324 11325 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 11326 } 11327 11328 static int 11329 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 11330 { 11331 struct adapter *sc = arg1; 11332 int rc; 11333 u_int dack_tmr, dack_re, v; 11334 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11335 11336 mtx_lock(&sc->reg_lock); 11337 if (hw_off_limits(sc)) 11338 rc = ENXIO; 11339 else { 11340 rc = 0; 11341 dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc, 11342 A_TP_TIMER_RESOLUTION)); 11343 dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER); 11344 } 11345 mtx_unlock(&sc->reg_lock); 11346 if (rc != 0) 11347 return (rc); 11348 11349 v = ((cclk_ps << dack_re) / 1000000) * dack_tmr; 11350 11351 return (sysctl_handle_int(oidp, &v, 0, req)); 11352 } 11353 11354 static int 11355 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 11356 { 11357 struct adapter *sc = arg1; 11358 int rc, reg = arg2; 11359 u_int tre; 11360 u_long tp_tick_us, v; 11361 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11362 11363 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 11364 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 11365 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 11366 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 11367 11368 mtx_lock(&sc->reg_lock); 11369 if (hw_off_limits(sc)) 11370 rc = ENXIO; 11371 else { 11372 rc = 0; 11373 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 11374 tp_tick_us = (cclk_ps << tre) / 1000000; 11375 if (reg == A_TP_INIT_SRTT) 11376 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 11377 else 11378 v = tp_tick_us * t4_read_reg(sc, reg); 11379 } 11380 mtx_unlock(&sc->reg_lock); 11381 if (rc != 0) 11382 return (rc); 11383 else 11384 return (sysctl_handle_long(oidp, &v, 0, req)); 11385 } 11386 11387 /* 11388 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 11389 * passed to this function. 11390 */ 11391 static int 11392 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 11393 { 11394 struct adapter *sc = arg1; 11395 int rc, idx = arg2; 11396 u_int v; 11397 11398 MPASS(idx >= 0 && idx <= 24); 11399 11400 mtx_lock(&sc->reg_lock); 11401 if (hw_off_limits(sc)) 11402 rc = ENXIO; 11403 else { 11404 rc = 0; 11405 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 11406 } 11407 mtx_unlock(&sc->reg_lock); 11408 if (rc != 0) 11409 return (rc); 11410 else 11411 return (sysctl_handle_int(oidp, &v, 0, req)); 11412 } 11413 11414 static int 11415 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 11416 { 11417 struct adapter *sc = arg1; 11418 int rc, idx = arg2; 11419 u_int shift, v, r; 11420 11421 MPASS(idx >= 0 && idx < 16); 11422 11423 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 11424 shift = (idx & 3) << 3; 11425 mtx_lock(&sc->reg_lock); 11426 if (hw_off_limits(sc)) 11427 rc = ENXIO; 11428 else { 11429 rc = 0; 11430 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 11431 } 11432 mtx_unlock(&sc->reg_lock); 11433 if (rc != 0) 11434 return (rc); 11435 else 11436 return (sysctl_handle_int(oidp, &v, 0, req)); 11437 } 11438 11439 static int 11440 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 11441 { 11442 struct vi_info *vi = arg1; 11443 struct adapter *sc = vi->adapter; 11444 int idx, rc, i; 11445 struct sge_ofld_rxq *ofld_rxq; 11446 uint8_t v; 11447 11448 idx = vi->ofld_tmr_idx; 11449 11450 rc = sysctl_handle_int(oidp, &idx, 0, req); 11451 if (rc != 0 || req->newptr == NULL) 11452 return (rc); 11453 11454 if (idx < 0 || idx >= SGE_NTIMERS) 11455 return (EINVAL); 11456 11457 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11458 "t4otmr"); 11459 if (rc) 11460 return (rc); 11461 11462 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 11463 for_each_ofld_rxq(vi, i, ofld_rxq) { 11464 #ifdef atomic_store_rel_8 11465 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 11466 #else 11467 ofld_rxq->iq.intr_params = v; 11468 #endif 11469 } 11470 vi->ofld_tmr_idx = idx; 11471 11472 end_synchronized_op(sc, LOCK_HELD); 11473 return (0); 11474 } 11475 11476 static int 11477 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 11478 { 11479 struct vi_info *vi = arg1; 11480 struct adapter *sc = vi->adapter; 11481 int idx, rc; 11482 11483 idx = vi->ofld_pktc_idx; 11484 11485 rc = sysctl_handle_int(oidp, &idx, 0, req); 11486 if (rc != 0 || req->newptr == NULL) 11487 return (rc); 11488 11489 if (idx < -1 || idx >= SGE_NCOUNTERS) 11490 return (EINVAL); 11491 11492 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11493 "t4opktc"); 11494 if (rc) 11495 return (rc); 11496 11497 if (vi->flags & VI_INIT_DONE) 11498 rc = EBUSY; /* cannot be changed once the queues are created */ 11499 else 11500 vi->ofld_pktc_idx = idx; 11501 11502 end_synchronized_op(sc, LOCK_HELD); 11503 return (rc); 11504 } 11505 #endif 11506 11507 static int 11508 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 11509 { 11510 int rc; 11511 11512 if (cntxt->cid > M_CTXTQID) 11513 return (EINVAL); 11514 11515 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 11516 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 11517 return (EINVAL); 11518 11519 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 11520 if (rc) 11521 return (rc); 11522 11523 if (hw_off_limits(sc)) { 11524 rc = ENXIO; 11525 goto done; 11526 } 11527 11528 if (sc->flags & FW_OK) { 11529 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 11530 &cntxt->data[0]); 11531 if (rc == 0) 11532 goto done; 11533 } 11534 11535 /* 11536 * Read via firmware failed or wasn't even attempted. Read directly via 11537 * the backdoor. 11538 */ 11539 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 11540 done: 11541 end_synchronized_op(sc, 0); 11542 return (rc); 11543 } 11544 11545 static int 11546 load_fw(struct adapter *sc, struct t4_data *fw) 11547 { 11548 int rc; 11549 uint8_t *fw_data; 11550 11551 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 11552 if (rc) 11553 return (rc); 11554 11555 if (hw_off_limits(sc)) { 11556 rc = ENXIO; 11557 goto done; 11558 } 11559 11560 /* 11561 * The firmware, with the sole exception of the memory parity error 11562 * handler, runs from memory and not flash. It is almost always safe to 11563 * install a new firmware on a running system. Just set bit 1 in 11564 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 11565 */ 11566 if (sc->flags & FULL_INIT_DONE && 11567 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 11568 rc = EBUSY; 11569 goto done; 11570 } 11571 11572 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 11573 11574 rc = copyin(fw->data, fw_data, fw->len); 11575 if (rc == 0) 11576 rc = -t4_load_fw(sc, fw_data, fw->len); 11577 11578 free(fw_data, M_CXGBE); 11579 done: 11580 end_synchronized_op(sc, 0); 11581 return (rc); 11582 } 11583 11584 static int 11585 load_cfg(struct adapter *sc, struct t4_data *cfg) 11586 { 11587 int rc; 11588 uint8_t *cfg_data = NULL; 11589 11590 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11591 if (rc) 11592 return (rc); 11593 11594 if (hw_off_limits(sc)) { 11595 rc = ENXIO; 11596 goto done; 11597 } 11598 11599 if (cfg->len == 0) { 11600 /* clear */ 11601 rc = -t4_load_cfg(sc, NULL, 0); 11602 goto done; 11603 } 11604 11605 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 11606 11607 rc = copyin(cfg->data, cfg_data, cfg->len); 11608 if (rc == 0) 11609 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 11610 11611 free(cfg_data, M_CXGBE); 11612 done: 11613 end_synchronized_op(sc, 0); 11614 return (rc); 11615 } 11616 11617 static int 11618 load_boot(struct adapter *sc, struct t4_bootrom *br) 11619 { 11620 int rc; 11621 uint8_t *br_data = NULL; 11622 u_int offset; 11623 11624 if (br->len > 1024 * 1024) 11625 return (EFBIG); 11626 11627 if (br->pf_offset == 0) { 11628 /* pfidx */ 11629 if (br->pfidx_addr > 7) 11630 return (EINVAL); 11631 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 11632 A_PCIE_PF_EXPROM_OFST))); 11633 } else if (br->pf_offset == 1) { 11634 /* offset */ 11635 offset = G_OFFSET(br->pfidx_addr); 11636 } else { 11637 return (EINVAL); 11638 } 11639 11640 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 11641 if (rc) 11642 return (rc); 11643 11644 if (hw_off_limits(sc)) { 11645 rc = ENXIO; 11646 goto done; 11647 } 11648 11649 if (br->len == 0) { 11650 /* clear */ 11651 rc = -t4_load_boot(sc, NULL, offset, 0); 11652 goto done; 11653 } 11654 11655 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 11656 11657 rc = copyin(br->data, br_data, br->len); 11658 if (rc == 0) 11659 rc = -t4_load_boot(sc, br_data, offset, br->len); 11660 11661 free(br_data, M_CXGBE); 11662 done: 11663 end_synchronized_op(sc, 0); 11664 return (rc); 11665 } 11666 11667 static int 11668 load_bootcfg(struct adapter *sc, struct t4_data *bc) 11669 { 11670 int rc; 11671 uint8_t *bc_data = NULL; 11672 11673 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11674 if (rc) 11675 return (rc); 11676 11677 if (hw_off_limits(sc)) { 11678 rc = ENXIO; 11679 goto done; 11680 } 11681 11682 if (bc->len == 0) { 11683 /* clear */ 11684 rc = -t4_load_bootcfg(sc, NULL, 0); 11685 goto done; 11686 } 11687 11688 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 11689 11690 rc = copyin(bc->data, bc_data, bc->len); 11691 if (rc == 0) 11692 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 11693 11694 free(bc_data, M_CXGBE); 11695 done: 11696 end_synchronized_op(sc, 0); 11697 return (rc); 11698 } 11699 11700 static int 11701 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 11702 { 11703 int rc; 11704 struct cudbg_init *cudbg; 11705 void *handle, *buf; 11706 11707 /* buf is large, don't block if no memory is available */ 11708 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 11709 if (buf == NULL) 11710 return (ENOMEM); 11711 11712 handle = cudbg_alloc_handle(); 11713 if (handle == NULL) { 11714 rc = ENOMEM; 11715 goto done; 11716 } 11717 11718 cudbg = cudbg_get_init(handle); 11719 cudbg->adap = sc; 11720 cudbg->print = (cudbg_print_cb)printf; 11721 11722 #ifndef notyet 11723 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 11724 __func__, dump->wr_flash, dump->len, dump->data); 11725 #endif 11726 11727 if (dump->wr_flash) 11728 cudbg->use_flash = 1; 11729 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 11730 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 11731 11732 rc = cudbg_collect(handle, buf, &dump->len); 11733 if (rc != 0) 11734 goto done; 11735 11736 rc = copyout(buf, dump->data, dump->len); 11737 done: 11738 cudbg_free_handle(handle); 11739 free(buf, M_CXGBE); 11740 return (rc); 11741 } 11742 11743 static void 11744 free_offload_policy(struct t4_offload_policy *op) 11745 { 11746 struct offload_rule *r; 11747 int i; 11748 11749 if (op == NULL) 11750 return; 11751 11752 r = &op->rule[0]; 11753 for (i = 0; i < op->nrules; i++, r++) { 11754 free(r->bpf_prog.bf_insns, M_CXGBE); 11755 } 11756 free(op->rule, M_CXGBE); 11757 free(op, M_CXGBE); 11758 } 11759 11760 static int 11761 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 11762 { 11763 int i, rc, len; 11764 struct t4_offload_policy *op, *old; 11765 struct bpf_program *bf; 11766 const struct offload_settings *s; 11767 struct offload_rule *r; 11768 void *u; 11769 11770 if (!is_offload(sc)) 11771 return (ENODEV); 11772 11773 if (uop->nrules == 0) { 11774 /* Delete installed policies. */ 11775 op = NULL; 11776 goto set_policy; 11777 } else if (uop->nrules > 256) { /* arbitrary */ 11778 return (E2BIG); 11779 } 11780 11781 /* Copy userspace offload policy to kernel */ 11782 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 11783 op->nrules = uop->nrules; 11784 len = op->nrules * sizeof(struct offload_rule); 11785 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11786 rc = copyin(uop->rule, op->rule, len); 11787 if (rc) { 11788 free(op->rule, M_CXGBE); 11789 free(op, M_CXGBE); 11790 return (rc); 11791 } 11792 11793 r = &op->rule[0]; 11794 for (i = 0; i < op->nrules; i++, r++) { 11795 11796 /* Validate open_type */ 11797 if (r->open_type != OPEN_TYPE_LISTEN && 11798 r->open_type != OPEN_TYPE_ACTIVE && 11799 r->open_type != OPEN_TYPE_PASSIVE && 11800 r->open_type != OPEN_TYPE_DONTCARE) { 11801 error: 11802 /* 11803 * Rules 0 to i have malloc'd filters that need to be 11804 * freed. Rules i+1 to nrules have userspace pointers 11805 * and should be left alone. 11806 */ 11807 op->nrules = i; 11808 free_offload_policy(op); 11809 return (rc); 11810 } 11811 11812 /* Validate settings */ 11813 s = &r->settings; 11814 if ((s->offload != 0 && s->offload != 1) || 11815 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 11816 s->sched_class < -1 || 11817 s->sched_class >= sc->params.nsched_cls) { 11818 rc = EINVAL; 11819 goto error; 11820 } 11821 11822 bf = &r->bpf_prog; 11823 u = bf->bf_insns; /* userspace ptr */ 11824 bf->bf_insns = NULL; 11825 if (bf->bf_len == 0) { 11826 /* legal, matches everything */ 11827 continue; 11828 } 11829 len = bf->bf_len * sizeof(*bf->bf_insns); 11830 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11831 rc = copyin(u, bf->bf_insns, len); 11832 if (rc != 0) 11833 goto error; 11834 11835 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 11836 rc = EINVAL; 11837 goto error; 11838 } 11839 } 11840 set_policy: 11841 rw_wlock(&sc->policy_lock); 11842 old = sc->policy; 11843 sc->policy = op; 11844 rw_wunlock(&sc->policy_lock); 11845 free_offload_policy(old); 11846 11847 return (0); 11848 } 11849 11850 #define MAX_READ_BUF_SIZE (128 * 1024) 11851 static int 11852 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 11853 { 11854 uint32_t addr, remaining, n; 11855 uint32_t *buf; 11856 int rc; 11857 uint8_t *dst; 11858 11859 mtx_lock(&sc->reg_lock); 11860 if (hw_off_limits(sc)) 11861 rc = ENXIO; 11862 else 11863 rc = validate_mem_range(sc, mr->addr, mr->len); 11864 mtx_unlock(&sc->reg_lock); 11865 if (rc != 0) 11866 return (rc); 11867 11868 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 11869 addr = mr->addr; 11870 remaining = mr->len; 11871 dst = (void *)mr->data; 11872 11873 while (remaining) { 11874 n = min(remaining, MAX_READ_BUF_SIZE); 11875 mtx_lock(&sc->reg_lock); 11876 if (hw_off_limits(sc)) 11877 rc = ENXIO; 11878 else 11879 read_via_memwin(sc, 2, addr, buf, n); 11880 mtx_unlock(&sc->reg_lock); 11881 if (rc != 0) 11882 break; 11883 11884 rc = copyout(buf, dst, n); 11885 if (rc != 0) 11886 break; 11887 11888 dst += n; 11889 remaining -= n; 11890 addr += n; 11891 } 11892 11893 free(buf, M_CXGBE); 11894 return (rc); 11895 } 11896 #undef MAX_READ_BUF_SIZE 11897 11898 static int 11899 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 11900 { 11901 int rc; 11902 11903 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 11904 return (EINVAL); 11905 11906 if (i2cd->len > sizeof(i2cd->data)) 11907 return (EFBIG); 11908 11909 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 11910 if (rc) 11911 return (rc); 11912 if (hw_off_limits(sc)) 11913 rc = ENXIO; 11914 else 11915 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 11916 i2cd->offset, i2cd->len, &i2cd->data[0]); 11917 end_synchronized_op(sc, 0); 11918 11919 return (rc); 11920 } 11921 11922 static int 11923 clear_stats(struct adapter *sc, u_int port_id) 11924 { 11925 int i, v, chan_map; 11926 struct port_info *pi; 11927 struct vi_info *vi; 11928 struct sge_rxq *rxq; 11929 struct sge_txq *txq; 11930 struct sge_wrq *wrq; 11931 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 11932 struct sge_ofld_txq *ofld_txq; 11933 #endif 11934 #ifdef TCP_OFFLOAD 11935 struct sge_ofld_rxq *ofld_rxq; 11936 #endif 11937 11938 if (port_id >= sc->params.nports) 11939 return (EINVAL); 11940 pi = sc->port[port_id]; 11941 if (pi == NULL) 11942 return (EIO); 11943 11944 mtx_lock(&sc->reg_lock); 11945 if (!hw_off_limits(sc)) { 11946 /* MAC stats */ 11947 t4_clr_port_stats(sc, pi->tx_chan); 11948 if (is_t6(sc)) { 11949 if (pi->fcs_reg != -1) 11950 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 11951 else 11952 pi->stats.rx_fcs_err = 0; 11953 } 11954 for_each_vi(pi, v, vi) { 11955 if (vi->flags & VI_INIT_DONE) 11956 t4_clr_vi_stats(sc, vi->vin); 11957 } 11958 chan_map = pi->rx_e_chan_map; 11959 v = 0; /* reuse */ 11960 while (chan_map) { 11961 i = ffs(chan_map) - 1; 11962 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 11963 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 11964 chan_map &= ~(1 << i); 11965 } 11966 } 11967 mtx_unlock(&sc->reg_lock); 11968 pi->tx_parse_error = 0; 11969 pi->tnl_cong_drops = 0; 11970 11971 /* 11972 * Since this command accepts a port, clear stats for 11973 * all VIs on this port. 11974 */ 11975 for_each_vi(pi, v, vi) { 11976 if (vi->flags & VI_INIT_DONE) { 11977 11978 for_each_rxq(vi, i, rxq) { 11979 #if defined(INET) || defined(INET6) 11980 rxq->lro.lro_queued = 0; 11981 rxq->lro.lro_flushed = 0; 11982 #endif 11983 rxq->rxcsum = 0; 11984 rxq->vlan_extraction = 0; 11985 rxq->vxlan_rxcsum = 0; 11986 11987 rxq->fl.cl_allocated = 0; 11988 rxq->fl.cl_recycled = 0; 11989 rxq->fl.cl_fast_recycled = 0; 11990 } 11991 11992 for_each_txq(vi, i, txq) { 11993 txq->txcsum = 0; 11994 txq->tso_wrs = 0; 11995 txq->vlan_insertion = 0; 11996 txq->imm_wrs = 0; 11997 txq->sgl_wrs = 0; 11998 txq->txpkt_wrs = 0; 11999 txq->txpkts0_wrs = 0; 12000 txq->txpkts1_wrs = 0; 12001 txq->txpkts0_pkts = 0; 12002 txq->txpkts1_pkts = 0; 12003 txq->txpkts_flush = 0; 12004 txq->raw_wrs = 0; 12005 txq->vxlan_tso_wrs = 0; 12006 txq->vxlan_txcsum = 0; 12007 txq->kern_tls_records = 0; 12008 txq->kern_tls_short = 0; 12009 txq->kern_tls_partial = 0; 12010 txq->kern_tls_full = 0; 12011 txq->kern_tls_octets = 0; 12012 txq->kern_tls_waste = 0; 12013 txq->kern_tls_options = 0; 12014 txq->kern_tls_header = 0; 12015 txq->kern_tls_fin = 0; 12016 txq->kern_tls_fin_short = 0; 12017 txq->kern_tls_cbc = 0; 12018 txq->kern_tls_gcm = 0; 12019 mp_ring_reset_stats(txq->r); 12020 } 12021 12022 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12023 for_each_ofld_txq(vi, i, ofld_txq) { 12024 ofld_txq->wrq.tx_wrs_direct = 0; 12025 ofld_txq->wrq.tx_wrs_copied = 0; 12026 counter_u64_zero(ofld_txq->tx_iscsi_pdus); 12027 counter_u64_zero(ofld_txq->tx_iscsi_octets); 12028 counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs); 12029 counter_u64_zero(ofld_txq->tx_aio_jobs); 12030 counter_u64_zero(ofld_txq->tx_aio_octets); 12031 counter_u64_zero(ofld_txq->tx_toe_tls_records); 12032 counter_u64_zero(ofld_txq->tx_toe_tls_octets); 12033 } 12034 #endif 12035 #ifdef TCP_OFFLOAD 12036 for_each_ofld_rxq(vi, i, ofld_rxq) { 12037 ofld_rxq->fl.cl_allocated = 0; 12038 ofld_rxq->fl.cl_recycled = 0; 12039 ofld_rxq->fl.cl_fast_recycled = 0; 12040 counter_u64_zero( 12041 ofld_rxq->rx_iscsi_ddp_setup_ok); 12042 counter_u64_zero( 12043 ofld_rxq->rx_iscsi_ddp_setup_error); 12044 ofld_rxq->rx_iscsi_ddp_pdus = 0; 12045 ofld_rxq->rx_iscsi_ddp_octets = 0; 12046 ofld_rxq->rx_iscsi_fl_pdus = 0; 12047 ofld_rxq->rx_iscsi_fl_octets = 0; 12048 ofld_rxq->rx_aio_ddp_jobs = 0; 12049 ofld_rxq->rx_aio_ddp_octets = 0; 12050 ofld_rxq->rx_toe_tls_records = 0; 12051 ofld_rxq->rx_toe_tls_octets = 0; 12052 ofld_rxq->rx_toe_ddp_octets = 0; 12053 counter_u64_zero(ofld_rxq->ddp_buffer_alloc); 12054 counter_u64_zero(ofld_rxq->ddp_buffer_reuse); 12055 counter_u64_zero(ofld_rxq->ddp_buffer_free); 12056 } 12057 #endif 12058 12059 if (IS_MAIN_VI(vi)) { 12060 wrq = &sc->sge.ctrlq[pi->port_id]; 12061 wrq->tx_wrs_direct = 0; 12062 wrq->tx_wrs_copied = 0; 12063 } 12064 } 12065 } 12066 12067 return (0); 12068 } 12069 12070 static int 12071 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12072 { 12073 #ifdef INET6 12074 struct in6_addr in6; 12075 12076 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12077 if (t4_get_clip_entry(sc, &in6, true) != NULL) 12078 return (0); 12079 else 12080 return (EIO); 12081 #else 12082 return (ENOTSUP); 12083 #endif 12084 } 12085 12086 static int 12087 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12088 { 12089 #ifdef INET6 12090 struct in6_addr in6; 12091 12092 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12093 return (t4_release_clip_addr(sc, &in6)); 12094 #else 12095 return (ENOTSUP); 12096 #endif 12097 } 12098 12099 int 12100 t4_os_find_pci_capability(struct adapter *sc, int cap) 12101 { 12102 int i; 12103 12104 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 12105 } 12106 12107 int 12108 t4_os_pci_save_state(struct adapter *sc) 12109 { 12110 device_t dev; 12111 struct pci_devinfo *dinfo; 12112 12113 dev = sc->dev; 12114 dinfo = device_get_ivars(dev); 12115 12116 pci_cfg_save(dev, dinfo, 0); 12117 return (0); 12118 } 12119 12120 int 12121 t4_os_pci_restore_state(struct adapter *sc) 12122 { 12123 device_t dev; 12124 struct pci_devinfo *dinfo; 12125 12126 dev = sc->dev; 12127 dinfo = device_get_ivars(dev); 12128 12129 pci_cfg_restore(dev, dinfo); 12130 return (0); 12131 } 12132 12133 void 12134 t4_os_portmod_changed(struct port_info *pi) 12135 { 12136 struct adapter *sc = pi->adapter; 12137 struct vi_info *vi; 12138 if_t ifp; 12139 static const char *mod_str[] = { 12140 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 12141 }; 12142 12143 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 12144 ("%s: port_type %u", __func__, pi->port_type)); 12145 12146 vi = &pi->vi[0]; 12147 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 12148 PORT_LOCK(pi); 12149 build_medialist(pi); 12150 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 12151 fixup_link_config(pi); 12152 apply_link_config(pi); 12153 } 12154 PORT_UNLOCK(pi); 12155 end_synchronized_op(sc, LOCK_HELD); 12156 } 12157 12158 ifp = vi->ifp; 12159 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 12160 if_printf(ifp, "transceiver unplugged.\n"); 12161 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 12162 if_printf(ifp, "unknown transceiver inserted.\n"); 12163 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 12164 if_printf(ifp, "unsupported transceiver inserted.\n"); 12165 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 12166 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 12167 port_top_speed(pi), mod_str[pi->mod_type]); 12168 } else { 12169 if_printf(ifp, "transceiver (type %d) inserted.\n", 12170 pi->mod_type); 12171 } 12172 } 12173 12174 void 12175 t4_os_link_changed(struct port_info *pi) 12176 { 12177 struct vi_info *vi; 12178 if_t ifp; 12179 struct link_config *lc = &pi->link_cfg; 12180 struct adapter *sc = pi->adapter; 12181 int v; 12182 12183 PORT_LOCK_ASSERT_OWNED(pi); 12184 12185 if (is_t6(sc)) { 12186 if (lc->link_ok) { 12187 if (lc->speed > 25000 || 12188 (lc->speed == 25000 && lc->fec == FEC_RS)) { 12189 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12190 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS); 12191 } else { 12192 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12193 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS); 12194 } 12195 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 12196 pi->stats.rx_fcs_err = 0; 12197 } else { 12198 pi->fcs_reg = -1; 12199 } 12200 } else { 12201 MPASS(pi->fcs_reg != -1); 12202 MPASS(pi->fcs_base == 0); 12203 } 12204 12205 for_each_vi(pi, v, vi) { 12206 ifp = vi->ifp; 12207 if (ifp == NULL || IS_DETACHING(vi)) 12208 continue; 12209 12210 if (lc->link_ok) { 12211 if_setbaudrate(ifp, IF_Mbps(lc->speed)); 12212 if_link_state_change(ifp, LINK_STATE_UP); 12213 } else { 12214 if_link_state_change(ifp, LINK_STATE_DOWN); 12215 } 12216 } 12217 } 12218 12219 void 12220 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 12221 { 12222 struct adapter *sc; 12223 12224 sx_slock(&t4_list_lock); 12225 SLIST_FOREACH(sc, &t4_list, link) { 12226 /* 12227 * func should not make any assumptions about what state sc is 12228 * in - the only guarantee is that sc->sc_lock is a valid lock. 12229 */ 12230 func(sc, arg); 12231 } 12232 sx_sunlock(&t4_list_lock); 12233 } 12234 12235 static int 12236 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 12237 struct thread *td) 12238 { 12239 int rc; 12240 struct adapter *sc = dev->si_drv1; 12241 12242 rc = priv_check(td, PRIV_DRIVER); 12243 if (rc != 0) 12244 return (rc); 12245 12246 switch (cmd) { 12247 case CHELSIO_T4_GETREG: { 12248 struct t4_reg *edata = (struct t4_reg *)data; 12249 12250 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12251 return (EFAULT); 12252 12253 mtx_lock(&sc->reg_lock); 12254 if (hw_off_limits(sc)) 12255 rc = ENXIO; 12256 else if (edata->size == 4) 12257 edata->val = t4_read_reg(sc, edata->addr); 12258 else if (edata->size == 8) 12259 edata->val = t4_read_reg64(sc, edata->addr); 12260 else 12261 rc = EINVAL; 12262 mtx_unlock(&sc->reg_lock); 12263 12264 break; 12265 } 12266 case CHELSIO_T4_SETREG: { 12267 struct t4_reg *edata = (struct t4_reg *)data; 12268 12269 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12270 return (EFAULT); 12271 12272 mtx_lock(&sc->reg_lock); 12273 if (hw_off_limits(sc)) 12274 rc = ENXIO; 12275 else if (edata->size == 4) { 12276 if (edata->val & 0xffffffff00000000) 12277 rc = EINVAL; 12278 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 12279 } else if (edata->size == 8) 12280 t4_write_reg64(sc, edata->addr, edata->val); 12281 else 12282 rc = EINVAL; 12283 mtx_unlock(&sc->reg_lock); 12284 12285 break; 12286 } 12287 case CHELSIO_T4_REGDUMP: { 12288 struct t4_regdump *regs = (struct t4_regdump *)data; 12289 int reglen = t4_get_regs_len(sc); 12290 uint8_t *buf; 12291 12292 if (regs->len < reglen) { 12293 regs->len = reglen; /* hint to the caller */ 12294 return (ENOBUFS); 12295 } 12296 12297 regs->len = reglen; 12298 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 12299 mtx_lock(&sc->reg_lock); 12300 if (hw_off_limits(sc)) 12301 rc = ENXIO; 12302 else 12303 get_regs(sc, regs, buf); 12304 mtx_unlock(&sc->reg_lock); 12305 if (rc == 0) 12306 rc = copyout(buf, regs->data, reglen); 12307 free(buf, M_CXGBE); 12308 break; 12309 } 12310 case CHELSIO_T4_GET_FILTER_MODE: 12311 rc = get_filter_mode(sc, (uint32_t *)data); 12312 break; 12313 case CHELSIO_T4_SET_FILTER_MODE: 12314 rc = set_filter_mode(sc, *(uint32_t *)data); 12315 break; 12316 case CHELSIO_T4_SET_FILTER_MASK: 12317 rc = set_filter_mask(sc, *(uint32_t *)data); 12318 break; 12319 case CHELSIO_T4_GET_FILTER: 12320 rc = get_filter(sc, (struct t4_filter *)data); 12321 break; 12322 case CHELSIO_T4_SET_FILTER: 12323 rc = set_filter(sc, (struct t4_filter *)data); 12324 break; 12325 case CHELSIO_T4_DEL_FILTER: 12326 rc = del_filter(sc, (struct t4_filter *)data); 12327 break; 12328 case CHELSIO_T4_GET_SGE_CONTEXT: 12329 rc = get_sge_context(sc, (struct t4_sge_context *)data); 12330 break; 12331 case CHELSIO_T4_LOAD_FW: 12332 rc = load_fw(sc, (struct t4_data *)data); 12333 break; 12334 case CHELSIO_T4_GET_MEM: 12335 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 12336 break; 12337 case CHELSIO_T4_GET_I2C: 12338 rc = read_i2c(sc, (struct t4_i2c_data *)data); 12339 break; 12340 case CHELSIO_T4_CLEAR_STATS: 12341 rc = clear_stats(sc, *(uint32_t *)data); 12342 break; 12343 case CHELSIO_T4_SCHED_CLASS: 12344 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 12345 break; 12346 case CHELSIO_T4_SCHED_QUEUE: 12347 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 12348 break; 12349 case CHELSIO_T4_GET_TRACER: 12350 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 12351 break; 12352 case CHELSIO_T4_SET_TRACER: 12353 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 12354 break; 12355 case CHELSIO_T4_LOAD_CFG: 12356 rc = load_cfg(sc, (struct t4_data *)data); 12357 break; 12358 case CHELSIO_T4_LOAD_BOOT: 12359 rc = load_boot(sc, (struct t4_bootrom *)data); 12360 break; 12361 case CHELSIO_T4_LOAD_BOOTCFG: 12362 rc = load_bootcfg(sc, (struct t4_data *)data); 12363 break; 12364 case CHELSIO_T4_CUDBG_DUMP: 12365 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 12366 break; 12367 case CHELSIO_T4_SET_OFLD_POLICY: 12368 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 12369 break; 12370 case CHELSIO_T4_HOLD_CLIP_ADDR: 12371 rc = hold_clip_addr(sc, (struct t4_clip_addr *)data); 12372 break; 12373 case CHELSIO_T4_RELEASE_CLIP_ADDR: 12374 rc = release_clip_addr(sc, (struct t4_clip_addr *)data); 12375 break; 12376 default: 12377 rc = ENOTTY; 12378 } 12379 12380 return (rc); 12381 } 12382 12383 #ifdef TCP_OFFLOAD 12384 int 12385 toe_capability(struct vi_info *vi, bool enable) 12386 { 12387 int rc; 12388 struct port_info *pi = vi->pi; 12389 struct adapter *sc = pi->adapter; 12390 12391 ASSERT_SYNCHRONIZED_OP(sc); 12392 12393 if (!is_offload(sc)) 12394 return (ENODEV); 12395 if (hw_off_limits(sc)) 12396 return (ENXIO); 12397 12398 if (enable) { 12399 #ifdef KERN_TLS 12400 if (sc->flags & KERN_TLS_ON && is_t6(sc)) { 12401 int i, j, n; 12402 struct port_info *p; 12403 struct vi_info *v; 12404 12405 /* 12406 * Reconfigure hardware for TOE if TXTLS is not enabled 12407 * on any ifnet. 12408 */ 12409 n = 0; 12410 for_each_port(sc, i) { 12411 p = sc->port[i]; 12412 for_each_vi(p, j, v) { 12413 if (if_getcapenable(v->ifp) & IFCAP_TXTLS) { 12414 CH_WARN(sc, 12415 "%s has NIC TLS enabled.\n", 12416 device_get_nameunit(v->dev)); 12417 n++; 12418 } 12419 } 12420 } 12421 if (n > 0) { 12422 CH_WARN(sc, "Disable NIC TLS on all interfaces " 12423 "associated with this adapter before " 12424 "trying to enable TOE.\n"); 12425 return (EAGAIN); 12426 } 12427 rc = t6_config_kern_tls(sc, false); 12428 if (rc) 12429 return (rc); 12430 } 12431 #endif 12432 if ((if_getcapenable(vi->ifp) & IFCAP_TOE) != 0) { 12433 /* TOE is already enabled. */ 12434 return (0); 12435 } 12436 12437 /* 12438 * We need the port's queues around so that we're able to send 12439 * and receive CPLs to/from the TOE even if the ifnet for this 12440 * port has never been UP'd administratively. 12441 */ 12442 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 12443 return (rc); 12444 if (!(pi->vi[0].flags & VI_INIT_DONE) && 12445 ((rc = vi_init(&pi->vi[0])) != 0)) 12446 return (rc); 12447 12448 if (isset(&sc->offload_map, pi->port_id)) { 12449 /* TOE is enabled on another VI of this port. */ 12450 MPASS(pi->uld_vis > 0); 12451 pi->uld_vis++; 12452 return (0); 12453 } 12454 12455 if (!uld_active(sc, ULD_TOM)) { 12456 rc = t4_activate_uld(sc, ULD_TOM); 12457 if (rc == EAGAIN) { 12458 log(LOG_WARNING, 12459 "You must kldload t4_tom.ko before trying " 12460 "to enable TOE on a cxgbe interface.\n"); 12461 } 12462 if (rc != 0) 12463 return (rc); 12464 KASSERT(sc->tom_softc != NULL, 12465 ("%s: TOM activated but softc NULL", __func__)); 12466 KASSERT(uld_active(sc, ULD_TOM), 12467 ("%s: TOM activated but flag not set", __func__)); 12468 } 12469 12470 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 12471 if (!uld_active(sc, ULD_IWARP)) 12472 (void) t4_activate_uld(sc, ULD_IWARP); 12473 if (!uld_active(sc, ULD_ISCSI)) 12474 (void) t4_activate_uld(sc, ULD_ISCSI); 12475 12476 if (pi->uld_vis++ == 0) 12477 setbit(&sc->offload_map, pi->port_id); 12478 } else { 12479 if ((if_getcapenable(vi->ifp) & IFCAP_TOE) == 0) { 12480 /* TOE is already disabled. */ 12481 return (0); 12482 } 12483 MPASS(isset(&sc->offload_map, pi->port_id)); 12484 MPASS(pi->uld_vis > 0); 12485 if (--pi->uld_vis == 0) 12486 clrbit(&sc->offload_map, pi->port_id); 12487 } 12488 12489 return (0); 12490 } 12491 12492 /* 12493 * Add an upper layer driver to the global list. 12494 */ 12495 int 12496 t4_register_uld(struct uld_info *ui, int id) 12497 { 12498 int rc; 12499 12500 if (id < 0 || id > ULD_MAX) 12501 return (EINVAL); 12502 sx_xlock(&t4_uld_list_lock); 12503 if (t4_uld_list[id] != NULL) 12504 rc = EEXIST; 12505 else { 12506 t4_uld_list[id] = ui; 12507 rc = 0; 12508 } 12509 sx_xunlock(&t4_uld_list_lock); 12510 return (rc); 12511 } 12512 12513 int 12514 t4_unregister_uld(struct uld_info *ui, int id) 12515 { 12516 12517 if (id < 0 || id > ULD_MAX) 12518 return (EINVAL); 12519 sx_xlock(&t4_uld_list_lock); 12520 MPASS(t4_uld_list[id] == ui); 12521 t4_uld_list[id] = NULL; 12522 sx_xunlock(&t4_uld_list_lock); 12523 return (0); 12524 } 12525 12526 int 12527 t4_activate_uld(struct adapter *sc, int id) 12528 { 12529 int rc; 12530 12531 ASSERT_SYNCHRONIZED_OP(sc); 12532 12533 if (id < 0 || id > ULD_MAX) 12534 return (EINVAL); 12535 12536 /* Adapter needs to be initialized before any ULD can be activated. */ 12537 if (!(sc->flags & FULL_INIT_DONE)) { 12538 rc = adapter_init(sc); 12539 if (rc != 0) 12540 return (rc); 12541 } 12542 12543 sx_slock(&t4_uld_list_lock); 12544 if (t4_uld_list[id] == NULL) 12545 rc = EAGAIN; /* load the KLD with this ULD and try again. */ 12546 else { 12547 rc = t4_uld_list[id]->uld_activate(sc); 12548 if (rc == 0) 12549 setbit(&sc->active_ulds, id); 12550 } 12551 sx_sunlock(&t4_uld_list_lock); 12552 12553 return (rc); 12554 } 12555 12556 int 12557 t4_deactivate_uld(struct adapter *sc, int id) 12558 { 12559 int rc; 12560 12561 ASSERT_SYNCHRONIZED_OP(sc); 12562 12563 if (id < 0 || id > ULD_MAX) 12564 return (EINVAL); 12565 12566 sx_slock(&t4_uld_list_lock); 12567 if (t4_uld_list[id] == NULL) 12568 rc = ENXIO; 12569 else { 12570 rc = t4_uld_list[id]->uld_deactivate(sc); 12571 if (rc == 0) 12572 clrbit(&sc->active_ulds, id); 12573 } 12574 sx_sunlock(&t4_uld_list_lock); 12575 12576 return (rc); 12577 } 12578 12579 static int 12580 deactivate_all_uld(struct adapter *sc) 12581 { 12582 int i, rc; 12583 12584 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld"); 12585 if (rc != 0) 12586 return (ENXIO); 12587 sx_slock(&t4_uld_list_lock); 12588 for (i = 0; i <= ULD_MAX; i++) { 12589 if (t4_uld_list[i] == NULL || !uld_active(sc, i)) 12590 continue; 12591 rc = t4_uld_list[i]->uld_deactivate(sc); 12592 if (rc != 0) 12593 break; 12594 clrbit(&sc->active_ulds, i); 12595 } 12596 sx_sunlock(&t4_uld_list_lock); 12597 end_synchronized_op(sc, 0); 12598 12599 return (rc); 12600 } 12601 12602 static void 12603 stop_all_uld(struct adapter *sc) 12604 { 12605 int i; 12606 12607 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldst") != 0) 12608 return; 12609 sx_slock(&t4_uld_list_lock); 12610 for (i = 0; i <= ULD_MAX; i++) { 12611 if (t4_uld_list[i] == NULL || !uld_active(sc, i) || 12612 t4_uld_list[i]->uld_stop == NULL) 12613 continue; 12614 (void) t4_uld_list[i]->uld_stop(sc); 12615 } 12616 sx_sunlock(&t4_uld_list_lock); 12617 end_synchronized_op(sc, 0); 12618 } 12619 12620 static void 12621 restart_all_uld(struct adapter *sc) 12622 { 12623 int i; 12624 12625 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldre") != 0) 12626 return; 12627 sx_slock(&t4_uld_list_lock); 12628 for (i = 0; i <= ULD_MAX; i++) { 12629 if (t4_uld_list[i] == NULL || !uld_active(sc, i) || 12630 t4_uld_list[i]->uld_restart == NULL) 12631 continue; 12632 (void) t4_uld_list[i]->uld_restart(sc); 12633 } 12634 sx_sunlock(&t4_uld_list_lock); 12635 end_synchronized_op(sc, 0); 12636 } 12637 12638 int 12639 uld_active(struct adapter *sc, int id) 12640 { 12641 12642 MPASS(id >= 0 && id <= ULD_MAX); 12643 12644 return (isset(&sc->active_ulds, id)); 12645 } 12646 #endif 12647 12648 #ifdef KERN_TLS 12649 static int 12650 ktls_capability(struct adapter *sc, bool enable) 12651 { 12652 ASSERT_SYNCHRONIZED_OP(sc); 12653 12654 if (!is_ktls(sc)) 12655 return (ENODEV); 12656 if (!is_t6(sc)) 12657 return (0); 12658 if (hw_off_limits(sc)) 12659 return (ENXIO); 12660 12661 if (enable) { 12662 if (sc->flags & KERN_TLS_ON) 12663 return (0); /* already on */ 12664 if (sc->offload_map != 0) { 12665 CH_WARN(sc, 12666 "Disable TOE on all interfaces associated with " 12667 "this adapter before trying to enable NIC TLS.\n"); 12668 return (EAGAIN); 12669 } 12670 return (t6_config_kern_tls(sc, true)); 12671 } else { 12672 /* 12673 * Nothing to do for disable. If TOE is enabled sometime later 12674 * then toe_capability will reconfigure the hardware. 12675 */ 12676 return (0); 12677 } 12678 } 12679 #endif 12680 12681 /* 12682 * t = ptr to tunable. 12683 * nc = number of CPUs. 12684 * c = compiled in default for that tunable. 12685 */ 12686 static void 12687 calculate_nqueues(int *t, int nc, const int c) 12688 { 12689 int nq; 12690 12691 if (*t > 0) 12692 return; 12693 nq = *t < 0 ? -*t : c; 12694 *t = min(nc, nq); 12695 } 12696 12697 /* 12698 * Come up with reasonable defaults for some of the tunables, provided they're 12699 * not set by the user (in which case we'll use the values as is). 12700 */ 12701 static void 12702 tweak_tunables(void) 12703 { 12704 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 12705 12706 if (t4_ntxq < 1) { 12707 #ifdef RSS 12708 t4_ntxq = rss_getnumbuckets(); 12709 #else 12710 calculate_nqueues(&t4_ntxq, nc, NTXQ); 12711 #endif 12712 } 12713 12714 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 12715 12716 if (t4_nrxq < 1) { 12717 #ifdef RSS 12718 t4_nrxq = rss_getnumbuckets(); 12719 #else 12720 calculate_nqueues(&t4_nrxq, nc, NRXQ); 12721 #endif 12722 } 12723 12724 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 12725 12726 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12727 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 12728 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 12729 #endif 12730 #ifdef TCP_OFFLOAD 12731 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 12732 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 12733 #endif 12734 12735 #if defined(TCP_OFFLOAD) || defined(KERN_TLS) 12736 if (t4_toecaps_allowed == -1) 12737 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 12738 #else 12739 if (t4_toecaps_allowed == -1) 12740 t4_toecaps_allowed = 0; 12741 #endif 12742 12743 #ifdef TCP_OFFLOAD 12744 if (t4_rdmacaps_allowed == -1) { 12745 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 12746 FW_CAPS_CONFIG_RDMA_RDMAC; 12747 } 12748 12749 if (t4_iscsicaps_allowed == -1) { 12750 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 12751 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 12752 FW_CAPS_CONFIG_ISCSI_T10DIF; 12753 } 12754 12755 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 12756 t4_tmr_idx_ofld = TMR_IDX_OFLD; 12757 12758 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 12759 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 12760 #else 12761 if (t4_rdmacaps_allowed == -1) 12762 t4_rdmacaps_allowed = 0; 12763 12764 if (t4_iscsicaps_allowed == -1) 12765 t4_iscsicaps_allowed = 0; 12766 #endif 12767 12768 #ifdef DEV_NETMAP 12769 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ); 12770 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ); 12771 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 12772 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 12773 #endif 12774 12775 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 12776 t4_tmr_idx = TMR_IDX; 12777 12778 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 12779 t4_pktc_idx = PKTC_IDX; 12780 12781 if (t4_qsize_txq < 128) 12782 t4_qsize_txq = 128; 12783 12784 if (t4_qsize_rxq < 128) 12785 t4_qsize_rxq = 128; 12786 while (t4_qsize_rxq & 7) 12787 t4_qsize_rxq++; 12788 12789 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 12790 12791 /* 12792 * Number of VIs to create per-port. The first VI is the "main" regular 12793 * VI for the port. The rest are additional virtual interfaces on the 12794 * same physical port. Note that the main VI does not have native 12795 * netmap support but the extra VIs do. 12796 * 12797 * Limit the number of VIs per port to the number of available 12798 * MAC addresses per port. 12799 */ 12800 if (t4_num_vis < 1) 12801 t4_num_vis = 1; 12802 if (t4_num_vis > nitems(vi_mac_funcs)) { 12803 t4_num_vis = nitems(vi_mac_funcs); 12804 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 12805 } 12806 12807 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 12808 pcie_relaxed_ordering = 1; 12809 #if defined(__i386__) || defined(__amd64__) 12810 if (cpu_vendor_id == CPU_VENDOR_INTEL) 12811 pcie_relaxed_ordering = 0; 12812 #endif 12813 } 12814 } 12815 12816 #ifdef DDB 12817 static void 12818 t4_dump_mem(struct adapter *sc, u_int addr, u_int len) 12819 { 12820 uint32_t base, j, off, pf, reg, save, win_pos; 12821 12822 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 12823 save = t4_read_reg(sc, reg); 12824 base = sc->memwin[2].mw_base; 12825 12826 if (is_t4(sc)) { 12827 pf = 0; 12828 win_pos = addr & ~0xf; /* start must be 16B aligned */ 12829 } else { 12830 pf = V_PFNUM(sc->pf); 12831 win_pos = addr & ~0x7f; /* start must be 128B aligned */ 12832 } 12833 off = addr - win_pos; 12834 t4_write_reg(sc, reg, win_pos | pf); 12835 t4_read_reg(sc, reg); 12836 12837 while (len > 0 && !db_pager_quit) { 12838 uint32_t buf[8]; 12839 for (j = 0; j < 8; j++, off += 4) 12840 buf[j] = htonl(t4_read_reg(sc, base + off)); 12841 12842 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 12843 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 12844 buf[7]); 12845 if (len <= sizeof(buf)) 12846 len = 0; 12847 else 12848 len -= sizeof(buf); 12849 } 12850 12851 t4_write_reg(sc, reg, save); 12852 t4_read_reg(sc, reg); 12853 } 12854 12855 static void 12856 t4_dump_tcb(struct adapter *sc, int tid) 12857 { 12858 uint32_t tcb_addr; 12859 12860 /* Dump TCB for the tid */ 12861 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 12862 tcb_addr += tid * TCB_SIZE; 12863 t4_dump_mem(sc, tcb_addr, TCB_SIZE); 12864 } 12865 12866 static void 12867 t4_dump_devlog(struct adapter *sc) 12868 { 12869 struct devlog_params *dparams = &sc->params.devlog; 12870 struct fw_devlog_e e; 12871 int i, first, j, m, nentries, rc; 12872 uint64_t ftstamp = UINT64_MAX; 12873 12874 if (dparams->start == 0) { 12875 db_printf("devlog params not valid\n"); 12876 return; 12877 } 12878 12879 nentries = dparams->size / sizeof(struct fw_devlog_e); 12880 m = fwmtype_to_hwmtype(dparams->memtype); 12881 12882 /* Find the first entry. */ 12883 first = -1; 12884 for (i = 0; i < nentries && !db_pager_quit; i++) { 12885 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12886 sizeof(e), (void *)&e); 12887 if (rc != 0) 12888 break; 12889 12890 if (e.timestamp == 0) 12891 break; 12892 12893 e.timestamp = be64toh(e.timestamp); 12894 if (e.timestamp < ftstamp) { 12895 ftstamp = e.timestamp; 12896 first = i; 12897 } 12898 } 12899 12900 if (first == -1) 12901 return; 12902 12903 i = first; 12904 do { 12905 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12906 sizeof(e), (void *)&e); 12907 if (rc != 0) 12908 return; 12909 12910 if (e.timestamp == 0) 12911 return; 12912 12913 e.timestamp = be64toh(e.timestamp); 12914 e.seqno = be32toh(e.seqno); 12915 for (j = 0; j < 8; j++) 12916 e.params[j] = be32toh(e.params[j]); 12917 12918 db_printf("%10d %15ju %8s %8s ", 12919 e.seqno, e.timestamp, 12920 (e.level < nitems(devlog_level_strings) ? 12921 devlog_level_strings[e.level] : "UNKNOWN"), 12922 (e.facility < nitems(devlog_facility_strings) ? 12923 devlog_facility_strings[e.facility] : "UNKNOWN")); 12924 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 12925 e.params[3], e.params[4], e.params[5], e.params[6], 12926 e.params[7]); 12927 12928 if (++i == nentries) 12929 i = 0; 12930 } while (i != first && !db_pager_quit); 12931 } 12932 12933 static DB_DEFINE_TABLE(show, t4, show_t4); 12934 12935 DB_TABLE_COMMAND_FLAGS(show_t4, devlog, db_show_devlog, CS_OWN) 12936 { 12937 device_t dev; 12938 int t; 12939 bool valid; 12940 12941 valid = false; 12942 t = db_read_token(); 12943 if (t == tIDENT) { 12944 dev = device_lookup_by_name(db_tok_string); 12945 valid = true; 12946 } 12947 db_skip_to_eol(); 12948 if (!valid) { 12949 db_printf("usage: show t4 devlog <nexus>\n"); 12950 return; 12951 } 12952 12953 if (dev == NULL) { 12954 db_printf("device not found\n"); 12955 return; 12956 } 12957 12958 t4_dump_devlog(device_get_softc(dev)); 12959 } 12960 12961 DB_TABLE_COMMAND_FLAGS(show_t4, tcb, db_show_t4tcb, CS_OWN) 12962 { 12963 device_t dev; 12964 int radix, tid, t; 12965 bool valid; 12966 12967 valid = false; 12968 radix = db_radix; 12969 db_radix = 10; 12970 t = db_read_token(); 12971 if (t == tIDENT) { 12972 dev = device_lookup_by_name(db_tok_string); 12973 t = db_read_token(); 12974 if (t == tNUMBER) { 12975 tid = db_tok_number; 12976 valid = true; 12977 } 12978 } 12979 db_radix = radix; 12980 db_skip_to_eol(); 12981 if (!valid) { 12982 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 12983 return; 12984 } 12985 12986 if (dev == NULL) { 12987 db_printf("device not found\n"); 12988 return; 12989 } 12990 if (tid < 0) { 12991 db_printf("invalid tid\n"); 12992 return; 12993 } 12994 12995 t4_dump_tcb(device_get_softc(dev), tid); 12996 } 12997 12998 DB_TABLE_COMMAND_FLAGS(show_t4, memdump, db_show_memdump, CS_OWN) 12999 { 13000 device_t dev; 13001 int radix, t; 13002 bool valid; 13003 13004 valid = false; 13005 radix = db_radix; 13006 db_radix = 10; 13007 t = db_read_token(); 13008 if (t == tIDENT) { 13009 dev = device_lookup_by_name(db_tok_string); 13010 t = db_read_token(); 13011 if (t == tNUMBER) { 13012 addr = db_tok_number; 13013 t = db_read_token(); 13014 if (t == tNUMBER) { 13015 count = db_tok_number; 13016 valid = true; 13017 } 13018 } 13019 } 13020 db_radix = radix; 13021 db_skip_to_eol(); 13022 if (!valid) { 13023 db_printf("usage: show t4 memdump <nexus> <addr> <len>\n"); 13024 return; 13025 } 13026 13027 if (dev == NULL) { 13028 db_printf("device not found\n"); 13029 return; 13030 } 13031 if (addr < 0) { 13032 db_printf("invalid address\n"); 13033 return; 13034 } 13035 if (count <= 0) { 13036 db_printf("invalid length\n"); 13037 return; 13038 } 13039 13040 t4_dump_mem(device_get_softc(dev), addr, count); 13041 } 13042 #endif 13043 13044 static eventhandler_tag vxlan_start_evtag; 13045 static eventhandler_tag vxlan_stop_evtag; 13046 13047 struct vxlan_evargs { 13048 if_t ifp; 13049 uint16_t port; 13050 }; 13051 13052 static void 13053 enable_vxlan_rx(struct adapter *sc) 13054 { 13055 int i, rc; 13056 struct port_info *pi; 13057 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 13058 13059 ASSERT_SYNCHRONIZED_OP(sc); 13060 13061 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) | 13062 F_VXLAN_EN); 13063 for_each_port(sc, i) { 13064 pi = sc->port[i]; 13065 if (pi->vxlan_tcam_entry == true) 13066 continue; 13067 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac, 13068 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 13069 true); 13070 if (rc < 0) { 13071 rc = -rc; 13072 CH_ERR(&pi->vi[0], 13073 "failed to add VXLAN TCAM entry: %d.\n", rc); 13074 } else { 13075 MPASS(rc == sc->rawf_base + pi->port_id); 13076 pi->vxlan_tcam_entry = true; 13077 } 13078 } 13079 } 13080 13081 static void 13082 t4_vxlan_start(struct adapter *sc, void *arg) 13083 { 13084 struct vxlan_evargs *v = arg; 13085 13086 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13087 return; 13088 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0) 13089 return; 13090 13091 if (sc->vxlan_refcount == 0) { 13092 sc->vxlan_port = v->port; 13093 sc->vxlan_refcount = 1; 13094 if (!hw_off_limits(sc)) 13095 enable_vxlan_rx(sc); 13096 } else if (sc->vxlan_port == v->port) { 13097 sc->vxlan_refcount++; 13098 } else { 13099 CH_ERR(sc, "VXLAN already configured on port %d; " 13100 "ignoring attempt to configure it on port %d\n", 13101 sc->vxlan_port, v->port); 13102 } 13103 end_synchronized_op(sc, 0); 13104 } 13105 13106 static void 13107 t4_vxlan_stop(struct adapter *sc, void *arg) 13108 { 13109 struct vxlan_evargs *v = arg; 13110 13111 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13112 return; 13113 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0) 13114 return; 13115 13116 /* 13117 * VXLANs may have been configured before the driver was loaded so we 13118 * may see more stops than starts. This is not handled cleanly but at 13119 * least we keep the refcount sane. 13120 */ 13121 if (sc->vxlan_port != v->port) 13122 goto done; 13123 if (sc->vxlan_refcount == 0) { 13124 CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; " 13125 "ignoring attempt to stop it again.\n", sc->vxlan_port); 13126 } else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc)) 13127 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0); 13128 done: 13129 end_synchronized_op(sc, 0); 13130 } 13131 13132 static void 13133 t4_vxlan_start_handler(void *arg __unused, if_t ifp, 13134 sa_family_t family, u_int port) 13135 { 13136 struct vxlan_evargs v; 13137 13138 MPASS(family == AF_INET || family == AF_INET6); 13139 v.ifp = ifp; 13140 v.port = port; 13141 13142 t4_iterate(t4_vxlan_start, &v); 13143 } 13144 13145 static void 13146 t4_vxlan_stop_handler(void *arg __unused, if_t ifp, sa_family_t family, 13147 u_int port) 13148 { 13149 struct vxlan_evargs v; 13150 13151 MPASS(family == AF_INET || family == AF_INET6); 13152 v.ifp = ifp; 13153 v.port = port; 13154 13155 t4_iterate(t4_vxlan_stop, &v); 13156 } 13157 13158 13159 static struct sx mlu; /* mod load unload */ 13160 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 13161 13162 static int 13163 mod_event(module_t mod, int cmd, void *arg) 13164 { 13165 int rc = 0; 13166 static int loaded = 0; 13167 13168 switch (cmd) { 13169 case MOD_LOAD: 13170 sx_xlock(&mlu); 13171 if (loaded++ == 0) { 13172 t4_sge_modload(); 13173 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13174 t4_filter_rpl, CPL_COOKIE_FILTER); 13175 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 13176 do_l2t_write_rpl, CPL_COOKIE_FILTER); 13177 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 13178 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 13179 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13180 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 13181 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 13182 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 13183 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 13184 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 13185 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 13186 do_smt_write_rpl); 13187 sx_init(&t4_list_lock, "T4/T5 adapters"); 13188 SLIST_INIT(&t4_list); 13189 callout_init(&fatal_callout, 1); 13190 #ifdef TCP_OFFLOAD 13191 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 13192 #endif 13193 #ifdef INET6 13194 t4_clip_modload(); 13195 #endif 13196 #ifdef KERN_TLS 13197 t6_ktls_modload(); 13198 #endif 13199 t4_tracer_modload(); 13200 tweak_tunables(); 13201 vxlan_start_evtag = 13202 EVENTHANDLER_REGISTER(vxlan_start, 13203 t4_vxlan_start_handler, NULL, 13204 EVENTHANDLER_PRI_ANY); 13205 vxlan_stop_evtag = 13206 EVENTHANDLER_REGISTER(vxlan_stop, 13207 t4_vxlan_stop_handler, NULL, 13208 EVENTHANDLER_PRI_ANY); 13209 reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK, 13210 taskqueue_thread_enqueue, &reset_tq); 13211 taskqueue_start_threads(&reset_tq, 1, PI_SOFT, 13212 "t4_rst_thr"); 13213 } 13214 sx_xunlock(&mlu); 13215 break; 13216 13217 case MOD_UNLOAD: 13218 sx_xlock(&mlu); 13219 if (--loaded == 0) { 13220 #ifdef TCP_OFFLOAD 13221 int i; 13222 #endif 13223 int tries; 13224 13225 taskqueue_free(reset_tq); 13226 13227 tries = 0; 13228 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 13229 uprintf("%ju clusters with custom free routine " 13230 "still is use.\n", t4_sge_extfree_refs()); 13231 pause("t4unload", 2 * hz); 13232 } 13233 13234 sx_slock(&t4_list_lock); 13235 if (!SLIST_EMPTY(&t4_list)) { 13236 rc = EBUSY; 13237 sx_sunlock(&t4_list_lock); 13238 goto done_unload; 13239 } 13240 #ifdef TCP_OFFLOAD 13241 sx_slock(&t4_uld_list_lock); 13242 for (i = 0; i <= ULD_MAX; i++) { 13243 if (t4_uld_list[i] != NULL) { 13244 rc = EBUSY; 13245 sx_sunlock(&t4_uld_list_lock); 13246 sx_sunlock(&t4_list_lock); 13247 goto done_unload; 13248 } 13249 } 13250 sx_sunlock(&t4_uld_list_lock); 13251 #endif 13252 sx_sunlock(&t4_list_lock); 13253 13254 if (t4_sge_extfree_refs() == 0) { 13255 EVENTHANDLER_DEREGISTER(vxlan_start, 13256 vxlan_start_evtag); 13257 EVENTHANDLER_DEREGISTER(vxlan_stop, 13258 vxlan_stop_evtag); 13259 t4_tracer_modunload(); 13260 #ifdef KERN_TLS 13261 t6_ktls_modunload(); 13262 #endif 13263 #ifdef INET6 13264 t4_clip_modunload(); 13265 #endif 13266 #ifdef TCP_OFFLOAD 13267 sx_destroy(&t4_uld_list_lock); 13268 #endif 13269 sx_destroy(&t4_list_lock); 13270 t4_sge_modunload(); 13271 loaded = 0; 13272 } else { 13273 rc = EBUSY; 13274 loaded++; /* undo earlier decrement */ 13275 } 13276 } 13277 done_unload: 13278 sx_xunlock(&mlu); 13279 break; 13280 } 13281 13282 return (rc); 13283 } 13284 13285 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0); 13286 MODULE_VERSION(t4nex, 1); 13287 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 13288 #ifdef DEV_NETMAP 13289 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 13290 #endif /* DEV_NETMAP */ 13291 13292 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0); 13293 MODULE_VERSION(t5nex, 1); 13294 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 13295 #ifdef DEV_NETMAP 13296 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 13297 #endif /* DEV_NETMAP */ 13298 13299 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0); 13300 MODULE_VERSION(t6nex, 1); 13301 MODULE_DEPEND(t6nex, crypto, 1, 1, 1); 13302 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 13303 #ifdef DEV_NETMAP 13304 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 13305 #endif /* DEV_NETMAP */ 13306 13307 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0); 13308 MODULE_VERSION(cxgbe, 1); 13309 13310 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0); 13311 MODULE_VERSION(cxl, 1); 13312 13313 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0); 13314 MODULE_VERSION(cc, 1); 13315 13316 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0); 13317 MODULE_VERSION(vcxgbe, 1); 13318 13319 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0); 13320 MODULE_VERSION(vcxl, 1); 13321 13322 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0); 13323 MODULE_VERSION(vcc, 1); 13324