1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_ratelimit.h" 37 #include "opt_rss.h" 38 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/priv.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #if defined(__i386__) || defined(__amd64__) 69 #include <machine/md_var.h> 70 #include <machine/cputypes.h> 71 #include <vm/vm.h> 72 #include <vm/pmap.h> 73 #endif 74 #include <crypto/rijndael/rijndael.h> 75 #ifdef DDB 76 #include <ddb/ddb.h> 77 #include <ddb/db_lex.h> 78 #endif 79 80 #include "common/common.h" 81 #include "common/t4_msg.h" 82 #include "common/t4_regs.h" 83 #include "common/t4_regs_values.h" 84 #include "cudbg/cudbg.h" 85 #include "t4_clip.h" 86 #include "t4_ioctl.h" 87 #include "t4_l2t.h" 88 #include "t4_mp_ring.h" 89 #include "t4_if.h" 90 #include "t4_smt.h" 91 92 /* T4 bus driver interface */ 93 static int t4_probe(device_t); 94 static int t4_attach(device_t); 95 static int t4_detach(device_t); 96 static int t4_child_location_str(device_t, device_t, char *, size_t); 97 static int t4_ready(device_t); 98 static int t4_read_port_device(device_t, int, device_t *); 99 static device_method_t t4_methods[] = { 100 DEVMETHOD(device_probe, t4_probe), 101 DEVMETHOD(device_attach, t4_attach), 102 DEVMETHOD(device_detach, t4_detach), 103 104 DEVMETHOD(bus_child_location_str, t4_child_location_str), 105 106 DEVMETHOD(t4_is_main_ready, t4_ready), 107 DEVMETHOD(t4_read_port_device, t4_read_port_device), 108 109 DEVMETHOD_END 110 }; 111 static driver_t t4_driver = { 112 "t4nex", 113 t4_methods, 114 sizeof(struct adapter) 115 }; 116 117 118 /* T4 port (cxgbe) interface */ 119 static int cxgbe_probe(device_t); 120 static int cxgbe_attach(device_t); 121 static int cxgbe_detach(device_t); 122 device_method_t cxgbe_methods[] = { 123 DEVMETHOD(device_probe, cxgbe_probe), 124 DEVMETHOD(device_attach, cxgbe_attach), 125 DEVMETHOD(device_detach, cxgbe_detach), 126 { 0, 0 } 127 }; 128 static driver_t cxgbe_driver = { 129 "cxgbe", 130 cxgbe_methods, 131 sizeof(struct port_info) 132 }; 133 134 /* T4 VI (vcxgbe) interface */ 135 static int vcxgbe_probe(device_t); 136 static int vcxgbe_attach(device_t); 137 static int vcxgbe_detach(device_t); 138 static device_method_t vcxgbe_methods[] = { 139 DEVMETHOD(device_probe, vcxgbe_probe), 140 DEVMETHOD(device_attach, vcxgbe_attach), 141 DEVMETHOD(device_detach, vcxgbe_detach), 142 { 0, 0 } 143 }; 144 static driver_t vcxgbe_driver = { 145 "vcxgbe", 146 vcxgbe_methods, 147 sizeof(struct vi_info) 148 }; 149 150 static d_ioctl_t t4_ioctl; 151 152 static struct cdevsw t4_cdevsw = { 153 .d_version = D_VERSION, 154 .d_ioctl = t4_ioctl, 155 .d_name = "t4nex", 156 }; 157 158 /* T5 bus driver interface */ 159 static int t5_probe(device_t); 160 static device_method_t t5_methods[] = { 161 DEVMETHOD(device_probe, t5_probe), 162 DEVMETHOD(device_attach, t4_attach), 163 DEVMETHOD(device_detach, t4_detach), 164 165 DEVMETHOD(bus_child_location_str, t4_child_location_str), 166 167 DEVMETHOD(t4_is_main_ready, t4_ready), 168 DEVMETHOD(t4_read_port_device, t4_read_port_device), 169 170 DEVMETHOD_END 171 }; 172 static driver_t t5_driver = { 173 "t5nex", 174 t5_methods, 175 sizeof(struct adapter) 176 }; 177 178 179 /* T5 port (cxl) interface */ 180 static driver_t cxl_driver = { 181 "cxl", 182 cxgbe_methods, 183 sizeof(struct port_info) 184 }; 185 186 /* T5 VI (vcxl) interface */ 187 static driver_t vcxl_driver = { 188 "vcxl", 189 vcxgbe_methods, 190 sizeof(struct vi_info) 191 }; 192 193 /* T6 bus driver interface */ 194 static int t6_probe(device_t); 195 static device_method_t t6_methods[] = { 196 DEVMETHOD(device_probe, t6_probe), 197 DEVMETHOD(device_attach, t4_attach), 198 DEVMETHOD(device_detach, t4_detach), 199 200 DEVMETHOD(bus_child_location_str, t4_child_location_str), 201 202 DEVMETHOD(t4_is_main_ready, t4_ready), 203 DEVMETHOD(t4_read_port_device, t4_read_port_device), 204 205 DEVMETHOD_END 206 }; 207 static driver_t t6_driver = { 208 "t6nex", 209 t6_methods, 210 sizeof(struct adapter) 211 }; 212 213 214 /* T6 port (cc) interface */ 215 static driver_t cc_driver = { 216 "cc", 217 cxgbe_methods, 218 sizeof(struct port_info) 219 }; 220 221 /* T6 VI (vcc) interface */ 222 static driver_t vcc_driver = { 223 "vcc", 224 vcxgbe_methods, 225 sizeof(struct vi_info) 226 }; 227 228 /* ifnet interface */ 229 static void cxgbe_init(void *); 230 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 231 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 232 static void cxgbe_qflush(struct ifnet *); 233 234 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 235 236 /* 237 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 238 * then ADAPTER_LOCK, then t4_uld_list_lock. 239 */ 240 static struct sx t4_list_lock; 241 SLIST_HEAD(, adapter) t4_list; 242 #ifdef TCP_OFFLOAD 243 static struct sx t4_uld_list_lock; 244 SLIST_HEAD(, uld_info) t4_uld_list; 245 #endif 246 247 /* 248 * Tunables. See tweak_tunables() too. 249 * 250 * Each tunable is set to a default value here if it's known at compile-time. 251 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 252 * provide a reasonable default (upto n) when the driver is loaded. 253 * 254 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 255 * T5 are under hw.cxl. 256 */ 257 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters"); 258 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters"); 259 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters"); 260 261 /* 262 * Number of queues for tx and rx, NIC and offload. 263 */ 264 #define NTXQ 16 265 int t4_ntxq = -NTXQ; 266 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 267 "Number of TX queues per port"); 268 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 269 270 #define NRXQ 8 271 int t4_nrxq = -NRXQ; 272 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 273 "Number of RX queues per port"); 274 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 275 276 #define NTXQ_VI 1 277 static int t4_ntxq_vi = -NTXQ_VI; 278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 279 "Number of TX queues per VI"); 280 281 #define NRXQ_VI 1 282 static int t4_nrxq_vi = -NRXQ_VI; 283 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 284 "Number of RX queues per VI"); 285 286 static int t4_rsrv_noflowq = 0; 287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 288 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 289 290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 291 #define NOFLDTXQ 8 292 static int t4_nofldtxq = -NOFLDTXQ; 293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 294 "Number of offload TX queues per port"); 295 296 #define NOFLDRXQ 2 297 static int t4_nofldrxq = -NOFLDRXQ; 298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 299 "Number of offload RX queues per port"); 300 301 #define NOFLDTXQ_VI 1 302 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 304 "Number of offload TX queues per VI"); 305 306 #define NOFLDRXQ_VI 1 307 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 309 "Number of offload RX queues per VI"); 310 311 #define TMR_IDX_OFLD 1 312 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 314 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 315 316 #define PKTC_IDX_OFLD (-1) 317 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 319 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 320 321 /* 0 means chip/fw default, non-zero number is value in microseconds */ 322 static u_long t4_toe_keepalive_idle = 0; 323 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 324 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 325 326 /* 0 means chip/fw default, non-zero number is value in microseconds */ 327 static u_long t4_toe_keepalive_interval = 0; 328 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 329 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 330 331 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 332 static int t4_toe_keepalive_count = 0; 333 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 334 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 335 336 /* 0 means chip/fw default, non-zero number is value in microseconds */ 337 static u_long t4_toe_rexmt_min = 0; 338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 339 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 340 341 /* 0 means chip/fw default, non-zero number is value in microseconds */ 342 static u_long t4_toe_rexmt_max = 0; 343 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 344 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 345 346 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 347 static int t4_toe_rexmt_count = 0; 348 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 349 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 350 351 /* -1 means chip/fw default, other values are raw backoff values to use */ 352 static int t4_toe_rexmt_backoff[16] = { 353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 354 }; 355 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0, 356 "cxgbe(4) TOE retransmit backoff values"); 357 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 358 &t4_toe_rexmt_backoff[0], 0, ""); 359 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 360 &t4_toe_rexmt_backoff[1], 0, ""); 361 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 362 &t4_toe_rexmt_backoff[2], 0, ""); 363 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_backoff[3], 0, ""); 365 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_backoff[4], 0, ""); 367 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 368 &t4_toe_rexmt_backoff[5], 0, ""); 369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 370 &t4_toe_rexmt_backoff[6], 0, ""); 371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 372 &t4_toe_rexmt_backoff[7], 0, ""); 373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_backoff[8], 0, ""); 375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_backoff[9], 0, ""); 377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 378 &t4_toe_rexmt_backoff[10], 0, ""); 379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 380 &t4_toe_rexmt_backoff[11], 0, ""); 381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 382 &t4_toe_rexmt_backoff[12], 0, ""); 383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[13], 0, ""); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[14], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[15], 0, ""); 389 #endif 390 391 #ifdef DEV_NETMAP 392 #define NNMTXQ_VI 2 393 static int t4_nnmtxq_vi = -NNMTXQ_VI; 394 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 395 "Number of netmap TX queues per VI"); 396 397 #define NNMRXQ_VI 2 398 static int t4_nnmrxq_vi = -NNMRXQ_VI; 399 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 400 "Number of netmap RX queues per VI"); 401 #endif 402 403 /* 404 * Holdoff parameters for ports. 405 */ 406 #define TMR_IDX 1 407 int t4_tmr_idx = TMR_IDX; 408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 409 0, "Holdoff timer index"); 410 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 411 412 #define PKTC_IDX (-1) 413 int t4_pktc_idx = PKTC_IDX; 414 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 415 0, "Holdoff packet counter index"); 416 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 417 418 /* 419 * Size (# of entries) of each tx and rx queue. 420 */ 421 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 423 "Number of descriptors in each TX queue"); 424 425 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 427 "Number of descriptors in each RX queue"); 428 429 /* 430 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 431 */ 432 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 434 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 435 436 /* 437 * Configuration file. All the _CF names here are special. 438 */ 439 #define DEFAULT_CF "default" 440 #define BUILTIN_CF "built-in" 441 #define FLASH_CF "flash" 442 #define UWIRE_CF "uwire" 443 #define FPGA_CF "fpga" 444 static char t4_cfg_file[32] = DEFAULT_CF; 445 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 446 sizeof(t4_cfg_file), "Firmware configuration file"); 447 448 /* 449 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 450 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 451 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 452 * mark or when signalled to do so, 0 to never emit PAUSE. 453 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 454 * negotiated settings will override rx_pause/tx_pause. 455 * Otherwise rx_pause/tx_pause are applied forcibly. 456 */ 457 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 459 &t4_pause_settings, 0, 460 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 461 462 /* 463 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 464 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 465 * 0 to disable FEC. 466 */ 467 static int t4_fec = -1; 468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 469 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 470 471 /* 472 * Link autonegotiation. 473 * -1 to run with the firmware default. 474 * 0 to disable. 475 * 1 to enable. 476 */ 477 static int t4_autoneg = -1; 478 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 479 "Link autonegotiation"); 480 481 /* 482 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 483 * encouraged respectively). '-n' is the same as 'n' except the firmware 484 * version used in the checks is read from the firmware bundled with the driver. 485 */ 486 static int t4_fw_install = 1; 487 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 488 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 489 490 /* 491 * ASIC features that will be used. Disable the ones you don't want so that the 492 * chip resources aren't wasted on features that will not be used. 493 */ 494 static int t4_nbmcaps_allowed = 0; 495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 496 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 497 498 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 499 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 500 &t4_linkcaps_allowed, 0, "Default link capabilities"); 501 502 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 503 FW_CAPS_CONFIG_SWITCH_EGRESS; 504 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 505 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 506 507 #ifdef RATELIMIT 508 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 509 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 510 #else 511 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 512 FW_CAPS_CONFIG_NIC_HASHFILTER; 513 #endif 514 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 515 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 516 517 static int t4_toecaps_allowed = -1; 518 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 519 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 520 521 static int t4_rdmacaps_allowed = -1; 522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 523 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 524 525 static int t4_cryptocaps_allowed = -1; 526 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 527 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 528 529 static int t4_iscsicaps_allowed = -1; 530 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 531 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 532 533 static int t4_fcoecaps_allowed = 0; 534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 535 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 536 537 static int t5_write_combine = 0; 538 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 539 0, "Use WC instead of UC for BAR2"); 540 541 static int t4_num_vis = 1; 542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 543 "Number of VIs per port"); 544 545 /* 546 * PCIe Relaxed Ordering. 547 * -1: driver should figure out a good value. 548 * 0: disable RO. 549 * 1: enable RO. 550 * 2: leave RO alone. 551 */ 552 static int pcie_relaxed_ordering = -1; 553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 554 &pcie_relaxed_ordering, 0, 555 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 556 557 static int t4_panic_on_fatal_err = 0; 558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN, 559 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 560 561 #ifdef TCP_OFFLOAD 562 /* 563 * TOE tunables. 564 */ 565 static int t4_cop_managed_offloading = 0; 566 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 567 &t4_cop_managed_offloading, 0, 568 "COP (Connection Offload Policy) controls all TOE offload"); 569 #endif 570 571 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 572 static int vi_mac_funcs[] = { 573 FW_VI_FUNC_ETH, 574 FW_VI_FUNC_OFLD, 575 FW_VI_FUNC_IWARP, 576 FW_VI_FUNC_OPENISCSI, 577 FW_VI_FUNC_OPENFCOE, 578 FW_VI_FUNC_FOISCSI, 579 FW_VI_FUNC_FOFCOE, 580 }; 581 582 struct intrs_and_queues { 583 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 584 uint16_t num_vis; /* number of VIs for each port */ 585 uint16_t nirq; /* Total # of vectors */ 586 uint16_t ntxq; /* # of NIC txq's for each port */ 587 uint16_t nrxq; /* # of NIC rxq's for each port */ 588 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 589 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 590 591 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 592 uint16_t ntxq_vi; /* # of NIC txq's */ 593 uint16_t nrxq_vi; /* # of NIC rxq's */ 594 uint16_t nofldtxq_vi; /* # of TOE txq's */ 595 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 596 uint16_t nnmtxq_vi; /* # of netmap txq's */ 597 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 598 }; 599 600 static void setup_memwin(struct adapter *); 601 static void position_memwin(struct adapter *, int, uint32_t); 602 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 603 static int fwmtype_to_hwmtype(int); 604 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 605 uint32_t *); 606 static int fixup_devlog_params(struct adapter *); 607 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 608 static int contact_firmware(struct adapter *); 609 static int partition_resources(struct adapter *); 610 static int get_params__pre_init(struct adapter *); 611 static int set_params__pre_init(struct adapter *); 612 static int get_params__post_init(struct adapter *); 613 static int set_params__post_init(struct adapter *); 614 static void t4_set_desc(struct adapter *); 615 static bool fixed_ifmedia(struct port_info *); 616 static void build_medialist(struct port_info *); 617 static void init_link_config(struct port_info *); 618 static int fixup_link_config(struct port_info *); 619 static int apply_link_config(struct port_info *); 620 static int cxgbe_init_synchronized(struct vi_info *); 621 static int cxgbe_uninit_synchronized(struct vi_info *); 622 static void quiesce_txq(struct adapter *, struct sge_txq *); 623 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 624 static void quiesce_iq(struct adapter *, struct sge_iq *); 625 static void quiesce_fl(struct adapter *, struct sge_fl *); 626 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 627 driver_intr_t *, void *, char *); 628 static int t4_free_irq(struct adapter *, struct irq *); 629 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 630 static void vi_refresh_stats(struct adapter *, struct vi_info *); 631 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 632 static void cxgbe_tick(void *); 633 static void cxgbe_sysctls(struct port_info *); 634 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 635 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 636 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 637 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 638 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 639 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 640 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 641 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 642 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 643 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 644 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 645 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 646 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 647 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 648 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 649 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 650 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 651 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 652 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 653 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 654 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 655 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 656 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 657 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 658 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 659 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 660 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 661 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 662 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 663 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 664 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 665 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 666 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 667 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 668 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 669 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 670 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 671 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 672 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 673 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 674 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 675 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 676 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 677 #ifdef TCP_OFFLOAD 678 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 679 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 680 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 681 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 682 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 683 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 684 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 685 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 686 #endif 687 static int get_sge_context(struct adapter *, struct t4_sge_context *); 688 static int load_fw(struct adapter *, struct t4_data *); 689 static int load_cfg(struct adapter *, struct t4_data *); 690 static int load_boot(struct adapter *, struct t4_bootrom *); 691 static int load_bootcfg(struct adapter *, struct t4_data *); 692 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 693 static void free_offload_policy(struct t4_offload_policy *); 694 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 695 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 696 static int read_i2c(struct adapter *, struct t4_i2c_data *); 697 #ifdef TCP_OFFLOAD 698 static int toe_capability(struct vi_info *, int); 699 #endif 700 static int mod_event(module_t, int, void *); 701 static int notify_siblings(device_t, int); 702 703 struct { 704 uint16_t device; 705 char *desc; 706 } t4_pciids[] = { 707 {0xa000, "Chelsio Terminator 4 FPGA"}, 708 {0x4400, "Chelsio T440-dbg"}, 709 {0x4401, "Chelsio T420-CR"}, 710 {0x4402, "Chelsio T422-CR"}, 711 {0x4403, "Chelsio T440-CR"}, 712 {0x4404, "Chelsio T420-BCH"}, 713 {0x4405, "Chelsio T440-BCH"}, 714 {0x4406, "Chelsio T440-CH"}, 715 {0x4407, "Chelsio T420-SO"}, 716 {0x4408, "Chelsio T420-CX"}, 717 {0x4409, "Chelsio T420-BT"}, 718 {0x440a, "Chelsio T404-BT"}, 719 {0x440e, "Chelsio T440-LP-CR"}, 720 }, t5_pciids[] = { 721 {0xb000, "Chelsio Terminator 5 FPGA"}, 722 {0x5400, "Chelsio T580-dbg"}, 723 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 724 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 725 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 726 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 727 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 728 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 729 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 730 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 731 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 732 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 733 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 734 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 735 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 736 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 737 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 738 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 739 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 740 741 /* Custom */ 742 {0x5483, "Custom T540-CR"}, 743 {0x5484, "Custom T540-BT"}, 744 }, t6_pciids[] = { 745 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 746 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 747 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 748 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 749 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 750 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 751 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 752 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 753 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 754 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 755 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 756 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 757 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 758 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 759 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 760 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 761 762 /* Custom */ 763 {0x6480, "Custom T6225-CR"}, 764 {0x6481, "Custom T62100-CR"}, 765 {0x6482, "Custom T6225-CR"}, 766 {0x6483, "Custom T62100-CR"}, 767 {0x6484, "Custom T64100-CR"}, 768 {0x6485, "Custom T6240-SO"}, 769 {0x6486, "Custom T6225-SO-CR"}, 770 {0x6487, "Custom T6225-CR"}, 771 }; 772 773 #ifdef TCP_OFFLOAD 774 /* 775 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 776 * be exactly the same for both rxq and ofld_rxq. 777 */ 778 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 779 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 780 #endif 781 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 782 783 static int 784 t4_probe(device_t dev) 785 { 786 int i; 787 uint16_t v = pci_get_vendor(dev); 788 uint16_t d = pci_get_device(dev); 789 uint8_t f = pci_get_function(dev); 790 791 if (v != PCI_VENDOR_ID_CHELSIO) 792 return (ENXIO); 793 794 /* Attach only to PF0 of the FPGA */ 795 if (d == 0xa000 && f != 0) 796 return (ENXIO); 797 798 for (i = 0; i < nitems(t4_pciids); i++) { 799 if (d == t4_pciids[i].device) { 800 device_set_desc(dev, t4_pciids[i].desc); 801 return (BUS_PROBE_DEFAULT); 802 } 803 } 804 805 return (ENXIO); 806 } 807 808 static int 809 t5_probe(device_t dev) 810 { 811 int i; 812 uint16_t v = pci_get_vendor(dev); 813 uint16_t d = pci_get_device(dev); 814 uint8_t f = pci_get_function(dev); 815 816 if (v != PCI_VENDOR_ID_CHELSIO) 817 return (ENXIO); 818 819 /* Attach only to PF0 of the FPGA */ 820 if (d == 0xb000 && f != 0) 821 return (ENXIO); 822 823 for (i = 0; i < nitems(t5_pciids); i++) { 824 if (d == t5_pciids[i].device) { 825 device_set_desc(dev, t5_pciids[i].desc); 826 return (BUS_PROBE_DEFAULT); 827 } 828 } 829 830 return (ENXIO); 831 } 832 833 static int 834 t6_probe(device_t dev) 835 { 836 int i; 837 uint16_t v = pci_get_vendor(dev); 838 uint16_t d = pci_get_device(dev); 839 840 if (v != PCI_VENDOR_ID_CHELSIO) 841 return (ENXIO); 842 843 for (i = 0; i < nitems(t6_pciids); i++) { 844 if (d == t6_pciids[i].device) { 845 device_set_desc(dev, t6_pciids[i].desc); 846 return (BUS_PROBE_DEFAULT); 847 } 848 } 849 850 return (ENXIO); 851 } 852 853 static void 854 t5_attribute_workaround(device_t dev) 855 { 856 device_t root_port; 857 uint32_t v; 858 859 /* 860 * The T5 chips do not properly echo the No Snoop and Relaxed 861 * Ordering attributes when replying to a TLP from a Root 862 * Port. As a workaround, find the parent Root Port and 863 * disable No Snoop and Relaxed Ordering. Note that this 864 * affects all devices under this root port. 865 */ 866 root_port = pci_find_pcie_root_port(dev); 867 if (root_port == NULL) { 868 device_printf(dev, "Unable to find parent root port\n"); 869 return; 870 } 871 872 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 873 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 874 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 875 0) 876 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 877 device_get_nameunit(root_port)); 878 } 879 880 static const struct devnames devnames[] = { 881 { 882 .nexus_name = "t4nex", 883 .ifnet_name = "cxgbe", 884 .vi_ifnet_name = "vcxgbe", 885 .pf03_drv_name = "t4iov", 886 .vf_nexus_name = "t4vf", 887 .vf_ifnet_name = "cxgbev" 888 }, { 889 .nexus_name = "t5nex", 890 .ifnet_name = "cxl", 891 .vi_ifnet_name = "vcxl", 892 .pf03_drv_name = "t5iov", 893 .vf_nexus_name = "t5vf", 894 .vf_ifnet_name = "cxlv" 895 }, { 896 .nexus_name = "t6nex", 897 .ifnet_name = "cc", 898 .vi_ifnet_name = "vcc", 899 .pf03_drv_name = "t6iov", 900 .vf_nexus_name = "t6vf", 901 .vf_ifnet_name = "ccv" 902 } 903 }; 904 905 void 906 t4_init_devnames(struct adapter *sc) 907 { 908 int id; 909 910 id = chip_id(sc); 911 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 912 sc->names = &devnames[id - CHELSIO_T4]; 913 else { 914 device_printf(sc->dev, "chip id %d is not supported.\n", id); 915 sc->names = NULL; 916 } 917 } 918 919 static int 920 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 921 { 922 const char *parent, *name; 923 long value; 924 int line, unit; 925 926 line = 0; 927 parent = device_get_nameunit(sc->dev); 928 name = sc->names->ifnet_name; 929 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 930 if (resource_long_value(name, unit, "port", &value) == 0 && 931 value == pi->port_id) 932 return (unit); 933 } 934 return (-1); 935 } 936 937 static int 938 t4_attach(device_t dev) 939 { 940 struct adapter *sc; 941 int rc = 0, i, j, rqidx, tqidx, nports; 942 struct make_dev_args mda; 943 struct intrs_and_queues iaq; 944 struct sge *s; 945 uint32_t *buf; 946 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 947 int ofld_tqidx; 948 #endif 949 #ifdef TCP_OFFLOAD 950 int ofld_rqidx; 951 #endif 952 #ifdef DEV_NETMAP 953 int nm_rqidx, nm_tqidx; 954 #endif 955 int num_vis; 956 957 sc = device_get_softc(dev); 958 sc->dev = dev; 959 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 960 961 if ((pci_get_device(dev) & 0xff00) == 0x5400) 962 t5_attribute_workaround(dev); 963 pci_enable_busmaster(dev); 964 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 965 uint32_t v; 966 967 pci_set_max_read_req(dev, 4096); 968 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 969 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 970 if (pcie_relaxed_ordering == 0 && 971 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 972 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 973 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 974 } else if (pcie_relaxed_ordering == 1 && 975 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 976 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 977 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 978 } 979 } 980 981 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 982 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 983 sc->traceq = -1; 984 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 985 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 986 device_get_nameunit(dev)); 987 988 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 989 device_get_nameunit(dev)); 990 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 991 t4_add_adapter(sc); 992 993 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 994 TAILQ_INIT(&sc->sfl); 995 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 996 997 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 998 999 sc->policy = NULL; 1000 rw_init(&sc->policy_lock, "connection offload policy"); 1001 1002 rc = t4_map_bars_0_and_4(sc); 1003 if (rc != 0) 1004 goto done; /* error message displayed already */ 1005 1006 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1007 1008 /* Prepare the adapter for operation. */ 1009 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1010 rc = -t4_prep_adapter(sc, buf); 1011 free(buf, M_CXGBE); 1012 if (rc != 0) { 1013 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1014 goto done; 1015 } 1016 1017 /* 1018 * This is the real PF# to which we're attaching. Works from within PCI 1019 * passthrough environments too, where pci_get_function() could return a 1020 * different PF# depending on the passthrough configuration. We need to 1021 * use the real PF# in all our communication with the firmware. 1022 */ 1023 j = t4_read_reg(sc, A_PL_WHOAMI); 1024 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1025 sc->mbox = sc->pf; 1026 1027 t4_init_devnames(sc); 1028 if (sc->names == NULL) { 1029 rc = ENOTSUP; 1030 goto done; /* error message displayed already */ 1031 } 1032 1033 /* 1034 * Do this really early, with the memory windows set up even before the 1035 * character device. The userland tool's register i/o and mem read 1036 * will work even in "recovery mode". 1037 */ 1038 setup_memwin(sc); 1039 if (t4_init_devlog_params(sc, 0) == 0) 1040 fixup_devlog_params(sc); 1041 make_dev_args_init(&mda); 1042 mda.mda_devsw = &t4_cdevsw; 1043 mda.mda_uid = UID_ROOT; 1044 mda.mda_gid = GID_WHEEL; 1045 mda.mda_mode = 0600; 1046 mda.mda_si_drv1 = sc; 1047 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1048 if (rc != 0) 1049 device_printf(dev, "failed to create nexus char device: %d.\n", 1050 rc); 1051 1052 /* Go no further if recovery mode has been requested. */ 1053 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1054 device_printf(dev, "recovery mode.\n"); 1055 goto done; 1056 } 1057 1058 #if defined(__i386__) 1059 if ((cpu_feature & CPUID_CX8) == 0) { 1060 device_printf(dev, "64 bit atomics not available.\n"); 1061 rc = ENOTSUP; 1062 goto done; 1063 } 1064 #endif 1065 1066 /* Contact the firmware and try to become the master driver. */ 1067 rc = contact_firmware(sc); 1068 if (rc != 0) 1069 goto done; /* error message displayed already */ 1070 MPASS(sc->flags & FW_OK); 1071 1072 rc = get_params__pre_init(sc); 1073 if (rc != 0) 1074 goto done; /* error message displayed already */ 1075 1076 if (sc->flags & MASTER_PF) { 1077 rc = partition_resources(sc); 1078 if (rc != 0) 1079 goto done; /* error message displayed already */ 1080 t4_intr_clear(sc); 1081 } 1082 1083 rc = get_params__post_init(sc); 1084 if (rc != 0) 1085 goto done; /* error message displayed already */ 1086 1087 rc = set_params__post_init(sc); 1088 if (rc != 0) 1089 goto done; /* error message displayed already */ 1090 1091 rc = t4_map_bar_2(sc); 1092 if (rc != 0) 1093 goto done; /* error message displayed already */ 1094 1095 rc = t4_create_dma_tag(sc); 1096 if (rc != 0) 1097 goto done; /* error message displayed already */ 1098 1099 /* 1100 * First pass over all the ports - allocate VIs and initialize some 1101 * basic parameters like mac address, port type, etc. 1102 */ 1103 for_each_port(sc, i) { 1104 struct port_info *pi; 1105 1106 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1107 sc->port[i] = pi; 1108 1109 /* These must be set before t4_port_init */ 1110 pi->adapter = sc; 1111 pi->port_id = i; 1112 /* 1113 * XXX: vi[0] is special so we can't delay this allocation until 1114 * pi->nvi's final value is known. 1115 */ 1116 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1117 M_ZERO | M_WAITOK); 1118 1119 /* 1120 * Allocate the "main" VI and initialize parameters 1121 * like mac addr. 1122 */ 1123 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1124 if (rc != 0) { 1125 device_printf(dev, "unable to initialize port %d: %d\n", 1126 i, rc); 1127 free(pi->vi, M_CXGBE); 1128 free(pi, M_CXGBE); 1129 sc->port[i] = NULL; 1130 goto done; 1131 } 1132 1133 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1134 device_get_nameunit(dev), i); 1135 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1136 sc->chan_map[pi->tx_chan] = i; 1137 1138 /* All VIs on this port share this media. */ 1139 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1140 cxgbe_media_status); 1141 1142 PORT_LOCK(pi); 1143 init_link_config(pi); 1144 fixup_link_config(pi); 1145 build_medialist(pi); 1146 if (fixed_ifmedia(pi)) 1147 pi->flags |= FIXED_IFMEDIA; 1148 PORT_UNLOCK(pi); 1149 1150 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1151 t4_ifnet_unit(sc, pi)); 1152 if (pi->dev == NULL) { 1153 device_printf(dev, 1154 "failed to add device for port %d.\n", i); 1155 rc = ENXIO; 1156 goto done; 1157 } 1158 pi->vi[0].dev = pi->dev; 1159 device_set_softc(pi->dev, pi); 1160 } 1161 1162 /* 1163 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1164 */ 1165 nports = sc->params.nports; 1166 rc = cfg_itype_and_nqueues(sc, &iaq); 1167 if (rc != 0) 1168 goto done; /* error message displayed already */ 1169 1170 num_vis = iaq.num_vis; 1171 sc->intr_type = iaq.intr_type; 1172 sc->intr_count = iaq.nirq; 1173 1174 s = &sc->sge; 1175 s->nrxq = nports * iaq.nrxq; 1176 s->ntxq = nports * iaq.ntxq; 1177 if (num_vis > 1) { 1178 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1179 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1180 } 1181 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1182 s->neq += nports; /* ctrl queues: 1 per port */ 1183 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1184 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1185 if (is_offload(sc) || is_ethoffload(sc)) { 1186 s->nofldtxq = nports * iaq.nofldtxq; 1187 if (num_vis > 1) 1188 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1189 s->neq += s->nofldtxq; 1190 1191 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1192 M_CXGBE, M_ZERO | M_WAITOK); 1193 } 1194 #endif 1195 #ifdef TCP_OFFLOAD 1196 if (is_offload(sc)) { 1197 s->nofldrxq = nports * iaq.nofldrxq; 1198 if (num_vis > 1) 1199 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1200 s->neq += s->nofldrxq; /* free list */ 1201 s->niq += s->nofldrxq; 1202 1203 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1204 M_CXGBE, M_ZERO | M_WAITOK); 1205 } 1206 #endif 1207 #ifdef DEV_NETMAP 1208 if (num_vis > 1) { 1209 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1210 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1211 } 1212 s->neq += s->nnmtxq + s->nnmrxq; 1213 s->niq += s->nnmrxq; 1214 1215 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1216 M_CXGBE, M_ZERO | M_WAITOK); 1217 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1218 M_CXGBE, M_ZERO | M_WAITOK); 1219 #endif 1220 1221 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1222 M_ZERO | M_WAITOK); 1223 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1224 M_ZERO | M_WAITOK); 1225 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1226 M_ZERO | M_WAITOK); 1227 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1228 M_ZERO | M_WAITOK); 1229 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1230 M_ZERO | M_WAITOK); 1231 1232 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1233 M_ZERO | M_WAITOK); 1234 1235 t4_init_l2t(sc, M_WAITOK); 1236 t4_init_smt(sc, M_WAITOK); 1237 t4_init_tx_sched(sc); 1238 #ifdef RATELIMIT 1239 t4_init_etid_table(sc); 1240 #endif 1241 #ifdef INET6 1242 t4_init_clip_table(sc); 1243 #endif 1244 if (sc->vres.key.size != 0) 1245 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1246 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1247 1248 /* 1249 * Second pass over the ports. This time we know the number of rx and 1250 * tx queues that each port should get. 1251 */ 1252 rqidx = tqidx = 0; 1253 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1254 ofld_tqidx = 0; 1255 #endif 1256 #ifdef TCP_OFFLOAD 1257 ofld_rqidx = 0; 1258 #endif 1259 #ifdef DEV_NETMAP 1260 nm_rqidx = nm_tqidx = 0; 1261 #endif 1262 for_each_port(sc, i) { 1263 struct port_info *pi = sc->port[i]; 1264 struct vi_info *vi; 1265 1266 if (pi == NULL) 1267 continue; 1268 1269 pi->nvi = num_vis; 1270 for_each_vi(pi, j, vi) { 1271 vi->pi = pi; 1272 vi->qsize_rxq = t4_qsize_rxq; 1273 vi->qsize_txq = t4_qsize_txq; 1274 1275 vi->first_rxq = rqidx; 1276 vi->first_txq = tqidx; 1277 vi->tmr_idx = t4_tmr_idx; 1278 vi->pktc_idx = t4_pktc_idx; 1279 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1280 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1281 1282 rqidx += vi->nrxq; 1283 tqidx += vi->ntxq; 1284 1285 if (j == 0 && vi->ntxq > 1) 1286 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1287 else 1288 vi->rsrv_noflowq = 0; 1289 1290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1291 vi->first_ofld_txq = ofld_tqidx; 1292 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1293 ofld_tqidx += vi->nofldtxq; 1294 #endif 1295 #ifdef TCP_OFFLOAD 1296 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1297 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1298 vi->first_ofld_rxq = ofld_rqidx; 1299 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1300 1301 ofld_rqidx += vi->nofldrxq; 1302 #endif 1303 #ifdef DEV_NETMAP 1304 if (j > 0) { 1305 vi->first_nm_rxq = nm_rqidx; 1306 vi->first_nm_txq = nm_tqidx; 1307 vi->nnmrxq = iaq.nnmrxq_vi; 1308 vi->nnmtxq = iaq.nnmtxq_vi; 1309 nm_rqidx += vi->nnmrxq; 1310 nm_tqidx += vi->nnmtxq; 1311 } 1312 #endif 1313 } 1314 } 1315 1316 rc = t4_setup_intr_handlers(sc); 1317 if (rc != 0) { 1318 device_printf(dev, 1319 "failed to setup interrupt handlers: %d\n", rc); 1320 goto done; 1321 } 1322 1323 rc = bus_generic_probe(dev); 1324 if (rc != 0) { 1325 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1326 goto done; 1327 } 1328 1329 /* 1330 * Ensure thread-safe mailbox access (in debug builds). 1331 * 1332 * So far this was the only thread accessing the mailbox but various 1333 * ifnets and sysctls are about to be created and their handlers/ioctls 1334 * will access the mailbox from different threads. 1335 */ 1336 sc->flags |= CHK_MBOX_ACCESS; 1337 1338 rc = bus_generic_attach(dev); 1339 if (rc != 0) { 1340 device_printf(dev, 1341 "failed to attach all child ports: %d\n", rc); 1342 goto done; 1343 } 1344 1345 device_printf(dev, 1346 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1347 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1348 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1349 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1350 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1351 1352 t4_set_desc(sc); 1353 1354 notify_siblings(dev, 0); 1355 1356 done: 1357 if (rc != 0 && sc->cdev) { 1358 /* cdev was created and so cxgbetool works; recover that way. */ 1359 device_printf(dev, 1360 "error during attach, adapter is now in recovery mode.\n"); 1361 rc = 0; 1362 } 1363 1364 if (rc != 0) 1365 t4_detach_common(dev); 1366 else 1367 t4_sysctls(sc); 1368 1369 return (rc); 1370 } 1371 1372 static int 1373 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen) 1374 { 1375 struct adapter *sc; 1376 struct port_info *pi; 1377 int i; 1378 1379 sc = device_get_softc(bus); 1380 buf[0] = '\0'; 1381 for_each_port(sc, i) { 1382 pi = sc->port[i]; 1383 if (pi != NULL && pi->dev == dev) { 1384 snprintf(buf, buflen, "port=%d", pi->port_id); 1385 break; 1386 } 1387 } 1388 return (0); 1389 } 1390 1391 static int 1392 t4_ready(device_t dev) 1393 { 1394 struct adapter *sc; 1395 1396 sc = device_get_softc(dev); 1397 if (sc->flags & FW_OK) 1398 return (0); 1399 return (ENXIO); 1400 } 1401 1402 static int 1403 t4_read_port_device(device_t dev, int port, device_t *child) 1404 { 1405 struct adapter *sc; 1406 struct port_info *pi; 1407 1408 sc = device_get_softc(dev); 1409 if (port < 0 || port >= MAX_NPORTS) 1410 return (EINVAL); 1411 pi = sc->port[port]; 1412 if (pi == NULL || pi->dev == NULL) 1413 return (ENXIO); 1414 *child = pi->dev; 1415 return (0); 1416 } 1417 1418 static int 1419 notify_siblings(device_t dev, int detaching) 1420 { 1421 device_t sibling; 1422 int error, i; 1423 1424 error = 0; 1425 for (i = 0; i < PCI_FUNCMAX; i++) { 1426 if (i == pci_get_function(dev)) 1427 continue; 1428 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1429 pci_get_slot(dev), i); 1430 if (sibling == NULL || !device_is_attached(sibling)) 1431 continue; 1432 if (detaching) 1433 error = T4_DETACH_CHILD(sibling); 1434 else 1435 (void)T4_ATTACH_CHILD(sibling); 1436 if (error) 1437 break; 1438 } 1439 return (error); 1440 } 1441 1442 /* 1443 * Idempotent 1444 */ 1445 static int 1446 t4_detach(device_t dev) 1447 { 1448 struct adapter *sc; 1449 int rc; 1450 1451 sc = device_get_softc(dev); 1452 1453 rc = notify_siblings(dev, 1); 1454 if (rc) { 1455 device_printf(dev, 1456 "failed to detach sibling devices: %d\n", rc); 1457 return (rc); 1458 } 1459 1460 return (t4_detach_common(dev)); 1461 } 1462 1463 int 1464 t4_detach_common(device_t dev) 1465 { 1466 struct adapter *sc; 1467 struct port_info *pi; 1468 int i, rc; 1469 1470 sc = device_get_softc(dev); 1471 1472 if (sc->cdev) { 1473 destroy_dev(sc->cdev); 1474 sc->cdev = NULL; 1475 } 1476 1477 sc->flags &= ~CHK_MBOX_ACCESS; 1478 if (sc->flags & FULL_INIT_DONE) { 1479 if (!(sc->flags & IS_VF)) 1480 t4_intr_disable(sc); 1481 } 1482 1483 if (device_is_attached(dev)) { 1484 rc = bus_generic_detach(dev); 1485 if (rc) { 1486 device_printf(dev, 1487 "failed to detach child devices: %d\n", rc); 1488 return (rc); 1489 } 1490 } 1491 1492 for (i = 0; i < sc->intr_count; i++) 1493 t4_free_irq(sc, &sc->irq[i]); 1494 1495 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1496 t4_free_tx_sched(sc); 1497 1498 for (i = 0; i < MAX_NPORTS; i++) { 1499 pi = sc->port[i]; 1500 if (pi) { 1501 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1502 if (pi->dev) 1503 device_delete_child(dev, pi->dev); 1504 1505 mtx_destroy(&pi->pi_lock); 1506 free(pi->vi, M_CXGBE); 1507 free(pi, M_CXGBE); 1508 } 1509 } 1510 1511 device_delete_children(dev); 1512 1513 if (sc->flags & FULL_INIT_DONE) 1514 adapter_full_uninit(sc); 1515 1516 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1517 t4_fw_bye(sc, sc->mbox); 1518 1519 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1520 pci_release_msi(dev); 1521 1522 if (sc->regs_res) 1523 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1524 sc->regs_res); 1525 1526 if (sc->udbs_res) 1527 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1528 sc->udbs_res); 1529 1530 if (sc->msix_res) 1531 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1532 sc->msix_res); 1533 1534 if (sc->l2t) 1535 t4_free_l2t(sc->l2t); 1536 if (sc->smt) 1537 t4_free_smt(sc->smt); 1538 #ifdef RATELIMIT 1539 t4_free_etid_table(sc); 1540 #endif 1541 if (sc->key_map) 1542 vmem_destroy(sc->key_map); 1543 #ifdef INET6 1544 t4_destroy_clip_table(sc); 1545 #endif 1546 1547 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1548 free(sc->sge.ofld_txq, M_CXGBE); 1549 #endif 1550 #ifdef TCP_OFFLOAD 1551 free(sc->sge.ofld_rxq, M_CXGBE); 1552 #endif 1553 #ifdef DEV_NETMAP 1554 free(sc->sge.nm_rxq, M_CXGBE); 1555 free(sc->sge.nm_txq, M_CXGBE); 1556 #endif 1557 free(sc->irq, M_CXGBE); 1558 free(sc->sge.rxq, M_CXGBE); 1559 free(sc->sge.txq, M_CXGBE); 1560 free(sc->sge.ctrlq, M_CXGBE); 1561 free(sc->sge.iqmap, M_CXGBE); 1562 free(sc->sge.eqmap, M_CXGBE); 1563 free(sc->tids.ftid_tab, M_CXGBE); 1564 free(sc->tids.hpftid_tab, M_CXGBE); 1565 free_hftid_hash(&sc->tids); 1566 free(sc->tids.atid_tab, M_CXGBE); 1567 free(sc->tids.tid_tab, M_CXGBE); 1568 free(sc->tt.tls_rx_ports, M_CXGBE); 1569 t4_destroy_dma_tag(sc); 1570 if (mtx_initialized(&sc->sc_lock)) { 1571 sx_xlock(&t4_list_lock); 1572 SLIST_REMOVE(&t4_list, sc, adapter, link); 1573 sx_xunlock(&t4_list_lock); 1574 mtx_destroy(&sc->sc_lock); 1575 } 1576 1577 callout_drain(&sc->sfl_callout); 1578 if (mtx_initialized(&sc->tids.ftid_lock)) { 1579 mtx_destroy(&sc->tids.ftid_lock); 1580 cv_destroy(&sc->tids.ftid_cv); 1581 } 1582 if (mtx_initialized(&sc->tids.atid_lock)) 1583 mtx_destroy(&sc->tids.atid_lock); 1584 if (mtx_initialized(&sc->sfl_lock)) 1585 mtx_destroy(&sc->sfl_lock); 1586 if (mtx_initialized(&sc->ifp_lock)) 1587 mtx_destroy(&sc->ifp_lock); 1588 if (mtx_initialized(&sc->reg_lock)) 1589 mtx_destroy(&sc->reg_lock); 1590 1591 if (rw_initialized(&sc->policy_lock)) { 1592 rw_destroy(&sc->policy_lock); 1593 #ifdef TCP_OFFLOAD 1594 if (sc->policy != NULL) 1595 free_offload_policy(sc->policy); 1596 #endif 1597 } 1598 1599 for (i = 0; i < NUM_MEMWIN; i++) { 1600 struct memwin *mw = &sc->memwin[i]; 1601 1602 if (rw_initialized(&mw->mw_lock)) 1603 rw_destroy(&mw->mw_lock); 1604 } 1605 1606 bzero(sc, sizeof(*sc)); 1607 1608 return (0); 1609 } 1610 1611 static int 1612 cxgbe_probe(device_t dev) 1613 { 1614 char buf[128]; 1615 struct port_info *pi = device_get_softc(dev); 1616 1617 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1618 device_set_desc_copy(dev, buf); 1619 1620 return (BUS_PROBE_DEFAULT); 1621 } 1622 1623 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1624 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1625 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 1626 IFCAP_HWRXTSTMP) 1627 #define T4_CAP_ENABLE (T4_CAP) 1628 1629 static int 1630 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1631 { 1632 struct ifnet *ifp; 1633 struct sbuf *sb; 1634 1635 vi->xact_addr_filt = -1; 1636 callout_init(&vi->tick, 1); 1637 1638 /* Allocate an ifnet and set it up */ 1639 ifp = if_alloc(IFT_ETHER); 1640 if (ifp == NULL) { 1641 device_printf(dev, "Cannot allocate ifnet\n"); 1642 return (ENOMEM); 1643 } 1644 vi->ifp = ifp; 1645 ifp->if_softc = vi; 1646 1647 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1648 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1649 1650 ifp->if_init = cxgbe_init; 1651 ifp->if_ioctl = cxgbe_ioctl; 1652 ifp->if_transmit = cxgbe_transmit; 1653 ifp->if_qflush = cxgbe_qflush; 1654 ifp->if_get_counter = cxgbe_get_counter; 1655 #ifdef RATELIMIT 1656 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 1657 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify; 1658 ifp->if_snd_tag_query = cxgbe_snd_tag_query; 1659 ifp->if_snd_tag_free = cxgbe_snd_tag_free; 1660 #endif 1661 1662 ifp->if_capabilities = T4_CAP; 1663 ifp->if_capenable = T4_CAP_ENABLE; 1664 #ifdef TCP_OFFLOAD 1665 if (vi->nofldrxq != 0) 1666 ifp->if_capabilities |= IFCAP_TOE; 1667 #endif 1668 #ifdef RATELIMIT 1669 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) { 1670 ifp->if_capabilities |= IFCAP_TXRTLMT; 1671 ifp->if_capenable |= IFCAP_TXRTLMT; 1672 } 1673 #endif 1674 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1675 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1676 1677 ifp->if_hw_tsomax = IP_MAXPACKET; 1678 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 1679 #ifdef RATELIMIT 1680 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) 1681 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO; 1682 #endif 1683 ifp->if_hw_tsomaxsegsize = 65536; 1684 1685 ether_ifattach(ifp, vi->hw_addr); 1686 #ifdef DEV_NETMAP 1687 if (vi->nnmrxq != 0) 1688 cxgbe_nm_attach(vi); 1689 #endif 1690 sb = sbuf_new_auto(); 1691 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1692 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1693 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 1694 case IFCAP_TOE: 1695 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 1696 break; 1697 case IFCAP_TOE | IFCAP_TXRTLMT: 1698 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 1699 break; 1700 case IFCAP_TXRTLMT: 1701 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 1702 break; 1703 } 1704 #endif 1705 #ifdef TCP_OFFLOAD 1706 if (ifp->if_capabilities & IFCAP_TOE) 1707 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 1708 #endif 1709 #ifdef DEV_NETMAP 1710 if (ifp->if_capabilities & IFCAP_NETMAP) 1711 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1712 vi->nnmtxq, vi->nnmrxq); 1713 #endif 1714 sbuf_finish(sb); 1715 device_printf(dev, "%s\n", sbuf_data(sb)); 1716 sbuf_delete(sb); 1717 1718 vi_sysctls(vi); 1719 1720 return (0); 1721 } 1722 1723 static int 1724 cxgbe_attach(device_t dev) 1725 { 1726 struct port_info *pi = device_get_softc(dev); 1727 struct adapter *sc = pi->adapter; 1728 struct vi_info *vi; 1729 int i, rc; 1730 1731 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1732 1733 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1734 if (rc) 1735 return (rc); 1736 1737 for_each_vi(pi, i, vi) { 1738 if (i == 0) 1739 continue; 1740 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1741 if (vi->dev == NULL) { 1742 device_printf(dev, "failed to add VI %d\n", i); 1743 continue; 1744 } 1745 device_set_softc(vi->dev, vi); 1746 } 1747 1748 cxgbe_sysctls(pi); 1749 1750 bus_generic_attach(dev); 1751 1752 return (0); 1753 } 1754 1755 static void 1756 cxgbe_vi_detach(struct vi_info *vi) 1757 { 1758 struct ifnet *ifp = vi->ifp; 1759 1760 ether_ifdetach(ifp); 1761 1762 /* Let detach proceed even if these fail. */ 1763 #ifdef DEV_NETMAP 1764 if (ifp->if_capabilities & IFCAP_NETMAP) 1765 cxgbe_nm_detach(vi); 1766 #endif 1767 cxgbe_uninit_synchronized(vi); 1768 callout_drain(&vi->tick); 1769 vi_full_uninit(vi); 1770 1771 if_free(vi->ifp); 1772 vi->ifp = NULL; 1773 } 1774 1775 static int 1776 cxgbe_detach(device_t dev) 1777 { 1778 struct port_info *pi = device_get_softc(dev); 1779 struct adapter *sc = pi->adapter; 1780 int rc; 1781 1782 /* Detach the extra VIs first. */ 1783 rc = bus_generic_detach(dev); 1784 if (rc) 1785 return (rc); 1786 device_delete_children(dev); 1787 1788 doom_vi(sc, &pi->vi[0]); 1789 1790 if (pi->flags & HAS_TRACEQ) { 1791 sc->traceq = -1; /* cloner should not create ifnet */ 1792 t4_tracer_port_detach(sc); 1793 } 1794 1795 cxgbe_vi_detach(&pi->vi[0]); 1796 callout_drain(&pi->tick); 1797 ifmedia_removeall(&pi->media); 1798 1799 end_synchronized_op(sc, 0); 1800 1801 return (0); 1802 } 1803 1804 static void 1805 cxgbe_init(void *arg) 1806 { 1807 struct vi_info *vi = arg; 1808 struct adapter *sc = vi->pi->adapter; 1809 1810 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1811 return; 1812 cxgbe_init_synchronized(vi); 1813 end_synchronized_op(sc, 0); 1814 } 1815 1816 static int 1817 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1818 { 1819 int rc = 0, mtu, flags; 1820 struct vi_info *vi = ifp->if_softc; 1821 struct port_info *pi = vi->pi; 1822 struct adapter *sc = pi->adapter; 1823 struct ifreq *ifr = (struct ifreq *)data; 1824 uint32_t mask; 1825 1826 switch (cmd) { 1827 case SIOCSIFMTU: 1828 mtu = ifr->ifr_mtu; 1829 if (mtu < ETHERMIN || mtu > MAX_MTU) 1830 return (EINVAL); 1831 1832 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1833 if (rc) 1834 return (rc); 1835 ifp->if_mtu = mtu; 1836 if (vi->flags & VI_INIT_DONE) { 1837 t4_update_fl_bufsize(ifp); 1838 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1839 rc = update_mac_settings(ifp, XGMAC_MTU); 1840 } 1841 end_synchronized_op(sc, 0); 1842 break; 1843 1844 case SIOCSIFFLAGS: 1845 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 1846 if (rc) 1847 return (rc); 1848 1849 if (ifp->if_flags & IFF_UP) { 1850 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1851 flags = vi->if_flags; 1852 if ((ifp->if_flags ^ flags) & 1853 (IFF_PROMISC | IFF_ALLMULTI)) { 1854 rc = update_mac_settings(ifp, 1855 XGMAC_PROMISC | XGMAC_ALLMULTI); 1856 } 1857 } else { 1858 rc = cxgbe_init_synchronized(vi); 1859 } 1860 vi->if_flags = ifp->if_flags; 1861 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1862 rc = cxgbe_uninit_synchronized(vi); 1863 } 1864 end_synchronized_op(sc, 0); 1865 break; 1866 1867 case SIOCADDMULTI: 1868 case SIOCDELMULTI: 1869 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 1870 if (rc) 1871 return (rc); 1872 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1873 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1874 end_synchronized_op(sc, 0); 1875 break; 1876 1877 case SIOCSIFCAP: 1878 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1879 if (rc) 1880 return (rc); 1881 1882 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1883 if (mask & IFCAP_TXCSUM) { 1884 ifp->if_capenable ^= IFCAP_TXCSUM; 1885 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1886 1887 if (IFCAP_TSO4 & ifp->if_capenable && 1888 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1889 ifp->if_capenable &= ~IFCAP_TSO4; 1890 if_printf(ifp, 1891 "tso4 disabled due to -txcsum.\n"); 1892 } 1893 } 1894 if (mask & IFCAP_TXCSUM_IPV6) { 1895 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1896 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1897 1898 if (IFCAP_TSO6 & ifp->if_capenable && 1899 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1900 ifp->if_capenable &= ~IFCAP_TSO6; 1901 if_printf(ifp, 1902 "tso6 disabled due to -txcsum6.\n"); 1903 } 1904 } 1905 if (mask & IFCAP_RXCSUM) 1906 ifp->if_capenable ^= IFCAP_RXCSUM; 1907 if (mask & IFCAP_RXCSUM_IPV6) 1908 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1909 1910 /* 1911 * Note that we leave CSUM_TSO alone (it is always set). The 1912 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1913 * sending a TSO request our way, so it's sufficient to toggle 1914 * IFCAP_TSOx only. 1915 */ 1916 if (mask & IFCAP_TSO4) { 1917 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1918 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1919 if_printf(ifp, "enable txcsum first.\n"); 1920 rc = EAGAIN; 1921 goto fail; 1922 } 1923 ifp->if_capenable ^= IFCAP_TSO4; 1924 } 1925 if (mask & IFCAP_TSO6) { 1926 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1927 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1928 if_printf(ifp, "enable txcsum6 first.\n"); 1929 rc = EAGAIN; 1930 goto fail; 1931 } 1932 ifp->if_capenable ^= IFCAP_TSO6; 1933 } 1934 if (mask & IFCAP_LRO) { 1935 #if defined(INET) || defined(INET6) 1936 int i; 1937 struct sge_rxq *rxq; 1938 1939 ifp->if_capenable ^= IFCAP_LRO; 1940 for_each_rxq(vi, i, rxq) { 1941 if (ifp->if_capenable & IFCAP_LRO) 1942 rxq->iq.flags |= IQ_LRO_ENABLED; 1943 else 1944 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1945 } 1946 #endif 1947 } 1948 #ifdef TCP_OFFLOAD 1949 if (mask & IFCAP_TOE) { 1950 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1951 1952 rc = toe_capability(vi, enable); 1953 if (rc != 0) 1954 goto fail; 1955 1956 ifp->if_capenable ^= mask; 1957 } 1958 #endif 1959 if (mask & IFCAP_VLAN_HWTAGGING) { 1960 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1961 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1962 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1963 } 1964 if (mask & IFCAP_VLAN_MTU) { 1965 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1966 1967 /* Need to find out how to disable auto-mtu-inflation */ 1968 } 1969 if (mask & IFCAP_VLAN_HWTSO) 1970 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1971 if (mask & IFCAP_VLAN_HWCSUM) 1972 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1973 #ifdef RATELIMIT 1974 if (mask & IFCAP_TXRTLMT) 1975 ifp->if_capenable ^= IFCAP_TXRTLMT; 1976 #endif 1977 if (mask & IFCAP_HWRXTSTMP) { 1978 int i; 1979 struct sge_rxq *rxq; 1980 1981 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 1982 for_each_rxq(vi, i, rxq) { 1983 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 1984 rxq->iq.flags |= IQ_RX_TIMESTAMP; 1985 else 1986 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 1987 } 1988 } 1989 1990 #ifdef VLAN_CAPABILITIES 1991 VLAN_CAPABILITIES(ifp); 1992 #endif 1993 fail: 1994 end_synchronized_op(sc, 0); 1995 break; 1996 1997 case SIOCSIFMEDIA: 1998 case SIOCGIFMEDIA: 1999 case SIOCGIFXMEDIA: 2000 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 2001 break; 2002 2003 case SIOCGI2C: { 2004 struct ifi2creq i2c; 2005 2006 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 2007 if (rc != 0) 2008 break; 2009 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 2010 rc = EPERM; 2011 break; 2012 } 2013 if (i2c.len > sizeof(i2c.data)) { 2014 rc = EINVAL; 2015 break; 2016 } 2017 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 2018 if (rc) 2019 return (rc); 2020 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 2021 i2c.offset, i2c.len, &i2c.data[0]); 2022 end_synchronized_op(sc, 0); 2023 if (rc == 0) 2024 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 2025 break; 2026 } 2027 2028 default: 2029 rc = ether_ioctl(ifp, cmd, data); 2030 } 2031 2032 return (rc); 2033 } 2034 2035 static int 2036 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 2037 { 2038 struct vi_info *vi = ifp->if_softc; 2039 struct port_info *pi = vi->pi; 2040 struct adapter *sc = pi->adapter; 2041 struct sge_txq *txq; 2042 void *items[1]; 2043 int rc; 2044 2045 M_ASSERTPKTHDR(m); 2046 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 2047 2048 if (__predict_false(pi->link_cfg.link_ok == false)) { 2049 m_freem(m); 2050 return (ENETDOWN); 2051 } 2052 2053 rc = parse_pkt(sc, &m); 2054 if (__predict_false(rc != 0)) { 2055 MPASS(m == NULL); /* was freed already */ 2056 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 2057 return (rc); 2058 } 2059 #ifdef RATELIMIT 2060 if (m->m_pkthdr.snd_tag != NULL) { 2061 /* EAGAIN tells the stack we are not the correct interface. */ 2062 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) { 2063 m_freem(m); 2064 return (EAGAIN); 2065 } 2066 2067 return (ethofld_transmit(ifp, m)); 2068 } 2069 #endif 2070 2071 /* Select a txq. */ 2072 txq = &sc->sge.txq[vi->first_txq]; 2073 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2074 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 2075 vi->rsrv_noflowq); 2076 2077 items[0] = m; 2078 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 2079 if (__predict_false(rc != 0)) 2080 m_freem(m); 2081 2082 return (rc); 2083 } 2084 2085 static void 2086 cxgbe_qflush(struct ifnet *ifp) 2087 { 2088 struct vi_info *vi = ifp->if_softc; 2089 struct sge_txq *txq; 2090 int i; 2091 2092 /* queues do not exist if !VI_INIT_DONE. */ 2093 if (vi->flags & VI_INIT_DONE) { 2094 for_each_txq(vi, i, txq) { 2095 TXQ_LOCK(txq); 2096 txq->eq.flags |= EQ_QFLUSH; 2097 TXQ_UNLOCK(txq); 2098 while (!mp_ring_is_idle(txq->r)) { 2099 mp_ring_check_drainage(txq->r, 0); 2100 pause("qflush", 1); 2101 } 2102 TXQ_LOCK(txq); 2103 txq->eq.flags &= ~EQ_QFLUSH; 2104 TXQ_UNLOCK(txq); 2105 } 2106 } 2107 if_qflush(ifp); 2108 } 2109 2110 static uint64_t 2111 vi_get_counter(struct ifnet *ifp, ift_counter c) 2112 { 2113 struct vi_info *vi = ifp->if_softc; 2114 struct fw_vi_stats_vf *s = &vi->stats; 2115 2116 vi_refresh_stats(vi->pi->adapter, vi); 2117 2118 switch (c) { 2119 case IFCOUNTER_IPACKETS: 2120 return (s->rx_bcast_frames + s->rx_mcast_frames + 2121 s->rx_ucast_frames); 2122 case IFCOUNTER_IERRORS: 2123 return (s->rx_err_frames); 2124 case IFCOUNTER_OPACKETS: 2125 return (s->tx_bcast_frames + s->tx_mcast_frames + 2126 s->tx_ucast_frames + s->tx_offload_frames); 2127 case IFCOUNTER_OERRORS: 2128 return (s->tx_drop_frames); 2129 case IFCOUNTER_IBYTES: 2130 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 2131 s->rx_ucast_bytes); 2132 case IFCOUNTER_OBYTES: 2133 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 2134 s->tx_ucast_bytes + s->tx_offload_bytes); 2135 case IFCOUNTER_IMCASTS: 2136 return (s->rx_mcast_frames); 2137 case IFCOUNTER_OMCASTS: 2138 return (s->tx_mcast_frames); 2139 case IFCOUNTER_OQDROPS: { 2140 uint64_t drops; 2141 2142 drops = 0; 2143 if (vi->flags & VI_INIT_DONE) { 2144 int i; 2145 struct sge_txq *txq; 2146 2147 for_each_txq(vi, i, txq) 2148 drops += counter_u64_fetch(txq->r->drops); 2149 } 2150 2151 return (drops); 2152 2153 } 2154 2155 default: 2156 return (if_get_counter_default(ifp, c)); 2157 } 2158 } 2159 2160 uint64_t 2161 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2162 { 2163 struct vi_info *vi = ifp->if_softc; 2164 struct port_info *pi = vi->pi; 2165 struct adapter *sc = pi->adapter; 2166 struct port_stats *s = &pi->stats; 2167 2168 if (pi->nvi > 1 || sc->flags & IS_VF) 2169 return (vi_get_counter(ifp, c)); 2170 2171 cxgbe_refresh_stats(sc, pi); 2172 2173 switch (c) { 2174 case IFCOUNTER_IPACKETS: 2175 return (s->rx_frames); 2176 2177 case IFCOUNTER_IERRORS: 2178 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2179 s->rx_fcs_err + s->rx_len_err); 2180 2181 case IFCOUNTER_OPACKETS: 2182 return (s->tx_frames); 2183 2184 case IFCOUNTER_OERRORS: 2185 return (s->tx_error_frames); 2186 2187 case IFCOUNTER_IBYTES: 2188 return (s->rx_octets); 2189 2190 case IFCOUNTER_OBYTES: 2191 return (s->tx_octets); 2192 2193 case IFCOUNTER_IMCASTS: 2194 return (s->rx_mcast_frames); 2195 2196 case IFCOUNTER_OMCASTS: 2197 return (s->tx_mcast_frames); 2198 2199 case IFCOUNTER_IQDROPS: 2200 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2201 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2202 s->rx_trunc3 + pi->tnl_cong_drops); 2203 2204 case IFCOUNTER_OQDROPS: { 2205 uint64_t drops; 2206 2207 drops = s->tx_drop; 2208 if (vi->flags & VI_INIT_DONE) { 2209 int i; 2210 struct sge_txq *txq; 2211 2212 for_each_txq(vi, i, txq) 2213 drops += counter_u64_fetch(txq->r->drops); 2214 } 2215 2216 return (drops); 2217 2218 } 2219 2220 default: 2221 return (if_get_counter_default(ifp, c)); 2222 } 2223 } 2224 2225 /* 2226 * The kernel picks a media from the list we had provided but we still validate 2227 * the requeste. 2228 */ 2229 int 2230 cxgbe_media_change(struct ifnet *ifp) 2231 { 2232 struct vi_info *vi = ifp->if_softc; 2233 struct port_info *pi = vi->pi; 2234 struct ifmedia *ifm = &pi->media; 2235 struct link_config *lc = &pi->link_cfg; 2236 struct adapter *sc = pi->adapter; 2237 int rc; 2238 2239 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2240 if (rc != 0) 2241 return (rc); 2242 PORT_LOCK(pi); 2243 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2244 /* ifconfig .. media autoselect */ 2245 if (!(lc->supported & FW_PORT_CAP32_ANEG)) { 2246 rc = ENOTSUP; /* AN not supported by transceiver */ 2247 goto done; 2248 } 2249 lc->requested_aneg = AUTONEG_ENABLE; 2250 lc->requested_speed = 0; 2251 lc->requested_fc |= PAUSE_AUTONEG; 2252 } else { 2253 lc->requested_aneg = AUTONEG_DISABLE; 2254 lc->requested_speed = 2255 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2256 lc->requested_fc = 0; 2257 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2258 lc->requested_fc |= PAUSE_RX; 2259 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2260 lc->requested_fc |= PAUSE_TX; 2261 } 2262 if (pi->up_vis > 0) { 2263 fixup_link_config(pi); 2264 rc = apply_link_config(pi); 2265 } 2266 done: 2267 PORT_UNLOCK(pi); 2268 end_synchronized_op(sc, 0); 2269 return (rc); 2270 } 2271 2272 /* 2273 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2274 * given speed. 2275 */ 2276 static int 2277 port_mword(struct port_info *pi, uint32_t speed) 2278 { 2279 2280 MPASS(speed & M_FW_PORT_CAP32_SPEED); 2281 MPASS(powerof2(speed)); 2282 2283 switch(pi->port_type) { 2284 case FW_PORT_TYPE_BT_SGMII: 2285 case FW_PORT_TYPE_BT_XFI: 2286 case FW_PORT_TYPE_BT_XAUI: 2287 /* BaseT */ 2288 switch (speed) { 2289 case FW_PORT_CAP32_SPEED_100M: 2290 return (IFM_100_T); 2291 case FW_PORT_CAP32_SPEED_1G: 2292 return (IFM_1000_T); 2293 case FW_PORT_CAP32_SPEED_10G: 2294 return (IFM_10G_T); 2295 } 2296 break; 2297 case FW_PORT_TYPE_KX4: 2298 if (speed == FW_PORT_CAP32_SPEED_10G) 2299 return (IFM_10G_KX4); 2300 break; 2301 case FW_PORT_TYPE_CX4: 2302 if (speed == FW_PORT_CAP32_SPEED_10G) 2303 return (IFM_10G_CX4); 2304 break; 2305 case FW_PORT_TYPE_KX: 2306 if (speed == FW_PORT_CAP32_SPEED_1G) 2307 return (IFM_1000_KX); 2308 break; 2309 case FW_PORT_TYPE_KR: 2310 case FW_PORT_TYPE_BP_AP: 2311 case FW_PORT_TYPE_BP4_AP: 2312 case FW_PORT_TYPE_BP40_BA: 2313 case FW_PORT_TYPE_KR4_100G: 2314 case FW_PORT_TYPE_KR_SFP28: 2315 case FW_PORT_TYPE_KR_XLAUI: 2316 switch (speed) { 2317 case FW_PORT_CAP32_SPEED_1G: 2318 return (IFM_1000_KX); 2319 case FW_PORT_CAP32_SPEED_10G: 2320 return (IFM_10G_KR); 2321 case FW_PORT_CAP32_SPEED_25G: 2322 return (IFM_25G_KR); 2323 case FW_PORT_CAP32_SPEED_40G: 2324 return (IFM_40G_KR4); 2325 case FW_PORT_CAP32_SPEED_50G: 2326 return (IFM_50G_KR2); 2327 case FW_PORT_CAP32_SPEED_100G: 2328 return (IFM_100G_KR4); 2329 } 2330 break; 2331 case FW_PORT_TYPE_FIBER_XFI: 2332 case FW_PORT_TYPE_FIBER_XAUI: 2333 case FW_PORT_TYPE_SFP: 2334 case FW_PORT_TYPE_QSFP_10G: 2335 case FW_PORT_TYPE_QSA: 2336 case FW_PORT_TYPE_QSFP: 2337 case FW_PORT_TYPE_CR4_QSFP: 2338 case FW_PORT_TYPE_CR_QSFP: 2339 case FW_PORT_TYPE_CR2_QSFP: 2340 case FW_PORT_TYPE_SFP28: 2341 /* Pluggable transceiver */ 2342 switch (pi->mod_type) { 2343 case FW_PORT_MOD_TYPE_LR: 2344 switch (speed) { 2345 case FW_PORT_CAP32_SPEED_1G: 2346 return (IFM_1000_LX); 2347 case FW_PORT_CAP32_SPEED_10G: 2348 return (IFM_10G_LR); 2349 case FW_PORT_CAP32_SPEED_25G: 2350 return (IFM_25G_LR); 2351 case FW_PORT_CAP32_SPEED_40G: 2352 return (IFM_40G_LR4); 2353 case FW_PORT_CAP32_SPEED_50G: 2354 return (IFM_50G_LR2); 2355 case FW_PORT_CAP32_SPEED_100G: 2356 return (IFM_100G_LR4); 2357 } 2358 break; 2359 case FW_PORT_MOD_TYPE_SR: 2360 switch (speed) { 2361 case FW_PORT_CAP32_SPEED_1G: 2362 return (IFM_1000_SX); 2363 case FW_PORT_CAP32_SPEED_10G: 2364 return (IFM_10G_SR); 2365 case FW_PORT_CAP32_SPEED_25G: 2366 return (IFM_25G_SR); 2367 case FW_PORT_CAP32_SPEED_40G: 2368 return (IFM_40G_SR4); 2369 case FW_PORT_CAP32_SPEED_50G: 2370 return (IFM_50G_SR2); 2371 case FW_PORT_CAP32_SPEED_100G: 2372 return (IFM_100G_SR4); 2373 } 2374 break; 2375 case FW_PORT_MOD_TYPE_ER: 2376 if (speed == FW_PORT_CAP32_SPEED_10G) 2377 return (IFM_10G_ER); 2378 break; 2379 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2380 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2381 switch (speed) { 2382 case FW_PORT_CAP32_SPEED_1G: 2383 return (IFM_1000_CX); 2384 case FW_PORT_CAP32_SPEED_10G: 2385 return (IFM_10G_TWINAX); 2386 case FW_PORT_CAP32_SPEED_25G: 2387 return (IFM_25G_CR); 2388 case FW_PORT_CAP32_SPEED_40G: 2389 return (IFM_40G_CR4); 2390 case FW_PORT_CAP32_SPEED_50G: 2391 return (IFM_50G_CR2); 2392 case FW_PORT_CAP32_SPEED_100G: 2393 return (IFM_100G_CR4); 2394 } 2395 break; 2396 case FW_PORT_MOD_TYPE_LRM: 2397 if (speed == FW_PORT_CAP32_SPEED_10G) 2398 return (IFM_10G_LRM); 2399 break; 2400 case FW_PORT_MOD_TYPE_NA: 2401 MPASS(0); /* Not pluggable? */ 2402 /* fall throough */ 2403 case FW_PORT_MOD_TYPE_ERROR: 2404 case FW_PORT_MOD_TYPE_UNKNOWN: 2405 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2406 break; 2407 case FW_PORT_MOD_TYPE_NONE: 2408 return (IFM_NONE); 2409 } 2410 break; 2411 case FW_PORT_TYPE_NONE: 2412 return (IFM_NONE); 2413 } 2414 2415 return (IFM_UNKNOWN); 2416 } 2417 2418 void 2419 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2420 { 2421 struct vi_info *vi = ifp->if_softc; 2422 struct port_info *pi = vi->pi; 2423 struct adapter *sc = pi->adapter; 2424 struct link_config *lc = &pi->link_cfg; 2425 2426 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2427 return; 2428 PORT_LOCK(pi); 2429 2430 if (pi->up_vis == 0) { 2431 /* 2432 * If all the interfaces are administratively down the firmware 2433 * does not report transceiver changes. Refresh port info here 2434 * so that ifconfig displays accurate ifmedia at all times. 2435 * This is the only reason we have a synchronized op in this 2436 * function. Just PORT_LOCK would have been enough otherwise. 2437 */ 2438 t4_update_port_info(pi); 2439 build_medialist(pi); 2440 } 2441 2442 /* ifm_status */ 2443 ifmr->ifm_status = IFM_AVALID; 2444 if (lc->link_ok == false) 2445 goto done; 2446 ifmr->ifm_status |= IFM_ACTIVE; 2447 2448 /* ifm_active */ 2449 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2450 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2451 if (lc->fc & PAUSE_RX) 2452 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2453 if (lc->fc & PAUSE_TX) 2454 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2455 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 2456 done: 2457 PORT_UNLOCK(pi); 2458 end_synchronized_op(sc, 0); 2459 } 2460 2461 static int 2462 vcxgbe_probe(device_t dev) 2463 { 2464 char buf[128]; 2465 struct vi_info *vi = device_get_softc(dev); 2466 2467 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2468 vi - vi->pi->vi); 2469 device_set_desc_copy(dev, buf); 2470 2471 return (BUS_PROBE_DEFAULT); 2472 } 2473 2474 static int 2475 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2476 { 2477 int func, index, rc; 2478 uint32_t param, val; 2479 2480 ASSERT_SYNCHRONIZED_OP(sc); 2481 2482 index = vi - pi->vi; 2483 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2484 KASSERT(index < nitems(vi_mac_funcs), 2485 ("%s: VI %s doesn't have a MAC func", __func__, 2486 device_get_nameunit(vi->dev))); 2487 func = vi_mac_funcs[index]; 2488 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2489 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 2490 if (rc < 0) { 2491 device_printf(vi->dev, "failed to allocate virtual interface %d" 2492 "for port %d: %d\n", index, pi->port_id, -rc); 2493 return (-rc); 2494 } 2495 vi->viid = rc; 2496 2497 if (vi->rss_size == 1) { 2498 /* 2499 * This VI didn't get a slice of the RSS table. Reduce the 2500 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2501 * configuration file (nvi, rssnvi for this PF) if this is a 2502 * problem. 2503 */ 2504 device_printf(vi->dev, "RSS table not available.\n"); 2505 vi->rss_base = 0xffff; 2506 2507 return (0); 2508 } 2509 2510 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2511 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2512 V_FW_PARAMS_PARAM_YZ(vi->viid); 2513 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2514 if (rc) 2515 vi->rss_base = 0xffff; 2516 else { 2517 MPASS((val >> 16) == vi->rss_size); 2518 vi->rss_base = val & 0xffff; 2519 } 2520 2521 return (0); 2522 } 2523 2524 static int 2525 vcxgbe_attach(device_t dev) 2526 { 2527 struct vi_info *vi; 2528 struct port_info *pi; 2529 struct adapter *sc; 2530 int rc; 2531 2532 vi = device_get_softc(dev); 2533 pi = vi->pi; 2534 sc = pi->adapter; 2535 2536 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2537 if (rc) 2538 return (rc); 2539 rc = alloc_extra_vi(sc, pi, vi); 2540 end_synchronized_op(sc, 0); 2541 if (rc) 2542 return (rc); 2543 2544 rc = cxgbe_vi_attach(dev, vi); 2545 if (rc) { 2546 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2547 return (rc); 2548 } 2549 return (0); 2550 } 2551 2552 static int 2553 vcxgbe_detach(device_t dev) 2554 { 2555 struct vi_info *vi; 2556 struct adapter *sc; 2557 2558 vi = device_get_softc(dev); 2559 sc = vi->pi->adapter; 2560 2561 doom_vi(sc, vi); 2562 2563 cxgbe_vi_detach(vi); 2564 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2565 2566 end_synchronized_op(sc, 0); 2567 2568 return (0); 2569 } 2570 2571 static struct callout fatal_callout; 2572 2573 static void 2574 delayed_panic(void *arg) 2575 { 2576 struct adapter *sc = arg; 2577 2578 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 2579 } 2580 2581 void 2582 t4_fatal_err(struct adapter *sc, bool fw_error) 2583 { 2584 2585 t4_shutdown_adapter(sc); 2586 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n", 2587 device_get_nameunit(sc->dev)); 2588 if (fw_error) { 2589 ASSERT_SYNCHRONIZED_OP(sc); 2590 sc->flags |= ADAP_ERR; 2591 } else { 2592 ADAPTER_LOCK(sc); 2593 sc->flags |= ADAP_ERR; 2594 ADAPTER_UNLOCK(sc); 2595 } 2596 2597 if (t4_panic_on_fatal_err) { 2598 log(LOG_ALERT, "%s: panic on fatal error after 30s", 2599 device_get_nameunit(sc->dev)); 2600 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 2601 } 2602 } 2603 2604 void 2605 t4_add_adapter(struct adapter *sc) 2606 { 2607 sx_xlock(&t4_list_lock); 2608 SLIST_INSERT_HEAD(&t4_list, sc, link); 2609 sx_xunlock(&t4_list_lock); 2610 } 2611 2612 int 2613 t4_map_bars_0_and_4(struct adapter *sc) 2614 { 2615 sc->regs_rid = PCIR_BAR(0); 2616 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2617 &sc->regs_rid, RF_ACTIVE); 2618 if (sc->regs_res == NULL) { 2619 device_printf(sc->dev, "cannot map registers.\n"); 2620 return (ENXIO); 2621 } 2622 sc->bt = rman_get_bustag(sc->regs_res); 2623 sc->bh = rman_get_bushandle(sc->regs_res); 2624 sc->mmio_len = rman_get_size(sc->regs_res); 2625 setbit(&sc->doorbells, DOORBELL_KDB); 2626 2627 sc->msix_rid = PCIR_BAR(4); 2628 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2629 &sc->msix_rid, RF_ACTIVE); 2630 if (sc->msix_res == NULL) { 2631 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2632 return (ENXIO); 2633 } 2634 2635 return (0); 2636 } 2637 2638 int 2639 t4_map_bar_2(struct adapter *sc) 2640 { 2641 2642 /* 2643 * T4: only iWARP driver uses the userspace doorbells. There is no need 2644 * to map it if RDMA is disabled. 2645 */ 2646 if (is_t4(sc) && sc->rdmacaps == 0) 2647 return (0); 2648 2649 sc->udbs_rid = PCIR_BAR(2); 2650 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2651 &sc->udbs_rid, RF_ACTIVE); 2652 if (sc->udbs_res == NULL) { 2653 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2654 return (ENXIO); 2655 } 2656 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2657 2658 if (chip_id(sc) >= CHELSIO_T5) { 2659 setbit(&sc->doorbells, DOORBELL_UDB); 2660 #if defined(__i386__) || defined(__amd64__) 2661 if (t5_write_combine) { 2662 int rc, mode; 2663 2664 /* 2665 * Enable write combining on BAR2. This is the 2666 * userspace doorbell BAR and is split into 128B 2667 * (UDBS_SEG_SIZE) doorbell regions, each associated 2668 * with an egress queue. The first 64B has the doorbell 2669 * and the second 64B can be used to submit a tx work 2670 * request with an implicit doorbell. 2671 */ 2672 2673 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2674 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2675 if (rc == 0) { 2676 clrbit(&sc->doorbells, DOORBELL_UDB); 2677 setbit(&sc->doorbells, DOORBELL_WCWR); 2678 setbit(&sc->doorbells, DOORBELL_UDBWC); 2679 } else { 2680 device_printf(sc->dev, 2681 "couldn't enable write combining: %d\n", 2682 rc); 2683 } 2684 2685 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2686 t4_write_reg(sc, A_SGE_STAT_CFG, 2687 V_STATSOURCE_T5(7) | mode); 2688 } 2689 #endif 2690 } 2691 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2692 2693 return (0); 2694 } 2695 2696 struct memwin_init { 2697 uint32_t base; 2698 uint32_t aperture; 2699 }; 2700 2701 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2702 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2703 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2704 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2705 }; 2706 2707 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2708 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2709 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2710 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2711 }; 2712 2713 static void 2714 setup_memwin(struct adapter *sc) 2715 { 2716 const struct memwin_init *mw_init; 2717 struct memwin *mw; 2718 int i; 2719 uint32_t bar0; 2720 2721 if (is_t4(sc)) { 2722 /* 2723 * Read low 32b of bar0 indirectly via the hardware backdoor 2724 * mechanism. Works from within PCI passthrough environments 2725 * too, where rman_get_start() can return a different value. We 2726 * need to program the T4 memory window decoders with the actual 2727 * addresses that will be coming across the PCIe link. 2728 */ 2729 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2730 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2731 2732 mw_init = &t4_memwin[0]; 2733 } else { 2734 /* T5+ use the relative offset inside the PCIe BAR */ 2735 bar0 = 0; 2736 2737 mw_init = &t5_memwin[0]; 2738 } 2739 2740 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2741 rw_init(&mw->mw_lock, "memory window access"); 2742 mw->mw_base = mw_init->base; 2743 mw->mw_aperture = mw_init->aperture; 2744 mw->mw_curpos = 0; 2745 t4_write_reg(sc, 2746 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2747 (mw->mw_base + bar0) | V_BIR(0) | 2748 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2749 rw_wlock(&mw->mw_lock); 2750 position_memwin(sc, i, 0); 2751 rw_wunlock(&mw->mw_lock); 2752 } 2753 2754 /* flush */ 2755 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2756 } 2757 2758 /* 2759 * Positions the memory window at the given address in the card's address space. 2760 * There are some alignment requirements and the actual position may be at an 2761 * address prior to the requested address. mw->mw_curpos always has the actual 2762 * position of the window. 2763 */ 2764 static void 2765 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2766 { 2767 struct memwin *mw; 2768 uint32_t pf; 2769 uint32_t reg; 2770 2771 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2772 mw = &sc->memwin[idx]; 2773 rw_assert(&mw->mw_lock, RA_WLOCKED); 2774 2775 if (is_t4(sc)) { 2776 pf = 0; 2777 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2778 } else { 2779 pf = V_PFNUM(sc->pf); 2780 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2781 } 2782 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2783 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2784 t4_read_reg(sc, reg); /* flush */ 2785 } 2786 2787 int 2788 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2789 int len, int rw) 2790 { 2791 struct memwin *mw; 2792 uint32_t mw_end, v; 2793 2794 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2795 2796 /* Memory can only be accessed in naturally aligned 4 byte units */ 2797 if (addr & 3 || len & 3 || len <= 0) 2798 return (EINVAL); 2799 2800 mw = &sc->memwin[idx]; 2801 while (len > 0) { 2802 rw_rlock(&mw->mw_lock); 2803 mw_end = mw->mw_curpos + mw->mw_aperture; 2804 if (addr >= mw_end || addr < mw->mw_curpos) { 2805 /* Will need to reposition the window */ 2806 if (!rw_try_upgrade(&mw->mw_lock)) { 2807 rw_runlock(&mw->mw_lock); 2808 rw_wlock(&mw->mw_lock); 2809 } 2810 rw_assert(&mw->mw_lock, RA_WLOCKED); 2811 position_memwin(sc, idx, addr); 2812 rw_downgrade(&mw->mw_lock); 2813 mw_end = mw->mw_curpos + mw->mw_aperture; 2814 } 2815 rw_assert(&mw->mw_lock, RA_RLOCKED); 2816 while (addr < mw_end && len > 0) { 2817 if (rw == 0) { 2818 v = t4_read_reg(sc, mw->mw_base + addr - 2819 mw->mw_curpos); 2820 *val++ = le32toh(v); 2821 } else { 2822 v = *val++; 2823 t4_write_reg(sc, mw->mw_base + addr - 2824 mw->mw_curpos, htole32(v)); 2825 } 2826 addr += 4; 2827 len -= 4; 2828 } 2829 rw_runlock(&mw->mw_lock); 2830 } 2831 2832 return (0); 2833 } 2834 2835 int 2836 alloc_atid_tab(struct tid_info *t, int flags) 2837 { 2838 int i; 2839 2840 MPASS(t->natids > 0); 2841 MPASS(t->atid_tab == NULL); 2842 2843 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2844 M_ZERO | flags); 2845 if (t->atid_tab == NULL) 2846 return (ENOMEM); 2847 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2848 t->afree = t->atid_tab; 2849 t->atids_in_use = 0; 2850 for (i = 1; i < t->natids; i++) 2851 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2852 t->atid_tab[t->natids - 1].next = NULL; 2853 2854 return (0); 2855 } 2856 2857 void 2858 free_atid_tab(struct tid_info *t) 2859 { 2860 2861 KASSERT(t->atids_in_use == 0, 2862 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2863 2864 if (mtx_initialized(&t->atid_lock)) 2865 mtx_destroy(&t->atid_lock); 2866 free(t->atid_tab, M_CXGBE); 2867 t->atid_tab = NULL; 2868 } 2869 2870 int 2871 alloc_atid(struct adapter *sc, void *ctx) 2872 { 2873 struct tid_info *t = &sc->tids; 2874 int atid = -1; 2875 2876 mtx_lock(&t->atid_lock); 2877 if (t->afree) { 2878 union aopen_entry *p = t->afree; 2879 2880 atid = p - t->atid_tab; 2881 MPASS(atid <= M_TID_TID); 2882 t->afree = p->next; 2883 p->data = ctx; 2884 t->atids_in_use++; 2885 } 2886 mtx_unlock(&t->atid_lock); 2887 return (atid); 2888 } 2889 2890 void * 2891 lookup_atid(struct adapter *sc, int atid) 2892 { 2893 struct tid_info *t = &sc->tids; 2894 2895 return (t->atid_tab[atid].data); 2896 } 2897 2898 void 2899 free_atid(struct adapter *sc, int atid) 2900 { 2901 struct tid_info *t = &sc->tids; 2902 union aopen_entry *p = &t->atid_tab[atid]; 2903 2904 mtx_lock(&t->atid_lock); 2905 p->next = t->afree; 2906 t->afree = p; 2907 t->atids_in_use--; 2908 mtx_unlock(&t->atid_lock); 2909 } 2910 2911 static void 2912 queue_tid_release(struct adapter *sc, int tid) 2913 { 2914 2915 CXGBE_UNIMPLEMENTED("deferred tid release"); 2916 } 2917 2918 void 2919 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2920 { 2921 struct wrqe *wr; 2922 struct cpl_tid_release *req; 2923 2924 wr = alloc_wrqe(sizeof(*req), ctrlq); 2925 if (wr == NULL) { 2926 queue_tid_release(sc, tid); /* defer */ 2927 return; 2928 } 2929 req = wrtod(wr); 2930 2931 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2932 2933 t4_wrq_tx(sc, wr); 2934 } 2935 2936 static int 2937 t4_range_cmp(const void *a, const void *b) 2938 { 2939 return ((const struct t4_range *)a)->start - 2940 ((const struct t4_range *)b)->start; 2941 } 2942 2943 /* 2944 * Verify that the memory range specified by the addr/len pair is valid within 2945 * the card's address space. 2946 */ 2947 static int 2948 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 2949 { 2950 struct t4_range mem_ranges[4], *r, *next; 2951 uint32_t em, addr_len; 2952 int i, n, remaining; 2953 2954 /* Memory can only be accessed in naturally aligned 4 byte units */ 2955 if (addr & 3 || len & 3 || len == 0) 2956 return (EINVAL); 2957 2958 /* Enabled memories */ 2959 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2960 2961 r = &mem_ranges[0]; 2962 n = 0; 2963 bzero(r, sizeof(mem_ranges)); 2964 if (em & F_EDRAM0_ENABLE) { 2965 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2966 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2967 if (r->size > 0) { 2968 r->start = G_EDRAM0_BASE(addr_len) << 20; 2969 if (addr >= r->start && 2970 addr + len <= r->start + r->size) 2971 return (0); 2972 r++; 2973 n++; 2974 } 2975 } 2976 if (em & F_EDRAM1_ENABLE) { 2977 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2978 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2979 if (r->size > 0) { 2980 r->start = G_EDRAM1_BASE(addr_len) << 20; 2981 if (addr >= r->start && 2982 addr + len <= r->start + r->size) 2983 return (0); 2984 r++; 2985 n++; 2986 } 2987 } 2988 if (em & F_EXT_MEM_ENABLE) { 2989 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2990 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2991 if (r->size > 0) { 2992 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2993 if (addr >= r->start && 2994 addr + len <= r->start + r->size) 2995 return (0); 2996 r++; 2997 n++; 2998 } 2999 } 3000 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 3001 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3002 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 3003 if (r->size > 0) { 3004 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 3005 if (addr >= r->start && 3006 addr + len <= r->start + r->size) 3007 return (0); 3008 r++; 3009 n++; 3010 } 3011 } 3012 MPASS(n <= nitems(mem_ranges)); 3013 3014 if (n > 1) { 3015 /* Sort and merge the ranges. */ 3016 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 3017 3018 /* Start from index 0 and examine the next n - 1 entries. */ 3019 r = &mem_ranges[0]; 3020 for (remaining = n - 1; remaining > 0; remaining--, r++) { 3021 3022 MPASS(r->size > 0); /* r is a valid entry. */ 3023 next = r + 1; 3024 MPASS(next->size > 0); /* and so is the next one. */ 3025 3026 while (r->start + r->size >= next->start) { 3027 /* Merge the next one into the current entry. */ 3028 r->size = max(r->start + r->size, 3029 next->start + next->size) - r->start; 3030 n--; /* One fewer entry in total. */ 3031 if (--remaining == 0) 3032 goto done; /* short circuit */ 3033 next++; 3034 } 3035 if (next != r + 1) { 3036 /* 3037 * Some entries were merged into r and next 3038 * points to the first valid entry that couldn't 3039 * be merged. 3040 */ 3041 MPASS(next->size > 0); /* must be valid */ 3042 memcpy(r + 1, next, remaining * sizeof(*r)); 3043 #ifdef INVARIANTS 3044 /* 3045 * This so that the foo->size assertion in the 3046 * next iteration of the loop do the right 3047 * thing for entries that were pulled up and are 3048 * no longer valid. 3049 */ 3050 MPASS(n < nitems(mem_ranges)); 3051 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 3052 sizeof(struct t4_range)); 3053 #endif 3054 } 3055 } 3056 done: 3057 /* Done merging the ranges. */ 3058 MPASS(n > 0); 3059 r = &mem_ranges[0]; 3060 for (i = 0; i < n; i++, r++) { 3061 if (addr >= r->start && 3062 addr + len <= r->start + r->size) 3063 return (0); 3064 } 3065 } 3066 3067 return (EFAULT); 3068 } 3069 3070 static int 3071 fwmtype_to_hwmtype(int mtype) 3072 { 3073 3074 switch (mtype) { 3075 case FW_MEMTYPE_EDC0: 3076 return (MEM_EDC0); 3077 case FW_MEMTYPE_EDC1: 3078 return (MEM_EDC1); 3079 case FW_MEMTYPE_EXTMEM: 3080 return (MEM_MC0); 3081 case FW_MEMTYPE_EXTMEM1: 3082 return (MEM_MC1); 3083 default: 3084 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 3085 } 3086 } 3087 3088 /* 3089 * Verify that the memory range specified by the memtype/offset/len pair is 3090 * valid and lies entirely within the memtype specified. The global address of 3091 * the start of the range is returned in addr. 3092 */ 3093 static int 3094 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 3095 uint32_t *addr) 3096 { 3097 uint32_t em, addr_len, maddr; 3098 3099 /* Memory can only be accessed in naturally aligned 4 byte units */ 3100 if (off & 3 || len & 3 || len == 0) 3101 return (EINVAL); 3102 3103 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3104 switch (fwmtype_to_hwmtype(mtype)) { 3105 case MEM_EDC0: 3106 if (!(em & F_EDRAM0_ENABLE)) 3107 return (EINVAL); 3108 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3109 maddr = G_EDRAM0_BASE(addr_len) << 20; 3110 break; 3111 case MEM_EDC1: 3112 if (!(em & F_EDRAM1_ENABLE)) 3113 return (EINVAL); 3114 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3115 maddr = G_EDRAM1_BASE(addr_len) << 20; 3116 break; 3117 case MEM_MC: 3118 if (!(em & F_EXT_MEM_ENABLE)) 3119 return (EINVAL); 3120 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3121 maddr = G_EXT_MEM_BASE(addr_len) << 20; 3122 break; 3123 case MEM_MC1: 3124 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 3125 return (EINVAL); 3126 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3127 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 3128 break; 3129 default: 3130 return (EINVAL); 3131 } 3132 3133 *addr = maddr + off; /* global address */ 3134 return (validate_mem_range(sc, *addr, len)); 3135 } 3136 3137 static int 3138 fixup_devlog_params(struct adapter *sc) 3139 { 3140 struct devlog_params *dparams = &sc->params.devlog; 3141 int rc; 3142 3143 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 3144 dparams->size, &dparams->addr); 3145 3146 return (rc); 3147 } 3148 3149 static void 3150 update_nirq(struct intrs_and_queues *iaq, int nports) 3151 { 3152 int extra = T4_EXTRA_INTR; 3153 3154 iaq->nirq = extra; 3155 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 3156 iaq->nirq += nports * (iaq->num_vis - 1) * 3157 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 3158 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 3159 } 3160 3161 /* 3162 * Adjust requirements to fit the number of interrupts available. 3163 */ 3164 static void 3165 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 3166 int navail) 3167 { 3168 int old_nirq; 3169 const int nports = sc->params.nports; 3170 3171 MPASS(nports > 0); 3172 MPASS(navail > 0); 3173 3174 bzero(iaq, sizeof(*iaq)); 3175 iaq->intr_type = itype; 3176 iaq->num_vis = t4_num_vis; 3177 iaq->ntxq = t4_ntxq; 3178 iaq->ntxq_vi = t4_ntxq_vi; 3179 iaq->nrxq = t4_nrxq; 3180 iaq->nrxq_vi = t4_nrxq_vi; 3181 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3182 if (is_offload(sc) || is_ethoffload(sc)) { 3183 iaq->nofldtxq = t4_nofldtxq; 3184 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3185 } 3186 #endif 3187 #ifdef TCP_OFFLOAD 3188 if (is_offload(sc)) { 3189 iaq->nofldrxq = t4_nofldrxq; 3190 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3191 } 3192 #endif 3193 #ifdef DEV_NETMAP 3194 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3195 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3196 #endif 3197 3198 update_nirq(iaq, nports); 3199 if (iaq->nirq <= navail && 3200 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3201 /* 3202 * This is the normal case -- there are enough interrupts for 3203 * everything. 3204 */ 3205 goto done; 3206 } 3207 3208 /* 3209 * If extra VIs have been configured try reducing their count and see if 3210 * that works. 3211 */ 3212 while (iaq->num_vis > 1) { 3213 iaq->num_vis--; 3214 update_nirq(iaq, nports); 3215 if (iaq->nirq <= navail && 3216 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3217 device_printf(sc->dev, "virtual interfaces per port " 3218 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3219 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3220 "itype %d, navail %u, nirq %d.\n", 3221 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3222 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3223 itype, navail, iaq->nirq); 3224 goto done; 3225 } 3226 } 3227 3228 /* 3229 * Extra VIs will not be created. Log a message if they were requested. 3230 */ 3231 MPASS(iaq->num_vis == 1); 3232 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3233 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3234 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3235 if (iaq->num_vis != t4_num_vis) { 3236 device_printf(sc->dev, "extra virtual interfaces disabled. " 3237 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3238 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3239 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3240 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3241 } 3242 3243 /* 3244 * Keep reducing the number of NIC rx queues to the next lower power of 3245 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3246 * if that works. 3247 */ 3248 do { 3249 if (iaq->nrxq > 1) { 3250 do { 3251 iaq->nrxq--; 3252 } while (!powerof2(iaq->nrxq)); 3253 } 3254 if (iaq->nofldrxq > 1) 3255 iaq->nofldrxq >>= 1; 3256 3257 old_nirq = iaq->nirq; 3258 update_nirq(iaq, nports); 3259 if (iaq->nirq <= navail && 3260 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3261 device_printf(sc->dev, "running with reduced number of " 3262 "rx queues because of shortage of interrupts. " 3263 "nrxq=%u, nofldrxq=%u. " 3264 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3265 iaq->nofldrxq, itype, navail, iaq->nirq); 3266 goto done; 3267 } 3268 } while (old_nirq != iaq->nirq); 3269 3270 /* One interrupt for everything. Ugh. */ 3271 device_printf(sc->dev, "running with minimal number of queues. " 3272 "itype %d, navail %u.\n", itype, navail); 3273 iaq->nirq = 1; 3274 MPASS(iaq->nrxq == 1); 3275 iaq->ntxq = 1; 3276 if (iaq->nofldrxq > 1) 3277 iaq->nofldtxq = 1; 3278 done: 3279 MPASS(iaq->num_vis > 0); 3280 if (iaq->num_vis > 1) { 3281 MPASS(iaq->nrxq_vi > 0); 3282 MPASS(iaq->ntxq_vi > 0); 3283 } 3284 MPASS(iaq->nirq > 0); 3285 MPASS(iaq->nrxq > 0); 3286 MPASS(iaq->ntxq > 0); 3287 if (itype == INTR_MSI) { 3288 MPASS(powerof2(iaq->nirq)); 3289 } 3290 } 3291 3292 static int 3293 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3294 { 3295 int rc, itype, navail, nalloc; 3296 3297 for (itype = INTR_MSIX; itype; itype >>= 1) { 3298 3299 if ((itype & t4_intr_types) == 0) 3300 continue; /* not allowed */ 3301 3302 if (itype == INTR_MSIX) 3303 navail = pci_msix_count(sc->dev); 3304 else if (itype == INTR_MSI) 3305 navail = pci_msi_count(sc->dev); 3306 else 3307 navail = 1; 3308 restart: 3309 if (navail == 0) 3310 continue; 3311 3312 calculate_iaq(sc, iaq, itype, navail); 3313 nalloc = iaq->nirq; 3314 rc = 0; 3315 if (itype == INTR_MSIX) 3316 rc = pci_alloc_msix(sc->dev, &nalloc); 3317 else if (itype == INTR_MSI) 3318 rc = pci_alloc_msi(sc->dev, &nalloc); 3319 3320 if (rc == 0 && nalloc > 0) { 3321 if (nalloc == iaq->nirq) 3322 return (0); 3323 3324 /* 3325 * Didn't get the number requested. Use whatever number 3326 * the kernel is willing to allocate. 3327 */ 3328 device_printf(sc->dev, "fewer vectors than requested, " 3329 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3330 itype, iaq->nirq, nalloc); 3331 pci_release_msi(sc->dev); 3332 navail = nalloc; 3333 goto restart; 3334 } 3335 3336 device_printf(sc->dev, 3337 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3338 itype, rc, iaq->nirq, nalloc); 3339 } 3340 3341 device_printf(sc->dev, 3342 "failed to find a usable interrupt type. " 3343 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3344 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3345 3346 return (ENXIO); 3347 } 3348 3349 #define FW_VERSION(chip) ( \ 3350 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3351 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3352 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3353 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3354 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3355 3356 /* Just enough of fw_hdr to cover all version info. */ 3357 struct fw_h { 3358 __u8 ver; 3359 __u8 chip; 3360 __be16 len512; 3361 __be32 fw_ver; 3362 __be32 tp_microcode_ver; 3363 __u8 intfver_nic; 3364 __u8 intfver_vnic; 3365 __u8 intfver_ofld; 3366 __u8 intfver_ri; 3367 __u8 intfver_iscsipdu; 3368 __u8 intfver_iscsi; 3369 __u8 intfver_fcoepdu; 3370 __u8 intfver_fcoe; 3371 }; 3372 /* Spot check a couple of fields. */ 3373 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 3374 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 3375 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 3376 3377 struct fw_info { 3378 uint8_t chip; 3379 char *kld_name; 3380 char *fw_mod_name; 3381 struct fw_h fw_h; 3382 } fw_info[] = { 3383 { 3384 .chip = CHELSIO_T4, 3385 .kld_name = "t4fw_cfg", 3386 .fw_mod_name = "t4fw", 3387 .fw_h = { 3388 .chip = FW_HDR_CHIP_T4, 3389 .fw_ver = htobe32(FW_VERSION(T4)), 3390 .intfver_nic = FW_INTFVER(T4, NIC), 3391 .intfver_vnic = FW_INTFVER(T4, VNIC), 3392 .intfver_ofld = FW_INTFVER(T4, OFLD), 3393 .intfver_ri = FW_INTFVER(T4, RI), 3394 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3395 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3396 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3397 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3398 }, 3399 }, { 3400 .chip = CHELSIO_T5, 3401 .kld_name = "t5fw_cfg", 3402 .fw_mod_name = "t5fw", 3403 .fw_h = { 3404 .chip = FW_HDR_CHIP_T5, 3405 .fw_ver = htobe32(FW_VERSION(T5)), 3406 .intfver_nic = FW_INTFVER(T5, NIC), 3407 .intfver_vnic = FW_INTFVER(T5, VNIC), 3408 .intfver_ofld = FW_INTFVER(T5, OFLD), 3409 .intfver_ri = FW_INTFVER(T5, RI), 3410 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3411 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3412 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3413 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3414 }, 3415 }, { 3416 .chip = CHELSIO_T6, 3417 .kld_name = "t6fw_cfg", 3418 .fw_mod_name = "t6fw", 3419 .fw_h = { 3420 .chip = FW_HDR_CHIP_T6, 3421 .fw_ver = htobe32(FW_VERSION(T6)), 3422 .intfver_nic = FW_INTFVER(T6, NIC), 3423 .intfver_vnic = FW_INTFVER(T6, VNIC), 3424 .intfver_ofld = FW_INTFVER(T6, OFLD), 3425 .intfver_ri = FW_INTFVER(T6, RI), 3426 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3427 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3428 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3429 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3430 }, 3431 } 3432 }; 3433 3434 static struct fw_info * 3435 find_fw_info(int chip) 3436 { 3437 int i; 3438 3439 for (i = 0; i < nitems(fw_info); i++) { 3440 if (fw_info[i].chip == chip) 3441 return (&fw_info[i]); 3442 } 3443 return (NULL); 3444 } 3445 3446 /* 3447 * Is the given firmware API compatible with the one the driver was compiled 3448 * with? 3449 */ 3450 static int 3451 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 3452 { 3453 3454 /* short circuit if it's the exact same firmware version */ 3455 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3456 return (1); 3457 3458 /* 3459 * XXX: Is this too conservative? Perhaps I should limit this to the 3460 * features that are supported in the driver. 3461 */ 3462 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3463 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3464 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3465 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3466 return (1); 3467 #undef SAME_INTF 3468 3469 return (0); 3470 } 3471 3472 static int 3473 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 3474 const struct firmware **fw) 3475 { 3476 struct fw_info *fw_info; 3477 3478 *dcfg = NULL; 3479 if (fw != NULL) 3480 *fw = NULL; 3481 3482 fw_info = find_fw_info(chip_id(sc)); 3483 if (fw_info == NULL) { 3484 device_printf(sc->dev, 3485 "unable to look up firmware information for chip %d.\n", 3486 chip_id(sc)); 3487 return (EINVAL); 3488 } 3489 3490 *dcfg = firmware_get(fw_info->kld_name); 3491 if (*dcfg != NULL) { 3492 if (fw != NULL) 3493 *fw = firmware_get(fw_info->fw_mod_name); 3494 return (0); 3495 } 3496 3497 return (ENOENT); 3498 } 3499 3500 static void 3501 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 3502 const struct firmware *fw) 3503 { 3504 3505 if (fw != NULL) 3506 firmware_put(fw, FIRMWARE_UNLOAD); 3507 if (dcfg != NULL) 3508 firmware_put(dcfg, FIRMWARE_UNLOAD); 3509 } 3510 3511 /* 3512 * Return values: 3513 * 0 means no firmware install attempted. 3514 * ERESTART means a firmware install was attempted and was successful. 3515 * +ve errno means a firmware install was attempted but failed. 3516 */ 3517 static int 3518 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 3519 const struct fw_h *drv_fw, const char *reason, int *already) 3520 { 3521 const struct firmware *cfg, *fw; 3522 const uint32_t c = be32toh(card_fw->fw_ver); 3523 uint32_t d, k; 3524 int rc, fw_install; 3525 struct fw_h bundled_fw; 3526 bool load_attempted; 3527 3528 cfg = fw = NULL; 3529 load_attempted = false; 3530 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 3531 3532 if (reason != NULL) 3533 goto install; 3534 3535 if ((sc->flags & FW_OK) == 0) { 3536 3537 if (c == 0xffffffff) { 3538 reason = "missing"; 3539 goto install; 3540 } 3541 3542 return (0); 3543 } 3544 3545 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 3546 if (t4_fw_install < 0) { 3547 rc = load_fw_module(sc, &cfg, &fw); 3548 if (rc != 0 || fw == NULL) { 3549 device_printf(sc->dev, 3550 "failed to load firmware module: %d. cfg %p, fw %p;" 3551 " will use compiled-in firmware version for" 3552 "hw.cxgbe.fw_install checks.\n", 3553 rc, cfg, fw); 3554 } else { 3555 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 3556 } 3557 load_attempted = true; 3558 } 3559 d = be32toh(bundled_fw.fw_ver); 3560 3561 if (!fw_compatible(card_fw, &bundled_fw)) { 3562 reason = "incompatible or unusable"; 3563 goto install; 3564 } 3565 3566 if (d > c) { 3567 reason = "older than the version bundled with this driver"; 3568 goto install; 3569 } 3570 3571 if (fw_install == 2 && d != c) { 3572 reason = "different than the version bundled with this driver"; 3573 goto install; 3574 } 3575 3576 /* No reason to do anything to the firmware already on the card. */ 3577 rc = 0; 3578 goto done; 3579 3580 install: 3581 rc = 0; 3582 if ((*already)++) 3583 goto done; 3584 3585 if (fw_install == 0) { 3586 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3587 "but the driver is prohibited from installing a firmware " 3588 "on the card.\n", 3589 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3590 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3591 3592 goto done; 3593 } 3594 3595 /* 3596 * We'll attempt to install a firmware. Load the module first (if it 3597 * hasn't been loaded already). 3598 */ 3599 if (!load_attempted) { 3600 rc = load_fw_module(sc, &cfg, &fw); 3601 if (rc != 0 || fw == NULL) { 3602 device_printf(sc->dev, 3603 "failed to load firmware module: %d. cfg %p, fw %p\n", 3604 rc, cfg, fw); 3605 /* carry on */ 3606 } 3607 } 3608 if (fw == NULL) { 3609 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3610 "but the driver cannot take corrective action because it " 3611 "is unable to load the firmware module.\n", 3612 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3613 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3614 rc = sc->flags & FW_OK ? 0 : ENOENT; 3615 goto done; 3616 } 3617 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 3618 if (k != d) { 3619 MPASS(t4_fw_install > 0); 3620 device_printf(sc->dev, 3621 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 3622 "expecting (%u.%u.%u.%u) and will not be used.\n", 3623 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3624 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 3625 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3626 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3627 rc = sc->flags & FW_OK ? 0 : EINVAL; 3628 goto done; 3629 } 3630 3631 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3632 "installing firmware %u.%u.%u.%u on card.\n", 3633 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3634 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3635 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3636 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3637 3638 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3639 if (rc != 0) { 3640 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 3641 } else { 3642 /* Installed successfully, update the cached header too. */ 3643 rc = ERESTART; 3644 memcpy(card_fw, fw->data, sizeof(*card_fw)); 3645 } 3646 done: 3647 unload_fw_module(sc, cfg, fw); 3648 3649 return (rc); 3650 } 3651 3652 /* 3653 * Establish contact with the firmware and attempt to become the master driver. 3654 * 3655 * A firmware will be installed to the card if needed (if the driver is allowed 3656 * to do so). 3657 */ 3658 static int 3659 contact_firmware(struct adapter *sc) 3660 { 3661 int rc, already = 0; 3662 enum dev_state state; 3663 struct fw_info *fw_info; 3664 struct fw_hdr *card_fw; /* fw on the card */ 3665 const struct fw_h *drv_fw; 3666 3667 fw_info = find_fw_info(chip_id(sc)); 3668 if (fw_info == NULL) { 3669 device_printf(sc->dev, 3670 "unable to look up firmware information for chip %d.\n", 3671 chip_id(sc)); 3672 return (EINVAL); 3673 } 3674 drv_fw = &fw_info->fw_h; 3675 3676 /* Read the header of the firmware on the card */ 3677 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3678 restart: 3679 rc = -t4_get_fw_hdr(sc, card_fw); 3680 if (rc != 0) { 3681 device_printf(sc->dev, 3682 "unable to read firmware header from card's flash: %d\n", 3683 rc); 3684 goto done; 3685 } 3686 3687 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 3688 &already); 3689 if (rc == ERESTART) 3690 goto restart; 3691 if (rc != 0) 3692 goto done; 3693 3694 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3695 if (rc < 0 || state == DEV_STATE_ERR) { 3696 rc = -rc; 3697 device_printf(sc->dev, 3698 "failed to connect to the firmware: %d, %d. " 3699 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3700 #if 0 3701 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3702 "not responding properly to HELLO", &already) == ERESTART) 3703 goto restart; 3704 #endif 3705 goto done; 3706 } 3707 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 3708 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 3709 3710 if (rc == sc->pf) { 3711 sc->flags |= MASTER_PF; 3712 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3713 NULL, &already); 3714 if (rc == ERESTART) 3715 rc = 0; 3716 else if (rc != 0) 3717 goto done; 3718 } else if (state == DEV_STATE_UNINIT) { 3719 /* 3720 * We didn't get to be the master so we definitely won't be 3721 * configuring the chip. It's a bug if someone else hasn't 3722 * configured it already. 3723 */ 3724 device_printf(sc->dev, "couldn't be master(%d), " 3725 "device not already initialized either(%d). " 3726 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3727 rc = EPROTO; 3728 goto done; 3729 } else { 3730 /* 3731 * Some other PF is the master and has configured the chip. 3732 * This is allowed but untested. 3733 */ 3734 device_printf(sc->dev, "PF%d is master, device state %d. " 3735 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3736 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 3737 sc->cfcsum = 0; 3738 rc = 0; 3739 } 3740 done: 3741 if (rc != 0 && sc->flags & FW_OK) { 3742 t4_fw_bye(sc, sc->mbox); 3743 sc->flags &= ~FW_OK; 3744 } 3745 free(card_fw, M_CXGBE); 3746 return (rc); 3747 } 3748 3749 static int 3750 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 3751 uint32_t mtype, uint32_t moff) 3752 { 3753 struct fw_info *fw_info; 3754 const struct firmware *dcfg, *rcfg = NULL; 3755 const uint32_t *cfdata; 3756 uint32_t cflen, addr; 3757 int rc; 3758 3759 load_fw_module(sc, &dcfg, NULL); 3760 3761 /* Card specific interpretation of "default". */ 3762 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3763 if (pci_get_device(sc->dev) == 0x440a) 3764 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 3765 if (is_fpga(sc)) 3766 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 3767 } 3768 3769 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3770 if (dcfg == NULL) { 3771 device_printf(sc->dev, 3772 "KLD with default config is not available.\n"); 3773 rc = ENOENT; 3774 goto done; 3775 } 3776 cfdata = dcfg->data; 3777 cflen = dcfg->datasize & ~3; 3778 } else { 3779 char s[32]; 3780 3781 fw_info = find_fw_info(chip_id(sc)); 3782 if (fw_info == NULL) { 3783 device_printf(sc->dev, 3784 "unable to look up firmware information for chip %d.\n", 3785 chip_id(sc)); 3786 rc = EINVAL; 3787 goto done; 3788 } 3789 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 3790 3791 rcfg = firmware_get(s); 3792 if (rcfg == NULL) { 3793 device_printf(sc->dev, 3794 "unable to load module \"%s\" for configuration " 3795 "profile \"%s\".\n", s, cfg_file); 3796 rc = ENOENT; 3797 goto done; 3798 } 3799 cfdata = rcfg->data; 3800 cflen = rcfg->datasize & ~3; 3801 } 3802 3803 if (cflen > FLASH_CFG_MAX_SIZE) { 3804 device_printf(sc->dev, 3805 "config file too long (%d, max allowed is %d).\n", 3806 cflen, FLASH_CFG_MAX_SIZE); 3807 rc = EINVAL; 3808 goto done; 3809 } 3810 3811 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3812 if (rc != 0) { 3813 device_printf(sc->dev, 3814 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 3815 __func__, mtype, moff, cflen, rc); 3816 rc = EINVAL; 3817 goto done; 3818 } 3819 write_via_memwin(sc, 2, addr, cfdata, cflen); 3820 done: 3821 if (rcfg != NULL) 3822 firmware_put(rcfg, FIRMWARE_UNLOAD); 3823 unload_fw_module(sc, dcfg, NULL); 3824 return (rc); 3825 } 3826 3827 struct caps_allowed { 3828 uint16_t nbmcaps; 3829 uint16_t linkcaps; 3830 uint16_t switchcaps; 3831 uint16_t niccaps; 3832 uint16_t toecaps; 3833 uint16_t rdmacaps; 3834 uint16_t cryptocaps; 3835 uint16_t iscsicaps; 3836 uint16_t fcoecaps; 3837 }; 3838 3839 #define FW_PARAM_DEV(param) \ 3840 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3841 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3842 #define FW_PARAM_PFVF(param) \ 3843 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3844 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3845 3846 /* 3847 * Provide a configuration profile to the firmware and have it initialize the 3848 * chip accordingly. This may involve uploading a configuration file to the 3849 * card. 3850 */ 3851 static int 3852 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 3853 const struct caps_allowed *caps_allowed) 3854 { 3855 int rc; 3856 struct fw_caps_config_cmd caps; 3857 uint32_t mtype, moff, finicsum, cfcsum, param, val; 3858 3859 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3860 if (rc != 0) { 3861 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3862 return (rc); 3863 } 3864 3865 bzero(&caps, sizeof(caps)); 3866 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3867 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3868 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 3869 mtype = 0; 3870 moff = 0; 3871 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3872 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 3873 mtype = FW_MEMTYPE_FLASH; 3874 moff = t4_flash_cfg_addr(sc); 3875 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3876 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3877 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3878 FW_LEN16(caps)); 3879 } else { 3880 /* 3881 * Ask the firmware where it wants us to upload the config file. 3882 */ 3883 param = FW_PARAM_DEV(CF); 3884 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3885 if (rc != 0) { 3886 /* No support for config file? Shouldn't happen. */ 3887 device_printf(sc->dev, 3888 "failed to query config file location: %d.\n", rc); 3889 goto done; 3890 } 3891 mtype = G_FW_PARAMS_PARAM_Y(val); 3892 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3893 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3894 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3895 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3896 FW_LEN16(caps)); 3897 3898 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 3899 if (rc != 0) { 3900 device_printf(sc->dev, 3901 "failed to upload config file to card: %d.\n", rc); 3902 goto done; 3903 } 3904 } 3905 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3906 if (rc != 0) { 3907 device_printf(sc->dev, "failed to pre-process config file: %d " 3908 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3909 goto done; 3910 } 3911 3912 finicsum = be32toh(caps.finicsum); 3913 cfcsum = be32toh(caps.cfcsum); /* actual */ 3914 if (finicsum != cfcsum) { 3915 device_printf(sc->dev, 3916 "WARNING: config file checksum mismatch: %08x %08x\n", 3917 finicsum, cfcsum); 3918 } 3919 sc->cfcsum = cfcsum; 3920 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 3921 3922 /* 3923 * Let the firmware know what features will (not) be used so it can tune 3924 * things accordingly. 3925 */ 3926 #define LIMIT_CAPS(x) do { \ 3927 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 3928 } while (0) 3929 LIMIT_CAPS(nbm); 3930 LIMIT_CAPS(link); 3931 LIMIT_CAPS(switch); 3932 LIMIT_CAPS(nic); 3933 LIMIT_CAPS(toe); 3934 LIMIT_CAPS(rdma); 3935 LIMIT_CAPS(crypto); 3936 LIMIT_CAPS(iscsi); 3937 LIMIT_CAPS(fcoe); 3938 #undef LIMIT_CAPS 3939 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3940 /* 3941 * TOE and hashfilters are mutually exclusive. It is a config 3942 * file or firmware bug if both are reported as available. Try 3943 * to cope with the situation in non-debug builds by disabling 3944 * TOE. 3945 */ 3946 MPASS(caps.toecaps == 0); 3947 3948 caps.toecaps = 0; 3949 caps.rdmacaps = 0; 3950 caps.iscsicaps = 0; 3951 } 3952 3953 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3954 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3955 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3956 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3957 if (rc != 0) { 3958 device_printf(sc->dev, 3959 "failed to process config file: %d.\n", rc); 3960 goto done; 3961 } 3962 3963 t4_tweak_chip_settings(sc); 3964 set_params__pre_init(sc); 3965 3966 /* get basic stuff going */ 3967 rc = -t4_fw_initialize(sc, sc->mbox); 3968 if (rc != 0) { 3969 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 3970 goto done; 3971 } 3972 done: 3973 return (rc); 3974 } 3975 3976 /* 3977 * Partition chip resources for use between various PFs, VFs, etc. 3978 */ 3979 static int 3980 partition_resources(struct adapter *sc) 3981 { 3982 char cfg_file[sizeof(t4_cfg_file)]; 3983 struct caps_allowed caps_allowed; 3984 int rc; 3985 bool fallback; 3986 3987 /* Only the master driver gets to configure the chip resources. */ 3988 MPASS(sc->flags & MASTER_PF); 3989 3990 #define COPY_CAPS(x) do { \ 3991 caps_allowed.x##caps = t4_##x##caps_allowed; \ 3992 } while (0) 3993 bzero(&caps_allowed, sizeof(caps_allowed)); 3994 COPY_CAPS(nbm); 3995 COPY_CAPS(link); 3996 COPY_CAPS(switch); 3997 COPY_CAPS(nic); 3998 COPY_CAPS(toe); 3999 COPY_CAPS(rdma); 4000 COPY_CAPS(crypto); 4001 COPY_CAPS(iscsi); 4002 COPY_CAPS(fcoe); 4003 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 4004 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 4005 retry: 4006 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 4007 if (rc != 0 && fallback) { 4008 device_printf(sc->dev, 4009 "failed (%d) to configure card with \"%s\" profile, " 4010 "will fall back to a basic configuration and retry.\n", 4011 rc, cfg_file); 4012 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 4013 bzero(&caps_allowed, sizeof(caps_allowed)); 4014 COPY_CAPS(nbm); 4015 COPY_CAPS(link); 4016 COPY_CAPS(switch); 4017 COPY_CAPS(nic); 4018 fallback = false; 4019 goto retry; 4020 } 4021 #undef COPY_CAPS 4022 return (rc); 4023 } 4024 4025 /* 4026 * Retrieve parameters that are needed (or nice to have) very early. 4027 */ 4028 static int 4029 get_params__pre_init(struct adapter *sc) 4030 { 4031 int rc; 4032 uint32_t param[2], val[2]; 4033 4034 t4_get_version_info(sc); 4035 4036 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 4037 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 4038 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 4039 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 4040 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 4041 4042 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 4043 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 4044 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 4045 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 4046 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 4047 4048 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 4049 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 4050 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 4051 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 4052 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 4053 4054 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 4055 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 4056 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 4057 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 4058 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 4059 4060 param[0] = FW_PARAM_DEV(PORTVEC); 4061 param[1] = FW_PARAM_DEV(CCLK); 4062 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4063 if (rc != 0) { 4064 device_printf(sc->dev, 4065 "failed to query parameters (pre_init): %d.\n", rc); 4066 return (rc); 4067 } 4068 4069 sc->params.portvec = val[0]; 4070 sc->params.nports = bitcount32(val[0]); 4071 sc->params.vpd.cclk = val[1]; 4072 4073 /* Read device log parameters. */ 4074 rc = -t4_init_devlog_params(sc, 1); 4075 if (rc == 0) 4076 fixup_devlog_params(sc); 4077 else { 4078 device_printf(sc->dev, 4079 "failed to get devlog parameters: %d.\n", rc); 4080 rc = 0; /* devlog isn't critical for device operation */ 4081 } 4082 4083 return (rc); 4084 } 4085 4086 /* 4087 * Any params that need to be set before FW_INITIALIZE. 4088 */ 4089 static int 4090 set_params__pre_init(struct adapter *sc) 4091 { 4092 int rc = 0; 4093 uint32_t param, val; 4094 4095 if (chip_id(sc) >= CHELSIO_T6) { 4096 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 4097 val = 1; 4098 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4099 /* firmwares < 1.20.1.0 do not have this param. */ 4100 if (rc == FW_EINVAL && sc->params.fw_vers < 4101 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4102 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) { 4103 rc = 0; 4104 } 4105 if (rc != 0) { 4106 device_printf(sc->dev, 4107 "failed to enable high priority filters :%d.\n", 4108 rc); 4109 } 4110 } 4111 4112 /* Enable opaque VIIDs with firmwares that support it. */ 4113 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 4114 val = 1; 4115 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4116 if (rc == 0 && val == 1) 4117 sc->params.viid_smt_extn_support = true; 4118 else 4119 sc->params.viid_smt_extn_support = false; 4120 4121 return (rc); 4122 } 4123 4124 /* 4125 * Retrieve various parameters that are of interest to the driver. The device 4126 * has been initialized by the firmware at this point. 4127 */ 4128 static int 4129 get_params__post_init(struct adapter *sc) 4130 { 4131 int rc; 4132 uint32_t param[7], val[7]; 4133 struct fw_caps_config_cmd caps; 4134 4135 param[0] = FW_PARAM_PFVF(IQFLINT_START); 4136 param[1] = FW_PARAM_PFVF(EQ_START); 4137 param[2] = FW_PARAM_PFVF(FILTER_START); 4138 param[3] = FW_PARAM_PFVF(FILTER_END); 4139 param[4] = FW_PARAM_PFVF(L2T_START); 4140 param[5] = FW_PARAM_PFVF(L2T_END); 4141 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 4142 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 4143 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 4144 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 4145 if (rc != 0) { 4146 device_printf(sc->dev, 4147 "failed to query parameters (post_init): %d.\n", rc); 4148 return (rc); 4149 } 4150 4151 sc->sge.iq_start = val[0]; 4152 sc->sge.eq_start = val[1]; 4153 if ((int)val[3] > (int)val[2]) { 4154 sc->tids.ftid_base = val[2]; 4155 sc->tids.ftid_end = val[3]; 4156 sc->tids.nftids = val[3] - val[2] + 1; 4157 } 4158 sc->vres.l2t.start = val[4]; 4159 sc->vres.l2t.size = val[5] - val[4] + 1; 4160 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 4161 ("%s: L2 table size (%u) larger than expected (%u)", 4162 __func__, sc->vres.l2t.size, L2T_SIZE)); 4163 sc->params.core_vdd = val[6]; 4164 4165 if (chip_id(sc) >= CHELSIO_T6) { 4166 4167 sc->tids.tid_base = t4_read_reg(sc, 4168 A_LE_DB_ACTIVE_TABLE_START_INDEX); 4169 4170 param[0] = FW_PARAM_PFVF(HPFILTER_START); 4171 param[1] = FW_PARAM_PFVF(HPFILTER_END); 4172 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4173 if (rc != 0) { 4174 device_printf(sc->dev, 4175 "failed to query hpfilter parameters: %d.\n", rc); 4176 return (rc); 4177 } 4178 if ((int)val[1] > (int)val[0]) { 4179 sc->tids.hpftid_base = val[0]; 4180 sc->tids.hpftid_end = val[1]; 4181 sc->tids.nhpftids = val[1] - val[0] + 1; 4182 4183 /* 4184 * These should go off if the layout changes and the 4185 * driver needs to catch up. 4186 */ 4187 MPASS(sc->tids.hpftid_base == 0); 4188 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 4189 } 4190 } 4191 4192 /* 4193 * MPSBGMAP is queried separately because only recent firmwares support 4194 * it as a parameter and we don't want the compound query above to fail 4195 * on older firmwares. 4196 */ 4197 param[0] = FW_PARAM_DEV(MPSBGMAP); 4198 val[0] = 0; 4199 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4200 if (rc == 0) 4201 sc->params.mps_bg_map = val[0]; 4202 else 4203 sc->params.mps_bg_map = 0; 4204 4205 /* 4206 * Determine whether the firmware supports the filter2 work request. 4207 * This is queried separately for the same reason as MPSBGMAP above. 4208 */ 4209 param[0] = FW_PARAM_DEV(FILTER2_WR); 4210 val[0] = 0; 4211 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4212 if (rc == 0) 4213 sc->params.filter2_wr_support = val[0] != 0; 4214 else 4215 sc->params.filter2_wr_support = 0; 4216 4217 /* 4218 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 4219 * This is queried separately for the same reason as other params above. 4220 */ 4221 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4222 val[0] = 0; 4223 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4224 if (rc == 0) 4225 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 4226 else 4227 sc->params.ulptx_memwrite_dsgl = false; 4228 4229 /* get capabilites */ 4230 bzero(&caps, sizeof(caps)); 4231 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4232 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4233 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4234 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4235 if (rc != 0) { 4236 device_printf(sc->dev, 4237 "failed to get card capabilities: %d.\n", rc); 4238 return (rc); 4239 } 4240 4241 #define READ_CAPS(x) do { \ 4242 sc->x = htobe16(caps.x); \ 4243 } while (0) 4244 READ_CAPS(nbmcaps); 4245 READ_CAPS(linkcaps); 4246 READ_CAPS(switchcaps); 4247 READ_CAPS(niccaps); 4248 READ_CAPS(toecaps); 4249 READ_CAPS(rdmacaps); 4250 READ_CAPS(cryptocaps); 4251 READ_CAPS(iscsicaps); 4252 READ_CAPS(fcoecaps); 4253 4254 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 4255 MPASS(chip_id(sc) > CHELSIO_T4); 4256 MPASS(sc->toecaps == 0); 4257 sc->toecaps = 0; 4258 4259 param[0] = FW_PARAM_DEV(NTID); 4260 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4261 if (rc != 0) { 4262 device_printf(sc->dev, 4263 "failed to query HASHFILTER parameters: %d.\n", rc); 4264 return (rc); 4265 } 4266 sc->tids.ntids = val[0]; 4267 if (sc->params.fw_vers < 4268 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4269 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4270 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4271 sc->tids.ntids -= sc->tids.nhpftids; 4272 } 4273 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4274 sc->params.hash_filter = 1; 4275 } 4276 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 4277 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 4278 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 4279 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4280 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 4281 if (rc != 0) { 4282 device_printf(sc->dev, 4283 "failed to query NIC parameters: %d.\n", rc); 4284 return (rc); 4285 } 4286 if ((int)val[1] > (int)val[0]) { 4287 sc->tids.etid_base = val[0]; 4288 sc->tids.etid_end = val[1]; 4289 sc->tids.netids = val[1] - val[0] + 1; 4290 sc->params.eo_wr_cred = val[2]; 4291 sc->params.ethoffload = 1; 4292 } 4293 } 4294 if (sc->toecaps) { 4295 /* query offload-related parameters */ 4296 param[0] = FW_PARAM_DEV(NTID); 4297 param[1] = FW_PARAM_PFVF(SERVER_START); 4298 param[2] = FW_PARAM_PFVF(SERVER_END); 4299 param[3] = FW_PARAM_PFVF(TDDP_START); 4300 param[4] = FW_PARAM_PFVF(TDDP_END); 4301 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4302 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4303 if (rc != 0) { 4304 device_printf(sc->dev, 4305 "failed to query TOE parameters: %d.\n", rc); 4306 return (rc); 4307 } 4308 sc->tids.ntids = val[0]; 4309 if (sc->params.fw_vers < 4310 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4311 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4312 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4313 sc->tids.ntids -= sc->tids.nhpftids; 4314 } 4315 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4316 if ((int)val[2] > (int)val[1]) { 4317 sc->tids.stid_base = val[1]; 4318 sc->tids.nstids = val[2] - val[1] + 1; 4319 } 4320 sc->vres.ddp.start = val[3]; 4321 sc->vres.ddp.size = val[4] - val[3] + 1; 4322 sc->params.ofldq_wr_cred = val[5]; 4323 sc->params.offload = 1; 4324 } else { 4325 /* 4326 * The firmware attempts memfree TOE configuration for -SO cards 4327 * and will report toecaps=0 if it runs out of resources (this 4328 * depends on the config file). It may not report 0 for other 4329 * capabilities dependent on the TOE in this case. Set them to 4330 * 0 here so that the driver doesn't bother tracking resources 4331 * that will never be used. 4332 */ 4333 sc->iscsicaps = 0; 4334 sc->rdmacaps = 0; 4335 } 4336 if (sc->rdmacaps) { 4337 param[0] = FW_PARAM_PFVF(STAG_START); 4338 param[1] = FW_PARAM_PFVF(STAG_END); 4339 param[2] = FW_PARAM_PFVF(RQ_START); 4340 param[3] = FW_PARAM_PFVF(RQ_END); 4341 param[4] = FW_PARAM_PFVF(PBL_START); 4342 param[5] = FW_PARAM_PFVF(PBL_END); 4343 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4344 if (rc != 0) { 4345 device_printf(sc->dev, 4346 "failed to query RDMA parameters(1): %d.\n", rc); 4347 return (rc); 4348 } 4349 sc->vres.stag.start = val[0]; 4350 sc->vres.stag.size = val[1] - val[0] + 1; 4351 sc->vres.rq.start = val[2]; 4352 sc->vres.rq.size = val[3] - val[2] + 1; 4353 sc->vres.pbl.start = val[4]; 4354 sc->vres.pbl.size = val[5] - val[4] + 1; 4355 4356 param[0] = FW_PARAM_PFVF(SQRQ_START); 4357 param[1] = FW_PARAM_PFVF(SQRQ_END); 4358 param[2] = FW_PARAM_PFVF(CQ_START); 4359 param[3] = FW_PARAM_PFVF(CQ_END); 4360 param[4] = FW_PARAM_PFVF(OCQ_START); 4361 param[5] = FW_PARAM_PFVF(OCQ_END); 4362 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4363 if (rc != 0) { 4364 device_printf(sc->dev, 4365 "failed to query RDMA parameters(2): %d.\n", rc); 4366 return (rc); 4367 } 4368 sc->vres.qp.start = val[0]; 4369 sc->vres.qp.size = val[1] - val[0] + 1; 4370 sc->vres.cq.start = val[2]; 4371 sc->vres.cq.size = val[3] - val[2] + 1; 4372 sc->vres.ocq.start = val[4]; 4373 sc->vres.ocq.size = val[5] - val[4] + 1; 4374 4375 param[0] = FW_PARAM_PFVF(SRQ_START); 4376 param[1] = FW_PARAM_PFVF(SRQ_END); 4377 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4378 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4379 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4380 if (rc != 0) { 4381 device_printf(sc->dev, 4382 "failed to query RDMA parameters(3): %d.\n", rc); 4383 return (rc); 4384 } 4385 sc->vres.srq.start = val[0]; 4386 sc->vres.srq.size = val[1] - val[0] + 1; 4387 sc->params.max_ordird_qp = val[2]; 4388 sc->params.max_ird_adapter = val[3]; 4389 } 4390 if (sc->iscsicaps) { 4391 param[0] = FW_PARAM_PFVF(ISCSI_START); 4392 param[1] = FW_PARAM_PFVF(ISCSI_END); 4393 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4394 if (rc != 0) { 4395 device_printf(sc->dev, 4396 "failed to query iSCSI parameters: %d.\n", rc); 4397 return (rc); 4398 } 4399 sc->vres.iscsi.start = val[0]; 4400 sc->vres.iscsi.size = val[1] - val[0] + 1; 4401 } 4402 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4403 param[0] = FW_PARAM_PFVF(TLS_START); 4404 param[1] = FW_PARAM_PFVF(TLS_END); 4405 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4406 if (rc != 0) { 4407 device_printf(sc->dev, 4408 "failed to query TLS parameters: %d.\n", rc); 4409 return (rc); 4410 } 4411 sc->vres.key.start = val[0]; 4412 sc->vres.key.size = val[1] - val[0] + 1; 4413 } 4414 4415 t4_init_sge_params(sc); 4416 4417 /* 4418 * We've got the params we wanted to query via the firmware. Now grab 4419 * some others directly from the chip. 4420 */ 4421 rc = t4_read_chip_settings(sc); 4422 4423 return (rc); 4424 } 4425 4426 static int 4427 set_params__post_init(struct adapter *sc) 4428 { 4429 uint32_t param, val; 4430 #ifdef TCP_OFFLOAD 4431 int i, v, shift; 4432 #endif 4433 4434 /* ask for encapsulated CPLs */ 4435 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4436 val = 1; 4437 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4438 4439 /* Enable 32b port caps if the firmware supports it. */ 4440 param = FW_PARAM_PFVF(PORT_CAPS32); 4441 val = 1; 4442 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 4443 sc->params.port_caps32 = 1; 4444 4445 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 4446 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 4447 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 4448 V_MASKFILTER(val - 1)); 4449 4450 #ifdef TCP_OFFLOAD 4451 /* 4452 * Override the TOE timers with user provided tunables. This is not the 4453 * recommended way to change the timers (the firmware config file is) so 4454 * these tunables are not documented. 4455 * 4456 * All the timer tunables are in microseconds. 4457 */ 4458 if (t4_toe_keepalive_idle != 0) { 4459 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4460 v &= M_KEEPALIVEIDLE; 4461 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4462 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4463 } 4464 if (t4_toe_keepalive_interval != 0) { 4465 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4466 v &= M_KEEPALIVEINTVL; 4467 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4468 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4469 } 4470 if (t4_toe_keepalive_count != 0) { 4471 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4472 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4473 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4474 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4475 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4476 } 4477 if (t4_toe_rexmt_min != 0) { 4478 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4479 v &= M_RXTMIN; 4480 t4_set_reg_field(sc, A_TP_RXT_MIN, 4481 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4482 } 4483 if (t4_toe_rexmt_max != 0) { 4484 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4485 v &= M_RXTMAX; 4486 t4_set_reg_field(sc, A_TP_RXT_MAX, 4487 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4488 } 4489 if (t4_toe_rexmt_count != 0) { 4490 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4491 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4492 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4493 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4494 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4495 } 4496 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4497 if (t4_toe_rexmt_backoff[i] != -1) { 4498 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4499 shift = (i & 3) << 3; 4500 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4501 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4502 } 4503 } 4504 #endif 4505 return (0); 4506 } 4507 4508 #undef FW_PARAM_PFVF 4509 #undef FW_PARAM_DEV 4510 4511 static void 4512 t4_set_desc(struct adapter *sc) 4513 { 4514 char buf[128]; 4515 struct adapter_params *p = &sc->params; 4516 4517 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4518 4519 device_set_desc_copy(sc->dev, buf); 4520 } 4521 4522 static inline void 4523 ifmedia_add4(struct ifmedia *ifm, int m) 4524 { 4525 4526 ifmedia_add(ifm, m, 0, NULL); 4527 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4528 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4529 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4530 } 4531 4532 /* 4533 * This is the selected media, which is not quite the same as the active media. 4534 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 4535 * and active are not the same, and "media: Ethernet selected" otherwise. 4536 */ 4537 static void 4538 set_current_media(struct port_info *pi) 4539 { 4540 struct link_config *lc; 4541 struct ifmedia *ifm; 4542 int mword; 4543 u_int speed; 4544 4545 PORT_LOCK_ASSERT_OWNED(pi); 4546 4547 /* Leave current media alone if it's already set to IFM_NONE. */ 4548 ifm = &pi->media; 4549 if (ifm->ifm_cur != NULL && 4550 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4551 return; 4552 4553 lc = &pi->link_cfg; 4554 if (lc->requested_aneg != AUTONEG_DISABLE && 4555 lc->supported & FW_PORT_CAP32_ANEG) { 4556 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4557 return; 4558 } 4559 mword = IFM_ETHER | IFM_FDX; 4560 if (lc->requested_fc & PAUSE_TX) 4561 mword |= IFM_ETH_TXPAUSE; 4562 if (lc->requested_fc & PAUSE_RX) 4563 mword |= IFM_ETH_RXPAUSE; 4564 if (lc->requested_speed == 0) 4565 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 4566 else 4567 speed = lc->requested_speed; 4568 mword |= port_mword(pi, speed_to_fwcap(speed)); 4569 ifmedia_set(ifm, mword); 4570 } 4571 4572 /* 4573 * Returns true if the ifmedia list for the port cannot change. 4574 */ 4575 static bool 4576 fixed_ifmedia(struct port_info *pi) 4577 { 4578 4579 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 4580 pi->port_type == FW_PORT_TYPE_BT_XFI || 4581 pi->port_type == FW_PORT_TYPE_BT_XAUI || 4582 pi->port_type == FW_PORT_TYPE_KX4 || 4583 pi->port_type == FW_PORT_TYPE_KX || 4584 pi->port_type == FW_PORT_TYPE_KR || 4585 pi->port_type == FW_PORT_TYPE_BP_AP || 4586 pi->port_type == FW_PORT_TYPE_BP4_AP || 4587 pi->port_type == FW_PORT_TYPE_BP40_BA || 4588 pi->port_type == FW_PORT_TYPE_KR4_100G || 4589 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 4590 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 4591 } 4592 4593 static void 4594 build_medialist(struct port_info *pi) 4595 { 4596 uint32_t ss, speed; 4597 int unknown, mword, bit; 4598 struct link_config *lc; 4599 struct ifmedia *ifm; 4600 4601 PORT_LOCK_ASSERT_OWNED(pi); 4602 4603 if (pi->flags & FIXED_IFMEDIA) 4604 return; 4605 4606 /* 4607 * Rebuild the ifmedia list. 4608 */ 4609 ifm = &pi->media; 4610 ifmedia_removeall(ifm); 4611 lc = &pi->link_cfg; 4612 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */ 4613 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 4614 MPASS(ss != 0); 4615 no_media: 4616 MPASS(LIST_EMPTY(&ifm->ifm_list)); 4617 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 4618 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 4619 return; 4620 } 4621 4622 unknown = 0; 4623 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 4624 speed = 1 << bit; 4625 MPASS(speed & M_FW_PORT_CAP32_SPEED); 4626 if (ss & speed) { 4627 mword = port_mword(pi, speed); 4628 if (mword == IFM_NONE) { 4629 goto no_media; 4630 } else if (mword == IFM_UNKNOWN) 4631 unknown++; 4632 else 4633 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 4634 } 4635 } 4636 if (unknown > 0) /* Add one unknown for all unknown media types. */ 4637 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 4638 if (lc->supported & FW_PORT_CAP32_ANEG) 4639 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 4640 4641 set_current_media(pi); 4642 } 4643 4644 /* 4645 * Initialize the requested fields in the link config based on driver tunables. 4646 */ 4647 static void 4648 init_link_config(struct port_info *pi) 4649 { 4650 struct link_config *lc = &pi->link_cfg; 4651 4652 PORT_LOCK_ASSERT_OWNED(pi); 4653 4654 lc->requested_speed = 0; 4655 4656 if (t4_autoneg == 0) 4657 lc->requested_aneg = AUTONEG_DISABLE; 4658 else if (t4_autoneg == 1) 4659 lc->requested_aneg = AUTONEG_ENABLE; 4660 else 4661 lc->requested_aneg = AUTONEG_AUTO; 4662 4663 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 4664 PAUSE_AUTONEG); 4665 4666 if (t4_fec == -1 || t4_fec & FEC_AUTO) 4667 lc->requested_fec = FEC_AUTO; 4668 else { 4669 lc->requested_fec = FEC_NONE; 4670 if (t4_fec & FEC_RS) 4671 lc->requested_fec |= FEC_RS; 4672 if (t4_fec & FEC_BASER_RS) 4673 lc->requested_fec |= FEC_BASER_RS; 4674 } 4675 } 4676 4677 /* 4678 * Makes sure that all requested settings comply with what's supported by the 4679 * port. Returns the number of settings that were invalid and had to be fixed. 4680 */ 4681 static int 4682 fixup_link_config(struct port_info *pi) 4683 { 4684 int n = 0; 4685 struct link_config *lc = &pi->link_cfg; 4686 uint32_t fwspeed; 4687 4688 PORT_LOCK_ASSERT_OWNED(pi); 4689 4690 /* Speed (when not autonegotiating) */ 4691 if (lc->requested_speed != 0) { 4692 fwspeed = speed_to_fwcap(lc->requested_speed); 4693 if ((fwspeed & lc->supported) == 0) { 4694 n++; 4695 lc->requested_speed = 0; 4696 } 4697 } 4698 4699 /* Link autonegotiation */ 4700 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 4701 lc->requested_aneg == AUTONEG_DISABLE || 4702 lc->requested_aneg == AUTONEG_AUTO); 4703 if (lc->requested_aneg == AUTONEG_ENABLE && 4704 !(lc->supported & FW_PORT_CAP32_ANEG)) { 4705 n++; 4706 lc->requested_aneg = AUTONEG_AUTO; 4707 } 4708 4709 /* Flow control */ 4710 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 4711 if (lc->requested_fc & PAUSE_TX && 4712 !(lc->supported & FW_PORT_CAP32_FC_TX)) { 4713 n++; 4714 lc->requested_fc &= ~PAUSE_TX; 4715 } 4716 if (lc->requested_fc & PAUSE_RX && 4717 !(lc->supported & FW_PORT_CAP32_FC_RX)) { 4718 n++; 4719 lc->requested_fc &= ~PAUSE_RX; 4720 } 4721 if (!(lc->requested_fc & PAUSE_AUTONEG) && 4722 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) { 4723 n++; 4724 lc->requested_fc |= PAUSE_AUTONEG; 4725 } 4726 4727 /* FEC */ 4728 if ((lc->requested_fec & FEC_RS && 4729 !(lc->supported & FW_PORT_CAP32_FEC_RS)) || 4730 (lc->requested_fec & FEC_BASER_RS && 4731 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) { 4732 n++; 4733 lc->requested_fec = FEC_AUTO; 4734 } 4735 4736 return (n); 4737 } 4738 4739 /* 4740 * Apply the requested L1 settings, which are expected to be valid, to the 4741 * hardware. 4742 */ 4743 static int 4744 apply_link_config(struct port_info *pi) 4745 { 4746 struct adapter *sc = pi->adapter; 4747 struct link_config *lc = &pi->link_cfg; 4748 int rc; 4749 4750 #ifdef INVARIANTS 4751 ASSERT_SYNCHRONIZED_OP(sc); 4752 PORT_LOCK_ASSERT_OWNED(pi); 4753 4754 if (lc->requested_aneg == AUTONEG_ENABLE) 4755 MPASS(lc->supported & FW_PORT_CAP32_ANEG); 4756 if (!(lc->requested_fc & PAUSE_AUTONEG)) 4757 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE); 4758 if (lc->requested_fc & PAUSE_TX) 4759 MPASS(lc->supported & FW_PORT_CAP32_FC_TX); 4760 if (lc->requested_fc & PAUSE_RX) 4761 MPASS(lc->supported & FW_PORT_CAP32_FC_RX); 4762 if (lc->requested_fec & FEC_RS) 4763 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS); 4764 if (lc->requested_fec & FEC_BASER_RS) 4765 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS); 4766 #endif 4767 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4768 if (rc != 0) { 4769 /* Don't complain if the VF driver gets back an EPERM. */ 4770 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 4771 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4772 } else { 4773 /* 4774 * An L1_CFG will almost always result in a link-change event if 4775 * the link is up, and the driver will refresh the actual 4776 * fec/fc/etc. when the notification is processed. If the link 4777 * is down then the actual settings are meaningless. 4778 * 4779 * This takes care of the case where a change in the L1 settings 4780 * may not result in a notification. 4781 */ 4782 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 4783 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 4784 } 4785 return (rc); 4786 } 4787 4788 #define FW_MAC_EXACT_CHUNK 7 4789 4790 /* 4791 * Program the port's XGMAC based on parameters in ifnet. The caller also 4792 * indicates which parameters should be programmed (the rest are left alone). 4793 */ 4794 int 4795 update_mac_settings(struct ifnet *ifp, int flags) 4796 { 4797 int rc = 0; 4798 struct vi_info *vi = ifp->if_softc; 4799 struct port_info *pi = vi->pi; 4800 struct adapter *sc = pi->adapter; 4801 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4802 4803 ASSERT_SYNCHRONIZED_OP(sc); 4804 KASSERT(flags, ("%s: not told what to update.", __func__)); 4805 4806 if (flags & XGMAC_MTU) 4807 mtu = ifp->if_mtu; 4808 4809 if (flags & XGMAC_PROMISC) 4810 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4811 4812 if (flags & XGMAC_ALLMULTI) 4813 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4814 4815 if (flags & XGMAC_VLANEX) 4816 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4817 4818 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4819 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4820 allmulti, 1, vlanex, false); 4821 if (rc) { 4822 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4823 rc); 4824 return (rc); 4825 } 4826 } 4827 4828 if (flags & XGMAC_UCADDR) { 4829 uint8_t ucaddr[ETHER_ADDR_LEN]; 4830 4831 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4832 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4833 ucaddr, true, &vi->smt_idx); 4834 if (rc < 0) { 4835 rc = -rc; 4836 if_printf(ifp, "change_mac failed: %d\n", rc); 4837 return (rc); 4838 } else { 4839 vi->xact_addr_filt = rc; 4840 rc = 0; 4841 } 4842 } 4843 4844 if (flags & XGMAC_MCADDRS) { 4845 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4846 int del = 1; 4847 uint64_t hash = 0; 4848 struct ifmultiaddr *ifma; 4849 int i = 0, j; 4850 4851 if_maddr_rlock(ifp); 4852 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4853 if (ifma->ifma_addr->sa_family != AF_LINK) 4854 continue; 4855 mcaddr[i] = 4856 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4857 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4858 i++; 4859 4860 if (i == FW_MAC_EXACT_CHUNK) { 4861 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4862 del, i, mcaddr, NULL, &hash, 0); 4863 if (rc < 0) { 4864 rc = -rc; 4865 for (j = 0; j < i; j++) { 4866 if_printf(ifp, 4867 "failed to add mc address" 4868 " %02x:%02x:%02x:" 4869 "%02x:%02x:%02x rc=%d\n", 4870 mcaddr[j][0], mcaddr[j][1], 4871 mcaddr[j][2], mcaddr[j][3], 4872 mcaddr[j][4], mcaddr[j][5], 4873 rc); 4874 } 4875 goto mcfail; 4876 } 4877 del = 0; 4878 i = 0; 4879 } 4880 } 4881 if (i > 0) { 4882 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4883 mcaddr, NULL, &hash, 0); 4884 if (rc < 0) { 4885 rc = -rc; 4886 for (j = 0; j < i; j++) { 4887 if_printf(ifp, 4888 "failed to add mc address" 4889 " %02x:%02x:%02x:" 4890 "%02x:%02x:%02x rc=%d\n", 4891 mcaddr[j][0], mcaddr[j][1], 4892 mcaddr[j][2], mcaddr[j][3], 4893 mcaddr[j][4], mcaddr[j][5], 4894 rc); 4895 } 4896 goto mcfail; 4897 } 4898 } 4899 4900 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4901 if (rc != 0) 4902 if_printf(ifp, "failed to set mc address hash: %d", rc); 4903 mcfail: 4904 if_maddr_runlock(ifp); 4905 } 4906 4907 return (rc); 4908 } 4909 4910 /* 4911 * {begin|end}_synchronized_op must be called from the same thread. 4912 */ 4913 int 4914 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4915 char *wmesg) 4916 { 4917 int rc, pri; 4918 4919 #ifdef WITNESS 4920 /* the caller thinks it's ok to sleep, but is it really? */ 4921 if (flags & SLEEP_OK) 4922 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4923 "begin_synchronized_op"); 4924 #endif 4925 4926 if (INTR_OK) 4927 pri = PCATCH; 4928 else 4929 pri = 0; 4930 4931 ADAPTER_LOCK(sc); 4932 for (;;) { 4933 4934 if (vi && IS_DOOMED(vi)) { 4935 rc = ENXIO; 4936 goto done; 4937 } 4938 4939 if (!IS_BUSY(sc)) { 4940 rc = 0; 4941 break; 4942 } 4943 4944 if (!(flags & SLEEP_OK)) { 4945 rc = EBUSY; 4946 goto done; 4947 } 4948 4949 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4950 rc = EINTR; 4951 goto done; 4952 } 4953 } 4954 4955 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4956 SET_BUSY(sc); 4957 #ifdef INVARIANTS 4958 sc->last_op = wmesg; 4959 sc->last_op_thr = curthread; 4960 sc->last_op_flags = flags; 4961 #endif 4962 4963 done: 4964 if (!(flags & HOLD_LOCK) || rc) 4965 ADAPTER_UNLOCK(sc); 4966 4967 return (rc); 4968 } 4969 4970 /* 4971 * Tell if_ioctl and if_init that the VI is going away. This is 4972 * special variant of begin_synchronized_op and must be paired with a 4973 * call to end_synchronized_op. 4974 */ 4975 void 4976 doom_vi(struct adapter *sc, struct vi_info *vi) 4977 { 4978 4979 ADAPTER_LOCK(sc); 4980 SET_DOOMED(vi); 4981 wakeup(&sc->flags); 4982 while (IS_BUSY(sc)) 4983 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4984 SET_BUSY(sc); 4985 #ifdef INVARIANTS 4986 sc->last_op = "t4detach"; 4987 sc->last_op_thr = curthread; 4988 sc->last_op_flags = 0; 4989 #endif 4990 ADAPTER_UNLOCK(sc); 4991 } 4992 4993 /* 4994 * {begin|end}_synchronized_op must be called from the same thread. 4995 */ 4996 void 4997 end_synchronized_op(struct adapter *sc, int flags) 4998 { 4999 5000 if (flags & LOCK_HELD) 5001 ADAPTER_LOCK_ASSERT_OWNED(sc); 5002 else 5003 ADAPTER_LOCK(sc); 5004 5005 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 5006 CLR_BUSY(sc); 5007 wakeup(&sc->flags); 5008 ADAPTER_UNLOCK(sc); 5009 } 5010 5011 static int 5012 cxgbe_init_synchronized(struct vi_info *vi) 5013 { 5014 struct port_info *pi = vi->pi; 5015 struct adapter *sc = pi->adapter; 5016 struct ifnet *ifp = vi->ifp; 5017 int rc = 0, i; 5018 struct sge_txq *txq; 5019 5020 ASSERT_SYNCHRONIZED_OP(sc); 5021 5022 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5023 return (0); /* already running */ 5024 5025 if (!(sc->flags & FULL_INIT_DONE) && 5026 ((rc = adapter_full_init(sc)) != 0)) 5027 return (rc); /* error message displayed already */ 5028 5029 if (!(vi->flags & VI_INIT_DONE) && 5030 ((rc = vi_full_init(vi)) != 0)) 5031 return (rc); /* error message displayed already */ 5032 5033 rc = update_mac_settings(ifp, XGMAC_ALL); 5034 if (rc) 5035 goto done; /* error message displayed already */ 5036 5037 PORT_LOCK(pi); 5038 if (pi->up_vis == 0) { 5039 t4_update_port_info(pi); 5040 fixup_link_config(pi); 5041 build_medialist(pi); 5042 apply_link_config(pi); 5043 } 5044 5045 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 5046 if (rc != 0) { 5047 if_printf(ifp, "enable_vi failed: %d\n", rc); 5048 PORT_UNLOCK(pi); 5049 goto done; 5050 } 5051 5052 /* 5053 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 5054 * if this changes. 5055 */ 5056 5057 for_each_txq(vi, i, txq) { 5058 TXQ_LOCK(txq); 5059 txq->eq.flags |= EQ_ENABLED; 5060 TXQ_UNLOCK(txq); 5061 } 5062 5063 /* 5064 * The first iq of the first port to come up is used for tracing. 5065 */ 5066 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 5067 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 5068 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 5069 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 5070 V_QUEUENUMBER(sc->traceq)); 5071 pi->flags |= HAS_TRACEQ; 5072 } 5073 5074 /* all ok */ 5075 pi->up_vis++; 5076 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5077 5078 if (pi->nvi > 1 || sc->flags & IS_VF) 5079 callout_reset(&vi->tick, hz, vi_tick, vi); 5080 else 5081 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 5082 if (pi->link_cfg.link_ok) 5083 t4_os_link_changed(pi); 5084 PORT_UNLOCK(pi); 5085 done: 5086 if (rc != 0) 5087 cxgbe_uninit_synchronized(vi); 5088 5089 return (rc); 5090 } 5091 5092 /* 5093 * Idempotent. 5094 */ 5095 static int 5096 cxgbe_uninit_synchronized(struct vi_info *vi) 5097 { 5098 struct port_info *pi = vi->pi; 5099 struct adapter *sc = pi->adapter; 5100 struct ifnet *ifp = vi->ifp; 5101 int rc, i; 5102 struct sge_txq *txq; 5103 5104 ASSERT_SYNCHRONIZED_OP(sc); 5105 5106 if (!(vi->flags & VI_INIT_DONE)) { 5107 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5108 KASSERT(0, ("uninited VI is running")); 5109 if_printf(ifp, "uninited VI with running ifnet. " 5110 "vi->flags 0x%016lx, if_flags 0x%08x, " 5111 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 5112 ifp->if_drv_flags); 5113 } 5114 return (0); 5115 } 5116 5117 /* 5118 * Disable the VI so that all its data in either direction is discarded 5119 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 5120 * tick) intact as the TP can deliver negative advice or data that it's 5121 * holding in its RAM (for an offloaded connection) even after the VI is 5122 * disabled. 5123 */ 5124 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 5125 if (rc) { 5126 if_printf(ifp, "disable_vi failed: %d\n", rc); 5127 return (rc); 5128 } 5129 5130 for_each_txq(vi, i, txq) { 5131 TXQ_LOCK(txq); 5132 txq->eq.flags &= ~EQ_ENABLED; 5133 TXQ_UNLOCK(txq); 5134 } 5135 5136 PORT_LOCK(pi); 5137 if (pi->nvi > 1 || sc->flags & IS_VF) 5138 callout_stop(&vi->tick); 5139 else 5140 callout_stop(&pi->tick); 5141 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5142 PORT_UNLOCK(pi); 5143 return (0); 5144 } 5145 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5146 pi->up_vis--; 5147 if (pi->up_vis > 0) { 5148 PORT_UNLOCK(pi); 5149 return (0); 5150 } 5151 5152 pi->link_cfg.link_ok = false; 5153 pi->link_cfg.speed = 0; 5154 pi->link_cfg.link_down_rc = 255; 5155 t4_os_link_changed(pi); 5156 PORT_UNLOCK(pi); 5157 5158 return (0); 5159 } 5160 5161 /* 5162 * It is ok for this function to fail midway and return right away. t4_detach 5163 * will walk the entire sc->irq list and clean up whatever is valid. 5164 */ 5165 int 5166 t4_setup_intr_handlers(struct adapter *sc) 5167 { 5168 int rc, rid, p, q, v; 5169 char s[8]; 5170 struct irq *irq; 5171 struct port_info *pi; 5172 struct vi_info *vi; 5173 struct sge *sge = &sc->sge; 5174 struct sge_rxq *rxq; 5175 #ifdef TCP_OFFLOAD 5176 struct sge_ofld_rxq *ofld_rxq; 5177 #endif 5178 #ifdef DEV_NETMAP 5179 struct sge_nm_rxq *nm_rxq; 5180 #endif 5181 #ifdef RSS 5182 int nbuckets = rss_getnumbuckets(); 5183 #endif 5184 5185 /* 5186 * Setup interrupts. 5187 */ 5188 irq = &sc->irq[0]; 5189 rid = sc->intr_type == INTR_INTX ? 0 : 1; 5190 if (forwarding_intr_to_fwq(sc)) 5191 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 5192 5193 /* Multiple interrupts. */ 5194 if (sc->flags & IS_VF) 5195 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 5196 ("%s: too few intr.", __func__)); 5197 else 5198 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 5199 ("%s: too few intr.", __func__)); 5200 5201 /* The first one is always error intr on PFs */ 5202 if (!(sc->flags & IS_VF)) { 5203 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 5204 if (rc != 0) 5205 return (rc); 5206 irq++; 5207 rid++; 5208 } 5209 5210 /* The second one is always the firmware event queue (first on VFs) */ 5211 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 5212 if (rc != 0) 5213 return (rc); 5214 irq++; 5215 rid++; 5216 5217 for_each_port(sc, p) { 5218 pi = sc->port[p]; 5219 for_each_vi(pi, v, vi) { 5220 vi->first_intr = rid - 1; 5221 5222 if (vi->nnmrxq > 0) { 5223 int n = max(vi->nrxq, vi->nnmrxq); 5224 5225 rxq = &sge->rxq[vi->first_rxq]; 5226 #ifdef DEV_NETMAP 5227 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 5228 #endif 5229 for (q = 0; q < n; q++) { 5230 snprintf(s, sizeof(s), "%x%c%x", p, 5231 'a' + v, q); 5232 if (q < vi->nrxq) 5233 irq->rxq = rxq++; 5234 #ifdef DEV_NETMAP 5235 if (q < vi->nnmrxq) 5236 irq->nm_rxq = nm_rxq++; 5237 5238 if (irq->nm_rxq != NULL && 5239 irq->rxq == NULL) { 5240 /* Netmap rx only */ 5241 rc = t4_alloc_irq(sc, irq, rid, 5242 t4_nm_intr, irq->nm_rxq, s); 5243 } 5244 if (irq->nm_rxq != NULL && 5245 irq->rxq != NULL) { 5246 /* NIC and Netmap rx */ 5247 rc = t4_alloc_irq(sc, irq, rid, 5248 t4_vi_intr, irq, s); 5249 } 5250 #endif 5251 if (irq->rxq != NULL && 5252 irq->nm_rxq == NULL) { 5253 /* NIC rx only */ 5254 rc = t4_alloc_irq(sc, irq, rid, 5255 t4_intr, irq->rxq, s); 5256 } 5257 if (rc != 0) 5258 return (rc); 5259 #ifdef RSS 5260 if (q < vi->nrxq) { 5261 bus_bind_intr(sc->dev, irq->res, 5262 rss_getcpu(q % nbuckets)); 5263 } 5264 #endif 5265 irq++; 5266 rid++; 5267 vi->nintr++; 5268 } 5269 } else { 5270 for_each_rxq(vi, q, rxq) { 5271 snprintf(s, sizeof(s), "%x%c%x", p, 5272 'a' + v, q); 5273 rc = t4_alloc_irq(sc, irq, rid, 5274 t4_intr, rxq, s); 5275 if (rc != 0) 5276 return (rc); 5277 #ifdef RSS 5278 bus_bind_intr(sc->dev, irq->res, 5279 rss_getcpu(q % nbuckets)); 5280 #endif 5281 irq++; 5282 rid++; 5283 vi->nintr++; 5284 } 5285 } 5286 #ifdef TCP_OFFLOAD 5287 for_each_ofld_rxq(vi, q, ofld_rxq) { 5288 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 5289 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 5290 ofld_rxq, s); 5291 if (rc != 0) 5292 return (rc); 5293 irq++; 5294 rid++; 5295 vi->nintr++; 5296 } 5297 #endif 5298 } 5299 } 5300 MPASS(irq == &sc->irq[sc->intr_count]); 5301 5302 return (0); 5303 } 5304 5305 int 5306 adapter_full_init(struct adapter *sc) 5307 { 5308 int rc, i; 5309 #ifdef RSS 5310 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5311 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5312 #endif 5313 5314 ASSERT_SYNCHRONIZED_OP(sc); 5315 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5316 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 5317 ("%s: FULL_INIT_DONE already", __func__)); 5318 5319 /* 5320 * queues that belong to the adapter (not any particular port). 5321 */ 5322 rc = t4_setup_adapter_queues(sc); 5323 if (rc != 0) 5324 goto done; 5325 5326 for (i = 0; i < nitems(sc->tq); i++) { 5327 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 5328 taskqueue_thread_enqueue, &sc->tq[i]); 5329 if (sc->tq[i] == NULL) { 5330 device_printf(sc->dev, 5331 "failed to allocate task queue %d\n", i); 5332 rc = ENOMEM; 5333 goto done; 5334 } 5335 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 5336 device_get_nameunit(sc->dev), i); 5337 } 5338 #ifdef RSS 5339 MPASS(RSS_KEYSIZE == 40); 5340 rss_getkey((void *)&raw_rss_key[0]); 5341 for (i = 0; i < nitems(rss_key); i++) { 5342 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 5343 } 5344 t4_write_rss_key(sc, &rss_key[0], -1, 1); 5345 #endif 5346 5347 if (!(sc->flags & IS_VF)) 5348 t4_intr_enable(sc); 5349 sc->flags |= FULL_INIT_DONE; 5350 done: 5351 if (rc != 0) 5352 adapter_full_uninit(sc); 5353 5354 return (rc); 5355 } 5356 5357 int 5358 adapter_full_uninit(struct adapter *sc) 5359 { 5360 int i; 5361 5362 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5363 5364 t4_teardown_adapter_queues(sc); 5365 5366 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 5367 taskqueue_free(sc->tq[i]); 5368 sc->tq[i] = NULL; 5369 } 5370 5371 sc->flags &= ~FULL_INIT_DONE; 5372 5373 return (0); 5374 } 5375 5376 #ifdef RSS 5377 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 5378 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 5379 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 5380 RSS_HASHTYPE_RSS_UDP_IPV6) 5381 5382 /* Translates kernel hash types to hardware. */ 5383 static int 5384 hashconfig_to_hashen(int hashconfig) 5385 { 5386 int hashen = 0; 5387 5388 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 5389 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 5390 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 5391 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 5392 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 5393 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5394 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5395 } 5396 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 5397 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5398 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5399 } 5400 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 5401 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5402 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 5403 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5404 5405 return (hashen); 5406 } 5407 5408 /* Translates hardware hash types to kernel. */ 5409 static int 5410 hashen_to_hashconfig(int hashen) 5411 { 5412 int hashconfig = 0; 5413 5414 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 5415 /* 5416 * If UDP hashing was enabled it must have been enabled for 5417 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 5418 * enabling any 4-tuple hash is nonsense configuration. 5419 */ 5420 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5421 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 5422 5423 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5424 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 5425 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5426 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 5427 } 5428 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5429 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 5430 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5431 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 5432 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 5433 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 5434 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 5435 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 5436 5437 return (hashconfig); 5438 } 5439 #endif 5440 5441 int 5442 vi_full_init(struct vi_info *vi) 5443 { 5444 struct adapter *sc = vi->pi->adapter; 5445 struct ifnet *ifp = vi->ifp; 5446 uint16_t *rss; 5447 struct sge_rxq *rxq; 5448 int rc, i, j; 5449 #ifdef RSS 5450 int nbuckets = rss_getnumbuckets(); 5451 int hashconfig = rss_gethashconfig(); 5452 int extra; 5453 #endif 5454 5455 ASSERT_SYNCHRONIZED_OP(sc); 5456 KASSERT((vi->flags & VI_INIT_DONE) == 0, 5457 ("%s: VI_INIT_DONE already", __func__)); 5458 5459 sysctl_ctx_init(&vi->ctx); 5460 vi->flags |= VI_SYSCTL_CTX; 5461 5462 /* 5463 * Allocate tx/rx/fl queues for this VI. 5464 */ 5465 rc = t4_setup_vi_queues(vi); 5466 if (rc != 0) 5467 goto done; /* error message displayed already */ 5468 5469 /* 5470 * Setup RSS for this VI. Save a copy of the RSS table for later use. 5471 */ 5472 if (vi->nrxq > vi->rss_size) { 5473 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 5474 "some queues will never receive traffic.\n", vi->nrxq, 5475 vi->rss_size); 5476 } else if (vi->rss_size % vi->nrxq) { 5477 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 5478 "expect uneven traffic distribution.\n", vi->nrxq, 5479 vi->rss_size); 5480 } 5481 #ifdef RSS 5482 if (vi->nrxq != nbuckets) { 5483 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5484 "performance will be impacted.\n", vi->nrxq, nbuckets); 5485 } 5486 #endif 5487 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5488 for (i = 0; i < vi->rss_size;) { 5489 #ifdef RSS 5490 j = rss_get_indirection_to_bucket(i); 5491 j %= vi->nrxq; 5492 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5493 rss[i++] = rxq->iq.abs_id; 5494 #else 5495 for_each_rxq(vi, j, rxq) { 5496 rss[i++] = rxq->iq.abs_id; 5497 if (i == vi->rss_size) 5498 break; 5499 } 5500 #endif 5501 } 5502 5503 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5504 vi->rss_size); 5505 if (rc != 0) { 5506 free(rss, M_CXGBE); 5507 if_printf(ifp, "rss_config failed: %d\n", rc); 5508 goto done; 5509 } 5510 5511 #ifdef RSS 5512 vi->hashen = hashconfig_to_hashen(hashconfig); 5513 5514 /* 5515 * We may have had to enable some hashes even though the global config 5516 * wants them disabled. This is a potential problem that must be 5517 * reported to the user. 5518 */ 5519 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 5520 5521 /* 5522 * If we consider only the supported hash types, then the enabled hashes 5523 * are a superset of the requested hashes. In other words, there cannot 5524 * be any supported hash that was requested but not enabled, but there 5525 * can be hashes that were not requested but had to be enabled. 5526 */ 5527 extra &= SUPPORTED_RSS_HASHTYPES; 5528 MPASS((extra & hashconfig) == 0); 5529 5530 if (extra) { 5531 if_printf(ifp, 5532 "global RSS config (0x%x) cannot be accommodated.\n", 5533 hashconfig); 5534 } 5535 if (extra & RSS_HASHTYPE_RSS_IPV4) 5536 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 5537 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 5538 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 5539 if (extra & RSS_HASHTYPE_RSS_IPV6) 5540 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 5541 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 5542 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 5543 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 5544 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 5545 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 5546 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 5547 #else 5548 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 5549 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 5550 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5551 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 5552 #endif 5553 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0); 5554 if (rc != 0) { 5555 free(rss, M_CXGBE); 5556 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 5557 goto done; 5558 } 5559 5560 vi->rss = rss; 5561 vi->flags |= VI_INIT_DONE; 5562 done: 5563 if (rc != 0) 5564 vi_full_uninit(vi); 5565 5566 return (rc); 5567 } 5568 5569 /* 5570 * Idempotent. 5571 */ 5572 int 5573 vi_full_uninit(struct vi_info *vi) 5574 { 5575 struct port_info *pi = vi->pi; 5576 struct adapter *sc = pi->adapter; 5577 int i; 5578 struct sge_rxq *rxq; 5579 struct sge_txq *txq; 5580 #ifdef TCP_OFFLOAD 5581 struct sge_ofld_rxq *ofld_rxq; 5582 #endif 5583 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5584 struct sge_wrq *ofld_txq; 5585 #endif 5586 5587 if (vi->flags & VI_INIT_DONE) { 5588 5589 /* Need to quiesce queues. */ 5590 5591 /* XXX: Only for the first VI? */ 5592 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5593 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5594 5595 for_each_txq(vi, i, txq) { 5596 quiesce_txq(sc, txq); 5597 } 5598 5599 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5600 for_each_ofld_txq(vi, i, ofld_txq) { 5601 quiesce_wrq(sc, ofld_txq); 5602 } 5603 #endif 5604 5605 for_each_rxq(vi, i, rxq) { 5606 quiesce_iq(sc, &rxq->iq); 5607 quiesce_fl(sc, &rxq->fl); 5608 } 5609 5610 #ifdef TCP_OFFLOAD 5611 for_each_ofld_rxq(vi, i, ofld_rxq) { 5612 quiesce_iq(sc, &ofld_rxq->iq); 5613 quiesce_fl(sc, &ofld_rxq->fl); 5614 } 5615 #endif 5616 free(vi->rss, M_CXGBE); 5617 free(vi->nm_rss, M_CXGBE); 5618 } 5619 5620 t4_teardown_vi_queues(vi); 5621 vi->flags &= ~VI_INIT_DONE; 5622 5623 return (0); 5624 } 5625 5626 static void 5627 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5628 { 5629 struct sge_eq *eq = &txq->eq; 5630 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5631 5632 (void) sc; /* unused */ 5633 5634 #ifdef INVARIANTS 5635 TXQ_LOCK(txq); 5636 MPASS((eq->flags & EQ_ENABLED) == 0); 5637 TXQ_UNLOCK(txq); 5638 #endif 5639 5640 /* Wait for the mp_ring to empty. */ 5641 while (!mp_ring_is_idle(txq->r)) { 5642 mp_ring_check_drainage(txq->r, 0); 5643 pause("rquiesce", 1); 5644 } 5645 5646 /* Then wait for the hardware to finish. */ 5647 while (spg->cidx != htobe16(eq->pidx)) 5648 pause("equiesce", 1); 5649 5650 /* Finally, wait for the driver to reclaim all descriptors. */ 5651 while (eq->cidx != eq->pidx) 5652 pause("dquiesce", 1); 5653 } 5654 5655 static void 5656 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5657 { 5658 5659 /* XXXTX */ 5660 } 5661 5662 static void 5663 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5664 { 5665 (void) sc; /* unused */ 5666 5667 /* Synchronize with the interrupt handler */ 5668 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5669 pause("iqfree", 1); 5670 } 5671 5672 static void 5673 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5674 { 5675 mtx_lock(&sc->sfl_lock); 5676 FL_LOCK(fl); 5677 fl->flags |= FL_DOOMED; 5678 FL_UNLOCK(fl); 5679 callout_stop(&sc->sfl_callout); 5680 mtx_unlock(&sc->sfl_lock); 5681 5682 KASSERT((fl->flags & FL_STARVING) == 0, 5683 ("%s: still starving", __func__)); 5684 } 5685 5686 static int 5687 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5688 driver_intr_t *handler, void *arg, char *name) 5689 { 5690 int rc; 5691 5692 irq->rid = rid; 5693 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5694 RF_SHAREABLE | RF_ACTIVE); 5695 if (irq->res == NULL) { 5696 device_printf(sc->dev, 5697 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5698 return (ENOMEM); 5699 } 5700 5701 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5702 NULL, handler, arg, &irq->tag); 5703 if (rc != 0) { 5704 device_printf(sc->dev, 5705 "failed to setup interrupt for rid %d, name %s: %d\n", 5706 rid, name, rc); 5707 } else if (name) 5708 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5709 5710 return (rc); 5711 } 5712 5713 static int 5714 t4_free_irq(struct adapter *sc, struct irq *irq) 5715 { 5716 if (irq->tag) 5717 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5718 if (irq->res) 5719 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5720 5721 bzero(irq, sizeof(*irq)); 5722 5723 return (0); 5724 } 5725 5726 static void 5727 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5728 { 5729 5730 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5731 t4_get_regs(sc, buf, regs->len); 5732 } 5733 5734 #define A_PL_INDIR_CMD 0x1f8 5735 5736 #define S_PL_AUTOINC 31 5737 #define M_PL_AUTOINC 0x1U 5738 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5739 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5740 5741 #define S_PL_VFID 20 5742 #define M_PL_VFID 0xffU 5743 #define V_PL_VFID(x) ((x) << S_PL_VFID) 5744 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5745 5746 #define S_PL_ADDR 0 5747 #define M_PL_ADDR 0xfffffU 5748 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5749 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5750 5751 #define A_PL_INDIR_DATA 0x1fc 5752 5753 static uint64_t 5754 read_vf_stat(struct adapter *sc, u_int vin, int reg) 5755 { 5756 u32 stats[2]; 5757 5758 mtx_assert(&sc->reg_lock, MA_OWNED); 5759 if (sc->flags & IS_VF) { 5760 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5761 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5762 } else { 5763 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5764 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 5765 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5766 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5767 } 5768 return (((uint64_t)stats[1]) << 32 | stats[0]); 5769 } 5770 5771 static void 5772 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 5773 { 5774 5775 #define GET_STAT(name) \ 5776 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 5777 5778 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5779 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5780 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5781 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5782 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5783 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5784 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5785 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5786 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5787 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5788 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5789 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5790 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5791 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5792 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5793 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5794 5795 #undef GET_STAT 5796 } 5797 5798 static void 5799 t4_clr_vi_stats(struct adapter *sc, u_int vin) 5800 { 5801 int reg; 5802 5803 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 5804 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5805 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5806 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5807 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5808 } 5809 5810 static void 5811 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5812 { 5813 struct timeval tv; 5814 const struct timeval interval = {0, 250000}; /* 250ms */ 5815 5816 if (!(vi->flags & VI_INIT_DONE)) 5817 return; 5818 5819 getmicrotime(&tv); 5820 timevalsub(&tv, &interval); 5821 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5822 return; 5823 5824 mtx_lock(&sc->reg_lock); 5825 t4_get_vi_stats(sc, vi->vin, &vi->stats); 5826 getmicrotime(&vi->last_refreshed); 5827 mtx_unlock(&sc->reg_lock); 5828 } 5829 5830 static void 5831 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5832 { 5833 u_int i, v, tnl_cong_drops, bg_map; 5834 struct timeval tv; 5835 const struct timeval interval = {0, 250000}; /* 250ms */ 5836 5837 getmicrotime(&tv); 5838 timevalsub(&tv, &interval); 5839 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5840 return; 5841 5842 tnl_cong_drops = 0; 5843 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5844 bg_map = pi->mps_bg_map; 5845 while (bg_map) { 5846 i = ffs(bg_map) - 1; 5847 mtx_lock(&sc->reg_lock); 5848 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5849 A_TP_MIB_TNL_CNG_DROP_0 + i); 5850 mtx_unlock(&sc->reg_lock); 5851 tnl_cong_drops += v; 5852 bg_map &= ~(1 << i); 5853 } 5854 pi->tnl_cong_drops = tnl_cong_drops; 5855 getmicrotime(&pi->last_refreshed); 5856 } 5857 5858 static void 5859 cxgbe_tick(void *arg) 5860 { 5861 struct port_info *pi = arg; 5862 struct adapter *sc = pi->adapter; 5863 5864 PORT_LOCK_ASSERT_OWNED(pi); 5865 cxgbe_refresh_stats(sc, pi); 5866 5867 callout_schedule(&pi->tick, hz); 5868 } 5869 5870 void 5871 vi_tick(void *arg) 5872 { 5873 struct vi_info *vi = arg; 5874 struct adapter *sc = vi->pi->adapter; 5875 5876 vi_refresh_stats(sc, vi); 5877 5878 callout_schedule(&vi->tick, hz); 5879 } 5880 5881 /* 5882 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5883 */ 5884 static char *caps_decoder[] = { 5885 "\20\001IPMI\002NCSI", /* 0: NBM */ 5886 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5887 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5888 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5889 "\006HASHFILTER\007ETHOFLD", 5890 "\20\001TOE", /* 4: TOE */ 5891 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5892 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5893 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5894 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5895 "\007T10DIF" 5896 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5897 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5898 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5899 "\004PO_INITIATOR\005PO_TARGET", 5900 }; 5901 5902 void 5903 t4_sysctls(struct adapter *sc) 5904 { 5905 struct sysctl_ctx_list *ctx; 5906 struct sysctl_oid *oid; 5907 struct sysctl_oid_list *children, *c0; 5908 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5909 5910 ctx = device_get_sysctl_ctx(sc->dev); 5911 5912 /* 5913 * dev.t4nex.X. 5914 */ 5915 oid = device_get_sysctl_tree(sc->dev); 5916 c0 = children = SYSCTL_CHILDREN(oid); 5917 5918 sc->sc_do_rxcopy = 1; 5919 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5920 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5921 5922 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5923 sc->params.nports, "# of ports"); 5924 5925 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5926 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells, 5927 sysctl_bitfield_8b, "A", "available doorbells"); 5928 5929 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5930 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5931 5932 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5933 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5934 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5935 "interrupt holdoff timer values (us)"); 5936 5937 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5938 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5939 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5940 "interrupt holdoff packet counter values"); 5941 5942 t4_sge_sysctls(sc, ctx, children); 5943 5944 sc->lro_timeout = 100; 5945 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5946 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5947 5948 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5949 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5950 5951 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5952 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5953 5954 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5955 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5956 5957 if (sc->flags & IS_VF) 5958 return; 5959 5960 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5961 NULL, chip_rev(sc), "chip hardware revision"); 5962 5963 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5964 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5965 5966 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5967 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5968 5969 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5970 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5971 5972 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5973 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5974 5975 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5976 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5977 5978 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5979 sc->er_version, 0, "expansion ROM version"); 5980 5981 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5982 sc->bs_version, 0, "bootstrap firmware version"); 5983 5984 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5985 NULL, sc->params.scfg_vers, "serial config version"); 5986 5987 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5988 NULL, sc->params.vpd_vers, "VPD version"); 5989 5990 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5991 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5992 5993 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5994 sc->cfcsum, "config file checksum"); 5995 5996 #define SYSCTL_CAP(name, n, text) \ 5997 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5998 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \ 5999 sysctl_bitfield_16b, "A", "available " text " capabilities") 6000 6001 SYSCTL_CAP(nbmcaps, 0, "NBM"); 6002 SYSCTL_CAP(linkcaps, 1, "link"); 6003 SYSCTL_CAP(switchcaps, 2, "switch"); 6004 SYSCTL_CAP(niccaps, 3, "NIC"); 6005 SYSCTL_CAP(toecaps, 4, "TCP offload"); 6006 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 6007 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 6008 SYSCTL_CAP(cryptocaps, 7, "crypto"); 6009 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 6010 #undef SYSCTL_CAP 6011 6012 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 6013 NULL, sc->tids.nftids, "number of filters"); 6014 6015 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 6016 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 6017 "chip temperature (in Celsius)"); 6018 6019 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING | 6020 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A", 6021 "microprocessor load averages (debug firmwares only)"); 6022 6023 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 6024 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 6025 6026 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 6027 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS, 6028 sysctl_cpus, "A", "local CPUs"); 6029 6030 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 6031 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS, 6032 sysctl_cpus, "A", "preferred CPUs for interrupts"); 6033 6034 /* 6035 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 6036 */ 6037 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 6038 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 6039 "logs and miscellaneous information"); 6040 children = SYSCTL_CHILDREN(oid); 6041 6042 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 6043 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6044 sysctl_cctrl, "A", "congestion control"); 6045 6046 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 6047 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6048 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 6049 6050 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 6051 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 6052 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 6053 6054 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 6055 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 6056 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 6057 6058 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 6059 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 6060 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 6061 6062 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 6063 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 6064 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 6065 6066 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 6067 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 6068 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 6069 6070 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 6071 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_la, 6072 "A", "CIM logic analyzer"); 6073 6074 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 6075 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6076 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 6077 6078 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 6079 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 6080 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 6081 6082 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 6083 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 6084 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 6085 6086 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 6087 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 6088 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 6089 6090 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 6091 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 6092 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 6093 6094 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 6095 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 6096 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 6097 6098 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 6099 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 6100 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 6101 6102 if (chip_id(sc) > CHELSIO_T4) { 6103 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 6104 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 6105 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 6106 6107 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 6108 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 6109 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 6110 } 6111 6112 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 6113 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6114 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 6115 6116 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 6117 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6118 sysctl_cim_qcfg, "A", "CIM queue configuration"); 6119 6120 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 6121 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6122 sysctl_cpl_stats, "A", "CPL statistics"); 6123 6124 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 6125 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6126 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 6127 6128 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 6129 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6130 sysctl_devlog, "A", "firmware's device log"); 6131 6132 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 6133 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6134 sysctl_fcoe_stats, "A", "FCoE statistics"); 6135 6136 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 6137 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6138 sysctl_hw_sched, "A", "hardware scheduler "); 6139 6140 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 6141 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6142 sysctl_l2t, "A", "hardware L2 table"); 6143 6144 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 6145 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6146 sysctl_smt, "A", "hardware source MAC table"); 6147 6148 #ifdef INET6 6149 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 6150 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6151 sysctl_clip, "A", "active CLIP table entries"); 6152 #endif 6153 6154 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 6155 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6156 sysctl_lb_stats, "A", "loopback statistics"); 6157 6158 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 6159 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6160 sysctl_meminfo, "A", "memory regions"); 6161 6162 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 6163 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6164 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 6165 "A", "MPS TCAM entries"); 6166 6167 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 6168 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6169 sysctl_path_mtus, "A", "path MTUs"); 6170 6171 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 6172 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6173 sysctl_pm_stats, "A", "PM statistics"); 6174 6175 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 6176 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6177 sysctl_rdma_stats, "A", "RDMA statistics"); 6178 6179 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 6180 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6181 sysctl_tcp_stats, "A", "TCP statistics"); 6182 6183 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 6184 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6185 sysctl_tids, "A", "TID information"); 6186 6187 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 6188 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6189 sysctl_tp_err_stats, "A", "TP error statistics"); 6190 6191 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 6192 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 6193 "TP logic analyzer event capture mask"); 6194 6195 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 6196 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6197 sysctl_tp_la, "A", "TP logic analyzer"); 6198 6199 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 6200 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6201 sysctl_tx_rate, "A", "Tx rate"); 6202 6203 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 6204 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6205 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 6206 6207 if (chip_id(sc) >= CHELSIO_T5) { 6208 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 6209 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6210 sysctl_wcwr_stats, "A", "write combined work requests"); 6211 } 6212 6213 #ifdef TCP_OFFLOAD 6214 if (is_offload(sc)) { 6215 int i; 6216 char s[4]; 6217 6218 /* 6219 * dev.t4nex.X.toe. 6220 */ 6221 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 6222 NULL, "TOE parameters"); 6223 children = SYSCTL_CHILDREN(oid); 6224 6225 sc->tt.cong_algorithm = -1; 6226 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 6227 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 6228 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 6229 "3 = highspeed)"); 6230 6231 sc->tt.sndbuf = 256 * 1024; 6232 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 6233 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 6234 6235 sc->tt.ddp = 0; 6236 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 6237 &sc->tt.ddp, 0, "DDP allowed"); 6238 6239 sc->tt.rx_coalesce = 1; 6240 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 6241 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 6242 6243 sc->tt.tls = 0; 6244 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 6245 &sc->tt.tls, 0, "Inline TLS allowed"); 6246 6247 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 6248 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 6249 "I", "TCP ports that use inline TLS+TOE RX"); 6250 6251 sc->tt.tx_align = 1; 6252 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 6253 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 6254 6255 sc->tt.tx_zcopy = 0; 6256 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 6257 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 6258 "Enable zero-copy aio_write(2)"); 6259 6260 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 6261 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6262 "cop_managed_offloading", CTLFLAG_RW, 6263 &sc->tt.cop_managed_offloading, 0, 6264 "COP (Connection Offload Policy) controls all TOE offload"); 6265 6266 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 6267 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 6268 "TP timer tick (us)"); 6269 6270 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 6271 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 6272 "TCP timestamp tick (us)"); 6273 6274 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 6275 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 6276 "DACK tick (us)"); 6277 6278 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 6279 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 6280 "IU", "DACK timer (us)"); 6281 6282 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 6283 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 6284 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 6285 6286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 6287 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 6288 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 6289 6290 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 6291 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 6292 sysctl_tp_timer, "LU", "Persist timer min (us)"); 6293 6294 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 6295 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 6296 sysctl_tp_timer, "LU", "Persist timer max (us)"); 6297 6298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 6299 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 6300 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 6301 6302 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 6303 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 6304 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 6305 6306 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 6307 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 6308 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 6309 6310 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 6311 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 6312 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 6313 6314 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 6315 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 6316 sysctl_tp_shift_cnt, "IU", 6317 "Number of SYN retransmissions before abort"); 6318 6319 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 6320 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 6321 sysctl_tp_shift_cnt, "IU", 6322 "Number of retransmissions before abort"); 6323 6324 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 6325 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 6326 sysctl_tp_shift_cnt, "IU", 6327 "Number of keepalive probes before abort"); 6328 6329 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 6330 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 6331 children = SYSCTL_CHILDREN(oid); 6332 for (i = 0; i < 16; i++) { 6333 snprintf(s, sizeof(s), "%u", i); 6334 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 6335 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 6336 "IU", "TOE retransmit backoff"); 6337 } 6338 } 6339 #endif 6340 } 6341 6342 void 6343 vi_sysctls(struct vi_info *vi) 6344 { 6345 struct sysctl_ctx_list *ctx; 6346 struct sysctl_oid *oid; 6347 struct sysctl_oid_list *children; 6348 6349 ctx = device_get_sysctl_ctx(vi->dev); 6350 6351 /* 6352 * dev.v?(cxgbe|cxl).X. 6353 */ 6354 oid = device_get_sysctl_tree(vi->dev); 6355 children = SYSCTL_CHILDREN(oid); 6356 6357 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 6358 vi->viid, "VI identifer"); 6359 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 6360 &vi->nrxq, 0, "# of rx queues"); 6361 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 6362 &vi->ntxq, 0, "# of tx queues"); 6363 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 6364 &vi->first_rxq, 0, "index of first rx queue"); 6365 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 6366 &vi->first_txq, 0, "index of first tx queue"); 6367 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 6368 vi->rss_base, "start of RSS indirection table"); 6369 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 6370 vi->rss_size, "size of RSS indirection table"); 6371 6372 if (IS_MAIN_VI(vi)) { 6373 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 6374 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 6375 "Reserve queue 0 for non-flowid packets"); 6376 } 6377 6378 #ifdef TCP_OFFLOAD 6379 if (vi->nofldrxq != 0) { 6380 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 6381 &vi->nofldrxq, 0, 6382 "# of rx queues for offloaded TCP connections"); 6383 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 6384 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 6385 "index of first TOE rx queue"); 6386 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 6387 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6388 sysctl_holdoff_tmr_idx_ofld, "I", 6389 "holdoff timer index for TOE queues"); 6390 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 6391 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6392 sysctl_holdoff_pktc_idx_ofld, "I", 6393 "holdoff packet counter index for TOE queues"); 6394 } 6395 #endif 6396 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 6397 if (vi->nofldtxq != 0) { 6398 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 6399 &vi->nofldtxq, 0, 6400 "# of tx queues for TOE/ETHOFLD"); 6401 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 6402 CTLFLAG_RD, &vi->first_ofld_txq, 0, 6403 "index of first TOE/ETHOFLD tx queue"); 6404 } 6405 #endif 6406 #ifdef DEV_NETMAP 6407 if (vi->nnmrxq != 0) { 6408 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 6409 &vi->nnmrxq, 0, "# of netmap rx queues"); 6410 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 6411 &vi->nnmtxq, 0, "# of netmap tx queues"); 6412 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 6413 CTLFLAG_RD, &vi->first_nm_rxq, 0, 6414 "index of first netmap rx queue"); 6415 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 6416 CTLFLAG_RD, &vi->first_nm_txq, 0, 6417 "index of first netmap tx queue"); 6418 } 6419 #endif 6420 6421 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 6422 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 6423 "holdoff timer index"); 6424 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 6425 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 6426 "holdoff packet counter index"); 6427 6428 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 6429 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 6430 "rx queue size"); 6431 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 6432 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 6433 "tx queue size"); 6434 } 6435 6436 static void 6437 cxgbe_sysctls(struct port_info *pi) 6438 { 6439 struct sysctl_ctx_list *ctx; 6440 struct sysctl_oid *oid; 6441 struct sysctl_oid_list *children, *children2; 6442 struct adapter *sc = pi->adapter; 6443 int i; 6444 char name[16]; 6445 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"}; 6446 6447 ctx = device_get_sysctl_ctx(pi->dev); 6448 6449 /* 6450 * dev.cxgbe.X. 6451 */ 6452 oid = device_get_sysctl_tree(pi->dev); 6453 children = SYSCTL_CHILDREN(oid); 6454 6455 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 6456 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 6457 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 6458 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6459 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 6460 "PHY temperature (in Celsius)"); 6461 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 6462 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 6463 "PHY firmware version"); 6464 } 6465 6466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 6467 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 6468 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 6469 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 6470 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 6471 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 6472 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 6473 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 6474 "autonegotiation (-1 = not supported)"); 6475 6476 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 6477 port_top_speed(pi), "max speed (in Gbps)"); 6478 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 6479 pi->mps_bg_map, "MPS buffer group map"); 6480 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 6481 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 6482 6483 if (sc->flags & IS_VF) 6484 return; 6485 6486 /* 6487 * dev.(cxgbe|cxl).X.tc. 6488 */ 6489 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 6490 "Tx scheduler traffic classes (cl_rl)"); 6491 children2 = SYSCTL_CHILDREN(oid); 6492 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 6493 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 6494 "pktsize for per-flow cl-rl (0 means up to the driver )"); 6495 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 6496 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 6497 "burstsize for per-flow cl-rl (0 means up to the driver)"); 6498 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 6499 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 6500 6501 snprintf(name, sizeof(name), "%d", i); 6502 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 6503 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 6504 "traffic class")); 6505 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 6506 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags, 6507 sysctl_bitfield_8b, "A", "flags"); 6508 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 6509 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 6510 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 6511 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 6512 sysctl_tc_params, "A", "traffic class parameters"); 6513 } 6514 6515 /* 6516 * dev.cxgbe.X.stats. 6517 */ 6518 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 6519 NULL, "port statistics"); 6520 children = SYSCTL_CHILDREN(oid); 6521 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 6522 &pi->tx_parse_error, 0, 6523 "# of tx packets with invalid length or # of segments"); 6524 6525 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 6526 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 6527 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 6528 sysctl_handle_t4_reg64, "QU", desc) 6529 6530 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 6531 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 6532 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 6533 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 6534 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 6535 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 6536 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 6537 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 6538 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 6539 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 6540 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 6541 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 6542 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 6543 "# of tx frames in this range", 6544 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 6545 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 6546 "# of tx frames in this range", 6547 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 6548 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 6549 "# of tx frames in this range", 6550 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 6551 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 6552 "# of tx frames in this range", 6553 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 6554 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 6555 "# of tx frames in this range", 6556 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 6557 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 6558 "# of tx frames in this range", 6559 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 6560 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 6561 "# of tx frames in this range", 6562 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 6563 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 6564 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 6565 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 6566 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 6567 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 6568 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 6569 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 6570 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 6571 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 6572 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 6573 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 6574 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 6575 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 6576 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 6577 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 6578 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 6579 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 6580 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 6581 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 6582 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 6583 6584 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 6585 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 6586 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 6587 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 6588 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 6589 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 6590 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 6591 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 6592 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 6593 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 6594 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 6595 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 6596 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 6597 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 6598 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 6599 "# of frames received with bad FCS", 6600 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 6601 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 6602 "# of frames received with length error", 6603 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 6604 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 6605 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 6606 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 6607 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 6608 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 6609 "# of rx frames in this range", 6610 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 6611 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 6612 "# of rx frames in this range", 6613 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 6614 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 6615 "# of rx frames in this range", 6616 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 6617 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 6618 "# of rx frames in this range", 6619 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 6620 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 6621 "# of rx frames in this range", 6622 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 6623 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 6624 "# of rx frames in this range", 6625 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 6626 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 6627 "# of rx frames in this range", 6628 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 6629 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 6630 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 6631 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 6632 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 6633 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 6634 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 6635 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 6636 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 6637 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6638 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6639 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6640 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6641 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6642 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6643 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6644 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6645 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6646 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6647 6648 #undef SYSCTL_ADD_T4_REG64 6649 6650 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6651 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6652 &pi->stats.name, desc) 6653 6654 /* We get these from port_stats and they may be stale by up to 1s */ 6655 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6656 "# drops due to buffer-group 0 overflows"); 6657 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6658 "# drops due to buffer-group 1 overflows"); 6659 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6660 "# drops due to buffer-group 2 overflows"); 6661 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6662 "# drops due to buffer-group 3 overflows"); 6663 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6664 "# of buffer-group 0 truncated packets"); 6665 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6666 "# of buffer-group 1 truncated packets"); 6667 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6668 "# of buffer-group 2 truncated packets"); 6669 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6670 "# of buffer-group 3 truncated packets"); 6671 6672 #undef SYSCTL_ADD_T4_PORTSTAT 6673 6674 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6675 CTLFLAG_RD, &pi->tx_tls_records, 6676 "# of TLS records transmitted"); 6677 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6678 CTLFLAG_RD, &pi->tx_tls_octets, 6679 "# of payload octets in transmitted TLS records"); 6680 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6681 CTLFLAG_RD, &pi->rx_tls_records, 6682 "# of TLS records received"); 6683 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6684 CTLFLAG_RD, &pi->rx_tls_octets, 6685 "# of payload octets in received TLS records"); 6686 } 6687 6688 static int 6689 sysctl_int_array(SYSCTL_HANDLER_ARGS) 6690 { 6691 int rc, *i, space = 0; 6692 struct sbuf sb; 6693 6694 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6695 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6696 if (space) 6697 sbuf_printf(&sb, " "); 6698 sbuf_printf(&sb, "%d", *i); 6699 space = 1; 6700 } 6701 rc = sbuf_finish(&sb); 6702 sbuf_delete(&sb); 6703 return (rc); 6704 } 6705 6706 static int 6707 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 6708 { 6709 int rc; 6710 struct sbuf *sb; 6711 6712 rc = sysctl_wire_old_buffer(req, 0); 6713 if (rc != 0) 6714 return(rc); 6715 6716 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6717 if (sb == NULL) 6718 return (ENOMEM); 6719 6720 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 6721 rc = sbuf_finish(sb); 6722 sbuf_delete(sb); 6723 6724 return (rc); 6725 } 6726 6727 static int 6728 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 6729 { 6730 int rc; 6731 struct sbuf *sb; 6732 6733 rc = sysctl_wire_old_buffer(req, 0); 6734 if (rc != 0) 6735 return(rc); 6736 6737 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6738 if (sb == NULL) 6739 return (ENOMEM); 6740 6741 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 6742 rc = sbuf_finish(sb); 6743 sbuf_delete(sb); 6744 6745 return (rc); 6746 } 6747 6748 static int 6749 sysctl_btphy(SYSCTL_HANDLER_ARGS) 6750 { 6751 struct port_info *pi = arg1; 6752 int op = arg2; 6753 struct adapter *sc = pi->adapter; 6754 u_int v; 6755 int rc; 6756 6757 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6758 if (rc) 6759 return (rc); 6760 /* XXX: magic numbers */ 6761 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6762 &v); 6763 end_synchronized_op(sc, 0); 6764 if (rc) 6765 return (rc); 6766 if (op == 0) 6767 v /= 256; 6768 6769 rc = sysctl_handle_int(oidp, &v, 0, req); 6770 return (rc); 6771 } 6772 6773 static int 6774 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6775 { 6776 struct vi_info *vi = arg1; 6777 int rc, val; 6778 6779 val = vi->rsrv_noflowq; 6780 rc = sysctl_handle_int(oidp, &val, 0, req); 6781 if (rc != 0 || req->newptr == NULL) 6782 return (rc); 6783 6784 if ((val >= 1) && (vi->ntxq > 1)) 6785 vi->rsrv_noflowq = 1; 6786 else 6787 vi->rsrv_noflowq = 0; 6788 6789 return (rc); 6790 } 6791 6792 static int 6793 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6794 { 6795 struct vi_info *vi = arg1; 6796 struct adapter *sc = vi->pi->adapter; 6797 int idx, rc, i; 6798 struct sge_rxq *rxq; 6799 uint8_t v; 6800 6801 idx = vi->tmr_idx; 6802 6803 rc = sysctl_handle_int(oidp, &idx, 0, req); 6804 if (rc != 0 || req->newptr == NULL) 6805 return (rc); 6806 6807 if (idx < 0 || idx >= SGE_NTIMERS) 6808 return (EINVAL); 6809 6810 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6811 "t4tmr"); 6812 if (rc) 6813 return (rc); 6814 6815 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6816 for_each_rxq(vi, i, rxq) { 6817 #ifdef atomic_store_rel_8 6818 atomic_store_rel_8(&rxq->iq.intr_params, v); 6819 #else 6820 rxq->iq.intr_params = v; 6821 #endif 6822 } 6823 vi->tmr_idx = idx; 6824 6825 end_synchronized_op(sc, LOCK_HELD); 6826 return (0); 6827 } 6828 6829 static int 6830 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6831 { 6832 struct vi_info *vi = arg1; 6833 struct adapter *sc = vi->pi->adapter; 6834 int idx, rc; 6835 6836 idx = vi->pktc_idx; 6837 6838 rc = sysctl_handle_int(oidp, &idx, 0, req); 6839 if (rc != 0 || req->newptr == NULL) 6840 return (rc); 6841 6842 if (idx < -1 || idx >= SGE_NCOUNTERS) 6843 return (EINVAL); 6844 6845 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6846 "t4pktc"); 6847 if (rc) 6848 return (rc); 6849 6850 if (vi->flags & VI_INIT_DONE) 6851 rc = EBUSY; /* cannot be changed once the queues are created */ 6852 else 6853 vi->pktc_idx = idx; 6854 6855 end_synchronized_op(sc, LOCK_HELD); 6856 return (rc); 6857 } 6858 6859 static int 6860 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6861 { 6862 struct vi_info *vi = arg1; 6863 struct adapter *sc = vi->pi->adapter; 6864 int qsize, rc; 6865 6866 qsize = vi->qsize_rxq; 6867 6868 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6869 if (rc != 0 || req->newptr == NULL) 6870 return (rc); 6871 6872 if (qsize < 128 || (qsize & 7)) 6873 return (EINVAL); 6874 6875 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6876 "t4rxqs"); 6877 if (rc) 6878 return (rc); 6879 6880 if (vi->flags & VI_INIT_DONE) 6881 rc = EBUSY; /* cannot be changed once the queues are created */ 6882 else 6883 vi->qsize_rxq = qsize; 6884 6885 end_synchronized_op(sc, LOCK_HELD); 6886 return (rc); 6887 } 6888 6889 static int 6890 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6891 { 6892 struct vi_info *vi = arg1; 6893 struct adapter *sc = vi->pi->adapter; 6894 int qsize, rc; 6895 6896 qsize = vi->qsize_txq; 6897 6898 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6899 if (rc != 0 || req->newptr == NULL) 6900 return (rc); 6901 6902 if (qsize < 128 || qsize > 65536) 6903 return (EINVAL); 6904 6905 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6906 "t4txqs"); 6907 if (rc) 6908 return (rc); 6909 6910 if (vi->flags & VI_INIT_DONE) 6911 rc = EBUSY; /* cannot be changed once the queues are created */ 6912 else 6913 vi->qsize_txq = qsize; 6914 6915 end_synchronized_op(sc, LOCK_HELD); 6916 return (rc); 6917 } 6918 6919 static int 6920 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6921 { 6922 struct port_info *pi = arg1; 6923 struct adapter *sc = pi->adapter; 6924 struct link_config *lc = &pi->link_cfg; 6925 int rc; 6926 6927 if (req->newptr == NULL) { 6928 struct sbuf *sb; 6929 static char *bits = "\20\1RX\2TX\3AUTO"; 6930 6931 rc = sysctl_wire_old_buffer(req, 0); 6932 if (rc != 0) 6933 return(rc); 6934 6935 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6936 if (sb == NULL) 6937 return (ENOMEM); 6938 6939 if (lc->link_ok) { 6940 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 6941 (lc->requested_fc & PAUSE_AUTONEG), bits); 6942 } else { 6943 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 6944 PAUSE_RX | PAUSE_AUTONEG), bits); 6945 } 6946 rc = sbuf_finish(sb); 6947 sbuf_delete(sb); 6948 } else { 6949 char s[2]; 6950 int n; 6951 6952 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 6953 PAUSE_AUTONEG)); 6954 s[1] = 0; 6955 6956 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6957 if (rc != 0) 6958 return(rc); 6959 6960 if (s[1] != 0) 6961 return (EINVAL); 6962 if (s[0] < '0' || s[0] > '9') 6963 return (EINVAL); /* not a number */ 6964 n = s[0] - '0'; 6965 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 6966 return (EINVAL); /* some other bit is set too */ 6967 6968 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6969 "t4PAUSE"); 6970 if (rc) 6971 return (rc); 6972 PORT_LOCK(pi); 6973 lc->requested_fc = n; 6974 fixup_link_config(pi); 6975 if (pi->up_vis > 0) 6976 rc = apply_link_config(pi); 6977 set_current_media(pi); 6978 PORT_UNLOCK(pi); 6979 end_synchronized_op(sc, 0); 6980 } 6981 6982 return (rc); 6983 } 6984 6985 static int 6986 sysctl_fec(SYSCTL_HANDLER_ARGS) 6987 { 6988 struct port_info *pi = arg1; 6989 struct adapter *sc = pi->adapter; 6990 struct link_config *lc = &pi->link_cfg; 6991 int rc; 6992 int8_t old; 6993 6994 if (req->newptr == NULL) { 6995 struct sbuf *sb; 6996 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO"; 6997 6998 rc = sysctl_wire_old_buffer(req, 0); 6999 if (rc != 0) 7000 return(rc); 7001 7002 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7003 if (sb == NULL) 7004 return (ENOMEM); 7005 7006 /* 7007 * Display the requested_fec when the link is down -- the actual 7008 * FEC makes sense only when the link is up. 7009 */ 7010 if (lc->link_ok) { 7011 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) | 7012 (lc->requested_fec & FEC_AUTO), bits); 7013 } else { 7014 sbuf_printf(sb, "%b", lc->requested_fec, bits); 7015 } 7016 rc = sbuf_finish(sb); 7017 sbuf_delete(sb); 7018 } else { 7019 char s[3]; 7020 int n; 7021 7022 snprintf(s, sizeof(s), "%d", 7023 lc->requested_fec == FEC_AUTO ? -1 : 7024 lc->requested_fec & M_FW_PORT_CAP32_FEC); 7025 7026 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 7027 if (rc != 0) 7028 return(rc); 7029 7030 n = strtol(&s[0], NULL, 0); 7031 if (n < 0 || n & FEC_AUTO) 7032 n = FEC_AUTO; 7033 else { 7034 if (n & ~M_FW_PORT_CAP32_FEC) 7035 return (EINVAL);/* some other bit is set too */ 7036 if (!powerof2(n)) 7037 return (EINVAL);/* one bit can be set at most */ 7038 } 7039 7040 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7041 "t4fec"); 7042 if (rc) 7043 return (rc); 7044 PORT_LOCK(pi); 7045 old = lc->requested_fec; 7046 if (n == FEC_AUTO) 7047 lc->requested_fec = FEC_AUTO; 7048 else if (n == 0) 7049 lc->requested_fec = FEC_NONE; 7050 else { 7051 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) != 7052 lc->supported) { 7053 rc = ENOTSUP; 7054 goto done; 7055 } 7056 lc->requested_fec = n; 7057 } 7058 fixup_link_config(pi); 7059 if (pi->up_vis > 0) { 7060 rc = apply_link_config(pi); 7061 if (rc != 0) { 7062 lc->requested_fec = old; 7063 if (rc == FW_EPROTO) 7064 rc = ENOTSUP; 7065 } 7066 } 7067 done: 7068 PORT_UNLOCK(pi); 7069 end_synchronized_op(sc, 0); 7070 } 7071 7072 return (rc); 7073 } 7074 7075 static int 7076 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 7077 { 7078 struct port_info *pi = arg1; 7079 struct adapter *sc = pi->adapter; 7080 struct link_config *lc = &pi->link_cfg; 7081 int rc, val; 7082 7083 if (lc->supported & FW_PORT_CAP32_ANEG) 7084 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 7085 else 7086 val = -1; 7087 rc = sysctl_handle_int(oidp, &val, 0, req); 7088 if (rc != 0 || req->newptr == NULL) 7089 return (rc); 7090 if (val == 0) 7091 val = AUTONEG_DISABLE; 7092 else if (val == 1) 7093 val = AUTONEG_ENABLE; 7094 else 7095 val = AUTONEG_AUTO; 7096 7097 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7098 "t4aneg"); 7099 if (rc) 7100 return (rc); 7101 PORT_LOCK(pi); 7102 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) { 7103 rc = ENOTSUP; 7104 goto done; 7105 } 7106 lc->requested_aneg = val; 7107 fixup_link_config(pi); 7108 if (pi->up_vis > 0) 7109 rc = apply_link_config(pi); 7110 set_current_media(pi); 7111 done: 7112 PORT_UNLOCK(pi); 7113 end_synchronized_op(sc, 0); 7114 return (rc); 7115 } 7116 7117 static int 7118 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 7119 { 7120 struct adapter *sc = arg1; 7121 int reg = arg2; 7122 uint64_t val; 7123 7124 val = t4_read_reg64(sc, reg); 7125 7126 return (sysctl_handle_64(oidp, &val, 0, req)); 7127 } 7128 7129 static int 7130 sysctl_temperature(SYSCTL_HANDLER_ARGS) 7131 { 7132 struct adapter *sc = arg1; 7133 int rc, t; 7134 uint32_t param, val; 7135 7136 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 7137 if (rc) 7138 return (rc); 7139 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7140 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7141 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 7142 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7143 end_synchronized_op(sc, 0); 7144 if (rc) 7145 return (rc); 7146 7147 /* unknown is returned as 0 but we display -1 in that case */ 7148 t = val == 0 ? -1 : val; 7149 7150 rc = sysctl_handle_int(oidp, &t, 0, req); 7151 return (rc); 7152 } 7153 7154 static int 7155 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 7156 { 7157 struct adapter *sc = arg1; 7158 struct sbuf *sb; 7159 int rc; 7160 uint32_t param, val; 7161 7162 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 7163 if (rc) 7164 return (rc); 7165 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7166 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 7167 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7168 end_synchronized_op(sc, 0); 7169 if (rc) 7170 return (rc); 7171 7172 rc = sysctl_wire_old_buffer(req, 0); 7173 if (rc != 0) 7174 return (rc); 7175 7176 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7177 if (sb == NULL) 7178 return (ENOMEM); 7179 7180 if (val == 0xffffffff) { 7181 /* Only debug and custom firmwares report load averages. */ 7182 sbuf_printf(sb, "not available"); 7183 } else { 7184 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 7185 (val >> 16) & 0xff); 7186 } 7187 rc = sbuf_finish(sb); 7188 sbuf_delete(sb); 7189 7190 return (rc); 7191 } 7192 7193 static int 7194 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 7195 { 7196 struct adapter *sc = arg1; 7197 struct sbuf *sb; 7198 int rc, i; 7199 uint16_t incr[NMTUS][NCCTRL_WIN]; 7200 static const char *dec_fac[] = { 7201 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 7202 "0.9375" 7203 }; 7204 7205 rc = sysctl_wire_old_buffer(req, 0); 7206 if (rc != 0) 7207 return (rc); 7208 7209 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7210 if (sb == NULL) 7211 return (ENOMEM); 7212 7213 t4_read_cong_tbl(sc, incr); 7214 7215 for (i = 0; i < NCCTRL_WIN; ++i) { 7216 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 7217 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 7218 incr[5][i], incr[6][i], incr[7][i]); 7219 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 7220 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 7221 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 7222 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 7223 } 7224 7225 rc = sbuf_finish(sb); 7226 sbuf_delete(sb); 7227 7228 return (rc); 7229 } 7230 7231 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 7232 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 7233 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 7234 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 7235 }; 7236 7237 static int 7238 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 7239 { 7240 struct adapter *sc = arg1; 7241 struct sbuf *sb; 7242 int rc, i, n, qid = arg2; 7243 uint32_t *buf, *p; 7244 char *qtype; 7245 u_int cim_num_obq = sc->chip_params->cim_num_obq; 7246 7247 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 7248 ("%s: bad qid %d\n", __func__, qid)); 7249 7250 if (qid < CIM_NUM_IBQ) { 7251 /* inbound queue */ 7252 qtype = "IBQ"; 7253 n = 4 * CIM_IBQ_SIZE; 7254 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7255 rc = t4_read_cim_ibq(sc, qid, buf, n); 7256 } else { 7257 /* outbound queue */ 7258 qtype = "OBQ"; 7259 qid -= CIM_NUM_IBQ; 7260 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 7261 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7262 rc = t4_read_cim_obq(sc, qid, buf, n); 7263 } 7264 7265 if (rc < 0) { 7266 rc = -rc; 7267 goto done; 7268 } 7269 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 7270 7271 rc = sysctl_wire_old_buffer(req, 0); 7272 if (rc != 0) 7273 goto done; 7274 7275 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7276 if (sb == NULL) { 7277 rc = ENOMEM; 7278 goto done; 7279 } 7280 7281 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 7282 for (i = 0, p = buf; i < n; i += 16, p += 4) 7283 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 7284 p[2], p[3]); 7285 7286 rc = sbuf_finish(sb); 7287 sbuf_delete(sb); 7288 done: 7289 free(buf, M_CXGBE); 7290 return (rc); 7291 } 7292 7293 static void 7294 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7295 { 7296 uint32_t *p; 7297 7298 sbuf_printf(sb, "Status Data PC%s", 7299 cfg & F_UPDBGLACAPTPCONLY ? "" : 7300 " LS0Stat LS0Addr LS0Data"); 7301 7302 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 7303 if (cfg & F_UPDBGLACAPTPCONLY) { 7304 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 7305 p[6], p[7]); 7306 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 7307 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 7308 p[4] & 0xff, p[5] >> 8); 7309 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 7310 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7311 p[1] & 0xf, p[2] >> 4); 7312 } else { 7313 sbuf_printf(sb, 7314 "\n %02x %x%07x %x%07x %08x %08x " 7315 "%08x%08x%08x%08x", 7316 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7317 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 7318 p[6], p[7]); 7319 } 7320 } 7321 } 7322 7323 static void 7324 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7325 { 7326 uint32_t *p; 7327 7328 sbuf_printf(sb, "Status Inst Data PC%s", 7329 cfg & F_UPDBGLACAPTPCONLY ? "" : 7330 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 7331 7332 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 7333 if (cfg & F_UPDBGLACAPTPCONLY) { 7334 sbuf_printf(sb, "\n %02x %08x %08x %08x", 7335 p[3] & 0xff, p[2], p[1], p[0]); 7336 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 7337 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 7338 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 7339 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 7340 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 7341 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 7342 p[6] >> 16); 7343 } else { 7344 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 7345 "%08x %08x %08x %08x %08x %08x", 7346 (p[9] >> 16) & 0xff, 7347 p[9] & 0xffff, p[8] >> 16, 7348 p[8] & 0xffff, p[7] >> 16, 7349 p[7] & 0xffff, p[6] >> 16, 7350 p[2], p[1], p[0], p[5], p[4], p[3]); 7351 } 7352 } 7353 } 7354 7355 static int 7356 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 7357 { 7358 uint32_t cfg, *buf; 7359 int rc; 7360 7361 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7362 if (rc != 0) 7363 return (rc); 7364 7365 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7366 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7367 M_ZERO | flags); 7368 if (buf == NULL) 7369 return (ENOMEM); 7370 7371 rc = -t4_cim_read_la(sc, buf, NULL); 7372 if (rc != 0) 7373 goto done; 7374 if (chip_id(sc) < CHELSIO_T6) 7375 sbuf_cim_la4(sc, sb, buf, cfg); 7376 else 7377 sbuf_cim_la6(sc, sb, buf, cfg); 7378 7379 done: 7380 free(buf, M_CXGBE); 7381 return (rc); 7382 } 7383 7384 static int 7385 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 7386 { 7387 struct adapter *sc = arg1; 7388 struct sbuf *sb; 7389 int rc; 7390 7391 rc = sysctl_wire_old_buffer(req, 0); 7392 if (rc != 0) 7393 return (rc); 7394 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7395 if (sb == NULL) 7396 return (ENOMEM); 7397 7398 rc = sbuf_cim_la(sc, sb, M_WAITOK); 7399 if (rc == 0) 7400 rc = sbuf_finish(sb); 7401 sbuf_delete(sb); 7402 return (rc); 7403 } 7404 7405 bool 7406 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose) 7407 { 7408 struct sbuf sb; 7409 int rc; 7410 7411 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7412 return (false); 7413 rc = sbuf_cim_la(sc, &sb, M_NOWAIT); 7414 if (rc == 0) { 7415 rc = sbuf_finish(&sb); 7416 if (rc == 0) { 7417 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s", 7418 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7419 } 7420 } 7421 sbuf_delete(&sb); 7422 return (false); 7423 } 7424 7425 static int 7426 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 7427 { 7428 struct adapter *sc = arg1; 7429 u_int i; 7430 struct sbuf *sb; 7431 uint32_t *buf, *p; 7432 int rc; 7433 7434 rc = sysctl_wire_old_buffer(req, 0); 7435 if (rc != 0) 7436 return (rc); 7437 7438 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7439 if (sb == NULL) 7440 return (ENOMEM); 7441 7442 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 7443 M_ZERO | M_WAITOK); 7444 7445 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 7446 p = buf; 7447 7448 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7449 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 7450 p[1], p[0]); 7451 } 7452 7453 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 7454 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7455 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 7456 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 7457 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 7458 (p[1] >> 2) | ((p[2] & 3) << 30), 7459 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 7460 p[0] & 1); 7461 } 7462 7463 rc = sbuf_finish(sb); 7464 sbuf_delete(sb); 7465 free(buf, M_CXGBE); 7466 return (rc); 7467 } 7468 7469 static int 7470 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 7471 { 7472 struct adapter *sc = arg1; 7473 u_int i; 7474 struct sbuf *sb; 7475 uint32_t *buf, *p; 7476 int rc; 7477 7478 rc = sysctl_wire_old_buffer(req, 0); 7479 if (rc != 0) 7480 return (rc); 7481 7482 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7483 if (sb == NULL) 7484 return (ENOMEM); 7485 7486 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 7487 M_ZERO | M_WAITOK); 7488 7489 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 7490 p = buf; 7491 7492 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 7493 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7494 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 7495 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 7496 p[4], p[3], p[2], p[1], p[0]); 7497 } 7498 7499 sbuf_printf(sb, "\n\nCntl ID Data"); 7500 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7501 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 7502 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 7503 } 7504 7505 rc = sbuf_finish(sb); 7506 sbuf_delete(sb); 7507 free(buf, M_CXGBE); 7508 return (rc); 7509 } 7510 7511 static int 7512 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 7513 { 7514 struct adapter *sc = arg1; 7515 struct sbuf *sb; 7516 int rc, i; 7517 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7518 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7519 uint16_t thres[CIM_NUM_IBQ]; 7520 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 7521 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 7522 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 7523 7524 cim_num_obq = sc->chip_params->cim_num_obq; 7525 if (is_t4(sc)) { 7526 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 7527 obq_rdaddr = A_UP_OBQ_0_REALADDR; 7528 } else { 7529 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 7530 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 7531 } 7532 nq = CIM_NUM_IBQ + cim_num_obq; 7533 7534 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 7535 if (rc == 0) 7536 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 7537 if (rc != 0) 7538 return (rc); 7539 7540 t4_read_cimq_cfg(sc, base, size, thres); 7541 7542 rc = sysctl_wire_old_buffer(req, 0); 7543 if (rc != 0) 7544 return (rc); 7545 7546 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7547 if (sb == NULL) 7548 return (ENOMEM); 7549 7550 sbuf_printf(sb, 7551 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 7552 7553 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 7554 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 7555 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 7556 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7557 G_QUEREMFLITS(p[2]) * 16); 7558 for ( ; i < nq; i++, p += 4, wr += 2) 7559 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 7560 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 7561 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7562 G_QUEREMFLITS(p[2]) * 16); 7563 7564 rc = sbuf_finish(sb); 7565 sbuf_delete(sb); 7566 7567 return (rc); 7568 } 7569 7570 static int 7571 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 7572 { 7573 struct adapter *sc = arg1; 7574 struct sbuf *sb; 7575 int rc; 7576 struct tp_cpl_stats stats; 7577 7578 rc = sysctl_wire_old_buffer(req, 0); 7579 if (rc != 0) 7580 return (rc); 7581 7582 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7583 if (sb == NULL) 7584 return (ENOMEM); 7585 7586 mtx_lock(&sc->reg_lock); 7587 t4_tp_get_cpl_stats(sc, &stats, 0); 7588 mtx_unlock(&sc->reg_lock); 7589 7590 if (sc->chip_params->nchan > 2) { 7591 sbuf_printf(sb, " channel 0 channel 1" 7592 " channel 2 channel 3"); 7593 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 7594 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 7595 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 7596 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 7597 } else { 7598 sbuf_printf(sb, " channel 0 channel 1"); 7599 sbuf_printf(sb, "\nCPL requests: %10u %10u", 7600 stats.req[0], stats.req[1]); 7601 sbuf_printf(sb, "\nCPL responses: %10u %10u", 7602 stats.rsp[0], stats.rsp[1]); 7603 } 7604 7605 rc = sbuf_finish(sb); 7606 sbuf_delete(sb); 7607 7608 return (rc); 7609 } 7610 7611 static int 7612 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 7613 { 7614 struct adapter *sc = arg1; 7615 struct sbuf *sb; 7616 int rc; 7617 struct tp_usm_stats stats; 7618 7619 rc = sysctl_wire_old_buffer(req, 0); 7620 if (rc != 0) 7621 return(rc); 7622 7623 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7624 if (sb == NULL) 7625 return (ENOMEM); 7626 7627 t4_get_usm_stats(sc, &stats, 1); 7628 7629 sbuf_printf(sb, "Frames: %u\n", stats.frames); 7630 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 7631 sbuf_printf(sb, "Drops: %u", stats.drops); 7632 7633 rc = sbuf_finish(sb); 7634 sbuf_delete(sb); 7635 7636 return (rc); 7637 } 7638 7639 static const char * const devlog_level_strings[] = { 7640 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 7641 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 7642 [FW_DEVLOG_LEVEL_ERR] = "ERR", 7643 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 7644 [FW_DEVLOG_LEVEL_INFO] = "INFO", 7645 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 7646 }; 7647 7648 static const char * const devlog_facility_strings[] = { 7649 [FW_DEVLOG_FACILITY_CORE] = "CORE", 7650 [FW_DEVLOG_FACILITY_CF] = "CF", 7651 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 7652 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 7653 [FW_DEVLOG_FACILITY_RES] = "RES", 7654 [FW_DEVLOG_FACILITY_HW] = "HW", 7655 [FW_DEVLOG_FACILITY_FLR] = "FLR", 7656 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 7657 [FW_DEVLOG_FACILITY_PHY] = "PHY", 7658 [FW_DEVLOG_FACILITY_MAC] = "MAC", 7659 [FW_DEVLOG_FACILITY_PORT] = "PORT", 7660 [FW_DEVLOG_FACILITY_VI] = "VI", 7661 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 7662 [FW_DEVLOG_FACILITY_ACL] = "ACL", 7663 [FW_DEVLOG_FACILITY_TM] = "TM", 7664 [FW_DEVLOG_FACILITY_QFC] = "QFC", 7665 [FW_DEVLOG_FACILITY_DCB] = "DCB", 7666 [FW_DEVLOG_FACILITY_ETH] = "ETH", 7667 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 7668 [FW_DEVLOG_FACILITY_RI] = "RI", 7669 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 7670 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 7671 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 7672 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 7673 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 7674 }; 7675 7676 static int 7677 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 7678 { 7679 int i, j, rc, nentries, first = 0; 7680 struct devlog_params *dparams = &sc->params.devlog; 7681 struct fw_devlog_e *buf, *e; 7682 uint64_t ftstamp = UINT64_MAX; 7683 7684 if (dparams->addr == 0) 7685 return (ENXIO); 7686 7687 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7688 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 7689 if (buf == NULL) 7690 return (ENOMEM); 7691 7692 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 7693 if (rc != 0) 7694 goto done; 7695 7696 nentries = dparams->size / sizeof(struct fw_devlog_e); 7697 for (i = 0; i < nentries; i++) { 7698 e = &buf[i]; 7699 7700 if (e->timestamp == 0) 7701 break; /* end */ 7702 7703 e->timestamp = be64toh(e->timestamp); 7704 e->seqno = be32toh(e->seqno); 7705 for (j = 0; j < 8; j++) 7706 e->params[j] = be32toh(e->params[j]); 7707 7708 if (e->timestamp < ftstamp) { 7709 ftstamp = e->timestamp; 7710 first = i; 7711 } 7712 } 7713 7714 if (buf[first].timestamp == 0) 7715 goto done; /* nothing in the log */ 7716 7717 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 7718 "Seq#", "Tstamp", "Level", "Facility", "Message"); 7719 7720 i = first; 7721 do { 7722 e = &buf[i]; 7723 if (e->timestamp == 0) 7724 break; /* end */ 7725 7726 sbuf_printf(sb, "%10d %15ju %8s %8s ", 7727 e->seqno, e->timestamp, 7728 (e->level < nitems(devlog_level_strings) ? 7729 devlog_level_strings[e->level] : "UNKNOWN"), 7730 (e->facility < nitems(devlog_facility_strings) ? 7731 devlog_facility_strings[e->facility] : "UNKNOWN")); 7732 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7733 e->params[2], e->params[3], e->params[4], 7734 e->params[5], e->params[6], e->params[7]); 7735 7736 if (++i == nentries) 7737 i = 0; 7738 } while (i != first); 7739 done: 7740 free(buf, M_CXGBE); 7741 return (rc); 7742 } 7743 7744 static int 7745 sysctl_devlog(SYSCTL_HANDLER_ARGS) 7746 { 7747 struct adapter *sc = arg1; 7748 int rc; 7749 struct sbuf *sb; 7750 7751 rc = sysctl_wire_old_buffer(req, 0); 7752 if (rc != 0) 7753 return (rc); 7754 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7755 if (sb == NULL) 7756 return (ENOMEM); 7757 7758 rc = sbuf_devlog(sc, sb, M_WAITOK); 7759 if (rc == 0) 7760 rc = sbuf_finish(sb); 7761 sbuf_delete(sb); 7762 return (rc); 7763 } 7764 7765 void 7766 t4_os_dump_devlog(struct adapter *sc) 7767 { 7768 int rc; 7769 struct sbuf sb; 7770 7771 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7772 return; 7773 rc = sbuf_devlog(sc, &sb, M_NOWAIT); 7774 if (rc == 0) { 7775 rc = sbuf_finish(&sb); 7776 if (rc == 0) { 7777 log(LOG_DEBUG, "%s: device log follows.\n%s", 7778 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7779 } 7780 } 7781 sbuf_delete(&sb); 7782 } 7783 7784 static int 7785 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7786 { 7787 struct adapter *sc = arg1; 7788 struct sbuf *sb; 7789 int rc; 7790 struct tp_fcoe_stats stats[MAX_NCHAN]; 7791 int i, nchan = sc->chip_params->nchan; 7792 7793 rc = sysctl_wire_old_buffer(req, 0); 7794 if (rc != 0) 7795 return (rc); 7796 7797 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7798 if (sb == NULL) 7799 return (ENOMEM); 7800 7801 for (i = 0; i < nchan; i++) 7802 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7803 7804 if (nchan > 2) { 7805 sbuf_printf(sb, " channel 0 channel 1" 7806 " channel 2 channel 3"); 7807 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7808 stats[0].octets_ddp, stats[1].octets_ddp, 7809 stats[2].octets_ddp, stats[3].octets_ddp); 7810 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7811 stats[0].frames_ddp, stats[1].frames_ddp, 7812 stats[2].frames_ddp, stats[3].frames_ddp); 7813 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7814 stats[0].frames_drop, stats[1].frames_drop, 7815 stats[2].frames_drop, stats[3].frames_drop); 7816 } else { 7817 sbuf_printf(sb, " channel 0 channel 1"); 7818 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7819 stats[0].octets_ddp, stats[1].octets_ddp); 7820 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7821 stats[0].frames_ddp, stats[1].frames_ddp); 7822 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7823 stats[0].frames_drop, stats[1].frames_drop); 7824 } 7825 7826 rc = sbuf_finish(sb); 7827 sbuf_delete(sb); 7828 7829 return (rc); 7830 } 7831 7832 static int 7833 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7834 { 7835 struct adapter *sc = arg1; 7836 struct sbuf *sb; 7837 int rc, i; 7838 unsigned int map, kbps, ipg, mode; 7839 unsigned int pace_tab[NTX_SCHED]; 7840 7841 rc = sysctl_wire_old_buffer(req, 0); 7842 if (rc != 0) 7843 return (rc); 7844 7845 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7846 if (sb == NULL) 7847 return (ENOMEM); 7848 7849 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7850 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7851 t4_read_pace_tbl(sc, pace_tab); 7852 7853 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7854 "Class IPG (0.1 ns) Flow IPG (us)"); 7855 7856 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7857 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7858 sbuf_printf(sb, "\n %u %-5s %u ", i, 7859 (mode & (1 << i)) ? "flow" : "class", map & 3); 7860 if (kbps) 7861 sbuf_printf(sb, "%9u ", kbps); 7862 else 7863 sbuf_printf(sb, " disabled "); 7864 7865 if (ipg) 7866 sbuf_printf(sb, "%13u ", ipg); 7867 else 7868 sbuf_printf(sb, " disabled "); 7869 7870 if (pace_tab[i]) 7871 sbuf_printf(sb, "%10u", pace_tab[i]); 7872 else 7873 sbuf_printf(sb, " disabled"); 7874 } 7875 7876 rc = sbuf_finish(sb); 7877 sbuf_delete(sb); 7878 7879 return (rc); 7880 } 7881 7882 static int 7883 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7884 { 7885 struct adapter *sc = arg1; 7886 struct sbuf *sb; 7887 int rc, i, j; 7888 uint64_t *p0, *p1; 7889 struct lb_port_stats s[2]; 7890 static const char *stat_name[] = { 7891 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7892 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7893 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7894 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7895 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7896 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7897 "BG2FramesTrunc:", "BG3FramesTrunc:" 7898 }; 7899 7900 rc = sysctl_wire_old_buffer(req, 0); 7901 if (rc != 0) 7902 return (rc); 7903 7904 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7905 if (sb == NULL) 7906 return (ENOMEM); 7907 7908 memset(s, 0, sizeof(s)); 7909 7910 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7911 t4_get_lb_stats(sc, i, &s[0]); 7912 t4_get_lb_stats(sc, i + 1, &s[1]); 7913 7914 p0 = &s[0].octets; 7915 p1 = &s[1].octets; 7916 sbuf_printf(sb, "%s Loopback %u" 7917 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7918 7919 for (j = 0; j < nitems(stat_name); j++) 7920 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7921 *p0++, *p1++); 7922 } 7923 7924 rc = sbuf_finish(sb); 7925 sbuf_delete(sb); 7926 7927 return (rc); 7928 } 7929 7930 static int 7931 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7932 { 7933 int rc = 0; 7934 struct port_info *pi = arg1; 7935 struct link_config *lc = &pi->link_cfg; 7936 struct sbuf *sb; 7937 7938 rc = sysctl_wire_old_buffer(req, 0); 7939 if (rc != 0) 7940 return(rc); 7941 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7942 if (sb == NULL) 7943 return (ENOMEM); 7944 7945 if (lc->link_ok || lc->link_down_rc == 255) 7946 sbuf_printf(sb, "n/a"); 7947 else 7948 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7949 7950 rc = sbuf_finish(sb); 7951 sbuf_delete(sb); 7952 7953 return (rc); 7954 } 7955 7956 struct mem_desc { 7957 unsigned int base; 7958 unsigned int limit; 7959 unsigned int idx; 7960 }; 7961 7962 static int 7963 mem_desc_cmp(const void *a, const void *b) 7964 { 7965 return ((const struct mem_desc *)a)->base - 7966 ((const struct mem_desc *)b)->base; 7967 } 7968 7969 static void 7970 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7971 unsigned int to) 7972 { 7973 unsigned int size; 7974 7975 if (from == to) 7976 return; 7977 7978 size = to - from + 1; 7979 if (size == 0) 7980 return; 7981 7982 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7983 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7984 } 7985 7986 static int 7987 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7988 { 7989 struct adapter *sc = arg1; 7990 struct sbuf *sb; 7991 int rc, i, n; 7992 uint32_t lo, hi, used, alloc; 7993 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 7994 static const char *region[] = { 7995 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 7996 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 7997 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 7998 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 7999 "RQUDP region:", "PBL region:", "TXPBL region:", 8000 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 8001 "On-chip queues:", "TLS keys:", 8002 }; 8003 struct mem_desc avail[4]; 8004 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 8005 struct mem_desc *md = mem; 8006 8007 rc = sysctl_wire_old_buffer(req, 0); 8008 if (rc != 0) 8009 return (rc); 8010 8011 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8012 if (sb == NULL) 8013 return (ENOMEM); 8014 8015 for (i = 0; i < nitems(mem); i++) { 8016 mem[i].limit = 0; 8017 mem[i].idx = i; 8018 } 8019 8020 /* Find and sort the populated memory ranges */ 8021 i = 0; 8022 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 8023 if (lo & F_EDRAM0_ENABLE) { 8024 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 8025 avail[i].base = G_EDRAM0_BASE(hi) << 20; 8026 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 8027 avail[i].idx = 0; 8028 i++; 8029 } 8030 if (lo & F_EDRAM1_ENABLE) { 8031 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 8032 avail[i].base = G_EDRAM1_BASE(hi) << 20; 8033 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 8034 avail[i].idx = 1; 8035 i++; 8036 } 8037 if (lo & F_EXT_MEM_ENABLE) { 8038 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 8039 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 8040 avail[i].limit = avail[i].base + 8041 (G_EXT_MEM_SIZE(hi) << 20); 8042 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 8043 i++; 8044 } 8045 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 8046 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 8047 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 8048 avail[i].limit = avail[i].base + 8049 (G_EXT_MEM1_SIZE(hi) << 20); 8050 avail[i].idx = 4; 8051 i++; 8052 } 8053 if (!i) /* no memory available */ 8054 return 0; 8055 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 8056 8057 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 8058 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 8059 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 8060 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 8061 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 8062 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 8063 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 8064 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 8065 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 8066 8067 /* the next few have explicit upper bounds */ 8068 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 8069 md->limit = md->base - 1 + 8070 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 8071 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 8072 md++; 8073 8074 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 8075 md->limit = md->base - 1 + 8076 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 8077 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 8078 md++; 8079 8080 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8081 if (chip_id(sc) <= CHELSIO_T5) 8082 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 8083 else 8084 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 8085 md->limit = 0; 8086 } else { 8087 md->base = 0; 8088 md->idx = nitems(region); /* hide it */ 8089 } 8090 md++; 8091 8092 #define ulp_region(reg) \ 8093 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 8094 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 8095 8096 ulp_region(RX_ISCSI); 8097 ulp_region(RX_TDDP); 8098 ulp_region(TX_TPT); 8099 ulp_region(RX_STAG); 8100 ulp_region(RX_RQ); 8101 ulp_region(RX_RQUDP); 8102 ulp_region(RX_PBL); 8103 ulp_region(TX_PBL); 8104 #undef ulp_region 8105 8106 md->base = 0; 8107 md->idx = nitems(region); 8108 if (!is_t4(sc)) { 8109 uint32_t size = 0; 8110 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 8111 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 8112 8113 if (is_t5(sc)) { 8114 if (sge_ctrl & F_VFIFO_ENABLE) 8115 size = G_DBVFIFO_SIZE(fifo_size); 8116 } else 8117 size = G_T6_DBVFIFO_SIZE(fifo_size); 8118 8119 if (size) { 8120 md->base = G_BASEADDR(t4_read_reg(sc, 8121 A_SGE_DBVFIFO_BADDR)); 8122 md->limit = md->base + (size << 2) - 1; 8123 } 8124 } 8125 md++; 8126 8127 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 8128 md->limit = 0; 8129 md++; 8130 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 8131 md->limit = 0; 8132 md++; 8133 8134 md->base = sc->vres.ocq.start; 8135 if (sc->vres.ocq.size) 8136 md->limit = md->base + sc->vres.ocq.size - 1; 8137 else 8138 md->idx = nitems(region); /* hide it */ 8139 md++; 8140 8141 md->base = sc->vres.key.start; 8142 if (sc->vres.key.size) 8143 md->limit = md->base + sc->vres.key.size - 1; 8144 else 8145 md->idx = nitems(region); /* hide it */ 8146 md++; 8147 8148 /* add any address-space holes, there can be up to 3 */ 8149 for (n = 0; n < i - 1; n++) 8150 if (avail[n].limit < avail[n + 1].base) 8151 (md++)->base = avail[n].limit; 8152 if (avail[n].limit) 8153 (md++)->base = avail[n].limit; 8154 8155 n = md - mem; 8156 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 8157 8158 for (lo = 0; lo < i; lo++) 8159 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 8160 avail[lo].limit - 1); 8161 8162 sbuf_printf(sb, "\n"); 8163 for (i = 0; i < n; i++) { 8164 if (mem[i].idx >= nitems(region)) 8165 continue; /* skip holes */ 8166 if (!mem[i].limit) 8167 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 8168 mem_region_show(sb, region[mem[i].idx], mem[i].base, 8169 mem[i].limit); 8170 } 8171 8172 sbuf_printf(sb, "\n"); 8173 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 8174 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 8175 mem_region_show(sb, "uP RAM:", lo, hi); 8176 8177 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 8178 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 8179 mem_region_show(sb, "uP Extmem2:", lo, hi); 8180 8181 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 8182 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 8183 G_PMRXMAXPAGE(lo), 8184 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 8185 (lo & F_PMRXNUMCHN) ? 2 : 1); 8186 8187 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 8188 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 8189 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 8190 G_PMTXMAXPAGE(lo), 8191 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 8192 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 8193 sbuf_printf(sb, "%u p-structs\n", 8194 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 8195 8196 for (i = 0; i < 4; i++) { 8197 if (chip_id(sc) > CHELSIO_T5) 8198 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 8199 else 8200 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 8201 if (is_t5(sc)) { 8202 used = G_T5_USED(lo); 8203 alloc = G_T5_ALLOC(lo); 8204 } else { 8205 used = G_USED(lo); 8206 alloc = G_ALLOC(lo); 8207 } 8208 /* For T6 these are MAC buffer groups */ 8209 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 8210 i, used, alloc); 8211 } 8212 for (i = 0; i < sc->chip_params->nchan; i++) { 8213 if (chip_id(sc) > CHELSIO_T5) 8214 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 8215 else 8216 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 8217 if (is_t5(sc)) { 8218 used = G_T5_USED(lo); 8219 alloc = G_T5_ALLOC(lo); 8220 } else { 8221 used = G_USED(lo); 8222 alloc = G_ALLOC(lo); 8223 } 8224 /* For T6 these are MAC buffer groups */ 8225 sbuf_printf(sb, 8226 "\nLoopback %d using %u pages out of %u allocated", 8227 i, used, alloc); 8228 } 8229 8230 rc = sbuf_finish(sb); 8231 sbuf_delete(sb); 8232 8233 return (rc); 8234 } 8235 8236 static inline void 8237 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 8238 { 8239 *mask = x | y; 8240 y = htobe64(y); 8241 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 8242 } 8243 8244 static int 8245 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 8246 { 8247 struct adapter *sc = arg1; 8248 struct sbuf *sb; 8249 int rc, i; 8250 8251 MPASS(chip_id(sc) <= CHELSIO_T5); 8252 8253 rc = sysctl_wire_old_buffer(req, 0); 8254 if (rc != 0) 8255 return (rc); 8256 8257 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8258 if (sb == NULL) 8259 return (ENOMEM); 8260 8261 sbuf_printf(sb, 8262 "Idx Ethernet address Mask Vld Ports PF" 8263 " VF Replication P0 P1 P2 P3 ML"); 8264 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8265 uint64_t tcamx, tcamy, mask; 8266 uint32_t cls_lo, cls_hi; 8267 uint8_t addr[ETHER_ADDR_LEN]; 8268 8269 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 8270 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 8271 if (tcamx & tcamy) 8272 continue; 8273 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8274 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8275 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8276 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 8277 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 8278 addr[3], addr[4], addr[5], (uintmax_t)mask, 8279 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 8280 G_PORTMAP(cls_hi), G_PF(cls_lo), 8281 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 8282 8283 if (cls_lo & F_REPLICATE) { 8284 struct fw_ldst_cmd ldst_cmd; 8285 8286 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8287 ldst_cmd.op_to_addrspace = 8288 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8289 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8290 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8291 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8292 ldst_cmd.u.mps.rplc.fid_idx = 8293 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8294 V_FW_LDST_CMD_IDX(i)); 8295 8296 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8297 "t4mps"); 8298 if (rc) 8299 break; 8300 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8301 sizeof(ldst_cmd), &ldst_cmd); 8302 end_synchronized_op(sc, 0); 8303 8304 if (rc != 0) { 8305 sbuf_printf(sb, "%36d", rc); 8306 rc = 0; 8307 } else { 8308 sbuf_printf(sb, " %08x %08x %08x %08x", 8309 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8310 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8311 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8312 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8313 } 8314 } else 8315 sbuf_printf(sb, "%36s", ""); 8316 8317 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 8318 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 8319 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 8320 } 8321 8322 if (rc) 8323 (void) sbuf_finish(sb); 8324 else 8325 rc = sbuf_finish(sb); 8326 sbuf_delete(sb); 8327 8328 return (rc); 8329 } 8330 8331 static int 8332 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 8333 { 8334 struct adapter *sc = arg1; 8335 struct sbuf *sb; 8336 int rc, i; 8337 8338 MPASS(chip_id(sc) > CHELSIO_T5); 8339 8340 rc = sysctl_wire_old_buffer(req, 0); 8341 if (rc != 0) 8342 return (rc); 8343 8344 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8345 if (sb == NULL) 8346 return (ENOMEM); 8347 8348 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 8349 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 8350 " Replication" 8351 " P0 P1 P2 P3 ML\n"); 8352 8353 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8354 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 8355 uint16_t ivlan; 8356 uint64_t tcamx, tcamy, val, mask; 8357 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 8358 uint8_t addr[ETHER_ADDR_LEN]; 8359 8360 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 8361 if (i < 256) 8362 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 8363 else 8364 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 8365 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8366 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8367 tcamy = G_DMACH(val) << 32; 8368 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8369 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8370 lookup_type = G_DATALKPTYPE(data2); 8371 port_num = G_DATAPORTNUM(data2); 8372 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8373 /* Inner header VNI */ 8374 vniy = ((data2 & F_DATAVIDH2) << 23) | 8375 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8376 dip_hit = data2 & F_DATADIPHIT; 8377 vlan_vld = 0; 8378 } else { 8379 vniy = 0; 8380 dip_hit = 0; 8381 vlan_vld = data2 & F_DATAVIDH2; 8382 ivlan = G_VIDL(val); 8383 } 8384 8385 ctl |= V_CTLXYBITSEL(1); 8386 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8387 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8388 tcamx = G_DMACH(val) << 32; 8389 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8390 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8391 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8392 /* Inner header VNI mask */ 8393 vnix = ((data2 & F_DATAVIDH2) << 23) | 8394 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8395 } else 8396 vnix = 0; 8397 8398 if (tcamx & tcamy) 8399 continue; 8400 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8401 8402 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8403 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8404 8405 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8406 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8407 "%012jx %06x %06x - - %3c" 8408 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 8409 addr[1], addr[2], addr[3], addr[4], addr[5], 8410 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 8411 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8412 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8413 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8414 } else { 8415 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8416 "%012jx - - ", i, addr[0], addr[1], 8417 addr[2], addr[3], addr[4], addr[5], 8418 (uintmax_t)mask); 8419 8420 if (vlan_vld) 8421 sbuf_printf(sb, "%4u Y ", ivlan); 8422 else 8423 sbuf_printf(sb, " - N "); 8424 8425 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 8426 lookup_type ? 'I' : 'O', port_num, 8427 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8428 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8429 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8430 } 8431 8432 8433 if (cls_lo & F_T6_REPLICATE) { 8434 struct fw_ldst_cmd ldst_cmd; 8435 8436 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8437 ldst_cmd.op_to_addrspace = 8438 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8439 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8440 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8441 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8442 ldst_cmd.u.mps.rplc.fid_idx = 8443 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8444 V_FW_LDST_CMD_IDX(i)); 8445 8446 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8447 "t6mps"); 8448 if (rc) 8449 break; 8450 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8451 sizeof(ldst_cmd), &ldst_cmd); 8452 end_synchronized_op(sc, 0); 8453 8454 if (rc != 0) { 8455 sbuf_printf(sb, "%72d", rc); 8456 rc = 0; 8457 } else { 8458 sbuf_printf(sb, " %08x %08x %08x %08x" 8459 " %08x %08x %08x %08x", 8460 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 8461 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 8462 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 8463 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 8464 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8465 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8466 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8467 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8468 } 8469 } else 8470 sbuf_printf(sb, "%72s", ""); 8471 8472 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 8473 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 8474 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 8475 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 8476 } 8477 8478 if (rc) 8479 (void) sbuf_finish(sb); 8480 else 8481 rc = sbuf_finish(sb); 8482 sbuf_delete(sb); 8483 8484 return (rc); 8485 } 8486 8487 static int 8488 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 8489 { 8490 struct adapter *sc = arg1; 8491 struct sbuf *sb; 8492 int rc; 8493 uint16_t mtus[NMTUS]; 8494 8495 rc = sysctl_wire_old_buffer(req, 0); 8496 if (rc != 0) 8497 return (rc); 8498 8499 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8500 if (sb == NULL) 8501 return (ENOMEM); 8502 8503 t4_read_mtu_tbl(sc, mtus, NULL); 8504 8505 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 8506 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 8507 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 8508 mtus[14], mtus[15]); 8509 8510 rc = sbuf_finish(sb); 8511 sbuf_delete(sb); 8512 8513 return (rc); 8514 } 8515 8516 static int 8517 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 8518 { 8519 struct adapter *sc = arg1; 8520 struct sbuf *sb; 8521 int rc, i; 8522 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 8523 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 8524 static const char *tx_stats[MAX_PM_NSTATS] = { 8525 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 8526 "Tx FIFO wait", NULL, "Tx latency" 8527 }; 8528 static const char *rx_stats[MAX_PM_NSTATS] = { 8529 "Read:", "Write bypass:", "Write mem:", "Flush:", 8530 "Rx FIFO wait", NULL, "Rx latency" 8531 }; 8532 8533 rc = sysctl_wire_old_buffer(req, 0); 8534 if (rc != 0) 8535 return (rc); 8536 8537 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8538 if (sb == NULL) 8539 return (ENOMEM); 8540 8541 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 8542 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 8543 8544 sbuf_printf(sb, " Tx pcmds Tx bytes"); 8545 for (i = 0; i < 4; i++) { 8546 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8547 tx_cyc[i]); 8548 } 8549 8550 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 8551 for (i = 0; i < 4; i++) { 8552 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8553 rx_cyc[i]); 8554 } 8555 8556 if (chip_id(sc) > CHELSIO_T5) { 8557 sbuf_printf(sb, 8558 "\n Total wait Total occupancy"); 8559 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8560 tx_cyc[i]); 8561 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8562 rx_cyc[i]); 8563 8564 i += 2; 8565 MPASS(i < nitems(tx_stats)); 8566 8567 sbuf_printf(sb, 8568 "\n Reads Total wait"); 8569 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8570 tx_cyc[i]); 8571 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8572 rx_cyc[i]); 8573 } 8574 8575 rc = sbuf_finish(sb); 8576 sbuf_delete(sb); 8577 8578 return (rc); 8579 } 8580 8581 static int 8582 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 8583 { 8584 struct adapter *sc = arg1; 8585 struct sbuf *sb; 8586 int rc; 8587 struct tp_rdma_stats stats; 8588 8589 rc = sysctl_wire_old_buffer(req, 0); 8590 if (rc != 0) 8591 return (rc); 8592 8593 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8594 if (sb == NULL) 8595 return (ENOMEM); 8596 8597 mtx_lock(&sc->reg_lock); 8598 t4_tp_get_rdma_stats(sc, &stats, 0); 8599 mtx_unlock(&sc->reg_lock); 8600 8601 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 8602 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 8603 8604 rc = sbuf_finish(sb); 8605 sbuf_delete(sb); 8606 8607 return (rc); 8608 } 8609 8610 static int 8611 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 8612 { 8613 struct adapter *sc = arg1; 8614 struct sbuf *sb; 8615 int rc; 8616 struct tp_tcp_stats v4, v6; 8617 8618 rc = sysctl_wire_old_buffer(req, 0); 8619 if (rc != 0) 8620 return (rc); 8621 8622 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8623 if (sb == NULL) 8624 return (ENOMEM); 8625 8626 mtx_lock(&sc->reg_lock); 8627 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 8628 mtx_unlock(&sc->reg_lock); 8629 8630 sbuf_printf(sb, 8631 " IP IPv6\n"); 8632 sbuf_printf(sb, "OutRsts: %20u %20u\n", 8633 v4.tcp_out_rsts, v6.tcp_out_rsts); 8634 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 8635 v4.tcp_in_segs, v6.tcp_in_segs); 8636 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 8637 v4.tcp_out_segs, v6.tcp_out_segs); 8638 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 8639 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 8640 8641 rc = sbuf_finish(sb); 8642 sbuf_delete(sb); 8643 8644 return (rc); 8645 } 8646 8647 static int 8648 sysctl_tids(SYSCTL_HANDLER_ARGS) 8649 { 8650 struct adapter *sc = arg1; 8651 struct sbuf *sb; 8652 int rc; 8653 struct tid_info *t = &sc->tids; 8654 8655 rc = sysctl_wire_old_buffer(req, 0); 8656 if (rc != 0) 8657 return (rc); 8658 8659 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8660 if (sb == NULL) 8661 return (ENOMEM); 8662 8663 if (t->natids) { 8664 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 8665 t->atids_in_use); 8666 } 8667 8668 if (t->nhpftids) { 8669 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 8670 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 8671 } 8672 8673 if (t->ntids) { 8674 sbuf_printf(sb, "TID range: "); 8675 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8676 uint32_t b, hb; 8677 8678 if (chip_id(sc) <= CHELSIO_T5) { 8679 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 8680 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 8681 } else { 8682 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 8683 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 8684 } 8685 8686 if (b) 8687 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1); 8688 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 8689 } else 8690 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1); 8691 sbuf_printf(sb, ", in use: %u\n", 8692 atomic_load_acq_int(&t->tids_in_use)); 8693 } 8694 8695 if (t->nstids) { 8696 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 8697 t->stid_base + t->nstids - 1, t->stids_in_use); 8698 } 8699 8700 if (t->nftids) { 8701 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 8702 t->ftid_end, t->ftids_in_use); 8703 } 8704 8705 if (t->netids) { 8706 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 8707 t->etid_base + t->netids - 1, t->etids_in_use); 8708 } 8709 8710 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 8711 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 8712 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 8713 8714 rc = sbuf_finish(sb); 8715 sbuf_delete(sb); 8716 8717 return (rc); 8718 } 8719 8720 static int 8721 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 8722 { 8723 struct adapter *sc = arg1; 8724 struct sbuf *sb; 8725 int rc; 8726 struct tp_err_stats stats; 8727 8728 rc = sysctl_wire_old_buffer(req, 0); 8729 if (rc != 0) 8730 return (rc); 8731 8732 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8733 if (sb == NULL) 8734 return (ENOMEM); 8735 8736 mtx_lock(&sc->reg_lock); 8737 t4_tp_get_err_stats(sc, &stats, 0); 8738 mtx_unlock(&sc->reg_lock); 8739 8740 if (sc->chip_params->nchan > 2) { 8741 sbuf_printf(sb, " channel 0 channel 1" 8742 " channel 2 channel 3\n"); 8743 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 8744 stats.mac_in_errs[0], stats.mac_in_errs[1], 8745 stats.mac_in_errs[2], stats.mac_in_errs[3]); 8746 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 8747 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 8748 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 8749 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 8750 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 8751 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 8752 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 8753 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 8754 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 8755 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 8756 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 8757 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 8758 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 8759 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 8760 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 8761 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 8762 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 8763 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 8764 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 8765 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 8766 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 8767 } else { 8768 sbuf_printf(sb, " channel 0 channel 1\n"); 8769 sbuf_printf(sb, "macInErrs: %10u %10u\n", 8770 stats.mac_in_errs[0], stats.mac_in_errs[1]); 8771 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 8772 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 8773 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 8774 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8775 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8776 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8777 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8778 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8779 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8780 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8781 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8782 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8783 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8784 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8785 } 8786 8787 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8788 stats.ofld_no_neigh, stats.ofld_cong_defer); 8789 8790 rc = sbuf_finish(sb); 8791 sbuf_delete(sb); 8792 8793 return (rc); 8794 } 8795 8796 static int 8797 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8798 { 8799 struct adapter *sc = arg1; 8800 struct tp_params *tpp = &sc->params.tp; 8801 u_int mask; 8802 int rc; 8803 8804 mask = tpp->la_mask >> 16; 8805 rc = sysctl_handle_int(oidp, &mask, 0, req); 8806 if (rc != 0 || req->newptr == NULL) 8807 return (rc); 8808 if (mask > 0xffff) 8809 return (EINVAL); 8810 tpp->la_mask = mask << 16; 8811 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8812 8813 return (0); 8814 } 8815 8816 struct field_desc { 8817 const char *name; 8818 u_int start; 8819 u_int width; 8820 }; 8821 8822 static void 8823 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8824 { 8825 char buf[32]; 8826 int line_size = 0; 8827 8828 while (f->name) { 8829 uint64_t mask = (1ULL << f->width) - 1; 8830 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8831 ((uintmax_t)v >> f->start) & mask); 8832 8833 if (line_size + len >= 79) { 8834 line_size = 8; 8835 sbuf_printf(sb, "\n "); 8836 } 8837 sbuf_printf(sb, "%s ", buf); 8838 line_size += len + 1; 8839 f++; 8840 } 8841 sbuf_printf(sb, "\n"); 8842 } 8843 8844 static const struct field_desc tp_la0[] = { 8845 { "RcfOpCodeOut", 60, 4 }, 8846 { "State", 56, 4 }, 8847 { "WcfState", 52, 4 }, 8848 { "RcfOpcSrcOut", 50, 2 }, 8849 { "CRxError", 49, 1 }, 8850 { "ERxError", 48, 1 }, 8851 { "SanityFailed", 47, 1 }, 8852 { "SpuriousMsg", 46, 1 }, 8853 { "FlushInputMsg", 45, 1 }, 8854 { "FlushInputCpl", 44, 1 }, 8855 { "RssUpBit", 43, 1 }, 8856 { "RssFilterHit", 42, 1 }, 8857 { "Tid", 32, 10 }, 8858 { "InitTcb", 31, 1 }, 8859 { "LineNumber", 24, 7 }, 8860 { "Emsg", 23, 1 }, 8861 { "EdataOut", 22, 1 }, 8862 { "Cmsg", 21, 1 }, 8863 { "CdataOut", 20, 1 }, 8864 { "EreadPdu", 19, 1 }, 8865 { "CreadPdu", 18, 1 }, 8866 { "TunnelPkt", 17, 1 }, 8867 { "RcfPeerFin", 16, 1 }, 8868 { "RcfReasonOut", 12, 4 }, 8869 { "TxCchannel", 10, 2 }, 8870 { "RcfTxChannel", 8, 2 }, 8871 { "RxEchannel", 6, 2 }, 8872 { "RcfRxChannel", 5, 1 }, 8873 { "RcfDataOutSrdy", 4, 1 }, 8874 { "RxDvld", 3, 1 }, 8875 { "RxOoDvld", 2, 1 }, 8876 { "RxCongestion", 1, 1 }, 8877 { "TxCongestion", 0, 1 }, 8878 { NULL } 8879 }; 8880 8881 static const struct field_desc tp_la1[] = { 8882 { "CplCmdIn", 56, 8 }, 8883 { "CplCmdOut", 48, 8 }, 8884 { "ESynOut", 47, 1 }, 8885 { "EAckOut", 46, 1 }, 8886 { "EFinOut", 45, 1 }, 8887 { "ERstOut", 44, 1 }, 8888 { "SynIn", 43, 1 }, 8889 { "AckIn", 42, 1 }, 8890 { "FinIn", 41, 1 }, 8891 { "RstIn", 40, 1 }, 8892 { "DataIn", 39, 1 }, 8893 { "DataInVld", 38, 1 }, 8894 { "PadIn", 37, 1 }, 8895 { "RxBufEmpty", 36, 1 }, 8896 { "RxDdp", 35, 1 }, 8897 { "RxFbCongestion", 34, 1 }, 8898 { "TxFbCongestion", 33, 1 }, 8899 { "TxPktSumSrdy", 32, 1 }, 8900 { "RcfUlpType", 28, 4 }, 8901 { "Eread", 27, 1 }, 8902 { "Ebypass", 26, 1 }, 8903 { "Esave", 25, 1 }, 8904 { "Static0", 24, 1 }, 8905 { "Cread", 23, 1 }, 8906 { "Cbypass", 22, 1 }, 8907 { "Csave", 21, 1 }, 8908 { "CPktOut", 20, 1 }, 8909 { "RxPagePoolFull", 18, 2 }, 8910 { "RxLpbkPkt", 17, 1 }, 8911 { "TxLpbkPkt", 16, 1 }, 8912 { "RxVfValid", 15, 1 }, 8913 { "SynLearned", 14, 1 }, 8914 { "SetDelEntry", 13, 1 }, 8915 { "SetInvEntry", 12, 1 }, 8916 { "CpcmdDvld", 11, 1 }, 8917 { "CpcmdSave", 10, 1 }, 8918 { "RxPstructsFull", 8, 2 }, 8919 { "EpcmdDvld", 7, 1 }, 8920 { "EpcmdFlush", 6, 1 }, 8921 { "EpcmdTrimPrefix", 5, 1 }, 8922 { "EpcmdTrimPostfix", 4, 1 }, 8923 { "ERssIp4Pkt", 3, 1 }, 8924 { "ERssIp6Pkt", 2, 1 }, 8925 { "ERssTcpUdpPkt", 1, 1 }, 8926 { "ERssFceFipPkt", 0, 1 }, 8927 { NULL } 8928 }; 8929 8930 static const struct field_desc tp_la2[] = { 8931 { "CplCmdIn", 56, 8 }, 8932 { "MpsVfVld", 55, 1 }, 8933 { "MpsPf", 52, 3 }, 8934 { "MpsVf", 44, 8 }, 8935 { "SynIn", 43, 1 }, 8936 { "AckIn", 42, 1 }, 8937 { "FinIn", 41, 1 }, 8938 { "RstIn", 40, 1 }, 8939 { "DataIn", 39, 1 }, 8940 { "DataInVld", 38, 1 }, 8941 { "PadIn", 37, 1 }, 8942 { "RxBufEmpty", 36, 1 }, 8943 { "RxDdp", 35, 1 }, 8944 { "RxFbCongestion", 34, 1 }, 8945 { "TxFbCongestion", 33, 1 }, 8946 { "TxPktSumSrdy", 32, 1 }, 8947 { "RcfUlpType", 28, 4 }, 8948 { "Eread", 27, 1 }, 8949 { "Ebypass", 26, 1 }, 8950 { "Esave", 25, 1 }, 8951 { "Static0", 24, 1 }, 8952 { "Cread", 23, 1 }, 8953 { "Cbypass", 22, 1 }, 8954 { "Csave", 21, 1 }, 8955 { "CPktOut", 20, 1 }, 8956 { "RxPagePoolFull", 18, 2 }, 8957 { "RxLpbkPkt", 17, 1 }, 8958 { "TxLpbkPkt", 16, 1 }, 8959 { "RxVfValid", 15, 1 }, 8960 { "SynLearned", 14, 1 }, 8961 { "SetDelEntry", 13, 1 }, 8962 { "SetInvEntry", 12, 1 }, 8963 { "CpcmdDvld", 11, 1 }, 8964 { "CpcmdSave", 10, 1 }, 8965 { "RxPstructsFull", 8, 2 }, 8966 { "EpcmdDvld", 7, 1 }, 8967 { "EpcmdFlush", 6, 1 }, 8968 { "EpcmdTrimPrefix", 5, 1 }, 8969 { "EpcmdTrimPostfix", 4, 1 }, 8970 { "ERssIp4Pkt", 3, 1 }, 8971 { "ERssIp6Pkt", 2, 1 }, 8972 { "ERssTcpUdpPkt", 1, 1 }, 8973 { "ERssFceFipPkt", 0, 1 }, 8974 { NULL } 8975 }; 8976 8977 static void 8978 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8979 { 8980 8981 field_desc_show(sb, *p, tp_la0); 8982 } 8983 8984 static void 8985 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8986 { 8987 8988 if (idx) 8989 sbuf_printf(sb, "\n"); 8990 field_desc_show(sb, p[0], tp_la0); 8991 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8992 field_desc_show(sb, p[1], tp_la0); 8993 } 8994 8995 static void 8996 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 8997 { 8998 8999 if (idx) 9000 sbuf_printf(sb, "\n"); 9001 field_desc_show(sb, p[0], tp_la0); 9002 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9003 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 9004 } 9005 9006 static int 9007 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 9008 { 9009 struct adapter *sc = arg1; 9010 struct sbuf *sb; 9011 uint64_t *buf, *p; 9012 int rc; 9013 u_int i, inc; 9014 void (*show_func)(struct sbuf *, uint64_t *, int); 9015 9016 rc = sysctl_wire_old_buffer(req, 0); 9017 if (rc != 0) 9018 return (rc); 9019 9020 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9021 if (sb == NULL) 9022 return (ENOMEM); 9023 9024 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 9025 9026 t4_tp_read_la(sc, buf, NULL); 9027 p = buf; 9028 9029 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 9030 case 2: 9031 inc = 2; 9032 show_func = tp_la_show2; 9033 break; 9034 case 3: 9035 inc = 2; 9036 show_func = tp_la_show3; 9037 break; 9038 default: 9039 inc = 1; 9040 show_func = tp_la_show; 9041 } 9042 9043 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 9044 (*show_func)(sb, p, i); 9045 9046 rc = sbuf_finish(sb); 9047 sbuf_delete(sb); 9048 free(buf, M_CXGBE); 9049 return (rc); 9050 } 9051 9052 static int 9053 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 9054 { 9055 struct adapter *sc = arg1; 9056 struct sbuf *sb; 9057 int rc; 9058 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 9059 9060 rc = sysctl_wire_old_buffer(req, 0); 9061 if (rc != 0) 9062 return (rc); 9063 9064 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9065 if (sb == NULL) 9066 return (ENOMEM); 9067 9068 t4_get_chan_txrate(sc, nrate, orate); 9069 9070 if (sc->chip_params->nchan > 2) { 9071 sbuf_printf(sb, " channel 0 channel 1" 9072 " channel 2 channel 3\n"); 9073 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 9074 nrate[0], nrate[1], nrate[2], nrate[3]); 9075 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 9076 orate[0], orate[1], orate[2], orate[3]); 9077 } else { 9078 sbuf_printf(sb, " channel 0 channel 1\n"); 9079 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 9080 nrate[0], nrate[1]); 9081 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 9082 orate[0], orate[1]); 9083 } 9084 9085 rc = sbuf_finish(sb); 9086 sbuf_delete(sb); 9087 9088 return (rc); 9089 } 9090 9091 static int 9092 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 9093 { 9094 struct adapter *sc = arg1; 9095 struct sbuf *sb; 9096 uint32_t *buf, *p; 9097 int rc, i; 9098 9099 rc = sysctl_wire_old_buffer(req, 0); 9100 if (rc != 0) 9101 return (rc); 9102 9103 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9104 if (sb == NULL) 9105 return (ENOMEM); 9106 9107 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 9108 M_ZERO | M_WAITOK); 9109 9110 t4_ulprx_read_la(sc, buf); 9111 p = buf; 9112 9113 sbuf_printf(sb, " Pcmd Type Message" 9114 " Data"); 9115 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 9116 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 9117 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 9118 } 9119 9120 rc = sbuf_finish(sb); 9121 sbuf_delete(sb); 9122 free(buf, M_CXGBE); 9123 return (rc); 9124 } 9125 9126 static int 9127 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 9128 { 9129 struct adapter *sc = arg1; 9130 struct sbuf *sb; 9131 int rc, v; 9132 9133 MPASS(chip_id(sc) >= CHELSIO_T5); 9134 9135 rc = sysctl_wire_old_buffer(req, 0); 9136 if (rc != 0) 9137 return (rc); 9138 9139 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9140 if (sb == NULL) 9141 return (ENOMEM); 9142 9143 v = t4_read_reg(sc, A_SGE_STAT_CFG); 9144 if (G_STATSOURCE_T5(v) == 7) { 9145 int mode; 9146 9147 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 9148 if (mode == 0) { 9149 sbuf_printf(sb, "total %d, incomplete %d", 9150 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9151 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9152 } else if (mode == 1) { 9153 sbuf_printf(sb, "total %d, data overflow %d", 9154 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9155 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9156 } else { 9157 sbuf_printf(sb, "unknown mode %d", mode); 9158 } 9159 } 9160 rc = sbuf_finish(sb); 9161 sbuf_delete(sb); 9162 9163 return (rc); 9164 } 9165 9166 static int 9167 sysctl_cpus(SYSCTL_HANDLER_ARGS) 9168 { 9169 struct adapter *sc = arg1; 9170 enum cpu_sets op = arg2; 9171 cpuset_t cpuset; 9172 struct sbuf *sb; 9173 int i, rc; 9174 9175 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 9176 9177 CPU_ZERO(&cpuset); 9178 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 9179 if (rc != 0) 9180 return (rc); 9181 9182 rc = sysctl_wire_old_buffer(req, 0); 9183 if (rc != 0) 9184 return (rc); 9185 9186 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9187 if (sb == NULL) 9188 return (ENOMEM); 9189 9190 CPU_FOREACH(i) 9191 sbuf_printf(sb, "%d ", i); 9192 rc = sbuf_finish(sb); 9193 sbuf_delete(sb); 9194 9195 return (rc); 9196 } 9197 9198 #ifdef TCP_OFFLOAD 9199 static int 9200 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 9201 { 9202 struct adapter *sc = arg1; 9203 int *old_ports, *new_ports; 9204 int i, new_count, rc; 9205 9206 if (req->newptr == NULL && req->oldptr == NULL) 9207 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 9208 sizeof(sc->tt.tls_rx_ports[0]))); 9209 9210 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 9211 if (rc) 9212 return (rc); 9213 9214 if (sc->tt.num_tls_rx_ports == 0) { 9215 i = -1; 9216 rc = SYSCTL_OUT(req, &i, sizeof(i)); 9217 } else 9218 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 9219 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 9220 if (rc == 0 && req->newptr != NULL) { 9221 new_count = req->newlen / sizeof(new_ports[0]); 9222 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 9223 M_WAITOK); 9224 rc = SYSCTL_IN(req, new_ports, new_count * 9225 sizeof(new_ports[0])); 9226 if (rc) 9227 goto err; 9228 9229 /* Allow setting to a single '-1' to clear the list. */ 9230 if (new_count == 1 && new_ports[0] == -1) { 9231 ADAPTER_LOCK(sc); 9232 old_ports = sc->tt.tls_rx_ports; 9233 sc->tt.tls_rx_ports = NULL; 9234 sc->tt.num_tls_rx_ports = 0; 9235 ADAPTER_UNLOCK(sc); 9236 free(old_ports, M_CXGBE); 9237 } else { 9238 for (i = 0; i < new_count; i++) { 9239 if (new_ports[i] < 1 || 9240 new_ports[i] > IPPORT_MAX) { 9241 rc = EINVAL; 9242 goto err; 9243 } 9244 } 9245 9246 ADAPTER_LOCK(sc); 9247 old_ports = sc->tt.tls_rx_ports; 9248 sc->tt.tls_rx_ports = new_ports; 9249 sc->tt.num_tls_rx_ports = new_count; 9250 ADAPTER_UNLOCK(sc); 9251 free(old_ports, M_CXGBE); 9252 new_ports = NULL; 9253 } 9254 err: 9255 free(new_ports, M_CXGBE); 9256 } 9257 end_synchronized_op(sc, 0); 9258 return (rc); 9259 } 9260 9261 static void 9262 unit_conv(char *buf, size_t len, u_int val, u_int factor) 9263 { 9264 u_int rem = val % factor; 9265 9266 if (rem == 0) 9267 snprintf(buf, len, "%u", val / factor); 9268 else { 9269 while (rem % 10 == 0) 9270 rem /= 10; 9271 snprintf(buf, len, "%u.%u", val / factor, rem); 9272 } 9273 } 9274 9275 static int 9276 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 9277 { 9278 struct adapter *sc = arg1; 9279 char buf[16]; 9280 u_int res, re; 9281 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9282 9283 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9284 switch (arg2) { 9285 case 0: 9286 /* timer_tick */ 9287 re = G_TIMERRESOLUTION(res); 9288 break; 9289 case 1: 9290 /* TCP timestamp tick */ 9291 re = G_TIMESTAMPRESOLUTION(res); 9292 break; 9293 case 2: 9294 /* DACK tick */ 9295 re = G_DELAYEDACKRESOLUTION(res); 9296 break; 9297 default: 9298 return (EDOOFUS); 9299 } 9300 9301 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 9302 9303 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 9304 } 9305 9306 static int 9307 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 9308 { 9309 struct adapter *sc = arg1; 9310 u_int res, dack_re, v; 9311 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9312 9313 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9314 dack_re = G_DELAYEDACKRESOLUTION(res); 9315 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 9316 9317 return (sysctl_handle_int(oidp, &v, 0, req)); 9318 } 9319 9320 static int 9321 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 9322 { 9323 struct adapter *sc = arg1; 9324 int reg = arg2; 9325 u_int tre; 9326 u_long tp_tick_us, v; 9327 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9328 9329 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 9330 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 9331 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 9332 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 9333 9334 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 9335 tp_tick_us = (cclk_ps << tre) / 1000000; 9336 9337 if (reg == A_TP_INIT_SRTT) 9338 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 9339 else 9340 v = tp_tick_us * t4_read_reg(sc, reg); 9341 9342 return (sysctl_handle_long(oidp, &v, 0, req)); 9343 } 9344 9345 /* 9346 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 9347 * passed to this function. 9348 */ 9349 static int 9350 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 9351 { 9352 struct adapter *sc = arg1; 9353 int idx = arg2; 9354 u_int v; 9355 9356 MPASS(idx >= 0 && idx <= 24); 9357 9358 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 9359 9360 return (sysctl_handle_int(oidp, &v, 0, req)); 9361 } 9362 9363 static int 9364 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 9365 { 9366 struct adapter *sc = arg1; 9367 int idx = arg2; 9368 u_int shift, v, r; 9369 9370 MPASS(idx >= 0 && idx < 16); 9371 9372 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 9373 shift = (idx & 3) << 3; 9374 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 9375 9376 return (sysctl_handle_int(oidp, &v, 0, req)); 9377 } 9378 9379 static int 9380 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 9381 { 9382 struct vi_info *vi = arg1; 9383 struct adapter *sc = vi->pi->adapter; 9384 int idx, rc, i; 9385 struct sge_ofld_rxq *ofld_rxq; 9386 uint8_t v; 9387 9388 idx = vi->ofld_tmr_idx; 9389 9390 rc = sysctl_handle_int(oidp, &idx, 0, req); 9391 if (rc != 0 || req->newptr == NULL) 9392 return (rc); 9393 9394 if (idx < 0 || idx >= SGE_NTIMERS) 9395 return (EINVAL); 9396 9397 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9398 "t4otmr"); 9399 if (rc) 9400 return (rc); 9401 9402 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 9403 for_each_ofld_rxq(vi, i, ofld_rxq) { 9404 #ifdef atomic_store_rel_8 9405 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 9406 #else 9407 ofld_rxq->iq.intr_params = v; 9408 #endif 9409 } 9410 vi->ofld_tmr_idx = idx; 9411 9412 end_synchronized_op(sc, LOCK_HELD); 9413 return (0); 9414 } 9415 9416 static int 9417 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 9418 { 9419 struct vi_info *vi = arg1; 9420 struct adapter *sc = vi->pi->adapter; 9421 int idx, rc; 9422 9423 idx = vi->ofld_pktc_idx; 9424 9425 rc = sysctl_handle_int(oidp, &idx, 0, req); 9426 if (rc != 0 || req->newptr == NULL) 9427 return (rc); 9428 9429 if (idx < -1 || idx >= SGE_NCOUNTERS) 9430 return (EINVAL); 9431 9432 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9433 "t4opktc"); 9434 if (rc) 9435 return (rc); 9436 9437 if (vi->flags & VI_INIT_DONE) 9438 rc = EBUSY; /* cannot be changed once the queues are created */ 9439 else 9440 vi->ofld_pktc_idx = idx; 9441 9442 end_synchronized_op(sc, LOCK_HELD); 9443 return (rc); 9444 } 9445 #endif 9446 9447 static int 9448 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 9449 { 9450 int rc; 9451 9452 if (cntxt->cid > M_CTXTQID) 9453 return (EINVAL); 9454 9455 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 9456 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 9457 return (EINVAL); 9458 9459 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 9460 if (rc) 9461 return (rc); 9462 9463 if (sc->flags & FW_OK) { 9464 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 9465 &cntxt->data[0]); 9466 if (rc == 0) 9467 goto done; 9468 } 9469 9470 /* 9471 * Read via firmware failed or wasn't even attempted. Read directly via 9472 * the backdoor. 9473 */ 9474 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 9475 done: 9476 end_synchronized_op(sc, 0); 9477 return (rc); 9478 } 9479 9480 static int 9481 load_fw(struct adapter *sc, struct t4_data *fw) 9482 { 9483 int rc; 9484 uint8_t *fw_data; 9485 9486 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 9487 if (rc) 9488 return (rc); 9489 9490 /* 9491 * The firmware, with the sole exception of the memory parity error 9492 * handler, runs from memory and not flash. It is almost always safe to 9493 * install a new firmware on a running system. Just set bit 1 in 9494 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 9495 */ 9496 if (sc->flags & FULL_INIT_DONE && 9497 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 9498 rc = EBUSY; 9499 goto done; 9500 } 9501 9502 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9503 if (fw_data == NULL) { 9504 rc = ENOMEM; 9505 goto done; 9506 } 9507 9508 rc = copyin(fw->data, fw_data, fw->len); 9509 if (rc == 0) 9510 rc = -t4_load_fw(sc, fw_data, fw->len); 9511 9512 free(fw_data, M_CXGBE); 9513 done: 9514 end_synchronized_op(sc, 0); 9515 return (rc); 9516 } 9517 9518 static int 9519 load_cfg(struct adapter *sc, struct t4_data *cfg) 9520 { 9521 int rc; 9522 uint8_t *cfg_data = NULL; 9523 9524 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9525 if (rc) 9526 return (rc); 9527 9528 if (cfg->len == 0) { 9529 /* clear */ 9530 rc = -t4_load_cfg(sc, NULL, 0); 9531 goto done; 9532 } 9533 9534 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9535 if (cfg_data == NULL) { 9536 rc = ENOMEM; 9537 goto done; 9538 } 9539 9540 rc = copyin(cfg->data, cfg_data, cfg->len); 9541 if (rc == 0) 9542 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9543 9544 free(cfg_data, M_CXGBE); 9545 done: 9546 end_synchronized_op(sc, 0); 9547 return (rc); 9548 } 9549 9550 static int 9551 load_boot(struct adapter *sc, struct t4_bootrom *br) 9552 { 9553 int rc; 9554 uint8_t *br_data = NULL; 9555 u_int offset; 9556 9557 if (br->len > 1024 * 1024) 9558 return (EFBIG); 9559 9560 if (br->pf_offset == 0) { 9561 /* pfidx */ 9562 if (br->pfidx_addr > 7) 9563 return (EINVAL); 9564 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9565 A_PCIE_PF_EXPROM_OFST))); 9566 } else if (br->pf_offset == 1) { 9567 /* offset */ 9568 offset = G_OFFSET(br->pfidx_addr); 9569 } else { 9570 return (EINVAL); 9571 } 9572 9573 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9574 if (rc) 9575 return (rc); 9576 9577 if (br->len == 0) { 9578 /* clear */ 9579 rc = -t4_load_boot(sc, NULL, offset, 0); 9580 goto done; 9581 } 9582 9583 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9584 if (br_data == NULL) { 9585 rc = ENOMEM; 9586 goto done; 9587 } 9588 9589 rc = copyin(br->data, br_data, br->len); 9590 if (rc == 0) 9591 rc = -t4_load_boot(sc, br_data, offset, br->len); 9592 9593 free(br_data, M_CXGBE); 9594 done: 9595 end_synchronized_op(sc, 0); 9596 return (rc); 9597 } 9598 9599 static int 9600 load_bootcfg(struct adapter *sc, struct t4_data *bc) 9601 { 9602 int rc; 9603 uint8_t *bc_data = NULL; 9604 9605 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9606 if (rc) 9607 return (rc); 9608 9609 if (bc->len == 0) { 9610 /* clear */ 9611 rc = -t4_load_bootcfg(sc, NULL, 0); 9612 goto done; 9613 } 9614 9615 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9616 if (bc_data == NULL) { 9617 rc = ENOMEM; 9618 goto done; 9619 } 9620 9621 rc = copyin(bc->data, bc_data, bc->len); 9622 if (rc == 0) 9623 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9624 9625 free(bc_data, M_CXGBE); 9626 done: 9627 end_synchronized_op(sc, 0); 9628 return (rc); 9629 } 9630 9631 static int 9632 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9633 { 9634 int rc; 9635 struct cudbg_init *cudbg; 9636 void *handle, *buf; 9637 9638 /* buf is large, don't block if no memory is available */ 9639 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9640 if (buf == NULL) 9641 return (ENOMEM); 9642 9643 handle = cudbg_alloc_handle(); 9644 if (handle == NULL) { 9645 rc = ENOMEM; 9646 goto done; 9647 } 9648 9649 cudbg = cudbg_get_init(handle); 9650 cudbg->adap = sc; 9651 cudbg->print = (cudbg_print_cb)printf; 9652 9653 #ifndef notyet 9654 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9655 __func__, dump->wr_flash, dump->len, dump->data); 9656 #endif 9657 9658 if (dump->wr_flash) 9659 cudbg->use_flash = 1; 9660 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9661 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9662 9663 rc = cudbg_collect(handle, buf, &dump->len); 9664 if (rc != 0) 9665 goto done; 9666 9667 rc = copyout(buf, dump->data, dump->len); 9668 done: 9669 cudbg_free_handle(handle); 9670 free(buf, M_CXGBE); 9671 return (rc); 9672 } 9673 9674 static void 9675 free_offload_policy(struct t4_offload_policy *op) 9676 { 9677 struct offload_rule *r; 9678 int i; 9679 9680 if (op == NULL) 9681 return; 9682 9683 r = &op->rule[0]; 9684 for (i = 0; i < op->nrules; i++, r++) { 9685 free(r->bpf_prog.bf_insns, M_CXGBE); 9686 } 9687 free(op->rule, M_CXGBE); 9688 free(op, M_CXGBE); 9689 } 9690 9691 static int 9692 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 9693 { 9694 int i, rc, len; 9695 struct t4_offload_policy *op, *old; 9696 struct bpf_program *bf; 9697 const struct offload_settings *s; 9698 struct offload_rule *r; 9699 void *u; 9700 9701 if (!is_offload(sc)) 9702 return (ENODEV); 9703 9704 if (uop->nrules == 0) { 9705 /* Delete installed policies. */ 9706 op = NULL; 9707 goto set_policy; 9708 } if (uop->nrules > 256) { /* arbitrary */ 9709 return (E2BIG); 9710 } 9711 9712 /* Copy userspace offload policy to kernel */ 9713 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 9714 op->nrules = uop->nrules; 9715 len = op->nrules * sizeof(struct offload_rule); 9716 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9717 rc = copyin(uop->rule, op->rule, len); 9718 if (rc) { 9719 free(op->rule, M_CXGBE); 9720 free(op, M_CXGBE); 9721 return (rc); 9722 } 9723 9724 r = &op->rule[0]; 9725 for (i = 0; i < op->nrules; i++, r++) { 9726 9727 /* Validate open_type */ 9728 if (r->open_type != OPEN_TYPE_LISTEN && 9729 r->open_type != OPEN_TYPE_ACTIVE && 9730 r->open_type != OPEN_TYPE_PASSIVE && 9731 r->open_type != OPEN_TYPE_DONTCARE) { 9732 error: 9733 /* 9734 * Rules 0 to i have malloc'd filters that need to be 9735 * freed. Rules i+1 to nrules have userspace pointers 9736 * and should be left alone. 9737 */ 9738 op->nrules = i; 9739 free_offload_policy(op); 9740 return (rc); 9741 } 9742 9743 /* Validate settings */ 9744 s = &r->settings; 9745 if ((s->offload != 0 && s->offload != 1) || 9746 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9747 s->sched_class < -1 || 9748 s->sched_class >= sc->chip_params->nsched_cls) { 9749 rc = EINVAL; 9750 goto error; 9751 } 9752 9753 bf = &r->bpf_prog; 9754 u = bf->bf_insns; /* userspace ptr */ 9755 bf->bf_insns = NULL; 9756 if (bf->bf_len == 0) { 9757 /* legal, matches everything */ 9758 continue; 9759 } 9760 len = bf->bf_len * sizeof(*bf->bf_insns); 9761 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9762 rc = copyin(u, bf->bf_insns, len); 9763 if (rc != 0) 9764 goto error; 9765 9766 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9767 rc = EINVAL; 9768 goto error; 9769 } 9770 } 9771 set_policy: 9772 rw_wlock(&sc->policy_lock); 9773 old = sc->policy; 9774 sc->policy = op; 9775 rw_wunlock(&sc->policy_lock); 9776 free_offload_policy(old); 9777 9778 return (0); 9779 } 9780 9781 #define MAX_READ_BUF_SIZE (128 * 1024) 9782 static int 9783 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9784 { 9785 uint32_t addr, remaining, n; 9786 uint32_t *buf; 9787 int rc; 9788 uint8_t *dst; 9789 9790 rc = validate_mem_range(sc, mr->addr, mr->len); 9791 if (rc != 0) 9792 return (rc); 9793 9794 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9795 addr = mr->addr; 9796 remaining = mr->len; 9797 dst = (void *)mr->data; 9798 9799 while (remaining) { 9800 n = min(remaining, MAX_READ_BUF_SIZE); 9801 read_via_memwin(sc, 2, addr, buf, n); 9802 9803 rc = copyout(buf, dst, n); 9804 if (rc != 0) 9805 break; 9806 9807 dst += n; 9808 remaining -= n; 9809 addr += n; 9810 } 9811 9812 free(buf, M_CXGBE); 9813 return (rc); 9814 } 9815 #undef MAX_READ_BUF_SIZE 9816 9817 static int 9818 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9819 { 9820 int rc; 9821 9822 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9823 return (EINVAL); 9824 9825 if (i2cd->len > sizeof(i2cd->data)) 9826 return (EFBIG); 9827 9828 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9829 if (rc) 9830 return (rc); 9831 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9832 i2cd->offset, i2cd->len, &i2cd->data[0]); 9833 end_synchronized_op(sc, 0); 9834 9835 return (rc); 9836 } 9837 9838 int 9839 t4_os_find_pci_capability(struct adapter *sc, int cap) 9840 { 9841 int i; 9842 9843 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9844 } 9845 9846 int 9847 t4_os_pci_save_state(struct adapter *sc) 9848 { 9849 device_t dev; 9850 struct pci_devinfo *dinfo; 9851 9852 dev = sc->dev; 9853 dinfo = device_get_ivars(dev); 9854 9855 pci_cfg_save(dev, dinfo, 0); 9856 return (0); 9857 } 9858 9859 int 9860 t4_os_pci_restore_state(struct adapter *sc) 9861 { 9862 device_t dev; 9863 struct pci_devinfo *dinfo; 9864 9865 dev = sc->dev; 9866 dinfo = device_get_ivars(dev); 9867 9868 pci_cfg_restore(dev, dinfo); 9869 return (0); 9870 } 9871 9872 void 9873 t4_os_portmod_changed(struct port_info *pi) 9874 { 9875 struct adapter *sc = pi->adapter; 9876 struct vi_info *vi; 9877 struct ifnet *ifp; 9878 static const char *mod_str[] = { 9879 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9880 }; 9881 9882 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 9883 ("%s: port_type %u", __func__, pi->port_type)); 9884 9885 vi = &pi->vi[0]; 9886 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9887 PORT_LOCK(pi); 9888 build_medialist(pi); 9889 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 9890 fixup_link_config(pi); 9891 apply_link_config(pi); 9892 } 9893 PORT_UNLOCK(pi); 9894 end_synchronized_op(sc, LOCK_HELD); 9895 } 9896 9897 ifp = vi->ifp; 9898 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9899 if_printf(ifp, "transceiver unplugged.\n"); 9900 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9901 if_printf(ifp, "unknown transceiver inserted.\n"); 9902 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9903 if_printf(ifp, "unsupported transceiver inserted.\n"); 9904 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9905 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9906 port_top_speed(pi), mod_str[pi->mod_type]); 9907 } else { 9908 if_printf(ifp, "transceiver (type %d) inserted.\n", 9909 pi->mod_type); 9910 } 9911 } 9912 9913 void 9914 t4_os_link_changed(struct port_info *pi) 9915 { 9916 struct vi_info *vi; 9917 struct ifnet *ifp; 9918 struct link_config *lc; 9919 int v; 9920 9921 PORT_LOCK_ASSERT_OWNED(pi); 9922 9923 for_each_vi(pi, v, vi) { 9924 ifp = vi->ifp; 9925 if (ifp == NULL) 9926 continue; 9927 9928 lc = &pi->link_cfg; 9929 if (lc->link_ok) { 9930 ifp->if_baudrate = IF_Mbps(lc->speed); 9931 if_link_state_change(ifp, LINK_STATE_UP); 9932 } else { 9933 if_link_state_change(ifp, LINK_STATE_DOWN); 9934 } 9935 } 9936 } 9937 9938 void 9939 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9940 { 9941 struct adapter *sc; 9942 9943 sx_slock(&t4_list_lock); 9944 SLIST_FOREACH(sc, &t4_list, link) { 9945 /* 9946 * func should not make any assumptions about what state sc is 9947 * in - the only guarantee is that sc->sc_lock is a valid lock. 9948 */ 9949 func(sc, arg); 9950 } 9951 sx_sunlock(&t4_list_lock); 9952 } 9953 9954 static int 9955 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9956 struct thread *td) 9957 { 9958 int rc; 9959 struct adapter *sc = dev->si_drv1; 9960 9961 rc = priv_check(td, PRIV_DRIVER); 9962 if (rc != 0) 9963 return (rc); 9964 9965 switch (cmd) { 9966 case CHELSIO_T4_GETREG: { 9967 struct t4_reg *edata = (struct t4_reg *)data; 9968 9969 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9970 return (EFAULT); 9971 9972 if (edata->size == 4) 9973 edata->val = t4_read_reg(sc, edata->addr); 9974 else if (edata->size == 8) 9975 edata->val = t4_read_reg64(sc, edata->addr); 9976 else 9977 return (EINVAL); 9978 9979 break; 9980 } 9981 case CHELSIO_T4_SETREG: { 9982 struct t4_reg *edata = (struct t4_reg *)data; 9983 9984 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9985 return (EFAULT); 9986 9987 if (edata->size == 4) { 9988 if (edata->val & 0xffffffff00000000) 9989 return (EINVAL); 9990 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9991 } else if (edata->size == 8) 9992 t4_write_reg64(sc, edata->addr, edata->val); 9993 else 9994 return (EINVAL); 9995 break; 9996 } 9997 case CHELSIO_T4_REGDUMP: { 9998 struct t4_regdump *regs = (struct t4_regdump *)data; 9999 int reglen = t4_get_regs_len(sc); 10000 uint8_t *buf; 10001 10002 if (regs->len < reglen) { 10003 regs->len = reglen; /* hint to the caller */ 10004 return (ENOBUFS); 10005 } 10006 10007 regs->len = reglen; 10008 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 10009 get_regs(sc, regs, buf); 10010 rc = copyout(buf, regs->data, reglen); 10011 free(buf, M_CXGBE); 10012 break; 10013 } 10014 case CHELSIO_T4_GET_FILTER_MODE: 10015 rc = get_filter_mode(sc, (uint32_t *)data); 10016 break; 10017 case CHELSIO_T4_SET_FILTER_MODE: 10018 rc = set_filter_mode(sc, *(uint32_t *)data); 10019 break; 10020 case CHELSIO_T4_GET_FILTER: 10021 rc = get_filter(sc, (struct t4_filter *)data); 10022 break; 10023 case CHELSIO_T4_SET_FILTER: 10024 rc = set_filter(sc, (struct t4_filter *)data); 10025 break; 10026 case CHELSIO_T4_DEL_FILTER: 10027 rc = del_filter(sc, (struct t4_filter *)data); 10028 break; 10029 case CHELSIO_T4_GET_SGE_CONTEXT: 10030 rc = get_sge_context(sc, (struct t4_sge_context *)data); 10031 break; 10032 case CHELSIO_T4_LOAD_FW: 10033 rc = load_fw(sc, (struct t4_data *)data); 10034 break; 10035 case CHELSIO_T4_GET_MEM: 10036 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 10037 break; 10038 case CHELSIO_T4_GET_I2C: 10039 rc = read_i2c(sc, (struct t4_i2c_data *)data); 10040 break; 10041 case CHELSIO_T4_CLEAR_STATS: { 10042 int i, v, bg_map; 10043 u_int port_id = *(uint32_t *)data; 10044 struct port_info *pi; 10045 struct vi_info *vi; 10046 10047 if (port_id >= sc->params.nports) 10048 return (EINVAL); 10049 pi = sc->port[port_id]; 10050 if (pi == NULL) 10051 return (EIO); 10052 10053 /* MAC stats */ 10054 t4_clr_port_stats(sc, pi->tx_chan); 10055 pi->tx_parse_error = 0; 10056 pi->tnl_cong_drops = 0; 10057 mtx_lock(&sc->reg_lock); 10058 for_each_vi(pi, v, vi) { 10059 if (vi->flags & VI_INIT_DONE) 10060 t4_clr_vi_stats(sc, vi->vin); 10061 } 10062 bg_map = pi->mps_bg_map; 10063 v = 0; /* reuse */ 10064 while (bg_map) { 10065 i = ffs(bg_map) - 1; 10066 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 10067 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 10068 bg_map &= ~(1 << i); 10069 } 10070 mtx_unlock(&sc->reg_lock); 10071 10072 /* 10073 * Since this command accepts a port, clear stats for 10074 * all VIs on this port. 10075 */ 10076 for_each_vi(pi, v, vi) { 10077 if (vi->flags & VI_INIT_DONE) { 10078 struct sge_rxq *rxq; 10079 struct sge_txq *txq; 10080 struct sge_wrq *wrq; 10081 10082 for_each_rxq(vi, i, rxq) { 10083 #if defined(INET) || defined(INET6) 10084 rxq->lro.lro_queued = 0; 10085 rxq->lro.lro_flushed = 0; 10086 #endif 10087 rxq->rxcsum = 0; 10088 rxq->vlan_extraction = 0; 10089 } 10090 10091 for_each_txq(vi, i, txq) { 10092 txq->txcsum = 0; 10093 txq->tso_wrs = 0; 10094 txq->vlan_insertion = 0; 10095 txq->imm_wrs = 0; 10096 txq->sgl_wrs = 0; 10097 txq->txpkt_wrs = 0; 10098 txq->txpkts0_wrs = 0; 10099 txq->txpkts1_wrs = 0; 10100 txq->txpkts0_pkts = 0; 10101 txq->txpkts1_pkts = 0; 10102 txq->raw_wrs = 0; 10103 mp_ring_reset_stats(txq->r); 10104 } 10105 10106 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10107 /* nothing to clear for each ofld_rxq */ 10108 10109 for_each_ofld_txq(vi, i, wrq) { 10110 wrq->tx_wrs_direct = 0; 10111 wrq->tx_wrs_copied = 0; 10112 } 10113 #endif 10114 10115 if (IS_MAIN_VI(vi)) { 10116 wrq = &sc->sge.ctrlq[pi->port_id]; 10117 wrq->tx_wrs_direct = 0; 10118 wrq->tx_wrs_copied = 0; 10119 } 10120 } 10121 } 10122 break; 10123 } 10124 case CHELSIO_T4_SCHED_CLASS: 10125 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 10126 break; 10127 case CHELSIO_T4_SCHED_QUEUE: 10128 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 10129 break; 10130 case CHELSIO_T4_GET_TRACER: 10131 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 10132 break; 10133 case CHELSIO_T4_SET_TRACER: 10134 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 10135 break; 10136 case CHELSIO_T4_LOAD_CFG: 10137 rc = load_cfg(sc, (struct t4_data *)data); 10138 break; 10139 case CHELSIO_T4_LOAD_BOOT: 10140 rc = load_boot(sc, (struct t4_bootrom *)data); 10141 break; 10142 case CHELSIO_T4_LOAD_BOOTCFG: 10143 rc = load_bootcfg(sc, (struct t4_data *)data); 10144 break; 10145 case CHELSIO_T4_CUDBG_DUMP: 10146 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 10147 break; 10148 case CHELSIO_T4_SET_OFLD_POLICY: 10149 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 10150 break; 10151 default: 10152 rc = ENOTTY; 10153 } 10154 10155 return (rc); 10156 } 10157 10158 #ifdef TCP_OFFLOAD 10159 static int 10160 toe_capability(struct vi_info *vi, int enable) 10161 { 10162 int rc; 10163 struct port_info *pi = vi->pi; 10164 struct adapter *sc = pi->adapter; 10165 10166 ASSERT_SYNCHRONIZED_OP(sc); 10167 10168 if (!is_offload(sc)) 10169 return (ENODEV); 10170 10171 if (enable) { 10172 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 10173 /* TOE is already enabled. */ 10174 return (0); 10175 } 10176 10177 /* 10178 * We need the port's queues around so that we're able to send 10179 * and receive CPLs to/from the TOE even if the ifnet for this 10180 * port has never been UP'd administratively. 10181 */ 10182 if (!(vi->flags & VI_INIT_DONE)) { 10183 rc = vi_full_init(vi); 10184 if (rc) 10185 return (rc); 10186 } 10187 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 10188 rc = vi_full_init(&pi->vi[0]); 10189 if (rc) 10190 return (rc); 10191 } 10192 10193 if (isset(&sc->offload_map, pi->port_id)) { 10194 /* TOE is enabled on another VI of this port. */ 10195 pi->uld_vis++; 10196 return (0); 10197 } 10198 10199 if (!uld_active(sc, ULD_TOM)) { 10200 rc = t4_activate_uld(sc, ULD_TOM); 10201 if (rc == EAGAIN) { 10202 log(LOG_WARNING, 10203 "You must kldload t4_tom.ko before trying " 10204 "to enable TOE on a cxgbe interface.\n"); 10205 } 10206 if (rc != 0) 10207 return (rc); 10208 KASSERT(sc->tom_softc != NULL, 10209 ("%s: TOM activated but softc NULL", __func__)); 10210 KASSERT(uld_active(sc, ULD_TOM), 10211 ("%s: TOM activated but flag not set", __func__)); 10212 } 10213 10214 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 10215 if (!uld_active(sc, ULD_IWARP)) 10216 (void) t4_activate_uld(sc, ULD_IWARP); 10217 if (!uld_active(sc, ULD_ISCSI)) 10218 (void) t4_activate_uld(sc, ULD_ISCSI); 10219 10220 pi->uld_vis++; 10221 setbit(&sc->offload_map, pi->port_id); 10222 } else { 10223 pi->uld_vis--; 10224 10225 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 10226 return (0); 10227 10228 KASSERT(uld_active(sc, ULD_TOM), 10229 ("%s: TOM never initialized?", __func__)); 10230 clrbit(&sc->offload_map, pi->port_id); 10231 } 10232 10233 return (0); 10234 } 10235 10236 /* 10237 * Add an upper layer driver to the global list. 10238 */ 10239 int 10240 t4_register_uld(struct uld_info *ui) 10241 { 10242 int rc = 0; 10243 struct uld_info *u; 10244 10245 sx_xlock(&t4_uld_list_lock); 10246 SLIST_FOREACH(u, &t4_uld_list, link) { 10247 if (u->uld_id == ui->uld_id) { 10248 rc = EEXIST; 10249 goto done; 10250 } 10251 } 10252 10253 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 10254 ui->refcount = 0; 10255 done: 10256 sx_xunlock(&t4_uld_list_lock); 10257 return (rc); 10258 } 10259 10260 int 10261 t4_unregister_uld(struct uld_info *ui) 10262 { 10263 int rc = EINVAL; 10264 struct uld_info *u; 10265 10266 sx_xlock(&t4_uld_list_lock); 10267 10268 SLIST_FOREACH(u, &t4_uld_list, link) { 10269 if (u == ui) { 10270 if (ui->refcount > 0) { 10271 rc = EBUSY; 10272 goto done; 10273 } 10274 10275 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 10276 rc = 0; 10277 goto done; 10278 } 10279 } 10280 done: 10281 sx_xunlock(&t4_uld_list_lock); 10282 return (rc); 10283 } 10284 10285 int 10286 t4_activate_uld(struct adapter *sc, int id) 10287 { 10288 int rc; 10289 struct uld_info *ui; 10290 10291 ASSERT_SYNCHRONIZED_OP(sc); 10292 10293 if (id < 0 || id > ULD_MAX) 10294 return (EINVAL); 10295 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 10296 10297 sx_slock(&t4_uld_list_lock); 10298 10299 SLIST_FOREACH(ui, &t4_uld_list, link) { 10300 if (ui->uld_id == id) { 10301 if (!(sc->flags & FULL_INIT_DONE)) { 10302 rc = adapter_full_init(sc); 10303 if (rc != 0) 10304 break; 10305 } 10306 10307 rc = ui->activate(sc); 10308 if (rc == 0) { 10309 setbit(&sc->active_ulds, id); 10310 ui->refcount++; 10311 } 10312 break; 10313 } 10314 } 10315 10316 sx_sunlock(&t4_uld_list_lock); 10317 10318 return (rc); 10319 } 10320 10321 int 10322 t4_deactivate_uld(struct adapter *sc, int id) 10323 { 10324 int rc; 10325 struct uld_info *ui; 10326 10327 ASSERT_SYNCHRONIZED_OP(sc); 10328 10329 if (id < 0 || id > ULD_MAX) 10330 return (EINVAL); 10331 rc = ENXIO; 10332 10333 sx_slock(&t4_uld_list_lock); 10334 10335 SLIST_FOREACH(ui, &t4_uld_list, link) { 10336 if (ui->uld_id == id) { 10337 rc = ui->deactivate(sc); 10338 if (rc == 0) { 10339 clrbit(&sc->active_ulds, id); 10340 ui->refcount--; 10341 } 10342 break; 10343 } 10344 } 10345 10346 sx_sunlock(&t4_uld_list_lock); 10347 10348 return (rc); 10349 } 10350 10351 int 10352 uld_active(struct adapter *sc, int uld_id) 10353 { 10354 10355 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 10356 10357 return (isset(&sc->active_ulds, uld_id)); 10358 } 10359 #endif 10360 10361 /* 10362 * t = ptr to tunable. 10363 * nc = number of CPUs. 10364 * c = compiled in default for that tunable. 10365 */ 10366 static void 10367 calculate_nqueues(int *t, int nc, const int c) 10368 { 10369 int nq; 10370 10371 if (*t > 0) 10372 return; 10373 nq = *t < 0 ? -*t : c; 10374 *t = min(nc, nq); 10375 } 10376 10377 /* 10378 * Come up with reasonable defaults for some of the tunables, provided they're 10379 * not set by the user (in which case we'll use the values as is). 10380 */ 10381 static void 10382 tweak_tunables(void) 10383 { 10384 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 10385 10386 if (t4_ntxq < 1) { 10387 #ifdef RSS 10388 t4_ntxq = rss_getnumbuckets(); 10389 #else 10390 calculate_nqueues(&t4_ntxq, nc, NTXQ); 10391 #endif 10392 } 10393 10394 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 10395 10396 if (t4_nrxq < 1) { 10397 #ifdef RSS 10398 t4_nrxq = rss_getnumbuckets(); 10399 #else 10400 calculate_nqueues(&t4_nrxq, nc, NRXQ); 10401 #endif 10402 } 10403 10404 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 10405 10406 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10407 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 10408 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 10409 #endif 10410 #ifdef TCP_OFFLOAD 10411 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 10412 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 10413 10414 if (t4_toecaps_allowed == -1) 10415 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 10416 10417 if (t4_rdmacaps_allowed == -1) { 10418 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 10419 FW_CAPS_CONFIG_RDMA_RDMAC; 10420 } 10421 10422 if (t4_iscsicaps_allowed == -1) { 10423 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 10424 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 10425 FW_CAPS_CONFIG_ISCSI_T10DIF; 10426 } 10427 10428 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 10429 t4_tmr_idx_ofld = TMR_IDX_OFLD; 10430 10431 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 10432 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 10433 #else 10434 if (t4_toecaps_allowed == -1) 10435 t4_toecaps_allowed = 0; 10436 10437 if (t4_rdmacaps_allowed == -1) 10438 t4_rdmacaps_allowed = 0; 10439 10440 if (t4_iscsicaps_allowed == -1) 10441 t4_iscsicaps_allowed = 0; 10442 #endif 10443 10444 #ifdef DEV_NETMAP 10445 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 10446 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 10447 #endif 10448 10449 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 10450 t4_tmr_idx = TMR_IDX; 10451 10452 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 10453 t4_pktc_idx = PKTC_IDX; 10454 10455 if (t4_qsize_txq < 128) 10456 t4_qsize_txq = 128; 10457 10458 if (t4_qsize_rxq < 128) 10459 t4_qsize_rxq = 128; 10460 while (t4_qsize_rxq & 7) 10461 t4_qsize_rxq++; 10462 10463 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 10464 10465 /* 10466 * Number of VIs to create per-port. The first VI is the "main" regular 10467 * VI for the port. The rest are additional virtual interfaces on the 10468 * same physical port. Note that the main VI does not have native 10469 * netmap support but the extra VIs do. 10470 * 10471 * Limit the number of VIs per port to the number of available 10472 * MAC addresses per port. 10473 */ 10474 if (t4_num_vis < 1) 10475 t4_num_vis = 1; 10476 if (t4_num_vis > nitems(vi_mac_funcs)) { 10477 t4_num_vis = nitems(vi_mac_funcs); 10478 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 10479 } 10480 10481 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 10482 pcie_relaxed_ordering = 1; 10483 #if defined(__i386__) || defined(__amd64__) 10484 if (cpu_vendor_id == CPU_VENDOR_INTEL) 10485 pcie_relaxed_ordering = 0; 10486 #endif 10487 } 10488 } 10489 10490 #ifdef DDB 10491 static void 10492 t4_dump_tcb(struct adapter *sc, int tid) 10493 { 10494 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 10495 10496 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 10497 save = t4_read_reg(sc, reg); 10498 base = sc->memwin[2].mw_base; 10499 10500 /* Dump TCB for the tid */ 10501 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 10502 tcb_addr += tid * TCB_SIZE; 10503 10504 if (is_t4(sc)) { 10505 pf = 0; 10506 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 10507 } else { 10508 pf = V_PFNUM(sc->pf); 10509 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 10510 } 10511 t4_write_reg(sc, reg, win_pos | pf); 10512 t4_read_reg(sc, reg); 10513 10514 off = tcb_addr - win_pos; 10515 for (i = 0; i < 4; i++) { 10516 uint32_t buf[8]; 10517 for (j = 0; j < 8; j++, off += 4) 10518 buf[j] = htonl(t4_read_reg(sc, base + off)); 10519 10520 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 10521 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 10522 buf[7]); 10523 } 10524 10525 t4_write_reg(sc, reg, save); 10526 t4_read_reg(sc, reg); 10527 } 10528 10529 static void 10530 t4_dump_devlog(struct adapter *sc) 10531 { 10532 struct devlog_params *dparams = &sc->params.devlog; 10533 struct fw_devlog_e e; 10534 int i, first, j, m, nentries, rc; 10535 uint64_t ftstamp = UINT64_MAX; 10536 10537 if (dparams->start == 0) { 10538 db_printf("devlog params not valid\n"); 10539 return; 10540 } 10541 10542 nentries = dparams->size / sizeof(struct fw_devlog_e); 10543 m = fwmtype_to_hwmtype(dparams->memtype); 10544 10545 /* Find the first entry. */ 10546 first = -1; 10547 for (i = 0; i < nentries && !db_pager_quit; i++) { 10548 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10549 sizeof(e), (void *)&e); 10550 if (rc != 0) 10551 break; 10552 10553 if (e.timestamp == 0) 10554 break; 10555 10556 e.timestamp = be64toh(e.timestamp); 10557 if (e.timestamp < ftstamp) { 10558 ftstamp = e.timestamp; 10559 first = i; 10560 } 10561 } 10562 10563 if (first == -1) 10564 return; 10565 10566 i = first; 10567 do { 10568 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10569 sizeof(e), (void *)&e); 10570 if (rc != 0) 10571 return; 10572 10573 if (e.timestamp == 0) 10574 return; 10575 10576 e.timestamp = be64toh(e.timestamp); 10577 e.seqno = be32toh(e.seqno); 10578 for (j = 0; j < 8; j++) 10579 e.params[j] = be32toh(e.params[j]); 10580 10581 db_printf("%10d %15ju %8s %8s ", 10582 e.seqno, e.timestamp, 10583 (e.level < nitems(devlog_level_strings) ? 10584 devlog_level_strings[e.level] : "UNKNOWN"), 10585 (e.facility < nitems(devlog_facility_strings) ? 10586 devlog_facility_strings[e.facility] : "UNKNOWN")); 10587 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10588 e.params[3], e.params[4], e.params[5], e.params[6], 10589 e.params[7]); 10590 10591 if (++i == nentries) 10592 i = 0; 10593 } while (i != first && !db_pager_quit); 10594 } 10595 10596 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10597 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10598 10599 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10600 { 10601 device_t dev; 10602 int t; 10603 bool valid; 10604 10605 valid = false; 10606 t = db_read_token(); 10607 if (t == tIDENT) { 10608 dev = device_lookup_by_name(db_tok_string); 10609 valid = true; 10610 } 10611 db_skip_to_eol(); 10612 if (!valid) { 10613 db_printf("usage: show t4 devlog <nexus>\n"); 10614 return; 10615 } 10616 10617 if (dev == NULL) { 10618 db_printf("device not found\n"); 10619 return; 10620 } 10621 10622 t4_dump_devlog(device_get_softc(dev)); 10623 } 10624 10625 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10626 { 10627 device_t dev; 10628 int radix, tid, t; 10629 bool valid; 10630 10631 valid = false; 10632 radix = db_radix; 10633 db_radix = 10; 10634 t = db_read_token(); 10635 if (t == tIDENT) { 10636 dev = device_lookup_by_name(db_tok_string); 10637 t = db_read_token(); 10638 if (t == tNUMBER) { 10639 tid = db_tok_number; 10640 valid = true; 10641 } 10642 } 10643 db_radix = radix; 10644 db_skip_to_eol(); 10645 if (!valid) { 10646 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10647 return; 10648 } 10649 10650 if (dev == NULL) { 10651 db_printf("device not found\n"); 10652 return; 10653 } 10654 if (tid < 0) { 10655 db_printf("invalid tid\n"); 10656 return; 10657 } 10658 10659 t4_dump_tcb(device_get_softc(dev), tid); 10660 } 10661 #endif 10662 10663 /* 10664 * Borrowed from cesa_prep_aes_key(). 10665 * 10666 * NB: The crypto engine wants the words in the decryption key in reverse 10667 * order. 10668 */ 10669 void 10670 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 10671 { 10672 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 10673 uint32_t *dkey; 10674 int i; 10675 10676 rijndaelKeySetupEnc(ek, enc_key, kbits); 10677 dkey = dec_key; 10678 dkey += (kbits / 8) / 4; 10679 10680 switch (kbits) { 10681 case 128: 10682 for (i = 0; i < 4; i++) 10683 *--dkey = htobe32(ek[4 * 10 + i]); 10684 break; 10685 case 192: 10686 for (i = 0; i < 2; i++) 10687 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10688 for (i = 0; i < 4; i++) 10689 *--dkey = htobe32(ek[4 * 12 + i]); 10690 break; 10691 case 256: 10692 for (i = 0; i < 4; i++) 10693 *--dkey = htobe32(ek[4 * 13 + i]); 10694 for (i = 0; i < 4; i++) 10695 *--dkey = htobe32(ek[4 * 14 + i]); 10696 break; 10697 } 10698 MPASS(dkey == dec_key); 10699 } 10700 10701 static struct sx mlu; /* mod load unload */ 10702 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10703 10704 static int 10705 mod_event(module_t mod, int cmd, void *arg) 10706 { 10707 int rc = 0; 10708 static int loaded = 0; 10709 10710 switch (cmd) { 10711 case MOD_LOAD: 10712 sx_xlock(&mlu); 10713 if (loaded++ == 0) { 10714 t4_sge_modload(); 10715 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10716 t4_filter_rpl, CPL_COOKIE_FILTER); 10717 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 10718 do_l2t_write_rpl, CPL_COOKIE_FILTER); 10719 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 10720 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 10721 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10722 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 10723 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 10724 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10725 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10726 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10727 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 10728 do_smt_write_rpl); 10729 sx_init(&t4_list_lock, "T4/T5 adapters"); 10730 SLIST_INIT(&t4_list); 10731 callout_init(&fatal_callout, 1); 10732 #ifdef TCP_OFFLOAD 10733 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10734 SLIST_INIT(&t4_uld_list); 10735 #endif 10736 #ifdef INET6 10737 t4_clip_modload(); 10738 #endif 10739 t4_tracer_modload(); 10740 tweak_tunables(); 10741 } 10742 sx_xunlock(&mlu); 10743 break; 10744 10745 case MOD_UNLOAD: 10746 sx_xlock(&mlu); 10747 if (--loaded == 0) { 10748 int tries; 10749 10750 sx_slock(&t4_list_lock); 10751 if (!SLIST_EMPTY(&t4_list)) { 10752 rc = EBUSY; 10753 sx_sunlock(&t4_list_lock); 10754 goto done_unload; 10755 } 10756 #ifdef TCP_OFFLOAD 10757 sx_slock(&t4_uld_list_lock); 10758 if (!SLIST_EMPTY(&t4_uld_list)) { 10759 rc = EBUSY; 10760 sx_sunlock(&t4_uld_list_lock); 10761 sx_sunlock(&t4_list_lock); 10762 goto done_unload; 10763 } 10764 #endif 10765 tries = 0; 10766 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10767 uprintf("%ju clusters with custom free routine " 10768 "still is use.\n", t4_sge_extfree_refs()); 10769 pause("t4unload", 2 * hz); 10770 } 10771 #ifdef TCP_OFFLOAD 10772 sx_sunlock(&t4_uld_list_lock); 10773 #endif 10774 sx_sunlock(&t4_list_lock); 10775 10776 if (t4_sge_extfree_refs() == 0) { 10777 t4_tracer_modunload(); 10778 #ifdef INET6 10779 t4_clip_modunload(); 10780 #endif 10781 #ifdef TCP_OFFLOAD 10782 sx_destroy(&t4_uld_list_lock); 10783 #endif 10784 sx_destroy(&t4_list_lock); 10785 t4_sge_modunload(); 10786 loaded = 0; 10787 } else { 10788 rc = EBUSY; 10789 loaded++; /* undo earlier decrement */ 10790 } 10791 } 10792 done_unload: 10793 sx_xunlock(&mlu); 10794 break; 10795 } 10796 10797 return (rc); 10798 } 10799 10800 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10801 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10802 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10803 10804 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10805 MODULE_VERSION(t4nex, 1); 10806 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10807 #ifdef DEV_NETMAP 10808 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10809 #endif /* DEV_NETMAP */ 10810 10811 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10812 MODULE_VERSION(t5nex, 1); 10813 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10814 #ifdef DEV_NETMAP 10815 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10816 #endif /* DEV_NETMAP */ 10817 10818 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10819 MODULE_VERSION(t6nex, 1); 10820 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10821 #ifdef DEV_NETMAP 10822 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10823 #endif /* DEV_NETMAP */ 10824 10825 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10826 MODULE_VERSION(cxgbe, 1); 10827 10828 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10829 MODULE_VERSION(cxl, 1); 10830 10831 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10832 MODULE_VERSION(cc, 1); 10833 10834 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10835 MODULE_VERSION(vcxgbe, 1); 10836 10837 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10838 MODULE_VERSION(vcxl, 1); 10839 10840 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10841 MODULE_VERSION(vcc, 1); 10842