1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ddb.h" 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_rss.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/priv.h> 39 #include <sys/kernel.h> 40 #include <sys/bus.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pci_private.h> 49 #include <sys/firmware.h> 50 #include <sys/sbuf.h> 51 #include <sys/smp.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_types.h> 58 #include <net/if_dl.h> 59 #include <net/if_vlan_var.h> 60 #ifdef RSS 61 #include <net/rss_config.h> 62 #endif 63 #if defined(__i386__) || defined(__amd64__) 64 #include <vm/vm.h> 65 #include <vm/pmap.h> 66 #endif 67 #ifdef DDB 68 #include <ddb/ddb.h> 69 #include <ddb/db_lex.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_msg.h" 74 #include "common/t4_regs.h" 75 #include "common/t4_regs_values.h" 76 #include "t4_ioctl.h" 77 #include "t4_l2t.h" 78 #include "t4_mp_ring.h" 79 #include "t4_if.h" 80 81 /* T4 bus driver interface */ 82 static int t4_probe(device_t); 83 static int t4_attach(device_t); 84 static int t4_detach(device_t); 85 static int t4_ready(device_t); 86 static int t4_read_port_device(device_t, int, device_t *); 87 static device_method_t t4_methods[] = { 88 DEVMETHOD(device_probe, t4_probe), 89 DEVMETHOD(device_attach, t4_attach), 90 DEVMETHOD(device_detach, t4_detach), 91 92 DEVMETHOD(t4_is_main_ready, t4_ready), 93 DEVMETHOD(t4_read_port_device, t4_read_port_device), 94 95 DEVMETHOD_END 96 }; 97 static driver_t t4_driver = { 98 "t4nex", 99 t4_methods, 100 sizeof(struct adapter) 101 }; 102 103 104 /* T4 port (cxgbe) interface */ 105 static int cxgbe_probe(device_t); 106 static int cxgbe_attach(device_t); 107 static int cxgbe_detach(device_t); 108 device_method_t cxgbe_methods[] = { 109 DEVMETHOD(device_probe, cxgbe_probe), 110 DEVMETHOD(device_attach, cxgbe_attach), 111 DEVMETHOD(device_detach, cxgbe_detach), 112 { 0, 0 } 113 }; 114 static driver_t cxgbe_driver = { 115 "cxgbe", 116 cxgbe_methods, 117 sizeof(struct port_info) 118 }; 119 120 /* T4 VI (vcxgbe) interface */ 121 static int vcxgbe_probe(device_t); 122 static int vcxgbe_attach(device_t); 123 static int vcxgbe_detach(device_t); 124 static device_method_t vcxgbe_methods[] = { 125 DEVMETHOD(device_probe, vcxgbe_probe), 126 DEVMETHOD(device_attach, vcxgbe_attach), 127 DEVMETHOD(device_detach, vcxgbe_detach), 128 { 0, 0 } 129 }; 130 static driver_t vcxgbe_driver = { 131 "vcxgbe", 132 vcxgbe_methods, 133 sizeof(struct vi_info) 134 }; 135 136 static d_ioctl_t t4_ioctl; 137 138 static struct cdevsw t4_cdevsw = { 139 .d_version = D_VERSION, 140 .d_ioctl = t4_ioctl, 141 .d_name = "t4nex", 142 }; 143 144 /* T5 bus driver interface */ 145 static int t5_probe(device_t); 146 static device_method_t t5_methods[] = { 147 DEVMETHOD(device_probe, t5_probe), 148 DEVMETHOD(device_attach, t4_attach), 149 DEVMETHOD(device_detach, t4_detach), 150 151 DEVMETHOD(t4_is_main_ready, t4_ready), 152 DEVMETHOD(t4_read_port_device, t4_read_port_device), 153 154 DEVMETHOD_END 155 }; 156 static driver_t t5_driver = { 157 "t5nex", 158 t5_methods, 159 sizeof(struct adapter) 160 }; 161 162 163 /* T5 port (cxl) interface */ 164 static driver_t cxl_driver = { 165 "cxl", 166 cxgbe_methods, 167 sizeof(struct port_info) 168 }; 169 170 /* T5 VI (vcxl) interface */ 171 static driver_t vcxl_driver = { 172 "vcxl", 173 vcxgbe_methods, 174 sizeof(struct vi_info) 175 }; 176 177 /* ifnet + media interface */ 178 static void cxgbe_init(void *); 179 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 180 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 181 static void cxgbe_qflush(struct ifnet *); 182 static int cxgbe_media_change(struct ifnet *); 183 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 184 185 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 186 187 /* 188 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 189 * then ADAPTER_LOCK, then t4_uld_list_lock. 190 */ 191 static struct sx t4_list_lock; 192 SLIST_HEAD(, adapter) t4_list; 193 #ifdef TCP_OFFLOAD 194 static struct sx t4_uld_list_lock; 195 SLIST_HEAD(, uld_info) t4_uld_list; 196 #endif 197 198 /* 199 * Tunables. See tweak_tunables() too. 200 * 201 * Each tunable is set to a default value here if it's known at compile-time. 202 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should 203 * provide a reasonable default when the driver is loaded. 204 * 205 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 206 * T5 are under hw.cxl. 207 */ 208 209 /* 210 * Number of queues for tx and rx, 10G and 1G, NIC and offload. 211 */ 212 #define NTXQ_10G 16 213 int t4_ntxq10g = -1; 214 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g); 215 216 #define NRXQ_10G 8 217 int t4_nrxq10g = -1; 218 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g); 219 220 #define NTXQ_1G 4 221 int t4_ntxq1g = -1; 222 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g); 223 224 #define NRXQ_1G 2 225 int t4_nrxq1g = -1; 226 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g); 227 228 #define NTXQ_VI 1 229 static int t4_ntxq_vi = -1; 230 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi); 231 232 #define NRXQ_VI 1 233 static int t4_nrxq_vi = -1; 234 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi); 235 236 static int t4_rsrv_noflowq = 0; 237 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq); 238 239 #ifdef TCP_OFFLOAD 240 #define NOFLDTXQ_10G 8 241 static int t4_nofldtxq10g = -1; 242 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g); 243 244 #define NOFLDRXQ_10G 2 245 static int t4_nofldrxq10g = -1; 246 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g); 247 248 #define NOFLDTXQ_1G 2 249 static int t4_nofldtxq1g = -1; 250 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g); 251 252 #define NOFLDRXQ_1G 1 253 static int t4_nofldrxq1g = -1; 254 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g); 255 256 #define NOFLDTXQ_VI 1 257 static int t4_nofldtxq_vi = -1; 258 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi); 259 260 #define NOFLDRXQ_VI 1 261 static int t4_nofldrxq_vi = -1; 262 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi); 263 #endif 264 265 #ifdef DEV_NETMAP 266 #define NNMTXQ_VI 2 267 static int t4_nnmtxq_vi = -1; 268 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi); 269 270 #define NNMRXQ_VI 2 271 static int t4_nnmrxq_vi = -1; 272 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi); 273 #endif 274 275 /* 276 * Holdoff parameters for 10G and 1G ports. 277 */ 278 #define TMR_IDX_10G 1 279 int t4_tmr_idx_10g = TMR_IDX_10G; 280 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g); 281 282 #define PKTC_IDX_10G (-1) 283 int t4_pktc_idx_10g = PKTC_IDX_10G; 284 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g); 285 286 #define TMR_IDX_1G 1 287 int t4_tmr_idx_1g = TMR_IDX_1G; 288 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g); 289 290 #define PKTC_IDX_1G (-1) 291 int t4_pktc_idx_1g = PKTC_IDX_1G; 292 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g); 293 294 /* 295 * Size (# of entries) of each tx and rx queue. 296 */ 297 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 298 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 299 300 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 301 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 302 303 /* 304 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 305 */ 306 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 307 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 308 309 /* 310 * Configuration file. 311 */ 312 #define DEFAULT_CF "default" 313 #define FLASH_CF "flash" 314 #define UWIRE_CF "uwire" 315 #define FPGA_CF "fpga" 316 static char t4_cfg_file[32] = DEFAULT_CF; 317 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 318 319 /* 320 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively). 321 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 322 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 323 * mark or when signalled to do so, 0 to never emit PAUSE. 324 */ 325 static int t4_pause_settings = PAUSE_TX | PAUSE_RX; 326 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings); 327 328 /* 329 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 330 * encouraged respectively). 331 */ 332 static unsigned int t4_fw_install = 1; 333 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 334 335 /* 336 * ASIC features that will be used. Disable the ones you don't want so that the 337 * chip resources aren't wasted on features that will not be used. 338 */ 339 static int t4_nbmcaps_allowed = 0; 340 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed); 341 342 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 343 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 344 345 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 346 FW_CAPS_CONFIG_SWITCH_EGRESS; 347 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed); 348 349 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC; 350 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 351 352 static int t4_toecaps_allowed = -1; 353 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 354 355 static int t4_rdmacaps_allowed = -1; 356 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 357 358 static int t4_cryptocaps_allowed = 0; 359 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed); 360 361 static int t4_iscsicaps_allowed = -1; 362 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 363 364 static int t4_fcoecaps_allowed = 0; 365 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 366 367 static int t5_write_combine = 0; 368 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 369 370 static int t4_num_vis = 1; 371 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis); 372 373 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */ 374 static int vi_mac_funcs[] = { 375 FW_VI_FUNC_OFLD, 376 FW_VI_FUNC_IWARP, 377 FW_VI_FUNC_OPENISCSI, 378 FW_VI_FUNC_OPENFCOE, 379 FW_VI_FUNC_FOISCSI, 380 FW_VI_FUNC_FOFCOE, 381 }; 382 383 struct intrs_and_queues { 384 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 385 uint16_t nirq; /* Total # of vectors */ 386 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */ 387 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */ 388 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */ 389 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */ 390 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */ 391 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */ 392 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */ 393 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */ 394 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */ 395 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */ 396 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */ 397 398 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 399 uint16_t ntxq_vi; /* # of NIC txq's */ 400 uint16_t nrxq_vi; /* # of NIC rxq's */ 401 uint16_t nofldtxq_vi; /* # of TOE txq's */ 402 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 403 uint16_t nnmtxq_vi; /* # of netmap txq's */ 404 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 405 }; 406 407 struct filter_entry { 408 uint32_t valid:1; /* filter allocated and valid */ 409 uint32_t locked:1; /* filter is administratively locked */ 410 uint32_t pending:1; /* filter action is pending firmware reply */ 411 uint32_t smtidx:8; /* Source MAC Table index for smac */ 412 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 413 414 struct t4_filter_specification fs; 415 }; 416 417 static void setup_memwin(struct adapter *); 418 static void position_memwin(struct adapter *, int, uint32_t); 419 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 420 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *, 421 int); 422 static inline int write_via_memwin(struct adapter *, int, uint32_t, 423 const uint32_t *, int); 424 static int validate_mem_range(struct adapter *, uint32_t, int); 425 static int fwmtype_to_hwmtype(int); 426 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 427 uint32_t *); 428 static int fixup_devlog_params(struct adapter *); 429 static int cfg_itype_and_nqueues(struct adapter *, int, int, int, 430 struct intrs_and_queues *); 431 static int prep_firmware(struct adapter *); 432 static int partition_resources(struct adapter *, const struct firmware *, 433 const char *); 434 static int get_params__pre_init(struct adapter *); 435 static int get_params__post_init(struct adapter *); 436 static int set_params__post_init(struct adapter *); 437 static void t4_set_desc(struct adapter *); 438 static void build_medialist(struct port_info *, struct ifmedia *); 439 static int cxgbe_init_synchronized(struct vi_info *); 440 static int cxgbe_uninit_synchronized(struct vi_info *); 441 static void quiesce_txq(struct adapter *, struct sge_txq *); 442 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 443 static void quiesce_iq(struct adapter *, struct sge_iq *); 444 static void quiesce_fl(struct adapter *, struct sge_fl *); 445 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 446 driver_intr_t *, void *, char *); 447 static int t4_free_irq(struct adapter *, struct irq *); 448 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 449 static void vi_refresh_stats(struct adapter *, struct vi_info *); 450 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 451 static void cxgbe_tick(void *); 452 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 453 static void cxgbe_sysctls(struct port_info *); 454 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 455 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 456 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 457 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 458 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 459 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 460 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 461 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 462 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 463 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 464 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 465 #ifdef SBUF_DRAIN 466 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 467 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 468 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 469 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 470 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 471 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 472 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 473 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 474 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 475 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 476 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 477 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 478 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 479 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 480 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 481 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 482 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 483 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 484 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 485 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 486 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 487 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 488 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 489 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 490 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 491 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 492 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 493 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 494 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 495 #endif 496 #ifdef TCP_OFFLOAD 497 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 498 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 499 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 500 #endif 501 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t); 502 static uint32_t mode_to_fconf(uint32_t); 503 static uint32_t mode_to_iconf(uint32_t); 504 static int check_fspec_against_fconf_iconf(struct adapter *, 505 struct t4_filter_specification *); 506 static int get_filter_mode(struct adapter *, uint32_t *); 507 static int set_filter_mode(struct adapter *, uint32_t); 508 static inline uint64_t get_filter_hits(struct adapter *, uint32_t); 509 static int get_filter(struct adapter *, struct t4_filter *); 510 static int set_filter(struct adapter *, struct t4_filter *); 511 static int del_filter(struct adapter *, struct t4_filter *); 512 static void clear_filter(struct filter_entry *); 513 static int set_filter_wr(struct adapter *, int); 514 static int del_filter_wr(struct adapter *, int); 515 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *, 516 struct mbuf *); 517 static int get_sge_context(struct adapter *, struct t4_sge_context *); 518 static int load_fw(struct adapter *, struct t4_data *); 519 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 520 static int read_i2c(struct adapter *, struct t4_i2c_data *); 521 #ifdef TCP_OFFLOAD 522 static int toe_capability(struct vi_info *, int); 523 #endif 524 static int mod_event(module_t, int, void *); 525 static int notify_siblings(device_t, int); 526 527 struct { 528 uint16_t device; 529 char *desc; 530 } t4_pciids[] = { 531 {0xa000, "Chelsio Terminator 4 FPGA"}, 532 {0x4400, "Chelsio T440-dbg"}, 533 {0x4401, "Chelsio T420-CR"}, 534 {0x4402, "Chelsio T422-CR"}, 535 {0x4403, "Chelsio T440-CR"}, 536 {0x4404, "Chelsio T420-BCH"}, 537 {0x4405, "Chelsio T440-BCH"}, 538 {0x4406, "Chelsio T440-CH"}, 539 {0x4407, "Chelsio T420-SO"}, 540 {0x4408, "Chelsio T420-CX"}, 541 {0x4409, "Chelsio T420-BT"}, 542 {0x440a, "Chelsio T404-BT"}, 543 {0x440e, "Chelsio T440-LP-CR"}, 544 }, t5_pciids[] = { 545 {0xb000, "Chelsio Terminator 5 FPGA"}, 546 {0x5400, "Chelsio T580-dbg"}, 547 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 548 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 549 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 550 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 551 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 552 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 553 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 554 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 555 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 556 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 557 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 558 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 559 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 560 #ifdef notyet 561 {0x5404, "Chelsio T520-BCH"}, 562 {0x5405, "Chelsio T540-BCH"}, 563 {0x5406, "Chelsio T540-CH"}, 564 {0x5408, "Chelsio T520-CX"}, 565 {0x540b, "Chelsio B520-SR"}, 566 {0x540c, "Chelsio B504-BT"}, 567 {0x540f, "Chelsio Amsterdam"}, 568 {0x5413, "Chelsio T580-CHR"}, 569 #endif 570 }; 571 572 #ifdef TCP_OFFLOAD 573 /* 574 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 575 * exactly the same for both rxq and ofld_rxq. 576 */ 577 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 578 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 579 #endif 580 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 581 582 static int 583 t4_probe(device_t dev) 584 { 585 int i; 586 uint16_t v = pci_get_vendor(dev); 587 uint16_t d = pci_get_device(dev); 588 uint8_t f = pci_get_function(dev); 589 590 if (v != PCI_VENDOR_ID_CHELSIO) 591 return (ENXIO); 592 593 /* Attach only to PF0 of the FPGA */ 594 if (d == 0xa000 && f != 0) 595 return (ENXIO); 596 597 for (i = 0; i < nitems(t4_pciids); i++) { 598 if (d == t4_pciids[i].device) { 599 device_set_desc(dev, t4_pciids[i].desc); 600 return (BUS_PROBE_DEFAULT); 601 } 602 } 603 604 return (ENXIO); 605 } 606 607 static int 608 t5_probe(device_t dev) 609 { 610 int i; 611 uint16_t v = pci_get_vendor(dev); 612 uint16_t d = pci_get_device(dev); 613 uint8_t f = pci_get_function(dev); 614 615 if (v != PCI_VENDOR_ID_CHELSIO) 616 return (ENXIO); 617 618 /* Attach only to PF0 of the FPGA */ 619 if (d == 0xb000 && f != 0) 620 return (ENXIO); 621 622 for (i = 0; i < nitems(t5_pciids); i++) { 623 if (d == t5_pciids[i].device) { 624 device_set_desc(dev, t5_pciids[i].desc); 625 return (BUS_PROBE_DEFAULT); 626 } 627 } 628 629 return (ENXIO); 630 } 631 632 static void 633 t5_attribute_workaround(device_t dev) 634 { 635 device_t root_port; 636 uint32_t v; 637 638 /* 639 * The T5 chips do not properly echo the No Snoop and Relaxed 640 * Ordering attributes when replying to a TLP from a Root 641 * Port. As a workaround, find the parent Root Port and 642 * disable No Snoop and Relaxed Ordering. Note that this 643 * affects all devices under this root port. 644 */ 645 root_port = pci_find_pcie_root_port(dev); 646 if (root_port == NULL) { 647 device_printf(dev, "Unable to find parent root port\n"); 648 return; 649 } 650 651 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 652 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 653 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 654 0) 655 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 656 device_get_nameunit(root_port)); 657 } 658 659 static int 660 t4_attach(device_t dev) 661 { 662 struct adapter *sc; 663 int rc = 0, i, j, n10g, n1g, rqidx, tqidx; 664 struct make_dev_args mda; 665 struct intrs_and_queues iaq; 666 struct sge *s; 667 uint8_t *buf; 668 #ifdef TCP_OFFLOAD 669 int ofld_rqidx, ofld_tqidx; 670 #endif 671 #ifdef DEV_NETMAP 672 int nm_rqidx, nm_tqidx; 673 #endif 674 int num_vis; 675 676 sc = device_get_softc(dev); 677 sc->dev = dev; 678 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 679 680 if ((pci_get_device(dev) & 0xff00) == 0x5400) 681 t5_attribute_workaround(dev); 682 pci_enable_busmaster(dev); 683 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 684 uint32_t v; 685 686 pci_set_max_read_req(dev, 4096); 687 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 688 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 689 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 690 691 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 692 } 693 694 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 695 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 696 sc->traceq = -1; 697 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 698 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 699 device_get_nameunit(dev)); 700 701 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 702 device_get_nameunit(dev)); 703 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 704 t4_add_adapter(sc); 705 706 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 707 TAILQ_INIT(&sc->sfl); 708 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 709 710 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 711 712 rc = t4_map_bars_0_and_4(sc); 713 if (rc != 0) 714 goto done; /* error message displayed already */ 715 716 /* 717 * This is the real PF# to which we're attaching. Works from within PCI 718 * passthrough environments too, where pci_get_function() could return a 719 * different PF# depending on the passthrough configuration. We need to 720 * use the real PF# in all our communication with the firmware. 721 */ 722 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI)); 723 sc->mbox = sc->pf; 724 725 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 726 727 /* Prepare the adapter for operation. */ 728 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 729 rc = -t4_prep_adapter(sc, buf); 730 free(buf, M_CXGBE); 731 if (rc != 0) { 732 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 733 goto done; 734 } 735 736 /* 737 * Do this really early, with the memory windows set up even before the 738 * character device. The userland tool's register i/o and mem read 739 * will work even in "recovery mode". 740 */ 741 setup_memwin(sc); 742 if (t4_init_devlog_params(sc, 0) == 0) 743 fixup_devlog_params(sc); 744 make_dev_args_init(&mda); 745 mda.mda_devsw = &t4_cdevsw; 746 mda.mda_uid = UID_ROOT; 747 mda.mda_gid = GID_WHEEL; 748 mda.mda_mode = 0600; 749 mda.mda_si_drv1 = sc; 750 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 751 if (rc != 0) 752 device_printf(dev, "failed to create nexus char device: %d.\n", 753 rc); 754 755 /* Go no further if recovery mode has been requested. */ 756 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 757 device_printf(dev, "recovery mode.\n"); 758 goto done; 759 } 760 761 #if defined(__i386__) 762 if ((cpu_feature & CPUID_CX8) == 0) { 763 device_printf(dev, "64 bit atomics not available.\n"); 764 rc = ENOTSUP; 765 goto done; 766 } 767 #endif 768 769 /* Prepare the firmware for operation */ 770 rc = prep_firmware(sc); 771 if (rc != 0) 772 goto done; /* error message displayed already */ 773 774 rc = get_params__post_init(sc); 775 if (rc != 0) 776 goto done; /* error message displayed already */ 777 778 rc = set_params__post_init(sc); 779 if (rc != 0) 780 goto done; /* error message displayed already */ 781 782 rc = t4_map_bar_2(sc); 783 if (rc != 0) 784 goto done; /* error message displayed already */ 785 786 rc = t4_create_dma_tag(sc); 787 if (rc != 0) 788 goto done; /* error message displayed already */ 789 790 /* 791 * Number of VIs to create per-port. The first VI is the "main" regular 792 * VI for the port. The rest are additional virtual interfaces on the 793 * same physical port. Note that the main VI does not have native 794 * netmap support but the extra VIs do. 795 * 796 * Limit the number of VIs per port to the number of available 797 * MAC addresses per port. 798 */ 799 if (t4_num_vis >= 1) 800 num_vis = t4_num_vis; 801 else 802 num_vis = 1; 803 if (num_vis > nitems(vi_mac_funcs)) { 804 num_vis = nitems(vi_mac_funcs); 805 device_printf(dev, "Number of VIs limited to %d\n", num_vis); 806 } 807 808 /* 809 * First pass over all the ports - allocate VIs and initialize some 810 * basic parameters like mac address, port type, etc. We also figure 811 * out whether a port is 10G or 1G and use that information when 812 * calculating how many interrupts to attempt to allocate. 813 */ 814 n10g = n1g = 0; 815 for_each_port(sc, i) { 816 struct port_info *pi; 817 818 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 819 sc->port[i] = pi; 820 821 /* These must be set before t4_port_init */ 822 pi->adapter = sc; 823 pi->port_id = i; 824 /* 825 * XXX: vi[0] is special so we can't delay this allocation until 826 * pi->nvi's final value is known. 827 */ 828 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE, 829 M_ZERO | M_WAITOK); 830 831 /* 832 * Allocate the "main" VI and initialize parameters 833 * like mac addr. 834 */ 835 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 836 if (rc != 0) { 837 device_printf(dev, "unable to initialize port %d: %d\n", 838 i, rc); 839 free(pi->vi, M_CXGBE); 840 free(pi, M_CXGBE); 841 sc->port[i] = NULL; 842 goto done; 843 } 844 845 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX); 846 pi->link_cfg.requested_fc |= t4_pause_settings; 847 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX); 848 pi->link_cfg.fc |= t4_pause_settings; 849 850 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, &pi->link_cfg); 851 if (rc != 0) { 852 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc); 853 free(pi->vi, M_CXGBE); 854 free(pi, M_CXGBE); 855 sc->port[i] = NULL; 856 goto done; 857 } 858 859 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 860 device_get_nameunit(dev), i); 861 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 862 sc->chan_map[pi->tx_chan] = i; 863 864 pi->tc = malloc(sizeof(struct tx_sched_class) * 865 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK); 866 867 if (is_10G_port(pi) || is_40G_port(pi)) { 868 n10g++; 869 } else { 870 n1g++; 871 } 872 873 pi->linkdnrc = -1; 874 875 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1); 876 if (pi->dev == NULL) { 877 device_printf(dev, 878 "failed to add device for port %d.\n", i); 879 rc = ENXIO; 880 goto done; 881 } 882 pi->vi[0].dev = pi->dev; 883 device_set_softc(pi->dev, pi); 884 } 885 886 /* 887 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 888 */ 889 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq); 890 if (rc != 0) 891 goto done; /* error message displayed already */ 892 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0) 893 num_vis = 1; 894 895 sc->intr_type = iaq.intr_type; 896 sc->intr_count = iaq.nirq; 897 898 s = &sc->sge; 899 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; 900 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; 901 if (num_vis > 1) { 902 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi; 903 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi; 904 } 905 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 906 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 907 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 908 #ifdef TCP_OFFLOAD 909 if (is_offload(sc)) { 910 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g; 911 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g; 912 if (num_vis > 1) { 913 s->nofldrxq += (n10g + n1g) * (num_vis - 1) * 914 iaq.nofldrxq_vi; 915 s->nofldtxq += (n10g + n1g) * (num_vis - 1) * 916 iaq.nofldtxq_vi; 917 } 918 s->neq += s->nofldtxq + s->nofldrxq; 919 s->niq += s->nofldrxq; 920 921 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 922 M_CXGBE, M_ZERO | M_WAITOK); 923 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 924 M_CXGBE, M_ZERO | M_WAITOK); 925 } 926 #endif 927 #ifdef DEV_NETMAP 928 if (num_vis > 1) { 929 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi; 930 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi; 931 } 932 s->neq += s->nnmtxq + s->nnmrxq; 933 s->niq += s->nnmrxq; 934 935 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 936 M_CXGBE, M_ZERO | M_WAITOK); 937 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 938 M_CXGBE, M_ZERO | M_WAITOK); 939 #endif 940 941 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE, 942 M_ZERO | M_WAITOK); 943 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 944 M_ZERO | M_WAITOK); 945 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 946 M_ZERO | M_WAITOK); 947 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 948 M_ZERO | M_WAITOK); 949 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 950 M_ZERO | M_WAITOK); 951 952 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 953 M_ZERO | M_WAITOK); 954 955 t4_init_l2t(sc, M_WAITOK); 956 957 /* 958 * Second pass over the ports. This time we know the number of rx and 959 * tx queues that each port should get. 960 */ 961 rqidx = tqidx = 0; 962 #ifdef TCP_OFFLOAD 963 ofld_rqidx = ofld_tqidx = 0; 964 #endif 965 #ifdef DEV_NETMAP 966 nm_rqidx = nm_tqidx = 0; 967 #endif 968 for_each_port(sc, i) { 969 struct port_info *pi = sc->port[i]; 970 struct vi_info *vi; 971 972 if (pi == NULL) 973 continue; 974 975 pi->nvi = num_vis; 976 for_each_vi(pi, j, vi) { 977 vi->pi = pi; 978 vi->qsize_rxq = t4_qsize_rxq; 979 vi->qsize_txq = t4_qsize_txq; 980 981 vi->first_rxq = rqidx; 982 vi->first_txq = tqidx; 983 if (is_10G_port(pi) || is_40G_port(pi)) { 984 vi->tmr_idx = t4_tmr_idx_10g; 985 vi->pktc_idx = t4_pktc_idx_10g; 986 vi->flags |= iaq.intr_flags_10g & INTR_RXQ; 987 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi; 988 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi; 989 } else { 990 vi->tmr_idx = t4_tmr_idx_1g; 991 vi->pktc_idx = t4_pktc_idx_1g; 992 vi->flags |= iaq.intr_flags_1g & INTR_RXQ; 993 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi; 994 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi; 995 } 996 rqidx += vi->nrxq; 997 tqidx += vi->ntxq; 998 999 if (j == 0 && vi->ntxq > 1) 1000 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0; 1001 else 1002 vi->rsrv_noflowq = 0; 1003 1004 #ifdef TCP_OFFLOAD 1005 vi->first_ofld_rxq = ofld_rqidx; 1006 vi->first_ofld_txq = ofld_tqidx; 1007 if (is_10G_port(pi) || is_40G_port(pi)) { 1008 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ; 1009 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g : 1010 iaq.nofldrxq_vi; 1011 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g : 1012 iaq.nofldtxq_vi; 1013 } else { 1014 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ; 1015 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g : 1016 iaq.nofldrxq_vi; 1017 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g : 1018 iaq.nofldtxq_vi; 1019 } 1020 ofld_rqidx += vi->nofldrxq; 1021 ofld_tqidx += vi->nofldtxq; 1022 #endif 1023 #ifdef DEV_NETMAP 1024 if (j > 0) { 1025 vi->first_nm_rxq = nm_rqidx; 1026 vi->first_nm_txq = nm_tqidx; 1027 vi->nnmrxq = iaq.nnmrxq_vi; 1028 vi->nnmtxq = iaq.nnmtxq_vi; 1029 nm_rqidx += vi->nnmrxq; 1030 nm_tqidx += vi->nnmtxq; 1031 } 1032 #endif 1033 } 1034 } 1035 1036 rc = t4_setup_intr_handlers(sc); 1037 if (rc != 0) { 1038 device_printf(dev, 1039 "failed to setup interrupt handlers: %d\n", rc); 1040 goto done; 1041 } 1042 1043 rc = bus_generic_attach(dev); 1044 if (rc != 0) { 1045 device_printf(dev, 1046 "failed to attach all child ports: %d\n", rc); 1047 goto done; 1048 } 1049 1050 device_printf(dev, 1051 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1052 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1053 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1054 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1055 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1056 1057 t4_set_desc(sc); 1058 1059 notify_siblings(dev, 0); 1060 1061 done: 1062 if (rc != 0 && sc->cdev) { 1063 /* cdev was created and so cxgbetool works; recover that way. */ 1064 device_printf(dev, 1065 "error during attach, adapter is now in recovery mode.\n"); 1066 rc = 0; 1067 } 1068 1069 if (rc != 0) 1070 t4_detach_common(dev); 1071 else 1072 t4_sysctls(sc); 1073 1074 return (rc); 1075 } 1076 1077 static int 1078 t4_ready(device_t dev) 1079 { 1080 struct adapter *sc; 1081 1082 sc = device_get_softc(dev); 1083 if (sc->flags & FW_OK) 1084 return (0); 1085 return (ENXIO); 1086 } 1087 1088 static int 1089 t4_read_port_device(device_t dev, int port, device_t *child) 1090 { 1091 struct adapter *sc; 1092 struct port_info *pi; 1093 1094 sc = device_get_softc(dev); 1095 if (port < 0 || port >= MAX_NPORTS) 1096 return (EINVAL); 1097 pi = sc->port[port]; 1098 if (pi == NULL || pi->dev == NULL) 1099 return (ENXIO); 1100 *child = pi->dev; 1101 return (0); 1102 } 1103 1104 static int 1105 notify_siblings(device_t dev, int detaching) 1106 { 1107 device_t sibling; 1108 int error, i; 1109 1110 error = 0; 1111 for (i = 0; i < PCI_FUNCMAX; i++) { 1112 if (i == pci_get_function(dev)) 1113 continue; 1114 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1115 pci_get_slot(dev), i); 1116 if (sibling == NULL || !device_is_attached(sibling)) 1117 continue; 1118 if (detaching) 1119 error = T4_DETACH_CHILD(sibling); 1120 else 1121 (void)T4_ATTACH_CHILD(sibling); 1122 if (error) 1123 break; 1124 } 1125 return (error); 1126 } 1127 1128 /* 1129 * Idempotent 1130 */ 1131 static int 1132 t4_detach(device_t dev) 1133 { 1134 struct adapter *sc; 1135 int rc; 1136 1137 sc = device_get_softc(dev); 1138 1139 rc = notify_siblings(dev, 1); 1140 if (rc) { 1141 device_printf(dev, 1142 "failed to detach sibling devices: %d\n", rc); 1143 return (rc); 1144 } 1145 1146 return (t4_detach_common(dev)); 1147 } 1148 1149 int 1150 t4_detach_common(device_t dev) 1151 { 1152 struct adapter *sc; 1153 struct port_info *pi; 1154 int i, rc; 1155 1156 sc = device_get_softc(dev); 1157 1158 if (sc->flags & FULL_INIT_DONE) { 1159 if (!(sc->flags & IS_VF)) 1160 t4_intr_disable(sc); 1161 } 1162 1163 if (sc->cdev) { 1164 destroy_dev(sc->cdev); 1165 sc->cdev = NULL; 1166 } 1167 1168 if (device_is_attached(dev)) { 1169 rc = bus_generic_detach(dev); 1170 if (rc) { 1171 device_printf(dev, 1172 "failed to detach child devices: %d\n", rc); 1173 return (rc); 1174 } 1175 } 1176 1177 for (i = 0; i < sc->intr_count; i++) 1178 t4_free_irq(sc, &sc->irq[i]); 1179 1180 for (i = 0; i < MAX_NPORTS; i++) { 1181 pi = sc->port[i]; 1182 if (pi) { 1183 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1184 if (pi->dev) 1185 device_delete_child(dev, pi->dev); 1186 1187 mtx_destroy(&pi->pi_lock); 1188 free(pi->vi, M_CXGBE); 1189 free(pi->tc, M_CXGBE); 1190 free(pi, M_CXGBE); 1191 } 1192 } 1193 1194 if (sc->flags & FULL_INIT_DONE) 1195 adapter_full_uninit(sc); 1196 1197 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1198 t4_fw_bye(sc, sc->mbox); 1199 1200 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1201 pci_release_msi(dev); 1202 1203 if (sc->regs_res) 1204 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1205 sc->regs_res); 1206 1207 if (sc->udbs_res) 1208 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1209 sc->udbs_res); 1210 1211 if (sc->msix_res) 1212 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1213 sc->msix_res); 1214 1215 if (sc->l2t) 1216 t4_free_l2t(sc->l2t); 1217 1218 #ifdef TCP_OFFLOAD 1219 free(sc->sge.ofld_rxq, M_CXGBE); 1220 free(sc->sge.ofld_txq, M_CXGBE); 1221 #endif 1222 #ifdef DEV_NETMAP 1223 free(sc->sge.nm_rxq, M_CXGBE); 1224 free(sc->sge.nm_txq, M_CXGBE); 1225 #endif 1226 free(sc->irq, M_CXGBE); 1227 free(sc->sge.rxq, M_CXGBE); 1228 free(sc->sge.txq, M_CXGBE); 1229 free(sc->sge.ctrlq, M_CXGBE); 1230 free(sc->sge.iqmap, M_CXGBE); 1231 free(sc->sge.eqmap, M_CXGBE); 1232 free(sc->tids.ftid_tab, M_CXGBE); 1233 t4_destroy_dma_tag(sc); 1234 if (mtx_initialized(&sc->sc_lock)) { 1235 sx_xlock(&t4_list_lock); 1236 SLIST_REMOVE(&t4_list, sc, adapter, link); 1237 sx_xunlock(&t4_list_lock); 1238 mtx_destroy(&sc->sc_lock); 1239 } 1240 1241 callout_drain(&sc->sfl_callout); 1242 if (mtx_initialized(&sc->tids.ftid_lock)) 1243 mtx_destroy(&sc->tids.ftid_lock); 1244 if (mtx_initialized(&sc->sfl_lock)) 1245 mtx_destroy(&sc->sfl_lock); 1246 if (mtx_initialized(&sc->ifp_lock)) 1247 mtx_destroy(&sc->ifp_lock); 1248 if (mtx_initialized(&sc->reg_lock)) 1249 mtx_destroy(&sc->reg_lock); 1250 1251 for (i = 0; i < NUM_MEMWIN; i++) { 1252 struct memwin *mw = &sc->memwin[i]; 1253 1254 if (rw_initialized(&mw->mw_lock)) 1255 rw_destroy(&mw->mw_lock); 1256 } 1257 1258 bzero(sc, sizeof(*sc)); 1259 1260 return (0); 1261 } 1262 1263 static int 1264 cxgbe_probe(device_t dev) 1265 { 1266 char buf[128]; 1267 struct port_info *pi = device_get_softc(dev); 1268 1269 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1270 device_set_desc_copy(dev, buf); 1271 1272 return (BUS_PROBE_DEFAULT); 1273 } 1274 1275 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1276 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1277 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1278 #define T4_CAP_ENABLE (T4_CAP) 1279 1280 static int 1281 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1282 { 1283 struct ifnet *ifp; 1284 struct sbuf *sb; 1285 1286 vi->xact_addr_filt = -1; 1287 callout_init(&vi->tick, 1); 1288 1289 /* Allocate an ifnet and set it up */ 1290 ifp = if_alloc(IFT_ETHER); 1291 if (ifp == NULL) { 1292 device_printf(dev, "Cannot allocate ifnet\n"); 1293 return (ENOMEM); 1294 } 1295 vi->ifp = ifp; 1296 ifp->if_softc = vi; 1297 1298 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1299 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1300 1301 ifp->if_init = cxgbe_init; 1302 ifp->if_ioctl = cxgbe_ioctl; 1303 ifp->if_transmit = cxgbe_transmit; 1304 ifp->if_qflush = cxgbe_qflush; 1305 ifp->if_get_counter = cxgbe_get_counter; 1306 1307 ifp->if_capabilities = T4_CAP; 1308 #ifdef TCP_OFFLOAD 1309 if (vi->nofldrxq != 0) 1310 ifp->if_capabilities |= IFCAP_TOE; 1311 #endif 1312 ifp->if_capenable = T4_CAP_ENABLE; 1313 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1314 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1315 1316 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1317 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1318 ifp->if_hw_tsomaxsegsize = 65536; 1319 1320 /* Initialize ifmedia for this VI */ 1321 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change, 1322 cxgbe_media_status); 1323 build_medialist(vi->pi, &vi->media); 1324 1325 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1326 EVENTHANDLER_PRI_ANY); 1327 1328 ether_ifattach(ifp, vi->hw_addr); 1329 #ifdef DEV_NETMAP 1330 if (vi->nnmrxq != 0) 1331 cxgbe_nm_attach(vi); 1332 #endif 1333 sb = sbuf_new_auto(); 1334 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1335 #ifdef TCP_OFFLOAD 1336 if (ifp->if_capabilities & IFCAP_TOE) 1337 sbuf_printf(sb, "; %d txq, %d rxq (TOE)", 1338 vi->nofldtxq, vi->nofldrxq); 1339 #endif 1340 #ifdef DEV_NETMAP 1341 if (ifp->if_capabilities & IFCAP_NETMAP) 1342 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1343 vi->nnmtxq, vi->nnmrxq); 1344 #endif 1345 sbuf_finish(sb); 1346 device_printf(dev, "%s\n", sbuf_data(sb)); 1347 sbuf_delete(sb); 1348 1349 vi_sysctls(vi); 1350 1351 return (0); 1352 } 1353 1354 static int 1355 cxgbe_attach(device_t dev) 1356 { 1357 struct port_info *pi = device_get_softc(dev); 1358 struct vi_info *vi; 1359 int i, rc; 1360 1361 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1362 1363 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1364 if (rc) 1365 return (rc); 1366 1367 for_each_vi(pi, i, vi) { 1368 if (i == 0) 1369 continue; 1370 vi->dev = device_add_child(dev, is_t4(pi->adapter) ? 1371 "vcxgbe" : "vcxl", -1); 1372 if (vi->dev == NULL) { 1373 device_printf(dev, "failed to add VI %d\n", i); 1374 continue; 1375 } 1376 device_set_softc(vi->dev, vi); 1377 } 1378 1379 cxgbe_sysctls(pi); 1380 1381 bus_generic_attach(dev); 1382 1383 return (0); 1384 } 1385 1386 static void 1387 cxgbe_vi_detach(struct vi_info *vi) 1388 { 1389 struct ifnet *ifp = vi->ifp; 1390 1391 ether_ifdetach(ifp); 1392 1393 if (vi->vlan_c) 1394 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1395 1396 /* Let detach proceed even if these fail. */ 1397 #ifdef DEV_NETMAP 1398 if (ifp->if_capabilities & IFCAP_NETMAP) 1399 cxgbe_nm_detach(vi); 1400 #endif 1401 cxgbe_uninit_synchronized(vi); 1402 callout_drain(&vi->tick); 1403 vi_full_uninit(vi); 1404 1405 ifmedia_removeall(&vi->media); 1406 if_free(vi->ifp); 1407 vi->ifp = NULL; 1408 } 1409 1410 static int 1411 cxgbe_detach(device_t dev) 1412 { 1413 struct port_info *pi = device_get_softc(dev); 1414 struct adapter *sc = pi->adapter; 1415 int rc; 1416 1417 /* Detach the extra VIs first. */ 1418 rc = bus_generic_detach(dev); 1419 if (rc) 1420 return (rc); 1421 device_delete_children(dev); 1422 1423 doom_vi(sc, &pi->vi[0]); 1424 1425 if (pi->flags & HAS_TRACEQ) { 1426 sc->traceq = -1; /* cloner should not create ifnet */ 1427 t4_tracer_port_detach(sc); 1428 } 1429 1430 cxgbe_vi_detach(&pi->vi[0]); 1431 callout_drain(&pi->tick); 1432 1433 end_synchronized_op(sc, 0); 1434 1435 return (0); 1436 } 1437 1438 static void 1439 cxgbe_init(void *arg) 1440 { 1441 struct vi_info *vi = arg; 1442 struct adapter *sc = vi->pi->adapter; 1443 1444 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1445 return; 1446 cxgbe_init_synchronized(vi); 1447 end_synchronized_op(sc, 0); 1448 } 1449 1450 static int 1451 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1452 { 1453 int rc = 0, mtu, flags, can_sleep; 1454 struct vi_info *vi = ifp->if_softc; 1455 struct adapter *sc = vi->pi->adapter; 1456 struct ifreq *ifr = (struct ifreq *)data; 1457 uint32_t mask; 1458 1459 switch (cmd) { 1460 case SIOCSIFMTU: 1461 mtu = ifr->ifr_mtu; 1462 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) 1463 return (EINVAL); 1464 1465 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1466 if (rc) 1467 return (rc); 1468 ifp->if_mtu = mtu; 1469 if (vi->flags & VI_INIT_DONE) { 1470 t4_update_fl_bufsize(ifp); 1471 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1472 rc = update_mac_settings(ifp, XGMAC_MTU); 1473 } 1474 end_synchronized_op(sc, 0); 1475 break; 1476 1477 case SIOCSIFFLAGS: 1478 can_sleep = 0; 1479 redo_sifflags: 1480 rc = begin_synchronized_op(sc, vi, 1481 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1482 if (rc) 1483 return (rc); 1484 1485 if (ifp->if_flags & IFF_UP) { 1486 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1487 flags = vi->if_flags; 1488 if ((ifp->if_flags ^ flags) & 1489 (IFF_PROMISC | IFF_ALLMULTI)) { 1490 if (can_sleep == 1) { 1491 end_synchronized_op(sc, 0); 1492 can_sleep = 0; 1493 goto redo_sifflags; 1494 } 1495 rc = update_mac_settings(ifp, 1496 XGMAC_PROMISC | XGMAC_ALLMULTI); 1497 } 1498 } else { 1499 if (can_sleep == 0) { 1500 end_synchronized_op(sc, LOCK_HELD); 1501 can_sleep = 1; 1502 goto redo_sifflags; 1503 } 1504 rc = cxgbe_init_synchronized(vi); 1505 } 1506 vi->if_flags = ifp->if_flags; 1507 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1508 if (can_sleep == 0) { 1509 end_synchronized_op(sc, LOCK_HELD); 1510 can_sleep = 1; 1511 goto redo_sifflags; 1512 } 1513 rc = cxgbe_uninit_synchronized(vi); 1514 } 1515 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1516 break; 1517 1518 case SIOCADDMULTI: 1519 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1520 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1521 if (rc) 1522 return (rc); 1523 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1524 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1525 end_synchronized_op(sc, LOCK_HELD); 1526 break; 1527 1528 case SIOCSIFCAP: 1529 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1530 if (rc) 1531 return (rc); 1532 1533 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1534 if (mask & IFCAP_TXCSUM) { 1535 ifp->if_capenable ^= IFCAP_TXCSUM; 1536 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1537 1538 if (IFCAP_TSO4 & ifp->if_capenable && 1539 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1540 ifp->if_capenable &= ~IFCAP_TSO4; 1541 if_printf(ifp, 1542 "tso4 disabled due to -txcsum.\n"); 1543 } 1544 } 1545 if (mask & IFCAP_TXCSUM_IPV6) { 1546 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1547 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1548 1549 if (IFCAP_TSO6 & ifp->if_capenable && 1550 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1551 ifp->if_capenable &= ~IFCAP_TSO6; 1552 if_printf(ifp, 1553 "tso6 disabled due to -txcsum6.\n"); 1554 } 1555 } 1556 if (mask & IFCAP_RXCSUM) 1557 ifp->if_capenable ^= IFCAP_RXCSUM; 1558 if (mask & IFCAP_RXCSUM_IPV6) 1559 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1560 1561 /* 1562 * Note that we leave CSUM_TSO alone (it is always set). The 1563 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1564 * sending a TSO request our way, so it's sufficient to toggle 1565 * IFCAP_TSOx only. 1566 */ 1567 if (mask & IFCAP_TSO4) { 1568 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1569 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1570 if_printf(ifp, "enable txcsum first.\n"); 1571 rc = EAGAIN; 1572 goto fail; 1573 } 1574 ifp->if_capenable ^= IFCAP_TSO4; 1575 } 1576 if (mask & IFCAP_TSO6) { 1577 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1578 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1579 if_printf(ifp, "enable txcsum6 first.\n"); 1580 rc = EAGAIN; 1581 goto fail; 1582 } 1583 ifp->if_capenable ^= IFCAP_TSO6; 1584 } 1585 if (mask & IFCAP_LRO) { 1586 #if defined(INET) || defined(INET6) 1587 int i; 1588 struct sge_rxq *rxq; 1589 1590 ifp->if_capenable ^= IFCAP_LRO; 1591 for_each_rxq(vi, i, rxq) { 1592 if (ifp->if_capenable & IFCAP_LRO) 1593 rxq->iq.flags |= IQ_LRO_ENABLED; 1594 else 1595 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1596 } 1597 #endif 1598 } 1599 #ifdef TCP_OFFLOAD 1600 if (mask & IFCAP_TOE) { 1601 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1602 1603 rc = toe_capability(vi, enable); 1604 if (rc != 0) 1605 goto fail; 1606 1607 ifp->if_capenable ^= mask; 1608 } 1609 #endif 1610 if (mask & IFCAP_VLAN_HWTAGGING) { 1611 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1612 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1613 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1614 } 1615 if (mask & IFCAP_VLAN_MTU) { 1616 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1617 1618 /* Need to find out how to disable auto-mtu-inflation */ 1619 } 1620 if (mask & IFCAP_VLAN_HWTSO) 1621 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1622 if (mask & IFCAP_VLAN_HWCSUM) 1623 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1624 1625 #ifdef VLAN_CAPABILITIES 1626 VLAN_CAPABILITIES(ifp); 1627 #endif 1628 fail: 1629 end_synchronized_op(sc, 0); 1630 break; 1631 1632 case SIOCSIFMEDIA: 1633 case SIOCGIFMEDIA: 1634 ifmedia_ioctl(ifp, ifr, &vi->media, cmd); 1635 break; 1636 1637 case SIOCGI2C: { 1638 struct ifi2creq i2c; 1639 1640 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 1641 if (rc != 0) 1642 break; 1643 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1644 rc = EPERM; 1645 break; 1646 } 1647 if (i2c.len > sizeof(i2c.data)) { 1648 rc = EINVAL; 1649 break; 1650 } 1651 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1652 if (rc) 1653 return (rc); 1654 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr, 1655 i2c.offset, i2c.len, &i2c.data[0]); 1656 end_synchronized_op(sc, 0); 1657 if (rc == 0) 1658 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 1659 break; 1660 } 1661 1662 default: 1663 rc = ether_ioctl(ifp, cmd, data); 1664 } 1665 1666 return (rc); 1667 } 1668 1669 static int 1670 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1671 { 1672 struct vi_info *vi = ifp->if_softc; 1673 struct port_info *pi = vi->pi; 1674 struct adapter *sc = pi->adapter; 1675 struct sge_txq *txq; 1676 void *items[1]; 1677 int rc; 1678 1679 M_ASSERTPKTHDR(m); 1680 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1681 1682 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1683 m_freem(m); 1684 return (ENETDOWN); 1685 } 1686 1687 rc = parse_pkt(sc, &m); 1688 if (__predict_false(rc != 0)) { 1689 MPASS(m == NULL); /* was freed already */ 1690 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1691 return (rc); 1692 } 1693 1694 /* Select a txq. */ 1695 txq = &sc->sge.txq[vi->first_txq]; 1696 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1697 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1698 vi->rsrv_noflowq); 1699 1700 items[0] = m; 1701 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 1702 if (__predict_false(rc != 0)) 1703 m_freem(m); 1704 1705 return (rc); 1706 } 1707 1708 static void 1709 cxgbe_qflush(struct ifnet *ifp) 1710 { 1711 struct vi_info *vi = ifp->if_softc; 1712 struct sge_txq *txq; 1713 int i; 1714 1715 /* queues do not exist if !VI_INIT_DONE. */ 1716 if (vi->flags & VI_INIT_DONE) { 1717 for_each_txq(vi, i, txq) { 1718 TXQ_LOCK(txq); 1719 txq->eq.flags &= ~EQ_ENABLED; 1720 TXQ_UNLOCK(txq); 1721 while (!mp_ring_is_idle(txq->r)) { 1722 mp_ring_check_drainage(txq->r, 0); 1723 pause("qflush", 1); 1724 } 1725 } 1726 } 1727 if_qflush(ifp); 1728 } 1729 1730 static uint64_t 1731 vi_get_counter(struct ifnet *ifp, ift_counter c) 1732 { 1733 struct vi_info *vi = ifp->if_softc; 1734 struct fw_vi_stats_vf *s = &vi->stats; 1735 1736 vi_refresh_stats(vi->pi->adapter, vi); 1737 1738 switch (c) { 1739 case IFCOUNTER_IPACKETS: 1740 return (s->rx_bcast_frames + s->rx_mcast_frames + 1741 s->rx_ucast_frames); 1742 case IFCOUNTER_IERRORS: 1743 return (s->rx_err_frames); 1744 case IFCOUNTER_OPACKETS: 1745 return (s->tx_bcast_frames + s->tx_mcast_frames + 1746 s->tx_ucast_frames + s->tx_offload_frames); 1747 case IFCOUNTER_OERRORS: 1748 return (s->tx_drop_frames); 1749 case IFCOUNTER_IBYTES: 1750 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 1751 s->rx_ucast_bytes); 1752 case IFCOUNTER_OBYTES: 1753 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 1754 s->tx_ucast_bytes + s->tx_offload_bytes); 1755 case IFCOUNTER_IMCASTS: 1756 return (s->rx_mcast_frames); 1757 case IFCOUNTER_OMCASTS: 1758 return (s->tx_mcast_frames); 1759 case IFCOUNTER_OQDROPS: { 1760 uint64_t drops; 1761 1762 drops = 0; 1763 if (vi->flags & VI_INIT_DONE) { 1764 int i; 1765 struct sge_txq *txq; 1766 1767 for_each_txq(vi, i, txq) 1768 drops += counter_u64_fetch(txq->r->drops); 1769 } 1770 1771 return (drops); 1772 1773 } 1774 1775 default: 1776 return (if_get_counter_default(ifp, c)); 1777 } 1778 } 1779 1780 uint64_t 1781 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 1782 { 1783 struct vi_info *vi = ifp->if_softc; 1784 struct port_info *pi = vi->pi; 1785 struct adapter *sc = pi->adapter; 1786 struct port_stats *s = &pi->stats; 1787 1788 if (pi->nvi > 1 || sc->flags & IS_VF) 1789 return (vi_get_counter(ifp, c)); 1790 1791 cxgbe_refresh_stats(sc, pi); 1792 1793 switch (c) { 1794 case IFCOUNTER_IPACKETS: 1795 return (s->rx_frames); 1796 1797 case IFCOUNTER_IERRORS: 1798 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 1799 s->rx_fcs_err + s->rx_len_err); 1800 1801 case IFCOUNTER_OPACKETS: 1802 return (s->tx_frames); 1803 1804 case IFCOUNTER_OERRORS: 1805 return (s->tx_error_frames); 1806 1807 case IFCOUNTER_IBYTES: 1808 return (s->rx_octets); 1809 1810 case IFCOUNTER_OBYTES: 1811 return (s->tx_octets); 1812 1813 case IFCOUNTER_IMCASTS: 1814 return (s->rx_mcast_frames); 1815 1816 case IFCOUNTER_OMCASTS: 1817 return (s->tx_mcast_frames); 1818 1819 case IFCOUNTER_IQDROPS: 1820 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 1821 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 1822 s->rx_trunc3 + pi->tnl_cong_drops); 1823 1824 case IFCOUNTER_OQDROPS: { 1825 uint64_t drops; 1826 1827 drops = s->tx_drop; 1828 if (vi->flags & VI_INIT_DONE) { 1829 int i; 1830 struct sge_txq *txq; 1831 1832 for_each_txq(vi, i, txq) 1833 drops += counter_u64_fetch(txq->r->drops); 1834 } 1835 1836 return (drops); 1837 1838 } 1839 1840 default: 1841 return (if_get_counter_default(ifp, c)); 1842 } 1843 } 1844 1845 static int 1846 cxgbe_media_change(struct ifnet *ifp) 1847 { 1848 struct vi_info *vi = ifp->if_softc; 1849 1850 device_printf(vi->dev, "%s unimplemented.\n", __func__); 1851 1852 return (EOPNOTSUPP); 1853 } 1854 1855 static void 1856 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1857 { 1858 struct vi_info *vi = ifp->if_softc; 1859 struct port_info *pi = vi->pi; 1860 struct ifmedia_entry *cur; 1861 int speed = pi->link_cfg.speed; 1862 1863 cur = vi->media.ifm_cur; 1864 1865 ifmr->ifm_status = IFM_AVALID; 1866 if (!pi->link_cfg.link_ok) 1867 return; 1868 1869 ifmr->ifm_status |= IFM_ACTIVE; 1870 1871 /* active and current will differ iff current media is autoselect. */ 1872 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 1873 return; 1874 1875 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 1876 if (speed == 10000) 1877 ifmr->ifm_active |= IFM_10G_T; 1878 else if (speed == 1000) 1879 ifmr->ifm_active |= IFM_1000_T; 1880 else if (speed == 100) 1881 ifmr->ifm_active |= IFM_100_TX; 1882 else if (speed == 10) 1883 ifmr->ifm_active |= IFM_10_T; 1884 else 1885 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 1886 speed)); 1887 } 1888 1889 static int 1890 vcxgbe_probe(device_t dev) 1891 { 1892 char buf[128]; 1893 struct vi_info *vi = device_get_softc(dev); 1894 1895 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 1896 vi - vi->pi->vi); 1897 device_set_desc_copy(dev, buf); 1898 1899 return (BUS_PROBE_DEFAULT); 1900 } 1901 1902 static int 1903 vcxgbe_attach(device_t dev) 1904 { 1905 struct vi_info *vi; 1906 struct port_info *pi; 1907 struct adapter *sc; 1908 int func, index, rc; 1909 u32 param, val; 1910 1911 vi = device_get_softc(dev); 1912 pi = vi->pi; 1913 sc = pi->adapter; 1914 1915 index = vi - pi->vi; 1916 KASSERT(index < nitems(vi_mac_funcs), 1917 ("%s: VI %s doesn't have a MAC func", __func__, 1918 device_get_nameunit(dev))); 1919 func = vi_mac_funcs[index]; 1920 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 1921 vi->hw_addr, &vi->rss_size, func, 0); 1922 if (rc < 0) { 1923 device_printf(dev, "Failed to allocate virtual interface " 1924 "for port %d: %d\n", pi->port_id, -rc); 1925 return (-rc); 1926 } 1927 vi->viid = rc; 1928 1929 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 1930 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 1931 V_FW_PARAMS_PARAM_YZ(vi->viid); 1932 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 1933 if (rc) 1934 vi->rss_base = 0xffff; 1935 else { 1936 /* MPASS((val >> 16) == rss_size); */ 1937 vi->rss_base = val & 0xffff; 1938 } 1939 1940 rc = cxgbe_vi_attach(dev, vi); 1941 if (rc) { 1942 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 1943 return (rc); 1944 } 1945 return (0); 1946 } 1947 1948 static int 1949 vcxgbe_detach(device_t dev) 1950 { 1951 struct vi_info *vi; 1952 struct adapter *sc; 1953 1954 vi = device_get_softc(dev); 1955 sc = vi->pi->adapter; 1956 1957 doom_vi(sc, vi); 1958 1959 cxgbe_vi_detach(vi); 1960 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 1961 1962 end_synchronized_op(sc, 0); 1963 1964 return (0); 1965 } 1966 1967 void 1968 t4_fatal_err(struct adapter *sc) 1969 { 1970 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 1971 t4_intr_disable(sc); 1972 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 1973 device_get_nameunit(sc->dev)); 1974 } 1975 1976 void 1977 t4_add_adapter(struct adapter *sc) 1978 { 1979 sx_xlock(&t4_list_lock); 1980 SLIST_INSERT_HEAD(&t4_list, sc, link); 1981 sx_xunlock(&t4_list_lock); 1982 } 1983 1984 int 1985 t4_map_bars_0_and_4(struct adapter *sc) 1986 { 1987 sc->regs_rid = PCIR_BAR(0); 1988 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1989 &sc->regs_rid, RF_ACTIVE); 1990 if (sc->regs_res == NULL) { 1991 device_printf(sc->dev, "cannot map registers.\n"); 1992 return (ENXIO); 1993 } 1994 sc->bt = rman_get_bustag(sc->regs_res); 1995 sc->bh = rman_get_bushandle(sc->regs_res); 1996 sc->mmio_len = rman_get_size(sc->regs_res); 1997 setbit(&sc->doorbells, DOORBELL_KDB); 1998 1999 sc->msix_rid = PCIR_BAR(4); 2000 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2001 &sc->msix_rid, RF_ACTIVE); 2002 if (sc->msix_res == NULL) { 2003 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2004 return (ENXIO); 2005 } 2006 2007 return (0); 2008 } 2009 2010 int 2011 t4_map_bar_2(struct adapter *sc) 2012 { 2013 2014 /* 2015 * T4: only iWARP driver uses the userspace doorbells. There is no need 2016 * to map it if RDMA is disabled. 2017 */ 2018 if (is_t4(sc) && sc->rdmacaps == 0) 2019 return (0); 2020 2021 sc->udbs_rid = PCIR_BAR(2); 2022 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2023 &sc->udbs_rid, RF_ACTIVE); 2024 if (sc->udbs_res == NULL) { 2025 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2026 return (ENXIO); 2027 } 2028 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2029 2030 if (chip_id(sc) >= CHELSIO_T5) { 2031 setbit(&sc->doorbells, DOORBELL_UDB); 2032 #if defined(__i386__) || defined(__amd64__) 2033 if (t5_write_combine) { 2034 int rc, mode; 2035 2036 /* 2037 * Enable write combining on BAR2. This is the 2038 * userspace doorbell BAR and is split into 128B 2039 * (UDBS_SEG_SIZE) doorbell regions, each associated 2040 * with an egress queue. The first 64B has the doorbell 2041 * and the second 64B can be used to submit a tx work 2042 * request with an implicit doorbell. 2043 */ 2044 2045 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2046 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2047 if (rc == 0) { 2048 clrbit(&sc->doorbells, DOORBELL_UDB); 2049 setbit(&sc->doorbells, DOORBELL_WCWR); 2050 setbit(&sc->doorbells, DOORBELL_UDBWC); 2051 } else { 2052 device_printf(sc->dev, 2053 "couldn't enable write combining: %d\n", 2054 rc); 2055 } 2056 2057 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2058 t4_write_reg(sc, A_SGE_STAT_CFG, 2059 V_STATSOURCE_T5(7) | mode); 2060 } 2061 #endif 2062 } 2063 2064 return (0); 2065 } 2066 2067 struct memwin_init { 2068 uint32_t base; 2069 uint32_t aperture; 2070 }; 2071 2072 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2073 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2074 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2075 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2076 }; 2077 2078 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2079 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2080 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2081 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2082 }; 2083 2084 static void 2085 setup_memwin(struct adapter *sc) 2086 { 2087 const struct memwin_init *mw_init; 2088 struct memwin *mw; 2089 int i; 2090 uint32_t bar0; 2091 2092 if (is_t4(sc)) { 2093 /* 2094 * Read low 32b of bar0 indirectly via the hardware backdoor 2095 * mechanism. Works from within PCI passthrough environments 2096 * too, where rman_get_start() can return a different value. We 2097 * need to program the T4 memory window decoders with the actual 2098 * addresses that will be coming across the PCIe link. 2099 */ 2100 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2101 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2102 2103 mw_init = &t4_memwin[0]; 2104 } else { 2105 /* T5+ use the relative offset inside the PCIe BAR */ 2106 bar0 = 0; 2107 2108 mw_init = &t5_memwin[0]; 2109 } 2110 2111 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2112 rw_init(&mw->mw_lock, "memory window access"); 2113 mw->mw_base = mw_init->base; 2114 mw->mw_aperture = mw_init->aperture; 2115 mw->mw_curpos = 0; 2116 t4_write_reg(sc, 2117 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2118 (mw->mw_base + bar0) | V_BIR(0) | 2119 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2120 rw_wlock(&mw->mw_lock); 2121 position_memwin(sc, i, 0); 2122 rw_wunlock(&mw->mw_lock); 2123 } 2124 2125 /* flush */ 2126 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2127 } 2128 2129 /* 2130 * Positions the memory window at the given address in the card's address space. 2131 * There are some alignment requirements and the actual position may be at an 2132 * address prior to the requested address. mw->mw_curpos always has the actual 2133 * position of the window. 2134 */ 2135 static void 2136 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2137 { 2138 struct memwin *mw; 2139 uint32_t pf; 2140 uint32_t reg; 2141 2142 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2143 mw = &sc->memwin[idx]; 2144 rw_assert(&mw->mw_lock, RA_WLOCKED); 2145 2146 if (is_t4(sc)) { 2147 pf = 0; 2148 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2149 } else { 2150 pf = V_PFNUM(sc->pf); 2151 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2152 } 2153 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2154 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2155 t4_read_reg(sc, reg); /* flush */ 2156 } 2157 2158 static int 2159 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2160 int len, int rw) 2161 { 2162 struct memwin *mw; 2163 uint32_t mw_end, v; 2164 2165 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2166 2167 /* Memory can only be accessed in naturally aligned 4 byte units */ 2168 if (addr & 3 || len & 3 || len <= 0) 2169 return (EINVAL); 2170 2171 mw = &sc->memwin[idx]; 2172 while (len > 0) { 2173 rw_rlock(&mw->mw_lock); 2174 mw_end = mw->mw_curpos + mw->mw_aperture; 2175 if (addr >= mw_end || addr < mw->mw_curpos) { 2176 /* Will need to reposition the window */ 2177 if (!rw_try_upgrade(&mw->mw_lock)) { 2178 rw_runlock(&mw->mw_lock); 2179 rw_wlock(&mw->mw_lock); 2180 } 2181 rw_assert(&mw->mw_lock, RA_WLOCKED); 2182 position_memwin(sc, idx, addr); 2183 rw_downgrade(&mw->mw_lock); 2184 mw_end = mw->mw_curpos + mw->mw_aperture; 2185 } 2186 rw_assert(&mw->mw_lock, RA_RLOCKED); 2187 while (addr < mw_end && len > 0) { 2188 if (rw == 0) { 2189 v = t4_read_reg(sc, mw->mw_base + addr - 2190 mw->mw_curpos); 2191 *val++ = le32toh(v); 2192 } else { 2193 v = *val++; 2194 t4_write_reg(sc, mw->mw_base + addr - 2195 mw->mw_curpos, htole32(v)); 2196 } 2197 addr += 4; 2198 len -= 4; 2199 } 2200 rw_runlock(&mw->mw_lock); 2201 } 2202 2203 return (0); 2204 } 2205 2206 static inline int 2207 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2208 int len) 2209 { 2210 2211 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 2212 } 2213 2214 static inline int 2215 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 2216 const uint32_t *val, int len) 2217 { 2218 2219 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 2220 } 2221 2222 static int 2223 t4_range_cmp(const void *a, const void *b) 2224 { 2225 return ((const struct t4_range *)a)->start - 2226 ((const struct t4_range *)b)->start; 2227 } 2228 2229 /* 2230 * Verify that the memory range specified by the addr/len pair is valid within 2231 * the card's address space. 2232 */ 2233 static int 2234 validate_mem_range(struct adapter *sc, uint32_t addr, int len) 2235 { 2236 struct t4_range mem_ranges[4], *r, *next; 2237 uint32_t em, addr_len; 2238 int i, n, remaining; 2239 2240 /* Memory can only be accessed in naturally aligned 4 byte units */ 2241 if (addr & 3 || len & 3 || len <= 0) 2242 return (EINVAL); 2243 2244 /* Enabled memories */ 2245 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2246 2247 r = &mem_ranges[0]; 2248 n = 0; 2249 bzero(r, sizeof(mem_ranges)); 2250 if (em & F_EDRAM0_ENABLE) { 2251 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2252 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2253 if (r->size > 0) { 2254 r->start = G_EDRAM0_BASE(addr_len) << 20; 2255 if (addr >= r->start && 2256 addr + len <= r->start + r->size) 2257 return (0); 2258 r++; 2259 n++; 2260 } 2261 } 2262 if (em & F_EDRAM1_ENABLE) { 2263 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2264 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2265 if (r->size > 0) { 2266 r->start = G_EDRAM1_BASE(addr_len) << 20; 2267 if (addr >= r->start && 2268 addr + len <= r->start + r->size) 2269 return (0); 2270 r++; 2271 n++; 2272 } 2273 } 2274 if (em & F_EXT_MEM_ENABLE) { 2275 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2276 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2277 if (r->size > 0) { 2278 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2279 if (addr >= r->start && 2280 addr + len <= r->start + r->size) 2281 return (0); 2282 r++; 2283 n++; 2284 } 2285 } 2286 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2287 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2288 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2289 if (r->size > 0) { 2290 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2291 if (addr >= r->start && 2292 addr + len <= r->start + r->size) 2293 return (0); 2294 r++; 2295 n++; 2296 } 2297 } 2298 MPASS(n <= nitems(mem_ranges)); 2299 2300 if (n > 1) { 2301 /* Sort and merge the ranges. */ 2302 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2303 2304 /* Start from index 0 and examine the next n - 1 entries. */ 2305 r = &mem_ranges[0]; 2306 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2307 2308 MPASS(r->size > 0); /* r is a valid entry. */ 2309 next = r + 1; 2310 MPASS(next->size > 0); /* and so is the next one. */ 2311 2312 while (r->start + r->size >= next->start) { 2313 /* Merge the next one into the current entry. */ 2314 r->size = max(r->start + r->size, 2315 next->start + next->size) - r->start; 2316 n--; /* One fewer entry in total. */ 2317 if (--remaining == 0) 2318 goto done; /* short circuit */ 2319 next++; 2320 } 2321 if (next != r + 1) { 2322 /* 2323 * Some entries were merged into r and next 2324 * points to the first valid entry that couldn't 2325 * be merged. 2326 */ 2327 MPASS(next->size > 0); /* must be valid */ 2328 memcpy(r + 1, next, remaining * sizeof(*r)); 2329 #ifdef INVARIANTS 2330 /* 2331 * This so that the foo->size assertion in the 2332 * next iteration of the loop do the right 2333 * thing for entries that were pulled up and are 2334 * no longer valid. 2335 */ 2336 MPASS(n < nitems(mem_ranges)); 2337 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2338 sizeof(struct t4_range)); 2339 #endif 2340 } 2341 } 2342 done: 2343 /* Done merging the ranges. */ 2344 MPASS(n > 0); 2345 r = &mem_ranges[0]; 2346 for (i = 0; i < n; i++, r++) { 2347 if (addr >= r->start && 2348 addr + len <= r->start + r->size) 2349 return (0); 2350 } 2351 } 2352 2353 return (EFAULT); 2354 } 2355 2356 static int 2357 fwmtype_to_hwmtype(int mtype) 2358 { 2359 2360 switch (mtype) { 2361 case FW_MEMTYPE_EDC0: 2362 return (MEM_EDC0); 2363 case FW_MEMTYPE_EDC1: 2364 return (MEM_EDC1); 2365 case FW_MEMTYPE_EXTMEM: 2366 return (MEM_MC0); 2367 case FW_MEMTYPE_EXTMEM1: 2368 return (MEM_MC1); 2369 default: 2370 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2371 } 2372 } 2373 2374 /* 2375 * Verify that the memory range specified by the memtype/offset/len pair is 2376 * valid and lies entirely within the memtype specified. The global address of 2377 * the start of the range is returned in addr. 2378 */ 2379 static int 2380 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 2381 uint32_t *addr) 2382 { 2383 uint32_t em, addr_len, maddr; 2384 2385 /* Memory can only be accessed in naturally aligned 4 byte units */ 2386 if (off & 3 || len & 3 || len == 0) 2387 return (EINVAL); 2388 2389 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2390 switch (fwmtype_to_hwmtype(mtype)) { 2391 case MEM_EDC0: 2392 if (!(em & F_EDRAM0_ENABLE)) 2393 return (EINVAL); 2394 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2395 maddr = G_EDRAM0_BASE(addr_len) << 20; 2396 break; 2397 case MEM_EDC1: 2398 if (!(em & F_EDRAM1_ENABLE)) 2399 return (EINVAL); 2400 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2401 maddr = G_EDRAM1_BASE(addr_len) << 20; 2402 break; 2403 case MEM_MC: 2404 if (!(em & F_EXT_MEM_ENABLE)) 2405 return (EINVAL); 2406 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2407 maddr = G_EXT_MEM_BASE(addr_len) << 20; 2408 break; 2409 case MEM_MC1: 2410 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 2411 return (EINVAL); 2412 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2413 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 2414 break; 2415 default: 2416 return (EINVAL); 2417 } 2418 2419 *addr = maddr + off; /* global address */ 2420 return (validate_mem_range(sc, *addr, len)); 2421 } 2422 2423 static int 2424 fixup_devlog_params(struct adapter *sc) 2425 { 2426 struct devlog_params *dparams = &sc->params.devlog; 2427 int rc; 2428 2429 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 2430 dparams->size, &dparams->addr); 2431 2432 return (rc); 2433 } 2434 2435 static int 2436 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis, 2437 struct intrs_and_queues *iaq) 2438 { 2439 int rc, itype, navail, nrxq10g, nrxq1g, n; 2440 int nofldrxq10g = 0, nofldrxq1g = 0; 2441 2442 bzero(iaq, sizeof(*iaq)); 2443 2444 iaq->ntxq10g = t4_ntxq10g; 2445 iaq->ntxq1g = t4_ntxq1g; 2446 iaq->ntxq_vi = t4_ntxq_vi; 2447 iaq->nrxq10g = nrxq10g = t4_nrxq10g; 2448 iaq->nrxq1g = nrxq1g = t4_nrxq1g; 2449 iaq->nrxq_vi = t4_nrxq_vi; 2450 iaq->rsrv_noflowq = t4_rsrv_noflowq; 2451 #ifdef TCP_OFFLOAD 2452 if (is_offload(sc)) { 2453 iaq->nofldtxq10g = t4_nofldtxq10g; 2454 iaq->nofldtxq1g = t4_nofldtxq1g; 2455 iaq->nofldtxq_vi = t4_nofldtxq_vi; 2456 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g; 2457 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g; 2458 iaq->nofldrxq_vi = t4_nofldrxq_vi; 2459 } 2460 #endif 2461 #ifdef DEV_NETMAP 2462 iaq->nnmtxq_vi = t4_nnmtxq_vi; 2463 iaq->nnmrxq_vi = t4_nnmrxq_vi; 2464 #endif 2465 2466 for (itype = INTR_MSIX; itype; itype >>= 1) { 2467 2468 if ((itype & t4_intr_types) == 0) 2469 continue; /* not allowed */ 2470 2471 if (itype == INTR_MSIX) 2472 navail = pci_msix_count(sc->dev); 2473 else if (itype == INTR_MSI) 2474 navail = pci_msi_count(sc->dev); 2475 else 2476 navail = 1; 2477 restart: 2478 if (navail == 0) 2479 continue; 2480 2481 iaq->intr_type = itype; 2482 iaq->intr_flags_10g = 0; 2483 iaq->intr_flags_1g = 0; 2484 2485 /* 2486 * Best option: an interrupt vector for errors, one for the 2487 * firmware event queue, and one for every rxq (NIC and TOE) of 2488 * every VI. The VIs that support netmap use the same 2489 * interrupts for the NIC rx queues and the netmap rx queues 2490 * because only one set of queues is active at a time. 2491 */ 2492 iaq->nirq = T4_EXTRA_INTR; 2493 iaq->nirq += n10g * (nrxq10g + nofldrxq10g); 2494 iaq->nirq += n1g * (nrxq1g + nofldrxq1g); 2495 iaq->nirq += (n10g + n1g) * (num_vis - 1) * 2496 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */ 2497 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi; 2498 if (iaq->nirq <= navail && 2499 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2500 iaq->intr_flags_10g = INTR_ALL; 2501 iaq->intr_flags_1g = INTR_ALL; 2502 goto allocate; 2503 } 2504 2505 /* Disable the VIs (and netmap) if there aren't enough intrs */ 2506 if (num_vis > 1) { 2507 device_printf(sc->dev, "virtual interfaces disabled " 2508 "because num_vis=%u with current settings " 2509 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, " 2510 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, " 2511 "nnmrxq_vi=%u) would need %u interrupts but " 2512 "only %u are available.\n", num_vis, nrxq10g, 2513 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi, 2514 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq, 2515 navail); 2516 num_vis = 1; 2517 iaq->ntxq_vi = iaq->nrxq_vi = 0; 2518 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 2519 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 2520 goto restart; 2521 } 2522 2523 /* 2524 * Second best option: a vector for errors, one for the firmware 2525 * event queue, and vectors for either all the NIC rx queues or 2526 * all the TOE rx queues. The queues that don't get vectors 2527 * will forward their interrupts to those that do. 2528 */ 2529 iaq->nirq = T4_EXTRA_INTR; 2530 if (nrxq10g >= nofldrxq10g) { 2531 iaq->intr_flags_10g = INTR_RXQ; 2532 iaq->nirq += n10g * nrxq10g; 2533 } else { 2534 iaq->intr_flags_10g = INTR_OFLD_RXQ; 2535 iaq->nirq += n10g * nofldrxq10g; 2536 } 2537 if (nrxq1g >= nofldrxq1g) { 2538 iaq->intr_flags_1g = INTR_RXQ; 2539 iaq->nirq += n1g * nrxq1g; 2540 } else { 2541 iaq->intr_flags_1g = INTR_OFLD_RXQ; 2542 iaq->nirq += n1g * nofldrxq1g; 2543 } 2544 if (iaq->nirq <= navail && 2545 (itype != INTR_MSI || powerof2(iaq->nirq))) 2546 goto allocate; 2547 2548 /* 2549 * Next best option: an interrupt vector for errors, one for the 2550 * firmware event queue, and at least one per main-VI. At this 2551 * point we know we'll have to downsize nrxq and/or nofldrxq to 2552 * fit what's available to us. 2553 */ 2554 iaq->nirq = T4_EXTRA_INTR; 2555 iaq->nirq += n10g + n1g; 2556 if (iaq->nirq <= navail) { 2557 int leftover = navail - iaq->nirq; 2558 2559 if (n10g > 0) { 2560 int target = max(nrxq10g, nofldrxq10g); 2561 2562 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ? 2563 INTR_RXQ : INTR_OFLD_RXQ; 2564 2565 n = 1; 2566 while (n < target && leftover >= n10g) { 2567 leftover -= n10g; 2568 iaq->nirq += n10g; 2569 n++; 2570 } 2571 iaq->nrxq10g = min(n, nrxq10g); 2572 #ifdef TCP_OFFLOAD 2573 iaq->nofldrxq10g = min(n, nofldrxq10g); 2574 #endif 2575 } 2576 2577 if (n1g > 0) { 2578 int target = max(nrxq1g, nofldrxq1g); 2579 2580 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ? 2581 INTR_RXQ : INTR_OFLD_RXQ; 2582 2583 n = 1; 2584 while (n < target && leftover >= n1g) { 2585 leftover -= n1g; 2586 iaq->nirq += n1g; 2587 n++; 2588 } 2589 iaq->nrxq1g = min(n, nrxq1g); 2590 #ifdef TCP_OFFLOAD 2591 iaq->nofldrxq1g = min(n, nofldrxq1g); 2592 #endif 2593 } 2594 2595 if (itype != INTR_MSI || powerof2(iaq->nirq)) 2596 goto allocate; 2597 } 2598 2599 /* 2600 * Least desirable option: one interrupt vector for everything. 2601 */ 2602 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1; 2603 iaq->intr_flags_10g = iaq->intr_flags_1g = 0; 2604 #ifdef TCP_OFFLOAD 2605 if (is_offload(sc)) 2606 iaq->nofldrxq10g = iaq->nofldrxq1g = 1; 2607 #endif 2608 allocate: 2609 navail = iaq->nirq; 2610 rc = 0; 2611 if (itype == INTR_MSIX) 2612 rc = pci_alloc_msix(sc->dev, &navail); 2613 else if (itype == INTR_MSI) 2614 rc = pci_alloc_msi(sc->dev, &navail); 2615 2616 if (rc == 0) { 2617 if (navail == iaq->nirq) 2618 return (0); 2619 2620 /* 2621 * Didn't get the number requested. Use whatever number 2622 * the kernel is willing to allocate (it's in navail). 2623 */ 2624 device_printf(sc->dev, "fewer vectors than requested, " 2625 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 2626 itype, iaq->nirq, navail); 2627 pci_release_msi(sc->dev); 2628 goto restart; 2629 } 2630 2631 device_printf(sc->dev, 2632 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 2633 itype, rc, iaq->nirq, navail); 2634 } 2635 2636 device_printf(sc->dev, 2637 "failed to find a usable interrupt type. " 2638 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 2639 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 2640 2641 return (ENXIO); 2642 } 2643 2644 #define FW_VERSION(chip) ( \ 2645 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 2646 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 2647 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 2648 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 2649 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 2650 2651 struct fw_info { 2652 uint8_t chip; 2653 char *kld_name; 2654 char *fw_mod_name; 2655 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 2656 } fw_info[] = { 2657 { 2658 .chip = CHELSIO_T4, 2659 .kld_name = "t4fw_cfg", 2660 .fw_mod_name = "t4fw", 2661 .fw_hdr = { 2662 .chip = FW_HDR_CHIP_T4, 2663 .fw_ver = htobe32_const(FW_VERSION(T4)), 2664 .intfver_nic = FW_INTFVER(T4, NIC), 2665 .intfver_vnic = FW_INTFVER(T4, VNIC), 2666 .intfver_ofld = FW_INTFVER(T4, OFLD), 2667 .intfver_ri = FW_INTFVER(T4, RI), 2668 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 2669 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 2670 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 2671 .intfver_fcoe = FW_INTFVER(T4, FCOE), 2672 }, 2673 }, { 2674 .chip = CHELSIO_T5, 2675 .kld_name = "t5fw_cfg", 2676 .fw_mod_name = "t5fw", 2677 .fw_hdr = { 2678 .chip = FW_HDR_CHIP_T5, 2679 .fw_ver = htobe32_const(FW_VERSION(T5)), 2680 .intfver_nic = FW_INTFVER(T5, NIC), 2681 .intfver_vnic = FW_INTFVER(T5, VNIC), 2682 .intfver_ofld = FW_INTFVER(T5, OFLD), 2683 .intfver_ri = FW_INTFVER(T5, RI), 2684 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 2685 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 2686 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 2687 .intfver_fcoe = FW_INTFVER(T5, FCOE), 2688 }, 2689 } 2690 }; 2691 2692 static struct fw_info * 2693 find_fw_info(int chip) 2694 { 2695 int i; 2696 2697 for (i = 0; i < nitems(fw_info); i++) { 2698 if (fw_info[i].chip == chip) 2699 return (&fw_info[i]); 2700 } 2701 return (NULL); 2702 } 2703 2704 /* 2705 * Is the given firmware API compatible with the one the driver was compiled 2706 * with? 2707 */ 2708 static int 2709 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 2710 { 2711 2712 /* short circuit if it's the exact same firmware version */ 2713 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 2714 return (1); 2715 2716 /* 2717 * XXX: Is this too conservative? Perhaps I should limit this to the 2718 * features that are supported in the driver. 2719 */ 2720 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 2721 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 2722 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 2723 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 2724 return (1); 2725 #undef SAME_INTF 2726 2727 return (0); 2728 } 2729 2730 /* 2731 * The firmware in the KLD is usable, but should it be installed? This routine 2732 * explains itself in detail if it indicates the KLD firmware should be 2733 * installed. 2734 */ 2735 static int 2736 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 2737 { 2738 const char *reason; 2739 2740 if (!card_fw_usable) { 2741 reason = "incompatible or unusable"; 2742 goto install; 2743 } 2744 2745 if (k > c) { 2746 reason = "older than the version bundled with this driver"; 2747 goto install; 2748 } 2749 2750 if (t4_fw_install == 2 && k != c) { 2751 reason = "different than the version bundled with this driver"; 2752 goto install; 2753 } 2754 2755 return (0); 2756 2757 install: 2758 if (t4_fw_install == 0) { 2759 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2760 "but the driver is prohibited from installing a different " 2761 "firmware on the card.\n", 2762 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2763 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 2764 2765 return (0); 2766 } 2767 2768 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2769 "installing firmware %u.%u.%u.%u on card.\n", 2770 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2771 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 2772 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 2773 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 2774 2775 return (1); 2776 } 2777 /* 2778 * Establish contact with the firmware and determine if we are the master driver 2779 * or not, and whether we are responsible for chip initialization. 2780 */ 2781 static int 2782 prep_firmware(struct adapter *sc) 2783 { 2784 const struct firmware *fw = NULL, *default_cfg; 2785 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 2786 enum dev_state state; 2787 struct fw_info *fw_info; 2788 struct fw_hdr *card_fw; /* fw on the card */ 2789 const struct fw_hdr *kld_fw; /* fw in the KLD */ 2790 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 2791 against */ 2792 2793 /* Contact firmware. */ 2794 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 2795 if (rc < 0 || state == DEV_STATE_ERR) { 2796 rc = -rc; 2797 device_printf(sc->dev, 2798 "failed to connect to the firmware: %d, %d.\n", rc, state); 2799 return (rc); 2800 } 2801 pf = rc; 2802 if (pf == sc->mbox) 2803 sc->flags |= MASTER_PF; 2804 else if (state == DEV_STATE_UNINIT) { 2805 /* 2806 * We didn't get to be the master so we definitely won't be 2807 * configuring the chip. It's a bug if someone else hasn't 2808 * configured it already. 2809 */ 2810 device_printf(sc->dev, "couldn't be master(%d), " 2811 "device not already initialized either(%d).\n", rc, state); 2812 return (EDOOFUS); 2813 } 2814 2815 /* This is the firmware whose headers the driver was compiled against */ 2816 fw_info = find_fw_info(chip_id(sc)); 2817 if (fw_info == NULL) { 2818 device_printf(sc->dev, 2819 "unable to look up firmware information for chip %d.\n", 2820 chip_id(sc)); 2821 return (EINVAL); 2822 } 2823 drv_fw = &fw_info->fw_hdr; 2824 2825 /* 2826 * The firmware KLD contains many modules. The KLD name is also the 2827 * name of the module that contains the default config file. 2828 */ 2829 default_cfg = firmware_get(fw_info->kld_name); 2830 2831 /* Read the header of the firmware on the card */ 2832 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 2833 rc = -t4_read_flash(sc, FLASH_FW_START, 2834 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 2835 if (rc == 0) 2836 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 2837 else { 2838 device_printf(sc->dev, 2839 "Unable to read card's firmware header: %d\n", rc); 2840 card_fw_usable = 0; 2841 } 2842 2843 /* This is the firmware in the KLD */ 2844 fw = firmware_get(fw_info->fw_mod_name); 2845 if (fw != NULL) { 2846 kld_fw = (const void *)fw->data; 2847 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 2848 } else { 2849 kld_fw = NULL; 2850 kld_fw_usable = 0; 2851 } 2852 2853 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 2854 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 2855 /* 2856 * Common case: the firmware on the card is an exact match and 2857 * the KLD is an exact match too, or the KLD is 2858 * absent/incompatible. Note that t4_fw_install = 2 is ignored 2859 * here -- use cxgbetool loadfw if you want to reinstall the 2860 * same firmware as the one on the card. 2861 */ 2862 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 2863 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 2864 be32toh(card_fw->fw_ver))) { 2865 2866 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 2867 if (rc != 0) { 2868 device_printf(sc->dev, 2869 "failed to install firmware: %d\n", rc); 2870 goto done; 2871 } 2872 2873 /* Installed successfully, update the cached header too. */ 2874 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 2875 card_fw_usable = 1; 2876 need_fw_reset = 0; /* already reset as part of load_fw */ 2877 } 2878 2879 if (!card_fw_usable) { 2880 uint32_t d, c, k; 2881 2882 d = ntohl(drv_fw->fw_ver); 2883 c = ntohl(card_fw->fw_ver); 2884 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 2885 2886 device_printf(sc->dev, "Cannot find a usable firmware: " 2887 "fw_install %d, chip state %d, " 2888 "driver compiled with %d.%d.%d.%d, " 2889 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 2890 t4_fw_install, state, 2891 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 2892 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 2893 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2894 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 2895 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 2896 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 2897 rc = EINVAL; 2898 goto done; 2899 } 2900 2901 /* Reset device */ 2902 if (need_fw_reset && 2903 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 2904 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 2905 if (rc != ETIMEDOUT && rc != EIO) 2906 t4_fw_bye(sc, sc->mbox); 2907 goto done; 2908 } 2909 sc->flags |= FW_OK; 2910 2911 rc = get_params__pre_init(sc); 2912 if (rc != 0) 2913 goto done; /* error message displayed already */ 2914 2915 /* Partition adapter resources as specified in the config file. */ 2916 if (state == DEV_STATE_UNINIT) { 2917 2918 KASSERT(sc->flags & MASTER_PF, 2919 ("%s: trying to change chip settings when not master.", 2920 __func__)); 2921 2922 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 2923 if (rc != 0) 2924 goto done; /* error message displayed already */ 2925 2926 t4_tweak_chip_settings(sc); 2927 2928 /* get basic stuff going */ 2929 rc = -t4_fw_initialize(sc, sc->mbox); 2930 if (rc != 0) { 2931 device_printf(sc->dev, "fw init failed: %d.\n", rc); 2932 goto done; 2933 } 2934 } else { 2935 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 2936 sc->cfcsum = 0; 2937 } 2938 2939 done: 2940 free(card_fw, M_CXGBE); 2941 if (fw != NULL) 2942 firmware_put(fw, FIRMWARE_UNLOAD); 2943 if (default_cfg != NULL) 2944 firmware_put(default_cfg, FIRMWARE_UNLOAD); 2945 2946 return (rc); 2947 } 2948 2949 #define FW_PARAM_DEV(param) \ 2950 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 2951 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 2952 #define FW_PARAM_PFVF(param) \ 2953 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 2954 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 2955 2956 /* 2957 * Partition chip resources for use between various PFs, VFs, etc. 2958 */ 2959 static int 2960 partition_resources(struct adapter *sc, const struct firmware *default_cfg, 2961 const char *name_prefix) 2962 { 2963 const struct firmware *cfg = NULL; 2964 int rc = 0; 2965 struct fw_caps_config_cmd caps; 2966 uint32_t mtype, moff, finicsum, cfcsum; 2967 2968 /* 2969 * Figure out what configuration file to use. Pick the default config 2970 * file for the card if the user hasn't specified one explicitly. 2971 */ 2972 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 2973 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 2974 /* Card specific overrides go here. */ 2975 if (pci_get_device(sc->dev) == 0x440a) 2976 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 2977 if (is_fpga(sc)) 2978 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 2979 } 2980 2981 /* 2982 * We need to load another module if the profile is anything except 2983 * "default" or "flash". 2984 */ 2985 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 2986 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 2987 char s[32]; 2988 2989 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 2990 cfg = firmware_get(s); 2991 if (cfg == NULL) { 2992 if (default_cfg != NULL) { 2993 device_printf(sc->dev, 2994 "unable to load module \"%s\" for " 2995 "configuration profile \"%s\", will use " 2996 "the default config file instead.\n", 2997 s, sc->cfg_file); 2998 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 2999 "%s", DEFAULT_CF); 3000 } else { 3001 device_printf(sc->dev, 3002 "unable to load module \"%s\" for " 3003 "configuration profile \"%s\", will use " 3004 "the config file on the card's flash " 3005 "instead.\n", s, sc->cfg_file); 3006 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3007 "%s", FLASH_CF); 3008 } 3009 } 3010 } 3011 3012 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3013 default_cfg == NULL) { 3014 device_printf(sc->dev, 3015 "default config file not available, will use the config " 3016 "file on the card's flash instead.\n"); 3017 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3018 } 3019 3020 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3021 u_int cflen; 3022 const uint32_t *cfdata; 3023 uint32_t param, val, addr; 3024 3025 KASSERT(cfg != NULL || default_cfg != NULL, 3026 ("%s: no config to upload", __func__)); 3027 3028 /* 3029 * Ask the firmware where it wants us to upload the config file. 3030 */ 3031 param = FW_PARAM_DEV(CF); 3032 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3033 if (rc != 0) { 3034 /* No support for config file? Shouldn't happen. */ 3035 device_printf(sc->dev, 3036 "failed to query config file location: %d.\n", rc); 3037 goto done; 3038 } 3039 mtype = G_FW_PARAMS_PARAM_Y(val); 3040 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3041 3042 /* 3043 * XXX: sheer laziness. We deliberately added 4 bytes of 3044 * useless stuffing/comments at the end of the config file so 3045 * it's ok to simply throw away the last remaining bytes when 3046 * the config file is not an exact multiple of 4. This also 3047 * helps with the validate_mt_off_len check. 3048 */ 3049 if (cfg != NULL) { 3050 cflen = cfg->datasize & ~3; 3051 cfdata = cfg->data; 3052 } else { 3053 cflen = default_cfg->datasize & ~3; 3054 cfdata = default_cfg->data; 3055 } 3056 3057 if (cflen > FLASH_CFG_MAX_SIZE) { 3058 device_printf(sc->dev, 3059 "config file too long (%d, max allowed is %d). " 3060 "Will try to use the config on the card, if any.\n", 3061 cflen, FLASH_CFG_MAX_SIZE); 3062 goto use_config_on_flash; 3063 } 3064 3065 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3066 if (rc != 0) { 3067 device_printf(sc->dev, 3068 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3069 "Will try to use the config on the card, if any.\n", 3070 __func__, mtype, moff, cflen, rc); 3071 goto use_config_on_flash; 3072 } 3073 write_via_memwin(sc, 2, addr, cfdata, cflen); 3074 } else { 3075 use_config_on_flash: 3076 mtype = FW_MEMTYPE_FLASH; 3077 moff = t4_flash_cfg_addr(sc); 3078 } 3079 3080 bzero(&caps, sizeof(caps)); 3081 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3082 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3083 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3084 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3085 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3086 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3087 if (rc != 0) { 3088 device_printf(sc->dev, 3089 "failed to pre-process config file: %d " 3090 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3091 goto done; 3092 } 3093 3094 finicsum = be32toh(caps.finicsum); 3095 cfcsum = be32toh(caps.cfcsum); 3096 if (finicsum != cfcsum) { 3097 device_printf(sc->dev, 3098 "WARNING: config file checksum mismatch: %08x %08x\n", 3099 finicsum, cfcsum); 3100 } 3101 sc->cfcsum = cfcsum; 3102 3103 #define LIMIT_CAPS(x) do { \ 3104 caps.x &= htobe16(t4_##x##_allowed); \ 3105 } while (0) 3106 3107 /* 3108 * Let the firmware know what features will (not) be used so it can tune 3109 * things accordingly. 3110 */ 3111 LIMIT_CAPS(nbmcaps); 3112 LIMIT_CAPS(linkcaps); 3113 LIMIT_CAPS(switchcaps); 3114 LIMIT_CAPS(niccaps); 3115 LIMIT_CAPS(toecaps); 3116 LIMIT_CAPS(rdmacaps); 3117 LIMIT_CAPS(cryptocaps); 3118 LIMIT_CAPS(iscsicaps); 3119 LIMIT_CAPS(fcoecaps); 3120 #undef LIMIT_CAPS 3121 3122 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3123 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3124 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3125 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3126 if (rc != 0) { 3127 device_printf(sc->dev, 3128 "failed to process config file: %d.\n", rc); 3129 } 3130 done: 3131 if (cfg != NULL) 3132 firmware_put(cfg, FIRMWARE_UNLOAD); 3133 return (rc); 3134 } 3135 3136 /* 3137 * Retrieve parameters that are needed (or nice to have) very early. 3138 */ 3139 static int 3140 get_params__pre_init(struct adapter *sc) 3141 { 3142 int rc; 3143 uint32_t param[2], val[2]; 3144 3145 t4_get_version_info(sc); 3146 3147 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3148 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3149 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3150 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3151 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3152 3153 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3154 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3155 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3156 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3157 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3158 3159 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3160 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3161 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3162 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3163 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3164 3165 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3166 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3167 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3168 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3169 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3170 3171 param[0] = FW_PARAM_DEV(PORTVEC); 3172 param[1] = FW_PARAM_DEV(CCLK); 3173 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3174 if (rc != 0) { 3175 device_printf(sc->dev, 3176 "failed to query parameters (pre_init): %d.\n", rc); 3177 return (rc); 3178 } 3179 3180 sc->params.portvec = val[0]; 3181 sc->params.nports = bitcount32(val[0]); 3182 sc->params.vpd.cclk = val[1]; 3183 3184 /* Read device log parameters. */ 3185 rc = -t4_init_devlog_params(sc, 1); 3186 if (rc == 0) 3187 fixup_devlog_params(sc); 3188 else { 3189 device_printf(sc->dev, 3190 "failed to get devlog parameters: %d.\n", rc); 3191 rc = 0; /* devlog isn't critical for device operation */ 3192 } 3193 3194 return (rc); 3195 } 3196 3197 /* 3198 * Retrieve various parameters that are of interest to the driver. The device 3199 * has been initialized by the firmware at this point. 3200 */ 3201 static int 3202 get_params__post_init(struct adapter *sc) 3203 { 3204 int rc; 3205 uint32_t param[7], val[7]; 3206 struct fw_caps_config_cmd caps; 3207 3208 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3209 param[1] = FW_PARAM_PFVF(EQ_START); 3210 param[2] = FW_PARAM_PFVF(FILTER_START); 3211 param[3] = FW_PARAM_PFVF(FILTER_END); 3212 param[4] = FW_PARAM_PFVF(L2T_START); 3213 param[5] = FW_PARAM_PFVF(L2T_END); 3214 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3215 if (rc != 0) { 3216 device_printf(sc->dev, 3217 "failed to query parameters (post_init): %d.\n", rc); 3218 return (rc); 3219 } 3220 3221 sc->sge.iq_start = val[0]; 3222 sc->sge.eq_start = val[1]; 3223 sc->tids.ftid_base = val[2]; 3224 sc->tids.nftids = val[3] - val[2] + 1; 3225 sc->params.ftid_min = val[2]; 3226 sc->params.ftid_max = val[3]; 3227 sc->vres.l2t.start = val[4]; 3228 sc->vres.l2t.size = val[5] - val[4] + 1; 3229 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3230 ("%s: L2 table size (%u) larger than expected (%u)", 3231 __func__, sc->vres.l2t.size, L2T_SIZE)); 3232 3233 /* get capabilites */ 3234 bzero(&caps, sizeof(caps)); 3235 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3236 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3237 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3238 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3239 if (rc != 0) { 3240 device_printf(sc->dev, 3241 "failed to get card capabilities: %d.\n", rc); 3242 return (rc); 3243 } 3244 3245 #define READ_CAPS(x) do { \ 3246 sc->x = htobe16(caps.x); \ 3247 } while (0) 3248 READ_CAPS(nbmcaps); 3249 READ_CAPS(linkcaps); 3250 READ_CAPS(switchcaps); 3251 READ_CAPS(niccaps); 3252 READ_CAPS(toecaps); 3253 READ_CAPS(rdmacaps); 3254 READ_CAPS(cryptocaps); 3255 READ_CAPS(iscsicaps); 3256 READ_CAPS(fcoecaps); 3257 3258 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 3259 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 3260 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 3261 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3262 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 3263 if (rc != 0) { 3264 device_printf(sc->dev, 3265 "failed to query NIC parameters: %d.\n", rc); 3266 return (rc); 3267 } 3268 sc->tids.etid_base = val[0]; 3269 sc->params.etid_min = val[0]; 3270 sc->tids.netids = val[1] - val[0] + 1; 3271 sc->params.netids = sc->tids.netids; 3272 sc->params.eo_wr_cred = val[2]; 3273 sc->params.ethoffload = 1; 3274 } 3275 3276 if (sc->toecaps) { 3277 /* query offload-related parameters */ 3278 param[0] = FW_PARAM_DEV(NTID); 3279 param[1] = FW_PARAM_PFVF(SERVER_START); 3280 param[2] = FW_PARAM_PFVF(SERVER_END); 3281 param[3] = FW_PARAM_PFVF(TDDP_START); 3282 param[4] = FW_PARAM_PFVF(TDDP_END); 3283 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3284 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3285 if (rc != 0) { 3286 device_printf(sc->dev, 3287 "failed to query TOE parameters: %d.\n", rc); 3288 return (rc); 3289 } 3290 sc->tids.ntids = val[0]; 3291 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3292 sc->tids.stid_base = val[1]; 3293 sc->tids.nstids = val[2] - val[1] + 1; 3294 sc->vres.ddp.start = val[3]; 3295 sc->vres.ddp.size = val[4] - val[3] + 1; 3296 sc->params.ofldq_wr_cred = val[5]; 3297 sc->params.offload = 1; 3298 } 3299 if (sc->rdmacaps) { 3300 param[0] = FW_PARAM_PFVF(STAG_START); 3301 param[1] = FW_PARAM_PFVF(STAG_END); 3302 param[2] = FW_PARAM_PFVF(RQ_START); 3303 param[3] = FW_PARAM_PFVF(RQ_END); 3304 param[4] = FW_PARAM_PFVF(PBL_START); 3305 param[5] = FW_PARAM_PFVF(PBL_END); 3306 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3307 if (rc != 0) { 3308 device_printf(sc->dev, 3309 "failed to query RDMA parameters(1): %d.\n", rc); 3310 return (rc); 3311 } 3312 sc->vres.stag.start = val[0]; 3313 sc->vres.stag.size = val[1] - val[0] + 1; 3314 sc->vres.rq.start = val[2]; 3315 sc->vres.rq.size = val[3] - val[2] + 1; 3316 sc->vres.pbl.start = val[4]; 3317 sc->vres.pbl.size = val[5] - val[4] + 1; 3318 3319 param[0] = FW_PARAM_PFVF(SQRQ_START); 3320 param[1] = FW_PARAM_PFVF(SQRQ_END); 3321 param[2] = FW_PARAM_PFVF(CQ_START); 3322 param[3] = FW_PARAM_PFVF(CQ_END); 3323 param[4] = FW_PARAM_PFVF(OCQ_START); 3324 param[5] = FW_PARAM_PFVF(OCQ_END); 3325 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3326 if (rc != 0) { 3327 device_printf(sc->dev, 3328 "failed to query RDMA parameters(2): %d.\n", rc); 3329 return (rc); 3330 } 3331 sc->vres.qp.start = val[0]; 3332 sc->vres.qp.size = val[1] - val[0] + 1; 3333 sc->vres.cq.start = val[2]; 3334 sc->vres.cq.size = val[3] - val[2] + 1; 3335 sc->vres.ocq.start = val[4]; 3336 sc->vres.ocq.size = val[5] - val[4] + 1; 3337 } 3338 if (sc->iscsicaps) { 3339 param[0] = FW_PARAM_PFVF(ISCSI_START); 3340 param[1] = FW_PARAM_PFVF(ISCSI_END); 3341 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3342 if (rc != 0) { 3343 device_printf(sc->dev, 3344 "failed to query iSCSI parameters: %d.\n", rc); 3345 return (rc); 3346 } 3347 sc->vres.iscsi.start = val[0]; 3348 sc->vres.iscsi.size = val[1] - val[0] + 1; 3349 } 3350 3351 t4_init_sge_params(sc); 3352 3353 /* 3354 * We've got the params we wanted to query via the firmware. Now grab 3355 * some others directly from the chip. 3356 */ 3357 rc = t4_read_chip_settings(sc); 3358 3359 return (rc); 3360 } 3361 3362 static int 3363 set_params__post_init(struct adapter *sc) 3364 { 3365 uint32_t param, val; 3366 3367 /* ask for encapsulated CPLs */ 3368 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3369 val = 1; 3370 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3371 3372 return (0); 3373 } 3374 3375 #undef FW_PARAM_PFVF 3376 #undef FW_PARAM_DEV 3377 3378 static void 3379 t4_set_desc(struct adapter *sc) 3380 { 3381 char buf[128]; 3382 struct adapter_params *p = &sc->params; 3383 3384 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 3385 3386 device_set_desc_copy(sc->dev, buf); 3387 } 3388 3389 static void 3390 build_medialist(struct port_info *pi, struct ifmedia *media) 3391 { 3392 int m; 3393 3394 PORT_LOCK(pi); 3395 3396 ifmedia_removeall(media); 3397 3398 m = IFM_ETHER | IFM_FDX; 3399 3400 switch(pi->port_type) { 3401 case FW_PORT_TYPE_BT_XFI: 3402 case FW_PORT_TYPE_BT_XAUI: 3403 ifmedia_add(media, m | IFM_10G_T, 0, NULL); 3404 /* fall through */ 3405 3406 case FW_PORT_TYPE_BT_SGMII: 3407 ifmedia_add(media, m | IFM_1000_T, 0, NULL); 3408 ifmedia_add(media, m | IFM_100_TX, 0, NULL); 3409 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL); 3410 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 3411 break; 3412 3413 case FW_PORT_TYPE_CX4: 3414 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL); 3415 ifmedia_set(media, m | IFM_10G_CX4); 3416 break; 3417 3418 case FW_PORT_TYPE_QSFP_10G: 3419 case FW_PORT_TYPE_SFP: 3420 case FW_PORT_TYPE_FIBER_XFI: 3421 case FW_PORT_TYPE_FIBER_XAUI: 3422 switch (pi->mod_type) { 3423 3424 case FW_PORT_MOD_TYPE_LR: 3425 ifmedia_add(media, m | IFM_10G_LR, 0, NULL); 3426 ifmedia_set(media, m | IFM_10G_LR); 3427 break; 3428 3429 case FW_PORT_MOD_TYPE_SR: 3430 ifmedia_add(media, m | IFM_10G_SR, 0, NULL); 3431 ifmedia_set(media, m | IFM_10G_SR); 3432 break; 3433 3434 case FW_PORT_MOD_TYPE_LRM: 3435 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL); 3436 ifmedia_set(media, m | IFM_10G_LRM); 3437 break; 3438 3439 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3440 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3441 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL); 3442 ifmedia_set(media, m | IFM_10G_TWINAX); 3443 break; 3444 3445 case FW_PORT_MOD_TYPE_NONE: 3446 m &= ~IFM_FDX; 3447 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3448 ifmedia_set(media, m | IFM_NONE); 3449 break; 3450 3451 case FW_PORT_MOD_TYPE_NA: 3452 case FW_PORT_MOD_TYPE_ER: 3453 default: 3454 device_printf(pi->dev, 3455 "unknown port_type (%d), mod_type (%d)\n", 3456 pi->port_type, pi->mod_type); 3457 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3458 ifmedia_set(media, m | IFM_UNKNOWN); 3459 break; 3460 } 3461 break; 3462 3463 case FW_PORT_TYPE_CR_QSFP: 3464 case FW_PORT_TYPE_SFP28: 3465 switch (pi->mod_type) { 3466 3467 case FW_PORT_MOD_TYPE_SR: 3468 MPASS(pi->port_type == FW_PORT_TYPE_SFP28); 3469 ifmedia_add(media, m | IFM_25G_SR, 0, NULL); 3470 ifmedia_set(media, m | IFM_25G_SR); 3471 break; 3472 3473 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3474 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3475 ifmedia_add(media, m | IFM_25G_CR, 0, NULL); 3476 ifmedia_set(media, m | IFM_25G_CR); 3477 break; 3478 3479 case FW_PORT_MOD_TYPE_NONE: 3480 m &= ~IFM_FDX; 3481 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3482 ifmedia_set(media, m | IFM_NONE); 3483 break; 3484 3485 default: 3486 device_printf(pi->dev, 3487 "unknown port_type (%d), mod_type (%d)\n", 3488 pi->port_type, pi->mod_type); 3489 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3490 ifmedia_set(media, m | IFM_UNKNOWN); 3491 break; 3492 } 3493 break; 3494 3495 case FW_PORT_TYPE_QSFP: 3496 switch (pi->mod_type) { 3497 3498 case FW_PORT_MOD_TYPE_LR: 3499 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL); 3500 ifmedia_set(media, m | IFM_40G_LR4); 3501 break; 3502 3503 case FW_PORT_MOD_TYPE_SR: 3504 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL); 3505 ifmedia_set(media, m | IFM_40G_SR4); 3506 break; 3507 3508 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3509 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3510 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL); 3511 ifmedia_set(media, m | IFM_40G_CR4); 3512 break; 3513 3514 case FW_PORT_MOD_TYPE_NONE: 3515 m &= ~IFM_FDX; 3516 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3517 ifmedia_set(media, m | IFM_NONE); 3518 break; 3519 3520 default: 3521 device_printf(pi->dev, 3522 "unknown port_type (%d), mod_type (%d)\n", 3523 pi->port_type, pi->mod_type); 3524 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3525 ifmedia_set(media, m | IFM_UNKNOWN); 3526 break; 3527 } 3528 break; 3529 3530 case FW_PORT_TYPE_CR2_QSFP: 3531 switch (pi->mod_type) { 3532 3533 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3534 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3535 ifmedia_add(media, m | IFM_50G_CR2, 0, NULL); 3536 ifmedia_set(media, m | IFM_50G_CR2); 3537 break; 3538 3539 case FW_PORT_MOD_TYPE_NONE: 3540 m &= ~IFM_FDX; 3541 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3542 ifmedia_set(media, m | IFM_NONE); 3543 break; 3544 3545 default: 3546 device_printf(pi->dev, 3547 "unknown port_type (%d), mod_type (%d)\n", 3548 pi->port_type, pi->mod_type); 3549 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3550 ifmedia_set(media, m | IFM_UNKNOWN); 3551 break; 3552 } 3553 break; 3554 3555 case FW_PORT_TYPE_KR4_100G: 3556 case FW_PORT_TYPE_CR4_QSFP: 3557 switch (pi->mod_type) { 3558 3559 case FW_PORT_MOD_TYPE_LR: 3560 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL); 3561 ifmedia_set(media, m | IFM_100G_LR4); 3562 break; 3563 3564 case FW_PORT_MOD_TYPE_SR: 3565 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL); 3566 ifmedia_set(media, m | IFM_100G_SR4); 3567 break; 3568 3569 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3570 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3571 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL); 3572 ifmedia_set(media, m | IFM_100G_CR4); 3573 break; 3574 3575 case FW_PORT_MOD_TYPE_NONE: 3576 m &= ~IFM_FDX; 3577 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3578 ifmedia_set(media, m | IFM_NONE); 3579 break; 3580 3581 default: 3582 device_printf(pi->dev, 3583 "unknown port_type (%d), mod_type (%d)\n", 3584 pi->port_type, pi->mod_type); 3585 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3586 ifmedia_set(media, m | IFM_UNKNOWN); 3587 break; 3588 } 3589 break; 3590 3591 default: 3592 device_printf(pi->dev, 3593 "unknown port_type (%d), mod_type (%d)\n", pi->port_type, 3594 pi->mod_type); 3595 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3596 ifmedia_set(media, m | IFM_UNKNOWN); 3597 break; 3598 } 3599 3600 PORT_UNLOCK(pi); 3601 } 3602 3603 #define FW_MAC_EXACT_CHUNK 7 3604 3605 /* 3606 * Program the port's XGMAC based on parameters in ifnet. The caller also 3607 * indicates which parameters should be programmed (the rest are left alone). 3608 */ 3609 int 3610 update_mac_settings(struct ifnet *ifp, int flags) 3611 { 3612 int rc = 0; 3613 struct vi_info *vi = ifp->if_softc; 3614 struct port_info *pi = vi->pi; 3615 struct adapter *sc = pi->adapter; 3616 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 3617 3618 ASSERT_SYNCHRONIZED_OP(sc); 3619 KASSERT(flags, ("%s: not told what to update.", __func__)); 3620 3621 if (flags & XGMAC_MTU) 3622 mtu = ifp->if_mtu; 3623 3624 if (flags & XGMAC_PROMISC) 3625 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 3626 3627 if (flags & XGMAC_ALLMULTI) 3628 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 3629 3630 if (flags & XGMAC_VLANEX) 3631 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 3632 3633 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 3634 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 3635 allmulti, 1, vlanex, false); 3636 if (rc) { 3637 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 3638 rc); 3639 return (rc); 3640 } 3641 } 3642 3643 if (flags & XGMAC_UCADDR) { 3644 uint8_t ucaddr[ETHER_ADDR_LEN]; 3645 3646 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 3647 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 3648 ucaddr, true, true); 3649 if (rc < 0) { 3650 rc = -rc; 3651 if_printf(ifp, "change_mac failed: %d\n", rc); 3652 return (rc); 3653 } else { 3654 vi->xact_addr_filt = rc; 3655 rc = 0; 3656 } 3657 } 3658 3659 if (flags & XGMAC_MCADDRS) { 3660 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 3661 int del = 1; 3662 uint64_t hash = 0; 3663 struct ifmultiaddr *ifma; 3664 int i = 0, j; 3665 3666 if_maddr_rlock(ifp); 3667 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 3668 if (ifma->ifma_addr->sa_family != AF_LINK) 3669 continue; 3670 mcaddr[i] = 3671 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 3672 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 3673 i++; 3674 3675 if (i == FW_MAC_EXACT_CHUNK) { 3676 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 3677 del, i, mcaddr, NULL, &hash, 0); 3678 if (rc < 0) { 3679 rc = -rc; 3680 for (j = 0; j < i; j++) { 3681 if_printf(ifp, 3682 "failed to add mc address" 3683 " %02x:%02x:%02x:" 3684 "%02x:%02x:%02x rc=%d\n", 3685 mcaddr[j][0], mcaddr[j][1], 3686 mcaddr[j][2], mcaddr[j][3], 3687 mcaddr[j][4], mcaddr[j][5], 3688 rc); 3689 } 3690 goto mcfail; 3691 } 3692 del = 0; 3693 i = 0; 3694 } 3695 } 3696 if (i > 0) { 3697 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 3698 mcaddr, NULL, &hash, 0); 3699 if (rc < 0) { 3700 rc = -rc; 3701 for (j = 0; j < i; j++) { 3702 if_printf(ifp, 3703 "failed to add mc address" 3704 " %02x:%02x:%02x:" 3705 "%02x:%02x:%02x rc=%d\n", 3706 mcaddr[j][0], mcaddr[j][1], 3707 mcaddr[j][2], mcaddr[j][3], 3708 mcaddr[j][4], mcaddr[j][5], 3709 rc); 3710 } 3711 goto mcfail; 3712 } 3713 } 3714 3715 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 3716 if (rc != 0) 3717 if_printf(ifp, "failed to set mc address hash: %d", rc); 3718 mcfail: 3719 if_maddr_runlock(ifp); 3720 } 3721 3722 return (rc); 3723 } 3724 3725 /* 3726 * {begin|end}_synchronized_op must be called from the same thread. 3727 */ 3728 int 3729 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 3730 char *wmesg) 3731 { 3732 int rc, pri; 3733 3734 #ifdef WITNESS 3735 /* the caller thinks it's ok to sleep, but is it really? */ 3736 if (flags & SLEEP_OK) 3737 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 3738 "begin_synchronized_op"); 3739 #endif 3740 3741 if (INTR_OK) 3742 pri = PCATCH; 3743 else 3744 pri = 0; 3745 3746 ADAPTER_LOCK(sc); 3747 for (;;) { 3748 3749 if (vi && IS_DOOMED(vi)) { 3750 rc = ENXIO; 3751 goto done; 3752 } 3753 3754 if (!IS_BUSY(sc)) { 3755 rc = 0; 3756 break; 3757 } 3758 3759 if (!(flags & SLEEP_OK)) { 3760 rc = EBUSY; 3761 goto done; 3762 } 3763 3764 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 3765 rc = EINTR; 3766 goto done; 3767 } 3768 } 3769 3770 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 3771 SET_BUSY(sc); 3772 #ifdef INVARIANTS 3773 sc->last_op = wmesg; 3774 sc->last_op_thr = curthread; 3775 sc->last_op_flags = flags; 3776 #endif 3777 3778 done: 3779 if (!(flags & HOLD_LOCK) || rc) 3780 ADAPTER_UNLOCK(sc); 3781 3782 return (rc); 3783 } 3784 3785 /* 3786 * Tell if_ioctl and if_init that the VI is going away. This is 3787 * special variant of begin_synchronized_op and must be paired with a 3788 * call to end_synchronized_op. 3789 */ 3790 void 3791 doom_vi(struct adapter *sc, struct vi_info *vi) 3792 { 3793 3794 ADAPTER_LOCK(sc); 3795 SET_DOOMED(vi); 3796 wakeup(&sc->flags); 3797 while (IS_BUSY(sc)) 3798 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 3799 SET_BUSY(sc); 3800 #ifdef INVARIANTS 3801 sc->last_op = "t4detach"; 3802 sc->last_op_thr = curthread; 3803 sc->last_op_flags = 0; 3804 #endif 3805 ADAPTER_UNLOCK(sc); 3806 } 3807 3808 /* 3809 * {begin|end}_synchronized_op must be called from the same thread. 3810 */ 3811 void 3812 end_synchronized_op(struct adapter *sc, int flags) 3813 { 3814 3815 if (flags & LOCK_HELD) 3816 ADAPTER_LOCK_ASSERT_OWNED(sc); 3817 else 3818 ADAPTER_LOCK(sc); 3819 3820 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 3821 CLR_BUSY(sc); 3822 wakeup(&sc->flags); 3823 ADAPTER_UNLOCK(sc); 3824 } 3825 3826 static int 3827 cxgbe_init_synchronized(struct vi_info *vi) 3828 { 3829 struct port_info *pi = vi->pi; 3830 struct adapter *sc = pi->adapter; 3831 struct ifnet *ifp = vi->ifp; 3832 int rc = 0, i; 3833 struct sge_txq *txq; 3834 3835 ASSERT_SYNCHRONIZED_OP(sc); 3836 3837 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3838 return (0); /* already running */ 3839 3840 if (!(sc->flags & FULL_INIT_DONE) && 3841 ((rc = adapter_full_init(sc)) != 0)) 3842 return (rc); /* error message displayed already */ 3843 3844 if (!(vi->flags & VI_INIT_DONE) && 3845 ((rc = vi_full_init(vi)) != 0)) 3846 return (rc); /* error message displayed already */ 3847 3848 rc = update_mac_settings(ifp, XGMAC_ALL); 3849 if (rc) 3850 goto done; /* error message displayed already */ 3851 3852 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 3853 if (rc != 0) { 3854 if_printf(ifp, "enable_vi failed: %d\n", rc); 3855 goto done; 3856 } 3857 3858 /* 3859 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 3860 * if this changes. 3861 */ 3862 3863 for_each_txq(vi, i, txq) { 3864 TXQ_LOCK(txq); 3865 txq->eq.flags |= EQ_ENABLED; 3866 TXQ_UNLOCK(txq); 3867 } 3868 3869 /* 3870 * The first iq of the first port to come up is used for tracing. 3871 */ 3872 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 3873 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 3874 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 3875 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 3876 V_QUEUENUMBER(sc->traceq)); 3877 pi->flags |= HAS_TRACEQ; 3878 } 3879 3880 /* all ok */ 3881 PORT_LOCK(pi); 3882 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3883 pi->up_vis++; 3884 3885 if (pi->nvi > 1 || sc->flags & IS_VF) 3886 callout_reset(&vi->tick, hz, vi_tick, vi); 3887 else 3888 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 3889 PORT_UNLOCK(pi); 3890 done: 3891 if (rc != 0) 3892 cxgbe_uninit_synchronized(vi); 3893 3894 return (rc); 3895 } 3896 3897 /* 3898 * Idempotent. 3899 */ 3900 static int 3901 cxgbe_uninit_synchronized(struct vi_info *vi) 3902 { 3903 struct port_info *pi = vi->pi; 3904 struct adapter *sc = pi->adapter; 3905 struct ifnet *ifp = vi->ifp; 3906 int rc, i; 3907 struct sge_txq *txq; 3908 3909 ASSERT_SYNCHRONIZED_OP(sc); 3910 3911 if (!(vi->flags & VI_INIT_DONE)) { 3912 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING), 3913 ("uninited VI is running")); 3914 return (0); 3915 } 3916 3917 /* 3918 * Disable the VI so that all its data in either direction is discarded 3919 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 3920 * tick) intact as the TP can deliver negative advice or data that it's 3921 * holding in its RAM (for an offloaded connection) even after the VI is 3922 * disabled. 3923 */ 3924 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 3925 if (rc) { 3926 if_printf(ifp, "disable_vi failed: %d\n", rc); 3927 return (rc); 3928 } 3929 3930 for_each_txq(vi, i, txq) { 3931 TXQ_LOCK(txq); 3932 txq->eq.flags &= ~EQ_ENABLED; 3933 TXQ_UNLOCK(txq); 3934 } 3935 3936 PORT_LOCK(pi); 3937 if (pi->nvi > 1 || sc->flags & IS_VF) 3938 callout_stop(&vi->tick); 3939 else 3940 callout_stop(&pi->tick); 3941 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3942 PORT_UNLOCK(pi); 3943 return (0); 3944 } 3945 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3946 pi->up_vis--; 3947 if (pi->up_vis > 0) { 3948 PORT_UNLOCK(pi); 3949 return (0); 3950 } 3951 PORT_UNLOCK(pi); 3952 3953 pi->link_cfg.link_ok = 0; 3954 pi->link_cfg.speed = 0; 3955 pi->linkdnrc = -1; 3956 t4_os_link_changed(sc, pi->port_id, 0, -1); 3957 3958 return (0); 3959 } 3960 3961 /* 3962 * It is ok for this function to fail midway and return right away. t4_detach 3963 * will walk the entire sc->irq list and clean up whatever is valid. 3964 */ 3965 int 3966 t4_setup_intr_handlers(struct adapter *sc) 3967 { 3968 int rc, rid, p, q, v; 3969 char s[8]; 3970 struct irq *irq; 3971 struct port_info *pi; 3972 struct vi_info *vi; 3973 struct sge *sge = &sc->sge; 3974 struct sge_rxq *rxq; 3975 #ifdef TCP_OFFLOAD 3976 struct sge_ofld_rxq *ofld_rxq; 3977 #endif 3978 #ifdef DEV_NETMAP 3979 struct sge_nm_rxq *nm_rxq; 3980 #endif 3981 #ifdef RSS 3982 int nbuckets = rss_getnumbuckets(); 3983 #endif 3984 3985 /* 3986 * Setup interrupts. 3987 */ 3988 irq = &sc->irq[0]; 3989 rid = sc->intr_type == INTR_INTX ? 0 : 1; 3990 if (sc->intr_count == 1) 3991 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 3992 3993 /* Multiple interrupts. */ 3994 if (sc->flags & IS_VF) 3995 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 3996 ("%s: too few intr.", __func__)); 3997 else 3998 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 3999 ("%s: too few intr.", __func__)); 4000 4001 /* The first one is always error intr on PFs */ 4002 if (!(sc->flags & IS_VF)) { 4003 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4004 if (rc != 0) 4005 return (rc); 4006 irq++; 4007 rid++; 4008 } 4009 4010 /* The second one is always the firmware event queue (first on VFs) */ 4011 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4012 if (rc != 0) 4013 return (rc); 4014 irq++; 4015 rid++; 4016 4017 for_each_port(sc, p) { 4018 pi = sc->port[p]; 4019 for_each_vi(pi, v, vi) { 4020 vi->first_intr = rid - 1; 4021 4022 if (vi->nnmrxq > 0) { 4023 int n = max(vi->nrxq, vi->nnmrxq); 4024 4025 MPASS(vi->flags & INTR_RXQ); 4026 4027 rxq = &sge->rxq[vi->first_rxq]; 4028 #ifdef DEV_NETMAP 4029 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4030 #endif 4031 for (q = 0; q < n; q++) { 4032 snprintf(s, sizeof(s), "%x%c%x", p, 4033 'a' + v, q); 4034 if (q < vi->nrxq) 4035 irq->rxq = rxq++; 4036 #ifdef DEV_NETMAP 4037 if (q < vi->nnmrxq) 4038 irq->nm_rxq = nm_rxq++; 4039 #endif 4040 rc = t4_alloc_irq(sc, irq, rid, 4041 t4_vi_intr, irq, s); 4042 if (rc != 0) 4043 return (rc); 4044 irq++; 4045 rid++; 4046 vi->nintr++; 4047 } 4048 } else if (vi->flags & INTR_RXQ) { 4049 for_each_rxq(vi, q, rxq) { 4050 snprintf(s, sizeof(s), "%x%c%x", p, 4051 'a' + v, q); 4052 rc = t4_alloc_irq(sc, irq, rid, 4053 t4_intr, rxq, s); 4054 if (rc != 0) 4055 return (rc); 4056 #ifdef RSS 4057 bus_bind_intr(sc->dev, irq->res, 4058 rss_getcpu(q % nbuckets)); 4059 #endif 4060 irq++; 4061 rid++; 4062 vi->nintr++; 4063 } 4064 } 4065 #ifdef TCP_OFFLOAD 4066 if (vi->flags & INTR_OFLD_RXQ) { 4067 for_each_ofld_rxq(vi, q, ofld_rxq) { 4068 snprintf(s, sizeof(s), "%x%c%x", p, 4069 'A' + v, q); 4070 rc = t4_alloc_irq(sc, irq, rid, 4071 t4_intr, ofld_rxq, s); 4072 if (rc != 0) 4073 return (rc); 4074 irq++; 4075 rid++; 4076 vi->nintr++; 4077 } 4078 } 4079 #endif 4080 } 4081 } 4082 MPASS(irq == &sc->irq[sc->intr_count]); 4083 4084 return (0); 4085 } 4086 4087 int 4088 adapter_full_init(struct adapter *sc) 4089 { 4090 int rc, i; 4091 4092 ASSERT_SYNCHRONIZED_OP(sc); 4093 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4094 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 4095 ("%s: FULL_INIT_DONE already", __func__)); 4096 4097 /* 4098 * queues that belong to the adapter (not any particular port). 4099 */ 4100 rc = t4_setup_adapter_queues(sc); 4101 if (rc != 0) 4102 goto done; 4103 4104 for (i = 0; i < nitems(sc->tq); i++) { 4105 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 4106 taskqueue_thread_enqueue, &sc->tq[i]); 4107 if (sc->tq[i] == NULL) { 4108 device_printf(sc->dev, 4109 "failed to allocate task queue %d\n", i); 4110 rc = ENOMEM; 4111 goto done; 4112 } 4113 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 4114 device_get_nameunit(sc->dev), i); 4115 } 4116 4117 if (!(sc->flags & IS_VF)) 4118 t4_intr_enable(sc); 4119 sc->flags |= FULL_INIT_DONE; 4120 done: 4121 if (rc != 0) 4122 adapter_full_uninit(sc); 4123 4124 return (rc); 4125 } 4126 4127 int 4128 adapter_full_uninit(struct adapter *sc) 4129 { 4130 int i; 4131 4132 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4133 4134 t4_teardown_adapter_queues(sc); 4135 4136 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 4137 taskqueue_free(sc->tq[i]); 4138 sc->tq[i] = NULL; 4139 } 4140 4141 sc->flags &= ~FULL_INIT_DONE; 4142 4143 return (0); 4144 } 4145 4146 #ifdef RSS 4147 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 4148 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 4149 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 4150 RSS_HASHTYPE_RSS_UDP_IPV6) 4151 4152 /* Translates kernel hash types to hardware. */ 4153 static int 4154 hashconfig_to_hashen(int hashconfig) 4155 { 4156 int hashen = 0; 4157 4158 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 4159 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 4160 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 4161 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 4162 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 4163 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4164 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4165 } 4166 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 4167 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4168 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4169 } 4170 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 4171 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4172 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 4173 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4174 4175 return (hashen); 4176 } 4177 4178 /* Translates hardware hash types to kernel. */ 4179 static int 4180 hashen_to_hashconfig(int hashen) 4181 { 4182 int hashconfig = 0; 4183 4184 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 4185 /* 4186 * If UDP hashing was enabled it must have been enabled for 4187 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 4188 * enabling any 4-tuple hash is nonsense configuration. 4189 */ 4190 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4191 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 4192 4193 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4194 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 4195 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4196 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 4197 } 4198 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4199 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 4200 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4201 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 4202 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 4203 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 4204 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 4205 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 4206 4207 return (hashconfig); 4208 } 4209 #endif 4210 4211 int 4212 vi_full_init(struct vi_info *vi) 4213 { 4214 struct adapter *sc = vi->pi->adapter; 4215 struct ifnet *ifp = vi->ifp; 4216 uint16_t *rss; 4217 struct sge_rxq *rxq; 4218 int rc, i, j, hashen; 4219 #ifdef RSS 4220 int nbuckets = rss_getnumbuckets(); 4221 int hashconfig = rss_gethashconfig(); 4222 int extra; 4223 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4224 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4225 #endif 4226 4227 ASSERT_SYNCHRONIZED_OP(sc); 4228 KASSERT((vi->flags & VI_INIT_DONE) == 0, 4229 ("%s: VI_INIT_DONE already", __func__)); 4230 4231 sysctl_ctx_init(&vi->ctx); 4232 vi->flags |= VI_SYSCTL_CTX; 4233 4234 /* 4235 * Allocate tx/rx/fl queues for this VI. 4236 */ 4237 rc = t4_setup_vi_queues(vi); 4238 if (rc != 0) 4239 goto done; /* error message displayed already */ 4240 4241 /* 4242 * Setup RSS for this VI. Save a copy of the RSS table for later use. 4243 */ 4244 if (vi->nrxq > vi->rss_size) { 4245 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 4246 "some queues will never receive traffic.\n", vi->nrxq, 4247 vi->rss_size); 4248 } else if (vi->rss_size % vi->nrxq) { 4249 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 4250 "expect uneven traffic distribution.\n", vi->nrxq, 4251 vi->rss_size); 4252 } 4253 #ifdef RSS 4254 MPASS(RSS_KEYSIZE == 40); 4255 if (vi->nrxq != nbuckets) { 4256 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 4257 "performance will be impacted.\n", vi->nrxq, nbuckets); 4258 } 4259 4260 rss_getkey((void *)&raw_rss_key[0]); 4261 for (i = 0; i < nitems(rss_key); i++) { 4262 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 4263 } 4264 t4_write_rss_key(sc, &rss_key[0], -1); 4265 #endif 4266 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 4267 for (i = 0; i < vi->rss_size;) { 4268 #ifdef RSS 4269 j = rss_get_indirection_to_bucket(i); 4270 j %= vi->nrxq; 4271 rxq = &sc->sge.rxq[vi->first_rxq + j]; 4272 rss[i++] = rxq->iq.abs_id; 4273 #else 4274 for_each_rxq(vi, j, rxq) { 4275 rss[i++] = rxq->iq.abs_id; 4276 if (i == vi->rss_size) 4277 break; 4278 } 4279 #endif 4280 } 4281 4282 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 4283 vi->rss_size); 4284 if (rc != 0) { 4285 if_printf(ifp, "rss_config failed: %d\n", rc); 4286 goto done; 4287 } 4288 4289 #ifdef RSS 4290 hashen = hashconfig_to_hashen(hashconfig); 4291 4292 /* 4293 * We may have had to enable some hashes even though the global config 4294 * wants them disabled. This is a potential problem that must be 4295 * reported to the user. 4296 */ 4297 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 4298 4299 /* 4300 * If we consider only the supported hash types, then the enabled hashes 4301 * are a superset of the requested hashes. In other words, there cannot 4302 * be any supported hash that was requested but not enabled, but there 4303 * can be hashes that were not requested but had to be enabled. 4304 */ 4305 extra &= SUPPORTED_RSS_HASHTYPES; 4306 MPASS((extra & hashconfig) == 0); 4307 4308 if (extra) { 4309 if_printf(ifp, 4310 "global RSS config (0x%x) cannot be accommodated.\n", 4311 hashconfig); 4312 } 4313 if (extra & RSS_HASHTYPE_RSS_IPV4) 4314 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 4315 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 4316 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 4317 if (extra & RSS_HASHTYPE_RSS_IPV6) 4318 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 4319 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 4320 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 4321 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 4322 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 4323 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 4324 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 4325 #else 4326 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 4327 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 4328 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4329 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 4330 #endif 4331 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]); 4332 if (rc != 0) { 4333 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 4334 goto done; 4335 } 4336 4337 vi->rss = rss; 4338 vi->flags |= VI_INIT_DONE; 4339 done: 4340 if (rc != 0) 4341 vi_full_uninit(vi); 4342 4343 return (rc); 4344 } 4345 4346 /* 4347 * Idempotent. 4348 */ 4349 int 4350 vi_full_uninit(struct vi_info *vi) 4351 { 4352 struct port_info *pi = vi->pi; 4353 struct adapter *sc = pi->adapter; 4354 int i; 4355 struct sge_rxq *rxq; 4356 struct sge_txq *txq; 4357 #ifdef TCP_OFFLOAD 4358 struct sge_ofld_rxq *ofld_rxq; 4359 struct sge_wrq *ofld_txq; 4360 #endif 4361 4362 if (vi->flags & VI_INIT_DONE) { 4363 4364 /* Need to quiesce queues. */ 4365 4366 /* XXX: Only for the first VI? */ 4367 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 4368 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 4369 4370 for_each_txq(vi, i, txq) { 4371 quiesce_txq(sc, txq); 4372 } 4373 4374 #ifdef TCP_OFFLOAD 4375 for_each_ofld_txq(vi, i, ofld_txq) { 4376 quiesce_wrq(sc, ofld_txq); 4377 } 4378 #endif 4379 4380 for_each_rxq(vi, i, rxq) { 4381 quiesce_iq(sc, &rxq->iq); 4382 quiesce_fl(sc, &rxq->fl); 4383 } 4384 4385 #ifdef TCP_OFFLOAD 4386 for_each_ofld_rxq(vi, i, ofld_rxq) { 4387 quiesce_iq(sc, &ofld_rxq->iq); 4388 quiesce_fl(sc, &ofld_rxq->fl); 4389 } 4390 #endif 4391 free(vi->rss, M_CXGBE); 4392 free(vi->nm_rss, M_CXGBE); 4393 } 4394 4395 t4_teardown_vi_queues(vi); 4396 vi->flags &= ~VI_INIT_DONE; 4397 4398 return (0); 4399 } 4400 4401 static void 4402 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 4403 { 4404 struct sge_eq *eq = &txq->eq; 4405 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4406 4407 (void) sc; /* unused */ 4408 4409 #ifdef INVARIANTS 4410 TXQ_LOCK(txq); 4411 MPASS((eq->flags & EQ_ENABLED) == 0); 4412 TXQ_UNLOCK(txq); 4413 #endif 4414 4415 /* Wait for the mp_ring to empty. */ 4416 while (!mp_ring_is_idle(txq->r)) { 4417 mp_ring_check_drainage(txq->r, 0); 4418 pause("rquiesce", 1); 4419 } 4420 4421 /* Then wait for the hardware to finish. */ 4422 while (spg->cidx != htobe16(eq->pidx)) 4423 pause("equiesce", 1); 4424 4425 /* Finally, wait for the driver to reclaim all descriptors. */ 4426 while (eq->cidx != eq->pidx) 4427 pause("dquiesce", 1); 4428 } 4429 4430 static void 4431 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 4432 { 4433 4434 /* XXXTX */ 4435 } 4436 4437 static void 4438 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 4439 { 4440 (void) sc; /* unused */ 4441 4442 /* Synchronize with the interrupt handler */ 4443 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 4444 pause("iqfree", 1); 4445 } 4446 4447 static void 4448 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 4449 { 4450 mtx_lock(&sc->sfl_lock); 4451 FL_LOCK(fl); 4452 fl->flags |= FL_DOOMED; 4453 FL_UNLOCK(fl); 4454 callout_stop(&sc->sfl_callout); 4455 mtx_unlock(&sc->sfl_lock); 4456 4457 KASSERT((fl->flags & FL_STARVING) == 0, 4458 ("%s: still starving", __func__)); 4459 } 4460 4461 static int 4462 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 4463 driver_intr_t *handler, void *arg, char *name) 4464 { 4465 int rc; 4466 4467 irq->rid = rid; 4468 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 4469 RF_SHAREABLE | RF_ACTIVE); 4470 if (irq->res == NULL) { 4471 device_printf(sc->dev, 4472 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 4473 return (ENOMEM); 4474 } 4475 4476 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 4477 NULL, handler, arg, &irq->tag); 4478 if (rc != 0) { 4479 device_printf(sc->dev, 4480 "failed to setup interrupt for rid %d, name %s: %d\n", 4481 rid, name, rc); 4482 } else if (name) 4483 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 4484 4485 return (rc); 4486 } 4487 4488 static int 4489 t4_free_irq(struct adapter *sc, struct irq *irq) 4490 { 4491 if (irq->tag) 4492 bus_teardown_intr(sc->dev, irq->res, irq->tag); 4493 if (irq->res) 4494 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 4495 4496 bzero(irq, sizeof(*irq)); 4497 4498 return (0); 4499 } 4500 4501 static void 4502 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 4503 { 4504 4505 regs->version = chip_id(sc) | chip_rev(sc) << 10; 4506 t4_get_regs(sc, buf, regs->len); 4507 } 4508 4509 #define A_PL_INDIR_CMD 0x1f8 4510 4511 #define S_PL_AUTOINC 31 4512 #define M_PL_AUTOINC 0x1U 4513 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 4514 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 4515 4516 #define S_PL_VFID 20 4517 #define M_PL_VFID 0xffU 4518 #define V_PL_VFID(x) ((x) << S_PL_VFID) 4519 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 4520 4521 #define S_PL_ADDR 0 4522 #define M_PL_ADDR 0xfffffU 4523 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 4524 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 4525 4526 #define A_PL_INDIR_DATA 0x1fc 4527 4528 static uint64_t 4529 read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 4530 { 4531 u32 stats[2]; 4532 4533 mtx_assert(&sc->reg_lock, MA_OWNED); 4534 if (sc->flags & IS_VF) { 4535 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 4536 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 4537 } else { 4538 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4539 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4540 V_PL_ADDR(VF_MPS_REG(reg))); 4541 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 4542 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 4543 } 4544 return (((uint64_t)stats[1]) << 32 | stats[0]); 4545 } 4546 4547 static void 4548 t4_get_vi_stats(struct adapter *sc, unsigned int viid, 4549 struct fw_vi_stats_vf *stats) 4550 { 4551 4552 #define GET_STAT(name) \ 4553 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 4554 4555 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 4556 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 4557 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 4558 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 4559 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 4560 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 4561 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 4562 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 4563 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 4564 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 4565 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 4566 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 4567 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 4568 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 4569 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 4570 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 4571 4572 #undef GET_STAT 4573 } 4574 4575 static void 4576 t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 4577 { 4578 int reg; 4579 4580 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4581 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4582 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 4583 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 4584 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 4585 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 4586 } 4587 4588 static void 4589 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 4590 { 4591 struct timeval tv; 4592 const struct timeval interval = {0, 250000}; /* 250ms */ 4593 4594 if (!(vi->flags & VI_INIT_DONE)) 4595 return; 4596 4597 getmicrotime(&tv); 4598 timevalsub(&tv, &interval); 4599 if (timevalcmp(&tv, &vi->last_refreshed, <)) 4600 return; 4601 4602 mtx_lock(&sc->reg_lock); 4603 t4_get_vi_stats(sc, vi->viid, &vi->stats); 4604 getmicrotime(&vi->last_refreshed); 4605 mtx_unlock(&sc->reg_lock); 4606 } 4607 4608 static void 4609 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 4610 { 4611 int i; 4612 u_int v, tnl_cong_drops; 4613 struct timeval tv; 4614 const struct timeval interval = {0, 250000}; /* 250ms */ 4615 4616 getmicrotime(&tv); 4617 timevalsub(&tv, &interval); 4618 if (timevalcmp(&tv, &pi->last_refreshed, <)) 4619 return; 4620 4621 tnl_cong_drops = 0; 4622 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 4623 for (i = 0; i < sc->chip_params->nchan; i++) { 4624 if (pi->rx_chan_map & (1 << i)) { 4625 mtx_lock(&sc->reg_lock); 4626 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 4627 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 4628 mtx_unlock(&sc->reg_lock); 4629 tnl_cong_drops += v; 4630 } 4631 } 4632 pi->tnl_cong_drops = tnl_cong_drops; 4633 getmicrotime(&pi->last_refreshed); 4634 } 4635 4636 static void 4637 cxgbe_tick(void *arg) 4638 { 4639 struct port_info *pi = arg; 4640 struct adapter *sc = pi->adapter; 4641 4642 PORT_LOCK_ASSERT_OWNED(pi); 4643 cxgbe_refresh_stats(sc, pi); 4644 4645 callout_schedule(&pi->tick, hz); 4646 } 4647 4648 void 4649 vi_tick(void *arg) 4650 { 4651 struct vi_info *vi = arg; 4652 struct adapter *sc = vi->pi->adapter; 4653 4654 vi_refresh_stats(sc, vi); 4655 4656 callout_schedule(&vi->tick, hz); 4657 } 4658 4659 static void 4660 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 4661 { 4662 struct ifnet *vlan; 4663 4664 if (arg != ifp || ifp->if_type != IFT_ETHER) 4665 return; 4666 4667 vlan = VLAN_DEVAT(ifp, vid); 4668 VLAN_SETCOOKIE(vlan, ifp); 4669 } 4670 4671 /* 4672 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 4673 */ 4674 static char *caps_decoder[] = { 4675 "\20\001IPMI\002NCSI", /* 0: NBM */ 4676 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 4677 "\20\001INGRESS\002EGRESS", /* 2: switch */ 4678 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 4679 "\006HASHFILTER\007ETHOFLD", 4680 "\20\001TOE", /* 4: TOE */ 4681 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 4682 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 4683 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 4684 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 4685 "\007T10DIF" 4686 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 4687 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 4688 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 4689 "\004PO_INITIATOR\005PO_TARGET", 4690 }; 4691 4692 void 4693 t4_sysctls(struct adapter *sc) 4694 { 4695 struct sysctl_ctx_list *ctx; 4696 struct sysctl_oid *oid; 4697 struct sysctl_oid_list *children, *c0; 4698 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 4699 4700 ctx = device_get_sysctl_ctx(sc->dev); 4701 4702 /* 4703 * dev.t4nex.X. 4704 */ 4705 oid = device_get_sysctl_tree(sc->dev); 4706 c0 = children = SYSCTL_CHILDREN(oid); 4707 4708 sc->sc_do_rxcopy = 1; 4709 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 4710 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 4711 4712 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 4713 sc->params.nports, "# of ports"); 4714 4715 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 4716 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 4717 sysctl_bitfield, "A", "available doorbells"); 4718 4719 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 4720 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 4721 4722 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 4723 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 4724 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 4725 "interrupt holdoff timer values (us)"); 4726 4727 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 4728 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 4729 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 4730 "interrupt holdoff packet counter values"); 4731 4732 t4_sge_sysctls(sc, ctx, children); 4733 4734 sc->lro_timeout = 100; 4735 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 4736 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 4737 4738 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 4739 &sc->debug_flags, 0, "flags to enable runtime debugging"); 4740 4741 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 4742 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 4743 4744 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 4745 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 4746 4747 if (sc->flags & IS_VF) 4748 return; 4749 4750 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 4751 NULL, chip_rev(sc), "chip hardware revision"); 4752 4753 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 4754 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 4755 4756 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 4757 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 4758 4759 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 4760 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 4761 4762 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 4763 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 4764 4765 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 4766 sc->er_version, 0, "expansion ROM version"); 4767 4768 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 4769 sc->bs_version, 0, "bootstrap firmware version"); 4770 4771 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 4772 NULL, sc->params.scfg_vers, "serial config version"); 4773 4774 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 4775 NULL, sc->params.vpd_vers, "VPD version"); 4776 4777 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 4778 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 4779 4780 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 4781 sc->cfcsum, "config file checksum"); 4782 4783 #define SYSCTL_CAP(name, n, text) \ 4784 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 4785 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \ 4786 sysctl_bitfield, "A", "available " text " capabilities") 4787 4788 SYSCTL_CAP(nbmcaps, 0, "NBM"); 4789 SYSCTL_CAP(linkcaps, 1, "link"); 4790 SYSCTL_CAP(switchcaps, 2, "switch"); 4791 SYSCTL_CAP(niccaps, 3, "NIC"); 4792 SYSCTL_CAP(toecaps, 4, "TCP offload"); 4793 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 4794 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 4795 SYSCTL_CAP(cryptocaps, 7, "crypto"); 4796 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 4797 #undef SYSCTL_CAP 4798 4799 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 4800 NULL, sc->tids.nftids, "number of filters"); 4801 4802 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 4803 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 4804 "chip temperature (in Celsius)"); 4805 4806 #ifdef SBUF_DRAIN 4807 /* 4808 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 4809 */ 4810 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 4811 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 4812 "logs and miscellaneous information"); 4813 children = SYSCTL_CHILDREN(oid); 4814 4815 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 4816 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4817 sysctl_cctrl, "A", "congestion control"); 4818 4819 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 4820 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4821 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 4822 4823 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 4824 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 4825 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 4826 4827 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 4828 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 4829 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 4830 4831 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 4832 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 4833 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 4834 4835 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 4836 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 4837 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 4838 4839 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 4840 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 4841 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 4842 4843 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 4844 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4845 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 4846 "A", "CIM logic analyzer"); 4847 4848 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 4849 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4850 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 4851 4852 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 4853 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 4854 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 4855 4856 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 4857 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 4858 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 4859 4860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 4861 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 4862 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 4863 4864 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 4865 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 4866 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 4867 4868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 4869 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 4870 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 4871 4872 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 4873 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 4874 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 4875 4876 if (chip_id(sc) > CHELSIO_T4) { 4877 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 4878 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 4879 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 4880 4881 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 4882 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 4883 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 4884 } 4885 4886 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 4887 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4888 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 4889 4890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 4891 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4892 sysctl_cim_qcfg, "A", "CIM queue configuration"); 4893 4894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 4895 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4896 sysctl_cpl_stats, "A", "CPL statistics"); 4897 4898 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 4899 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4900 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 4901 4902 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 4903 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4904 sysctl_devlog, "A", "firmware's device log"); 4905 4906 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 4907 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4908 sysctl_fcoe_stats, "A", "FCoE statistics"); 4909 4910 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 4911 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4912 sysctl_hw_sched, "A", "hardware scheduler "); 4913 4914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 4915 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4916 sysctl_l2t, "A", "hardware L2 table"); 4917 4918 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 4919 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4920 sysctl_lb_stats, "A", "loopback statistics"); 4921 4922 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 4923 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4924 sysctl_meminfo, "A", "memory regions"); 4925 4926 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 4927 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4928 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 4929 "A", "MPS TCAM entries"); 4930 4931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 4932 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4933 sysctl_path_mtus, "A", "path MTUs"); 4934 4935 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 4936 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4937 sysctl_pm_stats, "A", "PM statistics"); 4938 4939 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 4940 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4941 sysctl_rdma_stats, "A", "RDMA statistics"); 4942 4943 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 4944 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4945 sysctl_tcp_stats, "A", "TCP statistics"); 4946 4947 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 4948 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4949 sysctl_tids, "A", "TID information"); 4950 4951 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 4952 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4953 sysctl_tp_err_stats, "A", "TP error statistics"); 4954 4955 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 4956 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 4957 "TP logic analyzer event capture mask"); 4958 4959 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 4960 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4961 sysctl_tp_la, "A", "TP logic analyzer"); 4962 4963 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 4964 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4965 sysctl_tx_rate, "A", "Tx rate"); 4966 4967 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 4968 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4969 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 4970 4971 if (is_t5(sc)) { 4972 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 4973 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4974 sysctl_wcwr_stats, "A", "write combined work requests"); 4975 } 4976 #endif 4977 4978 #ifdef TCP_OFFLOAD 4979 if (is_offload(sc)) { 4980 /* 4981 * dev.t4nex.X.toe. 4982 */ 4983 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 4984 NULL, "TOE parameters"); 4985 children = SYSCTL_CHILDREN(oid); 4986 4987 sc->tt.sndbuf = 256 * 1024; 4988 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 4989 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 4990 4991 sc->tt.ddp = 0; 4992 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 4993 &sc->tt.ddp, 0, "DDP allowed"); 4994 4995 sc->tt.rx_coalesce = 1; 4996 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 4997 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 4998 4999 sc->tt.tx_align = 1; 5000 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 5001 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 5002 5003 sc->tt.tx_zcopy = 0; 5004 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 5005 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 5006 "Enable zero-copy aio_write(2)"); 5007 5008 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 5009 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 5010 "TP timer tick (us)"); 5011 5012 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 5013 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 5014 "TCP timestamp tick (us)"); 5015 5016 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 5017 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 5018 "DACK tick (us)"); 5019 5020 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 5021 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 5022 "IU", "DACK timer (us)"); 5023 5024 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 5025 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 5026 sysctl_tp_timer, "LU", "Retransmit min (us)"); 5027 5028 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 5029 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 5030 sysctl_tp_timer, "LU", "Retransmit max (us)"); 5031 5032 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 5033 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 5034 sysctl_tp_timer, "LU", "Persist timer min (us)"); 5035 5036 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 5037 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 5038 sysctl_tp_timer, "LU", "Persist timer max (us)"); 5039 5040 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 5041 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 5042 sysctl_tp_timer, "LU", "Keepidle idle timer (us)"); 5043 5044 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl", 5045 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 5046 sysctl_tp_timer, "LU", "Keepidle interval (us)"); 5047 5048 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 5049 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 5050 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 5051 5052 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 5053 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 5054 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 5055 } 5056 #endif 5057 } 5058 5059 void 5060 vi_sysctls(struct vi_info *vi) 5061 { 5062 struct sysctl_ctx_list *ctx; 5063 struct sysctl_oid *oid; 5064 struct sysctl_oid_list *children; 5065 5066 ctx = device_get_sysctl_ctx(vi->dev); 5067 5068 /* 5069 * dev.v?(cxgbe|cxl).X. 5070 */ 5071 oid = device_get_sysctl_tree(vi->dev); 5072 children = SYSCTL_CHILDREN(oid); 5073 5074 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 5075 vi->viid, "VI identifer"); 5076 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 5077 &vi->nrxq, 0, "# of rx queues"); 5078 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 5079 &vi->ntxq, 0, "# of tx queues"); 5080 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 5081 &vi->first_rxq, 0, "index of first rx queue"); 5082 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 5083 &vi->first_txq, 0, "index of first tx queue"); 5084 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 5085 vi->rss_size, "size of RSS indirection table"); 5086 5087 if (IS_MAIN_VI(vi)) { 5088 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 5089 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 5090 "Reserve queue 0 for non-flowid packets"); 5091 } 5092 5093 #ifdef TCP_OFFLOAD 5094 if (vi->nofldrxq != 0) { 5095 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 5096 &vi->nofldrxq, 0, 5097 "# of rx queues for offloaded TCP connections"); 5098 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 5099 &vi->nofldtxq, 0, 5100 "# of tx queues for offloaded TCP connections"); 5101 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 5102 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 5103 "index of first TOE rx queue"); 5104 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 5105 CTLFLAG_RD, &vi->first_ofld_txq, 0, 5106 "index of first TOE tx queue"); 5107 } 5108 #endif 5109 #ifdef DEV_NETMAP 5110 if (vi->nnmrxq != 0) { 5111 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 5112 &vi->nnmrxq, 0, "# of netmap rx queues"); 5113 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 5114 &vi->nnmtxq, 0, "# of netmap tx queues"); 5115 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 5116 CTLFLAG_RD, &vi->first_nm_rxq, 0, 5117 "index of first netmap rx queue"); 5118 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 5119 CTLFLAG_RD, &vi->first_nm_txq, 0, 5120 "index of first netmap tx queue"); 5121 } 5122 #endif 5123 5124 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 5125 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 5126 "holdoff timer index"); 5127 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 5128 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 5129 "holdoff packet counter index"); 5130 5131 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 5132 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 5133 "rx queue size"); 5134 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 5135 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 5136 "tx queue size"); 5137 } 5138 5139 static void 5140 cxgbe_sysctls(struct port_info *pi) 5141 { 5142 struct sysctl_ctx_list *ctx; 5143 struct sysctl_oid *oid; 5144 struct sysctl_oid_list *children, *children2; 5145 struct adapter *sc = pi->adapter; 5146 int i; 5147 char name[16]; 5148 5149 ctx = device_get_sysctl_ctx(pi->dev); 5150 5151 /* 5152 * dev.cxgbe.X. 5153 */ 5154 oid = device_get_sysctl_tree(pi->dev); 5155 children = SYSCTL_CHILDREN(oid); 5156 5157 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 5158 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 5159 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 5160 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 5161 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 5162 "PHY temperature (in Celsius)"); 5163 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 5164 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 5165 "PHY firmware version"); 5166 } 5167 5168 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 5169 CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings, 5170 "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)"); 5171 5172 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 5173 port_top_speed(pi), "max speed (in Gbps)"); 5174 5175 if (sc->flags & IS_VF) 5176 return; 5177 5178 /* 5179 * dev.(cxgbe|cxl).X.tc. 5180 */ 5181 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 5182 "Tx scheduler traffic classes"); 5183 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 5184 struct tx_sched_class *tc = &pi->tc[i]; 5185 5186 snprintf(name, sizeof(name), "%d", i); 5187 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 5188 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 5189 "traffic class")); 5190 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD, 5191 &tc->flags, 0, "flags"); 5192 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 5193 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 5194 #ifdef SBUF_DRAIN 5195 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 5196 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 5197 sysctl_tc_params, "A", "traffic class parameters"); 5198 #endif 5199 } 5200 5201 /* 5202 * dev.cxgbe.X.stats. 5203 */ 5204 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 5205 NULL, "port statistics"); 5206 children = SYSCTL_CHILDREN(oid); 5207 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 5208 &pi->tx_parse_error, 0, 5209 "# of tx packets with invalid length or # of segments"); 5210 5211 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 5212 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 5213 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 5214 sysctl_handle_t4_reg64, "QU", desc) 5215 5216 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 5217 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 5218 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 5219 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 5220 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 5221 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 5222 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 5223 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 5224 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 5225 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 5226 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 5227 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 5228 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 5229 "# of tx frames in this range", 5230 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 5231 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 5232 "# of tx frames in this range", 5233 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 5234 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 5235 "# of tx frames in this range", 5236 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 5237 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 5238 "# of tx frames in this range", 5239 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 5240 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 5241 "# of tx frames in this range", 5242 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 5243 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 5244 "# of tx frames in this range", 5245 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 5246 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 5247 "# of tx frames in this range", 5248 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 5249 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 5250 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 5251 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 5252 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 5253 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 5254 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 5255 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 5256 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 5257 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 5258 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 5259 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 5260 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 5261 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 5262 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 5263 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 5264 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 5265 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 5266 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 5267 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 5268 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 5269 5270 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 5271 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 5272 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 5273 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 5274 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 5275 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 5276 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 5277 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 5278 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 5279 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 5280 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 5281 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 5282 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 5283 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 5284 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 5285 "# of frames received with bad FCS", 5286 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 5287 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 5288 "# of frames received with length error", 5289 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 5290 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 5291 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 5292 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 5293 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 5294 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 5295 "# of rx frames in this range", 5296 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 5297 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 5298 "# of rx frames in this range", 5299 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 5300 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 5301 "# of rx frames in this range", 5302 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 5303 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 5304 "# of rx frames in this range", 5305 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 5306 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 5307 "# of rx frames in this range", 5308 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 5309 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 5310 "# of rx frames in this range", 5311 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 5312 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 5313 "# of rx frames in this range", 5314 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 5315 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 5316 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 5317 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 5318 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 5319 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 5320 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 5321 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 5322 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 5323 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 5324 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 5325 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 5326 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 5327 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 5328 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 5329 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 5330 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 5331 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 5332 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 5333 5334 #undef SYSCTL_ADD_T4_REG64 5335 5336 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 5337 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 5338 &pi->stats.name, desc) 5339 5340 /* We get these from port_stats and they may be stale by up to 1s */ 5341 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 5342 "# drops due to buffer-group 0 overflows"); 5343 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 5344 "# drops due to buffer-group 1 overflows"); 5345 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 5346 "# drops due to buffer-group 2 overflows"); 5347 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 5348 "# drops due to buffer-group 3 overflows"); 5349 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 5350 "# of buffer-group 0 truncated packets"); 5351 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 5352 "# of buffer-group 1 truncated packets"); 5353 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 5354 "# of buffer-group 2 truncated packets"); 5355 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 5356 "# of buffer-group 3 truncated packets"); 5357 5358 #undef SYSCTL_ADD_T4_PORTSTAT 5359 } 5360 5361 static int 5362 sysctl_int_array(SYSCTL_HANDLER_ARGS) 5363 { 5364 int rc, *i, space = 0; 5365 struct sbuf sb; 5366 5367 sbuf_new_for_sysctl(&sb, NULL, 64, req); 5368 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 5369 if (space) 5370 sbuf_printf(&sb, " "); 5371 sbuf_printf(&sb, "%d", *i); 5372 space = 1; 5373 } 5374 rc = sbuf_finish(&sb); 5375 sbuf_delete(&sb); 5376 return (rc); 5377 } 5378 5379 static int 5380 sysctl_bitfield(SYSCTL_HANDLER_ARGS) 5381 { 5382 int rc; 5383 struct sbuf *sb; 5384 5385 rc = sysctl_wire_old_buffer(req, 0); 5386 if (rc != 0) 5387 return(rc); 5388 5389 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5390 if (sb == NULL) 5391 return (ENOMEM); 5392 5393 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 5394 rc = sbuf_finish(sb); 5395 sbuf_delete(sb); 5396 5397 return (rc); 5398 } 5399 5400 static int 5401 sysctl_btphy(SYSCTL_HANDLER_ARGS) 5402 { 5403 struct port_info *pi = arg1; 5404 int op = arg2; 5405 struct adapter *sc = pi->adapter; 5406 u_int v; 5407 int rc; 5408 5409 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 5410 if (rc) 5411 return (rc); 5412 /* XXX: magic numbers */ 5413 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 5414 &v); 5415 end_synchronized_op(sc, 0); 5416 if (rc) 5417 return (rc); 5418 if (op == 0) 5419 v /= 256; 5420 5421 rc = sysctl_handle_int(oidp, &v, 0, req); 5422 return (rc); 5423 } 5424 5425 static int 5426 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 5427 { 5428 struct vi_info *vi = arg1; 5429 int rc, val; 5430 5431 val = vi->rsrv_noflowq; 5432 rc = sysctl_handle_int(oidp, &val, 0, req); 5433 if (rc != 0 || req->newptr == NULL) 5434 return (rc); 5435 5436 if ((val >= 1) && (vi->ntxq > 1)) 5437 vi->rsrv_noflowq = 1; 5438 else 5439 vi->rsrv_noflowq = 0; 5440 5441 return (rc); 5442 } 5443 5444 static int 5445 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 5446 { 5447 struct vi_info *vi = arg1; 5448 struct adapter *sc = vi->pi->adapter; 5449 int idx, rc, i; 5450 struct sge_rxq *rxq; 5451 #ifdef TCP_OFFLOAD 5452 struct sge_ofld_rxq *ofld_rxq; 5453 #endif 5454 uint8_t v; 5455 5456 idx = vi->tmr_idx; 5457 5458 rc = sysctl_handle_int(oidp, &idx, 0, req); 5459 if (rc != 0 || req->newptr == NULL) 5460 return (rc); 5461 5462 if (idx < 0 || idx >= SGE_NTIMERS) 5463 return (EINVAL); 5464 5465 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5466 "t4tmr"); 5467 if (rc) 5468 return (rc); 5469 5470 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 5471 for_each_rxq(vi, i, rxq) { 5472 #ifdef atomic_store_rel_8 5473 atomic_store_rel_8(&rxq->iq.intr_params, v); 5474 #else 5475 rxq->iq.intr_params = v; 5476 #endif 5477 } 5478 #ifdef TCP_OFFLOAD 5479 for_each_ofld_rxq(vi, i, ofld_rxq) { 5480 #ifdef atomic_store_rel_8 5481 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 5482 #else 5483 ofld_rxq->iq.intr_params = v; 5484 #endif 5485 } 5486 #endif 5487 vi->tmr_idx = idx; 5488 5489 end_synchronized_op(sc, LOCK_HELD); 5490 return (0); 5491 } 5492 5493 static int 5494 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 5495 { 5496 struct vi_info *vi = arg1; 5497 struct adapter *sc = vi->pi->adapter; 5498 int idx, rc; 5499 5500 idx = vi->pktc_idx; 5501 5502 rc = sysctl_handle_int(oidp, &idx, 0, req); 5503 if (rc != 0 || req->newptr == NULL) 5504 return (rc); 5505 5506 if (idx < -1 || idx >= SGE_NCOUNTERS) 5507 return (EINVAL); 5508 5509 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5510 "t4pktc"); 5511 if (rc) 5512 return (rc); 5513 5514 if (vi->flags & VI_INIT_DONE) 5515 rc = EBUSY; /* cannot be changed once the queues are created */ 5516 else 5517 vi->pktc_idx = idx; 5518 5519 end_synchronized_op(sc, LOCK_HELD); 5520 return (rc); 5521 } 5522 5523 static int 5524 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 5525 { 5526 struct vi_info *vi = arg1; 5527 struct adapter *sc = vi->pi->adapter; 5528 int qsize, rc; 5529 5530 qsize = vi->qsize_rxq; 5531 5532 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5533 if (rc != 0 || req->newptr == NULL) 5534 return (rc); 5535 5536 if (qsize < 128 || (qsize & 7)) 5537 return (EINVAL); 5538 5539 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5540 "t4rxqs"); 5541 if (rc) 5542 return (rc); 5543 5544 if (vi->flags & VI_INIT_DONE) 5545 rc = EBUSY; /* cannot be changed once the queues are created */ 5546 else 5547 vi->qsize_rxq = qsize; 5548 5549 end_synchronized_op(sc, LOCK_HELD); 5550 return (rc); 5551 } 5552 5553 static int 5554 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 5555 { 5556 struct vi_info *vi = arg1; 5557 struct adapter *sc = vi->pi->adapter; 5558 int qsize, rc; 5559 5560 qsize = vi->qsize_txq; 5561 5562 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5563 if (rc != 0 || req->newptr == NULL) 5564 return (rc); 5565 5566 if (qsize < 128 || qsize > 65536) 5567 return (EINVAL); 5568 5569 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5570 "t4txqs"); 5571 if (rc) 5572 return (rc); 5573 5574 if (vi->flags & VI_INIT_DONE) 5575 rc = EBUSY; /* cannot be changed once the queues are created */ 5576 else 5577 vi->qsize_txq = qsize; 5578 5579 end_synchronized_op(sc, LOCK_HELD); 5580 return (rc); 5581 } 5582 5583 static int 5584 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 5585 { 5586 struct port_info *pi = arg1; 5587 struct adapter *sc = pi->adapter; 5588 struct link_config *lc = &pi->link_cfg; 5589 int rc; 5590 5591 if (req->newptr == NULL) { 5592 struct sbuf *sb; 5593 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX"; 5594 5595 rc = sysctl_wire_old_buffer(req, 0); 5596 if (rc != 0) 5597 return(rc); 5598 5599 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5600 if (sb == NULL) 5601 return (ENOMEM); 5602 5603 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits); 5604 rc = sbuf_finish(sb); 5605 sbuf_delete(sb); 5606 } else { 5607 char s[2]; 5608 int n; 5609 5610 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX)); 5611 s[1] = 0; 5612 5613 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 5614 if (rc != 0) 5615 return(rc); 5616 5617 if (s[1] != 0) 5618 return (EINVAL); 5619 if (s[0] < '0' || s[0] > '9') 5620 return (EINVAL); /* not a number */ 5621 n = s[0] - '0'; 5622 if (n & ~(PAUSE_TX | PAUSE_RX)) 5623 return (EINVAL); /* some other bit is set too */ 5624 5625 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 5626 "t4PAUSE"); 5627 if (rc) 5628 return (rc); 5629 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) { 5630 int link_ok = lc->link_ok; 5631 5632 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 5633 lc->requested_fc |= n; 5634 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5635 lc->link_ok = link_ok; /* restore */ 5636 } 5637 end_synchronized_op(sc, 0); 5638 } 5639 5640 return (rc); 5641 } 5642 5643 static int 5644 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 5645 { 5646 struct adapter *sc = arg1; 5647 int reg = arg2; 5648 uint64_t val; 5649 5650 val = t4_read_reg64(sc, reg); 5651 5652 return (sysctl_handle_64(oidp, &val, 0, req)); 5653 } 5654 5655 static int 5656 sysctl_temperature(SYSCTL_HANDLER_ARGS) 5657 { 5658 struct adapter *sc = arg1; 5659 int rc, t; 5660 uint32_t param, val; 5661 5662 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 5663 if (rc) 5664 return (rc); 5665 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5666 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5667 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 5668 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5669 end_synchronized_op(sc, 0); 5670 if (rc) 5671 return (rc); 5672 5673 /* unknown is returned as 0 but we display -1 in that case */ 5674 t = val == 0 ? -1 : val; 5675 5676 rc = sysctl_handle_int(oidp, &t, 0, req); 5677 return (rc); 5678 } 5679 5680 #ifdef SBUF_DRAIN 5681 static int 5682 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 5683 { 5684 struct adapter *sc = arg1; 5685 struct sbuf *sb; 5686 int rc, i; 5687 uint16_t incr[NMTUS][NCCTRL_WIN]; 5688 static const char *dec_fac[] = { 5689 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 5690 "0.9375" 5691 }; 5692 5693 rc = sysctl_wire_old_buffer(req, 0); 5694 if (rc != 0) 5695 return (rc); 5696 5697 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5698 if (sb == NULL) 5699 return (ENOMEM); 5700 5701 t4_read_cong_tbl(sc, incr); 5702 5703 for (i = 0; i < NCCTRL_WIN; ++i) { 5704 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 5705 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 5706 incr[5][i], incr[6][i], incr[7][i]); 5707 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 5708 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 5709 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 5710 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 5711 } 5712 5713 rc = sbuf_finish(sb); 5714 sbuf_delete(sb); 5715 5716 return (rc); 5717 } 5718 5719 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 5720 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 5721 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 5722 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 5723 }; 5724 5725 static int 5726 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 5727 { 5728 struct adapter *sc = arg1; 5729 struct sbuf *sb; 5730 int rc, i, n, qid = arg2; 5731 uint32_t *buf, *p; 5732 char *qtype; 5733 u_int cim_num_obq = sc->chip_params->cim_num_obq; 5734 5735 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 5736 ("%s: bad qid %d\n", __func__, qid)); 5737 5738 if (qid < CIM_NUM_IBQ) { 5739 /* inbound queue */ 5740 qtype = "IBQ"; 5741 n = 4 * CIM_IBQ_SIZE; 5742 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5743 rc = t4_read_cim_ibq(sc, qid, buf, n); 5744 } else { 5745 /* outbound queue */ 5746 qtype = "OBQ"; 5747 qid -= CIM_NUM_IBQ; 5748 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 5749 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5750 rc = t4_read_cim_obq(sc, qid, buf, n); 5751 } 5752 5753 if (rc < 0) { 5754 rc = -rc; 5755 goto done; 5756 } 5757 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 5758 5759 rc = sysctl_wire_old_buffer(req, 0); 5760 if (rc != 0) 5761 goto done; 5762 5763 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 5764 if (sb == NULL) { 5765 rc = ENOMEM; 5766 goto done; 5767 } 5768 5769 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 5770 for (i = 0, p = buf; i < n; i += 16, p += 4) 5771 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 5772 p[2], p[3]); 5773 5774 rc = sbuf_finish(sb); 5775 sbuf_delete(sb); 5776 done: 5777 free(buf, M_CXGBE); 5778 return (rc); 5779 } 5780 5781 static int 5782 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 5783 { 5784 struct adapter *sc = arg1; 5785 u_int cfg; 5786 struct sbuf *sb; 5787 uint32_t *buf, *p; 5788 int rc; 5789 5790 MPASS(chip_id(sc) <= CHELSIO_T5); 5791 5792 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 5793 if (rc != 0) 5794 return (rc); 5795 5796 rc = sysctl_wire_old_buffer(req, 0); 5797 if (rc != 0) 5798 return (rc); 5799 5800 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5801 if (sb == NULL) 5802 return (ENOMEM); 5803 5804 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 5805 M_ZERO | M_WAITOK); 5806 5807 rc = -t4_cim_read_la(sc, buf, NULL); 5808 if (rc != 0) 5809 goto done; 5810 5811 sbuf_printf(sb, "Status Data PC%s", 5812 cfg & F_UPDBGLACAPTPCONLY ? "" : 5813 " LS0Stat LS0Addr LS0Data"); 5814 5815 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 5816 if (cfg & F_UPDBGLACAPTPCONLY) { 5817 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 5818 p[6], p[7]); 5819 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 5820 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 5821 p[4] & 0xff, p[5] >> 8); 5822 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 5823 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 5824 p[1] & 0xf, p[2] >> 4); 5825 } else { 5826 sbuf_printf(sb, 5827 "\n %02x %x%07x %x%07x %08x %08x " 5828 "%08x%08x%08x%08x", 5829 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 5830 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 5831 p[6], p[7]); 5832 } 5833 } 5834 5835 rc = sbuf_finish(sb); 5836 sbuf_delete(sb); 5837 done: 5838 free(buf, M_CXGBE); 5839 return (rc); 5840 } 5841 5842 static int 5843 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 5844 { 5845 struct adapter *sc = arg1; 5846 u_int cfg; 5847 struct sbuf *sb; 5848 uint32_t *buf, *p; 5849 int rc; 5850 5851 MPASS(chip_id(sc) > CHELSIO_T5); 5852 5853 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 5854 if (rc != 0) 5855 return (rc); 5856 5857 rc = sysctl_wire_old_buffer(req, 0); 5858 if (rc != 0) 5859 return (rc); 5860 5861 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5862 if (sb == NULL) 5863 return (ENOMEM); 5864 5865 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 5866 M_ZERO | M_WAITOK); 5867 5868 rc = -t4_cim_read_la(sc, buf, NULL); 5869 if (rc != 0) 5870 goto done; 5871 5872 sbuf_printf(sb, "Status Inst Data PC%s", 5873 cfg & F_UPDBGLACAPTPCONLY ? "" : 5874 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 5875 5876 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 5877 if (cfg & F_UPDBGLACAPTPCONLY) { 5878 sbuf_printf(sb, "\n %02x %08x %08x %08x", 5879 p[3] & 0xff, p[2], p[1], p[0]); 5880 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 5881 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 5882 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 5883 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 5884 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 5885 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 5886 p[6] >> 16); 5887 } else { 5888 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 5889 "%08x %08x %08x %08x %08x %08x", 5890 (p[9] >> 16) & 0xff, 5891 p[9] & 0xffff, p[8] >> 16, 5892 p[8] & 0xffff, p[7] >> 16, 5893 p[7] & 0xffff, p[6] >> 16, 5894 p[2], p[1], p[0], p[5], p[4], p[3]); 5895 } 5896 } 5897 5898 rc = sbuf_finish(sb); 5899 sbuf_delete(sb); 5900 done: 5901 free(buf, M_CXGBE); 5902 return (rc); 5903 } 5904 5905 static int 5906 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 5907 { 5908 struct adapter *sc = arg1; 5909 u_int i; 5910 struct sbuf *sb; 5911 uint32_t *buf, *p; 5912 int rc; 5913 5914 rc = sysctl_wire_old_buffer(req, 0); 5915 if (rc != 0) 5916 return (rc); 5917 5918 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5919 if (sb == NULL) 5920 return (ENOMEM); 5921 5922 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 5923 M_ZERO | M_WAITOK); 5924 5925 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 5926 p = buf; 5927 5928 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 5929 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 5930 p[1], p[0]); 5931 } 5932 5933 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 5934 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 5935 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 5936 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 5937 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 5938 (p[1] >> 2) | ((p[2] & 3) << 30), 5939 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 5940 p[0] & 1); 5941 } 5942 5943 rc = sbuf_finish(sb); 5944 sbuf_delete(sb); 5945 free(buf, M_CXGBE); 5946 return (rc); 5947 } 5948 5949 static int 5950 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 5951 { 5952 struct adapter *sc = arg1; 5953 u_int i; 5954 struct sbuf *sb; 5955 uint32_t *buf, *p; 5956 int rc; 5957 5958 rc = sysctl_wire_old_buffer(req, 0); 5959 if (rc != 0) 5960 return (rc); 5961 5962 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5963 if (sb == NULL) 5964 return (ENOMEM); 5965 5966 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 5967 M_ZERO | M_WAITOK); 5968 5969 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 5970 p = buf; 5971 5972 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 5973 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 5974 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 5975 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 5976 p[4], p[3], p[2], p[1], p[0]); 5977 } 5978 5979 sbuf_printf(sb, "\n\nCntl ID Data"); 5980 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 5981 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 5982 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 5983 } 5984 5985 rc = sbuf_finish(sb); 5986 sbuf_delete(sb); 5987 free(buf, M_CXGBE); 5988 return (rc); 5989 } 5990 5991 static int 5992 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 5993 { 5994 struct adapter *sc = arg1; 5995 struct sbuf *sb; 5996 int rc, i; 5997 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 5998 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 5999 uint16_t thres[CIM_NUM_IBQ]; 6000 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 6001 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 6002 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 6003 6004 cim_num_obq = sc->chip_params->cim_num_obq; 6005 if (is_t4(sc)) { 6006 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 6007 obq_rdaddr = A_UP_OBQ_0_REALADDR; 6008 } else { 6009 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 6010 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 6011 } 6012 nq = CIM_NUM_IBQ + cim_num_obq; 6013 6014 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 6015 if (rc == 0) 6016 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 6017 if (rc != 0) 6018 return (rc); 6019 6020 t4_read_cimq_cfg(sc, base, size, thres); 6021 6022 rc = sysctl_wire_old_buffer(req, 0); 6023 if (rc != 0) 6024 return (rc); 6025 6026 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6027 if (sb == NULL) 6028 return (ENOMEM); 6029 6030 sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 6031 6032 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 6033 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 6034 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 6035 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6036 G_QUEREMFLITS(p[2]) * 16); 6037 for ( ; i < nq; i++, p += 4, wr += 2) 6038 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 6039 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 6040 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6041 G_QUEREMFLITS(p[2]) * 16); 6042 6043 rc = sbuf_finish(sb); 6044 sbuf_delete(sb); 6045 6046 return (rc); 6047 } 6048 6049 static int 6050 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 6051 { 6052 struct adapter *sc = arg1; 6053 struct sbuf *sb; 6054 int rc; 6055 struct tp_cpl_stats stats; 6056 6057 rc = sysctl_wire_old_buffer(req, 0); 6058 if (rc != 0) 6059 return (rc); 6060 6061 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6062 if (sb == NULL) 6063 return (ENOMEM); 6064 6065 mtx_lock(&sc->reg_lock); 6066 t4_tp_get_cpl_stats(sc, &stats); 6067 mtx_unlock(&sc->reg_lock); 6068 6069 if (sc->chip_params->nchan > 2) { 6070 sbuf_printf(sb, " channel 0 channel 1" 6071 " channel 2 channel 3"); 6072 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 6073 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 6074 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 6075 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 6076 } else { 6077 sbuf_printf(sb, " channel 0 channel 1"); 6078 sbuf_printf(sb, "\nCPL requests: %10u %10u", 6079 stats.req[0], stats.req[1]); 6080 sbuf_printf(sb, "\nCPL responses: %10u %10u", 6081 stats.rsp[0], stats.rsp[1]); 6082 } 6083 6084 rc = sbuf_finish(sb); 6085 sbuf_delete(sb); 6086 6087 return (rc); 6088 } 6089 6090 static int 6091 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 6092 { 6093 struct adapter *sc = arg1; 6094 struct sbuf *sb; 6095 int rc; 6096 struct tp_usm_stats stats; 6097 6098 rc = sysctl_wire_old_buffer(req, 0); 6099 if (rc != 0) 6100 return(rc); 6101 6102 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6103 if (sb == NULL) 6104 return (ENOMEM); 6105 6106 t4_get_usm_stats(sc, &stats); 6107 6108 sbuf_printf(sb, "Frames: %u\n", stats.frames); 6109 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 6110 sbuf_printf(sb, "Drops: %u", stats.drops); 6111 6112 rc = sbuf_finish(sb); 6113 sbuf_delete(sb); 6114 6115 return (rc); 6116 } 6117 6118 static const char * const devlog_level_strings[] = { 6119 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 6120 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 6121 [FW_DEVLOG_LEVEL_ERR] = "ERR", 6122 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 6123 [FW_DEVLOG_LEVEL_INFO] = "INFO", 6124 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 6125 }; 6126 6127 static const char * const devlog_facility_strings[] = { 6128 [FW_DEVLOG_FACILITY_CORE] = "CORE", 6129 [FW_DEVLOG_FACILITY_CF] = "CF", 6130 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 6131 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 6132 [FW_DEVLOG_FACILITY_RES] = "RES", 6133 [FW_DEVLOG_FACILITY_HW] = "HW", 6134 [FW_DEVLOG_FACILITY_FLR] = "FLR", 6135 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 6136 [FW_DEVLOG_FACILITY_PHY] = "PHY", 6137 [FW_DEVLOG_FACILITY_MAC] = "MAC", 6138 [FW_DEVLOG_FACILITY_PORT] = "PORT", 6139 [FW_DEVLOG_FACILITY_VI] = "VI", 6140 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 6141 [FW_DEVLOG_FACILITY_ACL] = "ACL", 6142 [FW_DEVLOG_FACILITY_TM] = "TM", 6143 [FW_DEVLOG_FACILITY_QFC] = "QFC", 6144 [FW_DEVLOG_FACILITY_DCB] = "DCB", 6145 [FW_DEVLOG_FACILITY_ETH] = "ETH", 6146 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 6147 [FW_DEVLOG_FACILITY_RI] = "RI", 6148 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 6149 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 6150 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 6151 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 6152 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 6153 }; 6154 6155 static int 6156 sysctl_devlog(SYSCTL_HANDLER_ARGS) 6157 { 6158 struct adapter *sc = arg1; 6159 struct devlog_params *dparams = &sc->params.devlog; 6160 struct fw_devlog_e *buf, *e; 6161 int i, j, rc, nentries, first = 0; 6162 struct sbuf *sb; 6163 uint64_t ftstamp = UINT64_MAX; 6164 6165 if (dparams->addr == 0) 6166 return (ENXIO); 6167 6168 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 6169 if (buf == NULL) 6170 return (ENOMEM); 6171 6172 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 6173 if (rc != 0) 6174 goto done; 6175 6176 nentries = dparams->size / sizeof(struct fw_devlog_e); 6177 for (i = 0; i < nentries; i++) { 6178 e = &buf[i]; 6179 6180 if (e->timestamp == 0) 6181 break; /* end */ 6182 6183 e->timestamp = be64toh(e->timestamp); 6184 e->seqno = be32toh(e->seqno); 6185 for (j = 0; j < 8; j++) 6186 e->params[j] = be32toh(e->params[j]); 6187 6188 if (e->timestamp < ftstamp) { 6189 ftstamp = e->timestamp; 6190 first = i; 6191 } 6192 } 6193 6194 if (buf[first].timestamp == 0) 6195 goto done; /* nothing in the log */ 6196 6197 rc = sysctl_wire_old_buffer(req, 0); 6198 if (rc != 0) 6199 goto done; 6200 6201 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6202 if (sb == NULL) { 6203 rc = ENOMEM; 6204 goto done; 6205 } 6206 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 6207 "Seq#", "Tstamp", "Level", "Facility", "Message"); 6208 6209 i = first; 6210 do { 6211 e = &buf[i]; 6212 if (e->timestamp == 0) 6213 break; /* end */ 6214 6215 sbuf_printf(sb, "%10d %15ju %8s %8s ", 6216 e->seqno, e->timestamp, 6217 (e->level < nitems(devlog_level_strings) ? 6218 devlog_level_strings[e->level] : "UNKNOWN"), 6219 (e->facility < nitems(devlog_facility_strings) ? 6220 devlog_facility_strings[e->facility] : "UNKNOWN")); 6221 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 6222 e->params[2], e->params[3], e->params[4], 6223 e->params[5], e->params[6], e->params[7]); 6224 6225 if (++i == nentries) 6226 i = 0; 6227 } while (i != first); 6228 6229 rc = sbuf_finish(sb); 6230 sbuf_delete(sb); 6231 done: 6232 free(buf, M_CXGBE); 6233 return (rc); 6234 } 6235 6236 static int 6237 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 6238 { 6239 struct adapter *sc = arg1; 6240 struct sbuf *sb; 6241 int rc; 6242 struct tp_fcoe_stats stats[MAX_NCHAN]; 6243 int i, nchan = sc->chip_params->nchan; 6244 6245 rc = sysctl_wire_old_buffer(req, 0); 6246 if (rc != 0) 6247 return (rc); 6248 6249 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6250 if (sb == NULL) 6251 return (ENOMEM); 6252 6253 for (i = 0; i < nchan; i++) 6254 t4_get_fcoe_stats(sc, i, &stats[i]); 6255 6256 if (nchan > 2) { 6257 sbuf_printf(sb, " channel 0 channel 1" 6258 " channel 2 channel 3"); 6259 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 6260 stats[0].octets_ddp, stats[1].octets_ddp, 6261 stats[2].octets_ddp, stats[3].octets_ddp); 6262 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 6263 stats[0].frames_ddp, stats[1].frames_ddp, 6264 stats[2].frames_ddp, stats[3].frames_ddp); 6265 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 6266 stats[0].frames_drop, stats[1].frames_drop, 6267 stats[2].frames_drop, stats[3].frames_drop); 6268 } else { 6269 sbuf_printf(sb, " channel 0 channel 1"); 6270 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 6271 stats[0].octets_ddp, stats[1].octets_ddp); 6272 sbuf_printf(sb, "\nframesDDP: %16u %16u", 6273 stats[0].frames_ddp, stats[1].frames_ddp); 6274 sbuf_printf(sb, "\nframesDrop: %16u %16u", 6275 stats[0].frames_drop, stats[1].frames_drop); 6276 } 6277 6278 rc = sbuf_finish(sb); 6279 sbuf_delete(sb); 6280 6281 return (rc); 6282 } 6283 6284 static int 6285 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 6286 { 6287 struct adapter *sc = arg1; 6288 struct sbuf *sb; 6289 int rc, i; 6290 unsigned int map, kbps, ipg, mode; 6291 unsigned int pace_tab[NTX_SCHED]; 6292 6293 rc = sysctl_wire_old_buffer(req, 0); 6294 if (rc != 0) 6295 return (rc); 6296 6297 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6298 if (sb == NULL) 6299 return (ENOMEM); 6300 6301 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 6302 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 6303 t4_read_pace_tbl(sc, pace_tab); 6304 6305 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 6306 "Class IPG (0.1 ns) Flow IPG (us)"); 6307 6308 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 6309 t4_get_tx_sched(sc, i, &kbps, &ipg); 6310 sbuf_printf(sb, "\n %u %-5s %u ", i, 6311 (mode & (1 << i)) ? "flow" : "class", map & 3); 6312 if (kbps) 6313 sbuf_printf(sb, "%9u ", kbps); 6314 else 6315 sbuf_printf(sb, " disabled "); 6316 6317 if (ipg) 6318 sbuf_printf(sb, "%13u ", ipg); 6319 else 6320 sbuf_printf(sb, " disabled "); 6321 6322 if (pace_tab[i]) 6323 sbuf_printf(sb, "%10u", pace_tab[i]); 6324 else 6325 sbuf_printf(sb, " disabled"); 6326 } 6327 6328 rc = sbuf_finish(sb); 6329 sbuf_delete(sb); 6330 6331 return (rc); 6332 } 6333 6334 static int 6335 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 6336 { 6337 struct adapter *sc = arg1; 6338 struct sbuf *sb; 6339 int rc, i, j; 6340 uint64_t *p0, *p1; 6341 struct lb_port_stats s[2]; 6342 static const char *stat_name[] = { 6343 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 6344 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 6345 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 6346 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 6347 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 6348 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 6349 "BG2FramesTrunc:", "BG3FramesTrunc:" 6350 }; 6351 6352 rc = sysctl_wire_old_buffer(req, 0); 6353 if (rc != 0) 6354 return (rc); 6355 6356 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6357 if (sb == NULL) 6358 return (ENOMEM); 6359 6360 memset(s, 0, sizeof(s)); 6361 6362 for (i = 0; i < sc->chip_params->nchan; i += 2) { 6363 t4_get_lb_stats(sc, i, &s[0]); 6364 t4_get_lb_stats(sc, i + 1, &s[1]); 6365 6366 p0 = &s[0].octets; 6367 p1 = &s[1].octets; 6368 sbuf_printf(sb, "%s Loopback %u" 6369 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 6370 6371 for (j = 0; j < nitems(stat_name); j++) 6372 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 6373 *p0++, *p1++); 6374 } 6375 6376 rc = sbuf_finish(sb); 6377 sbuf_delete(sb); 6378 6379 return (rc); 6380 } 6381 6382 static int 6383 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 6384 { 6385 int rc = 0; 6386 struct port_info *pi = arg1; 6387 struct sbuf *sb; 6388 6389 rc = sysctl_wire_old_buffer(req, 0); 6390 if (rc != 0) 6391 return(rc); 6392 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 6393 if (sb == NULL) 6394 return (ENOMEM); 6395 6396 if (pi->linkdnrc < 0) 6397 sbuf_printf(sb, "n/a"); 6398 else 6399 sbuf_printf(sb, "%s", t4_link_down_rc_str(pi->linkdnrc)); 6400 6401 rc = sbuf_finish(sb); 6402 sbuf_delete(sb); 6403 6404 return (rc); 6405 } 6406 6407 struct mem_desc { 6408 unsigned int base; 6409 unsigned int limit; 6410 unsigned int idx; 6411 }; 6412 6413 static int 6414 mem_desc_cmp(const void *a, const void *b) 6415 { 6416 return ((const struct mem_desc *)a)->base - 6417 ((const struct mem_desc *)b)->base; 6418 } 6419 6420 static void 6421 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 6422 unsigned int to) 6423 { 6424 unsigned int size; 6425 6426 if (from == to) 6427 return; 6428 6429 size = to - from + 1; 6430 if (size == 0) 6431 return; 6432 6433 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 6434 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 6435 } 6436 6437 static int 6438 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 6439 { 6440 struct adapter *sc = arg1; 6441 struct sbuf *sb; 6442 int rc, i, n; 6443 uint32_t lo, hi, used, alloc; 6444 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 6445 static const char *region[] = { 6446 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 6447 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 6448 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 6449 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 6450 "RQUDP region:", "PBL region:", "TXPBL region:", 6451 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 6452 "On-chip queues:" 6453 }; 6454 struct mem_desc avail[4]; 6455 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 6456 struct mem_desc *md = mem; 6457 6458 rc = sysctl_wire_old_buffer(req, 0); 6459 if (rc != 0) 6460 return (rc); 6461 6462 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6463 if (sb == NULL) 6464 return (ENOMEM); 6465 6466 for (i = 0; i < nitems(mem); i++) { 6467 mem[i].limit = 0; 6468 mem[i].idx = i; 6469 } 6470 6471 /* Find and sort the populated memory ranges */ 6472 i = 0; 6473 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 6474 if (lo & F_EDRAM0_ENABLE) { 6475 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 6476 avail[i].base = G_EDRAM0_BASE(hi) << 20; 6477 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 6478 avail[i].idx = 0; 6479 i++; 6480 } 6481 if (lo & F_EDRAM1_ENABLE) { 6482 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 6483 avail[i].base = G_EDRAM1_BASE(hi) << 20; 6484 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 6485 avail[i].idx = 1; 6486 i++; 6487 } 6488 if (lo & F_EXT_MEM_ENABLE) { 6489 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 6490 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 6491 avail[i].limit = avail[i].base + 6492 (G_EXT_MEM_SIZE(hi) << 20); 6493 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 6494 i++; 6495 } 6496 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 6497 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 6498 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 6499 avail[i].limit = avail[i].base + 6500 (G_EXT_MEM1_SIZE(hi) << 20); 6501 avail[i].idx = 4; 6502 i++; 6503 } 6504 if (!i) /* no memory available */ 6505 return 0; 6506 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 6507 6508 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 6509 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 6510 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 6511 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 6512 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 6513 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 6514 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 6515 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 6516 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 6517 6518 /* the next few have explicit upper bounds */ 6519 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 6520 md->limit = md->base - 1 + 6521 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 6522 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 6523 md++; 6524 6525 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 6526 md->limit = md->base - 1 + 6527 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 6528 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 6529 md++; 6530 6531 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 6532 if (chip_id(sc) <= CHELSIO_T5) 6533 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 6534 else 6535 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 6536 md->limit = 0; 6537 } else { 6538 md->base = 0; 6539 md->idx = nitems(region); /* hide it */ 6540 } 6541 md++; 6542 6543 #define ulp_region(reg) \ 6544 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 6545 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 6546 6547 ulp_region(RX_ISCSI); 6548 ulp_region(RX_TDDP); 6549 ulp_region(TX_TPT); 6550 ulp_region(RX_STAG); 6551 ulp_region(RX_RQ); 6552 ulp_region(RX_RQUDP); 6553 ulp_region(RX_PBL); 6554 ulp_region(TX_PBL); 6555 #undef ulp_region 6556 6557 md->base = 0; 6558 md->idx = nitems(region); 6559 if (!is_t4(sc)) { 6560 uint32_t size = 0; 6561 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 6562 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 6563 6564 if (is_t5(sc)) { 6565 if (sge_ctrl & F_VFIFO_ENABLE) 6566 size = G_DBVFIFO_SIZE(fifo_size); 6567 } else 6568 size = G_T6_DBVFIFO_SIZE(fifo_size); 6569 6570 if (size) { 6571 md->base = G_BASEADDR(t4_read_reg(sc, 6572 A_SGE_DBVFIFO_BADDR)); 6573 md->limit = md->base + (size << 2) - 1; 6574 } 6575 } 6576 md++; 6577 6578 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 6579 md->limit = 0; 6580 md++; 6581 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 6582 md->limit = 0; 6583 md++; 6584 6585 md->base = sc->vres.ocq.start; 6586 if (sc->vres.ocq.size) 6587 md->limit = md->base + sc->vres.ocq.size - 1; 6588 else 6589 md->idx = nitems(region); /* hide it */ 6590 md++; 6591 6592 /* add any address-space holes, there can be up to 3 */ 6593 for (n = 0; n < i - 1; n++) 6594 if (avail[n].limit < avail[n + 1].base) 6595 (md++)->base = avail[n].limit; 6596 if (avail[n].limit) 6597 (md++)->base = avail[n].limit; 6598 6599 n = md - mem; 6600 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 6601 6602 for (lo = 0; lo < i; lo++) 6603 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 6604 avail[lo].limit - 1); 6605 6606 sbuf_printf(sb, "\n"); 6607 for (i = 0; i < n; i++) { 6608 if (mem[i].idx >= nitems(region)) 6609 continue; /* skip holes */ 6610 if (!mem[i].limit) 6611 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 6612 mem_region_show(sb, region[mem[i].idx], mem[i].base, 6613 mem[i].limit); 6614 } 6615 6616 sbuf_printf(sb, "\n"); 6617 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 6618 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 6619 mem_region_show(sb, "uP RAM:", lo, hi); 6620 6621 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 6622 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 6623 mem_region_show(sb, "uP Extmem2:", lo, hi); 6624 6625 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 6626 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 6627 G_PMRXMAXPAGE(lo), 6628 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 6629 (lo & F_PMRXNUMCHN) ? 2 : 1); 6630 6631 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 6632 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 6633 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 6634 G_PMTXMAXPAGE(lo), 6635 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 6636 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 6637 sbuf_printf(sb, "%u p-structs\n", 6638 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 6639 6640 for (i = 0; i < 4; i++) { 6641 if (chip_id(sc) > CHELSIO_T5) 6642 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 6643 else 6644 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 6645 if (is_t5(sc)) { 6646 used = G_T5_USED(lo); 6647 alloc = G_T5_ALLOC(lo); 6648 } else { 6649 used = G_USED(lo); 6650 alloc = G_ALLOC(lo); 6651 } 6652 /* For T6 these are MAC buffer groups */ 6653 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 6654 i, used, alloc); 6655 } 6656 for (i = 0; i < sc->chip_params->nchan; i++) { 6657 if (chip_id(sc) > CHELSIO_T5) 6658 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 6659 else 6660 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 6661 if (is_t5(sc)) { 6662 used = G_T5_USED(lo); 6663 alloc = G_T5_ALLOC(lo); 6664 } else { 6665 used = G_USED(lo); 6666 alloc = G_ALLOC(lo); 6667 } 6668 /* For T6 these are MAC buffer groups */ 6669 sbuf_printf(sb, 6670 "\nLoopback %d using %u pages out of %u allocated", 6671 i, used, alloc); 6672 } 6673 6674 rc = sbuf_finish(sb); 6675 sbuf_delete(sb); 6676 6677 return (rc); 6678 } 6679 6680 static inline void 6681 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 6682 { 6683 *mask = x | y; 6684 y = htobe64(y); 6685 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 6686 } 6687 6688 static int 6689 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 6690 { 6691 struct adapter *sc = arg1; 6692 struct sbuf *sb; 6693 int rc, i; 6694 6695 MPASS(chip_id(sc) <= CHELSIO_T5); 6696 6697 rc = sysctl_wire_old_buffer(req, 0); 6698 if (rc != 0) 6699 return (rc); 6700 6701 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6702 if (sb == NULL) 6703 return (ENOMEM); 6704 6705 sbuf_printf(sb, 6706 "Idx Ethernet address Mask Vld Ports PF" 6707 " VF Replication P0 P1 P2 P3 ML"); 6708 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 6709 uint64_t tcamx, tcamy, mask; 6710 uint32_t cls_lo, cls_hi; 6711 uint8_t addr[ETHER_ADDR_LEN]; 6712 6713 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 6714 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 6715 if (tcamx & tcamy) 6716 continue; 6717 tcamxy2valmask(tcamx, tcamy, addr, &mask); 6718 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 6719 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 6720 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 6721 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 6722 addr[3], addr[4], addr[5], (uintmax_t)mask, 6723 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 6724 G_PORTMAP(cls_hi), G_PF(cls_lo), 6725 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 6726 6727 if (cls_lo & F_REPLICATE) { 6728 struct fw_ldst_cmd ldst_cmd; 6729 6730 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 6731 ldst_cmd.op_to_addrspace = 6732 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 6733 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6734 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 6735 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 6736 ldst_cmd.u.mps.rplc.fid_idx = 6737 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 6738 V_FW_LDST_CMD_IDX(i)); 6739 6740 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 6741 "t4mps"); 6742 if (rc) 6743 break; 6744 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 6745 sizeof(ldst_cmd), &ldst_cmd); 6746 end_synchronized_op(sc, 0); 6747 6748 if (rc != 0) { 6749 sbuf_printf(sb, "%36d", rc); 6750 rc = 0; 6751 } else { 6752 sbuf_printf(sb, " %08x %08x %08x %08x", 6753 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 6754 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 6755 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 6756 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 6757 } 6758 } else 6759 sbuf_printf(sb, "%36s", ""); 6760 6761 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 6762 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 6763 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 6764 } 6765 6766 if (rc) 6767 (void) sbuf_finish(sb); 6768 else 6769 rc = sbuf_finish(sb); 6770 sbuf_delete(sb); 6771 6772 return (rc); 6773 } 6774 6775 static int 6776 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 6777 { 6778 struct adapter *sc = arg1; 6779 struct sbuf *sb; 6780 int rc, i; 6781 6782 MPASS(chip_id(sc) > CHELSIO_T5); 6783 6784 rc = sysctl_wire_old_buffer(req, 0); 6785 if (rc != 0) 6786 return (rc); 6787 6788 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6789 if (sb == NULL) 6790 return (ENOMEM); 6791 6792 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 6793 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 6794 " Replication" 6795 " P0 P1 P2 P3 ML\n"); 6796 6797 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 6798 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 6799 uint16_t ivlan; 6800 uint64_t tcamx, tcamy, val, mask; 6801 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 6802 uint8_t addr[ETHER_ADDR_LEN]; 6803 6804 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 6805 if (i < 256) 6806 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 6807 else 6808 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 6809 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 6810 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 6811 tcamy = G_DMACH(val) << 32; 6812 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 6813 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 6814 lookup_type = G_DATALKPTYPE(data2); 6815 port_num = G_DATAPORTNUM(data2); 6816 if (lookup_type && lookup_type != M_DATALKPTYPE) { 6817 /* Inner header VNI */ 6818 vniy = ((data2 & F_DATAVIDH2) << 23) | 6819 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 6820 dip_hit = data2 & F_DATADIPHIT; 6821 vlan_vld = 0; 6822 } else { 6823 vniy = 0; 6824 dip_hit = 0; 6825 vlan_vld = data2 & F_DATAVIDH2; 6826 ivlan = G_VIDL(val); 6827 } 6828 6829 ctl |= V_CTLXYBITSEL(1); 6830 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 6831 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 6832 tcamx = G_DMACH(val) << 32; 6833 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 6834 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 6835 if (lookup_type && lookup_type != M_DATALKPTYPE) { 6836 /* Inner header VNI mask */ 6837 vnix = ((data2 & F_DATAVIDH2) << 23) | 6838 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 6839 } else 6840 vnix = 0; 6841 6842 if (tcamx & tcamy) 6843 continue; 6844 tcamxy2valmask(tcamx, tcamy, addr, &mask); 6845 6846 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 6847 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 6848 6849 if (lookup_type && lookup_type != M_DATALKPTYPE) { 6850 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 6851 "%012jx %06x %06x - - %3c" 6852 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 6853 addr[1], addr[2], addr[3], addr[4], addr[5], 6854 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 6855 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 6856 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 6857 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 6858 } else { 6859 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 6860 "%012jx - - ", i, addr[0], addr[1], 6861 addr[2], addr[3], addr[4], addr[5], 6862 (uintmax_t)mask); 6863 6864 if (vlan_vld) 6865 sbuf_printf(sb, "%4u Y ", ivlan); 6866 else 6867 sbuf_printf(sb, " - N "); 6868 6869 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 6870 lookup_type ? 'I' : 'O', port_num, 6871 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 6872 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 6873 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 6874 } 6875 6876 6877 if (cls_lo & F_T6_REPLICATE) { 6878 struct fw_ldst_cmd ldst_cmd; 6879 6880 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 6881 ldst_cmd.op_to_addrspace = 6882 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 6883 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6884 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 6885 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 6886 ldst_cmd.u.mps.rplc.fid_idx = 6887 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 6888 V_FW_LDST_CMD_IDX(i)); 6889 6890 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 6891 "t6mps"); 6892 if (rc) 6893 break; 6894 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 6895 sizeof(ldst_cmd), &ldst_cmd); 6896 end_synchronized_op(sc, 0); 6897 6898 if (rc != 0) { 6899 sbuf_printf(sb, "%72d", rc); 6900 rc = 0; 6901 } else { 6902 sbuf_printf(sb, " %08x %08x %08x %08x" 6903 " %08x %08x %08x %08x", 6904 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 6905 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 6906 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 6907 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 6908 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 6909 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 6910 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 6911 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 6912 } 6913 } else 6914 sbuf_printf(sb, "%72s", ""); 6915 6916 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 6917 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 6918 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 6919 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 6920 } 6921 6922 if (rc) 6923 (void) sbuf_finish(sb); 6924 else 6925 rc = sbuf_finish(sb); 6926 sbuf_delete(sb); 6927 6928 return (rc); 6929 } 6930 6931 static int 6932 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 6933 { 6934 struct adapter *sc = arg1; 6935 struct sbuf *sb; 6936 int rc; 6937 uint16_t mtus[NMTUS]; 6938 6939 rc = sysctl_wire_old_buffer(req, 0); 6940 if (rc != 0) 6941 return (rc); 6942 6943 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6944 if (sb == NULL) 6945 return (ENOMEM); 6946 6947 t4_read_mtu_tbl(sc, mtus, NULL); 6948 6949 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 6950 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 6951 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 6952 mtus[14], mtus[15]); 6953 6954 rc = sbuf_finish(sb); 6955 sbuf_delete(sb); 6956 6957 return (rc); 6958 } 6959 6960 static int 6961 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 6962 { 6963 struct adapter *sc = arg1; 6964 struct sbuf *sb; 6965 int rc, i; 6966 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 6967 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 6968 static const char *tx_stats[MAX_PM_NSTATS] = { 6969 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 6970 "Tx FIFO wait", NULL, "Tx latency" 6971 }; 6972 static const char *rx_stats[MAX_PM_NSTATS] = { 6973 "Read:", "Write bypass:", "Write mem:", "Flush:", 6974 " Rx FIFO wait", NULL, "Rx latency" 6975 }; 6976 6977 rc = sysctl_wire_old_buffer(req, 0); 6978 if (rc != 0) 6979 return (rc); 6980 6981 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6982 if (sb == NULL) 6983 return (ENOMEM); 6984 6985 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 6986 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 6987 6988 sbuf_printf(sb, " Tx pcmds Tx bytes"); 6989 for (i = 0; i < 4; i++) { 6990 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 6991 tx_cyc[i]); 6992 } 6993 6994 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 6995 for (i = 0; i < 4; i++) { 6996 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 6997 rx_cyc[i]); 6998 } 6999 7000 if (chip_id(sc) > CHELSIO_T5) { 7001 sbuf_printf(sb, 7002 "\n Total wait Total occupancy"); 7003 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7004 tx_cyc[i]); 7005 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7006 rx_cyc[i]); 7007 7008 i += 2; 7009 MPASS(i < nitems(tx_stats)); 7010 7011 sbuf_printf(sb, 7012 "\n Reads Total wait"); 7013 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7014 tx_cyc[i]); 7015 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7016 rx_cyc[i]); 7017 } 7018 7019 rc = sbuf_finish(sb); 7020 sbuf_delete(sb); 7021 7022 return (rc); 7023 } 7024 7025 static int 7026 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 7027 { 7028 struct adapter *sc = arg1; 7029 struct sbuf *sb; 7030 int rc; 7031 struct tp_rdma_stats stats; 7032 7033 rc = sysctl_wire_old_buffer(req, 0); 7034 if (rc != 0) 7035 return (rc); 7036 7037 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7038 if (sb == NULL) 7039 return (ENOMEM); 7040 7041 mtx_lock(&sc->reg_lock); 7042 t4_tp_get_rdma_stats(sc, &stats); 7043 mtx_unlock(&sc->reg_lock); 7044 7045 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 7046 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 7047 7048 rc = sbuf_finish(sb); 7049 sbuf_delete(sb); 7050 7051 return (rc); 7052 } 7053 7054 static int 7055 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 7056 { 7057 struct adapter *sc = arg1; 7058 struct sbuf *sb; 7059 int rc; 7060 struct tp_tcp_stats v4, v6; 7061 7062 rc = sysctl_wire_old_buffer(req, 0); 7063 if (rc != 0) 7064 return (rc); 7065 7066 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7067 if (sb == NULL) 7068 return (ENOMEM); 7069 7070 mtx_lock(&sc->reg_lock); 7071 t4_tp_get_tcp_stats(sc, &v4, &v6); 7072 mtx_unlock(&sc->reg_lock); 7073 7074 sbuf_printf(sb, 7075 " IP IPv6\n"); 7076 sbuf_printf(sb, "OutRsts: %20u %20u\n", 7077 v4.tcp_out_rsts, v6.tcp_out_rsts); 7078 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 7079 v4.tcp_in_segs, v6.tcp_in_segs); 7080 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 7081 v4.tcp_out_segs, v6.tcp_out_segs); 7082 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 7083 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 7084 7085 rc = sbuf_finish(sb); 7086 sbuf_delete(sb); 7087 7088 return (rc); 7089 } 7090 7091 static int 7092 sysctl_tids(SYSCTL_HANDLER_ARGS) 7093 { 7094 struct adapter *sc = arg1; 7095 struct sbuf *sb; 7096 int rc; 7097 struct tid_info *t = &sc->tids; 7098 7099 rc = sysctl_wire_old_buffer(req, 0); 7100 if (rc != 0) 7101 return (rc); 7102 7103 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7104 if (sb == NULL) 7105 return (ENOMEM); 7106 7107 if (t->natids) { 7108 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 7109 t->atids_in_use); 7110 } 7111 7112 if (t->ntids) { 7113 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7114 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 7115 7116 if (b) { 7117 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1, 7118 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4, 7119 t->ntids - 1); 7120 } else { 7121 sbuf_printf(sb, "TID range: %u-%u", 7122 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4, 7123 t->ntids - 1); 7124 } 7125 } else 7126 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1); 7127 sbuf_printf(sb, ", in use: %u\n", 7128 atomic_load_acq_int(&t->tids_in_use)); 7129 } 7130 7131 if (t->nstids) { 7132 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 7133 t->stid_base + t->nstids - 1, t->stids_in_use); 7134 } 7135 7136 if (t->nftids) { 7137 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 7138 t->ftid_base + t->nftids - 1); 7139 } 7140 7141 if (t->netids) { 7142 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 7143 t->etid_base + t->netids - 1); 7144 } 7145 7146 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 7147 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 7148 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 7149 7150 rc = sbuf_finish(sb); 7151 sbuf_delete(sb); 7152 7153 return (rc); 7154 } 7155 7156 static int 7157 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 7158 { 7159 struct adapter *sc = arg1; 7160 struct sbuf *sb; 7161 int rc; 7162 struct tp_err_stats stats; 7163 7164 rc = sysctl_wire_old_buffer(req, 0); 7165 if (rc != 0) 7166 return (rc); 7167 7168 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7169 if (sb == NULL) 7170 return (ENOMEM); 7171 7172 mtx_lock(&sc->reg_lock); 7173 t4_tp_get_err_stats(sc, &stats); 7174 mtx_unlock(&sc->reg_lock); 7175 7176 if (sc->chip_params->nchan > 2) { 7177 sbuf_printf(sb, " channel 0 channel 1" 7178 " channel 2 channel 3\n"); 7179 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 7180 stats.mac_in_errs[0], stats.mac_in_errs[1], 7181 stats.mac_in_errs[2], stats.mac_in_errs[3]); 7182 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 7183 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 7184 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 7185 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 7186 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 7187 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 7188 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 7189 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 7190 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 7191 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 7192 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 7193 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 7194 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 7195 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 7196 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 7197 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 7198 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 7199 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 7200 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 7201 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 7202 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 7203 } else { 7204 sbuf_printf(sb, " channel 0 channel 1\n"); 7205 sbuf_printf(sb, "macInErrs: %10u %10u\n", 7206 stats.mac_in_errs[0], stats.mac_in_errs[1]); 7207 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 7208 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 7209 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 7210 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 7211 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 7212 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 7213 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 7214 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 7215 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 7216 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 7217 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 7218 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 7219 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 7220 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 7221 } 7222 7223 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 7224 stats.ofld_no_neigh, stats.ofld_cong_defer); 7225 7226 rc = sbuf_finish(sb); 7227 sbuf_delete(sb); 7228 7229 return (rc); 7230 } 7231 7232 static int 7233 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 7234 { 7235 struct adapter *sc = arg1; 7236 struct tp_params *tpp = &sc->params.tp; 7237 u_int mask; 7238 int rc; 7239 7240 mask = tpp->la_mask >> 16; 7241 rc = sysctl_handle_int(oidp, &mask, 0, req); 7242 if (rc != 0 || req->newptr == NULL) 7243 return (rc); 7244 if (mask > 0xffff) 7245 return (EINVAL); 7246 tpp->la_mask = mask << 16; 7247 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 7248 7249 return (0); 7250 } 7251 7252 struct field_desc { 7253 const char *name; 7254 u_int start; 7255 u_int width; 7256 }; 7257 7258 static void 7259 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 7260 { 7261 char buf[32]; 7262 int line_size = 0; 7263 7264 while (f->name) { 7265 uint64_t mask = (1ULL << f->width) - 1; 7266 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 7267 ((uintmax_t)v >> f->start) & mask); 7268 7269 if (line_size + len >= 79) { 7270 line_size = 8; 7271 sbuf_printf(sb, "\n "); 7272 } 7273 sbuf_printf(sb, "%s ", buf); 7274 line_size += len + 1; 7275 f++; 7276 } 7277 sbuf_printf(sb, "\n"); 7278 } 7279 7280 static const struct field_desc tp_la0[] = { 7281 { "RcfOpCodeOut", 60, 4 }, 7282 { "State", 56, 4 }, 7283 { "WcfState", 52, 4 }, 7284 { "RcfOpcSrcOut", 50, 2 }, 7285 { "CRxError", 49, 1 }, 7286 { "ERxError", 48, 1 }, 7287 { "SanityFailed", 47, 1 }, 7288 { "SpuriousMsg", 46, 1 }, 7289 { "FlushInputMsg", 45, 1 }, 7290 { "FlushInputCpl", 44, 1 }, 7291 { "RssUpBit", 43, 1 }, 7292 { "RssFilterHit", 42, 1 }, 7293 { "Tid", 32, 10 }, 7294 { "InitTcb", 31, 1 }, 7295 { "LineNumber", 24, 7 }, 7296 { "Emsg", 23, 1 }, 7297 { "EdataOut", 22, 1 }, 7298 { "Cmsg", 21, 1 }, 7299 { "CdataOut", 20, 1 }, 7300 { "EreadPdu", 19, 1 }, 7301 { "CreadPdu", 18, 1 }, 7302 { "TunnelPkt", 17, 1 }, 7303 { "RcfPeerFin", 16, 1 }, 7304 { "RcfReasonOut", 12, 4 }, 7305 { "TxCchannel", 10, 2 }, 7306 { "RcfTxChannel", 8, 2 }, 7307 { "RxEchannel", 6, 2 }, 7308 { "RcfRxChannel", 5, 1 }, 7309 { "RcfDataOutSrdy", 4, 1 }, 7310 { "RxDvld", 3, 1 }, 7311 { "RxOoDvld", 2, 1 }, 7312 { "RxCongestion", 1, 1 }, 7313 { "TxCongestion", 0, 1 }, 7314 { NULL } 7315 }; 7316 7317 static const struct field_desc tp_la1[] = { 7318 { "CplCmdIn", 56, 8 }, 7319 { "CplCmdOut", 48, 8 }, 7320 { "ESynOut", 47, 1 }, 7321 { "EAckOut", 46, 1 }, 7322 { "EFinOut", 45, 1 }, 7323 { "ERstOut", 44, 1 }, 7324 { "SynIn", 43, 1 }, 7325 { "AckIn", 42, 1 }, 7326 { "FinIn", 41, 1 }, 7327 { "RstIn", 40, 1 }, 7328 { "DataIn", 39, 1 }, 7329 { "DataInVld", 38, 1 }, 7330 { "PadIn", 37, 1 }, 7331 { "RxBufEmpty", 36, 1 }, 7332 { "RxDdp", 35, 1 }, 7333 { "RxFbCongestion", 34, 1 }, 7334 { "TxFbCongestion", 33, 1 }, 7335 { "TxPktSumSrdy", 32, 1 }, 7336 { "RcfUlpType", 28, 4 }, 7337 { "Eread", 27, 1 }, 7338 { "Ebypass", 26, 1 }, 7339 { "Esave", 25, 1 }, 7340 { "Static0", 24, 1 }, 7341 { "Cread", 23, 1 }, 7342 { "Cbypass", 22, 1 }, 7343 { "Csave", 21, 1 }, 7344 { "CPktOut", 20, 1 }, 7345 { "RxPagePoolFull", 18, 2 }, 7346 { "RxLpbkPkt", 17, 1 }, 7347 { "TxLpbkPkt", 16, 1 }, 7348 { "RxVfValid", 15, 1 }, 7349 { "SynLearned", 14, 1 }, 7350 { "SetDelEntry", 13, 1 }, 7351 { "SetInvEntry", 12, 1 }, 7352 { "CpcmdDvld", 11, 1 }, 7353 { "CpcmdSave", 10, 1 }, 7354 { "RxPstructsFull", 8, 2 }, 7355 { "EpcmdDvld", 7, 1 }, 7356 { "EpcmdFlush", 6, 1 }, 7357 { "EpcmdTrimPrefix", 5, 1 }, 7358 { "EpcmdTrimPostfix", 4, 1 }, 7359 { "ERssIp4Pkt", 3, 1 }, 7360 { "ERssIp6Pkt", 2, 1 }, 7361 { "ERssTcpUdpPkt", 1, 1 }, 7362 { "ERssFceFipPkt", 0, 1 }, 7363 { NULL } 7364 }; 7365 7366 static const struct field_desc tp_la2[] = { 7367 { "CplCmdIn", 56, 8 }, 7368 { "MpsVfVld", 55, 1 }, 7369 { "MpsPf", 52, 3 }, 7370 { "MpsVf", 44, 8 }, 7371 { "SynIn", 43, 1 }, 7372 { "AckIn", 42, 1 }, 7373 { "FinIn", 41, 1 }, 7374 { "RstIn", 40, 1 }, 7375 { "DataIn", 39, 1 }, 7376 { "DataInVld", 38, 1 }, 7377 { "PadIn", 37, 1 }, 7378 { "RxBufEmpty", 36, 1 }, 7379 { "RxDdp", 35, 1 }, 7380 { "RxFbCongestion", 34, 1 }, 7381 { "TxFbCongestion", 33, 1 }, 7382 { "TxPktSumSrdy", 32, 1 }, 7383 { "RcfUlpType", 28, 4 }, 7384 { "Eread", 27, 1 }, 7385 { "Ebypass", 26, 1 }, 7386 { "Esave", 25, 1 }, 7387 { "Static0", 24, 1 }, 7388 { "Cread", 23, 1 }, 7389 { "Cbypass", 22, 1 }, 7390 { "Csave", 21, 1 }, 7391 { "CPktOut", 20, 1 }, 7392 { "RxPagePoolFull", 18, 2 }, 7393 { "RxLpbkPkt", 17, 1 }, 7394 { "TxLpbkPkt", 16, 1 }, 7395 { "RxVfValid", 15, 1 }, 7396 { "SynLearned", 14, 1 }, 7397 { "SetDelEntry", 13, 1 }, 7398 { "SetInvEntry", 12, 1 }, 7399 { "CpcmdDvld", 11, 1 }, 7400 { "CpcmdSave", 10, 1 }, 7401 { "RxPstructsFull", 8, 2 }, 7402 { "EpcmdDvld", 7, 1 }, 7403 { "EpcmdFlush", 6, 1 }, 7404 { "EpcmdTrimPrefix", 5, 1 }, 7405 { "EpcmdTrimPostfix", 4, 1 }, 7406 { "ERssIp4Pkt", 3, 1 }, 7407 { "ERssIp6Pkt", 2, 1 }, 7408 { "ERssTcpUdpPkt", 1, 1 }, 7409 { "ERssFceFipPkt", 0, 1 }, 7410 { NULL } 7411 }; 7412 7413 static void 7414 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 7415 { 7416 7417 field_desc_show(sb, *p, tp_la0); 7418 } 7419 7420 static void 7421 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 7422 { 7423 7424 if (idx) 7425 sbuf_printf(sb, "\n"); 7426 field_desc_show(sb, p[0], tp_la0); 7427 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7428 field_desc_show(sb, p[1], tp_la0); 7429 } 7430 7431 static void 7432 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 7433 { 7434 7435 if (idx) 7436 sbuf_printf(sb, "\n"); 7437 field_desc_show(sb, p[0], tp_la0); 7438 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7439 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 7440 } 7441 7442 static int 7443 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 7444 { 7445 struct adapter *sc = arg1; 7446 struct sbuf *sb; 7447 uint64_t *buf, *p; 7448 int rc; 7449 u_int i, inc; 7450 void (*show_func)(struct sbuf *, uint64_t *, int); 7451 7452 rc = sysctl_wire_old_buffer(req, 0); 7453 if (rc != 0) 7454 return (rc); 7455 7456 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7457 if (sb == NULL) 7458 return (ENOMEM); 7459 7460 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 7461 7462 t4_tp_read_la(sc, buf, NULL); 7463 p = buf; 7464 7465 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 7466 case 2: 7467 inc = 2; 7468 show_func = tp_la_show2; 7469 break; 7470 case 3: 7471 inc = 2; 7472 show_func = tp_la_show3; 7473 break; 7474 default: 7475 inc = 1; 7476 show_func = tp_la_show; 7477 } 7478 7479 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 7480 (*show_func)(sb, p, i); 7481 7482 rc = sbuf_finish(sb); 7483 sbuf_delete(sb); 7484 free(buf, M_CXGBE); 7485 return (rc); 7486 } 7487 7488 static int 7489 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 7490 { 7491 struct adapter *sc = arg1; 7492 struct sbuf *sb; 7493 int rc; 7494 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 7495 7496 rc = sysctl_wire_old_buffer(req, 0); 7497 if (rc != 0) 7498 return (rc); 7499 7500 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7501 if (sb == NULL) 7502 return (ENOMEM); 7503 7504 t4_get_chan_txrate(sc, nrate, orate); 7505 7506 if (sc->chip_params->nchan > 2) { 7507 sbuf_printf(sb, " channel 0 channel 1" 7508 " channel 2 channel 3\n"); 7509 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 7510 nrate[0], nrate[1], nrate[2], nrate[3]); 7511 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 7512 orate[0], orate[1], orate[2], orate[3]); 7513 } else { 7514 sbuf_printf(sb, " channel 0 channel 1\n"); 7515 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 7516 nrate[0], nrate[1]); 7517 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 7518 orate[0], orate[1]); 7519 } 7520 7521 rc = sbuf_finish(sb); 7522 sbuf_delete(sb); 7523 7524 return (rc); 7525 } 7526 7527 static int 7528 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 7529 { 7530 struct adapter *sc = arg1; 7531 struct sbuf *sb; 7532 uint32_t *buf, *p; 7533 int rc, i; 7534 7535 rc = sysctl_wire_old_buffer(req, 0); 7536 if (rc != 0) 7537 return (rc); 7538 7539 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7540 if (sb == NULL) 7541 return (ENOMEM); 7542 7543 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 7544 M_ZERO | M_WAITOK); 7545 7546 t4_ulprx_read_la(sc, buf); 7547 p = buf; 7548 7549 sbuf_printf(sb, " Pcmd Type Message" 7550 " Data"); 7551 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 7552 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 7553 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 7554 } 7555 7556 rc = sbuf_finish(sb); 7557 sbuf_delete(sb); 7558 free(buf, M_CXGBE); 7559 return (rc); 7560 } 7561 7562 static int 7563 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 7564 { 7565 struct adapter *sc = arg1; 7566 struct sbuf *sb; 7567 int rc, v; 7568 7569 MPASS(chip_id(sc) >= CHELSIO_T5); 7570 7571 rc = sysctl_wire_old_buffer(req, 0); 7572 if (rc != 0) 7573 return (rc); 7574 7575 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7576 if (sb == NULL) 7577 return (ENOMEM); 7578 7579 v = t4_read_reg(sc, A_SGE_STAT_CFG); 7580 if (G_STATSOURCE_T5(v) == 7) { 7581 int mode; 7582 7583 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 7584 if (mode == 0) { 7585 sbuf_printf(sb, "total %d, incomplete %d", 7586 t4_read_reg(sc, A_SGE_STAT_TOTAL), 7587 t4_read_reg(sc, A_SGE_STAT_MATCH)); 7588 } else if (mode == 1) { 7589 sbuf_printf(sb, "total %d, data overflow %d", 7590 t4_read_reg(sc, A_SGE_STAT_TOTAL), 7591 t4_read_reg(sc, A_SGE_STAT_MATCH)); 7592 } else { 7593 sbuf_printf(sb, "unknown mode %d", mode); 7594 } 7595 } 7596 rc = sbuf_finish(sb); 7597 sbuf_delete(sb); 7598 7599 return (rc); 7600 } 7601 7602 static int 7603 sysctl_tc_params(SYSCTL_HANDLER_ARGS) 7604 { 7605 struct adapter *sc = arg1; 7606 struct tx_sched_class *tc; 7607 struct t4_sched_class_params p; 7608 struct sbuf *sb; 7609 int i, rc, port_id, flags, mbps, gbps; 7610 7611 rc = sysctl_wire_old_buffer(req, 0); 7612 if (rc != 0) 7613 return (rc); 7614 7615 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7616 if (sb == NULL) 7617 return (ENOMEM); 7618 7619 port_id = arg2 >> 16; 7620 MPASS(port_id < sc->params.nports); 7621 MPASS(sc->port[port_id] != NULL); 7622 i = arg2 & 0xffff; 7623 MPASS(i < sc->chip_params->nsched_cls); 7624 tc = &sc->port[port_id]->tc[i]; 7625 7626 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 7627 "t4tc_p"); 7628 if (rc) 7629 goto done; 7630 flags = tc->flags; 7631 p = tc->params; 7632 end_synchronized_op(sc, LOCK_HELD); 7633 7634 if ((flags & TX_SC_OK) == 0) { 7635 sbuf_printf(sb, "none"); 7636 goto done; 7637 } 7638 7639 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) { 7640 sbuf_printf(sb, "cl-wrr weight %u", p.weight); 7641 goto done; 7642 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL) 7643 sbuf_printf(sb, "cl-rl"); 7644 else if (p.level == SCHED_CLASS_LEVEL_CH_RL) 7645 sbuf_printf(sb, "ch-rl"); 7646 else { 7647 rc = ENXIO; 7648 goto done; 7649 } 7650 7651 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) { 7652 /* XXX: top speed or actual link speed? */ 7653 gbps = port_top_speed(sc->port[port_id]); 7654 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps); 7655 } 7656 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) { 7657 switch (p.rateunit) { 7658 case SCHED_CLASS_RATEUNIT_BITS: 7659 mbps = p.maxrate / 1000; 7660 gbps = p.maxrate / 1000000; 7661 if (p.maxrate == gbps * 1000000) 7662 sbuf_printf(sb, " %uGbps", gbps); 7663 else if (p.maxrate == mbps * 1000) 7664 sbuf_printf(sb, " %uMbps", mbps); 7665 else 7666 sbuf_printf(sb, " %uKbps", p.maxrate); 7667 break; 7668 case SCHED_CLASS_RATEUNIT_PKTS: 7669 sbuf_printf(sb, " %upps", p.maxrate); 7670 break; 7671 default: 7672 rc = ENXIO; 7673 goto done; 7674 } 7675 } 7676 7677 switch (p.mode) { 7678 case SCHED_CLASS_MODE_CLASS: 7679 sbuf_printf(sb, " aggregate"); 7680 break; 7681 case SCHED_CLASS_MODE_FLOW: 7682 sbuf_printf(sb, " per-flow"); 7683 break; 7684 default: 7685 rc = ENXIO; 7686 goto done; 7687 } 7688 7689 done: 7690 if (rc == 0) 7691 rc = sbuf_finish(sb); 7692 sbuf_delete(sb); 7693 7694 return (rc); 7695 } 7696 #endif 7697 7698 #ifdef TCP_OFFLOAD 7699 static void 7700 unit_conv(char *buf, size_t len, u_int val, u_int factor) 7701 { 7702 u_int rem = val % factor; 7703 7704 if (rem == 0) 7705 snprintf(buf, len, "%u", val / factor); 7706 else { 7707 while (rem % 10 == 0) 7708 rem /= 10; 7709 snprintf(buf, len, "%u.%u", val / factor, rem); 7710 } 7711 } 7712 7713 static int 7714 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 7715 { 7716 struct adapter *sc = arg1; 7717 char buf[16]; 7718 u_int res, re; 7719 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7720 7721 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 7722 switch (arg2) { 7723 case 0: 7724 /* timer_tick */ 7725 re = G_TIMERRESOLUTION(res); 7726 break; 7727 case 1: 7728 /* TCP timestamp tick */ 7729 re = G_TIMESTAMPRESOLUTION(res); 7730 break; 7731 case 2: 7732 /* DACK tick */ 7733 re = G_DELAYEDACKRESOLUTION(res); 7734 break; 7735 default: 7736 return (EDOOFUS); 7737 } 7738 7739 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 7740 7741 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 7742 } 7743 7744 static int 7745 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 7746 { 7747 struct adapter *sc = arg1; 7748 u_int res, dack_re, v; 7749 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7750 7751 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 7752 dack_re = G_DELAYEDACKRESOLUTION(res); 7753 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 7754 7755 return (sysctl_handle_int(oidp, &v, 0, req)); 7756 } 7757 7758 static int 7759 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 7760 { 7761 struct adapter *sc = arg1; 7762 int reg = arg2; 7763 u_int tre; 7764 u_long tp_tick_us, v; 7765 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7766 7767 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 7768 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 7769 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT || 7770 reg == A_TP_FINWAIT2_TIMER); 7771 7772 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 7773 tp_tick_us = (cclk_ps << tre) / 1000000; 7774 7775 if (reg == A_TP_INIT_SRTT) 7776 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 7777 else 7778 v = tp_tick_us * t4_read_reg(sc, reg); 7779 7780 return (sysctl_handle_long(oidp, &v, 0, req)); 7781 } 7782 #endif 7783 7784 static uint32_t 7785 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf) 7786 { 7787 uint32_t mode; 7788 7789 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR | 7790 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT; 7791 7792 if (fconf & F_FRAGMENTATION) 7793 mode |= T4_FILTER_IP_FRAGMENT; 7794 7795 if (fconf & F_MPSHITTYPE) 7796 mode |= T4_FILTER_MPS_HIT_TYPE; 7797 7798 if (fconf & F_MACMATCH) 7799 mode |= T4_FILTER_MAC_IDX; 7800 7801 if (fconf & F_ETHERTYPE) 7802 mode |= T4_FILTER_ETH_TYPE; 7803 7804 if (fconf & F_PROTOCOL) 7805 mode |= T4_FILTER_IP_PROTO; 7806 7807 if (fconf & F_TOS) 7808 mode |= T4_FILTER_IP_TOS; 7809 7810 if (fconf & F_VLAN) 7811 mode |= T4_FILTER_VLAN; 7812 7813 if (fconf & F_VNIC_ID) { 7814 mode |= T4_FILTER_VNIC; 7815 if (iconf & F_VNIC) 7816 mode |= T4_FILTER_IC_VNIC; 7817 } 7818 7819 if (fconf & F_PORT) 7820 mode |= T4_FILTER_PORT; 7821 7822 if (fconf & F_FCOE) 7823 mode |= T4_FILTER_FCoE; 7824 7825 return (mode); 7826 } 7827 7828 static uint32_t 7829 mode_to_fconf(uint32_t mode) 7830 { 7831 uint32_t fconf = 0; 7832 7833 if (mode & T4_FILTER_IP_FRAGMENT) 7834 fconf |= F_FRAGMENTATION; 7835 7836 if (mode & T4_FILTER_MPS_HIT_TYPE) 7837 fconf |= F_MPSHITTYPE; 7838 7839 if (mode & T4_FILTER_MAC_IDX) 7840 fconf |= F_MACMATCH; 7841 7842 if (mode & T4_FILTER_ETH_TYPE) 7843 fconf |= F_ETHERTYPE; 7844 7845 if (mode & T4_FILTER_IP_PROTO) 7846 fconf |= F_PROTOCOL; 7847 7848 if (mode & T4_FILTER_IP_TOS) 7849 fconf |= F_TOS; 7850 7851 if (mode & T4_FILTER_VLAN) 7852 fconf |= F_VLAN; 7853 7854 if (mode & T4_FILTER_VNIC) 7855 fconf |= F_VNIC_ID; 7856 7857 if (mode & T4_FILTER_PORT) 7858 fconf |= F_PORT; 7859 7860 if (mode & T4_FILTER_FCoE) 7861 fconf |= F_FCOE; 7862 7863 return (fconf); 7864 } 7865 7866 static uint32_t 7867 mode_to_iconf(uint32_t mode) 7868 { 7869 7870 if (mode & T4_FILTER_IC_VNIC) 7871 return (F_VNIC); 7872 return (0); 7873 } 7874 7875 static int check_fspec_against_fconf_iconf(struct adapter *sc, 7876 struct t4_filter_specification *fs) 7877 { 7878 struct tp_params *tpp = &sc->params.tp; 7879 uint32_t fconf = 0; 7880 7881 if (fs->val.frag || fs->mask.frag) 7882 fconf |= F_FRAGMENTATION; 7883 7884 if (fs->val.matchtype || fs->mask.matchtype) 7885 fconf |= F_MPSHITTYPE; 7886 7887 if (fs->val.macidx || fs->mask.macidx) 7888 fconf |= F_MACMATCH; 7889 7890 if (fs->val.ethtype || fs->mask.ethtype) 7891 fconf |= F_ETHERTYPE; 7892 7893 if (fs->val.proto || fs->mask.proto) 7894 fconf |= F_PROTOCOL; 7895 7896 if (fs->val.tos || fs->mask.tos) 7897 fconf |= F_TOS; 7898 7899 if (fs->val.vlan_vld || fs->mask.vlan_vld) 7900 fconf |= F_VLAN; 7901 7902 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) { 7903 fconf |= F_VNIC_ID; 7904 if (tpp->ingress_config & F_VNIC) 7905 return (EINVAL); 7906 } 7907 7908 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) { 7909 fconf |= F_VNIC_ID; 7910 if ((tpp->ingress_config & F_VNIC) == 0) 7911 return (EINVAL); 7912 } 7913 7914 if (fs->val.iport || fs->mask.iport) 7915 fconf |= F_PORT; 7916 7917 if (fs->val.fcoe || fs->mask.fcoe) 7918 fconf |= F_FCOE; 7919 7920 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map) 7921 return (E2BIG); 7922 7923 return (0); 7924 } 7925 7926 static int 7927 get_filter_mode(struct adapter *sc, uint32_t *mode) 7928 { 7929 struct tp_params *tpp = &sc->params.tp; 7930 7931 /* 7932 * We trust the cached values of the relevant TP registers. This means 7933 * things work reliably only if writes to those registers are always via 7934 * t4_set_filter_mode. 7935 */ 7936 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config); 7937 7938 return (0); 7939 } 7940 7941 static int 7942 set_filter_mode(struct adapter *sc, uint32_t mode) 7943 { 7944 struct tp_params *tpp = &sc->params.tp; 7945 uint32_t fconf, iconf; 7946 int rc; 7947 7948 iconf = mode_to_iconf(mode); 7949 if ((iconf ^ tpp->ingress_config) & F_VNIC) { 7950 /* 7951 * For now we just complain if A_TP_INGRESS_CONFIG is not 7952 * already set to the correct value for the requested filter 7953 * mode. It's not clear if it's safe to write to this register 7954 * on the fly. (And we trust the cached value of the register). 7955 */ 7956 return (EBUSY); 7957 } 7958 7959 fconf = mode_to_fconf(mode); 7960 7961 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 7962 "t4setfm"); 7963 if (rc) 7964 return (rc); 7965 7966 if (sc->tids.ftids_in_use > 0) { 7967 rc = EBUSY; 7968 goto done; 7969 } 7970 7971 #ifdef TCP_OFFLOAD 7972 if (uld_active(sc, ULD_TOM)) { 7973 rc = EBUSY; 7974 goto done; 7975 } 7976 #endif 7977 7978 rc = -t4_set_filter_mode(sc, fconf); 7979 done: 7980 end_synchronized_op(sc, LOCK_HELD); 7981 return (rc); 7982 } 7983 7984 static inline uint64_t 7985 get_filter_hits(struct adapter *sc, uint32_t fid) 7986 { 7987 uint32_t tcb_addr; 7988 7989 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) + 7990 (fid + sc->tids.ftid_base) * TCB_SIZE; 7991 7992 if (is_t4(sc)) { 7993 uint64_t hits; 7994 7995 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8); 7996 return (be64toh(hits)); 7997 } else { 7998 uint32_t hits; 7999 8000 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4); 8001 return (be32toh(hits)); 8002 } 8003 } 8004 8005 static int 8006 get_filter(struct adapter *sc, struct t4_filter *t) 8007 { 8008 int i, rc, nfilters = sc->tids.nftids; 8009 struct filter_entry *f; 8010 8011 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8012 "t4getf"); 8013 if (rc) 8014 return (rc); 8015 8016 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL || 8017 t->idx >= nfilters) { 8018 t->idx = 0xffffffff; 8019 goto done; 8020 } 8021 8022 f = &sc->tids.ftid_tab[t->idx]; 8023 for (i = t->idx; i < nfilters; i++, f++) { 8024 if (f->valid) { 8025 t->idx = i; 8026 t->l2tidx = f->l2t ? f->l2t->idx : 0; 8027 t->smtidx = f->smtidx; 8028 if (f->fs.hitcnts) 8029 t->hits = get_filter_hits(sc, t->idx); 8030 else 8031 t->hits = UINT64_MAX; 8032 t->fs = f->fs; 8033 8034 goto done; 8035 } 8036 } 8037 8038 t->idx = 0xffffffff; 8039 done: 8040 end_synchronized_op(sc, LOCK_HELD); 8041 return (0); 8042 } 8043 8044 static int 8045 set_filter(struct adapter *sc, struct t4_filter *t) 8046 { 8047 unsigned int nfilters, nports; 8048 struct filter_entry *f; 8049 int i, rc; 8050 8051 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf"); 8052 if (rc) 8053 return (rc); 8054 8055 nfilters = sc->tids.nftids; 8056 nports = sc->params.nports; 8057 8058 if (nfilters == 0) { 8059 rc = ENOTSUP; 8060 goto done; 8061 } 8062 8063 if (t->idx >= nfilters) { 8064 rc = EINVAL; 8065 goto done; 8066 } 8067 8068 /* Validate against the global filter mode and ingress config */ 8069 rc = check_fspec_against_fconf_iconf(sc, &t->fs); 8070 if (rc != 0) 8071 goto done; 8072 8073 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) { 8074 rc = EINVAL; 8075 goto done; 8076 } 8077 8078 if (t->fs.val.iport >= nports) { 8079 rc = EINVAL; 8080 goto done; 8081 } 8082 8083 /* Can't specify an iq if not steering to it */ 8084 if (!t->fs.dirsteer && t->fs.iq) { 8085 rc = EINVAL; 8086 goto done; 8087 } 8088 8089 /* IPv6 filter idx must be 4 aligned */ 8090 if (t->fs.type == 1 && 8091 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) { 8092 rc = EINVAL; 8093 goto done; 8094 } 8095 8096 if (!(sc->flags & FULL_INIT_DONE) && 8097 ((rc = adapter_full_init(sc)) != 0)) 8098 goto done; 8099 8100 if (sc->tids.ftid_tab == NULL) { 8101 KASSERT(sc->tids.ftids_in_use == 0, 8102 ("%s: no memory allocated but filters_in_use > 0", 8103 __func__)); 8104 8105 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) * 8106 nfilters, M_CXGBE, M_NOWAIT | M_ZERO); 8107 if (sc->tids.ftid_tab == NULL) { 8108 rc = ENOMEM; 8109 goto done; 8110 } 8111 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF); 8112 } 8113 8114 for (i = 0; i < 4; i++) { 8115 f = &sc->tids.ftid_tab[t->idx + i]; 8116 8117 if (f->pending || f->valid) { 8118 rc = EBUSY; 8119 goto done; 8120 } 8121 if (f->locked) { 8122 rc = EPERM; 8123 goto done; 8124 } 8125 8126 if (t->fs.type == 0) 8127 break; 8128 } 8129 8130 f = &sc->tids.ftid_tab[t->idx]; 8131 f->fs = t->fs; 8132 8133 rc = set_filter_wr(sc, t->idx); 8134 done: 8135 end_synchronized_op(sc, 0); 8136 8137 if (rc == 0) { 8138 mtx_lock(&sc->tids.ftid_lock); 8139 for (;;) { 8140 if (f->pending == 0) { 8141 rc = f->valid ? 0 : EIO; 8142 break; 8143 } 8144 8145 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8146 PCATCH, "t4setfw", 0)) { 8147 rc = EINPROGRESS; 8148 break; 8149 } 8150 } 8151 mtx_unlock(&sc->tids.ftid_lock); 8152 } 8153 return (rc); 8154 } 8155 8156 static int 8157 del_filter(struct adapter *sc, struct t4_filter *t) 8158 { 8159 unsigned int nfilters; 8160 struct filter_entry *f; 8161 int rc; 8162 8163 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf"); 8164 if (rc) 8165 return (rc); 8166 8167 nfilters = sc->tids.nftids; 8168 8169 if (nfilters == 0) { 8170 rc = ENOTSUP; 8171 goto done; 8172 } 8173 8174 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 || 8175 t->idx >= nfilters) { 8176 rc = EINVAL; 8177 goto done; 8178 } 8179 8180 if (!(sc->flags & FULL_INIT_DONE)) { 8181 rc = EAGAIN; 8182 goto done; 8183 } 8184 8185 f = &sc->tids.ftid_tab[t->idx]; 8186 8187 if (f->pending) { 8188 rc = EBUSY; 8189 goto done; 8190 } 8191 if (f->locked) { 8192 rc = EPERM; 8193 goto done; 8194 } 8195 8196 if (f->valid) { 8197 t->fs = f->fs; /* extra info for the caller */ 8198 rc = del_filter_wr(sc, t->idx); 8199 } 8200 8201 done: 8202 end_synchronized_op(sc, 0); 8203 8204 if (rc == 0) { 8205 mtx_lock(&sc->tids.ftid_lock); 8206 for (;;) { 8207 if (f->pending == 0) { 8208 rc = f->valid ? EIO : 0; 8209 break; 8210 } 8211 8212 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8213 PCATCH, "t4delfw", 0)) { 8214 rc = EINPROGRESS; 8215 break; 8216 } 8217 } 8218 mtx_unlock(&sc->tids.ftid_lock); 8219 } 8220 8221 return (rc); 8222 } 8223 8224 static void 8225 clear_filter(struct filter_entry *f) 8226 { 8227 if (f->l2t) 8228 t4_l2t_release(f->l2t); 8229 8230 bzero(f, sizeof (*f)); 8231 } 8232 8233 static int 8234 set_filter_wr(struct adapter *sc, int fidx) 8235 { 8236 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8237 struct fw_filter_wr *fwr; 8238 unsigned int ftid, vnic_vld, vnic_vld_mask; 8239 struct wrq_cookie cookie; 8240 8241 ASSERT_SYNCHRONIZED_OP(sc); 8242 8243 if (f->fs.newdmac || f->fs.newvlan) { 8244 /* This filter needs an L2T entry; allocate one. */ 8245 f->l2t = t4_l2t_alloc_switching(sc->l2t); 8246 if (f->l2t == NULL) 8247 return (EAGAIN); 8248 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport, 8249 f->fs.dmac)) { 8250 t4_l2t_release(f->l2t); 8251 f->l2t = NULL; 8252 return (ENOMEM); 8253 } 8254 } 8255 8256 /* Already validated against fconf, iconf */ 8257 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0); 8258 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0); 8259 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld) 8260 vnic_vld = 1; 8261 else 8262 vnic_vld = 0; 8263 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld) 8264 vnic_vld_mask = 1; 8265 else 8266 vnic_vld_mask = 0; 8267 8268 ftid = sc->tids.ftid_base + fidx; 8269 8270 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8271 if (fwr == NULL) 8272 return (ENOMEM); 8273 bzero(fwr, sizeof(*fwr)); 8274 8275 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR)); 8276 fwr->len16_pkd = htobe32(FW_LEN16(*fwr)); 8277 fwr->tid_to_iq = 8278 htobe32(V_FW_FILTER_WR_TID(ftid) | 8279 V_FW_FILTER_WR_RQTYPE(f->fs.type) | 8280 V_FW_FILTER_WR_NOREPLY(0) | 8281 V_FW_FILTER_WR_IQ(f->fs.iq)); 8282 fwr->del_filter_to_l2tix = 8283 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) | 8284 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) | 8285 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) | 8286 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) | 8287 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) | 8288 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) | 8289 V_FW_FILTER_WR_DMAC(f->fs.newdmac) | 8290 V_FW_FILTER_WR_SMAC(f->fs.newsmac) | 8291 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT || 8292 f->fs.newvlan == VLAN_REWRITE) | 8293 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE || 8294 f->fs.newvlan == VLAN_REWRITE) | 8295 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) | 8296 V_FW_FILTER_WR_TXCHAN(f->fs.eport) | 8297 V_FW_FILTER_WR_PRIO(f->fs.prio) | 8298 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0)); 8299 fwr->ethtype = htobe16(f->fs.val.ethtype); 8300 fwr->ethtypem = htobe16(f->fs.mask.ethtype); 8301 fwr->frag_to_ovlan_vldm = 8302 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) | 8303 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) | 8304 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) | 8305 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) | 8306 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) | 8307 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask)); 8308 fwr->smac_sel = 0; 8309 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) | 8310 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id)); 8311 fwr->maci_to_matchtypem = 8312 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) | 8313 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) | 8314 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) | 8315 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) | 8316 V_FW_FILTER_WR_PORT(f->fs.val.iport) | 8317 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) | 8318 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) | 8319 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype)); 8320 fwr->ptcl = f->fs.val.proto; 8321 fwr->ptclm = f->fs.mask.proto; 8322 fwr->ttyp = f->fs.val.tos; 8323 fwr->ttypm = f->fs.mask.tos; 8324 fwr->ivlan = htobe16(f->fs.val.vlan); 8325 fwr->ivlanm = htobe16(f->fs.mask.vlan); 8326 fwr->ovlan = htobe16(f->fs.val.vnic); 8327 fwr->ovlanm = htobe16(f->fs.mask.vnic); 8328 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip)); 8329 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm)); 8330 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip)); 8331 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm)); 8332 fwr->lp = htobe16(f->fs.val.dport); 8333 fwr->lpm = htobe16(f->fs.mask.dport); 8334 fwr->fp = htobe16(f->fs.val.sport); 8335 fwr->fpm = htobe16(f->fs.mask.sport); 8336 if (f->fs.newsmac) 8337 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma)); 8338 8339 f->pending = 1; 8340 sc->tids.ftids_in_use++; 8341 8342 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8343 return (0); 8344 } 8345 8346 static int 8347 del_filter_wr(struct adapter *sc, int fidx) 8348 { 8349 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8350 struct fw_filter_wr *fwr; 8351 unsigned int ftid; 8352 struct wrq_cookie cookie; 8353 8354 ftid = sc->tids.ftid_base + fidx; 8355 8356 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8357 if (fwr == NULL) 8358 return (ENOMEM); 8359 bzero(fwr, sizeof (*fwr)); 8360 8361 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id); 8362 8363 f->pending = 1; 8364 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8365 return (0); 8366 } 8367 8368 int 8369 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8370 { 8371 struct adapter *sc = iq->adapter; 8372 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1); 8373 unsigned int idx = GET_TID(rpl); 8374 unsigned int rc; 8375 struct filter_entry *f; 8376 8377 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 8378 rss->opcode)); 8379 MPASS(iq == &sc->sge.fwq); 8380 MPASS(is_ftid(sc, idx)); 8381 8382 idx -= sc->tids.ftid_base; 8383 f = &sc->tids.ftid_tab[idx]; 8384 rc = G_COOKIE(rpl->cookie); 8385 8386 mtx_lock(&sc->tids.ftid_lock); 8387 if (rc == FW_FILTER_WR_FLT_ADDED) { 8388 KASSERT(f->pending, ("%s: filter[%u] isn't pending.", 8389 __func__, idx)); 8390 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; 8391 f->pending = 0; /* asynchronous setup completed */ 8392 f->valid = 1; 8393 } else { 8394 if (rc != FW_FILTER_WR_FLT_DELETED) { 8395 /* Add or delete failed, display an error */ 8396 log(LOG_ERR, 8397 "filter %u setup failed with error %u\n", 8398 idx, rc); 8399 } 8400 8401 clear_filter(f); 8402 sc->tids.ftids_in_use--; 8403 } 8404 wakeup(&sc->tids.ftid_tab); 8405 mtx_unlock(&sc->tids.ftid_lock); 8406 8407 return (0); 8408 } 8409 8410 static int 8411 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8412 { 8413 8414 MPASS(iq->set_tcb_rpl != NULL); 8415 return (iq->set_tcb_rpl(iq, rss, m)); 8416 } 8417 8418 static int 8419 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8420 { 8421 8422 MPASS(iq->l2t_write_rpl != NULL); 8423 return (iq->l2t_write_rpl(iq, rss, m)); 8424 } 8425 8426 static int 8427 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 8428 { 8429 int rc; 8430 8431 if (cntxt->cid > M_CTXTQID) 8432 return (EINVAL); 8433 8434 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 8435 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 8436 return (EINVAL); 8437 8438 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 8439 if (rc) 8440 return (rc); 8441 8442 if (sc->flags & FW_OK) { 8443 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 8444 &cntxt->data[0]); 8445 if (rc == 0) 8446 goto done; 8447 } 8448 8449 /* 8450 * Read via firmware failed or wasn't even attempted. Read directly via 8451 * the backdoor. 8452 */ 8453 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 8454 done: 8455 end_synchronized_op(sc, 0); 8456 return (rc); 8457 } 8458 8459 static int 8460 load_fw(struct adapter *sc, struct t4_data *fw) 8461 { 8462 int rc; 8463 uint8_t *fw_data; 8464 8465 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 8466 if (rc) 8467 return (rc); 8468 8469 if (sc->flags & FULL_INIT_DONE) { 8470 rc = EBUSY; 8471 goto done; 8472 } 8473 8474 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 8475 if (fw_data == NULL) { 8476 rc = ENOMEM; 8477 goto done; 8478 } 8479 8480 rc = copyin(fw->data, fw_data, fw->len); 8481 if (rc == 0) 8482 rc = -t4_load_fw(sc, fw_data, fw->len); 8483 8484 free(fw_data, M_CXGBE); 8485 done: 8486 end_synchronized_op(sc, 0); 8487 return (rc); 8488 } 8489 8490 #define MAX_READ_BUF_SIZE (128 * 1024) 8491 static int 8492 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 8493 { 8494 uint32_t addr, remaining, n; 8495 uint32_t *buf; 8496 int rc; 8497 uint8_t *dst; 8498 8499 rc = validate_mem_range(sc, mr->addr, mr->len); 8500 if (rc != 0) 8501 return (rc); 8502 8503 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 8504 addr = mr->addr; 8505 remaining = mr->len; 8506 dst = (void *)mr->data; 8507 8508 while (remaining) { 8509 n = min(remaining, MAX_READ_BUF_SIZE); 8510 read_via_memwin(sc, 2, addr, buf, n); 8511 8512 rc = copyout(buf, dst, n); 8513 if (rc != 0) 8514 break; 8515 8516 dst += n; 8517 remaining -= n; 8518 addr += n; 8519 } 8520 8521 free(buf, M_CXGBE); 8522 return (rc); 8523 } 8524 #undef MAX_READ_BUF_SIZE 8525 8526 static int 8527 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 8528 { 8529 int rc; 8530 8531 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 8532 return (EINVAL); 8533 8534 if (i2cd->len > sizeof(i2cd->data)) 8535 return (EFBIG); 8536 8537 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 8538 if (rc) 8539 return (rc); 8540 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 8541 i2cd->offset, i2cd->len, &i2cd->data[0]); 8542 end_synchronized_op(sc, 0); 8543 8544 return (rc); 8545 } 8546 8547 static int 8548 in_range(int val, int lo, int hi) 8549 { 8550 8551 return (val < 0 || (val <= hi && val >= lo)); 8552 } 8553 8554 static int 8555 set_sched_class_config(struct adapter *sc, int minmax) 8556 { 8557 int rc; 8558 8559 if (minmax < 0) 8560 return (EINVAL); 8561 8562 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc"); 8563 if (rc) 8564 return (rc); 8565 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1); 8566 end_synchronized_op(sc, 0); 8567 8568 return (rc); 8569 } 8570 8571 static int 8572 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p, 8573 int sleep_ok) 8574 { 8575 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode; 8576 struct port_info *pi; 8577 struct tx_sched_class *tc; 8578 8579 if (p->level == SCHED_CLASS_LEVEL_CL_RL) 8580 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL; 8581 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR) 8582 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 8583 else if (p->level == SCHED_CLASS_LEVEL_CH_RL) 8584 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL; 8585 else 8586 return (EINVAL); 8587 8588 if (p->mode == SCHED_CLASS_MODE_CLASS) 8589 fw_mode = FW_SCHED_PARAMS_MODE_CLASS; 8590 else if (p->mode == SCHED_CLASS_MODE_FLOW) 8591 fw_mode = FW_SCHED_PARAMS_MODE_FLOW; 8592 else 8593 return (EINVAL); 8594 8595 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS) 8596 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE; 8597 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS) 8598 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE; 8599 else 8600 return (EINVAL); 8601 8602 if (p->ratemode == SCHED_CLASS_RATEMODE_REL) 8603 fw_ratemode = FW_SCHED_PARAMS_RATE_REL; 8604 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS) 8605 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS; 8606 else 8607 return (EINVAL); 8608 8609 /* Vet our parameters ... */ 8610 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1)) 8611 return (ERANGE); 8612 8613 pi = sc->port[sc->chan_map[p->channel]]; 8614 if (pi == NULL) 8615 return (ENXIO); 8616 MPASS(pi->tx_chan == p->channel); 8617 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */ 8618 8619 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) || 8620 !in_range(p->minrate, 0, top_speed) || 8621 !in_range(p->maxrate, 0, top_speed) || 8622 !in_range(p->weight, 0, 100)) 8623 return (ERANGE); 8624 8625 /* 8626 * Translate any unset parameters into the firmware's 8627 * nomenclature and/or fail the call if the parameters 8628 * are required ... 8629 */ 8630 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0) 8631 return (EINVAL); 8632 8633 if (p->minrate < 0) 8634 p->minrate = 0; 8635 if (p->maxrate < 0) { 8636 if (p->level == SCHED_CLASS_LEVEL_CL_RL || 8637 p->level == SCHED_CLASS_LEVEL_CH_RL) 8638 return (EINVAL); 8639 else 8640 p->maxrate = 0; 8641 } 8642 if (p->weight < 0) { 8643 if (p->level == SCHED_CLASS_LEVEL_CL_WRR) 8644 return (EINVAL); 8645 else 8646 p->weight = 0; 8647 } 8648 if (p->pktsize < 0) { 8649 if (p->level == SCHED_CLASS_LEVEL_CL_RL || 8650 p->level == SCHED_CLASS_LEVEL_CH_RL) 8651 return (EINVAL); 8652 else 8653 p->pktsize = 0; 8654 } 8655 8656 rc = begin_synchronized_op(sc, NULL, 8657 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp"); 8658 if (rc) 8659 return (rc); 8660 tc = &pi->tc[p->cl]; 8661 tc->params = *p; 8662 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode, 8663 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate, 8664 p->weight, p->pktsize, sleep_ok); 8665 if (rc == 0) 8666 tc->flags |= TX_SC_OK; 8667 else { 8668 /* 8669 * Unknown state at this point, see tc->params for what was 8670 * attempted. 8671 */ 8672 tc->flags &= ~TX_SC_OK; 8673 } 8674 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD); 8675 8676 return (rc); 8677 } 8678 8679 int 8680 t4_set_sched_class(struct adapter *sc, struct t4_sched_params *p) 8681 { 8682 8683 if (p->type != SCHED_CLASS_TYPE_PACKET) 8684 return (EINVAL); 8685 8686 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG) 8687 return (set_sched_class_config(sc, p->u.config.minmax)); 8688 8689 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS) 8690 return (set_sched_class_params(sc, &p->u.params, 1)); 8691 8692 return (EINVAL); 8693 } 8694 8695 int 8696 t4_set_sched_queue(struct adapter *sc, struct t4_sched_queue *p) 8697 { 8698 struct port_info *pi = NULL; 8699 struct vi_info *vi; 8700 struct sge_txq *txq; 8701 uint32_t fw_mnem, fw_queue, fw_class; 8702 int i, rc; 8703 8704 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq"); 8705 if (rc) 8706 return (rc); 8707 8708 if (p->port >= sc->params.nports) { 8709 rc = EINVAL; 8710 goto done; 8711 } 8712 8713 /* XXX: Only supported for the main VI. */ 8714 pi = sc->port[p->port]; 8715 vi = &pi->vi[0]; 8716 if (!(vi->flags & VI_INIT_DONE)) { 8717 /* tx queues not set up yet */ 8718 rc = EAGAIN; 8719 goto done; 8720 } 8721 8722 if (!in_range(p->queue, 0, vi->ntxq - 1) || 8723 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) { 8724 rc = EINVAL; 8725 goto done; 8726 } 8727 8728 /* 8729 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX 8730 * Scheduling Class in this case). 8731 */ 8732 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 8733 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH)); 8734 fw_class = p->cl < 0 ? 0xffffffff : p->cl; 8735 8736 /* 8737 * If op.queue is non-negative, then we're only changing the scheduling 8738 * on a single specified TX queue. 8739 */ 8740 if (p->queue >= 0) { 8741 txq = &sc->sge.txq[vi->first_txq + p->queue]; 8742 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 8743 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 8744 &fw_class); 8745 goto done; 8746 } 8747 8748 /* 8749 * Change the scheduling on all the TX queues for the 8750 * interface. 8751 */ 8752 for_each_txq(vi, i, txq) { 8753 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 8754 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 8755 &fw_class); 8756 if (rc) 8757 goto done; 8758 } 8759 8760 rc = 0; 8761 done: 8762 end_synchronized_op(sc, 0); 8763 return (rc); 8764 } 8765 8766 int 8767 t4_os_find_pci_capability(struct adapter *sc, int cap) 8768 { 8769 int i; 8770 8771 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 8772 } 8773 8774 int 8775 t4_os_pci_save_state(struct adapter *sc) 8776 { 8777 device_t dev; 8778 struct pci_devinfo *dinfo; 8779 8780 dev = sc->dev; 8781 dinfo = device_get_ivars(dev); 8782 8783 pci_cfg_save(dev, dinfo, 0); 8784 return (0); 8785 } 8786 8787 int 8788 t4_os_pci_restore_state(struct adapter *sc) 8789 { 8790 device_t dev; 8791 struct pci_devinfo *dinfo; 8792 8793 dev = sc->dev; 8794 dinfo = device_get_ivars(dev); 8795 8796 pci_cfg_restore(dev, dinfo); 8797 return (0); 8798 } 8799 8800 void 8801 t4_os_portmod_changed(const struct adapter *sc, int idx) 8802 { 8803 struct port_info *pi = sc->port[idx]; 8804 struct vi_info *vi; 8805 struct ifnet *ifp; 8806 int v; 8807 static const char *mod_str[] = { 8808 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 8809 }; 8810 8811 for_each_vi(pi, v, vi) { 8812 build_medialist(pi, &vi->media); 8813 } 8814 8815 ifp = pi->vi[0].ifp; 8816 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 8817 if_printf(ifp, "transceiver unplugged.\n"); 8818 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 8819 if_printf(ifp, "unknown transceiver inserted.\n"); 8820 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 8821 if_printf(ifp, "unsupported transceiver inserted.\n"); 8822 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 8823 if_printf(ifp, "%s transceiver inserted.\n", 8824 mod_str[pi->mod_type]); 8825 } else { 8826 if_printf(ifp, "transceiver (type %d) inserted.\n", 8827 pi->mod_type); 8828 } 8829 } 8830 8831 void 8832 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason) 8833 { 8834 struct port_info *pi = sc->port[idx]; 8835 struct vi_info *vi; 8836 struct ifnet *ifp; 8837 int v; 8838 8839 if (link_stat) 8840 pi->linkdnrc = -1; 8841 else { 8842 if (reason >= 0) 8843 pi->linkdnrc = reason; 8844 } 8845 for_each_vi(pi, v, vi) { 8846 ifp = vi->ifp; 8847 if (ifp == NULL) 8848 continue; 8849 8850 if (link_stat) { 8851 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed); 8852 if_link_state_change(ifp, LINK_STATE_UP); 8853 } else { 8854 if_link_state_change(ifp, LINK_STATE_DOWN); 8855 } 8856 } 8857 } 8858 8859 void 8860 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 8861 { 8862 struct adapter *sc; 8863 8864 sx_slock(&t4_list_lock); 8865 SLIST_FOREACH(sc, &t4_list, link) { 8866 /* 8867 * func should not make any assumptions about what state sc is 8868 * in - the only guarantee is that sc->sc_lock is a valid lock. 8869 */ 8870 func(sc, arg); 8871 } 8872 sx_sunlock(&t4_list_lock); 8873 } 8874 8875 static int 8876 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 8877 struct thread *td) 8878 { 8879 int rc; 8880 struct adapter *sc = dev->si_drv1; 8881 8882 rc = priv_check(td, PRIV_DRIVER); 8883 if (rc != 0) 8884 return (rc); 8885 8886 switch (cmd) { 8887 case CHELSIO_T4_GETREG: { 8888 struct t4_reg *edata = (struct t4_reg *)data; 8889 8890 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 8891 return (EFAULT); 8892 8893 if (edata->size == 4) 8894 edata->val = t4_read_reg(sc, edata->addr); 8895 else if (edata->size == 8) 8896 edata->val = t4_read_reg64(sc, edata->addr); 8897 else 8898 return (EINVAL); 8899 8900 break; 8901 } 8902 case CHELSIO_T4_SETREG: { 8903 struct t4_reg *edata = (struct t4_reg *)data; 8904 8905 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 8906 return (EFAULT); 8907 8908 if (edata->size == 4) { 8909 if (edata->val & 0xffffffff00000000) 8910 return (EINVAL); 8911 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 8912 } else if (edata->size == 8) 8913 t4_write_reg64(sc, edata->addr, edata->val); 8914 else 8915 return (EINVAL); 8916 break; 8917 } 8918 case CHELSIO_T4_REGDUMP: { 8919 struct t4_regdump *regs = (struct t4_regdump *)data; 8920 int reglen = t4_get_regs_len(sc); 8921 uint8_t *buf; 8922 8923 if (regs->len < reglen) { 8924 regs->len = reglen; /* hint to the caller */ 8925 return (ENOBUFS); 8926 } 8927 8928 regs->len = reglen; 8929 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 8930 get_regs(sc, regs, buf); 8931 rc = copyout(buf, regs->data, reglen); 8932 free(buf, M_CXGBE); 8933 break; 8934 } 8935 case CHELSIO_T4_GET_FILTER_MODE: 8936 rc = get_filter_mode(sc, (uint32_t *)data); 8937 break; 8938 case CHELSIO_T4_SET_FILTER_MODE: 8939 rc = set_filter_mode(sc, *(uint32_t *)data); 8940 break; 8941 case CHELSIO_T4_GET_FILTER: 8942 rc = get_filter(sc, (struct t4_filter *)data); 8943 break; 8944 case CHELSIO_T4_SET_FILTER: 8945 rc = set_filter(sc, (struct t4_filter *)data); 8946 break; 8947 case CHELSIO_T4_DEL_FILTER: 8948 rc = del_filter(sc, (struct t4_filter *)data); 8949 break; 8950 case CHELSIO_T4_GET_SGE_CONTEXT: 8951 rc = get_sge_context(sc, (struct t4_sge_context *)data); 8952 break; 8953 case CHELSIO_T4_LOAD_FW: 8954 rc = load_fw(sc, (struct t4_data *)data); 8955 break; 8956 case CHELSIO_T4_GET_MEM: 8957 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 8958 break; 8959 case CHELSIO_T4_GET_I2C: 8960 rc = read_i2c(sc, (struct t4_i2c_data *)data); 8961 break; 8962 case CHELSIO_T4_CLEAR_STATS: { 8963 int i, v; 8964 u_int port_id = *(uint32_t *)data; 8965 struct port_info *pi; 8966 struct vi_info *vi; 8967 8968 if (port_id >= sc->params.nports) 8969 return (EINVAL); 8970 pi = sc->port[port_id]; 8971 if (pi == NULL) 8972 return (EIO); 8973 8974 /* MAC stats */ 8975 t4_clr_port_stats(sc, pi->tx_chan); 8976 pi->tx_parse_error = 0; 8977 mtx_lock(&sc->reg_lock); 8978 for_each_vi(pi, v, vi) { 8979 if (vi->flags & VI_INIT_DONE) 8980 t4_clr_vi_stats(sc, vi->viid); 8981 } 8982 mtx_unlock(&sc->reg_lock); 8983 8984 /* 8985 * Since this command accepts a port, clear stats for 8986 * all VIs on this port. 8987 */ 8988 for_each_vi(pi, v, vi) { 8989 if (vi->flags & VI_INIT_DONE) { 8990 struct sge_rxq *rxq; 8991 struct sge_txq *txq; 8992 struct sge_wrq *wrq; 8993 8994 for_each_rxq(vi, i, rxq) { 8995 #if defined(INET) || defined(INET6) 8996 rxq->lro.lro_queued = 0; 8997 rxq->lro.lro_flushed = 0; 8998 #endif 8999 rxq->rxcsum = 0; 9000 rxq->vlan_extraction = 0; 9001 } 9002 9003 for_each_txq(vi, i, txq) { 9004 txq->txcsum = 0; 9005 txq->tso_wrs = 0; 9006 txq->vlan_insertion = 0; 9007 txq->imm_wrs = 0; 9008 txq->sgl_wrs = 0; 9009 txq->txpkt_wrs = 0; 9010 txq->txpkts0_wrs = 0; 9011 txq->txpkts1_wrs = 0; 9012 txq->txpkts0_pkts = 0; 9013 txq->txpkts1_pkts = 0; 9014 mp_ring_reset_stats(txq->r); 9015 } 9016 9017 #ifdef TCP_OFFLOAD 9018 /* nothing to clear for each ofld_rxq */ 9019 9020 for_each_ofld_txq(vi, i, wrq) { 9021 wrq->tx_wrs_direct = 0; 9022 wrq->tx_wrs_copied = 0; 9023 } 9024 #endif 9025 9026 if (IS_MAIN_VI(vi)) { 9027 wrq = &sc->sge.ctrlq[pi->port_id]; 9028 wrq->tx_wrs_direct = 0; 9029 wrq->tx_wrs_copied = 0; 9030 } 9031 } 9032 } 9033 break; 9034 } 9035 case CHELSIO_T4_SCHED_CLASS: 9036 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9037 break; 9038 case CHELSIO_T4_SCHED_QUEUE: 9039 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9040 break; 9041 case CHELSIO_T4_GET_TRACER: 9042 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9043 break; 9044 case CHELSIO_T4_SET_TRACER: 9045 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9046 break; 9047 default: 9048 rc = ENOTTY; 9049 } 9050 9051 return (rc); 9052 } 9053 9054 void 9055 t4_db_full(struct adapter *sc) 9056 { 9057 9058 CXGBE_UNIMPLEMENTED(__func__); 9059 } 9060 9061 void 9062 t4_db_dropped(struct adapter *sc) 9063 { 9064 9065 CXGBE_UNIMPLEMENTED(__func__); 9066 } 9067 9068 #ifdef TCP_OFFLOAD 9069 static int 9070 toe_capability(struct vi_info *vi, int enable) 9071 { 9072 int rc; 9073 struct port_info *pi = vi->pi; 9074 struct adapter *sc = pi->adapter; 9075 9076 ASSERT_SYNCHRONIZED_OP(sc); 9077 9078 if (!is_offload(sc)) 9079 return (ENODEV); 9080 9081 if (enable) { 9082 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9083 /* TOE is already enabled. */ 9084 return (0); 9085 } 9086 9087 /* 9088 * We need the port's queues around so that we're able to send 9089 * and receive CPLs to/from the TOE even if the ifnet for this 9090 * port has never been UP'd administratively. 9091 */ 9092 if (!(vi->flags & VI_INIT_DONE)) { 9093 rc = vi_full_init(vi); 9094 if (rc) 9095 return (rc); 9096 } 9097 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9098 rc = vi_full_init(&pi->vi[0]); 9099 if (rc) 9100 return (rc); 9101 } 9102 9103 if (isset(&sc->offload_map, pi->port_id)) { 9104 /* TOE is enabled on another VI of this port. */ 9105 pi->uld_vis++; 9106 return (0); 9107 } 9108 9109 if (!uld_active(sc, ULD_TOM)) { 9110 rc = t4_activate_uld(sc, ULD_TOM); 9111 if (rc == EAGAIN) { 9112 log(LOG_WARNING, 9113 "You must kldload t4_tom.ko before trying " 9114 "to enable TOE on a cxgbe interface.\n"); 9115 } 9116 if (rc != 0) 9117 return (rc); 9118 KASSERT(sc->tom_softc != NULL, 9119 ("%s: TOM activated but softc NULL", __func__)); 9120 KASSERT(uld_active(sc, ULD_TOM), 9121 ("%s: TOM activated but flag not set", __func__)); 9122 } 9123 9124 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9125 if (!uld_active(sc, ULD_IWARP)) 9126 (void) t4_activate_uld(sc, ULD_IWARP); 9127 if (!uld_active(sc, ULD_ISCSI)) 9128 (void) t4_activate_uld(sc, ULD_ISCSI); 9129 9130 pi->uld_vis++; 9131 setbit(&sc->offload_map, pi->port_id); 9132 } else { 9133 pi->uld_vis--; 9134 9135 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9136 return (0); 9137 9138 KASSERT(uld_active(sc, ULD_TOM), 9139 ("%s: TOM never initialized?", __func__)); 9140 clrbit(&sc->offload_map, pi->port_id); 9141 } 9142 9143 return (0); 9144 } 9145 9146 /* 9147 * Add an upper layer driver to the global list. 9148 */ 9149 int 9150 t4_register_uld(struct uld_info *ui) 9151 { 9152 int rc = 0; 9153 struct uld_info *u; 9154 9155 sx_xlock(&t4_uld_list_lock); 9156 SLIST_FOREACH(u, &t4_uld_list, link) { 9157 if (u->uld_id == ui->uld_id) { 9158 rc = EEXIST; 9159 goto done; 9160 } 9161 } 9162 9163 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9164 ui->refcount = 0; 9165 done: 9166 sx_xunlock(&t4_uld_list_lock); 9167 return (rc); 9168 } 9169 9170 int 9171 t4_unregister_uld(struct uld_info *ui) 9172 { 9173 int rc = EINVAL; 9174 struct uld_info *u; 9175 9176 sx_xlock(&t4_uld_list_lock); 9177 9178 SLIST_FOREACH(u, &t4_uld_list, link) { 9179 if (u == ui) { 9180 if (ui->refcount > 0) { 9181 rc = EBUSY; 9182 goto done; 9183 } 9184 9185 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 9186 rc = 0; 9187 goto done; 9188 } 9189 } 9190 done: 9191 sx_xunlock(&t4_uld_list_lock); 9192 return (rc); 9193 } 9194 9195 int 9196 t4_activate_uld(struct adapter *sc, int id) 9197 { 9198 int rc; 9199 struct uld_info *ui; 9200 9201 ASSERT_SYNCHRONIZED_OP(sc); 9202 9203 if (id < 0 || id > ULD_MAX) 9204 return (EINVAL); 9205 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 9206 9207 sx_slock(&t4_uld_list_lock); 9208 9209 SLIST_FOREACH(ui, &t4_uld_list, link) { 9210 if (ui->uld_id == id) { 9211 if (!(sc->flags & FULL_INIT_DONE)) { 9212 rc = adapter_full_init(sc); 9213 if (rc != 0) 9214 break; 9215 } 9216 9217 rc = ui->activate(sc); 9218 if (rc == 0) { 9219 setbit(&sc->active_ulds, id); 9220 ui->refcount++; 9221 } 9222 break; 9223 } 9224 } 9225 9226 sx_sunlock(&t4_uld_list_lock); 9227 9228 return (rc); 9229 } 9230 9231 int 9232 t4_deactivate_uld(struct adapter *sc, int id) 9233 { 9234 int rc; 9235 struct uld_info *ui; 9236 9237 ASSERT_SYNCHRONIZED_OP(sc); 9238 9239 if (id < 0 || id > ULD_MAX) 9240 return (EINVAL); 9241 rc = ENXIO; 9242 9243 sx_slock(&t4_uld_list_lock); 9244 9245 SLIST_FOREACH(ui, &t4_uld_list, link) { 9246 if (ui->uld_id == id) { 9247 rc = ui->deactivate(sc); 9248 if (rc == 0) { 9249 clrbit(&sc->active_ulds, id); 9250 ui->refcount--; 9251 } 9252 break; 9253 } 9254 } 9255 9256 sx_sunlock(&t4_uld_list_lock); 9257 9258 return (rc); 9259 } 9260 9261 int 9262 uld_active(struct adapter *sc, int uld_id) 9263 { 9264 9265 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 9266 9267 return (isset(&sc->active_ulds, uld_id)); 9268 } 9269 #endif 9270 9271 /* 9272 * Come up with reasonable defaults for some of the tunables, provided they're 9273 * not set by the user (in which case we'll use the values as is). 9274 */ 9275 static void 9276 tweak_tunables(void) 9277 { 9278 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 9279 9280 if (t4_ntxq10g < 1) { 9281 #ifdef RSS 9282 t4_ntxq10g = rss_getnumbuckets(); 9283 #else 9284 t4_ntxq10g = min(nc, NTXQ_10G); 9285 #endif 9286 } 9287 9288 if (t4_ntxq1g < 1) { 9289 #ifdef RSS 9290 /* XXX: way too many for 1GbE? */ 9291 t4_ntxq1g = rss_getnumbuckets(); 9292 #else 9293 t4_ntxq1g = min(nc, NTXQ_1G); 9294 #endif 9295 } 9296 9297 if (t4_ntxq_vi < 1) 9298 t4_ntxq_vi = min(nc, NTXQ_VI); 9299 9300 if (t4_nrxq10g < 1) { 9301 #ifdef RSS 9302 t4_nrxq10g = rss_getnumbuckets(); 9303 #else 9304 t4_nrxq10g = min(nc, NRXQ_10G); 9305 #endif 9306 } 9307 9308 if (t4_nrxq1g < 1) { 9309 #ifdef RSS 9310 /* XXX: way too many for 1GbE? */ 9311 t4_nrxq1g = rss_getnumbuckets(); 9312 #else 9313 t4_nrxq1g = min(nc, NRXQ_1G); 9314 #endif 9315 } 9316 9317 if (t4_nrxq_vi < 1) 9318 t4_nrxq_vi = min(nc, NRXQ_VI); 9319 9320 #ifdef TCP_OFFLOAD 9321 if (t4_nofldtxq10g < 1) 9322 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G); 9323 9324 if (t4_nofldtxq1g < 1) 9325 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G); 9326 9327 if (t4_nofldtxq_vi < 1) 9328 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI); 9329 9330 if (t4_nofldrxq10g < 1) 9331 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G); 9332 9333 if (t4_nofldrxq1g < 1) 9334 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G); 9335 9336 if (t4_nofldrxq_vi < 1) 9337 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI); 9338 9339 if (t4_toecaps_allowed == -1) 9340 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 9341 9342 if (t4_rdmacaps_allowed == -1) { 9343 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 9344 FW_CAPS_CONFIG_RDMA_RDMAC; 9345 } 9346 9347 if (t4_iscsicaps_allowed == -1) { 9348 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 9349 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 9350 FW_CAPS_CONFIG_ISCSI_T10DIF; 9351 } 9352 #else 9353 if (t4_toecaps_allowed == -1) 9354 t4_toecaps_allowed = 0; 9355 9356 if (t4_rdmacaps_allowed == -1) 9357 t4_rdmacaps_allowed = 0; 9358 9359 if (t4_iscsicaps_allowed == -1) 9360 t4_iscsicaps_allowed = 0; 9361 #endif 9362 9363 #ifdef DEV_NETMAP 9364 if (t4_nnmtxq_vi < 1) 9365 t4_nnmtxq_vi = min(nc, NNMTXQ_VI); 9366 9367 if (t4_nnmrxq_vi < 1) 9368 t4_nnmrxq_vi = min(nc, NNMRXQ_VI); 9369 #endif 9370 9371 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS) 9372 t4_tmr_idx_10g = TMR_IDX_10G; 9373 9374 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS) 9375 t4_pktc_idx_10g = PKTC_IDX_10G; 9376 9377 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS) 9378 t4_tmr_idx_1g = TMR_IDX_1G; 9379 9380 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS) 9381 t4_pktc_idx_1g = PKTC_IDX_1G; 9382 9383 if (t4_qsize_txq < 128) 9384 t4_qsize_txq = 128; 9385 9386 if (t4_qsize_rxq < 128) 9387 t4_qsize_rxq = 128; 9388 while (t4_qsize_rxq & 7) 9389 t4_qsize_rxq++; 9390 9391 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 9392 } 9393 9394 #ifdef DDB 9395 static void 9396 t4_dump_tcb(struct adapter *sc, int tid) 9397 { 9398 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 9399 9400 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 9401 save = t4_read_reg(sc, reg); 9402 base = sc->memwin[2].mw_base; 9403 9404 /* Dump TCB for the tid */ 9405 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9406 tcb_addr += tid * TCB_SIZE; 9407 9408 if (is_t4(sc)) { 9409 pf = 0; 9410 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 9411 } else { 9412 pf = V_PFNUM(sc->pf); 9413 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 9414 } 9415 t4_write_reg(sc, reg, win_pos | pf); 9416 t4_read_reg(sc, reg); 9417 9418 off = tcb_addr - win_pos; 9419 for (i = 0; i < 4; i++) { 9420 uint32_t buf[8]; 9421 for (j = 0; j < 8; j++, off += 4) 9422 buf[j] = htonl(t4_read_reg(sc, base + off)); 9423 9424 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 9425 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 9426 buf[7]); 9427 } 9428 9429 t4_write_reg(sc, reg, save); 9430 t4_read_reg(sc, reg); 9431 } 9432 9433 static void 9434 t4_dump_devlog(struct adapter *sc) 9435 { 9436 struct devlog_params *dparams = &sc->params.devlog; 9437 struct fw_devlog_e e; 9438 int i, first, j, m, nentries, rc; 9439 uint64_t ftstamp = UINT64_MAX; 9440 9441 if (dparams->start == 0) { 9442 db_printf("devlog params not valid\n"); 9443 return; 9444 } 9445 9446 nentries = dparams->size / sizeof(struct fw_devlog_e); 9447 m = fwmtype_to_hwmtype(dparams->memtype); 9448 9449 /* Find the first entry. */ 9450 first = -1; 9451 for (i = 0; i < nentries && !db_pager_quit; i++) { 9452 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9453 sizeof(e), (void *)&e); 9454 if (rc != 0) 9455 break; 9456 9457 if (e.timestamp == 0) 9458 break; 9459 9460 e.timestamp = be64toh(e.timestamp); 9461 if (e.timestamp < ftstamp) { 9462 ftstamp = e.timestamp; 9463 first = i; 9464 } 9465 } 9466 9467 if (first == -1) 9468 return; 9469 9470 i = first; 9471 do { 9472 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9473 sizeof(e), (void *)&e); 9474 if (rc != 0) 9475 return; 9476 9477 if (e.timestamp == 0) 9478 return; 9479 9480 e.timestamp = be64toh(e.timestamp); 9481 e.seqno = be32toh(e.seqno); 9482 for (j = 0; j < 8; j++) 9483 e.params[j] = be32toh(e.params[j]); 9484 9485 db_printf("%10d %15ju %8s %8s ", 9486 e.seqno, e.timestamp, 9487 (e.level < nitems(devlog_level_strings) ? 9488 devlog_level_strings[e.level] : "UNKNOWN"), 9489 (e.facility < nitems(devlog_facility_strings) ? 9490 devlog_facility_strings[e.facility] : "UNKNOWN")); 9491 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 9492 e.params[3], e.params[4], e.params[5], e.params[6], 9493 e.params[7]); 9494 9495 if (++i == nentries) 9496 i = 0; 9497 } while (i != first && !db_pager_quit); 9498 } 9499 9500 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 9501 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 9502 9503 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 9504 { 9505 device_t dev; 9506 int t; 9507 bool valid; 9508 9509 valid = false; 9510 t = db_read_token(); 9511 if (t == tIDENT) { 9512 dev = device_lookup_by_name(db_tok_string); 9513 valid = true; 9514 } 9515 db_skip_to_eol(); 9516 if (!valid) { 9517 db_printf("usage: show t4 devlog <nexus>\n"); 9518 return; 9519 } 9520 9521 if (dev == NULL) { 9522 db_printf("device not found\n"); 9523 return; 9524 } 9525 9526 t4_dump_devlog(device_get_softc(dev)); 9527 } 9528 9529 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 9530 { 9531 device_t dev; 9532 int radix, tid, t; 9533 bool valid; 9534 9535 valid = false; 9536 radix = db_radix; 9537 db_radix = 10; 9538 t = db_read_token(); 9539 if (t == tIDENT) { 9540 dev = device_lookup_by_name(db_tok_string); 9541 t = db_read_token(); 9542 if (t == tNUMBER) { 9543 tid = db_tok_number; 9544 valid = true; 9545 } 9546 } 9547 db_radix = radix; 9548 db_skip_to_eol(); 9549 if (!valid) { 9550 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 9551 return; 9552 } 9553 9554 if (dev == NULL) { 9555 db_printf("device not found\n"); 9556 return; 9557 } 9558 if (tid < 0) { 9559 db_printf("invalid tid\n"); 9560 return; 9561 } 9562 9563 t4_dump_tcb(device_get_softc(dev), tid); 9564 } 9565 #endif 9566 9567 static struct sx mlu; /* mod load unload */ 9568 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 9569 9570 static int 9571 mod_event(module_t mod, int cmd, void *arg) 9572 { 9573 int rc = 0; 9574 static int loaded = 0; 9575 9576 switch (cmd) { 9577 case MOD_LOAD: 9578 sx_xlock(&mlu); 9579 if (loaded++ == 0) { 9580 t4_sge_modload(); 9581 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl); 9582 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl); 9583 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 9584 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 9585 sx_init(&t4_list_lock, "T4/T5 adapters"); 9586 SLIST_INIT(&t4_list); 9587 #ifdef TCP_OFFLOAD 9588 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 9589 SLIST_INIT(&t4_uld_list); 9590 #endif 9591 t4_tracer_modload(); 9592 tweak_tunables(); 9593 } 9594 sx_xunlock(&mlu); 9595 break; 9596 9597 case MOD_UNLOAD: 9598 sx_xlock(&mlu); 9599 if (--loaded == 0) { 9600 int tries; 9601 9602 sx_slock(&t4_list_lock); 9603 if (!SLIST_EMPTY(&t4_list)) { 9604 rc = EBUSY; 9605 sx_sunlock(&t4_list_lock); 9606 goto done_unload; 9607 } 9608 #ifdef TCP_OFFLOAD 9609 sx_slock(&t4_uld_list_lock); 9610 if (!SLIST_EMPTY(&t4_uld_list)) { 9611 rc = EBUSY; 9612 sx_sunlock(&t4_uld_list_lock); 9613 sx_sunlock(&t4_list_lock); 9614 goto done_unload; 9615 } 9616 #endif 9617 tries = 0; 9618 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 9619 uprintf("%ju clusters with custom free routine " 9620 "still is use.\n", t4_sge_extfree_refs()); 9621 pause("t4unload", 2 * hz); 9622 } 9623 #ifdef TCP_OFFLOAD 9624 sx_sunlock(&t4_uld_list_lock); 9625 #endif 9626 sx_sunlock(&t4_list_lock); 9627 9628 if (t4_sge_extfree_refs() == 0) { 9629 t4_tracer_modunload(); 9630 #ifdef TCP_OFFLOAD 9631 sx_destroy(&t4_uld_list_lock); 9632 #endif 9633 sx_destroy(&t4_list_lock); 9634 t4_sge_modunload(); 9635 loaded = 0; 9636 } else { 9637 rc = EBUSY; 9638 loaded++; /* undo earlier decrement */ 9639 } 9640 } 9641 done_unload: 9642 sx_xunlock(&mlu); 9643 break; 9644 } 9645 9646 return (rc); 9647 } 9648 9649 static devclass_t t4_devclass, t5_devclass; 9650 static devclass_t cxgbe_devclass, cxl_devclass; 9651 static devclass_t vcxgbe_devclass, vcxl_devclass; 9652 9653 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 9654 MODULE_VERSION(t4nex, 1); 9655 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 9656 #ifdef DEV_NETMAP 9657 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 9658 #endif /* DEV_NETMAP */ 9659 9660 9661 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 9662 MODULE_VERSION(t5nex, 1); 9663 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 9664 #ifdef DEV_NETMAP 9665 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 9666 #endif /* DEV_NETMAP */ 9667 9668 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 9669 MODULE_VERSION(cxgbe, 1); 9670 9671 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 9672 MODULE_VERSION(cxl, 1); 9673 9674 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 9675 MODULE_VERSION(vcxgbe, 1); 9676 9677 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 9678 MODULE_VERSION(vcxl, 1); 9679