xref: /freebsd/sys/dev/cxgbe/t4_main.c (revision 7b80c8b7d8d9a4a634c5fd5334a9fe40f9ca0b3b) 
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2011, 2025 Chelsio Communications.
5  * Written by: Navdeep Parhar <np@FreeBSD.org>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 #include "opt_ddb.h"
31 #include "opt_inet.h"
32 #include "opt_inet6.h"
33 #include "opt_kern_tls.h"
34 #include "opt_ratelimit.h"
35 #include "opt_rss.h"
36 
37 #include <sys/param.h>
38 #include <sys/conf.h>
39 #include <sys/priv.h>
40 #include <sys/kernel.h>
41 #include <sys/bus.h>
42 #include <sys/eventhandler.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/queue.h>
46 #include <sys/taskqueue.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <sys/firmware.h>
50 #include <sys/sbuf.h>
51 #include <sys/smp.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/sysctl.h>
55 #include <net/ethernet.h>
56 #include <net/if.h>
57 #include <net/if_types.h>
58 #include <net/if_dl.h>
59 #include <net/if_vlan_var.h>
60 #ifdef RSS
61 #include <net/rss_config.h>
62 #endif
63 #include <netinet/in.h>
64 #include <netinet/ip.h>
65 #ifdef KERN_TLS
66 #include <netinet/tcp_seq.h>
67 #endif
68 #if defined(__i386__) || defined(__amd64__)
69 #include <machine/md_var.h>
70 #include <machine/cputypes.h>
71 #include <vm/vm.h>
72 #include <vm/pmap.h>
73 #endif
74 #ifdef DDB
75 #include <ddb/ddb.h>
76 #include <ddb/db_lex.h>
77 #endif
78 
79 #include "common/common.h"
80 #include "common/t4_msg.h"
81 #include "common/t4_regs.h"
82 #include "common/t4_regs_values.h"
83 #include "cudbg/cudbg.h"
84 #include "t4_clip.h"
85 #include "t4_ioctl.h"
86 #include "t4_l2t.h"
87 #include "t4_mp_ring.h"
88 #include "t4_if.h"
89 #include "t4_smt.h"
90 
91 /* T4 bus driver interface */
92 static int t4_probe(device_t);
93 static int t4_attach(device_t);
94 static int t4_detach(device_t);
95 static int t4_child_location(device_t, device_t, struct sbuf *);
96 static int t4_ready(device_t);
97 static int t4_read_port_device(device_t, int, device_t *);
98 static int t4_suspend(device_t);
99 static int t4_resume(device_t);
100 static int t4_reset_prepare(device_t, device_t);
101 static int t4_reset_post(device_t, device_t);
102 static device_method_t t4_methods[] = {
103 	DEVMETHOD(device_probe,		t4_probe),
104 	DEVMETHOD(device_attach,	t4_attach),
105 	DEVMETHOD(device_detach,	t4_detach),
106 	DEVMETHOD(device_suspend,	t4_suspend),
107 	DEVMETHOD(device_resume,	t4_resume),
108 
109 	DEVMETHOD(bus_child_location,	t4_child_location),
110 	DEVMETHOD(bus_reset_prepare,	t4_reset_prepare),
111 	DEVMETHOD(bus_reset_post,	t4_reset_post),
112 
113 	DEVMETHOD(t4_is_main_ready,	t4_ready),
114 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
115 
116 	DEVMETHOD_END
117 };
118 static driver_t t4_driver = {
119 	"t4nex",
120 	t4_methods,
121 	sizeof(struct adapter)
122 };
123 
124 
125 /* T4 port (cxgbe) interface */
126 static int cxgbe_probe(device_t);
127 static int cxgbe_attach(device_t);
128 static int cxgbe_detach(device_t);
129 device_method_t cxgbe_methods[] = {
130 	DEVMETHOD(device_probe,		cxgbe_probe),
131 	DEVMETHOD(device_attach,	cxgbe_attach),
132 	DEVMETHOD(device_detach,	cxgbe_detach),
133 	{ 0, 0 }
134 };
135 static driver_t cxgbe_driver = {
136 	"cxgbe",
137 	cxgbe_methods,
138 	sizeof(struct port_info)
139 };
140 
141 /* T4 VI (vcxgbe) interface */
142 static int vcxgbe_probe(device_t);
143 static int vcxgbe_attach(device_t);
144 static int vcxgbe_detach(device_t);
145 static device_method_t vcxgbe_methods[] = {
146 	DEVMETHOD(device_probe,		vcxgbe_probe),
147 	DEVMETHOD(device_attach,	vcxgbe_attach),
148 	DEVMETHOD(device_detach,	vcxgbe_detach),
149 	{ 0, 0 }
150 };
151 static driver_t vcxgbe_driver = {
152 	"vcxgbe",
153 	vcxgbe_methods,
154 	sizeof(struct vi_info)
155 };
156 
157 static d_ioctl_t t4_ioctl;
158 
159 static struct cdevsw t4_cdevsw = {
160        .d_version = D_VERSION,
161        .d_ioctl = t4_ioctl,
162        .d_name = "t4nex",
163 };
164 
165 /* T5 bus driver interface */
166 static int t5_probe(device_t);
167 static device_method_t t5_methods[] = {
168 	DEVMETHOD(device_probe,		t5_probe),
169 	DEVMETHOD(device_attach,	t4_attach),
170 	DEVMETHOD(device_detach,	t4_detach),
171 	DEVMETHOD(device_suspend,	t4_suspend),
172 	DEVMETHOD(device_resume,	t4_resume),
173 
174 	DEVMETHOD(bus_child_location,	t4_child_location),
175 	DEVMETHOD(bus_reset_prepare,	t4_reset_prepare),
176 	DEVMETHOD(bus_reset_post,	t4_reset_post),
177 
178 	DEVMETHOD(t4_is_main_ready,	t4_ready),
179 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
180 
181 	DEVMETHOD_END
182 };
183 static driver_t t5_driver = {
184 	"t5nex",
185 	t5_methods,
186 	sizeof(struct adapter)
187 };
188 
189 
190 /* T5 port (cxl) interface */
191 static driver_t cxl_driver = {
192 	"cxl",
193 	cxgbe_methods,
194 	sizeof(struct port_info)
195 };
196 
197 /* T5 VI (vcxl) interface */
198 static driver_t vcxl_driver = {
199 	"vcxl",
200 	vcxgbe_methods,
201 	sizeof(struct vi_info)
202 };
203 
204 /* T6 bus driver interface */
205 static int t6_probe(device_t);
206 static device_method_t t6_methods[] = {
207 	DEVMETHOD(device_probe,		t6_probe),
208 	DEVMETHOD(device_attach,	t4_attach),
209 	DEVMETHOD(device_detach,	t4_detach),
210 	DEVMETHOD(device_suspend,	t4_suspend),
211 	DEVMETHOD(device_resume,	t4_resume),
212 
213 	DEVMETHOD(bus_child_location,	t4_child_location),
214 	DEVMETHOD(bus_reset_prepare,	t4_reset_prepare),
215 	DEVMETHOD(bus_reset_post,	t4_reset_post),
216 
217 	DEVMETHOD(t4_is_main_ready,	t4_ready),
218 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
219 
220 	DEVMETHOD_END
221 };
222 static driver_t t6_driver = {
223 	"t6nex",
224 	t6_methods,
225 	sizeof(struct adapter)
226 };
227 
228 
229 /* T6 port (cc) interface */
230 static driver_t cc_driver = {
231 	"cc",
232 	cxgbe_methods,
233 	sizeof(struct port_info)
234 };
235 
236 /* T6 VI (vcc) interface */
237 static driver_t vcc_driver = {
238 	"vcc",
239 	vcxgbe_methods,
240 	sizeof(struct vi_info)
241 };
242 
243 /* T7+ bus driver interface */
244 static int ch_probe(device_t);
245 static device_method_t ch_methods[] = {
246 	DEVMETHOD(device_probe,		ch_probe),
247 	DEVMETHOD(device_attach,	t4_attach),
248 	DEVMETHOD(device_detach,	t4_detach),
249 	DEVMETHOD(device_suspend,	t4_suspend),
250 	DEVMETHOD(device_resume,	t4_resume),
251 
252 	DEVMETHOD(bus_child_location,	t4_child_location),
253 	DEVMETHOD(bus_reset_prepare, 	t4_reset_prepare),
254 	DEVMETHOD(bus_reset_post, 	t4_reset_post),
255 
256 	DEVMETHOD(t4_is_main_ready,	t4_ready),
257 	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
258 
259 	DEVMETHOD_END
260 };
261 static driver_t ch_driver = {
262 	"chnex",
263 	ch_methods,
264 	sizeof(struct adapter)
265 };
266 
267 
268 /* T7+ port (che) interface */
269 static driver_t che_driver = {
270 	"che",
271 	cxgbe_methods,
272 	sizeof(struct port_info)
273 };
274 
275 /* T7+ VI (vche) interface */
276 static driver_t vche_driver = {
277 	"vche",
278 	vcxgbe_methods,
279 	sizeof(struct vi_info)
280 };
281 
282 /* ifnet interface */
283 static void cxgbe_init(void *);
284 static int cxgbe_ioctl(if_t, unsigned long, caddr_t);
285 static int cxgbe_transmit(if_t, struct mbuf *);
286 static void cxgbe_qflush(if_t);
287 #if defined(KERN_TLS) || defined(RATELIMIT)
288 static int cxgbe_snd_tag_alloc(if_t, union if_snd_tag_alloc_params *,
289     struct m_snd_tag **);
290 #endif
291 
292 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
293 
294 /*
295  * Correct lock order when you need to acquire multiple locks is t4_list_lock,
296  * then ADAPTER_LOCK, then t4_uld_list_lock.
297  */
298 static struct sx t4_list_lock;
299 SLIST_HEAD(, adapter) t4_list;
300 #ifdef TCP_OFFLOAD
301 static struct sx t4_uld_list_lock;
302 struct uld_info *t4_uld_list[ULD_MAX + 1];
303 #endif
304 
305 /*
306  * Tunables.  See tweak_tunables() too.
307  *
308  * Each tunable is set to a default value here if it's known at compile-time.
309  * Otherwise it is set to -n as an indication to tweak_tunables() that it should
310  * provide a reasonable default (upto n) when the driver is loaded.
311  *
312  * Tunables applicable to both T4 and T5 are under hw.cxgbe.  Those specific to
313  * T5 are under hw.cxl.
314  */
315 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
316     "cxgbe(4) parameters");
317 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
318     "cxgbe(4) T5+ parameters");
319 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
320     "cxgbe(4) TOE parameters");
321 
322 /*
323  * Number of queues for tx and rx, NIC and offload.
324  */
325 #define NTXQ 16
326 int t4_ntxq = -NTXQ;
327 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
328     "Number of TX queues per port");
329 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq);	/* Old name, undocumented */
330 
331 #define NRXQ 8
332 int t4_nrxq = -NRXQ;
333 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
334     "Number of RX queues per port");
335 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq);	/* Old name, undocumented */
336 
337 #define NTXQ_VI 1
338 static int t4_ntxq_vi = -NTXQ_VI;
339 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
340     "Number of TX queues per VI");
341 
342 #define NRXQ_VI 1
343 static int t4_nrxq_vi = -NRXQ_VI;
344 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
345     "Number of RX queues per VI");
346 
347 static int t4_rsrv_noflowq = 0;
348 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
349     0, "Reserve TX queue 0 of each VI for non-flowid packets");
350 
351 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
352 #define NOFLDTXQ 8
353 static int t4_nofldtxq = -NOFLDTXQ;
354 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
355     "Number of offload TX queues per port");
356 
357 #define NOFLDTXQ_VI 1
358 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
359 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
360     "Number of offload TX queues per VI");
361 #endif
362 
363 #if defined(TCP_OFFLOAD)
364 #define NOFLDRXQ 2
365 static int t4_nofldrxq = -NOFLDRXQ;
366 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
367     "Number of offload RX queues per port");
368 
369 #define NOFLDRXQ_VI 1
370 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
371 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
372     "Number of offload RX queues per VI");
373 
374 #define TMR_IDX_OFLD 1
375 static int t4_tmr_idx_ofld = TMR_IDX_OFLD;
376 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
377     &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
378 
379 #define PKTC_IDX_OFLD (-1)
380 static int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
381 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
382     &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
383 
384 /* 0 means chip/fw default, non-zero number is value in microseconds */
385 static u_long t4_toe_keepalive_idle = 0;
386 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
387     &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
388 
389 /* 0 means chip/fw default, non-zero number is value in microseconds */
390 static u_long t4_toe_keepalive_interval = 0;
391 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
392     &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
393 
394 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
395 static int t4_toe_keepalive_count = 0;
396 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
397     &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
398 
399 /* 0 means chip/fw default, non-zero number is value in microseconds */
400 static u_long t4_toe_rexmt_min = 0;
401 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
402     &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
403 
404 /* 0 means chip/fw default, non-zero number is value in microseconds */
405 static u_long t4_toe_rexmt_max = 0;
406 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
407     &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
408 
409 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
410 static int t4_toe_rexmt_count = 0;
411 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
412     &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
413 
414 /* -1 means chip/fw default, other values are raw backoff values to use */
415 static int t4_toe_rexmt_backoff[16] = {
416 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
417 };
418 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff,
419     CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
420     "cxgbe(4) TOE retransmit backoff values");
421 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
422     &t4_toe_rexmt_backoff[0], 0, "");
423 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
424     &t4_toe_rexmt_backoff[1], 0, "");
425 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
426     &t4_toe_rexmt_backoff[2], 0, "");
427 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
428     &t4_toe_rexmt_backoff[3], 0, "");
429 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
430     &t4_toe_rexmt_backoff[4], 0, "");
431 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
432     &t4_toe_rexmt_backoff[5], 0, "");
433 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
434     &t4_toe_rexmt_backoff[6], 0, "");
435 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
436     &t4_toe_rexmt_backoff[7], 0, "");
437 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
438     &t4_toe_rexmt_backoff[8], 0, "");
439 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
440     &t4_toe_rexmt_backoff[9], 0, "");
441 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
442     &t4_toe_rexmt_backoff[10], 0, "");
443 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
444     &t4_toe_rexmt_backoff[11], 0, "");
445 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
446     &t4_toe_rexmt_backoff[12], 0, "");
447 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
448     &t4_toe_rexmt_backoff[13], 0, "");
449 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
450     &t4_toe_rexmt_backoff[14], 0, "");
451 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
452     &t4_toe_rexmt_backoff[15], 0, "");
453 
454 int t4_ddp_rcvbuf_len = 256 * 1024;
455 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_len, CTLFLAG_RWTUN,
456     &t4_ddp_rcvbuf_len, 0, "length of each DDP RX buffer");
457 
458 unsigned int t4_ddp_rcvbuf_cache = 4;
459 SYSCTL_UINT(_hw_cxgbe_toe, OID_AUTO, ddp_rcvbuf_cache, CTLFLAG_RWTUN,
460     &t4_ddp_rcvbuf_cache, 0,
461     "maximum number of free DDP RX buffers to cache per connection");
462 #endif
463 
464 #ifdef DEV_NETMAP
465 #define NN_MAIN_VI	(1 << 0)	/* Native netmap on the main VI */
466 #define NN_EXTRA_VI	(1 << 1)	/* Native netmap on the extra VI(s) */
467 static int t4_native_netmap = NN_EXTRA_VI;
468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap,
469     0, "Native netmap support.  bit 0 = main VI, bit 1 = extra VIs");
470 
471 #define NNMTXQ 8
472 static int t4_nnmtxq = -NNMTXQ;
473 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0,
474     "Number of netmap TX queues");
475 
476 #define NNMRXQ 8
477 static int t4_nnmrxq = -NNMRXQ;
478 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0,
479     "Number of netmap RX queues");
480 
481 #define NNMTXQ_VI 2
482 static int t4_nnmtxq_vi = -NNMTXQ_VI;
483 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
484     "Number of netmap TX queues per VI");
485 
486 #define NNMRXQ_VI 2
487 static int t4_nnmrxq_vi = -NNMRXQ_VI;
488 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
489     "Number of netmap RX queues per VI");
490 #endif
491 
492 /*
493  * Holdoff parameters for ports.
494  */
495 #define TMR_IDX 1
496 int t4_tmr_idx = TMR_IDX;
497 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
498     0, "Holdoff timer index");
499 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx);	/* Old name */
500 
501 #define PKTC_IDX (-1)
502 int t4_pktc_idx = PKTC_IDX;
503 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
504     0, "Holdoff packet counter index");
505 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx);	/* Old name */
506 
507 /*
508  * Size (# of entries) of each tx and rx queue.
509  */
510 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
511 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
512     "Number of descriptors in each TX queue");
513 
514 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
515 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
516     "Number of descriptors in each RX queue");
517 
518 /*
519  * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
520  */
521 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
523     0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
524 
525 /*
526  * Configuration file.  All the _CF names here are special.
527  */
528 #define DEFAULT_CF	"default"
529 #define BUILTIN_CF	"built-in"
530 #define FLASH_CF	"flash"
531 #define UWIRE_CF	"uwire"
532 #define FPGA_CF		"fpga"
533 static char t4_cfg_file[32] = DEFAULT_CF;
534 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
535     sizeof(t4_cfg_file), "Firmware configuration file");
536 
537 /*
538  * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
539  * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
540  * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
541  *            mark or when signalled to do so, 0 to never emit PAUSE.
542  * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
543  *                 negotiated settings will override rx_pause/tx_pause.
544  *                 Otherwise rx_pause/tx_pause are applied forcibly.
545  */
546 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
547 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
548     &t4_pause_settings, 0,
549     "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
550 
551 /*
552  * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
553  * -1 to run with the firmware default.  Same as FEC_AUTO (bit 5)
554  *  0 to disable FEC.
555  */
556 static int t4_fec = -1;
557 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
558     "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
559 
560 static const char *
561 t4_fec_bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2\6auto\7module";
562 
563 /*
564  * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it
565  * issues to the firmware.  If the firmware doesn't support FORCE_FEC then the
566  * driver runs as if this is set to 0.
567  * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay.
568  *  0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the
569  *    transceiver. Multiple FEC bits may not be okay but will be passed on to
570  *    the firmware anyway (may result in l1cfg errors with old firmwares).
571  *  1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO
572  *    means set all FEC bits that are valid for the speed.
573  */
574 static int t4_force_fec = -1;
575 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0,
576     "Controls the use of FORCE_FEC bit in L1 configuration.");
577 
578 /*
579  * Link autonegotiation.
580  * -1 to run with the firmware default.
581  *  0 to disable.
582  *  1 to enable.
583  */
584 static int t4_autoneg = -1;
585 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
586     "Link autonegotiation");
587 
588 /*
589  * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
590  * encouraged respectively).  '-n' is the same as 'n' except the firmware
591  * version used in the checks is read from the firmware bundled with the driver.
592  */
593 static int t4_fw_install = 1;
594 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
595     "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
596 
597 /*
598  * ASIC features that will be used.  Disable the ones you don't want so that the
599  * chip resources aren't wasted on features that will not be used.
600  */
601 static int t4_nbmcaps_allowed = 0;
602 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
603     &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
604 
605 static int t4_linkcaps_allowed = 0;	/* No DCBX, PPP, etc. by default */
606 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
607     &t4_linkcaps_allowed, 0, "Default link capabilities");
608 
609 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
610     FW_CAPS_CONFIG_SWITCH_EGRESS;
611 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
612     &t4_switchcaps_allowed, 0, "Default switch capabilities");
613 
614 static int t4_nvmecaps_allowed = -1;
615 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nvmecaps_allowed, CTLFLAG_RDTUN,
616     &t4_nvmecaps_allowed, 0, "Default NVMe capabilities");
617 
618 #ifdef RATELIMIT
619 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
620 	FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
621 #else
622 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
623 	FW_CAPS_CONFIG_NIC_HASHFILTER;
624 #endif
625 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
626     &t4_niccaps_allowed, 0, "Default NIC capabilities");
627 
628 static int t4_toecaps_allowed = -1;
629 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
630     &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
631 
632 static int t4_rdmacaps_allowed = -1;
633 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
634     &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
635 
636 static int t4_cryptocaps_allowed = -1;
637 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
638     &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
639 
640 static int t4_iscsicaps_allowed = -1;
641 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
642     &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
643 
644 static int t4_fcoecaps_allowed = 0;
645 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
646     &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
647 
648 static int t5_write_combine = 0;
649 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
650     0, "Use WC instead of UC for BAR2");
651 
652 /* From t4_sysctls: doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"} */
653 static int t4_doorbells_allowed = 0xf;
654 SYSCTL_INT(_hw_cxgbe, OID_AUTO, doorbells_allowed, CTLFLAG_RDTUN,
655 	   &t4_doorbells_allowed, 0, "Limit tx queues to these doorbells");
656 
657 static int t4_num_vis = 1;
658 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
659     "Number of VIs per port");
660 
661 /*
662  * PCIe Relaxed Ordering.
663  * -1: driver should figure out a good value.
664  * 0: disable RO.
665  * 1: enable RO.
666  * 2: leave RO alone.
667  */
668 static int pcie_relaxed_ordering = -1;
669 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
670     &pcie_relaxed_ordering, 0,
671     "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
672 
673 static int t4_panic_on_fatal_err = 0;
674 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN,
675     &t4_panic_on_fatal_err, 0, "panic on fatal errors");
676 
677 static int t4_reset_on_fatal_err = 0;
678 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN,
679     &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors");
680 
681 static int t4_reset_method = 1;
682 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_method, CTLFLAG_RWTUN, &t4_reset_method,
683     0, "reset method: 0 = PL_RST, 1 = PCIe secondary bus reset, 2 = PCIe link bounce");
684 
685 static int t4_clock_gate_on_suspend = 0;
686 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN,
687     &t4_clock_gate_on_suspend, 0, "gate the clock on suspend");
688 
689 static int t4_tx_vm_wr = 0;
690 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0,
691     "Use VM work requests to transmit packets.");
692 
693 /*
694  * Set to non-zero to enable the attack filter.  A packet that matches any of
695  * these conditions will get dropped on ingress:
696  * 1) IP && source address == destination address.
697  * 2) TCP/IP && source address is not a unicast address.
698  * 3) TCP/IP && destination address is not a unicast address.
699  * 4) IP && source address is loopback (127.x.y.z).
700  * 5) IP && destination address is loopback (127.x.y.z).
701  * 6) IPv6 && source address == destination address.
702  * 7) IPv6 && source address is not a unicast address.
703  * 8) IPv6 && source address is loopback (::1/128).
704  * 9) IPv6 && destination address is loopback (::1/128).
705  * 10) IPv6 && source address is unspecified (::/128).
706  * 11) IPv6 && destination address is unspecified (::/128).
707  * 12) TCP/IPv6 && source address is multicast (ff00::/8).
708  * 13) TCP/IPv6 && destination address is multicast (ff00::/8).
709  */
710 static int t4_attack_filter = 0;
711 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN,
712     &t4_attack_filter, 0, "Drop suspicious traffic");
713 
714 static int t4_drop_ip_fragments = 0;
715 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN,
716     &t4_drop_ip_fragments, 0, "Drop IP fragments");
717 
718 static int t4_drop_pkts_with_l2_errors = 1;
719 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN,
720     &t4_drop_pkts_with_l2_errors, 0,
721     "Drop all frames with Layer 2 length or checksum errors");
722 
723 static int t4_drop_pkts_with_l3_errors = 0;
724 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN,
725     &t4_drop_pkts_with_l3_errors, 0,
726     "Drop all frames with IP version, length, or checksum errors");
727 
728 static int t4_drop_pkts_with_l4_errors = 0;
729 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN,
730     &t4_drop_pkts_with_l4_errors, 0,
731     "Drop all frames with Layer 4 length, checksum, or other errors");
732 
733 #ifdef TCP_OFFLOAD
734 /*
735  * TOE tunables.
736  */
737 static int t4_cop_managed_offloading = 0;
738 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
739     &t4_cop_managed_offloading, 0,
740     "COP (Connection Offload Policy) controls all TOE offload");
741 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading);
742 #endif
743 
744 #ifdef KERN_TLS
745 /*
746  * This enables KERN_TLS for all adapters if set.
747  */
748 static int t4_kern_tls = 0;
749 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0,
750     "Enable KERN_TLS mode for T6 adapters");
751 
752 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
753     "cxgbe(4) KERN_TLS parameters");
754 
755 static int t4_tls_inline_keys = 0;
756 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN,
757     &t4_tls_inline_keys, 0,
758     "Always pass TLS keys in work requests (1) or attempt to store TLS keys "
759     "in card memory.");
760 
761 static int t4_tls_combo_wrs = 0;
762 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs,
763     0, "Attempt to combine TCB field updates with TLS record work requests.");
764 
765 static int t4_tls_short_records = 1;
766 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, short_records, CTLFLAG_RDTUN,
767     &t4_tls_short_records, 0, "Use cipher-only mode for short records.");
768 
769 static int t4_tls_partial_ghash = 1;
770 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, partial_ghash, CTLFLAG_RDTUN,
771     &t4_tls_partial_ghash, 0, "Use partial GHASH for AES-GCM records.");
772 #endif
773 
774 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
775 static int vi_mac_funcs[] = {
776 	FW_VI_FUNC_ETH,
777 	FW_VI_FUNC_OFLD,
778 	FW_VI_FUNC_IWARP,
779 	FW_VI_FUNC_OPENISCSI,
780 	FW_VI_FUNC_OPENFCOE,
781 	FW_VI_FUNC_FOISCSI,
782 	FW_VI_FUNC_FOFCOE,
783 };
784 
785 struct intrs_and_queues {
786 	uint16_t intr_type;	/* INTx, MSI, or MSI-X */
787 	uint16_t num_vis;	/* number of VIs for each port */
788 	uint16_t nirq;		/* Total # of vectors */
789 	uint16_t ntxq;		/* # of NIC txq's for each port */
790 	uint16_t nrxq;		/* # of NIC rxq's for each port */
791 	uint16_t nofldtxq;	/* # of TOE/ETHOFLD txq's for each port */
792 	uint16_t nofldrxq;	/* # of TOE rxq's for each port */
793 	uint16_t nnmtxq;	/* # of netmap txq's */
794 	uint16_t nnmrxq;	/* # of netmap rxq's */
795 
796 	/* The vcxgbe/vcxl interfaces use these and not the ones above. */
797 	uint16_t ntxq_vi;	/* # of NIC txq's */
798 	uint16_t nrxq_vi;	/* # of NIC rxq's */
799 	uint16_t nofldtxq_vi;	/* # of TOE txq's */
800 	uint16_t nofldrxq_vi;	/* # of TOE rxq's */
801 	uint16_t nnmtxq_vi;	/* # of netmap txq's */
802 	uint16_t nnmrxq_vi;	/* # of netmap rxq's */
803 };
804 
805 static void setup_memwin(struct adapter *);
806 static void position_memwin(struct adapter *, int, uint32_t);
807 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
808 static int fwmtype_to_hwmtype(int);
809 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
810     uint32_t *);
811 static int fixup_devlog_params(struct adapter *);
812 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
813 static int contact_firmware(struct adapter *);
814 static int partition_resources(struct adapter *);
815 static int get_params__pre_init(struct adapter *);
816 static int set_params__pre_init(struct adapter *);
817 static int get_params__post_init(struct adapter *);
818 static int set_params__post_init(struct adapter *);
819 static void t4_set_desc(struct adapter *);
820 static bool fixed_ifmedia(struct port_info *);
821 static void build_medialist(struct port_info *);
822 static void init_link_config(struct port_info *);
823 static int fixup_link_config(struct port_info *);
824 static int apply_link_config(struct port_info *);
825 static int cxgbe_init_synchronized(struct vi_info *);
826 static int cxgbe_uninit_synchronized(struct vi_info *);
827 static int adapter_full_init(struct adapter *);
828 static void adapter_full_uninit(struct adapter *);
829 static int vi_full_init(struct vi_info *);
830 static void vi_full_uninit(struct vi_info *);
831 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *);
832 static void quiesce_txq(struct sge_txq *);
833 static void quiesce_wrq(struct sge_wrq *);
834 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
835 static void quiesce_vi(struct vi_info *);
836 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
837     driver_intr_t *, void *, char *);
838 static int t4_free_irq(struct adapter *, struct irq *);
839 static void t4_init_atid_table(struct adapter *);
840 static void t4_free_atid_table(struct adapter *);
841 static void stop_atid_allocator(struct adapter *);
842 static void restart_atid_allocator(struct adapter *);
843 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
844 static void vi_refresh_stats(struct vi_info *);
845 static void cxgbe_refresh_stats(struct vi_info *);
846 static void cxgbe_tick(void *);
847 static void vi_tick(void *);
848 static void cxgbe_sysctls(struct port_info *);
849 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
850 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
851 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
852 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
853 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
854 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS);
855 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
856 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
857 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
858 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
859 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
860 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS);
861 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS);
862 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS);
863 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
864 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS);
865 static int sysctl_handle_t4_portstat64(SYSCTL_HANDLER_ARGS);
866 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
867 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
868 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
869 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS);
870 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
871 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
872 static int sysctl_cim_ibq(SYSCTL_HANDLER_ARGS);
873 static int sysctl_cim_obq(SYSCTL_HANDLER_ARGS);
874 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
875 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
876 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
877 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
878 static int sysctl_cim_qcfg_t7(SYSCTL_HANDLER_ARGS);
879 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
880 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
881 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS);
882 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
883 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
884 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
885 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
886 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
887 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
888 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
889 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
890 static int sysctl_mps_tcam_t7(SYSCTL_HANDLER_ARGS);
891 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
892 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
893 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
894 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
895 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
896 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
897 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS);
898 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
899 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
900 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
901 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
902 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
903 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
904 static int sysctl_reset(SYSCTL_HANDLER_ARGS);
905 #ifdef TCP_OFFLOAD
906 static int sysctl_tls(SYSCTL_HANDLER_ARGS);
907 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
908 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
909 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
910 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
911 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
912 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
913 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
914 #endif
915 static int get_sge_context(struct adapter *, int, uint32_t, int, uint32_t *);
916 static int load_fw(struct adapter *, struct t4_data *);
917 static int load_cfg(struct adapter *, struct t4_data *);
918 static int load_boot(struct adapter *, struct t4_bootrom *);
919 static int load_bootcfg(struct adapter *, struct t4_data *);
920 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
921 static void free_offload_policy(struct t4_offload_policy *);
922 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
923 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
924 static int read_i2c(struct adapter *, struct t4_i2c_data *);
925 static int clear_stats(struct adapter *, u_int);
926 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *);
927 static int release_clip_addr(struct adapter *, struct t4_clip_addr *);
928 static inline int stop_adapter(struct adapter *);
929 static inline void set_adapter_hwstatus(struct adapter *, const bool);
930 static int stop_lld(struct adapter *);
931 static inline int restart_adapter(struct adapter *);
932 static int restart_lld(struct adapter *);
933 #ifdef TCP_OFFLOAD
934 static int deactivate_all_uld(struct adapter *);
935 static void stop_all_uld(struct adapter *);
936 static void restart_all_uld(struct adapter *);
937 #endif
938 #ifdef KERN_TLS
939 static int ktls_capability(struct adapter *, bool);
940 #endif
941 static int mod_event(module_t, int, void *);
942 static int notify_siblings(device_t, int);
943 static uint64_t vi_get_counter(if_t, ift_counter);
944 static uint64_t cxgbe_get_counter(if_t, ift_counter);
945 static void enable_vxlan_rx(struct adapter *);
946 static void reset_adapter_task(void *, int);
947 static void fatal_error_task(void *, int);
948 static void dump_devlog(struct adapter *);
949 static void dump_cim_regs(struct adapter *);
950 static void dump_cimla(struct adapter *);
951 
952 struct {
953 	uint16_t device;
954 	char *desc;
955 } t4_pciids[] = {
956 	{0xa000, "Chelsio Terminator 4 FPGA"},
957 	{0x4400, "Chelsio T440-dbg"},
958 	{0x4401, "Chelsio T420-CR"},
959 	{0x4402, "Chelsio T422-CR"},
960 	{0x4403, "Chelsio T440-CR"},
961 	{0x4404, "Chelsio T420-BCH"},
962 	{0x4405, "Chelsio T440-BCH"},
963 	{0x4406, "Chelsio T440-CH"},
964 	{0x4407, "Chelsio T420-SO"},
965 	{0x4408, "Chelsio T420-CX"},
966 	{0x4409, "Chelsio T420-BT"},
967 	{0x440a, "Chelsio T404-BT"},
968 	{0x440e, "Chelsio T440-LP-CR"},
969 }, t5_pciids[] = {
970 	{0xb000, "Chelsio Terminator 5 FPGA"},
971 	{0x5400, "Chelsio T580-dbg"},
972 	{0x5401,  "Chelsio T520-CR"},		/* 2 x 10G */
973 	{0x5402,  "Chelsio T522-CR"},		/* 2 x 10G, 2 X 1G */
974 	{0x5403,  "Chelsio T540-CR"},		/* 4 x 10G */
975 	{0x5407,  "Chelsio T520-SO"},		/* 2 x 10G, nomem */
976 	{0x5409,  "Chelsio T520-BT"},		/* 2 x 10GBaseT */
977 	{0x540a,  "Chelsio T504-BT"},		/* 4 x 1G */
978 	{0x540d,  "Chelsio T580-CR"},		/* 2 x 40G */
979 	{0x540e,  "Chelsio T540-LP-CR"},	/* 4 x 10G */
980 	{0x5410,  "Chelsio T580-LP-CR"},	/* 2 x 40G */
981 	{0x5411,  "Chelsio T520-LL-CR"},	/* 2 x 10G */
982 	{0x5412,  "Chelsio T560-CR"},		/* 1 x 40G, 2 x 10G */
983 	{0x5414,  "Chelsio T580-LP-SO-CR"},	/* 2 x 40G, nomem */
984 	{0x5415,  "Chelsio T502-BT"},		/* 2 x 1G */
985 	{0x5418,  "Chelsio T540-BT"},		/* 4 x 10GBaseT */
986 	{0x5419,  "Chelsio T540-LP-BT"},	/* 4 x 10GBaseT */
987 	{0x541a,  "Chelsio T540-SO-BT"},	/* 4 x 10GBaseT, nomem */
988 	{0x541b,  "Chelsio T540-SO-CR"},	/* 4 x 10G, nomem */
989 
990 	/* Custom */
991 	{0x5483, "Custom T540-CR"},
992 	{0x5484, "Custom T540-BT"},
993 }, t6_pciids[] = {
994 	{0xc006, "Chelsio Terminator 6 FPGA"},	/* T6 PE10K6 FPGA (PF0) */
995 	{0x6400, "Chelsio T6-DBG-25"},		/* 2 x 10/25G, debug */
996 	{0x6401, "Chelsio T6225-CR"},		/* 2 x 10/25G */
997 	{0x6402, "Chelsio T6225-SO-CR"},	/* 2 x 10/25G, nomem */
998 	{0x6403, "Chelsio T6425-CR"},		/* 4 x 10/25G */
999 	{0x6404, "Chelsio T6425-SO-CR"},	/* 4 x 10/25G, nomem */
1000 	{0x6405, "Chelsio T6225-SO-OCP3"},	/* 2 x 10/25G, nomem */
1001 	{0x6406, "Chelsio T6225-OCP3"},		/* 2 x 10/25G */
1002 	{0x6407, "Chelsio T62100-LP-CR"},	/* 2 x 40/50/100G */
1003 	{0x6408, "Chelsio T62100-SO-CR"},	/* 2 x 40/50/100G, nomem */
1004 	{0x6409, "Chelsio T6210-BT"},		/* 2 x 10GBASE-T */
1005 	{0x640d, "Chelsio T62100-CR"},		/* 2 x 40/50/100G */
1006 	{0x6410, "Chelsio T6-DBG-100"},		/* 2 x 40/50/100G, debug */
1007 	{0x6411, "Chelsio T6225-LL-CR"},	/* 2 x 10/25G */
1008 	{0x6414, "Chelsio T62100-SO-OCP3"},	/* 2 x 40/50/100G, nomem */
1009 	{0x6415, "Chelsio T6201-BT"},		/* 2 x 1000BASE-T */
1010 
1011 	/* Custom */
1012 	{0x6480, "Custom T6225-CR"},
1013 	{0x6481, "Custom T62100-CR"},
1014 	{0x6482, "Custom T6225-CR"},
1015 	{0x6483, "Custom T62100-CR"},
1016 	{0x6484, "Custom T64100-CR"},
1017 	{0x6485, "Custom T6240-SO"},
1018 	{0x6486, "Custom T6225-SO-CR"},
1019 	{0x6487, "Custom T6225-CR"},
1020 }, t7_pciids[] = {
1021 	{0xd000, "Chelsio Terminator 7 FPGA"},	/* T7 PE12K FPGA */
1022 	{0x7400, "Chelsio T72200-DBG"},		/* 2 x 200G, debug */
1023 	{0x7401, "Chelsio T7250"},		/* 2 x 10/25/50G, 1 mem */
1024 	{0x7402, "Chelsio S7250"},		/* 2 x 10/25/50G, nomem */
1025 	{0x7403, "Chelsio T7450"},		/* 4 x 10/25/50G, 1 mem */
1026 	{0x7404, "Chelsio S7450"},		/* 4 x 10/25/50G, nomem */
1027 	{0x7405, "Chelsio T72200"},		/* 2 x 40/100/200G, 1 mem */
1028 	{0x7406, "Chelsio S72200"},		/* 2 x 40/100/200G, nomem */
1029 	{0x7407, "Chelsio T72200-FH"},		/* 2 x 40/100/200G, 2 mem */
1030 	{0x7408, "Chelsio S71400"},		/* 1 x 400G, nomem */
1031 	{0x7409, "Chelsio S7210-BT"},		/* 2 x 10GBASE-T, nomem */
1032 	{0x740a, "Chelsio T7450-RC"},		/* 4 x 10/25/50G, 1 mem, RC */
1033 	{0x740b, "Chelsio T72200-RC"},		/* 2 x 40/100/200G, 1 mem, RC */
1034 	{0x740c, "Chelsio T72200-FH-RC"},	/* 2 x 40/100/200G, 2 mem, RC */
1035 	{0x740d, "Chelsio S72200-OCP3"},	/* 2 x 40/100/200G OCP3 */
1036 	{0x740e, "Chelsio S7450-OCP3"},		/* 4 x 1/20/25/50G OCP3 */
1037 	{0x740f, "Chelsio S7410-BT-OCP3"},	/* 4 x 10GBASE-T OCP3 */
1038 	{0x7410, "Chelsio S7210-BT-A"},		/* 2 x 10GBASE-T */
1039 	{0x7411, "Chelsio T7_MAYRA_7"},		/* Motherboard */
1040 
1041 	/* Custom */
1042 	{0x7480, "Custom T7"},
1043 };
1044 
1045 #ifdef TCP_OFFLOAD
1046 /*
1047  * service_iq_fl() has an iq and needs the fl.  Offset of fl from the iq should
1048  * be exactly the same for both rxq and ofld_rxq.
1049  */
1050 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
1051 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
1052 #endif
1053 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
1054 
1055 static int
1056 t4_probe(device_t dev)
1057 {
1058 	int i;
1059 	uint16_t v = pci_get_vendor(dev);
1060 	uint16_t d = pci_get_device(dev);
1061 	uint8_t f = pci_get_function(dev);
1062 
1063 	if (v != PCI_VENDOR_ID_CHELSIO)
1064 		return (ENXIO);
1065 
1066 	/* Attach only to PF0 of the FPGA */
1067 	if (d == 0xa000 && f != 0)
1068 		return (ENXIO);
1069 
1070 	for (i = 0; i < nitems(t4_pciids); i++) {
1071 		if (d == t4_pciids[i].device) {
1072 			device_set_desc(dev, t4_pciids[i].desc);
1073 			return (BUS_PROBE_DEFAULT);
1074 		}
1075 	}
1076 
1077 	return (ENXIO);
1078 }
1079 
1080 static int
1081 t5_probe(device_t dev)
1082 {
1083 	int i;
1084 	uint16_t v = pci_get_vendor(dev);
1085 	uint16_t d = pci_get_device(dev);
1086 	uint8_t f = pci_get_function(dev);
1087 
1088 	if (v != PCI_VENDOR_ID_CHELSIO)
1089 		return (ENXIO);
1090 
1091 	/* Attach only to PF0 of the FPGA */
1092 	if (d == 0xb000 && f != 0)
1093 		return (ENXIO);
1094 
1095 	for (i = 0; i < nitems(t5_pciids); i++) {
1096 		if (d == t5_pciids[i].device) {
1097 			device_set_desc(dev, t5_pciids[i].desc);
1098 			return (BUS_PROBE_DEFAULT);
1099 		}
1100 	}
1101 
1102 	return (ENXIO);
1103 }
1104 
1105 static int
1106 t6_probe(device_t dev)
1107 {
1108 	int i;
1109 	uint16_t v = pci_get_vendor(dev);
1110 	uint16_t d = pci_get_device(dev);
1111 
1112 	if (v != PCI_VENDOR_ID_CHELSIO)
1113 		return (ENXIO);
1114 
1115 	for (i = 0; i < nitems(t6_pciids); i++) {
1116 		if (d == t6_pciids[i].device) {
1117 			device_set_desc(dev, t6_pciids[i].desc);
1118 			return (BUS_PROBE_DEFAULT);
1119 		}
1120 	}
1121 
1122 	return (ENXIO);
1123 }
1124 
1125 static int
1126 ch_probe(device_t dev)
1127 {
1128 	int i;
1129 	uint16_t v = pci_get_vendor(dev);
1130 	uint16_t d = pci_get_device(dev);
1131 	uint8_t f = pci_get_function(dev);
1132 
1133 	if (v != PCI_VENDOR_ID_CHELSIO)
1134 		return (ENXIO);
1135 
1136 	/* Attach only to PF0 of the FPGA */
1137 	if (d == 0xd000 && f != 0)
1138 		return (ENXIO);
1139 
1140 	for (i = 0; i < nitems(t7_pciids); i++) {
1141 		if (d == t7_pciids[i].device) {
1142 			device_set_desc(dev, t7_pciids[i].desc);
1143 			return (BUS_PROBE_DEFAULT);
1144 		}
1145 	}
1146 
1147 	return (ENXIO);
1148 }
1149 
1150 static void
1151 t5_attribute_workaround(device_t dev)
1152 {
1153 	device_t root_port;
1154 	uint32_t v;
1155 
1156 	/*
1157 	 * The T5 chips do not properly echo the No Snoop and Relaxed
1158 	 * Ordering attributes when replying to a TLP from a Root
1159 	 * Port.  As a workaround, find the parent Root Port and
1160 	 * disable No Snoop and Relaxed Ordering.  Note that this
1161 	 * affects all devices under this root port.
1162 	 */
1163 	root_port = pci_find_pcie_root_port(dev);
1164 	if (root_port == NULL) {
1165 		device_printf(dev, "Unable to find parent root port\n");
1166 		return;
1167 	}
1168 
1169 	v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
1170 	    PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
1171 	if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
1172 	    0)
1173 		device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
1174 		    device_get_nameunit(root_port));
1175 }
1176 
1177 static const struct devnames devnames[] = {
1178 	{
1179 		.nexus_name = "t4nex",
1180 		.ifnet_name = "cxgbe",
1181 		.vi_ifnet_name = "vcxgbe",
1182 		.pf03_drv_name = "t4iov",
1183 		.vf_nexus_name = "t4vf",
1184 		.vf_ifnet_name = "cxgbev"
1185 	}, {
1186 		.nexus_name = "t5nex",
1187 		.ifnet_name = "cxl",
1188 		.vi_ifnet_name = "vcxl",
1189 		.pf03_drv_name = "t5iov",
1190 		.vf_nexus_name = "t5vf",
1191 		.vf_ifnet_name = "cxlv"
1192 	}, {
1193 		.nexus_name = "t6nex",
1194 		.ifnet_name = "cc",
1195 		.vi_ifnet_name = "vcc",
1196 		.pf03_drv_name = "t6iov",
1197 		.vf_nexus_name = "t6vf",
1198 		.vf_ifnet_name = "ccv"
1199 	}, {
1200 		.nexus_name = "chnex",
1201 		.ifnet_name = "che",
1202 		.vi_ifnet_name = "vche",
1203 		.pf03_drv_name = "chiov",
1204 		.vf_nexus_name = "chvf",
1205 		.vf_ifnet_name = "chev"
1206 	}
1207 };
1208 
1209 void
1210 t4_init_devnames(struct adapter *sc)
1211 {
1212 	int id;
1213 
1214 	id = chip_id(sc);
1215 	if (id < CHELSIO_T4) {
1216 		device_printf(sc->dev, "chip id %d is not supported.\n", id);
1217 		sc->names = NULL;
1218 	} else if (id - CHELSIO_T4 < nitems(devnames))
1219 		sc->names = &devnames[id - CHELSIO_T4];
1220 	else
1221 		sc->names = &devnames[nitems(devnames) - 1];
1222 }
1223 
1224 static int
1225 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
1226 {
1227 	const char *parent, *name;
1228 	long value;
1229 	int line, unit;
1230 
1231 	line = 0;
1232 	parent = device_get_nameunit(sc->dev);
1233 	name = sc->names->ifnet_name;
1234 	while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
1235 		if (resource_long_value(name, unit, "port", &value) == 0 &&
1236 		    value == pi->port_id)
1237 			return (unit);
1238 	}
1239 	return (-1);
1240 }
1241 
1242 static void
1243 t4_calibration(void *arg)
1244 {
1245 	struct adapter *sc;
1246 	struct clock_sync *cur, *nex;
1247 	uint64_t hw;
1248 	sbintime_t sbt;
1249 	int next_up;
1250 
1251 	sc = (struct adapter *)arg;
1252 
1253 	KASSERT(hw_all_ok(sc), ("!hw_all_ok at t4_calibration"));
1254 	hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO);
1255 	sbt = sbinuptime();
1256 
1257 	cur = &sc->cal_info[sc->cal_current];
1258 	next_up = (sc->cal_current + 1) % CNT_CAL_INFO;
1259 	nex = &sc->cal_info[next_up];
1260 	if (__predict_false(sc->cal_count == 0)) {
1261 		/* First time in, just get the values in */
1262 		cur->hw_cur = hw;
1263 		cur->sbt_cur = sbt;
1264 		sc->cal_count++;
1265 		goto done;
1266 	}
1267 
1268 	if (cur->hw_cur == hw) {
1269 		/* The clock is not advancing? */
1270 		sc->cal_count = 0;
1271 		atomic_store_rel_int(&cur->gen, 0);
1272 		goto done;
1273 	}
1274 
1275 	seqc_write_begin(&nex->gen);
1276 	nex->hw_prev = cur->hw_cur;
1277 	nex->sbt_prev = cur->sbt_cur;
1278 	nex->hw_cur = hw;
1279 	nex->sbt_cur = sbt;
1280 	seqc_write_end(&nex->gen);
1281 	sc->cal_current = next_up;
1282 done:
1283 	callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration,
1284 	    sc, C_DIRECT_EXEC);
1285 }
1286 
1287 static void
1288 t4_calibration_start(struct adapter *sc)
1289 {
1290 	/*
1291 	 * Here if we have not done a calibration
1292 	 * then do so otherwise start the appropriate
1293 	 * timer.
1294 	 */
1295 	int i;
1296 
1297 	for (i = 0; i < CNT_CAL_INFO; i++) {
1298 		sc->cal_info[i].gen = 0;
1299 	}
1300 	sc->cal_current = 0;
1301 	sc->cal_count = 0;
1302 	sc->cal_gen = 0;
1303 	t4_calibration(sc);
1304 }
1305 
1306 static int
1307 t4_attach(device_t dev)
1308 {
1309 	struct adapter *sc;
1310 	int rc = 0, i, j, rqidx, tqidx, nports;
1311 	struct make_dev_args mda;
1312 	struct intrs_and_queues iaq;
1313 	struct sge *s;
1314 	uint32_t *buf;
1315 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1316 	int ofld_tqidx;
1317 #endif
1318 #ifdef TCP_OFFLOAD
1319 	int ofld_rqidx;
1320 #endif
1321 #ifdef DEV_NETMAP
1322 	int nm_rqidx, nm_tqidx;
1323 #endif
1324 	int num_vis;
1325 
1326 	sc = device_get_softc(dev);
1327 	sc->dev = dev;
1328 	sysctl_ctx_init(&sc->ctx);
1329 	TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
1330 	if (TUNABLE_INT_FETCH("hw.cxgbe.iflags", &sc->intr_flags) == 0)
1331 		sc->intr_flags = IHF_INTR_CLEAR_ON_INIT | IHF_CLR_ALL_UNIGNORED;
1332 
1333 	if ((pci_get_device(dev) & 0xff00) == 0x5400)
1334 		t5_attribute_workaround(dev);
1335 	pci_enable_busmaster(dev);
1336 	if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
1337 		uint32_t v;
1338 
1339 		pci_set_max_read_req(dev, 4096);
1340 		v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
1341 		sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
1342 		if (pcie_relaxed_ordering == 0 &&
1343 		    (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
1344 			v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
1345 			pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1346 		} else if (pcie_relaxed_ordering == 1 &&
1347 		    (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
1348 			v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
1349 			pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1350 		}
1351 	}
1352 
1353 	sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
1354 	sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
1355 	sc->traceq = -1;
1356 	mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
1357 	snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
1358 	    device_get_nameunit(dev));
1359 
1360 	snprintf(sc->lockname, sizeof(sc->lockname), "%s",
1361 	    device_get_nameunit(dev));
1362 	mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
1363 	t4_add_adapter(sc);
1364 
1365 	mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
1366 	TAILQ_INIT(&sc->sfl);
1367 	callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
1368 
1369 	mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1370 
1371 	sc->policy = NULL;
1372 	rw_init(&sc->policy_lock, "connection offload policy");
1373 
1374 	callout_init(&sc->ktls_tick, 1);
1375 
1376 	callout_init(&sc->cal_callout, 1);
1377 
1378 	refcount_init(&sc->vxlan_refcount, 0);
1379 
1380 	TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc);
1381 	TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc);
1382 
1383 	sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1384 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq",
1385 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues");
1386 	sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1387 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq",
1388 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue");
1389 
1390 	rc = t4_map_bars_0_and_4(sc);
1391 	if (rc != 0)
1392 		goto done; /* error message displayed already */
1393 
1394 	memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1395 	memset(sc->port_map, 0xff, sizeof(sc->port_map));
1396 
1397 	/* Prepare the adapter for operation. */
1398 	buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1399 	rc = -t4_prep_adapter(sc, buf);
1400 	free(buf, M_CXGBE);
1401 	if (rc != 0) {
1402 		device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1403 		goto done;
1404 	}
1405 
1406 	/*
1407 	 * This is the real PF# to which we're attaching.  Works from within PCI
1408 	 * passthrough environments too, where pci_get_function() could return a
1409 	 * different PF# depending on the passthrough configuration.  We need to
1410 	 * use the real PF# in all our communication with the firmware.
1411 	 */
1412 	j = t4_read_reg(sc, A_PL_WHOAMI);
1413 	sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1414 	sc->mbox = sc->pf;
1415 
1416 	t4_init_devnames(sc);
1417 	if (sc->names == NULL) {
1418 		rc = ENOTSUP;
1419 		goto done; /* error message displayed already */
1420 	}
1421 
1422 	/*
1423 	 * Do this really early, with the memory windows set up even before the
1424 	 * character device.  The userland tool's register i/o and mem read
1425 	 * will work even in "recovery mode".
1426 	 */
1427 	setup_memwin(sc);
1428 	if (t4_init_devlog_ncores_params(sc, 0) == 0)
1429 		fixup_devlog_params(sc);
1430 	make_dev_args_init(&mda);
1431 	mda.mda_devsw = &t4_cdevsw;
1432 	mda.mda_uid = UID_ROOT;
1433 	mda.mda_gid = GID_WHEEL;
1434 	mda.mda_mode = 0600;
1435 	mda.mda_si_drv1 = sc;
1436 	rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1437 	if (rc != 0)
1438 		device_printf(dev, "failed to create nexus char device: %d.\n",
1439 		    rc);
1440 
1441 	/* Go no further if recovery mode has been requested. */
1442 	if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1443 		device_printf(dev, "recovery mode.\n");
1444 		goto done;
1445 	}
1446 
1447 #if defined(__i386__)
1448 	if ((cpu_feature & CPUID_CX8) == 0) {
1449 		device_printf(dev, "64 bit atomics not available.\n");
1450 		rc = ENOTSUP;
1451 		goto done;
1452 	}
1453 #endif
1454 
1455 	/* Contact the firmware and try to become the master driver. */
1456 	rc = contact_firmware(sc);
1457 	if (rc != 0)
1458 		goto done; /* error message displayed already */
1459 	MPASS(sc->flags & FW_OK);
1460 
1461 	rc = get_params__pre_init(sc);
1462 	if (rc != 0)
1463 		goto done; /* error message displayed already */
1464 
1465 	if (sc->flags & MASTER_PF) {
1466 		rc = partition_resources(sc);
1467 		if (rc != 0)
1468 			goto done; /* error message displayed already */
1469 	}
1470 
1471 	rc = get_params__post_init(sc);
1472 	if (rc != 0)
1473 		goto done; /* error message displayed already */
1474 
1475 	rc = set_params__post_init(sc);
1476 	if (rc != 0)
1477 		goto done; /* error message displayed already */
1478 
1479 	rc = t4_map_bar_2(sc);
1480 	if (rc != 0)
1481 		goto done; /* error message displayed already */
1482 
1483 	rc = t4_adj_doorbells(sc);
1484 	if (rc != 0)
1485 		goto done; /* error message displayed already */
1486 
1487 	rc = t4_create_dma_tag(sc);
1488 	if (rc != 0)
1489 		goto done; /* error message displayed already */
1490 
1491 	/*
1492 	 * First pass over all the ports - allocate VIs and initialize some
1493 	 * basic parameters like mac address, port type, etc.
1494 	 */
1495 	for_each_port(sc, i) {
1496 		struct port_info *pi;
1497 
1498 		pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1499 		sc->port[i] = pi;
1500 
1501 		/* These must be set before t4_port_init */
1502 		pi->adapter = sc;
1503 		pi->port_id = i;
1504 		/*
1505 		 * XXX: vi[0] is special so we can't delay this allocation until
1506 		 * pi->nvi's final value is known.
1507 		 */
1508 		pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1509 		    M_ZERO | M_WAITOK);
1510 
1511 		/*
1512 		 * Allocate the "main" VI and initialize parameters
1513 		 * like mac addr.
1514 		 */
1515 		rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1516 		if (rc != 0) {
1517 			device_printf(dev, "unable to initialize port %d: %d\n",
1518 			    i, rc);
1519 			free(pi->vi, M_CXGBE);
1520 			free(pi, M_CXGBE);
1521 			sc->port[i] = NULL;
1522 			goto done;
1523 		}
1524 
1525 		if (is_bt(pi->port_type))
1526 			setbit(&sc->bt_map, pi->hw_port);
1527 		else
1528 			MPASS(!isset(&sc->bt_map, pi->hw_port));
1529 
1530 		snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1531 		    device_get_nameunit(dev), i);
1532 		mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1533 		for (j = 0; j < sc->params.tp.lb_nchan; j++)
1534 			sc->chan_map[pi->tx_chan + j] = i;
1535 		sc->port_map[pi->hw_port] = i;
1536 
1537 		/*
1538 		 * The MPS counter for FCS errors doesn't work correctly on the
1539 		 * T6 so we use the MAC counter here.  Which MAC is in use
1540 		 * depends on the link settings which will be known when the
1541 		 * link comes up.
1542 		 */
1543 		if (is_t6(sc))
1544 			pi->fcs_reg = -1;
1545 		else
1546 			pi->fcs_reg = A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L;
1547 		pi->fcs_base = 0;
1548 
1549 		/* All VIs on this port share this media. */
1550 		ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1551 		    cxgbe_media_status);
1552 
1553 		PORT_LOCK(pi);
1554 		init_link_config(pi);
1555 		fixup_link_config(pi);
1556 		build_medialist(pi);
1557 		if (fixed_ifmedia(pi))
1558 			pi->flags |= FIXED_IFMEDIA;
1559 		PORT_UNLOCK(pi);
1560 
1561 		pi->dev = device_add_child(dev, sc->names->ifnet_name,
1562 		    t4_ifnet_unit(sc, pi));
1563 		if (pi->dev == NULL) {
1564 			device_printf(dev,
1565 			    "failed to add device for port %d.\n", i);
1566 			rc = ENXIO;
1567 			goto done;
1568 		}
1569 		pi->vi[0].dev = pi->dev;
1570 		device_set_softc(pi->dev, pi);
1571 	}
1572 
1573 	/*
1574 	 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1575 	 */
1576 	nports = sc->params.nports;
1577 	rc = cfg_itype_and_nqueues(sc, &iaq);
1578 	if (rc != 0)
1579 		goto done; /* error message displayed already */
1580 
1581 	num_vis = iaq.num_vis;
1582 	sc->intr_type = iaq.intr_type;
1583 	sc->intr_count = iaq.nirq;
1584 
1585 	s = &sc->sge;
1586 	s->nctrlq = max(sc->params.nports, sc->params.ncores);
1587 	s->nrxq = nports * iaq.nrxq;
1588 	s->ntxq = nports * iaq.ntxq;
1589 	if (num_vis > 1) {
1590 		s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1591 		s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1592 	}
1593 	s->neq = s->ntxq + s->nrxq;	/* the free list in an rxq is an eq */
1594 	s->neq += nports;		/* ctrl queues: 1 per port */
1595 	s->niq = s->nrxq + 1;		/* 1 extra for firmware event queue */
1596 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1597 	if (is_offload(sc) || is_ethoffload(sc)) {
1598 		s->nofldtxq = nports * iaq.nofldtxq;
1599 		if (num_vis > 1)
1600 			s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1601 		s->neq += s->nofldtxq;
1602 
1603 		s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq),
1604 		    M_CXGBE, M_ZERO | M_WAITOK);
1605 	}
1606 #endif
1607 #ifdef TCP_OFFLOAD
1608 	if (is_offload(sc)) {
1609 		s->nofldrxq = nports * iaq.nofldrxq;
1610 		if (num_vis > 1)
1611 			s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1612 		s->neq += s->nofldrxq;	/* free list */
1613 		s->niq += s->nofldrxq;
1614 
1615 		s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1616 		    M_CXGBE, M_ZERO | M_WAITOK);
1617 	}
1618 #endif
1619 #ifdef DEV_NETMAP
1620 	s->nnmrxq = 0;
1621 	s->nnmtxq = 0;
1622 	if (t4_native_netmap & NN_MAIN_VI) {
1623 		s->nnmrxq += nports * iaq.nnmrxq;
1624 		s->nnmtxq += nports * iaq.nnmtxq;
1625 	}
1626 	if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) {
1627 		s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi;
1628 		s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi;
1629 	}
1630 	s->neq += s->nnmtxq + s->nnmrxq;
1631 	s->niq += s->nnmrxq;
1632 
1633 	s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1634 	    M_CXGBE, M_ZERO | M_WAITOK);
1635 	s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1636 	    M_CXGBE, M_ZERO | M_WAITOK);
1637 #endif
1638 	MPASS(s->niq <= s->iqmap_sz);
1639 	MPASS(s->neq <= s->eqmap_sz);
1640 
1641 	s->ctrlq = malloc(s->nctrlq * sizeof(struct sge_wrq), M_CXGBE,
1642 	    M_ZERO | M_WAITOK);
1643 	s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1644 	    M_ZERO | M_WAITOK);
1645 	s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1646 	    M_ZERO | M_WAITOK);
1647 	s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE,
1648 	    M_ZERO | M_WAITOK);
1649 	s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE,
1650 	    M_ZERO | M_WAITOK);
1651 
1652 	sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1653 	    M_ZERO | M_WAITOK);
1654 
1655 	t4_init_l2t(sc, M_WAITOK);
1656 	t4_init_smt(sc, M_WAITOK);
1657 	t4_init_tx_sched(sc);
1658 	t4_init_atid_table(sc);
1659 #ifdef RATELIMIT
1660 	t4_init_etid_table(sc);
1661 #endif
1662 #ifdef INET6
1663 	t4_init_clip_table(sc);
1664 #endif
1665 	if (sc->vres.key.size != 0)
1666 		sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1667 		    sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1668 	t4_init_tpt(sc);
1669 
1670 	/*
1671 	 * Second pass over the ports.  This time we know the number of rx and
1672 	 * tx queues that each port should get.
1673 	 */
1674 	rqidx = tqidx = 0;
1675 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1676 	ofld_tqidx = 0;
1677 #endif
1678 #ifdef TCP_OFFLOAD
1679 	ofld_rqidx = 0;
1680 #endif
1681 #ifdef DEV_NETMAP
1682 	nm_rqidx = nm_tqidx = 0;
1683 #endif
1684 	for_each_port(sc, i) {
1685 		struct port_info *pi = sc->port[i];
1686 		struct vi_info *vi;
1687 
1688 		if (pi == NULL)
1689 			continue;
1690 
1691 		pi->nvi = num_vis;
1692 		for_each_vi(pi, j, vi) {
1693 			vi->pi = pi;
1694 			vi->adapter = sc;
1695 			vi->first_intr = -1;
1696 			vi->qsize_rxq = t4_qsize_rxq;
1697 			vi->qsize_txq = t4_qsize_txq;
1698 
1699 			vi->first_rxq = rqidx;
1700 			vi->first_txq = tqidx;
1701 			vi->tmr_idx = t4_tmr_idx;
1702 			vi->pktc_idx = t4_pktc_idx;
1703 			vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1704 			vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1705 
1706 			rqidx += vi->nrxq;
1707 			tqidx += vi->ntxq;
1708 
1709 			if (j == 0 && vi->ntxq > 1)
1710 				vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1711 			else
1712 				vi->rsrv_noflowq = 0;
1713 
1714 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1715 			vi->first_ofld_txq = ofld_tqidx;
1716 			vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1717 			ofld_tqidx += vi->nofldtxq;
1718 #endif
1719 #ifdef TCP_OFFLOAD
1720 			vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1721 			vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1722 			vi->first_ofld_rxq = ofld_rqidx;
1723 			vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1724 
1725 			ofld_rqidx += vi->nofldrxq;
1726 #endif
1727 #ifdef DEV_NETMAP
1728 			vi->first_nm_rxq = nm_rqidx;
1729 			vi->first_nm_txq = nm_tqidx;
1730 			if (j == 0) {
1731 				vi->nnmrxq = iaq.nnmrxq;
1732 				vi->nnmtxq = iaq.nnmtxq;
1733 			} else {
1734 				vi->nnmrxq = iaq.nnmrxq_vi;
1735 				vi->nnmtxq = iaq.nnmtxq_vi;
1736 			}
1737 			nm_rqidx += vi->nnmrxq;
1738 			nm_tqidx += vi->nnmtxq;
1739 #endif
1740 		}
1741 	}
1742 
1743 	rc = t4_setup_intr_handlers(sc);
1744 	if (rc != 0) {
1745 		device_printf(dev,
1746 		    "failed to setup interrupt handlers: %d\n", rc);
1747 		goto done;
1748 	}
1749 
1750 	bus_identify_children(dev);
1751 
1752 	/*
1753 	 * Ensure thread-safe mailbox access (in debug builds).
1754 	 *
1755 	 * So far this was the only thread accessing the mailbox but various
1756 	 * ifnets and sysctls are about to be created and their handlers/ioctls
1757 	 * will access the mailbox from different threads.
1758 	 */
1759 	sc->flags |= CHK_MBOX_ACCESS;
1760 
1761 	bus_attach_children(dev);
1762 	t4_calibration_start(sc);
1763 
1764 	device_printf(dev,
1765 	    "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1766 	    sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1767 	    sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1768 	    (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1769 	    sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1770 
1771 	t4_set_desc(sc);
1772 
1773 	notify_siblings(dev, 0);
1774 
1775 done:
1776 	if (rc != 0 && sc->cdev) {
1777 		/* cdev was created and so cxgbetool works; recover that way. */
1778 		device_printf(dev,
1779 		    "error during attach, adapter is now in recovery mode.\n");
1780 		rc = 0;
1781 	}
1782 
1783 	if (rc != 0)
1784 		t4_detach_common(dev);
1785 	else
1786 		t4_sysctls(sc);
1787 
1788 	return (rc);
1789 }
1790 
1791 static int
1792 t4_child_location(device_t bus, device_t dev, struct sbuf *sb)
1793 {
1794 	struct adapter *sc;
1795 	struct port_info *pi;
1796 	int i;
1797 
1798 	sc = device_get_softc(bus);
1799 	for_each_port(sc, i) {
1800 		pi = sc->port[i];
1801 		if (pi != NULL && pi->dev == dev) {
1802 			sbuf_printf(sb, "port=%d", pi->port_id);
1803 			break;
1804 		}
1805 	}
1806 	return (0);
1807 }
1808 
1809 static int
1810 t4_ready(device_t dev)
1811 {
1812 	struct adapter *sc;
1813 
1814 	sc = device_get_softc(dev);
1815 	if (sc->flags & FW_OK)
1816 		return (0);
1817 	return (ENXIO);
1818 }
1819 
1820 static int
1821 t4_read_port_device(device_t dev, int port, device_t *child)
1822 {
1823 	struct adapter *sc;
1824 	struct port_info *pi;
1825 
1826 	sc = device_get_softc(dev);
1827 	if (port < 0 || port >= MAX_NPORTS)
1828 		return (EINVAL);
1829 	pi = sc->port[port];
1830 	if (pi == NULL || pi->dev == NULL)
1831 		return (ENXIO);
1832 	*child = pi->dev;
1833 	return (0);
1834 }
1835 
1836 static int
1837 notify_siblings(device_t dev, int detaching)
1838 {
1839 	device_t sibling;
1840 	int error, i;
1841 
1842 	error = 0;
1843 	for (i = 0; i < PCI_FUNCMAX; i++) {
1844 		if (i == pci_get_function(dev))
1845 			continue;
1846 		sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1847 		    pci_get_slot(dev), i);
1848 		if (sibling == NULL || !device_is_attached(sibling))
1849 			continue;
1850 		if (detaching)
1851 			error = T4_DETACH_CHILD(sibling);
1852 		else
1853 			(void)T4_ATTACH_CHILD(sibling);
1854 		if (error)
1855 			break;
1856 	}
1857 	return (error);
1858 }
1859 
1860 /*
1861  * Idempotent
1862  */
1863 static int
1864 t4_detach(device_t dev)
1865 {
1866 	int rc;
1867 
1868 	rc = notify_siblings(dev, 1);
1869 	if (rc) {
1870 		device_printf(dev,
1871 		    "failed to detach sibling devices: %d\n", rc);
1872 		return (rc);
1873 	}
1874 
1875 	return (t4_detach_common(dev));
1876 }
1877 
1878 int
1879 t4_detach_common(device_t dev)
1880 {
1881 	struct adapter *sc;
1882 	struct port_info *pi;
1883 	int i, rc;
1884 
1885 	sc = device_get_softc(dev);
1886 
1887 #ifdef TCP_OFFLOAD
1888 	rc = deactivate_all_uld(sc);
1889 	if (rc) {
1890 		device_printf(dev,
1891 		    "failed to detach upper layer drivers: %d\n", rc);
1892 		return (rc);
1893 	}
1894 #endif
1895 
1896 	if (sc->cdev) {
1897 		destroy_dev(sc->cdev);
1898 		sc->cdev = NULL;
1899 	}
1900 
1901 	sx_xlock(&t4_list_lock);
1902 	SLIST_REMOVE(&t4_list, sc, adapter, link);
1903 	sx_xunlock(&t4_list_lock);
1904 
1905 	sc->flags &= ~CHK_MBOX_ACCESS;
1906 	if (sc->flags & FULL_INIT_DONE) {
1907 		if (!(sc->flags & IS_VF))
1908 			t4_intr_disable(sc);
1909 	}
1910 
1911 	if (device_is_attached(dev)) {
1912 		rc = bus_detach_children(dev);
1913 		if (rc) {
1914 			device_printf(dev,
1915 			    "failed to detach child devices: %d\n", rc);
1916 			return (rc);
1917 		}
1918 	}
1919 
1920 	for (i = 0; i < sc->intr_count; i++)
1921 		t4_free_irq(sc, &sc->irq[i]);
1922 
1923 	if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1924 		t4_free_tx_sched(sc);
1925 
1926 	for (i = 0; i < MAX_NPORTS; i++) {
1927 		pi = sc->port[i];
1928 		if (pi) {
1929 			t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1930 
1931 			mtx_destroy(&pi->pi_lock);
1932 			free(pi->vi, M_CXGBE);
1933 			free(pi, M_CXGBE);
1934 		}
1935 	}
1936 	callout_stop(&sc->cal_callout);
1937 	callout_drain(&sc->cal_callout);
1938 	device_delete_children(dev);
1939 	sysctl_ctx_free(&sc->ctx);
1940 	adapter_full_uninit(sc);
1941 
1942 	if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1943 		t4_fw_bye(sc, sc->mbox);
1944 
1945 	if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1946 		pci_release_msi(dev);
1947 
1948 	if (sc->regs_res)
1949 		bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1950 		    sc->regs_res);
1951 
1952 	if (sc->udbs_res)
1953 		bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1954 		    sc->udbs_res);
1955 
1956 	if (sc->msix_res)
1957 		bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1958 		    sc->msix_res);
1959 
1960 	if (sc->l2t)
1961 		t4_free_l2t(sc);
1962 	if (sc->smt)
1963 		t4_free_smt(sc->smt);
1964 	t4_free_atid_table(sc);
1965 #ifdef RATELIMIT
1966 	t4_free_etid_table(sc);
1967 #endif
1968 	if (sc->key_map)
1969 		vmem_destroy(sc->key_map);
1970 	t4_free_tpt(sc);
1971 #ifdef INET6
1972 	t4_destroy_clip_table(sc);
1973 #endif
1974 
1975 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1976 	free(sc->sge.ofld_txq, M_CXGBE);
1977 #endif
1978 #ifdef TCP_OFFLOAD
1979 	free(sc->sge.ofld_rxq, M_CXGBE);
1980 #endif
1981 #ifdef DEV_NETMAP
1982 	free(sc->sge.nm_rxq, M_CXGBE);
1983 	free(sc->sge.nm_txq, M_CXGBE);
1984 #endif
1985 	free(sc->irq, M_CXGBE);
1986 	free(sc->sge.rxq, M_CXGBE);
1987 	free(sc->sge.txq, M_CXGBE);
1988 	free(sc->sge.ctrlq, M_CXGBE);
1989 	free(sc->sge.iqmap, M_CXGBE);
1990 	free(sc->sge.eqmap, M_CXGBE);
1991 	free(sc->tids.ftid_tab, M_CXGBE);
1992 	free(sc->tids.hpftid_tab, M_CXGBE);
1993 	free_hftid_hash(&sc->tids);
1994 	free(sc->tids.tid_tab, M_CXGBE);
1995 	t4_destroy_dma_tag(sc);
1996 
1997 	callout_drain(&sc->ktls_tick);
1998 	callout_drain(&sc->sfl_callout);
1999 	if (mtx_initialized(&sc->tids.ftid_lock)) {
2000 		mtx_destroy(&sc->tids.ftid_lock);
2001 		cv_destroy(&sc->tids.ftid_cv);
2002 	}
2003 	if (mtx_initialized(&sc->tids.atid_lock))
2004 		mtx_destroy(&sc->tids.atid_lock);
2005 	if (mtx_initialized(&sc->ifp_lock))
2006 		mtx_destroy(&sc->ifp_lock);
2007 
2008 	if (rw_initialized(&sc->policy_lock)) {
2009 		rw_destroy(&sc->policy_lock);
2010 #ifdef TCP_OFFLOAD
2011 		if (sc->policy != NULL)
2012 			free_offload_policy(sc->policy);
2013 #endif
2014 	}
2015 
2016 	for (i = 0; i < NUM_MEMWIN; i++) {
2017 		struct memwin *mw = &sc->memwin[i];
2018 
2019 		if (rw_initialized(&mw->mw_lock))
2020 			rw_destroy(&mw->mw_lock);
2021 	}
2022 
2023 	mtx_destroy(&sc->sfl_lock);
2024 	mtx_destroy(&sc->reg_lock);
2025 	mtx_destroy(&sc->sc_lock);
2026 
2027 	bzero(sc, sizeof(*sc));
2028 
2029 	return (0);
2030 }
2031 
2032 static inline int
2033 stop_adapter(struct adapter *sc)
2034 {
2035 	struct port_info *pi;
2036 	int i;
2037 
2038 	if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) {
2039 		CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n",
2040 			 __func__, curthread, sc->flags, sc->error_flags);
2041 		return (EALREADY);
2042 	}
2043 	CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread,
2044 		 sc->flags, sc->error_flags);
2045 	t4_shutdown_adapter(sc);
2046 	for_each_port(sc, i) {
2047 		pi = sc->port[i];
2048 		if (pi == NULL)
2049 			continue;
2050 		PORT_LOCK(pi);
2051 		if (pi->up_vis > 0 && pi->link_cfg.link_ok) {
2052 			/*
2053 			 * t4_shutdown_adapter has already shut down all the
2054 			 * PHYs but it also disables interrupts and DMA so there
2055 			 * won't be a link interrupt.  Update the state manually
2056 			 * if the link was up previously and inform the kernel.
2057 			 */
2058 			pi->link_cfg.link_ok = false;
2059 			t4_os_link_changed(pi);
2060 		}
2061 		PORT_UNLOCK(pi);
2062 	}
2063 
2064 	return (0);
2065 }
2066 
2067 static inline int
2068 restart_adapter(struct adapter *sc)
2069 {
2070 	uint32_t val;
2071 
2072 	if (!atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_STOPPED))) {
2073 		CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x, EALREADY\n",
2074 			 __func__, curthread, sc->flags, sc->error_flags);
2075 		return (EALREADY);
2076 	}
2077 	CH_ALERT(sc, "%s from %p, flags 0x%08x,0x%08x\n", __func__, curthread,
2078 		 sc->flags, sc->error_flags);
2079 
2080 	MPASS(hw_off_limits(sc));
2081 	MPASS((sc->flags & FW_OK) == 0);
2082 	MPASS((sc->flags & MASTER_PF) == 0);
2083 	MPASS(sc->reset_thread == NULL);
2084 
2085 	/*
2086 	 * The adapter is supposed to be back on PCIE with its config space and
2087 	 * BARs restored to their state before reset.  Register access via
2088 	 * t4_read_reg BAR0 should just work.
2089 	 */
2090 	sc->reset_thread = curthread;
2091 	val = t4_read_reg(sc, A_PL_WHOAMI);
2092 	if (val == 0xffffffff || val == 0xeeeeeeee) {
2093 		CH_ERR(sc, "%s: device registers not readable.\n", __func__);
2094 		sc->reset_thread = NULL;
2095 		atomic_set_int(&sc->error_flags, ADAP_STOPPED);
2096 		return (ENXIO);
2097 	}
2098 	atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR);
2099 	atomic_add_int(&sc->incarnation, 1);
2100 	atomic_add_int(&sc->num_resets, 1);
2101 
2102 	return (0);
2103 }
2104 
2105 static inline void
2106 set_adapter_hwstatus(struct adapter *sc, const bool usable)
2107 {
2108 	if (usable) {
2109 		/* Must be marked reusable by the designated thread. */
2110 		ASSERT_SYNCHRONIZED_OP(sc);
2111 		MPASS(sc->reset_thread == curthread);
2112 		mtx_lock(&sc->reg_lock);
2113 		atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS);
2114 		mtx_unlock(&sc->reg_lock);
2115 	} else {
2116 		/* Mark the adapter totally off limits. */
2117 		begin_synchronized_op(sc, NULL, SLEEP_OK, "t4hwsts");
2118 		mtx_lock(&sc->reg_lock);
2119 		atomic_set_int(&sc->error_flags, HW_OFF_LIMITS);
2120 		mtx_unlock(&sc->reg_lock);
2121 		sc->flags &= ~(FW_OK | MASTER_PF);
2122 		sc->reset_thread = NULL;
2123 		end_synchronized_op(sc, 0);
2124 	}
2125 }
2126 
2127 static int
2128 stop_lld(struct adapter *sc)
2129 {
2130 	struct port_info *pi;
2131 	struct vi_info *vi;
2132 	if_t ifp;
2133 	struct sge_rxq *rxq;
2134 	struct sge_txq *txq;
2135 	struct sge_wrq *wrq;
2136 #ifdef TCP_OFFLOAD
2137 	struct sge_ofld_rxq *ofld_rxq;
2138 #endif
2139 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2140 	struct sge_ofld_txq *ofld_txq;
2141 #endif
2142 	int rc, i, j, k;
2143 
2144 	/*
2145 	 * XXX: Can there be a synch_op in progress that will hang because
2146 	 * hardware has been stopped?  We'll hang too and the solution will be
2147 	 * to use a version of begin_synch_op that wakes up existing synch_op
2148 	 * with errors.  Maybe stop_adapter should do this wakeup?
2149 	 *
2150 	 * I don't think any synch_op could get stranded waiting for DMA or
2151 	 * interrupt so I think we're okay here.  Remove this comment block
2152 	 * after testing.
2153 	 */
2154 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4slld");
2155 	if (rc != 0)
2156 		return (ENXIO);
2157 
2158 	/* Quiesce all activity. */
2159 	for_each_port(sc, i) {
2160 		pi = sc->port[i];
2161 		if (pi == NULL)
2162 			continue;
2163 		pi->vxlan_tcam_entry = false;
2164 		for_each_vi(pi, j, vi) {
2165 			vi->xact_addr_filt = -1;
2166 			mtx_lock(&vi->tick_mtx);
2167 			vi->flags |= VI_SKIP_STATS;
2168 			mtx_unlock(&vi->tick_mtx);
2169 			if (!(vi->flags & VI_INIT_DONE))
2170 				continue;
2171 
2172 			ifp = vi->ifp;
2173 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2174 				mtx_lock(&vi->tick_mtx);
2175 				callout_stop(&vi->tick);
2176 				mtx_unlock(&vi->tick_mtx);
2177 				callout_drain(&vi->tick);
2178 			}
2179 
2180 			/*
2181 			 * Note that the HW is not available.
2182 			 */
2183 			for_each_txq(vi, k, txq) {
2184 				TXQ_LOCK(txq);
2185 				txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED);
2186 				TXQ_UNLOCK(txq);
2187 			}
2188 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2189 			for_each_ofld_txq(vi, k, ofld_txq) {
2190 				TXQ_LOCK(&ofld_txq->wrq);
2191 				ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED;
2192 				TXQ_UNLOCK(&ofld_txq->wrq);
2193 			}
2194 #endif
2195 			for_each_rxq(vi, k, rxq) {
2196 				rxq->iq.flags &= ~IQ_HW_ALLOCATED;
2197 			}
2198 #if defined(TCP_OFFLOAD)
2199 			for_each_ofld_rxq(vi, k, ofld_rxq) {
2200 				ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED;
2201 			}
2202 #endif
2203 
2204 			quiesce_vi(vi);
2205 		}
2206 
2207 		if (sc->flags & FULL_INIT_DONE) {
2208 			/* Control queue */
2209 			wrq = &sc->sge.ctrlq[i];
2210 			TXQ_LOCK(wrq);
2211 			wrq->eq.flags &= ~EQ_HW_ALLOCATED;
2212 			TXQ_UNLOCK(wrq);
2213 			quiesce_wrq(wrq);
2214 		}
2215 
2216 		if (pi->flags & HAS_TRACEQ) {
2217 			pi->flags &= ~HAS_TRACEQ;
2218 			sc->traceq = -1;
2219 			sc->tracer_valid = 0;
2220 			sc->tracer_enabled = 0;
2221 		}
2222 	}
2223 	if (sc->flags & FULL_INIT_DONE) {
2224 		/* Firmware event queue */
2225 		sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED;
2226 		quiesce_iq_fl(sc, &sc->sge.fwq, NULL);
2227 	}
2228 
2229 	/* Stop calibration */
2230 	callout_stop(&sc->cal_callout);
2231 	callout_drain(&sc->cal_callout);
2232 
2233 	if (t4_clock_gate_on_suspend) {
2234 		t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN |
2235 		    F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN |
2236 		    F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0);
2237 	}
2238 
2239 	end_synchronized_op(sc, 0);
2240 
2241 	stop_atid_allocator(sc);
2242 	t4_stop_l2t(sc);
2243 
2244 	return (rc);
2245 }
2246 
2247 int
2248 suspend_adapter(struct adapter *sc)
2249 {
2250 	stop_adapter(sc);
2251 	stop_lld(sc);
2252 #ifdef TCP_OFFLOAD
2253 	stop_all_uld(sc);
2254 #endif
2255 	set_adapter_hwstatus(sc, false);
2256 
2257 	return (0);
2258 }
2259 
2260 static int
2261 t4_suspend(device_t dev)
2262 {
2263 	struct adapter *sc = device_get_softc(dev);
2264 	int rc;
2265 
2266 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2267 	rc = suspend_adapter(sc);
2268 	CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread);
2269 
2270 	return (rc);
2271 }
2272 
2273 struct adapter_pre_reset_state {
2274 	u_int flags;
2275 	uint16_t nbmcaps;
2276 	uint16_t linkcaps;
2277 	uint16_t switchcaps;
2278 	uint16_t nvmecaps;
2279 	uint16_t niccaps;
2280 	uint16_t toecaps;
2281 	uint16_t rdmacaps;
2282 	uint16_t cryptocaps;
2283 	uint16_t iscsicaps;
2284 	uint16_t fcoecaps;
2285 
2286 	u_int cfcsum;
2287 	char cfg_file[32];
2288 
2289 	struct adapter_params params;
2290 	struct t4_virt_res vres;
2291 	struct tid_info tids;
2292 	struct sge sge;
2293 
2294 	int rawf_base;
2295 	int nrawf;
2296 
2297 };
2298 
2299 static void
2300 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2301 {
2302 
2303 	ASSERT_SYNCHRONIZED_OP(sc);
2304 
2305 	o->flags = sc->flags;
2306 
2307 	o->nbmcaps =  sc->nbmcaps;
2308 	o->linkcaps = sc->linkcaps;
2309 	o->switchcaps = sc->switchcaps;
2310 	o->nvmecaps = sc->nvmecaps;
2311 	o->niccaps = sc->niccaps;
2312 	o->toecaps = sc->toecaps;
2313 	o->rdmacaps = sc->rdmacaps;
2314 	o->cryptocaps = sc->cryptocaps;
2315 	o->iscsicaps = sc->iscsicaps;
2316 	o->fcoecaps = sc->fcoecaps;
2317 
2318 	o->cfcsum = sc->cfcsum;
2319 	MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file));
2320 	memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file));
2321 
2322 	o->params = sc->params;
2323 	o->vres = sc->vres;
2324 	o->tids = sc->tids;
2325 	o->sge = sc->sge;
2326 
2327 	o->rawf_base = sc->rawf_base;
2328 	o->nrawf = sc->nrawf;
2329 }
2330 
2331 static int
2332 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2333 {
2334 	int rc = 0;
2335 
2336 	ASSERT_SYNCHRONIZED_OP(sc);
2337 
2338 	/* Capabilities */
2339 #define COMPARE_CAPS(c) do { \
2340 	if (o->c##caps != sc->c##caps) { \
2341 		CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \
2342 		    sc->c##caps); \
2343 		rc = EINVAL; \
2344 	} \
2345 } while (0)
2346 	COMPARE_CAPS(nbm);
2347 	COMPARE_CAPS(link);
2348 	COMPARE_CAPS(switch);
2349 	COMPARE_CAPS(nvme);
2350 	COMPARE_CAPS(nic);
2351 	COMPARE_CAPS(toe);
2352 	COMPARE_CAPS(rdma);
2353 	COMPARE_CAPS(crypto);
2354 	COMPARE_CAPS(iscsi);
2355 	COMPARE_CAPS(fcoe);
2356 #undef COMPARE_CAPS
2357 
2358 	/* Firmware config file */
2359 	if (o->cfcsum != sc->cfcsum) {
2360 		CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file,
2361 		    o->cfcsum, sc->cfg_file, sc->cfcsum);
2362 		rc = EINVAL;
2363 	}
2364 
2365 #define COMPARE_PARAM(p, name) do { \
2366 	if (o->p != sc->p) { \
2367 		CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \
2368 		rc = EINVAL; \
2369 	} \
2370 } while (0)
2371 	COMPARE_PARAM(sge.iq_start, iq_start);
2372 	COMPARE_PARAM(sge.eq_start, eq_start);
2373 	COMPARE_PARAM(tids.ftid_base, ftid_base);
2374 	COMPARE_PARAM(tids.ftid_end, ftid_end);
2375 	COMPARE_PARAM(tids.nftids, nftids);
2376 	COMPARE_PARAM(vres.l2t.start, l2t_start);
2377 	COMPARE_PARAM(vres.l2t.size, l2t_size);
2378 	COMPARE_PARAM(sge.iqmap_sz, iqmap_sz);
2379 	COMPARE_PARAM(sge.eqmap_sz, eqmap_sz);
2380 	COMPARE_PARAM(tids.tid_base, tid_base);
2381 	COMPARE_PARAM(tids.hpftid_base, hpftid_base);
2382 	COMPARE_PARAM(tids.hpftid_end, hpftid_end);
2383 	COMPARE_PARAM(tids.nhpftids, nhpftids);
2384 	COMPARE_PARAM(rawf_base, rawf_base);
2385 	COMPARE_PARAM(nrawf, nrawf);
2386 	COMPARE_PARAM(params.mps_bg_map, mps_bg_map);
2387 	COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support);
2388 	COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl);
2389 	COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support);
2390 	COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr);
2391 	COMPARE_PARAM(tids.ntids, ntids);
2392 	COMPARE_PARAM(tids.etid_base, etid_base);
2393 	COMPARE_PARAM(tids.etid_end, etid_end);
2394 	COMPARE_PARAM(tids.netids, netids);
2395 	COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred);
2396 	COMPARE_PARAM(params.ethoffload, ethoffload);
2397 	COMPARE_PARAM(tids.natids, natids);
2398 	COMPARE_PARAM(tids.stid_base, stid_base);
2399 	COMPARE_PARAM(vres.ddp.start, ddp_start);
2400 	COMPARE_PARAM(vres.ddp.size, ddp_size);
2401 	COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred);
2402 	COMPARE_PARAM(vres.stag.start, stag_start);
2403 	COMPARE_PARAM(vres.stag.size, stag_size);
2404 	COMPARE_PARAM(vres.rq.start, rq_start);
2405 	COMPARE_PARAM(vres.rq.size, rq_size);
2406 	COMPARE_PARAM(vres.pbl.start, pbl_start);
2407 	COMPARE_PARAM(vres.pbl.size, pbl_size);
2408 	COMPARE_PARAM(vres.qp.start, qp_start);
2409 	COMPARE_PARAM(vres.qp.size, qp_size);
2410 	COMPARE_PARAM(vres.cq.start, cq_start);
2411 	COMPARE_PARAM(vres.cq.size, cq_size);
2412 	COMPARE_PARAM(vres.ocq.start, ocq_start);
2413 	COMPARE_PARAM(vres.ocq.size, ocq_size);
2414 	COMPARE_PARAM(vres.srq.start, srq_start);
2415 	COMPARE_PARAM(vres.srq.size, srq_size);
2416 	COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp);
2417 	COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter);
2418 	COMPARE_PARAM(vres.iscsi.start, iscsi_start);
2419 	COMPARE_PARAM(vres.iscsi.size, iscsi_size);
2420 	COMPARE_PARAM(vres.key.start, key_start);
2421 	COMPARE_PARAM(vres.key.size, key_size);
2422 #undef COMPARE_PARAM
2423 
2424 	return (rc);
2425 }
2426 
2427 static int
2428 restart_lld(struct adapter *sc)
2429 {
2430 	struct adapter_pre_reset_state *old_state = NULL;
2431 	struct port_info *pi;
2432 	struct vi_info *vi;
2433 	if_t ifp;
2434 	struct sge_txq *txq;
2435 	int rc, i, j, k;
2436 
2437 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rlld");
2438 	if (rc != 0)
2439 		return (ENXIO);
2440 
2441 	/* Restore memory window. */
2442 	setup_memwin(sc);
2443 
2444 	/* Go no further if recovery mode has been requested. */
2445 	if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
2446 		CH_ALERT(sc, "%s: recovery mode during restart.\n", __func__);
2447 		rc = 0;
2448 		set_adapter_hwstatus(sc, true);
2449 		goto done;
2450 	}
2451 
2452 	old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK);
2453 	save_caps_and_params(sc, old_state);
2454 
2455 	/* Reestablish contact with firmware and become the primary PF. */
2456 	rc = contact_firmware(sc);
2457 	if (rc != 0)
2458 		goto done; /* error message displayed already */
2459 	MPASS(sc->flags & FW_OK);
2460 
2461 	if (sc->flags & MASTER_PF) {
2462 		rc = partition_resources(sc);
2463 		if (rc != 0)
2464 			goto done; /* error message displayed already */
2465 	}
2466 
2467 	rc = get_params__post_init(sc);
2468 	if (rc != 0)
2469 		goto done; /* error message displayed already */
2470 
2471 	rc = set_params__post_init(sc);
2472 	if (rc != 0)
2473 		goto done; /* error message displayed already */
2474 
2475 	rc = compare_caps_and_params(sc, old_state);
2476 	if (rc != 0)
2477 		goto done; /* error message displayed already */
2478 
2479 	for_each_port(sc, i) {
2480 		pi = sc->port[i];
2481 		MPASS(pi != NULL);
2482 		MPASS(pi->vi != NULL);
2483 		MPASS(pi->vi[0].dev == pi->dev);
2484 
2485 		rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
2486 		if (rc != 0) {
2487 			CH_ERR(sc,
2488 			    "failed to re-initialize port %d: %d\n", i, rc);
2489 			goto done;
2490 		}
2491 		MPASS(sc->chan_map[pi->tx_chan] == i);
2492 
2493 		PORT_LOCK(pi);
2494 		fixup_link_config(pi);
2495 		build_medialist(pi);
2496 		PORT_UNLOCK(pi);
2497 		for_each_vi(pi, j, vi) {
2498 			if (IS_MAIN_VI(vi))
2499 				continue;
2500 			rc = alloc_extra_vi(sc, pi, vi);
2501 			if (rc != 0) {
2502 				CH_ERR(vi,
2503 				    "failed to re-allocate extra VI: %d\n", rc);
2504 				goto done;
2505 			}
2506 		}
2507 	}
2508 
2509 	/*
2510 	 * Interrupts and queues are about to be enabled and other threads will
2511 	 * want to access the hardware too.  It is safe to do so.  Note that
2512 	 * this thread is still in the middle of a synchronized_op.
2513 	 */
2514 	set_adapter_hwstatus(sc, true);
2515 
2516 	if (sc->flags & FULL_INIT_DONE) {
2517 		rc = adapter_full_init(sc);
2518 		if (rc != 0) {
2519 			CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc);
2520 			goto done;
2521 		}
2522 
2523 		if (sc->vxlan_refcount > 0)
2524 			enable_vxlan_rx(sc);
2525 
2526 		for_each_port(sc, i) {
2527 			pi = sc->port[i];
2528 			for_each_vi(pi, j, vi) {
2529 				mtx_lock(&vi->tick_mtx);
2530 				vi->flags &= ~VI_SKIP_STATS;
2531 				mtx_unlock(&vi->tick_mtx);
2532 				if (!(vi->flags & VI_INIT_DONE))
2533 					continue;
2534 				rc = vi_full_init(vi);
2535 				if (rc != 0) {
2536 					CH_ERR(vi, "failed to re-initialize "
2537 					    "interface: %d\n", rc);
2538 					goto done;
2539 				}
2540 				if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
2541 					sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
2542 					t4_set_trace_rss_control(sc, pi->tx_chan, sc->traceq);
2543 					pi->flags |= HAS_TRACEQ;
2544 				}
2545 
2546 				ifp = vi->ifp;
2547 				if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
2548 					continue;
2549 				/*
2550 				 * Note that we do not setup multicast addresses
2551 				 * in the first pass.  This ensures that the
2552 				 * unicast DMACs for all VIs on all ports get an
2553 				 * MPS TCAM entry.
2554 				 */
2555 				rc = update_mac_settings(ifp, XGMAC_ALL &
2556 				    ~XGMAC_MCADDRS);
2557 				if (rc != 0) {
2558 					CH_ERR(vi, "failed to re-configure MAC: %d\n", rc);
2559 					goto done;
2560 				}
2561 				rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true,
2562 				    true);
2563 				if (rc != 0) {
2564 					CH_ERR(vi, "failed to re-enable VI: %d\n", rc);
2565 					goto done;
2566 				}
2567 				for_each_txq(vi, k, txq) {
2568 					TXQ_LOCK(txq);
2569 					txq->eq.flags |= EQ_ENABLED;
2570 					TXQ_UNLOCK(txq);
2571 				}
2572 				mtx_lock(&vi->tick_mtx);
2573 				callout_schedule(&vi->tick, hz);
2574 				mtx_unlock(&vi->tick_mtx);
2575 			}
2576 			PORT_LOCK(pi);
2577 			if (pi->up_vis > 0) {
2578 				t4_update_port_info(pi);
2579 				fixup_link_config(pi);
2580 				build_medialist(pi);
2581 				apply_link_config(pi);
2582 				if (pi->link_cfg.link_ok)
2583 					t4_os_link_changed(pi);
2584 			}
2585 			PORT_UNLOCK(pi);
2586 		}
2587 
2588 		/* Now reprogram the L2 multicast addresses. */
2589 		for_each_port(sc, i) {
2590 			pi = sc->port[i];
2591 			for_each_vi(pi, j, vi) {
2592 				if (!(vi->flags & VI_INIT_DONE))
2593 					continue;
2594 				ifp = vi->ifp;
2595 				if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
2596 					continue;
2597 				rc = update_mac_settings(ifp, XGMAC_MCADDRS);
2598 				if (rc != 0) {
2599 					CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc);
2600 					rc = 0;	/* carry on */
2601 				}
2602 			}
2603 		}
2604 	}
2605 
2606 	/* Reset all calibration */
2607 	t4_calibration_start(sc);
2608 done:
2609 	end_synchronized_op(sc, 0);
2610 	free(old_state, M_CXGBE);
2611 
2612 	restart_atid_allocator(sc);
2613 	t4_restart_l2t(sc);
2614 
2615 	return (rc);
2616 }
2617 
2618 int
2619 resume_adapter(struct adapter *sc)
2620 {
2621 	restart_adapter(sc);
2622 	restart_lld(sc);
2623 #ifdef TCP_OFFLOAD
2624 	restart_all_uld(sc);
2625 #endif
2626 	return (0);
2627 }
2628 
2629 static int
2630 t4_resume(device_t dev)
2631 {
2632 	struct adapter *sc = device_get_softc(dev);
2633 	int rc;
2634 
2635 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2636 	rc = resume_adapter(sc);
2637 	CH_ALERT(sc, "%s end (thread %p).\n", __func__, curthread);
2638 
2639 	return (rc);
2640 }
2641 
2642 static int
2643 t4_reset_prepare(device_t dev, device_t child)
2644 {
2645 	struct adapter *sc = device_get_softc(dev);
2646 
2647 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2648 	return (0);
2649 }
2650 
2651 static int
2652 t4_reset_post(device_t dev, device_t child)
2653 {
2654 	struct adapter *sc = device_get_softc(dev);
2655 
2656 	CH_ALERT(sc, "%s from thread %p.\n", __func__, curthread);
2657 	return (0);
2658 }
2659 
2660 static int
2661 reset_adapter_with_pl_rst(struct adapter *sc)
2662 {
2663 	/* This is a t4_write_reg without the hw_off_limits check. */
2664 	MPASS(sc->error_flags & HW_OFF_LIMITS);
2665 	bus_space_write_4(sc->bt, sc->bh, A_PL_RST,
2666 			  F_PIORSTMODE | F_PIORST | F_AUTOPCIEPAUSE);
2667 	pause("pl_rst", 1 * hz);		/* Wait 1s for reset */
2668 	return (0);
2669 }
2670 
2671 static int
2672 reset_adapter_with_pcie_sbr(struct adapter *sc)
2673 {
2674 	device_t pdev = device_get_parent(sc->dev);
2675 	device_t gpdev = device_get_parent(pdev);
2676 	device_t *children;
2677 	int rc, i, lcap, lsta, nchildren;
2678 	uint32_t v;
2679 
2680 	rc = pci_find_cap(gpdev, PCIY_EXPRESS, &v);
2681 	if (rc != 0) {
2682 		CH_ERR(sc, "%s: pci_find_cap(%s, pcie) failed: %d\n", __func__,
2683 		    device_get_nameunit(gpdev), rc);
2684 		return (ENOTSUP);
2685 	}
2686 	lcap = v + PCIER_LINK_CAP;
2687 	lsta = v + PCIER_LINK_STA;
2688 
2689 	nchildren = 0;
2690 	device_get_children(pdev, &children, &nchildren);
2691 	for (i = 0; i < nchildren; i++)
2692 		pci_save_state(children[i]);
2693 	v = pci_read_config(gpdev, PCIR_BRIDGECTL_1, 2);
2694 	pci_write_config(gpdev, PCIR_BRIDGECTL_1, v | PCIB_BCR_SECBUS_RESET, 2);
2695 	pause("pcie_sbr1", hz / 10);	/* 100ms */
2696 	pci_write_config(gpdev, PCIR_BRIDGECTL_1, v, 2);
2697 	pause("pcie_sbr2", hz);		/* Wait 1s before restore_state. */
2698 	v = pci_read_config(gpdev, lsta, 2);
2699 	if (pci_read_config(gpdev, lcap, 2) & PCIEM_LINK_CAP_DL_ACTIVE)
2700 		rc = v & PCIEM_LINK_STA_DL_ACTIVE ? 0 : ETIMEDOUT;
2701 	else if (v & (PCIEM_LINK_STA_TRAINING_ERROR | PCIEM_LINK_STA_TRAINING))
2702 		rc = ETIMEDOUT;
2703 	else
2704 		rc = 0;
2705 	if (rc != 0)
2706 		CH_ERR(sc, "%s: PCIe link is down after reset, LINK_STA 0x%x\n",
2707 		    __func__, v);
2708 	else {
2709 		for (i = 0; i < nchildren; i++)
2710 			pci_restore_state(children[i]);
2711 	}
2712 	free(children, M_TEMP);
2713 
2714 	return (rc);
2715 }
2716 
2717 static int
2718 reset_adapter_with_pcie_link_bounce(struct adapter *sc)
2719 {
2720 	device_t pdev = device_get_parent(sc->dev);
2721 	device_t gpdev = device_get_parent(pdev);
2722 	device_t *children;
2723 	int rc, i, lcap, lctl, lsta, nchildren;
2724 	uint32_t v;
2725 
2726 	rc = pci_find_cap(gpdev, PCIY_EXPRESS, &v);
2727 	if (rc != 0) {
2728 		CH_ERR(sc, "%s: pci_find_cap(%s, pcie) failed: %d\n", __func__,
2729 		    device_get_nameunit(gpdev), rc);
2730 		return (ENOTSUP);
2731 	}
2732 	lcap = v + PCIER_LINK_CAP;
2733 	lctl = v + PCIER_LINK_CTL;
2734 	lsta = v + PCIER_LINK_STA;
2735 
2736 	nchildren = 0;
2737 	device_get_children(pdev, &children, &nchildren);
2738 	for (i = 0; i < nchildren; i++)
2739 		pci_save_state(children[i]);
2740 	v = pci_read_config(gpdev, lctl, 2);
2741 	pci_write_config(gpdev, lctl, v | PCIEM_LINK_CTL_LINK_DIS, 2);
2742 	pause("pcie_lnk1", 100 * hz / 1000);	/* 100ms */
2743 	pci_write_config(gpdev, lctl, v | PCIEM_LINK_CTL_RETRAIN_LINK, 2);
2744 	pause("pcie_lnk2", hz);		/* Wait 1s before restore_state. */
2745 	v = pci_read_config(gpdev, lsta, 2);
2746 	if (pci_read_config(gpdev, lcap, 2) & PCIEM_LINK_CAP_DL_ACTIVE)
2747 		rc = v & PCIEM_LINK_STA_DL_ACTIVE ? 0 : ETIMEDOUT;
2748 	else if (v & (PCIEM_LINK_STA_TRAINING_ERROR | PCIEM_LINK_STA_TRAINING))
2749 		rc = ETIMEDOUT;
2750 	else
2751 		rc = 0;
2752 	if (rc != 0)
2753 		CH_ERR(sc, "%s: PCIe link is down after reset, LINK_STA 0x%x\n",
2754 		    __func__, v);
2755 	else {
2756 		for (i = 0; i < nchildren; i++)
2757 			pci_restore_state(children[i]);
2758 	}
2759 	free(children, M_TEMP);
2760 
2761 	return (rc);
2762 }
2763 
2764 static inline int
2765 reset_adapter(struct adapter *sc)
2766 {
2767 	int rc;
2768 	const int reset_method = vm_guest == VM_GUEST_NO ? t4_reset_method : 0;
2769 
2770 	rc = suspend_adapter(sc);
2771 	if (rc != 0)
2772 		return (rc);
2773 
2774 	switch (reset_method) {
2775 	case 1:
2776 		rc = reset_adapter_with_pcie_sbr(sc);
2777 		break;
2778 	case 2:
2779 		rc = reset_adapter_with_pcie_link_bounce(sc);
2780 		break;
2781 	case 0:
2782 	default:
2783 		rc = reset_adapter_with_pl_rst(sc);
2784 		break;
2785 	}
2786 	if (rc == 0)
2787 		rc = resume_adapter(sc);
2788 	return (rc);
2789 }
2790 
2791 static void
2792 reset_adapter_task(void *arg, int pending)
2793 {
2794 	struct adapter *sc = arg;
2795 	const int flags = sc->flags;
2796 	const int eflags = sc->error_flags;
2797 	int rc;
2798 
2799 	if (pending > 1)
2800 		CH_ALERT(sc, "%s: pending %d\n", __func__, pending);
2801 	rc = reset_adapter(sc);
2802 	if (rc != 0) {
2803 		CH_ERR(sc, "adapter did not reset properly, rc = %d, "
2804 		       "flags 0x%08x -> 0x%08x, err_flags 0x%08x -> 0x%08x.\n",
2805 		       rc, flags, sc->flags, eflags, sc->error_flags);
2806 	}
2807 }
2808 
2809 static int
2810 cxgbe_probe(device_t dev)
2811 {
2812 	struct port_info *pi = device_get_softc(dev);
2813 
2814 	device_set_descf(dev, "port %d", pi->port_id);
2815 
2816 	return (BUS_PROBE_DEFAULT);
2817 }
2818 
2819 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
2820     IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
2821     IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
2822     IFCAP_HWRXTSTMP | IFCAP_MEXTPG)
2823 #define T4_CAP_ENABLE (T4_CAP)
2824 
2825 static void
2826 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
2827 {
2828 	if_t ifp;
2829 	struct sbuf *sb;
2830 	struct sysctl_ctx_list *ctx = &vi->ctx;
2831 	struct sysctl_oid_list *children;
2832 	struct pfil_head_args pa;
2833 	struct adapter *sc = vi->adapter;
2834 
2835 	sysctl_ctx_init(ctx);
2836 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev));
2837 	vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq",
2838 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues");
2839 	vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq",
2840 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues");
2841 #ifdef DEV_NETMAP
2842 	vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq",
2843 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues");
2844 	vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq",
2845 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues");
2846 #endif
2847 #ifdef TCP_OFFLOAD
2848 	vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq",
2849 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues");
2850 #endif
2851 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2852 	vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq",
2853 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues");
2854 #endif
2855 
2856 	vi->xact_addr_filt = -1;
2857 	mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF);
2858 	callout_init_mtx(&vi->tick, &vi->tick_mtx, 0);
2859 	if (sc->flags & IS_VF || t4_tx_vm_wr != 0)
2860 		vi->flags |= TX_USES_VM_WR;
2861 
2862 	/* Allocate an ifnet and set it up */
2863 	ifp = if_alloc_dev(IFT_ETHER, dev);
2864 	vi->ifp = ifp;
2865 	if_setsoftc(ifp, vi);
2866 
2867 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2868 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
2869 
2870 	if_setinitfn(ifp, cxgbe_init);
2871 	if_setioctlfn(ifp, cxgbe_ioctl);
2872 	if_settransmitfn(ifp, cxgbe_transmit);
2873 	if_setqflushfn(ifp, cxgbe_qflush);
2874 	if (vi->pi->nvi > 1 || sc->flags & IS_VF)
2875 		if_setgetcounterfn(ifp, vi_get_counter);
2876 	else
2877 		if_setgetcounterfn(ifp, cxgbe_get_counter);
2878 #if defined(KERN_TLS) || defined(RATELIMIT)
2879 	if_setsndtagallocfn(ifp, cxgbe_snd_tag_alloc);
2880 #endif
2881 #ifdef RATELIMIT
2882 	if_setratelimitqueryfn(ifp, cxgbe_ratelimit_query);
2883 #endif
2884 
2885 	if_setcapabilities(ifp, T4_CAP);
2886 	if_setcapenable(ifp, T4_CAP_ENABLE);
2887 	if_sethwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
2888 	    CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2889 	if (chip_id(sc) >= CHELSIO_T6) {
2890 		if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
2891 		if_setcapenablebit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
2892 		if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP |
2893 		    CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2894 		    CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN, 0);
2895 	}
2896 
2897 #ifdef TCP_OFFLOAD
2898 	if (vi->nofldrxq != 0)
2899 		if_setcapabilitiesbit(ifp, IFCAP_TOE, 0);
2900 #endif
2901 #ifdef RATELIMIT
2902 	if (is_ethoffload(sc) && vi->nofldtxq != 0) {
2903 		if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0);
2904 		if_setcapenablebit(ifp, IFCAP_TXRTLMT, 0);
2905 	}
2906 #endif
2907 
2908 	if_sethwtsomax(ifp, IP_MAXPACKET);
2909 	if (vi->flags & TX_USES_VM_WR)
2910 		if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_VM_TSO);
2911 	else
2912 		if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_TSO);
2913 #ifdef RATELIMIT
2914 	if (is_ethoffload(sc) && vi->nofldtxq != 0)
2915 		if_sethwtsomaxsegcount(ifp, TX_SGL_SEGS_EO_TSO);
2916 #endif
2917 	if_sethwtsomaxsegsize(ifp, 65536);
2918 #ifdef KERN_TLS
2919 	if (is_ktls(sc)) {
2920 		if_setcapabilitiesbit(ifp, IFCAP_TXTLS, 0);
2921 		if (sc->flags & KERN_TLS_ON || !is_t6(sc))
2922 			if_setcapenablebit(ifp, IFCAP_TXTLS, 0);
2923 	}
2924 #endif
2925 
2926 	ether_ifattach(ifp, vi->hw_addr);
2927 #ifdef DEV_NETMAP
2928 	if (vi->nnmrxq != 0)
2929 		cxgbe_nm_attach(vi);
2930 #endif
2931 	sb = sbuf_new_auto();
2932 	sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
2933 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2934 	switch (if_getcapabilities(ifp) & (IFCAP_TOE | IFCAP_TXRTLMT)) {
2935 	case IFCAP_TOE:
2936 		sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
2937 		break;
2938 	case IFCAP_TOE | IFCAP_TXRTLMT:
2939 		sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
2940 		break;
2941 	case IFCAP_TXRTLMT:
2942 		sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
2943 		break;
2944 	}
2945 #endif
2946 #ifdef TCP_OFFLOAD
2947 	if (if_getcapabilities(ifp) & IFCAP_TOE)
2948 		sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
2949 #endif
2950 #ifdef DEV_NETMAP
2951 	if (if_getcapabilities(ifp) & IFCAP_NETMAP)
2952 		sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
2953 		    vi->nnmtxq, vi->nnmrxq);
2954 #endif
2955 	sbuf_finish(sb);
2956 	device_printf(dev, "%s\n", sbuf_data(sb));
2957 	sbuf_delete(sb);
2958 
2959 	vi_sysctls(vi);
2960 
2961 	pa.pa_version = PFIL_VERSION;
2962 	pa.pa_flags = PFIL_IN;
2963 	pa.pa_type = PFIL_TYPE_ETHERNET;
2964 	pa.pa_headname = if_name(ifp);
2965 	vi->pfil = pfil_head_register(&pa);
2966 }
2967 
2968 static int
2969 cxgbe_attach(device_t dev)
2970 {
2971 	struct port_info *pi = device_get_softc(dev);
2972 	struct adapter *sc = pi->adapter;
2973 	struct vi_info *vi;
2974 	int i;
2975 
2976 	sysctl_ctx_init(&pi->ctx);
2977 
2978 	cxgbe_vi_attach(dev, &pi->vi[0]);
2979 
2980 	for_each_vi(pi, i, vi) {
2981 		if (i == 0)
2982 			continue;
2983 		vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, DEVICE_UNIT_ANY);
2984 		if (vi->dev == NULL) {
2985 			device_printf(dev, "failed to add VI %d\n", i);
2986 			continue;
2987 		}
2988 		device_set_softc(vi->dev, vi);
2989 	}
2990 
2991 	cxgbe_sysctls(pi);
2992 
2993 	bus_attach_children(dev);
2994 
2995 	return (0);
2996 }
2997 
2998 static void
2999 cxgbe_vi_detach(struct vi_info *vi)
3000 {
3001 	if_t ifp = vi->ifp;
3002 
3003 	if (vi->pfil != NULL) {
3004 		pfil_head_unregister(vi->pfil);
3005 		vi->pfil = NULL;
3006 	}
3007 
3008 	ether_ifdetach(ifp);
3009 
3010 	/* Let detach proceed even if these fail. */
3011 #ifdef DEV_NETMAP
3012 	if (if_getcapabilities(ifp) & IFCAP_NETMAP)
3013 		cxgbe_nm_detach(vi);
3014 #endif
3015 	cxgbe_uninit_synchronized(vi);
3016 	callout_drain(&vi->tick);
3017 	mtx_destroy(&vi->tick_mtx);
3018 	sysctl_ctx_free(&vi->ctx);
3019 	vi_full_uninit(vi);
3020 
3021 	if_free(vi->ifp);
3022 	vi->ifp = NULL;
3023 }
3024 
3025 static int
3026 cxgbe_detach(device_t dev)
3027 {
3028 	struct port_info *pi = device_get_softc(dev);
3029 	struct adapter *sc = pi->adapter;
3030 	int rc;
3031 
3032 	/* Detach the extra VIs first. */
3033 	rc = bus_generic_detach(dev);
3034 	if (rc)
3035 		return (rc);
3036 
3037 	sysctl_ctx_free(&pi->ctx);
3038 	begin_vi_detach(sc, &pi->vi[0]);
3039 	if (pi->flags & HAS_TRACEQ) {
3040 		sc->traceq = -1;	/* cloner should not create ifnet */
3041 		t4_tracer_port_detach(sc);
3042 	}
3043 	cxgbe_vi_detach(&pi->vi[0]);
3044 	ifmedia_removeall(&pi->media);
3045 	end_vi_detach(sc, &pi->vi[0]);
3046 
3047 	return (0);
3048 }
3049 
3050 static void
3051 cxgbe_init(void *arg)
3052 {
3053 	struct vi_info *vi = arg;
3054 	struct adapter *sc = vi->adapter;
3055 
3056 	if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
3057 		return;
3058 	cxgbe_init_synchronized(vi);
3059 	end_synchronized_op(sc, 0);
3060 }
3061 
3062 static int
3063 cxgbe_ioctl(if_t ifp, unsigned long cmd, caddr_t data)
3064 {
3065 	int rc = 0, mtu, flags;
3066 	struct vi_info *vi = if_getsoftc(ifp);
3067 	struct port_info *pi = vi->pi;
3068 	struct adapter *sc = pi->adapter;
3069 	struct ifreq *ifr = (struct ifreq *)data;
3070 	uint32_t mask;
3071 
3072 	switch (cmd) {
3073 	case SIOCSIFMTU:
3074 		mtu = ifr->ifr_mtu;
3075 		if (mtu < ETHERMIN || mtu > MAX_MTU)
3076 			return (EINVAL);
3077 
3078 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
3079 		if (rc)
3080 			return (rc);
3081 		if_setmtu(ifp, mtu);
3082 		if (vi->flags & VI_INIT_DONE) {
3083 			t4_update_fl_bufsize(ifp);
3084 			if (hw_all_ok(sc) &&
3085 			    if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3086 				rc = update_mac_settings(ifp, XGMAC_MTU);
3087 		}
3088 		end_synchronized_op(sc, 0);
3089 		break;
3090 
3091 	case SIOCSIFFLAGS:
3092 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
3093 		if (rc)
3094 			return (rc);
3095 
3096 		if (!hw_all_ok(sc)) {
3097 			rc = ENXIO;
3098 			goto fail;
3099 		}
3100 
3101 		if (if_getflags(ifp) & IFF_UP) {
3102 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3103 				flags = vi->if_flags;
3104 				if ((if_getflags(ifp) ^ flags) &
3105 				    (IFF_PROMISC | IFF_ALLMULTI)) {
3106 					rc = update_mac_settings(ifp,
3107 					    XGMAC_PROMISC | XGMAC_ALLMULTI);
3108 				}
3109 			} else {
3110 				rc = cxgbe_init_synchronized(vi);
3111 			}
3112 			vi->if_flags = if_getflags(ifp);
3113 		} else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3114 			rc = cxgbe_uninit_synchronized(vi);
3115 		}
3116 		end_synchronized_op(sc, 0);
3117 		break;
3118 
3119 	case SIOCADDMULTI:
3120 	case SIOCDELMULTI:
3121 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
3122 		if (rc)
3123 			return (rc);
3124 		if (hw_all_ok(sc) && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3125 			rc = update_mac_settings(ifp, XGMAC_MCADDRS);
3126 		end_synchronized_op(sc, 0);
3127 		break;
3128 
3129 	case SIOCSIFCAP:
3130 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
3131 		if (rc)
3132 			return (rc);
3133 
3134 		mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3135 		if (mask & IFCAP_TXCSUM) {
3136 			if_togglecapenable(ifp, IFCAP_TXCSUM);
3137 			if_togglehwassist(ifp, CSUM_TCP | CSUM_UDP | CSUM_IP);
3138 
3139 			if (IFCAP_TSO4 & if_getcapenable(ifp) &&
3140 			    !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3141 				mask &= ~IFCAP_TSO4;
3142 				if_setcapenablebit(ifp, 0, IFCAP_TSO4);
3143 				if_printf(ifp,
3144 				    "tso4 disabled due to -txcsum.\n");
3145 			}
3146 		}
3147 		if (mask & IFCAP_TXCSUM_IPV6) {
3148 			if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
3149 			if_togglehwassist(ifp, CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3150 
3151 			if (IFCAP_TSO6 & if_getcapenable(ifp) &&
3152 			    !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3153 				mask &= ~IFCAP_TSO6;
3154 				if_setcapenablebit(ifp, 0, IFCAP_TSO6);
3155 				if_printf(ifp,
3156 				    "tso6 disabled due to -txcsum6.\n");
3157 			}
3158 		}
3159 		if (mask & IFCAP_RXCSUM)
3160 			if_togglecapenable(ifp, IFCAP_RXCSUM);
3161 		if (mask & IFCAP_RXCSUM_IPV6)
3162 			if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
3163 
3164 		/*
3165 		 * Note that we leave CSUM_TSO alone (it is always set).  The
3166 		 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
3167 		 * sending a TSO request our way, so it's sufficient to toggle
3168 		 * IFCAP_TSOx only.
3169 		 */
3170 		if (mask & IFCAP_TSO4) {
3171 			if (!(IFCAP_TSO4 & if_getcapenable(ifp)) &&
3172 			    !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3173 				if_printf(ifp, "enable txcsum first.\n");
3174 				rc = EAGAIN;
3175 				goto fail;
3176 			}
3177 			if_togglecapenable(ifp, IFCAP_TSO4);
3178 		}
3179 		if (mask & IFCAP_TSO6) {
3180 			if (!(IFCAP_TSO6 & if_getcapenable(ifp)) &&
3181 			    !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3182 				if_printf(ifp, "enable txcsum6 first.\n");
3183 				rc = EAGAIN;
3184 				goto fail;
3185 			}
3186 			if_togglecapenable(ifp, IFCAP_TSO6);
3187 		}
3188 		if (mask & IFCAP_LRO) {
3189 #if defined(INET) || defined(INET6)
3190 			int i;
3191 			struct sge_rxq *rxq;
3192 
3193 			if_togglecapenable(ifp, IFCAP_LRO);
3194 			for_each_rxq(vi, i, rxq) {
3195 				if (if_getcapenable(ifp) & IFCAP_LRO)
3196 					rxq->iq.flags |= IQ_LRO_ENABLED;
3197 				else
3198 					rxq->iq.flags &= ~IQ_LRO_ENABLED;
3199 			}
3200 #endif
3201 		}
3202 #ifdef TCP_OFFLOAD
3203 		if (mask & IFCAP_TOE) {
3204 			int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TOE;
3205 
3206 			rc = toe_capability(vi, enable);
3207 			if (rc != 0)
3208 				goto fail;
3209 
3210 			if_togglecapenable(ifp, mask);
3211 		}
3212 #endif
3213 		if (mask & IFCAP_VLAN_HWTAGGING) {
3214 			if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
3215 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3216 				rc = update_mac_settings(ifp, XGMAC_VLANEX);
3217 		}
3218 		if (mask & IFCAP_VLAN_MTU) {
3219 			if_togglecapenable(ifp, IFCAP_VLAN_MTU);
3220 
3221 			/* Need to find out how to disable auto-mtu-inflation */
3222 		}
3223 		if (mask & IFCAP_VLAN_HWTSO)
3224 			if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
3225 		if (mask & IFCAP_VLAN_HWCSUM)
3226 			if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
3227 #ifdef RATELIMIT
3228 		if (mask & IFCAP_TXRTLMT)
3229 			if_togglecapenable(ifp, IFCAP_TXRTLMT);
3230 #endif
3231 		if (mask & IFCAP_HWRXTSTMP) {
3232 			int i;
3233 			struct sge_rxq *rxq;
3234 
3235 			if_togglecapenable(ifp, IFCAP_HWRXTSTMP);
3236 			for_each_rxq(vi, i, rxq) {
3237 				if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP)
3238 					rxq->iq.flags |= IQ_RX_TIMESTAMP;
3239 				else
3240 					rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
3241 			}
3242 		}
3243 		if (mask & IFCAP_MEXTPG)
3244 			if_togglecapenable(ifp, IFCAP_MEXTPG);
3245 
3246 #ifdef KERN_TLS
3247 		if (mask & IFCAP_TXTLS) {
3248 			int enable = (if_getcapenable(ifp) ^ mask) & IFCAP_TXTLS;
3249 
3250 			rc = ktls_capability(sc, enable);
3251 			if (rc != 0)
3252 				goto fail;
3253 
3254 			if_togglecapenable(ifp, mask & IFCAP_TXTLS);
3255 		}
3256 #endif
3257 		if (mask & IFCAP_VXLAN_HWCSUM) {
3258 			if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM);
3259 			if_togglehwassist(ifp, CSUM_INNER_IP6_UDP |
3260 			    CSUM_INNER_IP6_TCP | CSUM_INNER_IP |
3261 			    CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP);
3262 		}
3263 		if (mask & IFCAP_VXLAN_HWTSO) {
3264 			if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO);
3265 			if_togglehwassist(ifp, CSUM_INNER_IP6_TSO |
3266 			    CSUM_INNER_IP_TSO);
3267 		}
3268 
3269 #ifdef VLAN_CAPABILITIES
3270 		VLAN_CAPABILITIES(ifp);
3271 #endif
3272 fail:
3273 		end_synchronized_op(sc, 0);
3274 		break;
3275 
3276 	case SIOCSIFMEDIA:
3277 	case SIOCGIFMEDIA:
3278 	case SIOCGIFXMEDIA:
3279 		rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
3280 		break;
3281 
3282 	case SIOCGI2C: {
3283 		struct ifi2creq i2c;
3284 
3285 		rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3286 		if (rc != 0)
3287 			break;
3288 		if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3289 			rc = EPERM;
3290 			break;
3291 		}
3292 		if (i2c.len > sizeof(i2c.data)) {
3293 			rc = EINVAL;
3294 			break;
3295 		}
3296 		rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
3297 		if (rc)
3298 			return (rc);
3299 		if (!hw_all_ok(sc))
3300 			rc = ENXIO;
3301 		else
3302 			rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
3303 			    i2c.offset, i2c.len, &i2c.data[0]);
3304 		end_synchronized_op(sc, 0);
3305 		if (rc == 0)
3306 			rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3307 		break;
3308 	}
3309 
3310 	default:
3311 		rc = ether_ioctl(ifp, cmd, data);
3312 	}
3313 
3314 	return (rc);
3315 }
3316 
3317 static int
3318 cxgbe_transmit(if_t ifp, struct mbuf *m)
3319 {
3320 	struct vi_info *vi = if_getsoftc(ifp);
3321 	struct port_info *pi = vi->pi;
3322 	struct adapter *sc;
3323 	struct sge_txq *txq;
3324 	void *items[1];
3325 	int rc;
3326 
3327 	M_ASSERTPKTHDR(m);
3328 	MPASS(m->m_nextpkt == NULL);	/* not quite ready for this yet */
3329 #if defined(KERN_TLS) || defined(RATELIMIT)
3330 	if (m->m_pkthdr.csum_flags & CSUM_SND_TAG)
3331 		MPASS(m->m_pkthdr.snd_tag->ifp == ifp);
3332 #endif
3333 
3334 	if (__predict_false(pi->link_cfg.link_ok == false)) {
3335 		m_freem(m);
3336 		return (ENETDOWN);
3337 	}
3338 
3339 	rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR);
3340 	if (__predict_false(rc != 0)) {
3341 		if (__predict_true(rc == EINPROGRESS)) {
3342 			/* queued by parse_pkt */
3343 			MPASS(m != NULL);
3344 			return (0);
3345 		}
3346 
3347 		MPASS(m == NULL);			/* was freed already */
3348 		atomic_add_int(&pi->tx_parse_error, 1);	/* rare, atomic is ok */
3349 		return (rc);
3350 	}
3351 
3352 	/* Select a txq. */
3353 	sc = vi->adapter;
3354 	txq = &sc->sge.txq[vi->first_txq];
3355 	if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
3356 		txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
3357 		    vi->rsrv_noflowq);
3358 
3359 	items[0] = m;
3360 	rc = mp_ring_enqueue(txq->r, items, 1, 256);
3361 	if (__predict_false(rc != 0))
3362 		m_freem(m);
3363 
3364 	return (rc);
3365 }
3366 
3367 static void
3368 cxgbe_qflush(if_t ifp)
3369 {
3370 	struct vi_info *vi = if_getsoftc(ifp);
3371 	struct sge_txq *txq;
3372 	int i;
3373 
3374 	/* queues do not exist if !VI_INIT_DONE. */
3375 	if (vi->flags & VI_INIT_DONE) {
3376 		for_each_txq(vi, i, txq) {
3377 			TXQ_LOCK(txq);
3378 			txq->eq.flags |= EQ_QFLUSH;
3379 			TXQ_UNLOCK(txq);
3380 			while (!mp_ring_is_idle(txq->r)) {
3381 				mp_ring_check_drainage(txq->r, 4096);
3382 				pause("qflush", 1);
3383 			}
3384 			TXQ_LOCK(txq);
3385 			txq->eq.flags &= ~EQ_QFLUSH;
3386 			TXQ_UNLOCK(txq);
3387 		}
3388 	}
3389 	if_qflush(ifp);
3390 }
3391 
3392 static uint64_t
3393 vi_get_counter(if_t ifp, ift_counter c)
3394 {
3395 	struct vi_info *vi = if_getsoftc(ifp);
3396 	struct fw_vi_stats_vf *s = &vi->stats;
3397 
3398 	mtx_lock(&vi->tick_mtx);
3399 	vi_refresh_stats(vi);
3400 	mtx_unlock(&vi->tick_mtx);
3401 
3402 	switch (c) {
3403 	case IFCOUNTER_IPACKETS:
3404 		return (s->rx_bcast_frames + s->rx_mcast_frames +
3405 		    s->rx_ucast_frames);
3406 	case IFCOUNTER_IERRORS:
3407 		return (s->rx_err_frames);
3408 	case IFCOUNTER_OPACKETS:
3409 		return (s->tx_bcast_frames + s->tx_mcast_frames +
3410 		    s->tx_ucast_frames + s->tx_offload_frames);
3411 	case IFCOUNTER_OERRORS:
3412 		return (s->tx_drop_frames);
3413 	case IFCOUNTER_IBYTES:
3414 		return (s->rx_bcast_bytes + s->rx_mcast_bytes +
3415 		    s->rx_ucast_bytes);
3416 	case IFCOUNTER_OBYTES:
3417 		return (s->tx_bcast_bytes + s->tx_mcast_bytes +
3418 		    s->tx_ucast_bytes + s->tx_offload_bytes);
3419 	case IFCOUNTER_IMCASTS:
3420 		return (s->rx_mcast_frames);
3421 	case IFCOUNTER_OMCASTS:
3422 		return (s->tx_mcast_frames);
3423 	case IFCOUNTER_OQDROPS: {
3424 		uint64_t drops;
3425 
3426 		drops = 0;
3427 		if (vi->flags & VI_INIT_DONE) {
3428 			int i;
3429 			struct sge_txq *txq;
3430 
3431 			for_each_txq(vi, i, txq)
3432 				drops += counter_u64_fetch(txq->r->dropped);
3433 		}
3434 
3435 		return (drops);
3436 
3437 	}
3438 
3439 	default:
3440 		return (if_get_counter_default(ifp, c));
3441 	}
3442 }
3443 
3444 static uint64_t
3445 cxgbe_get_counter(if_t ifp, ift_counter c)
3446 {
3447 	struct vi_info *vi = if_getsoftc(ifp);
3448 	struct port_info *pi = vi->pi;
3449 	struct port_stats *s = &pi->stats;
3450 
3451 	mtx_lock(&vi->tick_mtx);
3452 	cxgbe_refresh_stats(vi);
3453 	mtx_unlock(&vi->tick_mtx);
3454 
3455 	switch (c) {
3456 	case IFCOUNTER_IPACKETS:
3457 		return (s->rx_frames);
3458 
3459 	case IFCOUNTER_IERRORS:
3460 		return (s->rx_jabber + s->rx_runt + s->rx_too_long +
3461 		    s->rx_fcs_err + s->rx_len_err);
3462 
3463 	case IFCOUNTER_OPACKETS:
3464 		return (s->tx_frames);
3465 
3466 	case IFCOUNTER_OERRORS:
3467 		return (s->tx_error_frames);
3468 
3469 	case IFCOUNTER_IBYTES:
3470 		return (s->rx_octets);
3471 
3472 	case IFCOUNTER_OBYTES:
3473 		return (s->tx_octets);
3474 
3475 	case IFCOUNTER_IMCASTS:
3476 		return (s->rx_mcast_frames);
3477 
3478 	case IFCOUNTER_OMCASTS:
3479 		return (s->tx_mcast_frames);
3480 
3481 	case IFCOUNTER_IQDROPS:
3482 		return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
3483 		    s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
3484 		    s->rx_trunc3 + pi->tnl_cong_drops);
3485 
3486 	case IFCOUNTER_OQDROPS: {
3487 		uint64_t drops;
3488 
3489 		drops = s->tx_drop;
3490 		if (vi->flags & VI_INIT_DONE) {
3491 			int i;
3492 			struct sge_txq *txq;
3493 
3494 			for_each_txq(vi, i, txq)
3495 				drops += counter_u64_fetch(txq->r->dropped);
3496 		}
3497 
3498 		return (drops);
3499 
3500 	}
3501 
3502 	default:
3503 		return (if_get_counter_default(ifp, c));
3504 	}
3505 }
3506 
3507 #if defined(KERN_TLS) || defined(RATELIMIT)
3508 static int
3509 cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params,
3510     struct m_snd_tag **pt)
3511 {
3512 	int error;
3513 
3514 	switch (params->hdr.type) {
3515 #ifdef RATELIMIT
3516 	case IF_SND_TAG_TYPE_RATE_LIMIT:
3517 		error = cxgbe_rate_tag_alloc(ifp, params, pt);
3518 		break;
3519 #endif
3520 #ifdef KERN_TLS
3521 	case IF_SND_TAG_TYPE_TLS:
3522 	{
3523 		struct vi_info *vi = if_getsoftc(ifp);
3524 
3525 		if (is_t6(vi->pi->adapter))
3526 			error = t6_tls_tag_alloc(ifp, params, pt);
3527 		else
3528 			error = t7_tls_tag_alloc(ifp, params, pt);
3529 		break;
3530 	}
3531 #endif
3532 	default:
3533 		error = EOPNOTSUPP;
3534 	}
3535 	return (error);
3536 }
3537 #endif
3538 
3539 /*
3540  * The kernel picks a media from the list we had provided but we still validate
3541  * the requeste.
3542  */
3543 int
3544 cxgbe_media_change(if_t ifp)
3545 {
3546 	struct vi_info *vi = if_getsoftc(ifp);
3547 	struct port_info *pi = vi->pi;
3548 	struct ifmedia *ifm = &pi->media;
3549 	struct link_config *lc = &pi->link_cfg;
3550 	struct adapter *sc = pi->adapter;
3551 	int rc;
3552 
3553 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
3554 	if (rc != 0)
3555 		return (rc);
3556 	PORT_LOCK(pi);
3557 	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
3558 		/* ifconfig .. media autoselect */
3559 		if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
3560 			rc = ENOTSUP; /* AN not supported by transceiver */
3561 			goto done;
3562 		}
3563 		lc->requested_aneg = AUTONEG_ENABLE;
3564 		lc->requested_speed = 0;
3565 		lc->requested_fc |= PAUSE_AUTONEG;
3566 	} else {
3567 		lc->requested_aneg = AUTONEG_DISABLE;
3568 		lc->requested_speed =
3569 		    ifmedia_baudrate(ifm->ifm_media) / 1000000;
3570 		lc->requested_fc = 0;
3571 		if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
3572 			lc->requested_fc |= PAUSE_RX;
3573 		if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
3574 			lc->requested_fc |= PAUSE_TX;
3575 	}
3576 	if (pi->up_vis > 0 && hw_all_ok(sc)) {
3577 		fixup_link_config(pi);
3578 		rc = apply_link_config(pi);
3579 	}
3580 done:
3581 	PORT_UNLOCK(pi);
3582 	end_synchronized_op(sc, 0);
3583 	return (rc);
3584 }
3585 
3586 /*
3587  * Base media word (without ETHER, pause, link active, etc.) for the port at the
3588  * given speed.
3589  */
3590 static int
3591 port_mword(struct port_info *pi, uint32_t speed)
3592 {
3593 
3594 	MPASS(speed & M_FW_PORT_CAP32_SPEED);
3595 	MPASS(powerof2(speed));
3596 
3597 	switch(pi->port_type) {
3598 	case FW_PORT_TYPE_BT_SGMII:
3599 	case FW_PORT_TYPE_BT_XFI:
3600 	case FW_PORT_TYPE_BT_XAUI:
3601 		/* BaseT */
3602 		switch (speed) {
3603 		case FW_PORT_CAP32_SPEED_100M:
3604 			return (IFM_100_T);
3605 		case FW_PORT_CAP32_SPEED_1G:
3606 			return (IFM_1000_T);
3607 		case FW_PORT_CAP32_SPEED_10G:
3608 			return (IFM_10G_T);
3609 		}
3610 		break;
3611 	case FW_PORT_TYPE_KX4:
3612 		if (speed == FW_PORT_CAP32_SPEED_10G)
3613 			return (IFM_10G_KX4);
3614 		break;
3615 	case FW_PORT_TYPE_CX4:
3616 		if (speed == FW_PORT_CAP32_SPEED_10G)
3617 			return (IFM_10G_CX4);
3618 		break;
3619 	case FW_PORT_TYPE_KX:
3620 		if (speed == FW_PORT_CAP32_SPEED_1G)
3621 			return (IFM_1000_KX);
3622 		break;
3623 	case FW_PORT_TYPE_KR:
3624 	case FW_PORT_TYPE_BP_AP:
3625 	case FW_PORT_TYPE_BP4_AP:
3626 	case FW_PORT_TYPE_BP40_BA:
3627 	case FW_PORT_TYPE_KR4_100G:
3628 	case FW_PORT_TYPE_KR_SFP28:
3629 	case FW_PORT_TYPE_KR_XLAUI:
3630 		switch (speed) {
3631 		case FW_PORT_CAP32_SPEED_1G:
3632 			return (IFM_1000_KX);
3633 		case FW_PORT_CAP32_SPEED_10G:
3634 			return (IFM_10G_KR);
3635 		case FW_PORT_CAP32_SPEED_25G:
3636 			return (IFM_25G_KR);
3637 		case FW_PORT_CAP32_SPEED_40G:
3638 			return (IFM_40G_KR4);
3639 		case FW_PORT_CAP32_SPEED_50G:
3640 			return (IFM_50G_KR2);
3641 		case FW_PORT_CAP32_SPEED_100G:
3642 			return (IFM_100G_KR4);
3643 		}
3644 		break;
3645 	case FW_PORT_TYPE_FIBER_XFI:
3646 	case FW_PORT_TYPE_FIBER_XAUI:
3647 	case FW_PORT_TYPE_SFP:
3648 	case FW_PORT_TYPE_QSFP_10G:
3649 	case FW_PORT_TYPE_QSA:
3650 	case FW_PORT_TYPE_QSFP:
3651 	case FW_PORT_TYPE_CR4_QSFP:
3652 	case FW_PORT_TYPE_CR_QSFP:
3653 	case FW_PORT_TYPE_CR2_QSFP:
3654 	case FW_PORT_TYPE_SFP28:
3655 	case FW_PORT_TYPE_SFP56:
3656 	case FW_PORT_TYPE_QSFP56:
3657 	case FW_PORT_TYPE_QSFPDD:
3658 		/* Pluggable transceiver */
3659 		switch (pi->mod_type) {
3660 		case FW_PORT_MOD_TYPE_LR:
3661 		case FW_PORT_MOD_TYPE_LR_SIMPLEX:
3662 			switch (speed) {
3663 			case FW_PORT_CAP32_SPEED_1G:
3664 				return (IFM_1000_LX);
3665 			case FW_PORT_CAP32_SPEED_10G:
3666 				return (IFM_10G_LR);
3667 			case FW_PORT_CAP32_SPEED_25G:
3668 				return (IFM_25G_LR);
3669 			case FW_PORT_CAP32_SPEED_40G:
3670 				return (IFM_40G_LR4);
3671 			case FW_PORT_CAP32_SPEED_50G:
3672 				return (IFM_50G_LR2);
3673 			case FW_PORT_CAP32_SPEED_100G:
3674 				return (IFM_100G_LR4);
3675 			case FW_PORT_CAP32_SPEED_200G:
3676 				return (IFM_200G_LR4);
3677 			case FW_PORT_CAP32_SPEED_400G:
3678 				return (IFM_400G_LR8);
3679 			}
3680 			break;
3681 		case FW_PORT_MOD_TYPE_SR:
3682 			switch (speed) {
3683 			case FW_PORT_CAP32_SPEED_1G:
3684 				return (IFM_1000_SX);
3685 			case FW_PORT_CAP32_SPEED_10G:
3686 				return (IFM_10G_SR);
3687 			case FW_PORT_CAP32_SPEED_25G:
3688 				return (IFM_25G_SR);
3689 			case FW_PORT_CAP32_SPEED_40G:
3690 				return (IFM_40G_SR4);
3691 			case FW_PORT_CAP32_SPEED_50G:
3692 				return (IFM_50G_SR2);
3693 			case FW_PORT_CAP32_SPEED_100G:
3694 				return (IFM_100G_SR4);
3695 			case FW_PORT_CAP32_SPEED_200G:
3696 				return (IFM_200G_SR4);
3697 			case FW_PORT_CAP32_SPEED_400G:
3698 				return (IFM_400G_SR8);
3699 			}
3700 			break;
3701 		case FW_PORT_MOD_TYPE_ER:
3702 			if (speed == FW_PORT_CAP32_SPEED_10G)
3703 				return (IFM_10G_ER);
3704 			break;
3705 		case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3706 		case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3707 			switch (speed) {
3708 			case FW_PORT_CAP32_SPEED_1G:
3709 				return (IFM_1000_CX);
3710 			case FW_PORT_CAP32_SPEED_10G:
3711 				return (IFM_10G_TWINAX);
3712 			case FW_PORT_CAP32_SPEED_25G:
3713 				return (IFM_25G_CR);
3714 			case FW_PORT_CAP32_SPEED_40G:
3715 				return (IFM_40G_CR4);
3716 			case FW_PORT_CAP32_SPEED_50G:
3717 				return (IFM_50G_CR2);
3718 			case FW_PORT_CAP32_SPEED_100G:
3719 				return (IFM_100G_CR4);
3720 			case FW_PORT_CAP32_SPEED_200G:
3721 				return (IFM_200G_CR4_PAM4);
3722 			case FW_PORT_CAP32_SPEED_400G:
3723 				return (IFM_400G_CR8);
3724 			}
3725 			break;
3726 		case FW_PORT_MOD_TYPE_LRM:
3727 			if (speed == FW_PORT_CAP32_SPEED_10G)
3728 				return (IFM_10G_LRM);
3729 			break;
3730 		case FW_PORT_MOD_TYPE_DR:
3731 			if (speed == FW_PORT_CAP32_SPEED_100G)
3732 				return (IFM_100G_DR);
3733 			if (speed == FW_PORT_CAP32_SPEED_200G)
3734 				return (IFM_200G_DR4);
3735 			if (speed == FW_PORT_CAP32_SPEED_400G)
3736 				return (IFM_400G_DR4);
3737 			break;
3738 		case FW_PORT_MOD_TYPE_NA:
3739 			MPASS(0);	/* Not pluggable? */
3740 			/* fall through */
3741 		case FW_PORT_MOD_TYPE_ERROR:
3742 		case FW_PORT_MOD_TYPE_UNKNOWN:
3743 		case FW_PORT_MOD_TYPE_NOTSUPPORTED:
3744 			break;
3745 		case FW_PORT_MOD_TYPE_NONE:
3746 			return (IFM_NONE);
3747 		}
3748 		break;
3749 	case M_FW_PORT_CMD_PTYPE:	/* FW_PORT_TYPE_NONE for old firmware */
3750 		if (chip_id(pi->adapter) >= CHELSIO_T7)
3751 			return (IFM_UNKNOWN);
3752 		/* fall through */
3753 	case FW_PORT_TYPE_NONE:
3754 		return (IFM_NONE);
3755 	}
3756 
3757 	return (IFM_UNKNOWN);
3758 }
3759 
3760 void
3761 cxgbe_media_status(if_t ifp, struct ifmediareq *ifmr)
3762 {
3763 	struct vi_info *vi = if_getsoftc(ifp);
3764 	struct port_info *pi = vi->pi;
3765 	struct adapter *sc = pi->adapter;
3766 	struct link_config *lc = &pi->link_cfg;
3767 
3768 	if (begin_synchronized_op(sc, vi , SLEEP_OK | INTR_OK, "t4med") != 0)
3769 		return;
3770 	PORT_LOCK(pi);
3771 
3772 	if (pi->up_vis == 0 && hw_all_ok(sc)) {
3773 		/*
3774 		 * If all the interfaces are administratively down the firmware
3775 		 * does not report transceiver changes.  Refresh port info here
3776 		 * so that ifconfig displays accurate ifmedia at all times.
3777 		 * This is the only reason we have a synchronized op in this
3778 		 * function.  Just PORT_LOCK would have been enough otherwise.
3779 		 */
3780 		t4_update_port_info(pi);
3781 		build_medialist(pi);
3782 	}
3783 
3784 	/* ifm_status */
3785 	ifmr->ifm_status = IFM_AVALID;
3786 	if (lc->link_ok == false)
3787 		goto done;
3788 	ifmr->ifm_status |= IFM_ACTIVE;
3789 
3790 	/* ifm_active */
3791 	ifmr->ifm_active = IFM_ETHER | IFM_FDX;
3792 	ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
3793 	if (lc->fc & PAUSE_RX)
3794 		ifmr->ifm_active |= IFM_ETH_RXPAUSE;
3795 	if (lc->fc & PAUSE_TX)
3796 		ifmr->ifm_active |= IFM_ETH_TXPAUSE;
3797 	ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
3798 done:
3799 	PORT_UNLOCK(pi);
3800 	end_synchronized_op(sc, 0);
3801 }
3802 
3803 static int
3804 vcxgbe_probe(device_t dev)
3805 {
3806 	struct vi_info *vi = device_get_softc(dev);
3807 
3808 	device_set_descf(dev, "port %d vi %td", vi->pi->port_id,
3809 	    vi - vi->pi->vi);
3810 
3811 	return (BUS_PROBE_DEFAULT);
3812 }
3813 
3814 static int
3815 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
3816 {
3817 	int func, index, rc;
3818 	uint32_t param, val;
3819 
3820 	ASSERT_SYNCHRONIZED_OP(sc);
3821 
3822 	index = vi - pi->vi;
3823 	MPASS(index > 0);	/* This function deals with _extra_ VIs only */
3824 	KASSERT(index < nitems(vi_mac_funcs),
3825 	    ("%s: VI %s doesn't have a MAC func", __func__,
3826 	    device_get_nameunit(vi->dev)));
3827 	func = vi_mac_funcs[index];
3828 	rc = t4_alloc_vi_func(sc, sc->mbox, pi->hw_port, sc->pf, 0, 1,
3829 	    vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
3830 	if (rc < 0) {
3831 		CH_ERR(vi, "failed to allocate virtual interface %d"
3832 		    "for port %d: %d\n", index, pi->port_id, -rc);
3833 		return (-rc);
3834 	}
3835 	vi->viid = rc;
3836 
3837 	if (vi->rss_size == 1) {
3838 		/*
3839 		 * This VI didn't get a slice of the RSS table.  Reduce the
3840 		 * number of VIs being created (hw.cxgbe.num_vis) or modify the
3841 		 * configuration file (nvi, rssnvi for this PF) if this is a
3842 		 * problem.
3843 		 */
3844 		device_printf(vi->dev, "RSS table not available.\n");
3845 		vi->rss_base = 0xffff;
3846 
3847 		return (0);
3848 	}
3849 
3850 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3851 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
3852 	    V_FW_PARAMS_PARAM_YZ(vi->viid);
3853 	rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
3854 	if (rc)
3855 		vi->rss_base = 0xffff;
3856 	else {
3857 		MPASS((val >> 16) == vi->rss_size);
3858 		vi->rss_base = val & 0xffff;
3859 	}
3860 
3861 	return (0);
3862 }
3863 
3864 static int
3865 vcxgbe_attach(device_t dev)
3866 {
3867 	struct vi_info *vi;
3868 	struct port_info *pi;
3869 	struct adapter *sc;
3870 	int rc;
3871 
3872 	vi = device_get_softc(dev);
3873 	pi = vi->pi;
3874 	sc = pi->adapter;
3875 
3876 	rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
3877 	if (rc)
3878 		return (rc);
3879 	rc = alloc_extra_vi(sc, pi, vi);
3880 	end_synchronized_op(sc, 0);
3881 	if (rc)
3882 		return (rc);
3883 
3884 	cxgbe_vi_attach(dev, vi);
3885 
3886 	return (0);
3887 }
3888 
3889 static int
3890 vcxgbe_detach(device_t dev)
3891 {
3892 	struct vi_info *vi;
3893 	struct adapter *sc;
3894 
3895 	vi = device_get_softc(dev);
3896 	sc = vi->adapter;
3897 
3898 	begin_vi_detach(sc, vi);
3899 	cxgbe_vi_detach(vi);
3900 	t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
3901 	end_vi_detach(sc, vi);
3902 
3903 	return (0);
3904 }
3905 
3906 static struct callout fatal_callout;
3907 static struct taskqueue *reset_tq;
3908 
3909 static void
3910 delayed_panic(void *arg)
3911 {
3912 	struct adapter *sc = arg;
3913 
3914 	panic("%s: panic on fatal error", device_get_nameunit(sc->dev));
3915 }
3916 
3917 static void
3918 fatal_error_task(void *arg, int pending)
3919 {
3920 	struct adapter *sc = arg;
3921 	int rc;
3922 
3923 	if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) {
3924 		dump_cim_regs(sc);
3925 		dump_cimla(sc);
3926 		dump_devlog(sc);
3927 	}
3928 
3929 	if (t4_reset_on_fatal_err) {
3930 		CH_ALERT(sc, "resetting adapter after fatal error.\n");
3931 		rc = reset_adapter(sc);
3932 		if (rc == 0 && t4_panic_on_fatal_err) {
3933 			CH_ALERT(sc, "reset was successful, "
3934 			    "system will NOT panic.\n");
3935 			return;
3936 		}
3937 	}
3938 
3939 	if (t4_panic_on_fatal_err) {
3940 		CH_ALERT(sc, "panicking on fatal error (after 30s).\n");
3941 		callout_reset(&fatal_callout, hz * 30, delayed_panic, sc);
3942 	}
3943 }
3944 
3945 void
3946 t4_fatal_err(struct adapter *sc, bool fw_error)
3947 {
3948 	stop_adapter(sc);
3949 	if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR)))
3950 		return;
3951 	if (fw_error) {
3952 		/*
3953 		 * We are here because of a firmware error/timeout and not
3954 		 * because of a hardware interrupt.  It is possible (although
3955 		 * not very likely) that an error interrupt was also raised but
3956 		 * this thread ran first and inhibited t4_intr_err.  We walk the
3957 		 * main INT_CAUSE registers here to make sure we haven't missed
3958 		 * anything interesting.
3959 		 */
3960 		t4_slow_intr_handler(sc, sc->intr_flags);
3961 		atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
3962 	}
3963 	t4_report_fw_error(sc);
3964 	log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n",
3965 	    device_get_nameunit(sc->dev), fw_error);
3966 	taskqueue_enqueue(reset_tq, &sc->fatal_error_task);
3967 }
3968 
3969 void
3970 t4_add_adapter(struct adapter *sc)
3971 {
3972 	sx_xlock(&t4_list_lock);
3973 	SLIST_INSERT_HEAD(&t4_list, sc, link);
3974 	sx_xunlock(&t4_list_lock);
3975 }
3976 
3977 int
3978 t4_map_bars_0_and_4(struct adapter *sc)
3979 {
3980 	sc->regs_rid = PCIR_BAR(0);
3981 	sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3982 	    &sc->regs_rid, RF_ACTIVE);
3983 	if (sc->regs_res == NULL) {
3984 		device_printf(sc->dev, "cannot map registers.\n");
3985 		return (ENXIO);
3986 	}
3987 	sc->bt = rman_get_bustag(sc->regs_res);
3988 	sc->bh = rman_get_bushandle(sc->regs_res);
3989 	sc->mmio_len = rman_get_size(sc->regs_res);
3990 	setbit(&sc->doorbells, DOORBELL_KDB);
3991 
3992 	sc->msix_rid = PCIR_BAR(4);
3993 	sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3994 	    &sc->msix_rid, RF_ACTIVE);
3995 	if (sc->msix_res == NULL) {
3996 		device_printf(sc->dev, "cannot map MSI-X BAR.\n");
3997 		return (ENXIO);
3998 	}
3999 
4000 	return (0);
4001 }
4002 
4003 int
4004 t4_map_bar_2(struct adapter *sc)
4005 {
4006 
4007 	/*
4008 	 * T4: only iWARP driver uses the userspace doorbells.  There is no need
4009 	 * to map it if RDMA is disabled.
4010 	 */
4011 	if (is_t4(sc) && sc->rdmacaps == 0)
4012 		return (0);
4013 
4014 	sc->udbs_rid = PCIR_BAR(2);
4015 	sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4016 	    &sc->udbs_rid, RF_ACTIVE);
4017 	if (sc->udbs_res == NULL) {
4018 		device_printf(sc->dev, "cannot map doorbell BAR.\n");
4019 		return (ENXIO);
4020 	}
4021 	sc->udbs_base = rman_get_virtual(sc->udbs_res);
4022 
4023 	if (chip_id(sc) >= CHELSIO_T5) {
4024 		setbit(&sc->doorbells, DOORBELL_UDB);
4025 #if defined(__i386__) || defined(__amd64__)
4026 		if (t5_write_combine) {
4027 			int rc, mode;
4028 
4029 			/*
4030 			 * Enable write combining on BAR2.  This is the
4031 			 * userspace doorbell BAR and is split into 128B
4032 			 * (UDBS_SEG_SIZE) doorbell regions, each associated
4033 			 * with an egress queue.  The first 64B has the doorbell
4034 			 * and the second 64B can be used to submit a tx work
4035 			 * request with an implicit doorbell.
4036 			 */
4037 
4038 			rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
4039 			    rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
4040 			if (rc == 0) {
4041 				clrbit(&sc->doorbells, DOORBELL_UDB);
4042 				setbit(&sc->doorbells, DOORBELL_WCWR);
4043 				setbit(&sc->doorbells, DOORBELL_UDBWC);
4044 			} else {
4045 				device_printf(sc->dev,
4046 				    "couldn't enable write combining: %d\n",
4047 				    rc);
4048 			}
4049 
4050 			mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
4051 			t4_write_reg(sc, A_SGE_STAT_CFG,
4052 			    V_STATSOURCE_T5(7) | mode);
4053 		}
4054 #endif
4055 	}
4056 	sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
4057 
4058 	return (0);
4059 }
4060 
4061 int
4062 t4_adj_doorbells(struct adapter *sc)
4063 {
4064 	if ((sc->doorbells & t4_doorbells_allowed) != 0) {
4065 		sc->doorbells &= t4_doorbells_allowed;
4066 		return (0);
4067 	}
4068 	CH_ERR(sc, "No usable doorbell (available = 0x%x, allowed = 0x%x).\n",
4069 	       sc->doorbells, t4_doorbells_allowed);
4070 	return (EINVAL);
4071 }
4072 
4073 struct memwin_init {
4074 	uint32_t base;
4075 	uint32_t aperture;
4076 };
4077 
4078 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
4079 	{ MEMWIN0_BASE, MEMWIN0_APERTURE },
4080 	{ MEMWIN1_BASE, MEMWIN1_APERTURE },
4081 	{ MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
4082 };
4083 
4084 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
4085 	{ MEMWIN0_BASE, MEMWIN0_APERTURE },
4086 	{ MEMWIN1_BASE, MEMWIN1_APERTURE },
4087 	{ MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
4088 };
4089 
4090 static void
4091 setup_memwin(struct adapter *sc)
4092 {
4093 	const struct memwin_init *mw_init;
4094 	struct memwin *mw;
4095 	int i;
4096 	uint32_t bar0, reg;
4097 
4098 	if (is_t4(sc)) {
4099 		/*
4100 		 * Read low 32b of bar0 indirectly via the hardware backdoor
4101 		 * mechanism.  Works from within PCI passthrough environments
4102 		 * too, where rman_get_start() can return a different value.  We
4103 		 * need to program the T4 memory window decoders with the actual
4104 		 * addresses that will be coming across the PCIe link.
4105 		 */
4106 		bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
4107 		bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
4108 
4109 		mw_init = &t4_memwin[0];
4110 	} else {
4111 		/* T5+ use the relative offset inside the PCIe BAR */
4112 		bar0 = 0;
4113 
4114 		mw_init = &t5_memwin[0];
4115 	}
4116 
4117 	for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
4118 		if (!rw_initialized(&mw->mw_lock)) {
4119 			rw_init(&mw->mw_lock, "memory window access");
4120 			mw->mw_base = mw_init->base;
4121 			mw->mw_aperture = mw_init->aperture;
4122 			mw->mw_curpos = 0;
4123 		}
4124 		reg = chip_id(sc) > CHELSIO_T6 ?
4125 		    PCIE_MEM_ACCESS_T7_REG(A_T7_PCIE_MEM_ACCESS_BASE_WIN, i) :
4126 		    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i);
4127 		t4_write_reg(sc, reg, (mw->mw_base + bar0) | V_BIR(0) |
4128 		    V_WINDOW(ilog2(mw->mw_aperture) - 10));
4129 		rw_wlock(&mw->mw_lock);
4130 		position_memwin(sc, i, mw->mw_curpos);
4131 		rw_wunlock(&mw->mw_lock);
4132 	}
4133 
4134 	/* flush */
4135 	t4_read_reg(sc, reg);
4136 }
4137 
4138 /*
4139  * Positions the memory window at the given address in the card's address space.
4140  * There are some alignment requirements and the actual position may be at an
4141  * address prior to the requested address.  mw->mw_curpos always has the actual
4142  * position of the window.
4143  */
4144 static void
4145 position_memwin(struct adapter *sc, int idx, uint32_t addr)
4146 {
4147 	struct memwin *mw;
4148 	uint32_t pf, reg, val;
4149 
4150 	MPASS(idx >= 0 && idx < NUM_MEMWIN);
4151 	mw = &sc->memwin[idx];
4152 	rw_assert(&mw->mw_lock, RA_WLOCKED);
4153 
4154 	if (is_t4(sc)) {
4155 		pf = 0;
4156 		mw->mw_curpos = addr & ~0xf;	/* start must be 16B aligned */
4157 	} else {
4158 		pf = V_PFNUM(sc->pf);
4159 		mw->mw_curpos = addr & ~0x7f;	/* start must be 128B aligned */
4160 	}
4161 	if (chip_id(sc) > CHELSIO_T6) {
4162 		reg = PCIE_MEM_ACCESS_T7_REG(A_PCIE_MEM_ACCESS_OFFSET0, idx);
4163 		val = (mw->mw_curpos >> X_T7_MEMOFST_SHIFT) | pf;
4164 	} else {
4165 		reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
4166 		val = mw->mw_curpos | pf;
4167 	}
4168 	t4_write_reg(sc, reg, val);
4169 	t4_read_reg(sc, reg);	/* flush */
4170 }
4171 
4172 int
4173 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
4174     int len, int rw)
4175 {
4176 	struct memwin *mw;
4177 	uint32_t mw_end, v;
4178 
4179 	MPASS(idx >= 0 && idx < NUM_MEMWIN);
4180 
4181 	/* Memory can only be accessed in naturally aligned 4 byte units */
4182 	if (addr & 3 || len & 3 || len <= 0)
4183 		return (EINVAL);
4184 
4185 	mw = &sc->memwin[idx];
4186 	while (len > 0) {
4187 		rw_rlock(&mw->mw_lock);
4188 		mw_end = mw->mw_curpos + mw->mw_aperture;
4189 		if (addr >= mw_end || addr < mw->mw_curpos) {
4190 			/* Will need to reposition the window */
4191 			if (!rw_try_upgrade(&mw->mw_lock)) {
4192 				rw_runlock(&mw->mw_lock);
4193 				rw_wlock(&mw->mw_lock);
4194 			}
4195 			rw_assert(&mw->mw_lock, RA_WLOCKED);
4196 			position_memwin(sc, idx, addr);
4197 			rw_downgrade(&mw->mw_lock);
4198 			mw_end = mw->mw_curpos + mw->mw_aperture;
4199 		}
4200 		rw_assert(&mw->mw_lock, RA_RLOCKED);
4201 		while (addr < mw_end && len > 0) {
4202 			if (rw == 0) {
4203 				v = t4_read_reg(sc, mw->mw_base + addr -
4204 				    mw->mw_curpos);
4205 				*val++ = le32toh(v);
4206 			} else {
4207 				v = *val++;
4208 				t4_write_reg(sc, mw->mw_base + addr -
4209 				    mw->mw_curpos, htole32(v));
4210 			}
4211 			addr += 4;
4212 			len -= 4;
4213 		}
4214 		rw_runlock(&mw->mw_lock);
4215 	}
4216 
4217 	return (0);
4218 }
4219 
4220 CTASSERT(M_TID_COOKIE == M_COOKIE);
4221 CTASSERT(MAX_ATIDS <= (M_TID_TID + 1));
4222 
4223 static void
4224 t4_init_atid_table(struct adapter *sc)
4225 {
4226 	struct tid_info *t;
4227 	int i;
4228 
4229 	t = &sc->tids;
4230 	if (t->natids == 0)
4231 		return;
4232 
4233 	MPASS(t->atid_tab == NULL);
4234 
4235 	t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
4236 	    M_ZERO | M_WAITOK);
4237 	mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
4238 	t->afree = t->atid_tab;
4239 	t->atids_in_use = 0;
4240 	t->atid_alloc_stopped = false;
4241 	for (i = 1; i < t->natids; i++)
4242 		t->atid_tab[i - 1].next = &t->atid_tab[i];
4243 	t->atid_tab[t->natids - 1].next = NULL;
4244 }
4245 
4246 static void
4247 t4_free_atid_table(struct adapter *sc)
4248 {
4249 	struct tid_info *t;
4250 
4251 	t = &sc->tids;
4252 
4253 	KASSERT(t->atids_in_use == 0,
4254 	    ("%s: %d atids still in use.", __func__, t->atids_in_use));
4255 
4256 	if (mtx_initialized(&t->atid_lock))
4257 		mtx_destroy(&t->atid_lock);
4258 	free(t->atid_tab, M_CXGBE);
4259 	t->atid_tab = NULL;
4260 }
4261 
4262 static void
4263 stop_atid_allocator(struct adapter *sc)
4264 {
4265 	struct tid_info *t = &sc->tids;
4266 
4267 	if (t->natids == 0)
4268 		return;
4269 	mtx_lock(&t->atid_lock);
4270 	t->atid_alloc_stopped = true;
4271 	mtx_unlock(&t->atid_lock);
4272 }
4273 
4274 static void
4275 restart_atid_allocator(struct adapter *sc)
4276 {
4277 	struct tid_info *t = &sc->tids;
4278 
4279 	if (t->natids == 0)
4280 		return;
4281 	mtx_lock(&t->atid_lock);
4282 	KASSERT(t->atids_in_use == 0,
4283 	    ("%s: %d atids still in use.", __func__, t->atids_in_use));
4284 	t->atid_alloc_stopped = false;
4285 	mtx_unlock(&t->atid_lock);
4286 }
4287 
4288 int
4289 alloc_atid(struct adapter *sc, void *ctx)
4290 {
4291 	struct tid_info *t = &sc->tids;
4292 	int atid = -1;
4293 
4294 	mtx_lock(&t->atid_lock);
4295 	if (t->afree && !t->atid_alloc_stopped) {
4296 		union aopen_entry *p = t->afree;
4297 
4298 		atid = p - t->atid_tab;
4299 		MPASS(atid <= M_TID_TID);
4300 		t->afree = p->next;
4301 		p->data = ctx;
4302 		t->atids_in_use++;
4303 	}
4304 	mtx_unlock(&t->atid_lock);
4305 	return (atid);
4306 }
4307 
4308 void *
4309 lookup_atid(struct adapter *sc, int atid)
4310 {
4311 	struct tid_info *t = &sc->tids;
4312 
4313 	return (t->atid_tab[atid].data);
4314 }
4315 
4316 void
4317 free_atid(struct adapter *sc, int atid)
4318 {
4319 	struct tid_info *t = &sc->tids;
4320 	union aopen_entry *p = &t->atid_tab[atid];
4321 
4322 	mtx_lock(&t->atid_lock);
4323 	p->next = t->afree;
4324 	t->afree = p;
4325 	t->atids_in_use--;
4326 	mtx_unlock(&t->atid_lock);
4327 }
4328 
4329 static void
4330 queue_tid_release(struct adapter *sc, int tid)
4331 {
4332 
4333 	CXGBE_UNIMPLEMENTED("deferred tid release");
4334 }
4335 
4336 void
4337 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
4338 {
4339 	struct wrqe *wr;
4340 	struct cpl_tid_release *req;
4341 
4342 	wr = alloc_wrqe(sizeof(*req), ctrlq);
4343 	if (wr == NULL) {
4344 		queue_tid_release(sc, tid);	/* defer */
4345 		return;
4346 	}
4347 	req = wrtod(wr);
4348 
4349 	INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
4350 
4351 	t4_wrq_tx(sc, wr);
4352 }
4353 
4354 static int
4355 t4_range_cmp(const void *a, const void *b)
4356 {
4357 	return ((const struct t4_range *)a)->start -
4358 	       ((const struct t4_range *)b)->start;
4359 }
4360 
4361 /*
4362  * Verify that the memory range specified by the addr/len pair is valid within
4363  * the card's address space.
4364  */
4365 static int
4366 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
4367 {
4368 	struct t4_range mem_ranges[4], *r, *next;
4369 	uint32_t em, addr_len;
4370 	int i, n, remaining;
4371 
4372 	/* Memory can only be accessed in naturally aligned 4 byte units */
4373 	if (addr & 3 || len & 3 || len == 0)
4374 		return (EINVAL);
4375 
4376 	/* Enabled memories */
4377 	em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
4378 
4379 	r = &mem_ranges[0];
4380 	n = 0;
4381 	bzero(r, sizeof(mem_ranges));
4382 	if (em & F_EDRAM0_ENABLE) {
4383 		addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
4384 		r->size = G_EDRAM0_SIZE(addr_len) << 20;
4385 		if (r->size > 0) {
4386 			r->start = G_EDRAM0_BASE(addr_len) << 20;
4387 			if (addr >= r->start &&
4388 			    addr + len <= r->start + r->size)
4389 				return (0);
4390 			r++;
4391 			n++;
4392 		}
4393 	}
4394 	if (em & F_EDRAM1_ENABLE) {
4395 		addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
4396 		r->size = G_EDRAM1_SIZE(addr_len) << 20;
4397 		if (r->size > 0) {
4398 			r->start = G_EDRAM1_BASE(addr_len) << 20;
4399 			if (addr >= r->start &&
4400 			    addr + len <= r->start + r->size)
4401 				return (0);
4402 			r++;
4403 			n++;
4404 		}
4405 	}
4406 	if (em & F_EXT_MEM_ENABLE) {
4407 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
4408 		r->size = G_EXT_MEM_SIZE(addr_len) << 20;
4409 		if (r->size > 0) {
4410 			r->start = G_EXT_MEM_BASE(addr_len) << 20;
4411 			if (addr >= r->start &&
4412 			    addr + len <= r->start + r->size)
4413 				return (0);
4414 			r++;
4415 			n++;
4416 		}
4417 	}
4418 	if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
4419 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
4420 		r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
4421 		if (r->size > 0) {
4422 			r->start = G_EXT_MEM1_BASE(addr_len) << 20;
4423 			if (addr >= r->start &&
4424 			    addr + len <= r->start + r->size)
4425 				return (0);
4426 			r++;
4427 			n++;
4428 		}
4429 	}
4430 	MPASS(n <= nitems(mem_ranges));
4431 
4432 	if (n > 1) {
4433 		/* Sort and merge the ranges. */
4434 		qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
4435 
4436 		/* Start from index 0 and examine the next n - 1 entries. */
4437 		r = &mem_ranges[0];
4438 		for (remaining = n - 1; remaining > 0; remaining--, r++) {
4439 
4440 			MPASS(r->size > 0);	/* r is a valid entry. */
4441 			next = r + 1;
4442 			MPASS(next->size > 0);	/* and so is the next one. */
4443 
4444 			while (r->start + r->size >= next->start) {
4445 				/* Merge the next one into the current entry. */
4446 				r->size = max(r->start + r->size,
4447 				    next->start + next->size) - r->start;
4448 				n--;	/* One fewer entry in total. */
4449 				if (--remaining == 0)
4450 					goto done;	/* short circuit */
4451 				next++;
4452 			}
4453 			if (next != r + 1) {
4454 				/*
4455 				 * Some entries were merged into r and next
4456 				 * points to the first valid entry that couldn't
4457 				 * be merged.
4458 				 */
4459 				MPASS(next->size > 0);	/* must be valid */
4460 				memcpy(r + 1, next, remaining * sizeof(*r));
4461 #ifdef INVARIANTS
4462 				/*
4463 				 * This so that the foo->size assertion in the
4464 				 * next iteration of the loop do the right
4465 				 * thing for entries that were pulled up and are
4466 				 * no longer valid.
4467 				 */
4468 				MPASS(n < nitems(mem_ranges));
4469 				bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
4470 				    sizeof(struct t4_range));
4471 #endif
4472 			}
4473 		}
4474 done:
4475 		/* Done merging the ranges. */
4476 		MPASS(n > 0);
4477 		r = &mem_ranges[0];
4478 		for (i = 0; i < n; i++, r++) {
4479 			if (addr >= r->start &&
4480 			    addr + len <= r->start + r->size)
4481 				return (0);
4482 		}
4483 	}
4484 
4485 	return (EFAULT);
4486 }
4487 
4488 static int
4489 fwmtype_to_hwmtype(int mtype)
4490 {
4491 
4492 	switch (mtype) {
4493 	case FW_MEMTYPE_EDC0:
4494 		return (MEM_EDC0);
4495 	case FW_MEMTYPE_EDC1:
4496 		return (MEM_EDC1);
4497 	case FW_MEMTYPE_EXTMEM:
4498 		return (MEM_MC0);
4499 	case FW_MEMTYPE_EXTMEM1:
4500 		return (MEM_MC1);
4501 	default:
4502 		panic("%s: cannot translate fw mtype %d.", __func__, mtype);
4503 	}
4504 }
4505 
4506 /*
4507  * Verify that the memory range specified by the memtype/offset/len pair is
4508  * valid and lies entirely within the memtype specified.  The global address of
4509  * the start of the range is returned in addr.
4510  */
4511 static int
4512 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
4513     uint32_t *addr)
4514 {
4515 	uint32_t em, addr_len, maddr;
4516 
4517 	/* Memory can only be accessed in naturally aligned 4 byte units */
4518 	if (off & 3 || len & 3 || len == 0)
4519 		return (EINVAL);
4520 
4521 	em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
4522 	switch (fwmtype_to_hwmtype(mtype)) {
4523 	case MEM_EDC0:
4524 		if (!(em & F_EDRAM0_ENABLE))
4525 			return (EINVAL);
4526 		addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
4527 		maddr = G_EDRAM0_BASE(addr_len) << 20;
4528 		break;
4529 	case MEM_EDC1:
4530 		if (!(em & F_EDRAM1_ENABLE))
4531 			return (EINVAL);
4532 		addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
4533 		maddr = G_EDRAM1_BASE(addr_len) << 20;
4534 		break;
4535 	case MEM_MC:
4536 		if (!(em & F_EXT_MEM_ENABLE))
4537 			return (EINVAL);
4538 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
4539 		maddr = G_EXT_MEM_BASE(addr_len) << 20;
4540 		break;
4541 	case MEM_MC1:
4542 		if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
4543 			return (EINVAL);
4544 		addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
4545 		maddr = G_EXT_MEM1_BASE(addr_len) << 20;
4546 		break;
4547 	default:
4548 		return (EINVAL);
4549 	}
4550 
4551 	*addr = maddr + off;	/* global address */
4552 	return (validate_mem_range(sc, *addr, len));
4553 }
4554 
4555 static int
4556 fixup_devlog_params(struct adapter *sc)
4557 {
4558 	struct devlog_params *dparams = &sc->params.devlog;
4559 	int rc;
4560 
4561 	rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
4562 	    dparams->size, &dparams->addr);
4563 
4564 	return (rc);
4565 }
4566 
4567 static void
4568 update_nirq(struct intrs_and_queues *iaq, int nports)
4569 {
4570 
4571 	iaq->nirq = T4_EXTRA_INTR;
4572 	iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq);
4573 	iaq->nirq += nports * iaq->nofldrxq;
4574 	iaq->nirq += nports * (iaq->num_vis - 1) *
4575 	    max(iaq->nrxq_vi, iaq->nnmrxq_vi);
4576 	iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
4577 }
4578 
4579 /*
4580  * Adjust requirements to fit the number of interrupts available.
4581  */
4582 static void
4583 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
4584     int navail)
4585 {
4586 	int old_nirq;
4587 	const int nports = sc->params.nports;
4588 
4589 	MPASS(nports > 0);
4590 	MPASS(navail > 0);
4591 
4592 	bzero(iaq, sizeof(*iaq));
4593 	iaq->intr_type = itype;
4594 	iaq->num_vis = t4_num_vis;
4595 	iaq->ntxq = t4_ntxq;
4596 	iaq->ntxq_vi = t4_ntxq_vi;
4597 	iaq->nrxq = t4_nrxq;
4598 	iaq->nrxq_vi = t4_nrxq_vi;
4599 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4600 	if (is_offload(sc) || is_ethoffload(sc)) {
4601 		if (sc->params.tid_qid_sel_mask == 0) {
4602 			iaq->nofldtxq = t4_nofldtxq;
4603 			iaq->nofldtxq_vi = t4_nofldtxq_vi;
4604 		} else {
4605 			iaq->nofldtxq = roundup(t4_nofldtxq, sc->params.ncores);
4606 			iaq->nofldtxq_vi = roundup(t4_nofldtxq_vi,
4607 			    sc->params.ncores);
4608 			if (iaq->nofldtxq != t4_nofldtxq)
4609 				device_printf(sc->dev,
4610 				    "nofldtxq updated (%d -> %d) for correct"
4611 				    " operation with %d firmware cores.\n",
4612 				    t4_nofldtxq, iaq->nofldtxq,
4613 				    sc->params.ncores);
4614 			if (iaq->num_vis > 1 &&
4615 			    iaq->nofldtxq_vi != t4_nofldtxq_vi)
4616 				device_printf(sc->dev,
4617 				    "nofldtxq_vi updated (%d -> %d) for correct"
4618 				    " operation with %d firmware cores.\n",
4619 				    t4_nofldtxq_vi, iaq->nofldtxq_vi,
4620 				    sc->params.ncores);
4621 		}
4622 	}
4623 #endif
4624 #ifdef TCP_OFFLOAD
4625 	if (is_offload(sc)) {
4626 		iaq->nofldrxq = t4_nofldrxq;
4627 		iaq->nofldrxq_vi = t4_nofldrxq_vi;
4628 	}
4629 #endif
4630 #ifdef DEV_NETMAP
4631 	if (t4_native_netmap & NN_MAIN_VI) {
4632 		iaq->nnmtxq = t4_nnmtxq;
4633 		iaq->nnmrxq = t4_nnmrxq;
4634 	}
4635 	if (t4_native_netmap & NN_EXTRA_VI) {
4636 		iaq->nnmtxq_vi = t4_nnmtxq_vi;
4637 		iaq->nnmrxq_vi = t4_nnmrxq_vi;
4638 	}
4639 #endif
4640 
4641 	update_nirq(iaq, nports);
4642 	if (iaq->nirq <= navail &&
4643 	    (itype != INTR_MSI || powerof2(iaq->nirq))) {
4644 		/*
4645 		 * This is the normal case -- there are enough interrupts for
4646 		 * everything.
4647 		 */
4648 		goto done;
4649 	}
4650 
4651 	/*
4652 	 * If extra VIs have been configured try reducing their count and see if
4653 	 * that works.
4654 	 */
4655 	while (iaq->num_vis > 1) {
4656 		iaq->num_vis--;
4657 		update_nirq(iaq, nports);
4658 		if (iaq->nirq <= navail &&
4659 		    (itype != INTR_MSI || powerof2(iaq->nirq))) {
4660 			device_printf(sc->dev, "virtual interfaces per port "
4661 			    "reduced to %d from %d.  nrxq=%u, nofldrxq=%u, "
4662 			    "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u.  "
4663 			    "itype %d, navail %u, nirq %d.\n",
4664 			    iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
4665 			    iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
4666 			    itype, navail, iaq->nirq);
4667 			goto done;
4668 		}
4669 	}
4670 
4671 	/*
4672 	 * Extra VIs will not be created.  Log a message if they were requested.
4673 	 */
4674 	MPASS(iaq->num_vis == 1);
4675 	iaq->ntxq_vi = iaq->nrxq_vi = 0;
4676 	iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
4677 	iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
4678 	if (iaq->num_vis != t4_num_vis) {
4679 		device_printf(sc->dev, "extra virtual interfaces disabled.  "
4680 		    "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
4681 		    "nnmrxq_vi=%u.  itype %d, navail %u, nirq %d.\n",
4682 		    iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
4683 		    iaq->nnmrxq_vi, itype, navail, iaq->nirq);
4684 	}
4685 
4686 	/*
4687 	 * Keep reducing the number of NIC rx queues to the next lower power of
4688 	 * 2 (for even RSS distribution) and halving the TOE rx queues and see
4689 	 * if that works.
4690 	 */
4691 	do {
4692 		if (iaq->nrxq > 1) {
4693 			iaq->nrxq = rounddown_pow_of_two(iaq->nrxq - 1);
4694 			if (iaq->nnmrxq > iaq->nrxq)
4695 				iaq->nnmrxq = iaq->nrxq;
4696 		}
4697 		if (iaq->nofldrxq > 1)
4698 			iaq->nofldrxq >>= 1;
4699 
4700 		old_nirq = iaq->nirq;
4701 		update_nirq(iaq, nports);
4702 		if (iaq->nirq <= navail &&
4703 		    (itype != INTR_MSI || powerof2(iaq->nirq))) {
4704 			device_printf(sc->dev, "running with reduced number of "
4705 			    "rx queues because of shortage of interrupts.  "
4706 			    "nrxq=%u, nofldrxq=%u.  "
4707 			    "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
4708 			    iaq->nofldrxq, itype, navail, iaq->nirq);
4709 			goto done;
4710 		}
4711 	} while (old_nirq != iaq->nirq);
4712 
4713 	/* One interrupt for everything.  Ugh. */
4714 	device_printf(sc->dev, "running with minimal number of queues.  "
4715 	    "itype %d, navail %u.\n", itype, navail);
4716 	iaq->nirq = 1;
4717 	iaq->nrxq = 1;
4718 	iaq->ntxq = 1;
4719 	if (iaq->nofldrxq > 0) {
4720 		iaq->nofldrxq = 1;
4721 		iaq->nofldtxq = 1;
4722 		if (sc->params.tid_qid_sel_mask == 0)
4723 			iaq->nofldtxq = 1;
4724 		else
4725 			iaq->nofldtxq = sc->params.ncores;
4726 	}
4727 	iaq->nnmtxq = 0;
4728 	iaq->nnmrxq = 0;
4729 done:
4730 	MPASS(iaq->num_vis > 0);
4731 	if (iaq->num_vis > 1) {
4732 		MPASS(iaq->nrxq_vi > 0);
4733 		MPASS(iaq->ntxq_vi > 0);
4734 	}
4735 	MPASS(iaq->nirq > 0);
4736 	MPASS(iaq->nrxq > 0);
4737 	MPASS(iaq->ntxq > 0);
4738 	if (itype == INTR_MSI)
4739 		MPASS(powerof2(iaq->nirq));
4740 	if (sc->params.tid_qid_sel_mask != 0)
4741 		MPASS(iaq->nofldtxq % sc->params.ncores == 0);
4742 }
4743 
4744 static int
4745 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
4746 {
4747 	int rc, itype, navail, nalloc;
4748 
4749 	for (itype = INTR_MSIX; itype; itype >>= 1) {
4750 
4751 		if ((itype & t4_intr_types) == 0)
4752 			continue;	/* not allowed */
4753 
4754 		if (itype == INTR_MSIX)
4755 			navail = pci_msix_count(sc->dev);
4756 		else if (itype == INTR_MSI)
4757 			navail = pci_msi_count(sc->dev);
4758 		else
4759 			navail = 1;
4760 restart:
4761 		if (navail == 0)
4762 			continue;
4763 
4764 		calculate_iaq(sc, iaq, itype, navail);
4765 		nalloc = iaq->nirq;
4766 		rc = 0;
4767 		if (itype == INTR_MSIX)
4768 			rc = pci_alloc_msix(sc->dev, &nalloc);
4769 		else if (itype == INTR_MSI)
4770 			rc = pci_alloc_msi(sc->dev, &nalloc);
4771 
4772 		if (rc == 0 && nalloc > 0) {
4773 			if (nalloc == iaq->nirq)
4774 				return (0);
4775 
4776 			/*
4777 			 * Didn't get the number requested.  Use whatever number
4778 			 * the kernel is willing to allocate.
4779 			 */
4780 			device_printf(sc->dev, "fewer vectors than requested, "
4781 			    "type=%d, req=%d, rcvd=%d; will downshift req.\n",
4782 			    itype, iaq->nirq, nalloc);
4783 			pci_release_msi(sc->dev);
4784 			navail = nalloc;
4785 			goto restart;
4786 		}
4787 
4788 		device_printf(sc->dev,
4789 		    "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
4790 		    itype, rc, iaq->nirq, nalloc);
4791 	}
4792 
4793 	device_printf(sc->dev,
4794 	    "failed to find a usable interrupt type.  "
4795 	    "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
4796 	    pci_msix_count(sc->dev), pci_msi_count(sc->dev));
4797 
4798 	return (ENXIO);
4799 }
4800 
4801 #define FW_VERSION(chip) ( \
4802     V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
4803     V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
4804     V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
4805     V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
4806 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
4807 
4808 /* Just enough of fw_hdr to cover all version info. */
4809 struct fw_h {
4810 	__u8	ver;
4811 	__u8	chip;
4812 	__be16	len512;
4813 	__be32	fw_ver;
4814 	__be32	tp_microcode_ver;
4815 	__u8	intfver_nic;
4816 	__u8	intfver_vnic;
4817 	__u8	intfver_ofld;
4818 	__u8	intfver_ri;
4819 	__u8	intfver_iscsipdu;
4820 	__u8	intfver_iscsi;
4821 	__u8	intfver_fcoepdu;
4822 	__u8	intfver_fcoe;
4823 };
4824 /* Spot check a couple of fields. */
4825 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
4826 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
4827 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
4828 
4829 struct fw_info {
4830 	uint8_t chip;
4831 	char *kld_name;
4832 	char *fw_mod_name;
4833 	struct fw_h fw_h;
4834 } fw_info[] = {
4835 	{
4836 		.chip = CHELSIO_T4,
4837 		.kld_name = "t4fw_cfg",
4838 		.fw_mod_name = "t4fw",
4839 		.fw_h = {
4840 			.chip = FW_HDR_CHIP_T4,
4841 			.fw_ver = htobe32(FW_VERSION(T4)),
4842 			.intfver_nic = FW_INTFVER(T4, NIC),
4843 			.intfver_vnic = FW_INTFVER(T4, VNIC),
4844 			.intfver_ofld = FW_INTFVER(T4, OFLD),
4845 			.intfver_ri = FW_INTFVER(T4, RI),
4846 			.intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
4847 			.intfver_iscsi = FW_INTFVER(T4, ISCSI),
4848 			.intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
4849 			.intfver_fcoe = FW_INTFVER(T4, FCOE),
4850 		},
4851 	}, {
4852 		.chip = CHELSIO_T5,
4853 		.kld_name = "t5fw_cfg",
4854 		.fw_mod_name = "t5fw",
4855 		.fw_h = {
4856 			.chip = FW_HDR_CHIP_T5,
4857 			.fw_ver = htobe32(FW_VERSION(T5)),
4858 			.intfver_nic = FW_INTFVER(T5, NIC),
4859 			.intfver_vnic = FW_INTFVER(T5, VNIC),
4860 			.intfver_ofld = FW_INTFVER(T5, OFLD),
4861 			.intfver_ri = FW_INTFVER(T5, RI),
4862 			.intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
4863 			.intfver_iscsi = FW_INTFVER(T5, ISCSI),
4864 			.intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
4865 			.intfver_fcoe = FW_INTFVER(T5, FCOE),
4866 		},
4867 	}, {
4868 		.chip = CHELSIO_T6,
4869 		.kld_name = "t6fw_cfg",
4870 		.fw_mod_name = "t6fw",
4871 		.fw_h = {
4872 			.chip = FW_HDR_CHIP_T6,
4873 			.fw_ver = htobe32(FW_VERSION(T6)),
4874 			.intfver_nic = FW_INTFVER(T6, NIC),
4875 			.intfver_vnic = FW_INTFVER(T6, VNIC),
4876 			.intfver_ofld = FW_INTFVER(T6, OFLD),
4877 			.intfver_ri = FW_INTFVER(T6, RI),
4878 			.intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4879 			.intfver_iscsi = FW_INTFVER(T6, ISCSI),
4880 			.intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4881 			.intfver_fcoe = FW_INTFVER(T6, FCOE),
4882 		},
4883 	}, {
4884 		.chip = CHELSIO_T7,
4885 		.kld_name = "t7fw_cfg",
4886 		.fw_mod_name = "t7fw",
4887 		.fw_h = {
4888 			.chip = FW_HDR_CHIP_T7,
4889 			.fw_ver = htobe32(FW_VERSION(T7)),
4890 			.intfver_nic = FW_INTFVER(T7, NIC),
4891 			.intfver_vnic = FW_INTFVER(T7, VNIC),
4892 			.intfver_ofld = FW_INTFVER(T7, OFLD),
4893 			.intfver_ri = FW_INTFVER(T7, RI),
4894 			.intfver_iscsipdu = FW_INTFVER(T7, ISCSIPDU),
4895 			.intfver_iscsi = FW_INTFVER(T7, ISCSI),
4896 			.intfver_fcoepdu = FW_INTFVER(T7, FCOEPDU),
4897 			.intfver_fcoe = FW_INTFVER(T7, FCOE),
4898 		},
4899 	}
4900 };
4901 
4902 static struct fw_info *
4903 find_fw_info(int chip)
4904 {
4905 	int i;
4906 
4907 	for (i = 0; i < nitems(fw_info); i++) {
4908 		if (fw_info[i].chip == chip)
4909 			return (&fw_info[i]);
4910 	}
4911 	return (NULL);
4912 }
4913 
4914 /*
4915  * Is the given firmware API compatible with the one the driver was compiled
4916  * with?
4917  */
4918 static int
4919 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
4920 {
4921 
4922 	/* short circuit if it's the exact same firmware version */
4923 	if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
4924 		return (1);
4925 
4926 	/*
4927 	 * XXX: Is this too conservative?  Perhaps I should limit this to the
4928 	 * features that are supported in the driver.
4929 	 */
4930 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
4931 	if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
4932 	    SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
4933 	    SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
4934 		return (1);
4935 #undef SAME_INTF
4936 
4937 	return (0);
4938 }
4939 
4940 static int
4941 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
4942     const struct firmware **fw)
4943 {
4944 	struct fw_info *fw_info;
4945 
4946 	*dcfg = NULL;
4947 	if (fw != NULL)
4948 		*fw = NULL;
4949 
4950 	fw_info = find_fw_info(chip_id(sc));
4951 	if (fw_info == NULL) {
4952 		device_printf(sc->dev,
4953 		    "unable to look up firmware information for chip %d.\n",
4954 		    chip_id(sc));
4955 		return (EINVAL);
4956 	}
4957 
4958 	*dcfg = firmware_get(fw_info->kld_name);
4959 	if (*dcfg != NULL) {
4960 		if (fw != NULL)
4961 			*fw = firmware_get(fw_info->fw_mod_name);
4962 		return (0);
4963 	}
4964 
4965 	return (ENOENT);
4966 }
4967 
4968 static void
4969 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
4970     const struct firmware *fw)
4971 {
4972 
4973 	if (fw != NULL)
4974 		firmware_put(fw, FIRMWARE_UNLOAD);
4975 	if (dcfg != NULL)
4976 		firmware_put(dcfg, FIRMWARE_UNLOAD);
4977 }
4978 
4979 /*
4980  * Return values:
4981  * 0 means no firmware install attempted.
4982  * ERESTART means a firmware install was attempted and was successful.
4983  * +ve errno means a firmware install was attempted but failed.
4984  */
4985 static int
4986 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
4987     const struct fw_h *drv_fw, const char *reason, int *already)
4988 {
4989 	const struct firmware *cfg, *fw;
4990 	const uint32_t c = be32toh(card_fw->fw_ver);
4991 	uint32_t d, k;
4992 	int rc, fw_install;
4993 	struct fw_h bundled_fw;
4994 	bool load_attempted;
4995 
4996 	cfg = fw = NULL;
4997 	load_attempted = false;
4998 	fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
4999 
5000 	memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
5001 	if (t4_fw_install < 0) {
5002 		rc = load_fw_module(sc, &cfg, &fw);
5003 		if (rc != 0 || fw == NULL) {
5004 			device_printf(sc->dev,
5005 			    "failed to load firmware module: %d. cfg %p, fw %p;"
5006 			    " will use compiled-in firmware version for"
5007 			    "hw.cxgbe.fw_install checks.\n",
5008 			    rc, cfg, fw);
5009 		} else {
5010 			memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
5011 		}
5012 		load_attempted = true;
5013 	}
5014 	d = be32toh(bundled_fw.fw_ver);
5015 
5016 	if (reason != NULL)
5017 		goto install;
5018 
5019 	if ((sc->flags & FW_OK) == 0) {
5020 
5021 		if (c == 0xffffffff) {
5022 			reason = "missing";
5023 			goto install;
5024 		}
5025 
5026 		rc = 0;
5027 		goto done;
5028 	}
5029 
5030 	if (!fw_compatible(card_fw, &bundled_fw)) {
5031 		reason = "incompatible or unusable";
5032 		goto install;
5033 	}
5034 
5035 	if (d > c) {
5036 		reason = "older than the version bundled with this driver";
5037 		goto install;
5038 	}
5039 
5040 	if (fw_install == 2 && d != c) {
5041 		reason = "different than the version bundled with this driver";
5042 		goto install;
5043 	}
5044 
5045 	/* No reason to do anything to the firmware already on the card. */
5046 	rc = 0;
5047 	goto done;
5048 
5049 install:
5050 	rc = 0;
5051 	if ((*already)++)
5052 		goto done;
5053 
5054 	if (fw_install == 0) {
5055 		device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
5056 		    "but the driver is prohibited from installing a firmware "
5057 		    "on the card.\n",
5058 		    G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
5059 		    G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
5060 
5061 		goto done;
5062 	}
5063 
5064 	/*
5065 	 * We'll attempt to install a firmware.  Load the module first (if it
5066 	 * hasn't been loaded already).
5067 	 */
5068 	if (!load_attempted) {
5069 		rc = load_fw_module(sc, &cfg, &fw);
5070 		if (rc != 0 || fw == NULL) {
5071 			device_printf(sc->dev,
5072 			    "failed to load firmware module: %d. cfg %p, fw %p\n",
5073 			    rc, cfg, fw);
5074 			/* carry on */
5075 		}
5076 	}
5077 	if (fw == NULL) {
5078 		device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
5079 		    "but the driver cannot take corrective action because it "
5080 		    "is unable to load the firmware module.\n",
5081 		    G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
5082 		    G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
5083 		rc = sc->flags & FW_OK ? 0 : ENOENT;
5084 		goto done;
5085 	}
5086 	k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
5087 	if (k != d) {
5088 		MPASS(t4_fw_install > 0);
5089 		device_printf(sc->dev,
5090 		    "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
5091 		    "expecting (%u.%u.%u.%u) and will not be used.\n",
5092 		    G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
5093 		    G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
5094 		    G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
5095 		    G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
5096 		rc = sc->flags & FW_OK ? 0 : EINVAL;
5097 		goto done;
5098 	}
5099 
5100 	device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
5101 	    "installing firmware %u.%u.%u.%u on card.\n",
5102 	    G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
5103 	    G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
5104 	    G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
5105 	    G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
5106 
5107 	rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
5108 	if (rc != 0) {
5109 		device_printf(sc->dev, "failed to install firmware: %d\n", rc);
5110 	} else {
5111 		/* Installed successfully, update the cached header too. */
5112 		rc = ERESTART;
5113 		memcpy(card_fw, fw->data, sizeof(*card_fw));
5114 	}
5115 done:
5116 	unload_fw_module(sc, cfg, fw);
5117 
5118 	return (rc);
5119 }
5120 
5121 /*
5122  * Establish contact with the firmware and attempt to become the master driver.
5123  *
5124  * A firmware will be installed to the card if needed (if the driver is allowed
5125  * to do so).
5126  */
5127 static int
5128 contact_firmware(struct adapter *sc)
5129 {
5130 	int rc, already = 0;
5131 	enum dev_state state;
5132 	struct fw_info *fw_info;
5133 	struct fw_hdr *card_fw;		/* fw on the card */
5134 	const struct fw_h *drv_fw;
5135 
5136 	fw_info = find_fw_info(chip_id(sc));
5137 	if (fw_info == NULL) {
5138 		device_printf(sc->dev,
5139 		    "unable to look up firmware information for chip %d.\n",
5140 		    chip_id(sc));
5141 		return (EINVAL);
5142 	}
5143 	drv_fw = &fw_info->fw_h;
5144 
5145 	/* Read the header of the firmware on the card */
5146 	card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
5147 restart:
5148 	rc = -t4_get_fw_hdr(sc, card_fw);
5149 	if (rc != 0) {
5150 		device_printf(sc->dev,
5151 		    "unable to read firmware header from card's flash: %d\n",
5152 		    rc);
5153 		goto done;
5154 	}
5155 
5156 	rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
5157 	    &already);
5158 	if (rc == ERESTART)
5159 		goto restart;
5160 	if (rc != 0)
5161 		goto done;
5162 
5163 	rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
5164 	if (rc < 0 || state == DEV_STATE_ERR) {
5165 		rc = -rc;
5166 		device_printf(sc->dev,
5167 		    "failed to connect to the firmware: %d, %d.  "
5168 		    "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
5169 #if 0
5170 		if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
5171 		    "not responding properly to HELLO", &already) == ERESTART)
5172 			goto restart;
5173 #endif
5174 		goto done;
5175 	}
5176 	MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
5177 	sc->flags |= FW_OK;	/* The firmware responded to the FW_HELLO. */
5178 
5179 	if (rc == sc->pf) {
5180 		sc->flags |= MASTER_PF;
5181 		rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
5182 		    NULL, &already);
5183 		if (rc == ERESTART)
5184 			rc = 0;
5185 		else if (rc != 0)
5186 			goto done;
5187 	} else if (state == DEV_STATE_UNINIT) {
5188 		/*
5189 		 * We didn't get to be the master so we definitely won't be
5190 		 * configuring the chip.  It's a bug if someone else hasn't
5191 		 * configured it already.
5192 		 */
5193 		device_printf(sc->dev, "couldn't be master(%d), "
5194 		    "device not already initialized either(%d).  "
5195 		    "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
5196 		rc = EPROTO;
5197 		goto done;
5198 	} else {
5199 		/*
5200 		 * Some other PF is the master and has configured the chip.
5201 		 * This is allowed but untested.
5202 		 */
5203 		device_printf(sc->dev, "PF%d is master, device state %d.  "
5204 		    "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
5205 		snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
5206 		sc->cfcsum = 0;
5207 		rc = 0;
5208 	}
5209 done:
5210 	if (rc != 0 && sc->flags & FW_OK) {
5211 		t4_fw_bye(sc, sc->mbox);
5212 		sc->flags &= ~FW_OK;
5213 	}
5214 	free(card_fw, M_CXGBE);
5215 	return (rc);
5216 }
5217 
5218 static int
5219 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
5220     uint32_t mtype, uint32_t moff, u_int maxlen)
5221 {
5222 	struct fw_info *fw_info;
5223 	const struct firmware *dcfg, *rcfg = NULL;
5224 	const uint32_t *cfdata;
5225 	uint32_t cflen, addr;
5226 	int rc;
5227 
5228 	load_fw_module(sc, &dcfg, NULL);
5229 
5230 	/* Card specific interpretation of "default". */
5231 	if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
5232 		if (pci_get_device(sc->dev) == 0x440a)
5233 			snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
5234 		if (is_fpga(sc))
5235 			snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
5236 	}
5237 
5238 	if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
5239 		if (dcfg == NULL) {
5240 			device_printf(sc->dev,
5241 			    "KLD with default config is not available.\n");
5242 			rc = ENOENT;
5243 			goto done;
5244 		}
5245 		cfdata = dcfg->data;
5246 		cflen = dcfg->datasize & ~3;
5247 	} else {
5248 		char s[32];
5249 
5250 		fw_info = find_fw_info(chip_id(sc));
5251 		if (fw_info == NULL) {
5252 			device_printf(sc->dev,
5253 			    "unable to look up firmware information for chip %d.\n",
5254 			    chip_id(sc));
5255 			rc = EINVAL;
5256 			goto done;
5257 		}
5258 		snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
5259 
5260 		rcfg = firmware_get(s);
5261 		if (rcfg == NULL) {
5262 			device_printf(sc->dev,
5263 			    "unable to load module \"%s\" for configuration "
5264 			    "profile \"%s\".\n", s, cfg_file);
5265 			rc = ENOENT;
5266 			goto done;
5267 		}
5268 		cfdata = rcfg->data;
5269 		cflen = rcfg->datasize & ~3;
5270 	}
5271 
5272 	if (cflen > maxlen) {
5273 		device_printf(sc->dev,
5274 		    "config file too long (%d, max allowed is %d).\n",
5275 		    cflen, maxlen);
5276 		rc = EINVAL;
5277 		goto done;
5278 	}
5279 
5280 	rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
5281 	if (rc != 0) {
5282 		device_printf(sc->dev,
5283 		    "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
5284 		    __func__, mtype, moff, cflen, rc);
5285 		rc = EINVAL;
5286 		goto done;
5287 	}
5288 	write_via_memwin(sc, 2, addr, cfdata, cflen);
5289 done:
5290 	if (rcfg != NULL)
5291 		firmware_put(rcfg, FIRMWARE_UNLOAD);
5292 	unload_fw_module(sc, dcfg, NULL);
5293 	return (rc);
5294 }
5295 
5296 struct caps_allowed {
5297 	uint16_t nbmcaps;
5298 	uint16_t linkcaps;
5299 	uint16_t switchcaps;
5300 	uint16_t nvmecaps;
5301 	uint16_t niccaps;
5302 	uint16_t toecaps;
5303 	uint16_t rdmacaps;
5304 	uint16_t cryptocaps;
5305 	uint16_t iscsicaps;
5306 	uint16_t fcoecaps;
5307 };
5308 
5309 #define FW_PARAM_DEV(param) \
5310 	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5311 	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5312 #define FW_PARAM_PFVF(param) \
5313 	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5314 	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
5315 
5316 /*
5317  * Provide a configuration profile to the firmware and have it initialize the
5318  * chip accordingly.  This may involve uploading a configuration file to the
5319  * card.
5320  */
5321 static int
5322 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
5323     const struct caps_allowed *caps_allowed)
5324 {
5325 	int rc;
5326 	struct fw_caps_config_cmd caps;
5327 	uint32_t mtype, moff, finicsum, cfcsum, param, val;
5328 	unsigned int maxlen = 0;
5329 	const int cfg_addr = t4_flash_cfg_addr(sc, &maxlen);
5330 
5331 	rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
5332 	if (rc != 0) {
5333 		device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
5334 		return (rc);
5335 	}
5336 
5337 	bzero(&caps, sizeof(caps));
5338 	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5339 	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
5340 	if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
5341 		mtype = 0;
5342 		moff = 0;
5343 		caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5344 	} else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
5345 		mtype = FW_MEMTYPE_FLASH;
5346 		moff = cfg_addr;
5347 		caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
5348 		    V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5349 		    V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
5350 		    FW_LEN16(caps));
5351 	} else {
5352 		/*
5353 		 * Ask the firmware where it wants us to upload the config file.
5354 		 */
5355 		param = FW_PARAM_DEV(CF);
5356 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5357 		if (rc != 0) {
5358 			/* No support for config file?  Shouldn't happen. */
5359 			device_printf(sc->dev,
5360 			    "failed to query config file location: %d.\n", rc);
5361 			goto done;
5362 		}
5363 		mtype = G_FW_PARAMS_PARAM_Y(val);
5364 		moff = G_FW_PARAMS_PARAM_Z(val) << 16;
5365 		caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
5366 		    V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5367 		    V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
5368 		    FW_LEN16(caps));
5369 
5370 		rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff, maxlen);
5371 		if (rc != 0) {
5372 			device_printf(sc->dev,
5373 			    "failed to upload config file to card: %d.\n", rc);
5374 			goto done;
5375 		}
5376 	}
5377 	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
5378 	if (rc != 0) {
5379 		device_printf(sc->dev, "failed to pre-process config file: %d "
5380 		    "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
5381 		goto done;
5382 	}
5383 
5384 	finicsum = be32toh(caps.finicsum);
5385 	cfcsum = be32toh(caps.cfcsum);	/* actual */
5386 	if (finicsum != cfcsum) {
5387 		device_printf(sc->dev,
5388 		    "WARNING: config file checksum mismatch: %08x %08x\n",
5389 		    finicsum, cfcsum);
5390 	}
5391 	sc->cfcsum = cfcsum;
5392 	snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
5393 
5394 	/*
5395 	 * Let the firmware know what features will (not) be used so it can tune
5396 	 * things accordingly.
5397 	 */
5398 #define LIMIT_CAPS(x) do { \
5399 	caps.x##caps &= htobe16(caps_allowed->x##caps); \
5400 } while (0)
5401 	LIMIT_CAPS(nbm);
5402 	LIMIT_CAPS(link);
5403 	LIMIT_CAPS(switch);
5404 	LIMIT_CAPS(nvme);
5405 	LIMIT_CAPS(nic);
5406 	LIMIT_CAPS(toe);
5407 	LIMIT_CAPS(rdma);
5408 	LIMIT_CAPS(crypto);
5409 	LIMIT_CAPS(iscsi);
5410 	LIMIT_CAPS(fcoe);
5411 #undef LIMIT_CAPS
5412 	if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
5413 		/*
5414 		 * TOE and hashfilters are mutually exclusive.  It is a config
5415 		 * file or firmware bug if both are reported as available.  Try
5416 		 * to cope with the situation in non-debug builds by disabling
5417 		 * TOE.
5418 		 */
5419 		MPASS(caps.toecaps == 0);
5420 
5421 		caps.toecaps = 0;
5422 		caps.rdmacaps = 0;
5423 		caps.iscsicaps = 0;
5424 		caps.nvmecaps = 0;
5425 	}
5426 
5427 	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5428 	    F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5429 	caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5430 	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
5431 	if (rc != 0) {
5432 		device_printf(sc->dev,
5433 		    "failed to process config file: %d.\n", rc);
5434 		goto done;
5435 	}
5436 
5437 	t4_tweak_chip_settings(sc);
5438 	set_params__pre_init(sc);
5439 
5440 	/* get basic stuff going */
5441 	rc = -t4_fw_initialize(sc, sc->mbox);
5442 	if (rc != 0) {
5443 		device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
5444 		goto done;
5445 	}
5446 done:
5447 	return (rc);
5448 }
5449 
5450 /*
5451  * Partition chip resources for use between various PFs, VFs, etc.
5452  */
5453 static int
5454 partition_resources(struct adapter *sc)
5455 {
5456 	char cfg_file[sizeof(t4_cfg_file)];
5457 	struct caps_allowed caps_allowed;
5458 	int rc;
5459 	bool fallback;
5460 
5461 	/* Only the master driver gets to configure the chip resources. */
5462 	MPASS(sc->flags & MASTER_PF);
5463 
5464 #define COPY_CAPS(x) do { \
5465 	caps_allowed.x##caps = t4_##x##caps_allowed; \
5466 } while (0)
5467 	bzero(&caps_allowed, sizeof(caps_allowed));
5468 	COPY_CAPS(nbm);
5469 	COPY_CAPS(link);
5470 	COPY_CAPS(switch);
5471 	COPY_CAPS(nvme);
5472 	COPY_CAPS(nic);
5473 	COPY_CAPS(toe);
5474 	COPY_CAPS(rdma);
5475 	COPY_CAPS(crypto);
5476 	COPY_CAPS(iscsi);
5477 	COPY_CAPS(fcoe);
5478 	fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
5479 	snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
5480 retry:
5481 	rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
5482 	if (rc != 0 && fallback) {
5483 		dump_devlog(sc);
5484 		device_printf(sc->dev,
5485 		    "failed (%d) to configure card with \"%s\" profile, "
5486 		    "will fall back to a basic configuration and retry.\n",
5487 		    rc, cfg_file);
5488 		snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
5489 		bzero(&caps_allowed, sizeof(caps_allowed));
5490 		COPY_CAPS(switch);
5491 		caps_allowed.niccaps = FW_CAPS_CONFIG_NIC;
5492 		fallback = false;
5493 		goto retry;
5494 	}
5495 #undef COPY_CAPS
5496 	return (rc);
5497 }
5498 
5499 /*
5500  * Retrieve parameters that are needed (or nice to have) very early.
5501  */
5502 static int
5503 get_params__pre_init(struct adapter *sc)
5504 {
5505 	int rc;
5506 	uint32_t param[2], val[2];
5507 
5508 	t4_get_version_info(sc);
5509 
5510 	snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
5511 	    G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
5512 	    G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
5513 	    G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
5514 	    G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
5515 
5516 	snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
5517 	    G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
5518 	    G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
5519 	    G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
5520 	    G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
5521 
5522 	snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
5523 	    G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
5524 	    G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
5525 	    G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
5526 	    G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
5527 
5528 	snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
5529 	    G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
5530 	    G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
5531 	    G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
5532 	    G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
5533 
5534 	param[0] = FW_PARAM_DEV(PORTVEC);
5535 	param[1] = FW_PARAM_DEV(CCLK);
5536 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5537 	if (rc != 0) {
5538 		device_printf(sc->dev,
5539 		    "failed to query parameters (pre_init): %d.\n", rc);
5540 		return (rc);
5541 	}
5542 
5543 	sc->params.portvec = val[0];
5544 	sc->params.nports = bitcount32(val[0]);
5545 	sc->params.vpd.cclk = val[1];
5546 
5547 	/* Read device log parameters. */
5548 	rc = -t4_init_devlog_ncores_params(sc, 1);
5549 	if (rc == 0)
5550 		fixup_devlog_params(sc);
5551 	else {
5552 		device_printf(sc->dev,
5553 		    "failed to get devlog parameters: %d.\n", rc);
5554 		rc = 0;	/* devlog isn't critical for device operation */
5555 	}
5556 
5557 	return (rc);
5558 }
5559 
5560 /*
5561  * Any params that need to be set before FW_INITIALIZE.
5562  */
5563 static int
5564 set_params__pre_init(struct adapter *sc)
5565 {
5566 	int rc = 0;
5567 	uint32_t param, val;
5568 
5569 	if (chip_id(sc) >= CHELSIO_T6) {
5570 		param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
5571 		val = 1;
5572 		rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5573 		/* firmwares < 1.20.1.0 do not have this param. */
5574 		if (rc == FW_EINVAL &&
5575 		    sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) {
5576 			rc = 0;
5577 		}
5578 		if (rc != 0) {
5579 			device_printf(sc->dev,
5580 			    "failed to enable high priority filters :%d.\n",
5581 			    rc);
5582 		}
5583 
5584 		param = FW_PARAM_DEV(PPOD_EDRAM);
5585 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5586 		if (rc == 0 && val == 1) {
5587 			rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param,
5588 			    &val);
5589 			if (rc != 0) {
5590 				device_printf(sc->dev,
5591 				    "failed to set PPOD_EDRAM: %d.\n", rc);
5592 			}
5593 		}
5594 	}
5595 
5596 	/* Enable opaque VIIDs with firmwares that support it. */
5597 	param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
5598 	val = 1;
5599 	rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5600 	if (rc == 0 && val == 1)
5601 		sc->params.viid_smt_extn_support = true;
5602 	else
5603 		sc->params.viid_smt_extn_support = false;
5604 
5605 	return (rc);
5606 }
5607 
5608 /*
5609  * Retrieve various parameters that are of interest to the driver.  The device
5610  * has been initialized by the firmware at this point.
5611  */
5612 static int
5613 get_params__post_init(struct adapter *sc)
5614 {
5615 	int rc;
5616 	uint32_t param[7], val[7];
5617 	struct fw_caps_config_cmd caps;
5618 
5619 	param[0] = FW_PARAM_PFVF(IQFLINT_START);
5620 	param[1] = FW_PARAM_PFVF(EQ_START);
5621 	param[2] = FW_PARAM_PFVF(FILTER_START);
5622 	param[3] = FW_PARAM_PFVF(FILTER_END);
5623 	param[4] = FW_PARAM_PFVF(L2T_START);
5624 	param[5] = FW_PARAM_PFVF(L2T_END);
5625 	param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5626 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5627 	    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
5628 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
5629 	if (rc != 0) {
5630 		device_printf(sc->dev,
5631 		    "failed to query parameters (post_init): %d.\n", rc);
5632 		return (rc);
5633 	}
5634 
5635 	sc->sge.iq_start = val[0];
5636 	sc->sge.eq_start = val[1];
5637 	if ((int)val[3] > (int)val[2]) {
5638 		sc->tids.ftid_base = val[2];
5639 		sc->tids.ftid_end = val[3];
5640 		sc->tids.nftids = val[3] - val[2] + 1;
5641 	}
5642 	sc->vres.l2t.start = val[4];
5643 	sc->vres.l2t.size = val[5] - val[4] + 1;
5644 	/* val[5] is the last hwidx and it must not collide with F_SYNC_WR */
5645 	if (sc->vres.l2t.size > 0)
5646 		MPASS(fls(val[5]) <= S_SYNC_WR);
5647 	sc->params.core_vdd = val[6];
5648 
5649 	param[0] = FW_PARAM_PFVF(IQFLINT_END);
5650 	param[1] = FW_PARAM_PFVF(EQ_END);
5651 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5652 	if (rc != 0) {
5653 		device_printf(sc->dev,
5654 		    "failed to query parameters (post_init2): %d.\n", rc);
5655 		return (rc);
5656 	}
5657 	MPASS((int)val[0] >= sc->sge.iq_start);
5658 	sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1;
5659 	MPASS((int)val[1] >= sc->sge.eq_start);
5660 	sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1;
5661 
5662 	if (chip_id(sc) >= CHELSIO_T6) {
5663 
5664 		sc->tids.tid_base = t4_read_reg(sc,
5665 		    A_LE_DB_ACTIVE_TABLE_START_INDEX);
5666 
5667 		param[0] = FW_PARAM_PFVF(HPFILTER_START);
5668 		param[1] = FW_PARAM_PFVF(HPFILTER_END);
5669 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5670 		if (rc != 0) {
5671 			device_printf(sc->dev,
5672 			   "failed to query hpfilter parameters: %d.\n", rc);
5673 			return (rc);
5674 		}
5675 		if ((int)val[1] > (int)val[0]) {
5676 			sc->tids.hpftid_base = val[0];
5677 			sc->tids.hpftid_end = val[1];
5678 			sc->tids.nhpftids = val[1] - val[0] + 1;
5679 
5680 			/*
5681 			 * These should go off if the layout changes and the
5682 			 * driver needs to catch up.
5683 			 */
5684 			MPASS(sc->tids.hpftid_base == 0);
5685 			MPASS(sc->tids.tid_base == sc->tids.nhpftids);
5686 		}
5687 
5688 		param[0] = FW_PARAM_PFVF(RAWF_START);
5689 		param[1] = FW_PARAM_PFVF(RAWF_END);
5690 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5691 		if (rc != 0) {
5692 			device_printf(sc->dev,
5693 			   "failed to query rawf parameters: %d.\n", rc);
5694 			return (rc);
5695 		}
5696 		if ((int)val[1] > (int)val[0]) {
5697 			sc->rawf_base = val[0];
5698 			sc->nrawf = val[1] - val[0] + 1;
5699 		}
5700 	}
5701 
5702 	if (sc->params.ncores > 1) {
5703 		MPASS(chip_id(sc) >= CHELSIO_T7);
5704 
5705 		param[0] = FW_PARAM_DEV(TID_QID_SEL_MASK);
5706 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5707 		sc->params.tid_qid_sel_mask = rc == 0 ? val[0] : 0;
5708 	}
5709 
5710 	/*
5711 	 * The parameters that follow may not be available on all firmwares.  We
5712 	 * query them individually rather than in a compound query because old
5713 	 * firmwares fail the entire query if an unknown parameter is queried.
5714 	 */
5715 
5716 	/*
5717 	 * MPS buffer group configuration.
5718 	 */
5719 	param[0] = FW_PARAM_DEV(MPSBGMAP);
5720 	val[0] = 0;
5721 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5722 	if (rc == 0)
5723 		sc->params.mps_bg_map = val[0];
5724 	else
5725 		sc->params.mps_bg_map = UINT32_MAX;	/* Not a legal value. */
5726 
5727 	param[0] = FW_PARAM_DEV(TPCHMAP);
5728 	val[0] = 0;
5729 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5730 	if (rc == 0)
5731 		sc->params.tp_ch_map = val[0];
5732 	else
5733 		sc->params.tp_ch_map = UINT32_MAX;	/* Not a legal value. */
5734 
5735 	param[0] = FW_PARAM_DEV(TX_TPCHMAP);
5736 	val[0] = 0;
5737 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5738 	if (rc == 0)
5739 		sc->params.tx_tp_ch_map = val[0];
5740 	else
5741 		sc->params.tx_tp_ch_map = UINT32_MAX;	/* Not a legal value. */
5742 
5743 	/*
5744 	 * Determine whether the firmware supports the filter2 work request.
5745 	 */
5746 	param[0] = FW_PARAM_DEV(FILTER2_WR);
5747 	val[0] = 0;
5748 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5749 	if (rc == 0)
5750 		sc->params.filter2_wr_support = val[0] != 0;
5751 	else
5752 		sc->params.filter2_wr_support = 0;
5753 
5754 	/*
5755 	 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
5756 	 */
5757 	param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5758 	val[0] = 0;
5759 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5760 	if (rc == 0)
5761 		sc->params.ulptx_memwrite_dsgl = val[0] != 0;
5762 	else
5763 		sc->params.ulptx_memwrite_dsgl = false;
5764 
5765 	/* FW_RI_FR_NSMR_TPTE_WR support */
5766 	param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
5767 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5768 	if (rc == 0)
5769 		sc->params.fr_nsmr_tpte_wr_support = val[0] != 0;
5770 	else
5771 		sc->params.fr_nsmr_tpte_wr_support = false;
5772 
5773 	/* Support for 512 SGL entries per FR MR. */
5774 	param[0] = FW_PARAM_DEV(DEV_512SGL_MR);
5775 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5776 	if (rc == 0)
5777 		sc->params.dev_512sgl_mr = val[0] != 0;
5778 	else
5779 		sc->params.dev_512sgl_mr = false;
5780 
5781 	param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
5782 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5783 	if (rc == 0)
5784 		sc->params.max_pkts_per_eth_tx_pkts_wr = val[0];
5785 	else
5786 		sc->params.max_pkts_per_eth_tx_pkts_wr = 15;
5787 
5788 	param[0] = FW_PARAM_DEV(NUM_TM_CLASS);
5789 	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5790 	if (rc == 0) {
5791 		MPASS(val[0] > 0 && val[0] < 256);	/* nsched_cls is 8b */
5792 		sc->params.nsched_cls = val[0];
5793 	} else
5794 		sc->params.nsched_cls = sc->chip_params->nsched_cls;
5795 
5796 	/* get capabilites */
5797 	bzero(&caps, sizeof(caps));
5798 	caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5799 	    F_FW_CMD_REQUEST | F_FW_CMD_READ);
5800 	caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5801 	rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
5802 	if (rc != 0) {
5803 		device_printf(sc->dev,
5804 		    "failed to get card capabilities: %d.\n", rc);
5805 		return (rc);
5806 	}
5807 
5808 #define READ_CAPS(x) do { \
5809 	sc->x = htobe16(caps.x); \
5810 } while (0)
5811 	READ_CAPS(nbmcaps);
5812 	READ_CAPS(linkcaps);
5813 	READ_CAPS(switchcaps);
5814 	READ_CAPS(nvmecaps);
5815 	READ_CAPS(niccaps);
5816 	READ_CAPS(toecaps);
5817 	READ_CAPS(rdmacaps);
5818 	READ_CAPS(cryptocaps);
5819 	READ_CAPS(iscsicaps);
5820 	READ_CAPS(fcoecaps);
5821 
5822 	if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
5823 		MPASS(chip_id(sc) > CHELSIO_T4);
5824 		MPASS(sc->toecaps == 0);
5825 		sc->toecaps = 0;
5826 
5827 		param[0] = FW_PARAM_DEV(NTID);
5828 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5829 		if (rc != 0) {
5830 			device_printf(sc->dev,
5831 			    "failed to query HASHFILTER parameters: %d.\n", rc);
5832 			return (rc);
5833 		}
5834 		sc->tids.ntids = val[0];
5835 		if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5836 			MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5837 			sc->tids.ntids -= sc->tids.nhpftids;
5838 		}
5839 		sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5840 		sc->params.hash_filter = 1;
5841 	}
5842 	if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
5843 		param[0] = FW_PARAM_PFVF(ETHOFLD_START);
5844 		param[1] = FW_PARAM_PFVF(ETHOFLD_END);
5845 		param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5846 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
5847 		if (rc != 0) {
5848 			device_printf(sc->dev,
5849 			    "failed to query NIC parameters: %d.\n", rc);
5850 			return (rc);
5851 		}
5852 		if ((int)val[1] > (int)val[0]) {
5853 			sc->tids.etid_base = val[0];
5854 			sc->tids.etid_end = val[1];
5855 			sc->tids.netids = val[1] - val[0] + 1;
5856 			sc->params.eo_wr_cred = val[2];
5857 			sc->params.ethoffload = 1;
5858 		}
5859 	}
5860 	if (sc->toecaps) {
5861 		/* query offload-related parameters */
5862 		param[0] = FW_PARAM_DEV(NTID);
5863 		param[1] = FW_PARAM_PFVF(SERVER_START);
5864 		param[2] = FW_PARAM_PFVF(SERVER_END);
5865 		param[3] = FW_PARAM_PFVF(TDDP_START);
5866 		param[4] = FW_PARAM_PFVF(TDDP_END);
5867 		param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5868 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5869 		if (rc != 0) {
5870 			device_printf(sc->dev,
5871 			    "failed to query TOE parameters: %d.\n", rc);
5872 			return (rc);
5873 		}
5874 		sc->tids.ntids = val[0];
5875 		if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5876 			MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5877 			sc->tids.ntids -= sc->tids.nhpftids;
5878 		}
5879 		sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5880 		if ((int)val[2] > (int)val[1]) {
5881 			sc->tids.stid_base = val[1];
5882 			sc->tids.nstids = val[2] - val[1] + 1;
5883 		}
5884 		sc->vres.ddp.start = val[3];
5885 		sc->vres.ddp.size = val[4] - val[3] + 1;
5886 		sc->params.ofldq_wr_cred = val[5];
5887 		sc->params.offload = 1;
5888 	} else {
5889 		/*
5890 		 * The firmware attempts memfree TOE configuration for -SO cards
5891 		 * and will report toecaps=0 if it runs out of resources (this
5892 		 * depends on the config file).  It may not report 0 for other
5893 		 * capabilities dependent on the TOE in this case.  Set them to
5894 		 * 0 here so that the driver doesn't bother tracking resources
5895 		 * that will never be used.
5896 		 */
5897 		sc->iscsicaps = 0;
5898 		sc->nvmecaps = 0;
5899 		sc->rdmacaps = 0;
5900 	}
5901 	if (sc->nvmecaps || sc->rdmacaps) {
5902 		param[0] = FW_PARAM_PFVF(STAG_START);
5903 		param[1] = FW_PARAM_PFVF(STAG_END);
5904 		param[2] = FW_PARAM_PFVF(PBL_START);
5905 		param[3] = FW_PARAM_PFVF(PBL_END);
5906 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
5907 		if (rc != 0) {
5908 			device_printf(sc->dev,
5909 			    "failed to query NVMe/RDMA parameters: %d.\n", rc);
5910 			return (rc);
5911 		}
5912 		sc->vres.stag.start = val[0];
5913 		sc->vres.stag.size = val[1] - val[0] + 1;
5914 		sc->vres.pbl.start = val[2];
5915 		sc->vres.pbl.size = val[3] - val[2] + 1;
5916 	}
5917 	if (sc->rdmacaps) {
5918 		param[0] = FW_PARAM_PFVF(RQ_START);
5919 		param[1] = FW_PARAM_PFVF(RQ_END);
5920 		param[2] = FW_PARAM_PFVF(SQRQ_START);
5921 		param[3] = FW_PARAM_PFVF(SQRQ_END);
5922 		param[4] = FW_PARAM_PFVF(CQ_START);
5923 		param[5] = FW_PARAM_PFVF(CQ_END);
5924 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5925 		if (rc != 0) {
5926 			device_printf(sc->dev,
5927 			    "failed to query RDMA parameters(1): %d.\n", rc);
5928 			return (rc);
5929 		}
5930 		sc->vres.rq.start = val[0];
5931 		sc->vres.rq.size = val[1] - val[0] + 1;
5932 		sc->vres.qp.start = val[2];
5933 		sc->vres.qp.size = val[3] - val[2] + 1;
5934 		sc->vres.cq.start = val[4];
5935 		sc->vres.cq.size = val[5] - val[4] + 1;
5936 
5937 		param[0] = FW_PARAM_PFVF(OCQ_START);
5938 		param[1] = FW_PARAM_PFVF(OCQ_END);
5939 		param[2] = FW_PARAM_PFVF(SRQ_START);
5940 		param[3] = FW_PARAM_PFVF(SRQ_END);
5941 		param[4] = FW_PARAM_DEV(MAXORDIRD_QP);
5942 		param[5] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5943 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5944 		if (rc != 0) {
5945 			device_printf(sc->dev,
5946 			    "failed to query RDMA parameters(2): %d.\n", rc);
5947 			return (rc);
5948 		}
5949 		sc->vres.ocq.start = val[0];
5950 		sc->vres.ocq.size = val[1] - val[0] + 1;
5951 		sc->vres.srq.start = val[2];
5952 		sc->vres.srq.size = val[3] - val[2] + 1;
5953 		sc->params.max_ordird_qp = val[4];
5954 		sc->params.max_ird_adapter = val[5];
5955 	}
5956 	if (sc->iscsicaps) {
5957 		param[0] = FW_PARAM_PFVF(ISCSI_START);
5958 		param[1] = FW_PARAM_PFVF(ISCSI_END);
5959 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5960 		if (rc != 0) {
5961 			device_printf(sc->dev,
5962 			    "failed to query iSCSI parameters: %d.\n", rc);
5963 			return (rc);
5964 		}
5965 		sc->vres.iscsi.start = val[0];
5966 		sc->vres.iscsi.size = val[1] - val[0] + 1;
5967 	}
5968 	if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
5969 		param[0] = FW_PARAM_PFVF(TLS_START);
5970 		param[1] = FW_PARAM_PFVF(TLS_END);
5971 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5972 		if (rc != 0) {
5973 			device_printf(sc->dev,
5974 			    "failed to query TLS parameters: %d.\n", rc);
5975 			return (rc);
5976 		}
5977 		sc->vres.key.start = val[0];
5978 		sc->vres.key.size = val[1] - val[0] + 1;
5979 	}
5980 
5981 	/*
5982 	 * We've got the params we wanted to query directly from the firmware.
5983 	 * Grab some others via other means.
5984 	 */
5985 	t4_init_sge_params(sc);
5986 	t4_init_tp_params(sc);
5987 	t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
5988 	t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
5989 
5990 	rc = t4_verify_chip_settings(sc);
5991 	if (rc != 0)
5992 		return (rc);
5993 	t4_init_rx_buf_info(sc);
5994 
5995 	return (rc);
5996 }
5997 
5998 #ifdef KERN_TLS
5999 static void
6000 ktls_tick(void *arg)
6001 {
6002 	struct adapter *sc;
6003 	uint32_t tstamp;
6004 
6005 	sc = arg;
6006 	tstamp = tcp_ts_getticks();
6007 	t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1);
6008 	t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31);
6009 	callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK);
6010 }
6011 
6012 static int
6013 t6_config_kern_tls(struct adapter *sc, bool enable)
6014 {
6015 	int rc;
6016 	uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6017 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) |
6018 	    V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) |
6019 	    V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE);
6020 
6021 	rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &param);
6022 	if (rc != 0) {
6023 		CH_ERR(sc, "failed to %s NIC TLS: %d\n",
6024 		    enable ?  "enable" : "disable", rc);
6025 		return (rc);
6026 	}
6027 
6028 	if (enable) {
6029 		sc->flags |= KERN_TLS_ON;
6030 		callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc,
6031 		    C_HARDCLOCK);
6032 	} else {
6033 		sc->flags &= ~KERN_TLS_ON;
6034 		callout_stop(&sc->ktls_tick);
6035 	}
6036 
6037 	return (rc);
6038 }
6039 #endif
6040 
6041 static int
6042 set_params__post_init(struct adapter *sc)
6043 {
6044 	uint32_t mask, param, val;
6045 #ifdef TCP_OFFLOAD
6046 	int i, v, shift;
6047 #endif
6048 
6049 	/* ask for encapsulated CPLs */
6050 	param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
6051 	val = 1;
6052 	(void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
6053 
6054 	/* Enable 32b port caps if the firmware supports it. */
6055 	param = FW_PARAM_PFVF(PORT_CAPS32);
6056 	val = 1;
6057 	if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val) == 0)
6058 		sc->params.port_caps32 = 1;
6059 
6060 	/* Let filter + maskhash steer to a part of the VI's RSS region. */
6061 	val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
6062 	t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
6063 	    V_MASKFILTER(val - 1));
6064 
6065 	mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER |
6066 	    F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN |
6067 	    F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
6068 	    F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM;
6069 	val = 0;
6070 	if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) {
6071 		t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE,
6072 		    F_ATTACKFILTERENABLE);
6073 		val |= F_DROPERRORATTACK;
6074 	}
6075 	if (t4_drop_ip_fragments != 0) {
6076 		t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP,
6077 		    F_FRAGMENTDROP);
6078 		val |= F_DROPERRORFRAG;
6079 	}
6080 	if (t4_drop_pkts_with_l2_errors != 0)
6081 		val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN;
6082 	if (t4_drop_pkts_with_l3_errors != 0) {
6083 		val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN |
6084 		    F_DROPERRORCSUMIP;
6085 	}
6086 	if (t4_drop_pkts_with_l4_errors != 0) {
6087 		val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
6088 		    F_DROPERRORTCPOPT | F_DROPERRORCSUM;
6089 	}
6090 	t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val);
6091 
6092 #ifdef TCP_OFFLOAD
6093 	/*
6094 	 * Override the TOE timers with user provided tunables.  This is not the
6095 	 * recommended way to change the timers (the firmware config file is) so
6096 	 * these tunables are not documented.
6097 	 *
6098 	 * All the timer tunables are in microseconds.
6099 	 */
6100 	if (t4_toe_keepalive_idle != 0) {
6101 		v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
6102 		v &= M_KEEPALIVEIDLE;
6103 		t4_set_reg_field(sc, A_TP_KEEP_IDLE,
6104 		    V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
6105 	}
6106 	if (t4_toe_keepalive_interval != 0) {
6107 		v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
6108 		v &= M_KEEPALIVEINTVL;
6109 		t4_set_reg_field(sc, A_TP_KEEP_INTVL,
6110 		    V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
6111 	}
6112 	if (t4_toe_keepalive_count != 0) {
6113 		v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
6114 		t4_set_reg_field(sc, A_TP_SHIFT_CNT,
6115 		    V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
6116 		    V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
6117 		    V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
6118 	}
6119 	if (t4_toe_rexmt_min != 0) {
6120 		v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
6121 		v &= M_RXTMIN;
6122 		t4_set_reg_field(sc, A_TP_RXT_MIN,
6123 		    V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
6124 	}
6125 	if (t4_toe_rexmt_max != 0) {
6126 		v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
6127 		v &= M_RXTMAX;
6128 		t4_set_reg_field(sc, A_TP_RXT_MAX,
6129 		    V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
6130 	}
6131 	if (t4_toe_rexmt_count != 0) {
6132 		v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
6133 		t4_set_reg_field(sc, A_TP_SHIFT_CNT,
6134 		    V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
6135 		    V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
6136 		    V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
6137 	}
6138 	for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
6139 		if (t4_toe_rexmt_backoff[i] != -1) {
6140 			v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
6141 			shift = (i & 3) << 3;
6142 			t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
6143 			    M_TIMERBACKOFFINDEX0 << shift, v << shift);
6144 		}
6145 	}
6146 #endif
6147 
6148 	/*
6149 	 * Limit TOE connections to 2 reassembly "islands".  This is
6150 	 * required to permit migrating TOE connections to either
6151 	 * ULP_MODE_TCPDDP or UPL_MODE_TLS.
6152 	 */
6153 	t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, V_PASSMODE(M_PASSMODE),
6154 	    V_PASSMODE(2));
6155 
6156 #ifdef KERN_TLS
6157 	if (is_ktls(sc)) {
6158 		sc->tlst.inline_keys = t4_tls_inline_keys;
6159 		if (t4_kern_tls != 0 && is_t6(sc)) {
6160 			sc->tlst.combo_wrs = t4_tls_combo_wrs;
6161 			t6_config_kern_tls(sc, true);
6162 		} else {
6163 			sc->tlst.short_records = t4_tls_short_records;
6164 			sc->tlst.partial_ghash = t4_tls_partial_ghash;
6165 		}
6166 	}
6167 #endif
6168 	return (0);
6169 }
6170 
6171 #undef FW_PARAM_PFVF
6172 #undef FW_PARAM_DEV
6173 
6174 static void
6175 t4_set_desc(struct adapter *sc)
6176 {
6177 	struct adapter_params *p = &sc->params;
6178 
6179 	device_set_descf(sc->dev, "Chelsio %s", p->vpd.id);
6180 }
6181 
6182 static inline void
6183 ifmedia_add4(struct ifmedia *ifm, int m)
6184 {
6185 
6186 	ifmedia_add(ifm, m, 0, NULL);
6187 	ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
6188 	ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
6189 	ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
6190 }
6191 
6192 /*
6193  * This is the selected media, which is not quite the same as the active media.
6194  * The media line in ifconfig is "media: Ethernet selected (active)" if selected
6195  * and active are not the same, and "media: Ethernet selected" otherwise.
6196  */
6197 static void
6198 set_current_media(struct port_info *pi)
6199 {
6200 	struct link_config *lc;
6201 	struct ifmedia *ifm;
6202 	int mword;
6203 	u_int speed;
6204 
6205 	PORT_LOCK_ASSERT_OWNED(pi);
6206 
6207 	/* Leave current media alone if it's already set to IFM_NONE. */
6208 	ifm = &pi->media;
6209 	if (ifm->ifm_cur != NULL &&
6210 	    IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
6211 		return;
6212 
6213 	lc = &pi->link_cfg;
6214 	if (lc->requested_aneg != AUTONEG_DISABLE &&
6215 	    lc->pcaps & FW_PORT_CAP32_ANEG) {
6216 		ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
6217 		return;
6218 	}
6219 	mword = IFM_ETHER | IFM_FDX;
6220 	if (lc->requested_fc & PAUSE_TX)
6221 		mword |= IFM_ETH_TXPAUSE;
6222 	if (lc->requested_fc & PAUSE_RX)
6223 		mword |= IFM_ETH_RXPAUSE;
6224 	if (lc->requested_speed == 0)
6225 		speed = port_top_speed(pi) * 1000;	/* Gbps -> Mbps */
6226 	else
6227 		speed = lc->requested_speed;
6228 	mword |= port_mword(pi, speed_to_fwcap(speed));
6229 	ifmedia_set(ifm, mword);
6230 }
6231 
6232 /*
6233  * Returns true if the ifmedia list for the port cannot change.
6234  */
6235 static bool
6236 fixed_ifmedia(struct port_info *pi)
6237 {
6238 
6239 	return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
6240 	    pi->port_type == FW_PORT_TYPE_BT_XFI ||
6241 	    pi->port_type == FW_PORT_TYPE_BT_XAUI ||
6242 	    pi->port_type == FW_PORT_TYPE_KX4 ||
6243 	    pi->port_type == FW_PORT_TYPE_KX ||
6244 	    pi->port_type == FW_PORT_TYPE_KR ||
6245 	    pi->port_type == FW_PORT_TYPE_BP_AP ||
6246 	    pi->port_type == FW_PORT_TYPE_BP4_AP ||
6247 	    pi->port_type == FW_PORT_TYPE_BP40_BA ||
6248 	    pi->port_type == FW_PORT_TYPE_KR4_100G ||
6249 	    pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
6250 	    pi->port_type == FW_PORT_TYPE_KR_XLAUI);
6251 }
6252 
6253 static void
6254 build_medialist(struct port_info *pi)
6255 {
6256 	uint32_t ss, speed;
6257 	int unknown, mword, bit;
6258 	struct link_config *lc;
6259 	struct ifmedia *ifm;
6260 
6261 	PORT_LOCK_ASSERT_OWNED(pi);
6262 
6263 	if (pi->flags & FIXED_IFMEDIA)
6264 		return;
6265 
6266 	/*
6267 	 * Rebuild the ifmedia list.
6268 	 */
6269 	ifm = &pi->media;
6270 	ifmedia_removeall(ifm);
6271 	lc = &pi->link_cfg;
6272 	ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */
6273 	if (__predict_false(ss == 0)) {	/* not supposed to happen. */
6274 		MPASS(ss != 0);
6275 no_media:
6276 		MPASS(LIST_EMPTY(&ifm->ifm_list));
6277 		ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
6278 		ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
6279 		return;
6280 	}
6281 
6282 	unknown = 0;
6283 	for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
6284 		speed = 1 << bit;
6285 		MPASS(speed & M_FW_PORT_CAP32_SPEED);
6286 		if (ss & speed) {
6287 			mword = port_mword(pi, speed);
6288 			if (mword == IFM_NONE) {
6289 				goto no_media;
6290 			} else if (mword == IFM_UNKNOWN)
6291 				unknown++;
6292 			else
6293 				ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
6294 		}
6295 	}
6296 	if (unknown > 0) /* Add one unknown for all unknown media types. */
6297 		ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
6298 	if (lc->pcaps & FW_PORT_CAP32_ANEG)
6299 		ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
6300 
6301 	set_current_media(pi);
6302 }
6303 
6304 /*
6305  * Initialize the requested fields in the link config based on driver tunables.
6306  */
6307 static void
6308 init_link_config(struct port_info *pi)
6309 {
6310 	struct link_config *lc = &pi->link_cfg;
6311 
6312 	PORT_LOCK_ASSERT_OWNED(pi);
6313 
6314 	lc->requested_caps = 0;
6315 	lc->requested_speed = 0;
6316 
6317 	if (t4_autoneg == 0)
6318 		lc->requested_aneg = AUTONEG_DISABLE;
6319 	else if (t4_autoneg == 1)
6320 		lc->requested_aneg = AUTONEG_ENABLE;
6321 	else
6322 		lc->requested_aneg = AUTONEG_AUTO;
6323 
6324 	lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
6325 	    PAUSE_AUTONEG);
6326 
6327 	if (t4_fec & FEC_AUTO)
6328 		lc->requested_fec = FEC_AUTO;
6329 	else if (t4_fec == 0)
6330 		lc->requested_fec = FEC_NONE;
6331 	else {
6332 		/* -1 is handled by the FEC_AUTO block above and not here. */
6333 		lc->requested_fec = t4_fec &
6334 		    (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE);
6335 		if (lc->requested_fec == 0)
6336 			lc->requested_fec = FEC_AUTO;
6337 	}
6338 	if (t4_force_fec < 0)
6339 		lc->force_fec = -1;
6340 	else if (t4_force_fec > 0)
6341 		lc->force_fec = 1;
6342 	else
6343 		lc->force_fec = 0;
6344 }
6345 
6346 /*
6347  * Makes sure that all requested settings comply with what's supported by the
6348  * port.  Returns the number of settings that were invalid and had to be fixed.
6349  */
6350 static int
6351 fixup_link_config(struct port_info *pi)
6352 {
6353 	int n = 0;
6354 	struct link_config *lc = &pi->link_cfg;
6355 	uint32_t fwspeed;
6356 
6357 	PORT_LOCK_ASSERT_OWNED(pi);
6358 
6359 	/* Speed (when not autonegotiating) */
6360 	if (lc->requested_speed != 0) {
6361 		fwspeed = speed_to_fwcap(lc->requested_speed);
6362 		if ((fwspeed & lc->pcaps) == 0) {
6363 			n++;
6364 			lc->requested_speed = 0;
6365 		}
6366 	}
6367 
6368 	/* Link autonegotiation */
6369 	MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
6370 	    lc->requested_aneg == AUTONEG_DISABLE ||
6371 	    lc->requested_aneg == AUTONEG_AUTO);
6372 	if (lc->requested_aneg == AUTONEG_ENABLE &&
6373 	    !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
6374 		n++;
6375 		lc->requested_aneg = AUTONEG_AUTO;
6376 	}
6377 
6378 	/* Flow control */
6379 	MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
6380 	if (lc->requested_fc & PAUSE_TX &&
6381 	    !(lc->pcaps & FW_PORT_CAP32_FC_TX)) {
6382 		n++;
6383 		lc->requested_fc &= ~PAUSE_TX;
6384 	}
6385 	if (lc->requested_fc & PAUSE_RX &&
6386 	    !(lc->pcaps & FW_PORT_CAP32_FC_RX)) {
6387 		n++;
6388 		lc->requested_fc &= ~PAUSE_RX;
6389 	}
6390 	if (!(lc->requested_fc & PAUSE_AUTONEG) &&
6391 	    !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) {
6392 		n++;
6393 		lc->requested_fc |= PAUSE_AUTONEG;
6394 	}
6395 
6396 	/* FEC */
6397 	if ((lc->requested_fec & FEC_RS &&
6398 	    !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) ||
6399 	    (lc->requested_fec & FEC_BASER_RS &&
6400 	    !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) {
6401 		n++;
6402 		lc->requested_fec = FEC_AUTO;
6403 	}
6404 
6405 	return (n);
6406 }
6407 
6408 /*
6409  * Apply the requested L1 settings, which are expected to be valid, to the
6410  * hardware.
6411  */
6412 static int
6413 apply_link_config(struct port_info *pi)
6414 {
6415 	struct adapter *sc = pi->adapter;
6416 	struct link_config *lc = &pi->link_cfg;
6417 	int rc;
6418 
6419 #ifdef INVARIANTS
6420 	ASSERT_SYNCHRONIZED_OP(sc);
6421 	PORT_LOCK_ASSERT_OWNED(pi);
6422 
6423 	if (lc->requested_aneg == AUTONEG_ENABLE)
6424 		MPASS(lc->pcaps & FW_PORT_CAP32_ANEG);
6425 	if (!(lc->requested_fc & PAUSE_AUTONEG))
6426 		MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE);
6427 	if (lc->requested_fc & PAUSE_TX)
6428 		MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX);
6429 	if (lc->requested_fc & PAUSE_RX)
6430 		MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX);
6431 	if (lc->requested_fec & FEC_RS)
6432 		MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS);
6433 	if (lc->requested_fec & FEC_BASER_RS)
6434 		MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS);
6435 #endif
6436 	if (!(sc->flags & IS_VF)) {
6437 		rc = -t4_link_l1cfg(sc, sc->mbox, pi->hw_port, lc);
6438 		if (rc != 0) {
6439 			device_printf(pi->dev, "l1cfg failed: %d\n", rc);
6440 			return (rc);
6441 		}
6442 	}
6443 
6444 	/*
6445 	 * An L1_CFG will almost always result in a link-change event if the
6446 	 * link is up, and the driver will refresh the actual fec/fc/etc. when
6447 	 * the notification is processed.  If the link is down then the actual
6448 	 * settings are meaningless.
6449 	 *
6450 	 * This takes care of the case where a change in the L1 settings may not
6451 	 * result in a notification.
6452 	 */
6453 	if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
6454 		lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
6455 
6456 	return (0);
6457 }
6458 
6459 #define FW_MAC_EXACT_CHUNK	7
6460 struct mcaddr_ctx {
6461 	if_t ifp;
6462 	const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
6463 	uint64_t hash;
6464 	int i;
6465 	int del;
6466 	int rc;
6467 };
6468 
6469 static u_int
6470 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
6471 {
6472 	struct mcaddr_ctx *ctx = arg;
6473 	struct vi_info *vi = if_getsoftc(ctx->ifp);
6474 	struct port_info *pi = vi->pi;
6475 	struct adapter *sc = pi->adapter;
6476 
6477 	if (ctx->rc < 0)
6478 		return (0);
6479 
6480 	ctx->mcaddr[ctx->i] = LLADDR(sdl);
6481 	MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i]));
6482 	ctx->i++;
6483 
6484 	if (ctx->i == FW_MAC_EXACT_CHUNK) {
6485 		ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del,
6486 		    ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0);
6487 		if (ctx->rc < 0) {
6488 			int j;
6489 
6490 			for (j = 0; j < ctx->i; j++) {
6491 				if_printf(ctx->ifp,
6492 				    "failed to add mc address"
6493 				    " %02x:%02x:%02x:"
6494 				    "%02x:%02x:%02x rc=%d\n",
6495 				    ctx->mcaddr[j][0], ctx->mcaddr[j][1],
6496 				    ctx->mcaddr[j][2], ctx->mcaddr[j][3],
6497 				    ctx->mcaddr[j][4], ctx->mcaddr[j][5],
6498 				    -ctx->rc);
6499 			}
6500 			return (0);
6501 		}
6502 		ctx->del = 0;
6503 		ctx->i = 0;
6504 	}
6505 
6506 	return (1);
6507 }
6508 
6509 /*
6510  * Program the port's XGMAC based on parameters in ifnet.  The caller also
6511  * indicates which parameters should be programmed (the rest are left alone).
6512  */
6513 int
6514 update_mac_settings(if_t ifp, int flags)
6515 {
6516 	int rc = 0;
6517 	struct vi_info *vi = if_getsoftc(ifp);
6518 	struct port_info *pi = vi->pi;
6519 	struct adapter *sc = pi->adapter;
6520 	int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
6521 	uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
6522 
6523 	ASSERT_SYNCHRONIZED_OP(sc);
6524 	KASSERT(flags, ("%s: not told what to update.", __func__));
6525 
6526 	if (flags & XGMAC_MTU)
6527 		mtu = if_getmtu(ifp);
6528 
6529 	if (flags & XGMAC_PROMISC)
6530 		promisc = if_getflags(ifp) & IFF_PROMISC ? 1 : 0;
6531 
6532 	if (flags & XGMAC_ALLMULTI)
6533 		allmulti = if_getflags(ifp) & IFF_ALLMULTI ? 1 : 0;
6534 
6535 	if (flags & XGMAC_VLANEX)
6536 		vlanex = if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING ? 1 : 0;
6537 
6538 	if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
6539 		rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
6540 		    allmulti, 1, vlanex, false);
6541 		if (rc) {
6542 			if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
6543 			    rc);
6544 			return (rc);
6545 		}
6546 	}
6547 
6548 	if (flags & XGMAC_UCADDR) {
6549 		uint8_t ucaddr[ETHER_ADDR_LEN];
6550 
6551 		bcopy(if_getlladdr(ifp), ucaddr, sizeof(ucaddr));
6552 		rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
6553 		    ucaddr, true, &vi->smt_idx);
6554 		if (rc < 0) {
6555 			rc = -rc;
6556 			if_printf(ifp, "change_mac failed: %d\n", rc);
6557 			return (rc);
6558 		} else {
6559 			vi->xact_addr_filt = rc;
6560 			rc = 0;
6561 		}
6562 	}
6563 
6564 	if (flags & XGMAC_MCADDRS) {
6565 		struct epoch_tracker et;
6566 		struct mcaddr_ctx ctx;
6567 		int j;
6568 
6569 		ctx.ifp = ifp;
6570 		ctx.hash = 0;
6571 		ctx.i = 0;
6572 		ctx.del = 1;
6573 		ctx.rc = 0;
6574 		/*
6575 		 * Unlike other drivers, we accumulate list of pointers into
6576 		 * interface address lists and we need to keep it safe even
6577 		 * after if_foreach_llmaddr() returns, thus we must enter the
6578 		 * network epoch.
6579 		 */
6580 		NET_EPOCH_ENTER(et);
6581 		if_foreach_llmaddr(ifp, add_maddr, &ctx);
6582 		if (ctx.rc < 0) {
6583 			NET_EPOCH_EXIT(et);
6584 			rc = -ctx.rc;
6585 			return (rc);
6586 		}
6587 		if (ctx.i > 0) {
6588 			rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
6589 			    ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0);
6590 			NET_EPOCH_EXIT(et);
6591 			if (rc < 0) {
6592 				rc = -rc;
6593 				for (j = 0; j < ctx.i; j++) {
6594 					if_printf(ifp,
6595 					    "failed to add mcast address"
6596 					    " %02x:%02x:%02x:"
6597 					    "%02x:%02x:%02x rc=%d\n",
6598 					    ctx.mcaddr[j][0], ctx.mcaddr[j][1],
6599 					    ctx.mcaddr[j][2], ctx.mcaddr[j][3],
6600 					    ctx.mcaddr[j][4], ctx.mcaddr[j][5],
6601 					    rc);
6602 				}
6603 				return (rc);
6604 			}
6605 			ctx.del = 0;
6606 		} else
6607 			NET_EPOCH_EXIT(et);
6608 
6609 		rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0);
6610 		if (rc != 0)
6611 			if_printf(ifp, "failed to set mcast address hash: %d\n",
6612 			    rc);
6613 		if (ctx.del == 0) {
6614 			/* We clobbered the VXLAN entry if there was one. */
6615 			pi->vxlan_tcam_entry = false;
6616 		}
6617 	}
6618 
6619 	if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 &&
6620 	    pi->vxlan_tcam_entry == false) {
6621 		rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac,
6622 		    match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
6623 		    true);
6624 		if (rc < 0) {
6625 			rc = -rc;
6626 			if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n",
6627 			    rc);
6628 		} else {
6629 			MPASS(rc == sc->rawf_base + pi->port_id);
6630 			rc = 0;
6631 			pi->vxlan_tcam_entry = true;
6632 		}
6633 	}
6634 
6635 	return (rc);
6636 }
6637 
6638 /*
6639  * {begin|end}_synchronized_op must be called from the same thread.
6640  */
6641 int
6642 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
6643     char *wmesg)
6644 {
6645 	int rc;
6646 
6647 #ifdef WITNESS
6648 	/* the caller thinks it's ok to sleep, but is it really? */
6649 	if (flags & SLEEP_OK)
6650 		WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, __func__);
6651 #endif
6652 	ADAPTER_LOCK(sc);
6653 	for (;;) {
6654 
6655 		if (vi && IS_DETACHING(vi)) {
6656 			rc = ENXIO;
6657 			goto done;
6658 		}
6659 
6660 		if (!IS_BUSY(sc)) {
6661 			rc = 0;
6662 			break;
6663 		}
6664 
6665 		if (!(flags & SLEEP_OK)) {
6666 			rc = EBUSY;
6667 			goto done;
6668 		}
6669 
6670 		if (mtx_sleep(&sc->flags, &sc->sc_lock,
6671 		    flags & INTR_OK ? PCATCH : 0, wmesg, 0)) {
6672 			rc = EINTR;
6673 			goto done;
6674 		}
6675 	}
6676 
6677 	KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
6678 	SET_BUSY(sc);
6679 #ifdef INVARIANTS
6680 	sc->last_op = wmesg;
6681 	sc->last_op_thr = curthread;
6682 	sc->last_op_flags = flags;
6683 #endif
6684 
6685 done:
6686 	if (!(flags & HOLD_LOCK) || rc)
6687 		ADAPTER_UNLOCK(sc);
6688 
6689 	return (rc);
6690 }
6691 
6692 /*
6693  * Tell if_ioctl and if_init that the VI is going away.  This is
6694  * special variant of begin_synchronized_op and must be paired with a
6695  * call to end_vi_detach.
6696  */
6697 void
6698 begin_vi_detach(struct adapter *sc, struct vi_info *vi)
6699 {
6700 	ADAPTER_LOCK(sc);
6701 	SET_DETACHING(vi);
6702 	wakeup(&sc->flags);
6703 	while (IS_BUSY(sc))
6704 		mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
6705 	SET_BUSY(sc);
6706 #ifdef INVARIANTS
6707 	sc->last_op = "t4detach";
6708 	sc->last_op_thr = curthread;
6709 	sc->last_op_flags = 0;
6710 #endif
6711 	ADAPTER_UNLOCK(sc);
6712 }
6713 
6714 void
6715 end_vi_detach(struct adapter *sc, struct vi_info *vi)
6716 {
6717 	ADAPTER_LOCK(sc);
6718 	KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
6719 	CLR_BUSY(sc);
6720 	CLR_DETACHING(vi);
6721 	wakeup(&sc->flags);
6722 	ADAPTER_UNLOCK(sc);
6723 }
6724 
6725 /*
6726  * {begin|end}_synchronized_op must be called from the same thread.
6727  */
6728 void
6729 end_synchronized_op(struct adapter *sc, int flags)
6730 {
6731 
6732 	if (flags & LOCK_HELD)
6733 		ADAPTER_LOCK_ASSERT_OWNED(sc);
6734 	else
6735 		ADAPTER_LOCK(sc);
6736 
6737 	KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
6738 	CLR_BUSY(sc);
6739 	wakeup(&sc->flags);
6740 	ADAPTER_UNLOCK(sc);
6741 }
6742 
6743 static int
6744 cxgbe_init_synchronized(struct vi_info *vi)
6745 {
6746 	struct port_info *pi = vi->pi;
6747 	struct adapter *sc = pi->adapter;
6748 	if_t ifp = vi->ifp;
6749 	int rc = 0, i;
6750 	struct sge_txq *txq;
6751 
6752 	ASSERT_SYNCHRONIZED_OP(sc);
6753 
6754 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6755 		return (0);	/* already running */
6756 
6757 	if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0))
6758 		return (rc);	/* error message displayed already */
6759 
6760 	if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
6761 		return (rc); /* error message displayed already */
6762 
6763 	rc = update_mac_settings(ifp, XGMAC_ALL);
6764 	if (rc)
6765 		goto done;	/* error message displayed already */
6766 
6767 	PORT_LOCK(pi);
6768 	if (pi->up_vis == 0) {
6769 		t4_update_port_info(pi);
6770 		fixup_link_config(pi);
6771 		build_medialist(pi);
6772 		apply_link_config(pi);
6773 	}
6774 
6775 	rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
6776 	if (rc != 0) {
6777 		if_printf(ifp, "enable_vi failed: %d\n", rc);
6778 		PORT_UNLOCK(pi);
6779 		goto done;
6780 	}
6781 
6782 	/*
6783 	 * Can't fail from this point onwards.  Review cxgbe_uninit_synchronized
6784 	 * if this changes.
6785 	 */
6786 
6787 	for_each_txq(vi, i, txq) {
6788 		TXQ_LOCK(txq);
6789 		txq->eq.flags |= EQ_ENABLED;
6790 		TXQ_UNLOCK(txq);
6791 	}
6792 
6793 	/*
6794 	 * The first iq of the first port to come up is used for tracing.
6795 	 */
6796 	if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
6797 		sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
6798 		t4_set_trace_rss_control(sc, pi->tx_chan, sc->traceq);
6799 		pi->flags |= HAS_TRACEQ;
6800 	}
6801 
6802 	/* all ok */
6803 	pi->up_vis++;
6804 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
6805 	if (pi->link_cfg.link_ok)
6806 		t4_os_link_changed(pi);
6807 	PORT_UNLOCK(pi);
6808 
6809 	mtx_lock(&vi->tick_mtx);
6810 	if (vi->pi->nvi > 1 || sc->flags & IS_VF)
6811 		callout_reset(&vi->tick, hz, vi_tick, vi);
6812 	else
6813 		callout_reset(&vi->tick, hz, cxgbe_tick, vi);
6814 	mtx_unlock(&vi->tick_mtx);
6815 done:
6816 	if (rc != 0)
6817 		cxgbe_uninit_synchronized(vi);
6818 
6819 	return (rc);
6820 }
6821 
6822 /*
6823  * Idempotent.
6824  */
6825 static int
6826 cxgbe_uninit_synchronized(struct vi_info *vi)
6827 {
6828 	struct port_info *pi = vi->pi;
6829 	struct adapter *sc = pi->adapter;
6830 	if_t ifp = vi->ifp;
6831 	int rc, i;
6832 	struct sge_txq *txq;
6833 
6834 	ASSERT_SYNCHRONIZED_OP(sc);
6835 
6836 	if (!(vi->flags & VI_INIT_DONE)) {
6837 		if (__predict_false(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
6838 			KASSERT(0, ("uninited VI is running"));
6839 			if_printf(ifp, "uninited VI with running ifnet.  "
6840 			    "vi->flags 0x%016lx, if_flags 0x%08x, "
6841 			    "if_drv_flags 0x%08x\n", vi->flags, if_getflags(ifp),
6842 			    if_getdrvflags(ifp));
6843 		}
6844 		return (0);
6845 	}
6846 
6847 	/*
6848 	 * Disable the VI so that all its data in either direction is discarded
6849 	 * by the MPS.  Leave everything else (the queues, interrupts, and 1Hz
6850 	 * tick) intact as the TP can deliver negative advice or data that it's
6851 	 * holding in its RAM (for an offloaded connection) even after the VI is
6852 	 * disabled.
6853 	 */
6854 	rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
6855 	if (rc) {
6856 		if_printf(ifp, "disable_vi failed: %d\n", rc);
6857 		return (rc);
6858 	}
6859 
6860 	for_each_txq(vi, i, txq) {
6861 		TXQ_LOCK(txq);
6862 		txq->eq.flags &= ~EQ_ENABLED;
6863 		TXQ_UNLOCK(txq);
6864 	}
6865 
6866 	mtx_lock(&vi->tick_mtx);
6867 	callout_stop(&vi->tick);
6868 	mtx_unlock(&vi->tick_mtx);
6869 
6870 	PORT_LOCK(pi);
6871 	if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
6872 		PORT_UNLOCK(pi);
6873 		return (0);
6874 	}
6875 	if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
6876 	pi->up_vis--;
6877 	if (pi->up_vis > 0) {
6878 		PORT_UNLOCK(pi);
6879 		return (0);
6880 	}
6881 
6882 	pi->link_cfg.link_ok = false;
6883 	pi->link_cfg.speed = 0;
6884 	pi->link_cfg.link_down_rc = 255;
6885 	t4_os_link_changed(pi);
6886 	PORT_UNLOCK(pi);
6887 
6888 	return (0);
6889 }
6890 
6891 /*
6892  * It is ok for this function to fail midway and return right away.  t4_detach
6893  * will walk the entire sc->irq list and clean up whatever is valid.
6894  */
6895 int
6896 t4_setup_intr_handlers(struct adapter *sc)
6897 {
6898 	int rc, rid, p, q, v;
6899 	char s[8];
6900 	struct irq *irq;
6901 	struct port_info *pi;
6902 	struct vi_info *vi;
6903 	struct sge *sge = &sc->sge;
6904 	struct sge_rxq *rxq;
6905 #ifdef TCP_OFFLOAD
6906 	struct sge_ofld_rxq *ofld_rxq;
6907 #endif
6908 #ifdef DEV_NETMAP
6909 	struct sge_nm_rxq *nm_rxq;
6910 #endif
6911 #ifdef RSS
6912 	int nbuckets = rss_getnumbuckets();
6913 #endif
6914 
6915 	/*
6916 	 * Setup interrupts.
6917 	 */
6918 	irq = &sc->irq[0];
6919 	rid = sc->intr_type == INTR_INTX ? 0 : 1;
6920 	if (forwarding_intr_to_fwq(sc))
6921 		return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
6922 
6923 	/* Multiple interrupts. */
6924 	if (sc->flags & IS_VF)
6925 		KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
6926 		    ("%s: too few intr.", __func__));
6927 	else
6928 		KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
6929 		    ("%s: too few intr.", __func__));
6930 
6931 	/* The first one is always error intr on PFs */
6932 	if (!(sc->flags & IS_VF)) {
6933 		rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
6934 		if (rc != 0)
6935 			return (rc);
6936 		irq++;
6937 		rid++;
6938 	}
6939 
6940 	/* The second one is always the firmware event queue (first on VFs) */
6941 	rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
6942 	if (rc != 0)
6943 		return (rc);
6944 	irq++;
6945 	rid++;
6946 
6947 	for_each_port(sc, p) {
6948 		pi = sc->port[p];
6949 		for_each_vi(pi, v, vi) {
6950 			vi->first_intr = rid - 1;
6951 
6952 			if (vi->nnmrxq > 0) {
6953 				int n = max(vi->nrxq, vi->nnmrxq);
6954 
6955 				rxq = &sge->rxq[vi->first_rxq];
6956 #ifdef DEV_NETMAP
6957 				nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
6958 #endif
6959 				for (q = 0; q < n; q++) {
6960 					snprintf(s, sizeof(s), "%x%c%x", p,
6961 					    'a' + v, q);
6962 					if (q < vi->nrxq)
6963 						irq->rxq = rxq++;
6964 #ifdef DEV_NETMAP
6965 					if (q < vi->nnmrxq)
6966 						irq->nm_rxq = nm_rxq++;
6967 
6968 					if (irq->nm_rxq != NULL &&
6969 					    irq->rxq == NULL) {
6970 						/* Netmap rx only */
6971 						rc = t4_alloc_irq(sc, irq, rid,
6972 						    t4_nm_intr, irq->nm_rxq, s);
6973 					}
6974 					if (irq->nm_rxq != NULL &&
6975 					    irq->rxq != NULL) {
6976 						/* NIC and Netmap rx */
6977 						rc = t4_alloc_irq(sc, irq, rid,
6978 						    t4_vi_intr, irq, s);
6979 					}
6980 #endif
6981 					if (irq->rxq != NULL &&
6982 					    irq->nm_rxq == NULL) {
6983 						/* NIC rx only */
6984 						rc = t4_alloc_irq(sc, irq, rid,
6985 						    t4_intr, irq->rxq, s);
6986 					}
6987 					if (rc != 0)
6988 						return (rc);
6989 #ifdef RSS
6990 					if (q < vi->nrxq) {
6991 						bus_bind_intr(sc->dev, irq->res,
6992 						    rss_getcpu(q % nbuckets));
6993 					}
6994 #endif
6995 					irq++;
6996 					rid++;
6997 					vi->nintr++;
6998 				}
6999 			} else {
7000 				for_each_rxq(vi, q, rxq) {
7001 					snprintf(s, sizeof(s), "%x%c%x", p,
7002 					    'a' + v, q);
7003 					rc = t4_alloc_irq(sc, irq, rid,
7004 					    t4_intr, rxq, s);
7005 					if (rc != 0)
7006 						return (rc);
7007 #ifdef RSS
7008 					bus_bind_intr(sc->dev, irq->res,
7009 					    rss_getcpu(q % nbuckets));
7010 #endif
7011 					irq++;
7012 					rid++;
7013 					vi->nintr++;
7014 				}
7015 			}
7016 #ifdef TCP_OFFLOAD
7017 			for_each_ofld_rxq(vi, q, ofld_rxq) {
7018 				snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
7019 				rc = t4_alloc_irq(sc, irq, rid, t4_intr,
7020 				    ofld_rxq, s);
7021 				if (rc != 0)
7022 					return (rc);
7023 				irq++;
7024 				rid++;
7025 				vi->nintr++;
7026 			}
7027 #endif
7028 		}
7029 	}
7030 	MPASS(irq == &sc->irq[sc->intr_count]);
7031 
7032 	return (0);
7033 }
7034 
7035 static void
7036 write_global_rss_key(struct adapter *sc)
7037 {
7038 #ifdef RSS
7039 	int i;
7040 	uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
7041 	uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
7042 
7043 	CTASSERT(RSS_KEYSIZE == 40);
7044 
7045 	rss_getkey((void *)&raw_rss_key[0]);
7046 	for (i = 0; i < nitems(rss_key); i++) {
7047 		rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
7048 	}
7049 	t4_write_rss_key(sc, &rss_key[0], -1, 1);
7050 #endif
7051 }
7052 
7053 /*
7054  * Idempotent.
7055  */
7056 static int
7057 adapter_full_init(struct adapter *sc)
7058 {
7059 	int rc, i;
7060 
7061 	ASSERT_SYNCHRONIZED_OP(sc);
7062 
7063 	/*
7064 	 * queues that belong to the adapter (not any particular port).
7065 	 */
7066 	rc = t4_setup_adapter_queues(sc);
7067 	if (rc != 0)
7068 		return (rc);
7069 
7070 	MPASS(sc->params.nports <= nitems(sc->tq));
7071 	for (i = 0; i < sc->params.nports; i++) {
7072 		if (sc->tq[i] != NULL)
7073 			continue;
7074 		sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
7075 		    taskqueue_thread_enqueue, &sc->tq[i]);
7076 		if (sc->tq[i] == NULL) {
7077 			CH_ERR(sc, "failed to allocate task queue %d\n", i);
7078 			return (ENOMEM);
7079 		}
7080 		taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
7081 		    device_get_nameunit(sc->dev), i);
7082 	}
7083 
7084 	if (!(sc->flags & IS_VF)) {
7085 		write_global_rss_key(sc);
7086 		t4_intr_enable(sc);
7087 	}
7088 	return (0);
7089 }
7090 
7091 int
7092 adapter_init(struct adapter *sc)
7093 {
7094 	int rc;
7095 
7096 	ASSERT_SYNCHRONIZED_OP(sc);
7097 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
7098 	KASSERT((sc->flags & FULL_INIT_DONE) == 0,
7099 	    ("%s: FULL_INIT_DONE already", __func__));
7100 
7101 	rc = adapter_full_init(sc);
7102 	if (rc != 0)
7103 		adapter_full_uninit(sc);
7104 	else
7105 		sc->flags |= FULL_INIT_DONE;
7106 
7107 	return (rc);
7108 }
7109 
7110 /*
7111  * Idempotent.
7112  */
7113 static void
7114 adapter_full_uninit(struct adapter *sc)
7115 {
7116 	int i;
7117 
7118 	t4_teardown_adapter_queues(sc);
7119 
7120 	for (i = 0; i < nitems(sc->tq); i++) {
7121 		if (sc->tq[i] == NULL)
7122 			continue;
7123 		taskqueue_free(sc->tq[i]);
7124 		sc->tq[i] = NULL;
7125 	}
7126 
7127 	sc->flags &= ~FULL_INIT_DONE;
7128 }
7129 
7130 #ifdef RSS
7131 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
7132     RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
7133     RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
7134     RSS_HASHTYPE_RSS_UDP_IPV6)
7135 
7136 /* Translates kernel hash types to hardware. */
7137 static int
7138 hashconfig_to_hashen(int hashconfig)
7139 {
7140 	int hashen = 0;
7141 
7142 	if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
7143 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
7144 	if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
7145 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
7146 	if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
7147 		hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
7148 		    F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
7149 	}
7150 	if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
7151 		hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
7152 		    F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
7153 	}
7154 	if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
7155 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
7156 	if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
7157 		hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
7158 
7159 	return (hashen);
7160 }
7161 
7162 /* Translates hardware hash types to kernel. */
7163 static int
7164 hashen_to_hashconfig(int hashen)
7165 {
7166 	int hashconfig = 0;
7167 
7168 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
7169 		/*
7170 		 * If UDP hashing was enabled it must have been enabled for
7171 		 * either IPv4 or IPv6 (inclusive or).  Enabling UDP without
7172 		 * enabling any 4-tuple hash is nonsense configuration.
7173 		 */
7174 		MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
7175 		    F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
7176 
7177 		if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
7178 			hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
7179 		if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
7180 			hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
7181 	}
7182 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
7183 		hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
7184 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
7185 		hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
7186 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
7187 		hashconfig |= RSS_HASHTYPE_RSS_IPV4;
7188 	if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
7189 		hashconfig |= RSS_HASHTYPE_RSS_IPV6;
7190 
7191 	return (hashconfig);
7192 }
7193 #endif
7194 
7195 /*
7196  * Idempotent.
7197  */
7198 static int
7199 vi_full_init(struct vi_info *vi)
7200 {
7201 	struct adapter *sc = vi->adapter;
7202 	struct sge_rxq *rxq;
7203 	int rc, i, j;
7204 #ifdef RSS
7205 	int nbuckets = rss_getnumbuckets();
7206 	int hashconfig = rss_gethashconfig();
7207 	int extra;
7208 #endif
7209 
7210 	ASSERT_SYNCHRONIZED_OP(sc);
7211 
7212 	/*
7213 	 * Allocate tx/rx/fl queues for this VI.
7214 	 */
7215 	rc = t4_setup_vi_queues(vi);
7216 	if (rc != 0)
7217 		return (rc);
7218 
7219 	/*
7220 	 * Setup RSS for this VI.  Save a copy of the RSS table for later use.
7221 	 */
7222 	if (vi->nrxq > vi->rss_size) {
7223 		CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); "
7224 		    "some queues will never receive traffic.\n", vi->nrxq,
7225 		    vi->rss_size);
7226 	} else if (vi->rss_size % vi->nrxq) {
7227 		CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); "
7228 		    "expect uneven traffic distribution.\n", vi->nrxq,
7229 		    vi->rss_size);
7230 	}
7231 #ifdef RSS
7232 	if (vi->nrxq != nbuckets) {
7233 		CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);"
7234 		    "performance will be impacted.\n", vi->nrxq, nbuckets);
7235 	}
7236 #endif
7237 	if (vi->rss == NULL)
7238 		vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE,
7239 		    M_ZERO | M_WAITOK);
7240 	for (i = 0; i < vi->rss_size;) {
7241 #ifdef RSS
7242 		j = rss_get_indirection_to_bucket(i);
7243 		j %= vi->nrxq;
7244 		rxq = &sc->sge.rxq[vi->first_rxq + j];
7245 		vi->rss[i++] = rxq->iq.abs_id;
7246 #else
7247 		for_each_rxq(vi, j, rxq) {
7248 			vi->rss[i++] = rxq->iq.abs_id;
7249 			if (i == vi->rss_size)
7250 				break;
7251 		}
7252 #endif
7253 	}
7254 
7255 	rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
7256 	    vi->rss, vi->rss_size);
7257 	if (rc != 0) {
7258 		CH_ERR(vi, "rss_config failed: %d\n", rc);
7259 		return (rc);
7260 	}
7261 
7262 #ifdef RSS
7263 	vi->hashen = hashconfig_to_hashen(hashconfig);
7264 
7265 	/*
7266 	 * We may have had to enable some hashes even though the global config
7267 	 * wants them disabled.  This is a potential problem that must be
7268 	 * reported to the user.
7269 	 */
7270 	extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
7271 
7272 	/*
7273 	 * If we consider only the supported hash types, then the enabled hashes
7274 	 * are a superset of the requested hashes.  In other words, there cannot
7275 	 * be any supported hash that was requested but not enabled, but there
7276 	 * can be hashes that were not requested but had to be enabled.
7277 	 */
7278 	extra &= SUPPORTED_RSS_HASHTYPES;
7279 	MPASS((extra & hashconfig) == 0);
7280 
7281 	if (extra) {
7282 		CH_ALERT(vi,
7283 		    "global RSS config (0x%x) cannot be accommodated.\n",
7284 		    hashconfig);
7285 	}
7286 	if (extra & RSS_HASHTYPE_RSS_IPV4)
7287 		CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n");
7288 	if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
7289 		CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n");
7290 	if (extra & RSS_HASHTYPE_RSS_IPV6)
7291 		CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n");
7292 	if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
7293 		CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n");
7294 	if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
7295 		CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n");
7296 	if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
7297 		CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n");
7298 #else
7299 	vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
7300 	    F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
7301 	    F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
7302 	    F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
7303 #endif
7304 	rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0],
7305 	    0, 0);
7306 	if (rc != 0) {
7307 		CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc);
7308 		return (rc);
7309 	}
7310 
7311 	return (0);
7312 }
7313 
7314 int
7315 vi_init(struct vi_info *vi)
7316 {
7317 	int rc;
7318 
7319 	ASSERT_SYNCHRONIZED_OP(vi->adapter);
7320 	KASSERT((vi->flags & VI_INIT_DONE) == 0,
7321 	    ("%s: VI_INIT_DONE already", __func__));
7322 
7323 	rc = vi_full_init(vi);
7324 	if (rc != 0)
7325 		vi_full_uninit(vi);
7326 	else
7327 		vi->flags |= VI_INIT_DONE;
7328 
7329 	return (rc);
7330 }
7331 
7332 /*
7333  * Idempotent.
7334  */
7335 static void
7336 vi_full_uninit(struct vi_info *vi)
7337 {
7338 
7339 	if (vi->flags & VI_INIT_DONE) {
7340 		quiesce_vi(vi);
7341 		free(vi->rss, M_CXGBE);
7342 		free(vi->nm_rss, M_CXGBE);
7343 	}
7344 
7345 	t4_teardown_vi_queues(vi);
7346 	vi->flags &= ~VI_INIT_DONE;
7347 }
7348 
7349 static void
7350 quiesce_txq(struct sge_txq *txq)
7351 {
7352 	struct sge_eq *eq = &txq->eq;
7353 	struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
7354 
7355 	MPASS(eq->flags & EQ_SW_ALLOCATED);
7356 	MPASS(!(eq->flags & EQ_ENABLED));
7357 
7358 	/* Wait for the mp_ring to empty. */
7359 	while (!mp_ring_is_idle(txq->r)) {
7360 		mp_ring_check_drainage(txq->r, 4096);
7361 		pause("rquiesce", 1);
7362 	}
7363 	MPASS(txq->txp.npkt == 0);
7364 
7365 	if (eq->flags & EQ_HW_ALLOCATED) {
7366 		/*
7367 		 * Hardware is alive and working normally.  Wait for it to
7368 		 * finish and then wait for the driver to catch up and reclaim
7369 		 * all descriptors.
7370 		 */
7371 		while (spg->cidx != htobe16(eq->pidx))
7372 			pause("equiesce", 1);
7373 		while (eq->cidx != eq->pidx)
7374 			pause("dquiesce", 1);
7375 	} else {
7376 		/*
7377 		 * Hardware is unavailable.  Discard all pending tx and reclaim
7378 		 * descriptors directly.
7379 		 */
7380 		TXQ_LOCK(txq);
7381 		while (eq->cidx != eq->pidx) {
7382 			struct mbuf *m, *nextpkt;
7383 			struct tx_sdesc *txsd;
7384 
7385 			txsd = &txq->sdesc[eq->cidx];
7386 			for (m = txsd->m; m != NULL; m = nextpkt) {
7387 				nextpkt = m->m_nextpkt;
7388 				m->m_nextpkt = NULL;
7389 				m_freem(m);
7390 			}
7391 			IDXINCR(eq->cidx, txsd->desc_used, eq->sidx);
7392 		}
7393 		spg->pidx = spg->cidx = htobe16(eq->cidx);
7394 		TXQ_UNLOCK(txq);
7395 	}
7396 }
7397 
7398 static void
7399 quiesce_wrq(struct sge_wrq *wrq)
7400 {
7401 	struct wrqe *wr;
7402 
7403 	TXQ_LOCK(wrq);
7404 	while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) {
7405 		STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
7406 #ifdef INVARIANTS
7407 		wrq->nwr_pending--;
7408 		wrq->ndesc_needed -= howmany(wr->wr_len, EQ_ESIZE);
7409 #endif
7410 		free(wr, M_CXGBE);
7411 	}
7412 	MPASS(wrq->nwr_pending == 0);
7413 	MPASS(wrq->ndesc_needed == 0);
7414 	wrq->nwr_pending = 0;
7415 	wrq->ndesc_needed = 0;
7416 	TXQ_UNLOCK(wrq);
7417 }
7418 
7419 static void
7420 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
7421 {
7422 	/* Synchronize with the interrupt handler */
7423 	while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
7424 		pause("iqfree", 1);
7425 
7426 	if (fl != NULL) {
7427 		MPASS(iq->flags & IQ_HAS_FL);
7428 
7429 		mtx_lock(&sc->sfl_lock);
7430 		FL_LOCK(fl);
7431 		fl->flags |= FL_DOOMED;
7432 		FL_UNLOCK(fl);
7433 		callout_stop(&sc->sfl_callout);
7434 		mtx_unlock(&sc->sfl_lock);
7435 
7436 		KASSERT((fl->flags & FL_STARVING) == 0,
7437 		    ("%s: still starving", __func__));
7438 
7439 		/* Release all buffers if hardware is no longer available. */
7440 		if (!(iq->flags & IQ_HW_ALLOCATED))
7441 			free_fl_buffers(sc, fl);
7442 	}
7443 }
7444 
7445 /*
7446  * Wait for all activity on all the queues of the VI to complete.  It is assumed
7447  * that no new work is being enqueued by the hardware or the driver.  That part
7448  * should be arranged before calling this function.
7449  */
7450 static void
7451 quiesce_vi(struct vi_info *vi)
7452 {
7453 	int i;
7454 	struct adapter *sc = vi->adapter;
7455 	struct sge_rxq *rxq;
7456 	struct sge_txq *txq;
7457 #ifdef TCP_OFFLOAD
7458 	struct sge_ofld_rxq *ofld_rxq;
7459 #endif
7460 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7461 	struct sge_ofld_txq *ofld_txq;
7462 #endif
7463 
7464 	if (!(vi->flags & VI_INIT_DONE))
7465 		return;
7466 
7467 	for_each_txq(vi, i, txq) {
7468 		quiesce_txq(txq);
7469 	}
7470 
7471 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7472 	for_each_ofld_txq(vi, i, ofld_txq) {
7473 		quiesce_wrq(&ofld_txq->wrq);
7474 	}
7475 #endif
7476 
7477 	for_each_rxq(vi, i, rxq) {
7478 		quiesce_iq_fl(sc, &rxq->iq, &rxq->fl);
7479 	}
7480 
7481 #ifdef TCP_OFFLOAD
7482 	for_each_ofld_rxq(vi, i, ofld_rxq) {
7483 		quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl);
7484 	}
7485 #endif
7486 }
7487 
7488 static int
7489 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
7490     driver_intr_t *handler, void *arg, char *name)
7491 {
7492 	int rc;
7493 
7494 	irq->rid = rid;
7495 	irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
7496 	    RF_SHAREABLE | RF_ACTIVE);
7497 	if (irq->res == NULL) {
7498 		device_printf(sc->dev,
7499 		    "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
7500 		return (ENOMEM);
7501 	}
7502 
7503 	rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
7504 	    NULL, handler, arg, &irq->tag);
7505 	if (rc != 0) {
7506 		device_printf(sc->dev,
7507 		    "failed to setup interrupt for rid %d, name %s: %d\n",
7508 		    rid, name, rc);
7509 	} else if (name)
7510 		bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
7511 
7512 	return (rc);
7513 }
7514 
7515 static int
7516 t4_free_irq(struct adapter *sc, struct irq *irq)
7517 {
7518 	if (irq->tag)
7519 		bus_teardown_intr(sc->dev, irq->res, irq->tag);
7520 	if (irq->res)
7521 		bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
7522 
7523 	bzero(irq, sizeof(*irq));
7524 
7525 	return (0);
7526 }
7527 
7528 static void
7529 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
7530 {
7531 
7532 	regs->version = chip_id(sc) | chip_rev(sc) << 10;
7533 	t4_get_regs(sc, buf, regs->len);
7534 }
7535 
7536 #define	A_PL_INDIR_CMD	0x1f8
7537 
7538 #define	S_PL_AUTOINC	31
7539 #define	M_PL_AUTOINC	0x1U
7540 #define	V_PL_AUTOINC(x)	((x) << S_PL_AUTOINC)
7541 #define	G_PL_AUTOINC(x)	(((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
7542 
7543 #define	S_PL_VFID	20
7544 #define	M_PL_VFID	0xffU
7545 #define	V_PL_VFID(x)	((x) << S_PL_VFID)
7546 #define	G_PL_VFID(x)	(((x) >> S_PL_VFID) & M_PL_VFID)
7547 
7548 #define	S_PL_ADDR	0
7549 #define	M_PL_ADDR	0xfffffU
7550 #define	V_PL_ADDR(x)	((x) << S_PL_ADDR)
7551 #define	G_PL_ADDR(x)	(((x) >> S_PL_ADDR) & M_PL_ADDR)
7552 
7553 #define	A_PL_INDIR_DATA	0x1fc
7554 
7555 static uint64_t
7556 read_vf_stat(struct adapter *sc, u_int vin, int reg)
7557 {
7558 	u32 stats[2];
7559 
7560 	if (sc->flags & IS_VF) {
7561 		stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
7562 		stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
7563 	} else {
7564 		mtx_assert(&sc->reg_lock, MA_OWNED);
7565 		t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
7566 		    V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));
7567 		stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
7568 		stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
7569 	}
7570 	return (((uint64_t)stats[1]) << 32 | stats[0]);
7571 }
7572 
7573 static void
7574 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats)
7575 {
7576 
7577 #define GET_STAT(name) \
7578 	read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L)
7579 
7580 	if (!(sc->flags & IS_VF))
7581 		mtx_lock(&sc->reg_lock);
7582 	stats->tx_bcast_bytes    = GET_STAT(TX_VF_BCAST_BYTES);
7583 	stats->tx_bcast_frames   = GET_STAT(TX_VF_BCAST_FRAMES);
7584 	stats->tx_mcast_bytes    = GET_STAT(TX_VF_MCAST_BYTES);
7585 	stats->tx_mcast_frames   = GET_STAT(TX_VF_MCAST_FRAMES);
7586 	stats->tx_ucast_bytes    = GET_STAT(TX_VF_UCAST_BYTES);
7587 	stats->tx_ucast_frames   = GET_STAT(TX_VF_UCAST_FRAMES);
7588 	stats->tx_drop_frames    = GET_STAT(TX_VF_DROP_FRAMES);
7589 	stats->tx_offload_bytes  = GET_STAT(TX_VF_OFFLOAD_BYTES);
7590 	stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
7591 	stats->rx_bcast_bytes    = GET_STAT(RX_VF_BCAST_BYTES);
7592 	stats->rx_bcast_frames   = GET_STAT(RX_VF_BCAST_FRAMES);
7593 	stats->rx_mcast_bytes    = GET_STAT(RX_VF_MCAST_BYTES);
7594 	stats->rx_mcast_frames   = GET_STAT(RX_VF_MCAST_FRAMES);
7595 	stats->rx_ucast_bytes    = GET_STAT(RX_VF_UCAST_BYTES);
7596 	stats->rx_ucast_frames   = GET_STAT(RX_VF_UCAST_FRAMES);
7597 	stats->rx_err_frames     = GET_STAT(RX_VF_ERR_FRAMES);
7598 	if (!(sc->flags & IS_VF))
7599 		mtx_unlock(&sc->reg_lock);
7600 
7601 #undef GET_STAT
7602 }
7603 
7604 static void
7605 t4_clr_vi_stats(struct adapter *sc, u_int vin)
7606 {
7607 	int reg;
7608 
7609 	t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) |
7610 	    V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
7611 	for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
7612 	     reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
7613 		t4_write_reg(sc, A_PL_INDIR_DATA, 0);
7614 }
7615 
7616 static void
7617 vi_refresh_stats(struct vi_info *vi)
7618 {
7619 	struct timeval tv;
7620 	const struct timeval interval = {0, 250000};	/* 250ms */
7621 
7622 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7623 
7624 	if (vi->flags & VI_SKIP_STATS)
7625 		return;
7626 
7627 	getmicrotime(&tv);
7628 	timevalsub(&tv, &interval);
7629 	if (timevalcmp(&tv, &vi->last_refreshed, <))
7630 		return;
7631 
7632 	t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats);
7633 	getmicrotime(&vi->last_refreshed);
7634 }
7635 
7636 static void
7637 cxgbe_refresh_stats(struct vi_info *vi)
7638 {
7639 	u_int i, v, tnl_cong_drops, chan_map;
7640 	struct timeval tv;
7641 	const struct timeval interval = {0, 250000};	/* 250ms */
7642 	struct port_info *pi;
7643 	struct adapter *sc;
7644 
7645 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7646 
7647 	if (vi->flags & VI_SKIP_STATS)
7648 		return;
7649 
7650 	getmicrotime(&tv);
7651 	timevalsub(&tv, &interval);
7652 	if (timevalcmp(&tv, &vi->last_refreshed, <))
7653 		return;
7654 
7655 	pi = vi->pi;
7656 	sc = vi->adapter;
7657 	tnl_cong_drops = 0;
7658 	t4_get_port_stats(sc, pi->hw_port, &pi->stats);
7659 	chan_map = pi->rx_e_chan_map;
7660 	while (chan_map) {
7661 		i = ffs(chan_map) - 1;
7662 		mtx_lock(&sc->reg_lock);
7663 		t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
7664 		    A_TP_MIB_TNL_CNG_DROP_0 + i);
7665 		mtx_unlock(&sc->reg_lock);
7666 		tnl_cong_drops += v;
7667 		chan_map &= ~(1 << i);
7668 	}
7669 	pi->tnl_cong_drops = tnl_cong_drops;
7670 	getmicrotime(&vi->last_refreshed);
7671 }
7672 
7673 static void
7674 cxgbe_tick(void *arg)
7675 {
7676 	struct vi_info *vi = arg;
7677 
7678 	MPASS(IS_MAIN_VI(vi));
7679 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7680 
7681 	cxgbe_refresh_stats(vi);
7682 	callout_schedule(&vi->tick, hz);
7683 }
7684 
7685 static void
7686 vi_tick(void *arg)
7687 {
7688 	struct vi_info *vi = arg;
7689 
7690 	mtx_assert(&vi->tick_mtx, MA_OWNED);
7691 
7692 	vi_refresh_stats(vi);
7693 	callout_schedule(&vi->tick, hz);
7694 }
7695 
7696 /* CIM inbound queues */
7697 static const char *t4_ibq[CIM_NUM_IBQ] = {
7698 	"ibq_tp0", "ibq_tp1", "ibq_ulp", "ibq_sge0", "ibq_sge1", "ibq_ncsi"
7699 };
7700 static const char *t7_ibq[CIM_NUM_IBQ_T7] = {
7701 	"ibq_tp0", "ibq_tp1", "ibq_tp2", "ibq_tp3", "ibq_ulp", "ibq_sge0",
7702 	"ibq_sge1", "ibq_ncsi", NULL, "ibq_ipc1", "ibq_ipc2", "ibq_ipc3",
7703 	"ibq_ipc4", "ibq_ipc5", "ibq_ipc6", "ibq_ipc7"
7704 };
7705 static const char *t7_ibq_sec[] = {
7706 	"ibq_tp0", "ibq_tp1", "ibq_tp2", "ibq_tp3", "ibq_ulp", "ibq_sge0",
7707 	NULL, NULL, NULL, "ibq_ipc0"
7708 };
7709 
7710 /* CIM outbound queues */
7711 static const char *t4_obq[CIM_NUM_OBQ_T5] = {
7712 	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", "obq_ncsi",
7713 	"obq_sge_rx_q0", "obq_sge_rx_q1" /* These two are T5/T6 only */
7714 };
7715 static const char *t7_obq[CIM_NUM_OBQ_T7] = {
7716 	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", "obq_ncsi",
7717 	"obq_sge_rx_q0", NULL, NULL, "obq_ipc1", "obq_ipc2", "obq_ipc3",
7718 	"obq_ipc4", "obq_ipc5", "obq_ipc6", "obq_ipc7"
7719 };
7720 static const char *t7_obq_sec[] = {
7721 	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", NULL,
7722 	"obq_sge_rx_q0", NULL, NULL, "obq_ipc0"
7723 };
7724 
7725 static void
7726 cim_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
7727     struct sysctl_oid_list *c0)
7728 {
7729 	struct sysctl_oid *oid;
7730 	struct sysctl_oid_list *children1;
7731 	int i, j, qcount;
7732 	char s[16];
7733 	const char **qname;
7734 
7735 	oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "cim",
7736 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CIM block");
7737 	c0 = SYSCTL_CHILDREN(oid);
7738 
7739 	SYSCTL_ADD_U8(ctx, c0, OID_AUTO, "ncores", CTLFLAG_RD, NULL,
7740 	    sc->params.ncores, "# of active CIM cores");
7741 
7742 	for (i = 0; i < sc->params.ncores; i++) {
7743 		snprintf(s, sizeof(s), "%u", i);
7744 		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, s,
7745 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CIM core");
7746 		children1 = SYSCTL_CHILDREN(oid);
7747 
7748 		/*
7749 		 * CTLFLAG_SKIP because the misc.devlog sysctl already displays
7750 		 * the log for all cores.  Use this sysctl to get the log for a
7751 		 * particular core only.
7752 		 */
7753 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "devlog",
7754 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
7755 		    sc, i, sysctl_devlog, "A", "firmware's device log");
7756 
7757 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "loadavg",
7758 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7759 		    sysctl_loadavg, "A",
7760 		    "microprocessor load averages (select firmwares only)");
7761 
7762 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "qcfg",
7763 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7764 		    chip_id(sc) > CHELSIO_T6 ? sysctl_cim_qcfg_t7 : sysctl_cim_qcfg,
7765 		    "A", "Queue configuration");
7766 
7767 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "la",
7768 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7769 		    sysctl_cim_la, "A", "Logic analyzer");
7770 
7771 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "ma_la",
7772 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7773 		    sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
7774 
7775 		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "pif_la",
7776 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
7777 		    sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
7778 
7779 		/* IBQs */
7780 		switch (chip_id(sc)) {
7781 		case CHELSIO_T4:
7782 		case CHELSIO_T5:
7783 		case CHELSIO_T6:
7784 			qname = &t4_ibq[0];
7785 			qcount = nitems(t4_ibq);
7786 			break;
7787 		case CHELSIO_T7:
7788 		default:
7789 			if (i == 0) {
7790 				qname = &t7_ibq[0];
7791 				qcount = nitems(t7_ibq);
7792 			} else {
7793 				qname = &t7_ibq_sec[0];
7794 				qcount = nitems(t7_ibq_sec);
7795 			}
7796 			break;
7797 		}
7798 		MPASS(qcount <= sc->chip_params->cim_num_ibq);
7799 		for (j = 0; j < qcount; j++) {
7800 			if (qname[j] == NULL)
7801 				continue;
7802 			SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, qname[j],
7803 			    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7804 			    (i << 16) | j, sysctl_cim_ibq, "A", NULL);
7805 		}
7806 
7807 		/* OBQs */
7808 		switch (chip_id(sc)) {
7809 		case CHELSIO_T4:
7810 			qname = t4_obq;
7811 			qcount = CIM_NUM_OBQ;
7812 			break;
7813 		case CHELSIO_T5:
7814 		case CHELSIO_T6:
7815 			qname = t4_obq;
7816 			qcount = nitems(t4_obq);
7817 			break;
7818 		case CHELSIO_T7:
7819 		default:
7820 			if (i == 0) {
7821 				qname = t7_obq;
7822 				qcount = nitems(t7_obq);
7823 			} else {
7824 				qname = t7_obq_sec;
7825 				qcount = nitems(t7_obq_sec);
7826 			}
7827 			break;
7828 		}
7829 		MPASS(qcount <= sc->chip_params->cim_num_obq);
7830 		for (j = 0; j < qcount; j++) {
7831 			if (qname[j] == NULL)
7832 				continue;
7833 			SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, qname[j],
7834 			    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7835 			    (i << 16) | j, sysctl_cim_obq, "A", NULL);
7836 		}
7837 	}
7838 }
7839 
7840 /*
7841  * Should match fw_caps_config_<foo> enums in t4fw_interface.h
7842  */
7843 static char *caps_decoder[] = {
7844 	"\20\001IPMI\002NCSI",				/* 0: NBM */
7845 	"\20\001PPP\002QFC\003DCBX",			/* 1: link */
7846 	"\20\001INGRESS\002EGRESS",			/* 2: switch */
7847 	"\20\001NIC\002VM\003IDS\004UM\005UM_ISGL"	/* 3: NIC */
7848 	    "\006HASHFILTER\007ETHOFLD",
7849 	"\20\001TOE\002SENDPATH",			/* 4: TOE */
7850 	"\20\001RDDP\002RDMAC\003ROCEv2",		/* 5: RDMA */
7851 	"\20\001INITIATOR_PDU\002TARGET_PDU"		/* 6: iSCSI */
7852 	    "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
7853 	    "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
7854 	    "\007T10DIF"
7855 	    "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
7856 	"\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE"	/* 7: Crypto */
7857 	    "\004TLS_HW,\005TOE_IPSEC",
7858 	"\20\001INITIATOR\002TARGET\003CTRL_OFLD"	/* 8: FCoE */
7859 		    "\004PO_INITIATOR\005PO_TARGET",
7860 	"\20\001NVMe_TCP",				/* 9: NVMe */
7861 };
7862 
7863 void
7864 t4_sysctls(struct adapter *sc)
7865 {
7866 	struct sysctl_ctx_list *ctx = &sc->ctx;
7867 	struct sysctl_oid *oid;
7868 	struct sysctl_oid_list *children, *c0;
7869 	static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
7870 
7871 	/*
7872 	 * dev.t4nex.X.
7873 	 */
7874 	oid = device_get_sysctl_tree(sc->dev);
7875 	c0 = children = SYSCTL_CHILDREN(oid);
7876 
7877 	sc->sc_do_rxcopy = 1;
7878 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
7879 	    &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
7880 
7881 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
7882 	    sc->params.nports, "# of ports");
7883 
7884 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
7885 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells,
7886 	    (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A",
7887 	    "available doorbells");
7888 
7889 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
7890 	    sc->params.vpd.cclk, "core clock frequency (in KHz)");
7891 
7892 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
7893 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7894 	    sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val),
7895 	    sysctl_int_array, "A", "interrupt holdoff timer values (us)");
7896 
7897 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
7898 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7899 	    sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val),
7900 	    sysctl_int_array, "A", "interrupt holdoff packet counter values");
7901 
7902 	t4_sge_sysctls(sc, ctx, children);
7903 
7904 	sc->lro_timeout = 100;
7905 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
7906 	    &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
7907 
7908 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
7909 	    &sc->debug_flags, 0, "flags to enable runtime debugging");
7910 
7911 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iflags", CTLFLAG_RW,
7912 	    &sc->intr_flags, 0, "flags for the slow interrupt handler");
7913 
7914 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
7915 	    CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
7916 
7917 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
7918 	    CTLFLAG_RD, sc->fw_version, 0, "firmware version");
7919 
7920 	if (sc->flags & IS_VF)
7921 		return;
7922 
7923 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
7924 	    NULL, chip_rev(sc), "chip hardware revision");
7925 
7926 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
7927 	    CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
7928 
7929 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
7930 	    CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
7931 
7932 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
7933 	    CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
7934 
7935 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
7936 	    CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
7937 
7938 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
7939 	    CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
7940 
7941 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
7942 	    sc->er_version, 0, "expansion ROM version");
7943 
7944 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
7945 	    sc->bs_version, 0, "bootstrap firmware version");
7946 
7947 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
7948 	    NULL, sc->params.scfg_vers, "serial config version");
7949 
7950 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
7951 	    NULL, sc->params.vpd_vers, "VPD version");
7952 
7953 	SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
7954 	    CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
7955 
7956 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
7957 	    sc->cfcsum, "config file checksum");
7958 
7959 #define SYSCTL_CAP(name, n, text) \
7960 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
7961 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \
7962 	    (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \
7963 	    "available " text " capabilities")
7964 
7965 	SYSCTL_CAP(nbmcaps, 0, "NBM");
7966 	SYSCTL_CAP(linkcaps, 1, "link");
7967 	SYSCTL_CAP(switchcaps, 2, "switch");
7968 	SYSCTL_CAP(nvmecaps, 9, "NVMe");
7969 	SYSCTL_CAP(niccaps, 3, "NIC");
7970 	SYSCTL_CAP(toecaps, 4, "TCP offload");
7971 	SYSCTL_CAP(rdmacaps, 5, "RDMA");
7972 	SYSCTL_CAP(iscsicaps, 6, "iSCSI");
7973 	SYSCTL_CAP(cryptocaps, 7, "crypto");
7974 	SYSCTL_CAP(fcoecaps, 8, "FCoE");
7975 #undef SYSCTL_CAP
7976 
7977 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
7978 	    NULL, sc->tids.nftids, "number of filters");
7979 
7980 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
7981 	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7982 	    sysctl_temperature, "I", "chip temperature (in Celsius)");
7983 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor",
7984 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
7985 	    sysctl_reset_sensor, "I", "reset the chip's temperature sensor.");
7986 
7987 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd",
7988 	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd,
7989 	    "I", "core Vdd (in mV)");
7990 
7991 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
7992 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS,
7993 	    sysctl_cpus, "A", "local CPUs");
7994 
7995 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
7996 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS,
7997 	    sysctl_cpus, "A", "preferred CPUs for interrupts");
7998 
7999 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW,
8000 	    &sc->swintr, 0, "software triggered interrupts");
8001 
8002 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset",
8003 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I",
8004 	    "1 = reset adapter, 0 = zero reset counter");
8005 
8006 	/*
8007 	 * dev.t4nex.X.misc.  Marked CTLFLAG_SKIP to avoid information overload.
8008 	 */
8009 	oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
8010 	    CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL,
8011 	    "logs and miscellaneous information");
8012 	children = SYSCTL_CHILDREN(oid);
8013 
8014 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
8015 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8016 	    sysctl_cctrl, "A", "congestion control");
8017 
8018 	cim_sysctls(sc, ctx, children);
8019 
8020 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
8021 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8022 	    sysctl_cpl_stats, "A", "CPL statistics");
8023 
8024 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
8025 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8026 	    sysctl_ddp_stats, "A", "non-TCP DDP statistics");
8027 
8028 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats",
8029 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8030 	    sysctl_tid_stats, "A", "tid stats");
8031 
8032 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
8033 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, -1,
8034 	    sysctl_devlog, "A", "firmware's device log (all cores)");
8035 
8036 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
8037 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8038 	    sysctl_fcoe_stats, "A", "FCoE statistics");
8039 
8040 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
8041 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8042 	    sysctl_hw_sched, "A", "hardware scheduler ");
8043 
8044 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
8045 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8046 	    sysctl_l2t, "A", "hardware L2 table");
8047 
8048 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
8049 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8050 	    sysctl_smt, "A", "hardware source MAC table");
8051 
8052 #ifdef INET6
8053 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
8054 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8055 	    sysctl_clip, "A", "active CLIP table entries");
8056 #endif
8057 
8058 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
8059 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8060 	    sysctl_lb_stats, "A", "loopback statistics");
8061 
8062 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
8063 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8064 	    sysctl_meminfo, "A", "memory regions");
8065 
8066 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
8067 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8068 	    chip_id(sc) >= CHELSIO_T7 ? sysctl_mps_tcam_t7 :
8069 	    (chip_id(sc) >= CHELSIO_T6 ? sysctl_mps_tcam_t6 : sysctl_mps_tcam),
8070 	    "A", "MPS TCAM entries");
8071 
8072 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
8073 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8074 	    sysctl_path_mtus, "A", "path MTUs");
8075 
8076 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
8077 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8078 	    sysctl_pm_stats, "A", "PM statistics");
8079 
8080 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
8081 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8082 	    sysctl_rdma_stats, "A", "RDMA statistics");
8083 
8084 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
8085 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8086 	    sysctl_tcp_stats, "A", "TCP statistics");
8087 
8088 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
8089 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8090 	    sysctl_tids, "A", "TID information");
8091 
8092 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
8093 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8094 	    sysctl_tp_err_stats, "A", "TP error statistics");
8095 
8096 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats",
8097 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8098 	    sysctl_tnl_stats, "A", "TP tunnel statistics");
8099 
8100 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
8101 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
8102 	    sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask");
8103 
8104 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
8105 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8106 	    sysctl_tp_la, "A", "TP logic analyzer");
8107 
8108 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
8109 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8110 	    sysctl_tx_rate, "A", "Tx rate");
8111 
8112 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
8113 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8114 	    sysctl_ulprx_la, "A", "ULPRX logic analyzer");
8115 
8116 	if (chip_id(sc) >= CHELSIO_T5) {
8117 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
8118 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8119 		    sysctl_wcwr_stats, "A", "write combined work requests");
8120 	}
8121 
8122 #ifdef KERN_TLS
8123 	if (is_ktls(sc)) {
8124 		/*
8125 		 * dev.t4nex.0.tls.
8126 		 */
8127 		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls",
8128 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters");
8129 		children = SYSCTL_CHILDREN(oid);
8130 
8131 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys",
8132 		    CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS "
8133 		    "keys in work requests (1) or attempt to store TLS keys "
8134 		    "in card memory.");
8135 
8136 		if (is_t6(sc))
8137 			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs",
8138 			    CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to "
8139 			    "combine TCB field updates with TLS record work "
8140 			    "requests.");
8141 		else {
8142 			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "short_records",
8143 			    CTLFLAG_RW, &sc->tlst.short_records, 0,
8144 			    "Use cipher-only mode for short records.");
8145 			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "partial_ghash",
8146 			    CTLFLAG_RW, &sc->tlst.partial_ghash, 0,
8147 			    "Use partial GHASH for AES-GCM records.");
8148 		}
8149 	}
8150 #endif
8151 
8152 #ifdef TCP_OFFLOAD
8153 	if (is_offload(sc)) {
8154 		int i;
8155 		char s[4];
8156 
8157 		/*
8158 		 * dev.t4nex.X.toe.
8159 		 */
8160 		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe",
8161 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters");
8162 		children = SYSCTL_CHILDREN(oid);
8163 
8164 		sc->tt.cong_algorithm = -1;
8165 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
8166 		    CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
8167 		    "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
8168 		    "3 = highspeed)");
8169 
8170 		sc->tt.sndbuf = -1;
8171 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
8172 		    &sc->tt.sndbuf, 0, "hardware send buffer");
8173 
8174 		sc->tt.ddp = 0;
8175 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp",
8176 		    CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, "");
8177 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW,
8178 		    &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)");
8179 
8180 		sc->tt.rx_coalesce = -1;
8181 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
8182 		    CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
8183 
8184 		sc->tt.tls = 1;
8185 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT |
8186 		    CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I",
8187 		    "Inline TLS allowed");
8188 
8189 		sc->tt.tx_align = -1;
8190 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
8191 		    CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
8192 
8193 		sc->tt.tx_zcopy = 0;
8194 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
8195 		    CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
8196 		    "Enable zero-copy aio_write(2)");
8197 
8198 		sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
8199 		SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8200 		    "cop_managed_offloading", CTLFLAG_RW,
8201 		    &sc->tt.cop_managed_offloading, 0,
8202 		    "COP (Connection Offload Policy) controls all TOE offload");
8203 
8204 		sc->tt.autorcvbuf_inc = 16 * 1024;
8205 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc",
8206 		    CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0,
8207 		    "autorcvbuf increment");
8208 
8209 		sc->tt.update_hc_on_pmtu_change = 1;
8210 		SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8211 		    "update_hc_on_pmtu_change", CTLFLAG_RW,
8212 		    &sc->tt.update_hc_on_pmtu_change, 0,
8213 		    "Update hostcache entry if the PMTU changes");
8214 
8215 		sc->tt.iso = 1;
8216 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW,
8217 		    &sc->tt.iso, 0, "Enable iSCSI segmentation offload");
8218 
8219 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
8220 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8221 		    sysctl_tp_tick, "A", "TP timer tick (us)");
8222 
8223 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
8224 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1,
8225 		    sysctl_tp_tick, "A", "TCP timestamp tick (us)");
8226 
8227 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
8228 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2,
8229 		    sysctl_tp_tick, "A", "DACK tick (us)");
8230 
8231 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
8232 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
8233 		    sysctl_tp_dack_timer, "IU", "DACK timer (us)");
8234 
8235 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
8236 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8237 		    A_TP_RXT_MIN, sysctl_tp_timer, "LU",
8238 		    "Minimum retransmit interval (us)");
8239 
8240 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
8241 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8242 		    A_TP_RXT_MAX, sysctl_tp_timer, "LU",
8243 		    "Maximum retransmit interval (us)");
8244 
8245 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
8246 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8247 		    A_TP_PERS_MIN, sysctl_tp_timer, "LU",
8248 		    "Persist timer min (us)");
8249 
8250 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
8251 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8252 		    A_TP_PERS_MAX, sysctl_tp_timer, "LU",
8253 		    "Persist timer max (us)");
8254 
8255 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
8256 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8257 		    A_TP_KEEP_IDLE, sysctl_tp_timer, "LU",
8258 		    "Keepalive idle timer (us)");
8259 
8260 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
8261 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8262 		    A_TP_KEEP_INTVL, sysctl_tp_timer, "LU",
8263 		    "Keepalive interval timer (us)");
8264 
8265 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
8266 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8267 		    A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)");
8268 
8269 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
8270 		    CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8271 		    A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU",
8272 		    "FINWAIT2 timer (us)");
8273 
8274 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
8275 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8276 		    S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU",
8277 		    "Number of SYN retransmissions before abort");
8278 
8279 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
8280 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8281 		    S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU",
8282 		    "Number of retransmissions before abort");
8283 
8284 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
8285 		    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8286 		    S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU",
8287 		    "Number of keepalive probes before abort");
8288 
8289 		oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
8290 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
8291 		    "TOE retransmit backoffs");
8292 		children = SYSCTL_CHILDREN(oid);
8293 		for (i = 0; i < 16; i++) {
8294 			snprintf(s, sizeof(s), "%u", i);
8295 			SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
8296 			    CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8297 			    i, sysctl_tp_backoff, "IU",
8298 			    "TOE retransmit backoff");
8299 		}
8300 	}
8301 #endif
8302 }
8303 
8304 void
8305 vi_sysctls(struct vi_info *vi)
8306 {
8307 	struct sysctl_ctx_list *ctx = &vi->ctx;
8308 	struct sysctl_oid *oid;
8309 	struct sysctl_oid_list *children;
8310 
8311 	/*
8312 	 * dev.v?(cxgbe|cxl).X.
8313 	 */
8314 	oid = device_get_sysctl_tree(vi->dev);
8315 	children = SYSCTL_CHILDREN(oid);
8316 
8317 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
8318 	    vi->viid, "VI identifer");
8319 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
8320 	    &vi->nrxq, 0, "# of rx queues");
8321 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
8322 	    &vi->ntxq, 0, "# of tx queues");
8323 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
8324 	    &vi->first_rxq, 0, "index of first rx queue");
8325 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
8326 	    &vi->first_txq, 0, "index of first tx queue");
8327 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
8328 	    vi->rss_base, "start of RSS indirection table");
8329 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
8330 	    vi->rss_size, "size of RSS indirection table");
8331 
8332 	if (IS_MAIN_VI(vi)) {
8333 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
8334 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8335 		    sysctl_noflowq, "IU",
8336 		    "Reserve queue 0 for non-flowid packets");
8337 	}
8338 
8339 	if (vi->adapter->flags & IS_VF) {
8340 		MPASS(vi->flags & TX_USES_VM_WR);
8341 		SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD,
8342 		    NULL, 1, "use VM work requests for transmit");
8343 	} else {
8344 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr",
8345 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8346 		    sysctl_tx_vm_wr, "I", "use VM work requestes for transmit");
8347 	}
8348 
8349 #ifdef TCP_OFFLOAD
8350 	if (vi->nofldrxq != 0) {
8351 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
8352 		    &vi->nofldrxq, 0,
8353 		    "# of rx queues for offloaded TCP connections");
8354 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
8355 		    CTLFLAG_RD, &vi->first_ofld_rxq, 0,
8356 		    "index of first TOE rx queue");
8357 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
8358 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8359 		    sysctl_holdoff_tmr_idx_ofld, "I",
8360 		    "holdoff timer index for TOE queues");
8361 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
8362 		    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8363 		    sysctl_holdoff_pktc_idx_ofld, "I",
8364 		    "holdoff packet counter index for TOE queues");
8365 	}
8366 #endif
8367 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
8368 	if (vi->nofldtxq != 0) {
8369 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
8370 		    &vi->nofldtxq, 0,
8371 		    "# of tx queues for TOE/ETHOFLD");
8372 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
8373 		    CTLFLAG_RD, &vi->first_ofld_txq, 0,
8374 		    "index of first TOE/ETHOFLD tx queue");
8375 	}
8376 #endif
8377 #ifdef DEV_NETMAP
8378 	if (vi->nnmrxq != 0) {
8379 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
8380 		    &vi->nnmrxq, 0, "# of netmap rx queues");
8381 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
8382 		    &vi->nnmtxq, 0, "# of netmap tx queues");
8383 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
8384 		    CTLFLAG_RD, &vi->first_nm_rxq, 0,
8385 		    "index of first netmap rx queue");
8386 		SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
8387 		    CTLFLAG_RD, &vi->first_nm_txq, 0,
8388 		    "index of first netmap tx queue");
8389 	}
8390 #endif
8391 
8392 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
8393 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8394 	    sysctl_holdoff_tmr_idx, "I", "holdoff timer index");
8395 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
8396 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8397 	    sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index");
8398 
8399 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
8400 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8401 	    sysctl_qsize_rxq, "I", "rx queue size");
8402 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
8403 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
8404 	    sysctl_qsize_txq, "I", "tx queue size");
8405 }
8406 
8407 static void
8408 cxgbe_sysctls(struct port_info *pi)
8409 {
8410 	struct sysctl_ctx_list *ctx = &pi->ctx;
8411 	struct sysctl_oid *oid;
8412 	struct sysctl_oid_list *children, *children2;
8413 	struct adapter *sc = pi->adapter;
8414 	int i;
8415 	char name[16];
8416 	static char *tc_flags = {"\20\1USER"};
8417 
8418 	/*
8419 	 * dev.cxgbe.X.
8420 	 */
8421 	oid = device_get_sysctl_tree(pi->dev);
8422 	children = SYSCTL_CHILDREN(oid);
8423 
8424 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc",
8425 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
8426 	    sysctl_linkdnrc, "A", "reason why link is down");
8427 	if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
8428 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
8429 		    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
8430 		    sysctl_btphy, "I", "PHY temperature (in Celsius)");
8431 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
8432 		    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1,
8433 		    sysctl_btphy, "I", "PHY firmware version");
8434 	}
8435 
8436 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
8437 	    CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8438 	    sysctl_pause_settings, "A",
8439 	    "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
8440 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec",
8441 	    CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A",
8442 	    "FEC in use on the link");
8443 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec",
8444 	    CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8445 	    sysctl_requested_fec, "A",
8446 	    "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)");
8447 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec",
8448 	    CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A",
8449 	    "FEC recommended by the cable/transceiver");
8450 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
8451 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8452 	    sysctl_autoneg, "I",
8453 	    "autonegotiation (-1 = not supported)");
8454 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec",
8455 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
8456 	    sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config");
8457 
8458 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD,
8459 	    &pi->link_cfg.requested_caps, 0, "L1 config requested by driver");
8460 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD,
8461 	    &pi->link_cfg.pcaps, 0, "port capabilities");
8462 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD,
8463 	    &pi->link_cfg.acaps, 0, "advertised capabilities");
8464 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD,
8465 	    &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities");
8466 
8467 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
8468 	    port_top_speed(pi), "max speed (in Gbps)");
8469 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
8470 	    pi->mps_bg_map, "MPS buffer group map");
8471 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
8472 	    NULL, pi->rx_e_chan_map, "TP rx e-channel map");
8473 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_chan", CTLFLAG_RD, NULL,
8474 	    pi->tx_chan, "TP tx c-channel");
8475 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_chan", CTLFLAG_RD, NULL,
8476 	    pi->rx_chan, "TP rx c-channel");
8477 
8478 	if (sc->flags & IS_VF)
8479 		return;
8480 
8481 	/*
8482 	 * dev.(cxgbe|cxl).X.tc.
8483 	 */
8484 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc",
8485 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
8486 	    "Tx scheduler traffic classes (cl_rl)");
8487 	children2 = SYSCTL_CHILDREN(oid);
8488 	SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
8489 	    CTLFLAG_RW, &pi->sched_params->pktsize, 0,
8490 	    "pktsize for per-flow cl-rl (0 means up to the driver )");
8491 	SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
8492 	    CTLFLAG_RW, &pi->sched_params->burstsize, 0,
8493 	    "burstsize for per-flow cl-rl (0 means up to the driver)");
8494 	for (i = 0; i < sc->params.nsched_cls; i++) {
8495 		struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
8496 
8497 		snprintf(name, sizeof(name), "%d", i);
8498 		children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
8499 		    SYSCTL_CHILDREN(oid), OID_AUTO, name,
8500 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class"));
8501 		SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state",
8502 		    CTLFLAG_RD, &tc->state, 0, "current state");
8503 		SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
8504 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags,
8505 		    (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags");
8506 		SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
8507 		    CTLFLAG_RD, &tc->refcount, 0, "references to this class");
8508 		SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
8509 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
8510 		    (pi->port_id << 16) | i, sysctl_tc_params, "A",
8511 		    "traffic class parameters");
8512 	}
8513 
8514 	/*
8515 	 * dev.cxgbe.X.stats.
8516 	 */
8517 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats",
8518 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics");
8519 	children = SYSCTL_CHILDREN(oid);
8520 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
8521 	    &pi->tx_parse_error, 0,
8522 	    "# of tx packets with invalid length or # of segments");
8523 
8524 #define T4_LBSTAT(name, stat, desc) do { \
8525 	if (sc->params.tp.lb_mode) { \
8526 		SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8527 		    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, \
8528 		    A_MPS_PORT_STAT_##stat##_L, \
8529 		    sysctl_handle_t4_portstat64, "QU", desc); \
8530 	} else { \
8531 		SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8532 		    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
8533 		    t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \
8534 		    sysctl_handle_t4_reg64, "QU", desc); \
8535 	} \
8536 } while (0)
8537 
8538 	T4_LBSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames");
8539 	T4_LBSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames");
8540 	T4_LBSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames");
8541 	T4_LBSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames");
8542 	T4_LBSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames");
8543 	T4_LBSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames");
8544 	T4_LBSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range");
8545 	T4_LBSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range");
8546 	T4_LBSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range");
8547 	T4_LBSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range");
8548 	T4_LBSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range");
8549 	T4_LBSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range");
8550 	T4_LBSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range");
8551 	T4_LBSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames");
8552 	T4_LBSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted");
8553 	T4_LBSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted");
8554 	T4_LBSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted");
8555 	T4_LBSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted");
8556 	T4_LBSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted");
8557 	T4_LBSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted");
8558 	T4_LBSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted");
8559 	T4_LBSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted");
8560 	T4_LBSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted");
8561 
8562 	T4_LBSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames");
8563 	T4_LBSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames");
8564 	T4_LBSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames");
8565 	T4_LBSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames");
8566 	T4_LBSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames");
8567 	T4_LBSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU");
8568 	T4_LBSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames");
8569 	if (is_t6(sc)) {
8570 		/* Read from port_stats and may be stale by up to 1s */
8571 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rx_fcs_err",
8572 		    CTLFLAG_RD, &pi->stats.rx_fcs_err,
8573 		    "# of frames received with bad FCS since last link up");
8574 	} else {
8575 		T4_LBSTAT(rx_fcs_err, RX_PORT_CRC_ERROR,
8576 		    "# of frames received with bad FCS");
8577 	}
8578 	T4_LBSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error");
8579 	T4_LBSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors");
8580 	T4_LBSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received");
8581 	T4_LBSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range");
8582 	T4_LBSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range");
8583 	T4_LBSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range");
8584 	T4_LBSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range");
8585 	T4_LBSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range");
8586 	T4_LBSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range");
8587 	T4_LBSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range");
8588 	T4_LBSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received");
8589 	T4_LBSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received");
8590 	T4_LBSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received");
8591 	T4_LBSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received");
8592 	T4_LBSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received");
8593 	T4_LBSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received");
8594 	T4_LBSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received");
8595 	T4_LBSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received");
8596 	T4_LBSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received");
8597 #undef T4_LBSTAT
8598 
8599 #define T4_REGSTAT(name, stat, desc) do { \
8600 	SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
8601 	    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
8602 	    A_MPS_STAT_##stat##_L, sysctl_handle_t4_reg64, "QU", desc); \
8603 } while (0)
8604 
8605 	if (pi->mps_bg_map & 1) {
8606 		T4_REGSTAT(rx_ovflow0, RX_BG_0_MAC_DROP_FRAME,
8607 		    "# drops due to buffer-group 0 overflows");
8608 		T4_REGSTAT(rx_trunc0, RX_BG_0_MAC_TRUNC_FRAME,
8609 		    "# of buffer-group 0 truncated packets");
8610 	}
8611 	if (pi->mps_bg_map & 2) {
8612 		T4_REGSTAT(rx_ovflow1, RX_BG_1_MAC_DROP_FRAME,
8613 		    "# drops due to buffer-group 1 overflows");
8614 		T4_REGSTAT(rx_trunc1, RX_BG_1_MAC_TRUNC_FRAME,
8615 		    "# of buffer-group 1 truncated packets");
8616 	}
8617 	if (pi->mps_bg_map & 4) {
8618 		T4_REGSTAT(rx_ovflow2, RX_BG_2_MAC_DROP_FRAME,
8619 		    "# drops due to buffer-group 2 overflows");
8620 		T4_REGSTAT(rx_trunc2, RX_BG_2_MAC_TRUNC_FRAME,
8621 		    "# of buffer-group 2 truncated packets");
8622 	}
8623 	if (pi->mps_bg_map & 8) {
8624 		T4_REGSTAT(rx_ovflow3, RX_BG_3_MAC_DROP_FRAME,
8625 		    "# drops due to buffer-group 3 overflows");
8626 		T4_REGSTAT(rx_trunc3, RX_BG_3_MAC_TRUNC_FRAME,
8627 		    "# of buffer-group 3 truncated packets");
8628 	}
8629 #undef T4_REGSTAT
8630 }
8631 
8632 static int
8633 sysctl_int_array(SYSCTL_HANDLER_ARGS)
8634 {
8635 	int rc, *i, space = 0;
8636 	struct sbuf sb;
8637 
8638 	sbuf_new_for_sysctl(&sb, NULL, 64, req);
8639 	for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
8640 		if (space)
8641 			sbuf_printf(&sb, " ");
8642 		sbuf_printf(&sb, "%d", *i);
8643 		space = 1;
8644 	}
8645 	rc = sbuf_finish(&sb);
8646 	sbuf_delete(&sb);
8647 	return (rc);
8648 }
8649 
8650 static int
8651 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
8652 {
8653 	int rc;
8654 	struct sbuf *sb;
8655 
8656 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8657 	if (sb == NULL)
8658 		return (ENOMEM);
8659 
8660 	sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
8661 	rc = sbuf_finish(sb);
8662 	sbuf_delete(sb);
8663 
8664 	return (rc);
8665 }
8666 
8667 static int
8668 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
8669 {
8670 	int rc;
8671 	struct sbuf *sb;
8672 
8673 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8674 	if (sb == NULL)
8675 		return (ENOMEM);
8676 
8677 	sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
8678 	rc = sbuf_finish(sb);
8679 	sbuf_delete(sb);
8680 
8681 	return (rc);
8682 }
8683 
8684 static int
8685 sysctl_btphy(SYSCTL_HANDLER_ARGS)
8686 {
8687 	struct port_info *pi = arg1;
8688 	int op = arg2;
8689 	struct adapter *sc = pi->adapter;
8690 	u_int v;
8691 	int rc;
8692 
8693 	rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
8694 	if (rc)
8695 		return (rc);
8696 	if (!hw_all_ok(sc))
8697 		rc = ENXIO;
8698 	else {
8699 		/* XXX: magic numbers */
8700 		rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e,
8701 		    op ? 0x20 : 0xc820, &v);
8702 	}
8703 	end_synchronized_op(sc, 0);
8704 	if (rc)
8705 		return (rc);
8706 	if (op == 0)
8707 		v /= 256;
8708 
8709 	rc = sysctl_handle_int(oidp, &v, 0, req);
8710 	return (rc);
8711 }
8712 
8713 static int
8714 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
8715 {
8716 	struct vi_info *vi = arg1;
8717 	int rc, val;
8718 
8719 	val = vi->rsrv_noflowq;
8720 	rc = sysctl_handle_int(oidp, &val, 0, req);
8721 	if (rc != 0 || req->newptr == NULL)
8722 		return (rc);
8723 
8724 	if ((val >= 1) && (vi->ntxq > 1))
8725 		vi->rsrv_noflowq = 1;
8726 	else
8727 		vi->rsrv_noflowq = 0;
8728 
8729 	return (rc);
8730 }
8731 
8732 static int
8733 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS)
8734 {
8735 	struct vi_info *vi = arg1;
8736 	struct adapter *sc = vi->adapter;
8737 	int rc, val, i;
8738 
8739 	MPASS(!(sc->flags & IS_VF));
8740 
8741 	val = vi->flags & TX_USES_VM_WR ? 1 : 0;
8742 	rc = sysctl_handle_int(oidp, &val, 0, req);
8743 	if (rc != 0 || req->newptr == NULL)
8744 		return (rc);
8745 
8746 	if (val != 0 && val != 1)
8747 		return (EINVAL);
8748 
8749 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8750 	    "t4txvm");
8751 	if (rc)
8752 		return (rc);
8753 	if (!hw_all_ok(sc))
8754 		rc = ENXIO;
8755 	else if (if_getdrvflags(vi->ifp) & IFF_DRV_RUNNING) {
8756 		/*
8757 		 * We don't want parse_pkt to run with one setting (VF or PF)
8758 		 * and then eth_tx to see a different setting but still use
8759 		 * stale information calculated by parse_pkt.
8760 		 */
8761 		rc = EBUSY;
8762 	} else {
8763 		struct port_info *pi = vi->pi;
8764 		struct sge_txq *txq;
8765 		uint32_t ctrl0;
8766 		uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr;
8767 
8768 		if (val) {
8769 			vi->flags |= TX_USES_VM_WR;
8770 			if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO);
8771 			ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8772 			    V_TXPKT_INTF(pi->hw_port));
8773 			if (!(sc->flags & IS_VF))
8774 				npkt--;
8775 		} else {
8776 			vi->flags &= ~TX_USES_VM_WR;
8777 			if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO);
8778 			ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8779 			    V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) |
8780 			    V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
8781 		}
8782 		for_each_txq(vi, i, txq) {
8783 			txq->cpl_ctrl0 = ctrl0;
8784 			txq->txp.max_npkt = npkt;
8785 		}
8786 	}
8787 	end_synchronized_op(sc, LOCK_HELD);
8788 	return (rc);
8789 }
8790 
8791 static int
8792 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
8793 {
8794 	struct vi_info *vi = arg1;
8795 	struct adapter *sc = vi->adapter;
8796 	int idx, rc, i;
8797 	struct sge_rxq *rxq;
8798 	uint8_t v;
8799 
8800 	idx = vi->tmr_idx;
8801 
8802 	rc = sysctl_handle_int(oidp, &idx, 0, req);
8803 	if (rc != 0 || req->newptr == NULL)
8804 		return (rc);
8805 
8806 	if (idx < 0 || idx >= SGE_NTIMERS)
8807 		return (EINVAL);
8808 
8809 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8810 	    "t4tmr");
8811 	if (rc)
8812 		return (rc);
8813 
8814 	v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
8815 	for_each_rxq(vi, i, rxq) {
8816 #ifdef atomic_store_rel_8
8817 		atomic_store_rel_8(&rxq->iq.intr_params, v);
8818 #else
8819 		rxq->iq.intr_params = v;
8820 #endif
8821 	}
8822 	vi->tmr_idx = idx;
8823 
8824 	end_synchronized_op(sc, LOCK_HELD);
8825 	return (0);
8826 }
8827 
8828 static int
8829 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
8830 {
8831 	struct vi_info *vi = arg1;
8832 	struct adapter *sc = vi->adapter;
8833 	int idx, rc;
8834 
8835 	idx = vi->pktc_idx;
8836 
8837 	rc = sysctl_handle_int(oidp, &idx, 0, req);
8838 	if (rc != 0 || req->newptr == NULL)
8839 		return (rc);
8840 
8841 	if (idx < -1 || idx >= SGE_NCOUNTERS)
8842 		return (EINVAL);
8843 
8844 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8845 	    "t4pktc");
8846 	if (rc)
8847 		return (rc);
8848 
8849 	if (vi->flags & VI_INIT_DONE)
8850 		rc = EBUSY; /* cannot be changed once the queues are created */
8851 	else
8852 		vi->pktc_idx = idx;
8853 
8854 	end_synchronized_op(sc, LOCK_HELD);
8855 	return (rc);
8856 }
8857 
8858 static int
8859 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
8860 {
8861 	struct vi_info *vi = arg1;
8862 	struct adapter *sc = vi->adapter;
8863 	int qsize, rc;
8864 
8865 	qsize = vi->qsize_rxq;
8866 
8867 	rc = sysctl_handle_int(oidp, &qsize, 0, req);
8868 	if (rc != 0 || req->newptr == NULL)
8869 		return (rc);
8870 
8871 	if (qsize < 128 || (qsize & 7))
8872 		return (EINVAL);
8873 
8874 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8875 	    "t4rxqs");
8876 	if (rc)
8877 		return (rc);
8878 
8879 	if (vi->flags & VI_INIT_DONE)
8880 		rc = EBUSY; /* cannot be changed once the queues are created */
8881 	else
8882 		vi->qsize_rxq = qsize;
8883 
8884 	end_synchronized_op(sc, LOCK_HELD);
8885 	return (rc);
8886 }
8887 
8888 static int
8889 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
8890 {
8891 	struct vi_info *vi = arg1;
8892 	struct adapter *sc = vi->adapter;
8893 	int qsize, rc;
8894 
8895 	qsize = vi->qsize_txq;
8896 
8897 	rc = sysctl_handle_int(oidp, &qsize, 0, req);
8898 	if (rc != 0 || req->newptr == NULL)
8899 		return (rc);
8900 
8901 	if (qsize < 128 || qsize > 65536)
8902 		return (EINVAL);
8903 
8904 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8905 	    "t4txqs");
8906 	if (rc)
8907 		return (rc);
8908 
8909 	if (vi->flags & VI_INIT_DONE)
8910 		rc = EBUSY; /* cannot be changed once the queues are created */
8911 	else
8912 		vi->qsize_txq = qsize;
8913 
8914 	end_synchronized_op(sc, LOCK_HELD);
8915 	return (rc);
8916 }
8917 
8918 static int
8919 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
8920 {
8921 	struct port_info *pi = arg1;
8922 	struct adapter *sc = pi->adapter;
8923 	struct link_config *lc = &pi->link_cfg;
8924 	int rc;
8925 
8926 	if (req->newptr == NULL) {
8927 		struct sbuf *sb;
8928 		static char *bits = "\20\1RX\2TX\3AUTO";
8929 
8930 		sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8931 		if (sb == NULL)
8932 			return (ENOMEM);
8933 
8934 		if (lc->link_ok) {
8935 			sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
8936 			    (lc->requested_fc & PAUSE_AUTONEG), bits);
8937 		} else {
8938 			sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
8939 			    PAUSE_RX | PAUSE_AUTONEG), bits);
8940 		}
8941 		rc = sbuf_finish(sb);
8942 		sbuf_delete(sb);
8943 	} else {
8944 		char s[2];
8945 		int n;
8946 
8947 		s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
8948 		    PAUSE_AUTONEG));
8949 		s[1] = 0;
8950 
8951 		rc = sysctl_handle_string(oidp, s, sizeof(s), req);
8952 		if (rc != 0)
8953 			return(rc);
8954 
8955 		if (s[1] != 0)
8956 			return (EINVAL);
8957 		if (s[0] < '0' || s[0] > '9')
8958 			return (EINVAL);	/* not a number */
8959 		n = s[0] - '0';
8960 		if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
8961 			return (EINVAL);	/* some other bit is set too */
8962 
8963 		rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
8964 		    "t4PAUSE");
8965 		if (rc)
8966 			return (rc);
8967 		if (hw_all_ok(sc)) {
8968 			PORT_LOCK(pi);
8969 			lc->requested_fc = n;
8970 			fixup_link_config(pi);
8971 			if (pi->up_vis > 0)
8972 				rc = apply_link_config(pi);
8973 			set_current_media(pi);
8974 			PORT_UNLOCK(pi);
8975 		}
8976 		end_synchronized_op(sc, 0);
8977 	}
8978 
8979 	return (rc);
8980 }
8981 
8982 static int
8983 sysctl_link_fec(SYSCTL_HANDLER_ARGS)
8984 {
8985 	struct port_info *pi = arg1;
8986 	struct link_config *lc = &pi->link_cfg;
8987 	int rc;
8988 	struct sbuf *sb;
8989 
8990 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8991 	if (sb == NULL)
8992 		return (ENOMEM);
8993 	if (lc->link_ok)
8994 		sbuf_printf(sb, "%b", lc->fec, t4_fec_bits);
8995 	else
8996 		sbuf_printf(sb, "no link");
8997 	rc = sbuf_finish(sb);
8998 	sbuf_delete(sb);
8999 
9000 	return (rc);
9001 }
9002 
9003 static int
9004 sysctl_requested_fec(SYSCTL_HANDLER_ARGS)
9005 {
9006 	struct port_info *pi = arg1;
9007 	struct adapter *sc = pi->adapter;
9008 	struct link_config *lc = &pi->link_cfg;
9009 	int rc;
9010 	int8_t old;
9011 
9012 	if (req->newptr == NULL) {
9013 		struct sbuf *sb;
9014 
9015 		sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
9016 		if (sb == NULL)
9017 			return (ENOMEM);
9018 
9019 		sbuf_printf(sb, "%b", lc->requested_fec, t4_fec_bits);
9020 		rc = sbuf_finish(sb);
9021 		sbuf_delete(sb);
9022 	} else {
9023 		char s[8];
9024 		int n;
9025 
9026 		snprintf(s, sizeof(s), "%d",
9027 		    lc->requested_fec == FEC_AUTO ? -1 :
9028 		    lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE));
9029 
9030 		rc = sysctl_handle_string(oidp, s, sizeof(s), req);
9031 		if (rc != 0)
9032 			return(rc);
9033 
9034 		n = strtol(&s[0], NULL, 0);
9035 		if (n < 0 || n & FEC_AUTO)
9036 			n = FEC_AUTO;
9037 		else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE))
9038 			return (EINVAL);/* some other bit is set too */
9039 
9040 		rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
9041 		    "t4reqf");
9042 		if (rc)
9043 			return (rc);
9044 		PORT_LOCK(pi);
9045 		old = lc->requested_fec;
9046 		if (n == FEC_AUTO)
9047 			lc->requested_fec = FEC_AUTO;
9048 		else if (n == 0 || n == FEC_NONE)
9049 			lc->requested_fec = FEC_NONE;
9050 		else {
9051 			if ((lc->pcaps |
9052 			    V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) !=
9053 			    lc->pcaps) {
9054 				rc = ENOTSUP;
9055 				goto done;
9056 			}
9057 			lc->requested_fec = n & (M_FW_PORT_CAP32_FEC |
9058 			    FEC_MODULE);
9059 		}
9060 		if (hw_all_ok(sc)) {
9061 			fixup_link_config(pi);
9062 			if (pi->up_vis > 0) {
9063 				rc = apply_link_config(pi);
9064 				if (rc != 0) {
9065 					lc->requested_fec = old;
9066 					if (rc == FW_EPROTO)
9067 						rc = ENOTSUP;
9068 				}
9069 			}
9070 		}
9071 done:
9072 		PORT_UNLOCK(pi);
9073 		end_synchronized_op(sc, 0);
9074 	}
9075 
9076 	return (rc);
9077 }
9078 
9079 static int
9080 sysctl_module_fec(SYSCTL_HANDLER_ARGS)
9081 {
9082 	struct port_info *pi = arg1;
9083 	struct adapter *sc = pi->adapter;
9084 	struct link_config *lc = &pi->link_cfg;
9085 	int rc;
9086 	int8_t fec;
9087 	struct sbuf *sb;
9088 
9089 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
9090 	if (sb == NULL)
9091 		return (ENOMEM);
9092 
9093 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) {
9094 		rc = EBUSY;
9095 		goto done;
9096 	}
9097 	if (!hw_all_ok(sc)) {
9098 		rc = ENXIO;
9099 		goto done;
9100 	}
9101 	PORT_LOCK(pi);
9102 	if (pi->up_vis == 0) {
9103 		/*
9104 		 * If all the interfaces are administratively down the firmware
9105 		 * does not report transceiver changes.  Refresh port info here.
9106 		 * This is the only reason we have a synchronized op in this
9107 		 * function.  Just PORT_LOCK would have been enough otherwise.
9108 		 */
9109 		t4_update_port_info(pi);
9110 	}
9111 
9112 	fec = lc->fec_hint;
9113 	if (pi->mod_type == FW_PORT_MOD_TYPE_NONE ||
9114 	    !fec_supported(lc->pcaps)) {
9115 		PORT_UNLOCK(pi);
9116 		sbuf_printf(sb, "n/a");
9117 	} else {
9118 		if (fec == 0)
9119 			fec = FEC_NONE;
9120 		PORT_UNLOCK(pi);
9121 		sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, t4_fec_bits);
9122 	}
9123 	rc = sbuf_finish(sb);
9124 done:
9125 	sbuf_delete(sb);
9126 	end_synchronized_op(sc, 0);
9127 
9128 	return (rc);
9129 }
9130 
9131 static int
9132 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
9133 {
9134 	struct port_info *pi = arg1;
9135 	struct adapter *sc = pi->adapter;
9136 	struct link_config *lc = &pi->link_cfg;
9137 	int rc, val;
9138 
9139 	if (lc->pcaps & FW_PORT_CAP32_ANEG)
9140 		val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
9141 	else
9142 		val = -1;
9143 	rc = sysctl_handle_int(oidp, &val, 0, req);
9144 	if (rc != 0 || req->newptr == NULL)
9145 		return (rc);
9146 	if (val == 0)
9147 		val = AUTONEG_DISABLE;
9148 	else if (val == 1)
9149 		val = AUTONEG_ENABLE;
9150 	else
9151 		val = AUTONEG_AUTO;
9152 
9153 	rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
9154 	    "t4aneg");
9155 	if (rc)
9156 		return (rc);
9157 	PORT_LOCK(pi);
9158 	if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
9159 		rc = ENOTSUP;
9160 		goto done;
9161 	}
9162 	lc->requested_aneg = val;
9163 	if (hw_all_ok(sc)) {
9164 		fixup_link_config(pi);
9165 		if (pi->up_vis > 0)
9166 			rc = apply_link_config(pi);
9167 		set_current_media(pi);
9168 	}
9169 done:
9170 	PORT_UNLOCK(pi);
9171 	end_synchronized_op(sc, 0);
9172 	return (rc);
9173 }
9174 
9175 static int
9176 sysctl_force_fec(SYSCTL_HANDLER_ARGS)
9177 {
9178 	struct port_info *pi = arg1;
9179 	struct adapter *sc = pi->adapter;
9180 	struct link_config *lc = &pi->link_cfg;
9181 	int rc, val;
9182 
9183 	val = lc->force_fec;
9184 	MPASS(val >= -1 && val <= 1);
9185 	rc = sysctl_handle_int(oidp, &val, 0, req);
9186 	if (rc != 0 || req->newptr == NULL)
9187 		return (rc);
9188 	if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC))
9189 		return (ENOTSUP);
9190 	if (val < -1 || val > 1)
9191 		return (EINVAL);
9192 
9193 	rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff");
9194 	if (rc)
9195 		return (rc);
9196 	PORT_LOCK(pi);
9197 	lc->force_fec = val;
9198 	if (hw_all_ok(sc)) {
9199 		fixup_link_config(pi);
9200 		if (pi->up_vis > 0)
9201 			rc = apply_link_config(pi);
9202 	}
9203 	PORT_UNLOCK(pi);
9204 	end_synchronized_op(sc, 0);
9205 	return (rc);
9206 }
9207 
9208 static int
9209 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
9210 {
9211 	struct adapter *sc = arg1;
9212 	int rc, reg = arg2;
9213 	uint64_t val;
9214 
9215 	mtx_lock(&sc->reg_lock);
9216 	if (hw_off_limits(sc))
9217 		rc = ENXIO;
9218 	else {
9219 		rc = 0;
9220 		val = t4_read_reg64(sc, reg);
9221 	}
9222 	mtx_unlock(&sc->reg_lock);
9223 	if (rc == 0)
9224 		rc = sysctl_handle_64(oidp, &val, 0, req);
9225 	return (rc);
9226 }
9227 
9228 static int
9229 sysctl_handle_t4_portstat64(SYSCTL_HANDLER_ARGS)
9230 {
9231 	struct port_info *pi = arg1;
9232 	struct adapter *sc = pi->adapter;
9233 	int rc, i, reg = arg2;
9234 	uint64_t val;
9235 
9236 	mtx_lock(&sc->reg_lock);
9237 	if (hw_off_limits(sc))
9238 		rc = ENXIO;
9239 	else {
9240 		val = 0;
9241 		for (i = 0; i < sc->params.tp.lb_nchan; i++) {
9242 			val += t4_read_reg64(sc,
9243 			    t4_port_reg(sc, pi->tx_chan + i, reg));
9244 		}
9245 		rc = 0;
9246 	}
9247 	mtx_unlock(&sc->reg_lock);
9248 	if (rc == 0)
9249 		rc = sysctl_handle_64(oidp, &val, 0, req);
9250 	return (rc);
9251 }
9252 
9253 static int
9254 sysctl_temperature(SYSCTL_HANDLER_ARGS)
9255 {
9256 	struct adapter *sc = arg1;
9257 	int rc, t;
9258 	uint32_t param, val;
9259 
9260 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
9261 	if (rc)
9262 		return (rc);
9263 	if (!hw_all_ok(sc))
9264 		rc = ENXIO;
9265 	else {
9266 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9267 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
9268 		    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
9269 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
9270 	}
9271 	end_synchronized_op(sc, 0);
9272 	if (rc)
9273 		return (rc);
9274 
9275 	/* unknown is returned as 0 but we display -1 in that case */
9276 	t = val == 0 ? -1 : val;
9277 
9278 	rc = sysctl_handle_int(oidp, &t, 0, req);
9279 	return (rc);
9280 }
9281 
9282 static int
9283 sysctl_vdd(SYSCTL_HANDLER_ARGS)
9284 {
9285 	struct adapter *sc = arg1;
9286 	int rc;
9287 	uint32_t param, val;
9288 
9289 	if (sc->params.core_vdd == 0) {
9290 		rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
9291 		    "t4vdd");
9292 		if (rc)
9293 			return (rc);
9294 		if (!hw_all_ok(sc))
9295 			rc = ENXIO;
9296 		else {
9297 			param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9298 			    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
9299 			    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
9300 			rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1,
9301 			    &param, &val);
9302 		}
9303 		end_synchronized_op(sc, 0);
9304 		if (rc)
9305 			return (rc);
9306 		sc->params.core_vdd = val;
9307 	}
9308 
9309 	return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req));
9310 }
9311 
9312 static int
9313 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS)
9314 {
9315 	struct adapter *sc = arg1;
9316 	int rc, v;
9317 	uint32_t param, val;
9318 
9319 	v = sc->sensor_resets;
9320 	rc = sysctl_handle_int(oidp, &v, 0, req);
9321 	if (rc != 0 || req->newptr == NULL || v <= 0)
9322 		return (rc);
9323 
9324 	if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) ||
9325 	    chip_id(sc) < CHELSIO_T5)
9326 		return (ENOTSUP);
9327 
9328 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst");
9329 	if (rc)
9330 		return (rc);
9331 	if (!hw_all_ok(sc))
9332 		rc = ENXIO;
9333 	else {
9334 		param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9335 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
9336 		    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR));
9337 		val = 1;
9338 		rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
9339 	}
9340 	end_synchronized_op(sc, 0);
9341 	if (rc == 0)
9342 		sc->sensor_resets++;
9343 	return (rc);
9344 }
9345 
9346 static int
9347 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
9348 {
9349 	struct adapter *sc = arg1;
9350 	struct sbuf *sb;
9351 	int rc;
9352 	uint32_t param, val;
9353 	uint8_t coreid = (uint8_t)arg2;
9354 
9355 	KASSERT(coreid < sc->params.ncores,
9356 	    ("%s: bad coreid %u\n", __func__, coreid));
9357 
9358 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
9359 	if (rc)
9360 		return (rc);
9361 	if (!hw_all_ok(sc))
9362 		rc = ENXIO;
9363 	else {
9364 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9365 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD) |
9366 		    V_FW_PARAMS_PARAM_Y(coreid);
9367 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
9368 	}
9369 	end_synchronized_op(sc, 0);
9370 	if (rc)
9371 		return (rc);
9372 
9373 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9374 	if (sb == NULL)
9375 		return (ENOMEM);
9376 
9377 	if (val == 0xffffffff) {
9378 		/* Only debug and custom firmwares report load averages. */
9379 		sbuf_printf(sb, "not available");
9380 	} else {
9381 		sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
9382 		    (val >> 16) & 0xff);
9383 	}
9384 	rc = sbuf_finish(sb);
9385 	sbuf_delete(sb);
9386 
9387 	return (rc);
9388 }
9389 
9390 static int
9391 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
9392 {
9393 	struct adapter *sc = arg1;
9394 	struct sbuf *sb;
9395 	int rc, i;
9396 	uint16_t incr[NMTUS][NCCTRL_WIN];
9397 	static const char *dec_fac[] = {
9398 		"0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
9399 		"0.9375"
9400 	};
9401 
9402 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9403 	if (sb == NULL)
9404 		return (ENOMEM);
9405 
9406 	rc = 0;
9407 	mtx_lock(&sc->reg_lock);
9408 	if (hw_off_limits(sc))
9409 		rc = ENXIO;
9410 	else
9411 		t4_read_cong_tbl(sc, incr);
9412 	mtx_unlock(&sc->reg_lock);
9413 	if (rc)
9414 		goto done;
9415 
9416 	for (i = 0; i < NCCTRL_WIN; ++i) {
9417 		sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
9418 		    incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
9419 		    incr[5][i], incr[6][i], incr[7][i]);
9420 		sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
9421 		    incr[8][i], incr[9][i], incr[10][i], incr[11][i],
9422 		    incr[12][i], incr[13][i], incr[14][i], incr[15][i],
9423 		    sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
9424 	}
9425 
9426 	rc = sbuf_finish(sb);
9427 done:
9428 	sbuf_delete(sb);
9429 	return (rc);
9430 }
9431 
9432 static int
9433 sysctl_cim_ibq(SYSCTL_HANDLER_ARGS)
9434 {
9435 	struct adapter *sc = arg1;
9436 	struct sbuf *sb;
9437 	int rc, i, n, qid, coreid;
9438 	uint32_t *buf, *p;
9439 
9440 	qid = arg2 & 0xffff;
9441 	coreid = arg2 >> 16;
9442 
9443 	KASSERT(qid >= 0 && qid < sc->chip_params->cim_num_ibq,
9444 	    ("%s: bad ibq qid %d\n", __func__, qid));
9445 	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
9446 	    ("%s: bad coreid %d\n", __func__, coreid));
9447 
9448 	n = 4 * CIM_IBQ_SIZE;
9449 	buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
9450 	mtx_lock(&sc->reg_lock);
9451 	if (hw_off_limits(sc))
9452 		rc = -ENXIO;
9453 	else
9454 		rc = t4_read_cim_ibq_core(sc, coreid, qid, buf, n);
9455 	mtx_unlock(&sc->reg_lock);
9456 	if (rc < 0) {
9457 		rc = -rc;
9458 		goto done;
9459 	}
9460 	n = rc * sizeof(uint32_t);	/* rc has # of words actually read */
9461 
9462 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9463 	if (sb == NULL) {
9464 		rc = ENOMEM;
9465 		goto done;
9466 	}
9467 	for (i = 0, p = buf; i < n; i += 16, p += 4)
9468 		sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
9469 		    p[2], p[3]);
9470 	rc = sbuf_finish(sb);
9471 	sbuf_delete(sb);
9472 done:
9473 	free(buf, M_CXGBE);
9474 	return (rc);
9475 }
9476 
9477 static int
9478 sysctl_cim_obq(SYSCTL_HANDLER_ARGS)
9479 {
9480 	struct adapter *sc = arg1;
9481 	struct sbuf *sb;
9482 	int rc, i, n, qid, coreid;
9483 	uint32_t *buf, *p;
9484 
9485 	qid = arg2 & 0xffff;
9486 	coreid = arg2 >> 16;
9487 
9488 	KASSERT(qid >= 0 && qid < sc->chip_params->cim_num_obq,
9489 	    ("%s: bad obq qid %d\n", __func__, qid));
9490 	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
9491 	    ("%s: bad coreid %d\n", __func__, coreid));
9492 
9493 	n = 6 * CIM_OBQ_SIZE * 4;
9494 	buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
9495 	mtx_lock(&sc->reg_lock);
9496 	if (hw_off_limits(sc))
9497 		rc = -ENXIO;
9498 	else
9499 		rc = t4_read_cim_obq_core(sc, coreid, qid, buf, n);
9500 	mtx_unlock(&sc->reg_lock);
9501 	if (rc < 0) {
9502 		rc = -rc;
9503 		goto done;
9504 	}
9505 	n = rc * sizeof(uint32_t);	/* rc has # of words actually read */
9506 
9507 	rc = sysctl_wire_old_buffer(req, 0);
9508 	if (rc != 0)
9509 		goto done;
9510 
9511 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9512 	if (sb == NULL) {
9513 		rc = ENOMEM;
9514 		goto done;
9515 	}
9516 	for (i = 0, p = buf; i < n; i += 16, p += 4)
9517 		sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
9518 		    p[2], p[3]);
9519 	rc = sbuf_finish(sb);
9520 	sbuf_delete(sb);
9521 done:
9522 	free(buf, M_CXGBE);
9523 	return (rc);
9524 }
9525 
9526 static void
9527 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
9528 {
9529 	uint32_t *p;
9530 
9531 	sbuf_printf(sb, "Status   Data      PC%s",
9532 	    cfg & F_UPDBGLACAPTPCONLY ? "" :
9533 	    "     LS0Stat  LS0Addr             LS0Data");
9534 
9535 	for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
9536 		if (cfg & F_UPDBGLACAPTPCONLY) {
9537 			sbuf_printf(sb, "\n  %02x   %08x %08x", p[5] & 0xff,
9538 			    p[6], p[7]);
9539 			sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x",
9540 			    (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
9541 			    p[4] & 0xff, p[5] >> 8);
9542 			sbuf_printf(sb, "\n  %02x   %x%07x %x%07x",
9543 			    (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
9544 			    p[1] & 0xf, p[2] >> 4);
9545 		} else {
9546 			sbuf_printf(sb,
9547 			    "\n  %02x   %x%07x %x%07x %08x %08x "
9548 			    "%08x%08x%08x%08x",
9549 			    (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
9550 			    p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
9551 			    p[6], p[7]);
9552 		}
9553 	}
9554 }
9555 
9556 static void
9557 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
9558 {
9559 	uint32_t *p;
9560 
9561 	sbuf_printf(sb, "Status   Inst    Data      PC%s",
9562 	    cfg & F_UPDBGLACAPTPCONLY ? "" :
9563 	    "     LS0Stat  LS0Addr  LS0Data  LS1Stat  LS1Addr  LS1Data");
9564 
9565 	for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
9566 		if (cfg & F_UPDBGLACAPTPCONLY) {
9567 			sbuf_printf(sb, "\n  %02x   %08x %08x %08x",
9568 			    p[3] & 0xff, p[2], p[1], p[0]);
9569 			sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x %02x%06x",
9570 			    (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
9571 			    p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
9572 			sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x",
9573 			    (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
9574 			    p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
9575 			    p[6] >> 16);
9576 		} else {
9577 			sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x "
9578 			    "%08x %08x %08x %08x %08x %08x",
9579 			    (p[9] >> 16) & 0xff,
9580 			    p[9] & 0xffff, p[8] >> 16,
9581 			    p[8] & 0xffff, p[7] >> 16,
9582 			    p[7] & 0xffff, p[6] >> 16,
9583 			    p[2], p[1], p[0], p[5], p[4], p[3]);
9584 		}
9585 	}
9586 }
9587 
9588 static int
9589 sbuf_cim_la(struct adapter *sc, int coreid, struct sbuf *sb, int flags)
9590 {
9591 	uint32_t cfg, *buf;
9592 	int rc;
9593 
9594 	MPASS(flags == M_WAITOK || flags == M_NOWAIT);
9595 	buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
9596 	    M_ZERO | flags);
9597 	if (buf == NULL)
9598 		return (ENOMEM);
9599 
9600 	mtx_lock(&sc->reg_lock);
9601 	if (hw_off_limits(sc))
9602 		rc = ENXIO;
9603 	else {
9604 		rc = -t4_cim_read_core(sc, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
9605 		    &cfg);
9606 		if (rc == 0)
9607 			rc = -t4_cim_read_la_core(sc, coreid, buf, NULL);
9608 	}
9609 	mtx_unlock(&sc->reg_lock);
9610 	if (rc == 0) {
9611 		if (chip_id(sc) < CHELSIO_T6)
9612 			sbuf_cim_la4(sc, sb, buf, cfg);
9613 		else
9614 			sbuf_cim_la6(sc, sb, buf, cfg);
9615 	}
9616 	free(buf, M_CXGBE);
9617 	return (rc);
9618 }
9619 
9620 static int
9621 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
9622 {
9623 	struct adapter *sc = arg1;
9624 	int coreid = arg2;
9625 	struct sbuf *sb;
9626 	int rc;
9627 
9628 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9629 	if (sb == NULL)
9630 		return (ENOMEM);
9631 
9632 	rc = sbuf_cim_la(sc, coreid, sb, M_WAITOK);
9633 	if (rc == 0)
9634 		rc = sbuf_finish(sb);
9635 	sbuf_delete(sb);
9636 	return (rc);
9637 }
9638 
9639 static void
9640 dump_cim_regs(struct adapter *sc)
9641 {
9642 	log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n",
9643 	    device_get_nameunit(sc->dev),
9644 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
9645 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
9646 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2),
9647 	    t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN),
9648 	    t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA));
9649 	log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n",
9650 	    device_get_nameunit(sc->dev),
9651 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
9652 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
9653 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800),
9654 	    t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800),
9655 	    t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN));
9656 }
9657 
9658 static void
9659 dump_cimla(struct adapter *sc)
9660 {
9661 	struct sbuf sb;
9662 	int rc;
9663 
9664 	if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
9665 		log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n",
9666 		    device_get_nameunit(sc->dev));
9667 		return;
9668 	}
9669 	rc = sbuf_cim_la(sc, 0, &sb, M_WAITOK);
9670 	if (rc == 0) {
9671 		rc = sbuf_finish(&sb);
9672 		if (rc == 0) {
9673 			log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n",
9674 			    device_get_nameunit(sc->dev), sbuf_data(&sb));
9675 		}
9676 	}
9677 	sbuf_delete(&sb);
9678 }
9679 
9680 void
9681 t4_os_cim_err(struct adapter *sc)
9682 {
9683 	atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
9684 }
9685 
9686 static int
9687 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
9688 {
9689 	struct adapter *sc = arg1;
9690 	u_int i;
9691 	struct sbuf *sb;
9692 	uint32_t *buf, *p;
9693 	int rc;
9694 
9695 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9696 	if (sb == NULL)
9697 		return (ENOMEM);
9698 
9699 	buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
9700 	    M_ZERO | M_WAITOK);
9701 
9702 	rc = 0;
9703 	mtx_lock(&sc->reg_lock);
9704 	if (hw_off_limits(sc))
9705 		rc = ENXIO;
9706 	else
9707 		t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
9708 	mtx_unlock(&sc->reg_lock);
9709 	if (rc)
9710 		goto done;
9711 
9712 	p = buf;
9713 	for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9714 		sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
9715 		    p[1], p[0]);
9716 	}
9717 
9718 	sbuf_printf(sb, "\n\nCnt ID Tag UE       Data       RDY VLD");
9719 	for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9720 		sbuf_printf(sb, "\n%3u %2u  %x   %u %08x%08x  %u   %u",
9721 		    (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
9722 		    (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
9723 		    (p[1] >> 2) | ((p[2] & 3) << 30),
9724 		    (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
9725 		    p[0] & 1);
9726 	}
9727 	rc = sbuf_finish(sb);
9728 done:
9729 	sbuf_delete(sb);
9730 	free(buf, M_CXGBE);
9731 	return (rc);
9732 }
9733 
9734 static int
9735 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
9736 {
9737 	struct adapter *sc = arg1;
9738 	u_int i;
9739 	struct sbuf *sb;
9740 	uint32_t *buf, *p;
9741 	int rc;
9742 
9743 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9744 	if (sb == NULL)
9745 		return (ENOMEM);
9746 
9747 	buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
9748 	    M_ZERO | M_WAITOK);
9749 
9750 	rc = 0;
9751 	mtx_lock(&sc->reg_lock);
9752 	if (hw_off_limits(sc))
9753 		rc = ENXIO;
9754 	else
9755 		t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
9756 	mtx_unlock(&sc->reg_lock);
9757 	if (rc)
9758 		goto done;
9759 
9760 	p = buf;
9761 	sbuf_printf(sb, "Cntl ID DataBE   Addr                 Data");
9762 	for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9763 		sbuf_printf(sb, "\n %02x  %02x  %04x  %08x %08x%08x%08x%08x",
9764 		    (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
9765 		    p[4], p[3], p[2], p[1], p[0]);
9766 	}
9767 
9768 	sbuf_printf(sb, "\n\nCntl ID               Data");
9769 	for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9770 		sbuf_printf(sb, "\n %02x  %02x %08x%08x%08x%08x",
9771 		    (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
9772 	}
9773 
9774 	rc = sbuf_finish(sb);
9775 done:
9776 	sbuf_delete(sb);
9777 	free(buf, M_CXGBE);
9778 	return (rc);
9779 }
9780 
9781 static int
9782 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
9783 {
9784 	struct adapter *sc = arg1;
9785 	struct sbuf *sb;
9786 	int rc, i;
9787 	uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9788 	uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9789 	uint16_t thres[CIM_NUM_IBQ];
9790 	uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
9791 	uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
9792 	u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
9793 	static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
9794 		"TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",	/* ibq's */
9795 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",	/* obq's */
9796 		"SGE0-RX", "SGE1-RX"	/* additional obq's (T5 onwards) */
9797 	};
9798 
9799 	MPASS(chip_id(sc) < CHELSIO_T7);
9800 
9801 	cim_num_obq = sc->chip_params->cim_num_obq;
9802 	if (is_t4(sc)) {
9803 		ibq_rdaddr = A_UP_IBQ_0_RDADDR;
9804 		obq_rdaddr = A_UP_OBQ_0_REALADDR;
9805 	} else {
9806 		ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
9807 		obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
9808 	}
9809 	nq = CIM_NUM_IBQ + cim_num_obq;
9810 
9811 	mtx_lock(&sc->reg_lock);
9812 	if (hw_off_limits(sc))
9813 		rc = ENXIO;
9814 	else {
9815 		rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
9816 		if (rc == 0) {
9817 			rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq,
9818 			    obq_wr);
9819 			if (rc == 0)
9820 				t4_read_cimq_cfg(sc, base, size, thres);
9821 		}
9822 	}
9823 	mtx_unlock(&sc->reg_lock);
9824 	if (rc)
9825 		return (rc);
9826 
9827 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9828 	if (sb == NULL)
9829 		return (ENOMEM);
9830 
9831 	sbuf_printf(sb,
9832 	    "  Queue  Base  Size Thres  RdPtr WrPtr  SOP  EOP Avail");
9833 
9834 	for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
9835 		sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
9836 		    qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
9837 		    G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9838 		    G_QUEREMFLITS(p[2]) * 16);
9839 	for ( ; i < nq; i++, p += 4, wr += 2)
9840 		sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u", qname[i],
9841 		    base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
9842 		    wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9843 		    G_QUEREMFLITS(p[2]) * 16);
9844 
9845 	rc = sbuf_finish(sb);
9846 	sbuf_delete(sb);
9847 
9848 	return (rc);
9849 }
9850 
9851 static int
9852 sysctl_cim_qcfg_t7(SYSCTL_HANDLER_ARGS)
9853 {
9854 	struct adapter *sc = arg1;
9855 	u_int coreid = arg2;
9856 	struct sbuf *sb;
9857 	int rc, i;
9858 	u_int addr;
9859 	uint16_t base[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
9860 	uint16_t size[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
9861 	uint16_t thres[CIM_NUM_IBQ_T7];
9862 	uint32_t obq_wr[2 * CIM_NUM_OBQ_T7], *wr = obq_wr;
9863 	uint32_t stat[4 * (CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7)], *p = stat;
9864 	static const char * const qname_ibq_t7[] = {
9865 		"TP0", "TP1", "TP2", "TP3", "ULP", "SGE0", "SGE1", "NC-SI",
9866 		"RSVD", "IPC1", "IPC2", "IPC3", "IPC4", "IPC5", "IPC6", "IPC7",
9867 	};
9868 	static const char * const qname_obq_t7[] = {
9869 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", "SGE0-RX",
9870 		"RSVD", "RSVD", "IPC1", "IPC2", "IPC3", "IPC4", "IPC5",
9871 		"IPC6", "IPC7"
9872 	};
9873 	static const char * const qname_ibq_sec_t7[] = {
9874 		"TP0", "TP1", "TP2", "TP3", "ULP", "SGE0", "RSVD", "RSVD",
9875 		"RSVD", "IPC0", "RSVD", "RSVD", "RSVD", "RSVD",	"RSVD", "RSVD",
9876 	};
9877 	static const char * const qname_obq_sec_t7[] = {
9878 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "RSVD", "SGE0-RX",
9879 		"RSVD", "RSVD", "IPC0", "RSVD", "RSVD", "RSVD", "RSVD",
9880 		"RSVD", "RSVD",
9881 	};
9882 
9883 	MPASS(chip_id(sc) >= CHELSIO_T7);
9884 
9885 	mtx_lock(&sc->reg_lock);
9886 	if (hw_off_limits(sc))
9887 		rc = ENXIO;
9888 	else {
9889 		rc = -t4_cim_read_core(sc, 1, coreid,
9890 		    A_T7_UP_IBQ_0_SHADOW_RDADDR, 4 * CIM_NUM_IBQ_T7, stat);
9891 		if (rc != 0)
9892 			goto unlock;
9893 
9894 		rc = -t4_cim_read_core(sc, 1, coreid,
9895 		    A_T7_UP_OBQ_0_SHADOW_RDADDR, 4 * CIM_NUM_OBQ_T7,
9896 		    &stat[4 * CIM_NUM_IBQ_T7]);
9897 		if (rc != 0)
9898 			goto unlock;
9899 
9900 		addr = A_T7_UP_OBQ_0_SHADOW_REALADDR;
9901 		for (i = 0; i < CIM_NUM_OBQ_T7 * 2; i++, addr += 8) {
9902 			rc = -t4_cim_read_core(sc, 1, coreid, addr, 1,
9903 			    &obq_wr[i]);
9904 			if (rc != 0)
9905 				goto unlock;
9906 		}
9907 		t4_read_cimq_cfg_core(sc, coreid, base, size, thres);
9908 	}
9909 unlock:
9910 	mtx_unlock(&sc->reg_lock);
9911 	if (rc)
9912 		return (rc);
9913 
9914 	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9915 	if (sb == NULL)
9916 		return (ENOMEM);
9917 
9918 	sbuf_printf(sb,
9919 	    "  Queue  Base  Size Thres  RdPtr WrPtr  SOP  EOP Avail");
9920 
9921 	for (i = 0; i < CIM_NUM_IBQ_T7; i++, p += 4) {
9922 		if (!size[i])
9923 			continue;
9924 
9925 		sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
9926 		    coreid == 0 ? qname_ibq_t7[i] : qname_ibq_sec_t7[i],
9927 		    base[i], size[i], thres[i], G_IBQRDADDR(p[0]) & 0xfff,
9928 		    G_IBQWRADDR(p[1]) & 0xfff, G_QUESOPCNT(p[3]),
9929 		    G_QUEEOPCNT(p[3]), G_T7_QUEREMFLITS(p[2]) * 16);
9930 	}
9931 
9932 	for ( ; i < CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7; i++, p += 4, wr += 2) {
9933 		if (!size[i])
9934 			continue;
9935 
9936 		sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u",
9937 		    coreid == 0 ? qname_obq_t7[i - CIM_NUM_IBQ_T7] :
9938 		    qname_obq_sec_t7[i - CIM_NUM_IBQ_T7],
9939 		    base[i], size[i], G_QUERDADDR(p[0]) & 0xfff,
9940 		    wr[0] << 1, G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9941 		    G_T7_QUEREMFLITS(p[2]) * 16);
9942 	}
9943 
9944 	rc = sbuf_finish(sb);
9945 	sbuf_delete(sb);
9946 	return (rc);
9947 }
9948 
9949 static int
9950 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
9951 {
9952 	struct adapter *sc = arg1;
9953 	struct sbuf *sb;
9954 	int rc;
9955 	struct tp_cpl_stats stats;
9956 
9957 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9958 	if (sb == NULL)
9959 		return (ENOMEM);
9960 
9961 	rc = 0;
9962 	mtx_lock(&sc->reg_lock);
9963 	if (hw_off_limits(sc))
9964 		rc = ENXIO;
9965 	else
9966 		t4_tp_get_cpl_stats(sc, &stats, 0);
9967 	mtx_unlock(&sc->reg_lock);
9968 	if (rc)
9969 		goto done;
9970 
9971 	if (sc->chip_params->nchan > 2) {
9972 		sbuf_printf(sb, "                 channel 0  channel 1"
9973 		    "  channel 2  channel 3");
9974 		sbuf_printf(sb, "\nCPL requests:   %10u %10u %10u %10u",
9975 		    stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
9976 		sbuf_printf(sb, "\nCPL responses:  %10u %10u %10u %10u",
9977 		    stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
9978 	} else {
9979 		sbuf_printf(sb, "                 channel 0  channel 1");
9980 		sbuf_printf(sb, "\nCPL requests:   %10u %10u",
9981 		    stats.req[0], stats.req[1]);
9982 		sbuf_printf(sb, "\nCPL responses:  %10u %10u",
9983 		    stats.rsp[0], stats.rsp[1]);
9984 	}
9985 
9986 	rc = sbuf_finish(sb);
9987 done:
9988 	sbuf_delete(sb);
9989 	return (rc);
9990 }
9991 
9992 static int
9993 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
9994 {
9995 	struct adapter *sc = arg1;
9996 	struct sbuf *sb;
9997 	int rc;
9998 	struct tp_usm_stats stats;
9999 
10000 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10001 	if (sb == NULL)
10002 		return (ENOMEM);
10003 
10004 	rc = 0;
10005 	mtx_lock(&sc->reg_lock);
10006 	if (hw_off_limits(sc))
10007 		rc = ENXIO;
10008 	else
10009 		t4_get_usm_stats(sc, &stats, 1);
10010 	mtx_unlock(&sc->reg_lock);
10011 	if (rc == 0) {
10012 		sbuf_printf(sb, "Frames: %u\n", stats.frames);
10013 		sbuf_printf(sb, "Octets: %ju\n", stats.octets);
10014 		sbuf_printf(sb, "Drops:  %u", stats.drops);
10015 		rc = sbuf_finish(sb);
10016 	}
10017 	sbuf_delete(sb);
10018 
10019 	return (rc);
10020 }
10021 
10022 static int
10023 sysctl_tid_stats(SYSCTL_HANDLER_ARGS)
10024 {
10025 	struct adapter *sc = arg1;
10026 	struct sbuf *sb;
10027 	int rc;
10028 	struct tp_tid_stats stats;
10029 
10030 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10031 	if (sb == NULL)
10032 		return (ENOMEM);
10033 
10034 	rc = 0;
10035 	mtx_lock(&sc->reg_lock);
10036 	if (hw_off_limits(sc))
10037 		rc = ENXIO;
10038 	else
10039 		t4_tp_get_tid_stats(sc, &stats, 1);
10040 	mtx_unlock(&sc->reg_lock);
10041 	if (rc == 0) {
10042 		sbuf_printf(sb, "Delete:     %u\n", stats.del);
10043 		sbuf_printf(sb, "Invalidate: %u\n", stats.inv);
10044 		sbuf_printf(sb, "Active:     %u\n", stats.act);
10045 		sbuf_printf(sb, "Passive:    %u", stats.pas);
10046 		rc = sbuf_finish(sb);
10047 	}
10048 	sbuf_delete(sb);
10049 
10050 	return (rc);
10051 }
10052 
10053 static const char * const devlog_level_strings[] = {
10054 	[FW_DEVLOG_LEVEL_EMERG]		= "EMERG",
10055 	[FW_DEVLOG_LEVEL_CRIT]		= "CRIT",
10056 	[FW_DEVLOG_LEVEL_ERR]		= "ERR",
10057 	[FW_DEVLOG_LEVEL_NOTICE]	= "NOTICE",
10058 	[FW_DEVLOG_LEVEL_INFO]		= "INFO",
10059 	[FW_DEVLOG_LEVEL_DEBUG]		= "DEBUG"
10060 };
10061 
10062 static const char * const devlog_facility_strings[] = {
10063 	[FW_DEVLOG_FACILITY_CORE]	= "CORE",
10064 	[FW_DEVLOG_FACILITY_CF]		= "CF",
10065 	[FW_DEVLOG_FACILITY_SCHED]	= "SCHED",
10066 	[FW_DEVLOG_FACILITY_TIMER]	= "TIMER",
10067 	[FW_DEVLOG_FACILITY_RES]	= "RES",
10068 	[FW_DEVLOG_FACILITY_HW]		= "HW",
10069 	[FW_DEVLOG_FACILITY_FLR]	= "FLR",
10070 	[FW_DEVLOG_FACILITY_DMAQ]	= "DMAQ",
10071 	[FW_DEVLOG_FACILITY_PHY]	= "PHY",
10072 	[FW_DEVLOG_FACILITY_MAC]	= "MAC",
10073 	[FW_DEVLOG_FACILITY_PORT]	= "PORT",
10074 	[FW_DEVLOG_FACILITY_VI]		= "VI",
10075 	[FW_DEVLOG_FACILITY_FILTER]	= "FILTER",
10076 	[FW_DEVLOG_FACILITY_ACL]	= "ACL",
10077 	[FW_DEVLOG_FACILITY_TM]		= "TM",
10078 	[FW_DEVLOG_FACILITY_QFC]	= "QFC",
10079 	[FW_DEVLOG_FACILITY_DCB]	= "DCB",
10080 	[FW_DEVLOG_FACILITY_ETH]	= "ETH",
10081 	[FW_DEVLOG_FACILITY_OFLD]	= "OFLD",
10082 	[FW_DEVLOG_FACILITY_RI]		= "RI",
10083 	[FW_DEVLOG_FACILITY_ISCSI]	= "ISCSI",
10084 	[FW_DEVLOG_FACILITY_FCOE]	= "FCOE",
10085 	[FW_DEVLOG_FACILITY_FOISCSI]	= "FOISCSI",
10086 	[FW_DEVLOG_FACILITY_FOFCOE]	= "FOFCOE",
10087 	[FW_DEVLOG_FACILITY_CHNET]	= "CHNET",
10088 };
10089 
10090 static int
10091 sbuf_devlog(struct adapter *sc, int coreid, struct sbuf *sb, int flags)
10092 {
10093 	int i, j, rc, nentries, first = 0;
10094 	struct devlog_params *dparams = &sc->params.devlog;
10095 	struct fw_devlog_e *buf, *e;
10096 	uint32_t addr, size;
10097 	uint64_t ftstamp = UINT64_MAX;
10098 
10099 	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
10100 	    ("%s: bad coreid %d\n", __func__, coreid));
10101 
10102 	if (dparams->addr == 0)
10103 		return (ENXIO);
10104 
10105 	size = dparams->size / sc->params.ncores;
10106 	addr = dparams->addr + coreid * size;
10107 
10108 	MPASS(flags == M_WAITOK || flags == M_NOWAIT);
10109 	buf = malloc(size, M_CXGBE, M_ZERO | flags);
10110 	if (buf == NULL)
10111 		return (ENOMEM);
10112 
10113 	mtx_lock(&sc->reg_lock);
10114 	if (hw_off_limits(sc))
10115 		rc = ENXIO;
10116 	else
10117 		rc = read_via_memwin(sc, 1, addr, (void *)buf, size);
10118 	mtx_unlock(&sc->reg_lock);
10119 	if (rc != 0)
10120 		goto done;
10121 
10122 	nentries = size / sizeof(struct fw_devlog_e);
10123 	for (i = 0; i < nentries; i++) {
10124 		e = &buf[i];
10125 
10126 		if (e->timestamp == 0)
10127 			break;	/* end */
10128 
10129 		e->timestamp = be64toh(e->timestamp);
10130 		e->seqno = be32toh(e->seqno);
10131 		for (j = 0; j < 8; j++)
10132 			e->params[j] = be32toh(e->params[j]);
10133 
10134 		if (e->timestamp < ftstamp) {
10135 			ftstamp = e->timestamp;
10136 			first = i;
10137 		}
10138 	}
10139 
10140 	if (buf[first].timestamp == 0)
10141 		goto done;	/* nothing in the log */
10142 
10143 	sbuf_printf(sb, "%10s  %15s  %8s  %8s  %s\n",
10144 	    "Seq#", "Tstamp", "Level", "Facility", "Message");
10145 
10146 	i = first;
10147 	do {
10148 		e = &buf[i];
10149 		if (e->timestamp == 0)
10150 			break;	/* end */
10151 
10152 		sbuf_printf(sb, "%10d  %15ju  %8s  %8s  ",
10153 		    e->seqno, e->timestamp,
10154 		    (e->level < nitems(devlog_level_strings) ?
10155 			devlog_level_strings[e->level] : "UNKNOWN"),
10156 		    (e->facility < nitems(devlog_facility_strings) ?
10157 			devlog_facility_strings[e->facility] : "UNKNOWN"));
10158 		sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
10159 		    e->params[2], e->params[3], e->params[4],
10160 		    e->params[5], e->params[6], e->params[7]);
10161 
10162 		if (++i == nentries)
10163 			i = 0;
10164 	} while (i != first);
10165 done:
10166 	free(buf, M_CXGBE);
10167 	return (rc);
10168 }
10169 
10170 static int
10171 sysctl_devlog(SYSCTL_HANDLER_ARGS)
10172 {
10173 	struct adapter *sc = arg1;
10174 	int rc, i, coreid = arg2;
10175 	struct sbuf *sb;
10176 
10177 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10178 	if (sb == NULL)
10179 		return (ENOMEM);
10180 	if (coreid == -1) {
10181 		/* -1 means all cores */
10182 		for (i = rc = 0; i < sc->params.ncores && rc == 0; i++) {
10183 			if (sc->params.ncores > 0)
10184 				sbuf_printf(sb, "=== CIM core %u ===\n", i);
10185 			rc = sbuf_devlog(sc, i, sb, M_WAITOK);
10186 		}
10187 	} else {
10188 		KASSERT(coreid >= 0 && coreid < sc->params.ncores,
10189 		    ("%s: bad coreid %d\n", __func__, coreid));
10190 		rc = sbuf_devlog(sc, coreid, sb, M_WAITOK);
10191 	}
10192 	if (rc == 0)
10193 		rc = sbuf_finish(sb);
10194 	sbuf_delete(sb);
10195 	return (rc);
10196 }
10197 
10198 static void
10199 dump_devlog(struct adapter *sc)
10200 {
10201 	int rc, i;
10202 	struct sbuf sb;
10203 
10204 	if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
10205 		log(LOG_DEBUG, "%s: failed to generate devlog dump.\n",
10206 		    device_get_nameunit(sc->dev));
10207 		return;
10208 	}
10209 	for (i = rc = 0; i < sc->params.ncores && rc == 0; i++) {
10210 		if (sc->params.ncores > 0)
10211 			sbuf_printf(&sb, "=== CIM core %u ===\n", i);
10212 		rc = sbuf_devlog(sc, i, &sb, M_WAITOK);
10213 	}
10214 	if (rc == 0) {
10215 		sbuf_finish(&sb);
10216 		log(LOG_DEBUG, "%s: device log follows.\n%s",
10217 		    device_get_nameunit(sc->dev), sbuf_data(&sb));
10218 	}
10219 	sbuf_delete(&sb);
10220 }
10221 
10222 static int
10223 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
10224 {
10225 	struct adapter *sc = arg1;
10226 	struct sbuf *sb;
10227 	int rc;
10228 	struct tp_fcoe_stats stats[MAX_NCHAN];
10229 	int i, nchan = sc->chip_params->nchan;
10230 
10231 	rc = 0;
10232 	mtx_lock(&sc->reg_lock);
10233 	if (hw_off_limits(sc))
10234 		rc = ENXIO;
10235 	else {
10236 		for (i = 0; i < nchan; i++)
10237 			t4_get_fcoe_stats(sc, i, &stats[i], 1);
10238 	}
10239 	mtx_unlock(&sc->reg_lock);
10240 	if (rc != 0)
10241 		return (rc);
10242 
10243 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10244 	if (sb == NULL)
10245 		return (ENOMEM);
10246 
10247 	if (nchan > 2) {
10248 		sbuf_printf(sb, "                   channel 0        channel 1"
10249 		    "        channel 2        channel 3");
10250 		sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju %16ju %16ju",
10251 		    stats[0].octets_ddp, stats[1].octets_ddp,
10252 		    stats[2].octets_ddp, stats[3].octets_ddp);
10253 		sbuf_printf(sb, "\nframesDDP:  %16u %16u %16u %16u",
10254 		    stats[0].frames_ddp, stats[1].frames_ddp,
10255 		    stats[2].frames_ddp, stats[3].frames_ddp);
10256 		sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
10257 		    stats[0].frames_drop, stats[1].frames_drop,
10258 		    stats[2].frames_drop, stats[3].frames_drop);
10259 	} else {
10260 		sbuf_printf(sb, "                   channel 0        channel 1");
10261 		sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju",
10262 		    stats[0].octets_ddp, stats[1].octets_ddp);
10263 		sbuf_printf(sb, "\nframesDDP:  %16u %16u",
10264 		    stats[0].frames_ddp, stats[1].frames_ddp);
10265 		sbuf_printf(sb, "\nframesDrop: %16u %16u",
10266 		    stats[0].frames_drop, stats[1].frames_drop);
10267 	}
10268 
10269 	rc = sbuf_finish(sb);
10270 	sbuf_delete(sb);
10271 
10272 	return (rc);
10273 }
10274 
10275 static int
10276 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
10277 {
10278 	struct adapter *sc = arg1;
10279 	struct sbuf *sb;
10280 	int rc, i;
10281 	unsigned int map, kbps, ipg, mode;
10282 	unsigned int pace_tab[NTX_SCHED];
10283 
10284 	sb = sbuf_new_for_sysctl(NULL, NULL, 512, req);
10285 	if (sb == NULL)
10286 		return (ENOMEM);
10287 
10288 	mtx_lock(&sc->reg_lock);
10289 	if (hw_off_limits(sc)) {
10290 		mtx_unlock(&sc->reg_lock);
10291 		rc = ENXIO;
10292 		goto done;
10293 	}
10294 
10295 	map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
10296 	mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
10297 	t4_read_pace_tbl(sc, pace_tab);
10298 	mtx_unlock(&sc->reg_lock);
10299 
10300 	sbuf_printf(sb, "Scheduler  Mode   Channel  Rate (Kbps)   "
10301 	    "Class IPG (0.1 ns)   Flow IPG (us)");
10302 
10303 	for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
10304 		t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
10305 		sbuf_printf(sb, "\n    %u      %-5s     %u     ", i,
10306 		    (mode & (1 << i)) ? "flow" : "class", map & 3);
10307 		if (kbps)
10308 			sbuf_printf(sb, "%9u     ", kbps);
10309 		else
10310 			sbuf_printf(sb, " disabled     ");
10311 
10312 		if (ipg)
10313 			sbuf_printf(sb, "%13u        ", ipg);
10314 		else
10315 			sbuf_printf(sb, "     disabled        ");
10316 
10317 		if (pace_tab[i])
10318 			sbuf_printf(sb, "%10u", pace_tab[i]);
10319 		else
10320 			sbuf_printf(sb, "  disabled");
10321 	}
10322 	rc = sbuf_finish(sb);
10323 done:
10324 	sbuf_delete(sb);
10325 	return (rc);
10326 }
10327 
10328 static int
10329 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
10330 {
10331 	struct adapter *sc = arg1;
10332 	struct sbuf *sb;
10333 	int rc, i, j;
10334 	uint64_t *p0, *p1;
10335 	struct lb_port_stats s[2];
10336 	static const char *stat_name[] = {
10337 		"OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
10338 		"UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
10339 		"Frames128To255:", "Frames256To511:", "Frames512To1023:",
10340 		"Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
10341 		"BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
10342 		"BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
10343 		"BG2FramesTrunc:", "BG3FramesTrunc:"
10344 	};
10345 
10346 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10347 	if (sb == NULL)
10348 		return (ENOMEM);
10349 
10350 	memset(s, 0, sizeof(s));
10351 
10352 	rc = 0;
10353 	for (i = 0; i < sc->chip_params->nchan; i += 2) {
10354 		mtx_lock(&sc->reg_lock);
10355 		if (hw_off_limits(sc))
10356 			rc = ENXIO;
10357 		else {
10358 			t4_get_lb_stats(sc, i, &s[0]);
10359 			t4_get_lb_stats(sc, i + 1, &s[1]);
10360 		}
10361 		mtx_unlock(&sc->reg_lock);
10362 		if (rc != 0)
10363 			break;
10364 
10365 		p0 = &s[0].octets;
10366 		p1 = &s[1].octets;
10367 		sbuf_printf(sb, "%s                       Loopback %u"
10368 		    "           Loopback %u", i == 0 ? "" : "\n", i, i + 1);
10369 
10370 		for (j = 0; j < nitems(stat_name); j++)
10371 			sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
10372 				   *p0++, *p1++);
10373 	}
10374 
10375 	if (rc == 0)
10376 		rc = sbuf_finish(sb);
10377 	sbuf_delete(sb);
10378 
10379 	return (rc);
10380 }
10381 
10382 static int
10383 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
10384 {
10385 	int rc = 0;
10386 	struct port_info *pi = arg1;
10387 	struct link_config *lc = &pi->link_cfg;
10388 	struct sbuf *sb;
10389 
10390 	sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
10391 	if (sb == NULL)
10392 		return (ENOMEM);
10393 
10394 	if (lc->link_ok || lc->link_down_rc == 255)
10395 		sbuf_printf(sb, "n/a");
10396 	else
10397 		sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
10398 
10399 	rc = sbuf_finish(sb);
10400 	sbuf_delete(sb);
10401 
10402 	return (rc);
10403 }
10404 
10405 struct mem_desc {
10406 	uint64_t base;
10407 	uint64_t limit;
10408 	u_int idx;
10409 };
10410 
10411 static int
10412 mem_desc_cmp(const void *a, const void *b)
10413 {
10414 	const uint64_t v1 = ((const struct mem_desc *)a)->base;
10415 	const uint64_t v2 = ((const struct mem_desc *)b)->base;
10416 
10417 	if (v1 < v2)
10418 		return (-1);
10419 	else if (v1 > v2)
10420 		return (1);
10421 
10422 	return (0);
10423 }
10424 
10425 static void
10426 mem_region_show(struct sbuf *sb, const char *name, uint64_t from, uint64_t to)
10427 {
10428 	uintmax_t size;
10429 
10430 	if (from == to)
10431 		return;
10432 
10433 	size = to - from + 1;
10434 	if (size == 0)
10435 		return;
10436 
10437 	if (from > UINT32_MAX || to > UINT32_MAX)
10438 		sbuf_printf(sb, "%-18s 0x%012jx-0x%012jx [%ju]\n", name,
10439 		    (uintmax_t)from, (uintmax_t)to, size);
10440 	else
10441 		sbuf_printf(sb, "%-18s 0x%08jx-0x%08jx [%ju]\n", name,
10442 		    (uintmax_t)from, (uintmax_t)to, size);
10443 }
10444 
10445 static int
10446 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
10447 {
10448 	struct adapter *sc = arg1;
10449 	struct sbuf *sb;
10450 	int rc, i, n, nchan;
10451 	uint32_t lo, hi, used, free, alloc;
10452 	static const char *memory[] = {
10453 		"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:"
10454 	};
10455 	static const char *region[] = {
10456 		"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
10457 		"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
10458 		"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
10459 		"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
10460 		"RQUDP region:", "PBL region:", "TXPBL region:",
10461 		"TLSKey region:", "RRQ region:", "NVMe STAG region:",
10462 		"NVMe RQ region:", "NVMe RXPBL region:", "NVMe TPT region:",
10463 		"NVMe TXPBL region:", "DBVFIFO region:", "ULPRX state:",
10464 		"ULPTX state:", "RoCE RRQ region:", "On-chip queues:",
10465 	};
10466 	struct mem_desc avail[4];
10467 	struct mem_desc mem[nitems(region) + 3];	/* up to 3 holes */
10468 	struct mem_desc *md;
10469 
10470 	rc = sysctl_wire_old_buffer(req, 0);
10471 	if (rc != 0)
10472 		return (rc);
10473 
10474 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10475 	if (sb == NULL)
10476 		return (ENOMEM);
10477 
10478 	for (i = 0; i < nitems(mem); i++) {
10479 		mem[i].limit = 0;
10480 		mem[i].idx = i;
10481 	}
10482 
10483 	mtx_lock(&sc->reg_lock);
10484 	if (hw_off_limits(sc)) {
10485 		rc = ENXIO;
10486 		goto done;
10487 	}
10488 
10489 	/* Find and sort the populated memory ranges */
10490 	i = 0;
10491 	lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
10492 	if (lo & F_EDRAM0_ENABLE) {
10493 		hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
10494 		if (chip_id(sc) >= CHELSIO_T7) {
10495 			avail[i].base = (uint64_t)G_T7_EDRAM0_BASE(hi) << 20;
10496 			avail[i].limit = avail[i].base +
10497 			    (G_T7_EDRAM0_SIZE(hi) << 20);
10498 		} else {
10499 			avail[i].base = (uint64_t)G_EDRAM0_BASE(hi) << 20;
10500 			avail[i].limit = avail[i].base +
10501 			    (G_EDRAM0_SIZE(hi) << 20);
10502 		}
10503 		avail[i].idx = 0;
10504 		i++;
10505 	}
10506 	if (lo & F_EDRAM1_ENABLE) {
10507 		hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
10508 		if (chip_id(sc) >= CHELSIO_T7) {
10509 			avail[i].base = (uint64_t)G_T7_EDRAM1_BASE(hi) << 20;
10510 			avail[i].limit = avail[i].base +
10511 			    (G_T7_EDRAM1_SIZE(hi) << 20);
10512 		} else {
10513 			avail[i].base = (uint64_t)G_EDRAM1_BASE(hi) << 20;
10514 			avail[i].limit = avail[i].base +
10515 			    (G_EDRAM1_SIZE(hi) << 20);
10516 		}
10517 		avail[i].idx = 1;
10518 		i++;
10519 	}
10520 	if (lo & F_EXT_MEM_ENABLE) {
10521 		switch (chip_id(sc)) {
10522 		case CHELSIO_T4:
10523 		case CHELSIO_T6:
10524 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
10525 			avail[i].base = (uint64_t)G_EXT_MEM_BASE(hi) << 20;
10526 			avail[i].limit = avail[i].base +
10527 			    (G_EXT_MEM_SIZE(hi) << 20);
10528 			avail[i].idx = 2;
10529 			break;
10530 		case CHELSIO_T5:
10531 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY0_BAR);
10532 			avail[i].base = (uint64_t)G_EXT_MEM0_BASE(hi) << 20;
10533 			avail[i].limit = avail[i].base +
10534 			    (G_EXT_MEM0_SIZE(hi) << 20);
10535 			avail[i].idx = 3;	/* Call it MC0 for T5 */
10536 			break;
10537 		default:
10538 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY0_BAR);
10539 			avail[i].base = (uint64_t)G_T7_EXT_MEM0_BASE(hi) << 20;
10540 			avail[i].limit = avail[i].base +
10541 			    (G_T7_EXT_MEM0_SIZE(hi) << 20);
10542 			avail[i].idx = 3;	/* Call it MC0 for T7+ */
10543 			break;
10544 		}
10545 		i++;
10546 	}
10547 	if (lo & F_EXT_MEM1_ENABLE && !(lo & F_MC_SPLIT)) {
10548 		/* Only T5 and T7+ have 2 MCs. */
10549 		MPASS(is_t5(sc) || chip_id(sc) >= CHELSIO_T7);
10550 
10551 		hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
10552 		if (chip_id(sc) >= CHELSIO_T7) {
10553 			avail[i].base = (uint64_t)G_T7_EXT_MEM1_BASE(hi) << 20;
10554 			avail[i].limit = avail[i].base +
10555 			    (G_T7_EXT_MEM1_SIZE(hi) << 20);
10556 		} else {
10557 			avail[i].base = (uint64_t)G_EXT_MEM1_BASE(hi) << 20;
10558 			avail[i].limit = avail[i].base +
10559 			    (G_EXT_MEM1_SIZE(hi) << 20);
10560 		}
10561 		avail[i].idx = 4;
10562 		i++;
10563 	}
10564 	if (lo & F_HMA_MUX) {
10565 		/* Only T6+ have HMA. */
10566 		MPASS(chip_id(sc) >= CHELSIO_T6);
10567 
10568 		if (chip_id(sc) >= CHELSIO_T7) {
10569 			hi = t4_read_reg(sc, A_MA_HOST_MEMORY_BAR);
10570 			avail[i].base = (uint64_t)G_HMATARGETBASE(hi) << 20;
10571 			avail[i].limit = avail[i].base +
10572 			    (G_T7_HMA_SIZE(hi) << 20);
10573 		} else {
10574 			hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
10575 			avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
10576 			avail[i].limit = avail[i].base +
10577 			    (G_EXT_MEM1_SIZE(hi) << 20);
10578 		}
10579 		avail[i].idx = 5;
10580 		i++;
10581 	}
10582 	MPASS(i <= nitems(avail));
10583 	if (!i)                                    /* no memory available */
10584 		goto done;
10585 	qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
10586 
10587 	md = &mem[0];
10588 	(md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
10589 	(md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
10590 	(md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
10591 	(md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10592 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
10593 	(md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
10594 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
10595 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
10596 	(md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
10597 
10598 	/* the next few have explicit upper bounds */
10599 	md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
10600 	md->limit = md->base - 1 +
10601 		    t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
10602 		    G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
10603 	md++;
10604 
10605 	md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
10606 	md->limit = md->base - 1 +
10607 		    t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
10608 		    G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
10609 	md++;
10610 
10611 	if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
10612 		if (chip_id(sc) <= CHELSIO_T5)
10613 			md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
10614 		else
10615 			md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
10616 		md->limit = 0;
10617 	} else {
10618 		md->base = 0;
10619 		md->idx = nitems(region);  /* hide it */
10620 	}
10621 	md++;
10622 
10623 #define ulp_region(reg) do {\
10624 		const u_int shift = chip_id(sc) >= CHELSIO_T7 ? 4 : 0; \
10625 		md->base = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT) << shift; \
10626 		md->limit = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) << shift; \
10627 		md->limit += (1 << shift) - 1; \
10628 		md++; \
10629 	} while (0)
10630 
10631 #define	hide_ulp_region() do { \
10632 		md->base = 0; \
10633 		md->idx = nitems(region); \
10634 		md++; \
10635 	} while (0)
10636 
10637 	ulp_region(RX_ISCSI);
10638 	ulp_region(RX_TDDP);
10639 	ulp_region(TX_TPT);
10640 	ulp_region(RX_STAG);
10641 	ulp_region(RX_RQ);
10642 	if (chip_id(sc) < CHELSIO_T7)
10643 		ulp_region(RX_RQUDP);
10644 	else
10645 		hide_ulp_region();
10646 	ulp_region(RX_PBL);
10647 	ulp_region(TX_PBL);
10648 	if (chip_id(sc) >= CHELSIO_T6)
10649 		ulp_region(RX_TLS_KEY);
10650 	else
10651 		hide_ulp_region();
10652 	if (chip_id(sc) >= CHELSIO_T7) {
10653 		ulp_region(RX_RRQ);
10654 		ulp_region(RX_NVME_TCP_STAG);
10655 		ulp_region(RX_NVME_TCP_RQ);
10656 		ulp_region(RX_NVME_TCP_PBL);
10657 		ulp_region(TX_NVME_TCP_TPT);
10658 		ulp_region(TX_NVME_TCP_PBL);
10659 	} else {
10660 		hide_ulp_region();
10661 		hide_ulp_region();
10662 		hide_ulp_region();
10663 		hide_ulp_region();
10664 		hide_ulp_region();
10665 		hide_ulp_region();
10666 	}
10667 #undef ulp_region
10668 #undef hide_ulp_region
10669 
10670 	md->base = 0;
10671 	if (is_t4(sc))
10672 		md->idx = nitems(region);
10673 	else {
10674 		uint32_t size = 0;
10675 		uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
10676 		uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
10677 
10678 		if (is_t5(sc)) {
10679 			if (sge_ctrl & F_VFIFO_ENABLE)
10680 				size = fifo_size << 2;
10681 		} else
10682 			size = G_T6_DBVFIFO_SIZE(fifo_size) << 6;
10683 
10684 		if (size) {
10685 			md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR);
10686 			md->limit = md->base + size - 1;
10687 		} else
10688 			md->idx = nitems(region);
10689 	}
10690 	md++;
10691 
10692 	md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
10693 	md->limit = 0;
10694 	md++;
10695 	md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
10696 	md->limit = 0;
10697 	md++;
10698 
10699 	if (chip_id(sc) >= CHELSIO_T7) {
10700 		t4_tp_pio_read(sc, &lo, 1, A_TP_ROCE_RRQ_BASE, false);
10701 		md->base = lo;
10702 	} else {
10703 		md->base = 0;
10704 		md->idx = nitems(region);
10705 	}
10706 	md++;
10707 
10708 	md->base = sc->vres.ocq.start;
10709 	if (sc->vres.ocq.size)
10710 		md->limit = md->base + sc->vres.ocq.size - 1;
10711 	else
10712 		md->idx = nitems(region);  /* hide it */
10713 	md++;
10714 
10715 	/* add any address-space holes, there can be up to 3 */
10716 	for (n = 0; n < i - 1; n++)
10717 		if (avail[n].limit < avail[n + 1].base)
10718 			(md++)->base = avail[n].limit;
10719 	if (avail[n].limit)
10720 		(md++)->base = avail[n].limit;
10721 
10722 	n = md - mem;
10723 	MPASS(n <= nitems(mem));
10724 	qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
10725 
10726 	for (lo = 0; lo < i; lo++)
10727 		mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
10728 				avail[lo].limit - 1);
10729 
10730 	sbuf_printf(sb, "\n");
10731 	for (i = 0; i < n; i++) {
10732 		if (mem[i].idx >= nitems(region))
10733 			continue;                        /* skip holes */
10734 		if (!mem[i].limit)
10735 			mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
10736 		mem_region_show(sb, region[mem[i].idx], mem[i].base,
10737 				mem[i].limit);
10738 	}
10739 
10740 	lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
10741 	hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
10742 	if (hi != lo  - 1) {
10743 		sbuf_printf(sb, "\n");
10744 		mem_region_show(sb, "uP RAM:", lo, hi);
10745 	}
10746 
10747 	lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
10748 	hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
10749 	if (hi != lo  - 1)
10750 		mem_region_show(sb, "uP Extmem2:", lo, hi);
10751 
10752 	lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
10753 	if (chip_id(sc) >= CHELSIO_T7)
10754 		nchan = 1 << G_T7_PMRXNUMCHN(lo);
10755 	else
10756 		nchan = lo & F_PMRXNUMCHN ? 2 : 1;
10757 	for (i = 0, free = 0; i < nchan; i++)
10758 		free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT));
10759 	sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n",
10760 		   G_PMRXMAXPAGE(lo), free,
10761 		   t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, nchan);
10762 
10763 	lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
10764 	hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
10765 	if (chip_id(sc) >= CHELSIO_T7)
10766 		nchan = 1 << G_T7_PMTXNUMCHN(lo);
10767 	else
10768 		nchan = 1 << G_PMTXNUMCHN(lo);
10769 	for (i = 0, free = 0; i < nchan; i++)
10770 		free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT));
10771 	sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n",
10772 		   G_PMTXMAXPAGE(lo), free,
10773 		   hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
10774 		   hi >= (1 << 20) ? 'M' : 'K', nchan);
10775 	sbuf_printf(sb, "%u p-structs (%u free)\n",
10776 		   t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT),
10777 		   G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT)));
10778 
10779 	for (i = 0; i < 4; i++) {
10780 		if (chip_id(sc) > CHELSIO_T5)
10781 			lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
10782 		else
10783 			lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
10784 		if (is_t5(sc)) {
10785 			used = G_T5_USED(lo);
10786 			alloc = G_T5_ALLOC(lo);
10787 		} else {
10788 			used = G_USED(lo);
10789 			alloc = G_ALLOC(lo);
10790 		}
10791 		/* For T6+ these are MAC buffer groups */
10792 		sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
10793 		    i, used, alloc);
10794 	}
10795 	for (i = 0; i < sc->chip_params->nchan; i++) {
10796 		if (chip_id(sc) > CHELSIO_T5)
10797 			lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
10798 		else
10799 			lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
10800 		if (is_t5(sc)) {
10801 			used = G_T5_USED(lo);
10802 			alloc = G_T5_ALLOC(lo);
10803 		} else {
10804 			used = G_USED(lo);
10805 			alloc = G_ALLOC(lo);
10806 		}
10807 		/* For T6+ these are MAC buffer groups */
10808 		sbuf_printf(sb,
10809 		    "\nLoopback %d using %u pages out of %u allocated",
10810 		    i, used, alloc);
10811 	}
10812 done:
10813 	mtx_unlock(&sc->reg_lock);
10814 	if (rc == 0)
10815 		rc = sbuf_finish(sb);
10816 	sbuf_delete(sb);
10817 	return (rc);
10818 }
10819 
10820 static inline void
10821 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
10822 {
10823 	*mask = x | y;
10824 	y = htobe64(y);
10825 	memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
10826 }
10827 
10828 static int
10829 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
10830 {
10831 	struct adapter *sc = arg1;
10832 	struct sbuf *sb;
10833 	int rc, i;
10834 
10835 	MPASS(chip_id(sc) <= CHELSIO_T5);
10836 
10837 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10838 	if (sb == NULL)
10839 		return (ENOMEM);
10840 
10841 	sbuf_printf(sb,
10842 	    "Idx  Ethernet address     Mask     Vld Ports PF"
10843 	    "  VF              Replication             P0 P1 P2 P3  ML");
10844 	rc = 0;
10845 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
10846 		uint64_t tcamx, tcamy, mask;
10847 		uint32_t cls_lo, cls_hi;
10848 		uint8_t addr[ETHER_ADDR_LEN];
10849 
10850 		mtx_lock(&sc->reg_lock);
10851 		if (hw_off_limits(sc))
10852 			rc = ENXIO;
10853 		else {
10854 			tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
10855 			tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
10856 		}
10857 		mtx_unlock(&sc->reg_lock);
10858 		if (rc != 0)
10859 			break;
10860 		if (tcamx & tcamy)
10861 			continue;
10862 		tcamxy2valmask(tcamx, tcamy, addr, &mask);
10863 		mtx_lock(&sc->reg_lock);
10864 		if (hw_off_limits(sc))
10865 			rc = ENXIO;
10866 		else {
10867 			cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
10868 			cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
10869 		}
10870 		mtx_unlock(&sc->reg_lock);
10871 		if (rc != 0)
10872 			break;
10873 		sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
10874 			   "  %c   %#x%4u%4d", i, addr[0], addr[1], addr[2],
10875 			   addr[3], addr[4], addr[5], (uintmax_t)mask,
10876 			   (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
10877 			   G_PORTMAP(cls_hi), G_PF(cls_lo),
10878 			   (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
10879 
10880 		if (cls_lo & F_REPLICATE) {
10881 			struct fw_ldst_cmd ldst_cmd;
10882 
10883 			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10884 			ldst_cmd.op_to_addrspace =
10885 			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
10886 				F_FW_CMD_REQUEST | F_FW_CMD_READ |
10887 				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
10888 			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
10889 			ldst_cmd.u.mps.rplc.fid_idx =
10890 			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
10891 				V_FW_LDST_CMD_IDX(i));
10892 
10893 			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
10894 			    "t4mps");
10895 			if (rc)
10896 				break;
10897 			if (hw_off_limits(sc))
10898 				rc = ENXIO;
10899 			else
10900 				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
10901 				    sizeof(ldst_cmd), &ldst_cmd);
10902 			end_synchronized_op(sc, 0);
10903 			if (rc != 0)
10904 				break;
10905 			else {
10906 				sbuf_printf(sb, " %08x %08x %08x %08x",
10907 				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
10908 				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
10909 				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
10910 				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
10911 			}
10912 		} else
10913 			sbuf_printf(sb, "%36s", "");
10914 
10915 		sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
10916 		    G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
10917 		    G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
10918 	}
10919 
10920 	if (rc)
10921 		(void) sbuf_finish(sb);
10922 	else
10923 		rc = sbuf_finish(sb);
10924 	sbuf_delete(sb);
10925 
10926 	return (rc);
10927 }
10928 
10929 static int
10930 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
10931 {
10932 	struct adapter *sc = arg1;
10933 	struct sbuf *sb;
10934 	int rc, i;
10935 
10936 	MPASS(chip_id(sc) == CHELSIO_T6);
10937 
10938 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10939 	if (sb == NULL)
10940 		return (ENOMEM);
10941 
10942 	sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
10943 	    "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
10944 	    "                           Replication"
10945 	    "                                    P0 P1 P2 P3  ML");
10946 
10947 	rc = 0;
10948 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
10949 		uint8_t dip_hit, vlan_vld, lookup_type, port_num;
10950 		uint16_t ivlan;
10951 		uint64_t tcamx, tcamy, val, mask;
10952 		uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
10953 		uint8_t addr[ETHER_ADDR_LEN];
10954 
10955 		ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
10956 		if (i < 256)
10957 			ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
10958 		else
10959 			ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
10960 		mtx_lock(&sc->reg_lock);
10961 		if (hw_off_limits(sc))
10962 			rc = ENXIO;
10963 		else {
10964 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
10965 			val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
10966 			tcamy = G_DMACH(val) << 32;
10967 			tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
10968 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
10969 		}
10970 		mtx_unlock(&sc->reg_lock);
10971 		if (rc != 0)
10972 			break;
10973 
10974 		lookup_type = G_DATALKPTYPE(data2);
10975 		port_num = G_DATAPORTNUM(data2);
10976 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
10977 			/* Inner header VNI */
10978 			vniy = ((data2 & F_DATAVIDH2) << 23) |
10979 				       (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
10980 			dip_hit = data2 & F_DATADIPHIT;
10981 			vlan_vld = 0;
10982 		} else {
10983 			vniy = 0;
10984 			dip_hit = 0;
10985 			vlan_vld = data2 & F_DATAVIDH2;
10986 			ivlan = G_VIDL(val);
10987 		}
10988 
10989 		ctl |= V_CTLXYBITSEL(1);
10990 		mtx_lock(&sc->reg_lock);
10991 		if (hw_off_limits(sc))
10992 			rc = ENXIO;
10993 		else {
10994 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
10995 			val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
10996 			tcamx = G_DMACH(val) << 32;
10997 			tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
10998 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
10999 		}
11000 		mtx_unlock(&sc->reg_lock);
11001 		if (rc != 0)
11002 			break;
11003 
11004 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11005 			/* Inner header VNI mask */
11006 			vnix = ((data2 & F_DATAVIDH2) << 23) |
11007 			       (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
11008 		} else
11009 			vnix = 0;
11010 
11011 		if (tcamx & tcamy)
11012 			continue;
11013 		tcamxy2valmask(tcamx, tcamy, addr, &mask);
11014 
11015 		mtx_lock(&sc->reg_lock);
11016 		if (hw_off_limits(sc))
11017 			rc = ENXIO;
11018 		else {
11019 			cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
11020 			cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
11021 		}
11022 		mtx_unlock(&sc->reg_lock);
11023 		if (rc != 0)
11024 			break;
11025 
11026 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11027 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11028 			    "%012jx %06x %06x    -    -   %3c"
11029 			    "        I  %4x   %3c   %#x%4u%4d", i, addr[0],
11030 			    addr[1], addr[2], addr[3], addr[4], addr[5],
11031 			    (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
11032 			    port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11033 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11034 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11035 		} else {
11036 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11037 			    "%012jx    -       -   ", i, addr[0], addr[1],
11038 			    addr[2], addr[3], addr[4], addr[5],
11039 			    (uintmax_t)mask);
11040 
11041 			if (vlan_vld)
11042 				sbuf_printf(sb, "%4u   Y     ", ivlan);
11043 			else
11044 				sbuf_printf(sb, "  -    N     ");
11045 
11046 			sbuf_printf(sb, "-      %3c  %4x   %3c   %#x%4u%4d",
11047 			    lookup_type ? 'I' : 'O', port_num,
11048 			    cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11049 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11050 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11051 		}
11052 
11053 
11054 		if (cls_lo & F_T6_REPLICATE) {
11055 			struct fw_ldst_cmd ldst_cmd;
11056 
11057 			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
11058 			ldst_cmd.op_to_addrspace =
11059 			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
11060 				F_FW_CMD_REQUEST | F_FW_CMD_READ |
11061 				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
11062 			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
11063 			ldst_cmd.u.mps.rplc.fid_idx =
11064 			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
11065 				V_FW_LDST_CMD_IDX(i));
11066 
11067 			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
11068 			    "t6mps");
11069 			if (rc)
11070 				break;
11071 			if (hw_off_limits(sc))
11072 				rc = ENXIO;
11073 			else
11074 				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
11075 				    sizeof(ldst_cmd), &ldst_cmd);
11076 			end_synchronized_op(sc, 0);
11077 			if (rc != 0)
11078 				break;
11079 			else {
11080 				sbuf_printf(sb, " %08x %08x %08x %08x"
11081 				    " %08x %08x %08x %08x",
11082 				    be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
11083 				    be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
11084 				    be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
11085 				    be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
11086 				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
11087 				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
11088 				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
11089 				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
11090 			}
11091 		} else
11092 			sbuf_printf(sb, "%72s", "");
11093 
11094 		sbuf_printf(sb, "%4u%3u%3u%3u %#x",
11095 		    G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
11096 		    G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
11097 		    (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
11098 	}
11099 
11100 	if (rc)
11101 		(void) sbuf_finish(sb);
11102 	else
11103 		rc = sbuf_finish(sb);
11104 	sbuf_delete(sb);
11105 
11106 	return (rc);
11107 }
11108 
11109 static int
11110 sysctl_mps_tcam_t7(SYSCTL_HANDLER_ARGS)
11111 {
11112 	struct adapter *sc = arg1;
11113 	struct sbuf *sb;
11114 	int rc, i;
11115 
11116 	MPASS(chip_id(sc) >= CHELSIO_T7);
11117 
11118 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11119 	if (sb == NULL)
11120 		return (ENOMEM);
11121 
11122 	sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
11123 	    "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
11124 	    "                           Replication"
11125 	    "                                    P0 P1 P2 P3  ML");
11126 
11127 	rc = 0;
11128 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
11129 		uint8_t dip_hit, vlan_vld, lookup_type, port_num;
11130 		uint16_t ivlan;
11131 		uint64_t tcamx, tcamy, val, mask;
11132 		uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
11133 		uint8_t addr[ETHER_ADDR_LEN];
11134 
11135 		/* Read tcamy */
11136 		ctl = (V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0));
11137 		if (chip_rev(sc) == 0) {
11138 			if (i < 256)
11139 				ctl |= V_CTLTCAMINDEX(i) | V_T7_CTLTCAMSEL(0);
11140 			else
11141 				ctl |= V_CTLTCAMINDEX(i - 256) | V_T7_CTLTCAMSEL(1);
11142 		} else {
11143 #if 0
11144 			ctl = (V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0));
11145 #endif
11146 			if (i < 512)
11147 				ctl |= V_CTLTCAMINDEX(i) | V_T7_CTLTCAMSEL(0);
11148 			else if (i < 1024)
11149 				ctl |= V_CTLTCAMINDEX(i - 512) | V_T7_CTLTCAMSEL(1);
11150 			else
11151 				ctl |= V_CTLTCAMINDEX(i - 1024) | V_T7_CTLTCAMSEL(2);
11152 		}
11153 
11154 		mtx_lock(&sc->reg_lock);
11155 		if (hw_off_limits(sc))
11156 			rc = ENXIO;
11157 		else {
11158 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
11159 			val = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA1_REQ_ID1);
11160 			tcamy = G_DMACH(val) << 32;
11161 			tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA0_REQ_ID1);
11162 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA2_REQ_ID1);
11163 		}
11164 		mtx_unlock(&sc->reg_lock);
11165 		if (rc != 0)
11166 			break;
11167 
11168 		lookup_type = G_DATALKPTYPE(data2);
11169 		port_num = G_DATAPORTNUM(data2);
11170 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11171 			/* Inner header VNI */
11172 			vniy = (((data2 & F_DATAVIDH2) |
11173 			    G_DATAVIDH1(data2)) << 16) | G_VIDL(val);
11174 			dip_hit = data2 & F_DATADIPHIT;
11175 			vlan_vld = 0;
11176 		} else {
11177 			vniy = 0;
11178 			dip_hit = 0;
11179 			vlan_vld = data2 & F_DATAVIDH2;
11180 			ivlan = G_VIDL(val);
11181 		}
11182 
11183 		ctl |= V_CTLXYBITSEL(1);
11184 		mtx_lock(&sc->reg_lock);
11185 		if (hw_off_limits(sc))
11186 			rc = ENXIO;
11187 		else {
11188 			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
11189 			val = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA1_REQ_ID1);
11190 			tcamx = G_DMACH(val) << 32;
11191 			tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA0_REQ_ID1);
11192 			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA2_REQ_ID1);
11193 		}
11194 		mtx_unlock(&sc->reg_lock);
11195 		if (rc != 0)
11196 			break;
11197 
11198 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11199 			/* Inner header VNI mask */
11200 			vnix = (((data2 & F_DATAVIDH2) |
11201 			    G_DATAVIDH1(data2)) << 16) | G_VIDL(val);
11202 		} else
11203 			vnix = 0;
11204 
11205 		if (tcamx & tcamy)
11206 			continue;
11207 		tcamxy2valmask(tcamx, tcamy, addr, &mask);
11208 
11209 		mtx_lock(&sc->reg_lock);
11210 		if (hw_off_limits(sc))
11211 			rc = ENXIO;
11212 		else {
11213 			if (chip_rev(sc) == 0) {
11214 				cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
11215 				cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
11216 			} else {
11217 				t4_write_reg(sc, A_MPS_CLS_SRAM_H,
11218 				    V_SRAMWRN(0) | V_SRAMINDEX(i));
11219 				cls_lo = t4_read_reg(sc, A_MPS_CLS_SRAM_L);
11220 				cls_hi = t4_read_reg(sc, A_MPS_CLS_SRAM_H);
11221 			}
11222 		}
11223 		mtx_unlock(&sc->reg_lock);
11224 		if (rc != 0)
11225 			break;
11226 
11227 		if (lookup_type && lookup_type != M_DATALKPTYPE) {
11228 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11229 			    "%012jx %06x %06x    -    -   %3c"
11230 			    "        I  %4x   %3c   %#x%4u%4d", i, addr[0],
11231 			    addr[1], addr[2], addr[3], addr[4], addr[5],
11232 			    (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
11233 			    port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11234 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11235 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11236 		} else {
11237 			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
11238 			    "%012jx    -       -   ", i, addr[0], addr[1],
11239 			    addr[2], addr[3], addr[4], addr[5],
11240 			    (uintmax_t)mask);
11241 
11242 			if (vlan_vld)
11243 				sbuf_printf(sb, "%4u   Y     ", ivlan);
11244 			else
11245 				sbuf_printf(sb, "  -    N     ");
11246 
11247 			sbuf_printf(sb, "-      %3c  %4x   %3c   %#x%4u%4d",
11248 			    lookup_type ? 'I' : 'O', port_num,
11249 			    cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11250 			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11251 			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11252 		}
11253 
11254 		if (cls_lo & F_T6_REPLICATE) {
11255 			struct fw_ldst_cmd ldst_cmd;
11256 
11257 			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
11258 			ldst_cmd.op_to_addrspace =
11259 			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
11260 				F_FW_CMD_REQUEST | F_FW_CMD_READ |
11261 				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
11262 			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
11263 			ldst_cmd.u.mps.rplc.fid_idx =
11264 			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
11265 				V_FW_LDST_CMD_IDX(i));
11266 
11267 			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
11268 			    "t6mps");
11269 			if (rc)
11270 				break;
11271 			if (hw_off_limits(sc))
11272 				rc = ENXIO;
11273 			else
11274 				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
11275 				    sizeof(ldst_cmd), &ldst_cmd);
11276 			end_synchronized_op(sc, 0);
11277 			if (rc != 0)
11278 				break;
11279 			else {
11280 				sbuf_printf(sb, " %08x %08x %08x %08x"
11281 				    " %08x %08x %08x %08x",
11282 				    be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
11283 				    be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
11284 				    be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
11285 				    be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
11286 				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
11287 				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
11288 				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
11289 				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
11290 			}
11291 		} else
11292 			sbuf_printf(sb, "%72s", "");
11293 
11294 		sbuf_printf(sb, "%4u%3u%3u%3u %#x",
11295 		    G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
11296 		    G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
11297 		    (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
11298 	}
11299 
11300 	if (rc)
11301 		(void) sbuf_finish(sb);
11302 	else
11303 		rc = sbuf_finish(sb);
11304 	sbuf_delete(sb);
11305 
11306 	return (rc);
11307 }
11308 
11309 static int
11310 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
11311 {
11312 	struct adapter *sc = arg1;
11313 	struct sbuf *sb;
11314 	int rc;
11315 	uint16_t mtus[NMTUS];
11316 
11317 	rc = 0;
11318 	mtx_lock(&sc->reg_lock);
11319 	if (hw_off_limits(sc))
11320 		rc = ENXIO;
11321 	else
11322 		t4_read_mtu_tbl(sc, mtus, NULL);
11323 	mtx_unlock(&sc->reg_lock);
11324 	if (rc != 0)
11325 		return (rc);
11326 
11327 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11328 	if (sb == NULL)
11329 		return (ENOMEM);
11330 
11331 	sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
11332 	    mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
11333 	    mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
11334 	    mtus[14], mtus[15]);
11335 
11336 	rc = sbuf_finish(sb);
11337 	sbuf_delete(sb);
11338 
11339 	return (rc);
11340 }
11341 
11342 static int
11343 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
11344 {
11345 	struct adapter *sc = arg1;
11346 	struct sbuf *sb;
11347 	int rc, i;
11348 	uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
11349 	uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
11350 	uint32_t stats[T7_PM_RX_CACHE_NSTATS];
11351 	static const char *tx_stats[MAX_PM_NSTATS] = {
11352 		"Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
11353 		"Tx FIFO wait", NULL, "Tx latency"
11354 	};
11355 	static const char *rx_stats[MAX_PM_NSTATS] = {
11356 		"Read:", "Write bypass:", "Write mem:", "Flush:",
11357 		"Rx FIFO wait", NULL, "Rx latency"
11358 	};
11359 
11360 	rc = 0;
11361 	mtx_lock(&sc->reg_lock);
11362 	if (hw_off_limits(sc))
11363 		rc = ENXIO;
11364 	else {
11365 		t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
11366 		t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
11367 		if (chip_id(sc) >= CHELSIO_T7)
11368 			t4_pmrx_cache_get_stats(sc, stats);
11369 	}
11370 	mtx_unlock(&sc->reg_lock);
11371 	if (rc != 0)
11372 		return (rc);
11373 
11374 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11375 	if (sb == NULL)
11376 		return (ENOMEM);
11377 
11378 	sbuf_printf(sb, "                Tx pcmds             Tx bytes");
11379 	for (i = 0; i < 4; i++) {
11380 		sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
11381 		    tx_cyc[i]);
11382 	}
11383 
11384 	sbuf_printf(sb, "\n                Rx pcmds             Rx bytes");
11385 	for (i = 0; i < 4; i++) {
11386 		sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
11387 		    rx_cyc[i]);
11388 	}
11389 
11390 	if (chip_id(sc) > CHELSIO_T5) {
11391 		sbuf_printf(sb,
11392 		    "\n              Total wait      Total occupancy");
11393 		sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
11394 		    tx_cyc[i]);
11395 		sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
11396 		    rx_cyc[i]);
11397 
11398 		i += 2;
11399 		MPASS(i < nitems(tx_stats));
11400 
11401 		sbuf_printf(sb,
11402 		    "\n                   Reads           Total wait");
11403 		sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
11404 		    tx_cyc[i]);
11405 		sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
11406 		    rx_cyc[i]);
11407 	}
11408 
11409 	if (chip_id(sc) >= CHELSIO_T7) {
11410 		i = 0;
11411 		sbuf_printf(sb, "\n\nPM RX Cache Stats\n");
11412 		sbuf_printf(sb, "%-40s    %u\n", "ReqWrite", stats[i++]);
11413 		sbuf_printf(sb, "%-40s    %u\n", "ReqReadInv", stats[i++]);
11414 		sbuf_printf(sb, "%-40s    %u\n", "ReqReadNoInv", stats[i++]);
11415 		sbuf_printf(sb, "%-40s    %u\n", "Write Split Request",
11416 			   stats[i++]);
11417 		sbuf_printf(sb, "%-40s    %u\n",
11418 			   "Normal Read Split (Read Invalidate)", stats[i++]);
11419 		sbuf_printf(sb, "%-40s    %u\n",
11420 			   "Feedback Read Split (Read NoInvalidate)",
11421 			   stats[i++]);
11422 		sbuf_printf(sb, "%-40s    %u\n", "Write Hit", stats[i++]);
11423 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit",
11424 			   stats[i++]);
11425 		sbuf_printf(sb, "%-40s    %u\n", "Feedback Read Hit",
11426 			   stats[i++]);
11427 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit Full Avail",
11428 			   stats[i++]);
11429 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit Full UnAvail",
11430 			   stats[i++]);
11431 		sbuf_printf(sb, "%-40s    %u\n",
11432 			   "Normal Read Hit Partial Avail",
11433 			   stats[i++]);
11434 		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Full Avail",
11435 			   stats[i++]);
11436 		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Full UnAvail",
11437 			   stats[i++]);
11438 		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Partial Avail",
11439 			   stats[i++]);
11440 		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Full Free",
11441 			   stats[i++]);
11442 		sbuf_printf(sb, "%-40s    %u\n",
11443 			   "Normal Read Part-avail Mul-Regions",
11444 			   stats[i++]);
11445 		sbuf_printf(sb, "%-40s    %u\n",
11446 			   "FB Read Part-avail Mul-Regions",
11447 			   stats[i++]);
11448 		sbuf_printf(sb, "%-40s    %u\n", "Write Miss FL Used",
11449 			   stats[i++]);
11450 		sbuf_printf(sb, "%-40s    %u\n", "Write Miss LRU Used",
11451 			   stats[i++]);
11452 		sbuf_printf(sb, "%-40s    %u\n",
11453 			   "Write Miss LRU-Multiple Evict", stats[i++]);
11454 		sbuf_printf(sb, "%-40s    %u\n",
11455 			   "Write Hit Increasing Islands", stats[i++]);
11456 		sbuf_printf(sb, "%-40s    %u\n",
11457 			   "Normal Read Island Read split", stats[i++]);
11458 		sbuf_printf(sb, "%-40s    %u\n", "Write Overflow Eviction",
11459 			   stats[i++]);
11460 		sbuf_printf(sb, "%-40s    %u", "Read Overflow Eviction",
11461 			   stats[i++]);
11462 	}
11463 
11464 	rc = sbuf_finish(sb);
11465 	sbuf_delete(sb);
11466 
11467 	return (rc);
11468 }
11469 
11470 static int
11471 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
11472 {
11473 	struct adapter *sc = arg1;
11474 	struct sbuf *sb;
11475 	int rc;
11476 	struct tp_rdma_stats stats;
11477 
11478 	rc = 0;
11479 	mtx_lock(&sc->reg_lock);
11480 	if (hw_off_limits(sc))
11481 		rc = ENXIO;
11482 	else
11483 		t4_tp_get_rdma_stats(sc, &stats, 0);
11484 	mtx_unlock(&sc->reg_lock);
11485 	if (rc != 0)
11486 		return (rc);
11487 
11488 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11489 	if (sb == NULL)
11490 		return (ENOMEM);
11491 
11492 	sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
11493 	sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
11494 
11495 	rc = sbuf_finish(sb);
11496 	sbuf_delete(sb);
11497 
11498 	return (rc);
11499 }
11500 
11501 static int
11502 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
11503 {
11504 	struct adapter *sc = arg1;
11505 	struct sbuf *sb;
11506 	int rc;
11507 	struct tp_tcp_stats v4, v6;
11508 
11509 	rc = 0;
11510 	mtx_lock(&sc->reg_lock);
11511 	if (hw_off_limits(sc))
11512 		rc = ENXIO;
11513 	else
11514 		t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
11515 	mtx_unlock(&sc->reg_lock);
11516 	if (rc != 0)
11517 		return (rc);
11518 
11519 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11520 	if (sb == NULL)
11521 		return (ENOMEM);
11522 
11523 	sbuf_printf(sb,
11524 	    "                                IP                 IPv6\n");
11525 	sbuf_printf(sb, "OutRsts:      %20u %20u\n",
11526 	    v4.tcp_out_rsts, v6.tcp_out_rsts);
11527 	sbuf_printf(sb, "InSegs:       %20ju %20ju\n",
11528 	    v4.tcp_in_segs, v6.tcp_in_segs);
11529 	sbuf_printf(sb, "OutSegs:      %20ju %20ju\n",
11530 	    v4.tcp_out_segs, v6.tcp_out_segs);
11531 	sbuf_printf(sb, "RetransSegs:  %20ju %20ju",
11532 	    v4.tcp_retrans_segs, v6.tcp_retrans_segs);
11533 
11534 	rc = sbuf_finish(sb);
11535 	sbuf_delete(sb);
11536 
11537 	return (rc);
11538 }
11539 
11540 static int
11541 sysctl_tids(SYSCTL_HANDLER_ARGS)
11542 {
11543 	struct adapter *sc = arg1;
11544 	struct sbuf *sb;
11545 	int rc;
11546 	uint32_t x, y;
11547 	struct tid_info *t = &sc->tids;
11548 
11549 	rc = 0;
11550 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11551 	if (sb == NULL)
11552 		return (ENOMEM);
11553 
11554 	if (t->natids) {
11555 		sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
11556 		    t->atids_in_use);
11557 	}
11558 
11559 	if (t->nhpftids) {
11560 		sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
11561 		    t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
11562 	}
11563 
11564 	if (t->ntids) {
11565 		bool hashen = false;
11566 
11567 		mtx_lock(&sc->reg_lock);
11568 		if (hw_off_limits(sc))
11569 			rc = ENXIO;
11570 		else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
11571 			hashen = true;
11572 			if (chip_id(sc) <= CHELSIO_T5) {
11573 				x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
11574 				y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
11575 			} else {
11576 				x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
11577 				y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
11578 			}
11579 		}
11580 		mtx_unlock(&sc->reg_lock);
11581 		if (rc != 0)
11582 			goto done;
11583 
11584 		sbuf_printf(sb, "TID range: ");
11585 		if (hashen) {
11586 			if (x)
11587 				sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1);
11588 			sbuf_printf(sb, "%u-%u", y, t->ntids - 1);
11589 		} else {
11590 			sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base +
11591 			    t->ntids - 1);
11592 		}
11593 		sbuf_printf(sb, ", in use: %u\n",
11594 		    atomic_load_acq_int(&t->tids_in_use));
11595 	}
11596 
11597 	if (t->nstids) {
11598 		sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
11599 		    t->stid_base + t->nstids - 1, t->stids_in_use);
11600 	}
11601 
11602 	if (t->nftids) {
11603 		sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
11604 		    t->ftid_end, t->ftids_in_use);
11605 	}
11606 
11607 	if (t->netids) {
11608 		sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
11609 		    t->etid_base + t->netids - 1, t->etids_in_use);
11610 	}
11611 
11612 	mtx_lock(&sc->reg_lock);
11613 	if (hw_off_limits(sc))
11614 		rc = ENXIO;
11615 	else {
11616 		x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4);
11617 		y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6);
11618 	}
11619 	mtx_unlock(&sc->reg_lock);
11620 	if (rc != 0)
11621 		goto done;
11622 	sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y);
11623 done:
11624 	if (rc == 0)
11625 		rc = sbuf_finish(sb);
11626 	else
11627 		(void)sbuf_finish(sb);
11628 	sbuf_delete(sb);
11629 
11630 	return (rc);
11631 }
11632 
11633 static int
11634 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
11635 {
11636 	struct adapter *sc = arg1;
11637 	struct sbuf *sb;
11638 	int rc;
11639 	struct tp_err_stats stats;
11640 
11641 	rc = 0;
11642 	mtx_lock(&sc->reg_lock);
11643 	if (hw_off_limits(sc))
11644 		rc = ENXIO;
11645 	else
11646 		t4_tp_get_err_stats(sc, &stats, 0);
11647 	mtx_unlock(&sc->reg_lock);
11648 	if (rc != 0)
11649 		return (rc);
11650 
11651 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11652 	if (sb == NULL)
11653 		return (ENOMEM);
11654 
11655 	if (sc->chip_params->nchan > 2) {
11656 		sbuf_printf(sb, "                 channel 0  channel 1"
11657 		    "  channel 2  channel 3\n");
11658 		sbuf_printf(sb, "macInErrs:      %10u %10u %10u %10u\n",
11659 		    stats.mac_in_errs[0], stats.mac_in_errs[1],
11660 		    stats.mac_in_errs[2], stats.mac_in_errs[3]);
11661 		sbuf_printf(sb, "hdrInErrs:      %10u %10u %10u %10u\n",
11662 		    stats.hdr_in_errs[0], stats.hdr_in_errs[1],
11663 		    stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
11664 		sbuf_printf(sb, "tcpInErrs:      %10u %10u %10u %10u\n",
11665 		    stats.tcp_in_errs[0], stats.tcp_in_errs[1],
11666 		    stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
11667 		sbuf_printf(sb, "tcp6InErrs:     %10u %10u %10u %10u\n",
11668 		    stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
11669 		    stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
11670 		sbuf_printf(sb, "tnlCongDrops:   %10u %10u %10u %10u\n",
11671 		    stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
11672 		    stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
11673 		sbuf_printf(sb, "tnlTxDrops:     %10u %10u %10u %10u\n",
11674 		    stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
11675 		    stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
11676 		sbuf_printf(sb, "ofldVlanDrops:  %10u %10u %10u %10u\n",
11677 		    stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
11678 		    stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
11679 		sbuf_printf(sb, "ofldChanDrops:  %10u %10u %10u %10u\n\n",
11680 		    stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
11681 		    stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
11682 	} else {
11683 		sbuf_printf(sb, "                 channel 0  channel 1\n");
11684 		sbuf_printf(sb, "macInErrs:      %10u %10u\n",
11685 		    stats.mac_in_errs[0], stats.mac_in_errs[1]);
11686 		sbuf_printf(sb, "hdrInErrs:      %10u %10u\n",
11687 		    stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
11688 		sbuf_printf(sb, "tcpInErrs:      %10u %10u\n",
11689 		    stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
11690 		sbuf_printf(sb, "tcp6InErrs:     %10u %10u\n",
11691 		    stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
11692 		sbuf_printf(sb, "tnlCongDrops:   %10u %10u\n",
11693 		    stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
11694 		sbuf_printf(sb, "tnlTxDrops:     %10u %10u\n",
11695 		    stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
11696 		sbuf_printf(sb, "ofldVlanDrops:  %10u %10u\n",
11697 		    stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
11698 		sbuf_printf(sb, "ofldChanDrops:  %10u %10u\n\n",
11699 		    stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
11700 	}
11701 
11702 	sbuf_printf(sb, "ofldNoNeigh:    %u\nofldCongDefer:  %u",
11703 	    stats.ofld_no_neigh, stats.ofld_cong_defer);
11704 
11705 	rc = sbuf_finish(sb);
11706 	sbuf_delete(sb);
11707 
11708 	return (rc);
11709 }
11710 
11711 static int
11712 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS)
11713 {
11714 	struct adapter *sc = arg1;
11715 	struct sbuf *sb;
11716 	int rc;
11717 	struct tp_tnl_stats stats;
11718 
11719 	rc = 0;
11720 	mtx_lock(&sc->reg_lock);
11721 	if (hw_off_limits(sc))
11722 		rc = ENXIO;
11723 	else
11724 		t4_tp_get_tnl_stats(sc, &stats, 1);
11725 	mtx_unlock(&sc->reg_lock);
11726 	if (rc != 0)
11727 		return (rc);
11728 
11729 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
11730 	if (sb == NULL)
11731 		return (ENOMEM);
11732 
11733 	if (sc->chip_params->nchan > 2) {
11734 		sbuf_printf(sb, "           channel 0  channel 1"
11735 		    "  channel 2  channel 3\n");
11736 		sbuf_printf(sb, "OutPkts:  %10u %10u %10u %10u\n",
11737 		    stats.out_pkt[0], stats.out_pkt[1],
11738 		    stats.out_pkt[2], stats.out_pkt[3]);
11739 		sbuf_printf(sb, "InPkts:   %10u %10u %10u %10u",
11740 		    stats.in_pkt[0], stats.in_pkt[1],
11741 		    stats.in_pkt[2], stats.in_pkt[3]);
11742 	} else {
11743 		sbuf_printf(sb, "           channel 0  channel 1\n");
11744 		sbuf_printf(sb, "OutPkts:  %10u %10u\n",
11745 		    stats.out_pkt[0], stats.out_pkt[1]);
11746 		sbuf_printf(sb, "InPkts:   %10u %10u",
11747 		    stats.in_pkt[0], stats.in_pkt[1]);
11748 	}
11749 
11750 	rc = sbuf_finish(sb);
11751 	sbuf_delete(sb);
11752 
11753 	return (rc);
11754 }
11755 
11756 static int
11757 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
11758 {
11759 	struct adapter *sc = arg1;
11760 	struct tp_params *tpp = &sc->params.tp;
11761 	u_int mask;
11762 	int rc;
11763 
11764 	mask = tpp->la_mask >> 16;
11765 	rc = sysctl_handle_int(oidp, &mask, 0, req);
11766 	if (rc != 0 || req->newptr == NULL)
11767 		return (rc);
11768 	if (mask > 0xffff)
11769 		return (EINVAL);
11770 	mtx_lock(&sc->reg_lock);
11771 	if (hw_off_limits(sc))
11772 		rc = ENXIO;
11773 	else {
11774 		tpp->la_mask = mask << 16;
11775 		t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U,
11776 		    tpp->la_mask);
11777 	}
11778 	mtx_unlock(&sc->reg_lock);
11779 
11780 	return (rc);
11781 }
11782 
11783 struct field_desc {
11784 	const char *name;
11785 	u_int start;
11786 	u_int width;
11787 };
11788 
11789 static void
11790 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
11791 {
11792 	char buf[32];
11793 	int line_size = 0;
11794 
11795 	while (f->name) {
11796 		uint64_t mask = (1ULL << f->width) - 1;
11797 		int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
11798 		    ((uintmax_t)v >> f->start) & mask);
11799 
11800 		if (line_size + len >= 79) {
11801 			line_size = 8;
11802 			sbuf_printf(sb, "\n        ");
11803 		}
11804 		sbuf_printf(sb, "%s ", buf);
11805 		line_size += len + 1;
11806 		f++;
11807 	}
11808 	sbuf_printf(sb, "\n");
11809 }
11810 
11811 static const struct field_desc tp_la0[] = {
11812 	{ "RcfOpCodeOut", 60, 4 },
11813 	{ "State", 56, 4 },
11814 	{ "WcfState", 52, 4 },
11815 	{ "RcfOpcSrcOut", 50, 2 },
11816 	{ "CRxError", 49, 1 },
11817 	{ "ERxError", 48, 1 },
11818 	{ "SanityFailed", 47, 1 },
11819 	{ "SpuriousMsg", 46, 1 },
11820 	{ "FlushInputMsg", 45, 1 },
11821 	{ "FlushInputCpl", 44, 1 },
11822 	{ "RssUpBit", 43, 1 },
11823 	{ "RssFilterHit", 42, 1 },
11824 	{ "Tid", 32, 10 },
11825 	{ "InitTcb", 31, 1 },
11826 	{ "LineNumber", 24, 7 },
11827 	{ "Emsg", 23, 1 },
11828 	{ "EdataOut", 22, 1 },
11829 	{ "Cmsg", 21, 1 },
11830 	{ "CdataOut", 20, 1 },
11831 	{ "EreadPdu", 19, 1 },
11832 	{ "CreadPdu", 18, 1 },
11833 	{ "TunnelPkt", 17, 1 },
11834 	{ "RcfPeerFin", 16, 1 },
11835 	{ "RcfReasonOut", 12, 4 },
11836 	{ "TxCchannel", 10, 2 },
11837 	{ "RcfTxChannel", 8, 2 },
11838 	{ "RxEchannel", 6, 2 },
11839 	{ "RcfRxChannel", 5, 1 },
11840 	{ "RcfDataOutSrdy", 4, 1 },
11841 	{ "RxDvld", 3, 1 },
11842 	{ "RxOoDvld", 2, 1 },
11843 	{ "RxCongestion", 1, 1 },
11844 	{ "TxCongestion", 0, 1 },
11845 	{ NULL }
11846 };
11847 
11848 static const struct field_desc tp_la1[] = {
11849 	{ "CplCmdIn", 56, 8 },
11850 	{ "CplCmdOut", 48, 8 },
11851 	{ "ESynOut", 47, 1 },
11852 	{ "EAckOut", 46, 1 },
11853 	{ "EFinOut", 45, 1 },
11854 	{ "ERstOut", 44, 1 },
11855 	{ "SynIn", 43, 1 },
11856 	{ "AckIn", 42, 1 },
11857 	{ "FinIn", 41, 1 },
11858 	{ "RstIn", 40, 1 },
11859 	{ "DataIn", 39, 1 },
11860 	{ "DataInVld", 38, 1 },
11861 	{ "PadIn", 37, 1 },
11862 	{ "RxBufEmpty", 36, 1 },
11863 	{ "RxDdp", 35, 1 },
11864 	{ "RxFbCongestion", 34, 1 },
11865 	{ "TxFbCongestion", 33, 1 },
11866 	{ "TxPktSumSrdy", 32, 1 },
11867 	{ "RcfUlpType", 28, 4 },
11868 	{ "Eread", 27, 1 },
11869 	{ "Ebypass", 26, 1 },
11870 	{ "Esave", 25, 1 },
11871 	{ "Static0", 24, 1 },
11872 	{ "Cread", 23, 1 },
11873 	{ "Cbypass", 22, 1 },
11874 	{ "Csave", 21, 1 },
11875 	{ "CPktOut", 20, 1 },
11876 	{ "RxPagePoolFull", 18, 2 },
11877 	{ "RxLpbkPkt", 17, 1 },
11878 	{ "TxLpbkPkt", 16, 1 },
11879 	{ "RxVfValid", 15, 1 },
11880 	{ "SynLearned", 14, 1 },
11881 	{ "SetDelEntry", 13, 1 },
11882 	{ "SetInvEntry", 12, 1 },
11883 	{ "CpcmdDvld", 11, 1 },
11884 	{ "CpcmdSave", 10, 1 },
11885 	{ "RxPstructsFull", 8, 2 },
11886 	{ "EpcmdDvld", 7, 1 },
11887 	{ "EpcmdFlush", 6, 1 },
11888 	{ "EpcmdTrimPrefix", 5, 1 },
11889 	{ "EpcmdTrimPostfix", 4, 1 },
11890 	{ "ERssIp4Pkt", 3, 1 },
11891 	{ "ERssIp6Pkt", 2, 1 },
11892 	{ "ERssTcpUdpPkt", 1, 1 },
11893 	{ "ERssFceFipPkt", 0, 1 },
11894 	{ NULL }
11895 };
11896 
11897 static const struct field_desc tp_la2[] = {
11898 	{ "CplCmdIn", 56, 8 },
11899 	{ "MpsVfVld", 55, 1 },
11900 	{ "MpsPf", 52, 3 },
11901 	{ "MpsVf", 44, 8 },
11902 	{ "SynIn", 43, 1 },
11903 	{ "AckIn", 42, 1 },
11904 	{ "FinIn", 41, 1 },
11905 	{ "RstIn", 40, 1 },
11906 	{ "DataIn", 39, 1 },
11907 	{ "DataInVld", 38, 1 },
11908 	{ "PadIn", 37, 1 },
11909 	{ "RxBufEmpty", 36, 1 },
11910 	{ "RxDdp", 35, 1 },
11911 	{ "RxFbCongestion", 34, 1 },
11912 	{ "TxFbCongestion", 33, 1 },
11913 	{ "TxPktSumSrdy", 32, 1 },
11914 	{ "RcfUlpType", 28, 4 },
11915 	{ "Eread", 27, 1 },
11916 	{ "Ebypass", 26, 1 },
11917 	{ "Esave", 25, 1 },
11918 	{ "Static0", 24, 1 },
11919 	{ "Cread", 23, 1 },
11920 	{ "Cbypass", 22, 1 },
11921 	{ "Csave", 21, 1 },
11922 	{ "CPktOut", 20, 1 },
11923 	{ "RxPagePoolFull", 18, 2 },
11924 	{ "RxLpbkPkt", 17, 1 },
11925 	{ "TxLpbkPkt", 16, 1 },
11926 	{ "RxVfValid", 15, 1 },
11927 	{ "SynLearned", 14, 1 },
11928 	{ "SetDelEntry", 13, 1 },
11929 	{ "SetInvEntry", 12, 1 },
11930 	{ "CpcmdDvld", 11, 1 },
11931 	{ "CpcmdSave", 10, 1 },
11932 	{ "RxPstructsFull", 8, 2 },
11933 	{ "EpcmdDvld", 7, 1 },
11934 	{ "EpcmdFlush", 6, 1 },
11935 	{ "EpcmdTrimPrefix", 5, 1 },
11936 	{ "EpcmdTrimPostfix", 4, 1 },
11937 	{ "ERssIp4Pkt", 3, 1 },
11938 	{ "ERssIp6Pkt", 2, 1 },
11939 	{ "ERssTcpUdpPkt", 1, 1 },
11940 	{ "ERssFceFipPkt", 0, 1 },
11941 	{ NULL }
11942 };
11943 
11944 static void
11945 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
11946 {
11947 
11948 	field_desc_show(sb, *p, tp_la0);
11949 }
11950 
11951 static void
11952 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
11953 {
11954 
11955 	if (idx)
11956 		sbuf_printf(sb, "\n");
11957 	field_desc_show(sb, p[0], tp_la0);
11958 	if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
11959 		field_desc_show(sb, p[1], tp_la0);
11960 }
11961 
11962 static void
11963 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
11964 {
11965 
11966 	if (idx)
11967 		sbuf_printf(sb, "\n");
11968 	field_desc_show(sb, p[0], tp_la0);
11969 	if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
11970 		field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
11971 }
11972 
11973 static int
11974 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
11975 {
11976 	struct adapter *sc = arg1;
11977 	struct sbuf *sb;
11978 	uint64_t *buf, *p;
11979 	int rc;
11980 	u_int i, inc;
11981 	void (*show_func)(struct sbuf *, uint64_t *, int);
11982 
11983 	rc = 0;
11984 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11985 	if (sb == NULL)
11986 		return (ENOMEM);
11987 
11988 	buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
11989 
11990 	mtx_lock(&sc->reg_lock);
11991 	if (hw_off_limits(sc))
11992 		rc = ENXIO;
11993 	else {
11994 		t4_tp_read_la(sc, buf, NULL);
11995 		switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
11996 		case 2:
11997 			inc = 2;
11998 			show_func = tp_la_show2;
11999 			break;
12000 		case 3:
12001 			inc = 2;
12002 			show_func = tp_la_show3;
12003 			break;
12004 		default:
12005 			inc = 1;
12006 			show_func = tp_la_show;
12007 		}
12008 	}
12009 	mtx_unlock(&sc->reg_lock);
12010 	if (rc != 0)
12011 		goto done;
12012 
12013 	p = buf;
12014 	for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
12015 		(*show_func)(sb, p, i);
12016 	rc = sbuf_finish(sb);
12017 done:
12018 	sbuf_delete(sb);
12019 	free(buf, M_CXGBE);
12020 	return (rc);
12021 }
12022 
12023 static int
12024 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
12025 {
12026 	struct adapter *sc = arg1;
12027 	struct sbuf *sb;
12028 	int rc;
12029 	u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
12030 
12031 	rc = 0;
12032 	mtx_lock(&sc->reg_lock);
12033 	if (hw_off_limits(sc))
12034 		rc = ENXIO;
12035 	else
12036 		t4_get_chan_txrate(sc, nrate, orate);
12037 	mtx_unlock(&sc->reg_lock);
12038 	if (rc != 0)
12039 		return (rc);
12040 
12041 	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
12042 	if (sb == NULL)
12043 		return (ENOMEM);
12044 
12045 	if (sc->chip_params->nchan > 2) {
12046 		sbuf_printf(sb, "              channel 0   channel 1"
12047 		    "   channel 2   channel 3\n");
12048 		sbuf_printf(sb, "NIC B/s:     %10ju  %10ju  %10ju  %10ju\n",
12049 		    nrate[0], nrate[1], nrate[2], nrate[3]);
12050 		sbuf_printf(sb, "Offload B/s: %10ju  %10ju  %10ju  %10ju",
12051 		    orate[0], orate[1], orate[2], orate[3]);
12052 	} else {
12053 		sbuf_printf(sb, "              channel 0   channel 1\n");
12054 		sbuf_printf(sb, "NIC B/s:     %10ju  %10ju\n",
12055 		    nrate[0], nrate[1]);
12056 		sbuf_printf(sb, "Offload B/s: %10ju  %10ju",
12057 		    orate[0], orate[1]);
12058 	}
12059 
12060 	rc = sbuf_finish(sb);
12061 	sbuf_delete(sb);
12062 
12063 	return (rc);
12064 }
12065 
12066 static int
12067 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
12068 {
12069 	struct adapter *sc = arg1;
12070 	struct sbuf *sb;
12071 	uint32_t *buf, *p;
12072 	int rc, i;
12073 
12074 	rc = 0;
12075 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12076 	if (sb == NULL)
12077 		return (ENOMEM);
12078 
12079 	buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
12080 	    M_ZERO | M_WAITOK);
12081 
12082 	mtx_lock(&sc->reg_lock);
12083 	if (hw_off_limits(sc))
12084 		rc = ENXIO;
12085 	else
12086 		t4_ulprx_read_la(sc, buf);
12087 	mtx_unlock(&sc->reg_lock);
12088 	if (rc != 0)
12089 		goto done;
12090 
12091 	p = buf;
12092 	sbuf_printf(sb, "      Pcmd        Type   Message"
12093 	    "                Data");
12094 	for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
12095 		sbuf_printf(sb, "\n%08x%08x  %4x  %08x  %08x%08x%08x%08x",
12096 		    p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
12097 	}
12098 	rc = sbuf_finish(sb);
12099 done:
12100 	sbuf_delete(sb);
12101 	free(buf, M_CXGBE);
12102 	return (rc);
12103 }
12104 
12105 static int
12106 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
12107 {
12108 	struct adapter *sc = arg1;
12109 	struct sbuf *sb;
12110 	int rc;
12111 	uint32_t cfg, s1, s2;
12112 
12113 	MPASS(chip_id(sc) >= CHELSIO_T5);
12114 
12115 	rc = 0;
12116 	mtx_lock(&sc->reg_lock);
12117 	if (hw_off_limits(sc))
12118 		rc = ENXIO;
12119 	else {
12120 		cfg = t4_read_reg(sc, A_SGE_STAT_CFG);
12121 		s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL);
12122 		s2 = t4_read_reg(sc, A_SGE_STAT_MATCH);
12123 	}
12124 	mtx_unlock(&sc->reg_lock);
12125 	if (rc != 0)
12126 		return (rc);
12127 
12128 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12129 	if (sb == NULL)
12130 		return (ENOMEM);
12131 
12132 	if (G_STATSOURCE_T5(cfg) == 7) {
12133 		int mode;
12134 
12135 		mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg);
12136 		if (mode == 0)
12137 			sbuf_printf(sb, "total %d, incomplete %d", s1, s2);
12138 		else if (mode == 1)
12139 			sbuf_printf(sb, "total %d, data overflow %d", s1, s2);
12140 		else
12141 			sbuf_printf(sb, "unknown mode %d", mode);
12142 	}
12143 	rc = sbuf_finish(sb);
12144 	sbuf_delete(sb);
12145 
12146 	return (rc);
12147 }
12148 
12149 static int
12150 sysctl_cpus(SYSCTL_HANDLER_ARGS)
12151 {
12152 	struct adapter *sc = arg1;
12153 	enum cpu_sets op = arg2;
12154 	cpuset_t cpuset;
12155 	struct sbuf *sb;
12156 	int i, rc;
12157 
12158 	MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
12159 
12160 	CPU_ZERO(&cpuset);
12161 	rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
12162 	if (rc != 0)
12163 		return (rc);
12164 
12165 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
12166 	if (sb == NULL)
12167 		return (ENOMEM);
12168 
12169 	CPU_FOREACH(i)
12170 		sbuf_printf(sb, "%d ", i);
12171 	rc = sbuf_finish(sb);
12172 	sbuf_delete(sb);
12173 
12174 	return (rc);
12175 }
12176 
12177 static int
12178 sysctl_reset(SYSCTL_HANDLER_ARGS)
12179 {
12180 	struct adapter *sc = arg1;
12181 	u_int val;
12182 	int rc;
12183 
12184 	val = atomic_load_int(&sc->num_resets);
12185 	rc = sysctl_handle_int(oidp, &val, 0, req);
12186 	if (rc != 0 || req->newptr == NULL)
12187 		return (rc);
12188 
12189 	if (val == 0) {
12190 		/* Zero out the counter that tracks reset. */
12191 		atomic_store_int(&sc->num_resets, 0);
12192 		return (0);
12193 	}
12194 
12195 	if (val != 1)
12196 		return (EINVAL);	/* 0 or 1 are the only legal values */
12197 
12198 	if (hw_off_limits(sc))		/* harmless race */
12199 		return (EALREADY);
12200 
12201 	taskqueue_enqueue(reset_tq, &sc->reset_task);
12202 	return (0);
12203 }
12204 
12205 #ifdef TCP_OFFLOAD
12206 static int
12207 sysctl_tls(SYSCTL_HANDLER_ARGS)
12208 {
12209 	struct adapter *sc = arg1;
12210 	int i, j, v, rc;
12211 	struct vi_info *vi;
12212 
12213 	v = sc->tt.tls;
12214 	rc = sysctl_handle_int(oidp, &v, 0, req);
12215 	if (rc != 0 || req->newptr == NULL)
12216 		return (rc);
12217 
12218 	if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS))
12219 		return (ENOTSUP);
12220 
12221 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls");
12222 	if (rc)
12223 		return (rc);
12224 	if (hw_off_limits(sc))
12225 		rc = ENXIO;
12226 	else {
12227 		sc->tt.tls = !!v;
12228 		for_each_port(sc, i) {
12229 			for_each_vi(sc->port[i], j, vi) {
12230 				if (vi->flags & VI_INIT_DONE)
12231 					t4_update_fl_bufsize(vi->ifp);
12232 			}
12233 		}
12234 	}
12235 	end_synchronized_op(sc, 0);
12236 
12237 	return (rc);
12238 
12239 }
12240 
12241 static void
12242 unit_conv(char *buf, size_t len, u_int val, u_int factor)
12243 {
12244 	u_int rem = val % factor;
12245 
12246 	if (rem == 0)
12247 		snprintf(buf, len, "%u", val / factor);
12248 	else {
12249 		while (rem % 10 == 0)
12250 			rem /= 10;
12251 		snprintf(buf, len, "%u.%u", val / factor, rem);
12252 	}
12253 }
12254 
12255 static int
12256 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
12257 {
12258 	struct adapter *sc = arg1;
12259 	char buf[16];
12260 	u_int res, re;
12261 	u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
12262 
12263 	mtx_lock(&sc->reg_lock);
12264 	if (hw_off_limits(sc))
12265 		res = (u_int)-1;
12266 	else
12267 		res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
12268 	mtx_unlock(&sc->reg_lock);
12269 	if (res == (u_int)-1)
12270 		return (ENXIO);
12271 
12272 	switch (arg2) {
12273 	case 0:
12274 		/* timer_tick */
12275 		re = G_TIMERRESOLUTION(res);
12276 		break;
12277 	case 1:
12278 		/* TCP timestamp tick */
12279 		re = G_TIMESTAMPRESOLUTION(res);
12280 		break;
12281 	case 2:
12282 		/* DACK tick */
12283 		re = G_DELAYEDACKRESOLUTION(res);
12284 		break;
12285 	default:
12286 		return (EDOOFUS);
12287 	}
12288 
12289 	unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
12290 
12291 	return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
12292 }
12293 
12294 static int
12295 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
12296 {
12297 	struct adapter *sc = arg1;
12298 	int rc;
12299 	u_int dack_tmr, dack_re, v;
12300 	u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
12301 
12302 	mtx_lock(&sc->reg_lock);
12303 	if (hw_off_limits(sc))
12304 		rc = ENXIO;
12305 	else {
12306 		rc = 0;
12307 		dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc,
12308 		    A_TP_TIMER_RESOLUTION));
12309 		dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER);
12310 	}
12311 	mtx_unlock(&sc->reg_lock);
12312 	if (rc != 0)
12313 		return (rc);
12314 
12315 	v = ((cclk_ps << dack_re) / 1000000) * dack_tmr;
12316 
12317 	return (sysctl_handle_int(oidp, &v, 0, req));
12318 }
12319 
12320 static int
12321 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
12322 {
12323 	struct adapter *sc = arg1;
12324 	int rc, reg = arg2;
12325 	u_int tre;
12326 	u_long tp_tick_us, v;
12327 	u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
12328 
12329 	MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
12330 	    reg == A_TP_PERS_MIN  || reg == A_TP_PERS_MAX ||
12331 	    reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
12332 	    reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
12333 
12334 	mtx_lock(&sc->reg_lock);
12335 	if (hw_off_limits(sc))
12336 		rc = ENXIO;
12337 	else {
12338 		rc = 0;
12339 		tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
12340 		tp_tick_us = (cclk_ps << tre) / 1000000;
12341 		if (reg == A_TP_INIT_SRTT)
12342 			v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
12343 		else
12344 			v = tp_tick_us * t4_read_reg(sc, reg);
12345 	}
12346 	mtx_unlock(&sc->reg_lock);
12347 	if (rc != 0)
12348 		return (rc);
12349 	else
12350 		return (sysctl_handle_long(oidp, &v, 0, req));
12351 }
12352 
12353 /*
12354  * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
12355  * passed to this function.
12356  */
12357 static int
12358 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
12359 {
12360 	struct adapter *sc = arg1;
12361 	int rc, idx = arg2;
12362 	u_int v;
12363 
12364 	MPASS(idx >= 0 && idx <= 24);
12365 
12366 	mtx_lock(&sc->reg_lock);
12367 	if (hw_off_limits(sc))
12368 		rc = ENXIO;
12369 	else {
12370 		rc = 0;
12371 		v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
12372 	}
12373 	mtx_unlock(&sc->reg_lock);
12374 	if (rc != 0)
12375 		return (rc);
12376 	else
12377 		return (sysctl_handle_int(oidp, &v, 0, req));
12378 }
12379 
12380 static int
12381 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
12382 {
12383 	struct adapter *sc = arg1;
12384 	int rc, idx = arg2;
12385 	u_int shift, v, r;
12386 
12387 	MPASS(idx >= 0 && idx < 16);
12388 
12389 	r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
12390 	shift = (idx & 3) << 3;
12391 	mtx_lock(&sc->reg_lock);
12392 	if (hw_off_limits(sc))
12393 		rc = ENXIO;
12394 	else {
12395 		rc = 0;
12396 		v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
12397 	}
12398 	mtx_unlock(&sc->reg_lock);
12399 	if (rc != 0)
12400 		return (rc);
12401 	else
12402 		return (sysctl_handle_int(oidp, &v, 0, req));
12403 }
12404 
12405 static int
12406 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
12407 {
12408 	struct vi_info *vi = arg1;
12409 	struct adapter *sc = vi->adapter;
12410 	int idx, rc, i;
12411 	struct sge_ofld_rxq *ofld_rxq;
12412 	uint8_t v;
12413 
12414 	idx = vi->ofld_tmr_idx;
12415 
12416 	rc = sysctl_handle_int(oidp, &idx, 0, req);
12417 	if (rc != 0 || req->newptr == NULL)
12418 		return (rc);
12419 
12420 	if (idx < 0 || idx >= SGE_NTIMERS)
12421 		return (EINVAL);
12422 
12423 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
12424 	    "t4otmr");
12425 	if (rc)
12426 		return (rc);
12427 
12428 	v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
12429 	for_each_ofld_rxq(vi, i, ofld_rxq) {
12430 #ifdef atomic_store_rel_8
12431 		atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
12432 #else
12433 		ofld_rxq->iq.intr_params = v;
12434 #endif
12435 	}
12436 	vi->ofld_tmr_idx = idx;
12437 
12438 	end_synchronized_op(sc, LOCK_HELD);
12439 	return (0);
12440 }
12441 
12442 static int
12443 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
12444 {
12445 	struct vi_info *vi = arg1;
12446 	struct adapter *sc = vi->adapter;
12447 	int idx, rc;
12448 
12449 	idx = vi->ofld_pktc_idx;
12450 
12451 	rc = sysctl_handle_int(oidp, &idx, 0, req);
12452 	if (rc != 0 || req->newptr == NULL)
12453 		return (rc);
12454 
12455 	if (idx < -1 || idx >= SGE_NCOUNTERS)
12456 		return (EINVAL);
12457 
12458 	rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
12459 	    "t4opktc");
12460 	if (rc)
12461 		return (rc);
12462 
12463 	if (vi->flags & VI_INIT_DONE)
12464 		rc = EBUSY; /* cannot be changed once the queues are created */
12465 	else
12466 		vi->ofld_pktc_idx = idx;
12467 
12468 	end_synchronized_op(sc, LOCK_HELD);
12469 	return (rc);
12470 }
12471 #endif
12472 
12473 static int
12474 get_sge_context(struct adapter *sc, int mem_id, uint32_t cid, int len,
12475     uint32_t *data)
12476 {
12477 	int rc;
12478 
12479 	if (len < sc->chip_params->sge_ctxt_size)
12480 		return (ENOBUFS);
12481 	if (cid > M_CTXTQID)
12482 		return (EINVAL);
12483 	if (mem_id != CTXT_EGRESS && mem_id != CTXT_INGRESS &&
12484 	    mem_id != CTXT_FLM && mem_id != CTXT_CNM)
12485 		return (EINVAL);
12486 
12487 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
12488 	if (rc)
12489 		return (rc);
12490 
12491 	if (hw_off_limits(sc)) {
12492 		rc = ENXIO;
12493 		goto done;
12494 	}
12495 
12496 	if (sc->flags & FW_OK) {
12497 		rc = -t4_sge_ctxt_rd(sc, sc->mbox, cid, mem_id, data);
12498 		if (rc == 0)
12499 			goto done;
12500 	}
12501 
12502 	/*
12503 	 * Read via firmware failed or wasn't even attempted.  Read directly via
12504 	 * the backdoor.
12505 	 */
12506 	rc = -t4_sge_ctxt_rd_bd(sc, cid, mem_id, data);
12507 done:
12508 	end_synchronized_op(sc, 0);
12509 	return (rc);
12510 }
12511 
12512 static int
12513 load_fw(struct adapter *sc, struct t4_data *fw)
12514 {
12515 	int rc;
12516 	uint8_t *fw_data;
12517 
12518 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
12519 	if (rc)
12520 		return (rc);
12521 
12522 	if (hw_off_limits(sc)) {
12523 		rc = ENXIO;
12524 		goto done;
12525 	}
12526 
12527 	/*
12528 	 * The firmware, with the sole exception of the memory parity error
12529 	 * handler, runs from memory and not flash.  It is almost always safe to
12530 	 * install a new firmware on a running system.  Just set bit 1 in
12531 	 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
12532 	 */
12533 	if (sc->flags & FULL_INIT_DONE &&
12534 	    (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
12535 		rc = EBUSY;
12536 		goto done;
12537 	}
12538 
12539 	fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
12540 
12541 	rc = copyin(fw->data, fw_data, fw->len);
12542 	if (rc == 0)
12543 		rc = -t4_load_fw(sc, fw_data, fw->len);
12544 
12545 	free(fw_data, M_CXGBE);
12546 done:
12547 	end_synchronized_op(sc, 0);
12548 	return (rc);
12549 }
12550 
12551 static int
12552 load_cfg(struct adapter *sc, struct t4_data *cfg)
12553 {
12554 	int rc;
12555 	uint8_t *cfg_data = NULL;
12556 
12557 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
12558 	if (rc)
12559 		return (rc);
12560 
12561 	if (hw_off_limits(sc)) {
12562 		rc = ENXIO;
12563 		goto done;
12564 	}
12565 
12566 	if (cfg->len == 0) {
12567 		/* clear */
12568 		rc = -t4_load_cfg(sc, NULL, 0);
12569 		goto done;
12570 	}
12571 
12572 	cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
12573 
12574 	rc = copyin(cfg->data, cfg_data, cfg->len);
12575 	if (rc == 0)
12576 		rc = -t4_load_cfg(sc, cfg_data, cfg->len);
12577 
12578 	free(cfg_data, M_CXGBE);
12579 done:
12580 	end_synchronized_op(sc, 0);
12581 	return (rc);
12582 }
12583 
12584 static int
12585 load_boot(struct adapter *sc, struct t4_bootrom *br)
12586 {
12587 	int rc;
12588 	uint8_t *br_data = NULL;
12589 	u_int offset;
12590 
12591 	if (br->len > 1024 * 1024)
12592 		return (EFBIG);
12593 
12594 	if (br->pf_offset == 0) {
12595 		/* pfidx */
12596 		if (br->pfidx_addr > 7)
12597 			return (EINVAL);
12598 		offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
12599 		    A_PCIE_PF_EXPROM_OFST)));
12600 	} else if (br->pf_offset == 1) {
12601 		/* offset */
12602 		offset = G_OFFSET(br->pfidx_addr);
12603 	} else {
12604 		return (EINVAL);
12605 	}
12606 
12607 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
12608 	if (rc)
12609 		return (rc);
12610 
12611 	if (hw_off_limits(sc)) {
12612 		rc = ENXIO;
12613 		goto done;
12614 	}
12615 
12616 	if (br->len == 0) {
12617 		/* clear */
12618 		rc = -t4_load_boot(sc, NULL, offset, 0);
12619 		goto done;
12620 	}
12621 
12622 	br_data = malloc(br->len, M_CXGBE, M_WAITOK);
12623 
12624 	rc = copyin(br->data, br_data, br->len);
12625 	if (rc == 0)
12626 		rc = -t4_load_boot(sc, br_data, offset, br->len);
12627 
12628 	free(br_data, M_CXGBE);
12629 done:
12630 	end_synchronized_op(sc, 0);
12631 	return (rc);
12632 }
12633 
12634 static int
12635 load_bootcfg(struct adapter *sc, struct t4_data *bc)
12636 {
12637 	int rc;
12638 	uint8_t *bc_data = NULL;
12639 
12640 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
12641 	if (rc)
12642 		return (rc);
12643 
12644 	if (hw_off_limits(sc)) {
12645 		rc = ENXIO;
12646 		goto done;
12647 	}
12648 
12649 	if (bc->len == 0) {
12650 		/* clear */
12651 		rc = -t4_load_bootcfg(sc, NULL, 0);
12652 		goto done;
12653 	}
12654 
12655 	bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
12656 
12657 	rc = copyin(bc->data, bc_data, bc->len);
12658 	if (rc == 0)
12659 		rc = -t4_load_bootcfg(sc, bc_data, bc->len);
12660 
12661 	free(bc_data, M_CXGBE);
12662 done:
12663 	end_synchronized_op(sc, 0);
12664 	return (rc);
12665 }
12666 
12667 static int
12668 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
12669 {
12670 	int rc;
12671 	struct cudbg_init *cudbg;
12672 	void *handle, *buf;
12673 
12674 	/* buf is large, don't block if no memory is available */
12675 	buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
12676 	if (buf == NULL)
12677 		return (ENOMEM);
12678 
12679 	handle = cudbg_alloc_handle();
12680 	if (handle == NULL) {
12681 		rc = ENOMEM;
12682 		goto done;
12683 	}
12684 
12685 	cudbg = cudbg_get_init(handle);
12686 	cudbg->adap = sc;
12687 	cudbg->print = (cudbg_print_cb)printf;
12688 
12689 #ifndef notyet
12690 	device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
12691 	    __func__, dump->wr_flash, dump->len, dump->data);
12692 #endif
12693 
12694 	if (dump->wr_flash)
12695 		cudbg->use_flash = 1;
12696 	MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
12697 	memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
12698 
12699 	rc = cudbg_collect(handle, buf, &dump->len);
12700 	if (rc != 0)
12701 		goto done;
12702 
12703 	rc = copyout(buf, dump->data, dump->len);
12704 done:
12705 	cudbg_free_handle(handle);
12706 	free(buf, M_CXGBE);
12707 	return (rc);
12708 }
12709 
12710 static void
12711 free_offload_policy(struct t4_offload_policy *op)
12712 {
12713 	struct offload_rule *r;
12714 	int i;
12715 
12716 	if (op == NULL)
12717 		return;
12718 
12719 	r = &op->rule[0];
12720 	for (i = 0; i < op->nrules; i++, r++) {
12721 		free(r->bpf_prog.bf_insns, M_CXGBE);
12722 	}
12723 	free(op->rule, M_CXGBE);
12724 	free(op, M_CXGBE);
12725 }
12726 
12727 static int
12728 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
12729 {
12730 	int i, rc, len;
12731 	struct t4_offload_policy *op, *old;
12732 	struct bpf_program *bf;
12733 	const struct offload_settings *s;
12734 	struct offload_rule *r;
12735 	void *u;
12736 
12737 	if (!is_offload(sc))
12738 		return (ENODEV);
12739 
12740 	if (uop->nrules == 0) {
12741 		/* Delete installed policies. */
12742 		op = NULL;
12743 		goto set_policy;
12744 	} else if (uop->nrules > 256) { /* arbitrary */
12745 		return (E2BIG);
12746 	}
12747 
12748 	/* Copy userspace offload policy to kernel */
12749 	op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
12750 	op->nrules = uop->nrules;
12751 	len = op->nrules * sizeof(struct offload_rule);
12752 	op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
12753 	rc = copyin(uop->rule, op->rule, len);
12754 	if (rc) {
12755 		free(op->rule, M_CXGBE);
12756 		free(op, M_CXGBE);
12757 		return (rc);
12758 	}
12759 
12760 	r = &op->rule[0];
12761 	for (i = 0; i < op->nrules; i++, r++) {
12762 
12763 		/* Validate open_type */
12764 		if (r->open_type != OPEN_TYPE_LISTEN &&
12765 		    r->open_type != OPEN_TYPE_ACTIVE &&
12766 		    r->open_type != OPEN_TYPE_PASSIVE &&
12767 		    r->open_type != OPEN_TYPE_DONTCARE) {
12768 error:
12769 			/*
12770 			 * Rules 0 to i have malloc'd filters that need to be
12771 			 * freed.  Rules i+1 to nrules have userspace pointers
12772 			 * and should be left alone.
12773 			 */
12774 			op->nrules = i;
12775 			free_offload_policy(op);
12776 			return (rc);
12777 		}
12778 
12779 		/* Validate settings */
12780 		s = &r->settings;
12781 		if ((s->offload != 0 && s->offload != 1) ||
12782 		    s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
12783 		    s->sched_class < -1 ||
12784 		    s->sched_class >= sc->params.nsched_cls) {
12785 			rc = EINVAL;
12786 			goto error;
12787 		}
12788 
12789 		bf = &r->bpf_prog;
12790 		u = bf->bf_insns;	/* userspace ptr */
12791 		bf->bf_insns = NULL;
12792 		if (bf->bf_len == 0) {
12793 			/* legal, matches everything */
12794 			continue;
12795 		}
12796 		len = bf->bf_len * sizeof(*bf->bf_insns);
12797 		bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
12798 		rc = copyin(u, bf->bf_insns, len);
12799 		if (rc != 0)
12800 			goto error;
12801 
12802 		if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
12803 			rc = EINVAL;
12804 			goto error;
12805 		}
12806 	}
12807 set_policy:
12808 	rw_wlock(&sc->policy_lock);
12809 	old = sc->policy;
12810 	sc->policy = op;
12811 	rw_wunlock(&sc->policy_lock);
12812 	free_offload_policy(old);
12813 
12814 	return (0);
12815 }
12816 
12817 #define MAX_READ_BUF_SIZE (128 * 1024)
12818 static int
12819 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
12820 {
12821 	uint32_t addr, remaining, n;
12822 	uint32_t *buf;
12823 	int rc;
12824 	uint8_t *dst;
12825 
12826 	mtx_lock(&sc->reg_lock);
12827 	if (hw_off_limits(sc))
12828 		rc = ENXIO;
12829 	else
12830 		rc = validate_mem_range(sc, mr->addr, mr->len);
12831 	mtx_unlock(&sc->reg_lock);
12832 	if (rc != 0)
12833 		return (rc);
12834 
12835 	buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
12836 	addr = mr->addr;
12837 	remaining = mr->len;
12838 	dst = (void *)mr->data;
12839 
12840 	while (remaining) {
12841 		n = min(remaining, MAX_READ_BUF_SIZE);
12842 		mtx_lock(&sc->reg_lock);
12843 		if (hw_off_limits(sc))
12844 			rc = ENXIO;
12845 		else
12846 			read_via_memwin(sc, 2, addr, buf, n);
12847 		mtx_unlock(&sc->reg_lock);
12848 		if (rc != 0)
12849 			break;
12850 
12851 		rc = copyout(buf, dst, n);
12852 		if (rc != 0)
12853 			break;
12854 
12855 		dst += n;
12856 		remaining -= n;
12857 		addr += n;
12858 	}
12859 
12860 	free(buf, M_CXGBE);
12861 	return (rc);
12862 }
12863 #undef MAX_READ_BUF_SIZE
12864 
12865 static int
12866 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
12867 {
12868 	int rc;
12869 
12870 	if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
12871 		return (EINVAL);
12872 
12873 	if (i2cd->len > sizeof(i2cd->data))
12874 		return (EFBIG);
12875 
12876 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
12877 	if (rc)
12878 		return (rc);
12879 	if (hw_off_limits(sc))
12880 		rc = ENXIO;
12881 	else
12882 		rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
12883 		    i2cd->offset, i2cd->len, &i2cd->data[0]);
12884 	end_synchronized_op(sc, 0);
12885 
12886 	return (rc);
12887 }
12888 
12889 static int
12890 clear_stats(struct adapter *sc, u_int port_id)
12891 {
12892 	int i, v, chan_map;
12893 	struct port_info *pi;
12894 	struct vi_info *vi;
12895 	struct sge_rxq *rxq;
12896 	struct sge_txq *txq;
12897 	struct sge_wrq *wrq;
12898 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
12899 	struct sge_ofld_txq *ofld_txq;
12900 #endif
12901 #ifdef TCP_OFFLOAD
12902 	struct sge_ofld_rxq *ofld_rxq;
12903 #endif
12904 
12905 	if (port_id >= sc->params.nports)
12906 		return (EINVAL);
12907 	pi = sc->port[port_id];
12908 	if (pi == NULL)
12909 		return (EIO);
12910 
12911 	mtx_lock(&sc->reg_lock);
12912 	if (!hw_off_limits(sc)) {
12913 		/* MAC stats */
12914 		t4_clr_port_stats(sc, pi->hw_port);
12915 		if (is_t6(sc)) {
12916 			if (pi->fcs_reg != -1)
12917 				pi->fcs_base = t4_read_reg64(sc,
12918 				    t4_port_reg(sc, pi->tx_chan, pi->fcs_reg));
12919 			else
12920 				pi->stats.rx_fcs_err = 0;
12921 		}
12922 		for_each_vi(pi, v, vi) {
12923 			if (vi->flags & VI_INIT_DONE)
12924 				t4_clr_vi_stats(sc, vi->vin);
12925 		}
12926 		chan_map = pi->rx_e_chan_map;
12927 		v = 0;	/* reuse */
12928 		while (chan_map) {
12929 			i = ffs(chan_map) - 1;
12930 			t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
12931 			    1, A_TP_MIB_TNL_CNG_DROP_0 + i);
12932 			chan_map &= ~(1 << i);
12933 		}
12934 	}
12935 	mtx_unlock(&sc->reg_lock);
12936 	pi->tx_parse_error = 0;
12937 	pi->tnl_cong_drops = 0;
12938 
12939 	/*
12940 	 * Since this command accepts a port, clear stats for
12941 	 * all VIs on this port.
12942 	 */
12943 	for_each_vi(pi, v, vi) {
12944 		if (vi->flags & VI_INIT_DONE) {
12945 
12946 			for_each_rxq(vi, i, rxq) {
12947 #if defined(INET) || defined(INET6)
12948 				rxq->lro.lro_queued = 0;
12949 				rxq->lro.lro_flushed = 0;
12950 #endif
12951 				rxq->rxcsum = 0;
12952 				rxq->vlan_extraction = 0;
12953 				rxq->vxlan_rxcsum = 0;
12954 
12955 				rxq->fl.cl_allocated = 0;
12956 				rxq->fl.cl_recycled = 0;
12957 				rxq->fl.cl_fast_recycled = 0;
12958 			}
12959 
12960 			for_each_txq(vi, i, txq) {
12961 				txq->txcsum = 0;
12962 				txq->tso_wrs = 0;
12963 				txq->vlan_insertion = 0;
12964 				txq->imm_wrs = 0;
12965 				txq->sgl_wrs = 0;
12966 				txq->txpkt_wrs = 0;
12967 				txq->txpkts0_wrs = 0;
12968 				txq->txpkts1_wrs = 0;
12969 				txq->txpkts0_pkts = 0;
12970 				txq->txpkts1_pkts = 0;
12971 				txq->txpkts_flush = 0;
12972 				txq->raw_wrs = 0;
12973 				txq->vxlan_tso_wrs = 0;
12974 				txq->vxlan_txcsum = 0;
12975 				txq->kern_tls_records = 0;
12976 				txq->kern_tls_short = 0;
12977 				txq->kern_tls_partial = 0;
12978 				txq->kern_tls_full = 0;
12979 				txq->kern_tls_octets = 0;
12980 				txq->kern_tls_waste = 0;
12981 				txq->kern_tls_header = 0;
12982 				txq->kern_tls_fin_short = 0;
12983 				txq->kern_tls_cbc = 0;
12984 				txq->kern_tls_gcm = 0;
12985 				if (is_t6(sc)) {
12986 					txq->kern_tls_options = 0;
12987 					txq->kern_tls_fin = 0;
12988 				} else {
12989 					txq->kern_tls_ghash_received = 0;
12990 					txq->kern_tls_ghash_requested = 0;
12991 					txq->kern_tls_lso = 0;
12992 					txq->kern_tls_partial_ghash = 0;
12993 					txq->kern_tls_splitmode = 0;
12994 					txq->kern_tls_trailer = 0;
12995 				}
12996 				mp_ring_reset_stats(txq->r);
12997 			}
12998 
12999 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
13000 			for_each_ofld_txq(vi, i, ofld_txq) {
13001 				ofld_txq->wrq.tx_wrs_direct = 0;
13002 				ofld_txq->wrq.tx_wrs_copied = 0;
13003 				counter_u64_zero(ofld_txq->tx_iscsi_pdus);
13004 				counter_u64_zero(ofld_txq->tx_iscsi_octets);
13005 				counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs);
13006 				counter_u64_zero(ofld_txq->tx_nvme_pdus);
13007 				counter_u64_zero(ofld_txq->tx_nvme_octets);
13008 				counter_u64_zero(ofld_txq->tx_nvme_iso_wrs);
13009 				counter_u64_zero(ofld_txq->tx_aio_jobs);
13010 				counter_u64_zero(ofld_txq->tx_aio_octets);
13011 				counter_u64_zero(ofld_txq->tx_toe_tls_records);
13012 				counter_u64_zero(ofld_txq->tx_toe_tls_octets);
13013 			}
13014 #endif
13015 #ifdef TCP_OFFLOAD
13016 			for_each_ofld_rxq(vi, i, ofld_rxq) {
13017 				ofld_rxq->fl.cl_allocated = 0;
13018 				ofld_rxq->fl.cl_recycled = 0;
13019 				ofld_rxq->fl.cl_fast_recycled = 0;
13020 				counter_u64_zero(
13021 				    ofld_rxq->rx_iscsi_ddp_setup_ok);
13022 				counter_u64_zero(
13023 				    ofld_rxq->rx_iscsi_ddp_setup_error);
13024 				ofld_rxq->rx_iscsi_ddp_pdus = 0;
13025 				ofld_rxq->rx_iscsi_ddp_octets = 0;
13026 				ofld_rxq->rx_iscsi_fl_pdus = 0;
13027 				ofld_rxq->rx_iscsi_fl_octets = 0;
13028 				counter_u64_zero(
13029 				    ofld_rxq->rx_nvme_ddp_setup_ok);
13030 				counter_u64_zero(
13031 				    ofld_rxq->rx_nvme_ddp_setup_no_stag);
13032 				counter_u64_zero(
13033 				    ofld_rxq->rx_nvme_ddp_setup_error);
13034 				counter_u64_zero(ofld_rxq->rx_nvme_ddp_pdus);
13035 				counter_u64_zero(ofld_rxq->rx_nvme_ddp_octets);
13036 				counter_u64_zero(ofld_rxq->rx_nvme_fl_pdus);
13037 				counter_u64_zero(ofld_rxq->rx_nvme_fl_octets);
13038 				counter_u64_zero(
13039 				    ofld_rxq->rx_nvme_invalid_headers);
13040 				counter_u64_zero(
13041 				    ofld_rxq->rx_nvme_header_digest_errors);
13042 				counter_u64_zero(
13043 				    ofld_rxq->rx_nvme_data_digest_errors);
13044 				ofld_rxq->rx_aio_ddp_jobs = 0;
13045 				ofld_rxq->rx_aio_ddp_octets = 0;
13046 				ofld_rxq->rx_toe_tls_records = 0;
13047 				ofld_rxq->rx_toe_tls_octets = 0;
13048 				ofld_rxq->rx_toe_ddp_octets = 0;
13049 				counter_u64_zero(ofld_rxq->ddp_buffer_alloc);
13050 				counter_u64_zero(ofld_rxq->ddp_buffer_reuse);
13051 				counter_u64_zero(ofld_rxq->ddp_buffer_free);
13052 			}
13053 #endif
13054 
13055 			if (IS_MAIN_VI(vi)) {
13056 				wrq = &sc->sge.ctrlq[pi->port_id];
13057 				wrq->tx_wrs_direct = 0;
13058 				wrq->tx_wrs_copied = 0;
13059 			}
13060 		}
13061 	}
13062 
13063 	return (0);
13064 }
13065 
13066 static int
13067 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
13068 {
13069 #ifdef INET6
13070 	struct in6_addr in6;
13071 
13072 	bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
13073 	if (t4_get_clip_entry(sc, &in6, true) != NULL)
13074 		return (0);
13075 	else
13076 		return (EIO);
13077 #else
13078 	return (ENOTSUP);
13079 #endif
13080 }
13081 
13082 static int
13083 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
13084 {
13085 #ifdef INET6
13086 	struct in6_addr in6;
13087 
13088 	bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
13089 	return (t4_release_clip_addr(sc, &in6));
13090 #else
13091 	return (ENOTSUP);
13092 #endif
13093 }
13094 
13095 int
13096 t4_os_find_pci_capability(struct adapter *sc, int cap)
13097 {
13098 	int i;
13099 
13100 	return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
13101 }
13102 
13103 void
13104 t4_os_portmod_changed(struct port_info *pi)
13105 {
13106 	struct adapter *sc = pi->adapter;
13107 	struct vi_info *vi;
13108 	if_t ifp;
13109 	static const char *mod_str[] = {
13110 		NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM",
13111 		"LR_SIMPLEX", "DR"
13112 	};
13113 
13114 	KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
13115 	    ("%s: port_type %u", __func__, pi->port_type));
13116 
13117 	vi = &pi->vi[0];
13118 	if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
13119 		PORT_LOCK(pi);
13120 		build_medialist(pi);
13121 		if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
13122 			fixup_link_config(pi);
13123 			apply_link_config(pi);
13124 		}
13125 		PORT_UNLOCK(pi);
13126 		end_synchronized_op(sc, LOCK_HELD);
13127 	}
13128 
13129 	ifp = vi->ifp;
13130 	if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
13131 		if_printf(ifp, "transceiver unplugged.\n");
13132 	else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
13133 		if_printf(ifp, "unknown transceiver inserted.\n");
13134 	else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
13135 		if_printf(ifp, "unsupported transceiver inserted.\n");
13136 	else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
13137 		if_printf(ifp, "%dGbps %s transceiver inserted.\n",
13138 		    port_top_speed(pi), mod_str[pi->mod_type]);
13139 	} else {
13140 		if_printf(ifp, "transceiver (type %d) inserted.\n",
13141 		    pi->mod_type);
13142 	}
13143 }
13144 
13145 void
13146 t4_os_link_changed(struct port_info *pi)
13147 {
13148 	struct vi_info *vi;
13149 	if_t ifp;
13150 	struct link_config *lc = &pi->link_cfg;
13151 	struct adapter *sc = pi->adapter;
13152 	int v;
13153 
13154 	PORT_LOCK_ASSERT_OWNED(pi);
13155 
13156 	if (is_t6(sc)) {
13157 		if (lc->link_ok) {
13158 			if (lc->speed > 25000 ||
13159 			    (lc->speed == 25000 && lc->fec == FEC_RS))
13160 				pi->fcs_reg = A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS;
13161 			else
13162 				pi->fcs_reg = A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS;
13163 			pi->fcs_base = t4_read_reg64(sc,
13164 			    t4_port_reg(sc, pi->tx_chan, pi->fcs_reg));
13165 			pi->stats.rx_fcs_err = 0;
13166 		} else {
13167 			pi->fcs_reg = -1;
13168 		}
13169 	} else {
13170 		MPASS(pi->fcs_reg != -1);
13171 		MPASS(pi->fcs_base == 0);
13172 	}
13173 
13174 	for_each_vi(pi, v, vi) {
13175 		ifp = vi->ifp;
13176 		if (ifp == NULL || IS_DETACHING(vi))
13177 			continue;
13178 
13179 		if (lc->link_ok) {
13180 			if_setbaudrate(ifp, IF_Mbps(lc->speed));
13181 			if_link_state_change(ifp, LINK_STATE_UP);
13182 		} else {
13183 			if_link_state_change(ifp, LINK_STATE_DOWN);
13184 		}
13185 	}
13186 }
13187 
13188 void
13189 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
13190 {
13191 	struct adapter *sc;
13192 
13193 	sx_slock(&t4_list_lock);
13194 	SLIST_FOREACH(sc, &t4_list, link) {
13195 		/*
13196 		 * func should not make any assumptions about what state sc is
13197 		 * in - the only guarantee is that sc->sc_lock is a valid lock.
13198 		 */
13199 		func(sc, arg);
13200 	}
13201 	sx_sunlock(&t4_list_lock);
13202 }
13203 
13204 static int
13205 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
13206     struct thread *td)
13207 {
13208 	int rc;
13209 	struct adapter *sc = dev->si_drv1;
13210 
13211 	rc = priv_check(td, PRIV_DRIVER);
13212 	if (rc != 0)
13213 		return (rc);
13214 
13215 	switch (cmd) {
13216 	case CHELSIO_T4_GETREG: {
13217 		struct t4_reg *edata = (struct t4_reg *)data;
13218 
13219 		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
13220 			return (EFAULT);
13221 
13222 		mtx_lock(&sc->reg_lock);
13223 		if (hw_off_limits(sc))
13224 			rc = ENXIO;
13225 		else if (edata->size == 4)
13226 			edata->val = t4_read_reg(sc, edata->addr);
13227 		else if (edata->size == 8)
13228 			edata->val = t4_read_reg64(sc, edata->addr);
13229 		else
13230 			rc = EINVAL;
13231 		mtx_unlock(&sc->reg_lock);
13232 
13233 		break;
13234 	}
13235 	case CHELSIO_T4_SETREG: {
13236 		struct t4_reg *edata = (struct t4_reg *)data;
13237 
13238 		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
13239 			return (EFAULT);
13240 
13241 		mtx_lock(&sc->reg_lock);
13242 		if (hw_off_limits(sc))
13243 			rc = ENXIO;
13244 		else if (edata->size == 4) {
13245 			if (edata->val & 0xffffffff00000000)
13246 				rc = EINVAL;
13247 			t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
13248 		} else if (edata->size == 8)
13249 			t4_write_reg64(sc, edata->addr, edata->val);
13250 		else
13251 			rc = EINVAL;
13252 		mtx_unlock(&sc->reg_lock);
13253 
13254 		break;
13255 	}
13256 	case CHELSIO_T4_REGDUMP: {
13257 		struct t4_regdump *regs = (struct t4_regdump *)data;
13258 		int reglen = t4_get_regs_len(sc);
13259 		uint8_t *buf;
13260 
13261 		if (regs->len < reglen) {
13262 			regs->len = reglen; /* hint to the caller */
13263 			return (ENOBUFS);
13264 		}
13265 
13266 		regs->len = reglen;
13267 		buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
13268 		mtx_lock(&sc->reg_lock);
13269 		if (hw_off_limits(sc))
13270 			rc = ENXIO;
13271 		else
13272 			get_regs(sc, regs, buf);
13273 		mtx_unlock(&sc->reg_lock);
13274 		if (rc == 0)
13275 			rc = copyout(buf, regs->data, reglen);
13276 		free(buf, M_CXGBE);
13277 		break;
13278 	}
13279 	case CHELSIO_T4_GET_FILTER_MODE:
13280 		rc = get_filter_mode(sc, (uint32_t *)data);
13281 		break;
13282 	case CHELSIO_T4_SET_FILTER_MODE:
13283 		rc = set_filter_mode(sc, *(uint32_t *)data);
13284 		break;
13285 	case CHELSIO_T4_SET_FILTER_MASK:
13286 		rc = set_filter_mask(sc, *(uint32_t *)data);
13287 		break;
13288 	case CHELSIO_T4_GET_FILTER:
13289 		rc = get_filter(sc, (struct t4_filter *)data);
13290 		break;
13291 	case CHELSIO_T4_SET_FILTER:
13292 		rc = set_filter(sc, (struct t4_filter *)data);
13293 		break;
13294 	case CHELSIO_T4_DEL_FILTER:
13295 		rc = del_filter(sc, (struct t4_filter *)data);
13296 		break;
13297 	case CHELSIO_T4_GET_SGE_CONTEXT: {
13298 		struct t4_sge_context *ctxt = (struct t4_sge_context *)data;
13299 
13300 		rc = get_sge_context(sc, ctxt->mem_id, ctxt->cid,
13301 		    sizeof(ctxt->data), &ctxt->data[0]);
13302 		break;
13303 	}
13304 	case CHELSIO_T4_LOAD_FW:
13305 		rc = load_fw(sc, (struct t4_data *)data);
13306 		break;
13307 	case CHELSIO_T4_GET_MEM:
13308 		rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
13309 		break;
13310 	case CHELSIO_T4_GET_I2C:
13311 		rc = read_i2c(sc, (struct t4_i2c_data *)data);
13312 		break;
13313 	case CHELSIO_T4_CLEAR_STATS:
13314 		rc = clear_stats(sc, *(uint32_t *)data);
13315 		break;
13316 	case CHELSIO_T4_SCHED_CLASS:
13317 		rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
13318 		break;
13319 	case CHELSIO_T4_SCHED_QUEUE:
13320 		rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
13321 		break;
13322 	case CHELSIO_T4_GET_TRACER:
13323 		rc = t4_get_tracer(sc, (struct t4_tracer *)data);
13324 		break;
13325 	case CHELSIO_T4_SET_TRACER:
13326 		rc = t4_set_tracer(sc, (struct t4_tracer *)data);
13327 		break;
13328 	case CHELSIO_T4_LOAD_CFG:
13329 		rc = load_cfg(sc, (struct t4_data *)data);
13330 		break;
13331 	case CHELSIO_T4_LOAD_BOOT:
13332 		rc = load_boot(sc, (struct t4_bootrom *)data);
13333 		break;
13334 	case CHELSIO_T4_LOAD_BOOTCFG:
13335 		rc = load_bootcfg(sc, (struct t4_data *)data);
13336 		break;
13337 	case CHELSIO_T4_CUDBG_DUMP:
13338 		rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
13339 		break;
13340 	case CHELSIO_T4_SET_OFLD_POLICY:
13341 		rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
13342 		break;
13343 	case CHELSIO_T4_HOLD_CLIP_ADDR:
13344 		rc = hold_clip_addr(sc, (struct t4_clip_addr *)data);
13345 		break;
13346 	case CHELSIO_T4_RELEASE_CLIP_ADDR:
13347 		rc = release_clip_addr(sc, (struct t4_clip_addr *)data);
13348 		break;
13349 	case CHELSIO_T4_GET_SGE_CTXT: {
13350 		struct t4_sge_ctxt *ctxt = (struct t4_sge_ctxt *)data;
13351 
13352 		rc = get_sge_context(sc, ctxt->mem_id, ctxt->cid,
13353 		    sizeof(ctxt->data), &ctxt->data[0]);
13354 		break;
13355 	}
13356 	default:
13357 		rc = ENOTTY;
13358 	}
13359 
13360 	return (rc);
13361 }
13362 
13363 #ifdef TCP_OFFLOAD
13364 int
13365 toe_capability(struct vi_info *vi, bool enable)
13366 {
13367 	int rc;
13368 	struct port_info *pi = vi->pi;
13369 	struct adapter *sc = pi->adapter;
13370 
13371 	ASSERT_SYNCHRONIZED_OP(sc);
13372 
13373 	if (!is_offload(sc))
13374 		return (ENODEV);
13375 	if (!hw_all_ok(sc))
13376 		return (ENXIO);
13377 
13378 	if (enable) {
13379 #ifdef KERN_TLS
13380 		if (sc->flags & KERN_TLS_ON && is_t6(sc)) {
13381 			int i, j, n;
13382 			struct port_info *p;
13383 			struct vi_info *v;
13384 
13385 			/*
13386 			 * Reconfigure hardware for TOE if TXTLS is not enabled
13387 			 * on any ifnet.
13388 			 */
13389 			n = 0;
13390 			for_each_port(sc, i) {
13391 				p = sc->port[i];
13392 				for_each_vi(p, j, v) {
13393 					if (if_getcapenable(v->ifp) & IFCAP_TXTLS) {
13394 						CH_WARN(sc,
13395 						    "%s has NIC TLS enabled.\n",
13396 						    device_get_nameunit(v->dev));
13397 						n++;
13398 					}
13399 				}
13400 			}
13401 			if (n > 0) {
13402 				CH_WARN(sc, "Disable NIC TLS on all interfaces "
13403 				    "associated with this adapter before "
13404 				    "trying to enable TOE.\n");
13405 				return (EAGAIN);
13406 			}
13407 			rc = t6_config_kern_tls(sc, false);
13408 			if (rc)
13409 				return (rc);
13410 		}
13411 #endif
13412 		if ((if_getcapenable(vi->ifp) & IFCAP_TOE) != 0) {
13413 			/* TOE is already enabled. */
13414 			return (0);
13415 		}
13416 
13417 		/*
13418 		 * We need the port's queues around so that we're able to send
13419 		 * and receive CPLs to/from the TOE even if the ifnet for this
13420 		 * port has never been UP'd administratively.
13421 		 */
13422 		if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
13423 			return (rc);
13424 		if (!(pi->vi[0].flags & VI_INIT_DONE) &&
13425 		    ((rc = vi_init(&pi->vi[0])) != 0))
13426 			return (rc);
13427 
13428 		if (isset(&sc->offload_map, pi->port_id)) {
13429 			/* TOE is enabled on another VI of this port. */
13430 			MPASS(pi->uld_vis > 0);
13431 			pi->uld_vis++;
13432 			return (0);
13433 		}
13434 
13435 		if (!uld_active(sc, ULD_TOM)) {
13436 			rc = t4_activate_uld(sc, ULD_TOM);
13437 			if (rc == EAGAIN) {
13438 				log(LOG_WARNING,
13439 				    "You must kldload t4_tom.ko before trying "
13440 				    "to enable TOE on a cxgbe interface.\n");
13441 			}
13442 			if (rc != 0)
13443 				return (rc);
13444 			KASSERT(sc->tom_softc != NULL,
13445 			    ("%s: TOM activated but softc NULL", __func__));
13446 			KASSERT(uld_active(sc, ULD_TOM),
13447 			    ("%s: TOM activated but flag not set", __func__));
13448 		}
13449 
13450 		/*
13451 		 * Activate iWARP, iSCSI, and NVMe too, if the modules
13452 		 * are loaded.
13453 		 */
13454 		if (!uld_active(sc, ULD_IWARP))
13455 			(void) t4_activate_uld(sc, ULD_IWARP);
13456 		if (!uld_active(sc, ULD_ISCSI))
13457 			(void) t4_activate_uld(sc, ULD_ISCSI);
13458 		if (!uld_active(sc, ULD_NVME))
13459 			(void) t4_activate_uld(sc, ULD_NVME);
13460 
13461 		if (pi->uld_vis++ == 0)
13462 			setbit(&sc->offload_map, pi->port_id);
13463 	} else {
13464 		if ((if_getcapenable(vi->ifp) & IFCAP_TOE) == 0) {
13465 			/* TOE is already disabled. */
13466 			return (0);
13467 		}
13468 		MPASS(isset(&sc->offload_map, pi->port_id));
13469 		MPASS(pi->uld_vis > 0);
13470 		if (--pi->uld_vis == 0)
13471 			clrbit(&sc->offload_map, pi->port_id);
13472 	}
13473 
13474 	return (0);
13475 }
13476 
13477 /*
13478  * Add an upper layer driver to the global list.
13479  */
13480 int
13481 t4_register_uld(struct uld_info *ui, int id)
13482 {
13483 	int rc;
13484 
13485 	if (id < 0 || id > ULD_MAX)
13486 		return (EINVAL);
13487 	sx_xlock(&t4_uld_list_lock);
13488 	if (t4_uld_list[id] != NULL)
13489 		rc = EEXIST;
13490 	else {
13491 		t4_uld_list[id] = ui;
13492 		rc = 0;
13493 	}
13494 	sx_xunlock(&t4_uld_list_lock);
13495 	return (rc);
13496 }
13497 
13498 int
13499 t4_unregister_uld(struct uld_info *ui, int id)
13500 {
13501 
13502 	if (id < 0 || id > ULD_MAX)
13503 		return (EINVAL);
13504 	sx_xlock(&t4_uld_list_lock);
13505 	MPASS(t4_uld_list[id] == ui);
13506 	t4_uld_list[id] = NULL;
13507 	sx_xunlock(&t4_uld_list_lock);
13508 	return (0);
13509 }
13510 
13511 int
13512 t4_activate_uld(struct adapter *sc, int id)
13513 {
13514 	int rc;
13515 
13516 	ASSERT_SYNCHRONIZED_OP(sc);
13517 
13518 	if (id < 0 || id > ULD_MAX)
13519 		return (EINVAL);
13520 
13521 	/* Adapter needs to be initialized before any ULD can be activated. */
13522 	if (!(sc->flags & FULL_INIT_DONE)) {
13523 		rc = adapter_init(sc);
13524 		if (rc != 0)
13525 			return (rc);
13526 	}
13527 
13528 	sx_slock(&t4_uld_list_lock);
13529 	if (t4_uld_list[id] == NULL)
13530 		rc = EAGAIN;	/* load the KLD with this ULD and try again. */
13531 	else {
13532 		rc = t4_uld_list[id]->uld_activate(sc);
13533 		if (rc == 0)
13534 			setbit(&sc->active_ulds, id);
13535 	}
13536 	sx_sunlock(&t4_uld_list_lock);
13537 
13538 	return (rc);
13539 }
13540 
13541 int
13542 t4_deactivate_uld(struct adapter *sc, int id)
13543 {
13544 	int rc;
13545 
13546 	ASSERT_SYNCHRONIZED_OP(sc);
13547 
13548 	if (id < 0 || id > ULD_MAX)
13549 		return (EINVAL);
13550 
13551 	sx_slock(&t4_uld_list_lock);
13552 	if (t4_uld_list[id] == NULL)
13553 		rc = ENXIO;
13554 	else {
13555 		rc = t4_uld_list[id]->uld_deactivate(sc);
13556 		if (rc == 0)
13557 			clrbit(&sc->active_ulds, id);
13558 	}
13559 	sx_sunlock(&t4_uld_list_lock);
13560 
13561 	return (rc);
13562 }
13563 
13564 static int
13565 deactivate_all_uld(struct adapter *sc)
13566 {
13567 	int i, rc;
13568 
13569 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld");
13570 	if (rc != 0)
13571 		return (ENXIO);
13572 	sx_slock(&t4_uld_list_lock);
13573 	for (i = 0; i <= ULD_MAX; i++) {
13574 		if (t4_uld_list[i] == NULL || !uld_active(sc, i))
13575 			continue;
13576 		rc = t4_uld_list[i]->uld_deactivate(sc);
13577 		if (rc != 0)
13578 			break;
13579 		clrbit(&sc->active_ulds, i);
13580 	}
13581 	sx_sunlock(&t4_uld_list_lock);
13582 	end_synchronized_op(sc, 0);
13583 
13584 	return (rc);
13585 }
13586 
13587 static void
13588 stop_all_uld(struct adapter *sc)
13589 {
13590 	int i;
13591 
13592 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldst") != 0)
13593 		return;
13594 	sx_slock(&t4_uld_list_lock);
13595 	for (i = 0; i <= ULD_MAX; i++) {
13596 		if (t4_uld_list[i] == NULL || !uld_active(sc, i) ||
13597 		    t4_uld_list[i]->uld_stop == NULL)
13598 			continue;
13599 		(void) t4_uld_list[i]->uld_stop(sc);
13600 	}
13601 	sx_sunlock(&t4_uld_list_lock);
13602 	end_synchronized_op(sc, 0);
13603 }
13604 
13605 static void
13606 restart_all_uld(struct adapter *sc)
13607 {
13608 	int i;
13609 
13610 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4uldre") != 0)
13611 		return;
13612 	sx_slock(&t4_uld_list_lock);
13613 	for (i = 0; i <= ULD_MAX; i++) {
13614 		if (t4_uld_list[i] == NULL || !uld_active(sc, i) ||
13615 		    t4_uld_list[i]->uld_restart == NULL)
13616 			continue;
13617 		(void) t4_uld_list[i]->uld_restart(sc);
13618 	}
13619 	sx_sunlock(&t4_uld_list_lock);
13620 	end_synchronized_op(sc, 0);
13621 }
13622 
13623 int
13624 uld_active(struct adapter *sc, int id)
13625 {
13626 
13627 	MPASS(id >= 0 && id <= ULD_MAX);
13628 
13629 	return (isset(&sc->active_ulds, id));
13630 }
13631 #endif
13632 
13633 #ifdef KERN_TLS
13634 static int
13635 ktls_capability(struct adapter *sc, bool enable)
13636 {
13637 	ASSERT_SYNCHRONIZED_OP(sc);
13638 
13639 	if (!is_ktls(sc))
13640 		return (ENODEV);
13641 	if (!is_t6(sc))
13642 		return (0);
13643 	if (!hw_all_ok(sc))
13644 		return (ENXIO);
13645 
13646 	if (enable) {
13647 		if (sc->flags & KERN_TLS_ON)
13648 			return (0);	/* already on */
13649 		if (sc->offload_map != 0) {
13650 			CH_WARN(sc,
13651 			    "Disable TOE on all interfaces associated with "
13652 			    "this adapter before trying to enable NIC TLS.\n");
13653 			return (EAGAIN);
13654 		}
13655 		return (t6_config_kern_tls(sc, true));
13656 	} else {
13657 		/*
13658 		 * Nothing to do for disable.  If TOE is enabled sometime later
13659 		 * then toe_capability will reconfigure the hardware.
13660 		 */
13661 		return (0);
13662 	}
13663 }
13664 #endif
13665 
13666 /*
13667  * t  = ptr to tunable.
13668  * nc = number of CPUs.
13669  * c  = compiled in default for that tunable.
13670  */
13671 static void
13672 calculate_nqueues(int *t, int nc, const int c)
13673 {
13674 	int nq;
13675 
13676 	if (*t > 0)
13677 		return;
13678 	nq = *t < 0 ? -*t : c;
13679 	*t = min(nc, nq);
13680 }
13681 
13682 /*
13683  * Come up with reasonable defaults for some of the tunables, provided they're
13684  * not set by the user (in which case we'll use the values as is).
13685  */
13686 static void
13687 tweak_tunables(void)
13688 {
13689 	int nc = mp_ncpus;	/* our snapshot of the number of CPUs */
13690 
13691 	if (t4_ntxq < 1) {
13692 #ifdef RSS
13693 		t4_ntxq = rss_getnumbuckets();
13694 #else
13695 		calculate_nqueues(&t4_ntxq, nc, NTXQ);
13696 #endif
13697 	}
13698 
13699 	calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
13700 
13701 	if (t4_nrxq < 1) {
13702 #ifdef RSS
13703 		t4_nrxq = rss_getnumbuckets();
13704 #else
13705 		calculate_nqueues(&t4_nrxq, nc, NRXQ);
13706 #endif
13707 	}
13708 
13709 	calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
13710 
13711 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
13712 	calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
13713 	calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
13714 #endif
13715 #ifdef TCP_OFFLOAD
13716 	calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
13717 	calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
13718 #endif
13719 
13720 #if defined(TCP_OFFLOAD) || defined(KERN_TLS)
13721 	if (t4_toecaps_allowed == -1)
13722 		t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
13723 #else
13724 	if (t4_toecaps_allowed == -1)
13725 		t4_toecaps_allowed = 0;
13726 #endif
13727 
13728 #ifdef TCP_OFFLOAD
13729 	if (t4_rdmacaps_allowed == -1) {
13730 		t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
13731 		    FW_CAPS_CONFIG_RDMA_RDMAC;
13732 	}
13733 
13734 	if (t4_iscsicaps_allowed == -1) {
13735 		t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
13736 		    FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
13737 		    FW_CAPS_CONFIG_ISCSI_T10DIF;
13738 	}
13739 
13740 	if (t4_nvmecaps_allowed == -1)
13741 		t4_nvmecaps_allowed = FW_CAPS_CONFIG_NVME_TCP;
13742 
13743 	if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
13744 		t4_tmr_idx_ofld = TMR_IDX_OFLD;
13745 
13746 	if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
13747 		t4_pktc_idx_ofld = PKTC_IDX_OFLD;
13748 #else
13749 	if (t4_rdmacaps_allowed == -1)
13750 		t4_rdmacaps_allowed = 0;
13751 
13752 	if (t4_iscsicaps_allowed == -1)
13753 		t4_iscsicaps_allowed = 0;
13754 
13755 	if (t4_nvmecaps_allowed == -1)
13756 		t4_nvmecaps_allowed = 0;
13757 #endif
13758 
13759 #ifdef DEV_NETMAP
13760 	calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ);
13761 	calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ);
13762 	calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
13763 	calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
13764 #endif
13765 
13766 	if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
13767 		t4_tmr_idx = TMR_IDX;
13768 
13769 	if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
13770 		t4_pktc_idx = PKTC_IDX;
13771 
13772 	if (t4_qsize_txq < 128)
13773 		t4_qsize_txq = 128;
13774 
13775 	if (t4_qsize_rxq < 128)
13776 		t4_qsize_rxq = 128;
13777 	while (t4_qsize_rxq & 7)
13778 		t4_qsize_rxq++;
13779 
13780 	t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
13781 
13782 	/*
13783 	 * Number of VIs to create per-port.  The first VI is the "main" regular
13784 	 * VI for the port.  The rest are additional virtual interfaces on the
13785 	 * same physical port.  Note that the main VI does not have native
13786 	 * netmap support but the extra VIs do.
13787 	 *
13788 	 * Limit the number of VIs per port to the number of available
13789 	 * MAC addresses per port.
13790 	 */
13791 	if (t4_num_vis < 1)
13792 		t4_num_vis = 1;
13793 	if (t4_num_vis > nitems(vi_mac_funcs)) {
13794 		t4_num_vis = nitems(vi_mac_funcs);
13795 		printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
13796 	}
13797 
13798 	if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
13799 		pcie_relaxed_ordering = 1;
13800 #if defined(__i386__) || defined(__amd64__)
13801 		if (cpu_vendor_id == CPU_VENDOR_INTEL)
13802 			pcie_relaxed_ordering = 0;
13803 #endif
13804 	}
13805 }
13806 
13807 #ifdef DDB
13808 static void
13809 t4_dump_mem(struct adapter *sc, u_int addr, u_int len)
13810 {
13811 	uint32_t base, j, off, pf, reg, save, win_pos;
13812 
13813 	reg = chip_id(sc) > CHELSIO_T6 ?
13814 	    PCIE_MEM_ACCESS_T7_REG(A_PCIE_MEM_ACCESS_OFFSET0, 2) :
13815 	    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
13816 	save = t4_read_reg(sc, reg);
13817 	base = sc->memwin[2].mw_base;
13818 
13819 	if (is_t4(sc)) {
13820 		pf = 0;
13821 		win_pos = addr & ~0xf;	/* start must be 16B aligned */
13822 	} else {
13823 		pf = V_PFNUM(sc->pf);
13824 		win_pos = addr & ~0x7f;	/* start must be 128B aligned */
13825 	}
13826 	off = addr - win_pos;
13827 	if (chip_id(sc) > CHELSIO_T6)
13828 		win_pos >>= X_T7_MEMOFST_SHIFT;
13829 	t4_write_reg(sc, reg, win_pos | pf);
13830 	t4_read_reg(sc, reg);
13831 
13832 	while (len > 0 && !db_pager_quit) {
13833 		uint32_t buf[8];
13834 		for (j = 0; j < 8; j++, off += 4)
13835 			buf[j] = htonl(t4_read_reg(sc, base + off));
13836 
13837 		db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
13838 		    buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
13839 		    buf[7]);
13840 		if (len <= sizeof(buf))
13841 			len = 0;
13842 		else
13843 			len -= sizeof(buf);
13844 	}
13845 
13846 	t4_write_reg(sc, reg, save);
13847 	t4_read_reg(sc, reg);
13848 }
13849 
13850 static void
13851 t4_dump_tcb(struct adapter *sc, int tid)
13852 {
13853 	uint32_t tcb_addr;
13854 
13855 	/* Dump TCB for the tid */
13856 	tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
13857 	tcb_addr += tid * TCB_SIZE;
13858 	t4_dump_mem(sc, tcb_addr, TCB_SIZE);
13859 }
13860 
13861 static void
13862 t4_dump_devlog(struct adapter *sc)
13863 {
13864 	struct devlog_params *dparams = &sc->params.devlog;
13865 	struct fw_devlog_e e;
13866 	int i, first, j, m, nentries, rc;
13867 	uint64_t ftstamp = UINT64_MAX;
13868 
13869 	if (dparams->start == 0) {
13870 		db_printf("devlog params not valid\n");
13871 		return;
13872 	}
13873 
13874 	nentries = dparams->size / sizeof(struct fw_devlog_e);
13875 	m = fwmtype_to_hwmtype(dparams->memtype);
13876 
13877 	/* Find the first entry. */
13878 	first = -1;
13879 	for (i = 0; i < nentries && !db_pager_quit; i++) {
13880 		rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
13881 		    sizeof(e), (void *)&e);
13882 		if (rc != 0)
13883 			break;
13884 
13885 		if (e.timestamp == 0)
13886 			break;
13887 
13888 		e.timestamp = be64toh(e.timestamp);
13889 		if (e.timestamp < ftstamp) {
13890 			ftstamp = e.timestamp;
13891 			first = i;
13892 		}
13893 	}
13894 
13895 	if (first == -1)
13896 		return;
13897 
13898 	i = first;
13899 	do {
13900 		rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
13901 		    sizeof(e), (void *)&e);
13902 		if (rc != 0)
13903 			return;
13904 
13905 		if (e.timestamp == 0)
13906 			return;
13907 
13908 		e.timestamp = be64toh(e.timestamp);
13909 		e.seqno = be32toh(e.seqno);
13910 		for (j = 0; j < 8; j++)
13911 			e.params[j] = be32toh(e.params[j]);
13912 
13913 		db_printf("%10d  %15ju  %8s  %8s  ",
13914 		    e.seqno, e.timestamp,
13915 		    (e.level < nitems(devlog_level_strings) ?
13916 			devlog_level_strings[e.level] : "UNKNOWN"),
13917 		    (e.facility < nitems(devlog_facility_strings) ?
13918 			devlog_facility_strings[e.facility] : "UNKNOWN"));
13919 		db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
13920 		    e.params[3], e.params[4], e.params[5], e.params[6],
13921 		    e.params[7]);
13922 
13923 		if (++i == nentries)
13924 			i = 0;
13925 	} while (i != first && !db_pager_quit);
13926 }
13927 
13928 static DB_DEFINE_TABLE(show, t4, show_t4);
13929 
13930 DB_TABLE_COMMAND_FLAGS(show_t4, devlog, db_show_devlog, CS_OWN)
13931 {
13932 	device_t dev;
13933 	int t;
13934 	bool valid;
13935 
13936 	valid = false;
13937 	t = db_read_token();
13938 	if (t == tIDENT) {
13939 		dev = device_lookup_by_name(db_tok_string);
13940 		valid = true;
13941 	}
13942 	db_skip_to_eol();
13943 	if (!valid) {
13944 		db_printf("usage: show t4 devlog <nexus>\n");
13945 		return;
13946 	}
13947 
13948 	if (dev == NULL) {
13949 		db_printf("device not found\n");
13950 		return;
13951 	}
13952 
13953 	t4_dump_devlog(device_get_softc(dev));
13954 }
13955 
13956 DB_TABLE_COMMAND_FLAGS(show_t4, tcb, db_show_t4tcb, CS_OWN)
13957 {
13958 	device_t dev;
13959 	int radix, tid, t;
13960 	bool valid;
13961 
13962 	valid = false;
13963 	radix = db_radix;
13964 	db_radix = 10;
13965 	t = db_read_token();
13966 	if (t == tIDENT) {
13967 		dev = device_lookup_by_name(db_tok_string);
13968 		t = db_read_token();
13969 		if (t == tNUMBER) {
13970 			tid = db_tok_number;
13971 			valid = true;
13972 		}
13973 	}
13974 	db_radix = radix;
13975 	db_skip_to_eol();
13976 	if (!valid) {
13977 		db_printf("usage: show t4 tcb <nexus> <tid>\n");
13978 		return;
13979 	}
13980 
13981 	if (dev == NULL) {
13982 		db_printf("device not found\n");
13983 		return;
13984 	}
13985 	if (tid < 0) {
13986 		db_printf("invalid tid\n");
13987 		return;
13988 	}
13989 
13990 	t4_dump_tcb(device_get_softc(dev), tid);
13991 }
13992 
13993 DB_TABLE_COMMAND_FLAGS(show_t4, memdump, db_show_memdump, CS_OWN)
13994 {
13995 	device_t dev;
13996 	int radix, t;
13997 	bool valid;
13998 
13999 	valid = false;
14000 	radix = db_radix;
14001 	db_radix = 10;
14002 	t = db_read_token();
14003 	if (t == tIDENT) {
14004 		dev = device_lookup_by_name(db_tok_string);
14005 		t = db_read_token();
14006 		if (t == tNUMBER) {
14007 			addr = db_tok_number;
14008 			t = db_read_token();
14009 			if (t == tNUMBER) {
14010 				count = db_tok_number;
14011 				valid = true;
14012 			}
14013 		}
14014 	}
14015 	db_radix = radix;
14016 	db_skip_to_eol();
14017 	if (!valid) {
14018 		db_printf("usage: show t4 memdump <nexus> <addr> <len>\n");
14019 		return;
14020 	}
14021 
14022 	if (dev == NULL) {
14023 		db_printf("device not found\n");
14024 		return;
14025 	}
14026 	if (addr < 0) {
14027 		db_printf("invalid address\n");
14028 		return;
14029 	}
14030 	if (count <= 0) {
14031 		db_printf("invalid length\n");
14032 		return;
14033 	}
14034 
14035 	t4_dump_mem(device_get_softc(dev), addr, count);
14036 }
14037 #endif
14038 
14039 static eventhandler_tag vxlan_start_evtag;
14040 static eventhandler_tag vxlan_stop_evtag;
14041 
14042 struct vxlan_evargs {
14043 	if_t ifp;
14044 	uint16_t port;
14045 };
14046 
14047 static void
14048 enable_vxlan_rx(struct adapter *sc)
14049 {
14050 	int i, rc;
14051 	struct port_info *pi;
14052 	uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
14053 
14054 	ASSERT_SYNCHRONIZED_OP(sc);
14055 
14056 	t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) |
14057 	    F_VXLAN_EN);
14058 	for_each_port(sc, i) {
14059 		pi = sc->port[i];
14060 		if (pi->vxlan_tcam_entry == true)
14061 			continue;
14062 		rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac,
14063 		    match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
14064 		    true);
14065 		if (rc < 0) {
14066 			rc = -rc;
14067 			CH_ERR(&pi->vi[0],
14068 			    "failed to add VXLAN TCAM entry: %d.\n", rc);
14069 		} else {
14070 			MPASS(rc == sc->rawf_base + pi->port_id);
14071 			pi->vxlan_tcam_entry = true;
14072 		}
14073 	}
14074 }
14075 
14076 static void
14077 t4_vxlan_start(struct adapter *sc, void *arg)
14078 {
14079 	struct vxlan_evargs *v = arg;
14080 
14081 	if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
14082 		return;
14083 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0)
14084 		return;
14085 
14086 	if (sc->vxlan_refcount == 0) {
14087 		sc->vxlan_port = v->port;
14088 		sc->vxlan_refcount = 1;
14089 		if (!hw_off_limits(sc))
14090 			enable_vxlan_rx(sc);
14091 	} else if (sc->vxlan_port == v->port) {
14092 		sc->vxlan_refcount++;
14093 	} else {
14094 		CH_ERR(sc, "VXLAN already configured on port  %d; "
14095 		    "ignoring attempt to configure it on port %d\n",
14096 		    sc->vxlan_port, v->port);
14097 	}
14098 	end_synchronized_op(sc, 0);
14099 }
14100 
14101 static void
14102 t4_vxlan_stop(struct adapter *sc, void *arg)
14103 {
14104 	struct vxlan_evargs *v = arg;
14105 
14106 	if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
14107 		return;
14108 	if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0)
14109 		return;
14110 
14111 	/*
14112 	 * VXLANs may have been configured before the driver was loaded so we
14113 	 * may see more stops than starts.  This is not handled cleanly but at
14114 	 * least we keep the refcount sane.
14115 	 */
14116 	if (sc->vxlan_port != v->port)
14117 		goto done;
14118 	if (sc->vxlan_refcount == 0) {
14119 		CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; "
14120 		    "ignoring attempt to stop it again.\n", sc->vxlan_port);
14121 	} else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc))
14122 		t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0);
14123 done:
14124 	end_synchronized_op(sc, 0);
14125 }
14126 
14127 static void
14128 t4_vxlan_start_handler(void *arg __unused, if_t ifp,
14129     sa_family_t family, u_int port)
14130 {
14131 	struct vxlan_evargs v;
14132 
14133 	MPASS(family == AF_INET || family == AF_INET6);
14134 	v.ifp = ifp;
14135 	v.port = port;
14136 
14137 	t4_iterate(t4_vxlan_start, &v);
14138 }
14139 
14140 static void
14141 t4_vxlan_stop_handler(void *arg __unused, if_t ifp, sa_family_t family,
14142     u_int port)
14143 {
14144 	struct vxlan_evargs v;
14145 
14146 	MPASS(family == AF_INET || family == AF_INET6);
14147 	v.ifp = ifp;
14148 	v.port = port;
14149 
14150 	t4_iterate(t4_vxlan_stop, &v);
14151 }
14152 
14153 
14154 static struct sx mlu;	/* mod load unload */
14155 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
14156 
14157 static int
14158 mod_event(module_t mod, int cmd, void *arg)
14159 {
14160 	int rc = 0;
14161 	static int loaded = 0;
14162 
14163 	switch (cmd) {
14164 	case MOD_LOAD:
14165 		sx_xlock(&mlu);
14166 		if (loaded++ == 0) {
14167 			t4_sge_modload();
14168 			t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
14169 			    t4_filter_rpl, CPL_COOKIE_FILTER);
14170 			t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
14171 			    do_l2t_write_rpl, CPL_COOKIE_FILTER);
14172 			t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
14173 			    t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
14174 			t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
14175 			    t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
14176 			t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
14177 			    t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
14178 			t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
14179 			t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
14180 			t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
14181 			    do_smt_write_rpl);
14182 			sx_init(&t4_list_lock, "T4/T5 adapters");
14183 			SLIST_INIT(&t4_list);
14184 			callout_init(&fatal_callout, 1);
14185 #ifdef TCP_OFFLOAD
14186 			sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
14187 #endif
14188 #ifdef INET6
14189 			t4_clip_modload();
14190 #endif
14191 #ifdef KERN_TLS
14192 			t6_ktls_modload();
14193 			t7_ktls_modload();
14194 #endif
14195 			t4_tracer_modload();
14196 			tweak_tunables();
14197 			vxlan_start_evtag =
14198 			    EVENTHANDLER_REGISTER(vxlan_start,
14199 				t4_vxlan_start_handler, NULL,
14200 				EVENTHANDLER_PRI_ANY);
14201 			vxlan_stop_evtag =
14202 			    EVENTHANDLER_REGISTER(vxlan_stop,
14203 				t4_vxlan_stop_handler, NULL,
14204 				EVENTHANDLER_PRI_ANY);
14205 			reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK,
14206 			    taskqueue_thread_enqueue, &reset_tq);
14207 			taskqueue_start_threads(&reset_tq, 1, PI_SOFT,
14208 			    "t4_rst_thr");
14209 		}
14210 		sx_xunlock(&mlu);
14211 		break;
14212 
14213 	case MOD_UNLOAD:
14214 		sx_xlock(&mlu);
14215 		if (--loaded == 0) {
14216 #ifdef TCP_OFFLOAD
14217 			int i;
14218 #endif
14219 			int tries;
14220 
14221 			taskqueue_free(reset_tq);
14222 
14223 			tries = 0;
14224 			while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
14225 				uprintf("%ju clusters with custom free routine "
14226 				    "still is use.\n", t4_sge_extfree_refs());
14227 				pause("t4unload", 2 * hz);
14228 			}
14229 
14230 			sx_slock(&t4_list_lock);
14231 			if (!SLIST_EMPTY(&t4_list)) {
14232 				rc = EBUSY;
14233 				sx_sunlock(&t4_list_lock);
14234 				goto done_unload;
14235 			}
14236 #ifdef TCP_OFFLOAD
14237 			sx_slock(&t4_uld_list_lock);
14238 			for (i = 0; i <= ULD_MAX; i++) {
14239 				if (t4_uld_list[i] != NULL) {
14240 					rc = EBUSY;
14241 					sx_sunlock(&t4_uld_list_lock);
14242 					sx_sunlock(&t4_list_lock);
14243 					goto done_unload;
14244 				}
14245 			}
14246 			sx_sunlock(&t4_uld_list_lock);
14247 #endif
14248 			sx_sunlock(&t4_list_lock);
14249 
14250 			if (t4_sge_extfree_refs() == 0) {
14251 				EVENTHANDLER_DEREGISTER(vxlan_start,
14252 				    vxlan_start_evtag);
14253 				EVENTHANDLER_DEREGISTER(vxlan_stop,
14254 				    vxlan_stop_evtag);
14255 				t4_tracer_modunload();
14256 #ifdef KERN_TLS
14257 				t7_ktls_modunload();
14258 				t6_ktls_modunload();
14259 #endif
14260 #ifdef INET6
14261 				t4_clip_modunload();
14262 #endif
14263 #ifdef TCP_OFFLOAD
14264 				sx_destroy(&t4_uld_list_lock);
14265 #endif
14266 				sx_destroy(&t4_list_lock);
14267 				t4_sge_modunload();
14268 				loaded = 0;
14269 			} else {
14270 				rc = EBUSY;
14271 				loaded++;	/* undo earlier decrement */
14272 			}
14273 		}
14274 done_unload:
14275 		sx_xunlock(&mlu);
14276 		break;
14277 	}
14278 
14279 	return (rc);
14280 }
14281 
14282 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0);
14283 MODULE_VERSION(t4nex, 1);
14284 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
14285 #ifdef DEV_NETMAP
14286 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
14287 #endif /* DEV_NETMAP */
14288 
14289 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0);
14290 MODULE_VERSION(t5nex, 1);
14291 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
14292 #ifdef DEV_NETMAP
14293 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
14294 #endif /* DEV_NETMAP */
14295 
14296 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0);
14297 MODULE_VERSION(t6nex, 1);
14298 MODULE_DEPEND(t6nex, crypto, 1, 1, 1);
14299 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
14300 #ifdef DEV_NETMAP
14301 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
14302 #endif /* DEV_NETMAP */
14303 
14304 DRIVER_MODULE(chnex, pci, ch_driver, mod_event, 0);
14305 MODULE_VERSION(chnex, 1);
14306 MODULE_DEPEND(chnex, crypto, 1, 1, 1);
14307 MODULE_DEPEND(chnex, firmware, 1, 1, 1);
14308 #ifdef DEV_NETMAP
14309 MODULE_DEPEND(chnex, netmap, 1, 1, 1);
14310 #endif /* DEV_NETMAP */
14311 
14312 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0);
14313 MODULE_VERSION(cxgbe, 1);
14314 
14315 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0);
14316 MODULE_VERSION(cxl, 1);
14317 
14318 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0);
14319 MODULE_VERSION(cc, 1);
14320 
14321 DRIVER_MODULE(che, chnex, che_driver, 0, 0);
14322 MODULE_VERSION(che, 1);
14323 
14324 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0);
14325 MODULE_VERSION(vcxgbe, 1);
14326 
14327 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0);
14328 MODULE_VERSION(vcxl, 1);
14329 
14330 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0);
14331 MODULE_VERSION(vcc, 1);
14332 
14333 DRIVER_MODULE(vche, che, vche_driver, 0, 0);
14334 MODULE_VERSION(vche, 1);
14335