1 /*- 2 * Copyright (c) 2015-2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/module.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/iov.h> 35 #include <dev/pci/pcivar.h> 36 #include <net/if.h> 37 #include <net/if_vlan_var.h> 38 39 #ifdef PCI_IOV 40 #include <sys/nv.h> 41 #include <sys/iov_schema.h> 42 #include <dev/pci/pci_iov.h> 43 #endif 44 45 #include "common/common.h" 46 #include "common/t4_regs.h" 47 #include "t4_if.h" 48 49 struct t4iov_softc { 50 device_t sc_dev; 51 device_t sc_main; 52 bool sc_attached; 53 54 int pf; 55 int regs_rid; 56 struct resource *regs_res; 57 bus_space_handle_t bh; 58 bus_space_tag_t bt; 59 }; 60 61 struct { 62 uint16_t device; 63 char *desc; 64 } t4iov_pciids[] = { 65 {0x4000, "Chelsio T440-dbg"}, 66 {0x4001, "Chelsio T420-CR"}, 67 {0x4002, "Chelsio T422-CR"}, 68 {0x4003, "Chelsio T440-CR"}, 69 {0x4004, "Chelsio T420-BCH"}, 70 {0x4005, "Chelsio T440-BCH"}, 71 {0x4006, "Chelsio T440-CH"}, 72 {0x4007, "Chelsio T420-SO"}, 73 {0x4008, "Chelsio T420-CX"}, 74 {0x4009, "Chelsio T420-BT"}, 75 {0x400a, "Chelsio T404-BT"}, 76 {0x400e, "Chelsio T440-LP-CR"}, 77 }, t5iov_pciids[] = { 78 {0x5000, "Chelsio T580-dbg"}, 79 {0x5001, "Chelsio T520-CR"}, /* 2 x 10G */ 80 {0x5002, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 81 {0x5003, "Chelsio T540-CR"}, /* 4 x 10G */ 82 {0x5007, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 83 {0x5009, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 84 {0x500a, "Chelsio T504-BT"}, /* 4 x 1G */ 85 {0x500d, "Chelsio T580-CR"}, /* 2 x 40G */ 86 {0x500e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 87 {0x5010, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 88 {0x5011, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 89 {0x5012, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 90 {0x5014, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 91 {0x5015, "Chelsio T502-BT"}, /* 2 x 1G */ 92 {0x5018, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 93 {0x5019, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 94 {0x501a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 95 {0x501b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 96 }, t6iov_pciids[] = { 97 {0x6000, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 98 {0x6001, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 99 {0x6002, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 100 {0x6003, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 101 {0x6004, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 102 {0x6005, "Chelsio T6225-SO-OCP3"}, /* 2 x 10/25G, nomem */ 103 {0x6006, "Chelsio T6225-OCP3"}, /* 2 x 10/25G */ 104 {0x6007, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 105 {0x6008, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 106 {0x6009, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 107 {0x600d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 108 {0x6010, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 109 {0x6011, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 110 {0x6014, "Chelsio T62100-SO-OCP3"}, /* 2 x 40/50/100G, nomem */ 111 {0x6015, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 112 113 /* Custom */ 114 {0x6080, "Chelsio T6225 80"}, 115 {0x6081, "Chelsio T62100 81"}, 116 {0x6082, "Chelsio T6225-CR 82"}, 117 {0x6083, "Chelsio T62100-CR 83"}, 118 {0x6084, "Chelsio T64100-CR 84"}, 119 {0x6085, "Chelsio T6240-SO 85"}, 120 {0x6086, "Chelsio T6225-SO-CR 86"}, 121 {0x6087, "Chelsio T6225-CR 87"}, 122 }, t7iov_pciids[] = { 123 {0xd000, "Chelsio Terminator 7 FPGA"}, /* T7 PE12K FPGA */ 124 {0x7000, "Chelsio T72200-DBG"}, /* 2 x 200G, debug */ 125 {0x7001, "Chelsio T7250"}, /* 2 x 10/25/50G, 1 mem */ 126 {0x7002, "Chelsio S7250"}, /* 2 x 10/25/50G, nomem */ 127 {0x7003, "Chelsio T7450"}, /* 4 x 10/25/50G, 1 mem */ 128 {0x7004, "Chelsio S7450"}, /* 4 x 10/25/50G, nomem */ 129 {0x7005, "Chelsio T72200"}, /* 2 x 40/100/200G, 1 mem */ 130 {0x7006, "Chelsio S72200"}, /* 2 x 40/100/200G, nomem */ 131 {0x7007, "Chelsio T72200-FH"}, /* 2 x 40/100/200G, 2 mem */ 132 {0x7008, "Chelsio T71400"}, /* 1 x 400G, nomem */ 133 {0x7009, "Chelsio S7210-BT"}, /* 2 x 10GBASE-T, nomem */ 134 {0x700a, "Chelsio T7450-RC"}, /* 4 x 10/25/50G, 1 mem, RC */ 135 {0x700b, "Chelsio T72200-RC"}, /* 2 x 40/100/200G, 1 mem, RC */ 136 {0x700c, "Chelsio T72200-FH-RC"}, /* 2 x 40/100/200G, 2 mem, RC */ 137 {0x700d, "Chelsio S72200-OCP3"}, /* 2 x 40/100/200G OCP3 */ 138 {0x700e, "Chelsio S7450-OCP3"}, /* 4 x 1/20/25/50G OCP3 */ 139 {0x700f, "Chelsio S7410-BT-OCP3"}, /* 4 x 10GBASE-T OCP3 */ 140 {0x7010, "Chelsio S7210-BT-A"}, /* 2 x 10GBASE-T */ 141 {0x7011, "Chelsio T7_MAYRA_7"}, /* Motherboard */ 142 143 {0x7080, "Custom T7"}, 144 }; 145 146 static inline uint32_t 147 t4iov_read_reg(struct t4iov_softc *sc, uint32_t reg) 148 { 149 150 return bus_space_read_4(sc->bt, sc->bh, reg); 151 } 152 153 static int t4iov_attach_child(device_t dev); 154 155 static int 156 t4iov_probe(device_t dev) 157 { 158 uint16_t d; 159 size_t i; 160 161 if (pci_get_vendor(dev) != PCI_VENDOR_ID_CHELSIO) 162 return (ENXIO); 163 164 d = pci_get_device(dev); 165 for (i = 0; i < nitems(t4iov_pciids); i++) { 166 if (d == t4iov_pciids[i].device) { 167 device_set_desc(dev, t4iov_pciids[i].desc); 168 device_quiet(dev); 169 return (BUS_PROBE_DEFAULT); 170 } 171 } 172 return (ENXIO); 173 } 174 175 static int 176 t5iov_probe(device_t dev) 177 { 178 uint16_t d; 179 size_t i; 180 181 if (pci_get_vendor(dev) != PCI_VENDOR_ID_CHELSIO) 182 return (ENXIO); 183 184 d = pci_get_device(dev); 185 for (i = 0; i < nitems(t5iov_pciids); i++) { 186 if (d == t5iov_pciids[i].device) { 187 device_set_desc(dev, t5iov_pciids[i].desc); 188 device_quiet(dev); 189 return (BUS_PROBE_DEFAULT); 190 } 191 } 192 return (ENXIO); 193 } 194 195 static int 196 t6iov_probe(device_t dev) 197 { 198 uint16_t d; 199 size_t i; 200 201 if (pci_get_vendor(dev) != PCI_VENDOR_ID_CHELSIO) 202 return (ENXIO); 203 204 d = pci_get_device(dev); 205 for (i = 0; i < nitems(t6iov_pciids); i++) { 206 if (d == t6iov_pciids[i].device) { 207 device_set_desc(dev, t6iov_pciids[i].desc); 208 device_quiet(dev); 209 return (BUS_PROBE_DEFAULT); 210 } 211 } 212 return (ENXIO); 213 } 214 215 static int 216 chiov_probe(device_t dev) 217 { 218 uint16_t d; 219 size_t i; 220 221 if (pci_get_vendor(dev) != PCI_VENDOR_ID_CHELSIO) 222 return (ENXIO); 223 224 d = pci_get_device(dev); 225 for (i = 0; i < nitems(t7iov_pciids); i++) { 226 if (d == t7iov_pciids[i].device) { 227 device_set_desc(dev, t7iov_pciids[i].desc); 228 device_quiet(dev); 229 return (BUS_PROBE_DEFAULT); 230 } 231 } 232 return (ENXIO); 233 } 234 235 static int 236 t4iov_attach(device_t dev) 237 { 238 struct t4iov_softc *sc; 239 uint32_t pl_rev, whoami; 240 int error; 241 242 sc = device_get_softc(dev); 243 sc->sc_dev = dev; 244 245 sc->regs_rid = PCIR_BAR(0); 246 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 247 &sc->regs_rid, RF_ACTIVE); 248 if (sc->regs_res == NULL) { 249 device_printf(dev, "cannot map registers.\n"); 250 return (ENXIO); 251 } 252 sc->bt = rman_get_bustag(sc->regs_res); 253 sc->bh = rman_get_bushandle(sc->regs_res); 254 255 pl_rev = t4iov_read_reg(sc, A_PL_REV); 256 whoami = t4iov_read_reg(sc, A_PL_WHOAMI); 257 if (G_CHIPID(pl_rev) <= CHELSIO_T5) 258 sc->pf = G_SOURCEPF(whoami); 259 else 260 sc->pf = G_T6_SOURCEPF(whoami); 261 262 sc->sc_main = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 263 pci_get_slot(dev), 4); 264 if (sc->sc_main == NULL) { 265 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 266 sc->regs_res); 267 return (ENXIO); 268 } 269 if (T4_IS_MAIN_READY(sc->sc_main) == 0) { 270 error = t4iov_attach_child(dev); 271 if (error != 0) 272 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 273 sc->regs_res); 274 return (error); 275 } 276 return (0); 277 } 278 279 static int 280 t4iov_attach_child(device_t dev) 281 { 282 struct t4iov_softc *sc; 283 #ifdef PCI_IOV 284 nvlist_t *pf_schema, *vf_schema; 285 #endif 286 device_t pdev; 287 int error; 288 289 sc = device_get_softc(dev); 290 MPASS(!sc->sc_attached); 291 292 /* 293 * PF0-3 are associated with a specific port on the NIC (PF0 294 * with port 0, etc.). Ask the PF4 driver for the device for 295 * this function's associated port to determine if the port is 296 * present. 297 */ 298 error = T4_READ_PORT_DEVICE(sc->sc_main, pci_get_function(dev), &pdev); 299 if (error) 300 return (0); 301 302 #ifdef PCI_IOV 303 pf_schema = pci_iov_schema_alloc_node(); 304 vf_schema = pci_iov_schema_alloc_node(); 305 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); 306 pci_iov_schema_add_vlan(vf_schema, "vlan", 0, 0); 307 error = pci_iov_attach_name(dev, pf_schema, vf_schema, "%s", 308 device_get_nameunit(pdev)); 309 if (error) { 310 device_printf(dev, "Failed to initialize SR-IOV: %d\n", error); 311 return (0); 312 } 313 #endif 314 315 sc->sc_attached = true; 316 return (0); 317 } 318 319 static int 320 t4iov_detach_child(device_t dev) 321 { 322 struct t4iov_softc *sc; 323 #ifdef PCI_IOV 324 int error; 325 #endif 326 327 sc = device_get_softc(dev); 328 if (!sc->sc_attached) 329 return (0); 330 331 #ifdef PCI_IOV 332 error = pci_iov_detach(dev); 333 if (error != 0) { 334 device_printf(dev, "Failed to disable SR-IOV\n"); 335 return (error); 336 } 337 #endif 338 339 sc->sc_attached = false; 340 return (0); 341 } 342 343 static int 344 t4iov_detach(device_t dev) 345 { 346 struct t4iov_softc *sc; 347 int error; 348 349 sc = device_get_softc(dev); 350 if (sc->sc_attached) { 351 error = t4iov_detach_child(dev); 352 if (error) 353 return (error); 354 } 355 if (sc->regs_res) { 356 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 357 sc->regs_res); 358 } 359 return (0); 360 } 361 362 #ifdef PCI_IOV 363 static int 364 t4iov_iov_init(device_t dev, uint16_t num_vfs, const struct nvlist *config) 365 { 366 367 /* XXX: The Linux driver sets up a vf_monitor task on T4 adapters. */ 368 return (0); 369 } 370 371 static void 372 t4iov_iov_uninit(device_t dev) 373 { 374 } 375 376 static int 377 t4iov_add_vf(device_t dev, uint16_t vfnum, const struct nvlist *config) 378 { 379 const void *mac; 380 struct t4iov_softc *sc; 381 struct adapter *adap; 382 uint8_t ma[ETHER_ADDR_LEN]; 383 size_t size; 384 int rc; 385 386 sc = device_get_softc(dev); 387 MPASS(sc->sc_attached); 388 MPASS(sc->sc_main != NULL); 389 adap = device_get_softc(sc->sc_main); 390 391 if (nvlist_exists_binary(config, "mac-addr")) { 392 mac = nvlist_get_binary(config, "mac-addr", &size); 393 bcopy(mac, ma, ETHER_ADDR_LEN); 394 395 if (begin_synchronized_op(adap, NULL, SLEEP_OK | INTR_OK, 396 "t4vfma") != 0) 397 return (ENXIO); 398 rc = -t4_set_vf_mac(adap, sc->pf, vfnum + 1, 1, ma); 399 end_synchronized_op(adap, 0); 400 if (rc != 0) { 401 device_printf(dev, 402 "Failed to set VF%d MAC address to " 403 "%02x:%02x:%02x:%02x:%02x:%02x, rc = %d\n", vfnum, 404 ma[0], ma[1], ma[2], ma[3], ma[4], ma[5], rc); 405 return (rc); 406 } 407 } 408 409 if (nvlist_exists_number(config, "vlan")) { 410 uint16_t vlan = nvlist_get_number(config, "vlan"); 411 412 /* We can't restrict to VID 0 */ 413 if (vlan == DOT1Q_VID_NULL) 414 return (ENOTSUP); 415 416 if (vlan == VF_VLAN_TRUNK) 417 vlan = DOT1Q_VID_NULL; 418 419 if (begin_synchronized_op(adap, NULL, SLEEP_OK | INTR_OK, 420 "t4vfvl") != 0) 421 return (ENXIO); 422 rc = t4_set_vlan_acl(adap, sc->pf, vfnum + 1, vlan); 423 end_synchronized_op(adap, 0); 424 if (rc != 0) { 425 device_printf(dev, 426 "Failed to set VF%d VLAN to %d, rc = %d\n", 427 vfnum, vlan, rc); 428 return (rc); 429 } 430 } 431 432 return (0); 433 } 434 #endif 435 436 static device_method_t t4iov_methods[] = { 437 DEVMETHOD(device_probe, t4iov_probe), 438 DEVMETHOD(device_attach, t4iov_attach), 439 DEVMETHOD(device_detach, t4iov_detach), 440 441 #ifdef PCI_IOV 442 DEVMETHOD(pci_iov_init, t4iov_iov_init), 443 DEVMETHOD(pci_iov_uninit, t4iov_iov_uninit), 444 DEVMETHOD(pci_iov_add_vf, t4iov_add_vf), 445 #endif 446 447 DEVMETHOD(t4_attach_child, t4iov_attach_child), 448 DEVMETHOD(t4_detach_child, t4iov_detach_child), 449 450 DEVMETHOD_END 451 }; 452 453 static driver_t t4iov_driver = { 454 "t4iov", 455 t4iov_methods, 456 sizeof(struct t4iov_softc) 457 }; 458 459 static device_method_t t5iov_methods[] = { 460 DEVMETHOD(device_probe, t5iov_probe), 461 DEVMETHOD(device_attach, t4iov_attach), 462 DEVMETHOD(device_detach, t4iov_detach), 463 464 #ifdef PCI_IOV 465 DEVMETHOD(pci_iov_init, t4iov_iov_init), 466 DEVMETHOD(pci_iov_uninit, t4iov_iov_uninit), 467 DEVMETHOD(pci_iov_add_vf, t4iov_add_vf), 468 #endif 469 470 DEVMETHOD(t4_attach_child, t4iov_attach_child), 471 DEVMETHOD(t4_detach_child, t4iov_detach_child), 472 473 DEVMETHOD_END 474 }; 475 476 static driver_t t5iov_driver = { 477 "t5iov", 478 t5iov_methods, 479 sizeof(struct t4iov_softc) 480 }; 481 482 static device_method_t t6iov_methods[] = { 483 DEVMETHOD(device_probe, t6iov_probe), 484 DEVMETHOD(device_attach, t4iov_attach), 485 DEVMETHOD(device_detach, t4iov_detach), 486 487 #ifdef PCI_IOV 488 DEVMETHOD(pci_iov_init, t4iov_iov_init), 489 DEVMETHOD(pci_iov_uninit, t4iov_iov_uninit), 490 DEVMETHOD(pci_iov_add_vf, t4iov_add_vf), 491 #endif 492 493 DEVMETHOD(t4_attach_child, t4iov_attach_child), 494 DEVMETHOD(t4_detach_child, t4iov_detach_child), 495 496 DEVMETHOD_END 497 }; 498 499 static driver_t t6iov_driver = { 500 "t6iov", 501 t6iov_methods, 502 sizeof(struct t4iov_softc) 503 }; 504 505 static device_method_t chiov_methods[] = { 506 DEVMETHOD(device_probe, chiov_probe), 507 DEVMETHOD(device_attach, t4iov_attach), 508 DEVMETHOD(device_detach, t4iov_detach), 509 510 #ifdef PCI_IOV 511 DEVMETHOD(pci_iov_init, t4iov_iov_init), 512 DEVMETHOD(pci_iov_uninit, t4iov_iov_uninit), 513 DEVMETHOD(pci_iov_add_vf, t4iov_add_vf), 514 #endif 515 516 DEVMETHOD(t4_attach_child, t4iov_attach_child), 517 DEVMETHOD(t4_detach_child, t4iov_detach_child), 518 519 DEVMETHOD_END 520 }; 521 522 static driver_t chiov_driver = { 523 "chiov", 524 chiov_methods, 525 sizeof(struct t4iov_softc) 526 }; 527 DRIVER_MODULE(t4iov, pci, t4iov_driver, 0, 0); 528 MODULE_VERSION(t4iov, 1); 529 530 DRIVER_MODULE(t5iov, pci, t5iov_driver, 0, 0); 531 MODULE_VERSION(t5iov, 1); 532 533 DRIVER_MODULE(t6iov, pci, t6iov_driver, 0, 0); 534 MODULE_VERSION(t6iov, 1); 535 536 DRIVER_MODULE(chiov, pci, chiov_driver, 0, 0); 537 MODULE_VERSION(chiov, 1); 538