1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_IOCTL_H__ 32 #define __T4_IOCTL_H__ 33 34 #include <sys/types.h> 35 #include <net/ethernet.h> 36 37 /* 38 * Ioctl commands specific to this driver. 39 */ 40 enum { 41 T4_GETREG = 0x40, /* read register */ 42 T4_SETREG, /* write register */ 43 T4_REGDUMP, /* dump of all registers */ 44 T4_GET_FILTER_MODE, /* get global filter mode */ 45 T4_SET_FILTER_MODE, /* set global filter mode */ 46 T4_GET_FILTER, /* get information about a filter */ 47 T4_SET_FILTER, /* program a filter */ 48 T4_DEL_FILTER, /* delete a filter */ 49 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 50 T4_LOAD_FW, /* flash firmware */ 51 T4_GET_MEM, /* read memory */ 52 T4_GET_I2C, /* read from i2c addressible device */ 53 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 54 }; 55 56 struct t4_reg { 57 uint32_t addr; 58 uint32_t size; 59 uint64_t val; 60 }; 61 62 #define T4_REGDUMP_SIZE (160 * 1024) 63 #define T5_REGDUMP_SIZE (332 * 1024) 64 struct t4_regdump { 65 uint32_t version; 66 uint32_t len; /* bytes */ 67 uint32_t *data; 68 }; 69 70 struct t4_data { 71 uint32_t len; 72 uint8_t *data; 73 }; 74 75 struct t4_i2c_data { 76 uint8_t port_id; 77 uint8_t dev_addr; 78 uint8_t offset; 79 uint8_t len; 80 uint8_t data[8]; 81 }; 82 83 /* 84 * A hardware filter is some valid combination of these. 85 */ 86 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 87 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 88 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 89 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 90 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 91 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 92 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 93 #define T4_FILTER_PORT 0x80 /* Physical ingress port */ 94 #define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 95 #define T4_FILTER_VLAN 0x200 /* VLAN ID */ 96 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 97 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 98 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 99 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 100 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 101 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 102 103 /* Filter action */ 104 enum { 105 FILTER_PASS = 0, /* default */ 106 FILTER_DROP, 107 FILTER_SWITCH 108 }; 109 110 /* 802.1q manipulation on FILTER_SWITCH */ 111 enum { 112 VLAN_NOCHANGE = 0, /* default */ 113 VLAN_REMOVE, 114 VLAN_INSERT, 115 VLAN_REWRITE 116 }; 117 118 /* MPS match type */ 119 enum { 120 UCAST_EXACT = 0, /* exact unicast match */ 121 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 122 MCAST_EXACT = 2, /* exact multicast match */ 123 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 124 PROMISC = 4, /* no match but port is promiscuous */ 125 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 126 BCAST = 6, /* broadcast packet */ 127 }; 128 129 /* Rx steering */ 130 enum { 131 DST_MODE_QUEUE, /* queue is directly specified by filter */ 132 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 133 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 134 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 135 RSS subtable */ 136 }; 137 138 struct t4_filter_tuple { 139 /* 140 * These are always available. 141 */ 142 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 143 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 144 uint16_t sport; /* source port */ 145 uint16_t dport; /* destination port */ 146 147 /* 148 * A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP 149 * is used to select the global mode and all filters are limited to the 150 * set of fields allowed by the global mode. 151 */ 152 uint16_t vnic; /* VNIC id or outer VLAN tag */ 153 uint16_t vlan; /* VLAN tag */ 154 uint16_t ethtype; /* Ethernet type */ 155 uint8_t tos; /* TOS/Traffic Type */ 156 uint8_t proto; /* protocol type */ 157 uint32_t fcoe:1; /* FCoE packet */ 158 uint32_t iport:3; /* ingress port */ 159 uint32_t matchtype:3; /* MPS match type */ 160 uint32_t frag:1; /* fragmentation extension header */ 161 uint32_t macidx:9; /* exact match MAC index */ 162 uint32_t vlan_vld:1; /* VLAN valid */ 163 uint32_t vnic_vld:1; /* VNIC id/outer VLAN tag valid */ 164 }; 165 166 struct t4_filter_specification { 167 uint32_t hitcnts:1; /* count filter hits in TCB */ 168 uint32_t prio:1; /* filter has priority over active/server */ 169 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 170 uint32_t action:2; /* drop, pass, switch */ 171 uint32_t rpttid:1; /* report TID in RSS hash field */ 172 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 173 uint32_t iq:10; /* ingress queue */ 174 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 175 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 176 /* 1 => TCB contains IQ ID */ 177 178 /* 179 * Switch proxy/rewrite fields. An ingress packet which matches a 180 * filter with "switch" set will be looped back out as an egress 181 * packet -- potentially with some Ethernet header rewriting. 182 */ 183 uint32_t eport:2; /* egress port to switch packet out */ 184 uint32_t newdmac:1; /* rewrite destination MAC address */ 185 uint32_t newsmac:1; /* rewrite source MAC address */ 186 uint32_t newvlan:2; /* rewrite VLAN Tag */ 187 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 188 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 189 uint16_t vlan; /* VLAN Tag to insert */ 190 191 /* 192 * Filter rule value/mask pairs. 193 */ 194 struct t4_filter_tuple val; 195 struct t4_filter_tuple mask; 196 }; 197 198 struct t4_filter { 199 uint32_t idx; 200 uint16_t l2tidx; 201 uint16_t smtidx; 202 uint64_t hits; 203 struct t4_filter_specification fs; 204 }; 205 206 #define T4_SGE_CONTEXT_SIZE 24 207 enum { 208 SGE_CONTEXT_EGRESS, 209 SGE_CONTEXT_INGRESS, 210 SGE_CONTEXT_FLM, 211 SGE_CONTEXT_CNM 212 }; 213 214 struct t4_sge_context { 215 uint32_t mem_id; 216 uint32_t cid; 217 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 218 }; 219 220 struct t4_mem_range { 221 uint32_t addr; 222 uint32_t len; 223 uint32_t *data; 224 }; 225 226 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 227 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 228 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 229 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 230 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 231 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 232 #define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 233 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 234 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 235 struct t4_sge_context) 236 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 237 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 238 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 239 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 240 #endif 241