1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_IOCTL_H__ 34 #define __T4_IOCTL_H__ 35 36 #include <sys/types.h> 37 #include <net/ethernet.h> 38 39 /* 40 * Ioctl commands specific to this driver. 41 */ 42 enum { 43 T4_GETREG = 0x40, /* read register */ 44 T4_SETREG, /* write register */ 45 T4_REGDUMP, /* dump of all registers */ 46 T4_GET_FILTER_MODE, /* get global filter mode */ 47 T4_SET_FILTER_MODE, /* set global filter mode */ 48 T4_GET_FILTER, /* get information about a filter */ 49 T4_SET_FILTER, /* program a filter */ 50 T4_DEL_FILTER, /* delete a filter */ 51 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 52 T4_LOAD_FW, /* flash firmware */ 53 T4_GET_MEM, /* read memory */ 54 T4_GET_I2C, /* read from i2c addressible device */ 55 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 56 T4_SET_OFLD_POLICY, /* Set offload policy */ 57 T4_SET_SCHED_CLASS, /* set sched class */ 58 T4_SET_SCHED_QUEUE, /* set queue class */ 59 T4_GET_TRACER, /* get information about a tracer */ 60 T4_SET_TRACER, /* program a tracer */ 61 T4_LOAD_CFG, /* copy a config file to card's flash */ 62 T4_LOAD_BOOT, /* flash boot rom */ 63 T4_LOAD_BOOTCFG, /* flash bootcfg */ 64 T4_CUDBG_DUMP, /* debug dump of chip state */ 65 }; 66 67 struct t4_reg { 68 uint32_t addr; 69 uint32_t size; 70 uint64_t val; 71 }; 72 73 #define T4_REGDUMP_SIZE (160 * 1024) 74 #define T5_REGDUMP_SIZE (332 * 1024) 75 struct t4_regdump { 76 uint32_t version; 77 uint32_t len; /* bytes */ 78 uint32_t *data; 79 }; 80 81 struct t4_data { 82 uint32_t len; 83 uint8_t *data; 84 }; 85 86 struct t4_bootrom { 87 uint32_t pf_offset; 88 uint32_t pfidx_addr; 89 uint32_t len; 90 uint8_t *data; 91 }; 92 93 struct t4_i2c_data { 94 uint8_t port_id; 95 uint8_t dev_addr; 96 uint8_t offset; 97 uint8_t len; 98 uint8_t data[8]; 99 }; 100 101 /* 102 * A hardware filter is some valid combination of these. 103 */ 104 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 105 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 106 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 107 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 108 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 109 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 110 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 111 #define T4_FILTER_PORT 0x80 /* Physical ingress port */ 112 #define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 113 #define T4_FILTER_VLAN 0x200 /* VLAN ID */ 114 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 115 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 116 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 117 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 118 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 119 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 120 121 #define T4_FILTER_IC_VNIC 0x80000000 /* TP Ingress Config's F_VNIC 122 bit. It indicates whether 123 T4_FILTER_VNIC bit means VNIC 124 id (PF/VF) or outer VLAN. 125 0 = oVLAN, 1 = VNIC */ 126 127 /* Filter action */ 128 enum { 129 FILTER_PASS = 0, /* default */ 130 FILTER_DROP, 131 FILTER_SWITCH 132 }; 133 134 /* 802.1q manipulation on FILTER_SWITCH */ 135 enum { 136 VLAN_NOCHANGE = 0, /* default */ 137 VLAN_REMOVE, 138 VLAN_INSERT, 139 VLAN_REWRITE 140 }; 141 142 /* MPS match type */ 143 enum { 144 UCAST_EXACT = 0, /* exact unicast match */ 145 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 146 MCAST_EXACT = 2, /* exact multicast match */ 147 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 148 PROMISC = 4, /* no match but port is promiscuous */ 149 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 150 BCAST = 6, /* broadcast packet */ 151 }; 152 153 /* Rx steering */ 154 enum { 155 DST_MODE_QUEUE, /* queue is directly specified by filter */ 156 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 157 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 158 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 159 RSS subtable */ 160 }; 161 162 struct t4_filter_tuple { 163 /* 164 * These are always available. 165 */ 166 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 167 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 168 uint16_t sport; /* source port */ 169 uint16_t dport; /* destination port */ 170 171 /* 172 * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP 173 * is used to select the global mode and all filters are limited to the 174 * set of fields allowed by the global mode. 175 */ 176 uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */ 177 uint16_t vlan; /* VLAN tag */ 178 uint16_t ethtype; /* Ethernet type */ 179 uint8_t tos; /* TOS/Traffic Type */ 180 uint8_t proto; /* protocol type */ 181 uint32_t fcoe:1; /* FCoE packet */ 182 uint32_t iport:3; /* ingress port */ 183 uint32_t matchtype:3; /* MPS match type */ 184 uint32_t frag:1; /* fragmentation extension header */ 185 uint32_t macidx:9; /* exact match MAC index */ 186 uint32_t vlan_vld:1; /* VLAN valid */ 187 uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */ 188 uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */ 189 }; 190 191 struct t4_filter_specification { 192 uint32_t hitcnts:1; /* count filter hits in TCB */ 193 uint32_t prio:1; /* filter has priority over active/server */ 194 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 195 uint32_t action:2; /* drop, pass, switch */ 196 uint32_t rpttid:1; /* report TID in RSS hash field */ 197 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 198 uint32_t iq:10; /* ingress queue */ 199 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 200 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 201 /* 1 => TCB contains IQ ID */ 202 203 /* 204 * Switch proxy/rewrite fields. An ingress packet which matches a 205 * filter with "switch" set will be looped back out as an egress 206 * packet -- potentially with some Ethernet header rewriting. 207 */ 208 uint32_t eport:2; /* egress port to switch packet out */ 209 uint32_t newdmac:1; /* rewrite destination MAC address */ 210 uint32_t newsmac:1; /* rewrite source MAC address */ 211 uint32_t newvlan:2; /* rewrite VLAN Tag */ 212 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 213 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 214 uint16_t vlan; /* VLAN Tag to insert */ 215 216 /* 217 * Filter rule value/mask pairs. 218 */ 219 struct t4_filter_tuple val; 220 struct t4_filter_tuple mask; 221 }; 222 223 struct t4_filter { 224 uint32_t idx; 225 uint16_t l2tidx; 226 uint16_t smtidx; 227 uint64_t hits; 228 struct t4_filter_specification fs; 229 }; 230 231 /* Tx Scheduling Class parameters */ 232 struct t4_sched_class_params { 233 int8_t level; /* scheduler hierarchy level */ 234 int8_t mode; /* per-class or per-flow */ 235 int8_t rateunit; /* bit or packet rate */ 236 int8_t ratemode; /* %port relative or kbps absolute */ 237 int8_t channel; /* scheduler channel [0..N] */ 238 int8_t cl; /* scheduler class [0..N] */ 239 int32_t minrate; /* minimum rate */ 240 int32_t maxrate; /* maximum rate */ 241 int16_t weight; /* percent weight */ 242 int16_t pktsize; /* average packet size */ 243 }; 244 245 /* 246 * Support for "sched-class" command to allow a TX Scheduling Class to be 247 * programmed with various parameters. 248 */ 249 struct t4_sched_params { 250 int8_t subcmd; /* sub-command */ 251 int8_t type; /* packet or flow */ 252 union { 253 struct { /* sub-command SCHED_CLASS_CONFIG */ 254 int8_t minmax; /* minmax enable */ 255 } config; 256 struct t4_sched_class_params params; 257 uint8_t reserved[6 + 8 * 8]; 258 } u; 259 }; 260 261 enum { 262 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */ 263 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */ 264 }; 265 266 enum { 267 SCHED_CLASS_TYPE_PACKET, 268 }; 269 270 enum { 271 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */ 272 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */ 273 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */ 274 }; 275 276 enum { 277 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */ 278 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 279 }; 280 281 enum { 282 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */ 283 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */ 284 }; 285 286 enum { 287 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */ 288 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */ 289 }; 290 291 /* 292 * Support for "sched_queue" command to allow one or more NIC TX Queues to be 293 * bound to a TX Scheduling Class. 294 */ 295 struct t4_sched_queue { 296 uint8_t port; 297 int8_t queue; /* queue index; -1 => all queues */ 298 int8_t cl; /* class index; -1 => unbind */ 299 }; 300 301 #define T4_SGE_CONTEXT_SIZE 24 302 enum { 303 SGE_CONTEXT_EGRESS, 304 SGE_CONTEXT_INGRESS, 305 SGE_CONTEXT_FLM, 306 SGE_CONTEXT_CNM 307 }; 308 309 struct t4_sge_context { 310 uint32_t mem_id; 311 uint32_t cid; 312 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 313 }; 314 315 struct t4_mem_range { 316 uint32_t addr; 317 uint32_t len; 318 uint32_t *data; 319 }; 320 321 #define T4_TRACE_LEN 112 322 struct t4_trace_params { 323 uint32_t data[T4_TRACE_LEN / 4]; 324 uint32_t mask[T4_TRACE_LEN / 4]; 325 uint16_t snap_len; 326 uint16_t min_len; 327 uint8_t skip_ofst; 328 uint8_t skip_len; 329 uint8_t invert; 330 uint8_t port; 331 }; 332 333 struct t4_tracer { 334 uint8_t idx; 335 uint8_t enabled; 336 uint8_t valid; 337 struct t4_trace_params tp; 338 }; 339 340 struct t4_cudbg_dump { 341 uint8_t wr_flash; 342 uint8_t bitmap[16]; 343 uint32_t len; 344 uint8_t *data; 345 }; 346 347 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 348 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 349 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 350 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 351 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 352 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 353 #define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 354 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 355 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 356 struct t4_sge_context) 357 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 358 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 359 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 360 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 361 #define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \ 362 struct t4_sched_params) 363 #define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \ 364 struct t4_sched_queue) 365 #define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 366 #define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 367 #define CHELSIO_T4_LOAD_CFG _IOW('f', T4_LOAD_CFG, struct t4_data) 368 #define CHELSIO_T4_LOAD_BOOT _IOW('f', T4_LOAD_BOOT, struct t4_bootrom) 369 #define CHELSIO_T4_LOAD_BOOTCFG _IOW('f', T4_LOAD_BOOTCFG, struct t4_data) 370 #define CHELSIO_T4_CUDBG_DUMP _IOWR('f', T4_CUDBG_DUMP, struct t4_cudbg_dump) 371 #endif 372