1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_IOCTL_H__ 34 #define __T4_IOCTL_H__ 35 36 #include <sys/types.h> 37 #include <net/ethernet.h> 38 #include <net/bpf.h> 39 40 /* 41 * Ioctl commands specific to this driver. 42 */ 43 enum { 44 T4_GETREG = 0x40, /* read register */ 45 T4_SETREG, /* write register */ 46 T4_REGDUMP, /* dump of all registers */ 47 T4_GET_FILTER_MODE, /* get global filter mode */ 48 T4_SET_FILTER_MODE, /* set global filter mode */ 49 T4_GET_FILTER, /* get information about a filter */ 50 T4_SET_FILTER, /* program a filter */ 51 T4_DEL_FILTER, /* delete a filter */ 52 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 53 T4_LOAD_FW, /* flash firmware */ 54 T4_GET_MEM, /* read memory */ 55 T4_GET_I2C, /* read from i2c addressible device */ 56 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 57 T4_SET_OFLD_POLICY, /* Set offload policy */ 58 T4_SET_SCHED_CLASS, /* set sched class */ 59 T4_SET_SCHED_QUEUE, /* set queue class */ 60 T4_GET_TRACER, /* get information about a tracer */ 61 T4_SET_TRACER, /* program a tracer */ 62 T4_LOAD_CFG, /* copy a config file to card's flash */ 63 T4_LOAD_BOOT, /* flash boot rom */ 64 T4_LOAD_BOOTCFG, /* flash bootcfg */ 65 T4_CUDBG_DUMP, /* debug dump of chip state */ 66 T4_SET_FILTER_MASK, /* set filter mask (hashfilter mode) */ 67 T4_HOLD_CLIP_ADDR, /* add ref on an IP in the CLIP */ 68 T4_RELEASE_CLIP_ADDR, /* remove ref from an IP in the CLIP */ 69 }; 70 71 struct t4_reg { 72 uint32_t addr; 73 uint32_t size; 74 uint64_t val; 75 }; 76 77 #define T4_REGDUMP_SIZE (160 * 1024) 78 #define T5_REGDUMP_SIZE (332 * 1024) 79 struct t4_regdump { 80 uint32_t version; 81 uint32_t len; /* bytes */ 82 uint32_t *data; 83 }; 84 85 struct t4_data { 86 uint32_t len; 87 uint8_t *data; 88 }; 89 90 struct t4_bootrom { 91 uint32_t pf_offset; 92 uint32_t pfidx_addr; 93 uint32_t len; 94 uint8_t *data; 95 }; 96 97 struct t4_i2c_data { 98 uint8_t port_id; 99 uint8_t dev_addr; 100 uint8_t offset; 101 uint8_t len; 102 uint8_t data[8]; 103 }; 104 105 /* 106 * A hardware filter is some valid combination of these. 107 */ 108 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 109 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 110 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 111 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 112 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 113 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 114 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 115 #define T4_FILTER_PORT 0x80 /* Physical ingress port */ 116 #define T4_FILTER_VNIC 0x100 /* See the IC_* bits towards the end */ 117 #define T4_FILTER_VLAN 0x200 /* VLAN ID */ 118 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 119 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 120 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 121 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 122 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 123 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 124 /* 125 * T4_FILTER_VNIC's real meaning depends on the ingress config. 126 */ 127 #define T4_FILTER_IC_OVLAN 0 /* outer VLAN */ 128 #define T4_FILTER_IC_VNIC 0x80000000 /* VNIC id (PF/VF) */ 129 #define T4_FILTER_IC_ENCAP 0x40000000 130 131 /* Filter action */ 132 enum { 133 FILTER_PASS = 0, /* default */ 134 FILTER_DROP, 135 FILTER_SWITCH 136 }; 137 138 /* 802.1q manipulation on FILTER_SWITCH */ 139 enum { 140 VLAN_NOCHANGE = 0, /* default */ 141 VLAN_REMOVE, 142 VLAN_INSERT, 143 VLAN_REWRITE 144 }; 145 146 /* MPS match type */ 147 enum { 148 UCAST_EXACT = 0, /* exact unicast match */ 149 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 150 MCAST_EXACT = 2, /* exact multicast match */ 151 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 152 PROMISC = 4, /* no match but port is promiscuous */ 153 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 154 BCAST = 6, /* broadcast packet */ 155 }; 156 157 /* Rx steering */ 158 enum { 159 DST_MODE_QUEUE, /* queue is directly specified by filter */ 160 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 161 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 162 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 163 RSS subtable */ 164 }; 165 166 enum { 167 NAT_MODE_NONE = 0, /* No NAT performed */ 168 NAT_MODE_DIP, /* NAT on Dst IP */ 169 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 170 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 171 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 172 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 173 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 174 NAT_MODE_ALL /* NAT on entire 4-tuple */ 175 }; 176 177 struct t4_filter_tuple { 178 /* 179 * These are always available. 180 */ 181 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 182 uint8_t dip[16]; /* destination IP address (IPv4 in [3:0]) */ 183 uint16_t sport; /* source port */ 184 uint16_t dport; /* destination port */ 185 186 /* 187 * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP 188 * is used to select the global mode and all filters are limited to the 189 * set of fields allowed by the global mode. 190 */ 191 uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */ 192 uint16_t vlan; /* VLAN tag */ 193 uint16_t ethtype; /* Ethernet type */ 194 uint8_t tos; /* TOS/Traffic Type */ 195 uint8_t proto; /* protocol type */ 196 uint32_t fcoe:1; /* FCoE packet */ 197 uint32_t iport:3; /* ingress port */ 198 uint32_t matchtype:3; /* MPS match type */ 199 uint32_t frag:1; /* fragmentation extension header */ 200 uint32_t macidx:9; /* exact match MAC index */ 201 uint32_t vlan_vld:1; /* VLAN valid */ 202 uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */ 203 uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */ 204 }; 205 206 struct t4_filter_specification { 207 uint32_t hitcnts:1; /* count filter hits in TCB */ 208 uint32_t prio:1; /* filter has priority over active/server */ 209 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 210 uint32_t hash:1; /* 0 => LE TCAM, 1 => Hash */ 211 uint32_t action:2; /* drop, pass, switch */ 212 uint32_t rpttid:1; /* report TID in RSS hash field */ 213 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 214 uint32_t iq:10; /* ingress queue */ 215 uint32_t maskhash:1; /* dirsteer=0: steer to an RSS sub-region */ 216 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 217 /* 1 => TCB contains IQ ID */ 218 219 /* 220 * Switch proxy/rewrite fields. An ingress packet which matches a 221 * filter with "switch" set will be looped back out as an egress 222 * packet -- potentially with some Ethernet header rewriting. 223 */ 224 uint32_t eport:2; /* egress port to switch packet out */ 225 uint32_t newdmac:1; /* rewrite destination MAC address */ 226 uint32_t newsmac:1; /* rewrite source MAC address */ 227 uint32_t swapmac:1; /* swap SMAC/DMAC for loopback packet */ 228 uint32_t newvlan:2; /* rewrite VLAN Tag */ 229 uint32_t nat_mode:3; /* NAT operation mode */ 230 uint32_t nat_flag_chk:1;/* check TCP flags before NAT'ing */ 231 uint32_t nat_seq_chk; /* sequence value to use for NAT check*/ 232 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 233 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 234 uint16_t vlan; /* VLAN Tag to insert */ 235 236 uint8_t nat_dip[16]; /* destination IP to use after NAT'ing */ 237 uint8_t nat_sip[16]; /* source IP to use after NAT'ing */ 238 uint16_t nat_dport; /* destination port to use after NAT'ing */ 239 uint16_t nat_sport; /* source port to use after NAT'ing */ 240 241 /* 242 * Filter rule value/mask pairs. 243 */ 244 struct t4_filter_tuple val; 245 struct t4_filter_tuple mask; 246 }; 247 248 struct t4_filter { 249 uint32_t idx; 250 uint16_t l2tidx; 251 uint16_t smtidx; 252 uint64_t hits; 253 struct t4_filter_specification fs; 254 }; 255 256 /* Tx Scheduling Class parameters */ 257 struct t4_sched_class_params { 258 int8_t level; /* scheduler hierarchy level */ 259 int8_t mode; /* per-class or per-flow */ 260 int8_t rateunit; /* bit or packet rate */ 261 int8_t ratemode; /* %port relative or kbps absolute */ 262 int8_t channel; /* scheduler channel [0..N] */ 263 int8_t cl; /* scheduler class [0..N] */ 264 int32_t minrate; /* minimum rate */ 265 int32_t maxrate; /* maximum rate */ 266 int16_t weight; /* percent weight */ 267 int16_t pktsize; /* average packet size */ 268 }; 269 270 /* 271 * Support for "sched-class" command to allow a TX Scheduling Class to be 272 * programmed with various parameters. 273 */ 274 struct t4_sched_params { 275 int8_t subcmd; /* sub-command */ 276 int8_t type; /* packet or flow */ 277 union { 278 struct { /* sub-command SCHED_CLASS_CONFIG */ 279 int8_t minmax; /* minmax enable */ 280 } config; 281 struct t4_sched_class_params params; 282 uint8_t reserved[6 + 8 * 8]; 283 } u; 284 }; 285 286 enum { 287 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */ 288 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */ 289 }; 290 291 enum { 292 SCHED_CLASS_TYPE_PACKET, 293 }; 294 295 enum { 296 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */ 297 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */ 298 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */ 299 }; 300 301 enum { 302 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */ 303 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 304 }; 305 306 enum { 307 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */ 308 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */ 309 }; 310 311 enum { 312 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */ 313 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */ 314 }; 315 316 /* 317 * Support for "sched_queue" command to allow one or more NIC TX Queues to be 318 * bound to a TX Scheduling Class. 319 */ 320 struct t4_sched_queue { 321 uint8_t port; 322 int8_t queue; /* queue index; -1 => all queues */ 323 int8_t cl; /* class index; -1 => unbind */ 324 }; 325 326 #define T4_SGE_CONTEXT_SIZE 24 327 enum { 328 SGE_CONTEXT_EGRESS, 329 SGE_CONTEXT_INGRESS, 330 SGE_CONTEXT_FLM, 331 SGE_CONTEXT_CNM 332 }; 333 334 struct t4_sge_context { 335 uint32_t mem_id; 336 uint32_t cid; 337 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 338 }; 339 340 struct t4_mem_range { 341 uint32_t addr; 342 uint32_t len; 343 uint32_t *data; 344 }; 345 346 #define T4_TRACE_LEN 112 347 struct t4_trace_params { 348 uint32_t data[T4_TRACE_LEN / 4]; 349 uint32_t mask[T4_TRACE_LEN / 4]; 350 uint16_t snap_len; 351 uint16_t min_len; 352 uint8_t skip_ofst; 353 uint8_t skip_len; 354 uint8_t invert; 355 uint8_t port; 356 }; 357 358 struct t4_tracer { 359 uint8_t idx; 360 uint8_t enabled; 361 uint8_t valid; 362 struct t4_trace_params tp; 363 }; 364 365 struct t4_cudbg_dump { 366 uint8_t wr_flash; 367 uint8_t bitmap[16]; 368 uint32_t len; 369 uint8_t *data; 370 }; 371 372 enum { 373 OPEN_TYPE_LISTEN = 'L', 374 OPEN_TYPE_ACTIVE = 'A', 375 OPEN_TYPE_PASSIVE = 'P', 376 OPEN_TYPE_DONTCARE = 'D', 377 }; 378 379 enum { 380 QUEUE_RANDOM = -1, 381 QUEUE_ROUNDROBIN = -2, 382 }; 383 384 struct offload_settings { 385 int8_t offload; 386 int8_t rx_coalesce; 387 int8_t cong_algo; 388 int8_t sched_class; 389 int8_t tstamp; 390 int8_t sack; 391 int8_t nagle; 392 int8_t ecn; 393 int8_t ddp; 394 int8_t tls; 395 int16_t txq; 396 int16_t rxq; 397 int16_t mss; 398 }; 399 400 struct offload_rule { 401 char open_type; 402 struct offload_settings settings; 403 struct bpf_program bpf_prog; /* compiled program/filter */ 404 }; 405 406 /* 407 * An offload policy consists of a set of rules matched in sequence. The 408 * settings of the first rule that matches are applied to that connection. 409 */ 410 struct t4_offload_policy { 411 uint32_t nrules; 412 struct offload_rule *rule; 413 }; 414 415 /* Address/mask entry in the CLIP. FW_CLIP2_CMD is aware of the mask. */ 416 struct t4_clip_addr { 417 uint8_t addr[16]; 418 uint8_t mask[16]; 419 }; 420 421 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 422 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 423 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 424 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 425 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 426 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 427 #define CHELSIO_T4_SET_FILTER _IOWR('f', T4_SET_FILTER, struct t4_filter) 428 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 429 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 430 struct t4_sge_context) 431 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 432 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 433 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 434 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 435 #define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \ 436 struct t4_sched_params) 437 #define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \ 438 struct t4_sched_queue) 439 #define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 440 #define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 441 #define CHELSIO_T4_LOAD_CFG _IOW('f', T4_LOAD_CFG, struct t4_data) 442 #define CHELSIO_T4_LOAD_BOOT _IOW('f', T4_LOAD_BOOT, struct t4_bootrom) 443 #define CHELSIO_T4_LOAD_BOOTCFG _IOW('f', T4_LOAD_BOOTCFG, struct t4_data) 444 #define CHELSIO_T4_CUDBG_DUMP _IOWR('f', T4_CUDBG_DUMP, struct t4_cudbg_dump) 445 #define CHELSIO_T4_SET_OFLD_POLICY _IOW('f', T4_SET_OFLD_POLICY, struct t4_offload_policy) 446 #define CHELSIO_T4_SET_FILTER_MASK _IOW('f', T4_SET_FILTER_MASK, uint32_t) 447 #define CHELSIO_T4_HOLD_CLIP_ADDR _IOW('f', T4_HOLD_CLIP_ADDR, struct t4_clip_addr) 448 #define CHELSIO_T4_RELEASE_CLIP_ADDR _IOW('f', T4_RELEASE_CLIP_ADDR, struct t4_clip_addr) 449 #endif 450