1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_IOCTL_H__ 32 #define __T4_IOCTL_H__ 33 34 #include <sys/types.h> 35 #include <net/ethernet.h> 36 37 /* 38 * Ioctl commands specific to this driver. 39 */ 40 enum { 41 T4_GETREG = 0x40, /* read register */ 42 T4_SETREG, /* write register */ 43 T4_REGDUMP, /* dump of all registers */ 44 T4_GET_FILTER_MODE, /* get global filter mode */ 45 T4_SET_FILTER_MODE, /* set global filter mode */ 46 T4_GET_FILTER, /* get information about a filter */ 47 T4_SET_FILTER, /* program a filter */ 48 T4_DEL_FILTER, /* delete a filter */ 49 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 50 }; 51 52 struct t4_reg { 53 uint32_t addr; 54 uint32_t size; 55 uint64_t val; 56 }; 57 58 #define T4_REGDUMP_SIZE (160 * 1024) 59 struct t4_regdump { 60 uint32_t version; 61 uint32_t len; /* bytes */ 62 uint32_t *data; 63 }; 64 65 /* 66 * A hardware filter is some valid combination of these. 67 */ 68 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 69 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 70 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 71 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 72 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 73 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 74 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 75 #define T4_FILTER_PORT 0x80 /* Physical ingress port */ 76 #define T4_FILTER_OVLAN 0x100 /* Outer VLAN ID */ 77 #define T4_FILTER_IVLAN 0x200 /* Inner VLAN ID */ 78 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 79 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 80 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 81 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 82 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 83 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 84 85 /* Filter action */ 86 enum { 87 FILTER_PASS = 0, /* default */ 88 FILTER_DROP, 89 FILTER_SWITCH 90 }; 91 92 /* 802.1q manipulation on FILTER_SWITCH */ 93 enum { 94 VLAN_NOCHANGE = 0, /* default */ 95 VLAN_REMOVE, 96 VLAN_INSERT, 97 VLAN_REWRITE 98 }; 99 100 /* MPS match type */ 101 enum { 102 UCAST_EXACT = 0, /* exact unicast match */ 103 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 104 MCAST_EXACT = 2, /* exact multicast match */ 105 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 106 PROMISC = 4, /* no match but port is promiscuous */ 107 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 108 BCAST = 6, /* broadcast packet */ 109 }; 110 111 /* Rx steering */ 112 enum { 113 DST_MODE_QUEUE, /* queue is directly specified by filter */ 114 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 115 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 116 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 117 RSS subtable */ 118 }; 119 120 struct t4_filter_tuple { 121 /* 122 * These are always available. 123 */ 124 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 125 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 126 uint16_t sport; /* source port */ 127 uint16_t dport; /* destination port */ 128 129 /* 130 * A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP 131 * is used to select the global mode and all filters are limited to the 132 * set of fields allowed by the global mode. 133 */ 134 uint16_t ovlan; /* outer VLAN */ 135 uint16_t ivlan; /* inner VLAN */ 136 uint16_t ethtype; /* Ethernet type */ 137 uint8_t tos; /* TOS/Traffic Type */ 138 uint8_t proto; /* protocol type */ 139 uint32_t fcoe:1; /* FCoE packet */ 140 uint32_t iport:3; /* ingress port */ 141 uint32_t matchtype:3; /* MPS match type */ 142 uint32_t frag:1; /* fragmentation extension header */ 143 uint32_t macidx:9; /* exact match MAC index */ 144 uint32_t ivlan_vld:1; /* inner VLAN valid */ 145 uint32_t ovlan_vld:1; /* outer VLAN valid */ 146 }; 147 148 struct t4_filter_specification { 149 uint32_t hitcnts:1; /* count filter hits in TCB */ 150 uint32_t prio:1; /* filter has priority over active/server */ 151 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 152 uint32_t action:2; /* drop, pass, switch */ 153 uint32_t rpttid:1; /* report TID in RSS hash field */ 154 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 155 uint32_t iq:10; /* ingress queue */ 156 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 157 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 158 /* 1 => TCB contains IQ ID */ 159 160 /* 161 * Switch proxy/rewrite fields. An ingress packet which matches a 162 * filter with "switch" set will be looped back out as an egress 163 * packet -- potentially with some Ethernet header rewriting. 164 */ 165 uint32_t eport:2; /* egress port to switch packet out */ 166 uint32_t newdmac:1; /* rewrite destination MAC address */ 167 uint32_t newsmac:1; /* rewrite source MAC address */ 168 uint32_t newvlan:2; /* rewrite VLAN Tag */ 169 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 170 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 171 uint16_t vlan; /* VLAN Tag to insert */ 172 173 /* 174 * Filter rule value/mask pairs. 175 */ 176 struct t4_filter_tuple val; 177 struct t4_filter_tuple mask; 178 }; 179 180 struct t4_filter { 181 uint32_t idx; 182 uint16_t l2tidx; 183 uint16_t smtidx; 184 uint64_t hits; 185 struct t4_filter_specification fs; 186 }; 187 188 #define T4_SGE_CONTEXT_SIZE 24 189 enum { 190 SGE_CONTEXT_EGRESS, 191 SGE_CONTEXT_INGRESS, 192 SGE_CONTEXT_FLM, 193 SGE_CONTEXT_CNM 194 }; 195 196 struct t4_sge_context { 197 uint32_t mem_id; 198 uint32_t cid; 199 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 200 }; 201 202 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 203 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 204 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 205 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 206 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 207 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 208 #define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 209 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 210 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 211 struct t4_sge_context) 212 #endif 213