1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_IOCTL_H__ 34 #define __T4_IOCTL_H__ 35 36 #include <sys/types.h> 37 #include <net/ethernet.h> 38 #include <net/bpf.h> 39 40 /* 41 * Ioctl commands specific to this driver. 42 */ 43 enum { 44 T4_GETREG = 0x40, /* read register */ 45 T4_SETREG, /* write register */ 46 T4_REGDUMP, /* dump of all registers */ 47 T4_GET_FILTER_MODE, /* get global filter mode */ 48 T4_SET_FILTER_MODE, /* set global filter mode */ 49 T4_GET_FILTER, /* get information about a filter */ 50 T4_SET_FILTER, /* program a filter */ 51 T4_DEL_FILTER, /* delete a filter */ 52 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 53 T4_LOAD_FW, /* flash firmware */ 54 T4_GET_MEM, /* read memory */ 55 T4_GET_I2C, /* read from i2c addressible device */ 56 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 57 T4_SET_OFLD_POLICY, /* Set offload policy */ 58 T4_SET_SCHED_CLASS, /* set sched class */ 59 T4_SET_SCHED_QUEUE, /* set queue class */ 60 T4_GET_TRACER, /* get information about a tracer */ 61 T4_SET_TRACER, /* program a tracer */ 62 T4_LOAD_CFG, /* copy a config file to card's flash */ 63 T4_LOAD_BOOT, /* flash boot rom */ 64 T4_LOAD_BOOTCFG, /* flash bootcfg */ 65 T4_CUDBG_DUMP, /* debug dump of chip state */ 66 }; 67 68 struct t4_reg { 69 uint32_t addr; 70 uint32_t size; 71 uint64_t val; 72 }; 73 74 #define T4_REGDUMP_SIZE (160 * 1024) 75 #define T5_REGDUMP_SIZE (332 * 1024) 76 struct t4_regdump { 77 uint32_t version; 78 uint32_t len; /* bytes */ 79 uint32_t *data; 80 }; 81 82 struct t4_data { 83 uint32_t len; 84 uint8_t *data; 85 }; 86 87 struct t4_bootrom { 88 uint32_t pf_offset; 89 uint32_t pfidx_addr; 90 uint32_t len; 91 uint8_t *data; 92 }; 93 94 struct t4_i2c_data { 95 uint8_t port_id; 96 uint8_t dev_addr; 97 uint8_t offset; 98 uint8_t len; 99 uint8_t data[8]; 100 }; 101 102 /* 103 * A hardware filter is some valid combination of these. 104 */ 105 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 106 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 107 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 108 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 109 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 110 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 111 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 112 #define T4_FILTER_PORT 0x80 /* Physical ingress port */ 113 #define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 114 #define T4_FILTER_VLAN 0x200 /* VLAN ID */ 115 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 116 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 117 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 118 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 119 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 120 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 121 122 #define T4_FILTER_IC_VNIC 0x80000000 /* TP Ingress Config's F_VNIC 123 bit. It indicates whether 124 T4_FILTER_VNIC bit means VNIC 125 id (PF/VF) or outer VLAN. 126 0 = oVLAN, 1 = VNIC */ 127 128 /* Filter action */ 129 enum { 130 FILTER_PASS = 0, /* default */ 131 FILTER_DROP, 132 FILTER_SWITCH 133 }; 134 135 /* 802.1q manipulation on FILTER_SWITCH */ 136 enum { 137 VLAN_NOCHANGE = 0, /* default */ 138 VLAN_REMOVE, 139 VLAN_INSERT, 140 VLAN_REWRITE 141 }; 142 143 /* MPS match type */ 144 enum { 145 UCAST_EXACT = 0, /* exact unicast match */ 146 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 147 MCAST_EXACT = 2, /* exact multicast match */ 148 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 149 PROMISC = 4, /* no match but port is promiscuous */ 150 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 151 BCAST = 6, /* broadcast packet */ 152 }; 153 154 /* Rx steering */ 155 enum { 156 DST_MODE_QUEUE, /* queue is directly specified by filter */ 157 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 158 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 159 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 160 RSS subtable */ 161 }; 162 163 struct t4_filter_tuple { 164 /* 165 * These are always available. 166 */ 167 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 168 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 169 uint16_t sport; /* source port */ 170 uint16_t dport; /* destination port */ 171 172 /* 173 * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP 174 * is used to select the global mode and all filters are limited to the 175 * set of fields allowed by the global mode. 176 */ 177 uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */ 178 uint16_t vlan; /* VLAN tag */ 179 uint16_t ethtype; /* Ethernet type */ 180 uint8_t tos; /* TOS/Traffic Type */ 181 uint8_t proto; /* protocol type */ 182 uint32_t fcoe:1; /* FCoE packet */ 183 uint32_t iport:3; /* ingress port */ 184 uint32_t matchtype:3; /* MPS match type */ 185 uint32_t frag:1; /* fragmentation extension header */ 186 uint32_t macidx:9; /* exact match MAC index */ 187 uint32_t vlan_vld:1; /* VLAN valid */ 188 uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */ 189 uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */ 190 }; 191 192 struct t4_filter_specification { 193 uint32_t hitcnts:1; /* count filter hits in TCB */ 194 uint32_t prio:1; /* filter has priority over active/server */ 195 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 196 uint32_t action:2; /* drop, pass, switch */ 197 uint32_t rpttid:1; /* report TID in RSS hash field */ 198 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 199 uint32_t iq:10; /* ingress queue */ 200 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 201 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 202 /* 1 => TCB contains IQ ID */ 203 204 /* 205 * Switch proxy/rewrite fields. An ingress packet which matches a 206 * filter with "switch" set will be looped back out as an egress 207 * packet -- potentially with some Ethernet header rewriting. 208 */ 209 uint32_t eport:2; /* egress port to switch packet out */ 210 uint32_t newdmac:1; /* rewrite destination MAC address */ 211 uint32_t newsmac:1; /* rewrite source MAC address */ 212 uint32_t newvlan:2; /* rewrite VLAN Tag */ 213 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 214 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 215 uint16_t vlan; /* VLAN Tag to insert */ 216 217 /* 218 * Filter rule value/mask pairs. 219 */ 220 struct t4_filter_tuple val; 221 struct t4_filter_tuple mask; 222 }; 223 224 struct t4_filter { 225 uint32_t idx; 226 uint16_t l2tidx; 227 uint16_t smtidx; 228 uint64_t hits; 229 struct t4_filter_specification fs; 230 }; 231 232 /* Tx Scheduling Class parameters */ 233 struct t4_sched_class_params { 234 int8_t level; /* scheduler hierarchy level */ 235 int8_t mode; /* per-class or per-flow */ 236 int8_t rateunit; /* bit or packet rate */ 237 int8_t ratemode; /* %port relative or kbps absolute */ 238 int8_t channel; /* scheduler channel [0..N] */ 239 int8_t cl; /* scheduler class [0..N] */ 240 int32_t minrate; /* minimum rate */ 241 int32_t maxrate; /* maximum rate */ 242 int16_t weight; /* percent weight */ 243 int16_t pktsize; /* average packet size */ 244 }; 245 246 /* 247 * Support for "sched-class" command to allow a TX Scheduling Class to be 248 * programmed with various parameters. 249 */ 250 struct t4_sched_params { 251 int8_t subcmd; /* sub-command */ 252 int8_t type; /* packet or flow */ 253 union { 254 struct { /* sub-command SCHED_CLASS_CONFIG */ 255 int8_t minmax; /* minmax enable */ 256 } config; 257 struct t4_sched_class_params params; 258 uint8_t reserved[6 + 8 * 8]; 259 } u; 260 }; 261 262 enum { 263 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */ 264 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */ 265 }; 266 267 enum { 268 SCHED_CLASS_TYPE_PACKET, 269 }; 270 271 enum { 272 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */ 273 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */ 274 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */ 275 }; 276 277 enum { 278 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */ 279 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 280 }; 281 282 enum { 283 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */ 284 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */ 285 }; 286 287 enum { 288 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */ 289 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */ 290 }; 291 292 /* 293 * Support for "sched_queue" command to allow one or more NIC TX Queues to be 294 * bound to a TX Scheduling Class. 295 */ 296 struct t4_sched_queue { 297 uint8_t port; 298 int8_t queue; /* queue index; -1 => all queues */ 299 int8_t cl; /* class index; -1 => unbind */ 300 }; 301 302 #define T4_SGE_CONTEXT_SIZE 24 303 enum { 304 SGE_CONTEXT_EGRESS, 305 SGE_CONTEXT_INGRESS, 306 SGE_CONTEXT_FLM, 307 SGE_CONTEXT_CNM 308 }; 309 310 struct t4_sge_context { 311 uint32_t mem_id; 312 uint32_t cid; 313 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 314 }; 315 316 struct t4_mem_range { 317 uint32_t addr; 318 uint32_t len; 319 uint32_t *data; 320 }; 321 322 #define T4_TRACE_LEN 112 323 struct t4_trace_params { 324 uint32_t data[T4_TRACE_LEN / 4]; 325 uint32_t mask[T4_TRACE_LEN / 4]; 326 uint16_t snap_len; 327 uint16_t min_len; 328 uint8_t skip_ofst; 329 uint8_t skip_len; 330 uint8_t invert; 331 uint8_t port; 332 }; 333 334 struct t4_tracer { 335 uint8_t idx; 336 uint8_t enabled; 337 uint8_t valid; 338 struct t4_trace_params tp; 339 }; 340 341 struct t4_cudbg_dump { 342 uint8_t wr_flash; 343 uint8_t bitmap[16]; 344 uint32_t len; 345 uint8_t *data; 346 }; 347 348 enum { 349 OPEN_TYPE_LISTEN = 'L', 350 OPEN_TYPE_ACTIVE = 'A', 351 OPEN_TYPE_PASSIVE = 'P', 352 OPEN_TYPE_DONTCARE = 'D', 353 }; 354 355 struct offload_settings { 356 int8_t offload; 357 int8_t rx_coalesce; 358 int8_t cong_algo; 359 int8_t sched_class; 360 int8_t tstamp; 361 int8_t sack; 362 int8_t nagle; 363 int8_t ecn; 364 int8_t ddp; 365 int8_t tls; 366 int16_t txq; 367 int16_t rxq; 368 int16_t mss; 369 }; 370 371 struct offload_rule { 372 char open_type; 373 struct offload_settings settings; 374 struct bpf_program bpf_prog; /* compiled program/filter */ 375 }; 376 377 /* 378 * An offload policy consists of a set of rules matched in sequence. The 379 * settings of the first rule that matches are applied to that connection. 380 */ 381 struct t4_offload_policy { 382 uint32_t nrules; 383 struct offload_rule *rule; 384 }; 385 386 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 387 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 388 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 389 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 390 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 391 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 392 #define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 393 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 394 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 395 struct t4_sge_context) 396 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 397 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 398 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 399 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 400 #define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \ 401 struct t4_sched_params) 402 #define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \ 403 struct t4_sched_queue) 404 #define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 405 #define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 406 #define CHELSIO_T4_LOAD_CFG _IOW('f', T4_LOAD_CFG, struct t4_data) 407 #define CHELSIO_T4_LOAD_BOOT _IOW('f', T4_LOAD_BOOT, struct t4_bootrom) 408 #define CHELSIO_T4_LOAD_BOOTCFG _IOW('f', T4_LOAD_BOOTCFG, struct t4_data) 409 #define CHELSIO_T4_CUDBG_DUMP _IOWR('f', T4_CUDBG_DUMP, struct t4_cudbg_dump) 410 #define CHELSIO_T4_SET_OFLD_POLICY _IOW('f', T4_SET_OFLD_POLICY, struct t4_offload_policy) 411 #endif 412