1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_IOCTL_H__ 32 #define __T4_IOCTL_H__ 33 34 #include <sys/types.h> 35 #include <net/ethernet.h> 36 37 /* 38 * Ioctl commands specific to this driver. 39 */ 40 enum { 41 T4_GETREG = 0x40, /* read register */ 42 T4_SETREG, /* write register */ 43 T4_REGDUMP, /* dump of all registers */ 44 T4_GET_FILTER_MODE, /* get global filter mode */ 45 T4_SET_FILTER_MODE, /* set global filter mode */ 46 T4_GET_FILTER, /* get information about a filter */ 47 T4_SET_FILTER, /* program a filter */ 48 T4_DEL_FILTER, /* delete a filter */ 49 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 50 T4_LOAD_FW, /* flash firmware */ 51 T4_GET_MEM, /* read memory */ 52 T4_GET_I2C, /* read from i2c addressible device */ 53 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 54 }; 55 56 struct t4_reg { 57 uint32_t addr; 58 uint32_t size; 59 uint64_t val; 60 }; 61 62 #define T4_REGDUMP_SIZE (160 * 1024) 63 struct t4_regdump { 64 uint32_t version; 65 uint32_t len; /* bytes */ 66 uint32_t *data; 67 }; 68 69 struct t4_data { 70 uint32_t len; 71 uint8_t *data; 72 }; 73 74 struct t4_i2c_data { 75 uint8_t port_id; 76 uint8_t dev_addr; 77 uint8_t offset; 78 uint8_t len; 79 uint8_t data[8]; 80 }; 81 82 /* 83 * A hardware filter is some valid combination of these. 84 */ 85 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 86 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 87 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 88 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 89 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 90 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 91 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 92 #define T4_FILTER_PORT 0x80 /* Physical ingress port */ 93 #define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 94 #define T4_FILTER_VLAN 0x200 /* VLAN ID */ 95 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 96 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 97 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 98 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 99 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 100 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 101 102 /* Filter action */ 103 enum { 104 FILTER_PASS = 0, /* default */ 105 FILTER_DROP, 106 FILTER_SWITCH 107 }; 108 109 /* 802.1q manipulation on FILTER_SWITCH */ 110 enum { 111 VLAN_NOCHANGE = 0, /* default */ 112 VLAN_REMOVE, 113 VLAN_INSERT, 114 VLAN_REWRITE 115 }; 116 117 /* MPS match type */ 118 enum { 119 UCAST_EXACT = 0, /* exact unicast match */ 120 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 121 MCAST_EXACT = 2, /* exact multicast match */ 122 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 123 PROMISC = 4, /* no match but port is promiscuous */ 124 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 125 BCAST = 6, /* broadcast packet */ 126 }; 127 128 /* Rx steering */ 129 enum { 130 DST_MODE_QUEUE, /* queue is directly specified by filter */ 131 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 132 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 133 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 134 RSS subtable */ 135 }; 136 137 struct t4_filter_tuple { 138 /* 139 * These are always available. 140 */ 141 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 142 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 143 uint16_t sport; /* source port */ 144 uint16_t dport; /* destination port */ 145 146 /* 147 * A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP 148 * is used to select the global mode and all filters are limited to the 149 * set of fields allowed by the global mode. 150 */ 151 uint16_t vnic; /* VNIC id or outer VLAN tag */ 152 uint16_t vlan; /* VLAN tag */ 153 uint16_t ethtype; /* Ethernet type */ 154 uint8_t tos; /* TOS/Traffic Type */ 155 uint8_t proto; /* protocol type */ 156 uint32_t fcoe:1; /* FCoE packet */ 157 uint32_t iport:3; /* ingress port */ 158 uint32_t matchtype:3; /* MPS match type */ 159 uint32_t frag:1; /* fragmentation extension header */ 160 uint32_t macidx:9; /* exact match MAC index */ 161 uint32_t vlan_vld:1; /* VLAN valid */ 162 uint32_t vnic_vld:1; /* VNIC id/outer VLAN tag valid */ 163 }; 164 165 struct t4_filter_specification { 166 uint32_t hitcnts:1; /* count filter hits in TCB */ 167 uint32_t prio:1; /* filter has priority over active/server */ 168 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 169 uint32_t action:2; /* drop, pass, switch */ 170 uint32_t rpttid:1; /* report TID in RSS hash field */ 171 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 172 uint32_t iq:10; /* ingress queue */ 173 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 174 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 175 /* 1 => TCB contains IQ ID */ 176 177 /* 178 * Switch proxy/rewrite fields. An ingress packet which matches a 179 * filter with "switch" set will be looped back out as an egress 180 * packet -- potentially with some Ethernet header rewriting. 181 */ 182 uint32_t eport:2; /* egress port to switch packet out */ 183 uint32_t newdmac:1; /* rewrite destination MAC address */ 184 uint32_t newsmac:1; /* rewrite source MAC address */ 185 uint32_t newvlan:2; /* rewrite VLAN Tag */ 186 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 187 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 188 uint16_t vlan; /* VLAN Tag to insert */ 189 190 /* 191 * Filter rule value/mask pairs. 192 */ 193 struct t4_filter_tuple val; 194 struct t4_filter_tuple mask; 195 }; 196 197 struct t4_filter { 198 uint32_t idx; 199 uint16_t l2tidx; 200 uint16_t smtidx; 201 uint64_t hits; 202 struct t4_filter_specification fs; 203 }; 204 205 #define T4_SGE_CONTEXT_SIZE 24 206 enum { 207 SGE_CONTEXT_EGRESS, 208 SGE_CONTEXT_INGRESS, 209 SGE_CONTEXT_FLM, 210 SGE_CONTEXT_CNM 211 }; 212 213 struct t4_sge_context { 214 uint32_t mem_id; 215 uint32_t cid; 216 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 217 }; 218 219 struct t4_mem_range { 220 uint32_t addr; 221 uint32_t len; 222 uint32_t *data; 223 }; 224 225 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 226 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 227 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 228 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 229 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 230 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 231 #define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 232 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 233 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 234 struct t4_sge_context) 235 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 236 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 237 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 238 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 239 #endif 240