1 /* 2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 * 31 * $FreeBSD$ 32 */ 33 #ifndef __T4_H__ 34 #define __T4_H__ 35 36 #include "common/t4_regs_values.h" 37 #include "common/t4_regs.h" 38 /* 39 * Fixme: Adding missing defines 40 */ 41 #define SGE_PF_KDOORBELL 0x0 42 #define QID_MASK 0xffff8000U 43 #define QID_SHIFT 15 44 #define QID(x) ((x) << QID_SHIFT) 45 #define DBPRIO 0x00004000U 46 #define PIDX_MASK 0x00003fffU 47 #define PIDX_SHIFT 0 48 #define PIDX(x) ((x) << PIDX_SHIFT) 49 50 #define SGE_PF_GTS 0x4 51 #define INGRESSQID_MASK 0xffff0000U 52 #define INGRESSQID_SHIFT 16 53 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 54 #define TIMERREG_MASK 0x0000e000U 55 #define TIMERREG_SHIFT 13 56 #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 57 #define SEINTARM_MASK 0x00001000U 58 #define SEINTARM_SHIFT 12 59 #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 60 #define CIDXINC_MASK 0x00000fffU 61 #define CIDXINC_SHIFT 0 62 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 63 64 #define T4_MAX_NUM_PD 65536 65 #define T4_MAX_MR_SIZE (~0ULL) 66 #define T4_PAGESIZE_MASK 0xffffffff000 /* 4KB-8TB */ 67 #define T4_STAG_UNSET 0xffffffff 68 #define T4_FW_MAJ 0 69 #define A_PCIE_MA_SYNC 0x30b4 70 71 struct t4_status_page { 72 __be32 rsvd1; /* flit 0 - hw owns */ 73 __be16 rsvd2; 74 __be16 qid; 75 __be16 cidx; 76 __be16 pidx; 77 u8 qp_err; /* flit 1 - sw owns */ 78 u8 db_off; 79 u8 pad; 80 u16 host_wq_pidx; 81 u16 host_cidx; 82 u16 host_pidx; 83 }; 84 85 #define T4_EQ_ENTRY_SIZE 64 86 87 #define T4_SQ_NUM_SLOTS 5 88 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 89 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 90 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 91 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 92 sizeof(struct fw_ri_immd))) 93 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ 94 sizeof(struct fw_ri_rdma_write_wr) - \ 95 sizeof(struct fw_ri_immd))) 96 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ 97 sizeof(struct fw_ri_rdma_write_wr) - \ 98 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 99 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 100 sizeof(struct fw_ri_immd)) & ~31UL) 101 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 102 #define T4_MAX_FR_DSGL 1024 103 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64)) 104 105 static inline int t4_max_fr_depth(int use_dsgl) 106 { 107 return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH; 108 } 109 110 #define T4_RQ_NUM_SLOTS 2 111 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) 112 #define T4_MAX_RECV_SGE 4 113 114 union t4_wr { 115 struct fw_ri_res_wr res; 116 struct fw_ri_wr ri; 117 struct fw_ri_rdma_write_wr write; 118 struct fw_ri_send_wr send; 119 struct fw_ri_rdma_read_wr read; 120 struct fw_ri_bind_mw_wr bind; 121 struct fw_ri_fr_nsmr_wr fr; 122 struct fw_ri_fr_nsmr_tpte_wr fr_tpte; 123 struct fw_ri_inv_lstag_wr inv; 124 struct t4_status_page status; 125 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; 126 }; 127 128 union t4_recv_wr { 129 struct fw_ri_recv_wr recv; 130 struct t4_status_page status; 131 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; 132 }; 133 134 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, 135 enum fw_wr_opcodes opcode, u8 flags, u8 len16) 136 { 137 wqe->send.opcode = (u8)opcode; 138 wqe->send.flags = flags; 139 wqe->send.wrid = wrid; 140 wqe->send.r1[0] = 0; 141 wqe->send.r1[1] = 0; 142 wqe->send.r1[2] = 0; 143 wqe->send.len16 = len16; 144 } 145 146 /* CQE/AE status codes */ 147 #define T4_ERR_SUCCESS 0x0 148 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */ 149 /* STAG is offlimt, being 0, */ 150 /* or STAG_key mismatch */ 151 #define T4_ERR_PDID 0x2 /* PDID mismatch */ 152 #define T4_ERR_QPID 0x3 /* QPID mismatch */ 153 #define T4_ERR_ACCESS 0x4 /* Invalid access right */ 154 #define T4_ERR_WRAP 0x5 /* Wrap error */ 155 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */ 156 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ 157 /* shared memory region */ 158 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ 159 /* shared memory region */ 160 #define T4_ERR_ECC 0x9 /* ECC error detected */ 161 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ 162 /* reading PSTAG for a MW */ 163 /* Invalidate */ 164 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ 165 /* software error */ 166 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ 167 #define T4_ERR_CRC 0x10 /* CRC error */ 168 #define T4_ERR_MARKER 0x11 /* Marker error */ 169 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ 170 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ 171 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ 172 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ 173 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ 174 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ 175 #define T4_ERR_MSN 0x18 /* MSN error */ 176 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ 177 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ 178 /* or READ_REQ */ 179 #define T4_ERR_MSN_GAP 0x1B 180 #define T4_ERR_MSN_RANGE 0x1C 181 #define T4_ERR_IRD_OVERFLOW 0x1D 182 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ 183 /* software error */ 184 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ 185 /* mismatch) */ 186 /* 187 * CQE defs 188 */ 189 struct t4_cqe { 190 __be32 header; 191 __be32 len; 192 union { 193 struct { 194 __be32 stag; 195 __be32 msn; 196 } rcqe; 197 struct { 198 u32 stag; 199 u16 nada2; 200 u16 cidx; 201 } scqe; 202 struct { 203 __be32 wrid_hi; 204 __be32 wrid_low; 205 } gen; 206 u64 drain_cookie; 207 } u; 208 __be64 reserved; 209 __be64 bits_type_ts; 210 }; 211 212 /* macros for flit 0 of the cqe */ 213 214 #define S_CQE_QPID 12 215 #define M_CQE_QPID 0xFFFFF 216 #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID) 217 #define V_CQE_QPID(x) ((x)<<S_CQE_QPID) 218 219 #define S_CQE_SWCQE 11 220 #define M_CQE_SWCQE 0x1 221 #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE) 222 #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE) 223 224 #define S_CQE_STATUS 5 225 #define M_CQE_STATUS 0x1F 226 #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS) 227 #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS) 228 229 #define S_CQE_TYPE 4 230 #define M_CQE_TYPE 0x1 231 #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE) 232 #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE) 233 234 #define S_CQE_OPCODE 0 235 #define M_CQE_OPCODE 0xF 236 #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE) 237 #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE) 238 239 #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header))) 240 #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header))) 241 #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header))) 242 #define SQ_TYPE(x) (CQE_TYPE((x))) 243 #define RQ_TYPE(x) (!CQE_TYPE((x))) 244 #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header))) 245 #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header))) 246 247 #define CQE_SEND_OPCODE(x)(\ 248 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ 249 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ 250 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ 251 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) 252 253 #define CQE_LEN(x) (be32_to_cpu((x)->len)) 254 255 /* used for RQ completion processing */ 256 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) 257 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) 258 259 /* used for SQ completion processing */ 260 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) 261 #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag)) 262 263 /* generic accessor macros */ 264 #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi) 265 #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low) 266 #define CQE_DRAIN_COOKIE(x) (x)->u.drain_cookie; 267 268 /* macros for flit 3 of the cqe */ 269 #define S_CQE_GENBIT 63 270 #define M_CQE_GENBIT 0x1 271 #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT) 272 #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT) 273 274 #define S_CQE_OVFBIT 62 275 #define M_CQE_OVFBIT 0x1 276 #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT) 277 278 #define S_CQE_IQTYPE 60 279 #define M_CQE_IQTYPE 0x3 280 #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE) 281 282 #define M_CQE_TS 0x0fffffffffffffffULL 283 #define G_CQE_TS(x) ((x) & M_CQE_TS) 284 285 #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts))) 286 #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts))) 287 #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts))) 288 289 struct t4_swsqe { 290 u64 wr_id; 291 struct t4_cqe cqe; 292 int read_len; 293 int opcode; 294 int complete; 295 int signaled; 296 u16 idx; 297 int flushed; 298 struct timespec host_ts; 299 u64 sge_ts; 300 }; 301 302 static inline pgprot_t t4_pgprot_wc(pgprot_t prot) 303 { 304 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 305 return pgprot_writecombine(prot); 306 #else 307 return pgprot_noncached(prot); 308 #endif 309 } 310 311 enum { 312 T4_SQ_ONCHIP = (1<<0), 313 }; 314 315 struct t4_sq { 316 union t4_wr *queue; 317 bus_addr_t dma_addr; 318 DEFINE_DMA_UNMAP_ADDR(mapping); 319 unsigned long phys_addr; 320 struct t4_swsqe *sw_sq; 321 struct t4_swsqe *oldest_read; 322 void __iomem *bar2_va; 323 u64 bar2_pa; 324 size_t memsize; 325 u32 bar2_qid; 326 u32 qid; 327 u16 in_use; 328 u16 size; 329 u16 cidx; 330 u16 pidx; 331 u16 wq_pidx; 332 u16 wq_pidx_inc; 333 u16 flags; 334 short flush_cidx; 335 }; 336 337 struct t4_swrqe { 338 u64 wr_id; 339 }; 340 341 struct t4_rq { 342 union t4_recv_wr *queue; 343 bus_addr_t dma_addr; 344 DEFINE_DMA_UNMAP_ADDR(mapping); 345 unsigned long phys_addr; 346 struct t4_swrqe *sw_rq; 347 void __iomem *bar2_va; 348 u64 bar2_pa; 349 size_t memsize; 350 u32 bar2_qid; 351 u32 qid; 352 u32 msn; 353 u32 rqt_hwaddr; 354 u16 rqt_size; 355 u16 in_use; 356 u16 size; 357 u16 cidx; 358 u16 pidx; 359 u16 wq_pidx; 360 u16 wq_pidx_inc; 361 }; 362 363 struct t4_wq { 364 struct t4_sq sq; 365 struct t4_rq rq; 366 struct c4iw_rdev *rdev; 367 int flushed; 368 }; 369 370 static inline int t4_rqes_posted(struct t4_wq *wq) 371 { 372 return wq->rq.in_use; 373 } 374 375 static inline int t4_rq_empty(struct t4_wq *wq) 376 { 377 return wq->rq.in_use == 0; 378 } 379 380 static inline int t4_rq_full(struct t4_wq *wq) 381 { 382 return wq->rq.in_use == (wq->rq.size - 1); 383 } 384 385 static inline u32 t4_rq_avail(struct t4_wq *wq) 386 { 387 return wq->rq.size - 1 - wq->rq.in_use; 388 } 389 390 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) 391 { 392 wq->rq.in_use++; 393 if (++wq->rq.pidx == wq->rq.size) 394 wq->rq.pidx = 0; 395 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 396 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) 397 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; 398 } 399 400 static inline void t4_rq_consume(struct t4_wq *wq) 401 { 402 wq->rq.in_use--; 403 wq->rq.msn++; 404 if (++wq->rq.cidx == wq->rq.size) 405 wq->rq.cidx = 0; 406 } 407 408 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) 409 { 410 return wq->rq.queue[wq->rq.size].status.host_wq_pidx; 411 } 412 413 static inline u16 t4_rq_wq_size(struct t4_wq *wq) 414 { 415 return wq->rq.size * T4_RQ_NUM_SLOTS; 416 } 417 418 static inline int t4_sq_onchip(struct t4_sq *sq) 419 { 420 return sq->flags & T4_SQ_ONCHIP; 421 } 422 423 static inline int t4_sq_empty(struct t4_wq *wq) 424 { 425 return wq->sq.in_use == 0; 426 } 427 428 static inline int t4_sq_full(struct t4_wq *wq) 429 { 430 return wq->sq.in_use == (wq->sq.size - 1); 431 } 432 433 static inline u32 t4_sq_avail(struct t4_wq *wq) 434 { 435 return wq->sq.size - 1 - wq->sq.in_use; 436 } 437 438 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) 439 { 440 wq->sq.in_use++; 441 if (++wq->sq.pidx == wq->sq.size) 442 wq->sq.pidx = 0; 443 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 444 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) 445 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; 446 } 447 448 static inline void t4_sq_consume(struct t4_wq *wq) 449 { 450 BUG_ON(wq->sq.in_use < 1); 451 if (wq->sq.cidx == wq->sq.flush_cidx) 452 wq->sq.flush_cidx = -1; 453 wq->sq.in_use--; 454 if (++wq->sq.cidx == wq->sq.size) 455 wq->sq.cidx = 0; 456 } 457 458 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) 459 { 460 return wq->sq.queue[wq->sq.size].status.host_wq_pidx; 461 } 462 463 static inline u16 t4_sq_wq_size(struct t4_wq *wq) 464 { 465 return wq->sq.size * T4_SQ_NUM_SLOTS; 466 } 467 468 /* This function copies 64 byte coalesced work request to memory 469 * mapped BAR2 space. For coalesced WRs, the SGE fetches data 470 * from the FIFO instead of from Host. 471 */ 472 static inline void pio_copy(u64 __iomem *dst, u64 *src) 473 { 474 int count = 8; 475 476 while (count) { 477 writeq(*src, dst); 478 src++; 479 dst++; 480 count--; 481 } 482 } 483 484 static inline void 485 t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe, u8 wc) 486 { 487 488 /* Flush host queue memory writes. */ 489 wmb(); 490 if (wc && inc == 1 && wq->sq.bar2_qid == 0 && wqe) { 491 CTR2(KTR_IW_CXGBE, "%s: WC wq->sq.pidx = %d\n", 492 __func__, wq->sq.pidx); 493 pio_copy((u64 __iomem *) 494 ((u64)wq->sq.bar2_va + SGE_UDB_WCDOORBELL), 495 (u64 *)wqe); 496 } else { 497 CTR2(KTR_IW_CXGBE, "%s: DB wq->sq.pidx = %d\n", 498 __func__, wq->sq.pidx); 499 writel(V_PIDX_T5(inc) | V_QID(wq->sq.bar2_qid), 500 (void __iomem *)((u64)wq->sq.bar2_va + 501 SGE_UDB_KDOORBELL)); 502 } 503 504 /* Flush user doorbell area writes. */ 505 wmb(); 506 return; 507 } 508 509 static inline void 510 t4_ring_rq_db(struct t4_wq *wq, u16 inc, union t4_recv_wr *wqe, u8 wc) 511 { 512 513 /* Flush host queue memory writes. */ 514 wmb(); 515 if (wc && inc == 1 && wq->rq.bar2_qid == 0 && wqe) { 516 CTR2(KTR_IW_CXGBE, "%s: WC wq->rq.pidx = %d\n", 517 __func__, wq->rq.pidx); 518 pio_copy((u64 __iomem *)((u64)wq->rq.bar2_va + 519 SGE_UDB_WCDOORBELL), (u64 *)wqe); 520 } else { 521 CTR2(KTR_IW_CXGBE, "%s: DB wq->rq.pidx = %d\n", 522 __func__, wq->rq.pidx); 523 writel(V_PIDX_T5(inc) | V_QID(wq->rq.bar2_qid), 524 (void __iomem *)((u64)wq->rq.bar2_va + 525 SGE_UDB_KDOORBELL)); 526 } 527 528 /* Flush user doorbell area writes. */ 529 wmb(); 530 return; 531 } 532 533 static inline int t4_wq_in_error(struct t4_wq *wq) 534 { 535 return wq->rq.queue[wq->rq.size].status.qp_err; 536 } 537 538 static inline void t4_set_wq_in_error(struct t4_wq *wq) 539 { 540 wq->rq.queue[wq->rq.size].status.qp_err = 1; 541 } 542 543 enum t4_cq_flags { 544 CQ_ARMED = 1, 545 }; 546 547 struct t4_cq { 548 struct t4_cqe *queue; 549 bus_addr_t dma_addr; 550 DEFINE_DMA_UNMAP_ADDR(mapping); 551 struct t4_cqe *sw_queue; 552 void __iomem *bar2_va; 553 u64 bar2_pa; 554 u32 bar2_qid; 555 struct c4iw_rdev *rdev; 556 size_t memsize; 557 __be64 bits_type_ts; 558 u32 cqid; 559 u32 qid_mask; 560 int vector; 561 u16 size; /* including status page */ 562 u16 cidx; 563 u16 sw_pidx; 564 u16 sw_cidx; 565 u16 sw_in_use; 566 u16 cidx_inc; 567 u8 gen; 568 u8 error; 569 unsigned long flags; 570 }; 571 572 static inline void write_gts(struct t4_cq *cq, u32 val) 573 { 574 writel(val | V_INGRESSQID(cq->bar2_qid), 575 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 576 } 577 578 static inline int t4_clear_cq_armed(struct t4_cq *cq) 579 { 580 return test_and_clear_bit(CQ_ARMED, &cq->flags); 581 } 582 583 static inline int t4_arm_cq(struct t4_cq *cq, int se) 584 { 585 u32 val; 586 587 set_bit(CQ_ARMED, &cq->flags); 588 while (cq->cidx_inc > CIDXINC_MASK) { 589 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7); 590 writel(val | V_INGRESSQID(cq->bar2_qid), 591 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 592 cq->cidx_inc -= CIDXINC_MASK; 593 } 594 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6); 595 writel(val | V_INGRESSQID(cq->bar2_qid), 596 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 597 cq->cidx_inc = 0; 598 return 0; 599 } 600 601 static inline void t4_swcq_produce(struct t4_cq *cq) 602 { 603 cq->sw_in_use++; 604 if (cq->sw_in_use == cq->size) { 605 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u\n", 606 __func__, cq->cqid); 607 cq->error = 1; 608 BUG_ON(1); 609 } 610 if (++cq->sw_pidx == cq->size) 611 cq->sw_pidx = 0; 612 } 613 614 static inline void t4_swcq_consume(struct t4_cq *cq) 615 { 616 BUG_ON(cq->sw_in_use < 1); 617 cq->sw_in_use--; 618 if (++cq->sw_cidx == cq->size) 619 cq->sw_cidx = 0; 620 } 621 622 static inline void t4_hwcq_consume(struct t4_cq *cq) 623 { 624 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; 625 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == M_CIDXINC) { 626 u32 val; 627 628 val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7); 629 write_gts(cq, val); 630 cq->cidx_inc = 0; 631 } 632 if (++cq->cidx == cq->size) { 633 cq->cidx = 0; 634 cq->gen ^= 1; 635 } 636 } 637 638 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) 639 { 640 return (CQE_GENBIT(cqe) == cq->gen); 641 } 642 643 static inline int t4_cq_notempty(struct t4_cq *cq) 644 { 645 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]); 646 } 647 648 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 649 { 650 int ret; 651 u16 prev_cidx; 652 653 if (cq->cidx == 0) 654 prev_cidx = cq->size - 1; 655 else 656 prev_cidx = cq->cidx - 1; 657 658 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { 659 ret = -EOVERFLOW; 660 cq->error = 1; 661 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); 662 BUG_ON(1); 663 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 664 665 /* Ensure CQE is flushed to memory */ 666 rmb(); 667 *cqe = &cq->queue[cq->cidx]; 668 ret = 0; 669 } else 670 ret = -ENODATA; 671 return ret; 672 } 673 674 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 675 { 676 if (cq->sw_in_use == cq->size) { 677 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u\n", 678 __func__, cq->cqid); 679 cq->error = 1; 680 BUG_ON(1); 681 return NULL; 682 } 683 if (cq->sw_in_use) 684 return &cq->sw_queue[cq->sw_cidx]; 685 return NULL; 686 } 687 688 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 689 { 690 int ret = 0; 691 692 if (cq->error) 693 ret = -ENODATA; 694 else if (cq->sw_in_use) 695 *cqe = &cq->sw_queue[cq->sw_cidx]; 696 else 697 ret = t4_next_hw_cqe(cq, cqe); 698 return ret; 699 } 700 701 static inline int t4_cq_in_error(struct t4_cq *cq) 702 { 703 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err; 704 } 705 706 static inline void t4_set_cq_in_error(struct t4_cq *cq) 707 { 708 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1; 709 } 710 struct t4_dev_status_page { 711 u8 db_off; 712 u8 wc_supported; 713 u16 pad2; 714 u32 pad3; 715 u64 qp_start; 716 u64 qp_size; 717 u64 cq_start; 718 u64 cq_size; 719 }; 720 #endif 721