1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #ifndef __T4_H__ 34 #define __T4_H__ 35 36 #include "common/t4_regs_values.h" 37 #include "common/t4_regs.h" 38 /* 39 * Fixme: Adding missing defines 40 */ 41 #define SGE_PF_KDOORBELL 0x0 42 #define QID_MASK 0xffff8000U 43 #define QID_SHIFT 15 44 #define QID(x) ((x) << QID_SHIFT) 45 #define DBPRIO 0x00004000U 46 #define PIDX_MASK 0x00003fffU 47 #define PIDX_SHIFT 0 48 #define PIDX(x) ((x) << PIDX_SHIFT) 49 50 #define SGE_PF_GTS 0x4 51 #define INGRESSQID_MASK 0xffff0000U 52 #define INGRESSQID_SHIFT 16 53 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 54 #define TIMERREG_MASK 0x0000e000U 55 #define TIMERREG_SHIFT 13 56 #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 57 #define SEINTARM_MASK 0x00001000U 58 #define SEINTARM_SHIFT 12 59 #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 60 #define CIDXINC_MASK 0x00000fffU 61 #define CIDXINC_SHIFT 0 62 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 63 64 #define T4_MAX_NUM_PD 65536 65 #define T4_MAX_MR_SIZE (~0ULL) 66 #define T4_PAGESIZE_MASK 0xffffffff000 /* 4KB-8TB */ 67 #define T4_STAG_UNSET 0xffffffff 68 #define T4_FW_MAJ 0 69 #define A_PCIE_MA_SYNC 0x30b4 70 71 struct t4_status_page { 72 __be32 rsvd1; /* flit 0 - hw owns */ 73 __be16 rsvd2; 74 __be16 qid; 75 __be16 cidx; 76 __be16 pidx; 77 u8 qp_err; /* flit 1 - sw owns */ 78 u8 db_off; 79 u8 pad; 80 u16 host_wq_pidx; 81 u16 host_cidx; 82 u16 host_pidx; 83 }; 84 85 #define T4_EQ_ENTRY_SIZE 64 86 87 #define T4_SQ_NUM_SLOTS 5 88 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 89 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 90 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 91 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 92 sizeof(struct fw_ri_immd))) 93 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ 94 sizeof(struct fw_ri_rdma_write_wr) - \ 95 sizeof(struct fw_ri_immd))) 96 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ 97 sizeof(struct fw_ri_rdma_write_wr) - \ 98 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 99 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 100 sizeof(struct fw_ri_immd)) & ~31UL) 101 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 102 #define T4_MAX_FR_DSGL 1024 103 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64)) 104 #define T4_MAX_FR_FW_DSGL 4096 105 #define T4_MAX_FR_FW_DSGL_DEPTH (T4_MAX_FR_FW_DSGL / sizeof(u64)) 106 107 #define T4_RQ_NUM_SLOTS 2 108 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) 109 #define T4_MAX_RECV_SGE 4 110 111 union t4_wr { 112 struct fw_ri_res_wr res; 113 struct fw_ri_wr ri; 114 struct fw_ri_rdma_write_wr write; 115 struct fw_ri_send_wr send; 116 struct fw_ri_rdma_read_wr read; 117 struct fw_ri_bind_mw_wr bind; 118 struct fw_ri_fr_nsmr_wr fr; 119 struct fw_ri_fr_nsmr_tpte_wr fr_tpte; 120 struct fw_ri_inv_lstag_wr inv; 121 struct t4_status_page status; 122 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; 123 }; 124 125 union t4_recv_wr { 126 struct fw_ri_recv_wr recv; 127 struct t4_status_page status; 128 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; 129 }; 130 131 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, 132 enum fw_wr_opcodes opcode, u8 flags, u8 len16) 133 { 134 wqe->send.opcode = (u8)opcode; 135 wqe->send.flags = flags; 136 wqe->send.wrid = wrid; 137 wqe->send.r1[0] = 0; 138 wqe->send.r1[1] = 0; 139 wqe->send.r1[2] = 0; 140 wqe->send.len16 = len16; 141 } 142 143 /* CQE/AE status codes */ 144 #define T4_ERR_SUCCESS 0x0 145 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */ 146 /* STAG is offlimt, being 0, */ 147 /* or STAG_key mismatch */ 148 #define T4_ERR_PDID 0x2 /* PDID mismatch */ 149 #define T4_ERR_QPID 0x3 /* QPID mismatch */ 150 #define T4_ERR_ACCESS 0x4 /* Invalid access right */ 151 #define T4_ERR_WRAP 0x5 /* Wrap error */ 152 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */ 153 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ 154 /* shared memory region */ 155 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ 156 /* shared memory region */ 157 #define T4_ERR_ECC 0x9 /* ECC error detected */ 158 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ 159 /* reading PSTAG for a MW */ 160 /* Invalidate */ 161 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ 162 /* software error */ 163 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ 164 #define T4_ERR_CRC 0x10 /* CRC error */ 165 #define T4_ERR_MARKER 0x11 /* Marker error */ 166 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ 167 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ 168 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ 169 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ 170 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ 171 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ 172 #define T4_ERR_MSN 0x18 /* MSN error */ 173 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ 174 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ 175 /* or READ_REQ */ 176 #define T4_ERR_MSN_GAP 0x1B 177 #define T4_ERR_MSN_RANGE 0x1C 178 #define T4_ERR_IRD_OVERFLOW 0x1D 179 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ 180 /* software error */ 181 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ 182 /* mismatch) */ 183 /* 184 * CQE defs 185 */ 186 struct t4_cqe { 187 __be32 header; 188 __be32 len; 189 union { 190 struct { 191 __be32 stag; 192 __be32 msn; 193 } rcqe; 194 struct { 195 u32 stag; 196 u16 nada2; 197 u16 cidx; 198 } scqe; 199 struct { 200 __be32 wrid_hi; 201 __be32 wrid_low; 202 } gen; 203 u64 drain_cookie; 204 } u; 205 __be64 reserved; 206 __be64 bits_type_ts; 207 }; 208 209 /* macros for flit 0 of the cqe */ 210 211 #define S_CQE_QPID 12 212 #define M_CQE_QPID 0xFFFFF 213 #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID) 214 #define V_CQE_QPID(x) ((x)<<S_CQE_QPID) 215 216 #define S_CQE_SWCQE 11 217 #define M_CQE_SWCQE 0x1 218 #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE) 219 #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE) 220 221 #define S_CQE_STATUS 5 222 #define M_CQE_STATUS 0x1F 223 #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS) 224 #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS) 225 226 #define S_CQE_TYPE 4 227 #define M_CQE_TYPE 0x1 228 #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE) 229 #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE) 230 231 #define S_CQE_OPCODE 0 232 #define M_CQE_OPCODE 0xF 233 #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE) 234 #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE) 235 236 #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header))) 237 #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header))) 238 #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header))) 239 #define SQ_TYPE(x) (CQE_TYPE((x))) 240 #define RQ_TYPE(x) (!CQE_TYPE((x))) 241 #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header))) 242 #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header))) 243 244 #define CQE_SEND_OPCODE(x)(\ 245 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ 246 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ 247 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ 248 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) 249 250 #define CQE_LEN(x) (be32_to_cpu((x)->len)) 251 252 /* used for RQ completion processing */ 253 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) 254 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) 255 256 /* used for SQ completion processing */ 257 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) 258 #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag)) 259 260 /* generic accessor macros */ 261 #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi) 262 #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low) 263 #define CQE_DRAIN_COOKIE(x) (x)->u.drain_cookie; 264 265 /* macros for flit 3 of the cqe */ 266 #define S_CQE_GENBIT 63 267 #define M_CQE_GENBIT 0x1 268 #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT) 269 #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT) 270 271 #define S_CQE_OVFBIT 62 272 #define M_CQE_OVFBIT 0x1 273 #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT) 274 275 #define S_CQE_IQTYPE 60 276 #define M_CQE_IQTYPE 0x3 277 #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE) 278 279 #define M_CQE_TS 0x0fffffffffffffffULL 280 #define G_CQE_TS(x) ((x) & M_CQE_TS) 281 282 #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts))) 283 #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts))) 284 #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts))) 285 286 struct t4_swsqe { 287 u64 wr_id; 288 struct t4_cqe cqe; 289 int read_len; 290 int opcode; 291 int complete; 292 int signaled; 293 u16 idx; 294 int flushed; 295 struct timespec host_ts; 296 u64 sge_ts; 297 }; 298 299 static inline pgprot_t t4_pgprot_wc(pgprot_t prot) 300 { 301 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 302 return pgprot_writecombine(prot); 303 #else 304 return pgprot_noncached(prot); 305 #endif 306 } 307 308 enum { 309 T4_SQ_ONCHIP = (1<<0), 310 }; 311 312 struct t4_sq { 313 union t4_wr *queue; 314 bus_addr_t dma_addr; 315 DEFINE_DMA_UNMAP_ADDR(mapping); 316 unsigned long phys_addr; 317 struct t4_swsqe *sw_sq; 318 struct t4_swsqe *oldest_read; 319 void __iomem *bar2_va; 320 u64 bar2_pa; 321 size_t memsize; 322 u32 bar2_qid; 323 u32 qid; 324 u16 in_use; 325 u16 size; 326 u16 cidx; 327 u16 pidx; 328 u16 wq_pidx; 329 u16 wq_pidx_inc; 330 u16 flags; 331 short flush_cidx; 332 }; 333 334 struct t4_swrqe { 335 u64 wr_id; 336 }; 337 338 struct t4_rq { 339 union t4_recv_wr *queue; 340 bus_addr_t dma_addr; 341 DEFINE_DMA_UNMAP_ADDR(mapping); 342 unsigned long phys_addr; 343 struct t4_swrqe *sw_rq; 344 void __iomem *bar2_va; 345 u64 bar2_pa; 346 size_t memsize; 347 u32 bar2_qid; 348 u32 qid; 349 u32 msn; 350 u32 rqt_hwaddr; 351 u16 rqt_size; 352 u16 in_use; 353 u16 size; 354 u16 cidx; 355 u16 pidx; 356 u16 wq_pidx; 357 u16 wq_pidx_inc; 358 }; 359 360 struct t4_wq { 361 struct t4_sq sq; 362 struct t4_rq rq; 363 struct c4iw_rdev *rdev; 364 int flushed; 365 }; 366 367 static inline int t4_rqes_posted(struct t4_wq *wq) 368 { 369 return wq->rq.in_use; 370 } 371 372 static inline int t4_rq_empty(struct t4_wq *wq) 373 { 374 return wq->rq.in_use == 0; 375 } 376 377 static inline int t4_rq_full(struct t4_wq *wq) 378 { 379 return wq->rq.in_use == (wq->rq.size - 1); 380 } 381 382 static inline u32 t4_rq_avail(struct t4_wq *wq) 383 { 384 return wq->rq.size - 1 - wq->rq.in_use; 385 } 386 387 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) 388 { 389 wq->rq.in_use++; 390 if (++wq->rq.pidx == wq->rq.size) 391 wq->rq.pidx = 0; 392 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 393 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) 394 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; 395 } 396 397 static inline void t4_rq_consume(struct t4_wq *wq) 398 { 399 wq->rq.in_use--; 400 wq->rq.msn++; 401 if (++wq->rq.cidx == wq->rq.size) 402 wq->rq.cidx = 0; 403 } 404 405 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) 406 { 407 return wq->rq.queue[wq->rq.size].status.host_wq_pidx; 408 } 409 410 static inline u16 t4_rq_wq_size(struct t4_wq *wq) 411 { 412 return wq->rq.size * T4_RQ_NUM_SLOTS; 413 } 414 415 static inline int t4_sq_onchip(struct t4_sq *sq) 416 { 417 return sq->flags & T4_SQ_ONCHIP; 418 } 419 420 static inline int t4_sq_empty(struct t4_wq *wq) 421 { 422 return wq->sq.in_use == 0; 423 } 424 425 static inline int t4_sq_full(struct t4_wq *wq) 426 { 427 return wq->sq.in_use == (wq->sq.size - 1); 428 } 429 430 static inline u32 t4_sq_avail(struct t4_wq *wq) 431 { 432 return wq->sq.size - 1 - wq->sq.in_use; 433 } 434 435 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) 436 { 437 wq->sq.in_use++; 438 if (++wq->sq.pidx == wq->sq.size) 439 wq->sq.pidx = 0; 440 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 441 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) 442 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; 443 } 444 445 static inline void t4_sq_consume(struct t4_wq *wq) 446 { 447 BUG_ON(wq->sq.in_use < 1); 448 if (wq->sq.cidx == wq->sq.flush_cidx) 449 wq->sq.flush_cidx = -1; 450 wq->sq.in_use--; 451 if (++wq->sq.cidx == wq->sq.size) 452 wq->sq.cidx = 0; 453 } 454 455 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) 456 { 457 return wq->sq.queue[wq->sq.size].status.host_wq_pidx; 458 } 459 460 static inline u16 t4_sq_wq_size(struct t4_wq *wq) 461 { 462 return wq->sq.size * T4_SQ_NUM_SLOTS; 463 } 464 465 /* This function copies 64 byte coalesced work request to memory 466 * mapped BAR2 space. For coalesced WRs, the SGE fetches data 467 * from the FIFO instead of from Host. 468 */ 469 static inline void pio_copy(u64 __iomem *dst, u64 *src) 470 { 471 int count = 8; 472 473 while (count) { 474 writeq(*src, dst); 475 src++; 476 dst++; 477 count--; 478 } 479 } 480 481 static inline void 482 t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe, u8 wc) 483 { 484 485 /* Flush host queue memory writes. */ 486 wmb(); 487 if (wc && inc == 1 && wq->sq.bar2_qid == 0 && wqe) { 488 CTR2(KTR_IW_CXGBE, "%s: WC wq->sq.pidx = %d", 489 __func__, wq->sq.pidx); 490 pio_copy((u64 __iomem *) 491 ((u64)wq->sq.bar2_va + SGE_UDB_WCDOORBELL), 492 (u64 *)wqe); 493 } else { 494 CTR2(KTR_IW_CXGBE, "%s: DB wq->sq.pidx = %d", 495 __func__, wq->sq.pidx); 496 writel(V_PIDX_T5(inc) | V_QID(wq->sq.bar2_qid), 497 (void __iomem *)((u64)wq->sq.bar2_va + 498 SGE_UDB_KDOORBELL)); 499 } 500 501 /* Flush user doorbell area writes. */ 502 wmb(); 503 return; 504 } 505 506 static inline void 507 t4_ring_rq_db(struct t4_wq *wq, u16 inc, union t4_recv_wr *wqe, u8 wc) 508 { 509 510 /* Flush host queue memory writes. */ 511 wmb(); 512 if (wc && inc == 1 && wq->rq.bar2_qid == 0 && wqe) { 513 CTR2(KTR_IW_CXGBE, "%s: WC wq->rq.pidx = %d", 514 __func__, wq->rq.pidx); 515 pio_copy((u64 __iomem *)((u64)wq->rq.bar2_va + 516 SGE_UDB_WCDOORBELL), (u64 *)wqe); 517 } else { 518 CTR2(KTR_IW_CXGBE, "%s: DB wq->rq.pidx = %d", 519 __func__, wq->rq.pidx); 520 writel(V_PIDX_T5(inc) | V_QID(wq->rq.bar2_qid), 521 (void __iomem *)((u64)wq->rq.bar2_va + 522 SGE_UDB_KDOORBELL)); 523 } 524 525 /* Flush user doorbell area writes. */ 526 wmb(); 527 return; 528 } 529 530 static inline int t4_wq_in_error(struct t4_wq *wq) 531 { 532 return wq->rq.queue[wq->rq.size].status.qp_err; 533 } 534 535 static inline void t4_set_wq_in_error(struct t4_wq *wq) 536 { 537 wq->rq.queue[wq->rq.size].status.qp_err = 1; 538 } 539 540 enum t4_cq_flags { 541 CQ_ARMED = 1, 542 }; 543 544 struct t4_cq { 545 struct t4_cqe *queue; 546 bus_addr_t dma_addr; 547 DEFINE_DMA_UNMAP_ADDR(mapping); 548 struct t4_cqe *sw_queue; 549 void __iomem *bar2_va; 550 u64 bar2_pa; 551 u32 bar2_qid; 552 struct c4iw_rdev *rdev; 553 size_t memsize; 554 __be64 bits_type_ts; 555 u32 cqid; 556 u32 qid_mask; 557 int vector; 558 u16 size; /* including status page */ 559 u16 cidx; 560 u16 sw_pidx; 561 u16 sw_cidx; 562 u16 sw_in_use; 563 u16 cidx_inc; 564 u8 gen; 565 u8 error; 566 unsigned long flags; 567 }; 568 569 static inline void write_gts(struct t4_cq *cq, u32 val) 570 { 571 writel(val | V_INGRESSQID(cq->bar2_qid), 572 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 573 } 574 575 static inline int t4_clear_cq_armed(struct t4_cq *cq) 576 { 577 return test_and_clear_bit(CQ_ARMED, &cq->flags); 578 } 579 580 static inline int t4_arm_cq(struct t4_cq *cq, int se) 581 { 582 u32 val; 583 584 set_bit(CQ_ARMED, &cq->flags); 585 while (cq->cidx_inc > CIDXINC_MASK) { 586 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7); 587 writel(val | V_INGRESSQID(cq->bar2_qid), 588 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 589 cq->cidx_inc -= CIDXINC_MASK; 590 } 591 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6); 592 writel(val | V_INGRESSQID(cq->bar2_qid), 593 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 594 cq->cidx_inc = 0; 595 return 0; 596 } 597 598 static inline void t4_swcq_produce(struct t4_cq *cq) 599 { 600 cq->sw_in_use++; 601 if (cq->sw_in_use == cq->size) { 602 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u", 603 __func__, cq->cqid); 604 cq->error = 1; 605 BUG_ON(1); 606 } 607 if (++cq->sw_pidx == cq->size) 608 cq->sw_pidx = 0; 609 } 610 611 static inline void t4_swcq_consume(struct t4_cq *cq) 612 { 613 BUG_ON(cq->sw_in_use < 1); 614 cq->sw_in_use--; 615 if (++cq->sw_cidx == cq->size) 616 cq->sw_cidx = 0; 617 } 618 619 static inline void t4_hwcq_consume(struct t4_cq *cq) 620 { 621 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; 622 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == M_CIDXINC) { 623 u32 val; 624 625 val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7); 626 write_gts(cq, val); 627 cq->cidx_inc = 0; 628 } 629 if (++cq->cidx == cq->size) { 630 cq->cidx = 0; 631 cq->gen ^= 1; 632 } 633 } 634 635 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) 636 { 637 return (CQE_GENBIT(cqe) == cq->gen); 638 } 639 640 static inline int t4_cq_notempty(struct t4_cq *cq) 641 { 642 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]); 643 } 644 645 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 646 { 647 int ret; 648 u16 prev_cidx; 649 650 if (cq->cidx == 0) 651 prev_cidx = cq->size - 1; 652 else 653 prev_cidx = cq->cidx - 1; 654 655 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { 656 ret = -EOVERFLOW; 657 cq->error = 1; 658 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); 659 BUG_ON(1); 660 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 661 662 /* Ensure CQE is flushed to memory */ 663 rmb(); 664 *cqe = &cq->queue[cq->cidx]; 665 ret = 0; 666 } else 667 ret = -ENODATA; 668 return ret; 669 } 670 671 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 672 { 673 if (cq->sw_in_use == cq->size) { 674 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u", 675 __func__, cq->cqid); 676 cq->error = 1; 677 BUG_ON(1); 678 return NULL; 679 } 680 if (cq->sw_in_use) 681 return &cq->sw_queue[cq->sw_cidx]; 682 return NULL; 683 } 684 685 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 686 { 687 int ret = 0; 688 689 if (cq->error) 690 ret = -ENODATA; 691 else if (cq->sw_in_use) 692 *cqe = &cq->sw_queue[cq->sw_cidx]; 693 else 694 ret = t4_next_hw_cqe(cq, cqe); 695 return ret; 696 } 697 698 static inline int t4_cq_in_error(struct t4_cq *cq) 699 { 700 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err; 701 } 702 703 static inline void t4_set_cq_in_error(struct t4_cq *cq) 704 { 705 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1; 706 } 707 struct t4_dev_status_page { 708 u8 db_off; 709 u8 wc_supported; 710 u16 pad2; 711 u32 pad3; 712 u64 qp_start; 713 u64 qp_size; 714 u64 cq_start; 715 u64 cq_size; 716 }; 717 #endif 718