1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef __T4_H__ 36 #define __T4_H__ 37 38 #include "common/t4_regs_values.h" 39 #include "common/t4_regs.h" 40 /* 41 * Fixme: Adding missing defines 42 */ 43 #define SGE_PF_KDOORBELL 0x0 44 #define QID_MASK 0xffff8000U 45 #define QID_SHIFT 15 46 #define QID(x) ((x) << QID_SHIFT) 47 #define DBPRIO 0x00004000U 48 #define PIDX_MASK 0x00003fffU 49 #define PIDX_SHIFT 0 50 #define PIDX(x) ((x) << PIDX_SHIFT) 51 52 #define SGE_PF_GTS 0x4 53 #define INGRESSQID_MASK 0xffff0000U 54 #define INGRESSQID_SHIFT 16 55 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 56 #define TIMERREG_MASK 0x0000e000U 57 #define TIMERREG_SHIFT 13 58 #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 59 #define SEINTARM_MASK 0x00001000U 60 #define SEINTARM_SHIFT 12 61 #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 62 #define CIDXINC_MASK 0x00000fffU 63 #define CIDXINC_SHIFT 0 64 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 65 66 #define T4_MAX_NUM_PD 65536 67 #define T4_MAX_MR_SIZE (~0ULL) 68 #define T4_PAGESIZE_MASK 0xffffffff000 /* 4KB-8TB */ 69 #define T4_STAG_UNSET 0xffffffff 70 #define T4_FW_MAJ 0 71 #define A_PCIE_MA_SYNC 0x30b4 72 73 struct t4_status_page { 74 __be32 rsvd1; /* flit 0 - hw owns */ 75 __be16 rsvd2; 76 __be16 qid; 77 __be16 cidx; 78 __be16 pidx; 79 u8 qp_err; /* flit 1 - sw owns */ 80 u8 db_off; 81 u8 pad; 82 u16 host_wq_pidx; 83 u16 host_cidx; 84 u16 host_pidx; 85 }; 86 87 #define T4_EQ_ENTRY_SIZE 64 88 89 #define T4_SQ_NUM_SLOTS 5 90 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 91 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 92 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 93 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 94 sizeof(struct fw_ri_immd))) 95 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ 96 sizeof(struct fw_ri_rdma_write_wr) - \ 97 sizeof(struct fw_ri_immd))) 98 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ 99 sizeof(struct fw_ri_rdma_write_wr) - \ 100 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 101 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 102 sizeof(struct fw_ri_immd)) & ~31UL) 103 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 104 #define T4_MAX_FR_DSGL 1024 105 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64)) 106 107 static inline int t4_max_fr_depth(int use_dsgl) 108 { 109 return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH; 110 } 111 112 #define T4_RQ_NUM_SLOTS 2 113 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) 114 #define T4_MAX_RECV_SGE 4 115 116 union t4_wr { 117 struct fw_ri_res_wr res; 118 struct fw_ri_wr ri; 119 struct fw_ri_rdma_write_wr write; 120 struct fw_ri_send_wr send; 121 struct fw_ri_rdma_read_wr read; 122 struct fw_ri_bind_mw_wr bind; 123 struct fw_ri_fr_nsmr_wr fr; 124 struct fw_ri_fr_nsmr_tpte_wr fr_tpte; 125 struct fw_ri_inv_lstag_wr inv; 126 struct t4_status_page status; 127 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; 128 }; 129 130 union t4_recv_wr { 131 struct fw_ri_recv_wr recv; 132 struct t4_status_page status; 133 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; 134 }; 135 136 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, 137 enum fw_wr_opcodes opcode, u8 flags, u8 len16) 138 { 139 wqe->send.opcode = (u8)opcode; 140 wqe->send.flags = flags; 141 wqe->send.wrid = wrid; 142 wqe->send.r1[0] = 0; 143 wqe->send.r1[1] = 0; 144 wqe->send.r1[2] = 0; 145 wqe->send.len16 = len16; 146 } 147 148 /* CQE/AE status codes */ 149 #define T4_ERR_SUCCESS 0x0 150 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */ 151 /* STAG is offlimt, being 0, */ 152 /* or STAG_key mismatch */ 153 #define T4_ERR_PDID 0x2 /* PDID mismatch */ 154 #define T4_ERR_QPID 0x3 /* QPID mismatch */ 155 #define T4_ERR_ACCESS 0x4 /* Invalid access right */ 156 #define T4_ERR_WRAP 0x5 /* Wrap error */ 157 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */ 158 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ 159 /* shared memory region */ 160 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ 161 /* shared memory region */ 162 #define T4_ERR_ECC 0x9 /* ECC error detected */ 163 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ 164 /* reading PSTAG for a MW */ 165 /* Invalidate */ 166 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ 167 /* software error */ 168 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ 169 #define T4_ERR_CRC 0x10 /* CRC error */ 170 #define T4_ERR_MARKER 0x11 /* Marker error */ 171 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ 172 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ 173 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ 174 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ 175 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ 176 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ 177 #define T4_ERR_MSN 0x18 /* MSN error */ 178 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ 179 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ 180 /* or READ_REQ */ 181 #define T4_ERR_MSN_GAP 0x1B 182 #define T4_ERR_MSN_RANGE 0x1C 183 #define T4_ERR_IRD_OVERFLOW 0x1D 184 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ 185 /* software error */ 186 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ 187 /* mismatch) */ 188 /* 189 * CQE defs 190 */ 191 struct t4_cqe { 192 __be32 header; 193 __be32 len; 194 union { 195 struct { 196 __be32 stag; 197 __be32 msn; 198 } rcqe; 199 struct { 200 u32 stag; 201 u16 nada2; 202 u16 cidx; 203 } scqe; 204 struct { 205 __be32 wrid_hi; 206 __be32 wrid_low; 207 } gen; 208 u64 drain_cookie; 209 } u; 210 __be64 reserved; 211 __be64 bits_type_ts; 212 }; 213 214 /* macros for flit 0 of the cqe */ 215 216 #define S_CQE_QPID 12 217 #define M_CQE_QPID 0xFFFFF 218 #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID) 219 #define V_CQE_QPID(x) ((x)<<S_CQE_QPID) 220 221 #define S_CQE_SWCQE 11 222 #define M_CQE_SWCQE 0x1 223 #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE) 224 #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE) 225 226 #define S_CQE_STATUS 5 227 #define M_CQE_STATUS 0x1F 228 #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS) 229 #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS) 230 231 #define S_CQE_TYPE 4 232 #define M_CQE_TYPE 0x1 233 #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE) 234 #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE) 235 236 #define S_CQE_OPCODE 0 237 #define M_CQE_OPCODE 0xF 238 #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE) 239 #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE) 240 241 #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header))) 242 #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header))) 243 #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header))) 244 #define SQ_TYPE(x) (CQE_TYPE((x))) 245 #define RQ_TYPE(x) (!CQE_TYPE((x))) 246 #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header))) 247 #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header))) 248 249 #define CQE_SEND_OPCODE(x)(\ 250 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ 251 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ 252 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ 253 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) 254 255 #define CQE_LEN(x) (be32_to_cpu((x)->len)) 256 257 /* used for RQ completion processing */ 258 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) 259 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) 260 261 /* used for SQ completion processing */ 262 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) 263 #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag)) 264 265 /* generic accessor macros */ 266 #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi) 267 #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low) 268 #define CQE_DRAIN_COOKIE(x) (x)->u.drain_cookie; 269 270 /* macros for flit 3 of the cqe */ 271 #define S_CQE_GENBIT 63 272 #define M_CQE_GENBIT 0x1 273 #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT) 274 #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT) 275 276 #define S_CQE_OVFBIT 62 277 #define M_CQE_OVFBIT 0x1 278 #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT) 279 280 #define S_CQE_IQTYPE 60 281 #define M_CQE_IQTYPE 0x3 282 #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE) 283 284 #define M_CQE_TS 0x0fffffffffffffffULL 285 #define G_CQE_TS(x) ((x) & M_CQE_TS) 286 287 #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts))) 288 #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts))) 289 #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts))) 290 291 struct t4_swsqe { 292 u64 wr_id; 293 struct t4_cqe cqe; 294 int read_len; 295 int opcode; 296 int complete; 297 int signaled; 298 u16 idx; 299 int flushed; 300 struct timespec host_ts; 301 u64 sge_ts; 302 }; 303 304 static inline pgprot_t t4_pgprot_wc(pgprot_t prot) 305 { 306 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 307 return pgprot_writecombine(prot); 308 #else 309 return pgprot_noncached(prot); 310 #endif 311 } 312 313 enum { 314 T4_SQ_ONCHIP = (1<<0), 315 }; 316 317 struct t4_sq { 318 union t4_wr *queue; 319 bus_addr_t dma_addr; 320 DEFINE_DMA_UNMAP_ADDR(mapping); 321 unsigned long phys_addr; 322 struct t4_swsqe *sw_sq; 323 struct t4_swsqe *oldest_read; 324 void __iomem *bar2_va; 325 u64 bar2_pa; 326 size_t memsize; 327 u32 bar2_qid; 328 u32 qid; 329 u16 in_use; 330 u16 size; 331 u16 cidx; 332 u16 pidx; 333 u16 wq_pidx; 334 u16 wq_pidx_inc; 335 u16 flags; 336 short flush_cidx; 337 }; 338 339 struct t4_swrqe { 340 u64 wr_id; 341 }; 342 343 struct t4_rq { 344 union t4_recv_wr *queue; 345 bus_addr_t dma_addr; 346 DEFINE_DMA_UNMAP_ADDR(mapping); 347 unsigned long phys_addr; 348 struct t4_swrqe *sw_rq; 349 void __iomem *bar2_va; 350 u64 bar2_pa; 351 size_t memsize; 352 u32 bar2_qid; 353 u32 qid; 354 u32 msn; 355 u32 rqt_hwaddr; 356 u16 rqt_size; 357 u16 in_use; 358 u16 size; 359 u16 cidx; 360 u16 pidx; 361 u16 wq_pidx; 362 u16 wq_pidx_inc; 363 }; 364 365 struct t4_wq { 366 struct t4_sq sq; 367 struct t4_rq rq; 368 struct c4iw_rdev *rdev; 369 int flushed; 370 }; 371 372 static inline int t4_rqes_posted(struct t4_wq *wq) 373 { 374 return wq->rq.in_use; 375 } 376 377 static inline int t4_rq_empty(struct t4_wq *wq) 378 { 379 return wq->rq.in_use == 0; 380 } 381 382 static inline int t4_rq_full(struct t4_wq *wq) 383 { 384 return wq->rq.in_use == (wq->rq.size - 1); 385 } 386 387 static inline u32 t4_rq_avail(struct t4_wq *wq) 388 { 389 return wq->rq.size - 1 - wq->rq.in_use; 390 } 391 392 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) 393 { 394 wq->rq.in_use++; 395 if (++wq->rq.pidx == wq->rq.size) 396 wq->rq.pidx = 0; 397 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 398 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) 399 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; 400 } 401 402 static inline void t4_rq_consume(struct t4_wq *wq) 403 { 404 wq->rq.in_use--; 405 wq->rq.msn++; 406 if (++wq->rq.cidx == wq->rq.size) 407 wq->rq.cidx = 0; 408 } 409 410 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) 411 { 412 return wq->rq.queue[wq->rq.size].status.host_wq_pidx; 413 } 414 415 static inline u16 t4_rq_wq_size(struct t4_wq *wq) 416 { 417 return wq->rq.size * T4_RQ_NUM_SLOTS; 418 } 419 420 static inline int t4_sq_onchip(struct t4_sq *sq) 421 { 422 return sq->flags & T4_SQ_ONCHIP; 423 } 424 425 static inline int t4_sq_empty(struct t4_wq *wq) 426 { 427 return wq->sq.in_use == 0; 428 } 429 430 static inline int t4_sq_full(struct t4_wq *wq) 431 { 432 return wq->sq.in_use == (wq->sq.size - 1); 433 } 434 435 static inline u32 t4_sq_avail(struct t4_wq *wq) 436 { 437 return wq->sq.size - 1 - wq->sq.in_use; 438 } 439 440 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) 441 { 442 wq->sq.in_use++; 443 if (++wq->sq.pidx == wq->sq.size) 444 wq->sq.pidx = 0; 445 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 446 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) 447 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; 448 } 449 450 static inline void t4_sq_consume(struct t4_wq *wq) 451 { 452 BUG_ON(wq->sq.in_use < 1); 453 if (wq->sq.cidx == wq->sq.flush_cidx) 454 wq->sq.flush_cidx = -1; 455 wq->sq.in_use--; 456 if (++wq->sq.cidx == wq->sq.size) 457 wq->sq.cidx = 0; 458 } 459 460 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) 461 { 462 return wq->sq.queue[wq->sq.size].status.host_wq_pidx; 463 } 464 465 static inline u16 t4_sq_wq_size(struct t4_wq *wq) 466 { 467 return wq->sq.size * T4_SQ_NUM_SLOTS; 468 } 469 470 /* This function copies 64 byte coalesced work request to memory 471 * mapped BAR2 space. For coalesced WRs, the SGE fetches data 472 * from the FIFO instead of from Host. 473 */ 474 static inline void pio_copy(u64 __iomem *dst, u64 *src) 475 { 476 int count = 8; 477 478 while (count) { 479 writeq(*src, dst); 480 src++; 481 dst++; 482 count--; 483 } 484 } 485 486 static inline void 487 t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe, u8 wc) 488 { 489 490 /* Flush host queue memory writes. */ 491 wmb(); 492 if (wc && inc == 1 && wq->sq.bar2_qid == 0 && wqe) { 493 CTR2(KTR_IW_CXGBE, "%s: WC wq->sq.pidx = %d", 494 __func__, wq->sq.pidx); 495 pio_copy((u64 __iomem *) 496 ((u64)wq->sq.bar2_va + SGE_UDB_WCDOORBELL), 497 (u64 *)wqe); 498 } else { 499 CTR2(KTR_IW_CXGBE, "%s: DB wq->sq.pidx = %d", 500 __func__, wq->sq.pidx); 501 writel(V_PIDX_T5(inc) | V_QID(wq->sq.bar2_qid), 502 (void __iomem *)((u64)wq->sq.bar2_va + 503 SGE_UDB_KDOORBELL)); 504 } 505 506 /* Flush user doorbell area writes. */ 507 wmb(); 508 return; 509 } 510 511 static inline void 512 t4_ring_rq_db(struct t4_wq *wq, u16 inc, union t4_recv_wr *wqe, u8 wc) 513 { 514 515 /* Flush host queue memory writes. */ 516 wmb(); 517 if (wc && inc == 1 && wq->rq.bar2_qid == 0 && wqe) { 518 CTR2(KTR_IW_CXGBE, "%s: WC wq->rq.pidx = %d", 519 __func__, wq->rq.pidx); 520 pio_copy((u64 __iomem *)((u64)wq->rq.bar2_va + 521 SGE_UDB_WCDOORBELL), (u64 *)wqe); 522 } else { 523 CTR2(KTR_IW_CXGBE, "%s: DB wq->rq.pidx = %d", 524 __func__, wq->rq.pidx); 525 writel(V_PIDX_T5(inc) | V_QID(wq->rq.bar2_qid), 526 (void __iomem *)((u64)wq->rq.bar2_va + 527 SGE_UDB_KDOORBELL)); 528 } 529 530 /* Flush user doorbell area writes. */ 531 wmb(); 532 return; 533 } 534 535 static inline int t4_wq_in_error(struct t4_wq *wq) 536 { 537 return wq->rq.queue[wq->rq.size].status.qp_err; 538 } 539 540 static inline void t4_set_wq_in_error(struct t4_wq *wq) 541 { 542 wq->rq.queue[wq->rq.size].status.qp_err = 1; 543 } 544 545 enum t4_cq_flags { 546 CQ_ARMED = 1, 547 }; 548 549 struct t4_cq { 550 struct t4_cqe *queue; 551 bus_addr_t dma_addr; 552 DEFINE_DMA_UNMAP_ADDR(mapping); 553 struct t4_cqe *sw_queue; 554 void __iomem *bar2_va; 555 u64 bar2_pa; 556 u32 bar2_qid; 557 struct c4iw_rdev *rdev; 558 size_t memsize; 559 __be64 bits_type_ts; 560 u32 cqid; 561 u32 qid_mask; 562 int vector; 563 u16 size; /* including status page */ 564 u16 cidx; 565 u16 sw_pidx; 566 u16 sw_cidx; 567 u16 sw_in_use; 568 u16 cidx_inc; 569 u8 gen; 570 u8 error; 571 unsigned long flags; 572 }; 573 574 static inline void write_gts(struct t4_cq *cq, u32 val) 575 { 576 writel(val | V_INGRESSQID(cq->bar2_qid), 577 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 578 } 579 580 static inline int t4_clear_cq_armed(struct t4_cq *cq) 581 { 582 return test_and_clear_bit(CQ_ARMED, &cq->flags); 583 } 584 585 static inline int t4_arm_cq(struct t4_cq *cq, int se) 586 { 587 u32 val; 588 589 set_bit(CQ_ARMED, &cq->flags); 590 while (cq->cidx_inc > CIDXINC_MASK) { 591 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7); 592 writel(val | V_INGRESSQID(cq->bar2_qid), 593 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 594 cq->cidx_inc -= CIDXINC_MASK; 595 } 596 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6); 597 writel(val | V_INGRESSQID(cq->bar2_qid), 598 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 599 cq->cidx_inc = 0; 600 return 0; 601 } 602 603 static inline void t4_swcq_produce(struct t4_cq *cq) 604 { 605 cq->sw_in_use++; 606 if (cq->sw_in_use == cq->size) { 607 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u", 608 __func__, cq->cqid); 609 cq->error = 1; 610 BUG_ON(1); 611 } 612 if (++cq->sw_pidx == cq->size) 613 cq->sw_pidx = 0; 614 } 615 616 static inline void t4_swcq_consume(struct t4_cq *cq) 617 { 618 BUG_ON(cq->sw_in_use < 1); 619 cq->sw_in_use--; 620 if (++cq->sw_cidx == cq->size) 621 cq->sw_cidx = 0; 622 } 623 624 static inline void t4_hwcq_consume(struct t4_cq *cq) 625 { 626 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; 627 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == M_CIDXINC) { 628 u32 val; 629 630 val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7); 631 write_gts(cq, val); 632 cq->cidx_inc = 0; 633 } 634 if (++cq->cidx == cq->size) { 635 cq->cidx = 0; 636 cq->gen ^= 1; 637 } 638 } 639 640 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) 641 { 642 return (CQE_GENBIT(cqe) == cq->gen); 643 } 644 645 static inline int t4_cq_notempty(struct t4_cq *cq) 646 { 647 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]); 648 } 649 650 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 651 { 652 int ret; 653 u16 prev_cidx; 654 655 if (cq->cidx == 0) 656 prev_cidx = cq->size - 1; 657 else 658 prev_cidx = cq->cidx - 1; 659 660 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { 661 ret = -EOVERFLOW; 662 cq->error = 1; 663 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); 664 BUG_ON(1); 665 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 666 667 /* Ensure CQE is flushed to memory */ 668 rmb(); 669 *cqe = &cq->queue[cq->cidx]; 670 ret = 0; 671 } else 672 ret = -ENODATA; 673 return ret; 674 } 675 676 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 677 { 678 if (cq->sw_in_use == cq->size) { 679 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u", 680 __func__, cq->cqid); 681 cq->error = 1; 682 BUG_ON(1); 683 return NULL; 684 } 685 if (cq->sw_in_use) 686 return &cq->sw_queue[cq->sw_cidx]; 687 return NULL; 688 } 689 690 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 691 { 692 int ret = 0; 693 694 if (cq->error) 695 ret = -ENODATA; 696 else if (cq->sw_in_use) 697 *cqe = &cq->sw_queue[cq->sw_cidx]; 698 else 699 ret = t4_next_hw_cqe(cq, cqe); 700 return ret; 701 } 702 703 static inline int t4_cq_in_error(struct t4_cq *cq) 704 { 705 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err; 706 } 707 708 static inline void t4_set_cq_in_error(struct t4_cq *cq) 709 { 710 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1; 711 } 712 struct t4_dev_status_page { 713 u8 db_off; 714 u8 wc_supported; 715 u16 pad2; 716 u32 pad3; 717 u64 qp_start; 718 u64 qp_size; 719 u64 cq_start; 720 u64 cq_size; 721 }; 722 #endif 723