1 /* 2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 * 31 * $FreeBSD$ 32 */ 33 #ifndef __T4_H__ 34 #define __T4_H__ 35 36 /* 37 * Fixme: Adding missing defines 38 */ 39 #define SGE_PF_KDOORBELL 0x0 40 #define QID_MASK 0xffff8000U 41 #define QID_SHIFT 15 42 #define QID(x) ((x) << QID_SHIFT) 43 #define DBPRIO 0x00004000U 44 #define PIDX_MASK 0x00003fffU 45 #define PIDX_SHIFT 0 46 #define PIDX(x) ((x) << PIDX_SHIFT) 47 48 #define SGE_PF_GTS 0x4 49 #define INGRESSQID_MASK 0xffff0000U 50 #define INGRESSQID_SHIFT 16 51 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 52 #define TIMERREG_MASK 0x0000e000U 53 #define TIMERREG_SHIFT 13 54 #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 55 #define SEINTARM_MASK 0x00001000U 56 #define SEINTARM_SHIFT 12 57 #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 58 #define CIDXINC_MASK 0x00000fffU 59 #define CIDXINC_SHIFT 0 60 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 61 62 #define T4_MAX_NUM_QP (1<<16) 63 #define T4_MAX_NUM_CQ (1<<15) 64 #define T4_MAX_NUM_PD (1<<15) 65 #define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1) 66 #define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES) 67 #define T4_MAX_IQ_SIZE (65520 - 1) 68 #define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES) 69 #define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1) 70 #define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1) 71 #define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1) 72 #define T4_MAX_NUM_STAG (1<<15) 73 #define T4_MAX_MR_SIZE (~0ULL - 1) 74 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */ 75 #define T4_STAG_UNSET 0xffffffff 76 #define T4_FW_MAJ 0 77 #define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1) 78 #define A_PCIE_MA_SYNC 0x30b4 79 80 struct t4_status_page { 81 __be32 rsvd1; /* flit 0 - hw owns */ 82 __be16 rsvd2; 83 __be16 qid; 84 __be16 cidx; 85 __be16 pidx; 86 u8 qp_err; /* flit 1 - sw owns */ 87 u8 db_off; 88 u8 pad; 89 u16 host_wq_pidx; 90 u16 host_cidx; 91 u16 host_pidx; 92 }; 93 94 #define T4_EQ_ENTRY_SIZE 64 95 96 #define T4_SQ_NUM_SLOTS 5 97 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 98 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 99 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 100 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 101 sizeof(struct fw_ri_immd))) 102 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ 103 sizeof(struct fw_ri_rdma_write_wr) - \ 104 sizeof(struct fw_ri_immd))) 105 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ 106 sizeof(struct fw_ri_rdma_write_wr) - \ 107 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 108 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 109 sizeof(struct fw_ri_immd)) & ~31UL) 110 #define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 111 112 #define T4_RQ_NUM_SLOTS 2 113 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) 114 #define T4_MAX_RECV_SGE 4 115 116 union t4_wr { 117 struct fw_ri_res_wr res; 118 struct fw_ri_wr ri; 119 struct fw_ri_rdma_write_wr write; 120 struct fw_ri_send_wr send; 121 struct fw_ri_rdma_read_wr read; 122 struct fw_ri_bind_mw_wr bind; 123 struct fw_ri_fr_nsmr_wr fr; 124 struct fw_ri_inv_lstag_wr inv; 125 struct t4_status_page status; 126 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; 127 }; 128 129 union t4_recv_wr { 130 struct fw_ri_recv_wr recv; 131 struct t4_status_page status; 132 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; 133 }; 134 135 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, 136 enum fw_wr_opcodes opcode, u8 flags, u8 len16) 137 { 138 wqe->send.opcode = (u8)opcode; 139 wqe->send.flags = flags; 140 wqe->send.wrid = wrid; 141 wqe->send.r1[0] = 0; 142 wqe->send.r1[1] = 0; 143 wqe->send.r1[2] = 0; 144 wqe->send.len16 = len16; 145 } 146 147 /* CQE/AE status codes */ 148 #define T4_ERR_SUCCESS 0x0 149 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */ 150 /* STAG is offlimt, being 0, */ 151 /* or STAG_key mismatch */ 152 #define T4_ERR_PDID 0x2 /* PDID mismatch */ 153 #define T4_ERR_QPID 0x3 /* QPID mismatch */ 154 #define T4_ERR_ACCESS 0x4 /* Invalid access right */ 155 #define T4_ERR_WRAP 0x5 /* Wrap error */ 156 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */ 157 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ 158 /* shared memory region */ 159 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ 160 /* shared memory region */ 161 #define T4_ERR_ECC 0x9 /* ECC error detected */ 162 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ 163 /* reading PSTAG for a MW */ 164 /* Invalidate */ 165 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ 166 /* software error */ 167 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ 168 #define T4_ERR_CRC 0x10 /* CRC error */ 169 #define T4_ERR_MARKER 0x11 /* Marker error */ 170 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ 171 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ 172 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ 173 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ 174 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ 175 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ 176 #define T4_ERR_MSN 0x18 /* MSN error */ 177 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ 178 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ 179 /* or READ_REQ */ 180 #define T4_ERR_MSN_GAP 0x1B 181 #define T4_ERR_MSN_RANGE 0x1C 182 #define T4_ERR_IRD_OVERFLOW 0x1D 183 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ 184 /* software error */ 185 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ 186 /* mismatch) */ 187 /* 188 * CQE defs 189 */ 190 struct t4_cqe { 191 __be32 header; 192 __be32 len; 193 union { 194 struct { 195 __be32 stag; 196 __be32 msn; 197 } rcqe; 198 struct { 199 u32 nada1; 200 u16 nada2; 201 u16 cidx; 202 } scqe; 203 struct { 204 __be32 wrid_hi; 205 __be32 wrid_low; 206 } gen; 207 } u; 208 __be64 reserved; 209 __be64 bits_type_ts; 210 }; 211 212 /* macros for flit 0 of the cqe */ 213 214 #define S_CQE_QPID 12 215 #define M_CQE_QPID 0xFFFFF 216 #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID) 217 #define V_CQE_QPID(x) ((x)<<S_CQE_QPID) 218 219 #define S_CQE_SWCQE 11 220 #define M_CQE_SWCQE 0x1 221 #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE) 222 #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE) 223 224 #define S_CQE_STATUS 5 225 #define M_CQE_STATUS 0x1F 226 #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS) 227 #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS) 228 229 #define S_CQE_TYPE 4 230 #define M_CQE_TYPE 0x1 231 #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE) 232 #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE) 233 234 #define S_CQE_OPCODE 0 235 #define M_CQE_OPCODE 0xF 236 #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE) 237 #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE) 238 239 #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header))) 240 #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header))) 241 #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header))) 242 #define SQ_TYPE(x) (CQE_TYPE((x))) 243 #define RQ_TYPE(x) (!CQE_TYPE((x))) 244 #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header))) 245 #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header))) 246 247 #define CQE_SEND_OPCODE(x)(\ 248 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ 249 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ 250 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ 251 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) 252 253 #define CQE_LEN(x) (be32_to_cpu((x)->len)) 254 255 /* used for RQ completion processing */ 256 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) 257 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) 258 259 /* used for SQ completion processing */ 260 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) 261 262 /* generic accessor macros */ 263 #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi) 264 #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low) 265 266 /* macros for flit 3 of the cqe */ 267 #define S_CQE_GENBIT 63 268 #define M_CQE_GENBIT 0x1 269 #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT) 270 #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT) 271 272 #define S_CQE_OVFBIT 62 273 #define M_CQE_OVFBIT 0x1 274 #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT) 275 276 #define S_CQE_IQTYPE 60 277 #define M_CQE_IQTYPE 0x3 278 #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE) 279 280 #define M_CQE_TS 0x0fffffffffffffffULL 281 #define G_CQE_TS(x) ((x) & M_CQE_TS) 282 283 #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts))) 284 #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts))) 285 #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts))) 286 287 struct t4_swsqe { 288 u64 wr_id; 289 struct t4_cqe cqe; 290 int read_len; 291 int opcode; 292 int complete; 293 int signaled; 294 u16 idx; 295 }; 296 297 struct t4_sq { 298 union t4_wr *queue; 299 bus_addr_t dma_addr; 300 DECLARE_PCI_UNMAP_ADDR(mapping); 301 unsigned long phys_addr; 302 struct t4_swsqe *sw_sq; 303 struct t4_swsqe *oldest_read; 304 u64 udb; 305 size_t memsize; 306 u32 qid; 307 u16 in_use; 308 u16 size; 309 u16 cidx; 310 u16 pidx; 311 u16 wq_pidx; 312 u16 flags; 313 }; 314 315 struct t4_swrqe { 316 u64 wr_id; 317 }; 318 319 struct t4_rq { 320 union t4_recv_wr *queue; 321 bus_addr_t dma_addr; 322 DECLARE_PCI_UNMAP_ADDR(mapping); 323 struct t4_swrqe *sw_rq; 324 u64 udb; 325 size_t memsize; 326 u32 qid; 327 u32 msn; 328 u32 rqt_hwaddr; 329 u16 rqt_size; 330 u16 in_use; 331 u16 size; 332 u16 cidx; 333 u16 pidx; 334 u16 wq_pidx; 335 }; 336 337 struct t4_wq { 338 struct t4_sq sq; 339 struct t4_rq rq; 340 void __iomem *db; 341 void __iomem *gts; 342 struct c4iw_rdev *rdev; 343 }; 344 345 static inline int t4_rqes_posted(struct t4_wq *wq) 346 { 347 return wq->rq.in_use; 348 } 349 350 static inline int t4_rq_empty(struct t4_wq *wq) 351 { 352 return wq->rq.in_use == 0; 353 } 354 355 static inline int t4_rq_full(struct t4_wq *wq) 356 { 357 return wq->rq.in_use == (wq->rq.size - 1); 358 } 359 360 static inline u32 t4_rq_avail(struct t4_wq *wq) 361 { 362 return wq->rq.size - 1 - wq->rq.in_use; 363 } 364 365 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) 366 { 367 wq->rq.in_use++; 368 if (++wq->rq.pidx == wq->rq.size) 369 wq->rq.pidx = 0; 370 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 371 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) 372 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; 373 } 374 375 static inline void t4_rq_consume(struct t4_wq *wq) 376 { 377 wq->rq.in_use--; 378 wq->rq.msn++; 379 if (++wq->rq.cidx == wq->rq.size) 380 wq->rq.cidx = 0; 381 } 382 383 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) 384 { 385 return wq->rq.queue[wq->rq.size].status.host_wq_pidx; 386 } 387 388 static inline u16 t4_rq_wq_size(struct t4_wq *wq) 389 { 390 return wq->rq.size * T4_RQ_NUM_SLOTS; 391 } 392 393 static inline int t4_sq_empty(struct t4_wq *wq) 394 { 395 return wq->sq.in_use == 0; 396 } 397 398 static inline int t4_sq_full(struct t4_wq *wq) 399 { 400 return wq->sq.in_use == (wq->sq.size - 1); 401 } 402 403 static inline u32 t4_sq_avail(struct t4_wq *wq) 404 { 405 return wq->sq.size - 1 - wq->sq.in_use; 406 } 407 408 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) 409 { 410 wq->sq.in_use++; 411 if (++wq->sq.pidx == wq->sq.size) 412 wq->sq.pidx = 0; 413 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 414 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) 415 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; 416 } 417 418 static inline void t4_sq_consume(struct t4_wq *wq) 419 { 420 wq->sq.in_use--; 421 if (++wq->sq.cidx == wq->sq.size) 422 wq->sq.cidx = 0; 423 } 424 425 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) 426 { 427 return wq->sq.queue[wq->sq.size].status.host_wq_pidx; 428 } 429 430 static inline u16 t4_sq_wq_size(struct t4_wq *wq) 431 { 432 return wq->sq.size * T4_SQ_NUM_SLOTS; 433 } 434 435 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc) 436 { 437 wmb(); 438 writel(QID(wq->sq.qid) | PIDX(inc), wq->db); 439 } 440 441 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc) 442 { 443 wmb(); 444 writel(QID(wq->rq.qid) | PIDX(inc), wq->db); 445 } 446 447 static inline int t4_wq_in_error(struct t4_wq *wq) 448 { 449 return wq->rq.queue[wq->rq.size].status.qp_err; 450 } 451 452 static inline void t4_set_wq_in_error(struct t4_wq *wq) 453 { 454 wq->rq.queue[wq->rq.size].status.qp_err = 1; 455 } 456 457 static inline void t4_disable_wq_db(struct t4_wq *wq) 458 { 459 wq->rq.queue[wq->rq.size].status.db_off = 1; 460 } 461 462 static inline void t4_enable_wq_db(struct t4_wq *wq) 463 { 464 wq->rq.queue[wq->rq.size].status.db_off = 0; 465 } 466 467 static inline int t4_wq_db_enabled(struct t4_wq *wq) 468 { 469 return !wq->rq.queue[wq->rq.size].status.db_off; 470 } 471 472 struct t4_cq { 473 struct t4_cqe *queue; 474 bus_addr_t dma_addr; 475 DECLARE_PCI_UNMAP_ADDR(mapping); 476 struct t4_cqe *sw_queue; 477 void __iomem *gts; 478 struct c4iw_rdev *rdev; 479 u64 ugts; 480 size_t memsize; 481 __be64 bits_type_ts; 482 u32 cqid; 483 u16 size; /* including status page */ 484 u16 cidx; 485 u16 sw_pidx; 486 u16 sw_cidx; 487 u16 sw_in_use; 488 u16 cidx_inc; 489 u8 gen; 490 u8 error; 491 }; 492 493 static inline int t4_arm_cq(struct t4_cq *cq, int se) 494 { 495 u32 val; 496 497 while (cq->cidx_inc > CIDXINC_MASK) { 498 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) | 499 INGRESSQID(cq->cqid); 500 writel(val, cq->gts); 501 cq->cidx_inc -= CIDXINC_MASK; 502 } 503 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) | 504 INGRESSQID(cq->cqid); 505 writel(val, cq->gts); 506 cq->cidx_inc = 0; 507 return 0; 508 } 509 510 static inline void t4_swcq_produce(struct t4_cq *cq) 511 { 512 cq->sw_in_use++; 513 if (++cq->sw_pidx == cq->size) 514 cq->sw_pidx = 0; 515 } 516 517 static inline void t4_swcq_consume(struct t4_cq *cq) 518 { 519 cq->sw_in_use--; 520 if (++cq->sw_cidx == cq->size) 521 cq->sw_cidx = 0; 522 } 523 524 static inline void t4_hwcq_consume(struct t4_cq *cq) 525 { 526 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; 527 if (++cq->cidx_inc == (cq->size >> 4)) { 528 u32 val; 529 530 val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) | 531 INGRESSQID(cq->cqid); 532 writel(val, cq->gts); 533 cq->cidx_inc = 0; 534 } 535 if (++cq->cidx == cq->size) { 536 cq->cidx = 0; 537 cq->gen ^= 1; 538 } 539 } 540 541 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) 542 { 543 return (CQE_GENBIT(cqe) == cq->gen); 544 } 545 546 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 547 { 548 int ret; 549 u16 prev_cidx; 550 551 if (cq->cidx == 0) 552 prev_cidx = cq->size - 1; 553 else 554 prev_cidx = cq->cidx - 1; 555 556 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { 557 ret = -EOVERFLOW; 558 cq->error = 1; 559 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); 560 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 561 *cqe = &cq->queue[cq->cidx]; 562 ret = 0; 563 } else 564 ret = -ENODATA; 565 return ret; 566 } 567 568 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 569 { 570 if (cq->sw_in_use) 571 return &cq->sw_queue[cq->sw_cidx]; 572 return NULL; 573 } 574 575 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 576 { 577 int ret = 0; 578 579 if (cq->error) 580 ret = -ENODATA; 581 else if (cq->sw_in_use) 582 *cqe = &cq->sw_queue[cq->sw_cidx]; 583 else 584 ret = t4_next_hw_cqe(cq, cqe); 585 return ret; 586 } 587 588 static inline int t4_cq_in_error(struct t4_cq *cq) 589 { 590 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err; 591 } 592 593 static inline void t4_set_cq_in_error(struct t4_cq *cq) 594 { 595 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1; 596 } 597 #endif 598