1 /* 2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 * 31 * $FreeBSD$ 32 */ 33 #ifndef __T4_H__ 34 #define __T4_H__ 35 36 /* 37 * Fixme: Adding missing defines 38 */ 39 #define SGE_PF_KDOORBELL 0x0 40 #define QID_MASK 0xffff8000U 41 #define QID_SHIFT 15 42 #define QID(x) ((x) << QID_SHIFT) 43 #define DBPRIO 0x00004000U 44 #define PIDX_MASK 0x00003fffU 45 #define PIDX_SHIFT 0 46 #define PIDX(x) ((x) << PIDX_SHIFT) 47 48 #define SGE_PF_GTS 0x4 49 #define INGRESSQID_MASK 0xffff0000U 50 #define INGRESSQID_SHIFT 16 51 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 52 #define TIMERREG_MASK 0x0000e000U 53 #define TIMERREG_SHIFT 13 54 #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 55 #define SEINTARM_MASK 0x00001000U 56 #define SEINTARM_SHIFT 12 57 #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 58 #define CIDXINC_MASK 0x00000fffU 59 #define CIDXINC_SHIFT 0 60 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 61 62 #define T4_MAX_NUM_PD 65536 63 #define T4_MAX_EQ_SIZE 65520 64 #define T4_MAX_IQ_SIZE 65520 65 #define T4_MAX_RQ_SIZE(n) (8192 - (n) - 1) 66 #define T4_MAX_SQ_SIZE(n) (T4_MAX_EQ_SIZE - (n) - 1) 67 #define T4_MAX_QP_DEPTH(n) (T4_MAX_RQ_SIZE(n)) 68 #define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 2) 69 #define T4_MAX_MR_SIZE (~0ULL - 1) 70 #define T4_PAGESIZE_MASK 0xffffffff000 /* 4KB-8TB */ 71 #define T4_STAG_UNSET 0xffffffff 72 #define T4_FW_MAJ 0 73 #define A_PCIE_MA_SYNC 0x30b4 74 75 struct t4_status_page { 76 __be32 rsvd1; /* flit 0 - hw owns */ 77 __be16 rsvd2; 78 __be16 qid; 79 __be16 cidx; 80 __be16 pidx; 81 u8 qp_err; /* flit 1 - sw owns */ 82 u8 db_off; 83 u8 pad; 84 u16 host_wq_pidx; 85 u16 host_cidx; 86 u16 host_pidx; 87 }; 88 89 #define T4_EQ_ENTRY_SIZE 64 90 91 #define T4_SQ_NUM_SLOTS 5 92 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 93 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 94 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 95 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 96 sizeof(struct fw_ri_immd))) 97 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ 98 sizeof(struct fw_ri_rdma_write_wr) - \ 99 sizeof(struct fw_ri_immd))) 100 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ 101 sizeof(struct fw_ri_rdma_write_wr) - \ 102 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 103 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 104 sizeof(struct fw_ri_immd)) & ~31UL) 105 #define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 106 107 #define T4_RQ_NUM_SLOTS 2 108 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) 109 #define T4_MAX_RECV_SGE 4 110 111 union t4_wr { 112 struct fw_ri_res_wr res; 113 struct fw_ri_wr ri; 114 struct fw_ri_rdma_write_wr write; 115 struct fw_ri_send_wr send; 116 struct fw_ri_rdma_read_wr read; 117 struct fw_ri_bind_mw_wr bind; 118 struct fw_ri_fr_nsmr_wr fr; 119 struct fw_ri_inv_lstag_wr inv; 120 struct t4_status_page status; 121 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; 122 }; 123 124 union t4_recv_wr { 125 struct fw_ri_recv_wr recv; 126 struct t4_status_page status; 127 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; 128 }; 129 130 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, 131 enum fw_wr_opcodes opcode, u8 flags, u8 len16) 132 { 133 wqe->send.opcode = (u8)opcode; 134 wqe->send.flags = flags; 135 wqe->send.wrid = wrid; 136 wqe->send.r1[0] = 0; 137 wqe->send.r1[1] = 0; 138 wqe->send.r1[2] = 0; 139 wqe->send.len16 = len16; 140 } 141 142 /* CQE/AE status codes */ 143 #define T4_ERR_SUCCESS 0x0 144 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */ 145 /* STAG is offlimt, being 0, */ 146 /* or STAG_key mismatch */ 147 #define T4_ERR_PDID 0x2 /* PDID mismatch */ 148 #define T4_ERR_QPID 0x3 /* QPID mismatch */ 149 #define T4_ERR_ACCESS 0x4 /* Invalid access right */ 150 #define T4_ERR_WRAP 0x5 /* Wrap error */ 151 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */ 152 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ 153 /* shared memory region */ 154 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ 155 /* shared memory region */ 156 #define T4_ERR_ECC 0x9 /* ECC error detected */ 157 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ 158 /* reading PSTAG for a MW */ 159 /* Invalidate */ 160 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ 161 /* software error */ 162 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ 163 #define T4_ERR_CRC 0x10 /* CRC error */ 164 #define T4_ERR_MARKER 0x11 /* Marker error */ 165 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ 166 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ 167 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ 168 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ 169 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ 170 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ 171 #define T4_ERR_MSN 0x18 /* MSN error */ 172 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ 173 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ 174 /* or READ_REQ */ 175 #define T4_ERR_MSN_GAP 0x1B 176 #define T4_ERR_MSN_RANGE 0x1C 177 #define T4_ERR_IRD_OVERFLOW 0x1D 178 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ 179 /* software error */ 180 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ 181 /* mismatch) */ 182 /* 183 * CQE defs 184 */ 185 struct t4_cqe { 186 __be32 header; 187 __be32 len; 188 union { 189 struct { 190 __be32 stag; 191 __be32 msn; 192 } rcqe; 193 struct { 194 u32 nada1; 195 u16 nada2; 196 u16 cidx; 197 } scqe; 198 struct { 199 __be32 wrid_hi; 200 __be32 wrid_low; 201 } gen; 202 u64 drain_cookie; 203 } u; 204 __be64 reserved; 205 __be64 bits_type_ts; 206 }; 207 208 /* macros for flit 0 of the cqe */ 209 210 #define S_CQE_QPID 12 211 #define M_CQE_QPID 0xFFFFF 212 #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID) 213 #define V_CQE_QPID(x) ((x)<<S_CQE_QPID) 214 215 #define S_CQE_SWCQE 11 216 #define M_CQE_SWCQE 0x1 217 #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE) 218 #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE) 219 220 #define S_CQE_STATUS 5 221 #define M_CQE_STATUS 0x1F 222 #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS) 223 #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS) 224 225 #define S_CQE_TYPE 4 226 #define M_CQE_TYPE 0x1 227 #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE) 228 #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE) 229 230 #define S_CQE_OPCODE 0 231 #define M_CQE_OPCODE 0xF 232 #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE) 233 #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE) 234 235 #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header))) 236 #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header))) 237 #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header))) 238 #define SQ_TYPE(x) (CQE_TYPE((x))) 239 #define RQ_TYPE(x) (!CQE_TYPE((x))) 240 #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header))) 241 #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header))) 242 243 #define CQE_SEND_OPCODE(x)(\ 244 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ 245 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ 246 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ 247 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) 248 249 #define CQE_LEN(x) (be32_to_cpu((x)->len)) 250 251 /* used for RQ completion processing */ 252 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) 253 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) 254 255 /* used for SQ completion processing */ 256 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) 257 258 /* generic accessor macros */ 259 #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi) 260 #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low) 261 #define CQE_DRAIN_COOKIE(x) (x)->u.drain_cookie; 262 263 /* macros for flit 3 of the cqe */ 264 #define S_CQE_GENBIT 63 265 #define M_CQE_GENBIT 0x1 266 #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT) 267 #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT) 268 269 #define S_CQE_OVFBIT 62 270 #define M_CQE_OVFBIT 0x1 271 #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT) 272 273 #define S_CQE_IQTYPE 60 274 #define M_CQE_IQTYPE 0x3 275 #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE) 276 277 #define M_CQE_TS 0x0fffffffffffffffULL 278 #define G_CQE_TS(x) ((x) & M_CQE_TS) 279 280 #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts))) 281 #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts))) 282 #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts))) 283 284 struct t4_swsqe { 285 u64 wr_id; 286 struct t4_cqe cqe; 287 int read_len; 288 int opcode; 289 int complete; 290 int signaled; 291 u16 idx; 292 }; 293 294 struct t4_sq { 295 union t4_wr *queue; 296 bus_addr_t dma_addr; 297 DECLARE_PCI_UNMAP_ADDR(mapping); 298 unsigned long phys_addr; 299 struct t4_swsqe *sw_sq; 300 struct t4_swsqe *oldest_read; 301 u64 udb; 302 size_t memsize; 303 u32 qid; 304 u16 in_use; 305 u16 size; 306 u16 cidx; 307 u16 pidx; 308 u16 wq_pidx; 309 u16 flags; 310 }; 311 312 struct t4_swrqe { 313 u64 wr_id; 314 }; 315 316 struct t4_rq { 317 union t4_recv_wr *queue; 318 bus_addr_t dma_addr; 319 DECLARE_PCI_UNMAP_ADDR(mapping); 320 struct t4_swrqe *sw_rq; 321 u64 udb; 322 size_t memsize; 323 u32 qid; 324 u32 msn; 325 u32 rqt_hwaddr; 326 u16 rqt_size; 327 u16 in_use; 328 u16 size; 329 u16 cidx; 330 u16 pidx; 331 u16 wq_pidx; 332 }; 333 334 struct t4_wq { 335 struct t4_sq sq; 336 struct t4_rq rq; 337 void __iomem *db; 338 void __iomem *gts; 339 struct c4iw_rdev *rdev; 340 }; 341 342 static inline int t4_rqes_posted(struct t4_wq *wq) 343 { 344 return wq->rq.in_use; 345 } 346 347 static inline int t4_rq_empty(struct t4_wq *wq) 348 { 349 return wq->rq.in_use == 0; 350 } 351 352 static inline int t4_rq_full(struct t4_wq *wq) 353 { 354 return wq->rq.in_use == (wq->rq.size - 1); 355 } 356 357 static inline u32 t4_rq_avail(struct t4_wq *wq) 358 { 359 return wq->rq.size - 1 - wq->rq.in_use; 360 } 361 362 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) 363 { 364 wq->rq.in_use++; 365 if (++wq->rq.pidx == wq->rq.size) 366 wq->rq.pidx = 0; 367 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 368 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) 369 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; 370 } 371 372 static inline void t4_rq_consume(struct t4_wq *wq) 373 { 374 wq->rq.in_use--; 375 wq->rq.msn++; 376 if (++wq->rq.cidx == wq->rq.size) 377 wq->rq.cidx = 0; 378 } 379 380 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) 381 { 382 return wq->rq.queue[wq->rq.size].status.host_wq_pidx; 383 } 384 385 static inline u16 t4_rq_wq_size(struct t4_wq *wq) 386 { 387 return wq->rq.size * T4_RQ_NUM_SLOTS; 388 } 389 390 static inline int t4_sq_empty(struct t4_wq *wq) 391 { 392 return wq->sq.in_use == 0; 393 } 394 395 static inline int t4_sq_full(struct t4_wq *wq) 396 { 397 return wq->sq.in_use == (wq->sq.size - 1); 398 } 399 400 static inline u32 t4_sq_avail(struct t4_wq *wq) 401 { 402 return wq->sq.size - 1 - wq->sq.in_use; 403 } 404 405 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) 406 { 407 wq->sq.in_use++; 408 if (++wq->sq.pidx == wq->sq.size) 409 wq->sq.pidx = 0; 410 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 411 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) 412 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; 413 } 414 415 static inline void t4_sq_consume(struct t4_wq *wq) 416 { 417 wq->sq.in_use--; 418 if (++wq->sq.cidx == wq->sq.size) 419 wq->sq.cidx = 0; 420 } 421 422 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) 423 { 424 return wq->sq.queue[wq->sq.size].status.host_wq_pidx; 425 } 426 427 static inline u16 t4_sq_wq_size(struct t4_wq *wq) 428 { 429 return wq->sq.size * T4_SQ_NUM_SLOTS; 430 } 431 432 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc) 433 { 434 wmb(); 435 writel(QID(wq->sq.qid) | PIDX(inc), wq->db); 436 } 437 438 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc) 439 { 440 wmb(); 441 writel(QID(wq->rq.qid) | PIDX(inc), wq->db); 442 } 443 444 static inline int t4_wq_in_error(struct t4_wq *wq) 445 { 446 return wq->rq.queue[wq->rq.size].status.qp_err; 447 } 448 449 static inline void t4_set_wq_in_error(struct t4_wq *wq) 450 { 451 wq->rq.queue[wq->rq.size].status.qp_err = 1; 452 } 453 454 struct t4_cq { 455 struct t4_cqe *queue; 456 bus_addr_t dma_addr; 457 DECLARE_PCI_UNMAP_ADDR(mapping); 458 struct t4_cqe *sw_queue; 459 void __iomem *gts; 460 struct c4iw_rdev *rdev; 461 u64 ugts; 462 size_t memsize; 463 __be64 bits_type_ts; 464 u32 cqid; 465 u16 size; /* including status page */ 466 u16 cidx; 467 u16 sw_pidx; 468 u16 sw_cidx; 469 u16 sw_in_use; 470 u16 cidx_inc; 471 u8 gen; 472 u8 error; 473 }; 474 475 static inline int t4_arm_cq(struct t4_cq *cq, int se) 476 { 477 u32 val; 478 479 while (cq->cidx_inc > CIDXINC_MASK) { 480 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) | 481 INGRESSQID(cq->cqid); 482 writel(val, cq->gts); 483 cq->cidx_inc -= CIDXINC_MASK; 484 } 485 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) | 486 INGRESSQID(cq->cqid); 487 writel(val, cq->gts); 488 cq->cidx_inc = 0; 489 return 0; 490 } 491 492 static inline void t4_swcq_produce(struct t4_cq *cq) 493 { 494 cq->sw_in_use++; 495 if (++cq->sw_pidx == cq->size) 496 cq->sw_pidx = 0; 497 } 498 499 static inline void t4_swcq_consume(struct t4_cq *cq) 500 { 501 cq->sw_in_use--; 502 if (++cq->sw_cidx == cq->size) 503 cq->sw_cidx = 0; 504 } 505 506 static inline void t4_hwcq_consume(struct t4_cq *cq) 507 { 508 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; 509 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == M_CIDXINC) { 510 u32 val; 511 512 val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) | 513 INGRESSQID(cq->cqid); 514 writel(val, cq->gts); 515 cq->cidx_inc = 0; 516 } 517 if (++cq->cidx == cq->size) { 518 cq->cidx = 0; 519 cq->gen ^= 1; 520 } 521 } 522 523 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) 524 { 525 return (CQE_GENBIT(cqe) == cq->gen); 526 } 527 528 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 529 { 530 int ret; 531 u16 prev_cidx; 532 533 if (cq->cidx == 0) 534 prev_cidx = cq->size - 1; 535 else 536 prev_cidx = cq->cidx - 1; 537 538 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { 539 ret = -EOVERFLOW; 540 cq->error = 1; 541 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); 542 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 543 *cqe = &cq->queue[cq->cidx]; 544 ret = 0; 545 } else 546 ret = -ENODATA; 547 return ret; 548 } 549 550 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 551 { 552 if (cq->sw_in_use) 553 return &cq->sw_queue[cq->sw_cidx]; 554 return NULL; 555 } 556 557 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 558 { 559 int ret = 0; 560 561 if (cq->error) 562 ret = -ENODATA; 563 else if (cq->sw_in_use) 564 *cqe = &cq->sw_queue[cq->sw_cidx]; 565 else 566 ret = t4_next_hw_cqe(cq, cqe); 567 return ret; 568 } 569 570 static inline int t4_cq_in_error(struct t4_cq *cq) 571 { 572 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err; 573 } 574 575 static inline void t4_set_cq_in_error(struct t4_cq *cq) 576 { 577 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1; 578 } 579 #endif 580