1 /* 2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_inet.h" 36 37 #ifdef TCP_OFFLOAD 38 #include <sys/types.h> 39 #include <sys/malloc.h> 40 #include <sys/socket.h> 41 #include <sys/socketvar.h> 42 #include <sys/sockio.h> 43 #include <sys/taskqueue.h> 44 #include <netinet/in.h> 45 #include <net/route.h> 46 47 #include <netinet/in_systm.h> 48 #include <netinet/in_pcb.h> 49 #include <netinet/ip.h> 50 #include <netinet/ip_var.h> 51 #include <netinet/tcp_var.h> 52 #include <netinet/tcp.h> 53 #include <netinet/tcpip.h> 54 55 #include <netinet/toecore.h> 56 57 struct sge_iq; 58 struct rss_header; 59 struct cpl_set_tcb_rpl; 60 #include <linux/types.h> 61 #include "offload.h" 62 #include "tom/t4_tom.h" 63 64 #include "iw_cxgbe.h" 65 #include "user.h" 66 67 static int creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize); 68 69 70 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 71 { 72 unsigned long flag; 73 spin_lock_irqsave(&qhp->lock, flag); 74 qhp->attr.state = state; 75 spin_unlock_irqrestore(&qhp->lock, flag); 76 } 77 78 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 79 { 80 81 contigfree(sq->queue, sq->memsize, M_DEVBUF); 82 } 83 84 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 85 { 86 87 dealloc_host_sq(rdev, sq); 88 } 89 90 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 91 { 92 sq->queue = contigmalloc(sq->memsize, M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 93 4096, 0); 94 95 if (sq->queue) 96 sq->dma_addr = vtophys(sq->queue); 97 else 98 return -ENOMEM; 99 sq->phys_addr = vtophys(sq->queue); 100 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 101 CTR4(KTR_IW_CXGBE, "%s sq %p dma_addr %p phys_addr %p", __func__, 102 sq->queue, sq->dma_addr, sq->phys_addr); 103 return 0; 104 } 105 106 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 107 struct c4iw_dev_ucontext *uctx) 108 { 109 /* 110 * uP clears EQ contexts when the connection exits rdma mode, 111 * so no need to post a RESET WR for these EQs. 112 */ 113 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 114 dealloc_sq(rdev, &wq->sq); 115 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 116 kfree(wq->rq.sw_rq); 117 kfree(wq->sq.sw_sq); 118 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 119 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 120 return 0; 121 } 122 123 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 124 struct t4_cq *rcq, struct t4_cq *scq, 125 struct c4iw_dev_ucontext *uctx) 126 { 127 struct adapter *sc = rdev->adap; 128 int user = (uctx != &rdev->uctx); 129 struct fw_ri_res_wr *res_wr; 130 struct fw_ri_res *res; 131 int wr_len; 132 struct c4iw_wr_wait wr_wait; 133 int ret; 134 int eqsize; 135 struct wrqe *wr; 136 137 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 138 if (!wq->sq.qid) 139 return -ENOMEM; 140 141 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 142 if (!wq->rq.qid) 143 goto err1; 144 145 if (!user) { 146 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 147 GFP_KERNEL); 148 if (!wq->sq.sw_sq) 149 goto err2; 150 151 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 152 GFP_KERNEL); 153 if (!wq->rq.sw_rq) 154 goto err3; 155 } 156 157 /* RQT must be a power of 2. */ 158 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size); 159 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 160 if (!wq->rq.rqt_hwaddr) 161 goto err4; 162 163 if (alloc_host_sq(rdev, &wq->sq)) 164 goto err5; 165 166 memset(wq->sq.queue, 0, wq->sq.memsize); 167 pci_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 168 169 wq->rq.queue = contigmalloc(wq->rq.memsize, 170 M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 4096, 0); 171 if (wq->rq.queue) 172 wq->rq.dma_addr = vtophys(wq->rq.queue); 173 else 174 goto err6; 175 CTR5(KTR_IW_CXGBE, 176 "%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx", __func__, 177 wq->sq.queue, (unsigned long long)vtophys(wq->sq.queue), 178 wq->rq.queue, (unsigned long long)vtophys(wq->rq.queue)); 179 memset(wq->rq.queue, 0, wq->rq.memsize); 180 pci_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 181 182 wq->db = (void *)((unsigned long)rman_get_virtual(sc->regs_res) + 183 sc->sge_kdoorbell_reg); 184 wq->gts = (void *)((unsigned long)rman_get_virtual(rdev->adap->regs_res) 185 + sc->sge_gts_reg); 186 if (user) { 187 wq->sq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 188 (wq->sq.qid << rdev->qpshift)); 189 wq->sq.udb &= PAGE_MASK; 190 wq->rq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 191 (wq->rq.qid << rdev->qpshift)); 192 wq->rq.udb &= PAGE_MASK; 193 } 194 wq->rdev = rdev; 195 wq->rq.msn = 1; 196 197 /* build fw_ri_res_wr */ 198 wr_len = sizeof *res_wr + 2 * sizeof *res; 199 200 wr = alloc_wrqe(wr_len, &sc->sge.mgmtq); 201 if (wr == NULL) 202 return (0); 203 res_wr = wrtod(wr); 204 205 memset(res_wr, 0, wr_len); 206 res_wr->op_nres = cpu_to_be32( 207 V_FW_WR_OP(FW_RI_RES_WR) | 208 V_FW_RI_RES_WR_NRES(2) | 209 F_FW_WR_COMPL); 210 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 211 res_wr->cookie = (unsigned long) &wr_wait; 212 res = res_wr->res; 213 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 214 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 215 216 /* eqsize is the number of 64B entries plus the status page size. */ 217 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + 218 (sc->params.sge.spg_len / EQ_ESIZE); 219 220 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 221 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 222 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 223 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 224 V_FW_RI_RES_WR_IQID(scq->cqid)); 225 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 226 V_FW_RI_RES_WR_DCAEN(0) | 227 V_FW_RI_RES_WR_DCACPU(0) | 228 V_FW_RI_RES_WR_FBMIN(2) | 229 V_FW_RI_RES_WR_FBMAX(2) | 230 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 231 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 232 V_FW_RI_RES_WR_EQSIZE(eqsize)); 233 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 234 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 235 res++; 236 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 237 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 238 239 /* eqsize is the number of 64B entries plus the status page size. */ 240 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + 241 (sc->params.sge.spg_len / EQ_ESIZE); 242 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 243 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 244 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 245 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 246 V_FW_RI_RES_WR_IQID(rcq->cqid)); 247 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 248 V_FW_RI_RES_WR_DCAEN(0) | 249 V_FW_RI_RES_WR_DCACPU(0) | 250 V_FW_RI_RES_WR_FBMIN(2) | 251 V_FW_RI_RES_WR_FBMAX(2) | 252 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 253 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 254 V_FW_RI_RES_WR_EQSIZE(eqsize)); 255 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 256 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 257 258 c4iw_init_wr_wait(&wr_wait); 259 260 t4_wrq_tx(sc, wr); 261 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); 262 if (ret) 263 goto err7; 264 265 CTR6(KTR_IW_CXGBE, 266 "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx", 267 __func__, wq->sq.qid, wq->rq.qid, wq->db, 268 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb); 269 270 return 0; 271 err7: 272 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 273 err6: 274 dealloc_sq(rdev, &wq->sq); 275 err5: 276 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 277 err4: 278 kfree(wq->rq.sw_rq); 279 err3: 280 kfree(wq->sq.sw_sq); 281 err2: 282 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 283 err1: 284 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 285 return -ENOMEM; 286 } 287 288 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 289 struct ib_send_wr *wr, int max, u32 *plenp) 290 { 291 u8 *dstp, *srcp; 292 u32 plen = 0; 293 int i; 294 int rem, len; 295 296 dstp = (u8 *)immdp->data; 297 for (i = 0; i < wr->num_sge; i++) { 298 if ((plen + wr->sg_list[i].length) > max) 299 return -EMSGSIZE; 300 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 301 plen += wr->sg_list[i].length; 302 rem = wr->sg_list[i].length; 303 while (rem) { 304 if (dstp == (u8 *)&sq->queue[sq->size]) 305 dstp = (u8 *)sq->queue; 306 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 307 len = rem; 308 else 309 len = (u8 *)&sq->queue[sq->size] - dstp; 310 memcpy(dstp, srcp, len); 311 dstp += len; 312 srcp += len; 313 rem -= len; 314 } 315 } 316 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 317 if (len) 318 memset(dstp, 0, len); 319 immdp->op = FW_RI_DATA_IMMD; 320 immdp->r1 = 0; 321 immdp->r2 = 0; 322 immdp->immdlen = cpu_to_be32(plen); 323 *plenp = plen; 324 return 0; 325 } 326 327 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 328 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 329 int num_sge, u32 *plenp) 330 331 { 332 int i; 333 u32 plen = 0; 334 __be64 *flitp = (__be64 *)isglp->sge; 335 336 for (i = 0; i < num_sge; i++) { 337 if ((plen + sg_list[i].length) < plen) 338 return -EMSGSIZE; 339 plen += sg_list[i].length; 340 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 341 sg_list[i].length); 342 if (++flitp == queue_end) 343 flitp = queue_start; 344 *flitp = cpu_to_be64(sg_list[i].addr); 345 if (++flitp == queue_end) 346 flitp = queue_start; 347 } 348 *flitp = (__force __be64)0; 349 isglp->op = FW_RI_DATA_ISGL; 350 isglp->r1 = 0; 351 isglp->nsge = cpu_to_be16(num_sge); 352 isglp->r2 = 0; 353 if (plenp) 354 *plenp = plen; 355 return 0; 356 } 357 358 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 359 struct ib_send_wr *wr, u8 *len16) 360 { 361 u32 plen; 362 int size; 363 int ret; 364 365 if (wr->num_sge > T4_MAX_SEND_SGE) 366 return -EINVAL; 367 switch (wr->opcode) { 368 case IB_WR_SEND: 369 if (wr->send_flags & IB_SEND_SOLICITED) 370 wqe->send.sendop_pkd = cpu_to_be32( 371 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); 372 else 373 wqe->send.sendop_pkd = cpu_to_be32( 374 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); 375 wqe->send.stag_inv = 0; 376 break; 377 case IB_WR_SEND_WITH_INV: 378 if (wr->send_flags & IB_SEND_SOLICITED) 379 wqe->send.sendop_pkd = cpu_to_be32( 380 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV)); 381 else 382 wqe->send.sendop_pkd = cpu_to_be32( 383 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV)); 384 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 385 break; 386 387 default: 388 return -EINVAL; 389 } 390 391 plen = 0; 392 if (wr->num_sge) { 393 if (wr->send_flags & IB_SEND_INLINE) { 394 ret = build_immd(sq, wqe->send.u.immd_src, wr, 395 T4_MAX_SEND_INLINE, &plen); 396 if (ret) 397 return ret; 398 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 399 plen; 400 } else { 401 ret = build_isgl((__be64 *)sq->queue, 402 (__be64 *)&sq->queue[sq->size], 403 wqe->send.u.isgl_src, 404 wr->sg_list, wr->num_sge, &plen); 405 if (ret) 406 return ret; 407 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 408 wr->num_sge * sizeof(struct fw_ri_sge); 409 } 410 } else { 411 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 412 wqe->send.u.immd_src[0].r1 = 0; 413 wqe->send.u.immd_src[0].r2 = 0; 414 wqe->send.u.immd_src[0].immdlen = 0; 415 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 416 plen = 0; 417 } 418 *len16 = DIV_ROUND_UP(size, 16); 419 wqe->send.plen = cpu_to_be32(plen); 420 return 0; 421 } 422 423 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 424 struct ib_send_wr *wr, u8 *len16) 425 { 426 u32 plen; 427 int size; 428 int ret; 429 430 if (wr->num_sge > T4_MAX_SEND_SGE) 431 return -EINVAL; 432 wqe->write.r2 = 0; 433 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey); 434 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr); 435 if (wr->num_sge) { 436 if (wr->send_flags & IB_SEND_INLINE) { 437 ret = build_immd(sq, wqe->write.u.immd_src, wr, 438 T4_MAX_WRITE_INLINE, &plen); 439 if (ret) 440 return ret; 441 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 442 plen; 443 } else { 444 ret = build_isgl((__be64 *)sq->queue, 445 (__be64 *)&sq->queue[sq->size], 446 wqe->write.u.isgl_src, 447 wr->sg_list, wr->num_sge, &plen); 448 if (ret) 449 return ret; 450 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 451 wr->num_sge * sizeof(struct fw_ri_sge); 452 } 453 } else { 454 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 455 wqe->write.u.immd_src[0].r1 = 0; 456 wqe->write.u.immd_src[0].r2 = 0; 457 wqe->write.u.immd_src[0].immdlen = 0; 458 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 459 plen = 0; 460 } 461 *len16 = DIV_ROUND_UP(size, 16); 462 wqe->write.plen = cpu_to_be32(plen); 463 return 0; 464 } 465 466 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 467 { 468 if (wr->num_sge > 1) 469 return -EINVAL; 470 if (wr->num_sge) { 471 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey); 472 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr 473 >> 32)); 474 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr); 475 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 476 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 477 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 478 >> 32)); 479 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 480 } else { 481 wqe->read.stag_src = cpu_to_be32(2); 482 wqe->read.to_src_hi = 0; 483 wqe->read.to_src_lo = 0; 484 wqe->read.stag_sink = cpu_to_be32(2); 485 wqe->read.plen = 0; 486 wqe->read.to_sink_hi = 0; 487 wqe->read.to_sink_lo = 0; 488 } 489 wqe->read.r2 = 0; 490 wqe->read.r5 = 0; 491 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 492 return 0; 493 } 494 495 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 496 struct ib_recv_wr *wr, u8 *len16) 497 { 498 int ret; 499 500 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 501 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 502 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 503 if (ret) 504 return ret; 505 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 506 wr->num_sge * sizeof(struct fw_ri_sge), 16); 507 return 0; 508 } 509 510 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, 511 struct ib_send_wr *wr, u8 *len16) 512 { 513 514 struct fw_ri_immd *imdp; 515 __be64 *p; 516 int i; 517 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); 518 int rem; 519 520 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH) 521 return -EINVAL; 522 523 wqe->fr.qpbinde_to_dcacpu = 0; 524 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12; 525 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 526 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags); 527 wqe->fr.len_hi = 0; 528 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length); 529 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey); 530 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); 531 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & 532 0xffffffff); 533 WARN_ON(pbllen > T4_MAX_FR_IMMD); 534 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 535 imdp->op = FW_RI_DATA_IMMD; 536 imdp->r1 = 0; 537 imdp->r2 = 0; 538 imdp->immdlen = cpu_to_be32(pbllen); 539 p = (__be64 *)(imdp + 1); 540 rem = pbllen; 541 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { 542 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]); 543 rem -= sizeof *p; 544 if (++p == (__be64 *)&sq->queue[sq->size]) 545 p = (__be64 *)sq->queue; 546 } 547 BUG_ON(rem < 0); 548 while (rem) { 549 *p = 0; 550 rem -= sizeof *p; 551 if (++p == (__be64 *)&sq->queue[sq->size]) 552 p = (__be64 *)sq->queue; 553 } 554 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16); 555 return 0; 556 } 557 558 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, 559 u8 *len16) 560 { 561 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 562 wqe->inv.r2 = 0; 563 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 564 return 0; 565 } 566 567 void c4iw_qp_add_ref(struct ib_qp *qp) 568 { 569 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 570 atomic_inc(&(to_c4iw_qp(qp)->refcnt)); 571 } 572 573 void c4iw_qp_rem_ref(struct ib_qp *qp) 574 { 575 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 576 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt))) 577 wake_up(&(to_c4iw_qp(qp)->wait)); 578 } 579 580 static void complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr) 581 { 582 struct t4_cqe cqe = {}; 583 struct c4iw_cq *schp; 584 unsigned long flag; 585 struct t4_cq *cq; 586 587 schp = to_c4iw_cq(qhp->ibqp.send_cq); 588 cq = &schp->cq; 589 590 PDBG("%s drain sq id %u\n", __func__, qhp->wq.sq.qid); 591 cqe.u.drain_cookie = wr->wr_id; 592 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 593 V_CQE_OPCODE(C4IW_DRAIN_OPCODE) | 594 V_CQE_TYPE(1) | 595 V_CQE_SWCQE(1) | 596 V_CQE_QPID(qhp->wq.sq.qid)); 597 598 spin_lock_irqsave(&schp->lock, flag); 599 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 600 cq->sw_queue[cq->sw_pidx] = cqe; 601 t4_swcq_produce(cq); 602 spin_unlock_irqrestore(&schp->lock, flag); 603 604 spin_lock_irqsave(&schp->comp_handler_lock, flag); 605 (*schp->ibcq.comp_handler)(&schp->ibcq, 606 schp->ibcq.cq_context); 607 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 608 } 609 610 static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr) 611 { 612 struct t4_cqe cqe = {}; 613 struct c4iw_cq *rchp; 614 unsigned long flag; 615 struct t4_cq *cq; 616 617 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 618 cq = &rchp->cq; 619 620 PDBG("%s drain rq id %u\n", __func__, qhp->wq.sq.qid); 621 cqe.u.drain_cookie = wr->wr_id; 622 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 623 V_CQE_OPCODE(C4IW_DRAIN_OPCODE) | 624 V_CQE_TYPE(0) | 625 V_CQE_SWCQE(1) | 626 V_CQE_QPID(qhp->wq.sq.qid)); 627 628 spin_lock_irqsave(&rchp->lock, flag); 629 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 630 cq->sw_queue[cq->sw_pidx] = cqe; 631 t4_swcq_produce(cq); 632 spin_unlock_irqrestore(&rchp->lock, flag); 633 634 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 635 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 636 rchp->ibcq.cq_context); 637 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 638 } 639 640 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 641 struct ib_send_wr **bad_wr) 642 { 643 int err = 0; 644 u8 len16 = 0; 645 enum fw_wr_opcodes fw_opcode = 0; 646 enum fw_ri_wr_flags fw_flags; 647 struct c4iw_qp *qhp; 648 union t4_wr *wqe; 649 u32 num_wrs; 650 struct t4_swsqe *swsqe; 651 unsigned long flag; 652 u16 idx = 0; 653 654 qhp = to_c4iw_qp(ibqp); 655 spin_lock_irqsave(&qhp->lock, flag); 656 if (t4_wq_in_error(&qhp->wq)) { 657 spin_unlock_irqrestore(&qhp->lock, flag); 658 complete_sq_drain_wr(qhp, wr); 659 return err; 660 } 661 num_wrs = t4_sq_avail(&qhp->wq); 662 if (num_wrs == 0) { 663 spin_unlock_irqrestore(&qhp->lock, flag); 664 return -ENOMEM; 665 } 666 while (wr) { 667 if (num_wrs == 0) { 668 err = -ENOMEM; 669 *bad_wr = wr; 670 break; 671 } 672 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 673 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 674 675 fw_flags = 0; 676 if (wr->send_flags & IB_SEND_SOLICITED) 677 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 678 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all) 679 fw_flags |= FW_RI_COMPLETION_FLAG; 680 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 681 switch (wr->opcode) { 682 case IB_WR_SEND_WITH_INV: 683 case IB_WR_SEND: 684 if (wr->send_flags & IB_SEND_FENCE) 685 fw_flags |= FW_RI_READ_FENCE_FLAG; 686 fw_opcode = FW_RI_SEND_WR; 687 if (wr->opcode == IB_WR_SEND) 688 swsqe->opcode = FW_RI_SEND; 689 else 690 swsqe->opcode = FW_RI_SEND_WITH_INV; 691 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 692 break; 693 case IB_WR_RDMA_WRITE: 694 fw_opcode = FW_RI_RDMA_WRITE_WR; 695 swsqe->opcode = FW_RI_RDMA_WRITE; 696 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 697 break; 698 case IB_WR_RDMA_READ: 699 case IB_WR_RDMA_READ_WITH_INV: 700 fw_opcode = FW_RI_RDMA_READ_WR; 701 swsqe->opcode = FW_RI_READ_REQ; 702 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) 703 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 704 else 705 fw_flags = 0; 706 err = build_rdma_read(wqe, wr, &len16); 707 if (err) 708 break; 709 swsqe->read_len = wr->sg_list[0].length; 710 if (!qhp->wq.sq.oldest_read) 711 qhp->wq.sq.oldest_read = swsqe; 712 break; 713 case IB_WR_FAST_REG_MR: 714 fw_opcode = FW_RI_FR_NSMR_WR; 715 swsqe->opcode = FW_RI_FAST_REGISTER; 716 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16); 717 break; 718 case IB_WR_LOCAL_INV: 719 if (wr->send_flags & IB_SEND_FENCE) 720 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 721 fw_opcode = FW_RI_INV_LSTAG_WR; 722 swsqe->opcode = FW_RI_LOCAL_INV; 723 err = build_inv_stag(wqe, wr, &len16); 724 break; 725 default: 726 CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__, 727 wr->opcode); 728 err = -EINVAL; 729 } 730 if (err) { 731 *bad_wr = wr; 732 break; 733 } 734 swsqe->idx = qhp->wq.sq.pidx; 735 swsqe->complete = 0; 736 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) || 737 qhp->sq_sig_all; 738 swsqe->wr_id = wr->wr_id; 739 740 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 741 742 CTR5(KTR_IW_CXGBE, 743 "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u", 744 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 745 swsqe->opcode, swsqe->read_len); 746 wr = wr->next; 747 num_wrs--; 748 t4_sq_produce(&qhp->wq, len16); 749 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 750 } 751 752 t4_ring_sq_db(&qhp->wq, idx); 753 spin_unlock_irqrestore(&qhp->lock, flag); 754 return err; 755 } 756 757 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 758 struct ib_recv_wr **bad_wr) 759 { 760 int err = 0; 761 struct c4iw_qp *qhp; 762 union t4_recv_wr *wqe; 763 u32 num_wrs; 764 u8 len16 = 0; 765 unsigned long flag; 766 u16 idx = 0; 767 768 qhp = to_c4iw_qp(ibqp); 769 spin_lock_irqsave(&qhp->lock, flag); 770 if (t4_wq_in_error(&qhp->wq)) { 771 spin_unlock_irqrestore(&qhp->lock, flag); 772 complete_rq_drain_wr(qhp, wr); 773 return err; 774 } 775 num_wrs = t4_rq_avail(&qhp->wq); 776 if (num_wrs == 0) { 777 spin_unlock_irqrestore(&qhp->lock, flag); 778 return -ENOMEM; 779 } 780 while (wr) { 781 if (wr->num_sge > T4_MAX_RECV_SGE) { 782 err = -EINVAL; 783 *bad_wr = wr; 784 break; 785 } 786 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 787 qhp->wq.rq.wq_pidx * 788 T4_EQ_ENTRY_SIZE); 789 if (num_wrs) 790 err = build_rdma_recv(qhp, wqe, wr, &len16); 791 else 792 err = -ENOMEM; 793 if (err) { 794 *bad_wr = wr; 795 break; 796 } 797 798 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 799 800 wqe->recv.opcode = FW_RI_RECV_WR; 801 wqe->recv.r1 = 0; 802 wqe->recv.wrid = qhp->wq.rq.pidx; 803 wqe->recv.r2[0] = 0; 804 wqe->recv.r2[1] = 0; 805 wqe->recv.r2[2] = 0; 806 wqe->recv.len16 = len16; 807 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__, 808 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 809 t4_rq_produce(&qhp->wq, len16); 810 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 811 wr = wr->next; 812 num_wrs--; 813 } 814 815 t4_ring_rq_db(&qhp->wq, idx); 816 spin_unlock_irqrestore(&qhp->lock, flag); 817 return err; 818 } 819 820 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind) 821 { 822 return -ENOSYS; 823 } 824 825 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 826 u8 *ecode) 827 { 828 int status; 829 int tagged; 830 int opcode; 831 int rqtype; 832 int send_inv; 833 834 if (!err_cqe) { 835 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 836 *ecode = 0; 837 return; 838 } 839 840 status = CQE_STATUS(err_cqe); 841 opcode = CQE_OPCODE(err_cqe); 842 rqtype = RQ_TYPE(err_cqe); 843 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 844 (opcode == FW_RI_SEND_WITH_SE_INV); 845 tagged = (opcode == FW_RI_RDMA_WRITE) || 846 (rqtype && (opcode == FW_RI_READ_RESP)); 847 848 switch (status) { 849 case T4_ERR_STAG: 850 if (send_inv) { 851 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 852 *ecode = RDMAP_CANT_INV_STAG; 853 } else { 854 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 855 *ecode = RDMAP_INV_STAG; 856 } 857 break; 858 case T4_ERR_PDID: 859 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 860 if ((opcode == FW_RI_SEND_WITH_INV) || 861 (opcode == FW_RI_SEND_WITH_SE_INV)) 862 *ecode = RDMAP_CANT_INV_STAG; 863 else 864 *ecode = RDMAP_STAG_NOT_ASSOC; 865 break; 866 case T4_ERR_QPID: 867 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 868 *ecode = RDMAP_STAG_NOT_ASSOC; 869 break; 870 case T4_ERR_ACCESS: 871 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 872 *ecode = RDMAP_ACC_VIOL; 873 break; 874 case T4_ERR_WRAP: 875 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 876 *ecode = RDMAP_TO_WRAP; 877 break; 878 case T4_ERR_BOUND: 879 if (tagged) { 880 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 881 *ecode = DDPT_BASE_BOUNDS; 882 } else { 883 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 884 *ecode = RDMAP_BASE_BOUNDS; 885 } 886 break; 887 case T4_ERR_INVALIDATE_SHARED_MR: 888 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 889 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 890 *ecode = RDMAP_CANT_INV_STAG; 891 break; 892 case T4_ERR_ECC: 893 case T4_ERR_ECC_PSTAG: 894 case T4_ERR_INTERNAL_ERR: 895 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 896 *ecode = 0; 897 break; 898 case T4_ERR_OUT_OF_RQE: 899 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 900 *ecode = DDPU_INV_MSN_NOBUF; 901 break; 902 case T4_ERR_PBL_ADDR_BOUND: 903 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 904 *ecode = DDPT_BASE_BOUNDS; 905 break; 906 case T4_ERR_CRC: 907 *layer_type = LAYER_MPA|DDP_LLP; 908 *ecode = MPA_CRC_ERR; 909 break; 910 case T4_ERR_MARKER: 911 *layer_type = LAYER_MPA|DDP_LLP; 912 *ecode = MPA_MARKER_ERR; 913 break; 914 case T4_ERR_PDU_LEN_ERR: 915 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 916 *ecode = DDPU_MSG_TOOBIG; 917 break; 918 case T4_ERR_DDP_VERSION: 919 if (tagged) { 920 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 921 *ecode = DDPT_INV_VERS; 922 } else { 923 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 924 *ecode = DDPU_INV_VERS; 925 } 926 break; 927 case T4_ERR_RDMA_VERSION: 928 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 929 *ecode = RDMAP_INV_VERS; 930 break; 931 case T4_ERR_OPCODE: 932 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 933 *ecode = RDMAP_INV_OPCODE; 934 break; 935 case T4_ERR_DDP_QUEUE_NUM: 936 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 937 *ecode = DDPU_INV_QN; 938 break; 939 case T4_ERR_MSN: 940 case T4_ERR_MSN_GAP: 941 case T4_ERR_MSN_RANGE: 942 case T4_ERR_IRD_OVERFLOW: 943 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 944 *ecode = DDPU_INV_MSN_RANGE; 945 break; 946 case T4_ERR_TBIT: 947 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 948 *ecode = 0; 949 break; 950 case T4_ERR_MO: 951 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 952 *ecode = DDPU_INV_MO; 953 break; 954 default: 955 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 956 *ecode = 0; 957 break; 958 } 959 } 960 961 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 962 gfp_t gfp) 963 { 964 int ret; 965 struct fw_ri_wr *wqe; 966 struct terminate_message *term; 967 struct wrqe *wr; 968 struct socket *so = qhp->ep->com.so; 969 struct inpcb *inp = sotoinpcb(so); 970 struct tcpcb *tp = intotcpcb(inp); 971 struct toepcb *toep = tp->t_toe; 972 973 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 974 qhp->wq.sq.qid, qhp->ep->hwtid); 975 976 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 977 if (wr == NULL) 978 return; 979 wqe = wrtod(wr); 980 981 memset(wqe, 0, sizeof *wqe); 982 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR)); 983 wqe->flowid_len16 = cpu_to_be32( 984 V_FW_WR_FLOWID(qhp->ep->hwtid) | 985 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 986 987 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 988 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 989 term = (struct terminate_message *)wqe->u.terminate.termmsg; 990 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 991 term->layer_etype = qhp->attr.layer_etype; 992 term->ecode = qhp->attr.ecode; 993 } else 994 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 995 ret = creds(toep, inp, sizeof(*wqe)); 996 if (ret) { 997 free_wrqe(wr); 998 return; 999 } 1000 t4_wrq_tx(qhp->rhp->rdev.adap, wr); 1001 } 1002 1003 /* Assumes qhp lock is held. */ 1004 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 1005 struct c4iw_cq *schp) 1006 { 1007 int count; 1008 int flushed; 1009 unsigned long flag; 1010 1011 CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp, 1012 schp); 1013 1014 /* locking hierarchy: cq lock first, then qp lock. */ 1015 spin_lock_irqsave(&rchp->lock, flag); 1016 spin_lock(&qhp->lock); 1017 c4iw_flush_hw_cq(&rchp->cq); 1018 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 1019 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 1020 spin_unlock(&qhp->lock); 1021 spin_unlock_irqrestore(&rchp->lock, flag); 1022 if (flushed && rchp->ibcq.comp_handler) { 1023 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1024 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1025 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1026 } 1027 1028 /* locking hierarchy: cq lock first, then qp lock. */ 1029 spin_lock_irqsave(&schp->lock, flag); 1030 spin_lock(&qhp->lock); 1031 c4iw_flush_hw_cq(&schp->cq); 1032 c4iw_count_scqes(&schp->cq, &qhp->wq, &count); 1033 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count); 1034 spin_unlock(&qhp->lock); 1035 spin_unlock_irqrestore(&schp->lock, flag); 1036 if (flushed && schp->ibcq.comp_handler) { 1037 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1038 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context); 1039 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1040 } 1041 } 1042 1043 static void flush_qp(struct c4iw_qp *qhp) 1044 { 1045 struct c4iw_cq *rchp, *schp; 1046 unsigned long flag; 1047 1048 rchp = get_chp(qhp->rhp, qhp->attr.rcq); 1049 schp = get_chp(qhp->rhp, qhp->attr.scq); 1050 1051 if (qhp->ibqp.uobject) { 1052 t4_set_wq_in_error(&qhp->wq); 1053 t4_set_cq_in_error(&rchp->cq); 1054 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1055 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1056 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1057 if (schp != rchp) { 1058 t4_set_cq_in_error(&schp->cq); 1059 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1060 (*schp->ibcq.comp_handler)(&schp->ibcq, 1061 schp->ibcq.cq_context); 1062 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1063 } 1064 return; 1065 } 1066 __flush_qp(qhp, rchp, schp); 1067 } 1068 1069 static int 1070 rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep) 1071 { 1072 struct c4iw_rdev *rdev = &rhp->rdev; 1073 struct adapter *sc = rdev->adap; 1074 struct fw_ri_wr *wqe; 1075 int ret; 1076 struct wrqe *wr; 1077 struct socket *so = ep->com.so; 1078 struct inpcb *inp = sotoinpcb(so); 1079 struct tcpcb *tp = intotcpcb(inp); 1080 struct toepcb *toep = tp->t_toe; 1081 1082 KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__)); 1083 1084 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1085 qhp->wq.sq.qid, ep->hwtid); 1086 1087 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1088 if (wr == NULL) 1089 return (0); 1090 wqe = wrtod(wr); 1091 1092 memset(wqe, 0, sizeof *wqe); 1093 1094 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL); 1095 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1096 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1097 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1098 wqe->u.fini.type = FW_RI_TYPE_FINI; 1099 1100 c4iw_init_wr_wait(&ep->com.wr_wait); 1101 1102 ret = creds(toep, inp, sizeof(*wqe)); 1103 if (ret) { 1104 free_wrqe(wr); 1105 return ret; 1106 } 1107 t4_wrq_tx(sc, wr); 1108 1109 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1110 qhp->wq.sq.qid, __func__); 1111 return ret; 1112 } 1113 1114 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1115 { 1116 CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type); 1117 memset(&init->u, 0, sizeof init->u); 1118 switch (p2p_type) { 1119 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1120 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1121 init->u.write.stag_sink = cpu_to_be32(1); 1122 init->u.write.to_sink = cpu_to_be64(1); 1123 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1124 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1125 sizeof(struct fw_ri_immd), 1126 16); 1127 break; 1128 case FW_RI_INIT_P2PTYPE_READ_REQ: 1129 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1130 init->u.read.stag_src = cpu_to_be32(1); 1131 init->u.read.to_src_lo = cpu_to_be32(1); 1132 init->u.read.stag_sink = cpu_to_be32(1); 1133 init->u.read.to_sink_lo = cpu_to_be32(1); 1134 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1135 break; 1136 } 1137 } 1138 1139 static int 1140 creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize) 1141 { 1142 struct ofld_tx_sdesc *txsd; 1143 1144 CTR3(KTR_IW_CXGBE, "%s:creB %p %u", __func__, toep , wrsize); 1145 INP_WLOCK(inp); 1146 if ((inp->inp_flags & (INP_DROPPED | INP_TIMEWAIT)) != 0) { 1147 INP_WUNLOCK(inp); 1148 return (EINVAL); 1149 } 1150 txsd = &toep->txsd[toep->txsd_pidx]; 1151 txsd->tx_credits = howmany(wrsize, 16); 1152 txsd->plen = 0; 1153 KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0, 1154 ("%s: not enough credits (%d)", __func__, toep->tx_credits)); 1155 toep->tx_credits -= txsd->tx_credits; 1156 if (__predict_false(++toep->txsd_pidx == toep->txsd_total)) 1157 toep->txsd_pidx = 0; 1158 toep->txsd_avail--; 1159 INP_WUNLOCK(inp); 1160 CTR5(KTR_IW_CXGBE, "%s:creE %p %u %u %u", __func__, toep , 1161 txsd->tx_credits, toep->tx_credits, toep->txsd_pidx); 1162 return (0); 1163 } 1164 1165 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1166 { 1167 struct fw_ri_wr *wqe; 1168 int ret; 1169 struct wrqe *wr; 1170 struct c4iw_ep *ep = qhp->ep; 1171 struct c4iw_rdev *rdev = &qhp->rhp->rdev; 1172 struct adapter *sc = rdev->adap; 1173 struct socket *so = ep->com.so; 1174 struct inpcb *inp = sotoinpcb(so); 1175 struct tcpcb *tp = intotcpcb(inp); 1176 struct toepcb *toep = tp->t_toe; 1177 1178 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1179 qhp->wq.sq.qid, ep->hwtid); 1180 1181 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1182 if (wr == NULL) 1183 return (0); 1184 wqe = wrtod(wr); 1185 1186 memset(wqe, 0, sizeof *wqe); 1187 1188 wqe->op_compl = cpu_to_be32( 1189 V_FW_WR_OP(FW_RI_WR) | 1190 F_FW_WR_COMPL); 1191 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1192 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1193 1194 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1195 1196 wqe->u.init.type = FW_RI_TYPE_INIT; 1197 wqe->u.init.mpareqbit_p2ptype = 1198 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) | 1199 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type); 1200 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1201 if (qhp->attr.mpa_attr.recv_marker_enabled) 1202 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1203 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1204 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1205 if (qhp->attr.mpa_attr.crc_enabled) 1206 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1207 1208 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1209 FW_RI_QP_RDMA_WRITE_ENABLE | 1210 FW_RI_QP_BIND_ENABLE; 1211 if (!qhp->ibqp.uobject) 1212 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1213 FW_RI_QP_STAG0_ENABLE; 1214 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1215 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1216 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1217 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1218 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1219 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1220 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1221 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1222 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1223 wqe->u.init.iss = cpu_to_be32(ep->snd_seq); 1224 wqe->u.init.irs = cpu_to_be32(ep->rcv_seq); 1225 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1226 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1227 sc->vres.rq.start); 1228 if (qhp->attr.mpa_attr.initiator) 1229 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1230 1231 c4iw_init_wr_wait(&ep->com.wr_wait); 1232 1233 ret = creds(toep, inp, sizeof(*wqe)); 1234 if (ret) { 1235 free_wrqe(wr); 1236 return ret; 1237 } 1238 t4_wrq_tx(sc, wr); 1239 1240 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1241 qhp->wq.sq.qid, __func__); 1242 1243 toep->ulp_mode = ULP_MODE_RDMA; 1244 1245 return ret; 1246 } 1247 1248 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1249 enum c4iw_qp_attr_mask mask, 1250 struct c4iw_qp_attributes *attrs, 1251 int internal) 1252 { 1253 int ret = 0; 1254 struct c4iw_qp_attributes newattr = qhp->attr; 1255 int disconnect = 0; 1256 int terminate = 0; 1257 int abort = 0; 1258 int free = 0; 1259 struct c4iw_ep *ep = NULL; 1260 1261 CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp, 1262 qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep); 1263 CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state, 1264 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1265 1266 mutex_lock(&qhp->mutex); 1267 1268 /* Process attr changes if in IDLE */ 1269 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1270 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1271 ret = -EIO; 1272 goto out; 1273 } 1274 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1275 newattr.enable_rdma_read = attrs->enable_rdma_read; 1276 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1277 newattr.enable_rdma_write = attrs->enable_rdma_write; 1278 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1279 newattr.enable_bind = attrs->enable_bind; 1280 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1281 if (attrs->max_ord > c4iw_max_read_depth) { 1282 ret = -EINVAL; 1283 goto out; 1284 } 1285 newattr.max_ord = attrs->max_ord; 1286 } 1287 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1288 if (attrs->max_ird > c4iw_max_read_depth) { 1289 ret = -EINVAL; 1290 goto out; 1291 } 1292 newattr.max_ird = attrs->max_ird; 1293 } 1294 qhp->attr = newattr; 1295 } 1296 1297 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1298 goto out; 1299 if (qhp->attr.state == attrs->next_state) 1300 goto out; 1301 1302 switch (qhp->attr.state) { 1303 case C4IW_QP_STATE_IDLE: 1304 switch (attrs->next_state) { 1305 case C4IW_QP_STATE_RTS: 1306 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1307 ret = -EINVAL; 1308 goto out; 1309 } 1310 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1311 ret = -EINVAL; 1312 goto out; 1313 } 1314 qhp->attr.mpa_attr = attrs->mpa_attr; 1315 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1316 qhp->ep = qhp->attr.llp_stream_handle; 1317 set_state(qhp, C4IW_QP_STATE_RTS); 1318 1319 /* 1320 * Ref the endpoint here and deref when we 1321 * disassociate the endpoint from the QP. This 1322 * happens in CLOSING->IDLE transition or *->ERROR 1323 * transition. 1324 */ 1325 c4iw_get_ep(&qhp->ep->com); 1326 ret = rdma_init(rhp, qhp); 1327 if (ret) 1328 goto err; 1329 break; 1330 case C4IW_QP_STATE_ERROR: 1331 set_state(qhp, C4IW_QP_STATE_ERROR); 1332 flush_qp(qhp); 1333 break; 1334 default: 1335 ret = -EINVAL; 1336 goto out; 1337 } 1338 break; 1339 case C4IW_QP_STATE_RTS: 1340 switch (attrs->next_state) { 1341 case C4IW_QP_STATE_CLOSING: 1342 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2); 1343 set_state(qhp, C4IW_QP_STATE_CLOSING); 1344 ep = qhp->ep; 1345 if (!internal) { 1346 abort = 0; 1347 disconnect = 1; 1348 c4iw_get_ep(&qhp->ep->com); 1349 } 1350 if (qhp->ibqp.uobject) 1351 t4_set_wq_in_error(&qhp->wq); 1352 ret = rdma_fini(rhp, qhp, ep); 1353 if (ret) 1354 goto err; 1355 break; 1356 case C4IW_QP_STATE_TERMINATE: 1357 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1358 qhp->attr.layer_etype = attrs->layer_etype; 1359 qhp->attr.ecode = attrs->ecode; 1360 if (qhp->ibqp.uobject) 1361 t4_set_wq_in_error(&qhp->wq); 1362 ep = qhp->ep; 1363 if (!internal) 1364 terminate = 1; 1365 disconnect = 1; 1366 c4iw_get_ep(&qhp->ep->com); 1367 break; 1368 case C4IW_QP_STATE_ERROR: 1369 set_state(qhp, C4IW_QP_STATE_ERROR); 1370 if (qhp->ibqp.uobject) 1371 t4_set_wq_in_error(&qhp->wq); 1372 if (!internal) { 1373 abort = 1; 1374 disconnect = 1; 1375 ep = qhp->ep; 1376 c4iw_get_ep(&qhp->ep->com); 1377 } 1378 goto err; 1379 break; 1380 default: 1381 ret = -EINVAL; 1382 goto out; 1383 } 1384 break; 1385 case C4IW_QP_STATE_CLOSING: 1386 1387 /* 1388 * Allow kernel users to move to ERROR for qp draining. 1389 */ 1390 if (!internal && (qhp->ibqp.uobject || attrs->next_state != 1391 C4IW_QP_STATE_ERROR)) { 1392 ret = -EINVAL; 1393 goto out; 1394 } 1395 switch (attrs->next_state) { 1396 case C4IW_QP_STATE_IDLE: 1397 flush_qp(qhp); 1398 set_state(qhp, C4IW_QP_STATE_IDLE); 1399 qhp->attr.llp_stream_handle = NULL; 1400 c4iw_put_ep(&qhp->ep->com); 1401 qhp->ep = NULL; 1402 wake_up(&qhp->wait); 1403 break; 1404 case C4IW_QP_STATE_ERROR: 1405 goto err; 1406 default: 1407 ret = -EINVAL; 1408 goto err; 1409 } 1410 break; 1411 case C4IW_QP_STATE_ERROR: 1412 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1413 ret = -EINVAL; 1414 goto out; 1415 } 1416 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1417 ret = -EINVAL; 1418 goto out; 1419 } 1420 set_state(qhp, C4IW_QP_STATE_IDLE); 1421 break; 1422 case C4IW_QP_STATE_TERMINATE: 1423 if (!internal) { 1424 ret = -EINVAL; 1425 goto out; 1426 } 1427 goto err; 1428 break; 1429 default: 1430 printf("%s in a bad state %d\n", 1431 __func__, qhp->attr.state); 1432 ret = -EINVAL; 1433 goto err; 1434 break; 1435 } 1436 goto out; 1437 err: 1438 CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__, 1439 qhp->ep, qhp->wq.sq.qid); 1440 1441 /* disassociate the LLP connection */ 1442 qhp->attr.llp_stream_handle = NULL; 1443 if (!ep) 1444 ep = qhp->ep; 1445 qhp->ep = NULL; 1446 set_state(qhp, C4IW_QP_STATE_ERROR); 1447 free = 1; 1448 abort = 1; 1449 BUG_ON(!ep); 1450 flush_qp(qhp); 1451 wake_up(&qhp->wait); 1452 out: 1453 mutex_unlock(&qhp->mutex); 1454 1455 if (terminate) 1456 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1457 1458 /* 1459 * If disconnect is 1, then we need to initiate a disconnect 1460 * on the EP. This can be a normal close (RTS->CLOSING) or 1461 * an abnormal close (RTS/CLOSING->ERROR). 1462 */ 1463 if (disconnect) { 1464 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1465 GFP_KERNEL); 1466 c4iw_put_ep(&ep->com); 1467 } 1468 1469 /* 1470 * If free is 1, then we've disassociated the EP from the QP 1471 * and we need to dereference the EP. 1472 */ 1473 if (free) 1474 c4iw_put_ep(&ep->com); 1475 CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state); 1476 return ret; 1477 } 1478 1479 int c4iw_destroy_qp(struct ib_qp *ib_qp) 1480 { 1481 struct c4iw_dev *rhp; 1482 struct c4iw_qp *qhp; 1483 struct c4iw_qp_attributes attrs; 1484 struct c4iw_ucontext *ucontext; 1485 1486 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp); 1487 qhp = to_c4iw_qp(ib_qp); 1488 rhp = qhp->rhp; 1489 1490 attrs.next_state = C4IW_QP_STATE_ERROR; 1491 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1492 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1493 else 1494 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1495 wait_event(qhp->wait, !qhp->ep); 1496 1497 spin_lock_irq(&rhp->lock); 1498 remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1499 spin_unlock_irq(&rhp->lock); 1500 atomic_dec(&qhp->refcnt); 1501 wait_event(qhp->wait, !atomic_read(&qhp->refcnt)); 1502 1503 ucontext = ib_qp->uobject ? 1504 to_c4iw_ucontext(ib_qp->uobject->context) : NULL; 1505 destroy_qp(&rhp->rdev, &qhp->wq, 1506 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1507 1508 CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp, 1509 qhp->wq.sq.qid); 1510 kfree(qhp); 1511 return 0; 1512 } 1513 1514 struct ib_qp * 1515 c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1516 struct ib_udata *udata) 1517 { 1518 struct c4iw_dev *rhp; 1519 struct c4iw_qp *qhp; 1520 struct c4iw_pd *php; 1521 struct c4iw_cq *schp; 1522 struct c4iw_cq *rchp; 1523 struct c4iw_create_qp_resp uresp; 1524 int sqsize, rqsize; 1525 struct c4iw_ucontext *ucontext; 1526 int ret; 1527 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4; 1528 1529 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 1530 1531 if (attrs->qp_type != IB_QPT_RC) 1532 return ERR_PTR(-EINVAL); 1533 1534 php = to_c4iw_pd(pd); 1535 rhp = php->rhp; 1536 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1537 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1538 if (!schp || !rchp) 1539 return ERR_PTR(-EINVAL); 1540 1541 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1542 return ERR_PTR(-EINVAL); 1543 1544 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16); 1545 if (rqsize > T4_MAX_RQ_SIZE) 1546 return ERR_PTR(-E2BIG); 1547 1548 sqsize = roundup(attrs->cap.max_send_wr + 1, 16); 1549 if (sqsize > T4_MAX_SQ_SIZE) 1550 return ERR_PTR(-E2BIG); 1551 1552 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1553 1554 1555 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1556 if (!qhp) 1557 return ERR_PTR(-ENOMEM); 1558 qhp->wq.sq.size = sqsize; 1559 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue; 1560 qhp->wq.rq.size = rqsize; 1561 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue; 1562 1563 if (ucontext) { 1564 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1565 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1566 } 1567 1568 CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu", 1569 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize); 1570 1571 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1572 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1573 if (ret) 1574 goto err1; 1575 1576 attrs->cap.max_recv_wr = rqsize - 1; 1577 attrs->cap.max_send_wr = sqsize - 1; 1578 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1579 1580 qhp->rhp = rhp; 1581 qhp->attr.pd = php->pdid; 1582 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1583 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1584 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1585 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1586 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1587 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1588 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1589 qhp->attr.state = C4IW_QP_STATE_IDLE; 1590 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1591 qhp->attr.enable_rdma_read = 1; 1592 qhp->attr.enable_rdma_write = 1; 1593 qhp->attr.enable_bind = 1; 1594 qhp->attr.max_ord = 1; 1595 qhp->attr.max_ird = 1; 1596 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR; 1597 spin_lock_init(&qhp->lock); 1598 mutex_init(&qhp->mutex); 1599 init_waitqueue_head(&qhp->wait); 1600 atomic_set(&qhp->refcnt, 1); 1601 1602 spin_lock_irq(&rhp->lock); 1603 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1604 spin_unlock_irq(&rhp->lock); 1605 if (ret) 1606 goto err2; 1607 1608 if (udata) { 1609 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL); 1610 if (!mm1) { 1611 ret = -ENOMEM; 1612 goto err3; 1613 } 1614 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL); 1615 if (!mm2) { 1616 ret = -ENOMEM; 1617 goto err4; 1618 } 1619 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL); 1620 if (!mm3) { 1621 ret = -ENOMEM; 1622 goto err5; 1623 } 1624 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL); 1625 if (!mm4) { 1626 ret = -ENOMEM; 1627 goto err6; 1628 } 1629 uresp.flags = 0; 1630 uresp.qid_mask = rhp->rdev.qpmask; 1631 uresp.sqid = qhp->wq.sq.qid; 1632 uresp.sq_size = qhp->wq.sq.size; 1633 uresp.sq_memsize = qhp->wq.sq.memsize; 1634 uresp.rqid = qhp->wq.rq.qid; 1635 uresp.rq_size = qhp->wq.rq.size; 1636 uresp.rq_memsize = qhp->wq.rq.memsize; 1637 spin_lock(&ucontext->mmap_lock); 1638 uresp.sq_key = ucontext->key; 1639 ucontext->key += PAGE_SIZE; 1640 uresp.rq_key = ucontext->key; 1641 ucontext->key += PAGE_SIZE; 1642 uresp.sq_db_gts_key = ucontext->key; 1643 ucontext->key += PAGE_SIZE; 1644 uresp.rq_db_gts_key = ucontext->key; 1645 ucontext->key += PAGE_SIZE; 1646 spin_unlock(&ucontext->mmap_lock); 1647 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1648 if (ret) 1649 goto err7; 1650 mm1->key = uresp.sq_key; 1651 mm1->addr = qhp->wq.sq.phys_addr; 1652 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1653 CTR4(KTR_IW_CXGBE, "%s mm1 %x, %x, %d", __func__, mm1->key, 1654 mm1->addr, mm1->len); 1655 insert_mmap(ucontext, mm1); 1656 mm2->key = uresp.rq_key; 1657 mm2->addr = vtophys(qhp->wq.rq.queue); 1658 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1659 CTR4(KTR_IW_CXGBE, "%s mm2 %x, %x, %d", __func__, mm2->key, 1660 mm2->addr, mm2->len); 1661 insert_mmap(ucontext, mm2); 1662 mm3->key = uresp.sq_db_gts_key; 1663 mm3->addr = qhp->wq.sq.udb; 1664 mm3->len = PAGE_SIZE; 1665 CTR4(KTR_IW_CXGBE, "%s mm3 %x, %x, %d", __func__, mm3->key, 1666 mm3->addr, mm3->len); 1667 insert_mmap(ucontext, mm3); 1668 mm4->key = uresp.rq_db_gts_key; 1669 mm4->addr = qhp->wq.rq.udb; 1670 mm4->len = PAGE_SIZE; 1671 CTR4(KTR_IW_CXGBE, "%s mm4 %x, %x, %d", __func__, mm4->key, 1672 mm4->addr, mm4->len); 1673 insert_mmap(ucontext, mm4); 1674 } 1675 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1676 init_timer(&(qhp->timer)); 1677 CTR5(KTR_IW_CXGBE, 1678 "%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x", 1679 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries, 1680 qhp->wq.sq.qid); 1681 return &qhp->ibqp; 1682 err7: 1683 kfree(mm4); 1684 err6: 1685 kfree(mm3); 1686 err5: 1687 kfree(mm2); 1688 err4: 1689 kfree(mm1); 1690 err3: 1691 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1692 err2: 1693 destroy_qp(&rhp->rdev, &qhp->wq, 1694 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1695 err1: 1696 kfree(qhp); 1697 return ERR_PTR(ret); 1698 } 1699 1700 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1701 int attr_mask, struct ib_udata *udata) 1702 { 1703 struct c4iw_dev *rhp; 1704 struct c4iw_qp *qhp; 1705 enum c4iw_qp_attr_mask mask = 0; 1706 struct c4iw_qp_attributes attrs; 1707 1708 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp); 1709 1710 /* iwarp does not support the RTR state */ 1711 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1712 attr_mask &= ~IB_QP_STATE; 1713 1714 /* Make sure we still have something left to do */ 1715 if (!attr_mask) 1716 return 0; 1717 1718 memset(&attrs, 0, sizeof attrs); 1719 qhp = to_c4iw_qp(ibqp); 1720 rhp = qhp->rhp; 1721 1722 attrs.next_state = c4iw_convert_state(attr->qp_state); 1723 attrs.enable_rdma_read = (attr->qp_access_flags & 1724 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1725 attrs.enable_rdma_write = (attr->qp_access_flags & 1726 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1727 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1728 1729 1730 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1731 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1732 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1733 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1734 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1735 1736 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1737 } 1738 1739 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1740 { 1741 CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn); 1742 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1743 } 1744 1745 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1746 int attr_mask, struct ib_qp_init_attr *init_attr) 1747 { 1748 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1749 1750 memset(attr, 0, sizeof *attr); 1751 memset(init_attr, 0, sizeof *init_attr); 1752 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1753 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries; 1754 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries; 1755 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges; 1756 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges; 1757 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE; 1758 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0; 1759 return 0; 1760 } 1761 #endif 1762