1 /* 2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_inet.h" 36 37 #ifdef TCP_OFFLOAD 38 #include <sys/types.h> 39 #include <sys/malloc.h> 40 #include <sys/socket.h> 41 #include <sys/socketvar.h> 42 #include <sys/sockio.h> 43 #include <sys/taskqueue.h> 44 #include <netinet/in.h> 45 #include <net/neighbour.h> 46 #include <net/route.h> 47 48 #include <netinet/in_systm.h> 49 #include <netinet/in_pcb.h> 50 #include <netinet/ip.h> 51 #include <netinet/ip_var.h> 52 #include <netinet/tcp_var.h> 53 #include <netinet/tcp.h> 54 #include <netinet/tcpip.h> 55 56 #include <netinet/toecore.h> 57 58 struct sge_iq; 59 struct rss_header; 60 #include <linux/types.h> 61 #include "offload.h" 62 #include "tom/t4_tom.h" 63 64 #include "iw_cxgbe.h" 65 #include "user.h" 66 67 extern int db_delay_usecs; 68 extern int db_fc_threshold; 69 static void creds(struct toepcb *toep, size_t wrsize); 70 71 72 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 73 { 74 unsigned long flag; 75 spin_lock_irqsave(&qhp->lock, flag); 76 qhp->attr.state = state; 77 spin_unlock_irqrestore(&qhp->lock, flag); 78 } 79 80 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 81 { 82 83 contigfree(sq->queue, sq->memsize, M_DEVBUF); 84 } 85 86 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 87 { 88 89 dealloc_host_sq(rdev, sq); 90 } 91 92 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 93 { 94 sq->queue = contigmalloc(sq->memsize, M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 95 4096, 0); 96 97 if (sq->queue) 98 sq->dma_addr = vtophys(sq->queue); 99 else 100 return -ENOMEM; 101 sq->phys_addr = vtophys(sq->queue); 102 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 103 CTR4(KTR_IW_CXGBE, "%s sq %p dma_addr %p phys_addr %p", __func__, 104 sq->queue, sq->dma_addr, sq->phys_addr); 105 return 0; 106 } 107 108 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 109 struct c4iw_dev_ucontext *uctx) 110 { 111 /* 112 * uP clears EQ contexts when the connection exits rdma mode, 113 * so no need to post a RESET WR for these EQs. 114 */ 115 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 116 dealloc_sq(rdev, &wq->sq); 117 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 118 kfree(wq->rq.sw_rq); 119 kfree(wq->sq.sw_sq); 120 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 121 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 122 return 0; 123 } 124 125 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 126 struct t4_cq *rcq, struct t4_cq *scq, 127 struct c4iw_dev_ucontext *uctx) 128 { 129 struct adapter *sc = rdev->adap; 130 int user = (uctx != &rdev->uctx); 131 struct fw_ri_res_wr *res_wr; 132 struct fw_ri_res *res; 133 int wr_len; 134 struct c4iw_wr_wait wr_wait; 135 int ret; 136 int eqsize; 137 struct wrqe *wr; 138 139 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 140 if (!wq->sq.qid) 141 return -ENOMEM; 142 143 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 144 if (!wq->rq.qid) 145 goto err1; 146 147 if (!user) { 148 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 149 GFP_KERNEL); 150 if (!wq->sq.sw_sq) 151 goto err2; 152 153 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 154 GFP_KERNEL); 155 if (!wq->rq.sw_rq) 156 goto err3; 157 } 158 159 /* RQT must be a power of 2. */ 160 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size); 161 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 162 if (!wq->rq.rqt_hwaddr) 163 goto err4; 164 165 if (alloc_host_sq(rdev, &wq->sq)) 166 goto err5; 167 168 memset(wq->sq.queue, 0, wq->sq.memsize); 169 pci_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 170 171 wq->rq.queue = contigmalloc(wq->rq.memsize, 172 M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 4096, 0); 173 if (wq->rq.queue) 174 wq->rq.dma_addr = vtophys(wq->rq.queue); 175 else 176 goto err6; 177 CTR5(KTR_IW_CXGBE, 178 "%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx", __func__, 179 wq->sq.queue, (unsigned long long)vtophys(wq->sq.queue), 180 wq->rq.queue, (unsigned long long)vtophys(wq->rq.queue)); 181 memset(wq->rq.queue, 0, wq->rq.memsize); 182 pci_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 183 184 wq->db = (void *)((unsigned long)rman_get_virtual(sc->regs_res) + 185 MYPF_REG(SGE_PF_KDOORBELL)); 186 wq->gts = (void *)((unsigned long)rman_get_virtual(rdev->adap->regs_res) 187 + MYPF_REG(SGE_PF_GTS)); 188 if (user) { 189 wq->sq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 190 (wq->sq.qid << rdev->qpshift)); 191 wq->sq.udb &= PAGE_MASK; 192 wq->rq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 193 (wq->rq.qid << rdev->qpshift)); 194 wq->rq.udb &= PAGE_MASK; 195 } 196 wq->rdev = rdev; 197 wq->rq.msn = 1; 198 199 /* build fw_ri_res_wr */ 200 wr_len = sizeof *res_wr + 2 * sizeof *res; 201 202 wr = alloc_wrqe(wr_len, &sc->sge.mgmtq); 203 if (wr == NULL) 204 return (0); 205 res_wr = wrtod(wr); 206 207 memset(res_wr, 0, wr_len); 208 res_wr->op_nres = cpu_to_be32( 209 V_FW_WR_OP(FW_RI_RES_WR) | 210 V_FW_RI_RES_WR_NRES(2) | 211 F_FW_WR_COMPL); 212 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 213 res_wr->cookie = (unsigned long) &wr_wait; 214 res = res_wr->res; 215 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 216 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 217 218 /* eqsize is the number of 64B entries plus the status page size. */ 219 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + spg_creds; 220 221 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 222 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 223 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 224 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 225 V_FW_RI_RES_WR_IQID(scq->cqid)); 226 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 227 V_FW_RI_RES_WR_DCAEN(0) | 228 V_FW_RI_RES_WR_DCACPU(0) | 229 V_FW_RI_RES_WR_FBMIN(2) | 230 V_FW_RI_RES_WR_FBMAX(2) | 231 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 232 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 233 V_FW_RI_RES_WR_EQSIZE(eqsize)); 234 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 235 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 236 res++; 237 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 238 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 239 240 /* eqsize is the number of 64B entries plus the status page size. */ 241 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + spg_creds ; 242 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 243 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 244 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 245 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 246 V_FW_RI_RES_WR_IQID(rcq->cqid)); 247 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 248 V_FW_RI_RES_WR_DCAEN(0) | 249 V_FW_RI_RES_WR_DCACPU(0) | 250 V_FW_RI_RES_WR_FBMIN(2) | 251 V_FW_RI_RES_WR_FBMAX(2) | 252 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 253 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 254 V_FW_RI_RES_WR_EQSIZE(eqsize)); 255 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 256 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 257 258 c4iw_init_wr_wait(&wr_wait); 259 260 t4_wrq_tx(sc, wr); 261 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); 262 if (ret) 263 goto err7; 264 265 CTR6(KTR_IW_CXGBE, 266 "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx", 267 __func__, wq->sq.qid, wq->rq.qid, wq->db, 268 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb); 269 270 return 0; 271 err7: 272 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 273 err6: 274 dealloc_sq(rdev, &wq->sq); 275 err5: 276 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 277 err4: 278 kfree(wq->rq.sw_rq); 279 err3: 280 kfree(wq->sq.sw_sq); 281 err2: 282 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 283 err1: 284 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 285 return -ENOMEM; 286 } 287 288 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 289 struct ib_send_wr *wr, int max, u32 *plenp) 290 { 291 u8 *dstp, *srcp; 292 u32 plen = 0; 293 int i; 294 int rem, len; 295 296 dstp = (u8 *)immdp->data; 297 for (i = 0; i < wr->num_sge; i++) { 298 if ((plen + wr->sg_list[i].length) > max) 299 return -EMSGSIZE; 300 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 301 plen += wr->sg_list[i].length; 302 rem = wr->sg_list[i].length; 303 while (rem) { 304 if (dstp == (u8 *)&sq->queue[sq->size]) 305 dstp = (u8 *)sq->queue; 306 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 307 len = rem; 308 else 309 len = (u8 *)&sq->queue[sq->size] - dstp; 310 memcpy(dstp, srcp, len); 311 dstp += len; 312 srcp += len; 313 rem -= len; 314 } 315 } 316 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 317 if (len) 318 memset(dstp, 0, len); 319 immdp->op = FW_RI_DATA_IMMD; 320 immdp->r1 = 0; 321 immdp->r2 = 0; 322 immdp->immdlen = cpu_to_be32(plen); 323 *plenp = plen; 324 return 0; 325 } 326 327 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 328 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 329 int num_sge, u32 *plenp) 330 331 { 332 int i; 333 u32 plen = 0; 334 __be64 *flitp = (__be64 *)isglp->sge; 335 336 for (i = 0; i < num_sge; i++) { 337 if ((plen + sg_list[i].length) < plen) 338 return -EMSGSIZE; 339 plen += sg_list[i].length; 340 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 341 sg_list[i].length); 342 if (++flitp == queue_end) 343 flitp = queue_start; 344 *flitp = cpu_to_be64(sg_list[i].addr); 345 if (++flitp == queue_end) 346 flitp = queue_start; 347 } 348 *flitp = (__force __be64)0; 349 isglp->op = FW_RI_DATA_ISGL; 350 isglp->r1 = 0; 351 isglp->nsge = cpu_to_be16(num_sge); 352 isglp->r2 = 0; 353 if (plenp) 354 *plenp = plen; 355 return 0; 356 } 357 358 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 359 struct ib_send_wr *wr, u8 *len16) 360 { 361 u32 plen; 362 int size; 363 int ret; 364 365 if (wr->num_sge > T4_MAX_SEND_SGE) 366 return -EINVAL; 367 switch (wr->opcode) { 368 case IB_WR_SEND: 369 if (wr->send_flags & IB_SEND_SOLICITED) 370 wqe->send.sendop_pkd = cpu_to_be32( 371 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); 372 else 373 wqe->send.sendop_pkd = cpu_to_be32( 374 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); 375 wqe->send.stag_inv = 0; 376 break; 377 case IB_WR_SEND_WITH_INV: 378 if (wr->send_flags & IB_SEND_SOLICITED) 379 wqe->send.sendop_pkd = cpu_to_be32( 380 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV)); 381 else 382 wqe->send.sendop_pkd = cpu_to_be32( 383 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV)); 384 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 385 break; 386 387 default: 388 return -EINVAL; 389 } 390 391 plen = 0; 392 if (wr->num_sge) { 393 if (wr->send_flags & IB_SEND_INLINE) { 394 ret = build_immd(sq, wqe->send.u.immd_src, wr, 395 T4_MAX_SEND_INLINE, &plen); 396 if (ret) 397 return ret; 398 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 399 plen; 400 } else { 401 ret = build_isgl((__be64 *)sq->queue, 402 (__be64 *)&sq->queue[sq->size], 403 wqe->send.u.isgl_src, 404 wr->sg_list, wr->num_sge, &plen); 405 if (ret) 406 return ret; 407 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 408 wr->num_sge * sizeof(struct fw_ri_sge); 409 } 410 } else { 411 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 412 wqe->send.u.immd_src[0].r1 = 0; 413 wqe->send.u.immd_src[0].r2 = 0; 414 wqe->send.u.immd_src[0].immdlen = 0; 415 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 416 plen = 0; 417 } 418 *len16 = DIV_ROUND_UP(size, 16); 419 wqe->send.plen = cpu_to_be32(plen); 420 return 0; 421 } 422 423 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 424 struct ib_send_wr *wr, u8 *len16) 425 { 426 u32 plen; 427 int size; 428 int ret; 429 430 if (wr->num_sge > T4_MAX_SEND_SGE) 431 return -EINVAL; 432 wqe->write.r2 = 0; 433 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey); 434 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr); 435 if (wr->num_sge) { 436 if (wr->send_flags & IB_SEND_INLINE) { 437 ret = build_immd(sq, wqe->write.u.immd_src, wr, 438 T4_MAX_WRITE_INLINE, &plen); 439 if (ret) 440 return ret; 441 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 442 plen; 443 } else { 444 ret = build_isgl((__be64 *)sq->queue, 445 (__be64 *)&sq->queue[sq->size], 446 wqe->write.u.isgl_src, 447 wr->sg_list, wr->num_sge, &plen); 448 if (ret) 449 return ret; 450 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 451 wr->num_sge * sizeof(struct fw_ri_sge); 452 } 453 } else { 454 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 455 wqe->write.u.immd_src[0].r1 = 0; 456 wqe->write.u.immd_src[0].r2 = 0; 457 wqe->write.u.immd_src[0].immdlen = 0; 458 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 459 plen = 0; 460 } 461 *len16 = DIV_ROUND_UP(size, 16); 462 wqe->write.plen = cpu_to_be32(plen); 463 return 0; 464 } 465 466 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 467 { 468 if (wr->num_sge > 1) 469 return -EINVAL; 470 if (wr->num_sge) { 471 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey); 472 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr 473 >> 32)); 474 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr); 475 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 476 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 477 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 478 >> 32)); 479 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 480 } else { 481 wqe->read.stag_src = cpu_to_be32(2); 482 wqe->read.to_src_hi = 0; 483 wqe->read.to_src_lo = 0; 484 wqe->read.stag_sink = cpu_to_be32(2); 485 wqe->read.plen = 0; 486 wqe->read.to_sink_hi = 0; 487 wqe->read.to_sink_lo = 0; 488 } 489 wqe->read.r2 = 0; 490 wqe->read.r5 = 0; 491 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 492 return 0; 493 } 494 495 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 496 struct ib_recv_wr *wr, u8 *len16) 497 { 498 int ret; 499 500 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 501 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 502 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 503 if (ret) 504 return ret; 505 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 506 wr->num_sge * sizeof(struct fw_ri_sge), 16); 507 return 0; 508 } 509 510 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, 511 struct ib_send_wr *wr, u8 *len16) 512 { 513 514 struct fw_ri_immd *imdp; 515 __be64 *p; 516 int i; 517 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); 518 int rem; 519 520 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH) 521 return -EINVAL; 522 523 wqe->fr.qpbinde_to_dcacpu = 0; 524 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12; 525 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 526 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags); 527 wqe->fr.len_hi = 0; 528 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length); 529 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey); 530 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); 531 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & 532 0xffffffff); 533 WARN_ON(pbllen > T4_MAX_FR_IMMD); 534 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 535 imdp->op = FW_RI_DATA_IMMD; 536 imdp->r1 = 0; 537 imdp->r2 = 0; 538 imdp->immdlen = cpu_to_be32(pbllen); 539 p = (__be64 *)(imdp + 1); 540 rem = pbllen; 541 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { 542 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]); 543 rem -= sizeof *p; 544 if (++p == (__be64 *)&sq->queue[sq->size]) 545 p = (__be64 *)sq->queue; 546 } 547 BUG_ON(rem < 0); 548 while (rem) { 549 *p = 0; 550 rem -= sizeof *p; 551 if (++p == (__be64 *)&sq->queue[sq->size]) 552 p = (__be64 *)sq->queue; 553 } 554 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16); 555 return 0; 556 } 557 558 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, 559 u8 *len16) 560 { 561 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 562 wqe->inv.r2 = 0; 563 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 564 return 0; 565 } 566 567 void c4iw_qp_add_ref(struct ib_qp *qp) 568 { 569 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 570 atomic_inc(&(to_c4iw_qp(qp)->refcnt)); 571 } 572 573 void c4iw_qp_rem_ref(struct ib_qp *qp) 574 { 575 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 576 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt))) 577 wake_up(&(to_c4iw_qp(qp)->wait)); 578 } 579 580 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 581 struct ib_send_wr **bad_wr) 582 { 583 int err = 0; 584 u8 len16 = 0; 585 enum fw_wr_opcodes fw_opcode = 0; 586 enum fw_ri_wr_flags fw_flags; 587 struct c4iw_qp *qhp; 588 union t4_wr *wqe; 589 u32 num_wrs; 590 struct t4_swsqe *swsqe; 591 unsigned long flag; 592 u16 idx = 0; 593 594 qhp = to_c4iw_qp(ibqp); 595 spin_lock_irqsave(&qhp->lock, flag); 596 if (t4_wq_in_error(&qhp->wq)) { 597 spin_unlock_irqrestore(&qhp->lock, flag); 598 return -EINVAL; 599 } 600 num_wrs = t4_sq_avail(&qhp->wq); 601 if (num_wrs == 0) { 602 spin_unlock_irqrestore(&qhp->lock, flag); 603 return -ENOMEM; 604 } 605 while (wr) { 606 if (num_wrs == 0) { 607 err = -ENOMEM; 608 *bad_wr = wr; 609 break; 610 } 611 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 612 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 613 614 fw_flags = 0; 615 if (wr->send_flags & IB_SEND_SOLICITED) 616 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 617 if (wr->send_flags & IB_SEND_SIGNALED) 618 fw_flags |= FW_RI_COMPLETION_FLAG; 619 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 620 switch (wr->opcode) { 621 case IB_WR_SEND_WITH_INV: 622 case IB_WR_SEND: 623 if (wr->send_flags & IB_SEND_FENCE) 624 fw_flags |= FW_RI_READ_FENCE_FLAG; 625 fw_opcode = FW_RI_SEND_WR; 626 if (wr->opcode == IB_WR_SEND) 627 swsqe->opcode = FW_RI_SEND; 628 else 629 swsqe->opcode = FW_RI_SEND_WITH_INV; 630 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 631 break; 632 case IB_WR_RDMA_WRITE: 633 fw_opcode = FW_RI_RDMA_WRITE_WR; 634 swsqe->opcode = FW_RI_RDMA_WRITE; 635 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 636 break; 637 case IB_WR_RDMA_READ: 638 case IB_WR_RDMA_READ_WITH_INV: 639 fw_opcode = FW_RI_RDMA_READ_WR; 640 swsqe->opcode = FW_RI_READ_REQ; 641 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) 642 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 643 else 644 fw_flags = 0; 645 err = build_rdma_read(wqe, wr, &len16); 646 if (err) 647 break; 648 swsqe->read_len = wr->sg_list[0].length; 649 if (!qhp->wq.sq.oldest_read) 650 qhp->wq.sq.oldest_read = swsqe; 651 break; 652 case IB_WR_FAST_REG_MR: 653 fw_opcode = FW_RI_FR_NSMR_WR; 654 swsqe->opcode = FW_RI_FAST_REGISTER; 655 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16); 656 break; 657 case IB_WR_LOCAL_INV: 658 if (wr->send_flags & IB_SEND_FENCE) 659 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 660 fw_opcode = FW_RI_INV_LSTAG_WR; 661 swsqe->opcode = FW_RI_LOCAL_INV; 662 err = build_inv_stag(wqe, wr, &len16); 663 break; 664 default: 665 CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__, 666 wr->opcode); 667 err = -EINVAL; 668 } 669 if (err) { 670 *bad_wr = wr; 671 break; 672 } 673 swsqe->idx = qhp->wq.sq.pidx; 674 swsqe->complete = 0; 675 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED); 676 swsqe->wr_id = wr->wr_id; 677 678 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 679 680 CTR5(KTR_IW_CXGBE, 681 "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u", 682 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 683 swsqe->opcode, swsqe->read_len); 684 wr = wr->next; 685 num_wrs--; 686 t4_sq_produce(&qhp->wq, len16); 687 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 688 } 689 if (t4_wq_db_enabled(&qhp->wq)) 690 t4_ring_sq_db(&qhp->wq, idx); 691 spin_unlock_irqrestore(&qhp->lock, flag); 692 return err; 693 } 694 695 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 696 struct ib_recv_wr **bad_wr) 697 { 698 int err = 0; 699 struct c4iw_qp *qhp; 700 union t4_recv_wr *wqe; 701 u32 num_wrs; 702 u8 len16 = 0; 703 unsigned long flag; 704 u16 idx = 0; 705 706 qhp = to_c4iw_qp(ibqp); 707 spin_lock_irqsave(&qhp->lock, flag); 708 if (t4_wq_in_error(&qhp->wq)) { 709 spin_unlock_irqrestore(&qhp->lock, flag); 710 return -EINVAL; 711 } 712 num_wrs = t4_rq_avail(&qhp->wq); 713 if (num_wrs == 0) { 714 spin_unlock_irqrestore(&qhp->lock, flag); 715 return -ENOMEM; 716 } 717 while (wr) { 718 if (wr->num_sge > T4_MAX_RECV_SGE) { 719 err = -EINVAL; 720 *bad_wr = wr; 721 break; 722 } 723 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 724 qhp->wq.rq.wq_pidx * 725 T4_EQ_ENTRY_SIZE); 726 if (num_wrs) 727 err = build_rdma_recv(qhp, wqe, wr, &len16); 728 else 729 err = -ENOMEM; 730 if (err) { 731 *bad_wr = wr; 732 break; 733 } 734 735 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 736 737 wqe->recv.opcode = FW_RI_RECV_WR; 738 wqe->recv.r1 = 0; 739 wqe->recv.wrid = qhp->wq.rq.pidx; 740 wqe->recv.r2[0] = 0; 741 wqe->recv.r2[1] = 0; 742 wqe->recv.r2[2] = 0; 743 wqe->recv.len16 = len16; 744 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__, 745 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 746 t4_rq_produce(&qhp->wq, len16); 747 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 748 wr = wr->next; 749 num_wrs--; 750 } 751 if (t4_wq_db_enabled(&qhp->wq)) 752 t4_ring_rq_db(&qhp->wq, idx); 753 spin_unlock_irqrestore(&qhp->lock, flag); 754 return err; 755 } 756 757 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind) 758 { 759 return -ENOSYS; 760 } 761 762 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 763 u8 *ecode) 764 { 765 int status; 766 int tagged; 767 int opcode; 768 int rqtype; 769 int send_inv; 770 771 if (!err_cqe) { 772 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 773 *ecode = 0; 774 return; 775 } 776 777 status = CQE_STATUS(err_cqe); 778 opcode = CQE_OPCODE(err_cqe); 779 rqtype = RQ_TYPE(err_cqe); 780 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 781 (opcode == FW_RI_SEND_WITH_SE_INV); 782 tagged = (opcode == FW_RI_RDMA_WRITE) || 783 (rqtype && (opcode == FW_RI_READ_RESP)); 784 785 switch (status) { 786 case T4_ERR_STAG: 787 if (send_inv) { 788 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 789 *ecode = RDMAP_CANT_INV_STAG; 790 } else { 791 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 792 *ecode = RDMAP_INV_STAG; 793 } 794 break; 795 case T4_ERR_PDID: 796 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 797 if ((opcode == FW_RI_SEND_WITH_INV) || 798 (opcode == FW_RI_SEND_WITH_SE_INV)) 799 *ecode = RDMAP_CANT_INV_STAG; 800 else 801 *ecode = RDMAP_STAG_NOT_ASSOC; 802 break; 803 case T4_ERR_QPID: 804 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 805 *ecode = RDMAP_STAG_NOT_ASSOC; 806 break; 807 case T4_ERR_ACCESS: 808 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 809 *ecode = RDMAP_ACC_VIOL; 810 break; 811 case T4_ERR_WRAP: 812 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 813 *ecode = RDMAP_TO_WRAP; 814 break; 815 case T4_ERR_BOUND: 816 if (tagged) { 817 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 818 *ecode = DDPT_BASE_BOUNDS; 819 } else { 820 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 821 *ecode = RDMAP_BASE_BOUNDS; 822 } 823 break; 824 case T4_ERR_INVALIDATE_SHARED_MR: 825 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 826 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 827 *ecode = RDMAP_CANT_INV_STAG; 828 break; 829 case T4_ERR_ECC: 830 case T4_ERR_ECC_PSTAG: 831 case T4_ERR_INTERNAL_ERR: 832 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 833 *ecode = 0; 834 break; 835 case T4_ERR_OUT_OF_RQE: 836 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 837 *ecode = DDPU_INV_MSN_NOBUF; 838 break; 839 case T4_ERR_PBL_ADDR_BOUND: 840 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 841 *ecode = DDPT_BASE_BOUNDS; 842 break; 843 case T4_ERR_CRC: 844 *layer_type = LAYER_MPA|DDP_LLP; 845 *ecode = MPA_CRC_ERR; 846 break; 847 case T4_ERR_MARKER: 848 *layer_type = LAYER_MPA|DDP_LLP; 849 *ecode = MPA_MARKER_ERR; 850 break; 851 case T4_ERR_PDU_LEN_ERR: 852 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 853 *ecode = DDPU_MSG_TOOBIG; 854 break; 855 case T4_ERR_DDP_VERSION: 856 if (tagged) { 857 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 858 *ecode = DDPT_INV_VERS; 859 } else { 860 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 861 *ecode = DDPU_INV_VERS; 862 } 863 break; 864 case T4_ERR_RDMA_VERSION: 865 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 866 *ecode = RDMAP_INV_VERS; 867 break; 868 case T4_ERR_OPCODE: 869 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 870 *ecode = RDMAP_INV_OPCODE; 871 break; 872 case T4_ERR_DDP_QUEUE_NUM: 873 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 874 *ecode = DDPU_INV_QN; 875 break; 876 case T4_ERR_MSN: 877 case T4_ERR_MSN_GAP: 878 case T4_ERR_MSN_RANGE: 879 case T4_ERR_IRD_OVERFLOW: 880 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 881 *ecode = DDPU_INV_MSN_RANGE; 882 break; 883 case T4_ERR_TBIT: 884 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 885 *ecode = 0; 886 break; 887 case T4_ERR_MO: 888 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 889 *ecode = DDPU_INV_MO; 890 break; 891 default: 892 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 893 *ecode = 0; 894 break; 895 } 896 } 897 898 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 899 gfp_t gfp) 900 { 901 struct fw_ri_wr *wqe; 902 struct terminate_message *term; 903 struct wrqe *wr; 904 struct socket *so = qhp->ep->com.so; 905 struct inpcb *inp = sotoinpcb(so); 906 struct tcpcb *tp = intotcpcb(inp); 907 struct toepcb *toep = tp->t_toe; 908 909 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 910 qhp->wq.sq.qid, qhp->ep->hwtid); 911 912 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 913 if (wr == NULL) 914 return; 915 wqe = wrtod(wr); 916 917 memset(wqe, 0, sizeof *wqe); 918 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR)); 919 wqe->flowid_len16 = cpu_to_be32( 920 V_FW_WR_FLOWID(qhp->ep->hwtid) | 921 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 922 923 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 924 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 925 term = (struct terminate_message *)wqe->u.terminate.termmsg; 926 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 927 term->layer_etype = qhp->attr.layer_etype; 928 term->ecode = qhp->attr.ecode; 929 } else 930 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 931 creds(toep, sizeof(*wqe)); 932 t4_wrq_tx(qhp->rhp->rdev.adap, wr); 933 } 934 935 /* Assumes qhp lock is held. */ 936 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 937 struct c4iw_cq *schp) 938 { 939 int count; 940 int flushed; 941 unsigned long flag; 942 943 CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp, 944 schp); 945 946 /* locking hierarchy: cq lock first, then qp lock. */ 947 spin_lock_irqsave(&rchp->lock, flag); 948 spin_lock(&qhp->lock); 949 c4iw_flush_hw_cq(&rchp->cq); 950 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 951 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 952 spin_unlock(&qhp->lock); 953 spin_unlock_irqrestore(&rchp->lock, flag); 954 if (flushed) { 955 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 956 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 957 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 958 } 959 960 /* locking hierarchy: cq lock first, then qp lock. */ 961 spin_lock_irqsave(&schp->lock, flag); 962 spin_lock(&qhp->lock); 963 c4iw_flush_hw_cq(&schp->cq); 964 c4iw_count_scqes(&schp->cq, &qhp->wq, &count); 965 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count); 966 spin_unlock(&qhp->lock); 967 spin_unlock_irqrestore(&schp->lock, flag); 968 if (flushed) { 969 spin_lock_irqsave(&schp->comp_handler_lock, flag); 970 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context); 971 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 972 } 973 } 974 975 static void flush_qp(struct c4iw_qp *qhp) 976 { 977 struct c4iw_cq *rchp, *schp; 978 unsigned long flag; 979 980 rchp = get_chp(qhp->rhp, qhp->attr.rcq); 981 schp = get_chp(qhp->rhp, qhp->attr.scq); 982 983 if (qhp->ibqp.uobject) { 984 t4_set_wq_in_error(&qhp->wq); 985 t4_set_cq_in_error(&rchp->cq); 986 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 987 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 988 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 989 if (schp != rchp) { 990 t4_set_cq_in_error(&schp->cq); 991 spin_lock_irqsave(&schp->comp_handler_lock, flag); 992 (*schp->ibcq.comp_handler)(&schp->ibcq, 993 schp->ibcq.cq_context); 994 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 995 } 996 return; 997 } 998 __flush_qp(qhp, rchp, schp); 999 } 1000 1001 static int 1002 rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep) 1003 { 1004 struct c4iw_rdev *rdev = &rhp->rdev; 1005 struct adapter *sc = rdev->adap; 1006 struct fw_ri_wr *wqe; 1007 int ret; 1008 struct wrqe *wr; 1009 struct socket *so = ep->com.so; 1010 struct inpcb *inp = sotoinpcb(so); 1011 struct tcpcb *tp = intotcpcb(inp); 1012 struct toepcb *toep = tp->t_toe; 1013 1014 KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__)); 1015 1016 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1017 qhp->wq.sq.qid, ep->hwtid); 1018 1019 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1020 if (wr == NULL) 1021 return (0); 1022 wqe = wrtod(wr); 1023 1024 memset(wqe, 0, sizeof *wqe); 1025 1026 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL); 1027 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1028 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1029 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1030 wqe->u.fini.type = FW_RI_TYPE_FINI; 1031 1032 c4iw_init_wr_wait(&ep->com.wr_wait); 1033 1034 creds(toep, sizeof(*wqe)); 1035 t4_wrq_tx(sc, wr); 1036 1037 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1038 qhp->wq.sq.qid, __func__); 1039 return ret; 1040 } 1041 1042 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1043 { 1044 CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type); 1045 memset(&init->u, 0, sizeof init->u); 1046 switch (p2p_type) { 1047 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1048 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1049 init->u.write.stag_sink = cpu_to_be32(1); 1050 init->u.write.to_sink = cpu_to_be64(1); 1051 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1052 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1053 sizeof(struct fw_ri_immd), 1054 16); 1055 break; 1056 case FW_RI_INIT_P2PTYPE_READ_REQ: 1057 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1058 init->u.read.stag_src = cpu_to_be32(1); 1059 init->u.read.to_src_lo = cpu_to_be32(1); 1060 init->u.read.stag_sink = cpu_to_be32(1); 1061 init->u.read.to_sink_lo = cpu_to_be32(1); 1062 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1063 break; 1064 } 1065 } 1066 1067 static void 1068 creds(struct toepcb *toep, size_t wrsize) 1069 { 1070 struct ofld_tx_sdesc *txsd; 1071 1072 CTR3(KTR_IW_CXGBE, "%s:creB %p %u", __func__, toep , wrsize); 1073 INP_WLOCK(toep->inp); 1074 txsd = &toep->txsd[toep->txsd_pidx]; 1075 txsd->tx_credits = howmany(wrsize, 16); 1076 txsd->plen = 0; 1077 KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0, 1078 ("%s: not enough credits (%d)", __func__, toep->tx_credits)); 1079 toep->tx_credits -= txsd->tx_credits; 1080 if (__predict_false(++toep->txsd_pidx == toep->txsd_total)) 1081 toep->txsd_pidx = 0; 1082 toep->txsd_avail--; 1083 INP_WUNLOCK(toep->inp); 1084 CTR5(KTR_IW_CXGBE, "%s:creE %p %u %u %u", __func__, toep , 1085 txsd->tx_credits, toep->tx_credits, toep->txsd_pidx); 1086 } 1087 1088 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1089 { 1090 struct fw_ri_wr *wqe; 1091 int ret; 1092 struct wrqe *wr; 1093 struct c4iw_ep *ep = qhp->ep; 1094 struct c4iw_rdev *rdev = &qhp->rhp->rdev; 1095 struct adapter *sc = rdev->adap; 1096 struct socket *so = ep->com.so; 1097 struct inpcb *inp = sotoinpcb(so); 1098 struct tcpcb *tp = intotcpcb(inp); 1099 struct toepcb *toep = tp->t_toe; 1100 1101 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1102 qhp->wq.sq.qid, ep->hwtid); 1103 1104 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1105 if (wr == NULL) 1106 return (0); 1107 wqe = wrtod(wr); 1108 1109 memset(wqe, 0, sizeof *wqe); 1110 1111 wqe->op_compl = cpu_to_be32( 1112 V_FW_WR_OP(FW_RI_WR) | 1113 F_FW_WR_COMPL); 1114 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1115 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1116 1117 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1118 1119 wqe->u.init.type = FW_RI_TYPE_INIT; 1120 wqe->u.init.mpareqbit_p2ptype = 1121 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) | 1122 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type); 1123 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1124 if (qhp->attr.mpa_attr.recv_marker_enabled) 1125 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1126 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1127 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1128 if (qhp->attr.mpa_attr.crc_enabled) 1129 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1130 1131 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1132 FW_RI_QP_RDMA_WRITE_ENABLE | 1133 FW_RI_QP_BIND_ENABLE; 1134 if (!qhp->ibqp.uobject) 1135 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1136 FW_RI_QP_STAG0_ENABLE; 1137 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1138 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1139 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1140 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1141 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1142 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1143 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1144 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1145 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1146 wqe->u.init.iss = cpu_to_be32(ep->snd_seq); 1147 wqe->u.init.irs = cpu_to_be32(ep->rcv_seq); 1148 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1149 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1150 sc->vres.rq.start); 1151 if (qhp->attr.mpa_attr.initiator) 1152 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1153 1154 c4iw_init_wr_wait(&ep->com.wr_wait); 1155 1156 creds(toep, sizeof(*wqe)); 1157 t4_wrq_tx(sc, wr); 1158 1159 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1160 qhp->wq.sq.qid, __func__); 1161 1162 toep->ulp_mode = ULP_MODE_RDMA; 1163 1164 return ret; 1165 } 1166 1167 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1168 enum c4iw_qp_attr_mask mask, 1169 struct c4iw_qp_attributes *attrs, 1170 int internal) 1171 { 1172 int ret = 0; 1173 struct c4iw_qp_attributes newattr = qhp->attr; 1174 int disconnect = 0; 1175 int terminate = 0; 1176 int abort = 0; 1177 int free = 0; 1178 struct c4iw_ep *ep = NULL; 1179 1180 CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp, 1181 qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep); 1182 CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state, 1183 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1184 1185 mutex_lock(&qhp->mutex); 1186 1187 /* Process attr changes if in IDLE */ 1188 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1189 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1190 ret = -EIO; 1191 goto out; 1192 } 1193 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1194 newattr.enable_rdma_read = attrs->enable_rdma_read; 1195 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1196 newattr.enable_rdma_write = attrs->enable_rdma_write; 1197 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1198 newattr.enable_bind = attrs->enable_bind; 1199 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1200 if (attrs->max_ord > c4iw_max_read_depth) { 1201 ret = -EINVAL; 1202 goto out; 1203 } 1204 newattr.max_ord = attrs->max_ord; 1205 } 1206 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1207 if (attrs->max_ird > c4iw_max_read_depth) { 1208 ret = -EINVAL; 1209 goto out; 1210 } 1211 newattr.max_ird = attrs->max_ird; 1212 } 1213 qhp->attr = newattr; 1214 } 1215 1216 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1217 goto out; 1218 if (qhp->attr.state == attrs->next_state) 1219 goto out; 1220 1221 switch (qhp->attr.state) { 1222 case C4IW_QP_STATE_IDLE: 1223 switch (attrs->next_state) { 1224 case C4IW_QP_STATE_RTS: 1225 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1226 ret = -EINVAL; 1227 goto out; 1228 } 1229 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1230 ret = -EINVAL; 1231 goto out; 1232 } 1233 qhp->attr.mpa_attr = attrs->mpa_attr; 1234 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1235 qhp->ep = qhp->attr.llp_stream_handle; 1236 set_state(qhp, C4IW_QP_STATE_RTS); 1237 1238 /* 1239 * Ref the endpoint here and deref when we 1240 * disassociate the endpoint from the QP. This 1241 * happens in CLOSING->IDLE transition or *->ERROR 1242 * transition. 1243 */ 1244 c4iw_get_ep(&qhp->ep->com); 1245 ret = rdma_init(rhp, qhp); 1246 if (ret) 1247 goto err; 1248 break; 1249 case C4IW_QP_STATE_ERROR: 1250 set_state(qhp, C4IW_QP_STATE_ERROR); 1251 flush_qp(qhp); 1252 break; 1253 default: 1254 ret = -EINVAL; 1255 goto out; 1256 } 1257 break; 1258 case C4IW_QP_STATE_RTS: 1259 switch (attrs->next_state) { 1260 case C4IW_QP_STATE_CLOSING: 1261 //Fixme: Use atomic_read as same as Linux 1262 BUG_ON(qhp->ep->com.kref.count < 2); 1263 set_state(qhp, C4IW_QP_STATE_CLOSING); 1264 ep = qhp->ep; 1265 if (!internal) { 1266 abort = 0; 1267 disconnect = 1; 1268 c4iw_get_ep(&qhp->ep->com); 1269 } 1270 if (qhp->ibqp.uobject) 1271 t4_set_wq_in_error(&qhp->wq); 1272 ret = rdma_fini(rhp, qhp, ep); 1273 if (ret) 1274 goto err; 1275 break; 1276 case C4IW_QP_STATE_TERMINATE: 1277 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1278 qhp->attr.layer_etype = attrs->layer_etype; 1279 qhp->attr.ecode = attrs->ecode; 1280 if (qhp->ibqp.uobject) 1281 t4_set_wq_in_error(&qhp->wq); 1282 ep = qhp->ep; 1283 if (!internal) 1284 terminate = 1; 1285 disconnect = 1; 1286 c4iw_get_ep(&qhp->ep->com); 1287 break; 1288 case C4IW_QP_STATE_ERROR: 1289 set_state(qhp, C4IW_QP_STATE_ERROR); 1290 if (qhp->ibqp.uobject) 1291 t4_set_wq_in_error(&qhp->wq); 1292 if (!internal) { 1293 abort = 1; 1294 disconnect = 1; 1295 ep = qhp->ep; 1296 c4iw_get_ep(&qhp->ep->com); 1297 } 1298 goto err; 1299 break; 1300 default: 1301 ret = -EINVAL; 1302 goto out; 1303 } 1304 break; 1305 case C4IW_QP_STATE_CLOSING: 1306 if (!internal) { 1307 ret = -EINVAL; 1308 goto out; 1309 } 1310 switch (attrs->next_state) { 1311 case C4IW_QP_STATE_IDLE: 1312 flush_qp(qhp); 1313 set_state(qhp, C4IW_QP_STATE_IDLE); 1314 qhp->attr.llp_stream_handle = NULL; 1315 c4iw_put_ep(&qhp->ep->com); 1316 qhp->ep = NULL; 1317 wake_up(&qhp->wait); 1318 break; 1319 case C4IW_QP_STATE_ERROR: 1320 goto err; 1321 default: 1322 ret = -EINVAL; 1323 goto err; 1324 } 1325 break; 1326 case C4IW_QP_STATE_ERROR: 1327 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1328 ret = -EINVAL; 1329 goto out; 1330 } 1331 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1332 ret = -EINVAL; 1333 goto out; 1334 } 1335 set_state(qhp, C4IW_QP_STATE_IDLE); 1336 break; 1337 case C4IW_QP_STATE_TERMINATE: 1338 if (!internal) { 1339 ret = -EINVAL; 1340 goto out; 1341 } 1342 goto err; 1343 break; 1344 default: 1345 printf("%s in a bad state %d\n", 1346 __func__, qhp->attr.state); 1347 ret = -EINVAL; 1348 goto err; 1349 break; 1350 } 1351 goto out; 1352 err: 1353 CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__, 1354 qhp->ep, qhp->wq.sq.qid); 1355 1356 /* disassociate the LLP connection */ 1357 qhp->attr.llp_stream_handle = NULL; 1358 if (!ep) 1359 ep = qhp->ep; 1360 qhp->ep = NULL; 1361 set_state(qhp, C4IW_QP_STATE_ERROR); 1362 free = 1; 1363 wake_up(&qhp->wait); 1364 BUG_ON(!ep); 1365 flush_qp(qhp); 1366 out: 1367 mutex_unlock(&qhp->mutex); 1368 1369 if (terminate) 1370 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1371 1372 /* 1373 * If disconnect is 1, then we need to initiate a disconnect 1374 * on the EP. This can be a normal close (RTS->CLOSING) or 1375 * an abnormal close (RTS/CLOSING->ERROR). 1376 */ 1377 if (disconnect) { 1378 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1379 GFP_KERNEL); 1380 c4iw_put_ep(&ep->com); 1381 } 1382 1383 /* 1384 * If free is 1, then we've disassociated the EP from the QP 1385 * and we need to dereference the EP. 1386 */ 1387 if (free) 1388 c4iw_put_ep(&ep->com); 1389 CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state); 1390 return ret; 1391 } 1392 1393 static int enable_qp_db(int id, void *p, void *data) 1394 { 1395 struct c4iw_qp *qp = p; 1396 1397 t4_enable_wq_db(&qp->wq); 1398 return 0; 1399 } 1400 1401 int c4iw_destroy_qp(struct ib_qp *ib_qp) 1402 { 1403 struct c4iw_dev *rhp; 1404 struct c4iw_qp *qhp; 1405 struct c4iw_qp_attributes attrs; 1406 struct c4iw_ucontext *ucontext; 1407 1408 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp); 1409 qhp = to_c4iw_qp(ib_qp); 1410 rhp = qhp->rhp; 1411 1412 attrs.next_state = C4IW_QP_STATE_ERROR; 1413 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1414 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1415 else 1416 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1417 wait_event(qhp->wait, !qhp->ep); 1418 1419 spin_lock_irq(&rhp->lock); 1420 remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1421 rhp->qpcnt--; 1422 BUG_ON(rhp->qpcnt < 0); 1423 if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) { 1424 rhp->rdev.stats.db_state_transitions++; 1425 rhp->db_state = NORMAL; 1426 idr_for_each(&rhp->qpidr, enable_qp_db, NULL); 1427 } 1428 spin_unlock_irq(&rhp->lock); 1429 atomic_dec(&qhp->refcnt); 1430 wait_event(qhp->wait, !atomic_read(&qhp->refcnt)); 1431 1432 ucontext = ib_qp->uobject ? 1433 to_c4iw_ucontext(ib_qp->uobject->context) : NULL; 1434 destroy_qp(&rhp->rdev, &qhp->wq, 1435 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1436 1437 CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp, 1438 qhp->wq.sq.qid); 1439 kfree(qhp); 1440 return 0; 1441 } 1442 1443 static int disable_qp_db(int id, void *p, void *data) 1444 { 1445 struct c4iw_qp *qp = p; 1446 1447 t4_disable_wq_db(&qp->wq); 1448 return 0; 1449 } 1450 1451 struct ib_qp * 1452 c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1453 struct ib_udata *udata) 1454 { 1455 struct c4iw_dev *rhp; 1456 struct c4iw_qp *qhp; 1457 struct c4iw_pd *php; 1458 struct c4iw_cq *schp; 1459 struct c4iw_cq *rchp; 1460 struct c4iw_create_qp_resp uresp; 1461 int sqsize, rqsize; 1462 struct c4iw_ucontext *ucontext; 1463 int ret; 1464 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4; 1465 1466 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 1467 1468 if (attrs->qp_type != IB_QPT_RC) 1469 return ERR_PTR(-EINVAL); 1470 1471 php = to_c4iw_pd(pd); 1472 rhp = php->rhp; 1473 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1474 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1475 if (!schp || !rchp) 1476 return ERR_PTR(-EINVAL); 1477 1478 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1479 return ERR_PTR(-EINVAL); 1480 1481 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16); 1482 if (rqsize > T4_MAX_RQ_SIZE) 1483 return ERR_PTR(-E2BIG); 1484 1485 sqsize = roundup(attrs->cap.max_send_wr + 1, 16); 1486 if (sqsize > T4_MAX_SQ_SIZE) 1487 return ERR_PTR(-E2BIG); 1488 1489 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1490 1491 1492 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1493 if (!qhp) 1494 return ERR_PTR(-ENOMEM); 1495 qhp->wq.sq.size = sqsize; 1496 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue; 1497 qhp->wq.rq.size = rqsize; 1498 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue; 1499 1500 if (ucontext) { 1501 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1502 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1503 } 1504 1505 CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu", 1506 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize); 1507 1508 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1509 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1510 if (ret) 1511 goto err1; 1512 1513 attrs->cap.max_recv_wr = rqsize - 1; 1514 attrs->cap.max_send_wr = sqsize - 1; 1515 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1516 1517 qhp->rhp = rhp; 1518 qhp->attr.pd = php->pdid; 1519 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1520 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1521 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1522 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1523 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1524 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1525 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1526 qhp->attr.state = C4IW_QP_STATE_IDLE; 1527 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1528 qhp->attr.enable_rdma_read = 1; 1529 qhp->attr.enable_rdma_write = 1; 1530 qhp->attr.enable_bind = 1; 1531 qhp->attr.max_ord = 1; 1532 qhp->attr.max_ird = 1; 1533 spin_lock_init(&qhp->lock); 1534 mutex_init(&qhp->mutex); 1535 init_waitqueue_head(&qhp->wait); 1536 atomic_set(&qhp->refcnt, 1); 1537 1538 spin_lock_irq(&rhp->lock); 1539 if (rhp->db_state != NORMAL) 1540 t4_disable_wq_db(&qhp->wq); 1541 if (++rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) { 1542 rhp->rdev.stats.db_state_transitions++; 1543 rhp->db_state = FLOW_CONTROL; 1544 idr_for_each(&rhp->qpidr, disable_qp_db, NULL); 1545 } 1546 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1547 spin_unlock_irq(&rhp->lock); 1548 if (ret) 1549 goto err2; 1550 1551 if (udata) { 1552 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL); 1553 if (!mm1) { 1554 ret = -ENOMEM; 1555 goto err3; 1556 } 1557 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL); 1558 if (!mm2) { 1559 ret = -ENOMEM; 1560 goto err4; 1561 } 1562 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL); 1563 if (!mm3) { 1564 ret = -ENOMEM; 1565 goto err5; 1566 } 1567 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL); 1568 if (!mm4) { 1569 ret = -ENOMEM; 1570 goto err6; 1571 } 1572 uresp.flags = 0; 1573 uresp.qid_mask = rhp->rdev.qpmask; 1574 uresp.sqid = qhp->wq.sq.qid; 1575 uresp.sq_size = qhp->wq.sq.size; 1576 uresp.sq_memsize = qhp->wq.sq.memsize; 1577 uresp.rqid = qhp->wq.rq.qid; 1578 uresp.rq_size = qhp->wq.rq.size; 1579 uresp.rq_memsize = qhp->wq.rq.memsize; 1580 spin_lock(&ucontext->mmap_lock); 1581 uresp.sq_key = ucontext->key; 1582 ucontext->key += PAGE_SIZE; 1583 uresp.rq_key = ucontext->key; 1584 ucontext->key += PAGE_SIZE; 1585 uresp.sq_db_gts_key = ucontext->key; 1586 ucontext->key += PAGE_SIZE; 1587 uresp.rq_db_gts_key = ucontext->key; 1588 ucontext->key += PAGE_SIZE; 1589 spin_unlock(&ucontext->mmap_lock); 1590 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1591 if (ret) 1592 goto err7; 1593 mm1->key = uresp.sq_key; 1594 mm1->addr = qhp->wq.sq.phys_addr; 1595 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1596 CTR4(KTR_IW_CXGBE, "%s mm1 %x, %x, %d", __func__, mm1->key, 1597 mm1->addr, mm1->len); 1598 insert_mmap(ucontext, mm1); 1599 mm2->key = uresp.rq_key; 1600 mm2->addr = vtophys(qhp->wq.rq.queue); 1601 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1602 CTR4(KTR_IW_CXGBE, "%s mm2 %x, %x, %d", __func__, mm2->key, 1603 mm2->addr, mm2->len); 1604 insert_mmap(ucontext, mm2); 1605 mm3->key = uresp.sq_db_gts_key; 1606 mm3->addr = qhp->wq.sq.udb; 1607 mm3->len = PAGE_SIZE; 1608 CTR4(KTR_IW_CXGBE, "%s mm3 %x, %x, %d", __func__, mm3->key, 1609 mm3->addr, mm3->len); 1610 insert_mmap(ucontext, mm3); 1611 mm4->key = uresp.rq_db_gts_key; 1612 mm4->addr = qhp->wq.rq.udb; 1613 mm4->len = PAGE_SIZE; 1614 CTR4(KTR_IW_CXGBE, "%s mm4 %x, %x, %d", __func__, mm4->key, 1615 mm4->addr, mm4->len); 1616 insert_mmap(ucontext, mm4); 1617 } 1618 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1619 init_timer(&(qhp->timer)); 1620 CTR5(KTR_IW_CXGBE, 1621 "%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x", 1622 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries, 1623 qhp->wq.sq.qid); 1624 return &qhp->ibqp; 1625 err7: 1626 kfree(mm4); 1627 err6: 1628 kfree(mm3); 1629 err5: 1630 kfree(mm2); 1631 err4: 1632 kfree(mm1); 1633 err3: 1634 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1635 err2: 1636 destroy_qp(&rhp->rdev, &qhp->wq, 1637 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1638 err1: 1639 kfree(qhp); 1640 return ERR_PTR(ret); 1641 } 1642 1643 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1644 int attr_mask, struct ib_udata *udata) 1645 { 1646 struct c4iw_dev *rhp; 1647 struct c4iw_qp *qhp; 1648 enum c4iw_qp_attr_mask mask = 0; 1649 struct c4iw_qp_attributes attrs; 1650 1651 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp); 1652 1653 /* iwarp does not support the RTR state */ 1654 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1655 attr_mask &= ~IB_QP_STATE; 1656 1657 /* Make sure we still have something left to do */ 1658 if (!attr_mask) 1659 return 0; 1660 1661 memset(&attrs, 0, sizeof attrs); 1662 qhp = to_c4iw_qp(ibqp); 1663 rhp = qhp->rhp; 1664 1665 attrs.next_state = c4iw_convert_state(attr->qp_state); 1666 attrs.enable_rdma_read = (attr->qp_access_flags & 1667 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1668 attrs.enable_rdma_write = (attr->qp_access_flags & 1669 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1670 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1671 1672 1673 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1674 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1675 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1676 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1677 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1678 1679 /* 1680 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for 1681 * ringing the queue db when we're in DB_FULL mode. 1682 */ 1683 attrs.sq_db_inc = attr->sq_psn; 1684 attrs.rq_db_inc = attr->rq_psn; 1685 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0; 1686 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0; 1687 1688 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1689 } 1690 1691 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1692 { 1693 CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn); 1694 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1695 } 1696 1697 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1698 int attr_mask, struct ib_qp_init_attr *init_attr) 1699 { 1700 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1701 1702 memset(attr, 0, sizeof *attr); 1703 memset(init_attr, 0, sizeof *init_attr); 1704 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1705 return 0; 1706 } 1707 #endif 1708