1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 #include <sys/cdefs.h> 35 #include "opt_inet.h" 36 37 #ifdef TCP_OFFLOAD 38 #include <sys/types.h> 39 #include <sys/malloc.h> 40 #include <sys/socket.h> 41 #include <sys/socketvar.h> 42 #include <sys/sockio.h> 43 #include <sys/taskqueue.h> 44 #include <netinet/in.h> 45 #include <net/route.h> 46 47 #include <netinet/in_systm.h> 48 #include <netinet/in_pcb.h> 49 #include <netinet/ip.h> 50 #include <netinet/ip_var.h> 51 #include <netinet/tcp_var.h> 52 #include <netinet/tcp.h> 53 #include <netinet/tcpip.h> 54 55 #include <netinet/toecore.h> 56 57 struct sge_iq; 58 struct rss_header; 59 struct cpl_set_tcb_rpl; 60 #include <linux/types.h> 61 #include "offload.h" 62 #include "tom/t4_tom.h" 63 64 #include "iw_cxgbe.h" 65 #include "user.h" 66 67 static int creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize); 68 static int max_fr_immd = T4_MAX_FR_IMMD;//SYSCTL parameter later... 69 70 static int alloc_ird(struct c4iw_dev *dev, u32 ird) 71 { 72 int ret = 0; 73 74 spin_lock_irq(&dev->lock); 75 if (ird <= dev->avail_ird) 76 dev->avail_ird -= ird; 77 else 78 ret = -ENOMEM; 79 spin_unlock_irq(&dev->lock); 80 81 if (ret) 82 log(LOG_WARNING, "%s: device IRD resources exhausted\n", 83 device_get_nameunit(dev->rdev.adap->dev)); 84 85 return ret; 86 } 87 88 static void free_ird(struct c4iw_dev *dev, int ird) 89 { 90 spin_lock_irq(&dev->lock); 91 dev->avail_ird += ird; 92 spin_unlock_irq(&dev->lock); 93 } 94 95 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 96 { 97 unsigned long flag; 98 spin_lock_irqsave(&qhp->lock, flag); 99 qhp->attr.state = state; 100 spin_unlock_irqrestore(&qhp->lock, flag); 101 } 102 103 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 104 struct c4iw_dev_ucontext *uctx) 105 { 106 struct c4iw_dev *rhp = rdev_to_c4iw_dev(rdev); 107 /* 108 * uP clears EQ contexts when the connection exits rdma mode, 109 * so no need to post a RESET WR for these EQs. 110 */ 111 dma_free_coherent(rhp->ibdev.dma_device, 112 wq->rq.memsize, wq->rq.queue, 113 dma_unmap_addr(&wq->rq, mapping)); 114 dma_free_coherent(rhp->ibdev.dma_device, 115 wq->sq.memsize, wq->sq.queue, 116 dma_unmap_addr(&wq->sq, mapping)); 117 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 118 kfree(wq->rq.sw_rq); 119 kfree(wq->sq.sw_sq); 120 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 121 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 122 return 0; 123 } 124 125 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 126 struct t4_cq *rcq, struct t4_cq *scq, 127 struct c4iw_dev_ucontext *uctx) 128 { 129 struct adapter *sc = rdev->adap; 130 struct c4iw_dev *rhp = rdev_to_c4iw_dev(rdev); 131 int user = (uctx != &rdev->uctx); 132 struct fw_ri_res_wr *res_wr; 133 struct fw_ri_res *res; 134 int wr_len; 135 struct c4iw_wr_wait wr_wait; 136 int ret = 0; 137 int eqsize; 138 struct wrqe *wr; 139 u64 sq_bar2_qoffset = 0, rq_bar2_qoffset = 0; 140 141 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 142 if (!wq->sq.qid) 143 return -ENOMEM; 144 145 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 146 if (!wq->rq.qid) { 147 ret = -ENOMEM; 148 goto free_sq_qid; 149 } 150 151 if (!user) { 152 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 153 GFP_KERNEL); 154 if (!wq->sq.sw_sq) { 155 ret = -ENOMEM; 156 goto free_rq_qid; 157 } 158 159 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 160 GFP_KERNEL); 161 if (!wq->rq.sw_rq) { 162 ret = -ENOMEM; 163 goto free_sw_sq; 164 } 165 } 166 167 /* 168 * RQT must be a power of 2 and at least 16 deep. 169 */ 170 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16)); 171 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 172 if (!wq->rq.rqt_hwaddr) { 173 ret = -ENOMEM; 174 goto free_sw_rq; 175 } 176 177 /*QP memory, allocate DMAable memory for Send & Receive Queues */ 178 wq->sq.queue = dma_alloc_coherent(rhp->ibdev.dma_device, wq->sq.memsize, 179 &(wq->sq.dma_addr), GFP_KERNEL); 180 if (!wq->sq.queue) { 181 ret = -ENOMEM; 182 goto free_hwaddr; 183 } 184 wq->sq.phys_addr = vtophys(wq->sq.queue); 185 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 186 memset(wq->sq.queue, 0, wq->sq.memsize); 187 188 wq->rq.queue = dma_alloc_coherent(rhp->ibdev.dma_device, 189 wq->rq.memsize, &(wq->rq.dma_addr), GFP_KERNEL); 190 if (!wq->rq.queue) { 191 ret = -ENOMEM; 192 goto free_sq_dma; 193 } 194 wq->rq.phys_addr = vtophys(wq->rq.queue); 195 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 196 memset(wq->rq.queue, 0, wq->rq.memsize); 197 198 CTR5(KTR_IW_CXGBE, 199 "%s QP sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx", 200 __func__, 201 wq->sq.queue, (unsigned long long)wq->sq.phys_addr, 202 wq->rq.queue, (unsigned long long)wq->rq.phys_addr); 203 204 /* Doorbell/WC regions, determine the BAR2 queue offset and qid. */ 205 t4_bar2_sge_qregs(rdev->adap, wq->sq.qid, T4_BAR2_QTYPE_EGRESS, user, 206 &sq_bar2_qoffset, &wq->sq.bar2_qid); 207 t4_bar2_sge_qregs(rdev->adap, wq->rq.qid, T4_BAR2_QTYPE_EGRESS, user, 208 &rq_bar2_qoffset, &wq->rq.bar2_qid); 209 210 if (user) { 211 /* Compute BAR2 DB/WC physical address(page-aligned) for 212 * Userspace mapping. 213 */ 214 wq->sq.bar2_pa = (rdev->bar2_pa + sq_bar2_qoffset) & PAGE_MASK; 215 wq->rq.bar2_pa = (rdev->bar2_pa + rq_bar2_qoffset) & PAGE_MASK; 216 CTR3(KTR_IW_CXGBE, 217 "%s BAR2 DB/WC sq base pa 0x%llx rq base pa 0x%llx", 218 __func__, (unsigned long long)wq->sq.bar2_pa, 219 (unsigned long long)wq->rq.bar2_pa); 220 } else { 221 /* Compute BAR2 DB/WC virtual address to access in kernel. */ 222 wq->sq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva + 223 sq_bar2_qoffset); 224 wq->rq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva + 225 rq_bar2_qoffset); 226 CTR3(KTR_IW_CXGBE, "%s BAR2 DB/WC sq base va %p rq base va %p", 227 __func__, (unsigned long long)wq->sq.bar2_va, 228 (unsigned long long)wq->rq.bar2_va); 229 } 230 231 wq->rdev = rdev; 232 wq->rq.msn = 1; 233 234 /* build fw_ri_res_wr */ 235 wr_len = sizeof *res_wr + 2 * sizeof *res; 236 237 wr = alloc_wrqe(wr_len, &sc->sge.ctrlq[0]); 238 if (wr == NULL) { 239 ret = -ENOMEM; 240 goto free_rq_dma; 241 } 242 res_wr = wrtod(wr); 243 244 memset(res_wr, 0, wr_len); 245 res_wr->op_nres = cpu_to_be32( 246 V_FW_WR_OP(FW_RI_RES_WR) | 247 V_FW_RI_RES_WR_NRES(2) | 248 F_FW_WR_COMPL); 249 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 250 res_wr->cookie = (unsigned long) &wr_wait; 251 res = res_wr->res; 252 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 253 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 254 255 /* eqsize is the number of 64B entries plus the status page size. */ 256 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + 257 rdev->hw_queue.t4_eq_status_entries; 258 259 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 260 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 261 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 262 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 263 V_FW_RI_RES_WR_IQID(scq->cqid)); 264 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 265 V_FW_RI_RES_WR_DCAEN(0) | 266 V_FW_RI_RES_WR_DCACPU(0) | 267 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 268 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 269 V_FW_RI_RES_WR_FBMAX(3) | 270 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 271 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 272 V_FW_RI_RES_WR_EQSIZE(eqsize)); 273 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 274 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 275 res++; 276 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 277 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 278 279 /* eqsize is the number of 64B entries plus the status page size. */ 280 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + 281 rdev->hw_queue.t4_eq_status_entries; 282 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 283 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 284 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 285 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 286 V_FW_RI_RES_WR_IQID(rcq->cqid)); 287 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 288 V_FW_RI_RES_WR_DCAEN(0) | 289 V_FW_RI_RES_WR_DCACPU(0) | 290 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 291 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 292 V_FW_RI_RES_WR_FBMAX(3) | 293 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 294 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 295 V_FW_RI_RES_WR_EQSIZE(eqsize)); 296 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 297 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 298 299 c4iw_init_wr_wait(&wr_wait); 300 301 t4_wrq_tx(sc, wr); 302 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, 303 NULL, __func__); 304 if (ret) 305 goto free_rq_dma; 306 307 CTR5(KTR_IW_CXGBE, 308 "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx", 309 __func__, wq->sq.qid, wq->rq.qid, 310 (unsigned long long)wq->sq.bar2_va, 311 (unsigned long long)wq->rq.bar2_va); 312 313 return 0; 314 free_rq_dma: 315 dma_free_coherent(rhp->ibdev.dma_device, 316 wq->rq.memsize, wq->rq.queue, 317 dma_unmap_addr(&wq->rq, mapping)); 318 free_sq_dma: 319 dma_free_coherent(rhp->ibdev.dma_device, 320 wq->sq.memsize, wq->sq.queue, 321 dma_unmap_addr(&wq->sq, mapping)); 322 free_hwaddr: 323 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 324 free_sw_rq: 325 kfree(wq->rq.sw_rq); 326 free_sw_sq: 327 kfree(wq->sq.sw_sq); 328 free_rq_qid: 329 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 330 free_sq_qid: 331 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 332 return ret; 333 } 334 335 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 336 const struct ib_send_wr *wr, int max, u32 *plenp) 337 { 338 u8 *dstp, *srcp; 339 u32 plen = 0; 340 int i; 341 int rem, len; 342 343 dstp = (u8 *)immdp->data; 344 for (i = 0; i < wr->num_sge; i++) { 345 if ((plen + wr->sg_list[i].length) > max) 346 return -EMSGSIZE; 347 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 348 plen += wr->sg_list[i].length; 349 rem = wr->sg_list[i].length; 350 while (rem) { 351 if (dstp == (u8 *)&sq->queue[sq->size]) 352 dstp = (u8 *)sq->queue; 353 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 354 len = rem; 355 else 356 len = (u8 *)&sq->queue[sq->size] - dstp; 357 memcpy(dstp, srcp, len); 358 dstp += len; 359 srcp += len; 360 rem -= len; 361 } 362 } 363 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 364 if (len) 365 memset(dstp, 0, len); 366 immdp->op = FW_RI_DATA_IMMD; 367 immdp->r1 = 0; 368 immdp->r2 = 0; 369 immdp->immdlen = cpu_to_be32(plen); 370 *plenp = plen; 371 return 0; 372 } 373 374 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 375 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 376 int num_sge, u32 *plenp) 377 378 { 379 int i; 380 u32 plen = 0; 381 __be64 *flitp = (__be64 *)isglp->sge; 382 383 for (i = 0; i < num_sge; i++) { 384 if ((plen + sg_list[i].length) < plen) 385 return -EMSGSIZE; 386 plen += sg_list[i].length; 387 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 388 sg_list[i].length); 389 if (++flitp == queue_end) 390 flitp = queue_start; 391 *flitp = cpu_to_be64(sg_list[i].addr); 392 if (++flitp == queue_end) 393 flitp = queue_start; 394 } 395 *flitp = (__force __be64)0; 396 isglp->op = FW_RI_DATA_ISGL; 397 isglp->r1 = 0; 398 isglp->nsge = cpu_to_be16(num_sge); 399 isglp->r2 = 0; 400 if (plenp) 401 *plenp = plen; 402 return 0; 403 } 404 405 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 406 const struct ib_send_wr *wr, u8 *len16) 407 { 408 u32 plen; 409 int size; 410 int ret; 411 412 if (wr->num_sge > T4_MAX_SEND_SGE) 413 return -EINVAL; 414 switch (wr->opcode) { 415 case IB_WR_SEND: 416 if (wr->send_flags & IB_SEND_SOLICITED) 417 wqe->send.sendop_pkd = cpu_to_be32( 418 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); 419 else 420 wqe->send.sendop_pkd = cpu_to_be32( 421 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); 422 wqe->send.stag_inv = 0; 423 break; 424 case IB_WR_SEND_WITH_INV: 425 if (wr->send_flags & IB_SEND_SOLICITED) 426 wqe->send.sendop_pkd = cpu_to_be32( 427 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV)); 428 else 429 wqe->send.sendop_pkd = cpu_to_be32( 430 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV)); 431 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 432 break; 433 434 default: 435 return -EINVAL; 436 } 437 wqe->send.r3 = 0; 438 wqe->send.r4 = 0; 439 440 plen = 0; 441 if (wr->num_sge) { 442 if (wr->send_flags & IB_SEND_INLINE) { 443 ret = build_immd(sq, wqe->send.u.immd_src, wr, 444 T4_MAX_SEND_INLINE, &plen); 445 if (ret) 446 return ret; 447 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 448 plen; 449 } else { 450 ret = build_isgl((__be64 *)sq->queue, 451 (__be64 *)&sq->queue[sq->size], 452 wqe->send.u.isgl_src, 453 wr->sg_list, wr->num_sge, &plen); 454 if (ret) 455 return ret; 456 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 457 wr->num_sge * sizeof(struct fw_ri_sge); 458 } 459 } else { 460 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 461 wqe->send.u.immd_src[0].r1 = 0; 462 wqe->send.u.immd_src[0].r2 = 0; 463 wqe->send.u.immd_src[0].immdlen = 0; 464 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 465 plen = 0; 466 } 467 *len16 = DIV_ROUND_UP(size, 16); 468 wqe->send.plen = cpu_to_be32(plen); 469 return 0; 470 } 471 472 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 473 const struct ib_send_wr *wr, u8 *len16) 474 { 475 u32 plen; 476 int size; 477 int ret; 478 479 if (wr->num_sge > T4_MAX_SEND_SGE) 480 return -EINVAL; 481 wqe->write.immd_data = 0; 482 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey); 483 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr); 484 if (wr->num_sge) { 485 if (wr->send_flags & IB_SEND_INLINE) { 486 ret = build_immd(sq, wqe->write.u.immd_src, wr, 487 T4_MAX_WRITE_INLINE, &plen); 488 if (ret) 489 return ret; 490 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 491 plen; 492 } else { 493 ret = build_isgl((__be64 *)sq->queue, 494 (__be64 *)&sq->queue[sq->size], 495 wqe->write.u.isgl_src, 496 wr->sg_list, wr->num_sge, &plen); 497 if (ret) 498 return ret; 499 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 500 wr->num_sge * sizeof(struct fw_ri_sge); 501 } 502 } else { 503 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 504 wqe->write.u.immd_src[0].r1 = 0; 505 wqe->write.u.immd_src[0].r2 = 0; 506 wqe->write.u.immd_src[0].immdlen = 0; 507 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 508 plen = 0; 509 } 510 *len16 = DIV_ROUND_UP(size, 16); 511 wqe->write.plen = cpu_to_be32(plen); 512 return 0; 513 } 514 515 static int build_rdma_read(union t4_wr *wqe, const struct ib_send_wr *wr, u8 *len16) 516 { 517 if (wr->num_sge > 1) 518 return -EINVAL; 519 if (wr->num_sge && wr->sg_list[0].length) { 520 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey); 521 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr 522 >> 32)); 523 wqe->read.to_src_lo = 524 cpu_to_be32((u32)rdma_wr(wr)->remote_addr); 525 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 526 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 527 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 528 >> 32)); 529 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 530 } else { 531 wqe->read.stag_src = cpu_to_be32(2); 532 wqe->read.to_src_hi = 0; 533 wqe->read.to_src_lo = 0; 534 wqe->read.stag_sink = cpu_to_be32(2); 535 wqe->read.plen = 0; 536 wqe->read.to_sink_hi = 0; 537 wqe->read.to_sink_lo = 0; 538 } 539 wqe->read.r2 = 0; 540 wqe->read.r5 = 0; 541 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 542 return 0; 543 } 544 545 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 546 const struct ib_recv_wr *wr, u8 *len16) 547 { 548 int ret; 549 550 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 551 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 552 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 553 if (ret) 554 return ret; 555 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 556 wr->num_sge * sizeof(struct fw_ri_sge), 16); 557 return 0; 558 } 559 560 static int build_inv_stag(union t4_wr *wqe, const struct ib_send_wr *wr, 561 u8 *len16) 562 { 563 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 564 wqe->inv.r2 = 0; 565 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 566 return 0; 567 } 568 569 static void free_qp_work(struct work_struct *work) 570 { 571 struct c4iw_ucontext *ucontext; 572 struct c4iw_qp *qhp; 573 struct c4iw_dev *rhp; 574 575 qhp = container_of(work, struct c4iw_qp, free_work); 576 ucontext = qhp->ucontext; 577 rhp = qhp->rhp; 578 579 CTR3(KTR_IW_CXGBE, "%s qhp %p ucontext %p", __func__, 580 qhp, ucontext); 581 destroy_qp(&rhp->rdev, &qhp->wq, 582 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 583 584 kfree(qhp); 585 } 586 587 static void queue_qp_free(struct kref *kref) 588 { 589 struct c4iw_qp *qhp; 590 591 qhp = container_of(kref, struct c4iw_qp, kref); 592 CTR2(KTR_IW_CXGBE, "%s qhp %p", __func__, qhp); 593 queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work); 594 } 595 596 void c4iw_qp_add_ref(struct ib_qp *qp) 597 { 598 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 599 kref_get(&to_c4iw_qp(qp)->kref); 600 } 601 602 void c4iw_qp_rem_ref(struct ib_qp *qp) 603 { 604 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 605 kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free); 606 } 607 608 static void complete_sq_drain_wr(struct c4iw_qp *qhp, const struct ib_send_wr *wr) 609 { 610 struct t4_cqe cqe = {}; 611 struct c4iw_cq *schp; 612 unsigned long flag; 613 struct t4_cq *cq; 614 615 schp = to_c4iw_cq(qhp->ibqp.send_cq); 616 cq = &schp->cq; 617 618 PDBG("%s drain sq id %u\n", __func__, qhp->wq.sq.qid); 619 cqe.u.drain_cookie = wr->wr_id; 620 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 621 V_CQE_OPCODE(C4IW_DRAIN_OPCODE) | 622 V_CQE_TYPE(1) | 623 V_CQE_SWCQE(1) | 624 V_CQE_QPID(qhp->wq.sq.qid)); 625 626 spin_lock_irqsave(&schp->lock, flag); 627 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 628 cq->sw_queue[cq->sw_pidx] = cqe; 629 t4_swcq_produce(cq); 630 spin_unlock_irqrestore(&schp->lock, flag); 631 632 spin_lock_irqsave(&schp->comp_handler_lock, flag); 633 (*schp->ibcq.comp_handler)(&schp->ibcq, 634 schp->ibcq.cq_context); 635 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 636 } 637 638 static void complete_rq_drain_wr(struct c4iw_qp *qhp, const struct ib_recv_wr *wr) 639 { 640 struct t4_cqe cqe = {}; 641 struct c4iw_cq *rchp; 642 unsigned long flag; 643 struct t4_cq *cq; 644 645 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 646 cq = &rchp->cq; 647 648 PDBG("%s drain rq id %u\n", __func__, qhp->wq.sq.qid); 649 cqe.u.drain_cookie = wr->wr_id; 650 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 651 V_CQE_OPCODE(C4IW_DRAIN_OPCODE) | 652 V_CQE_TYPE(0) | 653 V_CQE_SWCQE(1) | 654 V_CQE_QPID(qhp->wq.sq.qid)); 655 656 spin_lock_irqsave(&rchp->lock, flag); 657 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 658 cq->sw_queue[cq->sw_pidx] = cqe; 659 t4_swcq_produce(cq); 660 spin_unlock_irqrestore(&rchp->lock, flag); 661 662 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 663 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 664 rchp->ibcq.cq_context); 665 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 666 } 667 668 static int build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr, 669 const struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16) 670 { 671 __be64 *p = (__be64 *)fr->pbl; 672 673 if (wr->mr->page_size > C4IW_MAX_PAGE_SIZE) 674 return -EINVAL; 675 676 fr->r2 = cpu_to_be32(0); 677 fr->stag = cpu_to_be32(mhp->ibmr.rkey); 678 679 fr->tpte.valid_to_pdid = cpu_to_be32(F_FW_RI_TPTE_VALID | 680 V_FW_RI_TPTE_STAGKEY((mhp->ibmr.rkey & M_FW_RI_TPTE_STAGKEY)) | 681 V_FW_RI_TPTE_STAGSTATE(1) | 682 V_FW_RI_TPTE_STAGTYPE(FW_RI_STAG_NSMR) | 683 V_FW_RI_TPTE_PDID(mhp->attr.pdid)); 684 fr->tpte.locread_to_qpid = cpu_to_be32( 685 V_FW_RI_TPTE_PERM(c4iw_ib_to_tpt_access(wr->access)) | 686 V_FW_RI_TPTE_ADDRTYPE(FW_RI_VA_BASED_TO) | 687 V_FW_RI_TPTE_PS(ilog2(wr->mr->page_size) - 12)); 688 fr->tpte.nosnoop_pbladdr = cpu_to_be32(V_FW_RI_TPTE_PBLADDR( 689 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3)); 690 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0); 691 fr->tpte.len_hi = cpu_to_be32(mhp->ibmr.length >> 32); 692 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length & 0xffffffff); 693 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 694 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff); 695 696 p[0] = cpu_to_be64((u64)mhp->mpl[0]); 697 p[1] = cpu_to_be64((u64)mhp->mpl[1]); 698 699 *len16 = DIV_ROUND_UP(sizeof(*fr), 16); 700 return 0; 701 } 702 703 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe, 704 const struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16, 705 bool dsgl_supported) 706 { 707 struct fw_ri_immd *imdp; 708 __be64 *p; 709 int i; 710 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32); 711 int rem; 712 713 if (mhp->mpl_len > t4_max_fr_depth(&mhp->rhp->rdev, use_dsgl)) 714 return -EINVAL; 715 if (wr->mr->page_size > C4IW_MAX_PAGE_SIZE) 716 return -EINVAL; 717 718 wqe->fr.qpbinde_to_dcacpu = 0; 719 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12; 720 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 721 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access); 722 wqe->fr.len_hi = cpu_to_be32(mhp->ibmr.length >> 32); 723 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length & 0xffffffff); 724 wqe->fr.stag = cpu_to_be32(wr->key); 725 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 726 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff); 727 728 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) { 729 struct fw_ri_dsgl *sglp; 730 731 for (i = 0; i < mhp->mpl_len; i++) 732 mhp->mpl[i] = 733 (__force u64)cpu_to_be64((u64)mhp->mpl[i]); 734 735 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1); 736 sglp->op = FW_RI_DATA_DSGL; 737 sglp->r1 = 0; 738 sglp->nsge = cpu_to_be16(1); 739 sglp->addr0 = cpu_to_be64(mhp->mpl_addr); 740 sglp->len0 = cpu_to_be32(pbllen); 741 742 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16); 743 } else { 744 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 745 imdp->op = FW_RI_DATA_IMMD; 746 imdp->r1 = 0; 747 imdp->r2 = 0; 748 imdp->immdlen = cpu_to_be32(pbllen); 749 p = (__be64 *)(imdp + 1); 750 rem = pbllen; 751 for (i = 0; i < mhp->mpl_len; i++) { 752 *p = cpu_to_be64((u64)mhp->mpl[i]); 753 rem -= sizeof(*p); 754 if (++p == (__be64 *)&sq->queue[sq->size]) 755 p = (__be64 *)sq->queue; 756 } 757 BUG_ON(rem < 0); 758 while (rem) { 759 *p = 0; 760 rem -= sizeof(*p); 761 if (++p == (__be64 *)&sq->queue[sq->size]) 762 p = (__be64 *)sq->queue; 763 } 764 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp) 765 + pbllen, 16); 766 } 767 768 return 0; 769 } 770 771 int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 772 const struct ib_send_wr **bad_wr) 773 { 774 int err = 0; 775 u8 len16 = 0; 776 enum fw_wr_opcodes fw_opcode = 0; 777 enum fw_ri_wr_flags fw_flags; 778 struct c4iw_qp *qhp; 779 union t4_wr *wqe = NULL; 780 u32 num_wrs; 781 struct t4_swsqe *swsqe; 782 unsigned long flag; 783 u16 idx = 0; 784 struct c4iw_rdev *rdev; 785 786 qhp = to_c4iw_qp(ibqp); 787 rdev = &qhp->rhp->rdev; 788 spin_lock_irqsave(&qhp->lock, flag); 789 if (t4_wq_in_error(&qhp->wq)) { 790 spin_unlock_irqrestore(&qhp->lock, flag); 791 complete_sq_drain_wr(qhp, wr); 792 return err; 793 } 794 num_wrs = t4_sq_avail(&qhp->wq); 795 if (num_wrs == 0) { 796 spin_unlock_irqrestore(&qhp->lock, flag); 797 *bad_wr = wr; 798 return -ENOMEM; 799 } 800 while (wr) { 801 if (num_wrs == 0) { 802 err = -ENOMEM; 803 *bad_wr = wr; 804 break; 805 } 806 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 807 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 808 809 fw_flags = 0; 810 if (wr->send_flags & IB_SEND_SOLICITED) 811 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 812 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all) 813 fw_flags |= FW_RI_COMPLETION_FLAG; 814 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 815 switch (wr->opcode) { 816 case IB_WR_SEND_WITH_INV: 817 case IB_WR_SEND: 818 if (wr->send_flags & IB_SEND_FENCE) 819 fw_flags |= FW_RI_READ_FENCE_FLAG; 820 fw_opcode = FW_RI_SEND_WR; 821 if (wr->opcode == IB_WR_SEND) 822 swsqe->opcode = FW_RI_SEND; 823 else 824 swsqe->opcode = FW_RI_SEND_WITH_INV; 825 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 826 break; 827 case IB_WR_RDMA_WRITE: 828 fw_opcode = FW_RI_RDMA_WRITE_WR; 829 swsqe->opcode = FW_RI_RDMA_WRITE; 830 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 831 break; 832 case IB_WR_RDMA_READ: 833 case IB_WR_RDMA_READ_WITH_INV: 834 fw_opcode = FW_RI_RDMA_READ_WR; 835 swsqe->opcode = FW_RI_READ_REQ; 836 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) { 837 c4iw_invalidate_mr(qhp->rhp, 838 wr->sg_list[0].lkey); 839 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 840 } else { 841 fw_flags = 0; 842 } 843 err = build_rdma_read(wqe, wr, &len16); 844 if (err) 845 break; 846 swsqe->read_len = wr->sg_list[0].length; 847 if (!qhp->wq.sq.oldest_read) 848 qhp->wq.sq.oldest_read = swsqe; 849 break; 850 case IB_WR_REG_MR: { 851 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr); 852 853 swsqe->opcode = FW_RI_FAST_REGISTER; 854 if (rdev->adap->params.fr_nsmr_tpte_wr_support && 855 !mhp->attr.state && mhp->mpl_len <= 2) { 856 fw_opcode = FW_RI_FR_NSMR_TPTE_WR; 857 err = build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr), 858 mhp, &len16); 859 } else { 860 fw_opcode = FW_RI_FR_NSMR_WR; 861 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), 862 mhp, &len16, 863 rdev->adap->params.ulptx_memwrite_dsgl); 864 } 865 if (err) 866 break; 867 mhp->attr.state = 1; 868 break; 869 } 870 case IB_WR_LOCAL_INV: 871 if (wr->send_flags & IB_SEND_FENCE) 872 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 873 fw_opcode = FW_RI_INV_LSTAG_WR; 874 swsqe->opcode = FW_RI_LOCAL_INV; 875 err = build_inv_stag(wqe, wr, &len16); 876 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey); 877 break; 878 default: 879 CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__, 880 wr->opcode); 881 err = -EINVAL; 882 } 883 if (err) { 884 *bad_wr = wr; 885 break; 886 } 887 swsqe->idx = qhp->wq.sq.pidx; 888 swsqe->complete = 0; 889 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) || 890 qhp->sq_sig_all; 891 swsqe->flushed = 0; 892 swsqe->wr_id = wr->wr_id; 893 894 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 895 896 CTR5(KTR_IW_CXGBE, 897 "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u", 898 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 899 swsqe->opcode, swsqe->read_len); 900 wr = wr->next; 901 num_wrs--; 902 t4_sq_produce(&qhp->wq, len16); 903 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 904 } 905 906 t4_ring_sq_db(&qhp->wq, idx, wqe, rdev->adap->iwt.wc_en); 907 spin_unlock_irqrestore(&qhp->lock, flag); 908 return err; 909 } 910 911 int c4iw_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 912 const struct ib_recv_wr **bad_wr) 913 { 914 int err = 0; 915 struct c4iw_qp *qhp; 916 union t4_recv_wr *wqe = NULL; 917 u32 num_wrs; 918 u8 len16 = 0; 919 unsigned long flag; 920 u16 idx = 0; 921 922 qhp = to_c4iw_qp(ibqp); 923 spin_lock_irqsave(&qhp->lock, flag); 924 if (t4_wq_in_error(&qhp->wq)) { 925 spin_unlock_irqrestore(&qhp->lock, flag); 926 complete_rq_drain_wr(qhp, wr); 927 return err; 928 } 929 num_wrs = t4_rq_avail(&qhp->wq); 930 if (num_wrs == 0) { 931 spin_unlock_irqrestore(&qhp->lock, flag); 932 *bad_wr = wr; 933 return -ENOMEM; 934 } 935 while (wr) { 936 if (wr->num_sge > T4_MAX_RECV_SGE) { 937 err = -EINVAL; 938 *bad_wr = wr; 939 break; 940 } 941 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 942 qhp->wq.rq.wq_pidx * 943 T4_EQ_ENTRY_SIZE); 944 if (num_wrs) 945 err = build_rdma_recv(qhp, wqe, wr, &len16); 946 else 947 err = -ENOMEM; 948 if (err) { 949 *bad_wr = wr; 950 break; 951 } 952 953 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 954 955 wqe->recv.opcode = FW_RI_RECV_WR; 956 wqe->recv.r1 = 0; 957 wqe->recv.wrid = qhp->wq.rq.pidx; 958 wqe->recv.r2[0] = 0; 959 wqe->recv.r2[1] = 0; 960 wqe->recv.r2[2] = 0; 961 wqe->recv.len16 = len16; 962 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__, 963 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 964 t4_rq_produce(&qhp->wq, len16); 965 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 966 wr = wr->next; 967 num_wrs--; 968 } 969 970 t4_ring_rq_db(&qhp->wq, idx, wqe, qhp->rhp->rdev.adap->iwt.wc_en); 971 spin_unlock_irqrestore(&qhp->lock, flag); 972 return err; 973 } 974 975 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 976 u8 *ecode) 977 { 978 int status; 979 int tagged; 980 int opcode; 981 int rqtype; 982 int send_inv; 983 984 if (!err_cqe) { 985 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 986 *ecode = 0; 987 return; 988 } 989 990 status = CQE_STATUS(err_cqe); 991 opcode = CQE_OPCODE(err_cqe); 992 rqtype = RQ_TYPE(err_cqe); 993 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 994 (opcode == FW_RI_SEND_WITH_SE_INV); 995 tagged = (opcode == FW_RI_RDMA_WRITE) || 996 (rqtype && (opcode == FW_RI_READ_RESP)); 997 998 switch (status) { 999 case T4_ERR_STAG: 1000 if (send_inv) { 1001 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1002 *ecode = RDMAP_CANT_INV_STAG; 1003 } else { 1004 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1005 *ecode = RDMAP_INV_STAG; 1006 } 1007 break; 1008 case T4_ERR_PDID: 1009 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1010 if ((opcode == FW_RI_SEND_WITH_INV) || 1011 (opcode == FW_RI_SEND_WITH_SE_INV)) 1012 *ecode = RDMAP_CANT_INV_STAG; 1013 else 1014 *ecode = RDMAP_STAG_NOT_ASSOC; 1015 break; 1016 case T4_ERR_QPID: 1017 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1018 *ecode = RDMAP_STAG_NOT_ASSOC; 1019 break; 1020 case T4_ERR_ACCESS: 1021 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1022 *ecode = RDMAP_ACC_VIOL; 1023 break; 1024 case T4_ERR_WRAP: 1025 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1026 *ecode = RDMAP_TO_WRAP; 1027 break; 1028 case T4_ERR_BOUND: 1029 if (tagged) { 1030 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1031 *ecode = DDPT_BASE_BOUNDS; 1032 } else { 1033 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1034 *ecode = RDMAP_BASE_BOUNDS; 1035 } 1036 break; 1037 case T4_ERR_INVALIDATE_SHARED_MR: 1038 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 1039 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1040 *ecode = RDMAP_CANT_INV_STAG; 1041 break; 1042 case T4_ERR_ECC: 1043 case T4_ERR_ECC_PSTAG: 1044 case T4_ERR_INTERNAL_ERR: 1045 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 1046 *ecode = 0; 1047 break; 1048 case T4_ERR_OUT_OF_RQE: 1049 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1050 *ecode = DDPU_INV_MSN_NOBUF; 1051 break; 1052 case T4_ERR_PBL_ADDR_BOUND: 1053 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1054 *ecode = DDPT_BASE_BOUNDS; 1055 break; 1056 case T4_ERR_CRC: 1057 *layer_type = LAYER_MPA|DDP_LLP; 1058 *ecode = MPA_CRC_ERR; 1059 break; 1060 case T4_ERR_MARKER: 1061 *layer_type = LAYER_MPA|DDP_LLP; 1062 *ecode = MPA_MARKER_ERR; 1063 break; 1064 case T4_ERR_PDU_LEN_ERR: 1065 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1066 *ecode = DDPU_MSG_TOOBIG; 1067 break; 1068 case T4_ERR_DDP_VERSION: 1069 if (tagged) { 1070 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1071 *ecode = DDPT_INV_VERS; 1072 } else { 1073 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1074 *ecode = DDPU_INV_VERS; 1075 } 1076 break; 1077 case T4_ERR_RDMA_VERSION: 1078 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1079 *ecode = RDMAP_INV_VERS; 1080 break; 1081 case T4_ERR_OPCODE: 1082 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1083 *ecode = RDMAP_INV_OPCODE; 1084 break; 1085 case T4_ERR_DDP_QUEUE_NUM: 1086 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1087 *ecode = DDPU_INV_QN; 1088 break; 1089 case T4_ERR_MSN: 1090 case T4_ERR_MSN_GAP: 1091 case T4_ERR_MSN_RANGE: 1092 case T4_ERR_IRD_OVERFLOW: 1093 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1094 *ecode = DDPU_INV_MSN_RANGE; 1095 break; 1096 case T4_ERR_TBIT: 1097 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 1098 *ecode = 0; 1099 break; 1100 case T4_ERR_MO: 1101 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1102 *ecode = DDPU_INV_MO; 1103 break; 1104 default: 1105 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1106 *ecode = 0; 1107 break; 1108 } 1109 } 1110 1111 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 1112 gfp_t gfp) 1113 { 1114 int ret; 1115 struct fw_ri_wr *wqe; 1116 struct terminate_message *term; 1117 struct wrqe *wr; 1118 struct socket *so = qhp->ep->com.so; 1119 struct inpcb *inp = sotoinpcb(so); 1120 struct tcpcb *tp = intotcpcb(inp); 1121 struct toepcb *toep = tp->t_toe; 1122 1123 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1124 qhp->wq.sq.qid, qhp->ep->hwtid); 1125 1126 wr = alloc_wrqe(sizeof(*wqe), &toep->ofld_txq->wrq); 1127 if (wr == NULL) 1128 return; 1129 wqe = wrtod(wr); 1130 1131 memset(wqe, 0, sizeof *wqe); 1132 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR)); 1133 wqe->flowid_len16 = cpu_to_be32( 1134 V_FW_WR_FLOWID(qhp->ep->hwtid) | 1135 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1136 1137 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 1138 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 1139 term = (struct terminate_message *)wqe->u.terminate.termmsg; 1140 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 1141 term->layer_etype = qhp->attr.layer_etype; 1142 term->ecode = qhp->attr.ecode; 1143 } else 1144 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 1145 ret = creds(toep, inp, sizeof(*wqe)); 1146 if (ret) { 1147 free_wrqe(wr); 1148 return; 1149 } 1150 t4_wrq_tx(qhp->rhp->rdev.adap, wr); 1151 } 1152 1153 /* Assumes qhp lock is held. */ 1154 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 1155 struct c4iw_cq *schp) 1156 { 1157 int count; 1158 int rq_flushed, sq_flushed; 1159 unsigned long flag; 1160 1161 CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp, 1162 schp); 1163 1164 /* locking hierarchy: cq lock first, then qp lock. */ 1165 spin_lock_irqsave(&rchp->lock, flag); 1166 spin_lock(&qhp->lock); 1167 1168 if (qhp->wq.flushed) { 1169 spin_unlock(&qhp->lock); 1170 spin_unlock_irqrestore(&rchp->lock, flag); 1171 return; 1172 } 1173 qhp->wq.flushed = 1; 1174 1175 c4iw_flush_hw_cq(rchp); 1176 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 1177 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 1178 spin_unlock(&qhp->lock); 1179 spin_unlock_irqrestore(&rchp->lock, flag); 1180 1181 /* locking hierarchy: cq lock first, then qp lock. */ 1182 spin_lock_irqsave(&schp->lock, flag); 1183 spin_lock(&qhp->lock); 1184 if (schp != rchp) 1185 c4iw_flush_hw_cq(schp); 1186 sq_flushed = c4iw_flush_sq(qhp); 1187 spin_unlock(&qhp->lock); 1188 spin_unlock_irqrestore(&schp->lock, flag); 1189 1190 if (schp == rchp) { 1191 if (t4_clear_cq_armed(&rchp->cq) && 1192 (rq_flushed || sq_flushed)) { 1193 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1194 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1195 rchp->ibcq.cq_context); 1196 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1197 } 1198 } else { 1199 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) { 1200 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1201 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1202 rchp->ibcq.cq_context); 1203 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1204 } 1205 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) { 1206 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1207 (*schp->ibcq.comp_handler)(&schp->ibcq, 1208 schp->ibcq.cq_context); 1209 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1210 } 1211 } 1212 } 1213 1214 static void flush_qp(struct c4iw_qp *qhp) 1215 { 1216 struct c4iw_cq *rchp, *schp; 1217 unsigned long flag; 1218 1219 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 1220 schp = to_c4iw_cq(qhp->ibqp.send_cq); 1221 1222 t4_set_wq_in_error(&qhp->wq); 1223 if (qhp->ibqp.uobject) { 1224 t4_set_cq_in_error(&rchp->cq); 1225 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1226 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1227 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1228 if (schp != rchp) { 1229 t4_set_cq_in_error(&schp->cq); 1230 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1231 (*schp->ibcq.comp_handler)(&schp->ibcq, 1232 schp->ibcq.cq_context); 1233 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1234 } 1235 return; 1236 } 1237 __flush_qp(qhp, rchp, schp); 1238 } 1239 1240 static int 1241 rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep) 1242 { 1243 struct c4iw_rdev *rdev = &rhp->rdev; 1244 struct adapter *sc = rdev->adap; 1245 struct fw_ri_wr *wqe; 1246 int ret; 1247 struct wrqe *wr; 1248 struct socket *so = ep->com.so; 1249 struct inpcb *inp = sotoinpcb(so); 1250 struct tcpcb *tp = intotcpcb(inp); 1251 struct toepcb *toep = tp->t_toe; 1252 1253 KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__)); 1254 1255 CTR5(KTR_IW_CXGBE, "%s qhp %p qid 0x%x ep %p tid %u", __func__, qhp, 1256 qhp->wq.sq.qid, ep, ep->hwtid); 1257 1258 wr = alloc_wrqe(sizeof(*wqe), &toep->ofld_txq->wrq); 1259 if (wr == NULL) 1260 return (0); 1261 wqe = wrtod(wr); 1262 1263 memset(wqe, 0, sizeof *wqe); 1264 1265 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL); 1266 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1267 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1268 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1269 wqe->u.fini.type = FW_RI_TYPE_FINI; 1270 1271 c4iw_init_wr_wait(&ep->com.wr_wait); 1272 1273 ret = creds(toep, inp, sizeof(*wqe)); 1274 if (ret) { 1275 free_wrqe(wr); 1276 return ret; 1277 } 1278 t4_wrq_tx(sc, wr); 1279 1280 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1281 qhp->wq.sq.qid, ep->com.so, __func__); 1282 return ret; 1283 } 1284 1285 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1286 { 1287 CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type); 1288 memset(&init->u, 0, sizeof init->u); 1289 switch (p2p_type) { 1290 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1291 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1292 init->u.write.stag_sink = cpu_to_be32(1); 1293 init->u.write.to_sink = cpu_to_be64(1); 1294 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1295 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1296 sizeof(struct fw_ri_immd), 1297 16); 1298 break; 1299 case FW_RI_INIT_P2PTYPE_READ_REQ: 1300 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1301 init->u.read.stag_src = cpu_to_be32(1); 1302 init->u.read.to_src_lo = cpu_to_be32(1); 1303 init->u.read.stag_sink = cpu_to_be32(1); 1304 init->u.read.to_sink_lo = cpu_to_be32(1); 1305 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1306 break; 1307 } 1308 } 1309 1310 static int 1311 creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize) 1312 { 1313 struct ofld_tx_sdesc *txsd; 1314 1315 CTR3(KTR_IW_CXGBE, "%s:creB %p %u", __func__, toep , wrsize); 1316 INP_WLOCK(inp); 1317 if ((inp->inp_flags & INP_DROPPED) != 0) { 1318 INP_WUNLOCK(inp); 1319 return (EINVAL); 1320 } 1321 txsd = &toep->txsd[toep->txsd_pidx]; 1322 txsd->tx_credits = howmany(wrsize, 16); 1323 txsd->plen = 0; 1324 KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0, 1325 ("%s: not enough credits (%d)", __func__, toep->tx_credits)); 1326 toep->tx_credits -= txsd->tx_credits; 1327 if (__predict_false(++toep->txsd_pidx == toep->txsd_total)) 1328 toep->txsd_pidx = 0; 1329 toep->txsd_avail--; 1330 INP_WUNLOCK(inp); 1331 CTR5(KTR_IW_CXGBE, "%s:creE %p %u %u %u", __func__, toep , 1332 txsd->tx_credits, toep->tx_credits, toep->txsd_pidx); 1333 return (0); 1334 } 1335 1336 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1337 { 1338 struct fw_ri_wr *wqe; 1339 int ret; 1340 struct wrqe *wr; 1341 struct c4iw_ep *ep = qhp->ep; 1342 struct c4iw_rdev *rdev = &qhp->rhp->rdev; 1343 struct adapter *sc = rdev->adap; 1344 struct socket *so = ep->com.so; 1345 struct inpcb *inp = sotoinpcb(so); 1346 struct tcpcb *tp = intotcpcb(inp); 1347 struct toepcb *toep = tp->t_toe; 1348 1349 CTR5(KTR_IW_CXGBE, "%s qhp %p qid 0x%x ep %p tid %u", __func__, qhp, 1350 qhp->wq.sq.qid, ep, ep->hwtid); 1351 1352 wr = alloc_wrqe(sizeof(*wqe), &toep->ofld_txq->wrq); 1353 if (wr == NULL) 1354 return (0); 1355 wqe = wrtod(wr); 1356 ret = alloc_ird(rhp, qhp->attr.max_ird); 1357 if (ret) { 1358 qhp->attr.max_ird = 0; 1359 free_wrqe(wr); 1360 return ret; 1361 } 1362 1363 memset(wqe, 0, sizeof *wqe); 1364 1365 wqe->op_compl = cpu_to_be32( 1366 V_FW_WR_OP(FW_RI_WR) | 1367 F_FW_WR_COMPL); 1368 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1369 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1370 1371 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1372 1373 wqe->u.init.type = FW_RI_TYPE_INIT; 1374 wqe->u.init.mpareqbit_p2ptype = 1375 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) | 1376 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type); 1377 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1378 if (qhp->attr.mpa_attr.recv_marker_enabled) 1379 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1380 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1381 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1382 if (qhp->attr.mpa_attr.crc_enabled) 1383 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1384 1385 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1386 FW_RI_QP_RDMA_WRITE_ENABLE | 1387 FW_RI_QP_BIND_ENABLE; 1388 if (!qhp->ibqp.uobject) 1389 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1390 FW_RI_QP_STAG0_ENABLE; 1391 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1392 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1393 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1394 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1395 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1396 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1397 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1398 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1399 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1400 wqe->u.init.iss = cpu_to_be32(ep->snd_seq); 1401 wqe->u.init.irs = cpu_to_be32(ep->rcv_seq); 1402 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1403 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1404 sc->vres.rq.start); 1405 if (qhp->attr.mpa_attr.initiator) 1406 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1407 1408 c4iw_init_wr_wait(&ep->com.wr_wait); 1409 1410 ret = creds(toep, inp, sizeof(*wqe)); 1411 if (ret) { 1412 free_wrqe(wr); 1413 free_ird(rhp, qhp->attr.max_ird); 1414 return ret; 1415 } 1416 t4_wrq_tx(sc, wr); 1417 1418 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1419 qhp->wq.sq.qid, ep->com.so, __func__); 1420 1421 toep->params.ulp_mode = ULP_MODE_RDMA; 1422 free_ird(rhp, qhp->attr.max_ird); 1423 1424 return ret; 1425 } 1426 1427 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1428 enum c4iw_qp_attr_mask mask, 1429 struct c4iw_qp_attributes *attrs, 1430 int internal) 1431 { 1432 int ret = 0; 1433 struct c4iw_qp_attributes newattr = qhp->attr; 1434 int disconnect = 0; 1435 int terminate = 0; 1436 int abort = 0; 1437 int free = 0; 1438 struct c4iw_ep *ep = NULL; 1439 1440 CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp, 1441 qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep); 1442 CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state, 1443 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1444 1445 mutex_lock(&qhp->mutex); 1446 1447 /* Process attr changes if in IDLE */ 1448 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1449 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1450 ret = -EIO; 1451 goto out; 1452 } 1453 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1454 newattr.enable_rdma_read = attrs->enable_rdma_read; 1455 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1456 newattr.enable_rdma_write = attrs->enable_rdma_write; 1457 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1458 newattr.enable_bind = attrs->enable_bind; 1459 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1460 if (attrs->max_ord > c4iw_max_read_depth) { 1461 ret = -EINVAL; 1462 goto out; 1463 } 1464 newattr.max_ord = attrs->max_ord; 1465 } 1466 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1467 if (attrs->max_ird > cur_max_read_depth(rhp)) { 1468 ret = -EINVAL; 1469 goto out; 1470 } 1471 newattr.max_ird = attrs->max_ird; 1472 } 1473 qhp->attr = newattr; 1474 } 1475 1476 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1477 goto out; 1478 if (qhp->attr.state == attrs->next_state) 1479 goto out; 1480 1481 /* Return EINPROGRESS if QP is already in transition state. 1482 * Eg: CLOSING->IDLE transition or *->ERROR transition. 1483 * This can happen while connection is switching(due to rdma_fini) 1484 * from iWARP/RDDP to TOE mode and any inflight RDMA RX data will 1485 * reach TOE driver -> TCP stack -> iWARP driver. In this way 1486 * iWARP driver keep receiving inflight RDMA RX data until socket 1487 * is closed or aborted. And if iWARP CM is in FPDU sate, then 1488 * it tries to put QP in TERM state and disconnects endpoint. 1489 * But as QP is already in transition state, this event is ignored. 1490 */ 1491 if ((qhp->attr.state >= C4IW_QP_STATE_ERROR) && 1492 (attrs->next_state == C4IW_QP_STATE_TERMINATE)) { 1493 ret = -EINPROGRESS; 1494 goto out; 1495 } 1496 1497 switch (qhp->attr.state) { 1498 case C4IW_QP_STATE_IDLE: 1499 switch (attrs->next_state) { 1500 case C4IW_QP_STATE_RTS: 1501 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1502 ret = -EINVAL; 1503 goto out; 1504 } 1505 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1506 ret = -EINVAL; 1507 goto out; 1508 } 1509 qhp->attr.mpa_attr = attrs->mpa_attr; 1510 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1511 qhp->ep = qhp->attr.llp_stream_handle; 1512 set_state(qhp, C4IW_QP_STATE_RTS); 1513 1514 /* 1515 * Ref the endpoint here and deref when we 1516 * disassociate the endpoint from the QP. This 1517 * happens in CLOSING->IDLE transition or *->ERROR 1518 * transition. 1519 */ 1520 c4iw_get_ep(&qhp->ep->com); 1521 ret = rdma_init(rhp, qhp); 1522 if (ret) 1523 goto err; 1524 break; 1525 case C4IW_QP_STATE_ERROR: 1526 set_state(qhp, C4IW_QP_STATE_ERROR); 1527 flush_qp(qhp); 1528 break; 1529 default: 1530 ret = -EINVAL; 1531 goto out; 1532 } 1533 break; 1534 case C4IW_QP_STATE_RTS: 1535 switch (attrs->next_state) { 1536 case C4IW_QP_STATE_CLOSING: 1537 BUG_ON(kref_read(&qhp->ep->com.kref) < 2); 1538 t4_set_wq_in_error(&qhp->wq); 1539 set_state(qhp, C4IW_QP_STATE_CLOSING); 1540 ep = qhp->ep; 1541 if (!internal) { 1542 abort = 0; 1543 disconnect = 1; 1544 c4iw_get_ep(&qhp->ep->com); 1545 } 1546 ret = rdma_fini(rhp, qhp, ep); 1547 if (ret) 1548 goto err; 1549 break; 1550 case C4IW_QP_STATE_TERMINATE: 1551 t4_set_wq_in_error(&qhp->wq); 1552 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1553 qhp->attr.layer_etype = attrs->layer_etype; 1554 qhp->attr.ecode = attrs->ecode; 1555 ep = qhp->ep; 1556 if (!internal) { 1557 c4iw_get_ep(&qhp->ep->com); 1558 terminate = 1; 1559 disconnect = 1; 1560 } else { 1561 terminate = qhp->attr.send_term; 1562 ret = rdma_fini(rhp, qhp, ep); 1563 if (ret) 1564 goto err; 1565 } 1566 break; 1567 case C4IW_QP_STATE_ERROR: 1568 t4_set_wq_in_error(&qhp->wq); 1569 set_state(qhp, C4IW_QP_STATE_ERROR); 1570 if (!internal) { 1571 abort = 1; 1572 disconnect = 1; 1573 ep = qhp->ep; 1574 c4iw_get_ep(&qhp->ep->com); 1575 } 1576 goto err; 1577 break; 1578 default: 1579 ret = -EINVAL; 1580 goto out; 1581 } 1582 break; 1583 case C4IW_QP_STATE_CLOSING: 1584 1585 /* 1586 * Allow kernel users to move to ERROR for qp draining. 1587 */ 1588 if (!internal && (qhp->ibqp.uobject || attrs->next_state != 1589 C4IW_QP_STATE_ERROR)) { 1590 ret = -EINVAL; 1591 goto out; 1592 } 1593 switch (attrs->next_state) { 1594 case C4IW_QP_STATE_IDLE: 1595 flush_qp(qhp); 1596 set_state(qhp, C4IW_QP_STATE_IDLE); 1597 qhp->attr.llp_stream_handle = NULL; 1598 c4iw_put_ep(&qhp->ep->com); 1599 qhp->ep = NULL; 1600 wake_up(&qhp->wait); 1601 break; 1602 case C4IW_QP_STATE_ERROR: 1603 goto err; 1604 default: 1605 ret = -EINVAL; 1606 goto err; 1607 } 1608 break; 1609 case C4IW_QP_STATE_ERROR: 1610 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1611 ret = -EINVAL; 1612 goto out; 1613 } 1614 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1615 ret = -EINVAL; 1616 goto out; 1617 } 1618 set_state(qhp, C4IW_QP_STATE_IDLE); 1619 break; 1620 case C4IW_QP_STATE_TERMINATE: 1621 if (!internal) { 1622 ret = -EINVAL; 1623 goto out; 1624 } 1625 goto err; 1626 break; 1627 default: 1628 printf("%s in a bad state %d\n", 1629 __func__, qhp->attr.state); 1630 ret = -EINVAL; 1631 goto err; 1632 break; 1633 } 1634 goto out; 1635 err: 1636 CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__, 1637 qhp->ep, qhp->wq.sq.qid); 1638 1639 /* disassociate the LLP connection */ 1640 qhp->attr.llp_stream_handle = NULL; 1641 if (!ep) 1642 ep = qhp->ep; 1643 qhp->ep = NULL; 1644 set_state(qhp, C4IW_QP_STATE_ERROR); 1645 free = 1; 1646 abort = 1; 1647 BUG_ON(!ep); 1648 flush_qp(qhp); 1649 wake_up(&qhp->wait); 1650 out: 1651 mutex_unlock(&qhp->mutex); 1652 1653 if (terminate) 1654 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1655 1656 /* 1657 * If disconnect is 1, then we need to initiate a disconnect 1658 * on the EP. This can be a normal close (RTS->CLOSING) or 1659 * an abnormal close (RTS/CLOSING->ERROR). 1660 */ 1661 if (disconnect) { 1662 __c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1663 GFP_KERNEL); 1664 c4iw_put_ep(&ep->com); 1665 } 1666 1667 /* 1668 * If free is 1, then we've disassociated the EP from the QP 1669 * and we need to dereference the EP. 1670 */ 1671 if (free) 1672 c4iw_put_ep(&ep->com); 1673 CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state); 1674 return ret; 1675 } 1676 1677 int c4iw_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 1678 { 1679 struct c4iw_dev *rhp; 1680 struct c4iw_qp *qhp; 1681 struct c4iw_qp_attributes attrs; 1682 1683 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp); 1684 qhp = to_c4iw_qp(ib_qp); 1685 rhp = qhp->rhp; 1686 1687 attrs.next_state = C4IW_QP_STATE_ERROR; 1688 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1689 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1690 else 1691 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1692 wait_event(qhp->wait, !qhp->ep); 1693 1694 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1695 1696 free_ird(rhp, qhp->attr.max_ird); 1697 c4iw_qp_rem_ref(ib_qp); 1698 1699 CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp, 1700 qhp->wq.sq.qid); 1701 return 0; 1702 } 1703 1704 struct ib_qp * 1705 c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1706 struct ib_udata *udata) 1707 { 1708 struct c4iw_dev *rhp; 1709 struct c4iw_qp *qhp; 1710 struct c4iw_pd *php; 1711 struct c4iw_cq *schp; 1712 struct c4iw_cq *rchp; 1713 struct c4iw_create_qp_resp uresp; 1714 unsigned int sqsize, rqsize; 1715 struct c4iw_ucontext *ucontext; 1716 int ret; 1717 struct c4iw_mm_entry *sq_key_mm = NULL, *rq_key_mm = NULL; 1718 struct c4iw_mm_entry *sq_db_key_mm = NULL, *rq_db_key_mm = NULL; 1719 1720 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 1721 1722 if (attrs->qp_type != IB_QPT_RC) 1723 return ERR_PTR(-EINVAL); 1724 1725 php = to_c4iw_pd(pd); 1726 rhp = php->rhp; 1727 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1728 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1729 if (!schp || !rchp) 1730 return ERR_PTR(-EINVAL); 1731 1732 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1733 return ERR_PTR(-EINVAL); 1734 1735 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size) 1736 return ERR_PTR(-E2BIG); 1737 rqsize = attrs->cap.max_recv_wr + 1; 1738 if (rqsize < 8) 1739 rqsize = 8; 1740 1741 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size) 1742 return ERR_PTR(-E2BIG); 1743 sqsize = attrs->cap.max_send_wr + 1; 1744 if (sqsize < 8) 1745 sqsize = 8; 1746 1747 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1748 1749 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1750 if (!qhp) 1751 return ERR_PTR(-ENOMEM); 1752 qhp->wq.sq.size = sqsize; 1753 qhp->wq.sq.memsize = 1754 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1755 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64); 1756 qhp->wq.sq.flush_cidx = -1; 1757 qhp->wq.rq.size = rqsize; 1758 qhp->wq.rq.memsize = 1759 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1760 sizeof(*qhp->wq.rq.queue); 1761 1762 if (ucontext) { 1763 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1764 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1765 } 1766 1767 CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu", 1768 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize); 1769 1770 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1771 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1772 if (ret) 1773 goto err1; 1774 1775 attrs->cap.max_recv_wr = rqsize - 1; 1776 attrs->cap.max_send_wr = sqsize - 1; 1777 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1778 1779 qhp->rhp = rhp; 1780 qhp->attr.pd = php->pdid; 1781 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1782 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1783 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1784 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1785 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1786 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1787 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1788 qhp->attr.state = C4IW_QP_STATE_IDLE; 1789 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1790 qhp->attr.enable_rdma_read = 1; 1791 qhp->attr.enable_rdma_write = 1; 1792 qhp->attr.enable_bind = 1; 1793 qhp->attr.max_ord = 0; 1794 qhp->attr.max_ird = 0; 1795 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR; 1796 spin_lock_init(&qhp->lock); 1797 mutex_init(&qhp->mutex); 1798 init_waitqueue_head(&qhp->wait); 1799 kref_init(&qhp->kref); 1800 INIT_WORK(&qhp->free_work, free_qp_work); 1801 1802 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1803 if (ret) 1804 goto err2; 1805 1806 if (udata) { 1807 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL); 1808 if (!sq_key_mm) { 1809 ret = -ENOMEM; 1810 goto err3; 1811 } 1812 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL); 1813 if (!rq_key_mm) { 1814 ret = -ENOMEM; 1815 goto err4; 1816 } 1817 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL); 1818 if (!sq_db_key_mm) { 1819 ret = -ENOMEM; 1820 goto err5; 1821 } 1822 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL); 1823 if (!rq_db_key_mm) { 1824 ret = -ENOMEM; 1825 goto err6; 1826 } 1827 uresp.flags = 0; 1828 uresp.qid_mask = rhp->rdev.qpmask; 1829 uresp.sqid = qhp->wq.sq.qid; 1830 uresp.sq_size = qhp->wq.sq.size; 1831 uresp.sq_memsize = qhp->wq.sq.memsize; 1832 uresp.rqid = qhp->wq.rq.qid; 1833 uresp.rq_size = qhp->wq.rq.size; 1834 uresp.rq_memsize = qhp->wq.rq.memsize; 1835 spin_lock(&ucontext->mmap_lock); 1836 uresp.ma_sync_key = 0; 1837 uresp.sq_key = ucontext->key; 1838 ucontext->key += PAGE_SIZE; 1839 uresp.rq_key = ucontext->key; 1840 ucontext->key += PAGE_SIZE; 1841 uresp.sq_db_gts_key = ucontext->key; 1842 ucontext->key += PAGE_SIZE; 1843 uresp.rq_db_gts_key = ucontext->key; 1844 ucontext->key += PAGE_SIZE; 1845 spin_unlock(&ucontext->mmap_lock); 1846 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1847 if (ret) 1848 goto err7; 1849 sq_key_mm->key = uresp.sq_key; 1850 sq_key_mm->addr = qhp->wq.sq.phys_addr; 1851 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1852 CTR4(KTR_IW_CXGBE, "%s sq_key_mm %x, %x, %d", __func__, 1853 sq_key_mm->key, sq_key_mm->addr, 1854 sq_key_mm->len); 1855 insert_mmap(ucontext, sq_key_mm); 1856 rq_key_mm->key = uresp.rq_key; 1857 rq_key_mm->addr = qhp->wq.rq.phys_addr; 1858 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1859 CTR4(KTR_IW_CXGBE, "%s rq_key_mm %x, %x, %d", __func__, 1860 rq_key_mm->key, rq_key_mm->addr, 1861 rq_key_mm->len); 1862 insert_mmap(ucontext, rq_key_mm); 1863 sq_db_key_mm->key = uresp.sq_db_gts_key; 1864 sq_db_key_mm->addr = (u64)qhp->wq.sq.bar2_pa; 1865 sq_db_key_mm->len = PAGE_SIZE; 1866 CTR4(KTR_IW_CXGBE, "%s sq_db_key_mm %x, %x, %d", __func__, 1867 sq_db_key_mm->key, sq_db_key_mm->addr, 1868 sq_db_key_mm->len); 1869 insert_mmap(ucontext, sq_db_key_mm); 1870 rq_db_key_mm->key = uresp.rq_db_gts_key; 1871 rq_db_key_mm->addr = (u64)qhp->wq.rq.bar2_pa; 1872 rq_db_key_mm->len = PAGE_SIZE; 1873 CTR4(KTR_IW_CXGBE, "%s rq_db_key_mm %x, %x, %d", __func__, 1874 rq_db_key_mm->key, rq_db_key_mm->addr, 1875 rq_db_key_mm->len); 1876 insert_mmap(ucontext, rq_db_key_mm); 1877 1878 qhp->ucontext = ucontext; 1879 } 1880 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1881 init_timer(&(qhp->timer)); 1882 1883 CTR5(KTR_IW_CXGBE, "%s sq id %u size %u memsize %zu num_entries %u", 1884 __func__, qhp->wq.sq.qid, 1885 qhp->wq.sq.size, qhp->wq.sq.memsize, attrs->cap.max_send_wr); 1886 CTR5(KTR_IW_CXGBE, "%s rq id %u size %u memsize %zu num_entries %u", 1887 __func__, qhp->wq.rq.qid, 1888 qhp->wq.rq.size, qhp->wq.rq.memsize, attrs->cap.max_recv_wr); 1889 return &qhp->ibqp; 1890 err7: 1891 kfree(rq_db_key_mm); 1892 err6: 1893 kfree(sq_db_key_mm); 1894 err5: 1895 kfree(rq_key_mm); 1896 err4: 1897 kfree(sq_key_mm); 1898 err3: 1899 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1900 err2: 1901 destroy_qp(&rhp->rdev, &qhp->wq, 1902 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1903 err1: 1904 kfree(qhp); 1905 return ERR_PTR(ret); 1906 } 1907 1908 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1909 int attr_mask, struct ib_udata *udata) 1910 { 1911 struct c4iw_dev *rhp; 1912 struct c4iw_qp *qhp; 1913 enum c4iw_qp_attr_mask mask = 0; 1914 struct c4iw_qp_attributes attrs; 1915 1916 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp); 1917 1918 /* iwarp does not support the RTR state */ 1919 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1920 attr_mask &= ~IB_QP_STATE; 1921 1922 /* Make sure we still have something left to do */ 1923 if (!attr_mask) 1924 return 0; 1925 1926 memset(&attrs, 0, sizeof attrs); 1927 qhp = to_c4iw_qp(ibqp); 1928 rhp = qhp->rhp; 1929 1930 attrs.next_state = c4iw_convert_state(attr->qp_state); 1931 attrs.enable_rdma_read = (attr->qp_access_flags & 1932 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1933 attrs.enable_rdma_write = (attr->qp_access_flags & 1934 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1935 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1936 1937 1938 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1939 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1940 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1941 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1942 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1943 1944 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1945 } 1946 1947 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1948 { 1949 CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn); 1950 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1951 } 1952 1953 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1954 int attr_mask, struct ib_qp_init_attr *init_attr) 1955 { 1956 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1957 1958 memset(attr, 0, sizeof *attr); 1959 memset(init_attr, 0, sizeof *init_attr); 1960 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1961 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries; 1962 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries; 1963 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges; 1964 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges; 1965 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE; 1966 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0; 1967 return 0; 1968 } 1969 #endif 1970