1 /* 2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_inet.h" 36 37 #ifdef TCP_OFFLOAD 38 #include <sys/types.h> 39 #include <sys/malloc.h> 40 #include <sys/socket.h> 41 #include <sys/socketvar.h> 42 #include <sys/sockio.h> 43 #include <sys/taskqueue.h> 44 #include <netinet/in.h> 45 #include <net/route.h> 46 47 #include <netinet/in_systm.h> 48 #include <netinet/in_pcb.h> 49 #include <netinet/ip.h> 50 #include <netinet/ip_var.h> 51 #include <netinet/tcp_var.h> 52 #include <netinet/tcp.h> 53 #include <netinet/tcpip.h> 54 55 #include <netinet/toecore.h> 56 57 struct sge_iq; 58 struct rss_header; 59 #include <linux/types.h> 60 #include "offload.h" 61 #include "tom/t4_tom.h" 62 63 #include "iw_cxgbe.h" 64 #include "user.h" 65 66 extern int db_delay_usecs; 67 extern int db_fc_threshold; 68 static void creds(struct toepcb *toep, size_t wrsize); 69 70 71 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 72 { 73 unsigned long flag; 74 spin_lock_irqsave(&qhp->lock, flag); 75 qhp->attr.state = state; 76 spin_unlock_irqrestore(&qhp->lock, flag); 77 } 78 79 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 80 { 81 82 contigfree(sq->queue, sq->memsize, M_DEVBUF); 83 } 84 85 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 86 { 87 88 dealloc_host_sq(rdev, sq); 89 } 90 91 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 92 { 93 sq->queue = contigmalloc(sq->memsize, M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 94 4096, 0); 95 96 if (sq->queue) 97 sq->dma_addr = vtophys(sq->queue); 98 else 99 return -ENOMEM; 100 sq->phys_addr = vtophys(sq->queue); 101 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 102 CTR4(KTR_IW_CXGBE, "%s sq %p dma_addr %p phys_addr %p", __func__, 103 sq->queue, sq->dma_addr, sq->phys_addr); 104 return 0; 105 } 106 107 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 108 struct c4iw_dev_ucontext *uctx) 109 { 110 /* 111 * uP clears EQ contexts when the connection exits rdma mode, 112 * so no need to post a RESET WR for these EQs. 113 */ 114 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 115 dealloc_sq(rdev, &wq->sq); 116 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 117 kfree(wq->rq.sw_rq); 118 kfree(wq->sq.sw_sq); 119 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 120 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 121 return 0; 122 } 123 124 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 125 struct t4_cq *rcq, struct t4_cq *scq, 126 struct c4iw_dev_ucontext *uctx) 127 { 128 struct adapter *sc = rdev->adap; 129 int user = (uctx != &rdev->uctx); 130 struct fw_ri_res_wr *res_wr; 131 struct fw_ri_res *res; 132 int wr_len; 133 struct c4iw_wr_wait wr_wait; 134 int ret; 135 int eqsize; 136 struct wrqe *wr; 137 138 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 139 if (!wq->sq.qid) 140 return -ENOMEM; 141 142 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 143 if (!wq->rq.qid) 144 goto err1; 145 146 if (!user) { 147 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 148 GFP_KERNEL); 149 if (!wq->sq.sw_sq) 150 goto err2; 151 152 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 153 GFP_KERNEL); 154 if (!wq->rq.sw_rq) 155 goto err3; 156 } 157 158 /* RQT must be a power of 2. */ 159 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size); 160 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 161 if (!wq->rq.rqt_hwaddr) 162 goto err4; 163 164 if (alloc_host_sq(rdev, &wq->sq)) 165 goto err5; 166 167 memset(wq->sq.queue, 0, wq->sq.memsize); 168 pci_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 169 170 wq->rq.queue = contigmalloc(wq->rq.memsize, 171 M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 4096, 0); 172 if (wq->rq.queue) 173 wq->rq.dma_addr = vtophys(wq->rq.queue); 174 else 175 goto err6; 176 CTR5(KTR_IW_CXGBE, 177 "%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx", __func__, 178 wq->sq.queue, (unsigned long long)vtophys(wq->sq.queue), 179 wq->rq.queue, (unsigned long long)vtophys(wq->rq.queue)); 180 memset(wq->rq.queue, 0, wq->rq.memsize); 181 pci_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 182 183 wq->db = (void *)((unsigned long)rman_get_virtual(sc->regs_res) + 184 MYPF_REG(SGE_PF_KDOORBELL)); 185 wq->gts = (void *)((unsigned long)rman_get_virtual(rdev->adap->regs_res) 186 + MYPF_REG(SGE_PF_GTS)); 187 if (user) { 188 wq->sq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 189 (wq->sq.qid << rdev->qpshift)); 190 wq->sq.udb &= PAGE_MASK; 191 wq->rq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 192 (wq->rq.qid << rdev->qpshift)); 193 wq->rq.udb &= PAGE_MASK; 194 } 195 wq->rdev = rdev; 196 wq->rq.msn = 1; 197 198 /* build fw_ri_res_wr */ 199 wr_len = sizeof *res_wr + 2 * sizeof *res; 200 201 wr = alloc_wrqe(wr_len, &sc->sge.mgmtq); 202 if (wr == NULL) 203 return (0); 204 res_wr = wrtod(wr); 205 206 memset(res_wr, 0, wr_len); 207 res_wr->op_nres = cpu_to_be32( 208 V_FW_WR_OP(FW_RI_RES_WR) | 209 V_FW_RI_RES_WR_NRES(2) | 210 F_FW_WR_COMPL); 211 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 212 res_wr->cookie = (unsigned long) &wr_wait; 213 res = res_wr->res; 214 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 215 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 216 217 /* eqsize is the number of 64B entries plus the status page size. */ 218 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + spg_creds; 219 220 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 221 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 222 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 223 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 224 V_FW_RI_RES_WR_IQID(scq->cqid)); 225 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 226 V_FW_RI_RES_WR_DCAEN(0) | 227 V_FW_RI_RES_WR_DCACPU(0) | 228 V_FW_RI_RES_WR_FBMIN(2) | 229 V_FW_RI_RES_WR_FBMAX(2) | 230 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 231 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 232 V_FW_RI_RES_WR_EQSIZE(eqsize)); 233 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 234 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 235 res++; 236 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 237 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 238 239 /* eqsize is the number of 64B entries plus the status page size. */ 240 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + spg_creds ; 241 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 242 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 243 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 244 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 245 V_FW_RI_RES_WR_IQID(rcq->cqid)); 246 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 247 V_FW_RI_RES_WR_DCAEN(0) | 248 V_FW_RI_RES_WR_DCACPU(0) | 249 V_FW_RI_RES_WR_FBMIN(2) | 250 V_FW_RI_RES_WR_FBMAX(2) | 251 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 252 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 253 V_FW_RI_RES_WR_EQSIZE(eqsize)); 254 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 255 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 256 257 c4iw_init_wr_wait(&wr_wait); 258 259 t4_wrq_tx(sc, wr); 260 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); 261 if (ret) 262 goto err7; 263 264 CTR6(KTR_IW_CXGBE, 265 "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx", 266 __func__, wq->sq.qid, wq->rq.qid, wq->db, 267 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb); 268 269 return 0; 270 err7: 271 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 272 err6: 273 dealloc_sq(rdev, &wq->sq); 274 err5: 275 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 276 err4: 277 kfree(wq->rq.sw_rq); 278 err3: 279 kfree(wq->sq.sw_sq); 280 err2: 281 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 282 err1: 283 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 284 return -ENOMEM; 285 } 286 287 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 288 struct ib_send_wr *wr, int max, u32 *plenp) 289 { 290 u8 *dstp, *srcp; 291 u32 plen = 0; 292 int i; 293 int rem, len; 294 295 dstp = (u8 *)immdp->data; 296 for (i = 0; i < wr->num_sge; i++) { 297 if ((plen + wr->sg_list[i].length) > max) 298 return -EMSGSIZE; 299 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 300 plen += wr->sg_list[i].length; 301 rem = wr->sg_list[i].length; 302 while (rem) { 303 if (dstp == (u8 *)&sq->queue[sq->size]) 304 dstp = (u8 *)sq->queue; 305 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 306 len = rem; 307 else 308 len = (u8 *)&sq->queue[sq->size] - dstp; 309 memcpy(dstp, srcp, len); 310 dstp += len; 311 srcp += len; 312 rem -= len; 313 } 314 } 315 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 316 if (len) 317 memset(dstp, 0, len); 318 immdp->op = FW_RI_DATA_IMMD; 319 immdp->r1 = 0; 320 immdp->r2 = 0; 321 immdp->immdlen = cpu_to_be32(plen); 322 *plenp = plen; 323 return 0; 324 } 325 326 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 327 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 328 int num_sge, u32 *plenp) 329 330 { 331 int i; 332 u32 plen = 0; 333 __be64 *flitp = (__be64 *)isglp->sge; 334 335 for (i = 0; i < num_sge; i++) { 336 if ((plen + sg_list[i].length) < plen) 337 return -EMSGSIZE; 338 plen += sg_list[i].length; 339 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 340 sg_list[i].length); 341 if (++flitp == queue_end) 342 flitp = queue_start; 343 *flitp = cpu_to_be64(sg_list[i].addr); 344 if (++flitp == queue_end) 345 flitp = queue_start; 346 } 347 *flitp = (__force __be64)0; 348 isglp->op = FW_RI_DATA_ISGL; 349 isglp->r1 = 0; 350 isglp->nsge = cpu_to_be16(num_sge); 351 isglp->r2 = 0; 352 if (plenp) 353 *plenp = plen; 354 return 0; 355 } 356 357 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 358 struct ib_send_wr *wr, u8 *len16) 359 { 360 u32 plen; 361 int size; 362 int ret; 363 364 if (wr->num_sge > T4_MAX_SEND_SGE) 365 return -EINVAL; 366 switch (wr->opcode) { 367 case IB_WR_SEND: 368 if (wr->send_flags & IB_SEND_SOLICITED) 369 wqe->send.sendop_pkd = cpu_to_be32( 370 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); 371 else 372 wqe->send.sendop_pkd = cpu_to_be32( 373 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); 374 wqe->send.stag_inv = 0; 375 break; 376 case IB_WR_SEND_WITH_INV: 377 if (wr->send_flags & IB_SEND_SOLICITED) 378 wqe->send.sendop_pkd = cpu_to_be32( 379 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV)); 380 else 381 wqe->send.sendop_pkd = cpu_to_be32( 382 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV)); 383 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 384 break; 385 386 default: 387 return -EINVAL; 388 } 389 390 plen = 0; 391 if (wr->num_sge) { 392 if (wr->send_flags & IB_SEND_INLINE) { 393 ret = build_immd(sq, wqe->send.u.immd_src, wr, 394 T4_MAX_SEND_INLINE, &plen); 395 if (ret) 396 return ret; 397 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 398 plen; 399 } else { 400 ret = build_isgl((__be64 *)sq->queue, 401 (__be64 *)&sq->queue[sq->size], 402 wqe->send.u.isgl_src, 403 wr->sg_list, wr->num_sge, &plen); 404 if (ret) 405 return ret; 406 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 407 wr->num_sge * sizeof(struct fw_ri_sge); 408 } 409 } else { 410 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 411 wqe->send.u.immd_src[0].r1 = 0; 412 wqe->send.u.immd_src[0].r2 = 0; 413 wqe->send.u.immd_src[0].immdlen = 0; 414 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 415 plen = 0; 416 } 417 *len16 = DIV_ROUND_UP(size, 16); 418 wqe->send.plen = cpu_to_be32(plen); 419 return 0; 420 } 421 422 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 423 struct ib_send_wr *wr, u8 *len16) 424 { 425 u32 plen; 426 int size; 427 int ret; 428 429 if (wr->num_sge > T4_MAX_SEND_SGE) 430 return -EINVAL; 431 wqe->write.r2 = 0; 432 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey); 433 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr); 434 if (wr->num_sge) { 435 if (wr->send_flags & IB_SEND_INLINE) { 436 ret = build_immd(sq, wqe->write.u.immd_src, wr, 437 T4_MAX_WRITE_INLINE, &plen); 438 if (ret) 439 return ret; 440 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 441 plen; 442 } else { 443 ret = build_isgl((__be64 *)sq->queue, 444 (__be64 *)&sq->queue[sq->size], 445 wqe->write.u.isgl_src, 446 wr->sg_list, wr->num_sge, &plen); 447 if (ret) 448 return ret; 449 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 450 wr->num_sge * sizeof(struct fw_ri_sge); 451 } 452 } else { 453 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 454 wqe->write.u.immd_src[0].r1 = 0; 455 wqe->write.u.immd_src[0].r2 = 0; 456 wqe->write.u.immd_src[0].immdlen = 0; 457 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 458 plen = 0; 459 } 460 *len16 = DIV_ROUND_UP(size, 16); 461 wqe->write.plen = cpu_to_be32(plen); 462 return 0; 463 } 464 465 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 466 { 467 if (wr->num_sge > 1) 468 return -EINVAL; 469 if (wr->num_sge) { 470 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey); 471 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr 472 >> 32)); 473 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr); 474 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 475 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 476 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 477 >> 32)); 478 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 479 } else { 480 wqe->read.stag_src = cpu_to_be32(2); 481 wqe->read.to_src_hi = 0; 482 wqe->read.to_src_lo = 0; 483 wqe->read.stag_sink = cpu_to_be32(2); 484 wqe->read.plen = 0; 485 wqe->read.to_sink_hi = 0; 486 wqe->read.to_sink_lo = 0; 487 } 488 wqe->read.r2 = 0; 489 wqe->read.r5 = 0; 490 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 491 return 0; 492 } 493 494 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 495 struct ib_recv_wr *wr, u8 *len16) 496 { 497 int ret; 498 499 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 500 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 501 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 502 if (ret) 503 return ret; 504 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 505 wr->num_sge * sizeof(struct fw_ri_sge), 16); 506 return 0; 507 } 508 509 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, 510 struct ib_send_wr *wr, u8 *len16) 511 { 512 513 struct fw_ri_immd *imdp; 514 __be64 *p; 515 int i; 516 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); 517 int rem; 518 519 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH) 520 return -EINVAL; 521 522 wqe->fr.qpbinde_to_dcacpu = 0; 523 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12; 524 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 525 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags); 526 wqe->fr.len_hi = 0; 527 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length); 528 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey); 529 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); 530 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & 531 0xffffffff); 532 WARN_ON(pbllen > T4_MAX_FR_IMMD); 533 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 534 imdp->op = FW_RI_DATA_IMMD; 535 imdp->r1 = 0; 536 imdp->r2 = 0; 537 imdp->immdlen = cpu_to_be32(pbllen); 538 p = (__be64 *)(imdp + 1); 539 rem = pbllen; 540 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { 541 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]); 542 rem -= sizeof *p; 543 if (++p == (__be64 *)&sq->queue[sq->size]) 544 p = (__be64 *)sq->queue; 545 } 546 BUG_ON(rem < 0); 547 while (rem) { 548 *p = 0; 549 rem -= sizeof *p; 550 if (++p == (__be64 *)&sq->queue[sq->size]) 551 p = (__be64 *)sq->queue; 552 } 553 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16); 554 return 0; 555 } 556 557 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, 558 u8 *len16) 559 { 560 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 561 wqe->inv.r2 = 0; 562 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 563 return 0; 564 } 565 566 void c4iw_qp_add_ref(struct ib_qp *qp) 567 { 568 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 569 atomic_inc(&(to_c4iw_qp(qp)->refcnt)); 570 } 571 572 void c4iw_qp_rem_ref(struct ib_qp *qp) 573 { 574 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 575 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt))) 576 wake_up(&(to_c4iw_qp(qp)->wait)); 577 } 578 579 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 580 struct ib_send_wr **bad_wr) 581 { 582 int err = 0; 583 u8 len16 = 0; 584 enum fw_wr_opcodes fw_opcode = 0; 585 enum fw_ri_wr_flags fw_flags; 586 struct c4iw_qp *qhp; 587 union t4_wr *wqe; 588 u32 num_wrs; 589 struct t4_swsqe *swsqe; 590 unsigned long flag; 591 u16 idx = 0; 592 593 qhp = to_c4iw_qp(ibqp); 594 spin_lock_irqsave(&qhp->lock, flag); 595 if (t4_wq_in_error(&qhp->wq)) { 596 spin_unlock_irqrestore(&qhp->lock, flag); 597 return -EINVAL; 598 } 599 num_wrs = t4_sq_avail(&qhp->wq); 600 if (num_wrs == 0) { 601 spin_unlock_irqrestore(&qhp->lock, flag); 602 return -ENOMEM; 603 } 604 while (wr) { 605 if (num_wrs == 0) { 606 err = -ENOMEM; 607 *bad_wr = wr; 608 break; 609 } 610 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 611 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 612 613 fw_flags = 0; 614 if (wr->send_flags & IB_SEND_SOLICITED) 615 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 616 if (wr->send_flags & IB_SEND_SIGNALED) 617 fw_flags |= FW_RI_COMPLETION_FLAG; 618 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 619 switch (wr->opcode) { 620 case IB_WR_SEND_WITH_INV: 621 case IB_WR_SEND: 622 if (wr->send_flags & IB_SEND_FENCE) 623 fw_flags |= FW_RI_READ_FENCE_FLAG; 624 fw_opcode = FW_RI_SEND_WR; 625 if (wr->opcode == IB_WR_SEND) 626 swsqe->opcode = FW_RI_SEND; 627 else 628 swsqe->opcode = FW_RI_SEND_WITH_INV; 629 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 630 break; 631 case IB_WR_RDMA_WRITE: 632 fw_opcode = FW_RI_RDMA_WRITE_WR; 633 swsqe->opcode = FW_RI_RDMA_WRITE; 634 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 635 break; 636 case IB_WR_RDMA_READ: 637 case IB_WR_RDMA_READ_WITH_INV: 638 fw_opcode = FW_RI_RDMA_READ_WR; 639 swsqe->opcode = FW_RI_READ_REQ; 640 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) 641 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 642 else 643 fw_flags = 0; 644 err = build_rdma_read(wqe, wr, &len16); 645 if (err) 646 break; 647 swsqe->read_len = wr->sg_list[0].length; 648 if (!qhp->wq.sq.oldest_read) 649 qhp->wq.sq.oldest_read = swsqe; 650 break; 651 case IB_WR_FAST_REG_MR: 652 fw_opcode = FW_RI_FR_NSMR_WR; 653 swsqe->opcode = FW_RI_FAST_REGISTER; 654 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16); 655 break; 656 case IB_WR_LOCAL_INV: 657 if (wr->send_flags & IB_SEND_FENCE) 658 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 659 fw_opcode = FW_RI_INV_LSTAG_WR; 660 swsqe->opcode = FW_RI_LOCAL_INV; 661 err = build_inv_stag(wqe, wr, &len16); 662 break; 663 default: 664 CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__, 665 wr->opcode); 666 err = -EINVAL; 667 } 668 if (err) { 669 *bad_wr = wr; 670 break; 671 } 672 swsqe->idx = qhp->wq.sq.pidx; 673 swsqe->complete = 0; 674 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED); 675 swsqe->wr_id = wr->wr_id; 676 677 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 678 679 CTR5(KTR_IW_CXGBE, 680 "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u", 681 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 682 swsqe->opcode, swsqe->read_len); 683 wr = wr->next; 684 num_wrs--; 685 t4_sq_produce(&qhp->wq, len16); 686 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 687 } 688 if (t4_wq_db_enabled(&qhp->wq)) 689 t4_ring_sq_db(&qhp->wq, idx); 690 spin_unlock_irqrestore(&qhp->lock, flag); 691 return err; 692 } 693 694 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 695 struct ib_recv_wr **bad_wr) 696 { 697 int err = 0; 698 struct c4iw_qp *qhp; 699 union t4_recv_wr *wqe; 700 u32 num_wrs; 701 u8 len16 = 0; 702 unsigned long flag; 703 u16 idx = 0; 704 705 qhp = to_c4iw_qp(ibqp); 706 spin_lock_irqsave(&qhp->lock, flag); 707 if (t4_wq_in_error(&qhp->wq)) { 708 spin_unlock_irqrestore(&qhp->lock, flag); 709 return -EINVAL; 710 } 711 num_wrs = t4_rq_avail(&qhp->wq); 712 if (num_wrs == 0) { 713 spin_unlock_irqrestore(&qhp->lock, flag); 714 return -ENOMEM; 715 } 716 while (wr) { 717 if (wr->num_sge > T4_MAX_RECV_SGE) { 718 err = -EINVAL; 719 *bad_wr = wr; 720 break; 721 } 722 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 723 qhp->wq.rq.wq_pidx * 724 T4_EQ_ENTRY_SIZE); 725 if (num_wrs) 726 err = build_rdma_recv(qhp, wqe, wr, &len16); 727 else 728 err = -ENOMEM; 729 if (err) { 730 *bad_wr = wr; 731 break; 732 } 733 734 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 735 736 wqe->recv.opcode = FW_RI_RECV_WR; 737 wqe->recv.r1 = 0; 738 wqe->recv.wrid = qhp->wq.rq.pidx; 739 wqe->recv.r2[0] = 0; 740 wqe->recv.r2[1] = 0; 741 wqe->recv.r2[2] = 0; 742 wqe->recv.len16 = len16; 743 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__, 744 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 745 t4_rq_produce(&qhp->wq, len16); 746 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 747 wr = wr->next; 748 num_wrs--; 749 } 750 if (t4_wq_db_enabled(&qhp->wq)) 751 t4_ring_rq_db(&qhp->wq, idx); 752 spin_unlock_irqrestore(&qhp->lock, flag); 753 return err; 754 } 755 756 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind) 757 { 758 return -ENOSYS; 759 } 760 761 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 762 u8 *ecode) 763 { 764 int status; 765 int tagged; 766 int opcode; 767 int rqtype; 768 int send_inv; 769 770 if (!err_cqe) { 771 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 772 *ecode = 0; 773 return; 774 } 775 776 status = CQE_STATUS(err_cqe); 777 opcode = CQE_OPCODE(err_cqe); 778 rqtype = RQ_TYPE(err_cqe); 779 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 780 (opcode == FW_RI_SEND_WITH_SE_INV); 781 tagged = (opcode == FW_RI_RDMA_WRITE) || 782 (rqtype && (opcode == FW_RI_READ_RESP)); 783 784 switch (status) { 785 case T4_ERR_STAG: 786 if (send_inv) { 787 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 788 *ecode = RDMAP_CANT_INV_STAG; 789 } else { 790 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 791 *ecode = RDMAP_INV_STAG; 792 } 793 break; 794 case T4_ERR_PDID: 795 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 796 if ((opcode == FW_RI_SEND_WITH_INV) || 797 (opcode == FW_RI_SEND_WITH_SE_INV)) 798 *ecode = RDMAP_CANT_INV_STAG; 799 else 800 *ecode = RDMAP_STAG_NOT_ASSOC; 801 break; 802 case T4_ERR_QPID: 803 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 804 *ecode = RDMAP_STAG_NOT_ASSOC; 805 break; 806 case T4_ERR_ACCESS: 807 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 808 *ecode = RDMAP_ACC_VIOL; 809 break; 810 case T4_ERR_WRAP: 811 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 812 *ecode = RDMAP_TO_WRAP; 813 break; 814 case T4_ERR_BOUND: 815 if (tagged) { 816 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 817 *ecode = DDPT_BASE_BOUNDS; 818 } else { 819 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 820 *ecode = RDMAP_BASE_BOUNDS; 821 } 822 break; 823 case T4_ERR_INVALIDATE_SHARED_MR: 824 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 825 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 826 *ecode = RDMAP_CANT_INV_STAG; 827 break; 828 case T4_ERR_ECC: 829 case T4_ERR_ECC_PSTAG: 830 case T4_ERR_INTERNAL_ERR: 831 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 832 *ecode = 0; 833 break; 834 case T4_ERR_OUT_OF_RQE: 835 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 836 *ecode = DDPU_INV_MSN_NOBUF; 837 break; 838 case T4_ERR_PBL_ADDR_BOUND: 839 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 840 *ecode = DDPT_BASE_BOUNDS; 841 break; 842 case T4_ERR_CRC: 843 *layer_type = LAYER_MPA|DDP_LLP; 844 *ecode = MPA_CRC_ERR; 845 break; 846 case T4_ERR_MARKER: 847 *layer_type = LAYER_MPA|DDP_LLP; 848 *ecode = MPA_MARKER_ERR; 849 break; 850 case T4_ERR_PDU_LEN_ERR: 851 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 852 *ecode = DDPU_MSG_TOOBIG; 853 break; 854 case T4_ERR_DDP_VERSION: 855 if (tagged) { 856 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 857 *ecode = DDPT_INV_VERS; 858 } else { 859 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 860 *ecode = DDPU_INV_VERS; 861 } 862 break; 863 case T4_ERR_RDMA_VERSION: 864 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 865 *ecode = RDMAP_INV_VERS; 866 break; 867 case T4_ERR_OPCODE: 868 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 869 *ecode = RDMAP_INV_OPCODE; 870 break; 871 case T4_ERR_DDP_QUEUE_NUM: 872 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 873 *ecode = DDPU_INV_QN; 874 break; 875 case T4_ERR_MSN: 876 case T4_ERR_MSN_GAP: 877 case T4_ERR_MSN_RANGE: 878 case T4_ERR_IRD_OVERFLOW: 879 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 880 *ecode = DDPU_INV_MSN_RANGE; 881 break; 882 case T4_ERR_TBIT: 883 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 884 *ecode = 0; 885 break; 886 case T4_ERR_MO: 887 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 888 *ecode = DDPU_INV_MO; 889 break; 890 default: 891 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 892 *ecode = 0; 893 break; 894 } 895 } 896 897 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 898 gfp_t gfp) 899 { 900 struct fw_ri_wr *wqe; 901 struct terminate_message *term; 902 struct wrqe *wr; 903 struct socket *so = qhp->ep->com.so; 904 struct inpcb *inp = sotoinpcb(so); 905 struct tcpcb *tp = intotcpcb(inp); 906 struct toepcb *toep = tp->t_toe; 907 908 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 909 qhp->wq.sq.qid, qhp->ep->hwtid); 910 911 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 912 if (wr == NULL) 913 return; 914 wqe = wrtod(wr); 915 916 memset(wqe, 0, sizeof *wqe); 917 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR)); 918 wqe->flowid_len16 = cpu_to_be32( 919 V_FW_WR_FLOWID(qhp->ep->hwtid) | 920 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 921 922 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 923 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 924 term = (struct terminate_message *)wqe->u.terminate.termmsg; 925 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 926 term->layer_etype = qhp->attr.layer_etype; 927 term->ecode = qhp->attr.ecode; 928 } else 929 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 930 creds(toep, sizeof(*wqe)); 931 t4_wrq_tx(qhp->rhp->rdev.adap, wr); 932 } 933 934 /* Assumes qhp lock is held. */ 935 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 936 struct c4iw_cq *schp) 937 { 938 int count; 939 int flushed; 940 unsigned long flag; 941 942 CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp, 943 schp); 944 945 /* locking hierarchy: cq lock first, then qp lock. */ 946 spin_lock_irqsave(&rchp->lock, flag); 947 spin_lock(&qhp->lock); 948 c4iw_flush_hw_cq(&rchp->cq); 949 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 950 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 951 spin_unlock(&qhp->lock); 952 spin_unlock_irqrestore(&rchp->lock, flag); 953 if (flushed) { 954 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 955 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 956 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 957 } 958 959 /* locking hierarchy: cq lock first, then qp lock. */ 960 spin_lock_irqsave(&schp->lock, flag); 961 spin_lock(&qhp->lock); 962 c4iw_flush_hw_cq(&schp->cq); 963 c4iw_count_scqes(&schp->cq, &qhp->wq, &count); 964 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count); 965 spin_unlock(&qhp->lock); 966 spin_unlock_irqrestore(&schp->lock, flag); 967 if (flushed) { 968 spin_lock_irqsave(&schp->comp_handler_lock, flag); 969 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context); 970 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 971 } 972 } 973 974 static void flush_qp(struct c4iw_qp *qhp) 975 { 976 struct c4iw_cq *rchp, *schp; 977 unsigned long flag; 978 979 rchp = get_chp(qhp->rhp, qhp->attr.rcq); 980 schp = get_chp(qhp->rhp, qhp->attr.scq); 981 982 if (qhp->ibqp.uobject) { 983 t4_set_wq_in_error(&qhp->wq); 984 t4_set_cq_in_error(&rchp->cq); 985 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 986 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 987 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 988 if (schp != rchp) { 989 t4_set_cq_in_error(&schp->cq); 990 spin_lock_irqsave(&schp->comp_handler_lock, flag); 991 (*schp->ibcq.comp_handler)(&schp->ibcq, 992 schp->ibcq.cq_context); 993 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 994 } 995 return; 996 } 997 __flush_qp(qhp, rchp, schp); 998 } 999 1000 static int 1001 rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep) 1002 { 1003 struct c4iw_rdev *rdev = &rhp->rdev; 1004 struct adapter *sc = rdev->adap; 1005 struct fw_ri_wr *wqe; 1006 int ret; 1007 struct wrqe *wr; 1008 struct socket *so = ep->com.so; 1009 struct inpcb *inp = sotoinpcb(so); 1010 struct tcpcb *tp = intotcpcb(inp); 1011 struct toepcb *toep = tp->t_toe; 1012 1013 KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__)); 1014 1015 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1016 qhp->wq.sq.qid, ep->hwtid); 1017 1018 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1019 if (wr == NULL) 1020 return (0); 1021 wqe = wrtod(wr); 1022 1023 memset(wqe, 0, sizeof *wqe); 1024 1025 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL); 1026 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1027 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1028 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1029 wqe->u.fini.type = FW_RI_TYPE_FINI; 1030 1031 c4iw_init_wr_wait(&ep->com.wr_wait); 1032 1033 creds(toep, sizeof(*wqe)); 1034 t4_wrq_tx(sc, wr); 1035 1036 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1037 qhp->wq.sq.qid, __func__); 1038 return ret; 1039 } 1040 1041 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1042 { 1043 CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type); 1044 memset(&init->u, 0, sizeof init->u); 1045 switch (p2p_type) { 1046 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1047 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1048 init->u.write.stag_sink = cpu_to_be32(1); 1049 init->u.write.to_sink = cpu_to_be64(1); 1050 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1051 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1052 sizeof(struct fw_ri_immd), 1053 16); 1054 break; 1055 case FW_RI_INIT_P2PTYPE_READ_REQ: 1056 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1057 init->u.read.stag_src = cpu_to_be32(1); 1058 init->u.read.to_src_lo = cpu_to_be32(1); 1059 init->u.read.stag_sink = cpu_to_be32(1); 1060 init->u.read.to_sink_lo = cpu_to_be32(1); 1061 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1062 break; 1063 } 1064 } 1065 1066 static void 1067 creds(struct toepcb *toep, size_t wrsize) 1068 { 1069 struct ofld_tx_sdesc *txsd; 1070 1071 CTR3(KTR_IW_CXGBE, "%s:creB %p %u", __func__, toep , wrsize); 1072 INP_WLOCK(toep->inp); 1073 txsd = &toep->txsd[toep->txsd_pidx]; 1074 txsd->tx_credits = howmany(wrsize, 16); 1075 txsd->plen = 0; 1076 KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0, 1077 ("%s: not enough credits (%d)", __func__, toep->tx_credits)); 1078 toep->tx_credits -= txsd->tx_credits; 1079 if (__predict_false(++toep->txsd_pidx == toep->txsd_total)) 1080 toep->txsd_pidx = 0; 1081 toep->txsd_avail--; 1082 INP_WUNLOCK(toep->inp); 1083 CTR5(KTR_IW_CXGBE, "%s:creE %p %u %u %u", __func__, toep , 1084 txsd->tx_credits, toep->tx_credits, toep->txsd_pidx); 1085 } 1086 1087 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1088 { 1089 struct fw_ri_wr *wqe; 1090 int ret; 1091 struct wrqe *wr; 1092 struct c4iw_ep *ep = qhp->ep; 1093 struct c4iw_rdev *rdev = &qhp->rhp->rdev; 1094 struct adapter *sc = rdev->adap; 1095 struct socket *so = ep->com.so; 1096 struct inpcb *inp = sotoinpcb(so); 1097 struct tcpcb *tp = intotcpcb(inp); 1098 struct toepcb *toep = tp->t_toe; 1099 1100 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1101 qhp->wq.sq.qid, ep->hwtid); 1102 1103 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1104 if (wr == NULL) 1105 return (0); 1106 wqe = wrtod(wr); 1107 1108 memset(wqe, 0, sizeof *wqe); 1109 1110 wqe->op_compl = cpu_to_be32( 1111 V_FW_WR_OP(FW_RI_WR) | 1112 F_FW_WR_COMPL); 1113 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1114 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1115 1116 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1117 1118 wqe->u.init.type = FW_RI_TYPE_INIT; 1119 wqe->u.init.mpareqbit_p2ptype = 1120 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) | 1121 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type); 1122 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1123 if (qhp->attr.mpa_attr.recv_marker_enabled) 1124 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1125 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1126 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1127 if (qhp->attr.mpa_attr.crc_enabled) 1128 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1129 1130 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1131 FW_RI_QP_RDMA_WRITE_ENABLE | 1132 FW_RI_QP_BIND_ENABLE; 1133 if (!qhp->ibqp.uobject) 1134 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1135 FW_RI_QP_STAG0_ENABLE; 1136 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1137 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1138 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1139 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1140 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1141 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1142 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1143 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1144 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1145 wqe->u.init.iss = cpu_to_be32(ep->snd_seq); 1146 wqe->u.init.irs = cpu_to_be32(ep->rcv_seq); 1147 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1148 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1149 sc->vres.rq.start); 1150 if (qhp->attr.mpa_attr.initiator) 1151 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1152 1153 c4iw_init_wr_wait(&ep->com.wr_wait); 1154 1155 creds(toep, sizeof(*wqe)); 1156 t4_wrq_tx(sc, wr); 1157 1158 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1159 qhp->wq.sq.qid, __func__); 1160 1161 toep->ulp_mode = ULP_MODE_RDMA; 1162 1163 return ret; 1164 } 1165 1166 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1167 enum c4iw_qp_attr_mask mask, 1168 struct c4iw_qp_attributes *attrs, 1169 int internal) 1170 { 1171 int ret = 0; 1172 struct c4iw_qp_attributes newattr = qhp->attr; 1173 int disconnect = 0; 1174 int terminate = 0; 1175 int abort = 0; 1176 int free = 0; 1177 struct c4iw_ep *ep = NULL; 1178 1179 CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp, 1180 qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep); 1181 CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state, 1182 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1183 1184 mutex_lock(&qhp->mutex); 1185 1186 /* Process attr changes if in IDLE */ 1187 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1188 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1189 ret = -EIO; 1190 goto out; 1191 } 1192 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1193 newattr.enable_rdma_read = attrs->enable_rdma_read; 1194 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1195 newattr.enable_rdma_write = attrs->enable_rdma_write; 1196 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1197 newattr.enable_bind = attrs->enable_bind; 1198 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1199 if (attrs->max_ord > c4iw_max_read_depth) { 1200 ret = -EINVAL; 1201 goto out; 1202 } 1203 newattr.max_ord = attrs->max_ord; 1204 } 1205 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1206 if (attrs->max_ird > c4iw_max_read_depth) { 1207 ret = -EINVAL; 1208 goto out; 1209 } 1210 newattr.max_ird = attrs->max_ird; 1211 } 1212 qhp->attr = newattr; 1213 } 1214 1215 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1216 goto out; 1217 if (qhp->attr.state == attrs->next_state) 1218 goto out; 1219 1220 switch (qhp->attr.state) { 1221 case C4IW_QP_STATE_IDLE: 1222 switch (attrs->next_state) { 1223 case C4IW_QP_STATE_RTS: 1224 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1225 ret = -EINVAL; 1226 goto out; 1227 } 1228 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1229 ret = -EINVAL; 1230 goto out; 1231 } 1232 qhp->attr.mpa_attr = attrs->mpa_attr; 1233 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1234 qhp->ep = qhp->attr.llp_stream_handle; 1235 set_state(qhp, C4IW_QP_STATE_RTS); 1236 1237 /* 1238 * Ref the endpoint here and deref when we 1239 * disassociate the endpoint from the QP. This 1240 * happens in CLOSING->IDLE transition or *->ERROR 1241 * transition. 1242 */ 1243 c4iw_get_ep(&qhp->ep->com); 1244 ret = rdma_init(rhp, qhp); 1245 if (ret) 1246 goto err; 1247 break; 1248 case C4IW_QP_STATE_ERROR: 1249 set_state(qhp, C4IW_QP_STATE_ERROR); 1250 flush_qp(qhp); 1251 break; 1252 default: 1253 ret = -EINVAL; 1254 goto out; 1255 } 1256 break; 1257 case C4IW_QP_STATE_RTS: 1258 switch (attrs->next_state) { 1259 case C4IW_QP_STATE_CLOSING: 1260 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2); 1261 set_state(qhp, C4IW_QP_STATE_CLOSING); 1262 ep = qhp->ep; 1263 if (!internal) { 1264 abort = 0; 1265 disconnect = 1; 1266 c4iw_get_ep(&qhp->ep->com); 1267 } 1268 if (qhp->ibqp.uobject) 1269 t4_set_wq_in_error(&qhp->wq); 1270 ret = rdma_fini(rhp, qhp, ep); 1271 if (ret) 1272 goto err; 1273 break; 1274 case C4IW_QP_STATE_TERMINATE: 1275 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1276 qhp->attr.layer_etype = attrs->layer_etype; 1277 qhp->attr.ecode = attrs->ecode; 1278 if (qhp->ibqp.uobject) 1279 t4_set_wq_in_error(&qhp->wq); 1280 ep = qhp->ep; 1281 if (!internal) 1282 terminate = 1; 1283 disconnect = 1; 1284 c4iw_get_ep(&qhp->ep->com); 1285 break; 1286 case C4IW_QP_STATE_ERROR: 1287 set_state(qhp, C4IW_QP_STATE_ERROR); 1288 if (qhp->ibqp.uobject) 1289 t4_set_wq_in_error(&qhp->wq); 1290 if (!internal) { 1291 abort = 1; 1292 disconnect = 1; 1293 ep = qhp->ep; 1294 c4iw_get_ep(&qhp->ep->com); 1295 } 1296 goto err; 1297 break; 1298 default: 1299 ret = -EINVAL; 1300 goto out; 1301 } 1302 break; 1303 case C4IW_QP_STATE_CLOSING: 1304 if (!internal) { 1305 ret = -EINVAL; 1306 goto out; 1307 } 1308 switch (attrs->next_state) { 1309 case C4IW_QP_STATE_IDLE: 1310 flush_qp(qhp); 1311 set_state(qhp, C4IW_QP_STATE_IDLE); 1312 qhp->attr.llp_stream_handle = NULL; 1313 c4iw_put_ep(&qhp->ep->com); 1314 qhp->ep = NULL; 1315 wake_up(&qhp->wait); 1316 break; 1317 case C4IW_QP_STATE_ERROR: 1318 goto err; 1319 default: 1320 ret = -EINVAL; 1321 goto err; 1322 } 1323 break; 1324 case C4IW_QP_STATE_ERROR: 1325 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1326 ret = -EINVAL; 1327 goto out; 1328 } 1329 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1330 ret = -EINVAL; 1331 goto out; 1332 } 1333 set_state(qhp, C4IW_QP_STATE_IDLE); 1334 break; 1335 case C4IW_QP_STATE_TERMINATE: 1336 if (!internal) { 1337 ret = -EINVAL; 1338 goto out; 1339 } 1340 goto err; 1341 break; 1342 default: 1343 printf("%s in a bad state %d\n", 1344 __func__, qhp->attr.state); 1345 ret = -EINVAL; 1346 goto err; 1347 break; 1348 } 1349 goto out; 1350 err: 1351 CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__, 1352 qhp->ep, qhp->wq.sq.qid); 1353 1354 /* disassociate the LLP connection */ 1355 qhp->attr.llp_stream_handle = NULL; 1356 if (!ep) 1357 ep = qhp->ep; 1358 qhp->ep = NULL; 1359 set_state(qhp, C4IW_QP_STATE_ERROR); 1360 free = 1; 1361 BUG_ON(!ep); 1362 flush_qp(qhp); 1363 wake_up(&qhp->wait); 1364 out: 1365 mutex_unlock(&qhp->mutex); 1366 1367 if (terminate) 1368 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1369 1370 /* 1371 * If disconnect is 1, then we need to initiate a disconnect 1372 * on the EP. This can be a normal close (RTS->CLOSING) or 1373 * an abnormal close (RTS/CLOSING->ERROR). 1374 */ 1375 if (disconnect) { 1376 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1377 GFP_KERNEL); 1378 c4iw_put_ep(&ep->com); 1379 } 1380 1381 /* 1382 * If free is 1, then we've disassociated the EP from the QP 1383 * and we need to dereference the EP. 1384 */ 1385 if (free) 1386 c4iw_put_ep(&ep->com); 1387 CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state); 1388 return ret; 1389 } 1390 1391 static int enable_qp_db(int id, void *p, void *data) 1392 { 1393 struct c4iw_qp *qp = p; 1394 1395 t4_enable_wq_db(&qp->wq); 1396 return 0; 1397 } 1398 1399 int c4iw_destroy_qp(struct ib_qp *ib_qp) 1400 { 1401 struct c4iw_dev *rhp; 1402 struct c4iw_qp *qhp; 1403 struct c4iw_qp_attributes attrs; 1404 struct c4iw_ucontext *ucontext; 1405 1406 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp); 1407 qhp = to_c4iw_qp(ib_qp); 1408 rhp = qhp->rhp; 1409 1410 attrs.next_state = C4IW_QP_STATE_ERROR; 1411 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1412 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1413 else 1414 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1415 wait_event(qhp->wait, !qhp->ep); 1416 1417 spin_lock_irq(&rhp->lock); 1418 remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1419 rhp->qpcnt--; 1420 BUG_ON(rhp->qpcnt < 0); 1421 if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) { 1422 rhp->rdev.stats.db_state_transitions++; 1423 rhp->db_state = NORMAL; 1424 idr_for_each(&rhp->qpidr, enable_qp_db, NULL); 1425 } 1426 spin_unlock_irq(&rhp->lock); 1427 atomic_dec(&qhp->refcnt); 1428 wait_event(qhp->wait, !atomic_read(&qhp->refcnt)); 1429 1430 ucontext = ib_qp->uobject ? 1431 to_c4iw_ucontext(ib_qp->uobject->context) : NULL; 1432 destroy_qp(&rhp->rdev, &qhp->wq, 1433 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1434 1435 CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp, 1436 qhp->wq.sq.qid); 1437 kfree(qhp); 1438 return 0; 1439 } 1440 1441 static int disable_qp_db(int id, void *p, void *data) 1442 { 1443 struct c4iw_qp *qp = p; 1444 1445 t4_disable_wq_db(&qp->wq); 1446 return 0; 1447 } 1448 1449 struct ib_qp * 1450 c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1451 struct ib_udata *udata) 1452 { 1453 struct c4iw_dev *rhp; 1454 struct c4iw_qp *qhp; 1455 struct c4iw_pd *php; 1456 struct c4iw_cq *schp; 1457 struct c4iw_cq *rchp; 1458 struct c4iw_create_qp_resp uresp; 1459 int sqsize, rqsize; 1460 struct c4iw_ucontext *ucontext; 1461 int ret; 1462 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4; 1463 1464 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 1465 1466 if (attrs->qp_type != IB_QPT_RC) 1467 return ERR_PTR(-EINVAL); 1468 1469 php = to_c4iw_pd(pd); 1470 rhp = php->rhp; 1471 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1472 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1473 if (!schp || !rchp) 1474 return ERR_PTR(-EINVAL); 1475 1476 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1477 return ERR_PTR(-EINVAL); 1478 1479 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16); 1480 if (rqsize > T4_MAX_RQ_SIZE) 1481 return ERR_PTR(-E2BIG); 1482 1483 sqsize = roundup(attrs->cap.max_send_wr + 1, 16); 1484 if (sqsize > T4_MAX_SQ_SIZE) 1485 return ERR_PTR(-E2BIG); 1486 1487 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1488 1489 1490 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1491 if (!qhp) 1492 return ERR_PTR(-ENOMEM); 1493 qhp->wq.sq.size = sqsize; 1494 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue; 1495 qhp->wq.rq.size = rqsize; 1496 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue; 1497 1498 if (ucontext) { 1499 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1500 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1501 } 1502 1503 CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu", 1504 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize); 1505 1506 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1507 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1508 if (ret) 1509 goto err1; 1510 1511 attrs->cap.max_recv_wr = rqsize - 1; 1512 attrs->cap.max_send_wr = sqsize - 1; 1513 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1514 1515 qhp->rhp = rhp; 1516 qhp->attr.pd = php->pdid; 1517 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1518 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1519 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1520 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1521 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1522 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1523 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1524 qhp->attr.state = C4IW_QP_STATE_IDLE; 1525 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1526 qhp->attr.enable_rdma_read = 1; 1527 qhp->attr.enable_rdma_write = 1; 1528 qhp->attr.enable_bind = 1; 1529 qhp->attr.max_ord = 1; 1530 qhp->attr.max_ird = 1; 1531 spin_lock_init(&qhp->lock); 1532 mutex_init(&qhp->mutex); 1533 init_waitqueue_head(&qhp->wait); 1534 atomic_set(&qhp->refcnt, 1); 1535 1536 spin_lock_irq(&rhp->lock); 1537 if (rhp->db_state != NORMAL) 1538 t4_disable_wq_db(&qhp->wq); 1539 if (++rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) { 1540 rhp->rdev.stats.db_state_transitions++; 1541 rhp->db_state = FLOW_CONTROL; 1542 idr_for_each(&rhp->qpidr, disable_qp_db, NULL); 1543 } 1544 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1545 spin_unlock_irq(&rhp->lock); 1546 if (ret) 1547 goto err2; 1548 1549 if (udata) { 1550 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL); 1551 if (!mm1) { 1552 ret = -ENOMEM; 1553 goto err3; 1554 } 1555 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL); 1556 if (!mm2) { 1557 ret = -ENOMEM; 1558 goto err4; 1559 } 1560 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL); 1561 if (!mm3) { 1562 ret = -ENOMEM; 1563 goto err5; 1564 } 1565 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL); 1566 if (!mm4) { 1567 ret = -ENOMEM; 1568 goto err6; 1569 } 1570 uresp.flags = 0; 1571 uresp.qid_mask = rhp->rdev.qpmask; 1572 uresp.sqid = qhp->wq.sq.qid; 1573 uresp.sq_size = qhp->wq.sq.size; 1574 uresp.sq_memsize = qhp->wq.sq.memsize; 1575 uresp.rqid = qhp->wq.rq.qid; 1576 uresp.rq_size = qhp->wq.rq.size; 1577 uresp.rq_memsize = qhp->wq.rq.memsize; 1578 spin_lock(&ucontext->mmap_lock); 1579 uresp.sq_key = ucontext->key; 1580 ucontext->key += PAGE_SIZE; 1581 uresp.rq_key = ucontext->key; 1582 ucontext->key += PAGE_SIZE; 1583 uresp.sq_db_gts_key = ucontext->key; 1584 ucontext->key += PAGE_SIZE; 1585 uresp.rq_db_gts_key = ucontext->key; 1586 ucontext->key += PAGE_SIZE; 1587 spin_unlock(&ucontext->mmap_lock); 1588 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1589 if (ret) 1590 goto err7; 1591 mm1->key = uresp.sq_key; 1592 mm1->addr = qhp->wq.sq.phys_addr; 1593 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1594 CTR4(KTR_IW_CXGBE, "%s mm1 %x, %x, %d", __func__, mm1->key, 1595 mm1->addr, mm1->len); 1596 insert_mmap(ucontext, mm1); 1597 mm2->key = uresp.rq_key; 1598 mm2->addr = vtophys(qhp->wq.rq.queue); 1599 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1600 CTR4(KTR_IW_CXGBE, "%s mm2 %x, %x, %d", __func__, mm2->key, 1601 mm2->addr, mm2->len); 1602 insert_mmap(ucontext, mm2); 1603 mm3->key = uresp.sq_db_gts_key; 1604 mm3->addr = qhp->wq.sq.udb; 1605 mm3->len = PAGE_SIZE; 1606 CTR4(KTR_IW_CXGBE, "%s mm3 %x, %x, %d", __func__, mm3->key, 1607 mm3->addr, mm3->len); 1608 insert_mmap(ucontext, mm3); 1609 mm4->key = uresp.rq_db_gts_key; 1610 mm4->addr = qhp->wq.rq.udb; 1611 mm4->len = PAGE_SIZE; 1612 CTR4(KTR_IW_CXGBE, "%s mm4 %x, %x, %d", __func__, mm4->key, 1613 mm4->addr, mm4->len); 1614 insert_mmap(ucontext, mm4); 1615 } 1616 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1617 init_timer(&(qhp->timer)); 1618 CTR5(KTR_IW_CXGBE, 1619 "%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x", 1620 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries, 1621 qhp->wq.sq.qid); 1622 return &qhp->ibqp; 1623 err7: 1624 kfree(mm4); 1625 err6: 1626 kfree(mm3); 1627 err5: 1628 kfree(mm2); 1629 err4: 1630 kfree(mm1); 1631 err3: 1632 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1633 err2: 1634 destroy_qp(&rhp->rdev, &qhp->wq, 1635 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1636 err1: 1637 kfree(qhp); 1638 return ERR_PTR(ret); 1639 } 1640 1641 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1642 int attr_mask, struct ib_udata *udata) 1643 { 1644 struct c4iw_dev *rhp; 1645 struct c4iw_qp *qhp; 1646 enum c4iw_qp_attr_mask mask = 0; 1647 struct c4iw_qp_attributes attrs; 1648 1649 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp); 1650 1651 /* iwarp does not support the RTR state */ 1652 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1653 attr_mask &= ~IB_QP_STATE; 1654 1655 /* Make sure we still have something left to do */ 1656 if (!attr_mask) 1657 return 0; 1658 1659 memset(&attrs, 0, sizeof attrs); 1660 qhp = to_c4iw_qp(ibqp); 1661 rhp = qhp->rhp; 1662 1663 attrs.next_state = c4iw_convert_state(attr->qp_state); 1664 attrs.enable_rdma_read = (attr->qp_access_flags & 1665 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1666 attrs.enable_rdma_write = (attr->qp_access_flags & 1667 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1668 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1669 1670 1671 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1672 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1673 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1674 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1675 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1676 1677 /* 1678 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for 1679 * ringing the queue db when we're in DB_FULL mode. 1680 */ 1681 attrs.sq_db_inc = attr->sq_psn; 1682 attrs.rq_db_inc = attr->rq_psn; 1683 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0; 1684 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0; 1685 1686 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1687 } 1688 1689 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1690 { 1691 CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn); 1692 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1693 } 1694 1695 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1696 int attr_mask, struct ib_qp_init_attr *init_attr) 1697 { 1698 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1699 1700 memset(attr, 0, sizeof *attr); 1701 memset(init_attr, 0, sizeof *init_attr); 1702 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1703 return 0; 1704 } 1705 #endif 1706