xref: /freebsd/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h (revision d9f0ce31900a48d1a2bfc1c8c86f79d1e831451a)
1 /*
2  * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *	  copyright notice, this list of conditions and the following
16  *	  disclaimer.
17  *      - Redistributions in binary form must reproduce the above
18  *	  copyright notice, this list of conditions and the following
19  *	  disclaimer in the documentation and/or other materials
20  *	  provided with the distribution.
21  *
22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29  * SOFTWARE.
30  *
31  * $FreeBSD$
32  */
33 #ifndef __IW_CXGB4_H__
34 #define __IW_CXGB4_H__
35 
36 #include <linux/list.h>
37 #include <linux/spinlock.h>
38 #include <linux/idr.h>
39 #include <linux/completion.h>
40 #include <linux/netdevice.h>
41 #include <linux/sched.h>
42 #include <linux/pci.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
47 #include <linux/io.h>
48 
49 #include <asm/byteorder.h>
50 
51 #include <netinet/in.h>
52 #include <netinet/toecore.h>
53 
54 #include <rdma/ib_verbs.h>
55 #include <rdma/iw_cm.h>
56 
57 #undef prefetch
58 
59 #include "common/common.h"
60 #include "common/t4_msg.h"
61 #include "common/t4_regs.h"
62 #include "common/t4_tcb.h"
63 #include "t4_l2t.h"
64 
65 #define DRV_NAME "iw_cxgbe"
66 #define MOD DRV_NAME ":"
67 #define KTR_IW_CXGBE	KTR_SPARE3
68 
69 extern int c4iw_debug;
70 #define PDBG(fmt, args...) \
71 do { \
72 	if (c4iw_debug) \
73 		printf(MOD fmt, ## args); \
74 } while (0)
75 
76 #include "t4.h"
77 
78 static inline void *cplhdr(struct mbuf *m)
79 {
80 	return mtod(m, void*);
81 }
82 
83 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
84 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
85 
86 #define C4IW_ID_TABLE_F_RANDOM 1       /* Pseudo-randomize the id's returned */
87 #define C4IW_ID_TABLE_F_EMPTY  2       /* Table is initially empty */
88 
89 struct c4iw_id_table {
90 	u32 flags;
91 	u32 start;              /* logical minimal id */
92 	u32 last;               /* hint for find */
93 	u32 max;
94 	spinlock_t lock;
95 	unsigned long *table;
96 };
97 
98 struct c4iw_resource {
99 	struct c4iw_id_table tpt_table;
100 	struct c4iw_id_table qid_table;
101 	struct c4iw_id_table pdid_table;
102 };
103 
104 struct c4iw_qid_list {
105 	struct list_head entry;
106 	u32 qid;
107 };
108 
109 struct c4iw_dev_ucontext {
110 	struct list_head qpids;
111 	struct list_head cqids;
112 	struct mutex lock;
113 };
114 
115 enum c4iw_rdev_flags {
116 	T4_FATAL_ERROR = (1<<0),
117 };
118 
119 struct c4iw_stat {
120 	u64 total;
121 	u64 cur;
122 	u64 max;
123 	u64 fail;
124 };
125 
126 struct c4iw_stats {
127 	struct mutex lock;
128 	struct c4iw_stat qid;
129 	struct c4iw_stat pd;
130 	struct c4iw_stat stag;
131 	struct c4iw_stat pbl;
132 	struct c4iw_stat rqt;
133 	u64  db_full;
134 	u64  db_empty;
135 	u64  db_drop;
136 	u64  db_state_transitions;
137 };
138 
139 struct c4iw_rdev {
140 	struct adapter *adap;
141 	struct c4iw_resource resource;
142 	unsigned long qpshift;
143 	u32 qpmask;
144 	unsigned long cqshift;
145 	u32 cqmask;
146 	struct c4iw_dev_ucontext uctx;
147 	struct gen_pool *pbl_pool;
148 	struct gen_pool *rqt_pool;
149 	u32 flags;
150 	struct c4iw_stats stats;
151 };
152 
153 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
154 {
155 	return rdev->flags & T4_FATAL_ERROR;
156 }
157 
158 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
159 {
160 	return (int)(rdev->adap->vres.stag.size >> 5);
161 }
162 
163 #define C4IW_WR_TO (10*HZ)
164 
165 struct c4iw_wr_wait {
166 	int ret;
167 	atomic_t completion;
168 };
169 
170 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
171 {
172 	wr_waitp->ret = 0;
173 	atomic_set(&wr_waitp->completion, 0);
174 }
175 
176 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
177 {
178 	wr_waitp->ret = ret;
179 	atomic_set(&wr_waitp->completion, 1);
180 	wakeup(wr_waitp);
181 }
182 
183 static inline int
184 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
185     u32 hwtid, u32 qpid, const char *func)
186 {
187 	struct adapter *sc = rdev->adap;
188 	unsigned to = C4IW_WR_TO;
189 
190 	while (!atomic_read(&wr_waitp->completion)) {
191                 tsleep(wr_waitp, 0, "c4iw_wait", to);
192                 if (SIGPENDING(curthread)) {
193 			printf("%s - Device %s not responding - "
194 			    "tid %u qpid %u\n", func,
195 			    device_get_nameunit(sc->dev), hwtid, qpid);
196                         if (c4iw_fatal_error(rdev)) {
197                                 wr_waitp->ret = -EIO;
198                                 break;
199                         }
200                         to = to << 2;
201                 }
202         }
203 	if (wr_waitp->ret)
204 		CTR4(KTR_IW_CXGBE, "%s: FW reply %d tid %u qpid %u",
205 		    device_get_nameunit(sc->dev), wr_waitp->ret, hwtid, qpid);
206 	return (wr_waitp->ret);
207 }
208 
209 enum db_state {
210 	NORMAL = 0,
211 	FLOW_CONTROL = 1,
212 	RECOVERY = 2
213 };
214 
215 struct c4iw_dev {
216 	struct ib_device ibdev;
217 	struct c4iw_rdev rdev;
218 	u32 device_cap_flags;
219 	struct idr cqidr;
220 	struct idr qpidr;
221 	struct idr mmidr;
222 	spinlock_t lock;
223 	struct dentry *debugfs_root;
224 	enum db_state db_state;
225 	int qpcnt;
226 };
227 
228 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
229 {
230 	return container_of(ibdev, struct c4iw_dev, ibdev);
231 }
232 
233 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
234 {
235 	return container_of(rdev, struct c4iw_dev, rdev);
236 }
237 
238 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
239 {
240 	return idr_find(&rhp->cqidr, cqid);
241 }
242 
243 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
244 {
245 	return idr_find(&rhp->qpidr, qpid);
246 }
247 
248 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
249 {
250 	return idr_find(&rhp->mmidr, mmid);
251 }
252 
253 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
254 				 void *handle, u32 id, int lock)
255 {
256 	int ret;
257 	int newid;
258 
259 	do {
260 		if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
261 			return -ENOMEM;
262 		if (lock)
263 			spin_lock_irq(&rhp->lock);
264 		ret = idr_get_new_above(idr, handle, id, &newid);
265 		BUG_ON(!ret && newid != id);
266 		if (lock)
267 			spin_unlock_irq(&rhp->lock);
268 	} while (ret == -EAGAIN);
269 
270 	return ret;
271 }
272 
273 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
274 				void *handle, u32 id)
275 {
276 	return _insert_handle(rhp, idr, handle, id, 1);
277 }
278 
279 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
280 				       void *handle, u32 id)
281 {
282 	return _insert_handle(rhp, idr, handle, id, 0);
283 }
284 
285 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
286 				   u32 id, int lock)
287 {
288 	if (lock)
289 		spin_lock_irq(&rhp->lock);
290 	idr_remove(idr, id);
291 	if (lock)
292 		spin_unlock_irq(&rhp->lock);
293 }
294 
295 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
296 {
297 	_remove_handle(rhp, idr, id, 1);
298 }
299 
300 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
301 					 struct idr *idr, u32 id)
302 {
303 	_remove_handle(rhp, idr, id, 0);
304 }
305 
306 struct c4iw_pd {
307 	struct ib_pd ibpd;
308 	u32 pdid;
309 	struct c4iw_dev *rhp;
310 };
311 
312 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
313 {
314 	return container_of(ibpd, struct c4iw_pd, ibpd);
315 }
316 
317 struct tpt_attributes {
318 	u64 len;
319 	u64 va_fbo;
320 	enum fw_ri_mem_perms perms;
321 	u32 stag;
322 	u32 pdid;
323 	u32 qpid;
324 	u32 pbl_addr;
325 	u32 pbl_size;
326 	u32 state:1;
327 	u32 type:2;
328 	u32 rsvd:1;
329 	u32 remote_invaliate_disable:1;
330 	u32 zbva:1;
331 	u32 mw_bind_enable:1;
332 	u32 page_size:5;
333 };
334 
335 struct c4iw_mr {
336 	struct ib_mr ibmr;
337 	struct ib_umem *umem;
338 	struct c4iw_dev *rhp;
339 	u64 kva;
340 	struct tpt_attributes attr;
341 };
342 
343 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
344 {
345 	return container_of(ibmr, struct c4iw_mr, ibmr);
346 }
347 
348 struct c4iw_mw {
349 	struct ib_mw ibmw;
350 	struct c4iw_dev *rhp;
351 	u64 kva;
352 	struct tpt_attributes attr;
353 };
354 
355 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
356 {
357 	return container_of(ibmw, struct c4iw_mw, ibmw);
358 }
359 
360 struct c4iw_fr_page_list {
361 	struct ib_fast_reg_page_list ibpl;
362 	DECLARE_PCI_UNMAP_ADDR(mapping);
363 	dma_addr_t dma_addr;
364 	struct c4iw_dev *dev;
365 	int size;
366 };
367 
368 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
369 					struct ib_fast_reg_page_list *ibpl)
370 {
371 	return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
372 }
373 
374 struct c4iw_cq {
375 	struct ib_cq ibcq;
376 	struct c4iw_dev *rhp;
377 	struct t4_cq cq;
378 	spinlock_t lock;
379 	spinlock_t comp_handler_lock;
380 	atomic_t refcnt;
381 	wait_queue_head_t wait;
382 };
383 
384 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
385 {
386 	return container_of(ibcq, struct c4iw_cq, ibcq);
387 }
388 
389 struct c4iw_mpa_attributes {
390 	u8 initiator;
391 	u8 recv_marker_enabled;
392 	u8 xmit_marker_enabled;
393 	u8 crc_enabled;
394 	u8 enhanced_rdma_conn;
395 	u8 version;
396 	u8 p2p_type;
397 };
398 
399 struct c4iw_qp_attributes {
400 	u32 scq;
401 	u32 rcq;
402 	u32 sq_num_entries;
403 	u32 rq_num_entries;
404 	u32 sq_max_sges;
405 	u32 sq_max_sges_rdma_write;
406 	u32 rq_max_sges;
407 	u32 state;
408 	u8 enable_rdma_read;
409 	u8 enable_rdma_write;
410 	u8 enable_bind;
411 	u8 enable_mmid0_fastreg;
412 	u32 max_ord;
413 	u32 max_ird;
414 	u32 pd;
415 	u32 next_state;
416 	char terminate_buffer[52];
417 	u32 terminate_msg_len;
418 	u8 is_terminate_local;
419 	struct c4iw_mpa_attributes mpa_attr;
420 	struct c4iw_ep *llp_stream_handle;
421 	u8 layer_etype;
422 	u8 ecode;
423 	u16 sq_db_inc;
424 	u16 rq_db_inc;
425 };
426 
427 struct c4iw_qp {
428 	struct ib_qp ibqp;
429 	struct c4iw_dev *rhp;
430 	struct c4iw_ep *ep;
431 	struct c4iw_qp_attributes attr;
432 	struct t4_wq wq;
433 	spinlock_t lock;
434 	struct mutex mutex;
435 	atomic_t refcnt;
436 	wait_queue_head_t wait;
437 	struct timer_list timer;
438 	int sq_sig_all;
439 };
440 
441 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
442 {
443 	return container_of(ibqp, struct c4iw_qp, ibqp);
444 }
445 
446 struct c4iw_ucontext {
447 	struct ib_ucontext ibucontext;
448 	struct c4iw_dev_ucontext uctx;
449 	u32 key;
450 	spinlock_t mmap_lock;
451 	struct list_head mmaps;
452 };
453 
454 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
455 {
456 	return container_of(c, struct c4iw_ucontext, ibucontext);
457 }
458 
459 struct c4iw_mm_entry {
460 	struct list_head entry;
461 	u64 addr;
462 	u32 key;
463 	unsigned len;
464 };
465 
466 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
467 						u32 key, unsigned len)
468 {
469 	struct list_head *pos, *nxt;
470 	struct c4iw_mm_entry *mm;
471 
472 	spin_lock(&ucontext->mmap_lock);
473 	list_for_each_safe(pos, nxt, &ucontext->mmaps) {
474 
475 		mm = list_entry(pos, struct c4iw_mm_entry, entry);
476 		if (mm->key == key && mm->len == len) {
477 			list_del_init(&mm->entry);
478 			spin_unlock(&ucontext->mmap_lock);
479 			CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
480 			     __func__, key, (unsigned long long) mm->addr,
481 			     mm->len);
482 			return mm;
483 		}
484 	}
485 	spin_unlock(&ucontext->mmap_lock);
486 	return NULL;
487 }
488 
489 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
490 			       struct c4iw_mm_entry *mm)
491 {
492 	spin_lock(&ucontext->mmap_lock);
493 	CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
494 	    (unsigned long long) mm->addr, mm->len);
495 	list_add_tail(&mm->entry, &ucontext->mmaps);
496 	spin_unlock(&ucontext->mmap_lock);
497 }
498 
499 enum c4iw_qp_attr_mask {
500 	C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
501 	C4IW_QP_ATTR_SQ_DB = 1<<1,
502 	C4IW_QP_ATTR_RQ_DB = 1<<2,
503 	C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
504 	C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
505 	C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
506 	C4IW_QP_ATTR_MAX_ORD = 1 << 11,
507 	C4IW_QP_ATTR_MAX_IRD = 1 << 12,
508 	C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
509 	C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
510 	C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
511 	C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
512 	C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
513 				     C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
514 				     C4IW_QP_ATTR_MAX_ORD |
515 				     C4IW_QP_ATTR_MAX_IRD |
516 				     C4IW_QP_ATTR_LLP_STREAM_HANDLE |
517 				     C4IW_QP_ATTR_STREAM_MSG_BUFFER |
518 				     C4IW_QP_ATTR_MPA_ATTR |
519 				     C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
520 };
521 
522 int c4iw_modify_qp(struct c4iw_dev *rhp,
523 				struct c4iw_qp *qhp,
524 				enum c4iw_qp_attr_mask mask,
525 				struct c4iw_qp_attributes *attrs,
526 				int internal);
527 
528 enum c4iw_qp_state {
529 	C4IW_QP_STATE_IDLE,
530 	C4IW_QP_STATE_RTS,
531 	C4IW_QP_STATE_ERROR,
532 	C4IW_QP_STATE_TERMINATE,
533 	C4IW_QP_STATE_CLOSING,
534 	C4IW_QP_STATE_TOT
535 };
536 
537 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
538 {
539 	switch (ib_state) {
540 	case IB_QPS_RESET:
541 	case IB_QPS_INIT:
542 		return C4IW_QP_STATE_IDLE;
543 	case IB_QPS_RTS:
544 		return C4IW_QP_STATE_RTS;
545 	case IB_QPS_SQD:
546 		return C4IW_QP_STATE_CLOSING;
547 	case IB_QPS_SQE:
548 		return C4IW_QP_STATE_TERMINATE;
549 	case IB_QPS_ERR:
550 		return C4IW_QP_STATE_ERROR;
551 	default:
552 		return -1;
553 	}
554 }
555 
556 static inline int to_ib_qp_state(int c4iw_qp_state)
557 {
558 	switch (c4iw_qp_state) {
559 	case C4IW_QP_STATE_IDLE:
560 		return IB_QPS_INIT;
561 	case C4IW_QP_STATE_RTS:
562 		return IB_QPS_RTS;
563 	case C4IW_QP_STATE_CLOSING:
564 		return IB_QPS_SQD;
565 	case C4IW_QP_STATE_TERMINATE:
566 		return IB_QPS_SQE;
567 	case C4IW_QP_STATE_ERROR:
568 		return IB_QPS_ERR;
569 	}
570 	return IB_QPS_ERR;
571 }
572 
573 static inline u32 c4iw_ib_to_tpt_access(int a)
574 {
575 	return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
576 	       (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
577 	       (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
578 	       FW_RI_MEM_ACCESS_LOCAL_READ;
579 }
580 
581 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
582 {
583 	return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
584 	       (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
585 }
586 
587 enum c4iw_mmid_state {
588 	C4IW_STAG_STATE_VALID,
589 	C4IW_STAG_STATE_INVALID
590 };
591 
592 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
593 
594 #define MPA_KEY_REQ "MPA ID Req Frame"
595 #define MPA_KEY_REP "MPA ID Rep Frame"
596 
597 #define MPA_MAX_PRIVATE_DATA	256
598 #define MPA_ENHANCED_RDMA_CONN	0x10
599 #define MPA_REJECT		0x20
600 #define MPA_CRC			0x40
601 #define MPA_MARKERS		0x80
602 #define MPA_FLAGS_MASK		0xE0
603 
604 #define MPA_V2_PEER2PEER_MODEL          0x8000
605 #define MPA_V2_ZERO_LEN_FPDU_RTR        0x4000
606 #define MPA_V2_RDMA_WRITE_RTR           0x8000
607 #define MPA_V2_RDMA_READ_RTR            0x4000
608 #define MPA_V2_IRD_ORD_MASK             0x3FFF
609 
610 #define c4iw_put_ep(ep) { \
611 	CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
612 	     __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
613 	WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \
614         kref_put(&((ep)->kref), _c4iw_free_ep); \
615 }
616 
617 #define c4iw_get_ep(ep) { \
618 	CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
619 	      __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
620         kref_get(&((ep)->kref));  \
621 }
622 
623 void _c4iw_free_ep(struct kref *kref);
624 
625 struct mpa_message {
626 	u8 key[16];
627 	u8 flags;
628 	u8 revision;
629 	__be16 private_data_size;
630 	u8 private_data[0];
631 };
632 
633 struct mpa_v2_conn_params {
634 	__be16 ird;
635 	__be16 ord;
636 };
637 
638 struct terminate_message {
639 	u8 layer_etype;
640 	u8 ecode;
641 	__be16 hdrct_rsvd;
642 	u8 len_hdrs[0];
643 };
644 
645 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
646 
647 enum c4iw_layers_types {
648 	LAYER_RDMAP		= 0x00,
649 	LAYER_DDP		= 0x10,
650 	LAYER_MPA		= 0x20,
651 	RDMAP_LOCAL_CATA	= 0x00,
652 	RDMAP_REMOTE_PROT	= 0x01,
653 	RDMAP_REMOTE_OP		= 0x02,
654 	DDP_LOCAL_CATA		= 0x00,
655 	DDP_TAGGED_ERR		= 0x01,
656 	DDP_UNTAGGED_ERR	= 0x02,
657 	DDP_LLP			= 0x03
658 };
659 
660 enum c4iw_rdma_ecodes {
661 	RDMAP_INV_STAG		= 0x00,
662 	RDMAP_BASE_BOUNDS	= 0x01,
663 	RDMAP_ACC_VIOL		= 0x02,
664 	RDMAP_STAG_NOT_ASSOC	= 0x03,
665 	RDMAP_TO_WRAP		= 0x04,
666 	RDMAP_INV_VERS		= 0x05,
667 	RDMAP_INV_OPCODE	= 0x06,
668 	RDMAP_STREAM_CATA	= 0x07,
669 	RDMAP_GLOBAL_CATA	= 0x08,
670 	RDMAP_CANT_INV_STAG	= 0x09,
671 	RDMAP_UNSPECIFIED	= 0xff
672 };
673 
674 enum c4iw_ddp_ecodes {
675 	DDPT_INV_STAG		= 0x00,
676 	DDPT_BASE_BOUNDS	= 0x01,
677 	DDPT_STAG_NOT_ASSOC	= 0x02,
678 	DDPT_TO_WRAP		= 0x03,
679 	DDPT_INV_VERS		= 0x04,
680 	DDPU_INV_QN		= 0x01,
681 	DDPU_INV_MSN_NOBUF	= 0x02,
682 	DDPU_INV_MSN_RANGE	= 0x03,
683 	DDPU_INV_MO		= 0x04,
684 	DDPU_MSG_TOOBIG		= 0x05,
685 	DDPU_INV_VERS		= 0x06
686 };
687 
688 enum c4iw_mpa_ecodes {
689 	MPA_CRC_ERR		= 0x02,
690 	MPA_MARKER_ERR		= 0x03,
691 	MPA_LOCAL_CATA          = 0x05,
692 	MPA_INSUFF_IRD          = 0x06,
693 	MPA_NOMATCH_RTR         = 0x07,
694 };
695 
696 enum c4iw_ep_state {
697 	IDLE = 0,
698 	LISTEN,
699 	CONNECTING,
700 	MPA_REQ_WAIT,
701 	MPA_REQ_SENT,
702 	MPA_REQ_RCVD,
703 	MPA_REP_SENT,
704 	FPDU_MODE,
705 	ABORTING,
706 	CLOSING,
707 	MORIBUND,
708 	DEAD,
709 };
710 
711 enum c4iw_ep_flags {
712 	PEER_ABORT_IN_PROGRESS	= 0,
713 	ABORT_REQ_IN_PROGRESS	= 1,
714 	RELEASE_RESOURCES	= 2,
715 	CLOSE_SENT		= 3,
716 	TIMEOUT                 = 4,
717 	QP_REFERENCED		= 5
718 };
719 
720 enum c4iw_ep_history {
721         ACT_OPEN_REQ            = 0,
722         ACT_OFLD_CONN           = 1,
723         ACT_OPEN_RPL            = 2,
724         ACT_ESTAB               = 3,
725         PASS_ACCEPT_REQ         = 4,
726         PASS_ESTAB              = 5,
727         ABORT_UPCALL            = 6,
728         ESTAB_UPCALL            = 7,
729         CLOSE_UPCALL            = 8,
730         ULP_ACCEPT              = 9,
731         ULP_REJECT              = 10,
732         TIMEDOUT                = 11,
733         PEER_ABORT              = 12,
734         PEER_CLOSE              = 13,
735         CONNREQ_UPCALL          = 14,
736         ABORT_CONN              = 15,
737         DISCONN_UPCALL          = 16,
738         EP_DISC_CLOSE           = 17,
739         EP_DISC_ABORT           = 18,
740         CONN_RPL_UPCALL         = 19,
741         ACT_RETRY_NOMEM         = 20,
742         ACT_RETRY_INUSE         = 21,
743         CLOSE_CON_RPL           = 22,
744         EP_DISC_FAIL            = 24,
745         QP_REFED                = 25,
746         QP_DEREFED              = 26,
747         CM_ID_REFED             = 27,
748         CM_ID_DEREFED           = 28
749 };
750 
751 struct c4iw_ep_common {
752 	TAILQ_ENTRY(c4iw_ep_common) entry;	/* Work queue attachment */
753 	struct iw_cm_id *cm_id;
754 	struct c4iw_qp *qp;
755 	struct c4iw_dev *dev;
756 	enum c4iw_ep_state state;
757 	struct kref kref;
758 	struct mutex mutex;
759 	struct sockaddr_in local_addr;
760 	struct sockaddr_in remote_addr;
761 	struct c4iw_wr_wait wr_wait;
762 	unsigned long flags;
763 	unsigned long history;
764         int rpl_err;
765         int rpl_done;
766         struct thread *thread;
767         struct socket *so;
768 };
769 
770 struct c4iw_listen_ep {
771 	struct c4iw_ep_common com;
772 	unsigned int stid;
773 	int backlog;
774 };
775 
776 struct c4iw_ep {
777 	struct c4iw_ep_common com;
778 	struct c4iw_ep *parent_ep;
779 	struct timer_list timer;
780 	struct list_head entry;
781 	unsigned int atid;
782 	u32 hwtid;
783 	u32 snd_seq;
784 	u32 rcv_seq;
785 	struct l2t_entry *l2t;
786 	struct dst_entry *dst;
787 	struct c4iw_mpa_attributes mpa_attr;
788 	u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
789 	unsigned int mpa_pkt_len;
790 	u32 ird;
791 	u32 ord;
792 	u32 smac_idx;
793 	u32 tx_chan;
794 	u32 mtu;
795 	u16 mss;
796 	u16 emss;
797 	u16 plen;
798 	u16 rss_qid;
799 	u16 txq_idx;
800 	u16 ctrlq_idx;
801 	u8 tos;
802 	u8 retry_with_mpa_v1;
803 	u8 tried_with_mpa_v1;
804 };
805 
806 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
807 {
808 	return cm_id->provider_data;
809 }
810 
811 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
812 {
813 	return cm_id->provider_data;
814 }
815 
816 static inline int compute_wscale(int win)
817 {
818 	int wscale = 0;
819 
820 	while (wscale < 14 && (65535<<wscale) < win)
821 		wscale++;
822 	return wscale;
823 }
824 
825 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
826 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
827 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
828 			u32 reserved, u32 flags);
829 void c4iw_id_table_free(struct c4iw_id_table *alloc);
830 
831 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
832 
833 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
834 		     struct l2t_entry *l2t);
835 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
836 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
837 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
838 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
839 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
840 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
841 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
842 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
843 void c4iw_destroy_resource(struct c4iw_resource *rscp);
844 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
845 int c4iw_register_device(struct c4iw_dev *dev);
846 void c4iw_unregister_device(struct c4iw_dev *dev);
847 int __init c4iw_cm_init(void);
848 void __exit c4iw_cm_term(void);
849 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
850 			       struct c4iw_dev_ucontext *uctx);
851 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
852 			    struct c4iw_dev_ucontext *uctx);
853 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
854 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
855 		      struct ib_send_wr **bad_wr);
856 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
857 		      struct ib_recv_wr **bad_wr);
858 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
859 		 struct ib_mw_bind *mw_bind);
860 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
861 int c4iw_create_listen_ep(struct iw_cm_id *cm_id, int backlog);
862 void c4iw_destroy_listen_ep(struct iw_cm_id *cm_id);
863 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
864 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
865 void c4iw_qp_add_ref(struct ib_qp *qp);
866 void c4iw_qp_rem_ref(struct ib_qp *qp);
867 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
868 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
869 					struct ib_device *device,
870 					int page_list_len);
871 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
872 int c4iw_dealloc_mw(struct ib_mw *mw);
873 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
874 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
875     virt, int acc, struct ib_udata *udata, int mr_id);
876 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
877 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
878 					struct ib_phys_buf *buffer_list,
879 					int num_phys_buf,
880 					int acc,
881 					u64 *iova_start);
882 int c4iw_reregister_phys_mem(struct ib_mr *mr,
883 				     int mr_rereg_mask,
884 				     struct ib_pd *pd,
885 				     struct ib_phys_buf *buffer_list,
886 				     int num_phys_buf,
887 				     int acc, u64 *iova_start);
888 int c4iw_dereg_mr(struct ib_mr *ib_mr);
889 int c4iw_destroy_cq(struct ib_cq *ib_cq);
890 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, struct ib_cq_init_attr *attr,
891 					struct ib_ucontext *ib_context,
892 					struct ib_udata *udata);
893 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
894 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
895 int c4iw_destroy_qp(struct ib_qp *ib_qp);
896 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
897 			     struct ib_qp_init_attr *attrs,
898 			     struct ib_udata *udata);
899 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
900 				 int attr_mask, struct ib_udata *udata);
901 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
902 		     int attr_mask, struct ib_qp_init_attr *init_attr);
903 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
904 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
905 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
906 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
907 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
908 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
909 void c4iw_flush_hw_cq(struct t4_cq *cq);
910 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
911 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
912 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
913 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
914 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
915 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
916 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
917 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
918 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
919 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
920 		struct c4iw_dev_ucontext *uctx);
921 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
922 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
923 		struct c4iw_dev_ucontext *uctx);
924 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
925 void process_newconn(struct iw_cm_id *parent_cm_id,
926 		struct socket *child_so);
927 
928 extern struct cxgb4_client t4c_client;
929 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
930 extern int c4iw_max_read_depth;
931 
932 #include <sys/blist.h>
933 struct gen_pool {
934         blist_t         gen_list;
935         daddr_t         gen_base;
936         int             gen_chunk_shift;
937         struct mutex      gen_lock;
938 };
939 
940 static __inline struct gen_pool *
941 gen_pool_create(daddr_t base, u_int chunk_shift, u_int len)
942 {
943         struct gen_pool *gp;
944 
945         gp = malloc(sizeof(struct gen_pool), M_DEVBUF, M_NOWAIT);
946         if (gp == NULL)
947                 return (NULL);
948 
949         memset(gp, 0, sizeof(struct gen_pool));
950         gp->gen_list = blist_create(len >> chunk_shift, M_NOWAIT);
951         if (gp->gen_list == NULL) {
952                 free(gp, M_DEVBUF);
953                 return (NULL);
954         }
955         blist_free(gp->gen_list, 0, len >> chunk_shift);
956         gp->gen_base = base;
957         gp->gen_chunk_shift = chunk_shift;
958         //mutex_init(&gp->gen_lock, "genpool", NULL, MTX_DUPOK|MTX_DEF);
959         mutex_init(&gp->gen_lock);
960 
961         return (gp);
962 }
963 
964 static __inline unsigned long
965 gen_pool_alloc(struct gen_pool *gp, int size)
966 {
967         int chunks;
968         daddr_t blkno;
969 
970         chunks = (size + (1<<gp->gen_chunk_shift) - 1) >> gp->gen_chunk_shift;
971         mutex_lock(&gp->gen_lock);
972         blkno = blist_alloc(gp->gen_list, chunks);
973         mutex_unlock(&gp->gen_lock);
974 
975         if (blkno == SWAPBLK_NONE)
976                 return (0);
977 
978         return (gp->gen_base + ((1 << gp->gen_chunk_shift) * blkno));
979 }
980 
981 static __inline void
982 gen_pool_free(struct gen_pool *gp, daddr_t address, int size)
983 {
984         int chunks;
985         daddr_t blkno;
986 
987         chunks = (size + (1<<gp->gen_chunk_shift) - 1) >> gp->gen_chunk_shift;
988         blkno = (address - gp->gen_base) / (1 << gp->gen_chunk_shift);
989         mutex_lock(&gp->gen_lock);
990         blist_free(gp->gen_list, blkno, chunks);
991         mutex_unlock(&gp->gen_lock);
992 }
993 
994 static __inline void
995 gen_pool_destroy(struct gen_pool *gp)
996 {
997         blist_destroy(gp->gen_list);
998         free(gp, M_DEVBUF);
999 }
1000 
1001 #if defined(__i386__) || defined(__amd64__)
1002 #define L1_CACHE_BYTES 128
1003 #else
1004 #define L1_CACHE_BYTES 32
1005 #endif
1006 
1007 static inline
1008 int idr_for_each(struct idr *idp,
1009                  int (*fn)(int id, void *p, void *data), void *data)
1010 {
1011         int n, id, max, error = 0;
1012         struct idr_layer *p;
1013         struct idr_layer *pa[MAX_LEVEL];
1014         struct idr_layer **paa = &pa[0];
1015 
1016         n = idp->layers * IDR_BITS;
1017         p = idp->top;
1018         max = 1 << n;
1019 
1020         id = 0;
1021         while (id < max) {
1022                 while (n > 0 && p) {
1023                         n -= IDR_BITS;
1024                         *paa++ = p;
1025                         p = p->ary[(id >> n) & IDR_MASK];
1026                 }
1027 
1028                 if (p) {
1029                         error = fn(id, (void *)p, data);
1030                         if (error)
1031                                 break;
1032                 }
1033 
1034                 id += 1 << n;
1035                 while (n < fls(id)) {
1036                         n += IDR_BITS;
1037                         p = *--paa;
1038                 }
1039         }
1040 
1041         return error;
1042 }
1043 
1044 void c4iw_cm_init_cpl(struct adapter *);
1045 void c4iw_cm_term_cpl(struct adapter *);
1046 
1047 void your_reg_device(struct c4iw_dev *dev);
1048 
1049 #define SGE_CTRLQ_NUM	0
1050 
1051 #endif
1052