xref: /freebsd/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h (revision 6966ac055c3b7a39266fb982493330df7a097997)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *	  copyright notice, this list of conditions and the following
18  *	  disclaimer.
19  *      - Redistributions in binary form must reproduce the above
20  *	  copyright notice, this list of conditions and the following
21  *	  disclaimer in the documentation and/or other materials
22  *	  provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  *
33  * $FreeBSD$
34  */
35 #ifndef __IW_CXGB4_H__
36 #define __IW_CXGB4_H__
37 
38 #include <linux/list.h>
39 #include <linux/spinlock.h>
40 #include <linux/idr.h>
41 #include <linux/completion.h>
42 #include <linux/netdevice.h>
43 #include <linux/sched.h>
44 #include <linux/pci.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/wait.h>
47 #include <linux/kref.h>
48 #include <linux/timer.h>
49 #include <linux/io.h>
50 #include <sys/vmem.h>
51 
52 #include <asm/byteorder.h>
53 
54 #include <netinet/in.h>
55 #include <netinet/toecore.h>
56 
57 #include <rdma/ib_verbs.h>
58 #include <rdma/iw_cm.h>
59 
60 #undef prefetch
61 
62 #include "common/common.h"
63 #include "common/t4_msg.h"
64 #include "common/t4_regs.h"
65 #include "common/t4_tcb.h"
66 #include "t4_l2t.h"
67 
68 #define DRV_NAME "iw_cxgbe"
69 #define MOD DRV_NAME ":"
70 #define KTR_IW_CXGBE	KTR_SPARE3
71 
72 extern int c4iw_debug;
73 extern int use_dsgl;
74 extern int inline_threshold;
75 
76 #define PDBG(fmt, args...) \
77 do { \
78 	if (c4iw_debug) \
79 		printf(MOD fmt, ## args); \
80 } while (0)
81 
82 #include "t4.h"
83 
84 static inline void *cplhdr(struct mbuf *m)
85 {
86 	return mtod(m, void*);
87 }
88 
89 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
90 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
91 
92 #define C4IW_ID_TABLE_F_RANDOM 1       /* Pseudo-randomize the id's returned */
93 #define C4IW_ID_TABLE_F_EMPTY  2       /* Table is initially empty */
94 #define C4IW_MAX_PAGE_SIZE 0x8000000
95 
96 struct c4iw_id_table {
97 	u32 flags;
98 	u32 start;              /* logical minimal id */
99 	u32 last;               /* hint for find */
100 	u32 max;
101 	spinlock_t lock;
102 	unsigned long *table;
103 };
104 
105 struct c4iw_resource {
106 	struct c4iw_id_table tpt_table;
107 	struct c4iw_id_table qid_table;
108 	struct c4iw_id_table pdid_table;
109 };
110 
111 struct c4iw_qid_list {
112 	struct list_head entry;
113 	u32 qid;
114 };
115 
116 struct c4iw_dev_ucontext {
117 	struct list_head qpids;
118 	struct list_head cqids;
119 	struct mutex lock;
120 };
121 
122 enum c4iw_rdev_flags {
123 	T4_FATAL_ERROR = (1<<0),
124 	T4_STATUS_PAGE_DISABLED = (1<<1),
125 };
126 
127 struct c4iw_stat {
128 	u64 total;
129 	u64 cur;
130 	u64 max;
131 	u64 fail;
132 };
133 
134 struct c4iw_stats {
135 	struct mutex lock;
136 	struct c4iw_stat qid;
137 	struct c4iw_stat pd;
138 	struct c4iw_stat stag;
139 	struct c4iw_stat pbl;
140 	struct c4iw_stat rqt;
141 };
142 
143 struct c4iw_hw_queue {
144 	int t4_eq_status_entries;
145 	int t4_max_eq_size;
146 	int t4_max_iq_size;
147 	int t4_max_rq_size;
148 	int t4_max_sq_size;
149 	int t4_max_qp_depth;
150 	int t4_max_cq_depth;
151 	int t4_stat_len;
152 };
153 
154 struct c4iw_rdev {
155 	struct adapter *adap;
156 	struct c4iw_resource resource;
157 	unsigned long qpshift;
158 	u32 qpmask;
159 	unsigned long cqshift;
160 	u32 cqmask;
161 	struct c4iw_dev_ucontext uctx;
162 	vmem_t          *rqt_arena;
163 	vmem_t          *pbl_arena;
164 	u32 flags;
165 	struct c4iw_stats stats;
166 	struct c4iw_hw_queue hw_queue;
167 	struct t4_dev_status_page *status_page;
168 	unsigned long bar2_pa;
169 	void __iomem *bar2_kva;
170 	unsigned int bar2_len;
171 	struct workqueue_struct *free_workq;
172 };
173 
174 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
175 {
176 	return rdev->flags & T4_FATAL_ERROR;
177 }
178 
179 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
180 {
181 	return (int)(rdev->adap->vres.stag.size >> 5);
182 }
183 
184 #define C4IW_WR_TO (60*HZ)
185 
186 struct c4iw_wr_wait {
187 	int ret;
188 	struct completion completion;
189 };
190 
191 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
192 {
193 	wr_waitp->ret = 0;
194 	init_completion(&wr_waitp->completion);
195 }
196 
197 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
198 {
199 	wr_waitp->ret = ret;
200 	complete(&wr_waitp->completion);
201 }
202 
203 static inline int
204 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
205 		u32 hwtid, u32 qpid, struct socket *so, const char *func)
206 {
207 	struct adapter *sc = rdev->adap;
208 	unsigned to = C4IW_WR_TO;
209 	int ret;
210 	int timedout = 0;
211 	struct timeval t1, t2;
212 
213 	if (c4iw_fatal_error(rdev)) {
214 		wr_waitp->ret = -EIO;
215 		goto out;
216 	}
217 
218 	getmicrotime(&t1);
219 	do {
220 		/* If waiting for reply in rdma_init()/rdma_fini() threads, then
221 		 * check if there are any connection errors.
222 		 */
223 		if (so && so->so_error) {
224 			wr_waitp->ret = -ECONNRESET;
225 			CTR5(KTR_IW_CXGBE, "%s - Connection ERROR %u for sock %p"
226 			    "tid %u qpid %u", func,
227 			    so->so_error, so, hwtid, qpid);
228 			break;
229 		}
230 
231 		ret = wait_for_completion_timeout(&wr_waitp->completion, to);
232 		if (!ret) {
233 			getmicrotime(&t2);
234 			timevalsub(&t2, &t1);
235 			printf("%s - Device %s not responding after %ld.%06ld "
236 			    "seconds - tid %u qpid %u\n", func,
237 			    device_get_nameunit(sc->dev), t2.tv_sec, t2.tv_usec,
238 			    hwtid, qpid);
239 			if (c4iw_fatal_error(rdev)) {
240 				wr_waitp->ret = -EIO;
241 				break;
242 			}
243 			to = to << 2;
244 			timedout = 1;
245 		}
246 	} while (!ret);
247 
248 out:
249 	if (timedout) {
250 		getmicrotime(&t2);
251 		timevalsub(&t2, &t1);
252 		printf("%s - Device %s reply after %ld.%06ld seconds - "
253 		    "tid %u qpid %u\n", func, device_get_nameunit(sc->dev),
254 		    t2.tv_sec, t2.tv_usec, hwtid, qpid);
255 	}
256 	if (wr_waitp->ret)
257 		CTR4(KTR_IW_CXGBE, "%p: FW reply %d tid %u qpid %u", sc,
258 		    wr_waitp->ret, hwtid, qpid);
259 	return (wr_waitp->ret);
260 }
261 
262 struct c4iw_dev {
263 	struct ib_device ibdev;
264 	struct c4iw_rdev rdev;
265 	u32 device_cap_flags;
266 	struct idr cqidr;
267 	struct idr qpidr;
268 	struct idr mmidr;
269 	spinlock_t lock;
270 	struct dentry *debugfs_root;
271 	u32 avail_ird;
272 };
273 
274 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
275 {
276 	return container_of(ibdev, struct c4iw_dev, ibdev);
277 }
278 
279 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
280 {
281 	return container_of(rdev, struct c4iw_dev, rdev);
282 }
283 
284 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
285 {
286 	return idr_find(&rhp->cqidr, cqid);
287 }
288 
289 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
290 {
291 	return idr_find(&rhp->qpidr, qpid);
292 }
293 
294 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
295 {
296 	return idr_find(&rhp->mmidr, mmid);
297 }
298 
299 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
300 				 void *handle, u32 id, int lock)
301 {
302 	int ret;
303 	int newid;
304 
305 	do {
306 		if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
307 			return -ENOMEM;
308 		if (lock)
309 			spin_lock_irq(&rhp->lock);
310 		ret = idr_get_new_above(idr, handle, id, &newid);
311 		BUG_ON(!ret && newid != id);
312 		if (lock)
313 			spin_unlock_irq(&rhp->lock);
314 	} while (ret == -EAGAIN);
315 
316 	return ret;
317 }
318 
319 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
320 				void *handle, u32 id)
321 {
322 	return _insert_handle(rhp, idr, handle, id, 1);
323 }
324 
325 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
326 				       void *handle, u32 id)
327 {
328 	return _insert_handle(rhp, idr, handle, id, 0);
329 }
330 
331 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
332 				   u32 id, int lock)
333 {
334 	if (lock)
335 		spin_lock_irq(&rhp->lock);
336 	idr_remove(idr, id);
337 	if (lock)
338 		spin_unlock_irq(&rhp->lock);
339 }
340 
341 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
342 {
343 	_remove_handle(rhp, idr, id, 1);
344 }
345 
346 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
347 					 struct idr *idr, u32 id)
348 {
349 	_remove_handle(rhp, idr, id, 0);
350 }
351 
352 extern int c4iw_max_read_depth;
353 
354 static inline int cur_max_read_depth(struct c4iw_dev *dev)
355 {
356 	return min(dev->rdev.adap->params.max_ordird_qp, c4iw_max_read_depth);
357 }
358 
359 struct c4iw_pd {
360 	struct ib_pd ibpd;
361 	u32 pdid;
362 	struct c4iw_dev *rhp;
363 };
364 
365 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
366 {
367 	return container_of(ibpd, struct c4iw_pd, ibpd);
368 }
369 
370 struct tpt_attributes {
371 	u64 len;
372 	u64 va_fbo;
373 	enum fw_ri_mem_perms perms;
374 	u32 stag;
375 	u32 pdid;
376 	u32 qpid;
377 	u32 pbl_addr;
378 	u32 pbl_size;
379 	u32 state:1;
380 	u32 type:2;
381 	u32 rsvd:1;
382 	u32 remote_invaliate_disable:1;
383 	u32 zbva:1;
384 	u32 mw_bind_enable:1;
385 	u32 page_size:5;
386 };
387 
388 struct c4iw_mr {
389 	struct ib_mr ibmr;
390 	struct ib_umem *umem;
391 	struct c4iw_dev *rhp;
392 	u64 kva;
393 	struct tpt_attributes attr;
394 	u64 *mpl;
395 	dma_addr_t mpl_addr;
396 	u32 max_mpl_len;
397 	u32 mpl_len;
398 };
399 
400 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
401 {
402 	return container_of(ibmr, struct c4iw_mr, ibmr);
403 }
404 
405 struct c4iw_mw {
406 	struct ib_mw ibmw;
407 	struct c4iw_dev *rhp;
408 	u64 kva;
409 	struct tpt_attributes attr;
410 };
411 
412 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
413 {
414 	return container_of(ibmw, struct c4iw_mw, ibmw);
415 }
416 
417 struct c4iw_cq {
418 	struct ib_cq ibcq;
419 	struct c4iw_dev *rhp;
420 	struct t4_cq cq;
421 	spinlock_t lock;
422 	spinlock_t comp_handler_lock;
423 	atomic_t refcnt;
424 	wait_queue_head_t wait;
425 };
426 
427 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
428 {
429 	return container_of(ibcq, struct c4iw_cq, ibcq);
430 }
431 
432 struct c4iw_mpa_attributes {
433 	u8 initiator;
434 	u8 recv_marker_enabled;
435 	u8 xmit_marker_enabled;
436 	u8 crc_enabled;
437 	u8 enhanced_rdma_conn;
438 	u8 version;
439 	u8 p2p_type;
440 };
441 
442 struct c4iw_qp_attributes {
443 	u32 scq;
444 	u32 rcq;
445 	u32 sq_num_entries;
446 	u32 rq_num_entries;
447 	u32 sq_max_sges;
448 	u32 sq_max_sges_rdma_write;
449 	u32 rq_max_sges;
450 	u32 state;
451 	u8 enable_rdma_read;
452 	u8 enable_rdma_write;
453 	u8 enable_bind;
454 	u8 enable_mmid0_fastreg;
455 	u32 max_ord;
456 	u32 max_ird;
457 	u32 pd;
458 	u32 next_state;
459 	char terminate_buffer[52];
460 	u32 terminate_msg_len;
461 	u8 is_terminate_local;
462 	struct c4iw_mpa_attributes mpa_attr;
463 	struct c4iw_ep *llp_stream_handle;
464 	u8 layer_etype;
465 	u8 ecode;
466 	u16 sq_db_inc;
467 	u16 rq_db_inc;
468 	u8 send_term;
469 };
470 
471 struct c4iw_qp {
472 	struct ib_qp ibqp;
473 	struct c4iw_dev *rhp;
474 	struct c4iw_ep *ep;
475 	struct c4iw_qp_attributes attr;
476 	struct t4_wq wq;
477 	spinlock_t lock;
478 	struct mutex mutex;
479 	struct kref kref;
480 	wait_queue_head_t wait;
481 	struct timer_list timer;
482 	int sq_sig_all;
483 	struct work_struct free_work;
484 	struct c4iw_ucontext *ucontext;
485 };
486 
487 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
488 {
489 	return container_of(ibqp, struct c4iw_qp, ibqp);
490 }
491 
492 struct c4iw_ucontext {
493 	struct ib_ucontext ibucontext;
494 	struct c4iw_dev_ucontext uctx;
495 	u32 key;
496 	spinlock_t mmap_lock;
497 	struct list_head mmaps;
498 	struct kref kref;
499 };
500 
501 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
502 {
503 	return container_of(c, struct c4iw_ucontext, ibucontext);
504 }
505 
506 void _c4iw_free_ucontext(struct kref *kref);
507 
508 static inline void c4iw_put_ucontext(struct c4iw_ucontext *ucontext)
509 {
510 	kref_put(&ucontext->kref, _c4iw_free_ucontext);
511 }
512 static inline void c4iw_get_ucontext(struct c4iw_ucontext *ucontext)
513 {
514 	kref_get(&ucontext->kref);
515 }
516 
517 struct c4iw_mm_entry {
518 	struct list_head entry;
519 	u64 addr;
520 	u32 key;
521 	unsigned len;
522 };
523 
524 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
525 						u32 key, unsigned len)
526 {
527 	struct list_head *pos, *nxt;
528 	struct c4iw_mm_entry *mm;
529 
530 	spin_lock(&ucontext->mmap_lock);
531 	list_for_each_safe(pos, nxt, &ucontext->mmaps) {
532 
533 		mm = list_entry(pos, struct c4iw_mm_entry, entry);
534 		if (mm->key == key && mm->len == len) {
535 			list_del_init(&mm->entry);
536 			spin_unlock(&ucontext->mmap_lock);
537 			CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
538 			     __func__, key, (unsigned long long) mm->addr,
539 			     mm->len);
540 			return mm;
541 		}
542 	}
543 	spin_unlock(&ucontext->mmap_lock);
544 	return NULL;
545 }
546 
547 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
548 			       struct c4iw_mm_entry *mm)
549 {
550 	spin_lock(&ucontext->mmap_lock);
551 	CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
552 	    (unsigned long long) mm->addr, mm->len);
553 	list_add_tail(&mm->entry, &ucontext->mmaps);
554 	spin_unlock(&ucontext->mmap_lock);
555 }
556 
557 enum c4iw_qp_attr_mask {
558 	C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
559 	C4IW_QP_ATTR_SQ_DB = 1<<1,
560 	C4IW_QP_ATTR_RQ_DB = 1<<2,
561 	C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
562 	C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
563 	C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
564 	C4IW_QP_ATTR_MAX_ORD = 1 << 11,
565 	C4IW_QP_ATTR_MAX_IRD = 1 << 12,
566 	C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
567 	C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
568 	C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
569 	C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
570 	C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
571 				     C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
572 				     C4IW_QP_ATTR_MAX_ORD |
573 				     C4IW_QP_ATTR_MAX_IRD |
574 				     C4IW_QP_ATTR_LLP_STREAM_HANDLE |
575 				     C4IW_QP_ATTR_STREAM_MSG_BUFFER |
576 				     C4IW_QP_ATTR_MPA_ATTR |
577 				     C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
578 };
579 
580 int c4iw_modify_qp(struct c4iw_dev *rhp,
581 				struct c4iw_qp *qhp,
582 				enum c4iw_qp_attr_mask mask,
583 				struct c4iw_qp_attributes *attrs,
584 				int internal);
585 
586 enum c4iw_qp_state {
587 	C4IW_QP_STATE_IDLE,
588 	C4IW_QP_STATE_RTS,
589 	C4IW_QP_STATE_ERROR,
590 	C4IW_QP_STATE_TERMINATE,
591 	C4IW_QP_STATE_CLOSING,
592 	C4IW_QP_STATE_TOT
593 };
594 
595 /*
596  * IW_CXGBE event bits.
597  * These bits are used for handling all events for a particular 'ep' serially.
598  */
599 #define	C4IW_EVENT_SOCKET	0x0001
600 #define	C4IW_EVENT_TIMEOUT	0x0002
601 #define	C4IW_EVENT_TERM		0x0004
602 
603 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
604 {
605 	switch (ib_state) {
606 	case IB_QPS_RESET:
607 	case IB_QPS_INIT:
608 		return C4IW_QP_STATE_IDLE;
609 	case IB_QPS_RTS:
610 		return C4IW_QP_STATE_RTS;
611 	case IB_QPS_SQD:
612 		return C4IW_QP_STATE_CLOSING;
613 	case IB_QPS_SQE:
614 		return C4IW_QP_STATE_TERMINATE;
615 	case IB_QPS_ERR:
616 		return C4IW_QP_STATE_ERROR;
617 	default:
618 		return -1;
619 	}
620 }
621 
622 static inline int to_ib_qp_state(int c4iw_qp_state)
623 {
624 	switch (c4iw_qp_state) {
625 	case C4IW_QP_STATE_IDLE:
626 		return IB_QPS_INIT;
627 	case C4IW_QP_STATE_RTS:
628 		return IB_QPS_RTS;
629 	case C4IW_QP_STATE_CLOSING:
630 		return IB_QPS_SQD;
631 	case C4IW_QP_STATE_TERMINATE:
632 		return IB_QPS_SQE;
633 	case C4IW_QP_STATE_ERROR:
634 		return IB_QPS_ERR;
635 	}
636 	return IB_QPS_ERR;
637 }
638 
639 #define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
640 
641 static inline u32 c4iw_ib_to_tpt_access(int a)
642 {
643 	return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
644 	       (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
645 	       (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
646 	       FW_RI_MEM_ACCESS_LOCAL_READ;
647 }
648 
649 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
650 {
651 	return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
652 	       (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
653 }
654 
655 enum c4iw_mmid_state {
656 	C4IW_STAG_STATE_VALID,
657 	C4IW_STAG_STATE_INVALID
658 };
659 
660 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
661 
662 #define MPA_KEY_REQ "MPA ID Req Frame"
663 #define MPA_KEY_REP "MPA ID Rep Frame"
664 
665 #define MPA_MAX_PRIVATE_DATA	256
666 #define MPA_ENHANCED_RDMA_CONN	0x10
667 #define MPA_REJECT		0x20
668 #define MPA_CRC			0x40
669 #define MPA_MARKERS		0x80
670 #define MPA_FLAGS_MASK		0xE0
671 
672 #define MPA_V2_PEER2PEER_MODEL          0x8000
673 #define MPA_V2_ZERO_LEN_FPDU_RTR        0x4000
674 #define MPA_V2_RDMA_WRITE_RTR           0x8000
675 #define MPA_V2_RDMA_READ_RTR            0x4000
676 #define MPA_V2_IRD_ORD_MASK             0x3FFF
677 
678 #define c4iw_put_ep(ep) { \
679 	CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
680 	     __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
681 	WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \
682         kref_put(&((ep)->kref), _c4iw_free_ep); \
683 }
684 
685 #define c4iw_get_ep(ep) { \
686 	CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
687 	      __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
688         kref_get(&((ep)->kref));  \
689 }
690 
691 void _c4iw_free_ep(struct kref *kref);
692 
693 struct mpa_message {
694 	u8 key[16];
695 	u8 flags;
696 	u8 revision;
697 	__be16 private_data_size;
698 	u8 private_data[0];
699 };
700 
701 struct mpa_v2_conn_params {
702 	__be16 ird;
703 	__be16 ord;
704 };
705 
706 struct terminate_message {
707 	u8 layer_etype;
708 	u8 ecode;
709 	__be16 hdrct_rsvd;
710 	u8 len_hdrs[0];
711 };
712 
713 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
714 
715 enum c4iw_layers_types {
716 	LAYER_RDMAP		= 0x00,
717 	LAYER_DDP		= 0x10,
718 	LAYER_MPA		= 0x20,
719 	RDMAP_LOCAL_CATA	= 0x00,
720 	RDMAP_REMOTE_PROT	= 0x01,
721 	RDMAP_REMOTE_OP		= 0x02,
722 	DDP_LOCAL_CATA		= 0x00,
723 	DDP_TAGGED_ERR		= 0x01,
724 	DDP_UNTAGGED_ERR	= 0x02,
725 	DDP_LLP			= 0x03
726 };
727 
728 enum c4iw_rdma_ecodes {
729 	RDMAP_INV_STAG		= 0x00,
730 	RDMAP_BASE_BOUNDS	= 0x01,
731 	RDMAP_ACC_VIOL		= 0x02,
732 	RDMAP_STAG_NOT_ASSOC	= 0x03,
733 	RDMAP_TO_WRAP		= 0x04,
734 	RDMAP_INV_VERS		= 0x05,
735 	RDMAP_INV_OPCODE	= 0x06,
736 	RDMAP_STREAM_CATA	= 0x07,
737 	RDMAP_GLOBAL_CATA	= 0x08,
738 	RDMAP_CANT_INV_STAG	= 0x09,
739 	RDMAP_UNSPECIFIED	= 0xff
740 };
741 
742 enum c4iw_ddp_ecodes {
743 	DDPT_INV_STAG		= 0x00,
744 	DDPT_BASE_BOUNDS	= 0x01,
745 	DDPT_STAG_NOT_ASSOC	= 0x02,
746 	DDPT_TO_WRAP		= 0x03,
747 	DDPT_INV_VERS		= 0x04,
748 	DDPU_INV_QN		= 0x01,
749 	DDPU_INV_MSN_NOBUF	= 0x02,
750 	DDPU_INV_MSN_RANGE	= 0x03,
751 	DDPU_INV_MO		= 0x04,
752 	DDPU_MSG_TOOBIG		= 0x05,
753 	DDPU_INV_VERS		= 0x06
754 };
755 
756 enum c4iw_mpa_ecodes {
757 	MPA_CRC_ERR		= 0x02,
758 	MPA_MARKER_ERR		= 0x03,
759 	MPA_LOCAL_CATA          = 0x05,
760 	MPA_INSUFF_IRD          = 0x06,
761 	MPA_NOMATCH_RTR         = 0x07,
762 };
763 
764 enum c4iw_ep_state {
765 	IDLE = 0,
766 	LISTEN,
767 	CONNECTING,
768 	MPA_REQ_WAIT,
769 	MPA_REQ_SENT,
770 	MPA_REQ_RCVD,
771 	MPA_REP_SENT,
772 	FPDU_MODE,
773 	ABORTING,
774 	CLOSING,
775 	MORIBUND,
776 	DEAD,
777 };
778 
779 enum c4iw_ep_flags {
780 	PEER_ABORT_IN_PROGRESS	= 0,
781 	ABORT_REQ_IN_PROGRESS	= 1,
782 	RELEASE_RESOURCES	= 2,
783 	CLOSE_SENT		= 3,
784 	TIMEOUT                 = 4,
785 	QP_REFERENCED		= 5,
786 	STOP_MPA_TIMER		= 7,
787 };
788 
789 enum c4iw_ep_history {
790         ACT_OPEN_REQ            = 0,
791         ACT_OFLD_CONN           = 1,
792         ACT_OPEN_RPL            = 2,
793         ACT_ESTAB               = 3,
794         PASS_ACCEPT_REQ         = 4,
795         PASS_ESTAB              = 5,
796         ABORT_UPCALL            = 6,
797         ESTAB_UPCALL            = 7,
798         CLOSE_UPCALL            = 8,
799         ULP_ACCEPT              = 9,
800         ULP_REJECT              = 10,
801         TIMEDOUT                = 11,
802         PEER_ABORT              = 12,
803         PEER_CLOSE              = 13,
804         CONNREQ_UPCALL          = 14,
805         ABORT_CONN              = 15,
806         DISCONN_UPCALL          = 16,
807         EP_DISC_CLOSE           = 17,
808         EP_DISC_ABORT           = 18,
809         CONN_RPL_UPCALL         = 19,
810         ACT_RETRY_NOMEM         = 20,
811         ACT_RETRY_INUSE         = 21,
812         CLOSE_CON_RPL           = 22,
813         EP_DISC_FAIL            = 24,
814         QP_REFED                = 25,
815         QP_DEREFED              = 26,
816         CM_ID_REFED             = 27,
817         CM_ID_DEREFED           = 28
818 };
819 
820 struct c4iw_ep_common {
821 	TAILQ_ENTRY(c4iw_ep_common) entry;	/* Work queue attachment */
822 	struct iw_cm_id *cm_id;
823 	struct c4iw_qp *qp;
824 	struct c4iw_dev *dev;
825 	enum c4iw_ep_state state;
826 	struct kref kref;
827 	struct mutex mutex;
828 	struct sockaddr_storage local_addr;
829 	struct sockaddr_storage remote_addr;
830 	struct c4iw_wr_wait wr_wait;
831 	unsigned long flags;
832 	unsigned long history;
833         int rpl_err;
834         int rpl_done;
835         struct thread *thread;
836         struct socket *so;
837 	int ep_events;
838 };
839 
840 struct c4iw_listen_ep {
841 	struct c4iw_ep_common com;
842 	unsigned int stid;
843 	int backlog;
844 	struct list_head listen_ep_list;  /* list of all listener ep's bound
845 					     to one port address */
846 };
847 
848 struct c4iw_ep {
849 	struct c4iw_ep_common com;
850 	struct c4iw_listen_ep *parent_ep;
851 	struct timer_list timer;
852 	unsigned int atid;
853 	u32 hwtid;
854 	u32 snd_seq;
855 	u32 rcv_seq;
856 	struct l2t_entry *l2t;
857 	struct dst_entry *dst;
858 	struct c4iw_mpa_attributes mpa_attr;
859 	u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
860 	unsigned int mpa_pkt_len;
861 	u32 ird;
862 	u32 ord;
863 	u32 tx_chan;
864 	u32 mtu;
865 	u16 mss;
866 	u16 plen;
867 	u16 rss_qid;
868 	u16 txq_idx;
869 	u16 ctrlq_idx;
870 	u8 tos;
871 	u8 retry_with_mpa_v1;
872 	u8 tried_with_mpa_v1;
873 };
874 
875 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
876 {
877 	return cm_id->provider_data;
878 }
879 
880 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
881 {
882 	return cm_id->provider_data;
883 }
884 
885 static inline int compute_wscale(int win)
886 {
887 	int wscale = 0;
888 
889 	while (wscale < 14 && (65535<<wscale) < win)
890 		wscale++;
891 	return wscale;
892 }
893 
894 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
895 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
896 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
897 			u32 reserved, u32 flags);
898 void c4iw_id_table_free(struct c4iw_id_table *alloc);
899 
900 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
901 
902 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
903 		     struct l2t_entry *l2t);
904 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
905 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
906 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
907 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
908 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
909 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
910 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
911 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
912 void c4iw_destroy_resource(struct c4iw_resource *rscp);
913 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
914 int c4iw_register_device(struct c4iw_dev *dev);
915 void c4iw_unregister_device(struct c4iw_dev *dev);
916 int __init c4iw_cm_init(void);
917 void __exit c4iw_cm_term(void);
918 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
919 			       struct c4iw_dev_ucontext *uctx);
920 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
921 			    struct c4iw_dev_ucontext *uctx);
922 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
923 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
924 		      struct ib_send_wr **bad_wr);
925 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
926 		      struct ib_recv_wr **bad_wr);
927 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
928 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
929 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
930 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
931 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
932 void c4iw_qp_add_ref(struct ib_qp *qp);
933 void c4iw_qp_rem_ref(struct ib_qp *qp);
934 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
935 			u32 max_num_sg);
936 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
937 		int sg_nents, unsigned int *sg_offset);
938 int c4iw_dealloc_mw(struct ib_mw *mw);
939 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
940 		struct ib_udata *udata);
941 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
942 		virt, int acc, struct ib_udata *udata);
943 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
944 int c4iw_dereg_mr(struct ib_mr *ib_mr);
945 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
946 int c4iw_destroy_cq(struct ib_cq *ib_cq);
947 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
948 				const struct ib_cq_init_attr *attr,
949 				struct ib_ucontext *ib_context,
950 				struct ib_udata *udata);
951 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
952 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
953 int c4iw_destroy_qp(struct ib_qp *ib_qp);
954 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
955 			     struct ib_qp_init_attr *attrs,
956 			     struct ib_udata *udata);
957 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
958 				 int attr_mask, struct ib_udata *udata);
959 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
960 		     int attr_mask, struct ib_qp_init_attr *init_attr);
961 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
962 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
963 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
964 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
965 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
966 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
967 void c4iw_flush_hw_cq(struct c4iw_cq *cq);
968 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
969 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
970 int __c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
971 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
972 int c4iw_flush_sq(struct c4iw_qp *qhp);
973 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
974 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
975 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
976 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
977 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
978 		struct c4iw_dev_ucontext *uctx);
979 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
980 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
981 		struct c4iw_dev_ucontext *uctx);
982 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
983 #endif
984