1 /* 2 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 * 31 * $FreeBSD$ 32 */ 33 #ifndef __IW_CXGB4_H__ 34 #define __IW_CXGB4_H__ 35 36 #include <linux/list.h> 37 #include <linux/spinlock.h> 38 #include <linux/idr.h> 39 #include <linux/completion.h> 40 #include <linux/netdevice.h> 41 #include <linux/sched.h> 42 #include <linux/pci.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/wait.h> 45 #include <linux/kref.h> 46 #include <linux/timer.h> 47 #include <linux/io.h> 48 49 #include <asm/byteorder.h> 50 51 #include <netinet/in.h> 52 #include <netinet/toecore.h> 53 54 #include <rdma/ib_verbs.h> 55 #include <rdma/iw_cm.h> 56 57 #undef prefetch 58 59 #include "common/common.h" 60 #include "common/t4_msg.h" 61 #include "common/t4_regs.h" 62 #include "common/t4_tcb.h" 63 #include "t4_l2t.h" 64 65 #define DRV_NAME "iw_cxgbe" 66 #define MOD DRV_NAME ":" 67 #define KTR_IW_CXGBE KTR_SPARE3 68 69 extern int c4iw_debug; 70 #define PDBG(fmt, args...) \ 71 do { \ 72 if (c4iw_debug) \ 73 printf(MOD fmt, ## args); \ 74 } while (0) 75 76 #include "t4.h" 77 78 static inline void *cplhdr(struct mbuf *m) 79 { 80 return mtod(m, void*); 81 } 82 83 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start) 84 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start) 85 86 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */ 87 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */ 88 89 struct c4iw_id_table { 90 u32 flags; 91 u32 start; /* logical minimal id */ 92 u32 last; /* hint for find */ 93 u32 max; 94 spinlock_t lock; 95 unsigned long *table; 96 }; 97 98 struct c4iw_resource { 99 struct c4iw_id_table tpt_table; 100 struct c4iw_id_table qid_table; 101 struct c4iw_id_table pdid_table; 102 }; 103 104 struct c4iw_qid_list { 105 struct list_head entry; 106 u32 qid; 107 }; 108 109 struct c4iw_dev_ucontext { 110 struct list_head qpids; 111 struct list_head cqids; 112 struct mutex lock; 113 }; 114 115 enum c4iw_rdev_flags { 116 T4_FATAL_ERROR = (1<<0), 117 }; 118 119 struct c4iw_stat { 120 u64 total; 121 u64 cur; 122 u64 max; 123 u64 fail; 124 }; 125 126 struct c4iw_stats { 127 struct mutex lock; 128 struct c4iw_stat qid; 129 struct c4iw_stat pd; 130 struct c4iw_stat stag; 131 struct c4iw_stat pbl; 132 struct c4iw_stat rqt; 133 u64 db_full; 134 u64 db_empty; 135 u64 db_drop; 136 u64 db_state_transitions; 137 }; 138 139 struct c4iw_rdev { 140 struct adapter *adap; 141 struct c4iw_resource resource; 142 unsigned long qpshift; 143 u32 qpmask; 144 unsigned long cqshift; 145 u32 cqmask; 146 struct c4iw_dev_ucontext uctx; 147 struct gen_pool *pbl_pool; 148 struct gen_pool *rqt_pool; 149 u32 flags; 150 struct c4iw_stats stats; 151 }; 152 153 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev) 154 { 155 return rdev->flags & T4_FATAL_ERROR; 156 } 157 158 static inline int c4iw_num_stags(struct c4iw_rdev *rdev) 159 { 160 return min((int)T4_MAX_NUM_STAG, (int)(rdev->adap->vres.stag.size >> 5)); 161 } 162 163 #define C4IW_WR_TO (10*HZ) 164 165 struct c4iw_wr_wait { 166 int ret; 167 atomic_t completion; 168 }; 169 170 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) 171 { 172 wr_waitp->ret = 0; 173 atomic_set(&wr_waitp->completion, 0); 174 } 175 176 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret) 177 { 178 wr_waitp->ret = ret; 179 atomic_set(&wr_waitp->completion, 1); 180 wakeup(wr_waitp); 181 } 182 183 static inline int 184 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp, 185 u32 hwtid, u32 qpid, const char *func) 186 { 187 struct adapter *sc = rdev->adap; 188 unsigned to = C4IW_WR_TO; 189 190 while (!atomic_read(&wr_waitp->completion)) { 191 tsleep(wr_waitp, 0, "c4iw_wait", to); 192 if (SIGPENDING(curthread)) { 193 printf("%s - Device %s not responding - " 194 "tid %u qpid %u\n", func, 195 device_get_nameunit(sc->dev), hwtid, qpid); 196 if (c4iw_fatal_error(rdev)) { 197 wr_waitp->ret = -EIO; 198 break; 199 } 200 to = to << 2; 201 } 202 } 203 if (wr_waitp->ret) 204 CTR4(KTR_IW_CXGBE, "%s: FW reply %d tid %u qpid %u", 205 device_get_nameunit(sc->dev), wr_waitp->ret, hwtid, qpid); 206 return (wr_waitp->ret); 207 } 208 209 enum db_state { 210 NORMAL = 0, 211 FLOW_CONTROL = 1, 212 RECOVERY = 2 213 }; 214 215 struct c4iw_dev { 216 struct ib_device ibdev; 217 struct c4iw_rdev rdev; 218 u32 device_cap_flags; 219 struct idr cqidr; 220 struct idr qpidr; 221 struct idr mmidr; 222 spinlock_t lock; 223 struct dentry *debugfs_root; 224 enum db_state db_state; 225 int qpcnt; 226 }; 227 228 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) 229 { 230 return container_of(ibdev, struct c4iw_dev, ibdev); 231 } 232 233 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev) 234 { 235 return container_of(rdev, struct c4iw_dev, rdev); 236 } 237 238 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid) 239 { 240 return idr_find(&rhp->cqidr, cqid); 241 } 242 243 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid) 244 { 245 return idr_find(&rhp->qpidr, qpid); 246 } 247 248 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid) 249 { 250 return idr_find(&rhp->mmidr, mmid); 251 } 252 253 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr, 254 void *handle, u32 id, int lock) 255 { 256 int ret; 257 int newid; 258 259 do { 260 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC)) 261 return -ENOMEM; 262 if (lock) 263 spin_lock_irq(&rhp->lock); 264 ret = idr_get_new_above(idr, handle, id, &newid); 265 BUG_ON(!ret && newid != id); 266 if (lock) 267 spin_unlock_irq(&rhp->lock); 268 } while (ret == -EAGAIN); 269 270 return ret; 271 } 272 273 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr, 274 void *handle, u32 id) 275 { 276 return _insert_handle(rhp, idr, handle, id, 1); 277 } 278 279 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr, 280 void *handle, u32 id) 281 { 282 return _insert_handle(rhp, idr, handle, id, 0); 283 } 284 285 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr, 286 u32 id, int lock) 287 { 288 if (lock) 289 spin_lock_irq(&rhp->lock); 290 idr_remove(idr, id); 291 if (lock) 292 spin_unlock_irq(&rhp->lock); 293 } 294 295 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id) 296 { 297 _remove_handle(rhp, idr, id, 1); 298 } 299 300 static inline void remove_handle_nolock(struct c4iw_dev *rhp, 301 struct idr *idr, u32 id) 302 { 303 _remove_handle(rhp, idr, id, 0); 304 } 305 306 struct c4iw_pd { 307 struct ib_pd ibpd; 308 u32 pdid; 309 struct c4iw_dev *rhp; 310 }; 311 312 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd) 313 { 314 return container_of(ibpd, struct c4iw_pd, ibpd); 315 } 316 317 struct tpt_attributes { 318 u64 len; 319 u64 va_fbo; 320 enum fw_ri_mem_perms perms; 321 u32 stag; 322 u32 pdid; 323 u32 qpid; 324 u32 pbl_addr; 325 u32 pbl_size; 326 u32 state:1; 327 u32 type:2; 328 u32 rsvd:1; 329 u32 remote_invaliate_disable:1; 330 u32 zbva:1; 331 u32 mw_bind_enable:1; 332 u32 page_size:5; 333 }; 334 335 struct c4iw_mr { 336 struct ib_mr ibmr; 337 struct ib_umem *umem; 338 struct c4iw_dev *rhp; 339 u64 kva; 340 struct tpt_attributes attr; 341 }; 342 343 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) 344 { 345 return container_of(ibmr, struct c4iw_mr, ibmr); 346 } 347 348 struct c4iw_mw { 349 struct ib_mw ibmw; 350 struct c4iw_dev *rhp; 351 u64 kva; 352 struct tpt_attributes attr; 353 }; 354 355 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) 356 { 357 return container_of(ibmw, struct c4iw_mw, ibmw); 358 } 359 360 struct c4iw_fr_page_list { 361 struct ib_fast_reg_page_list ibpl; 362 DECLARE_PCI_UNMAP_ADDR(mapping); 363 dma_addr_t dma_addr; 364 struct c4iw_dev *dev; 365 int size; 366 }; 367 368 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list( 369 struct ib_fast_reg_page_list *ibpl) 370 { 371 return container_of(ibpl, struct c4iw_fr_page_list, ibpl); 372 } 373 374 struct c4iw_cq { 375 struct ib_cq ibcq; 376 struct c4iw_dev *rhp; 377 struct t4_cq cq; 378 spinlock_t lock; 379 spinlock_t comp_handler_lock; 380 atomic_t refcnt; 381 wait_queue_head_t wait; 382 }; 383 384 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) 385 { 386 return container_of(ibcq, struct c4iw_cq, ibcq); 387 } 388 389 struct c4iw_mpa_attributes { 390 u8 initiator; 391 u8 recv_marker_enabled; 392 u8 xmit_marker_enabled; 393 u8 crc_enabled; 394 u8 enhanced_rdma_conn; 395 u8 version; 396 u8 p2p_type; 397 }; 398 399 struct c4iw_qp_attributes { 400 u32 scq; 401 u32 rcq; 402 u32 sq_num_entries; 403 u32 rq_num_entries; 404 u32 sq_max_sges; 405 u32 sq_max_sges_rdma_write; 406 u32 rq_max_sges; 407 u32 state; 408 u8 enable_rdma_read; 409 u8 enable_rdma_write; 410 u8 enable_bind; 411 u8 enable_mmid0_fastreg; 412 u32 max_ord; 413 u32 max_ird; 414 u32 pd; 415 u32 next_state; 416 char terminate_buffer[52]; 417 u32 terminate_msg_len; 418 u8 is_terminate_local; 419 struct c4iw_mpa_attributes mpa_attr; 420 struct c4iw_ep *llp_stream_handle; 421 u8 layer_etype; 422 u8 ecode; 423 u16 sq_db_inc; 424 u16 rq_db_inc; 425 }; 426 427 struct c4iw_qp { 428 struct ib_qp ibqp; 429 struct c4iw_dev *rhp; 430 struct c4iw_ep *ep; 431 struct c4iw_qp_attributes attr; 432 struct t4_wq wq; 433 spinlock_t lock; 434 struct mutex mutex; 435 atomic_t refcnt; 436 wait_queue_head_t wait; 437 struct timer_list timer; 438 }; 439 440 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) 441 { 442 return container_of(ibqp, struct c4iw_qp, ibqp); 443 } 444 445 struct c4iw_ucontext { 446 struct ib_ucontext ibucontext; 447 struct c4iw_dev_ucontext uctx; 448 u32 key; 449 spinlock_t mmap_lock; 450 struct list_head mmaps; 451 }; 452 453 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c) 454 { 455 return container_of(c, struct c4iw_ucontext, ibucontext); 456 } 457 458 struct c4iw_mm_entry { 459 struct list_head entry; 460 u64 addr; 461 u32 key; 462 unsigned len; 463 }; 464 465 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext, 466 u32 key, unsigned len) 467 { 468 struct list_head *pos, *nxt; 469 struct c4iw_mm_entry *mm; 470 471 spin_lock(&ucontext->mmap_lock); 472 list_for_each_safe(pos, nxt, &ucontext->mmaps) { 473 474 mm = list_entry(pos, struct c4iw_mm_entry, entry); 475 if (mm->key == key && mm->len == len) { 476 list_del_init(&mm->entry); 477 spin_unlock(&ucontext->mmap_lock); 478 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", 479 __func__, key, (unsigned long long) mm->addr, 480 mm->len); 481 return mm; 482 } 483 } 484 spin_unlock(&ucontext->mmap_lock); 485 return NULL; 486 } 487 488 static inline void insert_mmap(struct c4iw_ucontext *ucontext, 489 struct c4iw_mm_entry *mm) 490 { 491 spin_lock(&ucontext->mmap_lock); 492 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key, 493 (unsigned long long) mm->addr, mm->len); 494 list_add_tail(&mm->entry, &ucontext->mmaps); 495 spin_unlock(&ucontext->mmap_lock); 496 } 497 498 enum c4iw_qp_attr_mask { 499 C4IW_QP_ATTR_NEXT_STATE = 1 << 0, 500 C4IW_QP_ATTR_SQ_DB = 1<<1, 501 C4IW_QP_ATTR_RQ_DB = 1<<2, 502 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7, 503 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8, 504 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9, 505 C4IW_QP_ATTR_MAX_ORD = 1 << 11, 506 C4IW_QP_ATTR_MAX_IRD = 1 << 12, 507 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22, 508 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23, 509 C4IW_QP_ATTR_MPA_ATTR = 1 << 24, 510 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25, 511 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ | 512 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 513 C4IW_QP_ATTR_MAX_ORD | 514 C4IW_QP_ATTR_MAX_IRD | 515 C4IW_QP_ATTR_LLP_STREAM_HANDLE | 516 C4IW_QP_ATTR_STREAM_MSG_BUFFER | 517 C4IW_QP_ATTR_MPA_ATTR | 518 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE) 519 }; 520 521 int c4iw_modify_qp(struct c4iw_dev *rhp, 522 struct c4iw_qp *qhp, 523 enum c4iw_qp_attr_mask mask, 524 struct c4iw_qp_attributes *attrs, 525 int internal); 526 527 enum c4iw_qp_state { 528 C4IW_QP_STATE_IDLE, 529 C4IW_QP_STATE_RTS, 530 C4IW_QP_STATE_ERROR, 531 C4IW_QP_STATE_TERMINATE, 532 C4IW_QP_STATE_CLOSING, 533 C4IW_QP_STATE_TOT 534 }; 535 536 static inline int c4iw_convert_state(enum ib_qp_state ib_state) 537 { 538 switch (ib_state) { 539 case IB_QPS_RESET: 540 case IB_QPS_INIT: 541 return C4IW_QP_STATE_IDLE; 542 case IB_QPS_RTS: 543 return C4IW_QP_STATE_RTS; 544 case IB_QPS_SQD: 545 return C4IW_QP_STATE_CLOSING; 546 case IB_QPS_SQE: 547 return C4IW_QP_STATE_TERMINATE; 548 case IB_QPS_ERR: 549 return C4IW_QP_STATE_ERROR; 550 default: 551 return -1; 552 } 553 } 554 555 static inline int to_ib_qp_state(int c4iw_qp_state) 556 { 557 switch (c4iw_qp_state) { 558 case C4IW_QP_STATE_IDLE: 559 return IB_QPS_INIT; 560 case C4IW_QP_STATE_RTS: 561 return IB_QPS_RTS; 562 case C4IW_QP_STATE_CLOSING: 563 return IB_QPS_SQD; 564 case C4IW_QP_STATE_TERMINATE: 565 return IB_QPS_SQE; 566 case C4IW_QP_STATE_ERROR: 567 return IB_QPS_ERR; 568 } 569 return IB_QPS_ERR; 570 } 571 572 static inline u32 c4iw_ib_to_tpt_access(int a) 573 { 574 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 575 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) | 576 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) | 577 FW_RI_MEM_ACCESS_LOCAL_READ; 578 } 579 580 static inline u32 c4iw_ib_to_tpt_bind_access(int acc) 581 { 582 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 583 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0); 584 } 585 586 enum c4iw_mmid_state { 587 C4IW_STAG_STATE_VALID, 588 C4IW_STAG_STATE_INVALID 589 }; 590 591 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications" 592 593 #define MPA_KEY_REQ "MPA ID Req Frame" 594 #define MPA_KEY_REP "MPA ID Rep Frame" 595 596 #define MPA_MAX_PRIVATE_DATA 256 597 #define MPA_ENHANCED_RDMA_CONN 0x10 598 #define MPA_REJECT 0x20 599 #define MPA_CRC 0x40 600 #define MPA_MARKERS 0x80 601 #define MPA_FLAGS_MASK 0xE0 602 603 #define MPA_V2_PEER2PEER_MODEL 0x8000 604 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000 605 #define MPA_V2_RDMA_WRITE_RTR 0x8000 606 #define MPA_V2_RDMA_READ_RTR 0x4000 607 #define MPA_V2_IRD_ORD_MASK 0x3FFF 608 609 #define c4iw_put_ep(ep) { \ 610 CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \ 611 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \ 612 WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \ 613 kref_put(&((ep)->kref), _c4iw_free_ep); \ 614 } 615 616 #define c4iw_get_ep(ep) { \ 617 CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \ 618 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \ 619 kref_get(&((ep)->kref)); \ 620 } 621 622 void _c4iw_free_ep(struct kref *kref); 623 624 struct mpa_message { 625 u8 key[16]; 626 u8 flags; 627 u8 revision; 628 __be16 private_data_size; 629 u8 private_data[0]; 630 }; 631 632 struct mpa_v2_conn_params { 633 __be16 ird; 634 __be16 ord; 635 }; 636 637 struct terminate_message { 638 u8 layer_etype; 639 u8 ecode; 640 __be16 hdrct_rsvd; 641 u8 len_hdrs[0]; 642 }; 643 644 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28) 645 646 enum c4iw_layers_types { 647 LAYER_RDMAP = 0x00, 648 LAYER_DDP = 0x10, 649 LAYER_MPA = 0x20, 650 RDMAP_LOCAL_CATA = 0x00, 651 RDMAP_REMOTE_PROT = 0x01, 652 RDMAP_REMOTE_OP = 0x02, 653 DDP_LOCAL_CATA = 0x00, 654 DDP_TAGGED_ERR = 0x01, 655 DDP_UNTAGGED_ERR = 0x02, 656 DDP_LLP = 0x03 657 }; 658 659 enum c4iw_rdma_ecodes { 660 RDMAP_INV_STAG = 0x00, 661 RDMAP_BASE_BOUNDS = 0x01, 662 RDMAP_ACC_VIOL = 0x02, 663 RDMAP_STAG_NOT_ASSOC = 0x03, 664 RDMAP_TO_WRAP = 0x04, 665 RDMAP_INV_VERS = 0x05, 666 RDMAP_INV_OPCODE = 0x06, 667 RDMAP_STREAM_CATA = 0x07, 668 RDMAP_GLOBAL_CATA = 0x08, 669 RDMAP_CANT_INV_STAG = 0x09, 670 RDMAP_UNSPECIFIED = 0xff 671 }; 672 673 enum c4iw_ddp_ecodes { 674 DDPT_INV_STAG = 0x00, 675 DDPT_BASE_BOUNDS = 0x01, 676 DDPT_STAG_NOT_ASSOC = 0x02, 677 DDPT_TO_WRAP = 0x03, 678 DDPT_INV_VERS = 0x04, 679 DDPU_INV_QN = 0x01, 680 DDPU_INV_MSN_NOBUF = 0x02, 681 DDPU_INV_MSN_RANGE = 0x03, 682 DDPU_INV_MO = 0x04, 683 DDPU_MSG_TOOBIG = 0x05, 684 DDPU_INV_VERS = 0x06 685 }; 686 687 enum c4iw_mpa_ecodes { 688 MPA_CRC_ERR = 0x02, 689 MPA_MARKER_ERR = 0x03, 690 MPA_LOCAL_CATA = 0x05, 691 MPA_INSUFF_IRD = 0x06, 692 MPA_NOMATCH_RTR = 0x07, 693 }; 694 695 enum c4iw_ep_state { 696 IDLE = 0, 697 LISTEN, 698 CONNECTING, 699 MPA_REQ_WAIT, 700 MPA_REQ_SENT, 701 MPA_REQ_RCVD, 702 MPA_REP_SENT, 703 FPDU_MODE, 704 ABORTING, 705 CLOSING, 706 MORIBUND, 707 DEAD, 708 }; 709 710 enum c4iw_ep_flags { 711 PEER_ABORT_IN_PROGRESS = 0, 712 ABORT_REQ_IN_PROGRESS = 1, 713 RELEASE_RESOURCES = 2, 714 CLOSE_SENT = 3, 715 TIMEOUT = 4 716 }; 717 718 enum c4iw_ep_history { 719 ACT_OPEN_REQ = 0, 720 ACT_OFLD_CONN = 1, 721 ACT_OPEN_RPL = 2, 722 ACT_ESTAB = 3, 723 PASS_ACCEPT_REQ = 4, 724 PASS_ESTAB = 5, 725 ABORT_UPCALL = 6, 726 ESTAB_UPCALL = 7, 727 CLOSE_UPCALL = 8, 728 ULP_ACCEPT = 9, 729 ULP_REJECT = 10, 730 TIMEDOUT = 11, 731 PEER_ABORT = 12, 732 PEER_CLOSE = 13, 733 CONNREQ_UPCALL = 14, 734 ABORT_CONN = 15, 735 DISCONN_UPCALL = 16, 736 EP_DISC_CLOSE = 17, 737 EP_DISC_ABORT = 18, 738 CONN_RPL_UPCALL = 19, 739 ACT_RETRY_NOMEM = 20, 740 ACT_RETRY_INUSE = 21 741 }; 742 743 struct c4iw_ep_common { 744 TAILQ_ENTRY(c4iw_ep_common) entry; /* Work queue attachment */ 745 struct iw_cm_id *cm_id; 746 struct c4iw_qp *qp; 747 struct c4iw_dev *dev; 748 enum c4iw_ep_state state; 749 struct kref kref; 750 struct mutex mutex; 751 struct sockaddr_in local_addr; 752 struct sockaddr_in remote_addr; 753 struct c4iw_wr_wait wr_wait; 754 unsigned long flags; 755 unsigned long history; 756 int rpl_err; 757 int rpl_done; 758 struct thread *thread; 759 struct socket *so; 760 }; 761 762 struct c4iw_listen_ep { 763 struct c4iw_ep_common com; 764 unsigned int stid; 765 int backlog; 766 }; 767 768 struct c4iw_ep { 769 struct c4iw_ep_common com; 770 struct c4iw_ep *parent_ep; 771 struct timer_list timer; 772 struct list_head entry; 773 unsigned int atid; 774 u32 hwtid; 775 u32 snd_seq; 776 u32 rcv_seq; 777 struct l2t_entry *l2t; 778 struct dst_entry *dst; 779 struct c4iw_mpa_attributes mpa_attr; 780 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA]; 781 unsigned int mpa_pkt_len; 782 u32 ird; 783 u32 ord; 784 u32 smac_idx; 785 u32 tx_chan; 786 u32 mtu; 787 u16 mss; 788 u16 emss; 789 u16 plen; 790 u16 rss_qid; 791 u16 txq_idx; 792 u16 ctrlq_idx; 793 u8 tos; 794 u8 retry_with_mpa_v1; 795 u8 tried_with_mpa_v1; 796 }; 797 798 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id) 799 { 800 return cm_id->provider_data; 801 } 802 803 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id) 804 { 805 return cm_id->provider_data; 806 } 807 808 static inline int compute_wscale(int win) 809 { 810 int wscale = 0; 811 812 while (wscale < 14 && (65535<<wscale) < win) 813 wscale++; 814 return wscale; 815 } 816 817 u32 c4iw_id_alloc(struct c4iw_id_table *alloc); 818 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); 819 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, 820 u32 reserved, u32 flags); 821 void c4iw_id_table_free(struct c4iw_id_table *alloc); 822 823 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m); 824 825 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new, 826 struct l2t_entry *l2t); 827 u32 c4iw_get_resource(struct c4iw_id_table *id_table); 828 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry); 829 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid); 830 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev); 831 int c4iw_pblpool_create(struct c4iw_rdev *rdev); 832 int c4iw_rqtpool_create(struct c4iw_rdev *rdev); 833 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev); 834 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev); 835 void c4iw_destroy_resource(struct c4iw_resource *rscp); 836 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); 837 int c4iw_register_device(struct c4iw_dev *dev); 838 void c4iw_unregister_device(struct c4iw_dev *dev); 839 int __init c4iw_cm_init(void); 840 void __exit c4iw_cm_term(void); 841 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 842 struct c4iw_dev_ucontext *uctx); 843 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 844 struct c4iw_dev_ucontext *uctx); 845 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 846 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 847 struct ib_send_wr **bad_wr); 848 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 849 struct ib_recv_wr **bad_wr); 850 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, 851 struct ib_mw_bind *mw_bind); 852 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 853 int c4iw_create_listen_ep(struct iw_cm_id *cm_id, int backlog); 854 void c4iw_destroy_listen_ep(struct iw_cm_id *cm_id); 855 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 856 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); 857 void c4iw_qp_add_ref(struct ib_qp *qp); 858 void c4iw_qp_rem_ref(struct ib_qp *qp); 859 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list); 860 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl( 861 struct ib_device *device, 862 int page_list_len); 863 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth); 864 int c4iw_dealloc_mw(struct ib_mw *mw); 865 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type); 866 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64 867 virt, int acc, struct ib_udata *udata, int mr_id); 868 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); 869 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd, 870 struct ib_phys_buf *buffer_list, 871 int num_phys_buf, 872 int acc, 873 u64 *iova_start); 874 int c4iw_reregister_phys_mem(struct ib_mr *mr, 875 int mr_rereg_mask, 876 struct ib_pd *pd, 877 struct ib_phys_buf *buffer_list, 878 int num_phys_buf, 879 int acc, u64 *iova_start); 880 int c4iw_dereg_mr(struct ib_mr *ib_mr); 881 int c4iw_destroy_cq(struct ib_cq *ib_cq); 882 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, struct ib_cq_init_attr *attr, 883 struct ib_ucontext *ib_context, 884 struct ib_udata *udata); 885 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata); 886 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 887 int c4iw_destroy_qp(struct ib_qp *ib_qp); 888 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, 889 struct ib_qp_init_attr *attrs, 890 struct ib_udata *udata); 891 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 892 int attr_mask, struct ib_udata *udata); 893 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 894 int attr_mask, struct ib_qp_init_attr *init_attr); 895 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn); 896 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size); 897 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 898 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size); 899 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 900 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m); 901 void c4iw_flush_hw_cq(struct t4_cq *cq); 902 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 903 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 904 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); 905 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count); 906 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count); 907 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *); 908 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 909 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 910 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 911 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid, 912 struct c4iw_dev_ucontext *uctx); 913 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 914 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid, 915 struct c4iw_dev_ucontext *uctx); 916 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe); 917 void process_newconn(struct iw_cm_id *parent_cm_id, 918 struct socket *child_so); 919 920 extern struct cxgb4_client t4c_client; 921 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; 922 extern int c4iw_max_read_depth; 923 924 #include <sys/blist.h> 925 struct gen_pool { 926 blist_t gen_list; 927 daddr_t gen_base; 928 int gen_chunk_shift; 929 struct mutex gen_lock; 930 }; 931 932 static __inline struct gen_pool * 933 gen_pool_create(daddr_t base, u_int chunk_shift, u_int len) 934 { 935 struct gen_pool *gp; 936 937 gp = malloc(sizeof(struct gen_pool), M_DEVBUF, M_NOWAIT); 938 if (gp == NULL) 939 return (NULL); 940 941 memset(gp, 0, sizeof(struct gen_pool)); 942 gp->gen_list = blist_create(len >> chunk_shift, M_NOWAIT); 943 if (gp->gen_list == NULL) { 944 free(gp, M_DEVBUF); 945 return (NULL); 946 } 947 blist_free(gp->gen_list, 0, len >> chunk_shift); 948 gp->gen_base = base; 949 gp->gen_chunk_shift = chunk_shift; 950 //mutex_init(&gp->gen_lock, "genpool", NULL, MTX_DUPOK|MTX_DEF); 951 mutex_init(&gp->gen_lock); 952 953 return (gp); 954 } 955 956 static __inline unsigned long 957 gen_pool_alloc(struct gen_pool *gp, int size) 958 { 959 int chunks; 960 daddr_t blkno; 961 962 chunks = (size + (1<<gp->gen_chunk_shift) - 1) >> gp->gen_chunk_shift; 963 mutex_lock(&gp->gen_lock); 964 blkno = blist_alloc(gp->gen_list, chunks); 965 mutex_unlock(&gp->gen_lock); 966 967 if (blkno == SWAPBLK_NONE) 968 return (0); 969 970 return (gp->gen_base + ((1 << gp->gen_chunk_shift) * blkno)); 971 } 972 973 static __inline void 974 gen_pool_free(struct gen_pool *gp, daddr_t address, int size) 975 { 976 int chunks; 977 daddr_t blkno; 978 979 chunks = (size + (1<<gp->gen_chunk_shift) - 1) >> gp->gen_chunk_shift; 980 blkno = (address - gp->gen_base) / (1 << gp->gen_chunk_shift); 981 mutex_lock(&gp->gen_lock); 982 blist_free(gp->gen_list, blkno, chunks); 983 mutex_unlock(&gp->gen_lock); 984 } 985 986 static __inline void 987 gen_pool_destroy(struct gen_pool *gp) 988 { 989 blist_destroy(gp->gen_list); 990 free(gp, M_DEVBUF); 991 } 992 993 #if defined(__i386__) || defined(__amd64__) 994 #define L1_CACHE_BYTES 128 995 #else 996 #define L1_CACHE_BYTES 32 997 #endif 998 999 static inline 1000 int idr_for_each(struct idr *idp, 1001 int (*fn)(int id, void *p, void *data), void *data) 1002 { 1003 int n, id, max, error = 0; 1004 struct idr_layer *p; 1005 struct idr_layer *pa[MAX_LEVEL]; 1006 struct idr_layer **paa = &pa[0]; 1007 1008 n = idp->layers * IDR_BITS; 1009 p = idp->top; 1010 max = 1 << n; 1011 1012 id = 0; 1013 while (id < max) { 1014 while (n > 0 && p) { 1015 n -= IDR_BITS; 1016 *paa++ = p; 1017 p = p->ary[(id >> n) & IDR_MASK]; 1018 } 1019 1020 if (p) { 1021 error = fn(id, (void *)p, data); 1022 if (error) 1023 break; 1024 } 1025 1026 id += 1 << n; 1027 while (n < fls(id)) { 1028 n += IDR_BITS; 1029 p = *--paa; 1030 } 1031 } 1032 1033 return error; 1034 } 1035 1036 void c4iw_cm_init_cpl(struct adapter *); 1037 void c4iw_cm_term_cpl(struct adapter *); 1038 1039 void your_reg_device(struct c4iw_dev *dev); 1040 1041 #define SGE_CTRLQ_NUM 0 1042 1043 #endif 1044