1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 #include <sys/cdefs.h> 35 #include "opt_inet.h" 36 37 #ifdef TCP_OFFLOAD 38 #include <linux/slab.h> 39 40 #include "iw_cxgbe.h" 41 42 static void print_tpte(struct adapter *sc, const u32 stag, 43 const struct fw_ri_tpte *tpte) 44 { 45 const __be64 *p = (const void *)tpte; 46 47 CH_ERR(sc, "stag idx 0x%x valid %d key 0x%x state %d pdid %d " 48 "perm 0x%x ps %d len 0x%016llx va 0x%016llx\n", 49 stag & 0xffffff00, 50 G_FW_RI_TPTE_VALID(ntohl(tpte->valid_to_pdid)), 51 G_FW_RI_TPTE_STAGKEY(ntohl(tpte->valid_to_pdid)), 52 G_FW_RI_TPTE_STAGSTATE(ntohl(tpte->valid_to_pdid)), 53 G_FW_RI_TPTE_PDID(ntohl(tpte->valid_to_pdid)), 54 G_FW_RI_TPTE_PERM(ntohl(tpte->locread_to_qpid)), 55 G_FW_RI_TPTE_PS(ntohl(tpte->locread_to_qpid)), 56 (long long)(((u64)ntohl(tpte->len_hi) << 32) | ntohl(tpte->len_lo)), 57 (long long)(((u64)ntohl(tpte->va_hi) << 32) | ntohl(tpte->va_lo_fbo))); 58 CH_ERR(sc, "stag idx 0x%x: %016llx %016llx %016llx %016llx\n", 59 stag & 0xffffff00, 60 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 61 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3])); 62 } 63 64 void t4_dump_stag(struct adapter *sc, const u32 stag) 65 { 66 struct fw_ri_tpte tpte __aligned(sizeof(__be64)) = {0}; 67 const u32 offset = sc->vres.stag.start + ((stag >> 8) * 32); 68 69 if (offset > sc->vres.stag.start + sc->vres.stag.size - 32) { 70 CH_ERR(sc, "stag 0x%x is invalid for current configuration.\n", 71 stag); 72 return; 73 } 74 read_via_memwin(sc, 0, offset, (u32 *)&tpte, 32); 75 print_tpte(sc, stag, &tpte); 76 } 77 78 void t4_dump_all_stag(struct adapter *sc) 79 { 80 struct fw_ri_tpte tpte __aligned(sizeof(__be64)) = {0}; 81 const u32 first = sc->vres.stag.start; 82 const u32 last = first + sc->vres.stag.size - 32; 83 u32 offset, i; 84 85 for (i = 0, offset = first; offset <= last; i++, offset += 32) { 86 tpte.valid_to_pdid = 0; 87 read_via_memwin(sc, 0, offset, (u32 *)&tpte, 4); 88 if (tpte.valid_to_pdid != 0) { 89 read_via_memwin(sc, 0, offset, (u32 *)&tpte, 32); 90 print_tpte(sc, i << 8, &tpte); 91 } 92 } 93 } 94 95 static void dump_err_cqe(struct c4iw_dev *dev, struct t4_cqe *err_cqe) 96 { 97 struct adapter *sc = dev->rdev.adap; 98 __be64 *p = (void *)err_cqe; 99 100 CH_ERR(sc, "AE qpid 0x%x opcode %d status 0x%x " 101 "type %d wrid.hi 0x%x wrid.lo 0x%x\n", 102 CQE_QPID(err_cqe), CQE_OPCODE(err_cqe), 103 CQE_STATUS(err_cqe), CQE_TYPE(err_cqe), 104 CQE_WRID_HI(err_cqe), CQE_WRID_LOW(err_cqe)); 105 CH_ERR(sc, "%016llx %016llx %016llx %016llx\n", 106 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 107 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3])); 108 109 /* 110 * Ingress WRITE and READ_RESP errors provide 111 * the offending stag, so parse and log it. 112 */ 113 if (RQ_TYPE(err_cqe) && (CQE_OPCODE(err_cqe) == FW_RI_RDMA_WRITE || 114 CQE_OPCODE(err_cqe) == FW_RI_READ_RESP)) 115 t4_dump_stag(sc, CQE_WRID_STAG(err_cqe)); 116 } 117 118 static void post_qp_event(struct c4iw_dev *dev, struct c4iw_cq *chp, 119 struct c4iw_qp *qhp, 120 struct t4_cqe *err_cqe, 121 enum ib_event_type ib_event) 122 { 123 struct ib_event event; 124 struct c4iw_qp_attributes attrs; 125 unsigned long flag; 126 127 if ((qhp->attr.state == C4IW_QP_STATE_ERROR) || 128 (qhp->attr.state == C4IW_QP_STATE_TERMINATE)) { 129 CTR4(KTR_IW_CXGBE, "%s AE received after RTS - " 130 "qp state %d qpid 0x%x status 0x%x", __func__, 131 qhp->attr.state, qhp->wq.sq.qid, CQE_STATUS(err_cqe)); 132 return; 133 } 134 135 dump_err_cqe(dev, err_cqe); 136 137 if (qhp->attr.state == C4IW_QP_STATE_RTS) { 138 attrs.next_state = C4IW_QP_STATE_TERMINATE; 139 c4iw_modify_qp(qhp->rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, 140 &attrs, 0); 141 } 142 143 event.event = ib_event; 144 event.device = chp->ibcq.device; 145 if (ib_event == IB_EVENT_CQ_ERR) 146 event.element.cq = &chp->ibcq; 147 else 148 event.element.qp = &qhp->ibqp; 149 if (qhp->ibqp.event_handler) 150 (*qhp->ibqp.event_handler)(&event, qhp->ibqp.qp_context); 151 152 spin_lock_irqsave(&chp->comp_handler_lock, flag); 153 (*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context); 154 spin_unlock_irqrestore(&chp->comp_handler_lock, flag); 155 } 156 157 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe) 158 { 159 struct c4iw_cq *chp; 160 struct c4iw_qp *qhp; 161 u32 cqid; 162 163 spin_lock_irq(&dev->lock); 164 xa_lock_irq(&dev->qps); 165 qhp = xa_load(&dev->qps, CQE_QPID(err_cqe)); 166 if (!qhp) { 167 printf("BAD AE qpid 0x%x opcode %d " 168 "status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n", 169 CQE_QPID(err_cqe), 170 CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe), 171 CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe), 172 CQE_WRID_LOW(err_cqe)); 173 xa_unlock_irq(&dev->qps); 174 goto out; 175 } 176 177 if (SQ_TYPE(err_cqe)) 178 cqid = qhp->attr.scq; 179 else 180 cqid = qhp->attr.rcq; 181 chp = get_chp(dev, cqid); 182 if (!chp) { 183 printf("BAD AE cqid 0x%x qpid 0x%x opcode %d " 184 "status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n", 185 cqid, CQE_QPID(err_cqe), 186 CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe), 187 CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe), 188 CQE_WRID_LOW(err_cqe)); 189 xa_unlock_irq(&dev->qps); 190 goto out; 191 } 192 193 c4iw_qp_add_ref(&qhp->ibqp); 194 atomic_inc(&chp->refcnt); 195 xa_unlock_irq(&dev->qps); 196 197 /* Bad incoming write */ 198 if (RQ_TYPE(err_cqe) && 199 (CQE_OPCODE(err_cqe) == FW_RI_RDMA_WRITE)) { 200 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_REQ_ERR); 201 goto done; 202 } 203 204 switch (CQE_STATUS(err_cqe)) { 205 206 /* Completion Events */ 207 case T4_ERR_SUCCESS: 208 printf(KERN_ERR MOD "AE with status 0!\n"); 209 break; 210 211 case T4_ERR_STAG: 212 case T4_ERR_PDID: 213 case T4_ERR_QPID: 214 case T4_ERR_ACCESS: 215 case T4_ERR_WRAP: 216 case T4_ERR_BOUND: 217 case T4_ERR_INVALIDATE_SHARED_MR: 218 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 219 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_ACCESS_ERR); 220 break; 221 222 /* Device Fatal Errors */ 223 case T4_ERR_ECC: 224 case T4_ERR_ECC_PSTAG: 225 case T4_ERR_INTERNAL_ERR: 226 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_DEVICE_FATAL); 227 break; 228 229 /* QP Fatal Errors */ 230 case T4_ERR_OUT_OF_RQE: 231 case T4_ERR_PBL_ADDR_BOUND: 232 case T4_ERR_CRC: 233 case T4_ERR_MARKER: 234 case T4_ERR_PDU_LEN_ERR: 235 case T4_ERR_DDP_VERSION: 236 case T4_ERR_RDMA_VERSION: 237 case T4_ERR_OPCODE: 238 case T4_ERR_DDP_QUEUE_NUM: 239 case T4_ERR_MSN: 240 case T4_ERR_TBIT: 241 case T4_ERR_MO: 242 case T4_ERR_MSN_GAP: 243 case T4_ERR_MSN_RANGE: 244 case T4_ERR_RQE_ADDR_BOUND: 245 case T4_ERR_IRD_OVERFLOW: 246 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL); 247 break; 248 249 default: 250 printf("Unknown T4 status 0x%x QPID 0x%x\n", 251 CQE_STATUS(err_cqe), qhp->wq.sq.qid); 252 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL); 253 break; 254 } 255 done: 256 if (atomic_dec_and_test(&chp->refcnt)) 257 wake_up(&chp->wait); 258 c4iw_qp_rem_ref(&qhp->ibqp); 259 out: 260 return; 261 } 262 263 int c4iw_ev_handler(struct sge_iq *iq, const struct rsp_ctrl *rc) 264 { 265 struct c4iw_dev *dev = iq->adapter->iwarp_softc; 266 u32 qid = be32_to_cpu(rc->pldbuflen_qid); 267 struct c4iw_cq *chp; 268 unsigned long flag; 269 270 xa_lock_irqsave(&dev->cqs, flag); 271 chp = xa_load(&dev->cqs, qid); 272 if (chp) { 273 atomic_inc(&chp->refcnt); 274 xa_unlock_irqrestore(&dev->cqs, flag); 275 276 spin_lock_irqsave(&chp->comp_handler_lock, flag); 277 (*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context); 278 spin_unlock_irqrestore(&chp->comp_handler_lock, flag); 279 if (atomic_dec_and_test(&chp->refcnt)) 280 wake_up(&chp->wait); 281 } else { 282 CTR2(KTR_IW_CXGBE, "%s unknown cqid 0x%x", __func__, qid); 283 xa_unlock_irqrestore(&dev->cqs, flag); 284 } 285 286 return 0; 287 } 288 #endif 289