1# Chelsio T6 Factory Default configuration file. 2# 3# Copyright (C) 2014-2015 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7# TO ADAPTERS. 8 9 10# This file provides the default, power-on configuration for 2-port T6-based 11# adapters shipped from the factory. These defaults are designed to address 12# the needs of the vast majority of Terminator customers. The basic idea is to 13# have a default configuration which allows a customer to plug a Terminator 14# adapter in and have it work regardless of OS, driver or application except in 15# the most unusual and/or demanding customer applications. 16# 17# Many of the Terminator resources which are described by this configuration 18# are finite. This requires balancing the configuration/operation needs of 19# device drivers across OSes and a large number of customer application. 20# 21# Some of the more important resources to allocate and their constaints are: 22# 1. Virtual Interfaces: 256. 23# 2. Ingress Queues with Free Lists: 1024. 24# 3. Egress Queues: 128K. 25# 4. MSI-X Vectors: 1088. 26# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27# address matching on Ingress Packets. 28# 29# Some of the important OS/Driver resource needs are: 30# 6. Some OS Drivers will manage all resources through a single Physical 31# Function (currently PF4 but it could be any Physical Function). 32# 7. Some OS Drivers will manage different ports and functions (NIC, 33# storage, etc.) on different Physical Functions. For example, NIC 34# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc. 35# 36# Some of the customer application needs which need to be accommodated: 37# 8. Some customers will want to support large CPU count systems with 38# good scaling. Thus, we'll need to accommodate a number of 39# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40# to be involved per port and per application function. For example, 41# in the case where all ports and application functions will be 42# managed via a single Unified PF and we want to accommodate scaling up 43# to 8 CPUs, we would want: 44# 45# 2 ports * 46# 3 application functions (NIC, FCoE, iSCSI) per port * 47# 16 Ingress Queue/MSI-X Vectors per application function 48# 49# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50# (Plus a few for Firmware Event Queues, etc.) 51# 52# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54# and "PCI Device Passthrough" -- this is especially true for the NIC 55# application functionality. 56# 57 58 59# Global configuration settings. 60# 61[global] 62 rss_glb_config_mode = basicvirtual 63 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64 65 # PL_TIMEOUT register 66 pl_timeout_value = 1000 # the timeout value in units of us 67 68 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69 # Page Size and a 64B L1 Cache Line Size. It programs the 70 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71 # If a Master PF Driver finds itself on a machine with different 72 # parameters, then the Master PF Driver is responsible for initializing 73 # these parameters to appropriate values. 74 # 75 # Notes: 76 # 1. The Free List Buffer Sizes below are raw and the firmware will 77 # round them up to the Ingress Padding Boundary. 78 # 2. The SGE Timer Values below are expressed below in microseconds. 79 # The firmware will convert these values to Core Clock Ticks when 80 # it processes the configuration parameters. 81 # 82 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94 reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 95 reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL 96 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 97 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread 98 reg[0x173c] = 0x2/0x2 99 100 reg[0x1750] = 0x01000000/0x03c00000 # RDMA_INV_Handling = 1 101 # terminate_status_en = 0 102 # DISABLE = 0 103 104 #DBQ Timer duration = 1 cclk cycle duration * (sge_dbq_timertick+1) * sge_dbq_timer 105 #SGE DBQ tick value. All timers are multiple of this value 106 sge_dbq_timertick = 1 #in usecs 107 sge_dbq_timer = 1, 2, 4, 6, 8, 10, 12, 16 108 # enable TP_OUT_CONFIG.IPIDSPLITMODE 109 reg[0x7d04] = 0x00010000/0x00010000 110 111 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 112 113 reg[0x46004] = 0x3/0x3 # Crypto core reset 114 reg[0x46000] = 0xa/0xe # 16K ESH Hi Extraction window 115 116 #Tick granularities in kbps 117 tsch_ticks = 1000, 100, 10, 1 118 119 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 120 # filter control: compact, fcoemask 121 # server sram : srvrsram 122 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 123 # protocol, tos, vlan, vnic_id, port, fcoe 124 # valid filterModes are described the Terminator 5 Data Book 125 filterMode = fcoemask, srvrsram, ipsec, rocev2, fragmentation, mpshittype, protocol, vlan, port, fcoe 126 127 # filter tuples enforced in LE active region (equal to or subset of filterMode) 128 filterMask = protocol, ipsec, rocev2, fcoe 129 130 # Percentage of dynamic memory (in either the EDRAM or external MEM) 131 # to use for TP RX payload 132 tp_pmrx = 30 133 134 # TP RX payload page size 135 tp_pmrx_pagesize = 64K 136 137 # Percentage of dynamic memory (in either the EDRAM or external MEM) 138 # to use for TP TX payload 139 tp_pmtx = 50 140 141 # TP TX payload page size 142 tp_pmtx_pagesize = 64K 143 144 # TP OFLD MTUs 145 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 146 147 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC 148 reg[0x7d04] = 0x00010008/0x00010008 149 150 # TP_GLOBAL_CONFIG 151 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 152 153 # TP_PC_CONFIG 154 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 155 156 # TP_PARA_REG0 157 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 158 159 # ULPRX iSCSI Page Sizes 160 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 161 162 # LE_DB_CONFIG 163 reg[0x19c04] = 0x00400000/0x00440000 # LE Server SRAM Enable, 164 # LE IPv4 compression disabled 165 # LE_DB_HASH_CONFIG 166 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 167 168 # ULP_TX_CONFIG 169 reg[0x8dc0] = 0x00000104/0x02000104 # Enable ITT on PI err 170 # Enable more error msg for ... 171 # TPT error. 172 # Err2uP = 0 173 174 #ULP_RX_CTL1 175 reg[0x19330] = 0x000000f0/0x000000f0 # RDMA_Invld_Msg_Dis = 3 176 # ROCE_Invld_Msg_Dis = 3 177 178 #Enable iscsi completion moderation feature, disable rdma invlidate in ulptx 179 reg[0x1925c] = 0x000041c0/0x000031d0 # Enable offset decrement after 180 # PI extraction and before DDP. 181 # ulp insert pi source info in 182 # DIF. 183 # Enable iscsi hdr cmd mode. 184 # iscsi force cmd mode. 185 # Enable iscsi cmp mode. 186 # terminate_status_en = 0 187 188 #ULP_RX_CQE_GEN_EN 189 reg[0x19250] = 0x0/0x3 # Termimate_msg = 0 190 # Terminate_with_err = 0 191 192 #gc_disable = 3 # 3 - disable gc for hma/mc1 and mc0, 193 # 2 - disable gc for mc1/hma enable mc0, 194 # 1 - enable gc for mc1/hma disable mc0, 195 # 0 - enable gc for mc1/hma and for mc0, 196 # default gc enabled. 197 198 # HMA configuration (uncomment following lines to enable HMA) 199 hma_size = 92 # Size (in MBs) of host memory expected 200 hma_regions = iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq # What all regions to place in host memory 201 202 #mc[0]=0 203 #mc[1]=0 204 205# Some "definitions" to make the rest of this a bit more readable. We support 206# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 207# per function per port ... 208# 209# NMSIX = 1088 # available MSI-X Vectors 210# NVI = 256 # available Virtual Interfaces 211# NMPSTCAM = 336 # MPS TCAM entries 212# 213# NPORTS = 2 # ports 214# NCPUS = 16 # CPUs we want to support scalably 215# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 216 217# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 218# PF" which many OS Drivers will use to manage most or all functions. 219# 220# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 221# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 222# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 223# will be specified as the "Ingress Queue Asynchronous Destination Index." 224# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 225# than or equal to the number of Ingress Queues ... 226# 227# NVI_NIC = 4 # NIC access to NPORTS 228# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 229# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 230# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 231# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 232# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 233# 234# NVI_OFLD = 0 # Offload uses NIC function to access ports 235# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 236# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 237# NEQ_OFLD = 16 # Offload Egress Queues (FL) 238# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 239# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 240# 241# NVI_RDMA = 0 # RDMA uses NIC function to access ports 242# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 243# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 244# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 245# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 246# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 247# 248# NEQ_WD = 128 # Wire Direct TX Queues and FLs 249# NETHCTRL_WD = 64 # Wire Direct TX Queues 250# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 251# 252# NVI_ISCSI = 4 # ISCSI access to NPORTS 253# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 254# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 255# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 256# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 257# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 258# 259# NVI_FCOE = 4 # FCOE access to NPORTS 260# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 261# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 262# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 263# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 264# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 265 266# Two extra Ingress Queues per function for Firmware Events and Forwarded 267# Interrupts, and two extra interrupts per function for Firmware Events (or a 268# Forwarded Interrupt Queue) and General Interrupts per function. 269# 270# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 271# # Forwarded Interrupts 272# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 273# # General Interrupts 274 275# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 276# their interrupts forwarded to another set of Forwarded Interrupt Queues. 277# 278# NVI_HYPERV = 16 # VMs we want to support 279# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 280# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 281# NEQ_HYPERV = 32 # VIQs Free Lists 282# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 283# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 284 285# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 286# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 287# 288# NVI_UNIFIED = 28 289# NFLIQ_UNIFIED = 106 290# NETHCTRL_UNIFIED = 32 291# NEQ_UNIFIED = 124 292# NMPSTCAM_UNIFIED = 40 293# 294# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 295# that up to 128 to make sure the Unified PF doesn't run out of resources. 296# 297# NMSIX_UNIFIED = 128 298# 299# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 300# which is 34 but they're probably safe with 32. 301# 302# NMSIX_STORAGE = 32 303 304# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 305# associated with it. Thus, the MSI-X Vector allocations we give to the 306# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 307# provision many more Virtual Functions than we can if the UnifiedPF were 308# one of PF0-1. 309# 310 311# All of the below PCI-E parameters are actually stored in various *_init.txt 312# files. We include them below essentially as comments. 313# 314# For PF0-1 we assign 8 vectors each for NIC Ingress Queues of the associated 315# ports 0-1. 316# 317# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 318# 319# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 320# storage applications across all four possible ports. 321# 322# Additionally, since the UnifiedPF isn't one of the per-port Physical 323# Functions, we give the UnifiedPF and the PF0-1 Physical Functions 324# different PCI Device IDs which will allow Unified and Per-Port Drivers 325# to directly select the type of Physical Function to which they wish to be 326# attached. 327# 328# Note that the actual values used for the PCI-E Intelectual Property will be 329# 1 less than those below since that's the way it "counts" things. For 330# readability, we use the number we actually mean ... 331# 332# PF0_INT = 8 # NCPUS 333# PF1_INT = 8 # NCPUS 334# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 335# 336# PF4_INT = 128 # NMSIX_UNIFIED 337# PF5_INT = 32 # NMSIX_STORAGE 338# PF6_INT = 32 # NMSIX_STORAGE 339# PF7_INT = 0 # Nothing Assigned 340# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 341# 342# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 343# 344# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 345# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 346# 347# NVF = 16 348 349 350# For those OSes which manage different ports on different PFs, we need 351# only enough resources to support a single port's NIC application functions 352# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 353# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 354# managed on the "storage PFs" (see below). 355# 356 357# Some OS Drivers manage all application functions for all ports via PF4. 358# Thus we need to provide a large number of resources here. For Egress 359# Queues we need to account for both TX Queues as well as Free List Queues 360# (because the host is responsible for producing Free List Buffers for the 361# hardware to consume). 362# 363[function "0"] 364 wx_caps = all # write/execute permissions for all commands 365 r_caps = all # read permissions for all commands 366 nvi = 28 # NVI_UNIFIED 367 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 368 nethctrl = 96 # NETHCTRL_UNIFIED + NETHCTRL_WD 369 neq = 252 # NEQ_UNIFIED + NEQ_WD 370 nqpcq = 12288 371 nexactf = 40 # NMPSTCAM_UNIFIED 372 nrawf = 4 373 cmask = all # access to all channels 374 pmask = all # access to all four ports ... 375 nethofld = 1024 # number of user mode ethernet flow contexts 376 ncrypto_lookaside = 32 377 nclip = 32 # number of clip region entries 378 nfilter = 48 # number of filter region entries 379 nserver = 48 # number of server region entries 380 nhash = 12288 # number of hash region entries 381 nhpfilter = 64 # number of high priority filter region entries 382 #protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, ofld_sendpath 383 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp 384 tp_l2t = 3072 385 tp_ddp = 2 386 tp_ddp_iscsi = 2 387 tp_tls_key = 3 388 tp_tls_mxrxsize = 33792 # 32768 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes 389 tp_stag = 2 390 tp_pbl = 5 391 tp_rq = 7 392 tp_rrq = 4 393 tp_srq = 128 394 nipsec_tunnel16 = 64 # in unit of 16 395 nipsec_transport16 = 191 # in unit of 16 396 397 398# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 399# need to have Virtual Interfaces on each of the four ports with up to NCPUS 400# "Queue Sets" each. 401# 402[function "1"] 403 wx_caps = all # write/execute permissions for all commands 404 r_caps = all # read permissions for all commands 405 nvi = 4 # NPORTS 406 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 407 nethctrl = 32 # NPORTS*NCPUS 408 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 409 nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 410 cmask = all # access to all channels 411 pmask = all # access to all four ports ... 412 nserver = 16 413 nhash = 2048 414 tp_l2t = 1020 415 protocol = iscsi_initiator_fofld 416 tp_ddp_iscsi = 2 417 iscsi_ntask = 2048 418 iscsi_nsess = 2048 419 iscsi_nconn_per_session = 1 420 iscsi_ninitiator_instance = 64 421 422 423# The following function, 1023, is not an actual PCIE function but is used to 424# configure and reserve firmware internal resources that come from the global 425# resource pool. 426# 427[function "1023"] 428 wx_caps = all # write/execute permissions for all commands 429 r_caps = all # read permissions for all commands 430 nvi = 4 # NVI_UNIFIED 431 cmask = all # access to all channels 432 pmask = all # access to all four ports ... 433 nexactf = 8 # NPORTS + DCBX + 434 nfilter = 16 # number of filter region entries 435 #nhpfilter = 0 # number of high priority filter region entries 436 437 438# For Virtual functions, we only allow NIC functionality and we only allow 439# access to one port (1 << PF). Note that because of limitations in the 440# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 441# and GTS registers, the number of Ingress and Egress Queues must be a power 442# of 2. 443# 444[function "0/*"] # NVF 445 wx_caps = 0x82 # DMAQ | VF 446 r_caps = 0x86 # DMAQ | VF | PORT 447 nvi = 1 # 1 port 448 niqflint = 6 # 2 "Queue Sets" + NXIQ 449 nethctrl = 4 # 2 "Queue Sets" 450 neq = 8 # 2 "Queue Sets" * 2 451 nexactf = 4 452 cmask = all # access to all channels 453 pmask = 0x1 # access to only one port ... 454 455 456[function "1/*"] # NVF 457 wx_caps = 0x82 # DMAQ | VF 458 r_caps = 0x86 # DMAQ | VF | PORT 459 nvi = 1 # 1 port 460 niqflint = 6 # 2 "Queue Sets" + NXIQ 461 nethctrl = 4 # 2 "Queue Sets" 462 neq = 8 # 2 "Queue Sets" * 2 463 nexactf = 4 464 cmask = all # access to all channels 465 pmask = 0x2 # access to only one port ... 466 467 468# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 469# for packets from the wire as well as the loopback path of the L2 switch. The 470# folling params control how the buffer memory is distributed and the L2 flow 471# control settings: 472# 473# bg_mem: %-age of mem to use for port/buffer group 474# lpbk_mem: %-age of port/bg mem to use for loopback 475# hwm: high watermark; bytes available when starting to send pause 476# frames (in units of 0.1 MTU) 477# lwm: low watermark; bytes remaining when sending 'unpause' frame 478# (in inuits of 0.1 MTU) 479# dwm: minimum delta between high and low watermark (in units of 100 480# Bytes) 481# 482[port "0"] 483 dcb = ppp, dcbx, b2b # configure for DCB PPP and enable DCBX offload 484 hwm = 30 485 lwm = 15 486 dwm = 30 487 dcb_app_tlv[0] = 0x8906, ethertype, 3 488 dcb_app_tlv[1] = 0x8914, ethertype, 3 489 dcb_app_tlv[2] = 3260, socketnum, 5 490 491 492[port "1"] 493 dcb = ppp, dcbx, b2b 494 hwm = 30 495 lwm = 15 496 dwm = 30 497 dcb_app_tlv[0] = 0x8906, ethertype, 3 498 dcb_app_tlv[1] = 0x8914, ethertype, 3 499 dcb_app_tlv[2] = 3260, socketnum, 5 500 501[port "2"] 502 dcb = ppp, dcbx, b2b # configure for DCB PPP and enable DCBX offload 503 hwm = 30 504 lwm = 15 505 dwm = 30 506 dcb_app_tlv[0] = 0x8906, ethertype, 3 507 dcb_app_tlv[1] = 0x8914, ethertype, 3 508 dcb_app_tlv[2] = 3260, socketnum, 5 509 510 511[port "3"] 512 dcb = ppp, dcbx, b2b 513 hwm = 30 514 lwm = 15 515 dwm = 30 516 dcb_app_tlv[0] = 0x8906, ethertype, 3 517 dcb_app_tlv[1] = 0x8914, ethertype, 3 518 dcb_app_tlv[2] = 3260, socketnum, 5 519 520[fini] 521 version = 0x1425001d 522 checksum = 0x22432d98 523 524# Total resources used by above allocations: 525# Virtual Interfaces: 104 526# Ingress Queues/w Free Lists and Interrupts: 526 527# Egress Queues: 702 528# MPS TCAM Entries: 336 529# MSI-X Vectors: 736 530# Virtual Functions: 64 531