1# Chelsio T6 Factory Default configuration file. 2# 3# Copyright (C) 2014-2015 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7# TO ADAPTERS. 8 9 10# This file provides the default, power-on configuration for 2-port T6-based 11# adapters shipped from the factory. These defaults are designed to address 12# the needs of the vast majority of Terminator customers. The basic idea is to 13# have a default configuration which allows a customer to plug a Terminator 14# adapter in and have it work regardless of OS, driver or application except in 15# the most unusual and/or demanding customer applications. 16# 17# Many of the Terminator resources which are described by this configuration 18# are finite. This requires balancing the configuration/operation needs of 19# device drivers across OSes and a large number of customer application. 20# 21# Some of the more important resources to allocate and their constaints are: 22# 1. Virtual Interfaces: 256. 23# 2. Ingress Queues with Free Lists: 1024. 24# 3. Egress Queues: 128K. 25# 4. MSI-X Vectors: 1088. 26# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27# address matching on Ingress Packets. 28# 29# Some of the important OS/Driver resource needs are: 30# 6. Some OS Drivers will manage all resources through a single Physical 31# Function (currently PF4 but it could be any Physical Function). 32# 7. Some OS Drivers will manage different ports and functions (NIC, 33# storage, etc.) on different Physical Functions. For example, NIC 34# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc. 35# 36# Some of the customer application needs which need to be accommodated: 37# 8. Some customers will want to support large CPU count systems with 38# good scaling. Thus, we'll need to accommodate a number of 39# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40# to be involved per port and per application function. For example, 41# in the case where all ports and application functions will be 42# managed via a single Unified PF and we want to accommodate scaling up 43# to 8 CPUs, we would want: 44# 45# 2 ports * 46# 3 application functions (NIC, FCoE, iSCSI) per port * 47# 16 Ingress Queue/MSI-X Vectors per application function 48# 49# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50# (Plus a few for Firmware Event Queues, etc.) 51# 52# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54# and "PCI Device Passthrough" -- this is especially true for the NIC 55# application functionality. 56# 57 58 59# Global configuration settings. 60# 61[global] 62 rss_glb_config_mode = basicvirtual 63 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64 65 # PL_TIMEOUT register 66 pl_timeout_value = 200 # the timeout value in units of us 67 68 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69 # Page Size and a 64B L1 Cache Line Size. It programs the 70 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71 # If a Master PF Driver finds itself on a machine with different 72 # parameters, then the Master PF Driver is responsible for initializing 73 # these parameters to appropriate values. 74 # 75 # Notes: 76 # 1. The Free List Buffer Sizes below are raw and the firmware will 77 # round them up to the Ingress Padding Boundary. 78 # 2. The SGE Timer Values below are expressed below in microseconds. 79 # The firmware will convert these values to Core Clock Ticks when 80 # it processes the configuration parameters. 81 # 82 reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL 83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94 95 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 96 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread 97 98 # Set the SGE Doorbell Queue Timer "tick" to 5us and initialize 99 # the Timer Table to a default set of values (which are multiples 100 # of the Timer Tick). 101 # 102 sge_dbq_timertick = 5 103 sge_dbq_timer = 1, 2, 3, 5, 7, 9, 12, 16 104 105 # enable TP_OUT_CONFIG.IPIDSPLITMODE 106 reg[0x7d04] = 0x00010000/0x00010000 107 108 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 109 110 #Tick granularities in kbps 111 tsch_ticks = 100000, 10000, 1000, 10 112 113 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 114 # filter control: compact, fcoemask 115 # server sram : srvrsram 116 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 117 # protocol, tos, vlan, vnic_id, port, fcoe 118 # valid filterModes are described the Terminator 5 Data Book 119 # vnicMode = pf_vf #default. Other values are outer_vlan, encapsulation 120 filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 121 122 # filter tuples enforced in LE active region (equal to or subset of filterMode) 123 filterMask = protocol, fcoe 124 125 # Percentage of dynamic memory (in either the EDRAM or external MEM) 126 # to use for TP RX payload 127 tp_pmrx = 30 128 129 # TP RX payload page size 130 tp_pmrx_pagesize = 64K 131 132 # TP number of RX channels 133 tp_nrxch = 0 # 0 (auto) = 1 134 135 # Percentage of dynamic memory (in either the EDRAM or external MEM) 136 # to use for TP TX payload 137 tp_pmtx = 50 138 139 # TP TX payload page size 140 tp_pmtx_pagesize = 64K 141 142 # TP number of TX channels 143 tp_ntxch = 0 # 0 (auto) = equal number of ports 144 145 # TP OFLD MTUs 146 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 147 148 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC 149 reg[0x7d04] = 0x00010008/0x00010008 150 151 # TP_GLOBAL_CONFIG 152 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 153 154 # TP_PC_CONFIG 155 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 156 157 # TP_PARA_REG0 158 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 159 160 # ULPRX iSCSI Page Sizes 161 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 162 163 # LE_DB_CONFIG 164 reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled 165 # LE IPv4 compression disabled 166 # LE_DB_HASH_CONFIG 167 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 168 169 # ULP_TX_CONFIG 170 reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err 171 # Enable more error msg for ... 172 # TPT error. 173 174 # ULP_RX_MISC_FEATURE_ENABLE 175 #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit 176 # Enable offset decrement after ... 177 # PI extraction and before DDP 178 # ulp insert pi source info in DIF 179 # iscsi_eff_offset_en 180 181 #Enable iscsi completion moderation feature 182 reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after 183 # PI extraction and before DDP. 184 # ulp insert pi source info in 185 # DIF. 186 # Enable iscsi hdr cmd mode. 187 # iscsi force cmd mode. 188 # Enable iscsi cmp mode. 189 # MC configuration 190 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC, 2: enable BRBC 191 192 # HMA configuration 193 hma_size = 92 # Size (in MBs) of host memory expected 194 hma_regions = stag,pbl,rq # What all regions to place in host memory 195 196# Some "definitions" to make the rest of this a bit more readable. We support 197# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 198# per function per port ... 199# 200# NMSIX = 1088 # available MSI-X Vectors 201# NVI = 256 # available Virtual Interfaces 202# NMPSTCAM = 336 # MPS TCAM entries 203# 204# NPORTS = 2 # ports 205# NCPUS = 16 # CPUs we want to support scalably 206# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 207 208# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 209# PF" which many OS Drivers will use to manage most or all functions. 210# 211# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 212# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 213# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 214# will be specified as the "Ingress Queue Asynchronous Destination Index." 215# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 216# than or equal to the number of Ingress Queues ... 217# 218# NVI_NIC = 4 # NIC access to NPORTS 219# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 220# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 221# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 222# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 223# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 224# 225# NVI_OFLD = 0 # Offload uses NIC function to access ports 226# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 227# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 228# NEQ_OFLD = 16 # Offload Egress Queues (FL) 229# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 230# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 231# 232# NVI_RDMA = 0 # RDMA uses NIC function to access ports 233# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 234# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 235# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 236# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 237# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 238# 239# NEQ_WD = 128 # Wire Direct TX Queues and FLs 240# NETHCTRL_WD = 64 # Wire Direct TX Queues 241# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 242# 243# NVI_ISCSI = 4 # ISCSI access to NPORTS 244# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 245# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 246# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 247# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 248# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 249# 250# NVI_FCOE = 4 # FCOE access to NPORTS 251# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 252# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 253# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 254# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 255# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 256 257# Two extra Ingress Queues per function for Firmware Events and Forwarded 258# Interrupts, and two extra interrupts per function for Firmware Events (or a 259# Forwarded Interrupt Queue) and General Interrupts per function. 260# 261# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 262# # Forwarded Interrupts 263# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 264# # General Interrupts 265 266# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 267# their interrupts forwarded to another set of Forwarded Interrupt Queues. 268# 269# NVI_HYPERV = 16 # VMs we want to support 270# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 271# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 272# NEQ_HYPERV = 32 # VIQs Free Lists 273# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 274# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 275 276# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 277# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 278# 279# NVI_UNIFIED = 28 280# NFLIQ_UNIFIED = 106 281# NETHCTRL_UNIFIED = 32 282# NEQ_UNIFIED = 124 283# NMPSTCAM_UNIFIED = 40 284# 285# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 286# that up to 128 to make sure the Unified PF doesn't run out of resources. 287# 288# NMSIX_UNIFIED = 128 289# 290# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 291# which is 34 but they're probably safe with 32. 292# 293# NMSIX_STORAGE = 32 294 295# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 296# associated with it. Thus, the MSI-X Vector allocations we give to the 297# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 298# provision many more Virtual Functions than we can if the UnifiedPF were 299# one of PF0-3. 300# 301 302# All of the below PCI-E parameters are actually stored in various *_init.txt 303# files. We include them below essentially as comments. 304# 305# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 306# ports 0-3. 307# 308# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 309# 310# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 311# storage applications across all four possible ports. 312# 313# Additionally, since the UnifiedPF isn't one of the per-port Physical 314# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 315# different PCI Device IDs which will allow Unified and Per-Port Drivers 316# to directly select the type of Physical Function to which they wish to be 317# attached. 318# 319# Note that the actual values used for the PCI-E Intelectual Property will be 320# 1 less than those below since that's the way it "counts" things. For 321# readability, we use the number we actually mean ... 322# 323# PF0_INT = 8 # NCPUS 324# PF1_INT = 8 # NCPUS 325# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 326# 327# PF4_INT = 128 # NMSIX_UNIFIED 328# PF5_INT = 32 # NMSIX_STORAGE 329# PF6_INT = 32 # NMSIX_STORAGE 330# PF7_INT = 0 # Nothing Assigned 331# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 332# 333# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 334# 335# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 336# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 337# 338# NVF = 16 339 340 341# For those OSes which manage different ports on different PFs, we need 342# only enough resources to support a single port's NIC application functions 343# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 344# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 345# managed on the "storage PFs" (see below). 346# 347[function "0"] 348 nvf = 16 # NVF on this function 349 wx_caps = all # write/execute permissions for all commands 350 r_caps = all # read permissions for all commands 351 nvi = 1 # 1 port 352 niqflint = 8 # NCPUS "Queue Sets" 353 nethctrl = 8 # NCPUS "Queue Sets" 354 neq = 16 # niqflint + nethctrl Egress Queues 355 nexactf = 8 # number of exact MPSTCAM MAC filters 356 cmask = all # access to all channels 357 pmask = 0x1 # access to only one port 358 359 360[function "1"] 361 nvf = 16 # NVF on this function 362 wx_caps = all # write/execute permissions for all commands 363 r_caps = all # read permissions for all commands 364 nvi = 1 # 1 port 365 niqflint = 8 # NCPUS "Queue Sets" 366 nethctrl = 8 # NCPUS "Queue Sets" 367 neq = 16 # niqflint + nethctrl Egress Queues 368 nexactf = 8 # number of exact MPSTCAM MAC filters 369 cmask = all # access to all channels 370 pmask = 0x2 # access to only one port 371 372[function "2"] 373 nvf = 16 # NVF on this function 374 wx_caps = all # write/execute permissions for all commands 375 r_caps = all # read permissions for all commands 376 nvi = 1 # 1 port 377 niqflint = 8 # NCPUS "Queue Sets" 378 nethctrl = 8 # NCPUS "Queue Sets" 379 neq = 16 # niqflint + nethctrl Egress Queues 380 nexactf = 8 # number of exact MPSTCAM MAC filters 381 cmask = all # access to all channels 382 pmask = 0x4 # access to only one port 383 384[function "3"] 385 nvf = 16 # NVF on this function 386 wx_caps = all # write/execute permissions for all commands 387 r_caps = all # read permissions for all commands 388 nvi = 1 # 1 port 389 niqflint = 8 # NCPUS "Queue Sets" 390 nethctrl = 8 # NCPUS "Queue Sets" 391 neq = 16 # niqflint + nethctrl Egress Queues 392 nexactf = 8 # number of exact MPSTCAM MAC filters 393 cmask = all # access to all channels 394 pmask = 0x8 # access to only one port 395 396 397# Some OS Drivers manage all application functions for all ports via PF4. 398# Thus we need to provide a large number of resources here. For Egress 399# Queues we need to account for both TX Queues as well as Free List Queues 400# (because the host is responsible for producing Free List Buffers for the 401# hardware to consume). 402# 403[function "4"] 404 wx_caps = all # write/execute permissions for all commands 405 r_caps = all # read permissions for all commands 406 nvi = 28 # NVI_UNIFIED 407 niqflint = 218 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32) 408 nethctrl = 116 # NETHCTRL_UNIFIED + NETHCTRL_WD + ncrypto_lookaside 409 neq = 256 # NEQ_UNIFIED + NEQ_WD 410 nqpcq = 12288 411 nexactf = 40 # NMPSTCAM_UNIFIED 412 nrawf = 2 413 cmask = all # access to all channels 414 pmask = all # access to all four ports ... 415 nethofld = 1024 # number of user mode ethernet flow contexts 416 ncrypto_lookaside = 16 # Number of lookaside flow contexts 417 nclip = 320 # number of clip region entries 418 nfilter = 496 # number of filter region entries 419 nserver = 496 # number of server region entries 420 nhash = 12288 # number of hash region entries 421 nhpfilter = 64 # number of high priority filter region entries 422 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, nic_hashfilter 423 tp_l2t = 3072 424 tp_ddp = 2 425 tp_ddp_iscsi = 2 426 tp_tls_key = 3 427 tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes 428 tp_stag = 2 429 tp_pbl = 5 430 tp_rq = 7 431 tp_srq = 128 432 433# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 434# need to have Virtual Interfaces on each of the four ports with up to NCPUS 435# "Queue Sets" each. 436# 437[function "5"] 438 wx_caps = all # write/execute permissions for all commands 439 r_caps = all # read permissions for all commands 440 nvi = 4 # NPORTS 441 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 442 nethctrl = 32 # NPORTS*NCPUS 443 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 444 nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 445 cmask = all # access to all channels 446 pmask = all # access to all four ports ... 447 nserver = 16 448 nhash = 2048 449 tp_l2t = 1020 450 nclip = 64 451 protocol = iscsi_initiator_fofld 452 tp_ddp_iscsi = 2 453 iscsi_ntask = 2048 454 iscsi_nsess = 2048 455 iscsi_nconn_per_session = 1 456 iscsi_ninitiator_instance = 64 457 458 459[function "6"] 460 wx_caps = all # write/execute permissions for all commands 461 r_caps = all # read permissions for all commands 462 nvi = 4 # NPORTS 463 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 464 nethctrl = 32 # NPORTS*NCPUS 465 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 466 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 467 # which is OK since < MIN(SUM PF0..3, PF4) 468 # and we never load PF0..3 and PF4 concurrently 469 cmask = all # access to all channels 470 pmask = all # access to all four ports ... 471 nhash = 2048 472 tp_l2t = 4 473 protocol = fcoe_initiator 474 tp_ddp = 2 475 fcoe_nfcf = 16 476 fcoe_nvnp = 32 477 fcoe_nssn = 1024 478 479 480# The following function, 1023, is not an actual PCIE function but is used to 481# configure and reserve firmware internal resources that come from the global 482# resource pool. 483# 484[function "1023"] 485 wx_caps = all # write/execute permissions for all commands 486 r_caps = all # read permissions for all commands 487 nvi = 4 # NVI_UNIFIED 488 cmask = all # access to all channels 489 pmask = all # access to all four ports ... 490 nexactf = 8 # NPORTS + DCBX + 491 nfilter = 16 # number of filter region entries 492 493 494# For Virtual functions, we only allow NIC functionality and we only allow 495# access to one port (1 << PF). Note that because of limitations in the 496# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 497# and GTS registers, the number of Ingress and Egress Queues must be a power 498# of 2. 499# 500[function "0/*"] # NVF 501 wx_caps = 0x82 # DMAQ | VF 502 r_caps = 0x86 # DMAQ | VF | PORT 503 nvi = 1 # 1 port 504 niqflint = 6 # 2 "Queue Sets" + NXIQ 505 nethctrl = 4 # 2 "Queue Sets" 506 neq = 8 # 2 "Queue Sets" * 2 507 nexactf = 4 508 cmask = all # access to all channels 509 pmask = 0x1 # access to only one port ... 510 511 512[function "1/*"] # NVF 513 wx_caps = 0x82 # DMAQ | VF 514 r_caps = 0x86 # DMAQ | VF | PORT 515 nvi = 1 # 1 port 516 niqflint = 6 # 2 "Queue Sets" + NXIQ 517 nethctrl = 4 # 2 "Queue Sets" 518 neq = 8 # 2 "Queue Sets" * 2 519 nexactf = 4 520 cmask = all # access to all channels 521 pmask = 0x2 # access to only one port ... 522 523[function "2/*"] # NVF 524 wx_caps = 0x82 # DMAQ | VF 525 r_caps = 0x86 # DMAQ | VF | PORT 526 nvi = 1 # 1 port 527 niqflint = 6 # 2 "Queue Sets" + NXIQ 528 nethctrl = 4 # 2 "Queue Sets" 529 neq = 8 # 2 "Queue Sets" * 2 530 nexactf = 4 531 cmask = all # access to all channels 532 pmask = 0x1 # access to only one port ... 533 534 535[function "3/*"] # NVF 536 wx_caps = 0x82 # DMAQ | VF 537 r_caps = 0x86 # DMAQ | VF | PORT 538 nvi = 1 # 1 port 539 niqflint = 6 # 2 "Queue Sets" + NXIQ 540 nethctrl = 4 # 2 "Queue Sets" 541 neq = 8 # 2 "Queue Sets" * 2 542 nexactf = 4 543 cmask = all # access to all channels 544 pmask = 0x2 # access to only one port ... 545 546# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 547# for packets from the wire as well as the loopback path of the L2 switch. The 548# folling params control how the buffer memory is distributed and the L2 flow 549# control settings: 550# 551# bg_mem: %-age of mem to use for port/buffer group 552# lpbk_mem: %-age of port/bg mem to use for loopback 553# hwm: high watermark; bytes available when starting to send pause 554# frames (in units of 0.1 MTU) 555# lwm: low watermark; bytes remaining when sending 'unpause' frame 556# (in inuits of 0.1 MTU) 557# dwm: minimum delta between high and low watermark (in units of 100 558# Bytes) 559# 560[port "0"] 561 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 562 #bg_mem = 25 563 #lpbk_mem = 25 564 hwm = 60 565 lwm = 15 566 dwm = 30 567 dcb_app_tlv[0] = 0x8906, ethertype, 3 568 dcb_app_tlv[1] = 0x8914, ethertype, 3 569 dcb_app_tlv[2] = 3260, socketnum, 5 570 571[port "1"] 572 dcb = ppp, dcbx 573 #bg_mem = 25 574 #lpbk_mem = 25 575 hwm = 60 576 lwm = 15 577 dwm = 30 578 dcb_app_tlv[0] = 0x8906, ethertype, 3 579 dcb_app_tlv[1] = 0x8914, ethertype, 3 580 dcb_app_tlv[2] = 3260, socketnum, 5 581 582[fini] 583 version = 0x1425001d 584 checksum = 0xdbff9437 585 586# Total resources used by above allocations: 587# Virtual Interfaces: 104 588# Ingress Queues/w Free Lists and Interrupts: 526 589# Egress Queues: 702 590# MPS TCAM Entries: 336 591# MSI-X Vectors: 736 592# Virtual Functions: 64 593# 594# $FreeBSD$ 595# 596