1# Chelsio T6 Factory Default configuration file. 2# 3# Copyright (C) 2014-2016 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7# TO ADAPTERS. 8 9 10# This file provides the default, power-on configuration for 2-port T6-based 11# adapters shipped from the factory. These defaults are designed to address 12# the needs of the vast majority of Terminator customers. The basic idea is to 13# have a default configuration which allows a customer to plug a Terminator 14# adapter in and have it work regardless of OS, driver or application except in 15# the most unusual and/or demanding customer applications. 16# 17# Many of the Terminator resources which are described by this configuration 18# are finite. This requires balancing the configuration/operation needs of 19# device drivers across OSes and a large number of customer application. 20# 21# Some of the more important resources to allocate and their constaints are: 22# 1. Virtual Interfaces: 256. 23# 2. Ingress Queues with Free Lists: 1024. 24# 3. Egress Queues: 128K. 25# 4. MSI-X Vectors: 1088. 26# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27# address matching on Ingress Packets. 28# 29# Some of the important OS/Driver resource needs are: 30# 6. Some OS Drivers will manage all resources through a single Physical 31# Function (currently PF4 but it could be any Physical Function). 32# 7. Some OS Drivers will manage different ports and functions (NIC, 33# storage, etc.) on different Physical Functions. For example, NIC 34# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc. 35# 36# Some of the customer application needs which need to be accommodated: 37# 8. Some customers will want to support large CPU count systems with 38# good scaling. Thus, we'll need to accommodate a number of 39# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40# to be involved per port and per application function. For example, 41# in the case where all ports and application functions will be 42# managed via a single Unified PF and we want to accommodate scaling up 43# to 8 CPUs, we would want: 44# 45# 2 ports * 46# 3 application functions (NIC, FCoE, iSCSI) per port * 47# 16 Ingress Queue/MSI-X Vectors per application function 48# 49# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50# (Plus a few for Firmware Event Queues, etc.) 51# 52# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54# and "PCI Device Passthrough" -- this is especially true for the NIC 55# application functionality. 56# 57 58 59# Global configuration settings. 60# 61[global] 62 rss_glb_config_mode = basicvirtual 63 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64 65 # PL_TIMEOUT register 66 pl_timeout_value = 200 # the timeout value in units of us 67 68 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69 # Page Size and a 64B L1 Cache Line Size. It programs the 70 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71 # If a Master PF Driver finds itself on a machine with different 72 # parameters, then the Master PF Driver is responsible for initializing 73 # these parameters to appropriate values. 74 # 75 # Notes: 76 # 1. The Free List Buffer Sizes below are raw and the firmware will 77 # round them up to the Ingress Padding Boundary. 78 # 2. The SGE Timer Values below are expressed below in microseconds. 79 # The firmware will convert these values to Core Clock Ticks when 80 # it processes the configuration parameters. 81 # 82 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94 95 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 96 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread 97 98 # enable TP_OUT_CONFIG.IPIDSPLITMODE 99 reg[0x7d04] = 0x00010000/0x00010000 100 101 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 102 103 #Tick granularities in kbps 104 tsch_ticks = 100000, 10000, 1000, 10 105 106 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 107 # filter control: compact, fcoemask 108 # server sram : srvrsram 109 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 110 # protocol, tos, vlan, vnic_id, port, fcoe 111 # valid filterModes are described the Terminator 5 Data Book 112 filterMode = srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 113 114 # filter tuples enforced in LE active region (equal to or subset of filterMode) 115 filterMask = protocol 116 117 # Percentage of dynamic memory (in either the EDRAM or external MEM) 118 # to use for TP RX payload 119 tp_pmrx = 30 120 121 # TP RX payload page size 122 tp_pmrx_pagesize = 64K 123 124 # TP number of RX channels 125 tp_nrxch = 0 # 0 (auto) = 1 126 127 # Percentage of dynamic memory (in either the EDRAM or external MEM) 128 # to use for TP TX payload 129 tp_pmtx = 50 130 131 # TP TX payload page size 132 tp_pmtx_pagesize = 64K 133 134 # TP number of TX channels 135 tp_ntxch = 0 # 0 (auto) = equal number of ports 136 137 # TP OFLD MTUs 138 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 139 140 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC 141 reg[0x7d04] = 0x00010008/0x00010008 142 143 # TP_GLOBAL_CONFIG 144 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 145 146 # TP_PC_CONFIG 147 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 148 149 # TP_PARA_REG0 150 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 151 152 # LE_DB_CONFIG 153 reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled 154 # LE IPv4 compression disabled 155 # LE_DB_HASH_CONFIG 156 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 157 158 # ULP_TX_CONFIG 159 reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err 160 # Enable more error msg for ... 161 # TPT error. 162 163 # ULP_RX_MISC_FEATURE_ENABLE 164 #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit 165 # Enable offset decrement after ... 166 # PI extraction and before DDP 167 # ulp insert pi source info in DIF 168 # iscsi_eff_offset_en 169 170 #Enable iscsi completion moderation feature 171 reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after 172 # PI extraction and before DDP. 173 # ulp insert pi source info in 174 # DIF. 175 # Enable iscsi hdr cmd mode. 176 # iscsi force cmd mode. 177 # Enable iscsi cmp mode. 178 # MC configuration 179 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 180 181# Some "definitions" to make the rest of this a bit more readable. We support 182# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 183# per function per port ... 184# 185# NMSIX = 1088 # available MSI-X Vectors 186# NVI = 256 # available Virtual Interfaces 187# NMPSTCAM = 336 # MPS TCAM entries 188# 189# NPORTS = 2 # ports 190# NCPUS = 16 # CPUs we want to support scalably 191# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 192 193# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 194# PF" which many OS Drivers will use to manage most or all functions. 195# 196# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 197# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 198# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 199# will be specified as the "Ingress Queue Asynchronous Destination Index." 200# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 201# than or equal to the number of Ingress Queues ... 202# 203# NVI_NIC = 4 # NIC access to NPORTS 204# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 205# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 206# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 207# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 208# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 209# 210# NVI_OFLD = 0 # Offload uses NIC function to access ports 211# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 212# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 213# NEQ_OFLD = 16 # Offload Egress Queues (FL) 214# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 215# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 216# 217# NVI_RDMA = 0 # RDMA uses NIC function to access ports 218# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 219# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 220# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 221# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 222# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 223# 224# NEQ_WD = 128 # Wire Direct TX Queues and FLs 225# NETHCTRL_WD = 64 # Wire Direct TX Queues 226# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 227# 228# NVI_ISCSI = 4 # ISCSI access to NPORTS 229# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 230# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 231# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 232# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 233# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 234# 235# NVI_FCOE = 4 # FCOE access to NPORTS 236# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 237# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 238# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 239# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 240# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 241 242# Two extra Ingress Queues per function for Firmware Events and Forwarded 243# Interrupts, and two extra interrupts per function for Firmware Events (or a 244# Forwarded Interrupt Queue) and General Interrupts per function. 245# 246# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 247# # Forwarded Interrupts 248# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 249# # General Interrupts 250 251# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 252# their interrupts forwarded to another set of Forwarded Interrupt Queues. 253# 254# NVI_HYPERV = 16 # VMs we want to support 255# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 256# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 257# NEQ_HYPERV = 32 # VIQs Free Lists 258# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 259# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 260 261# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 262# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 263# 264# NVI_UNIFIED = 28 265# NFLIQ_UNIFIED = 106 266# NETHCTRL_UNIFIED = 32 267# NEQ_UNIFIED = 124 268# NMPSTCAM_UNIFIED = 40 269# 270# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 271# that up to 128 to make sure the Unified PF doesn't run out of resources. 272# 273# NMSIX_UNIFIED = 128 274# 275# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 276# which is 34 but they're probably safe with 32. 277# 278# NMSIX_STORAGE = 32 279 280# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 281# associated with it. Thus, the MSI-X Vector allocations we give to the 282# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 283# provision many more Virtual Functions than we can if the UnifiedPF were 284# one of PF0-3. 285# 286 287# All of the below PCI-E parameters are actually stored in various *_init.txt 288# files. We include them below essentially as comments. 289# 290# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 291# ports 0-3. 292# 293# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 294# 295# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 296# storage applications across all four possible ports. 297# 298# Additionally, since the UnifiedPF isn't one of the per-port Physical 299# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 300# different PCI Device IDs which will allow Unified and Per-Port Drivers 301# to directly select the type of Physical Function to which they wish to be 302# attached. 303# 304# Note that the actual values used for the PCI-E Intelectual Property will be 305# 1 less than those below since that's the way it "counts" things. For 306# readability, we use the number we actually mean ... 307# 308# PF0_INT = 8 # NCPUS 309# PF1_INT = 8 # NCPUS 310# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 311# 312# PF4_INT = 128 # NMSIX_UNIFIED 313# PF5_INT = 32 # NMSIX_STORAGE 314# PF6_INT = 32 # NMSIX_STORAGE 315# PF7_INT = 0 # Nothing Assigned 316# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 317# 318# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 319# 320# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 321# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 322# 323# NVF = 16 324 325 326# For those OSes which manage different ports on different PFs, we need 327# only enough resources to support a single port's NIC application functions 328# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 329# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 330# managed on the "storage PFs" (see below). 331# 332[function "0"] 333 nvf = 16 # NVF on this function 334 wx_caps = all # write/execute permissions for all commands 335 r_caps = all # read permissions for all commands 336 nvi = 1 # 1 port 337 niqflint = 8 # NCPUS "Queue Sets" 338 nethctrl = 8 # NCPUS "Queue Sets" 339 neq = 16 # niqflint + nethctrl Egress Queues 340 nexactf = 8 # number of exact MPSTCAM MAC filters 341 cmask = all # access to all channels 342 pmask = 0x1 # access to only one port 343 344 345[function "1"] 346 nvf = 16 # NVF on this function 347 wx_caps = all # write/execute permissions for all commands 348 r_caps = all # read permissions for all commands 349 nvi = 1 # 1 port 350 niqflint = 8 # NCPUS "Queue Sets" 351 nethctrl = 8 # NCPUS "Queue Sets" 352 neq = 16 # niqflint + nethctrl Egress Queues 353 nexactf = 8 # number of exact MPSTCAM MAC filters 354 cmask = all # access to all channels 355 pmask = 0x2 # access to only one port 356 357[function "2"] 358 nvf = 16 # NVF on this function 359 wx_caps = all # write/execute permissions for all commands 360 r_caps = all # read permissions for all commands 361 nvi = 1 # 1 port 362 niqflint = 8 # NCPUS "Queue Sets" 363 nethctrl = 8 # NCPUS "Queue Sets" 364 neq = 16 # niqflint + nethctrl Egress Queues 365 nexactf = 8 # number of exact MPSTCAM MAC filters 366 cmask = all # access to all channels 367 pmask = 0x4 # access to only one port 368 369[function "3"] 370 nvf = 16 # NVF on this function 371 wx_caps = all # write/execute permissions for all commands 372 r_caps = all # read permissions for all commands 373 nvi = 1 # 1 port 374 niqflint = 8 # NCPUS "Queue Sets" 375 nethctrl = 8 # NCPUS "Queue Sets" 376 neq = 16 # niqflint + nethctrl Egress Queues 377 nexactf = 8 # number of exact MPSTCAM MAC filters 378 cmask = all # access to all channels 379 pmask = 0x8 # access to only one port 380 381 382# Some OS Drivers manage all application functions for all ports via PF4. 383# Thus we need to provide a large number of resources here. For Egress 384# Queues we need to account for both TX Queues as well as Free List Queues 385# (because the host is responsible for producing Free List Buffers for the 386# hardware to consume). 387# 388[function "4"] 389 wx_caps = all # write/execute permissions for all commands 390 r_caps = all # read permissions for all commands 391 nvi = 28 # NVI_UNIFIED 392 niqflint = 202 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32) 393 nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 394 neq = 256 # NEQ_UNIFIED + NEQ_WD 395 nqpcq = 12288 396 nexactf = 40 # NMPSTCAM_UNIFIED 397 nrawf = 2 398 cmask = all # access to all channels 399 pmask = all # access to all four ports ... 400 nethofld = 1024 # number of user mode ethernet flow contexts 401 ncrypto_lookaside = 16 # Number of lookaside flow contexts 402 nclip = 320 # number of clip region entries 403 nfilter = 496 # number of filter region entries 404 nserver = 496 # number of server region entries 405 nhash = 12288 # number of hash region entries 406 nhpfilter = 0 # number of high priority filter region entries 407 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside 408 tp_l2t = 3072 409 tp_ddp = 2 410 tp_ddp_iscsi = 2 411 tp_tls_key = 3 412 tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes 413 tp_stag = 2 414 tp_pbl = 5 415 tp_rq = 7 416 tp_srq = 128 417 418# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 419# need to have Virtual Interfaces on each of the four ports with up to NCPUS 420# "Queue Sets" each. 421# 422[function "5"] 423 wx_caps = all # write/execute permissions for all commands 424 r_caps = all # read permissions for all commands 425 nvi = 4 # NPORTS 426 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 427 nethctrl = 32 # NPORTS*NCPUS 428 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 429 nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 430 cmask = all # access to all channels 431 pmask = all # access to all four ports ... 432 nserver = 16 433 nhash = 2048 434 tp_l2t = 1020 435 nclip = 64 436 protocol = iscsi_initiator_fofld 437 tp_ddp_iscsi = 2 438 iscsi_ntask = 2048 439 iscsi_nsess = 2048 440 iscsi_nconn_per_session = 1 441 iscsi_ninitiator_instance = 64 442 443 444[function "6"] 445 wx_caps = all # write/execute permissions for all commands 446 r_caps = all # read permissions for all commands 447 nvi = 4 # NPORTS 448 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 449 nethctrl = 32 # NPORTS*NCPUS 450 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 451 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 452 # which is OK since < MIN(SUM PF0..3, PF4) 453 # and we never load PF0..3 and PF4 concurrently 454 cmask = all # access to all channels 455 pmask = all # access to all four ports ... 456 nhash = 2048 457 tp_l2t = 4 458 protocol = fcoe_initiator 459 tp_ddp = 2 460 fcoe_nfcf = 16 461 fcoe_nvnp = 32 462 fcoe_nssn = 1024 463 464 465# The following function, 1023, is not an actual PCIE function but is used to 466# configure and reserve firmware internal resources that come from the global 467# resource pool. 468# 469[function "1023"] 470 wx_caps = all # write/execute permissions for all commands 471 r_caps = all # read permissions for all commands 472 nvi = 4 # NVI_UNIFIED 473 cmask = all # access to all channels 474 pmask = all # access to all four ports ... 475 nexactf = 8 # NPORTS + DCBX + 476 nfilter = 16 # number of filter region entries 477 478 479# For Virtual functions, we only allow NIC functionality and we only allow 480# access to one port (1 << PF). Note that because of limitations in the 481# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 482# and GTS registers, the number of Ingress and Egress Queues must be a power 483# of 2. 484# 485[function "0/*"] # NVF 486 wx_caps = 0x82 # DMAQ | VF 487 r_caps = 0x86 # DMAQ | VF | PORT 488 nvi = 1 # 1 port 489 niqflint = 4 # 2 "Queue Sets" + NXIQ 490 nethctrl = 2 # 2 "Queue Sets" 491 neq = 4 # 2 "Queue Sets" * 2 492 nexactf = 4 493 cmask = all # access to all channels 494 pmask = 0x1 # access to only one port ... 495 496 497[function "1/*"] # NVF 498 wx_caps = 0x82 # DMAQ | VF 499 r_caps = 0x86 # DMAQ | VF | PORT 500 nvi = 1 # 1 port 501 niqflint = 4 # 2 "Queue Sets" + NXIQ 502 nethctrl = 2 # 2 "Queue Sets" 503 neq = 4 # 2 "Queue Sets" * 2 504 nexactf = 4 505 cmask = all # access to all channels 506 pmask = 0x2 # access to only one port ... 507 508[function "2/*"] # NVF 509 wx_caps = 0x82 # DMAQ | VF 510 r_caps = 0x86 # DMAQ | VF | PORT 511 nvi = 1 # 1 port 512 niqflint = 4 # 2 "Queue Sets" + NXIQ 513 nethctrl = 2 # 2 "Queue Sets" 514 neq = 4 # 2 "Queue Sets" * 2 515 nexactf = 4 516 cmask = all # access to all channels 517 pmask = 0x1 # access to only one port ... 518 519 520[function "3/*"] # NVF 521 wx_caps = 0x82 # DMAQ | VF 522 r_caps = 0x86 # DMAQ | VF | PORT 523 nvi = 1 # 1 port 524 niqflint = 4 # 2 "Queue Sets" + NXIQ 525 nethctrl = 2 # 2 "Queue Sets" 526 neq = 4 # 2 "Queue Sets" * 2 527 nexactf = 4 528 cmask = all # access to all channels 529 pmask = 0x2 # access to only one port ... 530 531# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 532# for packets from the wire as well as the loopback path of the L2 switch. The 533# folling params control how the buffer memory is distributed and the L2 flow 534# control settings: 535# 536# bg_mem: %-age of mem to use for port/buffer group 537# lpbk_mem: %-age of port/bg mem to use for loopback 538# hwm: high watermark; bytes available when starting to send pause 539# frames (in units of 0.1 MTU) 540# lwm: low watermark; bytes remaining when sending 'unpause' frame 541# (in inuits of 0.1 MTU) 542# dwm: minimum delta between high and low watermark (in units of 100 543# Bytes) 544# 545[port "0"] 546 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 547 #bg_mem = 25 548 #lpbk_mem = 25 549 hwm = 60 550 lwm = 15 551 dwm = 30 552 dcb_app_tlv[0] = 0x8906, ethertype, 3 553 dcb_app_tlv[1] = 0x8914, ethertype, 3 554 dcb_app_tlv[2] = 3260, socketnum, 5 555 #aec_retry_cnt = 4 556 flags = an_dis 557 558 559[port "1"] 560 dcb = ppp, dcbx 561 #bg_mem = 25 562 #lpbk_mem = 25 563 hwm = 60 564 lwm = 15 565 dwm = 30 566 dcb_app_tlv[0] = 0x8906, ethertype, 3 567 dcb_app_tlv[1] = 0x8914, ethertype, 3 568 dcb_app_tlv[2] = 3260, socketnum, 5 569 #aec_retry_cnt = 4 570 flags = an_dis 571 572 573[fini] 574 version = 0x01000025 575 checksum = 0xb23e8983 576 577# Total resources used by above allocations: 578# Virtual Interfaces: 104 579# Ingress Queues/w Free Lists and Interrupts: 526 580# Egress Queues: 702 581# MPS TCAM Entries: 336 582# MSI-X Vectors: 736 583# Virtual Functions: 64 584# 585# $FreeBSD$ 586# 587