1# Firmware configuration file. 2# 3# Global limits (some are hardware limits, others are due to the firmware). 4# nvi = 128 virtual interfaces 5# niqflint = 1023 ingress queues with freelists and/or interrupts 6# nethctrl = 64K Ethernet or ctrl egress queues 7# neq = 64K egress queues of all kinds, including freelists 8# nexactf = 512 MPS TCAM entries, can oversubscribe. 9 10[global] 11 rss_glb_config_mode = basicvirtual 12 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 13 14 # PL_TIMEOUT register 15 pl_timeout_value = 200 # the timeout value in units of us 16 17 sge_timer_value = 1, 5, 10, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 18 19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread 20 21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 22 23 #Tick granularities in kbps 24 tsch_ticks = 100000, 10000, 1000, 10 25 26 filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe 27 filterMask = protocol 28 29 tp_pmrx = 36, 512 30 tp_pmrx_pagesize = 64K 31 32 # TP number of RX channels (0 = auto) 33 tp_nrxch = 0 34 35 tp_pmtx = 46, 512 36 tp_pmtx_pagesize = 64K 37 38 # TP number of TX channels (0 = auto) 39 tp_ntxch = 0 40 41 # TP OFLD MTUs 42 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 43 44 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC 45 reg[0x7d04] = 0x00010008/0x00010008 46 47 # TP_GLOBAL_CONFIG 48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 49 50 # TP_PC_CONFIG 51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 52 53 # TP_PARA_REG0 54 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 55 56 # cluster, lan, or wan. 57 tp_tcptuning = lan 58 59 # LE_DB_CONFIG 60 reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled 61 # LE IPv4 compression disabled 62 # LE_DB_HASH_CONFIG 63 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 64 65 # ULP_TX_CONFIG 66 reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err 67 # Enable more error msg for ... 68 # TPT error. 69 70 # ULP_RX_MISC_FEATURE_ENABLE 71 #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit 72 # Enable offset decrement after ... 73 # PI extraction and before DDP 74 # ulp insert pi source info in DIF 75 # iscsi_eff_offset_en 76 77 #Enable iscsi completion moderation feature 78 reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after 79 # PI extraction and before DDP. 80 # ulp insert pi source info in 81 # DIF. 82 # Enable iscsi hdr cmd mode. 83 # iscsi force cmd mode. 84 # Enable iscsi cmp mode. 85 # MC configuration 86 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 87 88# PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by 89# these 4 PFs only. 90[function "0"] 91 wx_caps = all 92 r_caps = all 93 nvi = 1 94 rssnvi = 0 95 niqflint = 2 96 nethctrl = 2 97 neq = 4 98 nexactf = 2 99 cmask = all 100 pmask = 0x1 101 102[function "1"] 103 wx_caps = all 104 r_caps = all 105 nvi = 1 106 rssnvi = 0 107 niqflint = 2 108 nethctrl = 2 109 neq = 4 110 nexactf = 2 111 cmask = all 112 pmask = 0x2 113 114[function "2"] 115 wx_caps = all 116 r_caps = all 117 nvi = 1 118 rssnvi = 0 119 niqflint = 2 120 nethctrl = 2 121 neq = 4 122 nexactf = 2 123 cmask = all 124 pmask = 0x4 125 126[function "3"] 127 wx_caps = all 128 r_caps = all 129 nvi = 1 130 rssnvi = 0 131 niqflint = 2 132 nethctrl = 2 133 neq = 4 134 nexactf = 2 135 cmask = all 136 pmask = 0x8 137 138# PF4 is the resource-rich PF that the bus/nexus driver attaches to. 139# It gets 32 MSI/128 MSI-X vectors. 140[function "4"] 141 wx_caps = all 142 r_caps = all 143 nvi = 32 144 rssnvi = 32 145 niqflint = 512 146 nethctrl = 1024 147 neq = 2048 148 nqpcq = 8192 149 nexactf = 456 150 cmask = all 151 pmask = all 152 ncrypto_lookaside = 16 153 nclip = 320 154 nethofld = 8192 155 156 # TCAM has 6K cells; each region must start at a multiple of 128 cell. 157 # Each entry in these categories takes 2 cells each. nhash will use the 158 # TCAM iff there is room left (that is, the rest don't add up to 3072). 159 nfilter = 2032 160 nserver = 512 161 nhpfilter = 0 162 nhash = 16384 163 protocol = ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside 164 tp_l2t = 4096 165 tp_ddp = 2 166 tp_ddp_iscsi = 2 167 tp_tls_key = 3 168 tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes 169 tp_stag = 2 170 tp_pbl = 5 171 tp_rq = 7 172 tp_srq = 128 173 174# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors. 175# Not used right now. 176[function "5"] 177 nvi = 1 178 rssnvi = 0 179 180# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors. 181# Not used right now. 182[function "6"] 183 nvi = 1 184 rssnvi = 0 185 186# The following function, 1023, is not an actual PCIE function but is used to 187# configure and reserve firmware internal resources that come from the global 188# resource pool. 189# 190[function "1023"] 191 wx_caps = all 192 r_caps = all 193 nvi = 4 194 rssnvi = 0 195 cmask = all 196 pmask = all 197 nexactf = 8 198 nfilter = 16 199 200 201# For Virtual functions, we only allow NIC functionality and we only allow 202# access to one port (1 << PF). Note that because of limitations in the 203# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 204# and GTS registers, the number of Ingress and Egress Queues must be a power 205# of 2. 206# 207[function "0/*"] 208 wx_caps = 0x82 209 r_caps = 0x86 210 nvi = 1 211 rssnvi = 0 212 niqflint = 2 213 nethctrl = 2 214 neq = 4 215 nexactf = 2 216 cmask = all 217 pmask = 0x1 218 219[function "1/*"] 220 wx_caps = 0x82 221 r_caps = 0x86 222 nvi = 1 223 rssnvi = 0 224 niqflint = 2 225 nethctrl = 2 226 neq = 4 227 nexactf = 2 228 cmask = all 229 pmask = 0x2 230 231[function "2/*"] 232 wx_caps = 0x82 233 r_caps = 0x86 234 nvi = 1 235 rssnvi = 0 236 niqflint = 2 237 nethctrl = 2 238 neq = 4 239 nexactf = 2 240 cmask = all 241 pmask = 0x1 242 243[function "3/*"] 244 wx_caps = 0x82 245 r_caps = 0x86 246 nvi = 1 247 rssnvi = 0 248 niqflint = 2 249 nethctrl = 2 250 neq = 4 251 nexactf = 2 252 cmask = all 253 pmask = 0x2 254 255# MPS has 192K buffer space for ingress packets from the wire as well as 256# loopback path of the L2 switch. 257[port "0"] 258 dcb = none 259 #bg_mem = 25 260 #lpbk_mem = 25 261 hwm = 60 262 lwm = 15 263 dwm = 30 264 265[port "1"] 266 dcb = none 267 #bg_mem = 25 268 #lpbk_mem = 25 269 hwm = 60 270 lwm = 15 271 dwm = 30 272 273[fini] 274 version = 0x1 275 checksum = 0x4528a6ac 276# 277# $FreeBSD$ 278# 279