1# Firmware configuration file. 2# 3# Global limits (some are hardware limits, others are due to the firmware). 4# nvi = 128 virtual interfaces 5# niqflint = 1023 ingress queues with freelists and/or interrupts 6# nethctrl = 64K Ethernet or ctrl egress queues 7# neq = 64K egress queues of all kinds, including freelists 8# nexactf = 512 MPS TCAM entries, can oversubscribe. 9 10[global] 11 rss_glb_config_mode = basicvirtual 12 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 13 14 # PL_TIMEOUT register 15 pl_timeout_value = 200 # the timeout value in units of us 16 17 sge_timer_value = 1, 5, 10, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 18 19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread 20 21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 22 23 #Tick granularities in kbps 24 tsch_ticks = 100000, 10000, 1000, 10 25 26 filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe 27 filterMask = protocol 28 29 tp_pmrx = 36, 512 30 tp_pmrx_pagesize = 64K 31 32 # TP number of RX channels (0 = auto) 33 tp_nrxch = 0 34 35 tp_pmtx = 46, 512 36 tp_pmtx_pagesize = 64K 37 38 # TP number of TX channels (0 = auto) 39 tp_ntxch = 0 40 41 # TP OFLD MTUs 42 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 43 44 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC 45 reg[0x7d04] = 0x00010008/0x00010008 46 47 # TP_GLOBAL_CONFIG 48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 49 50 # TP_PC_CONFIG 51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 52 53 # TP_PARA_REG0 54 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 55 56 # cluster, lan, or wan. 57 tp_tcptuning = lan 58 59 # LE_DB_CONFIG 60 reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled 61 # LE IPv4 compression disabled 62 # LE_DB_HASH_CONFIG 63 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 64 65 # ULP_TX_CONFIG 66 reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err 67 # Enable more error msg for ... 68 # TPT error. 69 70 # ULP_RX_MISC_FEATURE_ENABLE 71 #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit 72 # Enable offset decrement after ... 73 # PI extraction and before DDP 74 # ulp insert pi source info in DIF 75 # iscsi_eff_offset_en 76 77 #Enable iscsi completion moderation feature 78 reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after 79 # PI extraction and before DDP. 80 # ulp insert pi source info in 81 # DIF. 82 # Enable iscsi hdr cmd mode. 83 # iscsi force cmd mode. 84 # Enable iscsi cmp mode. 85 # MC configuration 86 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 87 88# PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by 89# these 4 PFs only. 90[function "0"] 91 nvf = 4 92 wx_caps = all 93 r_caps = all 94 nvi = 2 95 rssnvi = 2 96 niqflint = 4 97 nethctrl = 4 98 neq = 8 99 nexactf = 4 100 cmask = all 101 pmask = 0x1 102 103[function "1"] 104 nvf = 4 105 wx_caps = all 106 r_caps = all 107 nvi = 2 108 rssnvi = 2 109 niqflint = 4 110 nethctrl = 4 111 neq = 8 112 nexactf = 4 113 cmask = all 114 pmask = 0x2 115 116[function "2"] 117 nvf = 4 118 wx_caps = all 119 r_caps = all 120 nvi = 2 121 rssnvi = 2 122 niqflint = 4 123 nethctrl = 4 124 neq = 8 125 nexactf = 4 126 cmask = all 127 pmask = 0x4 128 129[function "3"] 130 nvf = 4 131 wx_caps = all 132 r_caps = all 133 nvi = 2 134 rssnvi = 2 135 niqflint = 4 136 nethctrl = 4 137 neq = 8 138 nexactf = 4 139 cmask = all 140 pmask = 0x8 141 142# PF4 is the resource-rich PF that the bus/nexus driver attaches to. 143# It gets 32 MSI/128 MSI-X vectors. 144[function "4"] 145 wx_caps = all 146 r_caps = all 147 nvi = 32 148 rssnvi = 8 149 niqflint = 512 150 nethctrl = 1024 151 neq = 2048 152 nqpcq = 8192 153 nexactf = 456 154 cmask = all 155 pmask = all 156 ncrypto_lookaside = 16 157 nclip = 320 158 nethofld = 8192 159 160 # TCAM has 6K cells; each region must start at a multiple of 128 cell. 161 # Each entry in these categories takes 2 cells each. nhash will use the 162 # TCAM iff there is room left (that is, the rest don't add up to 3072). 163 nfilter = 2032 164 nserver = 512 165 nhpfilter = 0 166 nhash = 16384 167 protocol = ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside 168 tp_l2t = 4096 169 tp_ddp = 2 170 tp_ddp_iscsi = 2 171 tp_tls_key = 3 172 tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes 173 tp_stag = 2 174 tp_pbl = 5 175 tp_rq = 7 176 tp_srq = 128 177 178# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors. 179# Not used right now. 180[function "5"] 181 nvi = 1 182 rssnvi = 0 183 184# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors. 185# Not used right now. 186[function "6"] 187 nvi = 1 188 rssnvi = 0 189 190# The following function, 1023, is not an actual PCIE function but is used to 191# configure and reserve firmware internal resources that come from the global 192# resource pool. 193# 194[function "1023"] 195 wx_caps = all 196 r_caps = all 197 nvi = 4 198 rssnvi = 0 199 cmask = all 200 pmask = all 201 nexactf = 8 202 nfilter = 16 203 204 205# For Virtual functions, we only allow NIC functionality and we only allow 206# access to one port (1 << PF). Note that because of limitations in the 207# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 208# and GTS registers, the number of Ingress and Egress Queues must be a power 209# of 2. 210# 211[function "0/*"] 212 wx_caps = 0x82 213 r_caps = 0x86 214 nvi = 1 215 rssnvi = 1 216 niqflint = 2 217 nethctrl = 2 218 neq = 4 219 nexactf = 2 220 cmask = all 221 pmask = 0x1 222 223[function "1/*"] 224 wx_caps = 0x82 225 r_caps = 0x86 226 nvi = 1 227 rssnvi = 1 228 niqflint = 2 229 nethctrl = 2 230 neq = 4 231 nexactf = 2 232 cmask = all 233 pmask = 0x2 234 235[function "2/*"] 236 wx_caps = 0x82 237 r_caps = 0x86 238 nvi = 1 239 rssnvi = 1 240 niqflint = 2 241 nethctrl = 2 242 neq = 4 243 nexactf = 2 244 cmask = all 245 pmask = 0x1 246 247[function "3/*"] 248 wx_caps = 0x82 249 r_caps = 0x86 250 nvi = 1 251 rssnvi = 1 252 niqflint = 2 253 nethctrl = 2 254 neq = 4 255 nexactf = 2 256 cmask = all 257 pmask = 0x2 258 259# MPS has 192K buffer space for ingress packets from the wire as well as 260# loopback path of the L2 switch. 261[port "0"] 262 dcb = none 263 #bg_mem = 25 264 #lpbk_mem = 25 265 hwm = 60 266 lwm = 15 267 dwm = 30 268 269[port "1"] 270 dcb = none 271 #bg_mem = 25 272 #lpbk_mem = 25 273 hwm = 60 274 lwm = 15 275 dwm = 30 276 277[fini] 278 version = 0x1 279 checksum = 0xf3e93001 280# 281# $FreeBSD$ 282# 283