1# Chelsio T5 Factory Default configuration file. 2# 3# Copyright (C) 2010-2014 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF 6# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT 7# IN PHYSICAL DAMAGE TO T4 ADAPTERS. 8 9# This file provides the default, power-on configuration for 4-port T4-based 10# adapters shipped from the factory. These defaults are designed to address 11# the needs of the vast majority of T4 customers. The basic idea is to have 12# a default configuration which allows a customer to plug a T4 adapter in and 13# have it work regardless of OS, driver or application except in the most 14# unusual and/or demanding customer applications. 15# 16# Many of the T4 resources which are described by this configuration are 17# finite. This requires balancing the configuration/operation needs of 18# device drivers across OSes and a large number of customer application. 19# 20# Some of the more important resources to allocate and their constaints are: 21# 1. Virtual Interfaces: 128. 22# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions 23# must use a power of 2 Ingress Queues. 24# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a 25# power of 2 Egress Queues. 26# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV 27# Virtual Functions based off of a Physical Function all get the 28# same umber of MSI-X Vectors as the base Physical Function. 29# Additionally, regardless of whether Virtual Functions are enabled or 30# not, their MSI-X "needs" are counted by the PCI-E implementation. 31# And finally, all Physical Funcations capable of supporting Virtual 32# Functions (PF0-3) must have the same number of configured TotalVFs in 33# their SR-IOV Capabilities. 34# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 35# address matching on Ingress Packets. 36# 37# Some of the important OS/Driver resource needs are: 38# 6. Some OS Drivers will manage all resources through a single Physical 39# Function (currently PF0 but it could be any Physical Function). Thus, 40# this "Unified PF" will need to have enough resources allocated to it 41# to allow for this. And because of the MSI-X resource allocation 42# constraints mentioned above, this probably means we'll either have to 43# severely limit the TotalVFs if we continue to use PF0 as the Unified PF 44# or we'll need to move the Unified PF into the PF4-7 range since those 45# Physical Functions don't have any Virtual Functions associated with 46# them. 47# 7. Some OS Drivers will manage different ports and functions (NIC, 48# storage, etc.) on different Physical Functions. For example, NIC 49# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. 50# 51# Some of the customer application needs which need to be accommodated: 52# 8. Some customers will want to support large CPU count systems with 53# good scaling. Thus, we'll need to accommodate a number of 54# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 55# to be involved per port and per application function. For example, 56# in the case where all ports and application functions will be 57# managed via a single Unified PF and we want to accommodate scaling up 58# to 8 CPUs, we would want: 59# 60# 4 ports * 61# 3 application functions (NIC, FCoE, iSCSI) per port * 62# 8 Ingress Queue/MSI-X Vectors per application function 63# 64# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 65# (Plus a few for Firmware Event Queues, etc.) 66# 67# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow 68# Virtual Machines to directly access T4 functionality via SR-IOV 69# Virtual Functions and "PCI Device Passthrough" -- this is especially 70# true for the NIC application functionality. (Note that there is 71# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual 72# Functions so this is in fact solely limited to NIC.) 73# 74 75 76# Global configuration settings. 77# 78[global] 79 rss_glb_config_mode = basicvirtual 80 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 81 82 # PL_TIMEOUT register 83 pl_timeout_value = 200 # the timeout value in units of us 84 85 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 86 # Page Size and a 64B L1 Cache Line Size. It programs the 87 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 88 # If a Master PF Driver finds itself on a machine with different 89 # parameters, then the Master PF Driver is responsible for initializing 90 # these parameters to appropriate values. 91 # 92 # Notes: 93 # 1. The Free List Buffer Sizes below are raw and the firmware will 94 # round them up to the Ingress Padding Boundary. 95 # 2. The SGE Timer Values below are expressed below in microseconds. 96 # The firmware will convert these values to Core Clock Ticks when 97 # it processes the configuration parameters. 98 # 99 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 100 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 101 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 102 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 103 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 104 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 105 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 106 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 107 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 108 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 109 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 110 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 111 reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 112 reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL 113 114 # SGE_THROTTLE_CONTROL 115 bar2throttlecount = 500 # bar2throttlecount in us 116 117 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 118 119 120 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if 121 # SGE_VFIFO_SIZE is not set, then 122 # firmware will set it up in function 123 # of number of egress queues used 124 125 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch 126 # threshold set to queue depth 127 # minus 128-entries for FL and HP 128 # queues, and 0xfff for LP which 129 # prompts the firmware to set it up 130 # in function of egress queues 131 # used 132 133 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which 134 # prompts the firmware to set it up in 135 # function of number of egress queues 136 # used 137 138 # enable TP_OUT_CONFIG.IPIDSPLITMODE 139 reg[0x7d04] = 0x00010000/0x00010000 140 141 reg[0x7dc0] = 0x062f8849 # TP_SHIFT_CNT 142 143 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 144 # filter control: compact, fcoemask 145 # server sram : srvrsram 146 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 147 # protocol, tos, vlan, vnic_id, port, fcoe 148 # valid filterModes are described the Terminator 5 Data Book 149 filterMode = srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 150 151 # filter tuples enforced in LE active region (equal to or subset of filterMode) 152 filterMask = protocol, fcoe 153 154 # Percentage of dynamic memory (in either the EDRAM or external MEM) 155 # to use for TP RX payload 156 tp_pmrx = 30, 512 157 158 # TP RX payload page size 159 tp_pmrx_pagesize = 64K 160 161 # TP number of RX channels 162 tp_nrxch = 0 # 0 (auto) = 1 163 164 # Percentage of dynamic memory (in either the EDRAM or external MEM) 165 # to use for TP TX payload 166 tp_pmtx = 50, 512 167 168 # TP TX payload page size 169 tp_pmtx_pagesize = 64K 170 171 # TP number of TX channels 172 tp_ntxch = 0 # 0 (auto) = equal number of ports 173 174 # TP OFLD MTUs 175 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 176 177 # TP_GLOBAL_CONFIG 178 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 179 180 # TP_PC_CONFIG 181 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 182 183 # TP_PARA_REG0 184 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 185 186 # LE_DB_CONFIG 187 reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable 188 189 # MC configuration 190 mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 191 mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC 192 193# Some "definitions" to make the rest of this a bit more readable. We support 194# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 195# per function per port ... 196# 197# NMSIX = 1088 # available MSI-X Vectors 198# NVI = 128 # available Virtual Interfaces 199# NMPSTCAM = 336 # MPS TCAM entries 200# 201# NPORTS = 4 # ports 202# NCPUS = 8 # CPUs we want to support scalably 203# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 204 205# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 206# PF" which many OS Drivers will use to manage most or all functions. 207# 208# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 209# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 210# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 211# will be specified as the "Ingress Queue Asynchronous Destination Index." 212# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 213# than or equal to the number of Ingress Queues ... 214# 215# NVI_NIC = 4 # NIC access to NPORTS 216# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 217# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 218# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 219# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 220# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 221# 222# NVI_OFLD = 0 # Offload uses NIC function to access ports 223# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 224# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 225# NEQ_OFLD = 16 # Offload Egress Queues (FL) 226# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 227# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 228# 229# NVI_RDMA = 0 # RDMA uses NIC function to access ports 230# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 231# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 232# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 233# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 234# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 235# 236# NEQ_WD = 128 # Wire Direct TX Queues and FLs 237# NETHCTRL_WD = 64 # Wire Direct TX Queues 238# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 239# 240# NVI_ISCSI = 4 # ISCSI access to NPORTS 241# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 242# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 243# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 244# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 245# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 246# 247# NVI_FCOE = 4 # FCOE access to NPORTS 248# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 249# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 250# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 251# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 252# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 253 254# Two extra Ingress Queues per function for Firmware Events and Forwarded 255# Interrupts, and two extra interrupts per function for Firmware Events (or a 256# Forwarded Interrupt Queue) and General Interrupts per function. 257# 258# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 259# # Forwarded Interrupts 260# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 261# # General Interrupts 262 263# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 264# their interrupts forwarded to another set of Forwarded Interrupt Queues. 265# 266# NVI_HYPERV = 16 # VMs we want to support 267# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 268# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 269# NEQ_HYPERV = 32 # VIQs Free Lists 270# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 271# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 272 273# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 274# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 275# 276# NVI_UNIFIED = 28 277# NFLIQ_UNIFIED = 106 278# NETHCTRL_UNIFIED = 32 279# NEQ_UNIFIED = 124 280# NMPSTCAM_UNIFIED = 40 281# 282# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 283# that up to 128 to make sure the Unified PF doesn't run out of resources. 284# 285# NMSIX_UNIFIED = 128 286# 287# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 288# which is 34 but they're probably safe with 32. 289# 290# NMSIX_STORAGE = 32 291 292# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 293# associated with it. Thus, the MSI-X Vector allocations we give to the 294# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 295# provision many more Virtual Functions than we can if the UnifiedPF were 296# one of PF0-3. 297# 298 299# All of the below PCI-E parameters are actually stored in various *_init.txt 300# files. We include them below essentially as comments. 301# 302# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 303# ports 0-3. 304# 305# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 306# 307# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 308# storage applications across all four possible ports. 309# 310# Additionally, since the UnifiedPF isn't one of the per-port Physical 311# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 312# different PCI Device IDs which will allow Unified and Per-Port Drivers 313# to directly select the type of Physical Function to which they wish to be 314# attached. 315# 316# Note that the actual values used for the PCI-E Intelectual Property will be 317# 1 less than those below since that's the way it "counts" things. For 318# readability, we use the number we actually mean ... 319# 320# PF0_INT = 8 # NCPUS 321# PF1_INT = 8 # NCPUS 322# PF2_INT = 8 # NCPUS 323# PF3_INT = 8 # NCPUS 324# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 325# 326# PF4_INT = 128 # NMSIX_UNIFIED 327# PF5_INT = 32 # NMSIX_STORAGE 328# PF6_INT = 32 # NMSIX_STORAGE 329# PF7_INT = 0 # Nothing Assigned 330# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 331# 332# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 333# 334# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 335# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 336# 337# NVF = 16 338 339# For those OSes which manage different ports on different PFs, we need 340# only enough resources to support a single port's NIC application functions 341# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 342# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 343# managed on the "storage PFs" (see below). 344# 345[function "0"] 346 nvf = 16 # NVF on this function 347 wx_caps = all # write/execute permissions for all commands 348 r_caps = all # read permissions for all commands 349 nvi = 1 # 1 port 350 niqflint = 8 # NCPUS "Queue Sets" 351 nethctrl = 8 # NCPUS "Queue Sets" 352 neq = 16 # niqflint + nethctrl Egress Queues 353 nexactf = 8 # number of exact MPSTCAM MAC filters 354 cmask = all # access to all channels 355 pmask = 0x1 # access to only one port 356 357[function "1"] 358 nvf = 16 # NVF on this function 359 wx_caps = all # write/execute permissions for all commands 360 r_caps = all # read permissions for all commands 361 nvi = 1 # 1 port 362 niqflint = 8 # NCPUS "Queue Sets" 363 nethctrl = 8 # NCPUS "Queue Sets" 364 neq = 16 # niqflint + nethctrl Egress Queues 365 nexactf = 8 # number of exact MPSTCAM MAC filters 366 cmask = all # access to all channels 367 pmask = 0x2 # access to only one port 368 369[function "2"] 370 nvf = 16 # NVF on this function 371 wx_caps = all # write/execute permissions for all commands 372 r_caps = all # read permissions for all commands 373 nvi = 1 # 1 port 374 niqflint = 8 # NCPUS "Queue Sets" 375 nethctrl = 8 # NCPUS "Queue Sets" 376 neq = 16 # niqflint + nethctrl Egress Queues 377 nexactf = 8 # number of exact MPSTCAM MAC filters 378 cmask = all # access to all channels 379 pmask = 0x4 # access to only one port 380 381[function "3"] 382 nvf = 16 # NVF on this function 383 wx_caps = all # write/execute permissions for all commands 384 r_caps = all # read permissions for all commands 385 nvi = 1 # 1 port 386 niqflint = 8 # NCPUS "Queue Sets" 387 nethctrl = 8 # NCPUS "Queue Sets" 388 neq = 16 # niqflint + nethctrl Egress Queues 389 nexactf = 8 # number of exact MPSTCAM MAC filters 390 cmask = all # access to all channels 391 pmask = 0x8 # access to only one port 392 393# Some OS Drivers manage all application functions for all ports via PF4. 394# Thus we need to provide a large number of resources here. For Egress 395# Queues we need to account for both TX Queues as well as Free List Queues 396# (because the host is responsible for producing Free List Buffers for the 397# hardware to consume). 398# 399[function "4"] 400 wx_caps = all # write/execute permissions for all commands 401 r_caps = all # read permissions for all commands 402 nvi = 28 # NVI_UNIFIED 403 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 404 nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 405 neq = 256 # NEQ_UNIFIED + NEQ_WD 406 nexactf = 40 # NMPSTCAM_UNIFIED 407 cmask = all # access to all channels 408 pmask = all # access to all four ports ... 409 nethofld = 1024 # number of user mode ethernet flow contexts 410 nroute = 32 # number of routing region entries 411 nclip = 32 # number of clip region entries 412 nfilter = 496 # number of filter region entries 413 nserver = 496 # number of server region entries 414 nhash = 12288 # number of hash region entries 415 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu 416 tp_l2t = 3072 417 tp_ddp = 2 418 tp_ddp_iscsi = 2 419 tp_stag = 2 420 tp_pbl = 5 421 tp_rq = 7 422 423# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 424# need to have Virtual Interfaces on each of the four ports with up to NCPUS 425# "Queue Sets" each. 426# 427[function "5"] 428 wx_caps = all # write/execute permissions for all commands 429 r_caps = all # read permissions for all commands 430 nvi = 4 # NPORTS 431 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 432 nethctrl = 32 # NPORTS*NCPUS 433 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 434 nexactf = 4 # NPORTS 435 cmask = all # access to all channels 436 pmask = all # access to all four ports ... 437 nserver = 16 438 nhash = 2048 439 tp_l2t = 1020 440 protocol = iscsi_initiator_fofld 441 tp_ddp_iscsi = 2 442 iscsi_ntask = 2048 443 iscsi_nsess = 2048 444 iscsi_nconn_per_session = 1 445 iscsi_ninitiator_instance = 64 446 447[function "6"] 448 wx_caps = all # write/execute permissions for all commands 449 r_caps = all # read permissions for all commands 450 nvi = 4 # NPORTS 451 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 452 nethctrl = 32 # NPORTS*NCPUS 453 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 454 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 455 # which is OK since < MIN(SUM PF0..3, PF4) 456 # and we never load PF0..3 and PF4 concurrently 457 cmask = all # access to all channels 458 pmask = all # access to all four ports ... 459 nhash = 2048 460 tp_l2t = 4 461 protocol = fcoe_initiator 462 tp_ddp = 2 463 fcoe_nfcf = 16 464 fcoe_nvnp = 32 465 fcoe_nssn = 1024 466 467# The following function, 1023, is not an actual PCIE function but is used to 468# configure and reserve firmware internal resources that come from the global 469# resource pool. 470# 471[function "1023"] 472 wx_caps = all # write/execute permissions for all commands 473 r_caps = all # read permissions for all commands 474 nvi = 4 # NVI_UNIFIED 475 cmask = all # access to all channels 476 pmask = all # access to all four ports ... 477 nexactf = 8 # NPORTS + DCBX + 478 nfilter = 16 # number of filter region entries 479 480# For Virtual functions, we only allow NIC functionality and we only allow 481# access to one port (1 << PF). Note that because of limitations in the 482# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 483# and GTS registers, the number of Ingress and Egress Queues must be a power 484# of 2. 485# 486[function "0/*"] # NVF 487 wx_caps = 0x82 # DMAQ | VF 488 r_caps = 0x86 # DMAQ | VF | PORT 489 nvi = 1 # 1 port 490 niqflint = 4 # 2 "Queue Sets" + NXIQ 491 nethctrl = 2 # 2 "Queue Sets" 492 neq = 4 # 2 "Queue Sets" * 2 493 nexactf = 4 494 cmask = all # access to all channels 495 pmask = 0x1 # access to only one port ... 496 497[function "1/*"] # NVF 498 wx_caps = 0x82 # DMAQ | VF 499 r_caps = 0x86 # DMAQ | VF | PORT 500 nvi = 1 # 1 port 501 niqflint = 4 # 2 "Queue Sets" + NXIQ 502 nethctrl = 2 # 2 "Queue Sets" 503 neq = 4 # 2 "Queue Sets" * 2 504 nexactf = 4 505 cmask = all # access to all channels 506 pmask = 0x2 # access to only one port ... 507 508[function "2/*"] # NVF 509 wx_caps = 0x82 # DMAQ | VF 510 r_caps = 0x86 # DMAQ | VF | PORT 511 nvi = 1 # 1 port 512 niqflint = 4 # 2 "Queue Sets" + NXIQ 513 nethctrl = 2 # 2 "Queue Sets" 514 neq = 4 # 2 "Queue Sets" * 2 515 nexactf = 4 516 cmask = all # access to all channels 517 pmask = 0x4 # access to only one port ... 518 519[function "3/*"] # NVF 520 wx_caps = 0x82 # DMAQ | VF 521 r_caps = 0x86 # DMAQ | VF | PORT 522 nvi = 1 # 1 port 523 niqflint = 4 # 2 "Queue Sets" + NXIQ 524 nethctrl = 2 # 2 "Queue Sets" 525 neq = 4 # 2 "Queue Sets" * 2 526 nexactf = 4 527 cmask = all # access to all channels 528 pmask = 0x8 # access to only one port ... 529 530# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 531# for packets from the wire as well as the loopback path of the L2 switch. The 532# folling params control how the buffer memory is distributed and the L2 flow 533# control settings: 534# 535# bg_mem: %-age of mem to use for port/buffer group 536# lpbk_mem: %-age of port/bg mem to use for loopback 537# hwm: high watermark; bytes available when starting to send pause 538# frames (in units of 0.1 MTU) 539# lwm: low watermark; bytes remaining when sending 'unpause' frame 540# (in inuits of 0.1 MTU) 541# dwm: minimum delta between high and low watermark (in units of 100 542# Bytes) 543# 544[port "0"] 545 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 546 bg_mem = 25 547 lpbk_mem = 25 548 hwm = 30 549 lwm = 15 550 dwm = 30 551 dcb_app_tlv[0] = 0x8906, ethertype, 3 552 dcb_app_tlv[1] = 0x8914, ethertype, 3 553 dcb_app_tlv[2] = 3260, socketnum, 5 554 555[port "1"] 556 dcb = ppp, dcbx 557 bg_mem = 25 558 lpbk_mem = 25 559 hwm = 30 560 lwm = 15 561 dwm = 30 562 dcb_app_tlv[0] = 0x8906, ethertype, 3 563 dcb_app_tlv[1] = 0x8914, ethertype, 3 564 dcb_app_tlv[2] = 3260, socketnum, 5 565 566[port "2"] 567 dcb = ppp, dcbx 568 bg_mem = 25 569 lpbk_mem = 25 570 hwm = 30 571 lwm = 15 572 dwm = 30 573 dcb_app_tlv[0] = 0x8906, ethertype, 3 574 dcb_app_tlv[1] = 0x8914, ethertype, 3 575 dcb_app_tlv[2] = 3260, socketnum, 5 576 577[port "3"] 578 dcb = ppp, dcbx 579 bg_mem = 25 580 lpbk_mem = 25 581 hwm = 30 582 lwm = 15 583 dwm = 30 584 dcb_app_tlv[0] = 0x8906, ethertype, 3 585 dcb_app_tlv[1] = 0x8914, ethertype, 3 586 dcb_app_tlv[2] = 3260, socketnum, 5 587 588[fini] 589 version = 0x14250016 590 checksum = 0xafaf8723 591 592# Total resources used by above allocations: 593# Virtual Interfaces: 104 594# Ingress Queues/w Free Lists and Interrupts: 526 595# Egress Queues: 702 596# MPS TCAM Entries: 336 597# MSI-X Vectors: 736 598# Virtual Functions: 64 599# 600# $FreeBSD$ 601# 602