1# Chelsio T5 Factory Default configuration file. 2# 3# Copyright (C) 2010-2017 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7# TO ADAPTERS. 8 9 10# This file provides the default, power-on configuration for 4-port T5-based 11# adapters shipped from the factory. These defaults are designed to address 12# the needs of the vast majority of Terminator customers. The basic idea is to 13# have a default configuration which allows a customer to plug a Terminator 14# adapter in and have it work regardless of OS, driver or application except in 15# the most unusual and/or demanding customer applications. 16# 17# Many of the Terminator resources which are described by this configuration 18# are finite. This requires balancing the configuration/operation needs of 19# device drivers across OSes and a large number of customer application. 20# 21# Some of the more important resources to allocate and their constaints are: 22# 1. Virtual Interfaces: 256. 23# 2. Ingress Queues with Free Lists: 1024. 24# 3. Egress Queues: 128K. 25# 4. MSI-X Vectors: 1088. 26# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27# address matching on Ingress Packets. 28# 29# Some of the important OS/Driver resource needs are: 30# 6. Some OS Drivers will manage all resources through a single Physical 31# Function (currently PF4 but it could be any Physical Function). 32# 7. Some OS Drivers will manage different ports and functions (NIC, 33# storage, etc.) on different Physical Functions. For example, NIC 34# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. 35# 36# Some of the customer application needs which need to be accommodated: 37# 8. Some customers will want to support large CPU count systems with 38# good scaling. Thus, we'll need to accommodate a number of 39# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40# to be involved per port and per application function. For example, 41# in the case where all ports and application functions will be 42# managed via a single Unified PF and we want to accommodate scaling up 43# to 8 CPUs, we would want: 44# 45# 4 ports * 46# 3 application functions (NIC, FCoE, iSCSI) per port * 47# 8 Ingress Queue/MSI-X Vectors per application function 48# 49# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50# (Plus a few for Firmware Event Queues, etc.) 51# 52# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54# and "PCI Device Passthrough" -- this is especially true for the NIC 55# application functionality. 56# 57 58 59# Global configuration settings. 60# 61[global] 62 rss_glb_config_mode = basicvirtual 63 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64 65 # PL_TIMEOUT register 66 pl_timeout_value = 10000 # the timeout value in units of us 67 68 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69 # Page Size and a 64B L1 Cache Line Size. It programs the 70 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71 # If a Master PF Driver finds itself on a machine with different 72 # parameters, then the Master PF Driver is responsible for initializing 73 # these parameters to appropriate values. 74 # 75 # Notes: 76 # 1. The Free List Buffer Sizes below are raw and the firmware will 77 # round them up to the Ingress Padding Boundary. 78 # 2. The SGE Timer Values below are expressed below in microseconds. 79 # The firmware will convert these values to Core Clock Ticks when 80 # it processes the configuration parameters. 81 # 82 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94 reg[0x10a4] = 0x00280000/0x3ffc0000 # SGE_DBFIFO_STATUS 95 reg[0x1118] = 0x00002800/0x00003c00 # SGE_DBFIFO_STATUS2 96 reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL 97 98 # SGE_THROTTLE_CONTROL 99 bar2throttlecount = 500 # bar2throttlecount in us 100 101 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 102 103 104 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if 105 # SGE_VFIFO_SIZE is not set, then 106 # firmware will set it up in function 107 # of number of egress queues used 108 109 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch 110 # threshold set to queue depth 111 # minus 128-entries for FL and HP 112 # queues, and 0xfff for LP which 113 # prompts the firmware to set it up 114 # in function of egress queues 115 # used 116 117 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which 118 # prompts the firmware to set it up in 119 # function of number of egress queues 120 # used 121 122 # enable TP_OUT_CONFIG.IPIDSPLITMODE 123 reg[0x7d04] = 0x00010000/0x00010000 124 125 # disable TP_PARA_REG3.RxFragEn 126 reg[0x7d6c] = 0x00000000/0x00007000 127 128 # enable TP_PARA_REG6.EnableCSnd 129 reg[0x7d78] = 0x00000400/0x00000000 130 131 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 132 133 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 134 # filter control: compact, fcoemask 135 # server sram : srvrsram 136 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 137 # protocol, tos, vlan, vnic_id, port, fcoe 138 # valid filterModes are described the Terminator 5 Data Book 139 filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 140 141 # filter tuples enforced in LE active region (equal to or subset of filterMode) 142 filterMask = protocol, fcoe 143 144 # Percentage of dynamic memory (in either the EDRAM or external MEM) 145 # to use for TP RX payload 146 tp_pmrx = 30 147 148 # TP RX payload page size 149 tp_pmrx_pagesize = 64K 150 151 # TP number of RX channels 152 tp_nrxch = 0 # 0 (auto) = 1 153 154 # Percentage of dynamic memory (in either the EDRAM or external MEM) 155 # to use for TP TX payload 156 tp_pmtx = 50 157 158 # TP TX payload page size 159 tp_pmtx_pagesize = 64K 160 161 # TP number of TX channels 162 tp_ntxch = 0 # 0 (auto) = equal number of ports 163 164 # TP OFLD MTUs 165 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 166 167 # TP_GLOBAL_CONFIG 168 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 169 170 # TP_PC_CONFIG 171 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 172 173 # TP_PARA_REG0 174 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 175 176 # ULPRX iSCSI Page Sizes 177 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 178 179 # LE_DB_CONFIG 180 reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable 181 182 # MC configuration 183 mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 184 mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC 185 186 # ULP_TX_CONFIG 187 reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ... 188 # TPT error. 189 190# Some "definitions" to make the rest of this a bit more readable. We support 191# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 192# per function per port ... 193# 194# NMSIX = 1088 # available MSI-X Vectors 195# NVI = 128 # available Virtual Interfaces 196# NMPSTCAM = 336 # MPS TCAM entries 197# 198# NPORTS = 4 # ports 199# NCPUS = 8 # CPUs we want to support scalably 200# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 201 202# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 203# PF" which many OS Drivers will use to manage most or all functions. 204# 205# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 206# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 207# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 208# will be specified as the "Ingress Queue Asynchronous Destination Index." 209# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 210# than or equal to the number of Ingress Queues ... 211# 212# NVI_NIC = 4 # NIC access to NPORTS 213# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 214# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 215# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 216# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 217# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 218# 219# NVI_OFLD = 0 # Offload uses NIC function to access ports 220# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 221# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 222# NEQ_OFLD = 16 # Offload Egress Queues (FL) 223# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 224# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 225# 226# NVI_RDMA = 0 # RDMA uses NIC function to access ports 227# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 228# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 229# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 230# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 231# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 232# 233# NEQ_WD = 128 # Wire Direct TX Queues and FLs 234# NETHCTRL_WD = 64 # Wire Direct TX Queues 235# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 236# 237# NVI_ISCSI = 4 # ISCSI access to NPORTS 238# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 239# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 240# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 241# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 242# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 243# 244# NVI_FCOE = 4 # FCOE access to NPORTS 245# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 246# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 247# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 248# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 249# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 250 251# Two extra Ingress Queues per function for Firmware Events and Forwarded 252# Interrupts, and two extra interrupts per function for Firmware Events (or a 253# Forwarded Interrupt Queue) and General Interrupts per function. 254# 255# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 256# # Forwarded Interrupts 257# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 258# # General Interrupts 259 260# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 261# their interrupts forwarded to another set of Forwarded Interrupt Queues. 262# 263# NVI_HYPERV = 16 # VMs we want to support 264# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 265# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 266# NEQ_HYPERV = 32 # VIQs Free Lists 267# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 268# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 269 270# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 271# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 272# 273# NVI_UNIFIED = 28 274# NFLIQ_UNIFIED = 106 275# NETHCTRL_UNIFIED = 32 276# NEQ_UNIFIED = 124 277# NMPSTCAM_UNIFIED = 40 278# 279# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 280# that up to 128 to make sure the Unified PF doesn't run out of resources. 281# 282# NMSIX_UNIFIED = 128 283# 284# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 285# which is 34 but they're probably safe with 32. 286# 287# NMSIX_STORAGE = 32 288 289# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 290# associated with it. Thus, the MSI-X Vector allocations we give to the 291# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 292# provision many more Virtual Functions than we can if the UnifiedPF were 293# one of PF0-3. 294# 295 296# All of the below PCI-E parameters are actually stored in various *_init.txt 297# files. We include them below essentially as comments. 298# 299# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 300# ports 0-3. 301# 302# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 303# 304# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 305# storage applications across all four possible ports. 306# 307# Additionally, since the UnifiedPF isn't one of the per-port Physical 308# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 309# different PCI Device IDs which will allow Unified and Per-Port Drivers 310# to directly select the type of Physical Function to which they wish to be 311# attached. 312# 313# Note that the actual values used for the PCI-E Intelectual Property will be 314# 1 less than those below since that's the way it "counts" things. For 315# readability, we use the number we actually mean ... 316# 317# PF0_INT = 8 # NCPUS 318# PF1_INT = 8 # NCPUS 319# PF2_INT = 8 # NCPUS 320# PF3_INT = 8 # NCPUS 321# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 322# 323# PF4_INT = 128 # NMSIX_UNIFIED 324# PF5_INT = 32 # NMSIX_STORAGE 325# PF6_INT = 32 # NMSIX_STORAGE 326# PF7_INT = 0 # Nothing Assigned 327# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 328# 329# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 330# 331# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 332# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 333# 334# NVF = 16 335 336 337# For those OSes which manage different ports on different PFs, we need 338# only enough resources to support a single port's NIC application functions 339# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 340# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 341# managed on the "storage PFs" (see below). 342# 343[function "0"] 344 nvf = 16 # NVF on this function 345 wx_caps = all # write/execute permissions for all commands 346 r_caps = all # read permissions for all commands 347 nvi = 1 # 1 port 348 niqflint = 8 # NCPUS "Queue Sets" 349 nethctrl = 8 # NCPUS "Queue Sets" 350 neq = 16 # niqflint + nethctrl Egress Queues 351 nexactf = 8 # number of exact MPSTCAM MAC filters 352 cmask = all # access to all channels 353 pmask = 0x1 # access to only one port 354 355 356[function "1"] 357 nvf = 16 # NVF on this function 358 wx_caps = all # write/execute permissions for all commands 359 r_caps = all # read permissions for all commands 360 nvi = 1 # 1 port 361 niqflint = 8 # NCPUS "Queue Sets" 362 nethctrl = 8 # NCPUS "Queue Sets" 363 neq = 16 # niqflint + nethctrl Egress Queues 364 nexactf = 8 # number of exact MPSTCAM MAC filters 365 cmask = all # access to all channels 366 pmask = 0x2 # access to only one port 367 368 369[function "2"] 370 nvf = 16 # NVF on this function 371 wx_caps = all # write/execute permissions for all commands 372 r_caps = all # read permissions for all commands 373 nvi = 1 # 1 port 374 niqflint = 8 # NCPUS "Queue Sets" 375 nethctrl = 8 # NCPUS "Queue Sets" 376 neq = 16 # niqflint + nethctrl Egress Queues 377 nexactf = 8 # number of exact MPSTCAM MAC filters 378 cmask = all # access to all channels 379 pmask = 0x4 # access to only one port 380 381 382[function "3"] 383 nvf = 16 # NVF on this function 384 wx_caps = all # write/execute permissions for all commands 385 r_caps = all # read permissions for all commands 386 nvi = 1 # 1 port 387 niqflint = 8 # NCPUS "Queue Sets" 388 nethctrl = 8 # NCPUS "Queue Sets" 389 neq = 16 # niqflint + nethctrl Egress Queues 390 nexactf = 8 # number of exact MPSTCAM MAC filters 391 cmask = all # access to all channels 392 pmask = 0x8 # access to only one port 393 394 395# Some OS Drivers manage all application functions for all ports via PF4. 396# Thus we need to provide a large number of resources here. For Egress 397# Queues we need to account for both TX Queues as well as Free List Queues 398# (because the host is responsible for producing Free List Buffers for the 399# hardware to consume). 400# 401[function "4"] 402 wx_caps = all # write/execute permissions for all commands 403 r_caps = all # read permissions for all commands 404 nvi = 28 # NVI_UNIFIED 405 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 406 nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 407 neq = 256 # NEQ_UNIFIED + NEQ_WD 408 nqpcq = 12288 409 nexactf = 40 # NMPSTCAM_UNIFIED 410 cmask = all # access to all channels 411 pmask = all # access to all four ports ... 412 nethofld = 1024 # number of user mode ethernet flow contexts 413 nroute = 32 # number of routing region entries 414 nclip = 32 # number of clip region entries 415 nfilter = 496 # number of filter region entries 416 nserver = 496 # number of server region entries 417 nhash = 12288 # number of hash region entries 418 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, nic_hashfilter 419 tp_l2t = 3072 420 tp_ddp = 2 421 tp_ddp_iscsi = 2 422 tp_stag = 2 423 tp_pbl = 5 424 tp_rq = 7 425 426 427# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 428# need to have Virtual Interfaces on each of the four ports with up to NCPUS 429# "Queue Sets" each. 430# 431[function "5"] 432 wx_caps = all # write/execute permissions for all commands 433 r_caps = all # read permissions for all commands 434 nvi = 4 # NPORTS 435 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 436 nethctrl = 32 # NPORTS*NCPUS 437 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 438 nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 439 cmask = all # access to all channels 440 pmask = all # access to all four ports ... 441 nserver = 16 442 nhash = 2048 443 tp_l2t = 1020 444 protocol = iscsi_initiator_fofld 445 tp_ddp_iscsi = 2 446 iscsi_ntask = 2048 447 iscsi_nsess = 2048 448 iscsi_nconn_per_session = 1 449 iscsi_ninitiator_instance = 64 450 451 452[function "6"] 453 wx_caps = all # write/execute permissions for all commands 454 r_caps = all # read permissions for all commands 455 nvi = 4 # NPORTS 456 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 457 nethctrl = 32 # NPORTS*NCPUS 458 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 459 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 460 # which is OK since < MIN(SUM PF0..3, PF4) 461 # and we never load PF0..3 and PF4 concurrently 462 cmask = all # access to all channels 463 pmask = all # access to all four ports ... 464 nhash = 2048 465 tp_l2t = 4 466 protocol = fcoe_initiator 467 tp_ddp = 2 468 fcoe_nfcf = 16 469 fcoe_nvnp = 32 470 fcoe_nssn = 1024 471 472 473# The following function, 1023, is not an actual PCIE function but is used to 474# configure and reserve firmware internal resources that come from the global 475# resource pool. 476# 477[function "1023"] 478 wx_caps = all # write/execute permissions for all commands 479 r_caps = all # read permissions for all commands 480 nvi = 4 # NVI_UNIFIED 481 cmask = all # access to all channels 482 pmask = all # access to all four ports ... 483 nexactf = 8 # NPORTS + DCBX + 484 nfilter = 16 # number of filter region entries 485 486 487# For Virtual functions, we only allow NIC functionality and we only allow 488# access to one port (1 << PF). Note that because of limitations in the 489# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 490# and GTS registers, the number of Ingress and Egress Queues must be a power 491# of 2. 492# 493[function "0/*"] # NVF 494 wx_caps = 0x82 # DMAQ | VF 495 r_caps = 0x86 # DMAQ | VF | PORT 496 nvi = 1 # 1 port 497 niqflint = 6 # 2 "Queue Sets" + NXIQ 498 nethctrl = 4 # 2 "Queue Sets" 499 neq = 8 # 2 "Queue Sets" * 2 500 nexactf = 4 501 cmask = all # access to all channels 502 pmask = 0x1 # access to only one port ... 503 504 505[function "1/*"] # NVF 506 wx_caps = 0x82 # DMAQ | VF 507 r_caps = 0x86 # DMAQ | VF | PORT 508 nvi = 1 # 1 port 509 niqflint = 6 # 2 "Queue Sets" + NXIQ 510 nethctrl = 4 # 2 "Queue Sets" 511 neq = 8 # 2 "Queue Sets" * 2 512 nexactf = 4 513 cmask = all # access to all channels 514 pmask = 0x2 # access to only one port ... 515 516 517[function "2/*"] # NVF 518 wx_caps = 0x82 # DMAQ | VF 519 r_caps = 0x86 # DMAQ | VF | PORT 520 nvi = 1 # 1 port 521 niqflint = 6 # 2 "Queue Sets" + NXIQ 522 nethctrl = 4 # 2 "Queue Sets" 523 neq = 8 # 2 "Queue Sets" * 2 524 nexactf = 4 525 cmask = all # access to all channels 526 pmask = 0x4 # access to only one port ... 527 528 529[function "3/*"] # NVF 530 wx_caps = 0x82 # DMAQ | VF 531 r_caps = 0x86 # DMAQ | VF | PORT 532 nvi = 1 # 1 port 533 niqflint = 6 # 2 "Queue Sets" + NXIQ 534 nethctrl = 4 # 2 "Queue Sets" 535 neq = 8 # 2 "Queue Sets" * 2 536 nexactf = 4 537 cmask = all # access to all channels 538 pmask = 0x8 # access to only one port ... 539 540 541# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 542# for packets from the wire as well as the loopback path of the L2 switch. The 543# folling params control how the buffer memory is distributed and the L2 flow 544# control settings: 545# 546# bg_mem: %-age of mem to use for port/buffer group 547# lpbk_mem: %-age of port/bg mem to use for loopback 548# hwm: high watermark; bytes available when starting to send pause 549# frames (in units of 0.1 MTU) 550# lwm: low watermark; bytes remaining when sending 'unpause' frame 551# (in inuits of 0.1 MTU) 552# dwm: minimum delta between high and low watermark (in units of 100 553# Bytes) 554# 555[port "0"] 556 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 557 bg_mem = 25 558 lpbk_mem = 25 559 hwm = 30 560 lwm = 15 561 dwm = 30 562 dcb_app_tlv[0] = 0x8906, ethertype, 3 563 dcb_app_tlv[1] = 0x8914, ethertype, 3 564 dcb_app_tlv[2] = 3260, socketnum, 5 565 566 567[port "1"] 568 dcb = ppp, dcbx 569 bg_mem = 25 570 lpbk_mem = 25 571 hwm = 30 572 lwm = 15 573 dwm = 30 574 dcb_app_tlv[0] = 0x8906, ethertype, 3 575 dcb_app_tlv[1] = 0x8914, ethertype, 3 576 dcb_app_tlv[2] = 3260, socketnum, 5 577 578 579[port "2"] 580 dcb = ppp, dcbx 581 bg_mem = 25 582 lpbk_mem = 25 583 hwm = 30 584 lwm = 15 585 dwm = 30 586 dcb_app_tlv[0] = 0x8906, ethertype, 3 587 dcb_app_tlv[1] = 0x8914, ethertype, 3 588 dcb_app_tlv[2] = 3260, socketnum, 5 589 590 591[port "3"] 592 dcb = ppp, dcbx 593 bg_mem = 25 594 lpbk_mem = 25 595 hwm = 30 596 lwm = 15 597 dwm = 30 598 dcb_app_tlv[0] = 0x8906, ethertype, 3 599 dcb_app_tlv[1] = 0x8914, ethertype, 3 600 dcb_app_tlv[2] = 3260, socketnum, 5 601 602 603[fini] 604 version = 0x1425001d 605 checksum = 0xd8c8fbd8 606 607# Total resources used by above allocations: 608# Virtual Interfaces: 104 609# Ingress Queues/w Free Lists and Interrupts: 526 610# Egress Queues: 702 611# MPS TCAM Entries: 336 612# MSI-X Vectors: 736 613# Virtual Functions: 64 614# 615# $FreeBSD$ 616# 617